On Thu, 2 Mar 2023 at 14:29, Takahiro Akashi wrote:
>
> On Wed, Mar 01, 2023 at 06:15:22PM +0900, Masahisa Kojima wrote:
> > Current mkeficapsule tool does not provide firmware
> > version management. EDK2 reference implementation inserts
> > the FMP Payload Header right before the payload.
> >
Hi Eddie,
[...]
>
> +int bootm_measure(struct bootm_headers *images)
> +{
> + int ret = 0;
> +
> + /* Skip measurement if EFI is going to do it */
> + if (images->os.os == IH_OS_EFI &&
> + IS_ENABLED(CONFIG_EFI_TCG2_PROTOCOL) &&
> + IS_ENABLED(CONFIG_BOOTM_EFI))
>
On 15:54-20230302, Neha Malcom Francis wrote:
> Hi Manorit
>
> On 01/03/23 15:01, Manorit Chawdhry wrote:
> > K3 devices have runtime type board detection. Make the default defconfig
> > include the secure configuration. Then remove the HS specific config.
> >
>
At present, 'buildman -A sandbox' adds the path containing the
toolchain at present. We can assume that this is in the path and
we don't want to set CROSS_COMPILE=/bin/ so change this to align
with what MakeEnvironment() does.
Signed-off-by: Simon Glass
---
tools/buildman/toolchain.py | 3 +--
Sure. Please send some instructions my way on how to proceed. I know
there is a u-boot manual, but I don't wanna mess up my mac mini m1
system. So I'd stick with instructions on your end. Ideally, the action
is reversible. I always keep complete system backups, though. My current
version is
Hello!
Apologies to bother y'all with this. I am at wit's end. I think this
is an issue that I've encountered before and figured out how to solve,
but I can't for the life of me figure out what to do this time around.
Whenever I try to `make O=../generic-build menuconfig` from my u-boot
build
Hi Akashi-san,
On Thu, 2 Mar 2023 at 14:09, Takahiro Akashi wrote:
>
> On Wed, Mar 01, 2023 at 06:15:19PM +0900, Masahisa Kojima wrote:
> > Firmware version management is not implemented in the current
> > FMP protocol.
> > EDK2 reference implementation capsule generation script inserts
> > the
On Thu, 2 Mar 2023 at 14:16, Takahiro Akashi wrote:
>
> On Wed, Mar 01, 2023 at 06:15:20PM +0900, Masahisa Kojima wrote:
> > Current FMP->GetImageInfo() always return 0 for the firmware
> > version, user can not identify which firmware version is currently
> > running through the EFI interface.
>
Hi Manorit
On 01/03/23 15:01, Manorit Chawdhry wrote:
K3 devices have runtime type board detection. Make the default defconfig
include the secure configuration. Then remove the HS specific config.
Non-HS devices will continue to boot due to runtime device type detection.
If TI_SECURE_DEV_PKG
Hello,
I am working on the PolarFire RISC-V icicle kit and use u-boot to start
my application.
I configured the firmware to start u-boot on all harts (cores) and found
out that u-boot uses a "HART lottery system" to decide which core/hart
it runs on.
In my special case I want u-boot to start
Hi Eddie,
This is fine foe now. I'll add a similar description for EFI in the future.
On Wed, Mar 01, 2023 at 04:50:56PM -0600, Eddie James wrote:
> Briefly describe the feature and specify the requirements.
>
> Signed-off-by: Eddie James
> Reviewed-by: Simon Glass
> ---
>
On Wed, Mar 01, 2023 at 08:39:23PM -0700, Simon Glass wrote:
> These board have moved to standard boot but the old 'distro_bootcmd'
> command is still active. Disable DISTRO_DEFAULTS to fix this.
>
> Signed-off-by: Simon Glass
> Tested-by: Vagrant Cascadian
> ---
>
> (no changes since v1)
>
>
On 3/2/23 10:14, Janne Grunau wrote:
On 2023-03-01 23:51:14 +0100, Marek Vasut wrote:
On 3/1/23 21:34, Simon Glass wrote:
+Marek Vasut +Bin Meng +Mark Kettenis +Tom Rini
On Wed, 1 Mar 2023 at 08:12, bluetail wrote:
Hello. user kettenis aka "Mark Kettenis" guided me write my bug report
to
On Thu, Mar 02, 2023 at 10:54:57AM +0800, Kever Yang wrote:
> Hi Linus,
>
> On 2023/2/23 16:59, Linus Walleij wrote:
> > On Mon, Feb 13, 2023 at 11:28 PM Chris Morgan
> > wrote:
> >
> > > From: Chris Morgan
> > >
> > > Use the new devicetree property of gpio-ranges to determine the GPIO
> >
From: Kamlesh Gurudasani
On high security devices, ROM enables firewalls to protect the OCSRAM
region access during bootup. Only after TIFS has started (and had
time to disable the OCSRAM firewall region) will we have write access to
the region.
So, move scratch board area to HSM RAM.
From: Kamlesh Gurudasani
On high security devices, ROM enables firewalls to protect the OCSRAM
region access during bootup. Only after TIFS has started (and had
time to disable the OCSRAM firewall region) will we have write access to
the region.
This means we will need to move the stack & heap
ср, 1 мар. 2023 г. в 18:58, Tom Rini :
>
> On Wed, Mar 01, 2023 at 01:43:38PM +0300, Dzmitry Sankouski wrote:
> > Current process of sending patches includes running checkpatch.pl
> > script for each patch, and fixing found style problems.
> > EditorConfig may help to prevent some style related
On Wed, Mar 01, 2023 at 08:39:27PM -0700, Simon Glass wrote:
> These two features use a lot of common options. Move them into a common
> CONFIG to reduce duplication.
>
> Resync defconfigs since this makes a lot of changes.
>
> Signed-off-by: Simon Glass
[snip]
> diff --git a/boot/Kconfig
On Wed, Mar 01, 2023 at 01:10:57PM -0700, Simon Glass wrote:
> Hi Tom,
>
> https://source.denx.de/u-boot/custodians/u-boot-dm/-/pipelines/15430
>
> The following changes since commit b0eda49bc9b00503366f2ec431be0178caf9e9b5:
>
> Merge tag 'u-boot-at91-fixes-2023.04-a' of
>
From: Ehsan Mohandesi
In IPv6, the default gateway and prefix length are determined by receiving
a router advertisement as defined in -
https://www.rfc-editor.org/rfc/rfc4861.
Add support for sending router solicitation (RS) and processing router
advertisements (RA).
If the RA has prefix info
Kamlesh Gurudasani writes:
Please ignore this series on personal id, bouncing back on u-boot@lists.denx.de
Will debug and post on u-boot@lists.denx.de directly.
> Add support for high security bootflow on am62 devices.
>
> On HS devices, ROM and TIFS will protect the RAM regions with
>
On Wed, Feb 22, 2023 at 09:33:59AM -0700, Simon Glass wrote:
> This check is not needed when the environment is not enabled, e.g. in
> SPL. Add a condition to handle this.
>
> Signed-off-by: Simon Glass
> ---
>
> (no changes since v1)
>
> cmd/nvedit.c | 2 ++
> 1 file changed, 2
From: Kamlesh Gurudasani
Add support for high security bootflow on am62 devices.
On HS devices, ROM and TIFS will protect the RAM regions with
firewalls. This means the wakeup domain's SPL will need to move the
stack and heap to HSM RAM to ensure it stays within its allotted
memory regions.
On Wed, Mar 01, 2023 at 08:19:24PM -0500, Nick Carraway wrote:
> Hello!
>
> Apologies to bother y'all with this. I am at wit's end. I think this
> is an issue that I've encountered before and figured out how to solve,
> but I can't for the life of me figure out what to do this time around.
>
>
Hello! I'm not rockchip maintainer, so please do not send me rockchip
patches unless it is something for which I really should take an
attention.
On Thursday 02 March 2023 15:12:57 Kever Yang wrote:
> rk3588 evb1 v10 is a evalution board from Rockchip, it is a dev board for
> rockchip and also a
Hi Eddie,
The good news, is that this generally seems to be working and is really
close to what I had in mind on code re-usage. Thanks for the patience!
The bad new now is that I think I found one last (famous last words)
problem
[...]
> + }
> +
> + /* Read PCR0 to check if previous
Hi Eddie,
On Thu, 2 Mar 2023 at 16:17, Ilias Apalodimas
wrote:
>
> Hi Eddie,
>
> The good news, is that this generally seems to be working and is really
> close to what I had in mind on code re-usage. Thanks for the patience!
>
> The bad new now is that I think I found one last (famous last
On Thu, Mar 02, 2023 at 06:00:43PM +0300, Dzmitry Sankouski wrote:
> ср, 1 мар. 2023 г. в 18:58, Tom Rini :
> >
> > On Wed, Mar 01, 2023 at 01:43:38PM +0300, Dzmitry Sankouski wrote:
> > > Current process of sending patches includes running checkpatch.pl
> > > script for each patch, and fixing
Here is the full output with V=1:
make -C /home/user/user-u-boot/generic-build
KBUILD_SRC=/home/user/user-u-boot/generic-raw \
-f /home/user/user-u-boot/generic-raw/Makefile menuconfig
make[1]: Entering directory '/home/user/user-u-boot/generic-build'
make -f
I don't know why, but doing a reset, then fetching, then re-checking
out that release fixed it. Seems very obvious now I had a
suspicion that it would be.
On Thu, Mar 2, 2023 at 12:02 PM Nick Carraway <1800ponysa...@gmail.com> wrote:
>
> Here is the full output with V=1:
>
> make -C
On 3/2/23 19:51, Janne Grunau wrote:
On 2023-03-02 18:33:15 +0100, Marek Vasut wrote:
On 3/2/23 10:14, Janne Grunau wrote:
On 2023-03-01 23:51:14 +0100, Marek Vasut wrote:
On 3/1/23 21:34, Simon Glass wrote:
+Marek Vasut +Bin Meng +Mark Kettenis +Tom Rini
On Wed, 1 Mar 2023 at 08:12,
Remapping console logs from soc uart2 (s1 termial) to css non-secure (uart_ap
terminal)
Change-Id: I554f3ab6eb8439c54f5568c47e48f1543ac67b44
Signed-off-by: Annam Sai Manisha
---
include/configs/total_compute.h | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git
On Wed, Mar 1, 2023 at 7:33 AM Tom Rini wrote:
> On Fri, Feb 24, 2023 at 10:10:30AM -0800, Troy Kisky wrote:
> > CONFIG_IS_ENABLED(FIT_SIGNATURE) will check for
> > CONFIG_TOOLS_FIT_SIGNATURE. So define it now in preparation.
> >
> > Signed-off-by: Troy Kisky
> > Reviewed-by: Simon Glass
> >
From: Kamlesh Gurudasani
Add support for high security bootflow on am62 devices.
On HS devices, ROM and TIFS will protect the RAM regions with
firewalls. This means the wakeup domain's SPL will need to move the
stack and heap to HSM RAM to ensure it stays within its allotted
memory regions.
Hi Eddie,
I found the issue. I still think we could squeeze things even more in our
abstraction. Specifically the measure_event() tcg2_agile_log_append()
contain some efi specific bits and I am trying to figure out if we can make
those more generic. However, that's not a show stopper for me.
On Wed, Feb 22, 2023 at 09:34:25AM -0700, Simon Glass wrote:
> At present we compile commands into U-Boot SPL even though they cannot
> be used. This wastes space. Adjust the condition to avoid this.
>
> Signed-off-by: Simon Glass
> ---
>
> Changes in v5:
> - Drop FSL_ISBC_KEY_EXT patch as it
On 3/2/23 07:23, Chunfeng Yun (云春峰) wrote:
Hi Marek,
Hi,
On Fri, 2023-02-17 at 14:35 +0100, Marek Vasut wrote:
On 2/17/23 10:04, Chunfeng Yun wrote:
There are 4 USB controllers on MT8195, the controllers (IP1~IP3,
exclude IP0) have a wrong default SOF/ITP interval which is
calculated from
On Thu, Mar 02, 2023 at 10:21:29AM -0800, Troy Kisky wrote:
> On Wed, Mar 1, 2023 at 7:33 AM Tom Rini wrote:
>
> > On Fri, Feb 24, 2023 at 10:10:30AM -0800, Troy Kisky wrote:
> > > CONFIG_IS_ENABLED(FIT_SIGNATURE) will check for
> > > CONFIG_TOOLS_FIT_SIGNATURE. So define it now in preparation.
On Wed, Feb 22, 2023 at 09:34:19AM -0700, Simon Glass wrote:
> This is not a CONFIG option so we should not be using IS_ENABLED() on it,
> particularly not when it is not defined to anything, so shows up as
> calling IS_ENABLED() with no arguments.
>
> Just check it normally.
>
> For
On Wed, Feb 22, 2023 at 09:34:02AM -0700, Simon Glass wrote:
> At present these are not included in SPL. They do add to code size but
> are a bit faster, so adjust the setting to add them.
>
> Signed-off-by: Simon Glass
> ---
>
> (no changes since v1)
>
> arch/x86/include/asm/string.h | 2 +-
On 2023-03-02 18:33:15 +0100, Marek Vasut wrote:
> On 3/2/23 10:14, Janne Grunau wrote:
> > On 2023-03-01 23:51:14 +0100, Marek Vasut wrote:
> > > On 3/1/23 21:34, Simon Glass wrote:
> > > > +Marek Vasut +Bin Meng +Mark Kettenis +Tom Rini
> > > >
> > > > On Wed, 1 Mar 2023 at 08:12, bluetail
>
Hi Dzmitry,
On Wed, Mar 1, 2023 at 7:44 AM Dzmitry Sankouski wrote:
>
> Current process of sending patches includes running checkpatch.pl
> script for each patch, and fixing found style problems.
> EditorConfig may help to prevent some style related problems
> (like spaces vs tab indentation) on
Add support for DH electronics i.MX8M Plus DHCOM SoM on PDK3 carrier board.
Currently supported are serial console, EQoS and FEC ethernets, eMMC, SD,
SPI NOR and USB 3.0 host.
Signed-off-by: Marek Vasut
---
Cc: Fabio Estevam
Cc: Peng Fan
Cc: Stefano Babic
---
arch/arm/dts/Makefile
Copy build artifacts for all test.py tests, so they show up in
artifacts storage for later inspection. The test.py tests output
in CI is basically useless, but it is far more useful in the html
output for analysis and debugging.
Reviewed-by: Simon Glass
Reviewed-by: Tom Rini
Suggested-by: Simon
Add board support for StarFive VisionFive v2.
Signed-off-by: Yanhong Wang
---
board/starfive/visionfive2/MAINTAINERS| 7 +
board/starfive/visionfive2/Makefile | 7 +
board/starfive/visionfive2/spl.c | 87
.../visionfive2/starfive_visionfive2.c|
Add Kconfig to select the basic functions for StarFive JH7110 SoC.
Signed-off-by: Yanhong Wang
---
arch/riscv/cpu/jh7110/Kconfig | 28
1 file changed, 28 insertions(+)
create mode 100644 arch/riscv/cpu/jh7110/Kconfig
diff --git a/arch/riscv/cpu/jh7110/Kconfig
This series of patches base on the latest branch/master, and add support
for the StarFive JH7110 RISC-V SoC and VisionFive V2 board. In order for
this to be achieved, the respective DT nodes have been added, and the
required defconfigs have been added to the boards' defconfig. What is more,
the
Add initial u-boot device tree for the JH7110 RISC-V SoC.
Signed-off-by: Yanhong Wang
---
arch/riscv/dts/jh7110-u-boot.dtsi | 95 +++
1 file changed, 95 insertions(+)
create mode 100644 arch/riscv/dts/jh7110-u-boot.dtsi
diff --git
Add resets for the StarFive JH7110 system(SYS),system-top-group(STG) and
always-on(AON) reset controller.
Signed-off-by: Yanhong Wang
---
.../dt-bindings/reset/starfive,jh7110-crg.h | 183 ++
1 file changed, 183 insertions(+)
create mode 100644
The fdt_addr_t and phys_addr_t size have been decoupled.
A 32bit CPU can expext 64-bit data from the device tree parser,
so use dev_read_addr_ptr in the rockchip_nfc.c file.
Signed-off-by: Johan Jonker
Reviewed-by: Michael Trimarchi
---
Changed V6:
use -EINVAL on return
---
On Wed, Mar 01, 2023 at 06:15:19PM +0900, Masahisa Kojima wrote:
> Firmware version management is not implemented in the current
> FMP protocol.
> EDK2 reference implementation capsule generation script inserts
> the FMP Payload Header right before the payload, it contains the
> firmware version
Add StarFive JH7110 SoC to support RISC-V arch.
Signed-off-by: Yanhong Wang
Reviewed-by: Rick Chen
---
arch/riscv/cpu/jh7110/Makefile| 10
arch/riscv/cpu/jh7110/cpu.c | 23
arch/riscv/cpu/jh7110/dram.c | 38 ++
Add all clock outputs for the StarFive JH7110 clock generator.
Signed-off-by: Yanhong Wang
---
.../dt-bindings/clock/starfive,jh7110-crg.h | 257 ++
1 file changed, 257 insertions(+)
create mode 100644 include/dt-bindings/clock/starfive,jh7110-crg.h
diff --git
Add a DM reset driver for StarFive JH7110 SoC.
Note that the register base address of reset controller is the
same with the clock controller. Therefore, there is no device
tree node alone for reset driver.It binds device node in
the clock driver
Signed-off-by: Yanhong Wang
---
Hi Akashi-san,
On Fri, 3 Mar 2023 at 09:10, Takahiro Akashi wrote:
>
> On Thu, Mar 02, 2023 at 07:05:50PM +0900, Masahisa Kojima wrote:
> > On Thu, 2 Mar 2023 at 14:16, Takahiro Akashi
> > wrote:
> > >
> > > On Wed, Mar 01, 2023 at 06:15:20PM +0900, Masahisa Kojima wrote:
> > > > Current
And a new entry type which supports generation of x509 certificates.
This uses a new 'openssl' btool with just one operation so far.
Signed-off-by: Simon Glass
---
Changes in v2:
- Add new patch to generate x509 certificates
tools/binman/btool/openssl.py | 94
Implement this feature since it is useful for updating FITs within an
image.
Signed-off-by: Simon Glass
---
Changes in v2:
- Update to support more replacement cases
tools/binman/binman.rst | 16 ++
tools/binman/control.py | 2 +
At present these are handled as if they are allowed to be missing, but
this is only true if the -M flag is provided. Fix this and add a test.
Signed-off-by: Simon Glass
---
Changes in v2:
- Add new patch to handle missing bintools correctly in fit
tools/binman/etype/fit.py | 2 ++
Add these flags for the 'replace' subcommand too, to aid debugging.
Signed-off-by: Simon Glass
44 2023 -0700
---
Changes in v2:
- Add new patch to allow preserving the output dir when replacing
tools/binman/binman.rst | 6 ++
tools/binman/cmdline.py | 16 ++--
The fdt_addr_t and phys_addr_t size have been decoupled. A 32bit CPU
can expect 64-bit data from the device tree parser, so use
devfdt_get_addr_index_ptr instead of the devfdt_get_addr_index function
in the various files in the drivers directory that cast to a pointer.
Signed-off-by: Johan Jonker
The DT specification supports CPUs with both 32-bit and 64-bit addressing
capabilities. In U-boot the fdt_addr_t and phys_addr_t size are coupled
by a typedef. The MTD NAND drivers for 32-bit CPU's can describe partitions
with a 64-bit reg property. These partitions synced from Linux end up with
The fdt_addr_t and phys_addr_t size have been decoupled. A 32bit CPU
can expect 64-bit data from the device tree parser, so fix some
debug strings with fdt_addr_t to be able to handle both sizes.
Signed-off-by: Johan Jonker
Reviewed-by: Simon Glass
---
Changed V5:
new patch
---
The fdt_addr_t and phys_addr_t size have been decoupled. A 32bit CPU
can expect 64-bit data from the device tree parser, so use
devfdt_get_addr_ptr instead of the devfdt_get_addr function in
the various files in the drivers directory that cast to a pointer.
Signed-off-by: Johan Jonker
The fdt_addr_t and phys_addr_t size have been decoupled. A 32bit CPU
can expect 64-bit data from the device tree parser, so use
devfdt_get_addr_size_index_ptr instead of the devfdt_get_addr_size_index
function in the various files in the drivers directory that cast to
a pointer.
Signed-off-by:
The fdt_addr_t and phys_addr_t size have been decoupled.
A 32bit CPU can expect 64-bit data from the device tree parser,
so fix ofnode_get_addr_size function with fdt_addr_t input to
be able to handle both sizes for stm32mp SoC in spl.c file.
Signed-off-by: Johan Jonker
---
Add driver for StarFive JH7110 to support ddr initialization in SPL.
Signed-off-by: Yanhong Wang
---
drivers/ram/Kconfig |1 +
drivers/ram/Makefile|4 +-
drivers/ram/starfive/Kconfig|5 +
drivers/ram/starfive/Makefile | 11 +
Add a DM clock driver for StarFive JH7110 SoC.
Signed-off-by: Yanhong Wang
---
drivers/clk/Kconfig | 1 +
drivers/clk/Makefile | 1 +
drivers/clk/starfive/Kconfig | 17 +
drivers/clk/starfive/Makefile | 4 +
From: Kuan Lim Lee
Add pinctrl driver for StarFive JH7110 SoC.
Signed-off-by: Kuan Lim Lee
Signed-off-by: Emil Renner Berthing
Signed-off-by: Jianlong Huang
Signed-off-by: Yanhong Wang
---
drivers/pinctrl/Kconfig | 1 +
drivers/pinctrl/Makefile
From: Jianlong Huang
Add pinctrl definitions for StarFive JH7110 SoC.
Signed-off-by: Kuan Lim Lee
Signed-off-by: Emil Renner Berthing
Signed-off-by: Jianlong Huang
Signed-off-by: Yanhong Wang
---
.../pinctrl/pinctrl-starfive-jh7110.h | 427 ++
1 file changed, 427
Add board support for StarFive VisionFive v2.
Signed-off-by: Yanhong Wang
---
arch/riscv/Kconfig | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 48ca4ff4c4..f6ed05906a 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -24,6 +24,9
This adds support for the StarFive JH7110 SoC which also
feature this SiFive cache controller.
Signed-off-by: Yanhong Wang
---
drivers/cache/cache-sifive-ccache.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/cache/cache-sifive-ccache.c
b/drivers/cache/cache-sifive-ccache.c
index
On Fri, 3 Mar 2023 at 09:17, Takahiro Akashi wrote:
>
> On Wed, Mar 01, 2023 at 06:15:19PM +0900, Masahisa Kojima wrote:
> > Firmware version management is not implemented in the current
> > FMP protocol.
> > EDK2 reference implementation capsule generation script inserts
> > the FMP Payload
This serie contains fixes for the Rockchip NFC driver,
which was ported to U-boot and merged with little review
and testing it seems.
Part 1 aims at passing the probe function without errors.
Extended with tree wide function cleanup needed for 64bit DT parsing.
Fixed are:
64bit FDT parsing
The fdt_addr_t and phys_addr_t size have been decoupled.
A 32bit CPU can expect 64-bit data from the device tree parser,
so use a reg variable with phys_addr_t size in the
dw-apb-timer.c file.
Signed-off-by: Johan Jonker
---
Changed V6:
remove cast
change title
---
The fdt_addr_t and phys_addr_t size have been decoupled.
A 32bit CPU can expect 64-bit data from the device tree parser,
so convert regmap_init_mem_plat() input to phys_addr_t in files
that use this function. Also correct struct syscon_base_plat
depending on CONFIG_PHYS_64BIT setting and fix
When fdt_addr_t and phys_addr_t are split it turns out that
the header don't match the functions, so fix the headers.
Signed-off-by: Johan Jonker
Reviewed-by: Simon Glass
Reviewed-by: Kever Yang
---
include/dm/ofnode.h | 16
1 file changed, 8 insertions(+), 8 deletions(-)
The fdt_addr_t and phys_addr_t size have been decoupled.
A 32bit CPU can expext 64-bit data from the device tree parser,
so use dev_read_addr_ptr in the rockchip-saradc.c file.
Signed-off-by: Johan Jonker
Reviewed-by: Kever Yang
---
Changed V6:
use -EINVAL on return
drop cast
---
Sandisk SDTNQGAMA is a 8GB size, 3.3V 8 bit chip with 16KB page size,
1KB write size and 40 bit ecc support
Signed-off-by: Paweł Jarosz
Signed-off-by: Johan Jonker
Reviewed-by: Kever Yang
---
drivers/mtd/nand/raw/nand_ids.c | 3 +++
1 file changed, 3 insertions(+)
diff --git
The fdt_addr_t and phys_addr_t size have been decoupled.
A 32bit CPU can expect 64-bit data from the device tree parser,
so use a reg variable with phys_addr_t size in the
rk_pwm.c file.
Signed-off-by: Johan Jonker
---
Changed V6:
new patch
---
drivers/pwm/rk_pwm.c | 2 +-
1 file changed, 1
CONFIG_SF_DEFAULT_SPEED is used in SPL SPI to configure and probe the
flash device during DM SPI uclass probing process, if the
spi-max-frequency is not available in the DTB. Currently the max
frequency is not available, because of the probing mechanism in SPI
uclass has not been fully updated to
Hi Quentin,
On Mon, 6 Feb 2023 at 03:26, Quentin Schulz
wrote:
>
> Hi Simon,
>
> On 2/4/23 23:24, Simon Glass wrote:
> > Implement this feature since it is useful for updating FITs within an
> > image.
> >
> > Signed-off-by: Simon Glass
> > ---
> >
> > tools/binman/binman.rst | 16
On Thu, Mar 02, 2023 at 07:05:50PM +0900, Masahisa Kojima wrote:
> On Thu, 2 Mar 2023 at 14:16, Takahiro Akashi
> wrote:
> >
> > On Wed, Mar 01, 2023 at 06:15:20PM +0900, Masahisa Kojima wrote:
> > > Current FMP->GetImageInfo() always return 0 for the firmware
> > > version, user can not
The fdt_addr_t and phys_addr_t size have been decoupled. A 32bit CPU
can expect 64-bit data from the device tree parser, so use
dev_read_addr_index_ptr instead of the dev_read_addr_index function
in the various files in the drivers directory that cast to a pointer.
Signed-off-by: Johan Jonker
The fdt_addr_t and phys_addr_t size have been decoupled. A 32bit CPU
can expect 64-bit data from the device tree parser, so use
dev_read_addr_ptr instead of the dev_read_addr function in the
various files in the drivers directory that cast to a pointer.
Signed-off-by: Johan Jonker
Reviewed-by:
The fdt_addr_t and phys_addr_t size have been decoupled.
A 32bit CPU can expect 64-bit data from the device tree parser,
so use devfdt_get_addr_index_ptr and devfdt_get_addr_size_index_ptr
function in the spi-aspeed-smc.c file. Also fix dev_dbg to be able
to handle both sizes.
Signed-off-by:
Add devfdt_get_addr_size_index_ptr function with the same
functionality as devfdt_get_addr_size_index, but instead
a return pointer is given.
Suggested-by: Michael Nazzareno Trimarchi
Signed-off-by: Johan Jonker
Reviewed-by: Michael Trimarchi
---
Changed V5:
fix spelling
use tabs
---
Add dev_read_addr_index_ptr function with the
same functionality as dev_read_addr_index,
but instead a return pointer is given.
Use map_sysmem() function as cast for the return.
Make same fix for dev_read_addr_ptr() function.
Signed-off-by: Johan Jonker
---
Changed V6:
use map_sysmem()
On Thu, Mar 2, 2023 at 5:26 PM Tony Dinh wrote:
>
> CONFIG_SF_DEFAULT_SPEED is used in SPL SPI to configure and probe the
> flash device during DM SPI uclass probing process, if the
> spi-max-frequency is not available in the DTB. Currently the max
> frequency is not available, because of the
This is the initial basic config for StarFive VisionFive v2 board. It
includes consol, Norflash, sdio, ddr etc.
Signed-off-by: Yanhong Wang
---
configs/starfive_visionfive2_defconfig | 79 ++
1 file changed, 79 insertions(+)
create mode 100644
Add initial device tree for the JH7110 RISC-V SoC.
Signed-off-by: Yanhong Wang
---
arch/riscv/dts/jh7110.dtsi | 582 +
1 file changed, 582 insertions(+)
create mode 100644 arch/riscv/dts/jh7110.dtsi
diff --git a/arch/riscv/dts/jh7110.dtsi
Add initial device tree for StarFive VisionFive v2 board.
Signed-off-by: Yanhong Wang
---
arch/riscv/dts/Makefile | 3 +-
...10-starfive-visionfive-2-v1.2a-u-boot.dtsi | 85 ++
.../jh7110-starfive-visionfive-2-v1.2a.dts| 12 +
Add Kconfig to select the basic functions for StarFive VisionFive v2 Board.
Signed-off-by: Yanhong Wang
---
board/starfive/visionfive2/Kconfig | 53 ++
1 file changed, 53 insertions(+)
create mode 100644 board/starfive/visionfive2/Kconfig
diff --git
CONFIG_SF_DEFAULT_SPEED is used in SPL SPI to configure and probe the
flash device during DM SPI uclass probing process, if the
spi-max-frequency is not available in the DTB. Currently the max
frequency is not available, because of the probing mechanism in SPI
uclass has not been fully updated to
On 2023-03-02 22:05:43 +0100, Marek Vasut wrote:
> On 3/2/23 19:51, Janne Grunau wrote:
> > On 2023-03-02 18:33:15 +0100, Marek Vasut wrote:
> > > On 3/2/23 10:14, Janne Grunau wrote:
> > > > On 2023-03-01 23:51:14 +0100, Marek Vasut wrote:
> > > > > On 3/1/23 21:34, Simon Glass wrote:
> > > > > >
The following changes since commit 49cba67852f1fb5ef481bef3532b2cda96816e45:
Merge branch 'next' of
https://source.denx.de/u-boot/custodians/u-boot-marvell into next
(2023-03-01 11:00:22 -0500)
are available in the Git repository at:
git://source.denx.de/u-boot-usb.git next
for you to
The compatible string for rk3308 has as fallback string
"rockchip,rv1108-nfc". As there is no logic in probe priority between
the SoC orientated string and the fall back, so remove the compatible
string "rockchip,rk3308-nfc" from the driver.
Signed-off-by: Johan Jonker
Reviewed-by: Kever Yang
The MTD framework in U-boot is not identical for drivers ported
from Linux. The rockchip_nfc driver was ported with OOB ops functions
while the framework expects a layout structure per chip.
Fix by adding a structure with OOB data and remove unused functions.
Signed-off-by: Johan Jonker
The MTD framework reserves 1 or 2 bytes for the bad block marker
depending on the bus size. The rockchip_nfc driver currently only
supports a 8 bit bus, but reserves standard 2 bytes for the BBM.
The first free OOB byte is therefore OOB2 at offset 2.
Page address(PA) bytes are moved to the last 4
Add flash_node to the rockchip_nfc driver chip structure in order
to find the partitions in the add_mtd_partitions_of() function.
Signed-off-by: Johan Jonker
Reviewed-by: Kever Yang
Reviewed-by: Michael Trimarchi
---
drivers/mtd/nand/raw/rockchip_nfc.c | 1 +
1 file changed, 1 insertion(+)
Hi Kamlesh!
On March 2, 2023 thus sayeth kaml...@ti.com:
> From: Kamlesh Gurudasani
>
> Add support for high security bootflow on am62 devices.
>
> On HS devices, ROM and TIFS will protect the RAM regions with
> firewalls. This means the wakeup domain's SPL will need to move the
> stack and
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