El Mon, Oct 23, 2023 at 10:21:52AM +0200, Heinrich Schuchardt deia:
>
> We will need separate patches for LGPL-2.0+ and LGPL-2.1+, too.
>
That'd be for LGPL-2.1+
The only case of LGPL-2.0+ in code is included in the patch you sent.
Well, there's another appearance of LGPL-2.0+ in
El Sun, Oct 22, 2023 at 07:47:07PM +0200, Heinrich Schuchardt deia:
> diff --git a/drivers/sound/tegra_ahub.c b/drivers/sound/tegra_ahub.c
> index 495a29c513..28f392504d 100644
> --- a/drivers/sound/tegra_ahub.c
> +++ b/drivers/sound/tegra_ahub.c
> @@ -1,4 +1,4 @@
> -// SPDX-License-Identifier:
On Mon, 23 Oct 2023 00:02:09 -0700, Simon Glass wrote:
> This series makes another attempt to support things like "mmc" in the
> boot_targets variable. The previous attempt introduced a bug which made
> iteration fail.
>
> New test coverage is provided for some previously untested behaviour, to
On Wed, 11 Oct 2023 13:26:42 -0700, Tony Dinh wrote:
> Add ahci sata bootdev and corresponding hunting function.
>
>
I know this is recent but given their importance, applied to u-boot/master,
thanks!
--
Tom
On Fri, 06 Oct 2023 20:34:28 -0700, Tony Dinh wrote:
> It's normal to have no SATA drive attached to the controller, so return a
> successful status when there is no block device found after probing.
>
> Note: this patch depends on the previous patch
>
Hi Caleb,
On Sat, 21 Oct 2023 at 01:43, Caleb Connolly wrote:
>
> Hi Simon,
>
> On 21/10/2023 01:45, Simon Glass wrote:
> > U-Boot typically sets up its malloc() pool near the top of memory. On
> > ARM64 systems this can result in an SMBIOS table above 4GB which is
> > not supported by SMBIOSv2.
On Sun, Oct 22, 2023 at 11:40:43PM +0200, Marek Vasut wrote:
> The R-Car Gen3 SD_CLK_CTRL register does not use BIT(16) to implement
> divider 1/1024, instead BIT(16) is reserved bit and divider 1/1024 is
> not supported. The divider 1/1024 is specific to Socionext variant of
> the IP, as is
On Sat, 21 Oct 2023 at 23:20, Heinrich Schuchardt
wrote:
>
> When compiling the sandbox with CONFIG_LTO=n, CONFIG_NET=n an error is
> reported:
>
> /usr/bin/ld: lib/efi_loader/efi_device_path.o:
> in function `efi_dp_from_eth':
> lib/efi_loader/efi_device_path.c:985:(.text+0xcf4):
>
Hi Heinrich,
On Sun, 22 Oct 2023 at 10:48, Heinrich Schuchardt
wrote:
>
> SPDX headers should use GPL-2.0-or-later and not GPL-2.0+.
>
> Signed-off-by: Heinrich Schuchardt
> ---
> Makefile | 2 +-
> README
On Sun, 22 Oct 2023 at 09:20, Heinrich Schuchardt <
heinrich.schucha...@canonical.com> wrote:
> When compiling the sandbox with CONFIG_LTO=n, CONFIG_NET=n an error is
> reported:
>
> /usr/bin/ld: lib/efi_loader/efi_device_path.o:
> in function `efi_dp_from_eth':
>
When symbols switch between the inited data section and the read-only
data section their visbility changes, at present, with the -B option.
This is confusing, since adding 'const' to a variable declaration can
make it look like a significant improvement in bloat. But in fact
nothing has changed.
This series extends the functionality of ti-secure-rom entry type in
binman to support enabling of split mode vs. the default lockstep mode
via changing the field in the x509 certificate. A DONOTMERGE patch is
added to give an example of how this can be done via the binman.dtsi
Changes in v4:
According to the TRMs of K3 platform of devices, the ROM boot image
format specifies a "Core Options Field" that provides the capability to
set the boot core in lockstep when set to 0 or to split mode when set
to 2. Add support for providing the same from the binman DTS. Also
modify existing test
Set boot core-opts to enable split mode for MCU R5 cluster by default.
This patch serves to demonstrate how this can be done.
Signed-off-by: Neha Malcom Francis
---
No change since v2
arch/arm/dts/k3-j7200-binman.dtsi | 3 +++
1 file changed, 3 insertions(+)
diff --git
label might have been set by a non device-tree based U-Boot driver already.
In my concrete case there is a PCI driver that uses device_bind_driver(..)
for different class types. The UCLASS_LED specific driver sets label
in its bind function.
Without this change the LEDs exposed by the PCI device
On 10/23/23 09:05, Simon Glass wrote:
Hi Heinrich,
On Sun, 22 Oct 2023 at 10:48, Heinrich Schuchardt
wrote:
SPDX headers should use GPL-2.0-or-later and not GPL-2.0+.
Signed-off-by: Heinrich Schuchardt
---
Makefile | 2 +-
README
Add uart baud rate table to arbel(npcm8xx) and poleg(npcm7xx)
Signed-off-by: Jim Liu
Changes for v2:
- Add commit message
Changes for v3:
- Modify CONFIG_SYS_BAUDRATE_TABLE
Changes for v4:
- No change
---
include/configs/arbel.h | 5 -
include/configs/poleg.h | 2 ++
2 files
1. Add name for gpio pinctrl function
2. Add baud rate table
3. Fix ecc ram size
- ECC ram size
- Fix wrong place to set dram bank size
4. Modify configs
Jim Liu (4):
pinctrl: npcm8xx: add name for gpio function
configs: npcm: support more uart baud rate
board: nuvuton: arbel: fix
1. Fix incorrect ram size of 4GB dram with ECC enabled
2. Fix wrong place to set dram bank size
- The dram bank size should be set in dram_init_banksize
- Dram_init should not access gd->bd because the board info
struct is not reserved yet.
Signed-off-by: Jim Liu
Changes for v2:
-
GPIO function name is needed in the debug log
Signed-off-by: Jim Liu
Changes for v2:
- add commit message
Changes for v3:
- no change
Changes for v4:
- no change
---
drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c | 1 +
1 file changed, 1 insertion(+)
diff --git
disable this config to improve flash program time
Signed-off-by: Jim Liu
Changes for v2:
- add commit message
Changes for v3:
- no change
Changes for v4:
- no change
---
configs/arbel_evb_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/configs/arbel_evb_defconfig
Describe flash memories based on the latest DT binding.
Signed-off-by: Michal Simek
---
Changes in v2:
- Add missing description for zc706
arch/arm/dts/zynq-zc706.dts | 5 +++--
arch/arm/dts/zynq-zc770-xm013.dts | 5 +++--
arch/arm/dts/zynqmp-m-a2197-01-revA.dts | 4 +++-
Hi Neha,
On Mon, 23 Oct 2023 at 00:06, Neha Malcom Francis wrote:
>
> Hi Simon
>
> On 19/10/23 19:25, Simon Glass wrote:
> > Hi Neha,
> >
> > On Tue, 17 Oct 2023 at 23:20, Neha Malcom Francis wrote:
> >>
> >> Hi Simon
> >>
> >> On 18/10/23 09:03, Simon Glass wrote:
> >>> Hi Neha,
> >>>
> >>> On
On 2023/10/18 22:01, Johan Jonker wrote:
Currently bounce buffer support is enabled for all block devices
when available. Add a flag to blk_desc to enable only on demand.
Signed-off-by: Johan Jonker
Reviewed-by: Kever Yang
Thanks,
- Kever
---
Changed V5:
New patch
---
On 19/10/2023 15.54, Marek Vasut wrote:
> On 10/19/23 11:58, Rasmus Villemoes wrote:
>> If the driver's own .bind method has populated uc_plat->label, don't
>> override that. This is necessary for an upcoming driver for ti,lp5562,
>> where the DT binding unfortunately says to use "chan-name" and
This series makes another attempt to support things like "mmc" in the
boot_targets variable. The previous attempt introduced a bug which made
iteration fail.
New test coverage is provided for some previously untested behaviour, to
prevent regressions.
Simon Glass (4):
Revert "bootstd: Scan
Scan the USB bus as well, so we can check that different uclasses work
correctly in boot_targets
update the function comment with more detail.
Signed-off-by: Simon Glass
---
test/boot/bootdev.c | 17 ++---
1 file changed, 14 insertions(+), 3 deletions(-)
diff --git
This commit was intended to allow all bootdevs in each boot_targets
entry to be scanned. However it causes bad ordering with bootdevs, e.g.
scanning Ethernet bootdevs when it should be keeping to mmc.
Revert it so we can try another approach.
This reverts commit
The current logic for "bootflow mmc" is flawed since it checks the
uclass of the bootdev instead of its parent, the media device. Correct
this and add a test that covers this scenario.
Signed-off-by: Simon Glass
---
boot/bootflow.c | 24 ++--
test/boot/bootdev.c | 13
When the boot_targets environment variable is used with the distro-boot
scripts, each device is included individually. For example, if there
are three mmc devices, then we will have something like:
boot_targets="mmc0 mmc1 mmc2"
In contrast, standard boot supports specifying just the uclass,
Hi Heinrich,
On Sat, 21 Oct 2023 at 21:53, Heinrich Schuchardt
wrote:
>
> On 10/21/23 17:42, Simon Glass wrote:
> > Hi Tom,
> >
> > On Fri, 20 Oct 2023 at 09:24, Tom Rini wrote:
> >>
> >> On Fri, Oct 20, 2023 at 05:40:03PM +0200, Heinrich Schuchardt wrote:
> >>> On 20.10.23 15:21, Simon Glass
On 19/10/2023 15.51, Marek Vasut wrote:
> On 10/19/23 11:58, Rasmus Villemoes wrote:
>> Many existing drivers, and led-uclass itself, rely on uc_plat->label
>> being NULL for the device representing the top node, as opposed to the
>> child nodes representing individual LEDs. This means that the
Hi Tom,
On Sun, 22 Oct 2023 at 16:45, Tom Rini wrote:
>
> On Sun, Oct 22, 2023 at 02:55:32PM -0700, Simon Glass wrote:
> > Hi,
> >
> > On Sun, 22 Oct 2023 at 07:59, Tom Rini wrote:
> > >
> > > On Sun, Oct 22, 2023 at 10:29:22AM -0400, Tom Rini wrote:
> > > > On Sun, Oct 22, 2023 at 08:08:11AM
Hi Simon
On 19/10/23 19:25, Simon Glass wrote:
Hi Neha,
On Tue, 17 Oct 2023 at 23:20, Neha Malcom Francis wrote:
Hi Simon
On 18/10/23 09:03, Simon Glass wrote:
Hi Neha,
On Tue, 17 Oct 2023 at 03:58, Neha Malcom Francis wrote:
Hi Simon
On 08/10/23 04:39, Simon Glass wrote:
Hi Neha,
Hi Tom,
On Sat, 21 Oct 2023 at 11:34, Tom Rini wrote:
>
> On Sat, Oct 21, 2023 at 08:43:00AM -0700, Simon Glass wrote:
> > On Fri, 20 Oct 2023 at 14:53, Tom Rini wrote:
> > >
> > > The primary motivation for having a sandbox without LTO build in CI is
> > > to ensure that we don't have that
On 10/23/23 09:08, Simon Glass wrote:
Hi Heinrich,
On Sat, 21 Oct 2023 at 21:53, Heinrich Schuchardt
wrote:
On 10/21/23 17:42, Simon Glass wrote:
Hi Tom,
On Fri, 20 Oct 2023 at 09:24, Tom Rini wrote:
On Fri, Oct 20, 2023 at 05:40:03PM +0200, Heinrich Schuchardt wrote:
On 20.10.23
On 10/23/23 10:21, Christian Gmeiner wrote:
label might have been set by a non device-tree based U-Boot driver already.
In my concrete case there is a PCI driver that uses device_bind_driver(..)
for different class types. The UCLASS_LED specific driver sets label
in its bind function.
Without
On 10-23 00:02, Simon Glass wrote:
>
> This series makes another attempt to support things like "mmc" in the
> boot_targets variable. The previous attempt introduced a bug which made
> iteration fail.
>
> New test coverage is provided for some previously untested behaviour, to
> prevent
On 2023/10/18 01:02, Jonas Karlman wrote:
Enable Kconfig options for the two USB 2.0 ports and bottom USB 3.0 port
on ROCK 5 Model A.
Signed-off-by: Jonas Karlman
Reviewed-by: Kever Yang
Thanks,
- Kever
---
v2:
- New patch
configs/rock5a-rk3588s_defconfig | 16 +++-
1
On 2023/10/18 01:02, Jonas Karlman wrote:
The device tree for rk3588 and rock-5b contain usb3 nodes that have
deviated too much from current state of submitted mainline linux usb3
patches, see [1].
Sync usb3 related nodes from latest patches and collaboras rk3588 tree
so that dwc3-generic
On 2023/10/18 05:40, Jonas Karlman wrote:
Xunlong Orange Pi 5 Plus is a single-board computer based on the
Rockchip RK3588 SoC. The board provides abundant interfaces, including
two HDMI output ports, one HDMI input port, two 2.5G Ethernet ports,
M.2 M-Key slot, M.2 E-Key slot, two USB 3.0,
On 2023/10/18 05:40, Jonas Karlman wrote:
Xunlong Orange Pi 5 is a single-board computer based on the Rockchip
RK3588S SoC. The board provides abundant interfaces, HDMI output, GPIO
interface, M.2 PCIe2.0, Type-C, Gigabit LAN port, 2*USB2.0, 1*USB3.0,
etc.
Features tested on a Orange Pi 5 4GB
On 10/23/23 11:11, Rasmus Villemoes wrote:
On 19/10/2023 15.58, Marek Vasut wrote:
On 10/19/23 11:58, Rasmus Villemoes wrote:
From: Doug Zobel
Driver for the TI LP5562 4 channel LED controller. Supports
independent on/off control of all 4 channels. Supports LED_BLINK on 3
independent
On 10/23/23 10:51, Rasmus Villemoes wrote:
On 19/10/2023 15.54, Marek Vasut wrote:
On 10/19/23 11:58, Rasmus Villemoes wrote:
If the driver's own .bind method has populated uc_plat->label, don't
override that. This is necessary for an upcoming driver for ti,lp5562,
where the DT binding
On 2023/10/17 23:59, Tom Fitzhenry wrote:
QuartzPro64 is a Rockchip RK3588 based SBC by Pine64.
UART and boot over SD/eMMC/RJ45 are tested to work.
Linux commits from next-20231013:
8152d3d070a9 ("arm64: dts: rockchip: Add QuartzPro64 SBC device tree")
Signed-off-by: Tom Fitzhenry
Cc:
Hi Tom,
please pull video driver updates for v2024.01-rc1.
CI: https://source.denx.de/u-boot/custodians/u-boot-video/-/pipelines/18257
Thanks!
The following changes since commit 9a3a58396b78b1f9d0c14580dc03f81d29207dd2:
Merge https://source.denx.de/u-boot/custodians/u-boot-marvell
On 10/23/23 10:28, Rasmus Villemoes wrote:
On 19/10/2023 15.51, Marek Vasut wrote:
On 10/19/23 11:58, Rasmus Villemoes wrote:
Many existing drivers, and led-uclass itself, rely on uc_plat->label
being NULL for the device representing the top node, as opposed to the
child nodes representing
Am Mo., 23. Okt. 2023 um 11:30 Uhr schrieb Rasmus Villemoes
:
>
> On 19/10/2023 15.54, Marek Vasut wrote:
> > On 10/19/23 11:58, Rasmus Villemoes wrote:
> >> If the driver's own .bind method has populated uc_plat->label, don't
> >> override that. This is necessary for an upcoming driver for
branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sh
(2023-10-17 09:15:56 -0400)
are available in the Git repository at:
https://source.denx.de/u-boot/custodians/u-boot-amlogic.git
tags/u-boot-amlogic-20231023
for you to fetch changes up
On 19/10/2023 15.58, Marek Vasut wrote:
> On 10/19/23 11:58, Rasmus Villemoes wrote:
>> From: Doug Zobel
>>
>> Driver for the TI LP5562 4 channel LED controller. Supports
>> independent on/off control of all 4 channels. Supports LED_BLINK on 3
>> independent channels: blue/green/red. The white
On 2023/10/18 02:24, Chris Morgan wrote:
From: Chris Morgan
Add support for the Powkiddy RK2023 and RGB30 to the Anbernic RGxx3.
While these devices are manufactured by Powkiddy instead of Anbernic,
the hardware is so similar they can all use the same bootloader.
Signed-off-by: Chris Morgan
Hi Chris,
On 2023/10/18 02:24, Chris Morgan wrote:
From: Chris Morgan
Add support for users to enter maskrom mode by holding the function
button when they power up the device.
Since the device has soldered eMMC and sometimes does not expose a clk
pin on the mainboard
This board already
On 2023/10/18 05:40, Jonas Karlman wrote:
From: Ricardo Pardini
Add support for XMC XM25QU128C (128M-bit) Serial Flash memory. Used on
the Xunlong Orange Pi 3B, 5 and 5 Plus boards.
Datasheet:
https://www.xmcwh.com/uploads/806/XM25QU128C_Ver2.0.pdf
Signed-off-by: Ricardo Pardini
On 2023/10/17 23:59, Tom Fitzhenry wrote:
This brings in more colours, e.g. ORANGE needed for the QuartzPro64 DT.
Linux commits:
472d7b9e8141 ("dt-bindings: leds: Expand LED_COLOR_ID definitions")
Signed-off-by: Tom Fitzhenry
Reviewed-by: Kever Yang
Thanks,
- Kever
---
On 2023/10/17 23:59, Tom Fitzhenry wrote:
QuartzPro64 is a Rockchip RK3588 based SBC by Pine64.
UART and boot over SD/eMMC/RJ45 are tested to work.
Linux commits from next-20231013:
8152d3d070a9 ("arm64: dts: rockchip: Add QuartzPro64 SBC device tree")
Signed-off-by: Tom Fitzhenry
Cc:
Hi Tom,
please pull the sunxi/master branch, containing the first part of the
2024.01 changes. Apologies for the late PR, there were quite some recent
activities (fixes and reviews), but I didn't want to delay this series
any longer, since it's been around one year in the making already:
This is
On 23/10/2023 11.39, Marek Vasut wrote:
> On 10/23/23 11:11, Rasmus Villemoes wrote:
>> On 19/10/2023 15.58, Marek Vasut wrote:
>>> On 10/19/23 11:58, Rasmus Villemoes wrote:
From: Doug Zobel
Driver for the TI LP5562 4 channel LED controller. Supports
independent on/off
QuartzPro64 is a Rockchip RK3588 based SBC by Pine64.
UART and boot over SD/eMMC/RJ45 are tested to work.
Linux commits from next-20231013:
8152d3d070a9 ("arm64: dts: rockchip: Add QuartzPro64 SBC device tree")
Signed-off-by: Tom Fitzhenry
Reviewed-by: Kever Yang
Cc: Eugen Hristev
Cc: Jonas
This brings in more colours, e.g. ORANGE needed for the QuartzPro64 DT.
Linux commits:
472d7b9e8141 ("dt-bindings: leds: Expand LED_COLOR_ID definitions")
Signed-off-by: Tom Fitzhenry
Reviewed-by: Kever Yang
---
include/dt-bindings/leds/common.h | 7 ++-
1 file changed, 6 insertions(+), 1
Changes since v2:
* Rebase on pending DT sync patch.
* Collect r-b tags.
Changes since v1:
* Sync recently added DT from linux-next
* Sync led dt-bindings
Tom Fitzhenry (2):
dt-bindings: leds: import common led bindings from linux v6.5
board: rockchip: add Pine64 QuartzPro64 RK3588 board
Kever Yang writes:
> On 2023/10/17 23:59, Tom Fitzhenry wrote:
>> This patch depends on "rockchip: rk3588: Sync device tree from linux
>> maintainer tree"[0], since the QuartzPro64 upstream DT depends on upstream
>> dtsi changes.
>
> This patch has been update to V2, and your patch are not
On 23.10.23 15:43, Tom Rini wrote:
On Sun, Oct 22, 2023 at 07:47:07PM +0200, Heinrich Schuchardt wrote:
SPDX headers should use GPL-2.0-or-later and not GPL-2.0+.
Signed-off-by: Heinrich Schuchardt
So, first, iirc GPL-2.0+ is deprecated, but still valid, yes? We should
use the current form
On Mon, Oct 23, 2023 at 03:51:39PM +0200, Heinrich Schuchardt wrote:
> On 23.10.23 15:43, Tom Rini wrote:
> > On Sun, Oct 22, 2023 at 07:47:07PM +0200, Heinrich Schuchardt wrote:
> >
> > > SPDX headers should use GPL-2.0-or-later and not GPL-2.0+.
> > >
> > > Signed-off-by: Heinrich Schuchardt
Hi Vishal!
+Tom
On October 23, 2023 thus sayeth Vishal Mahaveer:
> PLL calibration needs to be enabled when operating in non fractional
> mode. Add the sequence to do a fast calibration when using PLL
> in this mode.
>
> Signed-off-by: Vishal Mahaveer
Reviewed-by: Bryan Brattlof
> ---
>
On 10/18/23 17:00, Artur Rojek wrote:
Hi all,
this is v5 of the Conclusive KSTR-SAMA5D27 support series.
Patches [1/4], [2/4] and [3/4] remain unchanged.
In patch [4/4], a new dtsi file has been added in order to keep U-Boot
specific properties separate from the main dts. As such, MAINTAINERS
Hello Tom,
Please pull tag u-boot-at91-2024.01-b , the second set of at91 features
for 2024.01 cycle.
This feature set a new board named Conclusive KSTR sama5d27 with some
small prerequisites patches.
Thanks,
Eugen
The following changes since commit
From: Hugo Villeneuve
The address ariel.dalessan...@collabora.com is no longer working:
A message that you sent could not be delivered to one or more of its
recipients. This is a permanent error. The following address(es) failed:
ariel.dalessan...@collabora.com
host
Update the list of defconfigs, this was missed with the last pull
request of the u-boot-riscv tree.
Signed-off-by: Tom Rini
---
board/AndesTech/ae350/MAINTAINERS | 12
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/board/AndesTech/ae350/MAINTAINERS
> From: Simon Glass
> Date: Mon, 23 Oct 2023 00:04:14 -0700
>
> Hi Caleb,
>
> On Sat, 21 Oct 2023 at 01:43, Caleb Connolly
> wrote:
> >
> > Hi Simon,
> >
> > On 21/10/2023 01:45, Simon Glass wrote:
> > > U-Boot typically sets up its malloc() pool near the top of memory. On
> > > ARM64 systems
> From: Simon Glass
> Date: Mon, 23 Oct 2023 00:08:40 -0700
>
> > > fdt_node_check_compatible() does most of the work...then you need to
> > > check which FDT has the most specific match (i.e. latest in the string
> > > list). That handles things like board revisions, variants, etc.
> > >
> > >
At this point we have all of the defconfigs maintained again, so
re-enable the check to prevent further regressions.
Signed-off-by: Tom Rini
---
.azure-pipelines.yml | 2 +-
.gitlab-ci.yml | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/.azure-pipelines.yml
On Mon, Oct 23, 2023 at 05:37:34PM +0200, Mark Kettenis wrote:
> > From: Simon Glass
> > Date: Mon, 23 Oct 2023 00:08:40 -0700
> >
> > > > fdt_node_check_compatible() does most of the work...then you need to
> > > > check which FDT has the most specific match (i.e. latest in the string
> > > >
Hi Simon,
Thanks for the review.
On 19/10/23 19:26, Simon Glass wrote:
> Hi Devarsh,
>
> On Mon, 16 Oct 2023 at 10:06, Devarsh Thakkar wrote:
>>
>> Move the function to setup video memory before page table
>> reservation so that framebuffer memory gets reserved from
>> the end of RAM.
>>
>>
Enable DFU as an alternate USB boot method when script wasn't
uploaded, this fixes USB full boot on G12/SM1 boards.
Signed-off-by: Neil Armstrong
---
configs/ad401_defconfig| 2 ++
configs/bananapi-cm4-cm4io_defconfig | 2 ++
configs/bananapi-m2-pro_defconfig | 2 ++
Allow all boards to boot with a fitImage, but keep support for
Legacy image format for now.
Signed-off-by: Neil Armstrong
---
configs/bananapi-cm4-cm4io_defconfig | 4
configs/bananapi-m2-pro_defconfig | 4
configs/bananapi-m2s_defconfig| 4
Add boot over DFU RAM as an alternate to running script at
a fixed address like done today.
The main culprit is that it's not possible to do that
on G12A/Sm1 platforms due to changes in the USB boot protocol.
With this, U-Boot will present a DFU device with a ram slot where
the Host could write
In order to reuse addresses for DFU RAM, define them separately,
it's cleaner and will be easier to override.
Signed-off-by: Neil Armstrong
---
include/configs/meson64.h | 23 ---
1 file changed, 16 insertions(+), 7 deletions(-)
diff --git a/include/configs/meson64.h
From: Sam Edwards
Since the sunxi support nowadays generally prefers #defined register
offsets instead of modeling register layouts using C structs, now is a
good time to do this for PSCI as well. This patch moves away from using
the structs `sunxi_cpucfg_reg` and `sunxi_prcm_reg` in psci.c.
From: Sam Edwards
This patch adds the necessary code to make nonsec booting and PSCI
secondary core management functional on the R528/T113.
Signed-off-by: Sam Edwards
Tested-by: Maksim Kiselev
Tested-by: Kevin Amadiva
Reviewed-by: Andre Przywara
---
arch/arm/cpu/armv7/Kconfig | 3 +-
The MangoPi MQ-R board uses an Allwinner T113s Soc (with 128MB of
embedded DRAM), support for which was just added to the code.
Since the devicetree was already synced from the latest Linux kernel
tree, all we need is a _defconfig file to add support for the board.
Signed-off-by: Andre Przywara
On Mon, Oct 23, 2023 at 12:05:34AM -0700, Simon Glass wrote:
> Hi Tom,
>
> On Sat, 21 Oct 2023 at 11:34, Tom Rini wrote:
> >
> > On Sat, Oct 21, 2023 at 08:43:00AM -0700, Simon Glass wrote:
> > > On Fri, 20 Oct 2023 at 14:53, Tom Rini wrote:
> > > >
> > > > The primary motivation for having a
On Mon, Oct 23, 2023 at 12:52:43AM -0700, Simon Glass wrote:
> When symbols switch between the inited data section and the read-only
> data section their visbility changes, at present, with the -B option.
>
> This is confusing, since adding 'const' to a variable declaration can
> make it look
On Mon, Oct 23, 2023 at 12:05:28AM -0700, Simon Glass wrote:
> Hi Tom,
>
> On Sun, 22 Oct 2023 at 16:45, Tom Rini wrote:
> >
> > On Sun, Oct 22, 2023 at 02:55:32PM -0700, Simon Glass wrote:
> > > Hi,
> > >
> > > On Sun, 22 Oct 2023 at 07:59, Tom Rini wrote:
> > > >
> > > > On Sun, Oct 22, 2023
So far every Allwinner SoC used the same basic pincontroller/GPIO
register frame, and just differed by the number of implemented banks and
pins, plus some special functionality from time to time. However the D1
and successors use a slightly different pinctrl register layout.
Use that opportunity
On the Allwinner platform we were describing a quite comprehensive
memory map in a per-SoC header unser arch/arm.
In the old days that was used by every driver, but nowadays it should
only be needed by SPL drivers (not using the DT). Many addresses in
there were never used, and some are not needed
For the first time since at least the Allwinner A10 SoCs, the D1 (and
related cores) use a new pincontroller MMIO register layout, so we
cannot use our hardcoded, fixed offsets anymore.
Ideally this would all be handled by devicetree and DM drivers, but for
the DT-less SPL we still need the legacy
Allwinner seems to typically stick to a common MMIO memory map for
several SoCs, but from time to time does some breaking changes, which
also introduce new generations of some peripherals. The last time this
happened with the H6, which apart from re-organising the base addresses
also changed the
Apart from using the new pinctrl MMIO register layout, the Allwinner D1
and related SoCs still need to usual set of mux values hardcoded in
U-Boot's pinctrl driver.
Add the values we need so far to this list, so that DM based drivers
will just work without further ado.
Signed-off-by: Andre
So far we were open-coding the pincontroller's GPIO output/input access
in each function using that.
Provide functions that wrap that nicely, and follow the existing pattern
(set/get_{bank,}), so users don't need to know about the internals, and
we can abstract the new D1 pinctrl more easily.
From: Samuel Holland
Since the D1 CCU binding is defined, we can add support for its
gates/resets, following the pattern of the existing drivers.
Signed-off-by: Samuel Holland
Reviewed-by: Andre Przywara
Acked-by: Sean Anderson
Signed-off-by: Andre Przywara
---
drivers/clk/sunxi/Kconfig
The D1/R528/T113s SoCs introduce a new "LDO enable" bit in the CPUX_PLL.
Just enable that when we program that PLL.
Signed-off-by: Andre Przywara
---
arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h | 1 +
arch/arm/mach-sunxi/clock_sun50i_h6.c | 12 +++-
2 files changed, 8
The PLL_PERIPH0 clock changed a bit in the D1/R528/T113s SoCs: there is
new P0 divider at bits [18:16], and the M divider is 1.
Add code to support this version of "PLL6".
Signed-off-by: Andre Przywara
---
.../include/asm/arch-sunxi/clock_sun50i_h6.h | 2 ++
At the moment all Allwinner DRAM initialisation routines are stored in
arch/arm/mach-sunxi, even though those "drivers" are just a giant
collection of writel's, without any architectural dependency.
The R528/T113-s SoC (with ARM cores) and the D1/D1s Soc (with RISC-V
cores) share the same die, so
The Allwinner R528/T113-s/D1/D1s SoCs all share the same die, so use the
same DRAM initialisation code.
Make use of prior art here and lift some code from awboot[1], which
carried init code based on earlier decompilation efforts, but with a
GPL2 license tag.
This code has been heavily reworked and
From: Okhunjon Sobirjonov
Add support for eMMC (SMHC2) pin pull ups for R528 boards.
The D1 and T113s (and even R329) SoCs do not support 8-bit eMMC anymore,
so it's just four data pins to cover here.
Signed-off-by: Okhunjon Sobirjonov
Reviewed-by: Andre Przywara
[Andre: adjust commit
This adds the remaining code bits to teach U-Boot about Allwinner's
newest SoC generation. This was introduced with the RISC-V based
Allwinner D1 SoC, which actually shares a die with the ARM cores versions
called R528 (BGA, without DRAM) and T113s (QFP, with embedded DRAM).
This adds the new
At the moment we have each SoC's memory map defined in its own cpu.h,
which is included in include/configs/sunxi_common.h. This will be a
problem with the introduction of Allwinner RISC-V support.
Remove the inclusion of that header file from the common config header,
instead move the required
From: Sam Edwards
This patch restructures psci.c to get away from the "many different
function definitions switched by #ifdef" paradigm to the preferred style
of having a single function definition with `if (IS_ENABLED(...))` to
make the optimizer include only the appropriate function bodies
From: Sam Edwards
This is to prepare for R528, which does not have the typical
"CPUCFG" block; it has a "CPUX" block which provides these
same functions but is organized differently.
Moving the hardware-access bits to their own functions separates the
logic from the hardware so we can reuse the
Move the existing sunxi-specific low level pinctrl routines from
arch/arm/mach-sunxi into the existing GPIO code under drivers/gpio, so
that the common code can be shared outside of arch/arm.
This also takes the opportunity to move some definitions from our
header file into the driver C file, as
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