Hi Michal
Apologies for the late reply
On Wed, 6 Mar 2024 at 09:48, Michal Simek wrote:
>
>
>
> On 3/5/24 16:47, Ilias Apalodimas wrote:
> > On Fri, Feb 23, 2024 at 05:18:42PM +0100, Michal Simek wrote:
> >> There is no reason to describe u-boot.itb on system without SPL. Pretty
> >> much this
On Wed, Feb 21, 2024 at 01:00:14PM +0100, Nam Cao wrote:
> Distro boot scripts are deprecated. Use standard boot instead.
>
> Signed-off-by: Nam Cao
> ---
> configs/starfive_visionfive2_defconfig | 2 +-
> include/configs/starfive-visionfive2.h | 14 +-
> 2 files changed, 2
Add support for i.MX8MP reset controller, it has same reset IP inside
as the other iMX7 and iMX8 variants but with different module layout.
Inspired from counterpart Linux kernel v6.8-rc3 driver:
drivers/reset/reset-imx7.c. Use last Linux kernel driver reference
commit bad8a8afe19f ("reset:
pcie_imx doesn't seem to share any useful code for iMX8MP SoC and it is
rather tied to quite old port of pcie_designware driver from Linux which
suffices only iMX6 specific needs.
But currently we have the common DWC specific bits which alligns pretty
well with DW PCIe controller on iMX8MP SoC.
Add support for PCIe clocks required to enable PCIe support on
iMX8MP SoC.
Tested-by: Tim Harvey #imx8mp-venice*
Tested-by: Adam Ford #imx8mp-beacon-kit
Signed-off-by: Sumit Garg
---
drivers/clk/imx/clk-imx8mp.c | 6 ++
1 file changed, 6 insertions(+)
diff --git
Expose the high performance PLL as a regular Linux clock, so the
PCIe PHY can use it when there is no external refclock provided.
Inspired from counterpart Linux kernel v6.8-rc3 driver:
drivers/pmdomain/imx/imx8mp-blk-ctrl.c. Use last Linux kernel driver
reference commit 7476ddfd36ac ("pmdomain:
Add support for GPCv2 power domains and clock handling for PCIe and
PCIe PHY.
Tested-by: Tim Harvey #imx8mp-venice*
Tested-by: Adam Ford #imx8mp-beacon-kit
Signed-off-by: Sumit Garg
---
drivers/power/domain/imx8mp-hsiomix.c | 114 ++
1 file changed, 78 insertions(+),
imx7_reset_{deassert/assert}_imx* are a bit more confusing when compared
with imx*_reset_{deassert/assert}. So refactor driver to use function
names easier to understand. This shouldn't affect the functionality
though.
Suggested-by: Marek Vasut
Signed-off-by: Sumit Garg
---
power_domain_on/off() isn't refcounted and power domain bus shouldn't be
turned off for a single peripheral domain as it would negatively affect
other peripheral domains. So lets just skip turning off bus power
domain.
Fixes: 898e7610c62a ("imx: power-domain: Add i.MX8MP HSIOMIX driver")
pcie_imx doesn't seem to share any useful code for iMX8 SoC and it is
tied to quite old port of pcie_designware driver from Linux which
suffices only iMX6 specific needs.
But currently we have the common DWC specific bits which alligns pretty
well with DW PCIe controller on iMX8MP SoC. So lets
Add initial support for i.MX8M{M/P} PCIe PHY. On i.MX8M{M/P} SoCs PCIe
PHY initialization moved to this standalone PHY driver.
Inspired from counterpart Linux kernel v6.8-rc3 driver:
drivers/phy/freescale/phy-fsl-imx8m-pcie.c. Use last Linux kernel driver
reference commit 7559e7572c03 ("phy:
Add myself as maintainer for PCIe DWC IMX driver support.
Acked-by: Marek Vasut
Signed-off-by: Sumit Garg
---
MAINTAINERS | 6 ++
1 file changed, 6 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index fbb82b3df5d..e8fd4644fb4 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1378,6
From: Tim Harvey
Enable PCIe/NVMe support. Also, enable the reset, regmap and syscon
drivers which are a prerequisite for PCIe support.
Signed-off-by: Tim Harvey
---
configs/imx8mp_venice_defconfig | 8
1 file changed, 8 insertions(+)
diff --git a/configs/imx8mp_venice_defconfig
Enable PCIe/NVMe support. Also, enable the reset driver which
is a prerequisite for PCIe support.
Acked-by: Francesco Dolcini
Tested-by: Marcel Ziswiler
Signed-off-by: Sumit Garg
---
configs/verdin-imx8mp_defconfig | 6 ++
1 file changed, 6 insertions(+)
diff --git
On Tue, 12 Mar 2024 at 03:03, Volodymyr Babchuk
wrote:
>
> The current behaviour does a bitwise OR of the previous and new
> divider values, this is wrong as some bits maybe be set already. We
nit: s/maybe be/maybe/
> need to clear all the divider bits before applying new ones.
>
> This fixes
On 11/03/24 10:34 am, Anwar, Md Danish wrote:
>
>
> On 3/7/2024 6:16 PM, Tom Rini wrote:
>> On Wed, Feb 28, 2024 at 05:36:45PM +0530, MD Danish Anwar wrote:
>>> Add APIs to set a firmware_name to a rproc and boot the rproc with the
>>
>>> same firmware.
>>>
>>> Clients can call
On Sun, Mar 10, 2024 at 12:54:56AM +0800, Kongyang Liu wrote:
> Add Sophgo cv1800b SoC to support RISC-V arch.
>
> Signed-off-by: Kongyang Liu
> ---
>
> Changes in v2:
> - Remove duplicate code in function cleanup_before_linux
>
> arch/riscv/Kconfig | 1 +
>
Hi Colin,
On ven., mars 08, 2024 at 15:59, Sam Protsenko
wrote:
> On Fri, Mar 8, 2024 at 1:24 PM McAllister, Colin
> wrote:
>>
>> > Ah, ok, I see you replied to my comment here.
>>
>> Yes, sorry. Outlook is terrible to send inline responses too. I figured
>> just adding responses in the patch
On Tue, 12 Mar 2024 at 09:55, Sumit Garg wrote:
>
> Hi Peter,
>
> On Tue, 12 Mar 2024 at 15:13, Peter Robinson wrote:
> >
> > Hi Sumit,
> >
> > > pcie_imx doesn't seem to share any useful code for iMX8MP SoC and it is
> > > rather tied to quite old port of pcie_designware driver from Linux which
On Sun, Mar 10, 2024 at 01:56:46PM +0800, Kongyang Liu wrote:
> Add configs related to ethernet and ethernet boot command for Sophgo Milk-V
> Duo board
>
> Signed-off-by: Kongyang Liu
> ---
>
> configs/milkv_duo_defconfig | 4
> 1 file changed, 4 insertions(+)
Reviewed-by: Leo Yu-Chi
On Sun, Mar 10, 2024 at 01:51:55AM +0800, Kongyang Liu wrote:
> Add sdhci driver for cv1800b SoC.
>
> Signed-off-by: Kongyang Liu
> ---
>
> Changes in v2:
> - Refactored and simplified some of the code.
>
> drivers/mmc/Kconfig | 13
> drivers/mmc/Makefile| 1 +
>
On 3/11/24 12:37, Dan Carpenter wrote:
> On Fri, Mar 08, 2024 at 02:34:04PM +0100, Patrice Chotard wrote:
>> Move variable declaration at the beginning of the function.
>>
>
> The problem, presumably, is that when declarations are in the middle of
> a block then it triggers a GCC warning.
On Mon, 11 Mar 2024 at 17:57, Caleb Connolly wrote:
>
> Hi Sumit,
>
> On 11/03/2024 11:10, Sumit Garg wrote:
> > SE HMIBSC board uses UART1 as the main debug console, so add
> > corresponding clocks and pinmux support. Along with that update
> > instructions to enable clocks for debug UART
Add RAUC boot logic to the environment. This is the first board to
utilize this environment.
Signed-off-by: Leonard Anderweit
---
board/phytec/phycore_imx8mp/phycore_imx8mp.env | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git
Move the environment into the board directory and convert it from a C
header to a text file. Sort the variables alphabetically.
No functional changes.
Signed-off-by: Leonard Anderweit
---
.../phytec/phycore_imx8mp/phycore_imx8mp.env | 45 +++
include/configs/phycore_imx8mp.h
Move the default bootcmd from the defconfig to the board environment.
No change in functionality.
Signed-off-by: Leonard Anderweit
---
board/phytec/phycore_imx8mp/phycore_imx8mp.env | 12
configs/phycore-imx8mp_defconfig | 2 --
2 files changed, 12 insertions(+), 2
Add logic for booting systems with the RAUC update mechanism. This can
be reused by other phytec boards.
Signed-off-by: Leonard Anderweit
---
include/env/phytec/rauc.env | 52 +
1 file changed, 52 insertions(+)
create mode 100644 include/env/phytec/rauc.env
Add support for the redundant environment.
Signed-off-by: Leonard Anderweit
---
configs/phycore-imx8mp_defconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/configs/phycore-imx8mp_defconfig b/configs/phycore-imx8mp_defconfig
index fd492eba3c10..6c67f14b5559 100644
---
On Sun, Mar 10, 2024 at 01:56:44PM +0800, Kongyang Liu wrote:
> Initialize register in cv1800b ethernet phy to make it compatible with
> generic phy driver
>
> Signed-off-by: Kongyang Liu
> ---
>
> board/sophgo/milkv_duo/Makefile | 3 +-
> board/sophgo/milkv_duo/board.c| 4 ++
>
On Sun, Mar 10, 2024 at 01:56:45PM +0800, Kongyang Liu wrote:
> Add ethernet node for cv1800b SoC
>
> Signed-off-by: Kongyang Liu
> ---
>
> arch/riscv/dts/cv18xx.dtsi | 6 ++
> 1 file changed, 6 insertions(+)
Hi KongYang,
Will there be a patch adding this ethernet node for kernel as well
On Mon, 11 Mar 2024 at 20:20, Caleb Connolly wrote:
>
>
>
> On 11/03/2024 13:32, Stephan Gerhold wrote:
> > On Mon, Mar 11, 2024 at 12:27:11PM +, Caleb Connolly wrote:
> >> On 11/03/2024 11:10, Sumit Garg wrote:
> >>> SE HMIBSC board uses UART1 as the main debug console, so add
> >>>
On Sun, Mar 10, 2024 at 01:51:56AM +0800, Kongyang Liu wrote:
> Add clk node and sdhci node for cv18xx SoCs according to patches from Linux
> kernel.
>
> clk:
> https://lore.kernel.org/all/ia1pr20mb4953f9ad6792013b54636f05bb...@ia1pr20mb4953.namprd20.prod.outlook.com/
> sdhci:
From: Hari Nagalla
The K3 J721S2 SoCs have two C71x DSP subsystems in MAIN voltage domain,
and there are no C66x DSP subsystems on these SoCs. The C71x DSP subsystem
is a slighly updated version of the C71x DSP subsystem on J721e. The
C71x DSPs are 64 bit machine with fixed and floating point
This series adds relevant ip data in remoteproc driver for j721s2 compatible.
Logs:
https://gist.githubusercontent.com/apurvanandan1997/276098af439e11105ab9f809159fcc98/raw/
Changes in v3:
- Removed j721s2.env patch from the series
Link to v2:
From: Hari Nagalla
The K3 J721S2 SoCs have three dual-core R5F subsystems, one in MCU
voltage domain and the other two in MAIN voltage domain. These R5F
clusters are similar to the R5F clusters in J7200 SoCs.
Compatible Info is updated to support J721S2 SoCs.
Signed-off-by: Hari Nagalla
On Sun, Mar 10, 2024 at 12:54:57AM +0800, Kongyang Liu wrote:
> Add dcache operations invalidate_dcache_range and flush_dcache_range for
> cv1800b.
>
> Signed-off-by: Kongyang Liu
> ---
>
> (no changes since v1)
>
> arch/riscv/cpu/cv1800b/Makefile | 1 +
> arch/riscv/cpu/cv1800b/cache.c |
Dear Tom
Thank you for your reply soon.
You mean only changed U-boot need to comply with the license?
The proprietary OS no need to disclose(don't care) at this time, even if they
are merged by one image. right?
waiting for your kindly reply.
Regards
Lion
-Original Message-
From: "Tom
On Mon, 11 Mar 2024 at 18:07, Caleb Connolly wrote:
>
> Hi Sumit,
>
> On 11/03/2024 11:10, Sumit Garg wrote:
> > Add support for driving the GPIO pins as output low or high.
>
> Ohh, this is why it was never working for me >,<
Yeah you only implemented it for PMIC GPIOs.
> >
> > Signed-off-by:
Add a test for reset commands which performs resetting of CPU, It does
COLD reset by default and WARM reset with -w option.
Signed-off-by: Love Kumar
---
Changes in v2:
- Set bootmode through boardenv if modeboot is not defined
Changes in v3:
- Fix the issue with bad pattern found on console
Hi Peter,
On Tue, 12 Mar 2024 at 15:13, Peter Robinson wrote:
>
> Hi Sumit,
>
> > pcie_imx doesn't seem to share any useful code for iMX8MP SoC and it is
> > rather tied to quite old port of pcie_designware driver from Linux which
> > suffices only iMX6 specific needs.
> >
> > But currently we
On Tue, Mar 12, 2024 at 04:52:29PM +0800, Yang Xiwen wrote:
> On 3/11/2024 5:34 PM, Maxime Ripard wrote:
> > On Thu, Mar 07, 2024 at 07:18:05PM +0800, Yang Xiwen wrote:
> > > On 3/7/2024 4:48 PM, Maxime Ripard wrote:
> > > > Hi,
> > > >
> > > > On Thu, Mar 07, 2024 at 10:03:50AM +0800, Yang Xiwen
ase-commit: f3c979dd0053c082d2df170446923e7ce5edbc2d
change-id: 20240312-pcl-070-fix-b7bd8bd74d5b
Best regards,
--
Benjamin Hahn
Hi Sumit,
> pcie_imx doesn't seem to share any useful code for iMX8MP SoC and it is
> rather tied to quite old port of pcie_designware driver from Linux which
> suffices only iMX6 specific needs.
>
> But currently we have the common DWC specific bits which alligns pretty
> well with DW PCIe
On jeu., mars 07, 2024 at 16:54, Sam Protsenko
wrote:
> On Thu, Mar 7, 2024 at 4:11 PM Colin McAllister
> wrote:
>>
>> Found a missing semicolon in code protected by a #if that will never
>> evaluate to true due to a separate issue. Fixing this issue before
>> addressing the #if.
>>
>>
On Tue, 12 Mar 2024 at 03:03, Volodymyr Babchuk
wrote:
>
> Now sub-drivers for particular SoCs can register them as power domain
> drivers. This is needed for upcoming SM8150 support, because it needs
> to power up the Ethernet module.
>
> Signed-off-by: Volodymyr Babchuk
>
> ---
> Caleb
Add test case for saveenv command in non-JTAG bootmode which saves the
u-boot environment variables in persistent storage.
Signed-off-by: Love Kumar
---
Changes in v2:
- Set bootmode through boardenv if modeboot is not defined
Changes in v3:
- Fix the issue with bad patterns and escape
On 3/11/2024 5:34 PM, Maxime Ripard wrote:
On Thu, Mar 07, 2024 at 07:18:05PM +0800, Yang Xiwen wrote:
On 3/7/2024 4:48 PM, Maxime Ripard wrote:
Hi,
On Thu, Mar 07, 2024 at 10:03:50AM +0800, Yang Xiwen via B4 Relay wrote:
From: Yang Xiwen
Originally, the initial clock rate is hardcoded to
Hi Tom,
The following changes since commit f3c979dd0053c082d2df170446923e7ce5edbc2d:
Prepare v2024.04-rc4 (2024-03-11 13:11:46 -0400)
are available in the Git repository at:
https://source.denx.de/u-boot/custodians/u-boot-riscv.git
for you to fetch changes up to
This series adds RAUC boot logic for the phycore_imx8mp.
The first patch converts the environment from a CFG_EXTRA_ENV_SETTINGS #define
to a text environment for better readability and maintainability.
The second patch moves the default bootcmd from the defconfig to the board
environment.
The
On Sun, Mar 10, 2024 at 01:51:57AM +0800, Kongyang Liu wrote:
> Add configs related to sdhci and mmc for Sophgo Milk-V Duo board
>
> Signed-off-by: Kongyang Liu
> ---
>
> (no changes since v1)
>
> configs/milkv_duo_defconfig | 10 ++
> 1 file changed, 10 insertions(+)
Reviewed-by:
> On 06.03.24 11:00, Bo Gan wrote:
>
> Previously PLL node was missing from SPL dts. This caused BUS_ROOT to stay on
> OSC clock (24Mhz). As a result, all peripherals have to run at a much lower
> frequency, and loading from sdcard/emmc is slow.
> Thus, enabling PLL node in dts to fix this.
>
>
On 3/11/24 20:32, Francesco Dolcini wrote:
> Hello Patrice,
>
> On Mon, Mar 11, 2024 at 03:39:17PM +0100, Patrice Chotard wrote:
>> In case lmb_add_region_flags() is called with the same parameter than
>> an already existing lmb and this lmb is adjacent to its previous lmb with
>> different
On 3/9/24 03:11, Marek Vasut wrote:
> The current glue code is specific to STM32MP15xx, the upcoming STM32MP13xx
> will introduce another entry specific to the STM32MP13xx. Rename the current
> entry to eqos_stm32mp15_config in preparation for STM32MP13xx addition. No
> functional change.
>
>
On 3/9/24 03:11, Marek Vasut wrote:
> Move board_interface_eth_init() into eqos_probe_syscfg_stm32() in STM32
> driver glue code. The eqos_probe_syscfg_stm32() parses STM32 specific DT
> properties of this MAC and configures SYSCFG registers accordingly, there
> is nothing board specific
On 3/9/24 03:11, Marek Vasut wrote:
> Replace ifdef CONFIG_CLK with if (CONFIG_IS_ENABLED(CLK)) to improve code
> build coverage. Some of the functions printed debug("%s: OK\n", __func__);
> on exit with and without CLK enabled, some did not, make it consistent and
> print nothing if CLK is
On 3/9/24 03:11, Marek Vasut wrote:
> Use const bool for the values parsed out of DT. Drop the duplicate
> assignment of false into those bool variables, assign them directly
> with the content parsed out of DT. Abbreviate the variable name too.
>
> Signed-off-by: Marek Vasut
> ---
> Cc:
On 3/9/24 03:11, Marek Vasut wrote:
> From: Christophe Roullier
>
> Manage 2 ethernet instances, select which instance to configure with mask
> If mask is not present in DT, it is stm32mp15 platform.
>
> Signed-off-by: Christophe Roullier
> Signed-off-by: Marek Vasut # Rework the code
>
On 3/11/24 16:36, Kumar, Udit wrote:
>
> On 3/11/2024 8:09 PM, Patrice Chotard wrote:
>> In case lmb_add_region_flags() is called with the same parameter than
>> an already existing lmb and this lmb is adjacent to its previous lmb with
>> different flag, this lmb is added again.
>
>
> Same
On 3/9/24 03:11, Marek Vasut wrote:
> Use dev_*() only to print all the logs from this glue code,
> instead of mixing dev_*(), log_*(), pr_*() all in one code.
>
> Signed-off-by: Marek Vasut
> ---
> Cc: Christophe Roullier
> Cc: Joe Hershberger
> Cc: Patrice Chotard
> Cc: Patrick Delaunay
Enable saving variables to MMC(FAT) and SPI based on primary
bootmode. If bootmode is JTAG, dont save env anywhere(NOWHERE).
Enable ENV_FAT_DEVICE_AND_PART="0:auto" for versal-net platform as well.
Signed-off-by: Venkatesh Yadav Abbarapu
---
board/xilinx/versal-net/board.c | 30
On 3/9/24 03:11, Marek Vasut wrote:
> Move STM32 glue code into separate file to contain the STM32 specific
> code outside of the DWMAC core code. No functional change.
>
> Signed-off-by: Marek Vasut
> ---
> Cc: Christophe Roullier
> Cc: Joe Hershberger
> Cc: Patrice Chotard
> Cc: Patrick
On 05.03.24 16:47, Ilias Apalodimas wrote:
On Fri, Feb 23, 2024 at 05:18:42PM +0100, Michal Simek wrote:
There is no reason to describe u-boot.itb on system without SPL. Pretty
much this is cover all systems which are using only boot.bin which contains
all images inside.
Signed-off-by: Michal
On 3/9/24 03:11, Marek Vasut wrote:
> Use FIELD_PREP to configure content of ETH_SEL bitfield in SYSCFG_PMCSETR
> register. No functional change.
>
> Signed-off-by: Marek Vasut
> ---
> Cc: Christophe Roullier
> Cc: Joe Hershberger
> Cc: Patrice Chotard
> Cc: Patrick Delaunay
> Cc: Ramon
On 3/9/24 03:11, Marek Vasut wrote:
> Move the log_debug() calls on top of the bit manipulation code.
> No functional change.
>
> Signed-off-by: Marek Vasut
> ---
> Cc: Christophe Roullier
> Cc: Joe Hershberger
> Cc: Patrice Chotard
> Cc: Patrick Delaunay
> Cc: Ramon Fried
> Cc:
On Tue, Mar 12, 2024 at 05:59:44PM +0800, Leo Liang wrote:
> On Sun, Mar 10, 2024 at 01:56:45PM +0800, Kongyang Liu wrote:
> > Add ethernet node for cv1800b SoC
> >
> > Signed-off-by: Kongyang Liu
> > ---
> >
> > arch/riscv/dts/cv18xx.dtsi | 6 ++
> > 1 file changed, 6 insertions(+)
>
>
On 3/9/24 03:11, Marek Vasut wrote:
> From: Christophe Roullier
>
> Add compatible "st,stm32mp13-dwmac" to manage STM32MP13 boards.
>
> Signed-off-by: Christophe Roullier
> Signed-off-by: Marek Vasut # Rebase, reshuffle, squash code
> ---
> Cc: Christophe Roullier
> Cc: Joe Hershberger
>
This patch is to enable Agilex5 platform for Intel
product. Changes, modification and new files are
created for board, dts, configs and makefile to
create the base for Agilex5.
Signed-off-by: Jit Loon Lim
---
Changes v3 -> v4:
- Update defined to is_enabled
Changes v2 -> v3:
- Added FPGA 240G
V1:
https://patchwork.ozlabs.org/project/uboot/patch/20240220143603.22091-1-jit.loon@intel.com/
V2: Fixed Git auto-merge causing misalignment of code and insert/delete
V3: Added 240G FPGA DDR region
V4: Update defined to is_enabled
Jit Loon Lim (1):
arch: arm: Agilex5 enablement
On 3/9/24 03:11, Marek Vasut wrote:
> From: Patrick Delaunay
>
> Request the clk-ck earlier in probe in preparation for obtaining
> the clock rate from these clk-ck in eqos_probe_syscfg_stm32() in
> the follow up patch.
>
> Signed-off-by: Patrick Delaunay
> ---
> Cc: Christophe Roullier
>
Hi Mattijs,
I’ve been using git send-email, but there might be issues with what the Garmin
smtp server is doing to the email, like adding the footer. I sent a v4 PS in a
new thread using my personal email, but that email isn’t subscribed to this ML
so I think the patches are pending approval
commit 3d74a0977f514 ("ti: am335x: Remove unused linker script") removed
the linker script for the TI variant. This linker script doesn't seem to
do anything special and on top of that, has no definitions for the EFI
runtime sections.
So let's get rid of it and use the generic linker script which
The arm linker scripts had a mix of symbols and C defined variables in an
effort to emit relative references instead of absolute ones e.g [0]. A
linker bug prevented us from doing so [1] -- fixed since 2016.
This has led to confusion over the years, ending up with mixed section
definitions. Some
commit 3ebd1cbc49f0 ("arm: make __bss_start and __bss_end__ compiler-generated")
and
commit f84a7b8f54db ("ARM: Fix __bss_start and __bss_end in linker scripts")
were moving the bss_start/end on c generated variables that were
injected in their own sections. The reason was that we needed relative
This series adds RAUC boot logic for the phycore_imx8mp.
The first patch converts the environment from a CFG_EXTRA_ENV_SETTINGS #define
to a text environment for better readability and maintainability.
The second patch moves the default bootcmd from the defconfig to the board
environment.
The
Move the environment into the board directory and convert it from a C
header to a text file. Sort the variables alphabetically.
No functional changes.
Signed-off-by: Leonard Anderweit
Reviewed-by: Teresa Remmet
Tested-by: Teresa Remmet
---
.../phytec/phycore_imx8mp/phycore_imx8mp.env | 45
Move the default bootcmd from the defconfig to the board environment.
No change in functionality.
Signed-off-by: Leonard Anderweit
Tested-by: Teresa Remmet
---
board/phytec/phycore_imx8mp/phycore_imx8mp.env | 12
configs/phycore-imx8mp_defconfig | 2 --
2 files
Add support for the redundant environment.
Signed-off-by: Leonard Anderweit
Tested-by: Teresa Remmet
---
configs/phycore-imx8mp_defconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/configs/phycore-imx8mp_defconfig b/configs/phycore-imx8mp_defconfig
index fd492eba3c10..6c67f14b5559
Add RAUC boot logic to the environment. This is the first board to
utilize this environment.
Signed-off-by: Leonard Anderweit
Tested-by: Teresa Remmet
---
board/phytec/phycore_imx8mp/phycore_imx8mp.env | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git
On 3/5/24 12:02, Venkatesh Yadav Abbarapu wrote:
USB4 has been added to the boot targets and
also add support to enable JTAG.
Signed-off-by: Shubhangi Shrikrushna Mahalle
Signed-off-by: Venkatesh Yadav Abbarapu
---
board/xilinx/zynqmp/zynqmp_kria.env | 3 ++-
1 file changed, 2
Hi Colin,
On mar., mars 12, 2024 at 14:04, "McAllister, Colin"
wrote:
> Hi Mattijs,
>
> I’ve been using git send-email, but there might be issues with what the
> Garmin smtp server is doing to the email, like adding the footer. I sent a v4
> PS in a new thread using my personal email, but
mach Kconfig file select some options independently of if SPL is actually
enabled. It ends up in situation that SPL is disabled but symbols are still
present in .config. That's why add SPL dependency for them but also group
them with other SPL options in ARCH_ZYNQMP fragment with using imply
Am Dienstag, dem 12.03.2024 um 09:59 +0100 schrieb Leonard Anderweit:
> Add RAUC boot logic to the environment. This is the first board to
> utilize this environment.
>
> Signed-off-by: Leonard Anderweit
Tested-by: Teresa Remmet
> ---
> board/phytec/phycore_imx8mp/phycore_imx8mp.env | 7
Am Dienstag, dem 12.03.2024 um 09:59 +0100 schrieb Leonard Anderweit:
> Add logic for booting systems with the RAUC update mechanism. This
> can
> be reused by other phytec boards.
>
> Signed-off-by: Leonard Anderweit
Tested-by: Teresa Remmet
> ---
> include/env/phytec/rauc.env | 52
>
Add logic for booting systems with the RAUC update mechanism. This can
be reused by other phytec boards.
Signed-off-by: Leonard Anderweit
Tested-by: Teresa Remmet
---
include/env/phytec/rauc.env | 52 +
1 file changed, 52 insertions(+)
create mode 100644
On 3/6/24 04:27, Venkatesh Yadav Abbarapu wrote:
Currently only hw ecc is supported in U-Boot. If any other ecc mode is
given in DT, it simply through an error. So better print
what is being done.
Revert this patch once soft ecc support is fixed in future.
Signed-off-by: Ashok Reddy Soma
On 3/8/24 09:41, Michal Simek wrote:
Describe usb wakeup interrupt.
Signed-off-by: Michal Simek
---
arch/arm/dts/zynqmp.dtsi | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi
index
On 3/8/24 09:41, Michal Simek wrote:
Based on dt schema there is no need to specify flash via additional
compatible string and generic are enough.
Signed-off-by: Michal Simek
---
arch/arm/dts/zynqmp-sc-revB.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
Hi Colin,
Thank you for the patch.
On mar., mars 12, 2024 at 07:57, Colin McAllister wrote:
Sam also gave his review here:
https://lore.kernel.org/all/CAPLW+4kHmPtfACyND4Vc2p0ZrsyGY=+bRU=fdub4k1ux5p3...@mail.gmail.com/
Please include his review tag in the next submission.
I will add it at
Previous patches cleaning up linker symbols, also merged any explicit
. = ALIGN(x); into section definitions -- e.g '.bss ALIGN(x) :' instead
of '. - ALIGN(x); bss : {...}'
However, if the output address is not specified then one will be chosen
for the section. This address will be adjusted to
image_copy_start/end are defined as c variables in order to force the compiler
emit relative references. However, defining those within a section definition
will do the same thing since [0].
So let's remove the special sections from the linker scripts, the
variable definitions from sections.c and
Hello Leonard,
Am Dienstag, dem 12.03.2024 um 09:59 +0100 schrieb Leonard Anderweit:
> Move the environment into the board directory and convert it from a C
> header to a text file. Sort the variables alphabetically.
> No functional changes.
>
> Signed-off-by: Leonard Anderweit
> ---
>
Am Dienstag, dem 12.03.2024 um 09:59 +0100 schrieb Leonard Anderweit:
> Add support for the redundant environment.
>
> Signed-off-by: Leonard Anderweit
Tested-by: Teresa Remmet
> ---
> configs/phycore-imx8mp_defconfig | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git
Am Dienstag, dem 12.03.2024 um 09:59 +0100 schrieb Leonard Anderweit:
> Move the default bootcmd from the defconfig to the board environment.
> No change in functionality.
>
> Signed-off-by: Leonard Anderweit
Tested-by: Teresa Remmet
> ---
> board/phytec/phycore_imx8mp/phycore_imx8mp.env |
- Addresses compiler error due to missing semicolon
- Removes use of preprocessor macros with ANDROID_AB_BACKUP_OFFSET
Bug was found by noticing a semicolon was missing and not causing a
compiler error when CONFIG_ANDROID_AB_BACKUP_OFFSET was set. I submitted
a patch to fix the semicolon before
From: Colin McAllister
Currently, setting CONFIG_AB_BACKUP_OFFSET in a target's defconfig will
not actually enable the #if protected code in android_ab.c. This is
because "CONFIG_" should have been prepended to the config macro, or the
macros defined in kconfig.h could have been used.
The code
From: Colin McAllister
Found a missing semicolon in code protected by a #if that will never
evaluate to true due to a separate issue. Fixing this issue before
addressing the #if.
Fixes: 3430f24bc6 ("android_ab: Try backup booloader_message")
Signed-off-by: Colin McAllister
Cc: Joshua Watt
Cc:
Hello Sughosh,
We are planning to use these changes in the Corstone-1000 platform.
Do you have a timeline when these are going to get merged?
Thanks,
Bence
On Tue, Nov 21, 2023 at 12:30:24PM +0530, Sughosh Ganu wrote:
>
> Add support for generating capsules through a config file. Multiple
>
On 3/7/24 16:29, lukas.funke-...@weidmueller.com wrote:
From: Lukas Funke
ZynqMP CG series devices only have two cpus. In this
case the interrupt-affinity property has to adapted, because
cpu3 and cpu4 are missing. By adding a label to the pmu fwnode the
interrupt-affinity can be adapted in
On 3/12/24 07:14, Ilias Apalodimas wrote:
Hi Michal
Apologies for the late reply
On Wed, 6 Mar 2024 at 09:48, Michal Simek wrote:
On 3/5/24 16:47, Ilias Apalodimas wrote:
On Fri, Feb 23, 2024 at 05:18:42PM +0100, Michal Simek wrote:
There is no reason to describe u-boot.itb on system
__efi_runtime_rel_start/end are defined as c variables for arm7 only in
order to force the compiler emit relative references. However, defining
those within a section definition will do the same thing since [0].
On top of that the v8 linker scripts define it as a symbol.
So let's remove the
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