Dear Kumar Gala,
In message 1249352037-25832-2-git-send-email-ga...@kernel.crashing.org you
wrote:
Every platform that calls fsl_pci_init calls fsl_pci_setup_inbound_windows
before it calls fsl_pci_init. There isn't any reason to just call it
from fsl_pci_init and simplify things a bit.
...
STx AMC8548 board is an old, AMC form factor, MPC8548 based board intended
for RapidIO applications. It features 16MiB NAND flash, one DDR2 soDIMM
slot, ethernet on front panel and backplane, RapidIO on backplane, USB
controller on local bus (not currently enabled) and no PCI of any kind.
From: Alex Dubov oa...@yahoo.com
STx AMC8548 board is an old, AMC form factor, MPC8548 based board intended
for RapidIO applications. It features 16MiB NAND flash, one DDR2 soDIMM
slot, ethernet on front panel and backplane, RapidIO on backplane, USB
controller on local bus (not currently
Hi, All!
And one more question - how can I outpup some text to the LCD?
I wanna redirect printf/puts functions from Com1 to LCD. Maybe there is some
example I can look at?
--
Software Developer
General Satellite Corp.
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Dear oa...@yahoo.com,
In message 1249383697-28141-2-git-send-email-oa...@yahoo.com you wrote:
From: Alex Dubov oa...@yahoo.com
STx AMC8548 board is an old, AMC form factor, MPC8548 based board intended
for RapidIO applications. It features 16MiB NAND flash, one DDR2 soDIMM
slot, ethernet on
Dear Tuma,
In message 200908041619.12488.chernigovs...@spb.gs.ru you wrote:
And one more question - how can I outpup some text to the LCD?
I *really* recommend to RTFM.
I wanna redirect printf/puts functions from Com1 to LCD. Maybe there is some
example I can look at?
= setenv stdout lcd
Hi;
I am trying to bring up u-boot-2009-08-rc1 on IXP425 board. May
I know what's the reason that the TEXT_BASE is 0x00f8 instead of 0 or
0x5000?
Thanks.
Regards,
KH
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On 08/04/2009 02:59 PM, Teh Kok How wrote:
Hi;
I am trying to bring up u-boot-2009-08-rc1 on IXP425 board. May
I know what's the reason that the TEXT_BASE is 0x00f8 instead of 0 or
0x5000?
Thanks.
Hi Teh,
usually TEXT_BASE is offset, which size depends
On Aug 4, 2009, at 1:09 AM, Wolfgang Denk wrote:
Dear Kumar Gala,
In message 1249352037-25832-2-git-send-email-ga...@kernel.crashing.org
you wrote:
Every platform that calls fsl_pci_init calls
fsl_pci_setup_inbound_windows
before it calls fsl_pci_init. There isn't any reason to just
On Aug 4, 2009, at 1:07 AM, Wolfgang Denk wrote:
Dear Kumar Gala,
In message 1249352037-25832-1-git-send-email-ga...@kernel.crashing.org
you wrote:
Every platform that calls fsl_pci_init calls pci_setup_indirect
before
it calls fsl_pci_init. There isn't any reason to just call it
From: Alex Dubov oa...@yahoo.com
Move board definition files for STx XTC, GP3 and SSA boards into
common subdirectory and factor out common code.
-mno-spe flag common to all MPC85xx configurations does not work
so change it to -mspe=no which does (GCC bug 37759).
Signed-off-by: Alex Dubov
Dear Darius Augulis,
In message 4a78342c.5090...@gmail.com you wrote:
usually TEXT_BASE is offset, which size depends on your requirements for
No. TEXT_BASE is an absolute address.
stack size and memory size for malloc. If your DRAM base is 0x0 and
TEXT_BASE is 0xf8, you will have
I had two ideas on simple ways to convey the value of CCSRBAR, IMMR,
etc.. on various Freescale PPC SoCs. Knowing the value is useful in
debugging if you need to dump the register space. I wanted to see if
people had a preference or other ideas:
1. add it as output when we boot:
U-Boot
Hi
Thanks for reply.
I changed ECCM bit and it fixed NAND boot... read failed (ltesr)
problem.
However, now it again stuck after printing transferring control.
It lookes like it is able to copy u-boot image to RAM but not able to run
from there.
What could be problem in this ?
Thanks
Rupesh
Dear Kumar Gala,
In message 7acc3970-1b73-4828-941c-48c6601a7...@kernel.crashing.org you wrote:
I had two ideas on simple ways to convey the value of CCSRBAR, IMMR,
etc.. on various Freescale PPC SoCs. Knowing the value is useful in
debugging if you need to dump the register space. I
On Aug 4, 2009, at 9:24 AM, Wolfgang Denk wrote:
Dear Kumar Gala,
In message
7acc3970-1b73-4828-941c-48c6601a7...@kernel.crashing.org you wrote:
I had two ideas on simple ways to convey the value of CCSRBAR, IMMR,
etc.. on various Freescale PPC SoCs. Knowing the value is useful in
On 08/04/2009 04:49 PM, Wolfgang Denk wrote:
Dear Darius Augulis,
In message4a78342c.5090...@gmail.com you wrote:
usually TEXT_BASE is offset, which size depends on your requirements for
No. TEXT_BASE is an absolute address.
yes, but depends on the physical RAM base and size.
stack size
On Tue, 2009-08-04 at 09:27 -0500, Kumar Gala wrote:
On Aug 4, 2009, at 9:24 AM, Wolfgang Denk wrote:
Dear Kumar Gala,
In message
7acc3970-1b73-4828-941c-48c6601a7...@kernel.crashing.org you wrote:
I had two ideas on simple ways to convey the value of CCSRBAR, IMMR,
etc.. on
On Tue, 2009-08-04 at 14:27 +0200, Wolfgang Denk wrote:
Dear oa...@yahoo.com,
In message 1249383697-28141-2-git-send-email-oa...@yahoo.com you wrote:
From: Alex Dubov oa...@yahoo.com
STx AMC8548 board is an old, AMC form factor, MPC8548 based board intended
for RapidIO applications.
On Aug 4, 2009, at 9:43 AM, Peter Tyser wrote:
We'd toyed around with adding a memmap command which would display
chip select mappings, and/or tlb mappings. I think lots of people
(especially end-users) would find this info useful as the same issue
you
have with determining the CCSR
Dear Darius Augulis,
In message 4a784702.40...@gmail.com you wrote:
No. TEXT_BASE is an absolute address.
yes, but depends on the physical RAM base and size.
Only on ARM (and other architectures that copied it's broken
implementation). TEXT_BASE is an absolute address (in the boot flash)
All fair points.
It appears that the 'nand' commands don't use the new parser structure. The
'nand' and 'nboot' commands use the U_BOOT_CMD macro, and have repeatable
defined as 1. The 'nand' command is doing it's own sub-command parsing (via
strcnmp()'s), and as a result, all 'nand' commands
From: Alex Dubov oa...@yahoo.com
Put environment into .ppcenv section aligned on a smaller boot eraseblock
boundary near flash end.
Signed-off-by: Alex Dubov oa...@yahoo.com
---
board/stx/stxamc8548/u-boot.lds | 11 ++-
include/configs/stxamc8548.h|3 ++-
2 files changed, 12
I just noticed that we have MAX_PCI_REGIONS set to 7. On FSL 85xx/
86xx parts we can have as many as 9 windows. Should I just bump the #
of regions to 9 for everyone or #ifdef based on CONFIG_85xx/CONFIG_86xx?
- k
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On Tue, Aug 04, 2009 at 12:07:17PM -0400, J.C. Wren wrote:
All fair points.
It appears that the 'nand' commands don't use the new parser structure.
Do you mean U_BOOT_CMD_MKENT, find_cmd_tbl, etc?
The 'nand' and 'nboot' commands use the U_BOOT_CMD macro, and have
repeatable defined as 1.
On 19:55 Mon 03 Aug , Darius Augulis wrote:
On 07/08/2009 01:29 AM, Jean-Christophe PLAGNIOL-VILLARD wrote:
On 22:03 Tue 30 Jun , Darius Augulis wrote:
This board is based on Cortina Systems networking processor
CS3516. It has FA526 core, which is ARMv4 compatible.
Many SoC
On 09:54 Mon 03 Aug , Albin Tonnerre wrote:
On Sat, Aug 01, 2009 at 04:15:32PM +0200, Jean-Christophe PLAGNIOL-VILLARD
wrote :
On 10:32 Fri 24 Jul , Albin Tonnerre wrote:
The Calao TNY-A9260 and TNY-9G20 are boards manufactured and sold by Calao
Systems
On Tue, Aug 4, 2009 at 3:48 PM, Scott Wood scottw...@freescale.com wrote:
On Tue, Aug 04, 2009 at 12:07:17PM -0400, J.C. Wren wrote:
All fair points.
It appears that the 'nand' commands don't use the new parser structure.
Do you mean U_BOOT_CMD_MKENT, find_cmd_tbl, etc?
Not sure about
On 08/04/2009 10:48 PM, Jean-Christophe PLAGNIOL-VILLARD wrote:
On 09:42 Mon 03 Aug , Darius Augulis wrote:
On 07/08/2009 02:30 PM, Jean-Christophe PLAGNIOL-VILLARD wrote:
On 15:14 Fri 03 Jul , Po-Yu Chuang wrote:
This patch adds support for A320 development board from Faraday. This
On 08/04/2009 10:41 PM, Jean-Christophe PLAGNIOL-VILLARD wrote:
On 19:55 Mon 03 Aug , Darius Augulis wrote:
On 07/08/2009 01:29 AM, Jean-Christophe PLAGNIOL-VILLARD wrote:
On 22:03 Tue 30 Jun , Darius Augulis wrote:
This board is based on Cortina Systems networking processor
CS3516.
Dear Jean-Christophe PLAGNIOL-VILLARD,
In message 20090804194155.ga4...@game.jcrosoft.org you wrote:
...
+
+ldr r3, =GEMINI_GLOBAL_ID /* Global ID reg */
+ldr r4, [r3]
+ldr r5, =0xFF /* Chip revision mask */
+
Dear J.C. Wren,
In message 17434f2e0908041305i629aef0dmbf23e620a61fe...@mail.gmail.com you
wrote:
Not sure about that part. I just went back and looked at cmd_i2c.c,
cmd_yaffs2.c and a few others and I see they all do sub-command processing
with strncmp(), too. I had looked at one other
Hi all,
I see that miiphybb.c driver is used only with PPC architecture yet.
I would like to use it with ARM. Would be it reasonable to make this
driver arch independent? I have small patch and it changes defined ports
and pins with function calls, which should be provided by each CPU. I
Hi,
I have a similar p30 intel 64M flash.When I try to initialize both banks at
0x2000 and 0x2200, u-boot crashes while initializing second bank at
0x2200, i debugged and found out that u-boot couldn't sucessfully write
to second bank. But when i plug in the debugger to my board i
Dear oa...@yahoo.com,
In message 1249383697-28141-1-git-send-email-oa...@yahoo.com you wrote:
From: Alex Dubov oa...@yahoo.com
Move board definition files for STx XTC, GP3 and SSA boards into
common subdirectory and factor out common code.
-mno-spe flag common to all MPC85xx
Dear Darius Augulis,
In message 4a789d2f.1050...@gmail.com you wrote:
I see that miiphybb.c driver is used only with PPC architecture yet.
I would like to use it with ARM. Would be it reasonable to make this
driver arch independent? I have small patch and it changes defined ports
and pins
Dear oa...@yahoo.com,
In message 1249383697-28141-3-git-send-email-oa...@yahoo.com you wrote:
Put environment into .ppcenv section aligned on a smaller boot eraseblock
boundary near flash end.
Hm... if you change to code to using a smaller boot sector...
#define CONFIG_ENV_ADDR
Also fix some minor whitespace oddities while we're cleaning up
Signed-off-by: Peter Tyser pty...@xes-inc.com
---
board/xes/common/fsl_8xxx_clk.c |6 ++--
board/xes/common/fsl_8xxx_pci.c | 46 +-
board/xes/xpedite5200/xpedite5200.c | 17
On Sun, 2009-07-19 at 15:14 -0500, Peter Tyser wrote:
On Wed, 2009-02-04 at 15:14 -0600, Peter Tyser wrote:
Previously, waiting for auto-negotiation would only occur if a valid
link had been detected. Problems arose when attempting to use a
tsec immediately after bootup but before link was
On Fri, 2009-07-24 at 13:18 -0500, Peter Tyser wrote:
Previously, when CONFIG_MP was defined Boot Page Translation was
unconditionally enabled and secondary cores were put in a spin loop at
address 0xf000. The 0xfxxx address range (ie the Boot Page) was
being remapped to SDRAM via the
On Mon, Aug 03, 2009 at 05:45:14AM +0400, Ilya Yanok wrote:
+ if (this-options NAND_BUSWIDTH_16) {
+ void __iomem *main_buf = host-regs-main_area0;
+ /* compress the ID info */
+ writeb(readb(main_buf + 2), main_buf + 1);
+
Put environment into .ppcenv section aligned on a
smaller boot eraseblock
boundary near flash end.
Hm... if you change to code to using a smaller boot
sector...
#define CONFIG_ENV_ADDR
(CONFIG_SYS_MONITOR_BASE + 0x38000)
#define
CONFIG_ENV_SECT_SIZE 0x4000 /*
On Aug 4, 2009, at 6:01 AM, oa...@yahoo.com wrote:
From: Alex Dubov oa...@yahoo.com
Move board definition files for STx XTC, GP3 and SSA boards into
common subdirectory and factor out common code.
-mno-spe flag common to all MPC85xx configurations does not work
so change it to -mspe=no
Move board definition files for STx XTC, GP3 and SSA
boards into
common subdirectory and factor out common code.
-mno-spe flag common to all MPC85xx configurations
does not work
so change it to -mspe=no which does (GCC bug
37759).
Signed-off-by: Alex Dubov oa...@yahoo.com
Hi;
I understand Wolfgang's argument but setting the TEXT_BASE to this
arbitrary high address (DRAM_end - U-boot_size(_end - _start)) does not make
sense. I am new to ARM arch but in PowerPC and MIPS, the TEXT_BASE is always
set to the reset vector and in ARM, the reset vector is at 0 or
Just a general observation: if you are not sure that tlb/law files can be
safely factored out and most of the ddr.c files are actually board specific
overrides (common part being less than 10 lines) why had you requested me
to create a common board hierarchy for these STX boards in the first
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