-Original Message-
+/* Check USB PHY clock valid */
+static int usb_phy_clk_valid(struct usb_ehci *ehci) {
+ if ((!(in_be32(ehci-control) PHY_CLK_VALID))
+ (!in_be32(ehci-prictrl))) {
(!A !B) condition can certainly be done without the double negation
Dear Liu Shengzhou-B36685,
-Original Message-
+/* Check USB PHY clock valid */
+static int usb_phy_clk_valid(struct usb_ehci *ehci) {
+ if ((!(in_be32(ehci-control) PHY_CLK_VALID))
+ (!in_be32(ehci-prictrl))) {
(!A !B) condition can certainly be
-Original Message-
From: Marek Vasut [mailto:ma...@denx.de]
Sent: Thursday, October 18, 2012 3:16 PM
To: Liu Shengzhou-B36685
Cc: u-boot@lists.denx.de; Stefan Roese; ag...@denx.de
Subject: Re: [PATCH] powerpc/usb: fix bug of CPU hang when missing USB
PHY clock
Dear Liu
Dear Liu Shengzhou-B36685,
-Original Message-
From: Marek Vasut [mailto:ma...@denx.de]
Sent: Thursday, October 18, 2012 3:16 PM
To: Liu Shengzhou-B36685
Cc: u-boot@lists.denx.de; Stefan Roese; ag...@denx.de
Subject: Re: [PATCH] powerpc/usb: fix bug of CPU hang when missing USB
On 18 October 2012 08:43, Simon Glass s...@chromium.org wrote:
Hi Hatim,
On Tue, Oct 16, 2012 at 3:58 AM, Hatim Ali hatim...@samsung.com wrote:
From: Rajeshwari Shinde rajeshwar...@samsung.com
This patch adds pinmux support for SPI channels
Signed-off-by: Rajeshwari Shinde
Hi
I am working on a custom board (VPX Based P2020 board) and trying to port
u-boot-2011.09 (supports P2020 RDB) in it . Our board is similar to P2020RDB
board and the technical specification is shown below ,
-Processor
Freescale QorIQ P2020 processor
Dual PowerPC e500v2 cores at up
Only used here (and uart_base only for SPL).
Signed-off-by: Peter Korsgaard peter.korsga...@barco.com
---
arch/arm/cpu/armv7/am33xx/board.c |6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/arch/arm/cpu/armv7/am33xx/board.c
b/arch/arm/cpu/armv7/am33xx/board.c
index
The am33xx code currently contains a number of details specific to the
ti(-derived) boards in the common code. This series restructures the
arch code to make it possible to add other boards.
This series does not yet any new boards, as the board I'm working on is
using nand flash, and omap_gpmc
So platforms can override it with board_mmc_init() if needed.
Signed-off-by: Peter Korsgaard peter.korsga...@barco.com
---
arch/arm/cpu/armv7/am33xx/board.c |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/cpu/armv7/am33xx/board.c
So they are available for other boards.
Signed-off-by: Peter Korsgaard peter.korsga...@barco.com
---
arch/arm/cpu/armv7/am33xx/Makefile |1 +
arch/arm/cpu/armv7/am33xx/mux.c| 33
arch/arm/include/asm/arch-am33xx/mux.h | 261
The i2c header is specific to ti(-derived) boards, and not generic for all
am335x boards.
Signed-off-by: Peter Korsgaard peter.korsga...@barco.com
---
arch/arm/cpu/armv7/am33xx/board.c | 242
arch/arm/include/asm/arch-am33xx/sys_proto.h | 27 ---
So other parts can be added.
Signed-off-by: Peter Korsgaard peter.korsga...@barco.com
---
arch/arm/include/asm/arch-am33xx/ddr_defs.h | 64 +++
board/ti/am335x/board.c | 112 +++
2 files changed, 94 insertions(+), 82 deletions(-)
diff
Move the hardcoded ddr2/ddr3 settings for the ti boards to board code,
so other boards can use different types/timings.
Signed-off-by: Peter Korsgaard peter.korsga...@barco.com
---
arch/arm/cpu/armv7/am33xx/emif4.c | 114 +++
Hi,
On Wed, Oct 17, 2012 at 6:47 PM, Dennis Lan (dlan)
dennis.y...@gmail.com wrote:
HI ALL:
Is it just conventional to access IO register with wriltel, readl?
or is there any specific reason here.
what's the difference with direct access? writel has few arch releated
operation to
Hi
I get some misterious errors from time to time when decompressing an LZO
compressed image. The output is as follows
zmx25 bootm 0x8200
## Booting kernel from Legacy Image at 8200 ...
Image Name: zmx25-gfx ifs
Image Type: ARM QNX Kernel Image (lzo compressed)
Data Size:
Hi Jason,
On Wed, Oct 17, 2012 at 11:29 PM, Liu Hui-R64343 r64...@freescale.com wrote:
Why we need enable CONFIG_MMC_BOUNCE_BUFFER?
I learned the following from Marek:
you can't flush cache over unaligned addresses
so .. to make DMA work, we use the bounce buffer
so the address is cache
Hello,
I am trying to configure u-boot-2012.07 for the Colibri PXA270 board
from Toradex. I have configured it using the config file shipped within
u-boot, compiled it and got it running. My problem is that it takes
about 3 seconds till the first output on the serial port. I have tried
to
Hi Stefano,
I'd like to present an overview of my idea (pseudo code):
struct battery {
int (* battery_charge) ()
struct pmic *fg, *muic, *chrg
}
struct chrg {
int (*chrg_type) ()
int (*chrg_bat_present) ()
int (*chrg_state) ()
}
struct fg {
int
From: Vaibhav Hiremath hvaib...@ti.com
In order to support low power state, you must source kernel system
timers to persistent clock, available across suspend/resume. In case of
AM335x device, the only source we have is, RTC32K, available in
wakeup/always-on domain. Having said that, during
On Tue, Oct 16, 2012 at 03:50:08PM -0600, Stephen Warren wrote:
From: Stephen Warren swar...@nvidia.com
If the SPL extends beyond CONFIG_SYS_TEXT_BASE, then it will likely
corrupt the main U-Boot binary during execution, causing the main U-Boot
binary to fail. Check for this situation
On Wed, Oct 17, 2012 at 09:20:31PM -0600, Stephen Warren wrote:
On 10/17/2012 06:05 PM, Simon Glass wrote:
Hi Stephen.
On Tue, Oct 16, 2012 at 3:43 PM, Stephen Warren swar...@wwwdotorg.org
wrote:
On 10/16/2012 04:09 PM, Lucas Stach wrote:
Am Dienstag, den 16.10.2012, 15:50 -0600
On Thu, Oct 18, 2012 at 10:54:54AM +0800, Jason Jin wrote:
Resend the patches as they are not found in patchwork.
Two patches together with:
Marek Vasut (5):
m68k: Fix wrong assembler instruction in start.S
m68k: Fix unused variable warning
m68k: Fix unused variable warning in
On Tue, Oct 16, 2012 at 07:28:16PM -0500, Kim Phillips wrote:
This 32-patch series only begins to address making u-boot source more
'sparseable,' or sparse-clean, ultimately to catch type, address space,
and endianness mismatches and generally improve code quality. E.g., in this
initial dose
On Tue, Oct 16, 2012 at 07:28:24PM -0500, Kim Phillips wrote:
traps.c:*:1: warning: symbol 'print_backtrace' was not declared. Should it be
static?
traps.c:66:6: warning: symbol 'show_regs' was not declared. Should it be
static?
traps.c:93:1: warning: symbol '_exception' was not declared.
On Thu, Oct 18, 2012 at 01:21:09PM +0200, Peter Korsgaard wrote:
The i2c header is specific to ti(-derived) boards, and not generic for all
am335x boards.
Signed-off-by: Peter Korsgaard peter.korsga...@barco.com
[snip]
-/*
- * early system init of muxing and clocks.
- */
-void
On Thu, Oct 18, 2012 at 02:24:20PM +0200, Matthias Wei?er wrote:
Hi
I get some misterious errors from time to time when decompressing an
LZO compressed image. The output is as follows
zmx25 bootm 0x8200
## Booting kernel from Legacy Image at 8200 ...
Image Name: zmx25-gfx
Hello,
i want to use the crypto functions from polarssl in uboot.
My crypto lib choice is polarssl [http://polarssl.org/] and my target is
an omap4 panda board.
My first attempt was to extract the needed source files and headers from
polarssl and copy them to uboot directories and modify the
On Wed, Oct 17, 2012 at 08:19:23PM -0400, Jerry Van Baren wrote:
Hi David, Jon,
Kim Phillips created a series of patches to change variable declarations
that are big endian to be __be32/__be64. Since the device tree is
defined to be big endian, he created a patch to mark the appropriate
On Thu, Oct 18, 2012 at 10:21:32AM -0700, Tom Rini wrote:
On Thu, Oct 18, 2012 at 02:24:20PM +0200, Matthias Wei?er wrote:
Hi
I get some misterious errors from time to time when decompressing an
LZO compressed image. The output is as follows
zmx25 bootm 0x8200
## Booting
On Thu, Oct 18, 2012 at 01:50:18PM +0200, Peter Czypek wrote:
Hello,
i want to use the crypto functions from polarssl in uboot.
My crypto lib choice is polarssl [http://polarssl.org/] and my target is
an omap4 panda board.
What are you trying to accomplish exactly?
--
Tom
signature.asc
Tom == Tom Rini tr...@ti.com writes:
Hi,
Tom My concern is that a lot of this should be general. But I'm
Tom willing to re-investigate how to do things once you're able to
Tom fully move your platform to mainline.
I agree (as long as there's hooks for special platform stuff), but it is
Hi Jagannadha,
On Sun, 29 Jul 2012 19:56:08 +0530, Jagannadha Sutradharudu Teki
402ja...@gmail.com wrote:
This patch provides a support to use buffered writes on flash
for versatile and vexpress boards.
This will certainly increase the flash writes.
Signed-off-by: Jagannadha Sutradharudu
On 10/8/2012 6:19 AM, Stefano Babic wrote:
On 04/10/2012 03:47, Troy Kisky wrote:
Both set_imx_hdr_v1 and set_imx_hdr_v2 perform the
same check. Move check to before the set_imx_hdr call.
Signed-off-by: Troy Kisky troy.ki...@boundarydevices.com
---
v3: split into its own patch
---
Hi esw,
(resending as it was erroneously posted on gmane; sorry for any dupes)
On Thu, 4 Oct 2012 10:28:48 +0200, esw e...@bus-elektronik.de wrote:
Dear Lukasz,
Hi Jens and Helmut,
On Thu, Aug 23, 2012 at 10:13:13PM -, Lukasz Majewski wrote:
The restoration of GPT table (both
Current MUSB driver in U-Boot uses old UDC API while new gagdet
client drivers need new gadget API. Also current MUSB driver has
some significant limitations (like inability to handle tx for
endpoints other than ep0). So I think port of new Linux driver is
desirable.
This is initial port,
Linux usb/ch9.h seems to have all the same information (and more)
as usbdescriptors.h so use the former instead of the later one.
As a consequense of this change USB_SPEED_* values don't correspond
directly to EHCI speed encoding anymore, I've added necessary
recoding in EHCI driver. Also there
Signed-off-by: Ilya Yanok ya...@cogentembedded.com
Signed-off-by: Ilya Yanok ilya.ya...@cogentembedded.com
---
drivers/usb/gadget/config.c |1 -
drivers/usb/gadget/epautoconf.c |1 -
drivers/usb/gadget/ether.c |1 -
drivers/usb/gadget/s3c_udc_otg.c |1 -
Backend driver for MUSB OTG controllers found on TI AM33xx and
TI81xx SoCs (tested with AM33xx only).
Signed-off-by: Ilya Yanok ya...@cogentembedded.com
Signed-off-by: Ilya Yanok ilya.ya...@cogentembedded.com
---
Changes in v2:
- rename backend config option to CONFIG_USB_MUSB_DSPS
- we are
AM33xx has support for dual port MUSB OTG controller. This patch
adds initialization for the controller using new MUSB gadget
driver and ether gadget.
Signed-off-by: Ilya Yanok ilya.ya...@cogentembedded.com
---
Changes in v3:
- use clrsetbits_le32 for USB PHY ops
Enable musb gadget in Ethernet mode on port 0 and
musb host on port1.
Signed-off-by: Ilya Yanok ilya.ya...@cogentembedded.com
---
include/configs/am335x_evm.h | 27 +++
1 file changed, 27 insertions(+)
diff --git a/include/configs/am335x_evm.h
Add defines for MUSB IP block on AM35X SoCs.
Signed-off-by: Ilya Yanok ya...@cogentembedded.com
Signed-off-by: Ilya Yanok ilya.ya...@cogentembedded.com
---
arch/arm/include/asm/arch-omap3/am35x_def.h | 27 +++
1 file changed, 27 insertions(+)
diff --git
AM35XX specific functions for integrated USB PHY/MUSB IP.
Signed-off-by: Ilya Yanok ya...@cogentembedded.com
Signed-off-by: Ilya Yanok ilya.ya...@cogentembedded.com
---
arch/arm/cpu/armv7/omap3/Makefile |1 +
arch/arm/cpu/armv7/omap3/am35x_musb.c | 75
Backend driver for MUSB OTG controllers found on TI AM35x.
It seems that on AM35X interrupt status registers can be updated
_before_ core registers. As we don't use true interrupts in U-Boot
and poll interrupt status registers instead this can result in
interrupt handler being called with
Backend driver for MUSB OTG controllers found on TI OMAP2/3/4
(tested only on OMAP3 Beagle).
Signed-off-by: Ilya Yanok ya...@cogentembedded.com
Signed-off-by: Ilya Yanok ilya.ya...@cogentembedded.com
---
arch/arm/include/asm/omap_musb.h|4 +
drivers/usb/musb-new/Makefile |1 +
Add initialization for new MUSB framework.
Signed-off-by: Ilya Yanok ya...@cogentembedded.com
Signed-off-by: Ilya Yanok ilya.ya...@cogentembedded.com
---
board/ti/beagle/beagle.c | 43
include/configs/omap3_beagle.h |2 ++
2 files changed, 45
Use new musb framework instead of the old one on AM3517_EVM.
Signed-off-by: Ilya Yanok ya...@cogentembedded.com
Signed-off-by: Ilya Yanok ilya.ya...@cogentembedded.com
---
board/logicpd/am3517evm/am3517evm.c | 74 +++
include/configs/am3517_evm.h| 37
Enable using of new MUSB framework on Beagle.
NOTE! This is not just a change of backend code: top-level behavior
is also changed, we now use USB device port for USB Ethernet instead
of serial.
Signed-off-by: Ilya Yanok ya...@cogentembedded.com
Signed-off-by: Ilya Yanok
Add support for SEIKO 4.3'' WVGA panel on mx53loco.
By default, the CLAA WVGA panel is selected.
In order to support the SEIKO panel, undef CONFIG_CLAA_WVGA
and define CONFIG_SEIKO_WVGA in mx53loco.h.
Signed-off-by: Fabio Estevam fabio.este...@freescale.com
---
Hi Yann,
On Fri, 5 Oct 2012 14:09:49 +0200, Yann Vernier
yann.vern...@orsoc.se wrote:
Adding macros for more configurable lowlevel_init code.
Also cleanup of some typos.
---
arch/arm/include/asm/arch-ks8695/platform.h | 55 -
arch/arm/include/asm/arch-ks8695/regvalues.h |
On Thu, Oct 18, 2012 at 3:49 PM, Fabio Estevam
fabio.este...@freescale.comwrote:
Add support for SEIKO 4.3'' WVGA panel on mx53loco.
By default, the CLAA WVGA panel is selected.
In order to support the SEIKO panel, undef CONFIG_CLAA_WVGA
and define CONFIG_SEIKO_WVGA in mx53loco.h.
Hi Yann,
On Fri, 5 Oct 2012 14:09:50 +0200, Yann Vernier
yann.vern...@orsoc.se wrote:
Removed board specific MAC reading code from driver.
Should move the reading to the cm4008/cm41xx board code.
---
drivers/net/ks8695eth.c | 38 +-
1 file changed, 9
Hi Yann,
On Fri, 5 Oct 2012 14:09:53 +0200, Yann Vernier
yann.vern...@orsoc.se wrote:
Changed CONFIG_SYS_TEXT_BASE to actual address (required for
board_init_f) and moved it into cm4{008,1xx}.h, along with a warning
that it must match CONFIG_SYS_FLASH_BASE (since lowlevel_init
relocates
Hi Yann,
On Fri, 5 Oct 2012 14:09:54 +0200, Yann Vernier
yann.vern...@orsoc.se wrote:
Allows configuration macros to set SDRAM parameters.
---
arch/arm/cpu/arm920t/ks8695/lowlevel_init.S | 20 +++-
1 file changed, 11 insertions(+), 9 deletions(-)
diff --git
Hi Yann,
On Fri, 5 Oct 2012 14:09:56 +0200, Yann Vernier
yann.vern...@orsoc.se wrote:
A small bug caused code to set up LEDs to instead disable lots
of functionality in the Ethernet switch, including bounds checks.
---
arch/arm/cpu/arm920t/ks8695/lowlevel_init.S |2 +-
1 file changed,
Hi Yann,
On Fri, 5 Oct 2012 14:09:58 +0200, Yann Vernier
yann.vern...@orsoc.se wrote:
Previously code to do this was in the Ethernet driver itself.
Since it is board specific, moved it here, and altered it to
support preset MAC from environment.
---
board/cm4008/cm4008.c | 12
Dear Marek Vasut,
In message 1350470636-7625-1-git-send-email-ma...@denx.de you wrote:
This patch adds essential components for generation of the contents of
the linker section that is used by the linker-generated array. All of
the contents is held in a separate file, u-boot.lst, which is
SX1 does not build properly by itself, is not built
as part of MAKEALL arm or MAKEALL -a arm, and is only
present in Makefile, not boards.cfg. As it also has no
entry in MAINTAINERS, it is orphan and non-functional.
Remove it.
Signed-off-by: Albert ARIBAUD albert.u.b...@aribaud.net
---
Changes in
Hi,
I would like to know if it's really necessary to keep the dummy
functions in arch/arm/lib/eabi_compat.c.
These function should not be happen in our case (that why the body is
empty).
They have been introduced due to problems with some toolchains that was
referencing these functions. But we
Hi Stephen,
On Mon, 15 Oct 2012 23:10:35 -0600, Stephen Warren
swar...@wwwdotorg.org wrote:
The BCM2835 SoC contains (at least) two CPUs; the VideoCore (a/k/a GPU)
and the ARM CPU. The ARM CPU is often thought of as the main CPU.
However, the VideoCore actually controls the initial SoC boot,
Hi Stephen,
On Mon, 15 Oct 2012 23:10:36 -0600, Stephen Warren
swar...@wwwdotorg.org wrote:
The firmware running on the bcm2835 SoC's VideoCore CPU determines how
much of the system RAM is available for use by the ARM CPU. Previously,
U-Boot assumed that only 128MB was available, since this
On 10/18/2012 02:23 PM, Albert ARIBAUD wrote:
Hi Stephen,
On Mon, 15 Oct 2012 23:10:35 -0600, Stephen Warren
swar...@wwwdotorg.org wrote:
The BCM2835 SoC contains (at least) two CPUs; the VideoCore (a/k/a GPU)
and the ARM CPU. The ARM CPU is often thought of as the main CPU.
However, the
Hi Stephen,
On Wed, 17 Oct 2012 21:17:45 -0600, Stephen Warren
swar...@wwwdotorg.org wrote:
On 10/17/2012 05:58 PM, Simon Glass wrote:
Hi Stephen,
On Tue, Oct 16, 2012 at 2:50 PM, Stephen Warren swar...@wwwdotorg.org
wrote:
From: Stephen Warren swar...@nvidia.com
When
On 10/18/2012 10:31 AM, Tom Rini wrote:
On Wed, Oct 17, 2012 at 09:20:31PM -0600, Stephen Warren wrote:
On 10/17/2012 06:05 PM, Simon Glass wrote:
On Tue, Oct 16, 2012 at 3:43 PM, Stephen Warren
swar...@wwwdotorg.org wrote:
On 10/16/2012 04:09 PM, Lucas Stach wrote:
...
To ask the opposite
On 10/18/2012 10:27 AM, Tom Rini wrote:
On Tue, Oct 16, 2012 at 03:50:08PM -0600, Stephen Warren wrote:
From: Stephen Warren swar...@nvidia.com
If the SPL extends beyond CONFIG_SYS_TEXT_BASE, then it will
likely corrupt the main U-Boot binary during execution, causing
the main U-Boot
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
On 10/18/12 13:45, Stephen Warren wrote:
On 10/18/2012 10:27 AM, Tom Rini wrote:
On Tue, Oct 16, 2012 at 03:50:08PM -0600, Stephen Warren wrote:
From: Stephen Warren swar...@nvidia.com
If the SPL extends beyond CONFIG_SYS_TEXT_BASE, then it
Hi Yann,
On Fri, Oct 5, 2012 at 7:09 AM, Yann Vernier yann.vern...@orsoc.se wrote:
Removed board specific MAC reading code from driver.
Should move the reading to the cm4008/cm41xx board code.
---
drivers/net/ks8695eth.c | 38 +-
1 file changed, 9
On 10/18/2012 02:36 PM, Albert ARIBAUD wrote:
Hi Stephen,
On Wed, 17 Oct 2012 21:17:45 -0600, Stephen Warren
swar...@wwwdotorg.org wrote:
On 10/17/2012 05:58 PM, Simon Glass wrote:
Hi Stephen,
On Tue, Oct 16, 2012 at 2:50 PM, Stephen Warren swar...@wwwdotorg.org
wrote:
From: Stephen
On 10/18/2012 02:58 PM, Stephen Warren wrote:
On 10/18/2012 02:36 PM, Albert ARIBAUD wrote:
Hi Stephen,
On Wed, 17 Oct 2012 21:17:45 -0600, Stephen Warren
swar...@wwwdotorg.org wrote:
On 10/17/2012 05:58 PM, Simon Glass wrote:
Hi Stephen,
On Tue, Oct 16, 2012 at 2:50 PM, Stephen Warren
Hi Tom,
On Wed, 17 Oct 2012 13:18:29 -0700, Tom Rini tr...@ti.com wrote:
With ELDK4.2 libserial.o is too large to fit in the area before the
environment. Swap in libinput instead which is a little smaller.
Cc: Michael Schwingen mich...@schwingen.org
Signed-off-by: Tom Rini tr...@ti.com
On 10/18/2012 02:28 PM, Albert ARIBAUD wrote:
Hi Stephen,
On Mon, 15 Oct 2012 23:10:36 -0600, Stephen Warren
swar...@wwwdotorg.org wrote:
The firmware running on the bcm2835 SoC's VideoCore CPU determines how
much of the system RAM is available for use by the ARM CPU. Previously,
U-Boot
On Thu, 18 Oct 2012 23:11:12 +1100
David Gibson da...@gibson.dropbear.id.au wrote:
On Wed, Oct 17, 2012 at 08:19:23PM -0400, Jerry Van Baren wrote:
Hi David, Jon,
Kim Phillips created a series of patches to change variable declarations
that are big endian to be __be32/__be64. Since the
On Mon, Oct 15, 2012 at 10:47:49AM -0600, Stephen Warren wrote:
On 10/15/2012 10:33 AM, Rob Herring wrote:
On 10/11/2012 01:59 PM, Stephen Warren wrote:
From: Stephen Warren swar...@nvidia.com
Implement ls and fsload commands that act like {fat,ext2}{ls,load},
and transparently handle
Hi Gabriel,
On Thu, 18 Oct 2012 22:14:14 +0200, Gabriel Huau
cont...@huau-gabriel.fr wrote:
Hi,
I would like to know if it's really necessary to keep the dummy
functions in arch/arm/lib/eabi_compat.c.
These function should not be happen in our case (that why the body is
empty).
They
On 10/18/2012 06:01 PM, Tom Rini wrote:
On Mon, Oct 15, 2012 at 10:47:49AM -0600, Stephen Warren wrote:
On 10/15/2012 10:33 AM, Rob Herring wrote:
On 10/11/2012 01:59 PM, Stephen Warren wrote:
From: Stephen Warren swar...@nvidia.com
Implement ls and fsload commands that act like
Hi Stephen,
On Thu, 18 Oct 2012 14:34:27 -0600, Stephen Warren
swar...@wwwdotorg.org wrote:
On 10/18/2012 02:23 PM, Albert ARIBAUD wrote:
Hi Stephen,
On Mon, 15 Oct 2012 23:10:35 -0600, Stephen Warren
swar...@wwwdotorg.org wrote:
The BCM2835 SoC contains (at least) two CPUs; the
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
On 10/18/12 16:12, Rob Herring wrote:
On 10/18/2012 06:01 PM, Tom Rini wrote:
On Mon, Oct 15, 2012 at 10:47:49AM -0600, Stephen Warren wrote:
On 10/15/2012 10:33 AM, Rob Herring wrote:
On 10/11/2012 01:59 PM, Stephen Warren wrote:
From: Stephen
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
On 10/17/12 14:39, James Dougherty wrote:
Hi Tom, Hi Stefan,
I am still using this platform. Please don't remove! What do you
need to have it supported?
Well, the original message you were cc'd on went about a month without
reply. If you wish
From: Stephen Warren swar...@nvidia.com
When -ffunction-sections or -fdata-section are used, symbols are placed
into sections such as .data.eserial1_device and .bss.serial_current.
Update the linker script to explicitly include these. Without this
change (at least with my gcc-4.5.3 built using
From: Stephen Warren swar...@nvidia.com
Add an ASSERT() to u-boot.lds to detect an SPL that doesn't fit within
SPL_TEXT_BASE..SPL_MAX_SIZE.
Different .lds files implement this check in two possible ways:
1) An ASSERT() like this
2) Defining a MEMORY region of size SPL_MAX_SIZE, and re-directing
From: Stephen Warren swar...@nvidia.com
For Tegra, the SPL and main U-Boot are concatenated together to form a
single memory image. Hence, the maximum SPL size is the different in
TEXT_BASE for SPL and main U-Boot. Instead of manually calculating
SPL_MAX_SIZE based on those two TEXT_BASE, which
From: Stephen Warren swar...@nvidia.com
Seaboard and Ventana are very similar boards, and so share the seaboard.c
board file. The one difference needed so far is detected at run-time by
calling machine_is_ventana(). This bloats the Ventana build with code
that is never used. Switch to detecting
From: Stephen Warren swar...@nvidia.com
Seaboard has a GPIO that switches an external mux between Tegra's debug
UART and SPI flash. This is initialized from the SPL so that SPL debug
output can be seen. Simplify the code that does this, and don't actually
request the GPIO in the SPL; just program
On Fri, Oct 19, 2012 at 01:02:41AM +0200, Albert ARIBAUD wrote:
Hi Gabriel,
On Thu, 18 Oct 2012 22:14:14 +0200, Gabriel Huau
cont...@huau-gabriel.fr wrote:
Hi,
I would like to know if it's really necessary to keep the dummy
functions in arch/arm/lib/eabi_compat.c.
These
The following commit introduces some build failures for ColdFire
platform.
commit abaef69fbe683197607febeb2cc619490aca2a10
Author: Marek Vasut ma...@denx.de
Date: Thu Sep 13 16:51:38 2012 +0200
Add the missed header files.
Sign-off-by: Alison Wang b18...@freescale.com
---
This series contains a set of improvements for the SATA susbsystem, mostly
targeted at solid-state drivers and improving start-up time.
The patches are tested on various x86 Chromebooks.
Gabe Black (2):
ahci: Make sending the SETFEATURES_XFER command optional
ahci: Make the AHCI code find
From: Hung-Te Lin hun...@chromium.org
Implement write functionality in the scsi layer. A ''scsi write'
command is also added to console for testing.
Signed-off-by: Hung-Te Lin hun...@chromium.org
Signed-off-by: Simon Glass s...@chromium.org
---
common/cmd_scsi.c | 72
From: Vadim Bendebury vben...@chromium.org
With an Intel AHCI controller, the driver does not operate properly
if the requested amount of blocks to read exceeds 255.
It is probably possible to specify 0 as the block count and the driver
will read 256 blocks, but it was decided to limit the
From: Walter Murphy wmur...@google.com
Currently, this driver uses a 28bit interface to AHCI, this
limits the number of blocks addressable to 2^28, or the max
disk size to 512(2^28) or about 137GB. This change allows
supporting drives up to about 2TB.
Testing this is a bit difficult. There is
From: Taylor Hutt th...@chromium.org
The function ahci_set_feature() is only compiled when the manifest
constant 'CONFIG_AHCI_SETFEATURES_XFER' is defined, but it is used
once outside of such a conditional.
This change puts all uses of the function under the same preprocessor
conditional.
It
From: Taylor Hutt th...@chromium.org
Exynos5 automatically performs DMA when the SATA controller executes
commands. This adds the necessary dcache-to-memory flush
invalidation calls to allow the DMA to properly function.
Signed-off-by: Taylor Hutt th...@chromium.org
Signed-off-by: Simon Glass
From: Stefan Reinauer reina...@chromium.org
- print the correct speed
- print all the AHCI capability flags
(information taken from Linux kernel driver)
- clean up some comments
For example, this might show the following string:
AHCI 0001.0300 32 slots 6 ports 6 Gbps 0x3 impl SATA mode
From: Taylor Hutt th...@chromium.org
Update the assignment of various physical memory buffers used by the
SATA controller to explicitly be denoted as physical addresses.
The memory is identity-mapped, so these function calls are a nop, but
they provide good semantic documentation for any
From: Gabe Black gabebl...@chromium.org
In the structure returned by the ATA identify device command, there are two
fields which describe the device capacity. One is a 32 bit data type which
reports the number of sectors as a 28 bit LBA, and the other is a 64 bit data
type which is for a 48 bit
From: Vadim Bendebury vben...@chromium.org
Many AHCI controllers are identical, the main (and often the
only) difference being the PCI Vendor ID/Device ID combination
reported by the device.
This change allows the config file to define a list of PCI vendor
ID/device ID pairs. The driver would
From: Stefan Reinauer reina...@chromium.org
The existing code waits a whole second for the AHCI controller to reset.
Instead, let's poll the status register to see if the reset has
succeeded and return earlier if possible. This brings down the time for
AHCI probing from 1s to 20ms.
From: Gabe Black gabebl...@chromium.org
This command doesn't really do anything when talking to a SATA device, and
sending it confuses some of them. This change makes sending the command
optional, and defaults to not. The situations where it should be sent are not
the common case.
With the
From: Stefan Reinauer reina...@chromium.org
Add a new function to find out the number of available SCSI disks.
Signed-off-by: Stefan Reinauer reina...@chromium.org
Signed-off-by: Simon Glass s...@chromium.org
---
common/cmd_scsi.c |7 +++
include/scsi.h|2 ++
2 files changed, 9
From: Marc Jones marc.jo...@chromium.org
Add HDD handling to the SSD-only AHCI driver, by separately dealing with
spin-up and link-up.
Signed-off-by: Marc Jones marc.jo...@chromium.org
Signed-off-by: Simon Glass s...@chromium.org
---
drivers/block/ahci.c | 45
Enable AHCI driver for Intel SATA devices.
Signed-off-by: Simon Glass s...@chromium.org
---
include/configs/coreboot.h | 21 +
1 files changed, 21 insertions(+), 0 deletions(-)
diff --git a/include/configs/coreboot.h b/include/configs/coreboot.h
index 3df085b..968a9c5
From: Taylor Hutt th...@chromium.org
This cleanup replaces the hardcoded use of '20', which represents the
number of bytes in the FIS, with sizeof(fis).
Signed-off-by: Taylor Hutt th...@chromium.org
Signed-off-by: Simon Glass s...@chromium.org
---
drivers/block/ahci.c | 10 +-
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