[U-Boot] [PATCH] image: Add support for Plan 9
From 2c6086251774e6dcdba8ee9a83c8b5cbe2a643f4 Mon Sep 17 00:00:00 2001
This patch adds support for Plan 9 to image.c; primarily a cosmetic change
when booting Plan 9 kernels using U-Boot.
---
common/image.c | 1 +
include/image.h | 1 +
2 files changed, 2 insertions(+)
diff --git a/common/image.c b/common/image.c
index 6afbb40..60c2127 100644
--- a/common/image.c
+++ b/common/image.c
@@ -108,6 +108,7 @@ static const table_entry_t uimage_os[] = {
#endif
{ IH_OS_NETBSD, netbsd, NetBSD, },
{ IH_OS_OSE, ose, Enea OSE, },
+ { IH_OS_PLAN9, plan9, Plan 9, },
{ IH_OS_RTEMS, rtems, RTEMS, },
{ IH_OS_U_BOOT, u-boot, U-Boot, },
#if defined(CONFIG_CMD_ELF) || defined(USE_HOSTCC)
diff --git a/include/image.h b/include/image.h
index 8e285f9..4ad0e6b 100644
--- a/include/image.h
+++ b/include/image.h
@@ -84,6 +84,7 @@
#define IH_OS_UNITY 20 /* Unity OS */
#define IH_OS_INTEGRITY 21 /* INTEGRITY */
#define IH_OS_OSE 22 /* OSE */
+#define IH_OS_PLAN9 23 /* Plan 9 */
/*
* CPU Architecture Codes (supported by Linux)
--
1.8.2
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Re: [U-Boot] AT91SAM9M10 Custom Board U-boot reboot after Wrong Image Format
Hi Bo Thanks a lot for your help. Best regards MArcio On Sat, 16 Mar 2013 19:46:06 -0700 (PDT), Bo Shen [via U-Boot] wrote: Hi Marcio, This is not u-boot related, I think you should post this issue to Linux kernel mailing list. On 03/16/2013 10:58 PM, [hidden email] wrote: [Snip] NAND device: Manufacturer ID: 0x2c, Chip ID: 0xba (Micron NAND 256MiB 1,8V 16-bi t) Scanning device for bad blocks Bad eraseblock 40 at 0x0050 Bad eraseblock 41 at 0x0052 Bad eraseblock 800 at 0x0640 Bad eraseblock 801 at 0x0642 Creating 3 MTD partitions on atmel_nand: 0x-0x0050 : Bootstrap 0x0050-0x0640 : system 0x0640-0x1000 : userdata UBI: attaching mtd1 to ubi0 UBI: physical eraseblock size: 131072 bytes (128 KiB) UBI: logical eraseblock size: 129024 bytes UBI: smallest flash I/O unit: 2048 UBI: sub-page size: 512 UBI: VID header offset: 512 (aligned 512) UBI: data offset: 2048 I check the NAND flash spec and find you may use wrong parameters for generating UBIFS image. ---8--- Page size x16: 1056 words (1024 + 32 words) --- and no sub-page. So, I think mini I/O unit should be 1024 x 4 = 4096 Bytes uncorrectable error : uncorrectable error : uncorrectable error : uncorrectable error : UBI error: ubi_io_read: error -74 (ECC error) while reading 64 bytes from PEB 2: 0, read 64 bytes This is ECC error, I think you should also update the driver for atmel_nand.c (mainly ECC layout) Best Regards, Bo Shen ___ U-Boot mailing list [hidden email] http://lists.denx.de/mailman/listinfo/u-boot [1] - If you reply to this email, your message will be added to the discussion below: http://u-boot.10912.n7.nabble.com/AT91SAM9M10-Custom-Board-U-boot-reboot-after-Wrong-Image-Format-tp149567p149902.html [2] To unsubscribe from AT91SAM9M10 Custom Board U-boot reboot after Wrong Image Format, click here [3]. NAML [4] Links: -- [1] http://lists.denx.de/mailman/listinfo/u-boot [2] http://u-boot.10912.n7.nabble.com/AT91SAM9M10-Custom-Board-U-boot-reboot-after-Wrong-Image-Format-tp149567p149902.html [3] http://u-boot.10912.n7.nabble.com/template/NamlServlet.jtp?macro=unsubscribe_by_code|+|amp|+|node=149567|+|amp|+|code=bWFyY2lvQG5ldG9wZW4uY29tLmJyfDE0OTU2N3wxMDMwNzQyMzcx [4] http://u-boot.10912.n7.nabble.com/template/NamlServlet.jtp?macro=macro_viewer|+|amp|+|id=instant_html%21nabble%3Aemail.naml|+|amp|+|base=nabble.naml.namespaces.BasicNamespace-nabble.view.web.template.NabbleNamespace-nabble.view.web.template.NodeNamespace|+|amp|+|breadcrumbs=notify_subscribers%21nabble%3Aemail.naml-instant_emails%21nabble%3Aemail.naml-send_instant_email%21nabble%3Aemail.naml -- View this message in context: http://u-boot.10912.n7.nabble.com/AT91SAM9M10-Custom-Board-U-boot-reboot-after-Wrong-Image-Format-tp149567p149918.html Sent from the U-Boot mailing list archive at Nabble.com.___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Pull request: u-boot-arm/master
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 On 03/16/2013 04:19 AM, Albert ARIBAUD wrote: Hi Albert, On Fri, 15 Mar 2013 23:01:12 +0100, Albert ARIBAUD albert.u.b...@aribaud.net wrote: Hello Tom, Here is a PR for ARM. Note that doc/README.scrapyard will need a manual merge resolution due to ARM tree having a commit that reorders the headers and reformats the lines while mainline has a commit adding two new entries still in the older format. The following changes since commit fc959081d41aab2d6f4614c5fb3dd1b77ffcdcf4: x86: Enable CONFIG_OF_CONTROL on coreboot (2013-03-04 15:57:52 -0800) are available in the git repository at: git://git.denx.de/u-boot-arm master for you to fetch changes up to b27673ccbd3d5435319b5c09c3e7061f559f925d: Merge branch 'u-boot-tegra/master' into 'u-boot-arm/master' (2013-03-15 20:50:43 +0100) Sorry about the extra merge conflicts -- at the time of my posting, I only had the scapyard one. Seems like most new conflicts are due to Simon's BSS name change; that should be resolved by taking my BSS changes and changing the symbol's name as Simon does elsewhere, but by the looks of your IRC comment, you'd already figured it out and only the tegra conflict is left to resolve. I suspect I have all conflicts resolved correctly, but can't run-time test them. If someone with a Tegra platform would like to get ahold of me privately, quickly, I'll send along a binary to try out and confirm I've got the merge correct. Otherwise I'll post the diff monday morning. - -- Tom -BEGIN PGP SIGNATURE- Version: GnuPG v1.4.11 (GNU/Linux) Comment: Using GnuPG with Thunderbird - http://www.enigmail.net/ iQIcBAEBAgAGBQJRRhxAAAoJENk4IS6UOR1W70gP/0O2fnhKbuNYHw5g0BT8iapR +xfhKflu5+QDIcruCDX4QkzxgG8onvrBwAkjahSWMjJy+QRRjwM4ik24HYMzLbMN jWjy/AkJ9hAfrp4Knq/dcKkordM97Bsg0E2mrnSxJTxqQ8vRU5UzZdBga7bl3YRK U5+YeN5c9ZmGHHtbmhw7zbcPo+7ZwRQEhiMMa4hnCzjZiCu7h3ZNTCuenu/povcr enQ3LmGtmJdBHsyMccuYh0EJNnYeMnfFmNk5S3roH1ryxqiTOFZIk5n6O7xLxWBD BxeFC+KmFAt+pbXtl/CUrW0WWyw8YsecO5q/chl0tKXt/EeGGbcuABQ5RrBkXsYU zD0anY0y9xip8R81IRwbINqvOPxX0tkhJXSQoL6luYNgggZxt4xqrYEUaHaBQJE1 04jy12qRdH5ijUci6/PexY6yigS5yK+G3oiy7GVqSPWW/b3aCgdlygBSsKFONY9p KHjRNWMz5V/JRCDI0doEzsqJMO94OqGpyZLa6GWIyy6Fk+nheja/OZtDg/fQaSin 10V8GU9YqZ47Ojbr3r2thfDOsmxp4ICjIm2zoKPUuNG9JPImAf3CTtD+DGkijoU/ NIHqHjV3kBSVpxROTfNc8yc+jEjik7FoFCaRTjknKajuZbRTW8anQPiaSmX12WfR /3UQOpob05rx+OCYYEpq =L6aj -END PGP SIGNATURE- ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2] patman: Allow specifying the message ID your series is in reply to
Some versions of git don't seem to prompt you for the message ID that
your series is in reply to. Allow specifying this from the command
line.
Signed-off-by: Doug Anderson diand...@chromium.org
Acked-by: Simon Glass s...@chromium.org
---
Changes in v2:
- Adjusted docstring wording as per Otavio Salvador.
tools/patman/gitutil.py | 7 ++-
tools/patman/patman.py | 4 +++-
2 files changed, 9 insertions(+), 2 deletions(-)
diff --git a/tools/patman/gitutil.py b/tools/patman/gitutil.py
index ca3ba4a..c35d209 100644
--- a/tools/patman/gitutil.py
+++ b/tools/patman/gitutil.py
@@ -203,7 +203,7 @@ def BuildEmailList(in_list, tag=None, alias=None):
return result
def EmailPatches(series, cover_fname, args, dry_run, cc_fname,
-self_only=False, alias=None):
+self_only=False, alias=None, in_reply_to=None):
Email a patch series.
Args:
@@ -213,6 +213,8 @@ def EmailPatches(series, cover_fname, args, dry_run,
cc_fname,
dry_run: Just return the command that would be run
cc_fname: Filename of Cc file for per-commit Cc
self_only: True to just email to yourself as a test
+in_reply_to: If set we'll pass this to git as --in-reply-to.
+Should be a message ID that this is in reply to.
Returns:
Git command that was/would be run
@@ -262,6 +264,9 @@ def EmailPatches(series, cover_fname, args, dry_run,
cc_fname,
to = BuildEmailList([os.getenv('USER')], '--to', alias)
cc = []
cmd = ['git', 'send-email', '--annotate']
+if in_reply_to:
+cmd.append('--in-reply-to=%s' % in_reply_to)
+
cmd += to
cmd += cc
cmd += ['--cc-cmd', '%s --cc-cmd %s' % (sys.argv[0], cc_fname)]
diff --git a/tools/patman/patman.py b/tools/patman/patman.py
index e049081..377408d 100755
--- a/tools/patman/patman.py
+++ b/tools/patman/patman.py
@@ -53,6 +53,8 @@ parser.add_option('-n', '--dry-run', action='store_true',
dest='dry_run',
parser.add_option('-p', '--project', default=project.DetectProject(),
help=Project name; affects default option values and
aliases [default: %default])
+parser.add_option('-r', '--in-reply-to', type='string', action='store',
+ help=Message ID that this series is in reply to)
parser.add_option('-s', '--start', dest='start', type='int',
default=0, help='Commit to start creating patches from (0 = HEAD)')
parser.add_option('-t', '--test', action='store_true', dest='test',
@@ -163,7 +165,7 @@ else:
cmd = ''
if ok or options.ignore_errors:
cmd = gitutil.EmailPatches(series, cover_fname, args,
-options.dry_run, cc_file)
+options.dry_run, cc_file, in_reply_to=options.in_reply_to)
# For a dry run, just show our actions as a sanity check
if options.dry_run:
--
1.8.1.3
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[U-Boot] [PATCH 0/4 v7] Add ACE HW support for SHA256 and SHA1
This patch set adds hardware acceleration for SHA 256 with the help of ACE. Changes since v1: - Patch-1: Fixed few nits. - Patch-2: Removed not required config. - Patch-3: Added sha256 to hash command instead of new sha256 command. Changes since v2: - Patch-1: - Added falling back to software sha256 in case length exceeds buffer limit. - Reduced one tab at lines 533, 559 and 571 in the patch. - Removed space after a cast at line 506 in the patch. - Removed blank line at line 561 in the patch. - Removed space before semicolon at line 576 in the patch. - Patch-2: - Added SHA1 in the comment for config. - Patch-3: - Added new nodes for SHA1 and SHA256 in struct hash_algo for the case when ACE is enabled. - Added new declaration for function pointer hash_func_ws with different return type. - Patch-4: - New patch to enable config for hash command. Changes since v3: - Patch-1: - Removed buffer limit since there are 2 regs for address hash_msg_size_high and low. That means buffer length could go upto 2^64 bits which is practically - Removed falling back to software sha256 because there is no buffer limit. - Removed / 4 to sha1 and sha256 lengths and added increment to 4 in for loop at line 573. - Timed out still kept to be 100 ms since this is enough for hardware to switch status to idle from busy. In case it couldn't that means h/w is faulty. - Patch-2: - Added Acked-by: Simon Glass s...@chromium.org. - Patch-3: - New patch. - Patch-4: - Changed command names to lower case in algo struct. - Added generic ace_sha config. - Patch-5: Added acked-by Simon Glass - Added new generic config for ace_sha to enable ace support in hash.c. Changes since v4: - Patch-1: - Added include for clk.h. - Added define for MAX_FREQ. - Added timeout calculation as per frequency. - Changed i+=4 to i++ and len to len/4 in for loop at line 591 in this patch. - Added two new functions ace_sha256 and ace_sha1. - Patch-2: None. - Patch-3: - Changed function names in struct algo. - Replaced ACE_SHA_TYPE to CHUNSZ in struct algo. - Patch-4: Added Acked-by: Simon Glass s...@chromium.org. Changes since v5: - Patch-1: - Removed ace_sha.h. - Renamed ace_sfr.h as ace_sha.h. - Removed timeout and checking for PRNG_ERROR bit in HASH_STATUS register. PRNG_ERROR bit high means setup was not done properly. Since there is no way to detect faulty h/w, we consider the possible fact that h/w should not be able to setup feed properly if it's faulty. - Renamed function name ace_sha256 to hw_sha256 and ace_sha1 to hw_sha1. - Patch-2: None. - Patch-3: - Added file hw_sha.h. - Changed CONFIG_ACE_SHA to CONFIG_SHA_HW_ACCEL. - Renamed function names ace_sha1 and ace_sha256 to hw_sha1 and hw_sha256 respectively. - Patch-4: - Removed Acked-by: Simon Glass s...@chromium.org because of a change. - Changed CONFIG_ACE_SHA to CONFIG_SHA_HW_ACCEL. Changes since v6: - Patch-1: Added Acked-by: Simon Glass s...@chromium.org. - Patch-2: None. - Patch-3: - Changed position of hw_sha.h among includes (alpha order). - Rebased patch. - Patch-4: Added Acked-by: Simon Glass s...@chromium.org. Akshay Saraswat (4): Exynos: Add hardware accelerated SHA256 and SHA1 Exynos: config: Enable ACE HW for SHA 256 for Exynos gen: Add sha h/w acceleration to hash Exynos: config: Enable hash command Makefile | 1 + arch/arm/include/asm/arch-exynos/ace_sha.h | 327 + arch/arm/include/asm/arch-exynos/cpu.h | 4 + common/hash.c | 18 ++ drivers/crypto/Makefile| 47 + drivers/crypto/ace_sha.c | 129 include/configs/exynos5250-dt.h| 5 + include/hw_sha.h | 50 + 8 files changed, 581 insertions(+) create mode 100644 arch/arm/include/asm/arch-exynos/ace_sha.h create mode 100644 drivers/crypto/Makefile create mode 100644 drivers/crypto/ace_sha.c create mode 100644 include/hw_sha.h -- 1.8.0
[U-Boot] [PATCH 1/4 v7] Exynos: Add hardware accelerated SHA256 and SHA1
SHA-256 and SHA-1 accelerated using ACE hardware.
Signed-off-by: ARUN MANKUZHI aru...@samsung.com
Signed-off-by: Akshay Saraswat aksha...@samsung.com
Acked-by: Simon Glass s...@chromium.org
---
Changes since v1:
- Moved code to drivers/crypto.
- Fixed few other nits.
Changes since v2:
- Added falling back to software sha256 in case length exceeds buffer
limit.
- Reduced one tab at lines 533, 559 and 571 in this patch.
- Removed space after a cast at line 506 in this patch.
- Removed blank line at line 561 in this patch.
- Removed space before semicolon at line 576 in this patch.
Changes since v3:
- Removed buffer limit since there are 2 regs for address
hash_msg_size_high and low.
That means buffer length could go upto 2^64 bits which is practically
- Removed falling back to software sha256 because there is no buffer
limit.
- Removed / 4 to sha1 and sha256 lengths and added increment to 4 in
for
loop at line 573.
- Timed out still kept to be 100 ms since this is enough for hardware
to switch
status to idle from busy.
In case it couldn't that means h/w is faulty.
Changes since v4:
- Added include for clk.h.
- Added define for MAX_FREQ.
- Added timeout calculation as per frequency.
- Changed i+=4 to i++ and len to len/4 in for loop at line 591
in this patch.
- Added two new functions ace_sha256 and ace_sha1.
Changes since v5:
- Removed ace_sha.h.
- Renamed ace_sfr.h as ace_sha.h.
- Removed timeout and checking for PRNG_ERROR bit in HASH_STATUS
register.
PRNG_ERROR bit high means setup was not done properly. Since there is
no
way to detect faulty h/w, we consider the possible fact that h/w
should
not be able to setup feed properly if it's faulty.
- Renamed function name ace_sha256 to hw_sha256 and ace_sha1 to hw_sha1.
Changes since v6:
- Added Acked-by: Simon Glass s...@chromium.org.
Makefile | 1 +
arch/arm/include/asm/arch-exynos/ace_sha.h | 327 +
arch/arm/include/asm/arch-exynos/cpu.h | 4 +
drivers/crypto/Makefile| 47 +
drivers/crypto/ace_sha.c | 129
5 files changed, 508 insertions(+)
create mode 100644 arch/arm/include/asm/arch-exynos/ace_sha.h
create mode 100644 drivers/crypto/Makefile
create mode 100644 drivers/crypto/ace_sha.c
diff --git a/Makefile b/Makefile
index 55bd55c..54f86d8 100644
--- a/Makefile
+++ b/Makefile
@@ -273,6 +273,7 @@ LIBS-y += disk/libdisk.o
LIBS-y += drivers/bios_emulator/libatibiosemu.o
LIBS-y += drivers/block/libblock.o
LIBS-$(CONFIG_BOOTCOUNT_LIMIT) += drivers/bootcount/libbootcount.o
+LIBS-y += drivers/crypto/libcrypto.o
LIBS-y += drivers/dma/libdma.o
LIBS-y += drivers/fpga/libfpga.o
LIBS-y += drivers/gpio/libgpio.o
diff --git a/arch/arm/include/asm/arch-exynos/ace_sha.h
b/arch/arm/include/asm/arch-exynos/ace_sha.h
new file mode 100644
index 000..259f3d9
--- /dev/null
+++ b/arch/arm/include/asm/arch-exynos/ace_sha.h
@@ -0,0 +1,327 @@
+/*
+ * Header file for Advanced Crypto Engine - SFR definitions
+ *
+ * Copyright (c) 2012 Samsung Electronics
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+
+#ifndef __ACE_SHA_H
+#define __ACE_SHA_H
+
+struct exynos_ace_sfr {
+ unsigned intfc_intstat; /* base + 0 */
+ unsigned intfc_intenset;
+ unsigned intfc_intenclr;
+ unsigned intfc_intpend;
+ unsigned intfc_fifostat;
+ unsigned intfc_fifoctrl;
+ unsigned intfc_global;
+ unsigned intres1;
+ unsigned intfc_brdmas;
+ unsigned intfc_brdmal;
+ unsigned intfc_brdmac;
+ unsigned intres2;
+ unsigned intfc_btdmas;
+ unsigned intfc_btdmal;
+ unsigned intfc_btdmac;
+ unsigned intres3;
+ unsigned intfc_hrdmas;
+ unsigned intfc_hrdmal;
+ unsigned intfc_hrdmac;
+ unsigned intres4;
+ unsigned intfc_pkdmas;
+ unsigned intfc_pkdmal;
+ unsigned intfc_pkdmac;
+ unsigned intfc_pkdmao;
+
[U-Boot] [PATCH 3/4 v7] gen: Add sha h/w acceleration to hash
Adding H/W acceleration support to hash which can be used
to test SHA 256 hash algorithm.
Signed-off-by: ARUN MANKUZHI aru...@samsung.com
Signed-off-by: Akshay Saraswat aksha...@samsung.com
---
Changes since v1:
- Added sha256 support to hash command instead of new sha256 command.
Changes sice v2:
- Added new nodes for SHA1 and SHA256 in struct hash_algo for the case
when ACE is enabled.
- Added new declaration for function pointer hash_func_ws with
different return type.
Changes sice v3:
- Changed command names to lower case in algo struct.
- Added generic ace_sha config.
Changes sice v4:
- Changed function names in struct algo.
- Replaced ACE_SHA_TYPE to CHUNSZ in struct algo.
Changes sice v5:
- Added file hw_sha.h.
- Changed CONFIG_ACE_SHA to CONFIG_SHA_HW_ACCEL.
- Renamed function names ace_sha1 and ace_sha256 to hw_sha1 and
hw_sha256 respectively.
Changes sice v6:
- Changed position of hw_sha.h among includes (alpha order).
- Rebased patch.
common/hash.c| 18 ++
include/hw_sha.h | 50 ++
2 files changed, 68 insertions(+)
create mode 100644 include/hw_sha.h
diff --git a/common/hash.c b/common/hash.c
index f5badcb..5f46dc6 100644
--- a/common/hash.c
+++ b/common/hash.c
@@ -25,6 +25,7 @@
#include common.h
#include command.h
+#include hw_sha.h
#include hash.h
#include sha1.h
#include sha256.h
@@ -37,6 +38,23 @@
*/
static struct hash_algo hash_algo[] = {
/*
+* CONFIG_SHA_HW_ACCEL is defined if hardware acceleration is
+* available.
+*/
+#ifdef CONFIG_SHA_HW_ACCEL
+ {
+ sha1,
+ SHA1_SUM_LEN,
+ hw_sha1,
+ CHUNKSZ_SHA1,
+ }, {
+ sha256,
+ SHA256_SUM_LEN,
+ hw_sha256,
+ CHUNKSZ_SHA256,
+ },
+#endif
+ /*
* This is CONFIG_CMD_SHA1SUM instead of CONFIG_SHA1 since otherwise
* it bloats the code for boards which use SHA1 but not the 'hash'
* or 'sha1sum' commands.
diff --git a/include/hw_sha.h b/include/hw_sha.h
new file mode 100644
index 000..565e5a0
--- /dev/null
+++ b/include/hw_sha.h
@@ -0,0 +1,50 @@
+/*
+ * Header file for SHA hardware acceleration
+ *
+ * Copyright (c) 2012 Samsung Electronics
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+#ifndef __HW_SHA_H
+#define __HW_SHA_H
+
+
+/**
+ * Computes hash value of input pbuf using h/w acceleration
+ *
+ * @param in_addr A pointer to the input buffer
+ * @param bufleni Byte length of input buffer
+ * @param out_addr A pointer to the output buffer. When complete
+ * 32 bytes are copied to pout[0]...pout[31]. Thus, a user
+ * should allocate at least 32 bytes at pOut in advance.
+ * @param chunk_size chunk size for sha256
+ */
+void hw_sha256(const uchar *in_addr, uint buflen,
+ uchar *out_addr, uint chunk_size);
+
+/**
+ * Computes hash value of input pbuf using h/w acceleration
+ *
+ * @param in_addr A pointer to the input buffer
+ * @param bufleni Byte length of input buffer
+ * @param out_addr A pointer to the output buffer. When complete
+ * 32 bytes are copied to pout[0]...pout[31]. Thus, a user
+ * should allocate at least 32 bytes at pOut in advance.
+ * @param chunk_size chunk_size for sha1
+ */
+void hw_sha1(const uchar *in_addr, uint buflen,
+ uchar *out_addr, uint chunk_size);
+#endif
--
1.8.0
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[U-Boot] [PATCH 4/4 v7] Exynos: config: Enable hash command
This enables hash command. Tested with command hash sha256 0x40008000 0x2B 0x40009000. Used mm and md to write a standard string to memory location 0x40008000 and ran the above command to verify the output. Signed-off-by: ARUN MANKUZHI aru...@samsung.com Signed-off-by: Akshay Saraswat aksha...@samsung.com Acked-by: Simon Glass s...@chromium.org --- Changes since v2: - New patch to enable config for hash command. Changes since v3: - Added new generic config for ace_sha to enable ace support in hash.c. Changes since v4: - Added Acked-by: Simon Glass s...@chromium.org. Changes since v5: - Removed Acked-by: Simon Glass s...@chromium.org because of a change. - Changed CONFIG_ACE_SHA to CONFIG_SHA_HW_ACCEL. Changes since v6: - Added Acked-by: Simon Glass s...@chromium.org. include/configs/exynos5250-dt.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/configs/exynos5250-dt.h b/include/configs/exynos5250-dt.h index 1fb47a0..9680b9d 100644 --- a/include/configs/exynos5250-dt.h +++ b/include/configs/exynos5250-dt.h @@ -48,6 +48,7 @@ /* Enable ACE acceleration for SHA1 and SHA256 */ #define CONFIG_EXYNOS_ACE_SHA +#define CONFIG_SHA_HW_ACCEL #define CONFIG_SYS_SDRAM_BASE 0x4000 #define CONFIG_SYS_TEXT_BASE 0x43E0 @@ -117,6 +118,7 @@ #define CONFIG_CMD_EXT2 #define CONFIG_CMD_FAT #define CONFIG_CMD_NET +#define CONFIG_CMD_HASH #define CONFIG_BOOTDELAY 3 #define CONFIG_ZERO_BOOTDELAY_CHECK -- 1.8.0 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 2/4 v7] Exynos: config: Enable ACE HW for SHA 256 for Exynos
This enables SHA 256 for exynos. Signed-off-by: ARUN MANKUZHI aru...@samsung.com Signed-off-by: Akshay Saraswat aksha...@samsung.com Acked-by: Simon Glass s...@chromium.org --- Changes since v1: - Removed not required config. Changes sice v2: - Added SHA1 in the comment for config. Changes sice v3: - Added Acked-by: Simon Glass s...@chromium.org. Changes sice v4: - None. Changes sice v5: - None. Changes sice v6: - None. include/configs/exynos5250-dt.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/configs/exynos5250-dt.h b/include/configs/exynos5250-dt.h index 1c624d4..1fb47a0 100644 --- a/include/configs/exynos5250-dt.h +++ b/include/configs/exynos5250-dt.h @@ -46,6 +46,9 @@ /* Keep L2 Cache Disabled */ #define CONFIG_SYS_DCACHE_OFF +/* Enable ACE acceleration for SHA1 and SHA256 */ +#define CONFIG_EXYNOS_ACE_SHA + #define CONFIG_SYS_SDRAM_BASE 0x4000 #define CONFIG_SYS_TEXT_BASE 0x43E0 -- 1.8.0 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
