Re: [U-Boot] U-boot: Erase/read/write issue with S25fl256S flash device
Hi Jagan,
On Saturday 15 June 2013 09:47 PM, Jagan Teki wrote:
On 14-06-2013 20:13, Sourav Poddar wrote:
Hi Jagan,
On Friday 14 June 2013 08:08 PM, Jagan Teki wrote:
On 14-06-2013 20:03, Sourav Poddar wrote:
Hi,
On Wednesday 12 June 2013 01:00 PM, Sourav Poddar wrote:
Hi,
I am working on qspi flash device S25FL256S at u-boot level. I am
trying to
make use of the existing spi_flash.c framework available at u-boot
for
erasing/reading/writing
into the flash device.
There are several issues(mentioned below), which I faced while using
S25FL256s flash device
with my dra7xx board which has a qspi controller to which the above
mentioned flash device is attached.
1. Erase (spi_flash_cmd_erase)
Issuing a command something like this..
sf erase 0x0 0x5
- erases only first 0x2 bytes of flash device, anything above
that is not erase. I need to
issue separate commands after 0x2 for every 0x1 bytes.
Am i missing anything here?
2. read
sf read 8100 0 0x1
Read is not happening properly. The last few byte along the 4k
boundary always shows zero.
Above 4k bytes, read is not happening.
For ex:
DRA752 EVM # md 81000f00
81000f00:
81000f10:
81000f20:
81000f30:
81000f40:
81000f50:
81000f60:
81000f70:
81000f80:
81000f90:
81000fa0:
81000fb0:
81000fc0:
81000fd0:
81000fe0:
81000ff0: 00ff
In this dump, if you see 81000ff0 the last column shows 00
which is
not expected. and it happens along every 4k bytes.
So, to get rid of the above issue, I switched to page read with the
below patch[1],
which is giving me the correct result.
[1]:
@@ -147,17 +153,40 @@ int spi_flash_read_common(struct spi_flash
*flash, const u8 *cmd,
int spi_flash_cmd_read_fast(struct spi_flash *flash, u32 offset,
size_t len, void *data)
{
- u8 cmd[5];
+ unsigned long page_addr, byte_addr, page_size;
+ size_t chunk_len, actual;
+ int ret = 0;
+ u8 cmd[4];
/* Handle memory-mapped SPI */
if (flash-memory_map)
memcpy(data, flash-memory_map + offset, len);
+ page_size = flash-page_size;
+ page_addr = offset / page_size;
+ byte_addr = offset % page_size;
+
+ cmd[0] = CMD_READ_ARRAY_SLOW;
+ for (actual = 0; actual len; actual += chunk_len) {
+ chunk_len = min(len - actual, page_size - byte_addr);
+
+ cmd[1] = page_addr 8;
+ cmd[2] = page_addr;
+ cmd[3] = byte_addr;
+
+ ret = spi_flash_read_common(flash, cmd, sizeof(cmd),
data + actual, chunk_len);
+ if (ret 0) {
+ debug(SF: read failed);
+ break;
+ }
- cmd[0] = CMD_READ_ARRAY_FAST;
- spi_flash_addr(offset, cmd);
- cmd[4] = 0x00;
+ byte_addr += chunk_len;
+ if (byte_addr == page_size) {
+ page_addr++;
+ byte_addr = 0;
+ }
+ }
- return spi_flash_read_common(flash, cmd, sizeof(cmd), data,
len);
+ return ret;
}
Any idea about this?
3. write (spi_flash_cmd_write_multi)
write not happening properly.
observations: only able to write single page, anything after a
page is
not getting
written.
Workaround:
I did a write disable latch at the end of every write cycle(page
program) and enable it
again for the next loop. With this, I see I get rid of the above
issue.
@@ -117,6 +117,12 @@ int spi_flash_cmd_write_multi(struct spi_flash
*flash, u32 offset,
if (ret)
break;
+ ret = spi_flash_cmd_write_disable(flash);
+ if (ret 0) {
+ printf(SF: disabling write failed\n);
+ break;
+ }
+
Have anyone seen the above mentioned issues regarding
read/write/erase? OR is there any
configurations that I might be missing ?
Any Input on this?
Please wait, I am pushing some changes tonight or so.
We will continue this thread, after testing your part with these new
changes.
I will intimate you once
Re: [U-Boot] Porting U-boot-2013-04 to sdk for mips board
Hi Alll,
Can anyone please reply on this.
Regards,
krishna
On Fri, Jun 14, 2013 at 10:14 AM, krishna dwivedi
krishna.dwived...@gmail.com wrote:
Hi All,
In mips,i dont see the .reloc section in u-boot.lds.But in other
architechtures(like ppc),I see in u-boot.lds:
.reloc :
{
PROVIDE(_GOT2_TABLE_ = .);
KEEP(*(.got2))
KEEP(*(.got))
PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
_FIXUP_TABLE_ = .;
KEEP(*(.fixup))
}
__got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) 2) - 1;
__fixup_entries = (. - _FIXUP_TABLE_) 2;
1)Can anyone please let me know,if we dont need to add .reloc section in
u-boot.lds for MIPS processor?
2)I am newbie to u-boot,Please anyone provide me pointers what are the
things i need to do lowlevel_init for my mips processor.
Regards,
Krishna
On Thu, Jun 13, 2013 at 5:49 PM, krishna dwivedi
krishna.dwived...@gmail.com wrote:
Hi,
I am trying to port the u-boot2013:04 to sdk.During compilation,I am
running into error:*Undefined reference to _GLOBAL_OFFSET_TABLE*.I
checked in u-boot.lds file thr is no definition of _GLOBAL_OFFSET_TABLE.I
have added this piece of code in u-boot.lds:
.reloc :
{
KEEP(*(.got))
PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
}
In addition,i see reference of GLOBAL_OFFSET_TABLE.But it is not defined
in any file and even linker script.
Can anyone please confirm,if this is common issue in u-boot version
2013:04.
Regards,
krishna
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Re: [U-Boot] [PATCH] image: Use ENOENT instead of ENOMEDIUM for better compatibility
On 16.06.13 16:46, Simon Glass wrote: This error may not be defined on some platforms such as MacOS so host compilation will fail. Use one of the more common errors instead. Signed-off-by: Simon Glass s...@chromium.org Tested-by: Andreas Bießmann andreas.de...@googlemail.com on OS X 10.7.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] checkpatch.pl: Do not hardcode perl path
Dear Joel A Fernandes, On 16.06.13 17:44, Joel A Fernandes wrote: On Sunday, June 16, 2013, Jagannadha Sutradharudu Teki wrote: From: Jagannadha Sutradharudu Teki jagannadh.t...@gmail.comjavascript:; checkpatch.pl requires perl v5.10.0 to run but it doesn't require to place in /usr/bin/perl Use env to ensure that the interpreter used is the first one on environment's $PATH on system with several versions of perl installed. Signed-off-by: Jagannadha Sutradharudu Teki jagannadh.t...@gmail.comjavascript:; --- tools/checkpatch.pl | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/tools/checkpatch.pl b/tools/checkpatch.pl index 896e2bc..8dc5b9c 100755 --- a/tools/checkpatch.pl +++ b/tools/checkpatch.pl @@ -1,10 +1,11 @@ -#!/usr/bin/perl -w +#!/usr/bin/env perl Would it not work to pass in the -w here? this is not portable! BSD variants of env will only take a single parameter. Best regards Andreas Bießmann ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] U-boot: Erase/read/write issue with S25fl256S flash device
Hi Sourav,
On Mon, Jun 17, 2013 at 11:44 AM, Sourav Poddar sourav.pod...@ti.com wrote:
Hi Jagan,
On Saturday 15 June 2013 09:47 PM, Jagan Teki wrote:
On 14-06-2013 20:13, Sourav Poddar wrote:
Hi Jagan,
On Friday 14 June 2013 08:08 PM, Jagan Teki wrote:
On 14-06-2013 20:03, Sourav Poddar wrote:
Hi,
On Wednesday 12 June 2013 01:00 PM, Sourav Poddar wrote:
Hi,
I am working on qspi flash device S25FL256S at u-boot level. I am
trying to
make use of the existing spi_flash.c framework available at u-boot for
erasing/reading/writing
into the flash device.
There are several issues(mentioned below), which I faced while using
S25FL256s flash device
with my dra7xx board which has a qspi controller to which the above
mentioned flash device is attached.
1. Erase (spi_flash_cmd_erase)
Issuing a command something like this..
sf erase 0x0 0x5
- erases only first 0x2 bytes of flash device, anything above
that is not erase. I need to
issue separate commands after 0x2 for every 0x1 bytes.
Am i missing anything here?
2. read
sf read 8100 0 0x1
Read is not happening properly. The last few byte along the 4k
boundary always shows zero.
Above 4k bytes, read is not happening.
For ex:
DRA752 EVM # md 81000f00
81000f00:
81000f10:
81000f20:
81000f30:
81000f40:
81000f50:
81000f60:
81000f70:
81000f80:
81000f90:
81000fa0:
81000fb0:
81000fc0:
81000fd0:
81000fe0:
81000ff0: 00ff
In this dump, if you see 81000ff0 the last column shows 00 which
is
not expected. and it happens along every 4k bytes.
So, to get rid of the above issue, I switched to page read with the
below patch[1],
which is giving me the correct result.
[1]:
@@ -147,17 +153,40 @@ int spi_flash_read_common(struct spi_flash
*flash, const u8 *cmd,
int spi_flash_cmd_read_fast(struct spi_flash *flash, u32 offset,
size_t len, void *data)
{
- u8 cmd[5];
+ unsigned long page_addr, byte_addr, page_size;
+ size_t chunk_len, actual;
+ int ret = 0;
+ u8 cmd[4];
/* Handle memory-mapped SPI */
if (flash-memory_map)
memcpy(data, flash-memory_map + offset, len);
+ page_size = flash-page_size;
+ page_addr = offset / page_size;
+ byte_addr = offset % page_size;
+
+ cmd[0] = CMD_READ_ARRAY_SLOW;
+ for (actual = 0; actual len; actual += chunk_len) {
+ chunk_len = min(len - actual, page_size - byte_addr);
+
+ cmd[1] = page_addr 8;
+ cmd[2] = page_addr;
+ cmd[3] = byte_addr;
+
+ ret = spi_flash_read_common(flash, cmd, sizeof(cmd),
data + actual, chunk_len);
+ if (ret 0) {
+ debug(SF: read failed);
+ break;
+ }
- cmd[0] = CMD_READ_ARRAY_FAST;
- spi_flash_addr(offset, cmd);
- cmd[4] = 0x00;
+ byte_addr += chunk_len;
+ if (byte_addr == page_size) {
+ page_addr++;
+ byte_addr = 0;
+ }
+ }
- return spi_flash_read_common(flash, cmd, sizeof(cmd), data,
len);
+ return ret;
}
Any idea about this?
3. write (spi_flash_cmd_write_multi)
write not happening properly.
observations: only able to write single page, anything after a page is
not getting
written.
Workaround:
I did a write disable latch at the end of every write cycle(page
program) and enable it
again for the next loop. With this, I see I get rid of the above
issue.
@@ -117,6 +117,12 @@ int spi_flash_cmd_write_multi(struct spi_flash
*flash, u32 offset,
if (ret)
break;
+ ret = spi_flash_cmd_write_disable(flash);
+ if (ret 0) {
+ printf(SF: disabling write failed\n);
+ break;
+ }
+
Have anyone seen the above mentioned issues regarding
read/write/erase? OR is there any
configurations that I
Re: [U-Boot] TFTP timeouts, i.mx fec problem?
Hi Wolfgang, Interesting thought. Never looked at it from this site, but this can be true of course. Although somewhat harder to proof, I'm afraid. I will keep this in mind for any further testing I will do. Regards, Ruud -Oorspronkelijk bericht- Van: Wolfgang Denk [mailto:w...@denx.de] Verzonden: vrijdag 14 juni 2013 17:31 Aan: Ruud Commandeur CC: Eric Bénard; Marek Vašut; U-Boot list Onderwerp: Re: [U-Boot] TFTP timeouts, i.mx fec problem? Dear Ruud, In message 15ae5a936f5e3a42a9144e66875a0a89309...@server1-derijp.clb-Ben elux.lokaal you wrote: I noticed these pins on the board. They have optional pull-down resistors, which are not placed by default. This would result in mode[2:0] being 111: All capable. Auto-negotiation enabled. And as I look at the code, the cofiguration bits are set quite identical to this mode (10 + 100, Both FULL + HALF, aneg enabled). And on the other hand: after this sw-config + reset, the autonegotiation itself succeeds, indicated by the status bits and LED's. But for some reason it is not ready to transmit yet... Hm... autonegotiation does not happen on the board only, it is something between the board an the switch. Would it be possible that the switch takes longer to become ready to receive than the target board takes to become ready to send? Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de Like winter snow on summer lawn, time past is time gone. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] U-boot: Erase/read/write issue with S25fl256S flash device
HI Jagan,
On Monday 17 June 2013 12:17 PM, Jagan Teki wrote:
Hi Sourav,
On Mon, Jun 17, 2013 at 11:44 AM, Sourav Poddarsourav.pod...@ti.com wrote:
Hi Jagan,
On Saturday 15 June 2013 09:47 PM, Jagan Teki wrote:
On 14-06-2013 20:13, Sourav Poddar wrote:
Hi Jagan,
On Friday 14 June 2013 08:08 PM, Jagan Teki wrote:
On 14-06-2013 20:03, Sourav Poddar wrote:
Hi,
On Wednesday 12 June 2013 01:00 PM, Sourav Poddar wrote:
Hi,
I am working on qspi flash device S25FL256S at u-boot level. I am
trying to
make use of the existing spi_flash.c framework available at u-boot for
erasing/reading/writing
into the flash device.
There are several issues(mentioned below), which I faced while using
S25FL256s flash device
with my dra7xx board which has a qspi controller to which the above
mentioned flash device is attached.
1. Erase (spi_flash_cmd_erase)
Issuing a command something like this..
sf erase 0x0 0x5
- erases only first 0x2 bytes of flash device, anything above
that is not erase. I need to
issue separate commands after 0x2 for every 0x1 bytes.
Am i missing anything here?
2. read
sf read 8100 0 0x1
Read is not happening properly. The last few byte along the 4k
boundary always shows zero.
Above 4k bytes, read is not happening.
For ex:
DRA752 EVM # md 81000f00
81000f00:
81000f10:
81000f20:
81000f30:
81000f40:
81000f50:
81000f60:
81000f70:
81000f80:
81000f90:
81000fa0:
81000fb0:
81000fc0:
81000fd0:
81000fe0:
81000ff0: 00ff
In this dump, if you see 81000ff0 the last column shows 00 which
is
not expected. and it happens along every 4k bytes.
So, to get rid of the above issue, I switched to page read with the
below patch[1],
which is giving me the correct result.
[1]:
@@ -147,17 +153,40 @@ int spi_flash_read_common(struct spi_flash
*flash, const u8 *cmd,
int spi_flash_cmd_read_fast(struct spi_flash *flash, u32 offset,
size_t len, void *data)
{
- u8 cmd[5];
+ unsigned long page_addr, byte_addr, page_size;
+ size_t chunk_len, actual;
+ int ret = 0;
+ u8 cmd[4];
/* Handle memory-mapped SPI */
if (flash-memory_map)
memcpy(data, flash-memory_map + offset, len);
+ page_size = flash-page_size;
+ page_addr = offset / page_size;
+ byte_addr = offset % page_size;
+
+ cmd[0] = CMD_READ_ARRAY_SLOW;
+ for (actual = 0; actual len; actual += chunk_len) {
+ chunk_len = min(len - actual, page_size - byte_addr);
+
+ cmd[1] = page_addr 8;
+ cmd[2] = page_addr;
+ cmd[3] = byte_addr;
+
+ ret = spi_flash_read_common(flash, cmd, sizeof(cmd),
data + actual, chunk_len);
+ if (ret 0) {
+ debug(SF: read failed);
+ break;
+ }
- cmd[0] = CMD_READ_ARRAY_FAST;
- spi_flash_addr(offset, cmd);
- cmd[4] = 0x00;
+ byte_addr += chunk_len;
+ if (byte_addr == page_size) {
+ page_addr++;
+ byte_addr = 0;
+ }
+ }
- return spi_flash_read_common(flash, cmd, sizeof(cmd), data,
len);
+ return ret;
}
Any idea about this?
3. write (spi_flash_cmd_write_multi)
write not happening properly.
observations: only able to write single page, anything after a page is
not getting
written.
Workaround:
I did a write disable latch at the end of every write cycle(page
program) and enable it
again for the next loop. With this, I see I get rid of the above
issue.
@@ -117,6 +117,12 @@ int spi_flash_cmd_write_multi(struct spi_flash
*flash, u32 offset,
if (ret)
break;
+ ret = spi_flash_cmd_write_disable(flash);
+ if (ret 0) {
+ printf(SF: disabling write failed\n);
+ break;
+ }
+
Have anyone seen the above mentioned issues regarding
read/write/erase? OR is there any
configurations that I might be missing ?
Any Input on this?
Re: [U-Boot] Merge Window close date
Dear Masahiro Yamada, In message 20130617103018.2753.aa925...@jp.panasonic.com you wrote: I saw Release Cycle page (http://www.denx.de/wiki/U-Boot/ReleaseCycle), and I noticed, The Merge Window for the next release (v2013.07) was closed on Sat, Feb 09, 2013 23:59:59 CEST ^^^ Thanks, fixed. Could anyone fix it? Actually you could have fixed it yourslef - the web site is a wiki, and editing the page takes not much more effort than posting a message on the mailing list. Thanks for pointing out! Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de The first rule of magic is simple. Don't waste your time waving your hands and hoping when a rock or a club will do. - McCloctnik the Lucid ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] U-boot: Erase/read/write issue with S25fl256S flash device
On Mon, Jun 17, 2013 at 12:28 PM, Sourav Poddar sourav.pod...@ti.com wrote:
HI Jagan,
On Monday 17 June 2013 12:17 PM, Jagan Teki wrote:
Hi Sourav,
On Mon, Jun 17, 2013 at 11:44 AM, Sourav Poddarsourav.pod...@ti.com
wrote:
Hi Jagan,
On Saturday 15 June 2013 09:47 PM, Jagan Teki wrote:
On 14-06-2013 20:13, Sourav Poddar wrote:
Hi Jagan,
On Friday 14 June 2013 08:08 PM, Jagan Teki wrote:
On 14-06-2013 20:03, Sourav Poddar wrote:
Hi,
On Wednesday 12 June 2013 01:00 PM, Sourav Poddar wrote:
Hi,
I am working on qspi flash device S25FL256S at u-boot level. I am
trying to
make use of the existing spi_flash.c framework available at u-boot
for
erasing/reading/writing
into the flash device.
There are several issues(mentioned below), which I faced while using
S25FL256s flash device
with my dra7xx board which has a qspi controller to which the above
mentioned flash device is attached.
1. Erase (spi_flash_cmd_erase)
Issuing a command something like this..
sf erase 0x0 0x5
- erases only first 0x2 bytes of flash device, anything above
that is not erase. I need to
issue separate commands after 0x2 for every 0x1 bytes.
Am i missing anything here?
2. read
sf read 8100 0 0x1
Read is not happening properly. The last few byte along the 4k
boundary always shows zero.
Above 4k bytes, read is not happening.
For ex:
DRA752 EVM # md 81000f00
81000f00:
81000f10:
81000f20:
81000f30:
81000f40:
81000f50:
81000f60:
81000f70:
81000f80:
81000f90:
81000fa0:
81000fb0:
81000fc0:
81000fd0:
81000fe0:
81000ff0: 00ff
In this dump, if you see 81000ff0 the last column shows 00 which
is
not expected. and it happens along every 4k bytes.
So, to get rid of the above issue, I switched to page read with the
below patch[1],
which is giving me the correct result.
[1]:
@@ -147,17 +153,40 @@ int spi_flash_read_common(struct spi_flash
*flash, const u8 *cmd,
int spi_flash_cmd_read_fast(struct spi_flash *flash, u32 offset,
size_t len, void *data)
{
- u8 cmd[5];
+ unsigned long page_addr, byte_addr, page_size;
+ size_t chunk_len, actual;
+ int ret = 0;
+ u8 cmd[4];
/* Handle memory-mapped SPI */
if (flash-memory_map)
memcpy(data, flash-memory_map + offset, len);
+ page_size = flash-page_size;
+ page_addr = offset / page_size;
+ byte_addr = offset % page_size;
+
+ cmd[0] = CMD_READ_ARRAY_SLOW;
+ for (actual = 0; actual len; actual += chunk_len) {
+ chunk_len = min(len - actual, page_size -
byte_addr);
+
+ cmd[1] = page_addr 8;
+ cmd[2] = page_addr;
+ cmd[3] = byte_addr;
+
+ ret = spi_flash_read_common(flash, cmd, sizeof(cmd),
data + actual, chunk_len);
+ if (ret 0) {
+ debug(SF: read failed);
+ break;
+ }
- cmd[0] = CMD_READ_ARRAY_FAST;
- spi_flash_addr(offset, cmd);
- cmd[4] = 0x00;
+ byte_addr += chunk_len;
+ if (byte_addr == page_size) {
+ page_addr++;
+ byte_addr = 0;
+ }
+ }
- return spi_flash_read_common(flash, cmd, sizeof(cmd), data,
len);
+ return ret;
}
Any idea about this?
3. write (spi_flash_cmd_write_multi)
write not happening properly.
observations: only able to write single page, anything after a page
is
not getting
written.
Workaround:
I did a write disable latch at the end of every write cycle(page
program) and enable it
again for the next loop. With this, I see I get rid of the above
issue.
@@ -117,6 +117,12 @@ int spi_flash_cmd_write_multi(struct
spi_flash
*flash, u32 offset,
if (ret)
break;
+ ret = spi_flash_cmd_write_disable(flash);
+ if (ret 0) {
+ printf(SF: disabling write failed\n);
+
Re: [U-Boot] [PATCH] image: Use ENOENT instead of ENOMEDIUM for better compatibility
On 16.06.2013 17:46, Simon Glass wrote: This error may not be defined on some platforms such as MacOS so host compilation will fail. Use one of the more common errors instead. Signed-off-by: Simon Glass s...@chromium.org Tested-by: Lubomir Popov lpo...@mm-sol.com on MacOS X 10.8.3 with the following tools used for building U-Boot: arm-none-eabi-gcc (GCC) 4.7.2 GNU ld (GNU Binutils) 2.23.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] U-boot: Erase/read/write issue with S25fl256S flash device
On Monday 17 June 2013 12:35 PM, Jagan Teki wrote:
On Mon, Jun 17, 2013 at 12:28 PM, Sourav Poddarsourav.pod...@ti.com wrote:
HI Jagan,
On Monday 17 June 2013 12:17 PM, Jagan Teki wrote:
Hi Sourav,
On Mon, Jun 17, 2013 at 11:44 AM, Sourav Poddarsourav.pod...@ti.com
wrote:
Hi Jagan,
On Saturday 15 June 2013 09:47 PM, Jagan Teki wrote:
On 14-06-2013 20:13, Sourav Poddar wrote:
Hi Jagan,
On Friday 14 June 2013 08:08 PM, Jagan Teki wrote:
On 14-06-2013 20:03, Sourav Poddar wrote:
Hi,
On Wednesday 12 June 2013 01:00 PM, Sourav Poddar wrote:
Hi,
I am working on qspi flash device S25FL256S at u-boot level. I am
trying to
make use of the existing spi_flash.c framework available at u-boot
for
erasing/reading/writing
into the flash device.
There are several issues(mentioned below), which I faced while using
S25FL256s flash device
with my dra7xx board which has a qspi controller to which the above
mentioned flash device is attached.
1. Erase (spi_flash_cmd_erase)
Issuing a command something like this..
sf erase 0x0 0x5
- erases only first 0x2 bytes of flash device, anything above
that is not erase. I need to
issue separate commands after 0x2 for every 0x1 bytes.
Am i missing anything here?
2. read
sf read 8100 0 0x1
Read is not happening properly. The last few byte along the 4k
boundary always shows zero.
Above 4k bytes, read is not happening.
For ex:
DRA752 EVM # md 81000f00
81000f00:
81000f10:
81000f20:
81000f30:
81000f40:
81000f50:
81000f60:
81000f70:
81000f80:
81000f90:
81000fa0:
81000fb0:
81000fc0:
81000fd0:
81000fe0:
81000ff0: 00ff
In this dump, if you see 81000ff0 the last column shows 00 which
is
not expected. and it happens along every 4k bytes.
So, to get rid of the above issue, I switched to page read with the
below patch[1],
which is giving me the correct result.
[1]:
@@ -147,17 +153,40 @@ int spi_flash_read_common(struct spi_flash
*flash, const u8 *cmd,
int spi_flash_cmd_read_fast(struct spi_flash *flash, u32 offset,
size_t len, void *data)
{
- u8 cmd[5];
+ unsigned long page_addr, byte_addr, page_size;
+ size_t chunk_len, actual;
+ int ret = 0;
+ u8 cmd[4];
/* Handle memory-mapped SPI */
if (flash-memory_map)
memcpy(data, flash-memory_map + offset, len);
+ page_size = flash-page_size;
+ page_addr = offset / page_size;
+ byte_addr = offset % page_size;
+
+ cmd[0] = CMD_READ_ARRAY_SLOW;
+ for (actual = 0; actual len; actual += chunk_len) {
+ chunk_len = min(len - actual, page_size -
byte_addr);
+
+ cmd[1] = page_addr 8;
+ cmd[2] = page_addr;
+ cmd[3] = byte_addr;
+
+ ret = spi_flash_read_common(flash, cmd, sizeof(cmd),
data + actual, chunk_len);
+ if (ret 0) {
+ debug(SF: read failed);
+ break;
+ }
- cmd[0] = CMD_READ_ARRAY_FAST;
- spi_flash_addr(offset, cmd);
- cmd[4] = 0x00;
+ byte_addr += chunk_len;
+ if (byte_addr == page_size) {
+ page_addr++;
+ byte_addr = 0;
+ }
+ }
- return spi_flash_read_common(flash, cmd, sizeof(cmd), data,
len);
+ return ret;
}
Any idea about this?
3. write (spi_flash_cmd_write_multi)
write not happening properly.
observations: only able to write single page, anything after a page
is
not getting
written.
Workaround:
I did a write disable latch at the end of every write cycle(page
program) and enable it
again for the next loop. With this, I see I get rid of the above
issue.
@@ -117,6 +117,12 @@ int spi_flash_cmd_write_multi(struct
spi_flash
*flash, u32 offset,
if (ret)
break;
+ ret = spi_flash_cmd_write_disable(flash);
+ if (ret 0) {
+ printf(SF: disabling write failed\n);
+ break;
+ }
+
Have
Re: [U-Boot] U-boot: Erase/read/write issue with S25fl256S flash device
On Mon, Jun 17, 2013 at 12:41 PM, Sourav Poddar sourav.pod...@ti.com wrote:
On Monday 17 June 2013 12:35 PM, Jagan Teki wrote:
On Mon, Jun 17, 2013 at 12:28 PM, Sourav Poddarsourav.pod...@ti.com
wrote:
HI Jagan,
On Monday 17 June 2013 12:17 PM, Jagan Teki wrote:
Hi Sourav,
On Mon, Jun 17, 2013 at 11:44 AM, Sourav Poddarsourav.pod...@ti.com
wrote:
Hi Jagan,
On Saturday 15 June 2013 09:47 PM, Jagan Teki wrote:
On 14-06-2013 20:13, Sourav Poddar wrote:
Hi Jagan,
On Friday 14 June 2013 08:08 PM, Jagan Teki wrote:
On 14-06-2013 20:03, Sourav Poddar wrote:
Hi,
On Wednesday 12 June 2013 01:00 PM, Sourav Poddar wrote:
Hi,
I am working on qspi flash device S25FL256S at u-boot level. I am
trying to
make use of the existing spi_flash.c framework available at u-boot
for
erasing/reading/writing
into the flash device.
There are several issues(mentioned below), which I faced while
using
S25FL256s flash device
with my dra7xx board which has a qspi controller to which the
above
mentioned flash device is attached.
1. Erase (spi_flash_cmd_erase)
Issuing a command something like this..
sf erase 0x0 0x5
- erases only first 0x2 bytes of flash device, anything
above
that is not erase. I need to
issue separate commands after 0x2 for every 0x1
bytes.
Am i missing anything here?
2. read
sf read 8100 0 0x1
Read is not happening properly. The last few byte along the 4k
boundary always shows zero.
Above 4k bytes, read is not happening.
For ex:
DRA752 EVM # md 81000f00
81000f00:
81000f10:
81000f20:
81000f30:
81000f40:
81000f50:
81000f60:
81000f70:
81000f80:
81000f90:
81000fa0:
81000fb0:
81000fc0:
81000fd0:
81000fe0:
81000ff0: 00ff
In this dump, if you see 81000ff0 the last column shows 00
which
is
not expected. and it happens along every 4k bytes.
So, to get rid of the above issue, I switched to page read with
the
below patch[1],
which is giving me the correct result.
[1]:
@@ -147,17 +153,40 @@ int spi_flash_read_common(struct spi_flash
*flash, const u8 *cmd,
int spi_flash_cmd_read_fast(struct spi_flash *flash, u32
offset,
size_t len, void *data)
{
- u8 cmd[5];
+ unsigned long page_addr, byte_addr, page_size;
+ size_t chunk_len, actual;
+ int ret = 0;
+ u8 cmd[4];
/* Handle memory-mapped SPI */
if (flash-memory_map)
memcpy(data, flash-memory_map + offset, len);
+ page_size = flash-page_size;
+ page_addr = offset / page_size;
+ byte_addr = offset % page_size;
+
+ cmd[0] = CMD_READ_ARRAY_SLOW;
+ for (actual = 0; actual len; actual += chunk_len) {
+ chunk_len = min(len - actual, page_size -
byte_addr);
+
+ cmd[1] = page_addr 8;
+ cmd[2] = page_addr;
+ cmd[3] = byte_addr;
+
+ ret = spi_flash_read_common(flash, cmd,
sizeof(cmd),
data + actual, chunk_len);
+ if (ret 0) {
+ debug(SF: read failed);
+ break;
+ }
- cmd[0] = CMD_READ_ARRAY_FAST;
- spi_flash_addr(offset, cmd);
- cmd[4] = 0x00;
+ byte_addr += chunk_len;
+ if (byte_addr == page_size) {
+ page_addr++;
+ byte_addr = 0;
+ }
+ }
- return spi_flash_read_common(flash, cmd, sizeof(cmd),
data,
len);
+ return ret;
}
Any idea about this?
3. write (spi_flash_cmd_write_multi)
write not happening properly.
observations: only able to write single page, anything after a
page
is
not getting
written.
Workaround:
I did a write disable latch at the end of every write cycle(page
program) and enable it
again for the next loop. With this, I see I get rid of the above
issue.
@@ -117,6 +117,12 @@ int spi_flash_cmd_write_multi(struct
spi_flash
*flash, u32 offset,
if (ret)
break;
Re: [U-Boot] U-boot: Erase/read/write issue with S25fl256S flash device
On Monday 17 June 2013 12:44 PM, Jagan Teki wrote:
On Mon, Jun 17, 2013 at 12:41 PM, Sourav Poddarsourav.pod...@ti.com wrote:
On Monday 17 June 2013 12:35 PM, Jagan Teki wrote:
On Mon, Jun 17, 2013 at 12:28 PM, Sourav Poddarsourav.pod...@ti.com
wrote:
HI Jagan,
On Monday 17 June 2013 12:17 PM, Jagan Teki wrote:
Hi Sourav,
On Mon, Jun 17, 2013 at 11:44 AM, Sourav Poddarsourav.pod...@ti.com
wrote:
Hi Jagan,
On Saturday 15 June 2013 09:47 PM, Jagan Teki wrote:
On 14-06-2013 20:13, Sourav Poddar wrote:
Hi Jagan,
On Friday 14 June 2013 08:08 PM, Jagan Teki wrote:
On 14-06-2013 20:03, Sourav Poddar wrote:
Hi,
On Wednesday 12 June 2013 01:00 PM, Sourav Poddar wrote:
Hi,
I am working on qspi flash device S25FL256S at u-boot level. I am
trying to
make use of the existing spi_flash.c framework available at u-boot
for
erasing/reading/writing
into the flash device.
There are several issues(mentioned below), which I faced while
using
S25FL256s flash device
with my dra7xx board which has a qspi controller to which the
above
mentioned flash device is attached.
1. Erase (spi_flash_cmd_erase)
Issuing a command something like this..
sf erase 0x0 0x5
- erases only first 0x2 bytes of flash device, anything
above
that is not erase. I need to
issue separate commands after 0x2 for every 0x1
bytes.
Am i missing anything here?
2. read
sf read 8100 0 0x1
Read is not happening properly. The last few byte along the 4k
boundary always shows zero.
Above 4k bytes, read is not happening.
For ex:
DRA752 EVM # md 81000f00
81000f00:
81000f10:
81000f20:
81000f30:
81000f40:
81000f50:
81000f60:
81000f70:
81000f80:
81000f90:
81000fa0:
81000fb0:
81000fc0:
81000fd0:
81000fe0:
81000ff0: 00ff
In this dump, if you see 81000ff0 the last column shows 00
which
is
not expected. and it happens along every 4k bytes.
So, to get rid of the above issue, I switched to page read with
the
below patch[1],
which is giving me the correct result.
[1]:
@@ -147,17 +153,40 @@ int spi_flash_read_common(struct spi_flash
*flash, const u8 *cmd,
int spi_flash_cmd_read_fast(struct spi_flash *flash, u32
offset,
size_t len, void *data)
{
- u8 cmd[5];
+ unsigned long page_addr, byte_addr, page_size;
+ size_t chunk_len, actual;
+ int ret = 0;
+ u8 cmd[4];
/* Handle memory-mapped SPI */
if (flash-memory_map)
memcpy(data, flash-memory_map + offset, len);
+ page_size = flash-page_size;
+ page_addr = offset / page_size;
+ byte_addr = offset % page_size;
+
+ cmd[0] = CMD_READ_ARRAY_SLOW;
+ for (actual = 0; actuallen; actual += chunk_len) {
+ chunk_len = min(len - actual, page_size -
byte_addr);
+
+ cmd[1] = page_addr8;
+ cmd[2] = page_addr;
+ cmd[3] = byte_addr;
+
+ ret = spi_flash_read_common(flash, cmd,
sizeof(cmd),
data + actual, chunk_len);
+ if (ret0) {
+ debug(SF: read failed);
+ break;
+ }
- cmd[0] = CMD_READ_ARRAY_FAST;
- spi_flash_addr(offset, cmd);
- cmd[4] = 0x00;
+ byte_addr += chunk_len;
+ if (byte_addr == page_size) {
+ page_addr++;
+ byte_addr = 0;
+ }
+ }
- return spi_flash_read_common(flash, cmd, sizeof(cmd),
data,
len);
+ return ret;
}
Any idea about this?
3. write (spi_flash_cmd_write_multi)
write not happening properly.
observations: only able to write single page, anything after a
page
is
not getting
written.
Workaround:
I did a write disable latch at the end of every write cycle(page
program) and enable it
again for the next loop. With this, I see I get rid of the above
issue.
@@ -117,6 +117,12 @@ int spi_flash_cmd_write_multi(struct
spi_flash
*flash, u32 offset,
if (ret)
break;
+ ret = spi_flash_cmd_write_disable(flash);
+
Re: [U-Boot] U-boot: Erase/read/write issue with S25fl256S flash device
On Mon, Jun 17, 2013 at 12:49 PM, Sourav Poddar sourav.pod...@ti.com wrote:
On Monday 17 June 2013 12:44 PM, Jagan Teki wrote:
On Mon, Jun 17, 2013 at 12:41 PM, Sourav Poddarsourav.pod...@ti.com
wrote:
On Monday 17 June 2013 12:35 PM, Jagan Teki wrote:
On Mon, Jun 17, 2013 at 12:28 PM, Sourav Poddarsourav.pod...@ti.com
wrote:
HI Jagan,
On Monday 17 June 2013 12:17 PM, Jagan Teki wrote:
Hi Sourav,
On Mon, Jun 17, 2013 at 11:44 AM, Sourav Poddarsourav.pod...@ti.com
wrote:
Hi Jagan,
On Saturday 15 June 2013 09:47 PM, Jagan Teki wrote:
On 14-06-2013 20:13, Sourav Poddar wrote:
Hi Jagan,
On Friday 14 June 2013 08:08 PM, Jagan Teki wrote:
On 14-06-2013 20:03, Sourav Poddar wrote:
Hi,
On Wednesday 12 June 2013 01:00 PM, Sourav Poddar wrote:
Hi,
I am working on qspi flash device S25FL256S at u-boot level. I
am
trying to
make use of the existing spi_flash.c framework available at
u-boot
for
erasing/reading/writing
into the flash device.
There are several issues(mentioned below), which I faced while
using
S25FL256s flash device
with my dra7xx board which has a qspi controller to which the
above
mentioned flash device is attached.
1. Erase (spi_flash_cmd_erase)
Issuing a command something like this..
sf erase 0x0 0x5
- erases only first 0x2 bytes of flash device, anything
above
that is not erase. I need to
issue separate commands after 0x2 for every 0x1
bytes.
Am i missing anything here?
2. read
sf read 8100 0 0x1
Read is not happening properly. The last few byte along the 4k
boundary always shows zero.
Above 4k bytes, read is not happening.
For ex:
DRA752 EVM # md 81000f00
81000f00:
81000f10:
81000f20:
81000f30:
81000f40:
81000f50:
81000f60:
81000f70:
81000f80:
81000f90:
81000fa0:
81000fb0:
81000fc0:
81000fd0:
81000fe0:
81000ff0: 00ff
In this dump, if you see 81000ff0 the last column shows 00
which
is
not expected. and it happens along every 4k bytes.
So, to get rid of the above issue, I switched to page read with
the
below patch[1],
which is giving me the correct result.
[1]:
@@ -147,17 +153,40 @@ int spi_flash_read_common(struct spi_flash
*flash, const u8 *cmd,
int spi_flash_cmd_read_fast(struct spi_flash *flash, u32
offset,
size_t len, void *data)
{
- u8 cmd[5];
+ unsigned long page_addr, byte_addr, page_size;
+ size_t chunk_len, actual;
+ int ret = 0;
+ u8 cmd[4];
/* Handle memory-mapped SPI */
if (flash-memory_map)
memcpy(data, flash-memory_map + offset,
len);
+ page_size = flash-page_size;
+ page_addr = offset / page_size;
+ byte_addr = offset % page_size;
+
+ cmd[0] = CMD_READ_ARRAY_SLOW;
+ for (actual = 0; actuallen; actual += chunk_len) {
+ chunk_len = min(len - actual, page_size -
byte_addr);
+
+ cmd[1] = page_addr8;
+ cmd[2] = page_addr;
+ cmd[3] = byte_addr;
+
+ ret = spi_flash_read_common(flash, cmd,
sizeof(cmd),
data + actual, chunk_len);
+ if (ret0) {
+ debug(SF: read failed);
+ break;
+ }
- cmd[0] = CMD_READ_ARRAY_FAST;
- spi_flash_addr(offset, cmd);
- cmd[4] = 0x00;
+ byte_addr += chunk_len;
+ if (byte_addr == page_size) {
+ page_addr++;
+ byte_addr = 0;
+ }
+ }
- return spi_flash_read_common(flash, cmd, sizeof(cmd),
data,
len);
+ return ret;
}
Any idea about this?
3. write (spi_flash_cmd_write_multi)
write not happening properly.
observations: only able to write single page, anything after a
page
is
not getting
written.
Workaround:
I did a write disable latch at the end of every write cycle(page
program) and enable it
again for the next loop. With this, I see I get rid of the above
issue.
@@ -117,6 +117,12 @@ int
Re: [U-Boot] U-boot: Erase/read/write issue with S25fl256S flash device
Hi Jagan,
On Monday 17 June 2013 01:04 PM, Jagan Teki wrote:
On Mon, Jun 17, 2013 at 12:49 PM, Sourav Poddarsourav.pod...@ti.com wrote:
On Monday 17 June 2013 12:44 PM, Jagan Teki wrote:
On Mon, Jun 17, 2013 at 12:41 PM, Sourav Poddarsourav.pod...@ti.com
wrote:
On Monday 17 June 2013 12:35 PM, Jagan Teki wrote:
On Mon, Jun 17, 2013 at 12:28 PM, Sourav Poddarsourav.pod...@ti.com
wrote:
HI Jagan,
On Monday 17 June 2013 12:17 PM, Jagan Teki wrote:
Hi Sourav,
On Mon, Jun 17, 2013 at 11:44 AM, Sourav Poddarsourav.pod...@ti.com
wrote:
Hi Jagan,
On Saturday 15 June 2013 09:47 PM, Jagan Teki wrote:
On 14-06-2013 20:13, Sourav Poddar wrote:
Hi Jagan,
On Friday 14 June 2013 08:08 PM, Jagan Teki wrote:
On 14-06-2013 20:03, Sourav Poddar wrote:
Hi,
On Wednesday 12 June 2013 01:00 PM, Sourav Poddar wrote:
Hi,
I am working on qspi flash device S25FL256S at u-boot level. I
am
trying to
make use of the existing spi_flash.c framework available at
u-boot
for
erasing/reading/writing
into the flash device.
There are several issues(mentioned below), which I faced while
using
S25FL256s flash device
with my dra7xx board which has a qspi controller to which the
above
mentioned flash device is attached.
1. Erase (spi_flash_cmd_erase)
Issuing a command something like this..
sf erase 0x0 0x5
- erases only first 0x2 bytes of flash device, anything
above
that is not erase. I need to
issue separate commands after 0x2 for every 0x1
bytes.
Am i missing anything here?
2. read
sf read 8100 0 0x1
Read is not happening properly. The last few byte along the 4k
boundary always shows zero.
Above 4k bytes, read is not happening.
For ex:
DRA752 EVM # md 81000f00
81000f00:
81000f10:
81000f20:
81000f30:
81000f40:
81000f50:
81000f60:
81000f70:
81000f80:
81000f90:
81000fa0:
81000fb0:
81000fc0:
81000fd0:
81000fe0:
81000ff0: 00ff
In this dump, if you see 81000ff0 the last column shows 00
which
is
not expected. and it happens along every 4k bytes.
So, to get rid of the above issue, I switched to page read with
the
below patch[1],
which is giving me the correct result.
[1]:
@@ -147,17 +153,40 @@ int spi_flash_read_common(struct spi_flash
*flash, const u8 *cmd,
int spi_flash_cmd_read_fast(struct spi_flash *flash, u32
offset,
size_t len, void *data)
{
- u8 cmd[5];
+ unsigned long page_addr, byte_addr, page_size;
+ size_t chunk_len, actual;
+ int ret = 0;
+ u8 cmd[4];
/* Handle memory-mapped SPI */
if (flash-memory_map)
memcpy(data, flash-memory_map + offset,
len);
+ page_size = flash-page_size;
+ page_addr = offset / page_size;
+ byte_addr = offset % page_size;
+
+ cmd[0] = CMD_READ_ARRAY_SLOW;
+ for (actual = 0; actual len; actual += chunk_len) {
+ chunk_len = min(len - actual, page_size -
byte_addr);
+
+ cmd[1] = page_addr 8;
+ cmd[2] = page_addr;
+ cmd[3] = byte_addr;
+
+ ret = spi_flash_read_common(flash, cmd,
sizeof(cmd),
data + actual, chunk_len);
+ if (ret 0) {
+ debug(SF: read failed);
+ break;
+ }
- cmd[0] = CMD_READ_ARRAY_FAST;
- spi_flash_addr(offset, cmd);
- cmd[4] = 0x00;
+ byte_addr += chunk_len;
+ if (byte_addr == page_size) {
+ page_addr++;
+ byte_addr = 0;
+ }
+ }
- return spi_flash_read_common(flash, cmd, sizeof(cmd),
data,
len);
+ return ret;
}
Any idea about this?
3. write (spi_flash_cmd_write_multi)
write not happening properly.
observations: only able to write single page, anything after a
page
is
not getting
written.
Workaround:
I did a write disable latch at the end of every write cycle(page
program) and enable it
again for the next loop. With this, I see I get rid of the above
issue.
@@ -117,6 +117,12 @@ int spi_flash_cmd_write_multi(struct
spi_flash
*flash, u32 offset,
Re: [U-Boot] please pull u-boot-samsung master
On Mon, Jun 17, 2013 at 7:40 AM, Minkyu Kang mk7.k...@samsung.com wrote: Dear Albert, The following changes since commit d0a51373131c4ba565a2391d5ed78b87c406ce98: at91sam9260ek: move board id setup to config header (2013-05-12 16:49:14 +0200) are available in the git repository at: git://git.denx.de/u-boot-samsung master for you to fetch changes up to ed7bdc03eb516fb698ccc12ec5b4b9f132d05c5f: MMC: DWMMC: Fix FIFO_DEPTH calculation (2013-06-17 11:03:42 +0900) Akshay Saraswat (2): Exynos5: clock: Update the equation to calculate PLL output frequency Exynos: uart: s5p: enabling the uart tx/rx fifo Amar (9): FDT: Add compatible string for DWMMC EXYNOS5: FDT: Add DWMMC device node data DWMMC: Initialise dwmci and resolve EMMC read write issues EXYNOS5: DWMMC: Added FDT support for DWMMC EXYNOS5: DWMMC: Initialise the local variable to avoid unwanted results. SMDK5250: Initialise and Enable DWMMC, support FDT and non-FDT MMC: APIs to support resize of EMMC boot partition SMDK5250: Enable EMMC booting COMMON: MMC: Command to support EMMC booting and to resize EMMC boot partition Arkadiusz Wlodarczyk (1): arm:trats: change auto-booting to boot kernel with separate device tree blob Inderpal Singh (3): exynos: move tzpc_init to armv7/exynos exynos: update tzpc to make it common for exynos4 and exynos5 exynos: Update origen and smdkv310 to use common tzpc_init Naveen Krishna Chatradhi (2): power: exynos-tmu: fix warnings and clean up code power: exynos-tmu: use the mux_addr bit fields in tmu_control register Rajeshwari Shinde (3): SF: Add driver for Gigabyte device GD25LQ and GD25Q64B SMDK5250: Enable SPI Gigabyte device. SPI gigabyte flash driver is not available in drivers/mtd/spi/ Am i missing anything here, please help. -- Thanks, Jagan. MMC: DWMMC: Fix FIFO_DEPTH calculation arch/arm/cpu/armv7/exynos/Makefile |2 +- arch/arm/cpu/armv7/exynos/clock.c | 10 +- .../arm/cpu/armv7/exynos/tzpc.c| 25 +- arch/arm/cpu/armv7/s5p-common/Makefile |2 + arch/arm/dts/exynos5250.dtsi | 33 ++ arch/arm/include/asm/arch-exynos/cpu.h |4 + arch/arm/include/asm/arch-exynos/dwmmc.h | 11 +- arch/arm/include/asm/arch-exynos/tmu.h | 58 ++- arch/arm/include/asm/arch-exynos/tzpc.h| 20 + board/samsung/dts/exynos5250-smdk5250.dts | 24 ++ board/samsung/origen/lowlevel_init.S | 44 +- board/samsung/origen/origen_setup.h| 25 -- board/samsung/smdk5250/Makefile|5 +- board/samsung/smdk5250/clock_init.c| 18 + board/samsung/smdk5250/clock_init.h|5 + board/samsung/smdk5250/exynos5-dt.c| 423 board/samsung/smdk5250/lowlevel_init.S |2 + board/samsung/smdk5250/setup.h | 25 -- board/samsung/smdk5250/smdk5250.c | 223 +++ board/samsung/smdk5250/spl_boot.c | 64 ++- board/samsung/smdkv310/lowlevel_init.S | 60 +-- common/cmd_mmc.c | 109 - doc/device-tree-bindings/exynos/dwmmc.txt | 54 +++ drivers/mmc/dw_mmc.c | 27 +- drivers/mmc/exynos_dw_mmc.c| 127 +- drivers/mmc/mmc.c | 134 +++ drivers/mtd/spi/Makefile |1 + drivers/mtd/spi/gigadevice.c | 81 drivers/mtd/spi/spi_flash.c|3 + drivers/mtd/spi/spi_flash_internal.h |1 + drivers/power/exynos-tmu.c | 123 +++--- drivers/serial/serial_s5p.c| 13 +- drivers/video/exynos_fb.c |4 +- include/configs/exynos5250-dt.h| 11 +- include/configs/origen.h |2 + include/configs/smdkv310.h |2 + include/configs/trats.h| 17 +- include/dwmmc.h|3 + include/fdtdec.h |1 + include/mmc.h | 26 ++ lib/fdtdec.c |1 + spl/Makefile |4 + 42 files changed, 1356 insertions(+), 471 deletions(-) rename board/samsung/smdk5250/tzpc_init.c = arch/arm/cpu/armv7/exynos/tzpc.c (69%) create mode 100644 board/samsung/smdk5250/exynos5-dt.c create mode 100644 doc/device-tree-bindings/exynos/dwmmc.txt
Re: [U-Boot] [PATCH] powerpc/p1022ds: nand: introduce the TPL based on the SPL
-Original Message- From: Wood Scott-B07421 Sent: Saturday, June 15, 2013 12:37 AM To: Zhang Ying-B40530 Cc: Wood Scott-B07421; u-boot@lists.denx.de; aflem...@gmail.com; Xie Xiaobo-R63061 Subject: Re: [PATCH] powerpc/p1022ds: nand: introduce the TPL based on the SPL On 06/14/2013 05:08:49 AM, Zhang Ying-B40530 wrote: -Original Message- From: Wood Scott-B07421 Sent: Friday, June 14, 2013 5:50 AM To: Zhang Ying-B40530 Cc: Wood Scott-B07421; u-boot@lists.denx.de; aflem...@gmail.com; Xie Xiaobo-R63061 Subject: Re: [PATCH] powerpc/p1022ds: nand: introduce the TPL based on the SPL On 06/13/2013 02:27:44 AM, Zhang Ying-B40530 wrote: -Original Message- From: Wood Scott-B07421 Sent: Thursday, June 13, 2013 6:29 AM To: Zhang Ying-B40530 Cc: u-boot@lists.denx.de; aflem...@gmail.com; Xie Xiaobo-R63061; Zhang Ying-B40530 Subject: Re: [PATCH] powerpc/p1022ds: nand: introduce the TPL based on the SPL On 06/09/2013 12:54:43 AM, ying.zh...@freescale.com wrote: From: Ying Zhang b40...@freescale.com Due to the nand SPL on the board P1022DS has a size limit, it can not be more than 4K. So, the SPL cannot initialize the DDR with the SPD code. This patch introduces TPL to enable a loader stub that runs in the L2 SRAM, after being loaded by the code from the SPL. It initializes the DDR with the SPD. The TPL's size is sizeable, the maximum size must not exceed the size of L2 SRAM. It initializes the DDR through SPD code, and copys final uboot image to DDR. So there are three stage uboot images: * spl_boot, 4KB size, pad to 128K byte. * tpl_boot, 88K size, pad to 128K size. The env variables are copied to L2 SRAM, so that ddr SPD code can get the interleaving mode setting in env. It loads final uboot image from offset 256KB. * final uboot image, size is variable depends on the functions enabled. This patch is on top of the patch: powerpc/p1022ds: boot from SD Card with SPL Signed-off-by: Ying Zhang b40...@freescale.com --- Makefile | 25 +++- README | 55 ++- arch/powerpc/config.mk |2 + arch/powerpc/cpu/mpc85xx/spl_minimal.c | 16 ++ arch/powerpc/cpu/mpc85xx/u-boot-tpl.lds| 80 + .../cpu/mpc8xxx/ddr/lc_common_dimm_params.c|4 +- arch/powerpc/lib/Makefile |2 + board/freescale/p1022ds/Makefile |3 + board/freescale/p1022ds/spl_minimal.c | 56 +-- board/freescale/p1022ds/tlb.c |4 +- board/freescale/p1022ds/tpl.c | 101 common/Makefile|9 + common/cmd_nvedit.c|8 +- config.mk | 32 doc/README.TPL | 93 +++ drivers/mtd/nand/Makefile |8 + drivers/mtd/nand/fsl_elbc_tpl.c| 168 drivers/serial/serial.c|2 +- include/bootstage.h|3 +- include/configs/P1022DS.h | 75 +++-- tpl/Makefile | 161 +++ 21 files changed, 824 insertions(+), 83 deletions(-) create mode 100644 arch/powerpc/cpu/mpc85xx/u-boot-tpl.lds create mode 100644 board/freescale/p1022ds/tpl.c create mode 100644 doc/README.TPL create mode 100644 drivers/mtd/nand/fsl_elbc_tpl.c create mode 100644 tpl/Makefile diff --git a/README b/README index 7add6d4..04f9aa5 100644 --- a/README +++ b/README @@ -2985,9 +2985,10 @@ FIT uImage format: Set for the SPL on PPC mpc8xxx targets, support for arch/powerpc/cpu/mpc8xxx/ddr/libddr.o in SPL binary. - CONFIG_SPL_COMMON_INIT_DDR + CONFIG_COMMON_INIT_DDR Set for common ddr init with serial presence detect in - SPL binary. + SPL binary or TPL binary. + CONFIG_SYS_NAND_5_ADDR_CYCLE, CONFIG_SYS_NAND_PAGE_COUNT, CONFIG_SYS_NAND_PAGE_SIZE, CONFIG_SYS_NAND_OOBSIZE, CONFIG_SYS_NAND_BLOCK_SIZE, CONFIG_SYS_NAND_BAD_BLOCK_POS, @@ -3058,6 +3059,56 @@ FIT uImage format: option to re-enable it. This will affect the output of the bootm command when booting a FIT image. +- TPL framework + CONFIG_TPL + Enable building of TPL globally. + + CONFIG_TPL_LDSCRIPT + LDSCRIPT for linking the TPL binary. + + CONFIG_TPL_MAX_SIZE +
[U-Boot] [PATCH 2/2] I2C: mxc_i2c: Add support for Vybrid VF610 platform
This patch adds support for Vybrid VF610 platform.
There are some differences between i.MX6 and Vybrid for I2C controller.
(1) The registers' offset are different.
(2) The I2C clock divider values are different.
(3) In I2C control register, the enable/disable/reset bit is inverted for
Vybrid comparing to i.MX6.
(4) In I2C status register, the interrupt flag bit is cleared by writing 1
for Vybrid.
For i.MX6, this bit is cleared by writing 0.
(5) In I2C status register, the arbitration lost flag bit is cleared by writing
1 for Vybrid.
For i.MX6, this bit is cleared by writing 0.
Signed-off-by: Alison Wang b18...@freescale.com
---
drivers/i2c/mxc_i2c.c | 62 +--
1 file changed, 55 insertions(+), 7 deletions(-)
diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c
index a73b10b..85e3e8b 100644
--- a/drivers/i2c/mxc_i2c.c
+++ b/drivers/i2c/mxc_i2c.c
@@ -38,6 +38,15 @@
#include i2c.h
#include watchdog.h
+#ifdef I2C_QUIRK_REG
+struct mxc_i2c_regs {
+ uint8_t iadr;
+ uint8_t ifdr;
+ uint8_t i2cr;
+ uint8_t i2sr;
+ uint8_t i2dr;
+};
+#else
struct mxc_i2c_regs {
uint32_tiadr;
uint32_tifdr;
@@ -45,8 +54,8 @@ struct mxc_i2c_regs {
uint32_ti2sr;
uint32_ti2dr;
};
+#endif
-#define I2CR_IEN (1 7)
#define I2CR_IIEN (1 6)
#define I2CR_MSTA (1 5)
#define I2CR_MTX (1 4)
@@ -59,10 +68,39 @@ struct mxc_i2c_regs {
#define I2SR_IIF (1 1)
#define I2SR_RX_NO_AK (1 0)
+#ifdef I2C_QUIRK_REG
+#define I2CR_IEN (0 7)
+#define I2CR_IDIS (1 7)
+#define I2SR_IIF_CLEAR (1 1)
+#else
+#define I2CR_IEN (1 7)
+#define I2CR_IDIS (0 7)
+#define I2SR_IIF_CLEAR (0 1)
+#endif
+
#if defined(CONFIG_HARD_I2C) !defined(CONFIG_SYS_I2C_BASE)
#error define CONFIG_SYS_I2C_BASE to use the mxc_i2c driver
#endif
+#ifdef I2C_QUIRK_REG
+static u16 i2c_clk_div[60][2] = {
+ { 20, 0x00 }, { 22, 0x01 }, { 24, 0x02 }, { 26, 0x03 },
+ { 28, 0x04 }, { 30, 0x05 }, { 32, 0x09 }, { 34, 0x06 },
+ { 36, 0x0A }, { 40, 0x07 }, { 44, 0x0C }, { 48, 0x0D },
+ { 52, 0x43 }, { 56, 0x0E }, { 60, 0x45 }, { 64, 0x12 },
+ { 68, 0x0F }, { 72, 0x13 }, { 80, 0x14 }, { 88, 0x15 },
+ { 96, 0x19 }, { 104, 0x16 }, { 112, 0x1A }, { 128, 0x17 },
+ { 136, 0x4F }, { 144, 0x1C }, { 160, 0x1D }, { 176, 0x55 },
+ { 192, 0x1E }, { 208, 0x56 }, { 224, 0x22 }, { 228, 0x24 },
+ { 240, 0x1F }, { 256, 0x23 }, { 288, 0x5C }, { 320, 0x25 },
+ { 384, 0x26 }, { 448, 0x2A }, { 480, 0x27 }, { 512, 0x2B },
+ { 576, 0x2C }, { 640, 0x2D }, { 768, 0x31 }, { 896, 0x32 },
+ { 960, 0x2F }, { 1024, 0x33 }, { 1152, 0x34 }, { 1280, 0x35 },
+ { 1536, 0x36 }, { 1792, 0x3A }, { 1920, 0x37 }, { 2048, 0x3B },
+ { 2304, 0x3C }, { 2560, 0x3D }, { 3072, 0x3E }, { 3584, 0x7A },
+ { 3840, 0x3F }, { 4096, 0x7B }, { 5120, 0x7D }, { 6144, 0x7E },
+};
+#else
static u16 i2c_clk_div[50][2] = {
{ 22, 0x20 }, { 24, 0x21 }, { 26, 0x22 }, { 28, 0x23 },
{ 30, 0x00 }, { 32, 0x24 }, { 36, 0x25 }, { 40, 0x26 },
@@ -78,6 +116,7 @@ static u16 i2c_clk_div[50][2] = {
{ 1920, 0x1B }, { 2048, 0x3F }, { 2304, 0x1C }, { 2560, 0x1D },
{ 3072, 0x1E }, { 3840, 0x1F }
};
+#endif
/*
* Calculate and set proper clock divider
@@ -125,7 +164,7 @@ static int bus_i2c_set_bus_speed(void *base, int speed)
writeb(idx, i2c_regs-ifdr);
/* Reset module */
- writeb(0, i2c_regs-i2cr);
+ writeb(I2CR_IDIS, i2c_regs-i2cr);
writeb(0, i2c_regs-i2sr);
return 0;
}
@@ -157,7 +196,11 @@ static int wait_for_sr_state(struct mxc_i2c_regs
*i2c_regs, unsigned state)
for (;;) {
sr = readb(i2c_regs-i2sr);
if (sr I2SR_IAL) {
+#ifdef I2C_QUIRK_REG
+ writeb(sr | I2SR_IAL, i2c_regs-i2sr);
+#else
writeb(sr ~I2SR_IAL, i2c_regs-i2sr);
+#endif
printf(%s: Arbitration lost sr=%x cr=%x state=%x\n,
__func__, sr, readb(i2c_regs-i2cr), state);
return -ERESTART;
@@ -178,7 +221,7 @@ static int tx_byte(struct mxc_i2c_regs *i2c_regs, u8 byte)
{
int ret;
- writeb(0, i2c_regs-i2sr);
+ writeb(I2SR_IIF_CLEAR, i2c_regs-i2sr);
writeb(byte, i2c_regs-i2dr);
ret = wait_for_sr_state(i2c_regs, ST_IIF);
if (ret 0)
@@ -214,14 +257,18 @@ static int i2c_init_transfer_(struct mxc_i2c_regs
*i2c_regs,
int ret;
/* Enable I2C controller */
+#ifdef I2C_QUIRK_REG
+ if (readb(i2c_regs-i2cr) I2CR_IDIS) {
+#else
if (!(readb(i2c_regs-i2cr) I2CR_IEN)) {
+#endif
writeb(I2CR_IEN, i2c_regs-i2cr);
/* Wait for controller to be
[U-Boot] [PATCH 1/2] vf610: Add I2C support for Vybrid VF610 platform
This patch adds I2C support for Vybrid VF610 platform and adds
I2C0 support to VF610TWR board.
Signed-off-by: Alison Wang b18...@freescale.com
---
arch/arm/cpu/armv7/vf610/generic.c| 7 +++
arch/arm/include/asm/arch-vf610/clock.h | 1 +
arch/arm/include/asm/arch-vf610/crm_regs.h| 1 +
arch/arm/include/asm/arch-vf610/imx-regs.h| 1 +
arch/arm/include/asm/arch-vf610/iomux-vf610.h | 4
board/freescale/vf610twr/vf610twr.c | 14 +-
include/configs/vf610twr.h| 7 +++
7 files changed, 34 insertions(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv7/vf610/generic.c
b/arch/arm/cpu/armv7/vf610/generic.c
index 87f2a86..f6ef495 100644
--- a/arch/arm/cpu/armv7/vf610/generic.c
+++ b/arch/arm/cpu/armv7/vf610/generic.c
@@ -204,6 +204,11 @@ u32 get_fec_clk(void)
return freq;
}
+static u32 get_i2c_clk(void)
+{
+ return get_ipg_clk();
+}
+
unsigned int mxc_get_clock(enum mxc_clock clk)
{
switch (clk) {
@@ -219,6 +224,8 @@ unsigned int mxc_get_clock(enum mxc_clock clk)
return get_sdhc_clk();
case MXC_FEC_CLK:
return get_fec_clk();
+ case MXC_I2C_CLK:
+ return get_i2c_clk();
default:
break;
}
diff --git a/arch/arm/include/asm/arch-vf610/clock.h
b/arch/arm/include/asm/arch-vf610/clock.h
index 04e418c..3cbae0b 100644
--- a/arch/arm/include/asm/arch-vf610/clock.h
+++ b/arch/arm/include/asm/arch-vf610/clock.h
@@ -29,6 +29,7 @@ enum mxc_clock {
MXC_UART_CLK,
MXC_ESDHC_CLK,
MXC_FEC_CLK,
+ MXC_I2C_CLK,
};
void enable_ocotp_clk(unsigned char enable);
diff --git a/arch/arm/include/asm/arch-vf610/crm_regs.h
b/arch/arm/include/asm/arch-vf610/crm_regs.h
index e3f703d..6a67eb0 100644
--- a/arch/arm/include/asm/arch-vf610/crm_regs.h
+++ b/arch/arm/include/asm/arch-vf610/crm_regs.h
@@ -190,6 +190,7 @@ struct anadig_reg {
#define CCM_CCGR4_WKUP_CTRL_MASK (0x3 20)
#define CCM_CCGR4_CCM_CTRL_MASK(0x3 22)
#define CCM_CCGR4_GPC_CTRL_MASK(0x3 24)
+#define CCM_CCGR4_I2C0_CTRL_MASK (0x3 12)
#define CCM_CCGR6_OCOTP_CTRL_MASK (0x3 10)
#define CCM_CCGR6_DDRMC_CTRL_MASK (0x3 28)
#define CCM_CCGR7_SDHC1_CTRL_MASK (0x3 4)
diff --git a/arch/arm/include/asm/arch-vf610/imx-regs.h
b/arch/arm/include/asm/arch-vf610/imx-regs.h
index c9df32a..742e20a 100644
--- a/arch/arm/include/asm/arch-vf610/imx-regs.h
+++ b/arch/arm/include/asm/arch-vf610/imx-regs.h
@@ -103,6 +103,7 @@
#define CONFIG_IOMUX_SHARE_CONF_REG
#define FEC_QUIRK_ENET_MAC
+#define I2C_QUIRK_REG
/* MSCM interrupt rounter */
#define MSCM_IRSPRC_CP0_EN 1
diff --git a/arch/arm/include/asm/arch-vf610/iomux-vf610.h
b/arch/arm/include/asm/arch-vf610/iomux-vf610.h
index 1c728fa..7aeadce 100644
--- a/arch/arm/include/asm/arch-vf610/iomux-vf610.h
+++ b/arch/arm/include/asm/arch-vf610/iomux-vf610.h
@@ -30,6 +30,8 @@
#define VF610_ENET_PAD_CTRL(PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_50ohm | \
PAD_CTL_OBE_IBE_ENABLE)
#define VF610_DDR_PAD_CTRL PAD_CTL_DSE_25ohm
+#define VF610_I2C_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_50ohm | \
+ PAD_CTL_SPEED_HIGH | PAD_CTL_OBE_IBE_ENABLE)
enum {
VF610_PAD_PTA6__RMII0_CLKIN = IOMUX_PAD(0x, 0x, 2,
__NA_, 0, VF610_ENET_PAD_CTRL),
@@ -50,6 +52,8 @@ enum {
VF610_PAD_PTA27__ESDHC1_DAT1= IOMUX_PAD(0x0044, 0x0044, 5,
__NA_, 0, VF610_SDHC_PAD_CTRL),
VF610_PAD_PTA28__ESDHC1_DAT2= IOMUX_PAD(0x0048, 0x0048, 5,
__NA_, 0, VF610_SDHC_PAD_CTRL),
VF610_PAD_PTA29__ESDHC1_DAT3= IOMUX_PAD(0x004c, 0x004c, 5,
__NA_, 0, VF610_SDHC_PAD_CTRL),
+ VF610_PAD_PTB14__I2C0_SCL = IOMUX_PAD(0x0090, 0x0090, 2,
0x033c, 1, VF610_I2C_PAD_CTRL),
+ VF610_PAD_PTB15__I2C0_SDA = IOMUX_PAD(0x0094, 0x0094, 2,
0x0340, 1, VF610_I2C_PAD_CTRL),
VF610_PAD_DDR_A15__DDR_A_15 = IOMUX_PAD(0x0220, 0x0220, 0,
__NA_, 0, VF610_DDR_PAD_CTRL),
VF610_PAD_DDR_A14__DDR_A_14 = IOMUX_PAD(0x0224, 0x0224, 0,
__NA_, 0, VF610_DDR_PAD_CTRL),
VF610_PAD_DDR_A13__DDR_A_13 = IOMUX_PAD(0x0228, 0x0228, 0,
__NA_, 0, VF610_DDR_PAD_CTRL),
diff --git a/board/freescale/vf610twr/vf610twr.c
b/board/freescale/vf610twr/vf610twr.c
index f14df8b..391f97e 100644
--- a/board/freescale/vf610twr/vf610twr.c
+++ b/board/freescale/vf610twr/vf610twr.c
@@ -27,6 +27,7 @@
#include fsl_esdhc.h
#include miiphy.h
#include netdev.h
+#include i2c.h
DECLARE_GLOBAL_DATA_PTR;
@@ -280,6 +281,16 @@ static void setup_iomux_enet(void)
imx_iomux_v3_setup_multiple_pads(enet0_pads, ARRAY_SIZE(enet0_pads));
}
+static void setup_iomux_i2c(void)
+{
+ static const iomux_v3_cfg_t i2c0_pads[] =
[U-Boot] [PATCH 0/2] vf610: Add I2C support for Freescale Vybrid VF610 platform
This series contain the I2C support for Freescale Vybrid VF610 platform and VF610TWR board. Alison Wang (2): vf610: Add I2C support for Vybrid VF610 platform I2C: mxc_i2c: Add support for Vybrid VF610 platform arch/arm/cpu/armv7/vf610/generic.c| 7 +++ arch/arm/include/asm/arch-vf610/clock.h | 1 + arch/arm/include/asm/arch-vf610/crm_regs.h| 1 + arch/arm/include/asm/arch-vf610/imx-regs.h| 1 + arch/arm/include/asm/arch-vf610/iomux-vf610.h | 4 board/freescale/vf610twr/vf610twr.c | 14 +- drivers/i2c/mxc_i2c.c | 62 +++--- include/configs/vf610twr.h| 7 +++ 8 files changed, 89 insertions(+), 8 deletions(-) ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] U-boot: Erase/read/write issue with S25fl256S flash device
On Mon, Jun 17, 2013 at 1:11 PM, Sourav Poddar sourav.pod...@ti.com wrote:
Hi Jagan,
On Monday 17 June 2013 01:04 PM, Jagan Teki wrote:
On Mon, Jun 17, 2013 at 12:49 PM, Sourav Poddarsourav.pod...@ti.com
wrote:
On Monday 17 June 2013 12:44 PM, Jagan Teki wrote:
On Mon, Jun 17, 2013 at 12:41 PM, Sourav Poddarsourav.pod...@ti.com
wrote:
On Monday 17 June 2013 12:35 PM, Jagan Teki wrote:
On Mon, Jun 17, 2013 at 12:28 PM, Sourav Poddarsourav.pod...@ti.com
wrote:
HI Jagan,
On Monday 17 June 2013 12:17 PM, Jagan Teki wrote:
Hi Sourav,
On Mon, Jun 17, 2013 at 11:44 AM, Sourav
Poddarsourav.pod...@ti.com
wrote:
Hi Jagan,
On Saturday 15 June 2013 09:47 PM, Jagan Teki wrote:
On 14-06-2013 20:13, Sourav Poddar wrote:
Hi Jagan,
On Friday 14 June 2013 08:08 PM, Jagan Teki wrote:
On 14-06-2013 20:03, Sourav Poddar wrote:
Hi,
On Wednesday 12 June 2013 01:00 PM, Sourav Poddar wrote:
Hi,
I am working on qspi flash device S25FL256S at u-boot level. I
am
trying to
make use of the existing spi_flash.c framework available at
u-boot
for
erasing/reading/writing
into the flash device.
There are several issues(mentioned below), which I faced while
using
S25FL256s flash device
with my dra7xx board which has a qspi controller to which the
above
mentioned flash device is attached.
1. Erase (spi_flash_cmd_erase)
Issuing a command something like this..
sf erase 0x0 0x5
- erases only first 0x2 bytes of flash device,
anything
above
that is not erase. I need to
issue separate commands after 0x2 for every 0x1
bytes.
Am i missing anything here?
2. read
sf read 8100 0 0x1
Read is not happening properly. The last few byte along the 4k
boundary always shows zero.
Above 4k bytes, read is not happening.
For ex:
DRA752 EVM # md 81000f00
81000f00:
81000f10:
81000f20:
81000f30:
81000f40:
81000f50:
81000f60:
81000f70:
81000f80:
81000f90:
81000fa0:
81000fb0:
81000fc0:
81000fd0:
81000fe0:
81000ff0: 00ff
In this dump, if you see 81000ff0 the last column shows 00
which
is
not expected. and it happens along every 4k bytes.
So, to get rid of the above issue, I switched to page read
with
the
below patch[1],
which is giving me the correct result.
[1]:
@@ -147,17 +153,40 @@ int spi_flash_read_common(struct
spi_flash
*flash, const u8 *cmd,
int spi_flash_cmd_read_fast(struct spi_flash *flash, u32
offset,
size_t len, void *data)
{
- u8 cmd[5];
+ unsigned long page_addr, byte_addr, page_size;
+ size_t chunk_len, actual;
+ int ret = 0;
+ u8 cmd[4];
/* Handle memory-mapped SPI */
if (flash-memory_map)
memcpy(data, flash-memory_map + offset,
len);
+ page_size = flash-page_size;
+ page_addr = offset / page_size;
+ byte_addr = offset % page_size;
+
+ cmd[0] = CMD_READ_ARRAY_SLOW;
+ for (actual = 0; actual len; actual += chunk_len)
{
+ chunk_len = min(len - actual, page_size -
byte_addr);
+
+ cmd[1] = page_addr 8;
+ cmd[2] = page_addr;
+ cmd[3] = byte_addr;
+
+ ret = spi_flash_read_common(flash, cmd,
sizeof(cmd),
data + actual, chunk_len);
+ if (ret 0) {
+ debug(SF: read failed);
+ break;
+ }
- cmd[0] = CMD_READ_ARRAY_FAST;
- spi_flash_addr(offset, cmd);
- cmd[4] = 0x00;
+ byte_addr += chunk_len;
+ if (byte_addr == page_size) {
+ page_addr++;
+ byte_addr = 0;
+ }
+ }
- return spi_flash_read_common(flash, cmd, sizeof(cmd),
data,
len);
+ return ret;
}
Any idea about this?
3. write (spi_flash_cmd_write_multi)
write not happening properly.
observations: only able to write single page, anything after a
page
is
not getting
written.
Workaround:
I did a write disable latch at the end of
Re: [U-Boot] U-boot: Erase/read/write issue with S25fl256S flash device
On Monday 17 June 2013 02:09 PM, Jagan Teki wrote:
On Mon, Jun 17, 2013 at 1:11 PM, Sourav Poddarsourav.pod...@ti.com wrote:
Hi Jagan,
On Monday 17 June 2013 01:04 PM, Jagan Teki wrote:
On Mon, Jun 17, 2013 at 12:49 PM, Sourav Poddarsourav.pod...@ti.com
wrote:
On Monday 17 June 2013 12:44 PM, Jagan Teki wrote:
On Mon, Jun 17, 2013 at 12:41 PM, Sourav Poddarsourav.pod...@ti.com
wrote:
On Monday 17 June 2013 12:35 PM, Jagan Teki wrote:
On Mon, Jun 17, 2013 at 12:28 PM, Sourav Poddarsourav.pod...@ti.com
wrote:
HI Jagan,
On Monday 17 June 2013 12:17 PM, Jagan Teki wrote:
Hi Sourav,
On Mon, Jun 17, 2013 at 11:44 AM, Sourav
Poddarsourav.pod...@ti.com
wrote:
Hi Jagan,
On Saturday 15 June 2013 09:47 PM, Jagan Teki wrote:
On 14-06-2013 20:13, Sourav Poddar wrote:
Hi Jagan,
On Friday 14 June 2013 08:08 PM, Jagan Teki wrote:
On 14-06-2013 20:03, Sourav Poddar wrote:
Hi,
On Wednesday 12 June 2013 01:00 PM, Sourav Poddar wrote:
Hi,
I am working on qspi flash device S25FL256S at u-boot level. I
am
trying to
make use of the existing spi_flash.c framework available at
u-boot
for
erasing/reading/writing
into the flash device.
There are several issues(mentioned below), which I faced while
using
S25FL256s flash device
with my dra7xx board which has a qspi controller to which the
above
mentioned flash device is attached.
1. Erase (spi_flash_cmd_erase)
Issuing a command something like this..
sf erase 0x0 0x5
- erases only first 0x2 bytes of flash device,
anything
above
that is not erase. I need to
issue separate commands after 0x2 for every 0x1
bytes.
Am i missing anything here?
2. read
sf read 8100 0 0x1
Read is not happening properly. The last few byte along the 4k
boundary always shows zero.
Above 4k bytes, read is not happening.
For ex:
DRA752 EVM # md 81000f00
81000f00:
81000f10:
81000f20:
81000f30:
81000f40:
81000f50:
81000f60:
81000f70:
81000f80:
81000f90:
81000fa0:
81000fb0:
81000fc0:
81000fd0:
81000fe0:
81000ff0: 00ff
In this dump, if you see 81000ff0 the last column shows 00
which
is
not expected. and it happens along every 4k bytes.
So, to get rid of the above issue, I switched to page read
with
the
below patch[1],
which is giving me the correct result.
[1]:
@@ -147,17 +153,40 @@ int spi_flash_read_common(struct
spi_flash
*flash, const u8 *cmd,
int spi_flash_cmd_read_fast(struct spi_flash *flash, u32
offset,
size_t len, void *data)
{
- u8 cmd[5];
+ unsigned long page_addr, byte_addr, page_size;
+ size_t chunk_len, actual;
+ int ret = 0;
+ u8 cmd[4];
/* Handle memory-mapped SPI */
if (flash-memory_map)
memcpy(data, flash-memory_map + offset,
len);
+ page_size = flash-page_size;
+ page_addr = offset / page_size;
+ byte_addr = offset % page_size;
+
+ cmd[0] = CMD_READ_ARRAY_SLOW;
+ for (actual = 0; actual len; actual += chunk_len)
{
+ chunk_len = min(len - actual, page_size -
byte_addr);
+
+ cmd[1] = page_addr 8;
+ cmd[2] = page_addr;
+ cmd[3] = byte_addr;
+
+ ret = spi_flash_read_common(flash, cmd,
sizeof(cmd),
data + actual, chunk_len);
+ if (ret 0) {
+ debug(SF: read failed);
+ break;
+ }
- cmd[0] = CMD_READ_ARRAY_FAST;
- spi_flash_addr(offset, cmd);
- cmd[4] = 0x00;
+ byte_addr += chunk_len;
+ if (byte_addr == page_size) {
+ page_addr++;
+ byte_addr = 0;
+ }
+ }
- return spi_flash_read_common(flash, cmd, sizeof(cmd),
data,
len);
+ return ret;
}
Any idea about this?
3. write (spi_flash_cmd_write_multi)
write not happening properly.
observations: only able to write single page, anything after a
page
is
not getting
written.
Workaround:
I did a write disable latch at the end of every write
cycle(page
program) and enable it
again for the next loop. With this, I see I
[U-Boot] [PATCH v3 1/3] ARM: Tegra: FDT: Add USB EHCI function for T30/T114
Add DT node for USB EHCI function.
Add support for T30-Cardhu, T30-Beaver, T114-Dalmore boards.
Signed-off-by: Jim Lin ji...@nvidia.com
---
Changes in v2:
- Remove PLL parameters from dt file
Changes in v3:
- Change VBus GPIO from H.05 to DD.04 for Beaver board.
I don't have Beaver board. So this needs somebody to help test.
Thanks.
arch/arm/dts/tegra114.dtsi| 27 +++
arch/arm/dts/tegra30.dtsi | 27 +++
board/nvidia/dts/tegra114-dalmore.dts |7 +++
board/nvidia/dts/tegra30-beaver.dts |6 ++
board/nvidia/dts/tegra30-cardhu.dts |6 ++
include/fdtdec.h |2 ++
lib/fdtdec.c |2 ++
7 files changed, 77 insertions(+), 0 deletions(-)
diff --git a/arch/arm/dts/tegra114.dtsi b/arch/arm/dts/tegra114.dtsi
index f86d18d..f87d05a 100644
--- a/arch/arm/dts/tegra114.dtsi
+++ b/arch/arm/dts/tegra114.dtsi
@@ -216,4 +216,31 @@
clocks = tegra_car 15;
status = disable;
};
+
+ usb@7d00 {
+ compatible = nvidia,tegra114-ehci;
+ reg = 0x7d00 0x4000;
+ interrupts = 52;
+ phy_type = utmi;
+ clocks = tegra_car 22; /* PERIPH_ID_USBD */
+ status = disabled;
+ };
+
+ usb@7d004000 {
+ compatible = nvidia,tegra114-ehci;
+ reg = 0x7d004000 0x4000;
+ interrupts = 53;
+ phy_type = utmi;
+ clocks = tegra_car 58; /* PERIPH_ID_USB2 */
+ status = disabled;
+ };
+
+ usb@7d008000 {
+ compatible = nvidia,tegra114-ehci;
+ reg = 0x7d008000 0x4000;
+ interrupts = 129;
+ phy_type = utmi;
+ clocks = tegra_car 59; /* PERIPH_ID_USB3 */
+ status = disabled;
+ };
};
diff --git a/arch/arm/dts/tegra30.dtsi b/arch/arm/dts/tegra30.dtsi
index ccf154f..e5275c2 100644
--- a/arch/arm/dts/tegra30.dtsi
+++ b/arch/arm/dts/tegra30.dtsi
@@ -216,4 +216,31 @@
clocks = tegra_car 15;
status = disabled;
};
+
+ usb@7d00 {
+ compatible = nvidia,tegra30-ehci;
+ reg = 0x7d00 0x4000;
+ interrupts = 52;
+ phy_type = utmi;
+ clocks = tegra_car 22; /* PERIPH_ID_USBD */
+ status = disabled;
+ };
+
+ usb@7d004000 {
+ compatible = nvidia,tegra30-ehci;
+ reg = 0x7d004000 0x4000;
+ interrupts = 53;
+ phy_type = utmi;
+ clocks = tegra_car 58; /* PERIPH_ID_USB2 */
+ status = disabled;
+ };
+
+ usb@7d008000 {
+ compatible = nvidia,tegra30-ehci;
+ reg = 0x7d008000 0x4000;
+ interrupts = 129;
+ phy_type = utmi;
+ clocks = tegra_car 59; /* PERIPH_ID_USB3 */
+ status = disabled;
+ };
};
diff --git a/board/nvidia/dts/tegra114-dalmore.dts
b/board/nvidia/dts/tegra114-dalmore.dts
index 86e9459..435c01e 100644
--- a/board/nvidia/dts/tegra114-dalmore.dts
+++ b/board/nvidia/dts/tegra114-dalmore.dts
@@ -14,6 +14,7 @@
i2c4 = /i2c@7000c700;
sdhci0 = /sdhci@78000600;
sdhci1 = /sdhci@78000400;
+ usb0 = /usb@7d008000;
};
memory {
@@ -61,4 +62,10 @@
bus-width = 8;
status = okay;
};
+
+ usb@7d008000 {
+ /* SPDIF_IN: USB_VBUS_EN1 */
+ nvidia,vbus-gpio = gpio 86 0;
+ status = okay;
+ };
};
diff --git a/board/nvidia/dts/tegra30-beaver.dts
b/board/nvidia/dts/tegra30-beaver.dts
index 836169f..a7cc93e 100644
--- a/board/nvidia/dts/tegra30-beaver.dts
+++ b/board/nvidia/dts/tegra30-beaver.dts
@@ -14,6 +14,7 @@
i2c4 = /i2c@7000c700;
sdhci0 = /sdhci@78000600;
sdhci1 = /sdhci@7800;
+ usb0 = /usb@7d008000;
};
memory {
@@ -68,4 +69,9 @@
status = okay;
bus-width = 8;
};
+
+ usb@7d008000 {
+ nvidia,vbus-gpio = gpio 236 0; /* PDD4 */
+ status = okay;
+ };
};
diff --git a/board/nvidia/dts/tegra30-cardhu.dts
b/board/nvidia/dts/tegra30-cardhu.dts
index 4d22b48..071a464 100644
--- a/board/nvidia/dts/tegra30-cardhu.dts
+++ b/board/nvidia/dts/tegra30-cardhu.dts
@@ -14,6 +14,7 @@
i2c4 = /i2c@7000c700;
sdhci0 = /sdhci@78000600;
sdhci1 = /sdhci@7800;
+ usb0 = /usb@7d008000;
};
memory {
@@ -63,4 +64,9 @@
status = okay;
bus-width = 8;
};
+
+ usb@7d008000 {
+ nvidia,vbus-gpio = gpio 233 3;
[U-Boot] [PATCH v3 2/3] ARM: Tegra: USB: EHCI: Add support for Tegra30/Tegra114
Tegra30 and Tegra114 are compatible except PLL parameters.
Tested on Tegra30 Cardhu, and Tegra114 Dalmore
platforms. All works well.
Signed-off-by: Jim Lin ji...@nvidia.com
---
Changes in v2:
- Move common definitions into arch-tegra/usb.h and
chip specific definitions into arch-tegraXX(X)/usb.h
- In ehci-tegra.c, add PLL parameters for Tegra30 and Tegra114.
- In ehci-tegra.c, use the port pointed by nvidia,has-legacy-mode
to know whether we do special handling on Port Reset.
- Remove some irrelevant whitespace changes.
- Use if-else, instead of goto in ehci-tegra.c
init_utmi_usb_controller().
- Use original coding for PTS_MASK in ehci-tegra.c
init_utmi_usb_controller().
Reason is that these bits are read-only on Tegra20.
Don't need special handling between USB1 and USB3 ports.
- Use if-else, instead of goto in ehci-tegra.c board_usb_init().
Changes in v3:
None
arch/arm/include/asm/arch-tegra/clk_rst.h | 10 +
arch/arm/include/asm/arch-tegra/usb.h | 182 --
arch/arm/include/asm/arch-tegra114/usb.h | 156 +++
arch/arm/include/asm/arch-tegra20/usb.h | 155 +++
arch/arm/include/asm/arch-tegra30/usb.h | 168
board/nvidia/common/board.c |2 +-
drivers/usb/host/ehci-tegra.c | 297 +
7 files changed, 796 insertions(+), 174 deletions(-)
create mode 100644 arch/arm/include/asm/arch-tegra114/usb.h
create mode 100644 arch/arm/include/asm/arch-tegra20/usb.h
create mode 100644 arch/arm/include/asm/arch-tegra30/usb.h
diff --git a/arch/arm/include/asm/arch-tegra/clk_rst.h
b/arch/arm/include/asm/arch-tegra/clk_rst.h
index c754ec7..9b8de9c 100644
--- a/arch/arm/include/asm/arch-tegra/clk_rst.h
+++ b/arch/arm/include/asm/arch-tegra/clk_rst.h
@@ -225,6 +225,16 @@ enum {
IN_408_OUT_9_6_DIVISOR = 83,
};
+/* CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0 */
+#define PLLU_POWERDOWN (1 16)
+#define PLL_ENABLE_POWERDOWN (1 14)
+#define PLL_ACTIVE_POWERDOWN (1 12)
+
+/* CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0 */
+#define UTMIP_FORCE_PD_SAMP_C_POWERDOWN(1 4)
+#define UTMIP_FORCE_PD_SAMP_B_POWERDOWN(1 2)
+#define UTMIP_FORCE_PD_SAMP_A_POWERDOWN(1 0)
+
/* CLK_RST_CONTROLLER_OSC_CTRL_0 */
#define OSC_XOBP_SHIFT 1
#define OSC_XOBP_MASK (1U OSC_XOBP_SHIFT)
diff --git a/arch/arm/include/asm/arch-tegra/usb.h
b/arch/arm/include/asm/arch-tegra/usb.h
index ef6c089..cefe0d2 100644
--- a/arch/arm/include/asm/arch-tegra/usb.h
+++ b/arch/arm/include/asm/arch-tegra/usb.h
@@ -1,5 +1,6 @@
/*
* Copyright (c) 2011 The Chromium OS Authors.
+ * Copyright (c) 2013 NVIDIA Corporation
* See file CREDITS for list of people who contributed to this
* project.
*
@@ -22,120 +23,6 @@
#ifndef _TEGRA_USB_H_
#define _TEGRA_USB_H_
-
-/* USB Controller (USBx_CONTROLLER_) regs */
-struct usb_ctlr {
- /* 0x000 */
- uint id;
- uint reserved0;
- uint host;
- uint device;
-
- /* 0x010 */
- uint txbuf;
- uint rxbuf;
- uint reserved1[2];
-
- /* 0x020 */
- uint reserved2[56];
-
- /* 0x100 */
- u16 cap_length;
- u16 hci_version;
- uint hcs_params;
- uint hcc_params;
- uint reserved3[5];
-
- /* 0x120 */
- uint dci_version;
- uint dcc_params;
- uint reserved4[6];
-
- /* 0x140 */
- uint usb_cmd;
- uint usb_sts;
- uint usb_intr;
- uint frindex;
-
- /* 0x150 */
- uint reserved5;
- uint periodic_list_base;
- uint async_list_addr;
- uint async_tt_sts;
-
- /* 0x160 */
- uint burst_size;
- uint tx_fill_tuning;
- uint reserved6; /* is this port_sc1 on some controllers? */
- uint icusb_ctrl;
-
- /* 0x170 */
- uint ulpi_viewport;
- uint reserved7;
- uint endpt_nak;
- uint endpt_nak_enable;
-
- /* 0x180 */
- uint reserved;
- uint port_sc1;
- uint reserved8[6];
-
- /* 0x1a0 */
- uint reserved9;
- uint otgsc;
- uint usb_mode;
- uint endpt_setup_stat;
-
- /* 0x1b0 */
- uint reserved10[20];
-
- /* 0x200 */
- uint reserved11[0x80];
-
- /* 0x400 */
- uint susp_ctrl;
- uint phy_vbus_sensors;
- uint phy_vbus_wakeup_id;
- uint phy_alt_vbus_sys;
-
- /* 0x410 */
- uint usb1_legacy_ctrl;
- uint reserved12[4];
-
- /* 0x424 */
- uint ulpi_timing_ctrl_0;
- uint ulpi_timing_ctrl_1;
- uint reserved13[53];
-
- /* 0x500 */
- uint reserved14[64 * 3];
-
- /* 0x800 */
- uint utmip_pll_cfg0;
- uint utmip_pll_cfg1;
- uint utmip_xcvr_cfg0;
- uint utmip_bias_cfg0;
-
- /* 0x810 */
- uint utmip_hsrx_cfg0;
- uint utmip_hsrx_cfg1;
- uint utmip_fslsrx_cfg0;
- uint utmip_fslsrx_cfg1;
-
- /*
[U-Boot] [PATCH v3 3/3] Tegra: Config: Enable Tegra30/Tegra114 USB function
Add USB EHCI, storage and network support. Tested on Tegra30 Cardhu, and Tegra114 Dalmore platforms. All works well. Signed-off-by: Jim Lin ji...@nvidia.com --- Changes in v2: - Add support for Beaver board. Changes in v3: - None include/configs/beaver.h | 14 ++ include/configs/cardhu.h | 14 ++ include/configs/dalmore.h | 14 ++ include/configs/tegra114-common.h |3 +++ include/configs/tegra30-common.h |3 +++ 5 files changed, 48 insertions(+), 0 deletions(-) diff --git a/include/configs/beaver.h b/include/configs/beaver.h index 058da4f..165de13 100644 --- a/include/configs/beaver.h +++ b/include/configs/beaver.h @@ -71,6 +71,20 @@ #define CONFIG_CMD_SF #define CONFIG_SPI_FLASH_SIZE (4 20) +/* USB Host support */ +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_TEGRA +#define CONFIG_USB_STORAGE +#define CONFIG_CMD_USB + +/* USB networking support */ +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX + +/* General networking support */ +#define CONFIG_CMD_NET +#define CONFIG_CMD_DHCP + #include tegra-common-post.h #endif /* __CONFIG_H */ diff --git a/include/configs/cardhu.h b/include/configs/cardhu.h index 6a99175..fd46083 100644 --- a/include/configs/cardhu.h +++ b/include/configs/cardhu.h @@ -70,6 +70,20 @@ #define CONFIG_CMD_SF #define CONFIG_SPI_FLASH_SIZE (4 20) +/* USB Host support */ +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_TEGRA +#define CONFIG_USB_STORAGE +#define CONFIG_CMD_USB + +/* USB networking support */ +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX + +/* General networking support */ +#define CONFIG_CMD_NET +#define CONFIG_CMD_DHCP + #include tegra-common-post.h #endif /* __CONFIG_H */ diff --git a/include/configs/dalmore.h b/include/configs/dalmore.h index 7b68f7c..2723843 100644 --- a/include/configs/dalmore.h +++ b/include/configs/dalmore.h @@ -75,6 +75,20 @@ #define CONFIG_CMD_SF #define CONFIG_SPI_FLASH_SIZE (4 20) +/* USB Host support */ +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_TEGRA +#define CONFIG_USB_STORAGE +#define CONFIG_CMD_USB + +/* USB networking support */ +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX + +/* General networking support */ +#define CONFIG_CMD_NET +#define CONFIG_CMD_DHCP + #include tegra-common-post.h #endif /* __CONFIG_H */ diff --git a/include/configs/tegra114-common.h b/include/configs/tegra114-common.h index 721b29c..44e98e5 100644 --- a/include/configs/tegra114-common.h +++ b/include/configs/tegra114-common.h @@ -77,4 +77,7 @@ /* Total I2C ports on Tegra114 */ #define TEGRA_I2C_NUM_CONTROLLERS 5 +/* For USB EHCI controller */ +#define CONFIG_EHCI_IS_TDI + #endif /* _TEGRA114_COMMON_H_ */ diff --git a/include/configs/tegra30-common.h b/include/configs/tegra30-common.h index ed36e11..7ea36be 100644 --- a/include/configs/tegra30-common.h +++ b/include/configs/tegra30-common.h @@ -90,4 +90,7 @@ /* Total I2C ports on Tegra30 */ #define TEGRA_I2C_NUM_CONTROLLERS 5 +/* For USB EHCI controller */ +#define CONFIG_EHCI_IS_TDI + #endif /* _TEGRA30_COMMON_H_ */ -- 1.7.7 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [RFC] Safe Linux Updater
Hi, One month ago, I sent a first request for comments about an open source automatic updater for embedded systems using U-boot: the goal of this project was to split a flash memory or hard disk drive in multiple partition (2 or more) and install a new kernel and/or root filesystem on an empty or outdated partition. After reboot, we count the boot attempts on this new version of the system and if it fails to boot, we switch back to the last working partition. This guarantees we will eventually boot on a correct partition and that there is no chance to have an unsupervised equipment hang at the u-boot prompt. The u-boot environment would contain some variables to handle name, state and boot attempt count of each partition of the system. I would use CONFIG_ENV_OFFSET_REDUND to make writing on environment powerfail-safe. The environment contains 3 variables by partitions: - part_X_flag: handles state of partition X. It can be NONE for empty partition, OK for working system, LOCK for locking a partition to install a new system on it, UPDATED for new system version (we count boot attempts for this partition) and BAD for bad system which doesn't work. - part_X_count: handles boot attempts on partition X. - part_X_cmd: U-boot command used to boot on the partition X (e.g. partition address in flash). Environment contains also another variable: boot_seq which handles a list of bootable partition sorted by version. As suggested in previous emails, I have written two scripts to implement that: - An u-boot script to interpret all environment variables and boot on correct partition and count boot attempts when system boots on a new version. - A Linux script to change environment variables when an update is installed. The U-boot script reads boot_seq and boots on first partition of the list. If this partition is flagged OK, system boot normally. If the partition is flagged UPDATED, system try to boot on it and count boot attempts until attempts limit is reached. Then, the script will boot on next partition into boot list, always in counting boot attempts. This operation continue while partitions are available in the list. Partition flagged with NONE, LOCK or BAD are skipped. The Linux script has all commands necessary to automatically find and lock the best partition to install an update, to mark the locked partition as UPDATED and commands to mark a new version as good with OK or bad with BAD. This script uses fw_printenv and fw_setenv from U-boot tools. I would like your comments/suggestions on this system to improve it and to make sure this goes well into the general philosophy of U-Boot. Moreover, if it is possible, to upstream these scripts. Best regards, Alexandre Dilly ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] U-boot: Erase/read/write issue with S25fl256S flash device
On Mon, Jun 17, 2013 at 2:15 PM, Sourav Poddar sourav.pod...@ti.com wrote:
On Monday 17 June 2013 02:09 PM, Jagan Teki wrote:
On Mon, Jun 17, 2013 at 1:11 PM, Sourav Poddarsourav.pod...@ti.com
wrote:
Hi Jagan,
On Monday 17 June 2013 01:04 PM, Jagan Teki wrote:
On Mon, Jun 17, 2013 at 12:49 PM, Sourav Poddarsourav.pod...@ti.com
wrote:
On Monday 17 June 2013 12:44 PM, Jagan Teki wrote:
On Mon, Jun 17, 2013 at 12:41 PM, Sourav Poddarsourav.pod...@ti.com
wrote:
On Monday 17 June 2013 12:35 PM, Jagan Teki wrote:
On Mon, Jun 17, 2013 at 12:28 PM, Sourav
Poddarsourav.pod...@ti.com
wrote:
HI Jagan,
On Monday 17 June 2013 12:17 PM, Jagan Teki wrote:
Hi Sourav,
On Mon, Jun 17, 2013 at 11:44 AM, Sourav
Poddarsourav.pod...@ti.com
wrote:
Hi Jagan,
On Saturday 15 June 2013 09:47 PM, Jagan Teki wrote:
On 14-06-2013 20:13, Sourav Poddar wrote:
Hi Jagan,
On Friday 14 June 2013 08:08 PM, Jagan Teki wrote:
On 14-06-2013 20:03, Sourav Poddar wrote:
Hi,
On Wednesday 12 June 2013 01:00 PM, Sourav Poddar wrote:
Hi,
I am working on qspi flash device S25FL256S at u-boot level.
I
am
trying to
make use of the existing spi_flash.c framework available at
u-boot
for
erasing/reading/writing
into the flash device.
There are several issues(mentioned below), which I faced
while
using
S25FL256s flash device
with my dra7xx board which has a qspi controller to which
the
above
mentioned flash device is attached.
1. Erase (spi_flash_cmd_erase)
Issuing a command something like this..
sf erase 0x0 0x5
- erases only first 0x2 bytes of flash device,
anything
above
that is not erase. I need to
issue separate commands after 0x2 for every
0x1
bytes.
Am i missing anything here?
2. read
sf read 8100 0 0x1
Read is not happening properly. The last few byte along the
4k
boundary always shows zero.
Above 4k bytes, read is not happening.
For ex:
DRA752 EVM # md 81000f00
81000f00:
81000f10:
81000f20:
81000f30:
81000f40:
81000f50:
81000f60:
81000f70:
81000f80:
81000f90:
81000fa0:
81000fb0:
81000fc0:
81000fd0:
81000fe0:
81000ff0: 00ff
In this dump, if you see 81000ff0 the last column shows
00
which
is
not expected. and it happens along every 4k bytes.
So, to get rid of the above issue, I switched to page read
with
the
below patch[1],
which is giving me the correct result.
[1]:
@@ -147,17 +153,40 @@ int spi_flash_read_common(struct
spi_flash
*flash, const u8 *cmd,
int spi_flash_cmd_read_fast(struct spi_flash *flash,
u32
offset,
size_t len, void *data)
{
- u8 cmd[5];
+ unsigned long page_addr, byte_addr, page_size;
+ size_t chunk_len, actual;
+ int ret = 0;
+ u8 cmd[4];
/* Handle memory-mapped SPI */
if (flash-memory_map)
memcpy(data, flash-memory_map +
offset,
len);
+ page_size = flash-page_size;
+ page_addr = offset / page_size;
+ byte_addr = offset % page_size;
+
+ cmd[0] = CMD_READ_ARRAY_SLOW;
+ for (actual = 0; actual len; actual +=
chunk_len)
{
+ chunk_len = min(len - actual, page_size -
byte_addr);
+
+ cmd[1] = page_addr 8;
+ cmd[2] = page_addr;
+ cmd[3] = byte_addr;
+
+ ret = spi_flash_read_common(flash, cmd,
sizeof(cmd),
data + actual, chunk_len);
+ if (ret 0) {
+ debug(SF: read failed);
+ break;
+ }
- cmd[0] = CMD_READ_ARRAY_FAST;
- spi_flash_addr(offset, cmd);
- cmd[4] = 0x00;
+ byte_addr += chunk_len;
+ if (byte_addr == page_size) {
+ page_addr++;
+ byte_addr = 0;
+ }
+ }
- return spi_flash_read_common(flash, cmd,
sizeof(cmd),
data,
len);
+ return ret;
}
Any idea about this?
3. write (spi_flash_cmd_write_multi)
write not happening properly.
Re: [U-Boot] U-boot: Erase/read/write issue with S25fl256S flash device
On Monday 17 June 2013 03:28 PM, Jagan Teki wrote:
On Mon, Jun 17, 2013 at 2:15 PM, Sourav Poddarsourav.pod...@ti.com wrote:
On Monday 17 June 2013 02:09 PM, Jagan Teki wrote:
On Mon, Jun 17, 2013 at 1:11 PM, Sourav Poddarsourav.pod...@ti.com
wrote:
Hi Jagan,
On Monday 17 June 2013 01:04 PM, Jagan Teki wrote:
On Mon, Jun 17, 2013 at 12:49 PM, Sourav Poddarsourav.pod...@ti.com
wrote:
On Monday 17 June 2013 12:44 PM, Jagan Teki wrote:
On Mon, Jun 17, 2013 at 12:41 PM, Sourav Poddarsourav.pod...@ti.com
wrote:
On Monday 17 June 2013 12:35 PM, Jagan Teki wrote:
On Mon, Jun 17, 2013 at 12:28 PM, Sourav
Poddarsourav.pod...@ti.com
wrote:
HI Jagan,
On Monday 17 June 2013 12:17 PM, Jagan Teki wrote:
Hi Sourav,
On Mon, Jun 17, 2013 at 11:44 AM, Sourav
Poddarsourav.pod...@ti.com
wrote:
Hi Jagan,
On Saturday 15 June 2013 09:47 PM, Jagan Teki wrote:
On 14-06-2013 20:13, Sourav Poddar wrote:
Hi Jagan,
On Friday 14 June 2013 08:08 PM, Jagan Teki wrote:
On 14-06-2013 20:03, Sourav Poddar wrote:
Hi,
On Wednesday 12 June 2013 01:00 PM, Sourav Poddar wrote:
Hi,
I am working on qspi flash device S25FL256S at u-boot level.
I
am
trying to
make use of the existing spi_flash.c framework available at
u-boot
for
erasing/reading/writing
into the flash device.
There are several issues(mentioned below), which I faced
while
using
S25FL256s flash device
with my dra7xx board which has a qspi controller to which
the
above
mentioned flash device is attached.
1. Erase (spi_flash_cmd_erase)
Issuing a command something like this..
sf erase 0x0 0x5
- erases only first 0x2 bytes of flash device,
anything
above
that is not erase. I need to
issue separate commands after 0x2 for every
0x1
bytes.
Am i missing anything here?
2. read
sf read 8100 0 0x1
Read is not happening properly. The last few byte along the
4k
boundary always shows zero.
Above 4k bytes, read is not happening.
For ex:
DRA752 EVM # md 81000f00
81000f00:
81000f10:
81000f20:
81000f30:
81000f40:
81000f50:
81000f60:
81000f70:
81000f80:
81000f90:
81000fa0:
81000fb0:
81000fc0:
81000fd0:
81000fe0:
81000ff0: 00ff
In this dump, if you see 81000ff0 the last column shows
00
which
is
not expected. and it happens along every 4k bytes.
So, to get rid of the above issue, I switched to page read
with
the
below patch[1],
which is giving me the correct result.
[1]:
@@ -147,17 +153,40 @@ int spi_flash_read_common(struct
spi_flash
*flash, const u8 *cmd,
int spi_flash_cmd_read_fast(struct spi_flash *flash,
u32
offset,
size_t len, void *data)
{
- u8 cmd[5];
+ unsigned long page_addr, byte_addr, page_size;
+ size_t chunk_len, actual;
+ int ret = 0;
+ u8 cmd[4];
/* Handle memory-mapped SPI */
if (flash-memory_map)
memcpy(data, flash-memory_map +
offset,
len);
+ page_size = flash-page_size;
+ page_addr = offset / page_size;
+ byte_addr = offset % page_size;
+
+ cmd[0] = CMD_READ_ARRAY_SLOW;
+ for (actual = 0; actual len; actual +=
chunk_len)
{
+ chunk_len = min(len - actual, page_size -
byte_addr);
+
+ cmd[1] = page_addr 8;
+ cmd[2] = page_addr;
+ cmd[3] = byte_addr;
+
+ ret = spi_flash_read_common(flash, cmd,
sizeof(cmd),
data + actual, chunk_len);
+ if (ret 0) {
+ debug(SF: read failed);
+ break;
+ }
- cmd[0] = CMD_READ_ARRAY_FAST;
- spi_flash_addr(offset, cmd);
- cmd[4] = 0x00;
+ byte_addr += chunk_len;
+ if (byte_addr == page_size) {
+ page_addr++;
+ byte_addr = 0;
+ }
+ }
- return spi_flash_read_common(flash, cmd,
sizeof(cmd),
data,
len);
+ return ret;
}
Any idea about this?
3. write (spi_flash_cmd_write_multi)
write not happening properly.
observations: only able to write single page, anything after
a
page
is
not getting
written.
Re: [U-Boot] [PATCH v2 1/3] ARM: Tegra: FDT: Add USB EHCI function for T30/T114
On Sun, Jun 16, 2013 at 10:48:45PM +0200, Marek Vasut wrote:
Dear Thierry Reding,
On Sat, Jun 15, 2013 at 11:28:25PM +0200, Marek Vasut wrote:
Dear Thierry Reding,
On Fri, Jun 14, 2013 at 06:41:40PM +0800, Jim Lin wrote:
[...]
diff --git a/board/nvidia/dts/tegra30-beaver.dts
b/board/nvidia/dts/tegra30-beaver.dts
[...]
@@ -68,4 +69,9 @@
status = okay;
bus-width = 8;
};
+
+ usb@7d008000 {
+ nvidia,vbus-gpio = gpio 61 3; /* PH5,
USB13_VBUS_PULLUP */
This doesn't work for me on Beaver. I need to turn the above line into
this:
nvidia,vbus-gpio = gpio 236 0; /* PDD4 */
PDD4 is the correct GPIO according to the schematics and the pin is
high-active. Also as far as I can tell, 3 is not a meaningful value for
the U-Boot GPIO bindings. Only the value 1 (low-active) is used.
With that change applied on top of your patches I can see that a USB
flash drive connected to USB3 is indeed powered. However I noticed
something strange. When I try to use USB, I get this:
Tegra30 (Beaver) # usb start
(Re)start USB...
USB0: set_host_mode: GPIO 236 high
USB EHCI 1.00
scanning bus 0 for devices... 1 USB Device(s) found
scanning usb for storage devices... 0 Storage Device(s)
found
scanning usb for ethernet devices... 0 Ethernet
Device(s) found
So no storage device is detected, even though a USB flash drive is
connected and powered properly. If I repeat the same command, however,
the storage device is detected:
Tegra30 (Beaver) # usb reset
(Re)start USB...
USB0: set_host_mode: GPIO 236 high
USB EHCI 1.00
scanning bus 0 for devices... 2 USB Device(s) found
scanning usb for storage devices... 1 Storage Device(s)
found
scanning usb for ethernet devices... 0 Ethernet
Device(s) found
Any idea what might be going on here?
Try waiting a little after setting the GPIO maybe? The drive might need
some time to settle.
I can make it work on the first invocation of usb start by adding a
rather long mdelay() at the very end of ehci_hcd_init() in the Tegra
EHCI driver. The magic value seems to be 853 ms. 852 ms wasn't enough
in any of the test runs. 853 ms always worked.
However 850+ ms seems like a very long time for the device to settle,
and keeping it in the driver probably isn't a good idea. Furthermore I
cannot reproduce the same issue with a newer flash drive, which works
fine with no additional delays.
Try reverting 020bbcb usb: hub: Power-cycle on root-hub ports ... there's a
thread in the ML that it caused issues.
I reverted the following two patches:
0bf796f usb: hub: Parallelize power-cycling of root-hub ports
020bbcb usb: hub: Power-cycle on root-hub ports
because it wasn't trivial to revert only 020bbcb alone. However it
didn't change anything regarding the problem I was seeing.
Thierry
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Re: [U-Boot] [PATCH v2 1/3] ARM: Tegra: FDT: Add USB EHCI function for T30/T114
On Sat, Jun 15, 2013 at 09:46:19PM +0200, Marek Vasut wrote: Dear Jim Lin, Add DT node for USB EHCI function. Add support for T30-Cardhu, T30-Beaver, T114-Dalmore boards. I'd like to get ACK from someone with the actual hardware. btw. How usable is the cardhu with current U-Boot ? That's the ASUS TF700, right? How can I install U-Boot on it, is there any howto? I don't think Cardhu and TF700 are the same hardware. I'm not familiar with the TF700, but if you have access to the recovery mode you should be able to put mainline U-Boot on it using documentation found here: ftp://download.nvidia.com/tegra-public-appnotes/index.html There's also a pretty new tool to perform almost all of the required steps automatically: https://github.com/NVIDIA/tegra-uboot-flasher-scripts You should follow the instructions in the README-developer.txt to get started. But given that the hardware might not be the same as Cardhu, I'm not sure you can actually run mainline U-Boot on it. I don't suppose the schematics for the TF700 are available anywhere? =) Thierry pgp9F86fx8qFn.pgp Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] spi: Use DIV_ROUND_UP at appropriate places
On 14/06/2013 15:18, Jagan Teki wrote: This does not scale. What if a (trivial) patch touches 10 drivers? Yes, you are correct if the changes is common to across the all drivers or If the changes which are more in 10 spi drivers out of 20 or 10 for your example - use spi: and I think it's good to use above syntax as you changesd two drivers. I am just showing the possibilities of using the coding guidelines, nothing more. There is another issue: patman recognizes each subpart: and checks for an alias to find the e-mail to send patches, and stops to go on if it is not found. In this example, you can use patman if there is an entry for spi: (and this is you as SPI custodian) and also for mxc_spi:, and usually there is no maintainer for each driver. I agree that using a long chain does not scale, and I think the hidden rule to use subsystem: subject works well in most cases, Axel did in this patchset. Regards, Stefano -- = DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de = ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3 2/3] ARM: Tegra: USB: EHCI: Add support for Tegra30/Tegra114
On Mon, Jun 17, 2013 at 05:09:56PM +0800, Jim Lin wrote: [...] diff --git a/board/nvidia/common/board.c b/board/nvidia/common/board.c index 8d7a227..f0f81c9 100644 --- a/board/nvidia/common/board.c +++ b/board/nvidia/common/board.c @@ -46,7 +46,7 @@ #include asm/arch/emc.h #endif #ifdef CONFIG_USB_EHCI_TEGRA -#include asm/arch-tegra/usb.h +#include asm/arch/usb.h #endif #ifdef CONFIG_TEGRA_MMC #include asm/arch-tegra/tegra_mmc.h With this hunk applied I get the following new build warning: ../../nvidia/common/board.c: In function 'board_init': ../../nvidia/common/board.c:171:2: warning: implicit declaration of function 'board_usb_init' [-Wimplicit-function-declaration] board_usb_init(gd-fdt_blob); ^ Reverting that one hunk makes the warning go away again and everything still builds fine, so I think it can just be removed from the patch. Besides the one issue I'm still seeing with the very old flash drive, which might turn out not to be specific to Tegra, this series: Tested-by: Thierry Reding thierry.red...@gmail.com pgpEVEDZe7r2R.pgp Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] ARM: mxs: Make the console buffer smaller
Hi Marek, On 15/06/2013 23:41, Marek Vasut wrote: Using 1024 bytes for console buffer is unnecessarily too much, lower the amount for all MXS boards to 256. Signed-off-by: Marek Vasut ma...@denx.de Cc: Fabio Estevam fabio.este...@freescale.com Cc: Lauri Hintsala lauri.hints...@bluegiga.com Cc: Otavio Salvador ota...@ossystems.com.br Cc: Stefano Babic sba...@denx.de --- include/configs/mxs.h |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) Note: This depends on http://patchwork.ozlabs.org/patch/251631/ diff --git a/include/configs/mxs.h b/include/configs/mxs.h index a684166..161d89d 100644 --- a/include/configs/mxs.h +++ b/include/configs/mxs.h @@ -92,7 +92,7 @@ #ifndef CONFIG_SYS_PROMPT #define CONFIG_SYS_PROMPT= #endif -#define CONFIG_SYS_CBSIZE1024/* Console I/O buffer size */ +#define CONFIG_SYS_CBSIZE256 /* Console I/O buffer size */ #define CONFIG_SYS_PBSIZE\ (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print buffer size */ I am missing something: which is the real advantage to reduce the console buffer ? I do not think that the saved memory is worth, and on the other side more elaborated scripts (usings nested if-then-else) are quite long nowadays. Best regards, Stefano -- = DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de = ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 2/5] ARM: at91: sama5d3: remove unused definition about PMECC alpha table offset
Signed-off-by: Josh Wu josh...@atmel.com --- arch/arm/include/asm/arch-at91/sama5d3.h |2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm/include/asm/arch-at91/sama5d3.h b/arch/arm/include/asm/arch-at91/sama5d3.h index 883b932..aff12a6 100644 --- a/arch/arm/include/asm/arch-at91/sama5d3.h +++ b/arch/arm/include/asm/arch-at91/sama5d3.h @@ -194,8 +194,6 @@ */ #define ATMEL_PMECC_INDEX_OFFSET_512 0x1 #define ATMEL_PMECC_INDEX_OFFSET_1024 0x18000 -#define ATMEL_PMECC_ALPHA_OFFSET_512 0x1 -#define ATMEL_PMECC_ALPHA_OFFSET_1024 0x18000 /* * SAMA5D3 specific prototypes -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 3/5] linux/compat.h: move dev_err, dev_info and dev_dbg from usb driver to compat.h
Since kernel code current use many dev_xxx() instead of using printk. To
compatible, move those dev_xxx from usb driver to linux/compat.h. Then all
driver code can use dev_err, dev_info and dev_vdbg.
This patch also removed duplicated macro definitions in usb driver.
Signed-off-by: Josh Wu josh...@atmel.com
---
drivers/usb/musb-new/linux-compat.h | 16
include/linux/compat.h |8
2 files changed, 8 insertions(+), 16 deletions(-)
diff --git a/drivers/usb/musb-new/linux-compat.h
b/drivers/usb/musb-new/linux-compat.h
index 72c8c2b..d7a5663 100644
--- a/drivers/usb/musb-new/linux-compat.h
+++ b/drivers/usb/musb-new/linux-compat.h
@@ -39,15 +39,6 @@ typedef unsigned long dmaaddr_t;
#define cpu_relax() do {} while (0)
#define pr_debug(fmt, args...) debug(fmt, ##args)
-#define dev_dbg(dev, fmt, args...) \
- debug(fmt, ##args)
-#define dev_vdbg(dev, fmt, args...)\
- debug(fmt, ##args)
-#define dev_info(dev, fmt, args...)\
- printf(fmt, ##args)
-#define dev_err(dev, fmt, args...) \
- printf(fmt, ##args)
-#define printk printf
#define WARN(condition, fmt, args...) ({ \
int ret_warn = !!condition; \
@@ -55,13 +46,6 @@ typedef unsigned long dmaaddr_t;
printf(fmt, ##args);\
ret_warn; })
-#define KERN_DEBUG
-#define KERN_NOTICE
-#define KERN_WARNING
-#define KERN_ERR
-
-#define kfree(ptr) free(ptr)
-
#define pm_runtime_get_sync(dev) do {} while (0)
#define pm_runtime_put(dev) do {} while (0)
#define pm_runtime_put_sync(dev) do {} while (0)
diff --git a/include/linux/compat.h b/include/linux/compat.h
index e1338bf..3fdfb39 100644
--- a/include/linux/compat.h
+++ b/include/linux/compat.h
@@ -3,6 +3,14 @@
#define ndelay(x) udelay(1)
+#define dev_dbg(dev, fmt, args...) \
+ debug(fmt, ##args)
+#define dev_vdbg(dev, fmt, args...)\
+ debug(fmt, ##args)
+#define dev_info(dev, fmt, args...)\
+ printf(fmt, ##args)
+#define dev_err(dev, fmt, args...) \
+ printf(fmt, ##args)
#define printk printf
#define KERN_EMERG
--
1.7.9.5
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[U-Boot] [PATCH v2 1/5] ARM: at91: atmel_nand: pmecc driver will select the galois table by sector size
Define the galois index table offset in chip head file. So user do not need to set by himself. Driver will set it correctly according to sector_size. Signed-off-by: Josh Wu josh...@atmel.com --- arch/arm/include/asm/arch-at91/at91sam9x5.h |6 ++ doc/README.atmel_pmecc | 14 -- drivers/mtd/nand/atmel_nand.c |5 - include/configs/at91sam9x5ek.h |1 - include/configs/sama5d3xek.h|1 - 5 files changed, 10 insertions(+), 17 deletions(-) diff --git a/arch/arm/include/asm/arch-at91/at91sam9x5.h b/arch/arm/include/asm/arch-at91/at91sam9x5.h index 85e42f5..de9fa50 100644 --- a/arch/arm/include/asm/arch-at91/at91sam9x5.h +++ b/arch/arm/include/asm/arch-at91/at91sam9x5.h @@ -165,6 +165,12 @@ #define ATMEL_ID_UHP ATMEL_ID_UHPHS /* + * PMECC table in ROM + */ +#define ATMEL_PMECC_INDEX_OFFSET_512 0x8000 +#define ATMEL_PMECC_INDEX_OFFSET_1024 0x1 + +/* * at91sam9x5 specific prototypes */ #ifndef __ASSEMBLY__ diff --git a/doc/README.atmel_pmecc b/doc/README.atmel_pmecc index b483744..41f3bd7 100644 --- a/doc/README.atmel_pmecc +++ b/doc/README.atmel_pmecc @@ -19,17 +19,6 @@ To use PMECC in this driver, the user needs to set: It can be 2, 4, 8, 12 or 24. 2. The PMECC sector size: CONFIG_PMECC_SECTOR_SIZE. It only can be 512 or 1024. - 3. The PMECC index lookup table's offsets in ROM code: CONFIG_PMECC_INDEX_TABLE_OFFSET. - In the chip datasheet section Boot Stragegies, you can find - two Galois Field Table in the ROM code. One table is for 512-bytes - sector. Another is for 1024-byte sector. Each Galois Field includes - two sub-table: indext table alpha table. - In the beginning of each Galois Field Table is the index table, - Alpha table is in the following. - So the index table's offset is same as the Galois Field Table. - - Please set CONFIG_PMECC_INDEX_TABLE_OFFSET correctly according the - Galois Field Table's offset base on the sector size you used. Take AT91SAM9X5EK as an example, the board definition file likes: @@ -38,7 +27,4 @@ Take AT91SAM9X5EK as an example, the board definition file likes: #define CONFIG_ATMEL_NAND_HW_PMECC 1 #define CONFIG_PMECC_CAP 2 #define CONFIG_PMECC_SECTOR_SIZE 512 -#define CONFIG_PMECC_INDEX_TABLE_OFFSET0x8000 -NOTE: If you use 1024 as the sector size, then need set 0x1 as the - CONFIG_PMECC_INDEX_TABLE_OFFSET diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c index 3bfbaf8..139a479 100644 --- a/drivers/mtd/nand/atmel_nand.c +++ b/drivers/mtd/nand/atmel_nand.c @@ -653,7 +653,10 @@ static int atmel_pmecc_nand_init_params(struct nand_chip *nand, cap = host-pmecc_corr_cap = CONFIG_PMECC_CAP; sector_size = host-pmecc_sector_size = CONFIG_PMECC_SECTOR_SIZE; - host-pmecc_index_table_offset = CONFIG_PMECC_INDEX_TABLE_OFFSET; + if (host-pmecc_sector_size == 512) + host-pmecc_index_table_offset = ATMEL_PMECC_INDEX_OFFSET_512; + else + host-pmecc_index_table_offset = ATMEL_PMECC_INDEX_OFFSET_1024; MTDDEBUG(MTD_DEBUG_LEVEL1, Initialize PMECC params, cap: %d, sector: %d\n, diff --git a/include/configs/at91sam9x5ek.h b/include/configs/at91sam9x5ek.h index ee6e3fc..4364026 100644 --- a/include/configs/at91sam9x5ek.h +++ b/include/configs/at91sam9x5ek.h @@ -137,7 +137,6 @@ #define CONFIG_ATMEL_NAND_HW_PMECC 1 #define CONFIG_PMECC_CAP 2 #define CONFIG_PMECC_SECTOR_SIZE 512 -#define CONFIG_PMECC_INDEX_TABLE_OFFSET0x8000 #define CONFIG_MTD_DEVICE #define CONFIG_CMD_MTDPARTS diff --git a/include/configs/sama5d3xek.h b/include/configs/sama5d3xek.h index c13e983..67f8180 100644 --- a/include/configs/sama5d3xek.h +++ b/include/configs/sama5d3xek.h @@ -142,7 +142,6 @@ #define CONFIG_ATMEL_NAND_HW_PMECC #define CONFIG_PMECC_CAP 4 #define CONFIG_PMECC_SECTOR_SIZE 512 -#define CONFIG_PMECC_INDEX_TABLE_OFFSETATMEL_PMECC_INDEX_OFFSET_512 #define CONFIG_CMD_NAND_TRIMFFS #endif -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 0/5] ARM: at91: atmel_nand: check ONFI ecc minimum requirement
In this patch series, first we make the nand driver can dynamic change sector size and ecc correct bits. Then we enable ONFI ecc parameters check. v1 -- v2: Fixes according to Scoot Wood's suggestion - add a new patch which make all driver can use dev_err, dev_info, dev_dbg. - replace all printk to dev_err or dev_info. - fix pmecc data allocate error handler. - fix the pmecc ecc requirement selection, should use = instead of use . Josh Wu (5): ARM: at91: atmel_nand: pmecc driver will select the galois table by sector size ARM: at91: sama5d3: remove unused definition about PMECC alpha table offset linux/compat.h: move dev_err, dev_info and dev_dbg from usb driver to compat.h mtd: atmel_nand: alloc memory instead of use static array for pmecc data ARM: at91: atmel_nand: add code to check the ONFI parameter ECC requirement arch/arm/include/asm/arch-at91/at91sam9x5.h |6 + arch/arm/include/asm/arch-at91/sama5d3.h|2 - doc/README.atmel_pmecc | 14 -- drivers/mtd/nand/atmel_nand.c | 197 +-- drivers/usb/musb-new/linux-compat.h | 16 --- include/configs/at91sam9x5ek.h |1 - include/configs/sama5d3xek.h|1 - include/linux/compat.h |8 ++ 8 files changed, 201 insertions(+), 44 deletions(-) -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 4/5] mtd: atmel_nand: alloc memory instead of use static array for pmecc data
In this way, the pmecc corraction capbility can change in run time.
Signed-off-by: Josh Wu josh...@atmel.com
---
v1 -- v2:
replace printk with dev_err.
fix coding style.
free memory before return ENOMEM.
drivers/mtd/nand/atmel_nand.c | 63 -
1 file changed, 56 insertions(+), 7 deletions(-)
diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c
index 139a479..3cd403f 100644
--- a/drivers/mtd/nand/atmel_nand.c
+++ b/drivers/mtd/nand/atmel_nand.c
@@ -32,6 +32,7 @@
#include asm/arch/gpio.h
#include asm/arch/at91_pio.h
+#include malloc.h
#include nand.h
#include watchdog.h
@@ -66,13 +67,13 @@ struct atmel_nand_host {
void __iomem*pmecc_index_of;
/* data for pmecc computation */
- int16_t pmecc_smu[(CONFIG_PMECC_CAP + 2) * (2 * CONFIG_PMECC_CAP + 1)];
- int16_t pmecc_partial_syn[2 * CONFIG_PMECC_CAP + 1];
- int16_t pmecc_si[2 * CONFIG_PMECC_CAP + 1];
- int16_t pmecc_lmu[CONFIG_PMECC_CAP + 1]; /* polynomal order */
- int pmecc_mu[CONFIG_PMECC_CAP + 1];
- int pmecc_dmu[CONFIG_PMECC_CAP + 1];
- int pmecc_delta[CONFIG_PMECC_CAP + 1];
+ int16_t *pmecc_smu;
+ int16_t *pmecc_partial_syn;
+ int16_t *pmecc_si;
+ int16_t *pmecc_lmu; /* polynomal order */
+ int *pmecc_mu;
+ int *pmecc_dmu;
+ int *pmecc_delta;
};
static struct atmel_nand_host pmecc_host;
@@ -125,6 +126,48 @@ static void __iomem *pmecc_get_alpha_to(struct
atmel_nand_host *host)
table_size * sizeof(int16_t);
}
+static void pmecc_data_free(struct atmel_nand_host *host)
+{
+ free(host-pmecc_partial_syn);
+ free(host-pmecc_si);
+ free(host-pmecc_lmu);
+ free(host-pmecc_smu);
+ free(host-pmecc_mu);
+ free(host-pmecc_dmu);
+ free(host-pmecc_delta);
+}
+
+static int pmecc_data_alloc(struct atmel_nand_host *host)
+{
+ const int cap = host-pmecc_corr_cap;
+ int size;
+
+ size = (2 * cap + 1) * sizeof(int16_t);
+ host-pmecc_partial_syn = malloc(size);
+ host-pmecc_si = malloc(size);
+ host-pmecc_lmu = malloc((cap + 1) * sizeof(int16_t));
+ host-pmecc_smu = malloc((cap + 2) * size);
+
+ size = (cap + 1) * sizeof(int);
+ host-pmecc_mu = malloc(size);
+ host-pmecc_dmu = malloc(size);
+ host-pmecc_delta = malloc(size);
+
+ if (host-pmecc_partial_syn
+ host-pmecc_si
+ host-pmecc_lmu
+ host-pmecc_smu
+ host-pmecc_mu
+ host-pmecc_dmu
+ host-pmecc_delta)
+ return 0;
+
+ /* error happened */
+ pmecc_data_free(host);
+ return -ENOMEM;
+
+}
+
static void pmecc_gen_syndrome(struct mtd_info *mtd, int sector)
{
struct nand_chip *nand_chip = mtd-priv;
@@ -710,6 +753,12 @@ static int atmel_pmecc_nand_init_params(struct nand_chip
*nand,
return 0;
}
+ /* Allocate data for PMECC computation */
+ if (pmecc_data_alloc(host)) {
+ dev_err(NULL, Cannot allocate memory for PMECC
computation!\n);
+ return -ENOMEM;
+ }
+
nand-ecc.read_page = atmel_nand_pmecc_read_page;
nand-ecc.write_page = atmel_nand_pmecc_write_page;
nand-ecc.strength = cap;
--
1.7.9.5
___
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[U-Boot] [PATCH v2 5/5] ARM: at91: atmel_nand: add code to check the ONFI parameter ECC requirement
1. if CONFIG_SYS_NAND_ONFI_DETECTION is defined, driver will check NAND flash's
ecc minimum requirement in ONFI parameter.
a) if CONFIG_PMECC_CAP, CONFIG_PMECC_SECTOR_SIZE are defined. then use it.
Driver will display a WARNING if the values are different from ONFI
parameters.
b) if CONFIG_PMECC_CAP, CONFIG_PMECC_SECTOR_SIZE are not defined, then use
the value from ONFI parameters.
* If ONFI ECC parameters are in ONFI extended parameter page, since we
are not support it, so assume the minimum ecc requirement is 2 bits
in 512 bytes.
* For non-ONFI support nand flash, also assume the minimum ecc
requirement is 2 bits in 512 bytes.
2. if CONFIG_SYS_NAND_ONFI_DETECTION is not defined, just use CONFIG_PMECC_CAP
and CONFIG_PMECC_SECTOR_SIZE.
Signed-off-by: Josh Wu josh...@atmel.com
---
v1 -- v2:
use dev_err/info to replace printk.
fix typo mistake, that should use = instead of use .
drivers/mtd/nand/atmel_nand.c | 129 -
1 file changed, 127 insertions(+), 2 deletions(-)
diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c
index 3cd403f..ceba562 100644
--- a/drivers/mtd/nand/atmel_nand.c
+++ b/drivers/mtd/nand/atmel_nand.c
@@ -681,6 +681,98 @@ static void atmel_pmecc_core_init(struct mtd_info *mtd)
pmecc_writel(host-pmecc, ctrl, PMECC_CTRL_ENABLE);
}
+#ifdef CONFIG_SYS_NAND_ONFI_DETECTION
+/*
+ * get_onfi_ecc_param - Get ECC requirement from ONFI parameters
+ * @ecc_bits: store the ONFI ECC correct bits capbility
+ * @sector_size: in how many bytes that ONFI require to correct @ecc_bits
+ *
+ * Returns -1 if ONFI parameters is not supported. In this case @ecc_bits,
+ * @sector_size are initialize to 0.
+ * Return 0 if success to get the ECC requirement.
+ */
+static int get_onfi_ecc_param(struct nand_chip *chip,
+ int *ecc_bits, int *sector_size)
+{
+ *ecc_bits = *sector_size = 0;
+
+ if (chip-onfi_params.ecc_bits == 0xff)
+ /* TODO: the sector_size and ecc_bits need to be find in
+* extended ecc parameter, currently we don't support it.
+*/
+ return -1;
+
+ *ecc_bits = chip-onfi_params.ecc_bits;
+
+ /* The default sector size (ecc codeword size) is 512 */
+ *sector_size = 512;
+
+ return 0;
+}
+
+/*
+ * pmecc_choose_ecc - Get ecc requirement from ONFI parameters. If
+ *pmecc_corr_cap or pmecc_sector_size is 0, then set it as
+ *ONFI ECC parameters.
+ * @host: point to an atmel_nand_host structure.
+ *if host-pmecc_corr_cap is 0 then set it as the ONFI ecc_bits.
+ *if host-pmecc_sector_size is 0 then set it as the ONFI sector_size.
+ * @chip: point to an nand_chip structure.
+ * @cap: store the ONFI ECC correct bits capbility
+ * @sector_size: in how many bytes that ONFI require to correct @ecc_bits
+ *
+ * Return 0 if success. otherwise return the error code.
+ */
+static int pmecc_choose_ecc(struct atmel_nand_host *host,
+ struct nand_chip *chip,
+ int *cap, int *sector_size)
+{
+ /* Get ECC requirement from ONFI parameters */
+ *cap = *sector_size = 0;
+ if (chip-onfi_version) {
+ if (!get_onfi_ecc_param(chip, cap, sector_size))
+ pr_debug(ONFI params, minimum required ECC: %d bits in
%d bytes\n,
+ *cap, *sector_size);
+ else
+ dev_info(NULL, NAND chip ECC reqirement is in Extended
ONFI parameter, we don't support yet.\n);
+ } else {
+ dev_info(NULL, NAND chip is not ONFI compliant, assume
ecc_bits is 2 in 512 bytes);
+ }
+ if (*cap == 0 *sector_size == 0) {
+ /* Non-ONFI compliant or use extended ONFI parameters */
+ *cap = 2;
+ *sector_size = 512;
+ }
+
+ /* If head file doesn't specify then use the one in ONFI parameters */
+ if (host-pmecc_corr_cap == 0) {
+ /* use the most fitable ecc bits (the near bigger one ) */
+ if (*cap = 2)
+ host-pmecc_corr_cap = 2;
+ else if (*cap = 4)
+ host-pmecc_corr_cap = 4;
+ else if (*cap = 8)
+ host-pmecc_corr_cap = 8;
+ else if (*cap = 12)
+ host-pmecc_corr_cap = 12;
+ else if (*cap = 24)
+ host-pmecc_corr_cap = 24;
+ else
+ return -EINVAL;
+ }
+ if (host-pmecc_sector_size == 0) {
+ /* use the most fitable sector size (the near smaller one ) */
+ if (*sector_size = 1024)
+ host-pmecc_sector_size = 1024;
+ else if (*sector_size = 512)
+ host-pmecc_sector_size = 512;
+ else
+
Re: [U-Boot] [PATCH 3/3] arm: omap3: Add SPL support to cm_t35
Hi Stefan,
On 06/14/13 11:55, Stefan Roese wrote:
Add SPL U-Boot support to replace x-loader on the Compulab cm_t35
board. Currently only the 256MiB SDRAM board versions are supported.
Tested by booting via MMC and NAND.
Signed-off-by: Stefan Roese s...@denx.de
Cc: Tom Rini tr...@ti.com
Cc: Igor Grinberg grinb...@compulab.co.il
---
board/compulab/cm_t35/cm_t35.c | 18 +++-
include/configs/cm_t35.h | 64
--
2 files changed, 79 insertions(+), 3 deletions(-)
diff --git a/board/compulab/cm_t35/cm_t35.c b/board/compulab/cm_t35/cm_t35.c
index b0b80e5..cd7882e 100644
--- a/board/compulab/cm_t35/cm_t35.c
+++ b/board/compulab/cm_t35/cm_t35.c
@@ -120,6 +120,22 @@ static inline int splash_load_from_nand(void)
}
#endif /* CONFIG_CMD_NAND */
+#ifdef CONFIG_SPL_BUILD
+/*
+ * Routine: get_board_mem_timings
+ * Description: If we use SPL then there is no x-loader nor config header
+ * so we have to setup the DDR timings ourself on both banks.
+ */
+void get_board_mem_timings(struct board_sdrc_timings *timings)
+{
+ timings-mr = MICRON_V_MR_165;
+ timings-mcfg = MICRON_V_MCFG_165(256 20);
+ timings-ctrla = MICRON_V_ACTIMA_165;
+ timings-ctrlb = MICRON_V_ACTIMB_165;
+ timings-rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
+}
+#endif
I still haven't checked the timings...
Hopefully, I will sometime during this week.
+
int board_splash_screen_prepare(void)
{
char *env_splashimage_value;
@@ -443,7 +459,7 @@ void set_muxconf_regs(void)
cm_t3730_set_muxconf();
}
-#ifdef CONFIG_GENERIC_MMC
+#if defined(CONFIG_GENERIC_MMC) !defined(CONFIG_SPL_BUILD)
int board_mmc_getcd(struct mmc *mmc)
{
u8 val;
diff --git a/include/configs/cm_t35.h b/include/configs/cm_t35.h
index c6e357a..b76810d 100644
--- a/include/configs/cm_t35.h
+++ b/include/configs/cm_t35.h
@@ -40,8 +40,6 @@
#define CONFIG_OMAP_GPIO
#define CONFIG_CM_T3X/* working with CM-T35 and CM-T3730 */
-#define CONFIG_SYS_TEXT_BASE 0x80008000
-
#define CONFIG_SDRC /* The chip has SDRC controller */
#include asm/arch/cpu.h/* get chip and board defs */
@@ -341,4 +339,66 @@
#define CONFIG_BMP_16BPP
#define CONFIG_SPLASH_SCREEN_PREPARE
+/* Defines for SPL */
+#define CONFIG_SPL
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_NAND_SIMPLE
+#define CONFIG_SPL_TEXT_BASE 0x40200800
+#define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */
+#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
+
+#define CONFIG_SPL_BSS_START_ADDR0x8000
+#define CONFIG_SPL_BSS_MAX_SIZE 0x8 /* 512 KB */
+
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address
0x6 */
+#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
+#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1
+#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME u-boot.img
+
+#define CONFIG_SPL_BOARD_INIT
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBDISK_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SPL_FAT_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_BASE
+#define CONFIG_SPL_NAND_DRIVERS
+#define CONFIG_SPL_NAND_ECC
+#define CONFIG_SPL_GPIO_SUPPORT
+#define CONFIG_SPL_POWER_SUPPORT
+#define CONFIG_SPL_OMAP3_ID_NAND
+#define CONFIG_SPL_LDSCRIPT $(CPUDIR)/omap-common/u-boot-spl.lds
+
+/* NAND boot config */
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_PAGE_COUNT 64
+#define CONFIG_SYS_NAND_PAGE_SIZE2048
+#define CONFIG_SYS_NAND_OOBSIZE 64
+#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
+#define CONFIG_SYS_NAND_BAD_BLOCK_POSNAND_LARGE_BADBLOCK_POS
+/*
+ * Use the ECC/OOB layout from omap_gpmc.h that matches your chip:
+ * SP vs LP, 8bit vs 16bit: GPMC_NAND_HW_ECC_LAYOUT
+ */
+#define CONFIG_SYS_NAND_ECCPOS { 1, 2, 3, 4, 5, 6, 7, 8, 9, \
+ 10, 11, 12 }
+#define CONFIG_SYS_NAND_ECCSIZE 512
+#define CONFIG_SYS_NAND_ECCBYTES 3
+
+#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x8
+
+/*
+ * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
+ * 64 bytes before this address should be set aside for u-boot.img's
+ * header. That is 0x800FFFC0--0x8010 should not be used for any
+ * other needs.
+ */
+#define CONFIG_SYS_TEXT_BASE 0x8010
Now this is a problem.
This breaks the backward compatibility with our X-Loader and we
cannot just switch to 8010...
+#define CONFIG_SYS_SPL_MALLOC_START 0x80208000
+#define CONFIG_SYS_SPL_MALLOC_SIZE 0x10
+
#endif /* __CONFIG_H */
--
Regards,
Igor.
___
[U-Boot] [PATCH] board/bsc913x: Add config flag for bootdelay
Keep the value of CONFIG_BOOTDELAY as -1 to disable autoboot Signed-off-by: Harninder Rai harninder@freescale.com --- include/configs/BSC9131RDB.h |1 + include/configs/BSC9132QDS.h |1 + 2 files changed, 2 insertions(+), 0 deletions(-) diff --git a/include/configs/BSC9131RDB.h b/include/configs/BSC9131RDB.h index fd076e0..c56b119 100644 --- a/include/configs/BSC9131RDB.h +++ b/include/configs/BSC9131RDB.h @@ -393,6 +393,7 @@ extern unsigned long get_sdram_size(void); #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ #define CONFIG_BAUDRATE115200 +#define CONFIG_BOOTDELAY -1 /* Disable autoboot */ #defineCONFIG_EXTRA_ENV_SETTINGS \ netdev=eth0\0 \ diff --git a/include/configs/BSC9132QDS.h b/include/configs/BSC9132QDS.h index 9d15d0e..d54900a 100644 --- a/include/configs/BSC9132QDS.h +++ b/include/configs/BSC9132QDS.h @@ -607,6 +607,7 @@ combinations. this should be removed later #define CONFIG_UBOOTPATH u-boot.bin #define CONFIG_BAUDRATE115200 +#define CONFIG_BOOTDELAY -1 /* Disable autoboot */ #ifdef CONFIG_SDCARD #define CONFIG_DEF_HWCONFIGhwconfig=usb1:dr_mode=host,phy_type=ulpi\0 -- 1.5.5.6 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v5 00/14] arm: add Faraday A36x SoC platform support
From: Kuo-Jung Su dant...@faraday-tech.com
These patches introduce Faraday A36x SoC platform support.
Here are some public documents for your reference.
http://www.faraday-tech.com/html/documentation/index.html
There is also a A369 QEMU emulator available at my github account:
https://github.com/dantesu1218/qemu.git
Here is quick start for QEMU + U-Boot:
1. Download the QEMU source tree
$ git clone -b qemu-1.4.0 https://github.com/dantesu1218/qemu.git
2. Build Install the QEMU:
$ ./configure --target-list=arm-softmmu
$ make
$ make install
3. Launch u-boot with QEMU:
$ qemu-system-arm -M a369 -m 512M -nographic -kernel ~/u-boot-2013.04/u-boot
Changes for v5:
- Coding Style cleanup:
1. struct chip_regs __iomem *regs - struct chip_regs *regs
2. Move Faraday specific APIs into asm/arch-faraday/*.h
- Fix Copyright notices (dates) throughout the patch
- Make 'arm: dma_alloc_coherent: malloc() - memalign()' as a separate patch
- Make 'cfi_flash: use buffer length in unmap_physmem()' as a separate patch
- Define Faraday machine type in board's config header file
- Add the rationale to the command 'bootfa'
- Add myself as the maintainer for Faraday A360/A369 in MAINTAINERS.
- Chain the video:FTLCDC200 back to this patch series.
- Chain the nand:FTNANDC021 back to this patch series.
- Chain the net:FTGMAC100 FTMAC110 back to this patch series.
- Update Faraday Firmware Image Format:
1. Drop u-boot image support to simplify the design.
Since it's not possible for the hard-wired ROM code of A360/A369
to support U-boot images. And the real bootloader for A360/A369
is actually Faraday bootcode2, rather than U-Boot.
2. Add image creation timestamp
- Update 'arch/arm/cpu/faraday/start.S' with the new design, which move
relocation into 'arch/arm/lib/relocate.S'
- Drop i2c:FTI2C010 spi:FTSSP010_SPI support. The corresponding patch
would restart after this patch series have been accepted.
- Revise IRQ MMU design: Now the exception table would be mapped to
0x as a small page(4KB), rather than runtime adjust after
relocation finished.
- Revise irq:FTINTC020 design, now the irq is always enabled inside
irq_install_handler().
- Revise clock management system
- Revise FTPWMTMR010 FTTMR010 timer design:
1. Drop IRQ dependant implementation
2. Use gd-arch.timer_rate_hz for timer clock source
3. Use gd-arch.tbl for timestamp
Changes for v4:
- Coding Style cleanup.
- Break down the patch series:
- Patches without hard dependency to this series are now
seperate patches.
- Split up the patch into more logical changesets
(i.e. interrupt timers are now split up)
- Drop the faraday/nand.h to remove dependency to ftnandc021
- Drop the faraday/mmc.h to remove dependency to ftsdc010
- Add change logs to each part of the patch series to make
patchwork be able to grab comments.
Changes for v3:
- Coding Style cleanup.
There is still one warnning reported by checkpatch.pl,
however it's too deep for me to fix it.
Here is the shapshot for it:
-
WARNING: do not add new typedefs
#9735: FILE: include/lcd.h:258:
+typedef struct vidinfo {
-
- Drop bit fields from c struct.
- Drop macros for wirtel()/readl(), call them directly.
- Always insert a blank line between declarations and code.
- Replace all the infinite wait loop with a timeout.
- Add '__iomem' to all the declaration of HW register pointers.
- cmd_boot.c: Make it a separate stand-alone patch.
- ftspi020: Make it a separate stand-alone patch.
- dma-mapping.h: Have the global data ptr declared outside functions.
- dma-mapping.h: Add #if...#else...#endif to dma_free_coherent().
- MMU/D-Cache: Drop static non-cached region, now we use
map_physmem()/unmap_physmem() for dynamic mappings.
- ftmac110: Make a correction to multi-line comment style
- ftmac110: Use random MAC address while having trouble
to get one from environment variables.
- ftmac110: Add comments to timing control registers.
- ftnandc021: Re-write this driver with ECC enabled and
correct column address handling for OOB read/write,
and fixing issused addressed by Scott.
- a36x_config: No more static global network configurations.
- a36x_config: Add a common file for the redundant configurations.
Changes for v2:
- Coding Style cleanup.
- Use readl(), writel(), clrsetbits_le32() to replace REG() macros.
- Use structure based hardware registers to replace the macro constants.
- Replace BIT() with BIT_MASK().
- echi-faraday: Remove debug codes.
- ftmac110: Remove debug codes.
- cache-cp15: Enable write buffer in write-through mode.
Kuo-Jung Su (14):
arm:
[U-Boot] [PATCH v5 03/14] net: add Faraday FTMAC110 10/100Mbps ethernet support
From: Kuo-Jung Su dant...@faraday-tech.com Faraday FTMAC110 10/100Mbps supports half-word data transfer for Linux. However it has a weird DMA alignment issue: (1) Tx DMA Buffer Address: 1 bytes aligned: Invalid 2 bytes aligned: O.K 4 bytes aligned: O.K (2) Rx DMA Buffer Address: 1 bytes aligned: Invalid 2 bytes aligned: O.K 4 bytes aligned: Invalid!!! NOTE: No matter if MMU/D-cache is on or off, this patch always depends on previous patch: arm: dma_alloc_coherent: malloc() - memalign(). Because the FTMAC110 expects the tx/rx descriptors are always be aligned to 16-bytes boundary. Signed-off-by: Kuo-Jung Su dant...@faraday-tech.com CC: Albert ARIBAUD albert.u.b...@aribaud.net CC: Joe Hershberger joe.hershber...@gmail.com CC: Tom Rini tr...@ti.com --- Changes for v5: - Coding Style cleanup: struct chip_regs __iomem *regs - struct chip_regs *regs - Chain it back to Faraday A360/A369 patch series, because this strongly depends on patch to dma_alloc_coherent() at the Faraday A360/A369 patch series. Changes for v4: - Make it a separate patch, rather then a part of Faraday A36x patch series - Use macro constants for timeout control - Use only named constants for bit mask/shift and values - Drop the magic number from mdio read/write. Changes for v3: - Coding Style cleanup. - Drop bit fields from c struct. - Drop macros for wirtel()/readl(), call them directly. - Always insert a blank line between declarations and code. - Replace all the infinite wait loop with a timeout. - Add '__iomem' to all the declaration of HW register pointers. - Make a correction to multi-line comment style - Use random MAC address while having trouble to get one from environment variables. - Add comments to timing control registers. Changes for v2: - Coding Style cleanup. - Use readl(), writel(), clrsetbits_le32() to replace REG() macros. - Use structure based hardware registers to replace the macro constants. - Replace BIT() with BIT_MASK(). - ftmac110: Remove debug codes. drivers/net/Makefile |1 + drivers/net/ftmac110.c | 484 drivers/net/ftmac110.h | 188 +++ include/netdev.h |1 + 4 files changed, 674 insertions(+) create mode 100644 drivers/net/ftmac110.c create mode 100644 drivers/net/ftmac110.h diff --git a/drivers/net/Makefile b/drivers/net/Makefile index 786a656..0e23817 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -46,6 +46,7 @@ COBJS-$(CONFIG_ETHOC) += ethoc.o COBJS-$(CONFIG_FEC_MXC) += fec_mxc.o COBJS-$(CONFIG_FSLDMAFEC) += fsl_mcdmafec.o mcfmii.o COBJS-$(CONFIG_FTGMAC100) += ftgmac100.o +COBJS-$(CONFIG_FTMAC110) += ftmac110.o COBJS-$(CONFIG_FTMAC100) += ftmac100.o COBJS-$(CONFIG_GRETH) += greth.o COBJS-$(CONFIG_INCA_IP_SWITCH) += inca-ip_sw.o diff --git a/drivers/net/ftmac110.c b/drivers/net/ftmac110.c new file mode 100644 index 000..1afd95a --- /dev/null +++ b/drivers/net/ftmac110.c @@ -0,0 +1,484 @@ +/* + * Faraday 10/100Mbps Ethernet Controller + * + * (C) Copyright 2013 Faraday Technology + * Dante Su dant...@faraday-tech.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include common.h +#include command.h +#include malloc.h +#include net.h +#include asm/errno.h +#include asm/io.h +#include asm/dma-mapping.h + +#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) +#include miiphy.h +#endif + +#include ftmac110.h + +#define CFG_RXDES_NUM 8 +#define CFG_TXDES_NUM 2 +#define CFG_XBUF_SIZE 1536 + +#define CFG_MDIORD_TIMEOUT (CONFIG_SYS_HZ 1) /* 500 ms */ +#define CFG_MDIOWR_TIMEOUT (CONFIG_SYS_HZ 1) /* 500 ms */ +#define CFG_LINKUP_TIMEOUT (CONFIG_SYS_HZ 2) /* 4 sec */ + +/* + * FTMAC110 DMA design issue + * + * Its DMA engine has a weird restriction that its Rx DMA engine + * accepts only 16-bits aligned address, 32-bits aligned is not + * acceptable. However this restriction does not apply to Tx DMA. + * + * Conclusion: + * (1) Tx DMA Buffer Address: + * 1 bytes aligned: Invalid + * 2 bytes aligned: O.K + * 4 bytes aligned: O.K (- u-boot ZeroCopy is possible) + * (2) Rx DMA Buffer Address: + * 1 bytes aligned: Invalid + * 2 bytes aligned: O.K + * 4 bytes aligned: Invalid + */ +
[U-Boot] [PATCH v5 01/14] arm: dma_alloc_coherent: malloc() - memalign()
From: Kuo-Jung Su dant...@faraday-tech.com
Even though the MMU/D-cache is off, some DMA engines still
expect strict address alignment.
For example, the incoming Faraday FTMAC110 FTGMAC100 ethernet
controllers expect the tx/rx descriptors should always be aligned
to 16-bytes boundary.
Signed-off-by: Kuo-Jung Su dant...@faraday-tech.com
CC: Albert ARIBAUD albert.u.b...@aribaud.net
---
Changes for v5:
- Initial commit, which is separated from
arm: add MMU/D-Cache support for Faraday cores
arch/arm/include/asm/dma-mapping.h |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/dma-mapping.h
b/arch/arm/include/asm/dma-mapping.h
index 5bbb0a0..a11178f 100644
--- a/arch/arm/include/asm/dma-mapping.h
+++ b/arch/arm/include/asm/dma-mapping.h
@@ -32,7 +32,7 @@ enum dma_data_direction {
static void *dma_alloc_coherent(size_t len, unsigned long *handle)
{
- *handle = (unsigned long)malloc(len);
+ *handle = (unsigned long)memalign(ARCH_DMA_MINALIGN, len);
return (void *)*handle;
}
--
1.7.9.5
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v5 02/14] net: ftgmac100: add MMU/D-cache support
From: Kuo-Jung Su dant...@faraday-tech.com
1. Dynamically allocate the tx/rx descriptors
through dma_alloc_coherent(), instead of
allocating at compile/link time.
2. Do not block on ftgmac100_send(), the packet
has been copied to a safe buffer. Although it's
a little bit slower, but the tx performance is
never critical.
3. No matter if MMU/D-cache is on or off, this patch
always depends on previous patch:
arm: dma_alloc_coherent: malloc() - memalign().
Because the FTGMAC100 expects the tx/rx descriptors
are always be aligned to 16-bytes boundary.
Signed-off-by: Kuo-Jung Su dant...@faraday-tech.com
CC: Albert ARIBAUD albert.u.b...@aribaud.net
CC: Joe Hershberger joe.hershber...@gmail.com
CC: Tom Rini tr...@ti.com
---
Changes for v5:
- Chain it back to Faraday A360/A369 patch series, because this
strongly depends on patch to dma_alloc_coherent() at the
Faraday A360/A369 patch series.
Changes for v4:
- Make it a separate patch, rather then a part of
Faraday A36x patch series
Changes for v3:
- Coding Style cleanup
Changes for v2:
- Coding Style cleanup
- Cleanup (Drop cosmetic patch)
drivers/net/ftgmac100.c | 70 +--
1 file changed, 49 insertions(+), 21 deletions(-)
diff --git a/drivers/net/ftgmac100.c b/drivers/net/ftgmac100.c
index 69ba57d..2dbb328 100644
--- a/drivers/net/ftgmac100.c
+++ b/drivers/net/ftgmac100.c
@@ -27,11 +27,13 @@
#include malloc.h
#include net.h
#include asm/io.h
+#include asm/dma-mapping.h
#include linux/mii.h
#include ftgmac100.h
#define ETH_ZLEN 60
+#define CFG_XBUF_SIZE 1536
/* RBSR - hw default init value is also 0x640 */
#define RBSR_DEFAULT_VALUE 0x640
@@ -40,8 +42,10 @@
#define PKTBUFSTX 4 /* must be power of 2 */
struct ftgmac100_data {
- struct ftgmac100_txdes txdes[PKTBUFSTX];
- struct ftgmac100_rxdes rxdes[PKTBUFSRX];
+ ulong txdes_dma;
+ struct ftgmac100_txdes *txdes;
+ ulong rxdes_dma;
+ struct ftgmac100_rxdes *rxdes;
int tx_index;
int rx_index;
int phy_addr;
@@ -375,13 +379,34 @@ static int ftgmac100_init(struct eth_device *dev, bd_t
*bd)
{
struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev-iobase;
struct ftgmac100_data *priv = dev-priv;
- struct ftgmac100_txdes *txdes = priv-txdes;
- struct ftgmac100_rxdes *rxdes = priv-rxdes;
+ struct ftgmac100_txdes *txdes;
+ struct ftgmac100_rxdes *rxdes;
unsigned int maccr;
+ void *buf;
int i;
debug(%s()\n, __func__);
+ if (!priv-txdes) {
+ txdes = dma_alloc_coherent(
+ sizeof(*txdes) * PKTBUFSTX, priv-txdes_dma);
+ if (!txdes)
+ panic(ftgmac100: out of memory\n);
+ memset(txdes, 0, sizeof(*txdes) * PKTBUFSTX);
+ priv-txdes = txdes;
+ }
+ txdes = priv-txdes;
+
+ if (!priv-rxdes) {
+ rxdes = dma_alloc_coherent(
+ sizeof(*rxdes) * PKTBUFSRX, priv-rxdes_dma);
+ if (!rxdes)
+ panic(ftgmac100: out of memory\n);
+ memset(rxdes, 0, sizeof(*rxdes) * PKTBUFSRX);
+ priv-rxdes = rxdes;
+ }
+ rxdes = priv-rxdes;
+
/* set the ethernet address */
ftgmac100_set_mac_from_env(dev);
@@ -397,21 +422,31 @@ static int ftgmac100_init(struct eth_device *dev, bd_t
*bd)
for (i = 0; i PKTBUFSTX; i++) {
/* TXBUF_BADR */
- txdes[i].txdes3 = 0;
+ if (!txdes[i].txdes2) {
+ buf = memalign(ARCH_DMA_MINALIGN, CFG_XBUF_SIZE);
+ if (!buf)
+ panic(ftgmac100: out of memory\n);
+ txdes[i].txdes3 = virt_to_phys(buf);
+ txdes[i].txdes2 = (uint)buf;
+ }
txdes[i].txdes1 = 0;
}
for (i = 0; i PKTBUFSRX; i++) {
/* RXBUF_BADR */
- rxdes[i].rxdes3 = (unsigned int)NetRxPackets[i];
+ if (!rxdes[i].rxdes2) {
+ buf = NetRxPackets[i];
+ rxdes[i].rxdes3 = virt_to_phys(buf);
+ rxdes[i].rxdes2 = (uint)buf;
+ }
rxdes[i].rxdes0 = ~FTGMAC100_RXDES0_RXPKT_RDY;
}
/* transmit ring */
- writel((unsigned int)txdes, ftgmac100-txr_badr);
+ writel(priv-txdes_dma, ftgmac100-txr_badr);
/* receive ring */
- writel((unsigned int)rxdes, ftgmac100-rxr_badr);
+ writel(priv-rxdes_dma, ftgmac100-rxr_badr);
/* poll receive descriptor automatically */
writel(FTGMAC100_APTC_RXPOLL_CNT(1), ftgmac100-aptc);
@@ -466,8 +501,11 @@ static int ftgmac100_recv(struct eth_device *dev)
debug(%s(): RX buffer %d, %x received\n,
__func__,
[U-Boot] [PATCH v5 07/14] arm: add MMU/D-Cache support for Faraday cores
From: Kuo-Jung Su dant...@faraday-tech.com
This updates the map_physmem()/unmap_physmem(), and use
them to implement dma_alloc_coherent() dma_free_coherent().
It uses 1MB section for each mapping, and thus wastes lots of
address space, however this should still be good enough for
tiny systems (i.e. u-boot).
Signed-off-by: Kuo-Jung Su dant...@faraday-tech.com
CC: Albert Aribaud albert.u.b...@aribaud.net
---
Changes for v5:
- Add void dram_bank_mmu_setup() into 'arch/arm/cpu/faraday/cpu.c'
to override the weak function in cache-cp15.c.
- Use small page (4KB) to map relocated exception table to 0x
Changes for v4:
- Coding Style cleanup.
Changes for v3:
- Coding Style cleanup.
- Always insert a blank line between declarations and code.
- dma-mapping.h: Have the global data ptr declared outside functions.
- dma-mapping.h: Add #if...#else...#endif to dma_free_coherent().
- Drop static non-cached region, now we use map_physmem()/unmap_physmem()
for dynamic mappings.
Changes for v2:
- Coding Style cleanup.
- cache-cp15: Enable write buffer in write-through mode.
arch/arm/include/asm/dma-mapping.h | 59 -
arch/arm/include/asm/global_data.h |4 +
arch/arm/include/asm/io.h | 160 ++--
arch/arm/include/asm/system.h |7 +-
arch/arm/lib/cache-cp15.c | 12 +++
5 files changed, 230 insertions(+), 12 deletions(-)
diff --git a/arch/arm/include/asm/dma-mapping.h
b/arch/arm/include/asm/dma-mapping.h
index a11178f..5a13af5 100644
--- a/arch/arm/include/asm/dma-mapping.h
+++ b/arch/arm/include/asm/dma-mapping.h
@@ -3,6 +3,9 @@
* Stelian Pop stel...@popies.net
* Lead Tech Design www.leadtechdesign.com
*
+ * (C) Copyright 2010
+ * Dante Su dant...@faraday-tech.com
+ *
* See file CREDITS for list of people who contributed to this
* project.
*
@@ -24,22 +27,76 @@
#ifndef __ASM_ARM_DMA_MAPPING_H
#define __ASM_ARM_DMA_MAPPING_H
+#if defined(CONFIG_FARADAY) !defined(CONFIG_SYS_DCACHE_OFF)
+#include asm/u-boot.h
+#include asm/global_data.h
+#include asm/io.h
+#include malloc.h
+
+DECLARE_GLOBAL_DATA_PTR;
+#endif /* CONFIG_FARADAY !CONFIG_SYS_DCACHE_OFF */
+
enum dma_data_direction {
DMA_BIDIRECTIONAL = 0,
DMA_TO_DEVICE = 1,
DMA_FROM_DEVICE = 2,
};
-static void *dma_alloc_coherent(size_t len, unsigned long *handle)
+static inline void *dma_alloc_coherent(size_t len, unsigned long *handle)
{
+#if defined(CONFIG_FARADAY) !defined(CONFIG_SYS_DCACHE_OFF)
+ void *map, *va = memalign(ARCH_DMA_MINALIGN, len);
+
+ if (va gd-arch.cpu_mmu) {
+ invalidate_dcache_range((ulong)va, (ulong)va + len);
+ map = map_physmem((phys_addr_t)va, len, MAP_NOCACHE);
+ if (!map)
+ free(va);
+ va = map;
+ }
+
+ if (handle)
+ *handle = virt_to_phys(va);
+
+ return va;
+#else /* CONFIG_FARADAY !CONFIG_SYS_DCACHE_OFF */
*handle = (unsigned long)memalign(ARCH_DMA_MINALIGN, len);
return (void *)*handle;
+#endif /* CONFIG_FARADAY !CONFIG_SYS_DCACHE_OFF */
+}
+
+static inline void dma_free_coherent(void *vaddr, ulong len)
+{
+#if defined(CONFIG_FARADAY) !defined(CONFIG_SYS_DCACHE_OFF)
+ void *tmp = (void *)virt_to_phys(vaddr);
+ unmap_physmem(vaddr, len);
+ vaddr = tmp;
+#endif
+ free(vaddr);
}
static inline unsigned long dma_map_single(volatile void *vaddr, size_t len,
enum dma_data_direction dir)
{
+#if defined(CONFIG_FARADAY) !defined(CONFIG_SYS_DCACHE_OFF)
+ if (gd-arch.cpu_mmu) {
+ switch (dir) {
+ case DMA_BIDIRECTIONAL:
+ case DMA_TO_DEVICE:
+ flush_dcache_range((ulong)vaddr,
+ (ulong)vaddr + len);
+ break;
+
+ case DMA_FROM_DEVICE:
+ invalidate_dcache_range((ulong)vaddr,
+ (ulong)vaddr + len);
+ break;
+ }
+ }
+ return virt_to_phys((void *)vaddr);
+#else /* CONFIG_FARADAY !CONFIG_SYS_DCACHE_OFF */
return (unsigned long)vaddr;
+#endif /* CONFIG_FARADAY !CONFIG_SYS_DCACHE_OFF */
}
static inline void dma_unmap_single(volatile void *vaddr, size_t len,
diff --git a/arch/arm/include/asm/global_data.h
b/arch/arm/include/asm/global_data.h
index 7611d0a..fc78c6a 100644
--- a/arch/arm/include/asm/global_data.h
+++ b/arch/arm/include/asm/global_data.h
@@ -42,6 +42,10 @@ struct arch_global_data {
unsigned long pllb_rate_hz;
unsigned long at91_pllb_usb_init;
#endif
+#ifdef CONFIG_FARADAY
+ unsigned long cpu_id;
+ unsigned long cpu_mmu;/* has mmu */
+#endif
/* static data needed by most of timer.c on ARM platforms */
unsigned long timer_rate_hz;
[U-Boot] [PATCH v5 05/14] nand: add Faraday FTNANDC021 NAND controller support
From: Kuo-Jung Su dant...@faraday-tech.com
Faraday FTNANDC021 is a integrated NAND flash controller.
It use a build-in command table to abstract the underlying
NAND flash control logic.
For example:
Issuing a command 0x10 to FTNANDC021 would result in
a page write + a read status operation.
Signed-off-by: Kuo-Jung Su dant...@faraday-tech.com
CC: Albert ARIBAUD albert.u.b...@aribaud.net
CC: Scott Wood scottw...@freescale.com
---
Changes for v5 (Part of A360/A369 patch series):
- Coding Style cleanup:
struct chip_regs __iomem *regs - struct chip_regs *regs
- For there is a strong dependancy between this and A360/A369 patch
series, it had been chained back to A360/A369 patch series.
- The latest nand_base requires the ecc.strength to be set properlly,
so this patch adds ecc.strength setting accroding to ECC algorithm.
Changes for v5 (Standalone):
- Update README for the description of CONFIG_SYS_FTNANDC021_TIMING.
- Drop redundant white space. (i.e. if (mtd-writesize = ' '4096))
Changes for v4:
- Make it a separate patch, rather then a part of
Faraday A36x patch series
- Drop the faraday/nand.h to remove dependency to
Faraday A36x patch series.
- CONFIG_SYS_NAND_TIMING - CONFIG_SYS_FTNANDC021_TIMING
- Remove non-ECC code.
- Implement private hwecc read/write_page functions
to get rid of .eccpos .eccbytes.
- Use macro constants for timeout control
Changes for v3:
- Coding Style cleanup.
- Drop macros for wirtel()/readl(), call them directly.
- Always insert a blank line between declarations and code.
- Replace all the infinite wait loop with a timeout.
- Add '__iomem' to all the declaration of HW register pointers.
- Re-write this driver with ECC enabled and correct column address
handling for OOB read/write,
- Fix issuses addressed by Scott.
Changes for v2:
- Coding Style cleanup.
- Use readl(), writel(), clrsetbits_le32() to replace REG() macros.
- Use structure based hardware registers to replace the macro constants.
- Replace BIT() with BIT_MASK().
README|6 +
drivers/mtd/nand/Makefile |1 +
drivers/mtd/nand/ftnandc021.c | 622 +
include/faraday/ftnandc021.h | 153 ++
4 files changed, 782 insertions(+)
create mode 100644 drivers/mtd/nand/ftnandc021.c
create mode 100644 include/faraday/ftnandc021.h
diff --git a/README b/README
index ac1ec44..3dbb7cc 100644
--- a/README
+++ b/README
@@ -3930,6 +3930,12 @@ Low Level (hardware related) configuration options:
- drivers/mtd/nand/ndfc.c
- drivers/mtd/nand/mxc_nand.c
+- CONFIG_SYS_FTNANDC021_TIMING
+ This option specifies an array of customized timing parameters
+ for Faraday FTNANDC021 NAND flash controller.
+ e.g.
+ #define CONFIG_SYS_FTNANDC021_TIMING { 0x02240264, 0x42054209 }
+
- CONFIG_SYS_NDFC_EBC0_CFG
Sets the EBC0_CFG register for the NDFC. If not defined
a default value will be used.
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index 8821704..f2c8b1a 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -64,6 +64,7 @@ COBJS-$(CONFIG_NAND_FSL_ELBC) += fsl_elbc_nand.o
COBJS-$(CONFIG_NAND_FSL_IFC) += fsl_ifc_nand.o
COBJS-$(CONFIG_NAND_FSL_UPM) += fsl_upm.o
COBJS-$(CONFIG_NAND_FSMC) += fsmc_nand.o
+COBJS-$(CONFIG_NAND_FTNANDC021) += ftnandc021.o
COBJS-$(CONFIG_NAND_JZ4740) += jz4740_nand.o
COBJS-$(CONFIG_NAND_KB9202) += kb9202_nand.o
COBJS-$(CONFIG_NAND_KIRKWOOD) += kirkwood_nand.o
diff --git a/drivers/mtd/nand/ftnandc021.c b/drivers/mtd/nand/ftnandc021.c
new file mode 100644
index 000..b189909
--- /dev/null
+++ b/drivers/mtd/nand/ftnandc021.c
@@ -0,0 +1,622 @@
+/*
+ * Faraday NAND Flash Controller
+ *
+ * (C) Copyright 2013 Faraday Technology
+ * Dante Su dant...@faraday-tech.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#include common.h
+#include asm/errno.h
+#include asm/io.h
+#include asm/unaligned.h
+#include nand.h
+#include malloc.h
+
+#include faraday/ftnandc021.h
+
+#define CFG_CMD_TIMEOUT (CONFIG_SYS_HZ 2) /* 250 ms */
+#define CFG_RST_TIMEOUT CONFIG_SYS_HZ /* 1 sec reset timeout */
+#define
[U-Boot] [PATCH v5 06/14] cfi_flash: use buffer length in unmap_physmem()
From: Kuo-Jung Su dant...@faraday-tech.com While the flash_detect_legacy() of drivers/mtd/cfi_flash.c feed unmap_physmem() with MAP_NOCACHE as 2nd parameter, the do_spi_flash_read_write() of common/cmd_sf.c feed unmap_physmem() with the length of the mapped buffer as 2nd parameter. It's apparently a bug, and I personally think the 2nd parameter should be the length of the mapped buffer. Signed-off-by: Kuo-Jung Su dant...@faraday-tech.com CC: Albert Aribaud albert.u.b...@aribaud.net CC: Stefan Roese s...@denx.de --- Changes for v5: - Initial commit, which is separated from arm: add MMU/D-Cache support for Faraday cores drivers/mtd/cfi_flash.c |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mtd/cfi_flash.c b/drivers/mtd/cfi_flash.c index 25f8752..0d7a5ac 100644 --- a/drivers/mtd/cfi_flash.c +++ b/drivers/mtd/cfi_flash.c @@ -1820,7 +1820,7 @@ static int flash_detect_legacy(phys_addr_t base, int banknum) break; else unmap_physmem((void *)info-start[0], - MAP_NOCACHE); + info-portwidth); } } -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v5 08/14] arm: add Faraday processor core support
From: Kuo-Jung Su dant...@faraday-tech.com This adds i/d-cache control, mmu setup bootstrap code for Faraday cores. Signed-off-by: Kuo-Jung Su dant...@faraday-tech.com CC: Albert Aribaud albert.u.b...@aribaud.net --- Changes for v5: - Initial commit which is separated from arm: add Faraday common utilities arch/arm/cpu/faraday/Makefile | 55 + arch/arm/cpu/faraday/config.mk | 33 +++ arch/arm/cpu/faraday/cpu.c | 346 arch/arm/cpu/faraday/start.S | 431 4 files changed, 865 insertions(+) create mode 100644 arch/arm/cpu/faraday/Makefile create mode 100644 arch/arm/cpu/faraday/config.mk create mode 100644 arch/arm/cpu/faraday/cpu.c create mode 100644 arch/arm/cpu/faraday/start.S diff --git a/arch/arm/cpu/faraday/Makefile b/arch/arm/cpu/faraday/Makefile new file mode 100644 index 000..ecb240a --- /dev/null +++ b/arch/arm/cpu/faraday/Makefile @@ -0,0 +1,55 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, w...@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB= $(obj)lib$(CPU).o + +src-y := cpu.o + +START = start.o +COBJS = $(src-y) + +ifdef CONFIG_SPL_BUILD +ifdef CONFIG_SPL_NO_CPU_SUPPORT_CODE +START := +endif +endif + +SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) +START := $(addprefix $(obj),$(START)) + +all: $(obj).depend $(START) $(LIB) + +$(LIB):$(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +# + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +# diff --git a/arch/arm/cpu/faraday/config.mk b/arch/arm/cpu/faraday/config.mk new file mode 100644 index 000..f03030a --- /dev/null +++ b/arch/arm/cpu/faraday/config.mk @@ -0,0 +1,33 @@ +# +# (C) Copyright 2002 +# Gary Jennejohn, DENX Software Engineering, ga...@denx.de +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float + +PLATFORM_CPPFLAGS += -march=armv4 +# = +# +# Supply options according to compiler version +# +# = +PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) +PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT) diff --git a/arch/arm/cpu/faraday/cpu.c b/arch/arm/cpu/faraday/cpu.c new file mode 100644 index 000..570b8b2 --- /dev/null +++ b/arch/arm/cpu/faraday/cpu.c @@ -0,0 +1,346 @@ +/* + * arch/arm/cpu/faraday/cpu.c + * + * (C) Copyright 2013 Faraday Technology + * Dante Su dant...@faraday-tech.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with
[U-Boot] [PATCH v5 09/14] arm: add Faraday FTINTC020 interrupt controller support
From: Kuo-Jung Su dant...@faraday-tech.com
Signed-off-by: Kuo-Jung Su dant...@faraday-tech.com
CC: Albert Aribaud albert.u.b...@aribaud.net
---
Changes for v5:
- Coding Style cleanup.
- Now the irq is always enabled inside irq_install_handler().
Changes for v4:
- Coding Style cleanup.
- Break up from [arm: add Faraday A36x SoC platform support]
Changes for v3:
- Coding Style cleanup.
- Drop macros for wirtel()/readl(), call them directly.
- Always insert a blank line between declarations and code.
- Add '__iomem' to all the declaration of HW register pointers.
Changes for v2:
- Coding Style cleanup.
- Use readl(), writel(), clrsetbits_le32() to replace REG() macros.
- Use structure based hardware registers to replace the macro constants.
- Replace BIT() with BIT_MASK().
arch/arm/cpu/faraday/Makefile|1 +
arch/arm/cpu/faraday/ftintc020.c | 156 ++
include/common.h |3 +
include/faraday/ftintc020.h | 37 +
4 files changed, 197 insertions(+)
create mode 100644 arch/arm/cpu/faraday/ftintc020.c
create mode 100644 include/faraday/ftintc020.h
diff --git a/arch/arm/cpu/faraday/Makefile b/arch/arm/cpu/faraday/Makefile
index ecb240a..35926c2 100644
--- a/arch/arm/cpu/faraday/Makefile
+++ b/arch/arm/cpu/faraday/Makefile
@@ -26,6 +26,7 @@ include $(TOPDIR)/config.mk
LIB= $(obj)lib$(CPU).o
src-y := cpu.o
+src-$(CONFIG_FTINTC020) += ftintc020.o
START = start.o
COBJS = $(src-y)
diff --git a/arch/arm/cpu/faraday/ftintc020.c b/arch/arm/cpu/faraday/ftintc020.c
new file mode 100644
index 000..542f616
--- /dev/null
+++ b/arch/arm/cpu/faraday/ftintc020.c
@@ -0,0 +1,156 @@
+/*
+ * arch/arm/cpu/faraday/ftintc020.c
+ *
+ * (C) Copyright 2013 Faraday Technology
+ * Dante Su dant...@faraday-tech.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#include common.h
+#include asm/io.h
+
+#include faraday/ftintc020.h
+
+static struct ftintc020_regs *regs = (void __iomem *)CONFIG_FTINTC020_BASE;
+
+static struct {
+ void *data;
+ void (*func)(void *data);
+} irq_hndl[64];
+
+static inline void irq_acknowledge(int irq)
+{
+ uint32_t mask = BIT_MASK(irq);
+
+ if (irq 32)
+ writel(mask, regs-irq32.scr);
+ else
+ writel(mask, regs-irq64.scr);
+}
+
+void irq_enable(int irq)
+{
+ uint32_t mask = BIT_MASK(irq);
+
+ if (irq 32)
+ setbits_le32(regs-irq32.ena, mask);
+ else
+ setbits_le32(regs-irq64.ena, mask);
+}
+
+void irq_disable(int irq)
+{
+ uint32_t mask = BIT_MASK(irq);
+
+ if (irq 32)
+ clrbits_le32(regs-irq32.ena, mask);
+ else
+ clrbits_le32(regs-irq64.ena, mask);
+}
+
+void irq_set_trigger(int irq, int edge, int low)
+{
+ uint32_t mask = BIT_MASK(irq);
+
+ if (edge) {
+ if (irq 32)
+ setbits_le32(regs-irq32.tmr, mask);
+ else
+ setbits_le32(regs-irq64.tmr, mask);
+ } else {
+ if (irq 32)
+ clrbits_le32(regs-irq32.tmr, mask);
+ else
+ clrbits_le32(regs-irq64.tmr, mask);
+ }
+
+ if (low) {
+ if (irq 32)
+ setbits_le32(regs-irq32.tlr, mask);
+ else
+ setbits_le32(regs-irq64.tlr, mask);
+ } else {
+ if (irq 32)
+ clrbits_le32(regs-irq32.tlr, mask);
+ else
+ clrbits_le32(regs-irq64.tlr, mask);
+ }
+}
+
+void do_irq(struct pt_regs *pt_regs)
+{
+ int irq;
+ uint32_t stat;
+
+ irq = 32;
+ stat = readl(regs-irq64.sr); /* IRQ 32 ~ 63 */
+ if (!stat) {
+ irq = 0;
+ stat = readl(regs-irq32.sr); /* IRQ 0 ~ 31 */
+ }
+ irq += ffs(stat) - 1;
+
+ if (irq 0) {
+ printf(interrupts: no irq!?\n);
+ return;
+ }
+
+ if (irq_hndl[irq].func)
+ irq_hndl[irq].func(irq_hndl[irq].data);
+ else
+ printf(Unhandled IRQ = %d\n, irq);
+
+ irq_acknowledge(irq);
+}
+
+void irq_install_handler(int irq,
[U-Boot] [PATCH v5 04/14] video: add Faraday FTLCDC200 LCD controller support
From: Kuo-Jung Su dant...@faraday-tech.com
Faraday FTLCDC200 Color LCD controller performs translation of
pixel-coded data into the required formats and timings to
drive a variety of single/dual mono and color LCDs.
Depending on the LCD type and mode, the unpacked data can represent:
1. an actual true display gray or color value
2. an address to a 256 x 16 bit wide palette RAM gray or color value.
The FTLCDC200 generates 4 individual interrupts for:
1. DMA FIFO underflow
2. base address update
3. vertical status
4. bus error.
There is also a single combined interrupt that is raised when any of
the individual interrupts become active.
Signed-off-by: Kuo-Jung Su dant...@faraday-tech.com
CC: Albert Aribaud albert.u.b...@aribaud.net
CC: Anatolij Gustschin ag...@denx.de
---
Changes for v5:
- Coding Style cleanup:
struct chip_regs __iomem *regs - struct chip_regs *regs
- Chain it back to Faraday A360/A369 patch series, because
Faraday A369 depends on the header file of this patch
for I2C work-around.(Enable I2C clock to prevent I2C bus hangs)
Changes for v4:
- Nothing updates
Changes for v3:
- Nothing updates
Changes for v2:
- Make it a separate patch, rather then a part of
Faraday A36x patch series
drivers/video/Makefile |1 +
drivers/video/ftlcdc200.c | 148 ++
drivers/video/ftlcdc200_panel.c | 221 +++
include/faraday/ftlcdc200.h | 179 +++
include/lcd.h | 33 ++
5 files changed, 582 insertions(+)
create mode 100644 drivers/video/ftlcdc200.c
create mode 100644 drivers/video/ftlcdc200_panel.c
create mode 100644 include/faraday/ftlcdc200.h
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index 68ff34b..92ab9d1 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -35,6 +35,7 @@ COBJS-$(CONFIG_EXYNOS_MIPI_DSIM) += exynos_mipi_dsi.o
exynos_mipi_dsi_common.o \
exynos_mipi_dsi_lowlevel.o
COBJS-$(CONFIG_EXYNOS_PWM_BL) += exynos_pwm_bl.o
COBJS-$(CONFIG_FSL_DIU_FB) += fsl_diu_fb.o videomodes.o
+COBJS-$(CONFIG_FTLCDC200) += ftlcdc200.o ftlcdc200_panel.o
COBJS-$(CONFIG_MPC8XX_LCD) += mpc8xx_lcd.o
COBJS-$(CONFIG_PXA_LCD) += pxa_lcd.o
COBJS-$(CONFIG_S6E8AX0) += s6e8ax0.o
diff --git a/drivers/video/ftlcdc200.c b/drivers/video/ftlcdc200.c
new file mode 100644
index 000..331a35f
--- /dev/null
+++ b/drivers/video/ftlcdc200.c
@@ -0,0 +1,148 @@
+/*
+ * Faraday LCD Controller
+ *
+ * (C) Copyright 2013 Faraday Technology
+ * Dante Su dant...@faraday-tech.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#include common.h
+#include asm/io.h
+#include lcd.h
+#include faraday/ftlcdc200.h
+
+#ifndef CONFIG_FTLCDC200_FREQ
+#define CONFIG_FTLCDC200_FREQ clock_get_rate(AHB_CLK)
+#endif
+
+static struct ftlcdc200_regs *regs = (void __iomem *)CONFIG_FTLCDC200_BASE;
+
+static void ftlcdc2xx_fixup(struct vidinfo *panel)
+{
+ u_long ht, vt;
+ u_long div, clk;
+ long fps = 60;
+ long upper = 32767;
+ long lower = -32767;
+
+ if (panel-vl_fps)
+ return;
+
+ /* If it's serial mode */
+ if (panel-vl_serial SPPR_SERIAL)
+ clk = CONFIG_FTLCDC200_FREQ / 3;
+ else
+ clk = CONFIG_FTLCDC200_FREQ;
+
+ /* Derive clock divisor */
+ ht = panel-vl_col + panel-vl_hbp + panel-vl_hfp + panel-vl_hsw;
+ vt = panel-vl_row + panel-vl_vbp + panel-vl_vfp + panel-vl_vsw;
+ for (div = 1; div = 0x7f; ++div) {
+ long tmp = (clk / div / ht / vt);
+ if (fps tmp) {
+ lower = tmp;
+ break;
+ }
+ upper = tmp;
+ }
+ if ((upper - fps) (fps - lower))
+ div += 1;
+ div = (div 1) ? (div - 1) : div;
+
+ /* Update hardware register cache */
+ panel-vl_polarity = (panel-vl_polarity (~0x7f00))
+ | ((div - 1) 8);
+
+ /* Derive real frame rate */
+ panel-vl_fps = (u_long)(clk / div / ht / vt);
+
+ debug(ftlcdc200: %s\n, panel-vl_name);
+ debug(ftlcdc200: fps=%u (%u FPS %u)\n,
+ (unsigned int)panel-vl_fps,
+
[U-Boot] [PATCH v5 12/14] arm: add Faraday specific boot command
From: Kuo-Jung Su dant...@faraday-tech.com At the time of writting, none of Faraday NAND SPI controllers supports XIP (eXecute In Place). So the Faraday A360/A369 SoC has to implement a 1st level bootstrap code stored in the embedded ROM inside the SoC. After power-on, the ROM code (1st level bootstrap code) would load the 2nd bootstrap code into SRAM without any SDRAM initialization. The 2nd bootstrap code would then initialize SDRAM and load the generic firmware (u-boot/linux) into SDRAM, and finally make a long-jump to the firmware. Which means the SPL design of U-boot would never fit to A360/A369, since it's usually not possible to alter a embedded ROM code. And because both the 1st 2nd level bootstrap code use the private Faraday Firmware Image Format, it would be better to drop U-boot image support to simplify the design. Signed-off-by: Kuo-Jung Su dant...@faraday-tech.com CC: Albert Aribaud albert.u.b...@aribaud.net --- Changes for v5: - Rename from 'arm: add Faraday firmware image utility' into 'arm: add Faraday specific boot command' - Add missing CRC check to the command 'bootfa'. - Add rationale to the command 'bootfa'. Changes for v4: - Coding Style cleanup. - Break up from [arm: add Faraday A36x SoC platform support] Changes for v3: - Coding Style cleanup. - Always insert a blank line between declarations and code. Changes for v2: - Coding Style cleanup. arch/arm/cpu/faraday/Makefile |2 +- arch/arm/cpu/faraday/cmd_bootfa.c | 276 + arch/arm/cpu/faraday/fwimage.h| 47 +++ arch/arm/cpu/faraday/fwimage2.h | 67 + arch/arm/cpu/u-boot.lds | 11 ++ 5 files changed, 402 insertions(+), 1 deletion(-) create mode 100644 arch/arm/cpu/faraday/cmd_bootfa.c create mode 100644 arch/arm/cpu/faraday/fwimage.h create mode 100644 arch/arm/cpu/faraday/fwimage2.h diff --git a/arch/arm/cpu/faraday/Makefile b/arch/arm/cpu/faraday/Makefile index 6b96e32..ef6a72e 100644 --- a/arch/arm/cpu/faraday/Makefile +++ b/arch/arm/cpu/faraday/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB= $(obj)lib$(CPU).o -src-y := cpu.o +src-y := cpu.o cmd_bootfa.o src-$(CONFIG_FTINTC020) += ftintc020.o src-$(CONFIG_FTTMR010)+= fttmr010.o src-$(CONFIG_FTPWMTMR010) += ftpwmtmr010.o diff --git a/arch/arm/cpu/faraday/cmd_bootfa.c b/arch/arm/cpu/faraday/cmd_bootfa.c new file mode 100644 index 000..cdc47a3 --- /dev/null +++ b/arch/arm/cpu/faraday/cmd_bootfa.c @@ -0,0 +1,276 @@ +/* + * arch/arm/cpu/faraday/cmd_bootfa.c + * + * This command is used to boot faraday firmware from MMC/USB/SPI/NAND/NOR + * + * (C) Copyright 2013 Faraday Technology + * Dante Su dant...@faraday-tech.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +/* + * At the time of writting, none of Faraday NAND SPI controllers + * supports XIP (eXecute In Place). So the Faraday A360/A369 SoC has + * to implement a 1st level bootstrap code stored in the embedded ROM + * inside the SoC. + * + * After power-on, the ROM code (1st level bootstrap code) would load + * the 2nd bootstrap code into SRAM without any SDRAM initialization. + * + * The 2nd bootstrap code would then initialize SDRAM and load the + * generic firmware (u-boot/linux) into SDRAM, and finally make + * a long-jump to the firmware. + * + * Which means the SPL design of U-boot would never fit to A360/A369, + * since it's usually not possible to alter a embedded ROM code. + * And because both the 1st 2nd level bootstrap code use the private + * Faraday Firmware Image Format, it would be better to drop U-boot + * image support to simplify the design. + * + * The Faraday Firmware Image Format uses a 1 KB (1024 Bytes) header: + * + * ++ 0x + * | MAGIC | Magic number + * ++ 0x0004 + * | HDR LENGTH | The size of this header + * ++ 0x0008 + * || + * | SYS PARAMETERS | A set of (addr, data) for 32-bit register write, + * || which is for SDRAM initialization and timing control. + * ++ 0x0108 + * || + * | PART TABLE | A partition table with max. 10 entries. + * || + * ++ 0x03D8 + * | HDR CHECKSUM | Header Checksum (CRC32) + *
[U-Boot] [PATCH v5 10/14] arm: add Faraday FTTMR010 timer support
From: Kuo-Jung Su dant...@faraday-tech.com
Signed-off-by: Kuo-Jung Su dant...@faraday-tech.com
CC: Albert Aribaud albert.u.b...@aribaud.net
---
Changes for v5:
- Drop IRQ dependant implementation
- Use gd-arch.timer_rate_hz for timer clock source
- Use gd-arch.tbl for timestamp
Changes for v4:
- Coding Style cleanup.
- Break up from [arm: add Faraday A36x SoC platform support]
Changes for v3:
- Coding Style cleanup.
- Drop macros for wirtel()/readl(), call them directly.
- Always insert a blank line between declarations and code.
- Add '__iomem' to all the declaration of HW register pointers.
Changes for v2:
- Coding Style cleanup.
- Use readl(), writel(), clrsetbits_le32() to replace REG() macros.
- Use structure based hardware registers to replace the macro constants.
- Replace BIT() with BIT_MASK().
arch/arm/cpu/faraday/Makefile |1 +
arch/arm/cpu/faraday/fttmr010.c | 136 +++
include/faraday/fttmr010.h | 17 +
3 files changed, 154 insertions(+)
create mode 100644 arch/arm/cpu/faraday/fttmr010.c
diff --git a/arch/arm/cpu/faraday/Makefile b/arch/arm/cpu/faraday/Makefile
index 35926c2..658d9ed 100644
--- a/arch/arm/cpu/faraday/Makefile
+++ b/arch/arm/cpu/faraday/Makefile
@@ -27,6 +27,7 @@ LIB = $(obj)lib$(CPU).o
src-y := cpu.o
src-$(CONFIG_FTINTC020) += ftintc020.o
+src-$(CONFIG_FTTMR010)+= fttmr010.o
START = start.o
COBJS = $(src-y)
diff --git a/arch/arm/cpu/faraday/fttmr010.c b/arch/arm/cpu/faraday/fttmr010.c
new file mode 100644
index 000..9d6f7ac
--- /dev/null
+++ b/arch/arm/cpu/faraday/fttmr010.c
@@ -0,0 +1,136 @@
+/*
+ * arch/arm/cpu/faraday/fttmr010.c
+ *
+ * (C) Copyright 2013 Faraday Technology
+ * Dante Su dant...@faraday-tech.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#include common.h
+#include asm/io.h
+#include faraday/fttmr010.h
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct fttmr010 *regs = (void __iomem *)CONFIG_FTTMR010_BASE;
+
+void udelay_masked(unsigned long usec)
+{
+ ulong freq = gd-arch.timer_rate_hz;
+
+ /* Disable Timer2 */
+ clrbits_le32(regs-cr, FTTMR010_TM2_CRMASK);
+ /* Disable Timer2 interrupts */
+ writel(FTTMR010_TM2_ISRMASK, regs-interrupt_mask);
+ /* Clear Timer2 interrupts */
+ writel(FTTMR010_TM2_ISRMASK, regs-interrupt_state);
+
+ /* Configure Timer2 */
+ writel((freq / 100) * usec, regs-timer2_counter);
+ writel(0, regs-timer2_load);
+ writel(0, regs-timer2_match1);
+ writel(0, regs-timer2_match2);
+
+ /* Enable Timer2 */
+ setbits_le32(regs-cr,
+ FTTMR010_TM2_OFENABLE | FTTMR010_TM2_ENABLE);
+
+ /* Wait until timeout */
+ while (!(readl(regs-interrupt_state) FTTMR010_TM2_ISRMASK))
+ ;
+}
+
+void reset_timer_masked(void)
+{
+ ulong freq = gd-arch.timer_rate_hz;
+
+ /* Disable Timer1 */
+ clrbits_le32(regs-cr, FTTMR010_TM1_CRMASK);
+
+ /* Disable Clear Timer1 interrupts */
+ writel(FTTMR010_TM1_ISRMASK, regs-interrupt_mask);
+ writel(FTTMR010_TM1_ISRMASK, regs-interrupt_state);
+
+ /* Setup a longest periodic timer */
+ writel((0x / freq) * freq, regs-timer1_counter);
+ writel((0x / freq) * freq, regs-timer1_load);
+
+ writel(0, regs-timer1_match1);
+ writel(0, regs-timer1_match2);
+
+ /* Disable match interrupts */
+ writel(FTTMR010_TM1_MATCH1 | FTTMR010_TM1_MATCH2,
+ regs-interrupt_mask);
+
+ /* Enable Timer1 with overflow interrupt */
+ setbits_le32(regs-cr,
+ FTTMR010_TM1_OFENABLE | FTTMR010_TM1_ENABLE);
+}
+
+ulong get_timer_masked(void)
+{
+ ulong freq = gd-arch.timer_rate_hz;
+ ulong secs = 0x / freq;
+ ulong ms = freq / CONFIG_SYS_HZ;
+
+ if (readl(regs-interrupt_state) FTTMR010_TM1_ISRMASK) {
+ writel(FTTMR010_TM1_ISRMASK, regs-interrupt_state);
+ gd-arch.tbl += secs * CONFIG_SYS_HZ;
+ }
+
+ return gd-arch.tbl
+ + ((secs * freq) - readl(regs-timer1_counter)) / ms;
+}
+
+int timer_init(void)
+{
+ gd-arch.tbl = 0;
+ reset_timer_masked();
+ return 0;
+}
+
+void reset_timer(void)
+{
+
[U-Boot] [PATCH v5 13/14] mmc: ftsdc010_mci: clk_get_rate() - clock_get_rate()
From: Kuo-Jung Su dant...@faraday-tech.com This updates ftsdc010_mci.c for latest Faraday clock APIs. Signed-off-by: Kuo-Jung Su dant...@faraday-tech.com CC: Albert Aribaud albert.u.b...@aribaud.net CC: Andy Fleming aflem...@gmail.com --- Changes for v5: - Initial commit drivers/mmc/ftsdc010_mci.c |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mmc/ftsdc010_mci.c b/drivers/mmc/ftsdc010_mci.c index 562b14a..0a0a19b 100644 --- a/drivers/mmc/ftsdc010_mci.c +++ b/drivers/mmc/ftsdc010_mci.c @@ -363,7 +363,7 @@ int ftsdc010_mmc_init(int devid) #ifdef CONFIG_SYS_CLK_FREQ chip-sclk = CONFIG_SYS_CLK_FREQ; #else - chip-sclk = clk_get_rate(SDC); + chip-sclk = clock_get_rate(MMC_CLK); #endif mmc-voltages = MMC_VDD_32_33 | MMC_VDD_33_34; -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v5 11/14] arm: add Faraday FTPWMTMR010 timer support
From: Kuo-Jung Su dant...@faraday-tech.com
Signed-off-by: Kuo-Jung Su dant...@faraday-tech.com
CC: Albert Aribaud albert.u.b...@aribaud.net
---
Changes for v5:
- Drop IRQ dependant implementation
- Use gd-arch.timer_rate_hz for timer clock source
- Use gd-arch.tbl for timestamp
Changes for v4:
- Coding Style cleanup.
- Break up from [arm: add Faraday A36x SoC platform support]
Changes for v3:
- Coding Style cleanup.
- Drop macros for wirtel()/readl(), call them directly.
- Always insert a blank line between declarations and code.
- Add '__iomem' to all the declaration of HW register pointers.
Changes for v2:
- Coding Style cleanup.
- Use readl(), writel(), clrsetbits_le32() to replace REG() macros.
- Use structure based hardware registers to replace the macro constants.
- Replace BIT() with BIT_MASK().
arch/arm/cpu/faraday/Makefile |1 +
arch/arm/cpu/faraday/ftpwmtmr010.c | 128
include/faraday/ftpwmtmr010.h | 41
3 files changed, 170 insertions(+)
create mode 100644 arch/arm/cpu/faraday/ftpwmtmr010.c
create mode 100644 include/faraday/ftpwmtmr010.h
diff --git a/arch/arm/cpu/faraday/Makefile b/arch/arm/cpu/faraday/Makefile
index 658d9ed..6b96e32 100644
--- a/arch/arm/cpu/faraday/Makefile
+++ b/arch/arm/cpu/faraday/Makefile
@@ -28,6 +28,7 @@ LIB = $(obj)lib$(CPU).o
src-y := cpu.o
src-$(CONFIG_FTINTC020) += ftintc020.o
src-$(CONFIG_FTTMR010)+= fttmr010.o
+src-$(CONFIG_FTPWMTMR010) += ftpwmtmr010.o
START = start.o
COBJS = $(src-y)
diff --git a/arch/arm/cpu/faraday/ftpwmtmr010.c
b/arch/arm/cpu/faraday/ftpwmtmr010.c
new file mode 100644
index 000..8f8185e
--- /dev/null
+++ b/arch/arm/cpu/faraday/ftpwmtmr010.c
@@ -0,0 +1,128 @@
+/*
+ * arch/arm/cpu/faraday/ftpwmtmr010.c
+ *
+ * (C) Copyright 2013 Faraday Technology
+ * Dante Su dant...@faraday-tech.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#include common.h
+#include asm/io.h
+
+#include faraday/ftpwmtmr010.h
+
+#ifdef CONFIG_A369_FA606TE_PLATFORM
+#define TIMER_ID4
+#else
+#define TIMER_ID0
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct ftpwmtmr010_regs *regs = (void __iomem *)CONFIG_FTPWMTMR010_BASE;
+
+void udelay_masked(unsigned long usec)
+{
+ int id = TIMER_ID + 1;
+ ulong freq = gd-arch.timer_rate_hz;
+
+ /* timer re-start */
+ writel(0, regs-t[id].ctrl);
+ writel(BIT_MASK(id), regs-isr);
+ writel(0, regs-t[id].cmpb);
+ writel((freq / 100) * usec, regs-t[id].cntb);
+ writel(CTRL_INTEN | CTRL_START | CTRL_UPDATE, regs-t[id].ctrl);
+
+ /* wait for timer interrupt */
+ while (!(readl(regs-isr) BIT_MASK(id)))
+ ;
+
+ /* timer disabled */
+ writel(0, regs-t[id].ctrl);
+ writel(BIT_MASK(id), regs-isr);
+}
+
+void reset_timer_masked(void)
+{
+ int id = TIMER_ID;
+ ulong freq = gd-arch.timer_rate_hz;
+
+ writel(0, regs-t[id].ctrl);
+ writel(BIT_MASK(id), regs-isr);
+
+ /* setup a longest periodic timer */
+ writel((0x / freq) * freq, regs-t[id].cntb);
+
+ writel(0, regs-t[id].cmpb);
+ writel(CTRL_AUTORELOAD | CTRL_INTEN | CTRL_START | CTRL_UPDATE,
+ regs-t[id].ctrl);
+}
+
+ulong get_timer_masked(void)
+{
+ int id = TIMER_ID;
+ ulong freq = gd-arch.timer_rate_hz;
+ ulong secs = 0x / freq;
+ ulong ms = freq / CONFIG_SYS_HZ;
+
+ if (readl(regs-isr) BIT_MASK(id)) {
+ writel(BIT_MASK(id), regs-isr);
+ gd-arch.tbl += secs * CONFIG_SYS_HZ;
+ }
+
+ return gd-arch.tbl
+ + ((secs * freq - readl(regs-t[id].cnto)) / ms);
+}
+
+int timer_init(void)
+{
+ gd-arch.tbl = 0;
+ reset_timer_masked();
+ return 0;
+}
+
+void reset_timer(void)
+{
+ reset_timer_masked();
+}
+
+ulong get_timer(ulong base)
+{
+ return get_timer_masked() - base;
+}
+
+void __udelay(unsigned long usec)
+{
+ udelay_masked(usec);
+}
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On ARM it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+ return get_timer(0);
+}
+
+/*
+ * This function is derived from PowerPC code
Re: [U-Boot] [RFC] Safe Linux Updater
Dear Alexandre In message 130325823.452426.1371459938406.javamail.r...@openwide.fr you wrote: One month ago, I sent a first request for comments about an open source automatic updater for embedded systems using U-boot: the goal of this project was to split a flash memory or hard disk drive in multiple partition (2 or more) and install a new kern el and/or root filesystem on an empty or outdated partition. Could you please restrict yourline length to some 70 characters or so? Thanks!! The u-boot environment would contain some variables to handle name, state and boot attempt count of each partition of the system. I would use CONFIG_ENV_OFFSET_REDUND to make writing on environment powerfail-safe. The environment contains 3 variables by partitions: - part_X_flag: handles state of partition X. It can be NONE for empty partition, OK for working system, LOCK for locking a partition to install a new system on it, UPDATED for new system version (we count boot attempts for this partition) and BAD for ba d system which doesn't work. - part_X_count: handles boot attempts on partition X. - part_X_cmd: U-boot command used to boot on the partition X (e.g. partition address in flash). Environment contains also another variable: boot_seq which handles a list of bootable partition sorted by version. This sounds like a bad idea, for two reasons: 1) U-Boot already supports the boot count feature (but of course this hardware-specific as you need to find persistent storage for the counter). However, this does not consider which exact boot command has been executed (in your case: what the used boot partition was), it just counts the number of resets after the last power-on. Actually this is all you should need. Please note that this is a feature standardized for example in the Open Source Development Labs Carrier Grade Linux Requirements Definition, which says something like: CGL shall provide support for detecting a repeating reboot cycle due to recurring failures and will go to an offline state if this occurs. 2) Defining the boot counter as part of the envrionment requires automatic writes to the environment for each reset / reboot of the board. This is considered a bad idea, as it causes excessive flash wear. Normally you want to avoid all erase / write operations to the boot loader and it's private data structures in the process of a normal reboot / reset. Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de Microsoft Multitasking: several applications can crash at the same time. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 3/3] arm: omap3: Add SPL support to cm_t35
On Mon, Jun 17, 2013 at 02:53:27PM +0300, Igor Grinberg wrote: Hi Stefan, On 06/14/13 11:55, Stefan Roese wrote: Add SPL U-Boot support to replace x-loader on the Compulab cm_t35 board. Currently only the 256MiB SDRAM board versions are supported. Tested by booting via MMC and NAND. Signed-off-by: Stefan Roese s...@denx.de Cc: Tom Rini tr...@ti.com Cc: Igor Grinberg grinb...@compulab.co.il [snip] +/* + * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM + * 64 bytes before this address should be set aside for u-boot.img's + * header. That is 0x800FFFC0--0x8010 should not be used for any + * other needs. + */ +#define CONFIG_SYS_TEXT_BASE 0x8010 Now this is a problem. This breaks the backward compatibility with our X-Loader and we cannot just switch to 8010... And thinking back to when I was doing more OMAP3 conversions, there's no requirement to break compatibility with x-loader either. You just need to take care where you place things, see doc/SPL/README.omap3 for the SPL and X-Loader compatible setup. -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] ARM: mxs: Make the console buffer smaller
Hello Stefano, I'm CCing Wolfgang, Hi Marek, On 15/06/2013 23:41, Marek Vasut wrote: Using 1024 bytes for console buffer is unnecessarily too much, lower the amount for all MXS boards to 256. Signed-off-by: Marek Vasut ma...@denx.de Cc: Fabio Estevam fabio.este...@freescale.com Cc: Lauri Hintsala lauri.hints...@bluegiga.com Cc: Otavio Salvador ota...@ossystems.com.br Cc: Stefano Babic sba...@denx.de --- include/configs/mxs.h |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) Note: This depends on http://patchwork.ozlabs.org/patch/251631/ diff --git a/include/configs/mxs.h b/include/configs/mxs.h index a684166..161d89d 100644 --- a/include/configs/mxs.h +++ b/include/configs/mxs.h @@ -92,7 +92,7 @@ #ifndef CONFIG_SYS_PROMPT #define CONFIG_SYS_PROMPT = #endif -#define CONFIG_SYS_CBSIZE 1024/* Console I/O buffer size */ +#define CONFIG_SYS_CBSIZE 256 /* Console I/O buffer size */ #define CONFIG_SYS_PBSIZE \ (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print buffer size */ I am missing something: which is the real advantage to reduce the console buffer ? I do not think that the saved memory is worth, and on the other side more elaborated scripts (usings nested if-then-else) are quite long nowadays. True, but so far they didn't overflow this limit I believe. Some of them are hanging on the verge of blowing it though, good point. Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] ARM: mxs: Make the console buffer smaller
Hallo Marek, On 17/06/2013 14:51, Marek Vasut wrote: I am missing something: which is the real advantage to reduce the console buffer ? I do not think that the saved memory is worth, and on the other side more elaborated scripts (usings nested if-then-else) are quite long nowadays. True, but so far they didn't overflow this limit I believe. Some of them are hanging on the verge of blowing it though, good point. I think that a point to consider is if all scripts are already provided or we let the user/owner of the board to add his own scripts, as I presume. It is pity if he cannot do what u-boot really supports only to save some bytes. Best regards, Stefano -- = DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de = ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] ARM: mxs: Make the console buffer smaller
On Mon, Jun 17, 2013 at 10:07 AM, Stefano Babic sba...@denx.de wrote: Hallo Marek, On 17/06/2013 14:51, Marek Vasut wrote: I am missing something: which is the real advantage to reduce the console buffer ? I do not think that the saved memory is worth, and on the other side more elaborated scripts (usings nested if-then-else) are quite long nowadays. True, but so far they didn't overflow this limit I believe. Some of them are hanging on the verge of blowing it though, good point. I think that a point to consider is if all scripts are already provided or we let the user/owner of the board to add his own scripts, as I presume. It is pity if he cannot do what u-boot really supports only to save some bytes. I think this is more than enough to justify a bigger buffer. -- Otavio Salvador O.S. Systems http://www.ossystems.com.brhttp://projetos.ossystems.com.br Mobile: +55 (53) 9981-7854Mobile: +1 (347) 903-9750 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [RFC] Safe Linux Updater
Dear Wolfgang, I havn't seen the scripts of Alexandre but it sounds something like what we have already implemented. Wolfgang Denk wrote: Please note that this is a feature standardized for example in the Open Source Development Labs Carrier Grade Linux Requirements Definition, which says something like: CGL shall provide support for detecting a repeating reboot cycle due to recurring failures and will go to an offline state if this occurs. As I read Alexandre, the aim is to revert to a previous functional image, not to go to an offline state. Normally you want to avoid all erase / write operations to the boot loader and it's private data structures in the process of a normal reboot / reset. But a failing boot is not a normal boot. This should only occur when an update fails. After a maximum number of failing boots, the old functional image is used and there is no need to update the counter any more. Best Regards, Mats ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 3/3] arm: omap3: Add SPL support to cm_t35
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 On 06/17/13 15:38, Tom Rini wrote: On Mon, Jun 17, 2013 at 02:53:27PM +0300, Igor Grinberg wrote: Hi Stefan, On 06/14/13 11:55, Stefan Roese wrote: Add SPL U-Boot support to replace x-loader on the Compulab cm_t35 board. Currently only the 256MiB SDRAM board versions are supported. Tested by booting via MMC and NAND. Signed-off-by: Stefan Roese s...@denx.de Cc: Tom Rini tr...@ti.com Cc: Igor Grinberg grinb...@compulab.co.il [snip] +/* + * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM + * 64 bytes before this address should be set aside for u-boot.img's + * header. That is 0x800FFFC0--0x8010 should not be used for any + * other needs. + */ +#define CONFIG_SYS_TEXT_BASE 0x8010 Now this is a problem. This breaks the backward compatibility with our X-Loader and we cannot just switch to 8010... And thinking back to when I was doing more OMAP3 conversions, there's no requirement to break compatibility with x-loader either. You just need to take care where you place things, see doc/SPL/README.omap3 for the SPL and X-Loader compatible setup. Actually, I was thinking about adding a target in boards.cfg, but if we can make both (X-Loader and SPL) live in piece, then IMO, we should go for it. Thanks for the pointer! - -- Regards, Igor. -BEGIN PGP SIGNATURE- Version: GnuPG v2.0.17 (GNU/Linux) iQIcBAEBAgAGBQJRvxFwAAoJEBDE8YO64Efa0DsP/R0053VMz10juUsP38dFb7lb xcKQFmvJe0W1skIJZmFAa+1gUNYf1EMcHGx7JqIwtsVDBsHxK5fzAbj1mU4RbQUx zY5nmGtKlfiV1xPMQSrwo6rDxX3pPRId5rfC9sxpCwdliCFzvypfP6mPTcGm10db 2MygHvm+cXU1hNi7JPF3eRCVuqDhO/mrnES0MD2tkxfF88sJOYvvCBSLndJy+cF2 8FrnAC1w+4xnUqT33VTAf/P1+/2qzFcnrVXRNBn/fRfvahT91EuGwWrzqRrvvwNd lMTwSreO4RvvG6pa0RGgu6I6/6Ao5CYbjkznDzeyMl+001a2hxIlwuXb+yJaNneN lISSWSAnTT6AcoIRDGVOmFkWOzfmgZoqsikeBKA22jyzZymoXWwhJ5RM5/l0/OKu V7/X2vWuzTeAzbOlRMof25DtLk/vXdYA4vt6b9iyIffVPSq9WWGGJhPhgSfQ5rW1 S8k1JXbIn99TY6igyaK+7rf42FxOMZLyPdKH53qCM2G80XGy+Df7y2ZHyv8ssQRY f5w2CYSDo4ph01tGo3hI5bvz671yAoBUs6+/7ERofJ9gx2R0XOKUhfY6znIXeDMl o8AqyYpXTboDG9FRH0cE6Lud4CUt2sY2NQ/CkfdXyYIfeOGVqWUbLefc9cZNBGDe 4AoUHehr5tgIFNiT5yP+ =X70e -END PGP SIGNATURE- ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 3/3] arm: omap3: Add SPL support to cm_t35
On 17.06.2013 15:38, Igor Grinberg wrote: +/* + * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM + * 64 bytes before this address should be set aside for u-boot.img's + * header. That is 0x800FFFC0--0x8010 should not be used for any + * other needs. + */ +#define CONFIG_SYS_TEXT_BASE 0x8010 Now this is a problem. This breaks the backward compatibility with our X-Loader and we cannot just switch to 8010... And thinking back to when I was doing more OMAP3 conversions, there's no requirement to break compatibility with x-loader either. You just need to take care where you place things, see doc/SPL/README.omap3 for the SPL and X-Loader compatible setup. Actually, I was thinking about adding a target in boards.cfg, but if we can make both (X-Loader and SPL) live in piece, then IMO, we should go for it. I just did a quick check with moving CONFIG_SYS_TEXT_BASE back to 0x80008000 and CONFIG_SPL_BSS_START_ADDR up to 0x8010. Seems to work just fine. I'll submit a new version in a short while. Thanks, Stefan ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [RFC] Safe Linux Updater
Hi Mats, On 17/06/2013 15:25, Mats Kärrman wrote: Dear Wolfgang, I havn't seen the scripts of Alexandre but it sounds something like what we have already implemented. Wolfgang Denk wrote: Please note that this is a feature standardized for example in the Open Source Development Labs Carrier Grade Linux Requirements Definition, which says something like: CGL shall provide support for detecting a repeating reboot cycle due to recurring failures and will go to an offline state if this occurs. As I read Alexandre, the aim is to revert to a previous functional image, not to go to an offline state. This is already done in u-boot checking the value of the boot counter (in not persistency storage) and calling a script that switch back to the previous copy, if any. I find that the proposal does not scale well. Having partitions on a disk / SDCARd is a case, but we have several different way to boot. Think about kernel / rootfs into UBI or UBIFS, or saved as raw data in other kind of storages (NOR, SPI,..). Because we are talking about the feature updating, this should be abstracted from the specific case to be generalized in U-Boot. Normally you want to avoid all erase / write operations to the boot loader and it's private data structures in the process of a normal reboot / reset. But a failing boot is not a normal boot. This should only occur when an update fails. There are runtime conditions that can cause the boot to fail, due for example to power-supply. Or a degrading of the resources (flash gets wrong), and so on. Even if a failure due to a wrong update is a common case to have a failing boot, this is not the only use case. Best regards, Stefano Babic -- = DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de = ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 3/3] arm: omap3: Add SPL support to cm_t35
Add SPL U-Boot support to replace x-loader on the Compulab cm_t35
board. Currently only the 256MiB SDRAM board versions are supported.
Tested by booting via MMC and NAND.
Signed-off-by: Stefan Roese s...@denx.de
Cc: Tom Rini tr...@ti.com
Cc: Igor Grinberg grinb...@compulab.co.il
---
v2:
- Change CONFIG_SYS_TEXT_BASE back to 0x80008000 for x-loader
compatibility
- Change CONFIG_SPL_BSS_START_ADDR to 0x8010 to not overlap
with TEXT_BASE now
board/compulab/cm_t35/cm_t35.c | 18 +++-
include/configs/cm_t35.h | 64 --
2 files changed, 79 insertions(+), 3 deletions(-)
diff --git a/board/compulab/cm_t35/cm_t35.c b/board/compulab/cm_t35/cm_t35.c
index b0b80e5..cd7882e 100644
--- a/board/compulab/cm_t35/cm_t35.c
+++ b/board/compulab/cm_t35/cm_t35.c
@@ -120,6 +120,22 @@ static inline int splash_load_from_nand(void)
}
#endif /* CONFIG_CMD_NAND */
+#ifdef CONFIG_SPL_BUILD
+/*
+ * Routine: get_board_mem_timings
+ * Description: If we use SPL then there is no x-loader nor config header
+ * so we have to setup the DDR timings ourself on both banks.
+ */
+void get_board_mem_timings(struct board_sdrc_timings *timings)
+{
+ timings-mr = MICRON_V_MR_165;
+ timings-mcfg = MICRON_V_MCFG_165(256 20);
+ timings-ctrla = MICRON_V_ACTIMA_165;
+ timings-ctrlb = MICRON_V_ACTIMB_165;
+ timings-rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
+}
+#endif
+
int board_splash_screen_prepare(void)
{
char *env_splashimage_value;
@@ -443,7 +459,7 @@ void set_muxconf_regs(void)
cm_t3730_set_muxconf();
}
-#ifdef CONFIG_GENERIC_MMC
+#if defined(CONFIG_GENERIC_MMC) !defined(CONFIG_SPL_BUILD)
int board_mmc_getcd(struct mmc *mmc)
{
u8 val;
diff --git a/include/configs/cm_t35.h b/include/configs/cm_t35.h
index c6e357a..1dc2d5b 100644
--- a/include/configs/cm_t35.h
+++ b/include/configs/cm_t35.h
@@ -40,8 +40,6 @@
#define CONFIG_OMAP_GPIO
#define CONFIG_CM_T3X /* working with CM-T35 and CM-T3730 */
-#define CONFIG_SYS_TEXT_BASE 0x80008000
-
#define CONFIG_SDRC/* The chip has SDRC controller */
#include asm/arch/cpu.h /* get chip and board defs */
@@ -341,4 +339,66 @@
#define CONFIG_BMP_16BPP
#define CONFIG_SPLASH_SCREEN_PREPARE
+/* Defines for SPL */
+#define CONFIG_SPL
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_NAND_SIMPLE
+
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR0x300 /* address
0x6 */
+#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
+#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1
+#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME u-boot.img
+
+#define CONFIG_SPL_BOARD_INIT
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBDISK_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SPL_FAT_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_BASE
+#define CONFIG_SPL_NAND_DRIVERS
+#define CONFIG_SPL_NAND_ECC
+#define CONFIG_SPL_GPIO_SUPPORT
+#define CONFIG_SPL_POWER_SUPPORT
+#define CONFIG_SPL_OMAP3_ID_NAND
+#define CONFIG_SPL_LDSCRIPT$(CPUDIR)/omap-common/u-boot-spl.lds
+
+/* NAND boot config */
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_PAGE_COUNT 64
+#define CONFIG_SYS_NAND_PAGE_SIZE 2048
+#define CONFIG_SYS_NAND_OOBSIZE64
+#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
+/*
+ * Use the ECC/OOB layout from omap_gpmc.h that matches your chip:
+ * SP vs LP, 8bit vs 16bit: GPMC_NAND_HW_ECC_LAYOUT
+ */
+#define CONFIG_SYS_NAND_ECCPOS { 1, 2, 3, 4, 5, 6, 7, 8, 9, \
+10, 11, 12 }
+#define CONFIG_SYS_NAND_ECCSIZE512
+#define CONFIG_SYS_NAND_ECCBYTES 3
+
+#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_NAND_U_BOOT_OFFS0x8
+
+#define CONFIG_SPL_TEXT_BASE 0x40200800
+#define CONFIG_SPL_MAX_SIZE(54 * 1024) /* 8 KB for stack */
+#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
+
+/*
+ * Use 0x80008000 as TEXT_BASE here for compatibility reasons with the
+ * older x-loader implementations. And move the BSS area so that it
+ * doesn't overlap with TEXT_BASE.
+ */
+#define CONFIG_SYS_TEXT_BASE 0x80008000
+#define CONFIG_SPL_BSS_START_ADDR 0x8010
+#define CONFIG_SPL_BSS_MAX_SIZE0x8 /* 512 KB */
+
+#define CONFIG_SYS_SPL_MALLOC_START0x80208000
+#define CONFIG_SYS_SPL_MALLOC_SIZE 0x10
+
#endif /* __CONFIG_H */
--
1.8.2.3
___
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Re: [U-Boot] [PATCH] image: Use ENOENT instead of ENOMEDIUM for better compatibility
On Sun, Jun 16, 2013 at 07:46:49AM -0700, Simon Glass wrote: This error may not be defined on some platforms such as MacOS so host compilation will fail. Use one of the more common errors instead. Signed-off-by: Simon Glass s...@chromium.org Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [RFC] Safe Linux Updater
Dear Mats, In message ed3e0bcacd909541ba94a34c4a164d4c4fc91...@post.tritech.se you wrote: I havn't seen the scripts of Alexandre but it sounds something like what we have already implemented. I haven'ty seen the scripts either, but this is something that has been implemented many times before, with many variations depending on specific project needs. But as I mentioned before, most users do not push such scripts into mainline... Please note that this is a feature standardized for example in the Open Source Development Labs Carrier Grade Linux Requirements Definition, which says something like: CGL shall provide support for detecting a repeating reboot cycle due to recurring failures and will go to an offline state if this occurs. As I read Alexandre, the aim is to revert to a previous functional image, Yes, of course. And the boot counter is the mechanism that will decide when to do that. not to go to an offline state. Indeed. U-Boots boot counter will select an alternative boot command in this case - you can use this to hard hang or power off the board and so implement strictly CGL conformant behaviour, or you can do somthing else like fall back to the previous version. Normally you want to avoid all erase / write operations to the boot loader and it's private data structures in the process of a normal reboot / reset. But a failing boot is not a normal boot. This should only occur when an update fails. After a maximum number of failing boots, the old functional Alexandre wrote about a boot counter; he did not mention that he would update this only on failed boot attempts. Also, in my experience one should be especially careful when something fails, and in such a situation I would all the more restrain from messing with the environment if it can be avoided (and here it's trivial to avoid). image is used and there is no need to update the counter any more. Did you have a look at the current implementation of the boot counter for the systems where it is supported? Yes, we even do have a system where the boot counter is stored in an environment variable (due to hardware restrictions and the expectation that the system will normally not need to be rebooted at all), but normally is can be easily avoided to meddle with the environment for this functionality. Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de A person who is more than casually interested in computers should be well schooled in machine language, since it is a fundamental part of a computer. -- Donald Knuth ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 7/7] am335x_evm: Add support to boot from NOR.
On 13/05/13 19:28, Tom Rini wrote: From: Steve Kipisz s-kipi...@ti.com NOR requires that s_init be within the first 4KiB of the image so that we can perform the rest of the required pinmuxing to talk with the rest of NOR that we are found on. When NOR_BOOT is set we save our environment in NOR at 512KiB and a redundant copy at 768KiB. We avoid using SPL for this case and u-boot.bin is written directly to the start of NOR. I'm trying to get this up and running our NanoBone platform, but I'm having no success. Using a non NOR_BOOT version, I can boot u-boot and read / write to the NOR device (located at 0x0800). So I've compiled my NOR_BOOT version and stored it at the start of the flash device. But when I switch to booting from NOR (rather than SD) I get no output on the serial console. Using an oscilloscope, I can see the NOR chip select is active for a while (approx 350us), so *something* is trying to boot. How can I debug such an early part of the boot process ? Thanks for any help you can give me. Regards Mark J. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v4 0/8] Provide a mechanism to avoid using #ifdef everywhere
Many parts of the U-Boot code base are sprinkled with #ifdefs. This makes different boards compile different versions of the source code, meaning that we must build all boards to check for failures. It is easy to misspell an #ifdef and there is not as much checking of this by the compiler. Multiple dependent #ifdefs are harder to do than with if..then..else. Variable declarations must be #idefed as well as the code that uses them, often much later in the file/function. #ifdef indents don't match code indents and have their own separate indent feature. Overall, excessive use of #idef hurts readability and makes the code harder to modify and refactor. For people coming newly into the code base, #ifdefs can be a big barrier. The use of #ifdef in U-Boot has possibly got a little out of hand. In an attempt to turn the tide, this series includes a patch which provides a way to make CONFIG macros available to C code without using the preprocessor. This makes it possible to use standard C conditional features such as if/then instead of #ifdef. A README update exhorts compliance. As an example of how to use this, this series replaces all but two #ifdefs from the main code body of common/main.c, which is one of the largest users of #ifdef, even after a recent cleanup: for f in $(find . -name *.c); do echo $(grep -c ifdef $f) $f; do ne |sort -nr |head 81 ./common/board_r.c 57 ./arch/powerpc/cpu/mpc83xx/cpu_init.c 55 ./common/board_f.c 49 ./common/main.c 48 ./arch/powerpc/lib/board.c 47 ./drivers/video/cfb_console.c 40 ./drivers/mtd/cfi_flash.c 38 ./net/tftp.c 37 ./drivers/usb/host/ohci-hcd.c 36 ./drivers/fpga/ivm_core.c Code size for this series seems to be roughly neutral (below numbers are average change in byte size for each region: blackfin: (for 24/35 boards) all -11.0 text -11.0 x86: (for 1/1 boards) bss +20.0 data +4.0 text -24.0 avr32: (for 10/10 boards) all -8.4 text -8.4 sandbox: (for 1/1 boards) all +16.0 bss +16.0 m68k: (for 41/50 boards) all -31.9 text -31.9 powerpc: (for 639/641 boards) all -20.5 bss +0.0 rodata -0.5 text -20.0 sparc: (for 5/5 boards) all -28.8 text -28.8 sh: (for 16/21 boards) all -78.2 bss +3.2 rodata -15.5 text -66.0 nios2: (for 3/3 boards) all +24.0 bss +1.3 data -1.3 text +24.0 arm: (for 307/327 boards) all -41.0 bss +3.5 data +0.1 rodata -3.6 spl/u-boot-spl:all -0.1 spl/u-boot-spl:bss -0.1 text -41.0 Note that a config_drop.h file is added - this defines all the CONFIGs which are not used in any board config file. Without this, autoconf cannot define the macros for this CONFIGs. Compile time for main.c does not seem to be any different in my tests. The time to perform the 'dep' step (which now creates autoconf.h) increases, from about 2.8s to about 4.6s. This additional time is used to grep, sed and sort the contents of all the header file in U-Boot. The time for an incremental build is not affected. It would be much more efficient to maintain a list of all available CONFIG defines, but no such list exists at present. Buildman output shows no additional failures from mainline: 01: Merge branch 'master' of git://www.denx.de/git/u-boot-mmc blackfin: + bf561-acvilon cm-bf561 blackstamp br4 bct-brettl2 cm-bf527 dnp5370 bf506f-ezkit ip04 bf527-sdp bf609-ezkit bf537-stamp bf527-ezkit-v2 cm-bf537e tcm-bf518 cm-bf537u bf527-ezkit bf537-pnav cm-bf533 pr1 bf533-ezkit ibf-dsp561 bf537-srv1 cm-bf548 bf537-minotaur bf538f-ezkit bf548-ezkit bf525-ucr2 blackvme tcm-bf537 bf533-stamp bf518f-ezbrd bf527-ad7160-eval bf526-ezbrd bf561-ezkit m68k: + M54455EVB_a66 M5329AFEE M5249EVB idmr M5208EVBE M5475FFE M54451EVB astro_mcf5373l M54418TWR_serial_rmii M54455EVB_intel M5282EVB M54455EVB_i66 M5475GFE M5253DEMO M54455EVB_stm33 M5485BFE M5485DFE M5329BFEE M52277EVB M5475EFE M5475CFE M5485AFE M53017EVB M5475AFE M5485HFE M5235EVB M5253EVBE M54418TWR_nand_mii M54418TWR_nand_rmii_lowfreq TASREG cobra5272 M5475BFE M5475DFE M5275EVB M52277EVB_stmicro eb_cpu5282 eb_cpu5282_internal M54451EVB_stmicro M5271EVB M5485GFE M5485EFE M5485FFE M54418TWR M5235EVB_Flash32 M5373EVB M54418TWR_nand_rmii M54418TWR_serial_mii M5485CFE M54455EVB M5272C3 powerpc: + MVBLM7 MVSMR lcd4_lwmon5 sh: + rsk7269 rsk7264 sh7757lcr sh7752evb rsk7203 microblaze: + microblaze-generic openrisc: + openrisc-generic arm: + palmtc zipitz2 VCMA9 lubbock zynq_dcc vpac270_nor_128 colibri_pxa270 kzm9g zynq xaeniax polaris pxa255_idp lp8x4x vpac270_ond_256 vpac270_nor_256 smdk2410 h2200 balloon3 palmld trizepsiv nds32: + adp-ag101p adp-ag102 adp-ag101 02: Implement autoconf header file 03: main: Use autoconf for boot retry feature 04: main: Remove CONFIG #ifdefs from the abortboot() code 05: main: Use autoconf to remove #ifdefs around process_boot_delay() 06: main: Use autoconf for boot_delay code 07: main: Use autoconf for parser selection 08: main: Use autoconf in command line
[U-Boot] [PATCH v4 7/8] main: Use autoconf in command line reading
Remove #ifdefs in favour of autoconf for this code. This involves removing
a few unnecessary #ifdefs in headers also.
We have two versions of the code - one that handles command line editing and
one that is just a simple implementation. Create a new function called
readline_into_buffer() which calls either cread_line() or the new
simple_readline(), created to hold the 'simple' code.
The cread_print_hist_list() function is not actually used anywhere, so punt
it.
Signed-off-by: Simon Glass s...@chromium.org
Reviewed-by: Joe Hershberger joe.hershber...@ni.com
---
Changes in v4: None
Changes in v3: None
Changes in v2: None
common/main.c | 164 --
include/command.h | 2 -
include/common.h | 2 -
3 files changed, 73 insertions(+), 95 deletions(-)
diff --git a/common/main.c b/common/main.c
index b09bfb4..a854c3b 100644
--- a/common/main.c
+++ b/common/main.c
@@ -513,8 +513,6 @@ void reset_cmd_timeout(void)
}
#endif
-#ifdef CONFIG_CMDLINE_EDITING
-
/*
* cmdline-editing related codes from vivi.
* Author: Janghoon Lyu na...@mizi.com
@@ -617,27 +615,6 @@ static char* hist_next(void)
return (ret);
}
-#ifndef CONFIG_CMDLINE_EDITING
-static void cread_print_hist_list(void)
-{
- int i;
- unsigned long n;
-
- n = hist_num - hist_max;
-
- i = hist_add_idx + 1;
- while (1) {
- if (i hist_max)
- i = 0;
- if (i == hist_add_idx)
- break;
- printf(%s\n, hist_list[i]);
- n++;
- i++;
- }
-}
-#endif /* CONFIG_CMDLINE_EDITING */
-
#define BEGINNING_OF_LINE() { \
while (num) { \
getcmd_putch(CTL_BACKSPACE);\
@@ -899,27 +876,27 @@ static int cread_line(const char *const prompt, char
*buf, unsigned int *len,
REFRESH_TO_EOL();
continue;
}
-#ifdef CONFIG_AUTO_COMPLETE
- case '\t': {
- int num2, col;
+ case '\t':
+ if (autoconf_auto_complete()) {
+ int num2, col;
- /* do not autocomplete when in the middle */
- if (num eol_num) {
- getcmd_cbeep();
- break;
- }
+ /* do not autocomplete when in the middle */
+ if (num eol_num) {
+ getcmd_cbeep();
+ break;
+ }
- buf[num] = '\0';
- col = strlen(prompt) + eol_num;
- num2 = num;
- if (cmd_auto_complete(prompt, buf, num2, col)) {
- col = num2 - num;
- num += col;
- eol_num += col;
+ buf[num] = '\0';
+ col = strlen(prompt) + eol_num;
+ num2 = num;
+ if (cmd_auto_complete(prompt, buf, num2,
+ col)) {
+ col = num2 - num;
+ num += col;
+ eol_num += col;
+ }
+ break;
}
- break;
- }
-#endif
default:
cread_add_char(ichar, insert, num, eol_num, buf,
*len);
break;
@@ -935,8 +912,6 @@ static int cread_line(const char *const prompt, char *buf,
unsigned int *len,
return 0;
}
-#endif /* CONFIG_CMDLINE_EDITING */
-
//
/*
@@ -958,46 +933,14 @@ int readline (const char *const prompt)
return readline_into_buffer(prompt, console_buffer, 0);
}
-
-int readline_into_buffer(const char *const prompt, char *buffer, int timeout)
+static int simple_readline(const char *const prompt, int plen, char *p,
+ int timeout)
{
- char *p = buffer;
-#ifdef CONFIG_CMDLINE_EDITING
- unsigned int len = CONFIG_SYS_CBSIZE;
- int rc;
- static int initted = 0;
-
- /*
-* History uses a global array which is not
-* writable until after relocation to RAM.
-* Revert to non-history version if still
-* running from flash.
-*/
- if (gd-flags GD_FLG_RELOC) {
- if (!initted) {
- hist_init();
- initted = 1;
- }
-
- if (prompt)
- puts
[U-Boot] [PATCH v4 3/8] main: Remove CONFIG #ifdefs from the abortboot() code
Move this code over to using autoconf. We can add the autoconf values to
the delaykey[] array, and move the code that checks for autoconf values into
the loop.
Also change to using ARRAY_SIZE on delaykey[].
Signed-off-by: Simon Glass s...@chromium.org
Reviewed-by: Joe Hershberger joe.hershber...@ni.com
---
Changes in v4:
- Rebase on current master
Changes in v3: None
Changes in v2: None
common/main.c | 90 ++-
1 file changed, 34 insertions(+), 56 deletions(-)
diff --git a/common/main.c b/common/main.c
index 3a143ae..3a4754d 100644
--- a/common/main.c
+++ b/common/main.c
@@ -86,15 +86,20 @@ static int abortboot_keyed(int bootdelay)
int abort = 0;
uint64_t etime = endtick(bootdelay);
struct {
- char* str;
+ const char *str;
u_int len;
int retry;
+ const char *conf; /* Configuration value */
}
delaykey [] = {
- { str: getenv (bootdelaykey), retry: 1 },
- { str: getenv (bootdelaykey2), retry: 1 },
- { str: getenv (bootstopkey), retry: 0 },
- { str: getenv (bootstopkey2), retry: 0 },
+ { str: getenv(bootdelaykey), retry: 1,
+ conf: autoconf_autoboot_delay_str() },
+ { str: getenv(bootdelaykey2), retry: 1,
+ conf: autoconf_autoboot_delay_str2() },
+ { str: getenv(bootstopkey), retry: 0,
+ conf: autoconf_autoboot_stop_str() },
+ { str: getenv(bootstopkey2), retry: 0,
+ conf: autoconf_autoboot_stop_str2() },
};
char presskey [MAX_DELAY_STOP_STR];
@@ -102,33 +107,15 @@ static int abortboot_keyed(int bootdelay)
u_int presskey_max = 0;
u_int i;
-#ifndef CONFIG_ZERO_BOOTDELAY_CHECK
- if (bootdelay == 0)
+ if (!autoconf_zero_bootdelay_check() bootdelay == 0)
return 0;
-#endif
-# ifdef CONFIG_AUTOBOOT_PROMPT
- printf(CONFIG_AUTOBOOT_PROMPT);
-# endif
-
-# ifdef CONFIG_AUTOBOOT_DELAY_STR
- if (delaykey[0].str == NULL)
- delaykey[0].str = CONFIG_AUTOBOOT_DELAY_STR;
-# endif
-# ifdef CONFIG_AUTOBOOT_DELAY_STR2
- if (delaykey[1].str == NULL)
- delaykey[1].str = CONFIG_AUTOBOOT_DELAY_STR2;
-# endif
-# ifdef CONFIG_AUTOBOOT_STOP_STR
- if (delaykey[2].str == NULL)
- delaykey[2].str = CONFIG_AUTOBOOT_STOP_STR;
-# endif
-# ifdef CONFIG_AUTOBOOT_STOP_STR2
- if (delaykey[3].str == NULL)
- delaykey[3].str = CONFIG_AUTOBOOT_STOP_STR2;
-# endif
-
- for (i = 0; i sizeof(delaykey) / sizeof(delaykey[0]); i ++) {
+ if (autoconf_has_autoboot_prompt())
+ printf(autoconf_autoboot_prompt());
+
+ for (i = 0; i ARRAY_SIZE(delaykey); i++) {
+ if (delaykey[i].conf !delaykey[i].str)
+ delaykey[i].str = delaykey[i].conf;
delaykey[i].len = delaykey[i].str == NULL ?
0 : strlen (delaykey[i].str);
delaykey[i].len = delaykey[i].len MAX_DELAY_STOP_STR ?
@@ -158,7 +145,7 @@ static int abortboot_keyed(int bootdelay)
}
}
- for (i = 0; i sizeof(delaykey) / sizeof(delaykey[0]); i ++) {
+ for (i = 0; i ARRAY_SIZE(delaykey); i++) {
if (delaykey[i].len 0
presskey_len = delaykey[i].len
memcmp (presskey + presskey_len - delaykey[i].len,
@@ -180,45 +167,39 @@ static int abortboot_keyed(int bootdelay)
if (!abort)
debug_bootkeys(key timeout\n);
-#ifdef CONFIG_SILENT_CONSOLE
- if (abort)
+ if (autoconf_silent_console() abort)
gd-flags = ~GD_FLG_SILENT;
-#endif
return abort;
}
# else /* !defined(CONFIG_AUTOBOOT_KEYED) */
-#ifdef CONFIG_MENUKEY
-static int menukey = 0;
-#endif
+static int menukey;
static int abortboot_normal(int bootdelay)
{
int abort = 0;
unsigned long ts;
-#ifdef CONFIG_MENUPROMPT
- printf(CONFIG_MENUPROMPT);
-#else
- if (bootdelay = 0)
+ if (autoconf_menuprompt())
+ printf(autoconf_menuprompt());
+ else if (bootdelay = 0)
printf(Hit any key to stop autoboot: %2d , bootdelay);
-#endif
-#if defined CONFIG_ZERO_BOOTDELAY_CHECK
/*
-* Check if key already pressed
-* Don't check if bootdelay 0
+* If we need to do a bootdelay check even if bootdelay is 0, do
+* it here, since the loop below will be skipped in this case.
+* We don't do this check if bootdelay 0.
*/
- if (bootdelay = 0) {
- if (tstc()) { /* we got a key press */
+ if (autoconf_zero_bootdelay_check() bootdelay = 0) {
+
[U-Boot] [PATCH v4 5/8] main: Use autoconf for boot_delay code
Convert this function and its children to use autoconf instead of #ifdef.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v4:
- Rebase on current master
Changes in v3:
- Simplify code for finding out bootdelay from config or environment
Changes in v2: None
common/main.c | 74 +-
include/menu.h | 2 --
2 files changed, 32 insertions(+), 44 deletions(-)
diff --git a/common/main.c b/common/main.c
index dba6cee..fc55e06 100644
--- a/common/main.c
+++ b/common/main.c
@@ -302,52 +302,42 @@ static void process_fdt_options(const void *blob)
static void process_boot_delay(void)
{
- char *s;
- int bootdelay;
-#ifdef CONFIG_BOOTCOUNT_LIMIT
unsigned long bootcount = 0;
unsigned long bootlimit = 0;
-#endif /* CONFIG_BOOTCOUNT_LIMIT */
-
-#ifdef CONFIG_BOOTCOUNT_LIMIT
- bootcount = bootcount_load();
- bootcount++;
- bootcount_store (bootcount);
- setenv_ulong(bootcount, bootcount);
- bootlimit = getenv_ulong(bootlimit, 10, 0);
-#endif /* CONFIG_BOOTCOUNT_LIMIT */
-
- s = getenv (bootdelay);
- bootdelay = s ? (int)simple_strtol(s, NULL, 10) : autoconf_bootdelay();
-
-#ifdef CONFIG_OF_CONTROL
- bootdelay = fdtdec_get_config_int(gd-fdt_blob, bootdelay,
- bootdelay);
-#endif
+ const char *s;
+ int bootdelay;
+
+ if (autoconf_bootcount_limit()) {
+ bootcount = bootcount_load();
+ bootcount++;
+ bootcount_store(bootcount);
+ setenv_ulong(bootcount, bootcount);
+ bootlimit = getenv_ulong(bootlimit, 10, 0);
+ }
+ bootdelay = getenv_ulong(bootdelay, 10, autoconf_bootdelay());
+
+ if (autoconf_of_control()) {
+ bootdelay = fdtdec_get_config_int(gd-fdt_blob, bootdelay,
+ bootdelay);
+ }
debug (### main_loop entered: bootdelay=%d\n\n, bootdelay);
-#if defined(CONFIG_MENU_SHOW)
- bootdelay = menu_show(bootdelay);
-#endif
+ if (autoconf_menu_show())
+ bootdelay = menu_show(bootdelay);
if (autoconf_boot_retry_time())
init_cmd_timeout();
-#ifdef CONFIG_POST
- if (gd-flags GD_FLG_POSTFAIL) {
+ if (autoconf_post() (gd-flags GD_FLG_POSTFAIL)) {
s = getenv(failbootcmd);
- }
- else
-#endif /* CONFIG_POST */
-#ifdef CONFIG_BOOTCOUNT_LIMIT
- if (bootlimit (bootcount bootlimit)) {
+ } else if (autoconf_bootcount_limit() bootlimit
+ (bootcount bootlimit)) {
printf (Warning: Bootlimit (%u) exceeded. Using altbootcmd.\n,
(unsigned)bootlimit);
s = getenv (altbootcmd);
- }
- else
-#endif /* CONFIG_BOOTCOUNT_LIMIT */
+ } else {
s = getenv (bootcmd);
+ }
if (autoconf_of_control()) {
char *env;
@@ -370,24 +360,24 @@ static void process_boot_delay(void)
debug (### main_loop: bootcmd=\%s\\n, s ? s : UNDEFINED);
if (bootdelay != -1 s !abortboot(bootdelay)) {
-#ifdef CONFIG_AUTOBOOT_KEYED
- int prev = disable_ctrlc(1);/* disable Control C checking */
-#endif
+ int prev;
+
+ /* disable Control C checking */
+ if (autoconf_autoboot_keyed())
+ prev = disable_ctrlc(1);
run_command_list(s, -1, 0);
-#ifdef CONFIG_AUTOBOOT_KEYED
- disable_ctrlc(prev);/* restore Control C checking */
-#endif
+ /* restore Control C checking */
+ if (autoconf_autoboot_keyed())
+ disable_ctrlc(prev);
}
-#ifdef CONFIG_MENUKEY
- if (menukey == CONFIG_MENUKEY) {
+ if (autoconf_menukey() menukey == autoconf_menukey()) {
s = getenv(menucmd);
if (s)
run_command_list(s, -1, 0);
}
-#endif /* CONFIG_MENUKEY */
}
void main_loop(void)
diff --git a/include/menu.h b/include/menu.h
index d8200ee..bcc3ec4 100644
--- a/include/menu.h
+++ b/include/menu.h
@@ -31,7 +31,5 @@ int menu_destroy(struct menu *m);
void menu_display_statusline(struct menu *m);
int menu_default_choice(struct menu *m, void **choice);
-#if defined(CONFIG_MENU_SHOW)
int menu_show(int bootdelay);
-#endif
#endif /* __MENU_H__ */
--
1.8.3
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v4 6/8] main: Use autoconf for parser selection
Allow parser selection to make use of autoconf instead of #ifdefs.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v4:
- Rebase on current master
Changes in v3: None
Changes in v2: None
common/main.c | 87 +++---
include/hush.h | 2 --
2 files changed, 41 insertions(+), 48 deletions(-)
diff --git a/common/main.c b/common/main.c
index fc55e06..b09bfb4 100644
--- a/common/main.c
+++ b/common/main.c
@@ -382,12 +382,10 @@ static void process_boot_delay(void)
void main_loop(void)
{
-#ifndef CONFIG_SYS_HUSH_PARSER
static char lastcommand[CONFIG_SYS_CBSIZE] = { 0, };
int len;
int rc = 1;
int flag;
-#endif
#ifdef CONFIG_PREBOOT
char *p;
#endif
@@ -444,12 +442,11 @@ void main_loop(void)
/*
* Main Loop for Monitor Command Processing
*/
-#ifdef CONFIG_SYS_HUSH_PARSER
- parse_file_outer();
- /* This point is never reached */
- for (;;);
-#else
- for (;;) {
+ if (autoconf_sys_hush_parser()) {
+ parse_file_outer();
+ /* This point is never reached */
+ for (;;);
+ } else {
if (autoconf_boot_retry_time() rc = 0) {
/* Saw enough of a valid command to
* restart the timeout.
@@ -484,7 +481,6 @@ void main_loop(void)
lastcommand[0] = 0;
}
}
-#endif /*CONFIG_SYS_HUSH_PARSER*/
}
/*
@@ -1174,7 +1170,6 @@ int parse_line (char *line, char *argv[])
//
-#ifndef CONFIG_SYS_HUSH_PARSER
static void process_macros (const char *input, char *output)
{
char c, prev;
@@ -1382,7 +1377,6 @@ static int builtin_run_command(const char *cmd, int flag)
return rc ? rc : repeatable;
}
-#endif
/*
* Run a command using the selected parser.
@@ -1393,22 +1387,21 @@ static int builtin_run_command(const char *cmd, int
flag)
*/
int run_command(const char *cmd, int flag)
{
-#ifndef CONFIG_SYS_HUSH_PARSER
- /*
-* builtin_run_command can return 0 or 1 for success, so clean up
-* its result.
-*/
- if (builtin_run_command(cmd, flag) == -1)
- return 1;
-
- return 0;
-#else
- return parse_string_outer(cmd,
+ if (autoconf_sys_hush_parser()) {
+ return parse_string_outer(cmd,
FLAG_PARSE_SEMICOLON | FLAG_EXIT_FROM_LOOP);
-#endif
+ } else {
+ /*
+ * builtin_run_command can return 0 or 1 for success, so
+ * clean up its result.
+ */
+ if (builtin_run_command(cmd, flag) == -1)
+ return 1;
+
+ return 0;
+ }
}
-#ifndef CONFIG_SYS_HUSH_PARSER
/**
* Execute a list of command separated by ; or \n using the built-in parser.
*
@@ -1449,7 +1442,6 @@ static int builtin_run_command_list(char *cmd, int flag)
return rcode;
}
-#endif
int run_command_list(const char *cmd, int len, int flag)
{
@@ -1459,13 +1451,16 @@ int run_command_list(const char *cmd, int len, int flag)
if (len == -1) {
len = strlen(cmd);
-#ifdef CONFIG_SYS_HUSH_PARSER
- /* hush will never change our string */
- need_buff = 0;
-#else
- /* the built-in parser will change our string if it sees \n */
- need_buff = strchr(cmd, '\n') != NULL;
-#endif
+ if (autoconf_sys_hush_parser()) {
+ /* hush will never change our string */
+ need_buff = 0;
+ } else {
+ /*
+* the built-in parser will change our string if it
+* sees \n
+*/
+ need_buff = strchr(cmd, '\n') != NULL;
+ }
}
if (need_buff) {
buff = malloc(len + 1);
@@ -1474,20 +1469,20 @@ int run_command_list(const char *cmd, int len, int flag)
memcpy(buff, cmd, len);
buff[len] = '\0';
}
-#ifdef CONFIG_SYS_HUSH_PARSER
- rcode = parse_string_outer(buff, FLAG_PARSE_SEMICOLON);
-#else
- /*
-* This function will overwrite any \n it sees with a \0, which
-* is why it can't work with a const char *. Here we are making
-* using of internal knowledge of this function, to avoid always
-* doing a malloc() which is actually required only in a case that
-* is pretty rare.
-*/
- rcode = builtin_run_command_list(buff, flag);
- if (need_buff)
- free(buff);
-#endif
+ if (autoconf_sys_hush_parser()) {
+ rcode = parse_string_outer(buff, FLAG_PARSE_SEMICOLON);
+ } else {
+ /*
+ * This function will overwrite any \n it
[U-Boot] [PATCH v4 2/8] main: Use autoconf for boot retry feature
Change this feature to use autoconf instead of #ifdef.
Signed-off-by: Simon Glass s...@chromium.org
Reviewed-by: Joe Hershberger joe.hershber...@ni.com
---
Changes in v4:
- Rebase on current master
- Tidy up code style nits with new checkpatch
Changes in v3:
- Fix missing in if() statement
- Remove unneeded retry_min variable
Changes in v2: None
common/main.c | 73 ++-
1 file changed, 32 insertions(+), 41 deletions(-)
diff --git a/common/main.c b/common/main.c
index 56da214..3a143ae 100644
--- a/common/main.c
+++ b/common/main.c
@@ -65,17 +65,11 @@ static char * delete_char (char *buffer, char *p, int
*colp, int *np, int plen);
static const char erase_seq[] = \b \b; /* erase sequence
*/
static const char tab_seq[] = ;/* used to expand TABs
*/
-#ifdef CONFIG_BOOT_RETRY_TIME
static uint64_t endtime = 0; /* must be set, default is instant timeout */
static int retry_time = -1; /* -1 so can call readline before main_loop */
-#endif
#defineendtick(seconds) (get_ticks() + (uint64_t)(seconds) *
get_tbclk())
-#ifndef CONFIG_BOOT_RETRY_MIN
-#define CONFIG_BOOT_RETRY_MIN CONFIG_BOOT_RETRY_TIME
-#endif
-
#ifdef CONFIG_MODEM_SUPPORT
int do_mdm_init = 0;
extern void mdm_init(void); /* defined in board.c */
@@ -174,11 +168,10 @@ static int abortboot_keyed(int bootdelay)
delaykey[i].retry ? delay :
stop);
-# ifdef CONFIG_BOOT_RETRY_TIME
- /* don't retry auto boot */
- if (! delaykey[i].retry)
+ /* don't retry auto boot? */
+ if (autoconf_boot_retry_time()
+ !delaykey[i].retry)
retry_time = -1;
-# endif
abort = 1;
}
}
@@ -368,9 +361,8 @@ static void process_boot_delay(void)
#if defined(CONFIG_MENU_SHOW)
bootdelay = menu_show(bootdelay);
#endif
-# ifdef CONFIG_BOOT_RETRY_TIME
- init_cmd_timeout ();
-# endif/* CONFIG_BOOT_RETRY_TIME */
+ if (autoconf_boot_retry_time())
+ init_cmd_timeout();
#ifdef CONFIG_POST
if (gd-flags GD_FLG_POSTFAIL) {
@@ -499,14 +491,12 @@ void main_loop(void)
for (;;);
#else
for (;;) {
-#ifdef CONFIG_BOOT_RETRY_TIME
- if (rc = 0) {
+ if (autoconf_boot_retry_time() rc = 0) {
/* Saw enough of a valid command to
* restart the timeout.
*/
reset_cmd_timeout();
}
-#endif
len = readline (CONFIG_SYS_PROMPT);
flag = 0; /* assume no special flags for now */
@@ -514,19 +504,16 @@ void main_loop(void)
strcpy (lastcommand, console_buffer);
else if (len == 0)
flag |= CMD_FLAG_REPEAT;
-#ifdef CONFIG_BOOT_RETRY_TIME
- else if (len == -2) {
+ else if (autoconf_boot_retry_time() len == -2) {
/* -2 means timed out, retry autoboot
*/
- puts (\nTimed out waiting for command\n);
-# ifdef CONFIG_RESET_TO_RETRY
+ puts(\nTimed out waiting for command\n);
/* Reinit board to run initialization code again */
- do_reset (NULL, 0, 0, NULL);
-# else
- return; /* retry autoboot */
-# endif
+ if (autoconf_reset_to_retry())
+ do_reset(NULL, 0, 0, NULL);
+ else
+ return; /* retry autoboot */
}
-#endif
if (len == -1)
puts (INTERRUPT\n);
@@ -541,6 +528,10 @@ void main_loop(void)
#endif /*CONFIG_SYS_HUSH_PARSER*/
}
+/*
+ * Use ifdef here for the benefit of those archs not using
+ * -ffunction-sections, since these functions are exported.
+ */
#ifdef CONFIG_BOOT_RETRY_TIME
/***
* initialize command line timeout
@@ -552,10 +543,10 @@ void init_cmd_timeout(void)
if (s != NULL)
retry_time = (int)simple_strtol(s, NULL, 10);
else
- retry_time = CONFIG_BOOT_RETRY_TIME;
+ retry_time = autoconf_boot_retry_time();
- if (retry_time = 0 retry_time CONFIG_BOOT_RETRY_MIN)
- retry_time = CONFIG_BOOT_RETRY_MIN;
+ if (retry_time = 0 retry_time autoconf_boot_retry_min())
+ retry_time = autoconf_boot_retry_min();
}
/***
@@
[U-Boot] [PATCH v4 8/8] main: Use autoconf in main_loop()
Convert main_loop() over to use autoconf, and add a required prototype
to common.h.
The do_mdm_init variable is now always defined, but this seems like an
acceptable compromise.
In fdt_support.h the #ifdef used is CONFIG_OF_LIBFDT. However, even if
this is not defined we want to make the functions available for our
conditional-compilation scheme. The only place where we really don't
have access to these support functions is when USE_HOSTCC is defined.
So change the #ifdef to that.
Signed-off-by: Simon Glass s...@chromium.org
Reviewed-by: Joe Hershberger joe.hershber...@ni.com
---
Changes in v4:
- Rebase on current master
Changes in v3:
- Remove the extra config_of_libfdt() condition in main_loop()
Changes in v2: None
common/main.c | 72 +++
include/common.h | 1 +
include/fdt_support.h | 4 +--
3 files changed, 35 insertions(+), 42 deletions(-)
diff --git a/common/main.c b/common/main.c
index a854c3b..a5ef5fb 100644
--- a/common/main.c
+++ b/common/main.c
@@ -70,10 +70,7 @@ static int retry_time = -1; /* -1 so can call readline
before main_loop */
#defineendtick(seconds) (get_ticks() + (uint64_t)(seconds) *
get_tbclk())
-#ifdef CONFIG_MODEM_SUPPORT
int do_mdm_init = 0;
-extern void mdm_init(void); /* defined in board.c */
-#endif
/***
* Watch for 'delay' seconds for autoboot stop or autoboot delay string.
@@ -386,51 +383,47 @@ void main_loop(void)
int len;
int rc = 1;
int flag;
-#ifdef CONFIG_PREBOOT
- char *p;
-#endif
bootstage_mark_name(BOOTSTAGE_ID_MAIN_LOOP, main_loop);
-#ifdef CONFIG_MODEM_SUPPORT
- debug(DEBUG: main_loop: do_mdm_init=%d\n, do_mdm_init);
- if (do_mdm_init) {
- char *str = strdup(getenv(mdm_cmd));
- setenv(preboot, str); /* set or delete definition */
- if (str != NULL)
- free(str);
- mdm_init(); /* wait for modem connection */
+ if (autoconf_modem_support()) {
+ debug(DEBUG: main_loop: do_mdm_init=%d\n, do_mdm_init);
+ if (do_mdm_init) {
+ char *str = strdup(getenv(mdm_cmd));
+
+ setenv(preboot, str); /* set or delete definition */
+ if (str != NULL)
+ free(str);
+ mdm_init(); /* wait for modem connection */
+ }
}
-#endif /* CONFIG_MODEM_SUPPORT */
-#ifdef CONFIG_VERSION_VARIABLE
- {
+ if (autoconf_version_variable())
setenv(ver, version_string); /* set version variable */
- }
-#endif /* CONFIG_VERSION_VARIABLE */
-#ifdef CONFIG_SYS_HUSH_PARSER
- u_boot_hush_start();
-#endif
+ if (autoconf_sys_hush_parser())
+ u_boot_hush_start();
-#if defined(CONFIG_HUSH_INIT_VAR)
- hush_init_var();
-#endif
+ if (autoconf_hush_init_var())
+ hush_init_var();
+
+ if (autoconf_preboot()) {
+ char *p = getenv(preboot);
+
+ if (p) {
+ int prev;
-#ifdef CONFIG_PREBOOT
- p = getenv(preboot);
- if (p != NULL) {
-# ifdef CONFIG_AUTOBOOT_KEYED
- int prev = disable_ctrlc(1);/* disable Control C checking */
-# endif
+ /* disable Control C checking */
+ if (autoconf_autoboot_keyed())
+ prev = disable_ctrlc(1);
- run_command_list(p, -1, 0);
+ run_command_list(p, -1, 0);
-# ifdef CONFIG_AUTOBOOT_KEYED
- disable_ctrlc(prev);/* restore Control C checking */
-# endif
+ /* restore Control C checking */
+ if (autoconf_autoboot_keyed())
+ disable_ctrlc(prev);
+ }
}
-#endif /* CONFIG_PREBOOT */
#if defined(CONFIG_UPDATE_TFTP)
update_tftp(0UL);
@@ -472,14 +465,13 @@ void main_loop(void)
}
if (len == -1)
- puts (INTERRUPT\n);
+ puts(INTERRUPT\n);
else
rc = run_command(lastcommand, flag);
- if (rc = 0) {
- /* invalid command or not repeatable, forget it */
+ /* If an invalid command or not repeatable, forget it */
+ if (rc = 0)
lastcommand[0] = 0;
- }
}
}
diff --git a/include/common.h b/include/common.h
index f38cdad..0118ebf 100644
--- a/include/common.h
+++ b/include/common.h
@@ -328,6 +328,7 @@ extern u8 _binary_dt_dtb_start[]; /* embedded device tree
blob */
int set_cpu_clk_info(void);
int print_cpuinfo(void);
int update_flash_size(int flash_size);
+extern int mdm_init(void); /* defined in board.c */
Re: [U-Boot] [PATCH] checkpatch.pl: Do not hardcode perl path
On Mon, Jun 17, 2013 at 1:38 AM, Andreas Bießmann andreas.de...@googlemail.com wrote: Dear Joel A Fernandes, On 16.06.13 17:44, Joel A Fernandes wrote: On Sunday, June 16, 2013, Jagannadha Sutradharudu Teki wrote: From: Jagannadha Sutradharudu Teki jagannadh.t...@gmail.comjavascript:; checkpatch.pl requires perl v5.10.0 to run but it doesn't require to place in /usr/bin/perl Use env to ensure that the interpreter used is the first one on environment's $PATH on system with several versions of perl installed. Signed-off-by: Jagannadha Sutradharudu Teki jagannadh.t...@gmail.comjavascript:; --- tools/checkpatch.pl | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/tools/checkpatch.pl b/tools/checkpatch.pl index 896e2bc..8dc5b9c 100755 --- a/tools/checkpatch.pl +++ b/tools/checkpatch.pl @@ -1,10 +1,11 @@ -#!/usr/bin/perl -w +#!/usr/bin/env perl Would it not work to pass in the -w here? this is not portable! BSD variants of env will only take a single parameter. Sure yes I noticed that, this is an acceptable approach though I've seen some cases people solve the problem using exec. Thanks, Joel ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v4 1/8] Implement autoconf header file
Add support for generating an autoconf.h header file that can be used in
the source instead of #ifdef.
For example, instead of:
#ifdef CONFIG_VERSION_VARIABLE
setenv(ver, version_string); /* set version variable */
#endif
you can do:
if (autoconf_version_variable())
setenv(ver, version_string); /* set version variable */
The compiler will ensure that the dead code is eliminated, so the result
is the same.
Where the value of the CONFIG define is 0, you can use the autoconf_has...()
form. For example CONFIG_BOOTDELAY can be -ve, 0 or +ve, but if it is
defined at all, it affects behaviour:
#if defined(CONFIG_BOOTDELAY) (CONFIG_BOOTDELAY = 0)
s = getenv (bootdelay);
#endif
So we use:
if (autoconf_has_bootdelay() autoconf_bootdelay() = 0)
s = getenv (bootdelay);
This later form should only be used for such 'difficult' defines where a
zero value still means that the CONFIG should be considered to be defined.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v4: None
Changes in v3:
- Add comment as to why we use [A-Za-z0-9_][A-Za-z0-9_]*
- Rename sed scripts to more useful names
- Update config_xxx() to autoconf_xxx() in comments/README/sed
- Update config_xxx_enabled() to autoconf_has_xxx() in comments/README/sed
Changes in v2:
- Add a grep to the sed/sort pipe to speed up processing
- Fix up a few errors and comments in the original RFC
- Split out changes to main.c into separate patches
- Use autoconf_...() instead of config_...()
- Use autoconf_has_...() instead of config_..._enabled()
Makefile | 43 -
README | 87 --
include/common.h | 3 ++
include/config_drop.h | 17 +
tools/scripts/define2value.sed | 37 ++
tools/scripts/define2zero.sed | 32
6 files changed, 215 insertions(+), 4 deletions(-)
create mode 100644 include/config_drop.h
create mode 100644 tools/scripts/define2value.sed
create mode 100644 tools/scripts/define2zero.sed
diff --git a/Makefile b/Makefile
index 693b3f2..3c2ffd4 100644
--- a/Makefile
+++ b/Makefile
@@ -629,6 +629,7 @@ updater:
# parallel sub-makes creating .depend files simultaneously.
depend dep:$(TIMESTAMP_FILE) $(VERSION_FILE) \
$(obj)include/autoconf.mk \
+ $(obj)include/generated/autoconf.h \
$(obj)include/generated/generic-asm-offsets.h \
$(obj)include/generated/asm-offsets.h
for dir in $(SUBDIRS) $(CPUDIR) $(LDSCRIPT_MAKEFILE_DIR) ; do \
@@ -703,6 +704,45 @@ $(obj)include/autoconf.mk: $(obj)include/config.h
sed -n -f tools/scripts/define2mk.sed $@.tmp \
mv $@.tmp $@
+# Create a C header file where every '#define CONFIG_XXX value' becomes
+# '#define autoconf_xxx() value', or '#define autoconf_xxx() 0' where the
+# CONFIG is not used by this board configuration. This allows C code to do
+# things like 'if (autoconf_xxx())' and have the compiler remove the dead code,
+# instead of using '#ifdef CONFIG_XXX...#endif'. Note that in most cases
+# if the autoconf_...() returns 0 then the option is not enabled. In some rare
+# cases such as CONFIG_BOOTDELAY, the config can be enabled but still have a
+# a value of 0. So in addition we a #define autoconf_has_xxx(), setting the
+# value to 0 if the option is disabled, 1 if enabled. This last feature will
+# hopefully be deprecated soon.
+# The file is regenerated when any U-Boot header file changes.
+$(obj)include/generated/autoconf.h: $(obj)include/config.h
+ @$(XECHO) Generating $@ ; \
+ set -e ; \
+ : Extract the config macros to a C header file ; \
+ $(CPP) $(CFLAGS) -DDO_DEPS_ONLY -dM include/common.h | \
+ sed -n -f tools/scripts/define2value.sed $@.tmp; \
+ : Regenerate our list of all config macros if neeed ; \
+ if [ ! -f $@-all.tmp ] || \
+ find $(src) -name '*.h' -type f -newer $@-all.tmp | \
+ egrep -qv 'include/(autoconf.h|generated|config.h)'; \
+ then \
+ : Extract all config macros from all C header files ; \
+ : We can grep for CONFIG since the value will be dropped ; \
+ ( \
+ find ${src} -name *.h -type f | xargs \
+ cat | grep CONFIG | \
+ sed -n -f tools/scripts/define2zero.sed \
+ ) | sort | uniq $@-all.tmp; \
+ fi; \
+ : Extract the enabled config macros to a C header file ; \
+ $(CPP) $(CFLAGS) -DDO_DEPS_ONLY -dM include/common.h | \
+ sed -n -f tools/scripts/define2zero.sed | \
+ sort $@-enabled.tmp; \
+ set -e ; \
+ : Find CONFIGs that are not enabled ; \
+ comm -13 $@-enabled.tmp $@-all.tmp $@.tmp \
+ mv $@.tmp $@
+
Re: [U-Boot] [PATCH v2 7/7] am335x_evm: Add support to boot from NOR.
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 On 06/17/2013 10:43 AM, Mark Jackson wrote: On 13/05/13 19:28, Tom Rini wrote: From: Steve Kipisz s-kipi...@ti.com NOR requires that s_init be within the first 4KiB of the image so that we can perform the rest of the required pinmuxing to talk with the rest of NOR that we are found on. When NOR_BOOT is set we save our environment in NOR at 512KiB and a redundant copy at 768KiB. We avoid using SPL for this case and u-boot.bin is written directly to the start of NOR. I'm trying to get this up and running our NanoBone platform, but I'm having no success. Using a non NOR_BOOT version, I can boot u-boot and read / write to the NOR device (located at 0x0800). So I've compiled my NOR_BOOT version and stored it at the start of the flash device. But when I switch to booting from NOR (rather than SD) I get no output on the serial console. Using an oscilloscope, I can see the NOR chip select is active for a while (approx 350us), so *something* is trying to boot. How can I debug such an early part of the boot process ? Did you copy the parts that setup the pinmuxing in s_init for NOR? - -- Tom -BEGIN PGP SIGNATURE- Version: GnuPG v1.4.11 (GNU/Linux) Comment: Using GnuPG with Thunderbird - http://www.enigmail.net/ iQIcBAEBAgAGBQJRvyIDAAoJENk4IS6UOR1W0v4P/0Nudkj1/7PhxndIRr3z1pXa pbEDg3leDIiWHgoM5Z1Ruxti6s6l2LH+vzZ15Sl2XF4xrU8BQ6pxdBuMpbluiv2W ePr3P2iQ/C67pT5WqXwXO2uIXzTxtUWNc6VOcd1ejDUWfHOAPZjWa7ObpPnklc/o pGkN01xYuv+9Na/aLPVO2fB9KPE0t1xiVrAwReWaEGC8JaOMCN7XFslYjKSBOkRh yai3NycmR6N12JcZVvzpRkA5WbcI4GdGC0TK/RywmF3bP6DdgNmc1GMCfKyQRs0c h26S87AzUO4NyoEfecExLEhS8eP3LU0I5um2tp0kbLBOX/Wdy6hQ/Vn/LNGGFrDs +urLVetNZweznxlyDn+dtxvo7dEQyiiIHN0xzOVwONUhz9mTnhDk8HBQAPRAqwOK PVom+jNaG9UYxks4S0qjJvSiJR4VqvYdlOqMxwfPphIb0Nt1a/cVnhm7PCwWvvw2 q3bOAxq11+5aRDeBCOG+8rdFqotgXZ7ig4vwFb5qg4AFJE7wbJLoyAgxhO2o4KNe Opa8DZsA4Joier1tC2fVuqPcl00tsg9JOqMDug4pgKyCz0EGWtREgy4/KKLT0/9J JBXrv6h3D+tfUbNjNR7b5seMhK3WxYAMQQwgDGSLgs5Vwnydz5iI0Vp3xH21HSar 2SxW1hU4pMkAjBm2V4OA =BJ51 -END PGP SIGNATURE- ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v4 4/8] main: Use autoconf to remove #ifdefs around process_boot_delay()
Use autoconf to make process_boot_delay() be compiled always, and adjust
the caller and related functions as needed.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v4:
- Split out new patch to remove #ifdefs around process_boot_delay()
Changes in v3: None
Changes in v2: None
common/main.c | 71 ++-
1 file changed, 31 insertions(+), 40 deletions(-)
diff --git a/common/main.c b/common/main.c
index 3a4754d..dba6cee 100644
--- a/common/main.c
+++ b/common/main.c
@@ -79,8 +79,6 @@ extern void mdm_init(void); /* defined in board.c */
* Watch for 'delay' seconds for autoboot stop or autoboot delay string.
* returns: 0 - no key string, allow autoboot 1 - got key string, abort
*/
-#if defined(CONFIG_BOOTDELAY)
-# if defined(CONFIG_AUTOBOOT_KEYED)
static int abortboot_keyed(int bootdelay)
{
int abort = 0;
@@ -173,8 +171,6 @@ static int abortboot_keyed(int bootdelay)
return abort;
}
-# else /* !defined(CONFIG_AUTOBOOT_KEYED) */
-
static int menukey;
static int abortboot_normal(int bootdelay)
@@ -228,17 +224,14 @@ static int abortboot_normal(int bootdelay)
return abort;
}
-# endif/* CONFIG_AUTOBOOT_KEYED */
static int abortboot(int bootdelay)
{
-#ifdef CONFIG_AUTOBOOT_KEYED
- return abortboot_keyed(bootdelay);
-#else
- return abortboot_normal(bootdelay);
-#endif
+ if (autoconf_autoboot_keyed())
+ return abortboot_keyed(bootdelay);
+ else
+ return abortboot_normal(bootdelay);
}
-#endif /* CONFIG_BOOTDELAY */
/*
* Runs the given boot command securely. Specifically:
@@ -254,7 +247,6 @@ static int abortboot(int bootdelay)
* printing the error message to console.
*/
-#if defined(CONFIG_BOOTDELAY) defined(CONFIG_OF_CONTROL)
static void secure_boot_cmd(char *cmd)
{
cmd_tbl_t *cmdtp;
@@ -295,22 +287,21 @@ static void process_fdt_options(const void *blob)
/* Add an env variable to point to a kernel payload, if available */
addr = fdtdec_get_config_int(gd-fdt_blob, kernel-offset, 0);
- if (addr)
- setenv_addr(kernaddr, (void *)(CONFIG_SYS_TEXT_BASE + addr));
+ if (addr) {
+ setenv_addr(kernaddr,
+ (void *)(autoconf_sys_text_base() + addr));
+ }
/* Add an env variable to point to a root disk, if available */
addr = fdtdec_get_config_int(gd-fdt_blob, rootdisk-offset, 0);
- if (addr)
- setenv_addr(rootaddr, (void *)(CONFIG_SYS_TEXT_BASE + addr));
+ if (addr) {
+ setenv_addr(rootaddr,
+ (void *)(autoconf_sys_text_base() + addr));
+ }
}
-#endif /* CONFIG_OF_CONTROL */
-#ifdef CONFIG_BOOTDELAY
static void process_boot_delay(void)
{
-#ifdef CONFIG_OF_CONTROL
- char *env;
-#endif
char *s;
int bootdelay;
#ifdef CONFIG_BOOTCOUNT_LIMIT
@@ -327,7 +318,7 @@ static void process_boot_delay(void)
#endif /* CONFIG_BOOTCOUNT_LIMIT */
s = getenv (bootdelay);
- bootdelay = s ? (int)simple_strtol(s, NULL, 10) : CONFIG_BOOTDELAY;
+ bootdelay = s ? (int)simple_strtol(s, NULL, 10) : autoconf_bootdelay();
#ifdef CONFIG_OF_CONTROL
bootdelay = fdtdec_get_config_int(gd-fdt_blob, bootdelay,
@@ -357,23 +348,24 @@ static void process_boot_delay(void)
else
#endif /* CONFIG_BOOTCOUNT_LIMIT */
s = getenv (bootcmd);
-#ifdef CONFIG_OF_CONTROL
- /* Allow the fdt to override the boot command */
- env = fdtdec_get_config_string(gd-fdt_blob, bootcmd);
- if (env)
- s = env;
+ if (autoconf_of_control()) {
+ char *env;
- process_fdt_options(gd-fdt_blob);
+ /* Allow the fdt to override the boot command */
+ env = fdtdec_get_config_string(gd-fdt_blob, bootcmd);
+ if (env)
+ s = env;
- /*
-* If the bootsecure option was chosen, use secure_boot_cmd().
-* Always use 'env' in this case, since bootsecure requres that the
-* bootcmd was specified in the FDT too.
-*/
- if (fdtdec_get_config_int(gd-fdt_blob, bootsecure, 0))
- secure_boot_cmd(env);
+ process_fdt_options(gd-fdt_blob);
-#endif /* CONFIG_OF_CONTROL */
+ /*
+ * If the bootsecure option was chosen, use secure_boot_cmd().
+ * Always use 'env' in this case, since bootsecure requres that
+ * the bootcmd was specified in the FDT too.
+ */
+ if (fdtdec_get_config_int(gd-fdt_blob, bootsecure, 0))
+ secure_boot_cmd(env);
+ }
debug (### main_loop: bootcmd=\%s\\n, s ? s : UNDEFINED);
@@ -397,7 +389,6 @@ static void process_boot_delay(void)
}
#endif /* CONFIG_MENUKEY */
}
-#endif /* CONFIG_BOOTDELAY */
void main_loop(void)
{
@@
Re: [U-Boot] [PATCH v2 7/7] am335x_evm: Add support to boot from NOR.
On 17/06/13 15:49, Tom Rini wrote:
snip
Did you copy the parts that setup the pinmuxing in s_init for NOR?
This bit ?
#ifdef CONFIG_NOR_BOOT
asm(stmfd sp!, {r2 - r4});
asm(movw r4, #0x8A4);
asm(movw r3, #0x44E1);
asm(orrr4, r4, r3, lsl #16);
asm(movr2, #9);
asm(movr3, #8);
asm(gpmc_mux: str r2, [r4], #4);
asm(subs r3, r3, #1);
asm(bnegpmc_mux);
asm(ldmfd sp!, {r2 - r4});
#endif
Yes ... :-)
Mark J.
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Re: [U-Boot] [PATCH v2 7/7] am335x_evm: Add support to boot from NOR.
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
On 06/17/2013 10:59 AM, Mark Jackson wrote:
On 17/06/13 15:49, Tom Rini wrote:
snip
Did you copy the parts that setup the pinmuxing in s_init for
NOR?
This bit ?
#ifdef CONFIG_NOR_BOOT asm(stmfd sp!, {r2 - r4}); asm(movw
r4, #0x8A4); asm(movw r3, #0x44E1); asm(orrr4,
r4, r3, lsl #16); asm(movr2, #9); asm(movr3,
#8); asm(gpmc_mux: str r2, [r4], #4); asm(subs r3,
r3, #1); asm(bnegpmc_mux); asm(ldmfd sp!, {r2 -
r4}); #endif
Yes ... :-)
Right. Well, baring hints from Steve, time to hook up the JTAG and
see where it's stuck.
- --
Tom
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Comment: Using GnuPG with Thunderbird - http://www.enigmail.net/
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[U-Boot] [PATCH] am33xx: fix the ddr_cmdtctrl structure
Fix the wrong mapping between the DDR I/O control registers on AM33XX
SoCs and the software representation in the SPL code.
The most recent public TRM defines the following DDR I/O control registers
offsets:
* ddr_cmd0_ioctrl : offset 0x44E11404
* ddr_cmd1_ioctrl : offset 0x44E11408
* ddr_cmd2_ioctrl : offset 0x44E1140C
* ddr_data0_ioctrl: offset 0x44E11440
* ddr_data1_ioctrl: offset 0x44E11444
While the struct ddr_cmdtctrl has also some reserved bits in the beginning.
The struct is mapped to the address 0x44E11404. As a result cm0ioctl points
to the ddr_cmd1_ioctrl register, cm1ioctl to the ddr_cmd2_ioctrl and etc.
Registers ddr_cmd0_ioctrl and ddr_data0_ioctrl are never configured because
of this mapping mismatch.
Signed-off-by: Ilya Ledvich i...@compulab.co.il
---
arch/arm/include/asm/arch-am33xx/ddr_defs.h |1 -
1 file changed, 1 deletion(-)
diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h
b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
index fb4e78e..a529460 100644
--- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h
+++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
@@ -267,7 +267,6 @@ void config_ddr_data(const struct ddr_data *data, int nr);
* This structure represents the DDR io control on AM33XX devices.
*/
struct ddr_cmdtctrl {
- unsigned int resv1[1];
unsigned int cm0ioctl;
unsigned int cm1ioctl;
unsigned int cm2ioctl;
--
1.7.9.5
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Re: [U-Boot] [PATCH v2 7/7] am335x_evm: Add support to boot from NOR.
On 17/06/13 16:01, Tom Rini wrote:
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
On 06/17/2013 10:59 AM, Mark Jackson wrote:
On 17/06/13 15:49, Tom Rini wrote:
snip
Did you copy the parts that setup the pinmuxing in s_init for
NOR?
This bit ?
#ifdef CONFIG_NOR_BOOT asm(stmfd sp!, {r2 - r4}); asm(movw
r4, #0x8A4); asm(movw r3, #0x44E1); asm(orrr4,
r4, r3, lsl #16); asm(movr2, #9); asm(movr3,
#8); asm(gpmc_mux: str r2, [r4], #4); asm(subs r3,
r3, #1); asm(bnegpmc_mux); asm(ldmfd sp!, {r2 -
r4}); #endif
Yes ... :-)
Right. Well, baring hints from Steve, time to hook up the JTAG and
see where it's stuck.
Urm ... unfortunately, we have no JTAG on this board ... :-(
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Re: [U-Boot] [PATCH v2 7/7] am335x_evm: Add support to boot from NOR.
On 17/06/13 15:59, Mark Jackson wrote:
On 17/06/13 15:49, Tom Rini wrote:
snip
Did you copy the parts that setup the pinmuxing in s_init for NOR?
This bit ?
#ifdef CONFIG_NOR_BOOT
asm(stmfd sp!, {r2 - r4});
asm(movw r4, #0x8A4);
asm(movw r3, #0x44E1);
asm(orrr4, r4, r3, lsl #16);
asm(movr2, #9);
asm(movr3, #8);
asm(gpmc_mux: str r2, [r4], #4);
asm(subs r3, r3, #1);
asm(bnegpmc_mux);
asm(ldmfd sp!, {r2 - r4});
#endif
Yes ... :-)
Below is my entire s_init() routine.
One question ... the SPL code has:-
...
gd = gdata;
...
But there seems to be no similar assignment when in NOR boot mode.
I'm no expert in the internal workings of u-boot, so I thought I'd
check, just in case !?!
Cheers
Mark J.
---
void s_init(void)
{
/*
* The ROM will only have set up sufficient pinmux to allow for the
* first 4KiB NOR to be read, we must finish doing what we know of
* the NOR mux in this space in order to continue.
*/
#ifdef CONFIG_NOR_BOOT
asm(stmfd sp!, {r2 - r4});
asm(movw r4, #0x8A4);
asm(movw r3, #0x44E1);
asm(orrr4, r4, r3, lsl #16);
asm(movr2, #9);
asm(movr3, #8);
asm(gpmc_mux: str r2, [r4], #4);
asm(subs r3, r3, #1);
asm(bnegpmc_mux);
asm(ldmfd sp!, {r2 - r4});
#endif
/*
* Save the boot parameters passed from romcode.
* We cannot delay the saving further than this,
* to prevent overwrites.
*/
#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT)
save_omap_boot_params();
#endif
/* WDT1 is already running when the bootloader gets control
* Disable it to avoid random resets
*/
writel(0x, wdtimer-wdtwspr);
while (readl(wdtimer-wdtwwps) != 0x0)
;
writel(0x, wdtimer-wdtwspr);
while (readl(wdtimer-wdtwwps) != 0x0)
;
#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT)
/* Setup the PLLs and the clocks for the peripherals */
pll_init();
/* Enable RTC32K clock */
rtc32k_enable();
enable_board_pin_mux();
/* UART softreset */
u32 regVal;
regVal = readl(uart_base-uartsyscfg);
regVal |= UART_RESET;
writel(regVal, uart_base-uartsyscfg);
while ((readl(uart_base-uartsyssts)
UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK)
;
/* Disable smart idle */
regVal = readl(uart_base-uartsyscfg);
regVal |= UART_SMART_IDLE_EN;
writel(regVal, uart_base-uartsyscfg);
#if defined(CONFIG_NOR_BOOT)
/* We want our console now. */
gd-baudrate = CONFIG_BAUDRATE;
serial_init();
gd-have_console = 1;
puts(\nU-Boot NOR Boot\n);
#else
gd = gdata;
preloader_console_init();
#endif
config_ddr(303, MT41J128MJT125_IOCTRL_VALUE, ddr3_data,
ddr3_cmd_ctrl_data, ddr3_emif_reg_data, 0);
i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
#endif /* CONFIG_SPL_BUILD */
}
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Re: [U-Boot] [PATCH v2 7/7] am335x_evm: Add support to boot from NOR.
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
On 06/17/2013 11:23 AM, Mark Jackson wrote:
On 17/06/13 15:59, Mark Jackson wrote:
On 17/06/13 15:49, Tom Rini wrote:
snip
Did you copy the parts that setup the pinmuxing in s_init for
NOR?
This bit ?
#ifdef CONFIG_NOR_BOOT asm(stmfd sp!, {r2 - r4});
asm(movw r4, #0x8A4); asm(movw r3, #0x44E1);
asm(orrr4, r4, r3, lsl #16); asm(movr2, #9);
asm(movr3, #8); asm(gpmc_mux: str r2, [r4],
#4); asm(subs r3, r3, #1); asm(bnegpmc_mux);
asm(ldmfd sp!, {r2 - r4}); #endif
Yes ... :-)
Below is my entire s_init() routine.
One question ... the SPL code has:-
... gd = gdata; ...
But there seems to be no similar assignment when in NOR boot mode.
I'm no expert in the internal workings of u-boot, so I thought I'd
check, just in case !?!
Maybe some of the recent changes broke things? I recall having to
take a bit to track down where gd is assigned in the non-SPL case before..
- --
Tom
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Version: GnuPG v1.4.11 (GNU/Linux)
Comment: Using GnuPG with Thunderbird - http://www.enigmail.net/
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Re: [U-Boot] [PATCH v2 7/7] am335x_evm: Add support to boot from NOR.
Hi Mark,
On 17.06.2013 17:23, Mark Jackson wrote:
On 17/06/13 15:59, Mark Jackson wrote:
On 17/06/13 15:49, Tom Rini wrote:
snip
Did you copy the parts that setup the pinmuxing in s_init for NOR?
This bit ?
#ifdef CONFIG_NOR_BOOT
asm(stmfd sp!, {r2 - r4});
asm(movw r4, #0x8A4);
asm(movw r3, #0x44E1);
asm(orrr4, r4, r3, lsl #16);
asm(movr2, #9);
asm(movr3, #8);
asm(gpmc_mux: str r2, [r4], #4);
asm(subs r3, r3, #1);
asm(bnegpmc_mux);
asm(ldmfd sp!, {r2 - r4});
#endif
Yes ... :-)
Below is my entire s_init() routine.
One question ... the SPL code has:-
...
gd = gdata;
...
But there seems to be no similar assignment when in NOR boot mode.
I'm no expert in the internal workings of u-boot, so I thought I'd
check, just in case !?!
I just noticed you mentioning gd here and wanted to point you to a
patch that fixed a gd-related boot issue for me on OMAP3:
[U-Boot] [PATCH 1/3] arm: spl: Fix SPL booting for OMAP3
(sorry, I can't find a link to this patch right now and I'm in a hurry)
Not sure if this has something to do with your problem (I don't have the
time to dig into this mail thread today as I'm leaving right now).
Cheers,
Stefan
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Re: [U-Boot] [PATCH v2 7/7] am335x_evm: Add support to boot from NOR.
On 17/06/13 17:01, Stefan Roese wrote:
Hi Mark,
On 17.06.2013 17:23, Mark Jackson wrote:
snip
One question ... the SPL code has:-
...
gd = gdata;
...
But there seems to be no similar assignment when in NOR boot mode.
I'm no expert in the internal workings of u-boot, so I thought I'd
check, just in case !?!
I just noticed you mentioning gd here and wanted to point you to a
patch that fixed a gd-related boot issue for me on OMAP3:
[U-Boot] [PATCH 1/3] arm: spl: Fix SPL booting for OMAP3
(sorry, I can't find a link to this patch right now and I'm in a hurry)
Not sure if this has something to do with your problem (I don't have the
time to dig into this mail thread today as I'm leaving right now).
I'll look at that thanks.
But I've taken a slightly different approach, and added the following
to the start of s_init() ...
void s_init(void)
{
unsigned short *p = (unsigned short*)0x0800;
while (1)
{
int i;
for (i = 0; i (1 * 1024); i++)
{
unsigned short d = p[i];
d++;
*p = d;
}
}
...
AFAICT, that should just spin on reading/writing the NOR device,
but I still get only an initial 350us burst on the CS0 line, and
then nothing.
So I can only assume that the boot code isn't getting as far as
s_init() at all !!
In start.S and low_levelinit.c, there are various uses of:-
#ifdef CONFIG_SPL_BUILD
Do any of these also need referencing with a CONFIG_NOR_BOOT ?
Mark J.
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Re: [U-Boot] [PATCH v3 1/3] ARM: Tegra: FDT: Add USB EHCI function for T30/T114
On 06/17/2013 03:09 AM, Jim Lin wrote:
Add DT node for USB EHCI function.
Add support for T30-Cardhu, T30-Beaver, T114-Dalmore boards.
This patch shouldn't touch both DT files and code at the same time. The
code changes should be part of the patch to the USB driver.
diff --git a/board/nvidia/dts/tegra30-cardhu.dts
b/board/nvidia/dts/tegra30-cardhu.dts
+ usb@7d008000 {
+ nvidia,vbus-gpio = gpio 233 3; /* PDD1, EN_3V3_PU */
+ status = okay;
+ };
PDD1 is the wrong signal. That enables a 100L pullup to a bunch of
different signals, including the VBUS GPIO. Instead, I think you should
be using PEX_L1_PRSNT / EN_USB3_VBUS_OC / PDD4, which co-incidentally
matches the value in the Beaver .dts file in this patch, most likely
because Beaver is closely based on Cardhu.
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Re: [U-Boot] [PATCH v3 2/3] ARM: Tegra: USB: EHCI: Add support for Tegra30/Tegra114
On 06/17/2013 03:09 AM, Jim Lin wrote:
Tegra30 and Tegra114 are compatible except PLL parameters.
Tested on Tegra30 Cardhu, and Tegra114 Dalmore
platforms. All works well.
diff --git a/drivers/usb/host/ehci-tegra.c b/drivers/usb/host/ehci-tegra.c
+static u32 port_clear_csc; /* Port that needs to clear CSC after Port Reset
*/
What units is that variable in? The variable name should be more like
status_reg_addr_needing_clear_csc.
+static unsigned is_T30_compatible;
+static unsigned is_T114_compatible;
Given that there is code in this patch that does:
+ if (is_T30_compatible) {
+ if (is_T114_compatible)
I think those should be is_T30_or_later and is_T114_or_later.
But, testing against SoC version is the wrong way to go. Instead, the
code should set a bunch of feature flags based on the SoC it's running
on during initialization, and then test those feature flags throughout
the code. That way, if Tegra30 and (hypothetical future chips) Tegra200
and Tegra300 need a fix, but Tegra114 doesn't, you don't have to write
tortuous if statements throughout the code, but simply have a lookup
table that maps from SoC ID to the set of feature/fix flags that it needs.
See for example Linux kernel driver drivers/gpio/gpio-tegra.c's
tegra20_gpio_config, tegra30_gpio_config, and tegra_gpio_of_match[], or
drivers/dma/tegra20-apb-dma.c's tegra_dma_of_match[].
+static const unsigned *get_pll_timing(void)
+{
+ const unsigned *timing;
+
+ if (is_T30_compatible) {
+ if (is_T114_compatible)
+ timing = T114_usb_pll[clock_get_osc_freq()];
+ else
+ timing = T30_usb_pll[clock_get_osc_freq()];
+ } else {
+ timing = T20_usb_pll[clock_get_osc_freq()];
+ }
+
+ return timing;
+}
Following on from the feature flag discussion above, it'd be better to
simply include a pointer in the per-SoC configuration table that pointed
at the PLL table. That way, this function could be removed, and replaced
with a simple read through a pointer.
+int board_usb_init(const void *blob)
+{
+ int node_list[USB_PORTS_MAX];
+ int count, err = 0;
+
+ is_T30_compatible = 0;
+ is_T114_compatible = 0;
+
+ /* count may return 0 on error */
+ count = fdtdec_find_aliases_for_id(blob, usb,
+ COMPAT_NVIDIA_TEGRA20_USB, node_list, USB_PORTS_MAX);
+ if (count) {
+ err = process_usb_nodes(blob, node_list, count);
+ if (err)
+ printf(%s: Error processing T20 USB node!\n,
+__func__);
+ return err;
+ }
+ count = fdtdec_find_aliases_for_id(blob, usb,
+ COMPAT_NVIDIA_TEGRA114_USB, node_list, USB_PORTS_MAX);
+ if (count)
+ is_T114_compatible = 1;
+ else
+ count = fdtdec_find_aliases_for_id(blob, usb,
+ COMPAT_NVIDIA_TEGRA30_USB, node_list, USB_PORTS_MAX);
+ if (count) {
+ /* T114 is also mostly compatible to T30 */
+ is_T30_compatible = 1;
+ err = process_usb_nodes(blob, node_list, count);
+ if (err) {
+ if (is_T114_compatible)
+ printf(%s: Error processing T114 USB node!\n,
+__func__);
+ else
+ printf(%s: Error processing T30 USB node!\n,
+__func__);
(Following on from the comment below: Why not just say USB node rather
than T30 USB node or T114 USB node here. That way, you completely
avoid having to write an if statement.
+ }
+ }
+
+ return err;
+}
This function is pretty convoluted. It'd be far better to enhance
fdtdec_find_aliases_for_id() to accept a list of compatible values, and
simply return all matching instances in one go.
fdtdec_find_aliases_for_id() should also return the type of each
match, so you know if each one is a Tegra20/30/114 port.
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Re: [U-Boot] [PATCH v3 3/3] Tegra: Config: Enable Tegra30/Tegra114 USB function
On 06/17/2013 03:09 AM, Jim Lin wrote: Add USB EHCI, storage and network support. Tested on Tegra30 Cardhu, and Tegra114 Dalmore platforms. All works well. diff --git a/include/configs/beaver.h b/include/configs/beaver.h +/* USB Host support */ I notice that some Tegra20 boards include the following line here: #define CONFIG_USB_MAX_CONTROLLER_COUNT 3 Is this necessary here too? If it doesn't serve any purpose, can you send an extra patch to remove this from seaboard.h, harmony.h, trimslice.h, and colibtri_t20_iris.h. Thanks. +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_TEGRA +#define CONFIG_USB_STORAGE +#define CONFIG_CMD_USB ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/2] video: lcd: Add CONFIG_SPLASH_SCREEN_PREPARE support to CONFIG_VIDEO
Hi Igor,
On Sun, Jun 16, 2013 at 10:34 PM, Igor Grinberg grinb...@compulab.co.il wrote:
Hi Robert,
On 06/14/13 20:00, Robert Winkler wrote:
Create splash.c/h to put the function and any future common
splash screen code in.
Signed-off-by: Robert Winkler robert.wink...@boundarydevices.com
Thanks for the effort!
Several comments below...
---
common/Makefile | 1 +
common/lcd.c| 19 ++-
common/splash.c | 37 +
drivers/video/cfb_console.c | 8 ++--
include/lcd.h | 1 -
include/splash.h| 30 ++
6 files changed, 80 insertions(+), 16 deletions(-)
create mode 100644 common/splash.c
create mode 100644 include/splash.h
diff --git a/common/Makefile b/common/Makefile
index 0e0fff1..1d70584 100644
--- a/common/Makefile
+++ b/common/Makefile
@@ -203,6 +203,7 @@ COBJS-y += flash.o
COBJS-$(CONFIG_CMD_KGDB) += kgdb.o kgdb_stubs.o
COBJS-$(CONFIG_I2C_EDID) += edid.o
COBJS-$(CONFIG_KALLSYMS) += kallsyms.o
+COBJS-y += splash.o
I think this should depend on CONFIG_SPLASH_SCREEN.
No it shouldn't. The function is always called so it always needs to
be defined. It's the
same behavior we had before, it was always compiled into lcd.h.
Whether or not the CONFIG
was defined just changed whether it actually called
board_splash_screen_prepare or just returned 0.
This is of course true for when it's a weak function as well.
COBJS-$(CONFIG_LCD) += lcd.o
COBJS-$(CONFIG_LYNXKDI) += lynxkdi.o
COBJS-$(CONFIG_MENU) += menu.o
diff --git a/common/lcd.c b/common/lcd.c
index 3a60484..4a85ebb 100644
--- a/common/lcd.c
+++ b/common/lcd.c
@@ -43,6 +43,11 @@
#include lcd.h
#include watchdog.h
+/*
+ * Include splash.h for splash_screen_prepare() etc.
+ */
I think this comment is meaningless, the below include is self explanatory.
Agreed. I was just trying to match the other superfluous comments.
+#include splash.h
+
#if defined(CONFIG_CPU_PXA25X) || defined(CONFIG_CPU_PXA27X) || \
defined(CONFIG_CPU_MONAHANS)
#define CONFIG_CPU_PXA
@@ -1072,18 +1077,6 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y)
}
#endif
-#ifdef CONFIG_SPLASH_SCREEN_PREPARE
-static inline int splash_screen_prepare(void)
-{
- return board_splash_screen_prepare();
-}
-#else
-static inline int splash_screen_prepare(void)
-{
- return 0;
-}
-#endif
-
static void *lcd_logo(void)
{
#ifdef CONFIG_SPLASH_SCREEN
@@ -1096,7 +1089,7 @@ static void *lcd_logo(void)
do_splash = 0;
if (splash_screen_prepare())
- return (void *)gd-fb_base;
+ return (void *)lcd_base;
addr = simple_strtoul (s, NULL, 16);
#ifdef CONFIG_SPLASH_SCREEN_ALIGN
diff --git a/common/splash.c b/common/splash.c
new file mode 100644
index 000..fe13c69
--- /dev/null
+++ b/common/splash.c
@@ -0,0 +1,37 @@
+/*
+ * Copyright (C) 2013, Boundary Devices i...@boundarydevices.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
I would drop the postal address, as it changed in the past and
probably will change in the future and then we will have a bunch of
files with wrong address...
Good point, will do.
+ */
+
+#include splash.h
+#include config.h
+
+#ifdef CONFIG_SPLASH_SCREEN_PREPARE
+int splash_screen_prepare(void)
+{
+ return board_splash_screen_prepare();
+}
+#else
+int splash_screen_prepare(void)
+{
+ printf(SPLASH_SCREEN_PREPARE not defined\n);
+ return 0;
+}
+#endif
diff --git a/drivers/video/cfb_console.c b/drivers/video/cfb_console.c
index b769222..4543730 100644
--- a/drivers/video/cfb_console.c
+++ b/drivers/video/cfb_console.c
@@ -178,6 +178,11 @@
#include video_fb.h
/*
+ * Include splash.h for splash_screen_prepare() etc.
+ */
Same here, the below include does not need any comment.
+#include splash.h
+
+/*
* some Macros
*/
#define VIDEO_VISIBLE_COLS (pGD-winSizeX)
@@ -1991,10 +1996,9 @@ static void *video_logo(void)
#ifdef CONFIG_SPLASH_SCREEN
s = getenv(splashimage);
if (s != NULL) {
-
+
Re: [U-Boot] [SPI-TEST]: Request for test u-boot-spi/master-work
Hi Gary - Please check Jagan's latest patches on your HW. --Max -Original Message- From: Jagan Teki [mailto:jagannadh.t...@gmail.com] Sent: Saturday, June 15, 2013 11:49 AM To: U-Boot Mailing List Cc: Tom Rini; Michal Simek; Simon Glass; Rajeshwari Shinde; Syed Hussain; Willis, Max; Todd Legler (tlegler); Hoyler, Gernot; Daassi, Bacem Subject: [SPI-TEST]: Request for test u-boot-spi/master-work Hi All, In-fact this is a first time for sending test tagged mail. The reason for sending this is: We added many changes on spi_flash framework to support all sizes of flashes. I'd appreciate if anyone can test this master-work branch on u-boot-spi.git repo with your respective hw's $ git clone git://git.denx.de/u-boot-spi.git $ cd u-boot-spi $ git checkout -b master-work origin/master-work Please let me know for any issues/concerns. Apologies, if anyone hurt this kind of mail. -- Thanks, Jagan. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 7/7] am335x_evm: Add support to boot from NOR.
-Original Message-
From: Mark Jackson [mailto:mpfj-l...@newflow.co.uk]
Sent: Monday, June 17, 2013 11:10 AM
To: Stefan Roese
Cc: Rini, Tom; Kipisz, Steven; u-boot@lists.denx.de
Subject: Re: [U-Boot] [PATCH v2 7/7] am335x_evm: Add support to boot
from NOR.
On 17/06/13 17:01, Stefan Roese wrote:
Hi Mark,
On 17.06.2013 17:23, Mark Jackson wrote:
snip
One question ... the SPL code has:-
...
gd = gdata;
...
But there seems to be no similar assignment when in NOR boot mode.
I'm no expert in the internal workings of u-boot, so I thought I'd
check, just in case !?!
I just noticed you mentioning gd here and wanted to point you to a
patch that fixed a gd-related boot issue for me on OMAP3:
[U-Boot] [PATCH 1/3] arm: spl: Fix SPL booting for OMAP3
(sorry, I can't find a link to this patch right now and I'm in a
hurry)
Not sure if this has something to do with your problem (I don't have
the time to dig into this mail thread today as I'm leaving right now).
I'll look at that thanks.
But I've taken a slightly different approach, and added the following to the
start of s_init() ...
void s_init(void)
{
unsigned short *p = (unsigned short*)0x0800;
while (1)
{
int i;
for (i = 0; i (1 * 1024); i++)
{
unsigned short d = p[i];
d++;
*p = d;
}
}
...
AFAICT, that should just spin on reading/writing the NOR device, but I still
get
only an initial 350us burst on the CS0 line, and then nothing.
So I can only assume that the boot code isn't getting as far as
s_init() at all !!
In start.S and low_levelinit.c, there are various uses of:-
#ifdef CONFIG_SPL_BUILD
Do any of these also need referencing with a CONFIG_NOR_BOOT ?
Mark J.
Do you have a u-boot.lds in board/ti/am335x? That should put s_init() earlier
in the boot. Also, include/configs/am335x_evm.h should have
/* Custom script for NOR */
#define CONFIG_SYS_LDSCRIPT board/ti/am335x/u-boot.lds
Before using JTAG, take a look in System.map where s_init is located. For a
multiplex NOR it should be in the first 64K of address space.
Steve K.
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[U-Boot] [PATCH] mtd: nand/docg4: fix driver after Linux resync
Commit dfe64e2c89731a3f9950d7acd8681b68df2bae03:
mtd: resync with Linux-3.7.1
broke the docg4 driver. Specifically:
- some of the prototypes of the ecc methods changed
- the NAND_NO_AUTOINCR flag was removed
- the ecc.strength element was added.
This patch fixes these. Tested on the docg4 on my palmtre680 board.
Signed-off-by: Mike Dunn miked...@newsguy.com
---
drivers/mtd/nand/docg4.c | 26 ++
1 files changed, 14 insertions(+), 12 deletions(-)
diff --git a/drivers/mtd/nand/docg4.c b/drivers/mtd/nand/docg4.c
index 7dd9953..09f01c8 100644
--- a/drivers/mtd/nand/docg4.c
+++ b/drivers/mtd/nand/docg4.c
@@ -487,7 +487,7 @@ static void docg4_read_buf(struct mtd_info *mtd, uint8_t
*buf, int len)
}
static int docg4_read_oob(struct mtd_info *mtd, struct nand_chip *nand,
- int page, int sndcmd)
+ int page)
{
struct docg4_priv *doc = nand-priv;
void __iomem *docptr = CONFIG_SYS_NAND_BASE;
@@ -577,7 +577,7 @@ static void docg4_write_buf16(struct mtd_info *mtd, const
uint8_t *buf, int len)
writew(p[i], nand-IO_ADDR_W);
}
-static void write_page(struct mtd_info *mtd, struct nand_chip *nand,
+static int write_page(struct mtd_info *mtd, struct nand_chip *nand,
const uint8_t *buf, int use_ecc)
{
void __iomem *docptr = CONFIG_SYS_NAND_BASE;
@@ -626,16 +626,18 @@ static void write_page(struct mtd_info *mtd, struct
nand_chip *nand,
write_nop(docptr);
writew(0, docptr + DOC_DATAEND);
write_nop(docptr);
+
+ return 0;
}
-static void docg4_write_page_raw(struct mtd_info *mtd, struct nand_chip *nand,
-const uint8_t *buf)
+static int docg4_write_page_raw(struct mtd_info *mtd, struct nand_chip *nand,
+const uint8_t *buf, int oob_required)
{
return write_page(mtd, nand, buf, 0);
}
-static void docg4_write_page(struct mtd_info *mtd, struct nand_chip *nand,
-const uint8_t *buf)
+static int docg4_write_page(struct mtd_info *mtd, struct nand_chip *nand,
+const uint8_t *buf, int oob_required)
{
return write_page(mtd, nand, buf, 1);
}
@@ -706,13 +708,13 @@ static int read_page(struct mtd_info *mtd, struct
nand_chip *nand,
static int docg4_read_page_raw(struct mtd_info *mtd, struct nand_chip *nand,
- uint8_t *buf, int page)
+ uint8_t *buf, int oob_required, int page)
{
return read_page(mtd, nand, buf, page, 0);
}
static int docg4_read_page(struct mtd_info *mtd, struct nand_chip *nand,
- uint8_t *buf, int page)
+ uint8_t *buf, int oob_required, int page)
{
return read_page(mtd, nand, buf, page, 1);
}
@@ -779,7 +781,7 @@ static int read_factory_bbt(struct mtd_info *mtd)
return -ENOMEM;
read_page_prologue(CONFIG_SYS_NAND_BASE, g4_addr);
- status = docg4_read_page(mtd, nand, buf, DOCG4_FACTORY_BBT_PAGE);
+ status = docg4_read_page(mtd, nand, buf, 0, DOCG4_FACTORY_BBT_PAGE);
if (status)
goto exit;
@@ -858,7 +860,7 @@ static int docg4_block_markbad(struct mtd_info *mtd, loff_t
ofs)
/* write first page of block */
write_page_prologue(CONFIG_SYS_NAND_BASE, g4_addr);
- docg4_write_page(mtd, nand, buf);
+ docg4_write_page(mtd, nand, buf, 1);
ret = pageprog(mtd);
if (!ret)
mtd-ecc_stats.badblocks++;
@@ -959,8 +961,8 @@ int docg4_nand_init(struct mtd_info *mtd, struct nand_chip
*nand, int devnum)
nand-ecc.size = DOCG4_PAGE_SIZE;
nand-ecc.prepad = 8;
nand-ecc.bytes = 8;
- nand-options =
- NAND_BUSWIDTH_16 | NAND_NO_SUBPAGE_WRITE | NAND_NO_AUTOINCR;
+ nand-ecc.strength = DOCG4_T;
+ nand-options = NAND_BUSWIDTH_16 | NAND_NO_SUBPAGE_WRITE;
nand-controller = nand-hwcontrol;
/* methods */
--
1.7.8.6
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[U-Boot] [PATCH] pxa: turn icache off in cpu_init_crit()
The comment in the low-level initialization function cpu_init_crit() says that the caches are being disabled, but (oddly) the icache is actually turned on. This is probably not a good idea prior to relocating code, so this patch turns it off. Tested on the pxa270. Signed-off-by: Mike Dunn miked...@newsguy.com --- Because the current code seems quite deliberate in setting the icache bit, I looked for evidence of an errata on the pxa25x whereby the logic of this bit is inverted, but couldn't find any. arch/arm/cpu/pxa/start.S |3 +-- 1 files changed, 1 insertions(+), 2 deletions(-) diff --git a/arch/arm/cpu/pxa/start.S b/arch/arm/cpu/pxa/start.S index 2e3f65e..b1deb72 100644 --- a/arch/arm/cpu/pxa/start.S +++ b/arch/arm/cpu/pxa/start.S @@ -208,10 +208,9 @@ cpu_init_crit: * disable MMU stuff and caches */ mrc p15, 0, r0, c1, c0, 0 - bic r0, r0, #0x2300 @ clear bits 13, 9:8 (--V- --RS) + bic r0, r0, #0x3300 @ clear bits 13:12, 9:8 (--VI --RS) bic r0, r0, #0x0087 @ clear bits 7, 2:0 (B--- -CAM) orr r0, r0, #0x0002 @ set bit 2 (A) Align - orr r0, r0, #0x1000 @ set bit 12 (I) I-Cache mcr p15, 0, r0, c1, c0, 0 mov pc, lr /* back to my caller */ -- 1.7.8.6 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] arm: fix memory coherency problem after relocation
On the xscale, the icache must be invalidated and the write buffers drained after writing code over the data bus, even if the caches are disabled. After rebasing with the main git repository, u-boot began crashing in odd places on my pxa270 board (palmtreo680) after the code relocation routine ran. This patch fixes it. Cache coherency problems are often hit-and-miss (ha ha), and this latent problem didn't rear its ugly head until now. Tested on the pxa270. Signed-off-by: Mike Dunn miked...@newsguy.com --- I realize that __ARM_ARCH_5TE__ does not necessarily mean xscale. But how else to test for pxa2xx/ixp in an assembly file? I wouldn't expect any ill effects on a non-xscale v5te because these CP15 operations are defined the same way in the ARM Architecture Reference Manual for v5 cores, but unfortunately I only have a pxa270 xscale to test on. I experienced this same problem a couple years ago when I was getting OpenOCD working on the xscale. Often software breakpoints (replacing an instruction with the 'bkpt' instruction) would fail unless this operation was performed after replacing the instruction, even with caches off. The following two paragraphs are cut from section 4.2.7 of the xscale core developer's manual... If the instruction cache is not enabled, or code is being written to a non-cacheable region, software must still invalidate the instruction cache before using the newly-written code. This precaution ensures that state associated with the new code is not buffered elsewhere in the processor, such as the fetch buffers or the BTB. Naturally, when writing code as data, care must be taken to force it completely out of the processor into external memory before attempting to execute it. If writing into a non-cacheable region, flushing the write buffers is sufficient precaution (see Section 7.2.8 for a description of this arch/arm/lib/relocate.S | 10 ++ 1 files changed, 10 insertions(+), 0 deletions(-) diff --git a/arch/arm/lib/relocate.S b/arch/arm/lib/relocate.S index 4446da9..e2febed 100644 --- a/arch/arm/lib/relocate.S +++ b/arch/arm/lib/relocate.S @@ -92,6 +92,16 @@ fixnext: relocate_done: +#ifdef __ARM_ARCH_5TE__ + /* +* On xscale, icache must be invalidated and write buffers drained, +* even with cache disabled - 4.2.7 of xscale core developer's manual +*/ + mov r0, #0 /* arm reference manual: data SBZ */ + mcr p15, 0, r0, c7, c7, 0 /* invalidate icache */ + mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */ +#endif + /* ARMv4- don't know bx lr but the assembler fails to see that */ #ifdef __ARM_ARCH_4__ -- 1.7.8.6 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 2/3] video: lcd: Make splash_screen_prepare weak, remove config macro
Remove CONFIG_SPLASH_SCREEN_PREPARE from README
Add doc/README.splashprepare to document functionality
Signed-off-by: Robert Winkler robert.wink...@boundarydevices.com
---
README | 8
common/splash.c | 13 -
doc/README.splashprepare | 8
3 files changed, 12 insertions(+), 17 deletions(-)
create mode 100644 doc/README.splashprepare
diff --git a/README b/README
index b72ab2f..0686073 100644
--- a/README
+++ b/README
@@ -1605,14 +1605,6 @@ CBFS (Coreboot Filesystem) support
= vertically centered image
at x = dspWidth - bmpWidth - 9
- CONFIG_SPLASH_SCREEN_PREPARE
-
- If this option is set then the board_splash_screen_prepare()
- function, which must be defined in your code, is called as part
- of the splash screen display sequence. It gives the board an
- opportunity to prepare the splash image data before it is
- processed and sent to the frame buffer by U-Boot.
-
- Gzip compressed BMP image support: CONFIG_VIDEO_BMP_GZIP
If this option is set, additionally to standard BMP
diff --git a/common/splash.c b/common/splash.c
index 98de2be..1882e5f 100644
--- a/common/splash.c
+++ b/common/splash.c
@@ -21,16 +21,11 @@
*/
#include splash.h
-#include config.h
-#ifdef CONFIG_SPLASH_SCREEN_PREPARE
-int splash_screen_prepare(void)
-{
- return board_splash_screen_prepare();
-}
-#else
-int splash_screen_prepare(void)
+int __splash_screen_prepare(void)
{
return 0;
}
-#endif
+
+int splash_screen_prepare(void)
+ __attribute__ ((weak, alias(__splash_screen_prepare)));
diff --git a/doc/README.splashprepare b/doc/README.splashprepare
new file mode 100644
index 000..61b4ec5
--- /dev/null
+++ b/doc/README.splashprepare
@@ -0,0 +1,8 @@
+-
+Splash Screen
+-
+The splash_screen_prepare() function is a weak function defined in
+common/splash.c. It is called as part of the splash screen display
+sequence. It gives the board an opportunity to prepare the splash
+image data before it is processed and sent to the frame buffer by
+U-Boot. Define your own version to use this feature.
--
1.8.3
___
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[U-Boot] [PATCH 0/3 v2] video: lcd: splash screen prepare changes
The first 2 patches are the result of discussion in these threads: http://lists.denx.de/pipermail/u-boot/2013-May/155463.html http://lists.denx.de/pipermail/u-boot/2013-June/155630.html http://lists.denx.de/pipermail/u-boot/2013-June/155632.html The upshot is, move splash_screen_prepare to a common location so it can be used in cfb_console.c and (possibly) make it weak. The first patch can be accepted without the last two. The third patch is a fix for cm_t35 that's only necessary if we make it weak. Robert Winkler (3): video: lcd: Add CONFIG_SPLASH_SCREEN_PREPARE support to CONFIG_VIDEO video: lcd: Make splash_screen_prepare weak, remove config macro omap: cm_t35: Fix cm_t35 for weak splash_screen_prepare README | 8 board/compulab/cm_t35/cm_t35.c | 2 +- common/Makefile| 1 + common/lcd.c | 16 +++- common/splash.c| 31 +++ doc/README.splashprepare | 8 drivers/video/cfb_console.c| 5 +++-- include/configs/cm_t35.h | 1 - include/lcd.h | 1 - include/splash.h | 29 + 10 files changed, 76 insertions(+), 26 deletions(-) create mode 100644 common/splash.c create mode 100644 doc/README.splashprepare create mode 100644 include/splash.h -- 1.8.3 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/3 v2] video: lcd: Add CONFIG_SPLASH_SCREEN_PREPARE support to CONFIG_VIDEO
Create splash.c/h to put the function and any future common splash
screen code in.
Signed-off-by: Robert Winkler robert.wink...@boundarydevices.com
---
v2 changes:
remove superfluous comments
remove debug printf that slipped in
remove address from GPL comments
common/Makefile | 1 +
common/lcd.c| 16 +++-
common/splash.c | 36
drivers/video/cfb_console.c | 5 +++--
include/lcd.h | 1 -
include/splash.h| 29 +
6 files changed, 72 insertions(+), 16 deletions(-)
create mode 100644 common/splash.c
create mode 100644 include/splash.h
diff --git a/common/Makefile b/common/Makefile
index 1cfb132..b48f227 100644
--- a/common/Makefile
+++ b/common/Makefile
@@ -204,6 +204,7 @@ COBJS-y += flash.o
COBJS-$(CONFIG_CMD_KGDB) += kgdb.o kgdb_stubs.o
COBJS-$(CONFIG_I2C_EDID) += edid.o
COBJS-$(CONFIG_KALLSYMS) += kallsyms.o
+COBJS-y += splash.o
COBJS-$(CONFIG_LCD) += lcd.o
COBJS-$(CONFIG_LYNXKDI) += lynxkdi.o
COBJS-$(CONFIG_MENU) += menu.o
diff --git a/common/lcd.c b/common/lcd.c
index edae835..72ffcfb 100644
--- a/common/lcd.c
+++ b/common/lcd.c
@@ -43,6 +43,8 @@
#include lcd.h
#include watchdog.h
+#include splash.h
+
#if defined(CONFIG_CPU_PXA25X) || defined(CONFIG_CPU_PXA27X) || \
defined(CONFIG_CPU_MONAHANS)
#define CONFIG_CPU_PXA
@@ -1068,18 +1070,6 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y)
}
#endif
-#ifdef CONFIG_SPLASH_SCREEN_PREPARE
-static inline int splash_screen_prepare(void)
-{
- return board_splash_screen_prepare();
-}
-#else
-static inline int splash_screen_prepare(void)
-{
- return 0;
-}
-#endif
-
static void *lcd_logo(void)
{
#ifdef CONFIG_SPLASH_SCREEN
@@ -1092,7 +1082,7 @@ static void *lcd_logo(void)
do_splash = 0;
if (splash_screen_prepare())
- return (void *)gd-fb_base;
+ return (void *)lcd_base;
addr = simple_strtoul (s, NULL, 16);
#ifdef CONFIG_SPLASH_SCREEN_ALIGN
diff --git a/common/splash.c b/common/splash.c
new file mode 100644
index 000..98de2be
--- /dev/null
+++ b/common/splash.c
@@ -0,0 +1,36 @@
+/*
+ * Copyright (C) 2013, Boundary Devices i...@boundarydevices.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., http://www.fsf.org/about/contact/
+ *
+ */
+
+#include splash.h
+#include config.h
+
+#ifdef CONFIG_SPLASH_SCREEN_PREPARE
+int splash_screen_prepare(void)
+{
+ return board_splash_screen_prepare();
+}
+#else
+int splash_screen_prepare(void)
+{
+ return 0;
+}
+#endif
diff --git a/drivers/video/cfb_console.c b/drivers/video/cfb_console.c
index 0793f07..4e299c6 100644
--- a/drivers/video/cfb_console.c
+++ b/drivers/video/cfb_console.c
@@ -181,6 +181,8 @@
*/
#include video_fb.h
+#include splash.h
+
/*
* some Macros
*/
@@ -1995,10 +1997,9 @@ static void *video_logo(void)
#ifdef CONFIG_SPLASH_SCREEN
s = getenv(splashimage);
if (s != NULL) {
-
+ splash_screen_prepare();
addr = simple_strtoul(s, NULL, 16);
-
if (video_display_bitmap(addr,
video_logo_xpos,
video_logo_ypos) == 0) {
diff --git a/include/lcd.h b/include/lcd.h
index c6e7fc5..e58ffd0 100644
--- a/include/lcd.h
+++ b/include/lcd.h
@@ -37,7 +37,6 @@ extern struct vidinfo panel_info;
void lcd_ctrl_init(void *lcdbase);
void lcd_enable(void);
-int board_splash_screen_prepare(void);
/* setcolreg used in 8bpp/16bpp; initcolregs used in monochrome */
void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue);
diff --git a/include/splash.h b/include/splash.h
new file mode 100644
index 000..63b45e0
--- /dev/null
+++ b/include/splash.h
@@ -0,0 +1,29 @@
+/*
+ * Copyright (C) 2013, Boundary Devices i...@boundarydevices.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+
Re: [U-Boot] [PATCH v5 13/14] mmc: ftsdc010_mci: clk_get_rate() - clock_get_rate()
On Mon, Jun 17, 2013 at 7:07 AM, Kuo-Jung Su dant...@gmail.com wrote: From: Kuo-Jung Su dant...@faraday-tech.com This updates ftsdc010_mci.c for latest Faraday clock APIs. Signed-off-by: Kuo-Jung Su dant...@faraday-tech.com CC: Albert Aribaud albert.u.b...@aribaud.net CC: Andy Fleming aflem...@gmail.com Acked-by: Andy Fleming aflem...@freescale.com Since this is part of a series, it should go in with the rest of them, rather than through the mmc tree. Andy ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
