From: Jens Scharsig (BuS Elektronik) e...@bus-elektronik.de
Since UBIFS is enabled for cpux9k2, more malloc space is needed.
For the current uboot 2013.10-rcX the size is to small, this will fix the
startup problems by increasing the mallog space to 4MiB.
Signed-off-by: Jens Scharsig (BuS
Hi Rajeshwari,
On Wed, Sep 11, 2013 at 4:01 AM, Rajeshwari S Shinde
rajeshwar...@samsung.com wrote:
From: Akshay Saraswat aksha...@samsung.com
This patch modifies UNCON and UFCON values to make s5p
serial support exynos5420 by doing following changes:
* Enable Rx time-out interrupts.
*
Hi Rajeshwari,
On Wed, Sep 11, 2013 at 4:01 AM, Rajeshwari S Shinde
rajeshwar...@samsung.com wrote:
From: Akshay Saraswat aksha...@samsung.com
Adds code in pinmux and gpio framework to support Exynos5420.
Signed-off-by: Rajeshwari S Shinde rajeshwar...@samsung.com
Signed-off-by: Akshay
Hi Rajeshwari,
On Wed, Sep 11, 2013 at 4:01 AM, Rajeshwari S Shinde
rajeshwar...@samsung.com wrote:
Adding the base patch for Exynos based SMDK5420.
This shall enable compilation and basic boot support for
SMDK5420.
Signed-off-by: Rajeshwari S Shinde rajeshwar...@samsung.com
Hi Rajeshwari,
On Wed, Sep 11, 2013 at 4:01 AM, Rajeshwari S Shinde
rajeshwar...@samsung.com wrote:
This patch adds support for SMDK5420.
exynos5.dtsi created is a common file which has the nodes common
to both 5420 and 5250.
Signed-off-by: Akshay Saraswat aksha...@samsung.com
Hi Rajeshwari,
On Wed, Sep 11, 2013 at 4:01 AM, Rajeshwari S Shinde
rajeshwar...@samsung.com wrote:
Adding initial config for SMDK5420 to build and boot U-Boot
over Exynos based SMDK5420.
Signed-off-by: Rajeshwari S Shinde rajeshwar...@samsung.com
Signed-off-by: Akshay Saraswat
On Wed, Sep 11, 2013 at 4:01 AM, Rajeshwari S Shinde
rajeshwar...@samsung.com wrote:
When variable size SPL is used, the BL1 expects the SPL to be
encapsulated differently: instead of putting the checksum at a fixed
offset in the SPL blob, prepend the blob with a header including the
size
Hi Rajeshwari,
On Wed, Sep 11, 2013 at 4:01 AM, Rajeshwari S Shinde
rajeshwar...@samsung.com wrote:
SMDK5420 has a new Security Management Unit added
for dwmmc driver, hence, configuring the control
registers to support booting via eMMC.
Signed-off-by: Alim Akhtar alim.akh...@samsung.com
Hi,
On Sun, Sep 15, 2013 at 12:15 PM, Jagannadha Sutradharudu Teki
jagannadha.sutradharudu-t...@xilinx.com wrote:
Added new spi_flash_probe support, currently added N25Q*
flash part attributes support.
Updated the sector_size attributes as per the flash parts.
Looks fine for with this
Hi Masahiro,
On Tue, 17 Sep 2013 09:55:00 +0900, Masahiro Yamada
yamad...@jp.panasonic.com wrote:
Hello Albert, Tom.
Commit 27af930e9 added Active/Orphan status in the first column of boards.cfg.
Could you tell the definition of Active and Orphan.
At first I imagined Orphan means a
Hi Masahiro,
On Wed, 18 Sep 2013 13:00:18 +0900, Masahiro Yamada
yamad...@jp.panasonic.com wrote:
Hello Albert.
Commit 27af930e modified top Makefile as follows:
--- a/Makefile
+++ b/Makefile
@@ -838,7 +838,7 @@ unconfig:
sinclude $(obj).boards.depend
Hi Philippe,
On Wed, 18 Sep 2013 21:22:02 +0200, Philippe Reynes trem...@yahoo.fr
wrote:
Signed-off-by: Philippe Reynes trem...@yahoo.fr
---
README | 11 +++
arch/arm/cpu/armv7/mx5/clock.c |2 +-
arch/arm/cpu/armv7/mx6/clock.c |2 +-
Hi Jeroen,
On Sat, 17 Aug 2013 15:55:16 +0200, Jeroen Hofstee
jer...@myspectrum.nl wrote:
On 08/14/2013 08:25 PM, Jeroen Hofstee wrote:
diff --git a/arch/arm/config.mk b/arch/arm/config.mk
index 540a119..5e382ab 100644
--- a/arch/arm/config.mk
+++ b/arch/arm/config.mk
@@ -98,3 +98,5
Hi @Samsung,
Great that you have starting posting 5420 patches, one basic question
(a) What is the booting procedure for the secondary cores
(b) What is the booting procedure for the Little Secondary cores...
Would you be pushing the patches for these as well
On 9/19/13, Simon Glass
On Thu, Sep 19, 2013 at 11:46 AM, Simon Glass s...@chromium.org wrote:
Hi,
On Sun, Sep 15, 2013 at 12:15 PM, Jagannadha Sutradharudu Teki
jagannadha.sutradharudu-t...@xilinx.com wrote:
Added new spi_flash_probe support, currently added N25Q*
flash part attributes support.
Updated the
Hi Albert.
Yes. BTW, you do not need to double patches with explanatory mails.
Any explanations that you want to add but not be put in the commit,
just put them below the commit message delimiter, the --- line.
You are right. This thread was redundant.
Going forward I will do that. Thanks!
Commit 27af930e9a5c91365ca639ada580b338eabe4989 changed the boards.cfg format
but missed to change the parsing in buildman.
This patch changes c'tor of Board class to the new sequence, but omits
maintainer field.
Signed-off-by: Andreas Bießmann andreas.de...@googlemail.com
---
This patchset add support for a new Samsung board Trats2.
Multi i2c file is updated for third soft I2C adapter for Trats2 board
Battery support is added for Trats2.
This patchset depends on:
http://patchwork.ozlabs.org/patch/245307/
Changes in v5:
- updated Maintainer entry
- removed direct
Signed-off-by: Piotr Wilczek p.wilc...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
---
Changes in v5: none
Changes in v4: none
Changes in v3: none
Changes in v2: none
drivers/power/battery/Makefile |1 +
drivers/power/battery/bat_trats2.c | 65
Signed-off-by: Piotr Wilczek p.wilc...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
CC: Lukasz Majewski l.majew...@samsung.com
---
Changes in v5: updated for new i2c framework
Changes in v4: none
Changes in v3: none
Changes in v2: none
board/samsung/common/multi_i2c.c |
This patch add support for a new Samsung board Trats2.
Signed-off-by: Piotr Wilczek p.wilc...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
CC: Minkyu Kang mk7.k...@samsung.com
---
Changes in v5:
- updated Maintainer entry
- removed direct access to registers
- in
Dear e...@bus-elektronik.de,
e...@bus-elektronik.de e...@bus-elektronik.de writes:
From: Jens Scharsig (BuS Elektronik) e...@bus-elektronik.de
Since UBIFS is enabled for cpux9k2, more malloc space is needed.
For the current uboot 2013.10-rcX the size is to small, this will fix the
startup
Dear Albert Aribaud,
please pull the following fix into u-boot-arm/master for 2013.10 release.
The following changes since commit 771f74c3d31a265bae103b2b407286ec03a4589b:
arm: dma_alloc_coherent: malloc() - memalign() (2013-09-14 12:08:00 +0200)
are available in the git repository at:
Hi Rajesh, Simon,
On Sep 19, 2013, at 9:12 AM, Simon Glass wrote:
Hi Rajeshwari,
On Wed, Sep 11, 2013 at 4:01 AM, Rajeshwari S Shinde
rajeshwar...@samsung.com wrote:
SMDK5420 has a new Security Management Unit added
for dwmmc driver, hence, configuring the control
registers to support
Hi Masahiro,
On Mon, 19 Aug 2013 15:01:21 +0900, Masahiro Yamada
yamad...@jp.panasonic.com wrote:
Commit 5dc5f36 removed the support for B2 board,
which was the last S3C44B0 SoC board.
These series of patches remove s3c44b0-specific
code and drivers:
- arch/arm/cpu/s3c44b0/*
-
Hi Nobuhiro,
On Thu, 22 Aug 2013 13:23:28 +0900, Nobuhiro Iwamatsu
nobuhiro.iwamatsu...@renesas.com wrote:
diff --git a/arch/arm/include/asm/mach-types.h
b/arch/arm/include/asm/mach-types.h
index 440b041..67b88ad 100644
--- a/arch/arm/include/asm/mach-types.h
+++
Hi Nobuhiro,
On Thu, 22 Aug 2013 13:05:49 +0900, Nobuhiro Iwamatsu
nobuhiro.iwamatsu...@renesas.com wrote:
Signed-off-by: Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com
---
include/configs/kzm9g.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/configs/kzm9g.h
On 09/18/2013 06:28 PM, Michael Burr wrote:
This amends my previous patch (of Sept. 17, 2013, 5:29 p.m):
Initialize both bus masters as needed in 'i2c_init'.
The behavior of this code should be unchanged from the
old version if CONFIG_I2C_MULTI_BUS is not defined.
According to Heiko, this
Hi Eric,
On Wed, Sep 18, 2013 at 10:48 AM, Eric Nelson
eric.nel...@boundarydevices.com wrote:
As you know, we're loading the kernel using a boot script,
with various flavors for differing locations and environments,
so we've found it easier to pass environment variables for
board and CPU
Hi!
Adding Freeze Controller driver. All HPS IOs need to be
in freeze state during pin mux or IO buffer configuration.
It is to avoid any glitch which might happen
during the configuration from propagating to external devices.
Thanks for the patch.
(What version is it against? Aha, it
Humm, you are right, Bash expands this.
Anyway, I'll remove the {env,} (along with Simon's suggestions) once
there is no such dumpenvimage tool. My mistake.
Kind regards,
2013/9/18 Otavio Salvador ota...@ossystems.com.br:
On Tue, Sep 17, 2013 at 9:42 PM, guilherme.maciel.ferre...@gmail.com
Hi Masahiro,
On Wed, 18 Sep 2013 13:00:18 +0900, Masahiro Yamada
yamad...@jp.panasonic.com wrote:
Hello Albert.
Commit 27af930e modified top Makefile as follows:
--- a/Makefile
+++ b/Makefile
@@ -838,7 +838,7 @@ unconfig:
sinclude $(obj).boards.depend
On 09/17/2013 10:01 PM, Masahiro Yamada wrote:
In commit 27af930, the top Makefile was adjusted to the new
boards.cfg format.
But at the same time, -d option was added.
If you configure and make separately, for example
like follows:
make omap4_panda_config
make
On Mon, Sep 2, 2013 at 1:52 PM, Enric Balletbo Serra
eballe...@gmail.com wrote:
2013/9/2 Javier Martinez Canillas jav...@dowhile0.org:
There seems to be a naming convention for the configuration
files for boards using the same SoC family. This makes
easier to do changes that affect different
Dear Mateusz Zalega,
This commit unifies board-specific USB initialization implementations
under one symbol (usb_board_init), declaration of which is available in
usb.h.
New API allows selective initialization of USB controllers whenever needed.
Signed-off-by: Mateusz Zalega
Dear Marek Vasut,
Dear Mateusz Zalega,
This commit unifies board-specific USB initialization implementations
under one symbol (usb_board_init), declaration of which is available in
usb.h.
New API allows selective initialization of USB controllers whenever
needed.
On 09/19/2013 08:00 AM, Nishanth Menon wrote:
On 09/17/2013 10:01 PM, Masahiro Yamada wrote:
In commit 27af930, the top Makefile was adjusted to the new
boards.cfg format.
But at the same time, -d option was added.
If you configure and make separately, for example
like follows:
make
Hi Masahiro,
On Thu, 19 Sep 2013 14:49:52 +0200, Albert ARIBAUD
albert.u.b...@aribaud.net wrote:
Can you repost according to the patch posting guidelines at
My bad--you had posted correctly. :)
Amicalement,
--
Albert.
___
U-Boot mailing list
Hi Fabio,
On 09/19/2013 04:57 AM, Fabio Estevam wrote:
Hi Eric,
On Wed, Sep 18, 2013 at 10:48 AM, Eric Nelson
eric.nel...@boundarydevices.com wrote:
As you know, we're loading the kernel using a boot script,
with various flavors for differing locations and environments,
so we've found it
Signed-off-by: Pierre Aubert p.aub...@staubli.com
CC: Stefano Babic sba...@denx.de
---
arch/arm/cpu/armv7/mx6/clock.c | 75 --
arch/arm/include/asm/arch-mx6/crm_regs.h | 11
2 files changed, 61 insertions(+), 25 deletions(-)
diff --git
Dear Marek Vasut,
Dear Marek Vasut,
Dear Mateusz Zalega,
This commit unifies board-specific USB initialization implementations
under one symbol (usb_board_init), declaration of which is available in
usb.h.
New API allows selective initialization of USB controllers whenever
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On 09/15/2013 06:58 PM, Otavio Salvador wrote:
On Sun, Sep 15, 2013 at 1:50 PM, Fabio Estevam feste...@gmail.com wrote:
Hi Marek,
On Sun, Sep 15, 2013 at 1:45 PM, Marek Vasut ma...@denx.de wrote:
Tom, are you OK with such a hack (invoking the
On 09/19/2013 05:00 PM, Igor Grinberg wrote:
Hi Javier,
On 09/19/2013 04:04 PM, Javier Martinez Canillas wrote:
On Mon, Sep 2, 2013 at 1:52 PM, Enric Balletbo Serra
eballe...@gmail.com wrote:
2013/9/2 Javier Martinez Canillas jav...@dowhile0.org:
There seems to be a naming convention for
Hi Pavel,
On Thu, 2013-09-19 at 14:11 +0200, ZY - pavel wrote:
Hi!
Adding Freeze Controller driver. All HPS IOs need to be
in freeze state during pin mux or IO buffer configuration.
It is to avoid any glitch which might happen
during the configuration from propagating to external
On Thu, Sep 19, 2013 at 5:13 PM, Javier Martinez Canillas
javier.marti...@collabora.co.uk wrote:
On 09/19/2013 05:00 PM, Igor Grinberg wrote:
Hi Javier,
On 09/19/2013 04:04 PM, Javier Martinez Canillas wrote:
On Mon, Sep 2, 2013 at 1:52 PM, Enric Balletbo Serra
eballe...@gmail.com wrote:
Adding Freeze Controller driver. All HPS IOs need to be
in freeze state during pin mux or IO buffer configuration.
It is to avoid any glitch which might happen
during the configuration from propagating to external devices.
Signed-off-by: Chin Liang See cl...@altera.com
Cc: Wolfgang Denk
On 09/19/2013 07:14 AM, Ashish wrote:
On Thursday 19 September 2013 11:50 AM, sun york-R58495 wrote:
On Sep 18, 2013, at 9:54 PM, Ashish wrote:
York,
I am trying to understand how the fields of ORx registers are
filled. I am using MPC8641-HPCN board for evaluation purpose. In this
i am
Hi Javier,
On 09/19/2013 04:04 PM, Javier Martinez Canillas wrote:
On Mon, Sep 2, 2013 at 1:52 PM, Enric Balletbo Serra
eballe...@gmail.com wrote:
2013/9/2 Javier Martinez Canillas jav...@dowhile0.org:
There seems to be a naming convention for the configuration
files for boards using the
Hi Simon,
Thank you for comments.
Will add a check so that it will be executed only for Exynos5420 boards.
Thanks and Regards,
Rajeshwari.
On Thu, Sep 19, 2013 at 11:42 AM, Simon Glass s...@chromium.org wrote:
Hi Rajeshwari,
On Wed, Sep 11, 2013 at 4:01 AM, Rajeshwari S Shinde
Dear Hector Palacios,
On 09/19/2013 06:07 PM, Marek Vasut wrote:
Dear Huang Shijie,
Sorry, I think I got lost in the discussion. I will pull out.
btw Hector, I managed to verify JFFS2 mounting doesn't work on 3.10 , now
I'm trying to backport patches from -next and apply the GPMI
Dear Huang Shijie,
Sorry, I think I got lost in the discussion. I will pull out.
btw Hector, I managed to verify JFFS2 mounting doesn't work on 3.10 , now I'm
trying to backport patches from -next and apply the GPMI NAND patchset, without
much luck yet.
Best regards,
Marek Vasut
Hi Andre,
There is another approach taken in xen. (xen/arch/arm/mode_switch.S)
Which do you think is the better approach
Regards
-mj
On 9/19/13, Andre Przywara andre.przyw...@linaro.org wrote:
While actually switching to non-secure state is one thing, another
part of this process is to make
(for GIT URL and Changelog see below)
ARM CPUs with the virtualization extension have a new mode called
HYP mode, which allows hypervisors to safely control and monitor
guests. The current hypervisor implementations (KVM and Xen)
require the kernel to be entered in that HYP mode.
This patch
Hi Rajeshwari,
On Thu, Sep 19, 2013 at 9:42 AM, Rajeshwari Birje
rajeshwari.bi...@gmail.com wrote:
Hi Simon,
Thank you for comments.
Will add a check so that it will be executed only for Exynos5420 boards.
Also, I don't think an #ifdef for an SOC is permitted in driver code. Are
these
A prerequisite for using virtualization is to be in HYP mode, which
requires the CPU to be in non-secure state first.
Add a new file in arch/arm/cpu/armv7 to hold a monitor handler routine
which switches the CPU to non-secure state by setting the NS and
associated bits.
According to the ARM
To actually trigger the non-secure switch we just implemented, call
the switching routine from within the bootm command implementation.
This way we automatically enable this feature without further user
intervention.
Signed-off-by: Andre Przywara andre.przyw...@linaro.org
---
The core specific part of the work is done in the assembly routine
in nonsec_virt.S, introduced with the previous patch, but for the full
glory we need to setup the GIC distributor interface once for the
whole system, which is done in C here.
The routine is placed in arch/arm/cpu/armv7 to allow
Dear Marek Vasut,
On 09/19/2013 06:07 PM, Marek Vasut wrote:
btw Hector, I managed to verify JFFS2 mounting doesn't work on 3.10 , now I'm
trying to backport patches from -next and apply the GPMI NAND patchset, without
much luck yet.
If it helps, to make it work on v3.10 I had to apply lots
While actually switching to non-secure state is one thing, another
part of this process is to make sure that we still have full access
to the interrupt controller (GIC).
The GIC is fully aware of secure vs. non-secure state, some
registers are banked, others may be configured to be accessible from
To enable hypervisors utilizing the ARMv7 virtualization extension
on the Versatile Express board with the A15 core tile, we add the
required configuration variable.
Also we define the board specific smp_set_cpu_boot_addr() function to
set the start address for secondary cores in the VExpress
armv7.h contains some useful constants, but also C prototypes.
To include it also in assembly files, protect the non-assembly
part appropriately.
Signed-off-by: Andre Przywara andre.przyw...@linaro.org
---
arch/arm/include/asm/armv7.h | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
On 09/19/2013 06:07 PM, Marek Vasut wrote:
Dear Huang Shijie,
Sorry, I think I got lost in the discussion. I will pull out.
btw Hector, I managed to verify JFFS2 mounting doesn't work on 3.10 , now I'm
trying to backport patches from -next and apply the GPMI NAND patchset, without
much luck
For the KVM and XEN hypervisors to be usable, we need to enter the
kernel in HYP mode. Now that we already are in non-secure state,
HYP mode switching is within short reach.
While doing the non-secure switch, we have to enable the HVC
instruction and setup the HYP mode HVBAR (while still secure).
Currently the non-secure switch is only done for the boot processor.
To enable full SMP support, we have to switch all secondary cores
into non-secure state also.
So we add an entry point for secondary CPUs coming out of low-power
state and make sure we put them into WFI again after having
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On 09/19/2013 02:39 AM, Albert ARIBAUD wrote:
Hi Masahiro,
On Wed, 18 Sep 2013 13:00:18 +0900, Masahiro Yamada
yamad...@jp.panasonic.com wrote:
Hello Albert.
Commit 27af930e modified top Makefile as follows:
--- a/Makefile
+++
Signed-off-by: Pierre Aubert p.aub...@staubli.com
CC: Stefano Babic sba...@denx.de
---
Change for V2: Use the right macros for computing PFD dividers.
arch/arm/cpu/armv7/mx6/clock.c | 56 ++---
arch/arm/include/asm/arch-mx6/crm_regs.h | 11 --
2 files
Hi Jagan,
On Thu, Sep 19, 2013 at 1:06 AM, Jagan Teki jagannadh.t...@gmail.comwrote:
On Thu, Sep 19, 2013 at 11:46 AM, Simon Glass s...@chromium.org wrote:
Hi,
On Sun, Sep 15, 2013 at 12:15 PM, Jagannadha Sutradharudu Teki
jagannadha.sutradharudu-t...@xilinx.com wrote:
Added new
Dear Hector Palacios,
On 09/19/2013 06:07 PM, Marek Vasut wrote:
Dear Huang Shijie,
Sorry, I think I got lost in the discussion. I will pull out.
btw Hector, I managed to verify JFFS2 mounting doesn't work on 3.10 , now
I'm trying to backport patches from -next and apply the GPMI
On 09/19/2013 05:10 AM, Masahiro Yamada wrote:
Becuase fdt_check_header function takes (const void *)
type argument, the argument should be passed to it
without being casted to (char *).
Signed-off-by: Masahiro Yamada yamad...@jp.panasonic.com
---
Changes for v2:
- fix commit log (purely
Hello Albert,
On 09/19/2013 08:57 AM, Albert ARIBAUD wrote:
On Sat, 17 Aug 2013 15:55:16 +0200, Jeroen Hofstee
jer...@myspectrum.nl wrote:
On 08/14/2013 08:25 PM, Jeroen Hofstee wrote:
diff --git a/arch/arm/config.mk b/arch/arm/config.mk
index 540a119..5e382ab 100644
--- a/arch/arm/config.mk
-BEGIN PGP SIGNED MESSAGE-
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On 09/16/2013 05:51 AM, Gupta, Pekon wrote:
On Tue, Aug 06, 2013 at 01:45:08PM +0530, Pekon Gupta wrote:
ti814x_evm has on-board socket for using Micron (MT29Fxx) family of
NAND devices to GPMC interface. This patch
- adds NAND related pin-mux
Signed-off-by: Philippe Reynes trem...@yahoo.fr
---
include/configs/apf27.h | 11 ++-
include/configs/flea3.h |9 -
include/configs/imx31_phycore.h |7 +++
include/configs/m53evk.h |7 +++
include/configs/mx25pdk.h |
This serie is composed of three patches:
- one to fix the i2c init on the generic board
- one to port the i2c mxc driver to new subsystem
- one to update all configurations with i2c mxc driver
This serie was tested with success on armadeus apf27.
Difference between v3 and v2:
- change title of
Signed-off-by: Philippe Reynes trem...@yahoo.fr
---
README | 11 +++
arch/arm/cpu/armv7/mx5/clock.c |2 +-
arch/arm/cpu/armv7/mx6/clock.c |2 +-
arch/arm/imx-common/Makefile |2 +-
drivers/i2c/Makefile |2 +-
drivers/i2c/mxc_i2c.c |
Signed-off-by: Philippe Reynes trem...@yahoo.fr
---
common/board_f.c |4
1 files changed, 4 insertions(+), 0 deletions(-)
diff --git a/common/board_f.c b/common/board_f.c
index 0ada1af..f0664bc 100644
--- a/common/board_f.c
+++ b/common/board_f.c
@@ -249,7 +249,11 @@ void
On Thu, Sep 19, 2013 at 10:00:03PM +0530, Mj Embd wrote:
Hi Andre,
There is another approach taken in xen. (xen/arch/arm/mode_switch.S)
Which do you think is the better approach
Hi there,
I'm not sure I completely understand your question. Do you think this
patch series should be changed
On Mon, Sep 09, 2013 at 05:41:46PM +0200, Wolfgang Denk wrote:
Dear Rob,
In message 522de2ff.2080...@gmail.com you wrote:
What do I do with current boards that are wrong? I should make all these
Good question...
boards have build errors or fix them to use 1000 which may break them
two quick points
(a) xen already has a mode_switch code, so AFAIK xen might not use it
(as suggested by comment in another patch in this patch set)
(b) There are 2 methods of switching from Secure to Hyp mode
one you have proposed another implemented in xen. I was suggesting
take the best approach
Hello Christoffer,
I agree with both of you points.
What I found different in 2 approaches is that in your approach
S-Monitor-NS-Hyp using svc and hvc
While the other approach is setting the M bits directly in cpsr
Xen uses the following
cpsid aif, #0x16 /* Enter Monitor Mode*/
...
mrs
On Fri, Sep 20, 2013 at 01:27:48AM +0530, Mj Embd wrote:
two quick points
(a) xen already has a mode_switch code, so AFAIK xen might not use it
(as suggested by comment in another patch in this patch set)
For KVM the boot procedure for Hyp mode is quite clearly defined: the
kernel must be
All,
We have a design that has NAND as a secondary device (not the boot
device). The last four pages of the NAND flash are reported as bad.
Should this be true for all NAND flash devices we have?
Thanks,
Andy
___
U-Boot mailing list
On 09/19/2013 04:04 PM, ANDY KENNEDY wrote:
All,
We have a design that has NAND as a secondary device (not the boot
device). The last four pages of the NAND flash are reported as bad.
Should this be true for all NAND flash devices we have?
No, I wouldn't think so. Manufacturers qualify
On 09/19/2013 09:57 PM, Mj Embd wrote:
two quick points
(a) xen already has a mode_switch code, so AFAIK xen might not use it
(as suggested by comment in another patch in this patch set)
Just a few days ago Ian sent out patches to remove this code from Xen.
That code was never meant to
On 09/19/2013 01:57 PM, Tom Rini wrote:
On Tue, Sep 17, 2013 at 08:59:24AM -0700, York Sun wrote:
Albert,
Pardon me if this is a dumb question. I have been working on powerpc
platforms in the past. Now we (the developers I work with) are exploring
ARM cores. I am searching how memory is
On Fri, 2013-09-20 at 01:27 +0530, Mj Embd wrote:
two quick points
(a) xen already has a mode_switch code, so AFAIK xen might not use it
(as suggested by comment in another patch in this patch set)
Xen absolutely wants to use this code. The stuff in Xen was there as a
hack when this stuff
On Thu, 2013-09-19 at 21:11 +0100, Christoffer Dall wrote:
On Fri, Sep 20, 2013 at 01:27:48AM +0530, Mj Embd wrote:
two quick points
(a) xen already has a mode_switch code, so AFAIK xen might not use it
(as suggested by comment in another patch in this patch set)
For KVM the boot
On Sat, Aug 24, 2013 at 01:55:38PM +0200, Jeroen Hofstee wrote:
The movt/movw instruction can be used to hardcode an
memory location in the instruction itself. The linker
starts complaining about this if the compiler decides
to do so: relocation R_ARM_MOVW_ABS_NC against `a local
symbol' can
On 09/19/2013 10:38 PM, Mj Embd wrote:
Hello Christoffer,
I agree with both of you points.
What I found different in 2 approaches is that in your approach
S-Monitor-NS-Hyp using svc and hvc
While the other approach is setting the M bits directly in cpsr
Xen uses the following
cpsid aif,
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On 09/19/2013 05:08 PM, York Sun wrote:
On 09/19/2013 01:57 PM, Tom Rini wrote:
On Tue, Sep 17, 2013 at 08:59:24AM -0700, York Sun wrote:
Albert,
Pardon me if this is a dumb question. I have been working on
powerpc platforms in the past. Now
On Fri, Sep 20, 2013 at 3:01 AM, Andre Przywara
andre.przyw...@linaro.orgwrote:
On 09/19/2013 10:38 PM, Mj Embd wrote:
Hello Christoffer,
I agree with both of you points.
What I found different in 2 approaches is that in your approach
S-Monitor-NS-Hyp using svc and hvc
While the other
Dear York Sun,
In message 523b67d2.2050...@freescale.com you wrote:
So for ARM platforms, the majority don't have the flexibility of using
different DIMMs and/or clocks?
The majority of ARM systems are embedded designs which never use any
kind of DIMM, but raw soldered-on RAM chips.
Does it
On Thu, Sep 19, 2013 at 2:06 PM, Tom Rini tr...@ti.com wrote:
On Mon, Sep 09, 2013 at 05:41:46PM +0200, Wolfgang Denk wrote:
Dear Rob,
In message 522de2ff.2080...@gmail.com you wrote:
What do I do with current boards that are wrong? I should make all these
Good question...
boards have
On 09/19/2013 02:39 PM, Wolfgang Denk wrote:
Dear York Sun,
In message 523b67d2.2050...@freescale.com you wrote:
So for ARM platforms, the majority don't have the flexibility of using
different DIMMs and/or clocks?
The majority of ARM systems are embedded designs which never use any
Dear Julius Werner,
Why 8 * 1000? It's not clear.
I am not quite sure to be honest... it's been a while since I actually
wrote this patch. The EHCI spec gives no clear max for the
Periodic/Async Schedule disable (I assume not more than a frame,
though), and says the Run/Stop bit must halt
Just checking, is the mcr p15,0,r1,c1,c1,0 in sync with the following text
. I could be wrong here, just checking
B1.5.1 Arm Arch Ref Manual
-
To avoid security holes, software must not:
-
— Change from Secure to Non-secure state by using an MSR or CPS
instruction
to
On 09/19/2013 02:33 PM, Tom Rini wrote:
On 09/19/2013 05:08 PM, York Sun wrote:
On 09/19/2013 01:57 PM, Tom Rini wrote:
On Tue, Sep 17, 2013 at 08:59:24AM -0700, York Sun wrote:
Albert,
Pardon me if this is a dumb question. I have been working on
powerpc platforms in the past. Now we (the
On Tue, Sep 17, 2013 at 08:59:24AM -0700, York Sun wrote:
Albert,
Pardon me if this is a dumb question. I have been working on powerpc
platforms in the past. Now we (the developers I work with) are exploring
ARM cores. I am searching how memory is initialized and found different
solutions.
Hello Andre,
I need a bit clarification here, if you read the next line after the line
you have quoted. It clearly says that you can use a MCR to change from
Secure to NS in Monitor Mode
Use an MCR instruction that writes SCR.NS to change from Secure to
Non-secure state. This means ARM recommends
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On 09/19/2013 05:02 PM, Rob Herring wrote:
On Thu, Sep 19, 2013 at 2:06 PM, Tom Rini tr...@ti.com wrote:
On Mon, Sep 09, 2013 at 05:41:46PM +0200, Wolfgang Denk wrote:
Dear Rob,
In message 522de2ff.2080...@gmail.com you wrote:
What do I do with
Hi MJ,
On Thu, Sep 19, 2013 at 12:59 AM, MJ embd mj.e...@gmail.com wrote:
Hi @Samsung,
Great that you have starting posting 5420 patches, one basic question
(a) What is the booting procedure for the secondary cores
(b) What is the booting procedure for the Little Secondary cores...
Would
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