Re: [U-Boot] iMX6 PCie inbound traffic not working
Krunal Desai wrote: Can you get a dump of config space for the 82574? What are its BARs? = pci display 1.0.0 0 40 : 10d38086 0016 0200 0010 0010: 0110 01010001 0112 0020: 8086 0030: 00c8 0100 0040: 0050: 0060: 0070: 0080: 0090: 00a0: 0011 0003 2003 00b0: 00c0: c822d001 0f002000 00d0: 0080e005 00e0: 0001a010 8cc1 00112810 04031c11 00f0: 1011 Dave ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2] spi: soft_spi: Support NULL din/dout buffers
This mirrors the conventions used in other SPI drivers (kirkwood,
davinci, atmel, et al) where the din/dout buffer can be NULL when the
received/transmitted data isn't important. This reduces the need for
allocating additional buffers when write-only/read-only functionality is
needed.
In the din == NULL case, the received data is simply not stored. In the
dout == NULL case, zeroes are transmitted.
Signed-off-by: Andrew Ruder andrew.ru...@elecsyscorp.com
Cc: Jean-Christophe PLAGNIOL-VILLARD plagn...@jcrosoft.com
Cc: Jagan Teki jagannadh.t...@gmail.com
---
Cleaned up errors/warnings from checkpatch.pl. I'm surprised they were flagged
by the script since the actual ERRORs were all on lines I didn't change but were
only included in the context.
scripts/checkpatch.pl 0001-spi-soft_spi-Support-NULL-din-dout-buffers.patch
total: 0 errors, 0 warnings, 0 checks, 31 lines checked
drivers/spi/soft_spi.c | 18 --
1 file changed, 12 insertions(+), 6 deletions(-)
diff --git a/drivers/spi/soft_spi.c b/drivers/spi/soft_spi.c
index 5d22351..c969be3 100644
--- a/drivers/spi/soft_spi.c
+++ b/drivers/spi/soft_spi.c
@@ -136,10 +136,14 @@ int spi_xfer(struct spi_slave *slave, unsigned int
bitlen,
/*
* Check if it is time to work on a new byte.
*/
- if((j % 8) == 0) {
- tmpdout = *txd++;
+ if ((j % 8) == 0) {
+ if (txd)
+ tmpdout = *txd++;
+ else
+ tmpdout = 0;
if(j != 0) {
- *rxd++ = tmpdin;
+ if (rxd)
+ *rxd++ = tmpdin;
}
tmpdin = 0;
}
@@ -164,9 +168,11 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
* bits over to left-justify them. Then store the last byte
* read in.
*/
- if((bitlen % 8) != 0)
- tmpdin = 8 - (bitlen % 8);
- *rxd++ = tmpdin;
+ if (rxd) {
+ if ((bitlen % 8) != 0)
+ tmpdin = 8 - (bitlen % 8);
+ *rxd++ = tmpdin;
+ }
if (flags SPI_XFER_END)
spi_cs_deactivate(slave);
--
1.9.0.rc3.12.gbc97e2d
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Re: [U-Boot] iMX6 PCie inbound traffic not working
From: u-boot-boun...@lists.denx.de [mailto:u-boot-boun...@lists.denx.de] On Behalf Of David Müller (ELSOFT AG) Sent: Thursday, April 24, 2014 07:59 To: u-boot@lists.denx.de Subject: [U-Boot] iMX6 PCie inbound traffic not working I tried to use a Intel 82574 based miniPCIe NIC on a Freescale iMX6 eval board as shown below. It seems that the NIC is unable to read and/or write the descriptors in system memory. The settings of the PCIe core registers seems to be OK (according to the iMX6 RM). Any idea what i am missing? Can you get a dump of config space for the 82574? What are its BARs? Krunal (mobile) ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] am33xx : bit-flip correction in oob
Hi Pekon,
On Thu, Apr 24, 2014 at 1:53 PM, Gupta, Pekon pe...@ti.com wrote:
Hi Marek,
From: Belisko Marek [mailto:marek.beli...@gmail.com]
On Wed, Apr 23, 2014 at 8:04 PM, Gupta, Pekon pe...@ti.com wrote:
From: Belisko Marek [mailto:marek.beli...@gmail.com]
CC-ing Pekon Gupta which add those changes in commit:
6e562b1106ea6afc78752f50925e87e9dd14f8b4
On Tue, Apr 15, 2014 at 12:47 PM, Belisko Marek marek.beli...@gmail.com
wrote:
Hi,
we're running 2014.04-rc3 on custom am335x board (same configuration as
BBB).
When spl is loading u-boot from nand flash we can see a lot of
messages in console:
nand: bit-flip corrected @oob=0
It is always the same position (seems to be first byte in oob).
Anybody experienced same problem?
I've tested on 2 different flashes and result is same.
I was able to track down that read ecc from gpmc return always first
byte as 0xFF (in omap_calculate_ecc())
This shouldn't be the case if the page is programmed.
Following is the expected ECC layout of BCH8
Thanks for reply and sorry for wrong explanation. I mean read_ecc[0]
byte = 0xff.
What I found also is that data in read_ecc was completely different
from displayed when issue nand dump.
I found patch which fixes issue [1]. The u-boot doesn't anymore print
bit-flips in oob. I need to fix
also spl nand_read_page as when loading u-boot from nand in spl still
report issues.
One more question. Shouldn;t code for bitflip in oob looks like this:
--- a/drivers/mtd/nand/omap_gpmc.c
+++ b/drivers/mtd/nand/omap_gpmc.c
@@ -403,7 +403,7 @@ static int omap_correct_data_bch(struct mtd_info
*mtd, uint8_t *dat,
dat[byte_pos] ^= 1 bit_pos;
printf(nand: bit-flip corrected @data=%d\n,
byte_pos);
} else if (byte_pos error_max) {
- read_ecc[byte_pos - SECTOR_BYTES] = 1 bit_pos;
+ read_ecc[byte_pos - SECTOR_BYTES] ^= 1 bit_pos;
debug(nand: bit-flip corrected @oob=%d\n, byte_pos -
SECTOR_BYTES);
} else {
Yes absolutely. Please send a patch for this.
I think this got missed because read_ecc[] does not reach application layer.
Above layers are only interested in data portion, so even if the read_ecc[]
is uncorrected it doesn't matter to them. But yes this should be fixed.
Thanks for catching this.
OK I'll do.
[1] - http://e2e.ti.com/support/arm/sitara_arm/f/791/t/259699.aspx
Ahh.. Yes, I know of this issue..
The issue is mainly due to a NAND protocol violation in the omap driver
since the Random Data Output command (05h-E0h) expects to see only the column
address that should be addressed within the already loaded read page into the
read buffer. Only 2 address cycles with ALE active should be provided between
the 05h and E0h commands. The Page read command expects the full address
footprint (2bytes for column address + 3bytes for row address), but once the
page is loaded into the read buffer, Random Data Output should be used with
only 2bytes for column address.
But the mentioned fix is not at right place. This issue is there in
nand_base.c: nand_command_lp() which is part of generic NAND
framework. So I suggest to use following patch instead.
With original patch (or with your) it fix only u-boot but it doesn't
fix loading u-boot from SPL as it using custom nand_read_page (in
am335x_spl_bch.c)
and not from nand_bases there must be other update to fix this issue.
Probably something like:
--- a/drivers/mtd/nand/am335x_spl_bch.c
+++ b/drivers/mtd/nand/am335x_spl_bch.c
@@ -64,14 +64,16 @@ static int nand_command(int block, int page, uint32_t offs,
NAND_CTRL_ALE | NAND_CTRL_CHANGE); /* A[7:0] */
hwctrl(mtd, (offs 8) 0xff, NAND_CTRL_ALE); /* A[11:9] */
/* Row address */
- hwctrl(mtd, (page_addr 0xff), NAND_CTRL_ALE); /* A[19:12] */
- hwctrl(mtd, ((page_addr 8) 0xff),
- NAND_CTRL_ALE); /* A[27:20] */
-#ifdef CONFIG_SYS_NAND_5_ADDR_CYCLE
- /* One more address cycle for devices 128MiB */
- hwctrl(mtd, (page_addr 16) 0x0f,
- NAND_CTRL_ALE); /* A[31:28] */
-#endif
+ if (cmd != NAND_CMD_RNDOUT) {
+ hwctrl(mtd, (page_addr 0xff), NAND_CTRL_ALE); /* A[19:12] */
+ hwctrl(mtd, ((page_addr 8) 0xff), NAND_CTRL_ALE); /* A[27:20] */
+
+ #ifdef CONFIG_SYS_NAND_5_ADDR_CYCLE
+ /* One more address cycle for devices 128MiB */
+ hwctrl(mtd, (page_addr 16) 0x0f, NAND_CTRL_ALE); /* A[31:28] */
+ #endif
+ }
+
hwctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
--
diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c
index 5d3232c..80256b5 100644
--- a/drivers/mtd/nand/nand_base.c
+++ b/drivers/mtd/nand/nand_base.c
@@ -674,7 +674,7 @@ static void nand_command_lp(struct mtd_info *mtd,
unsigned int command,
ctrl = ~NAND_CTRL_CHANGE;
chip-cmd_ctrl(mtd, column 8, ctrl);
}
-
Re: [U-Boot] am33xx : bit-flip correction in oob
Hi Marek,
From: Belisko Marek [mailto:marek.beli...@gmail.com]
[...]
With original patch (or with your) it fix only u-boot but it doesn't
fix loading u-boot from SPL as it using custom nand_read_page (in
am335x_spl_bch.c)
and not from nand_bases there must be other update to fix this issue.
Probably something like:
--- a/drivers/mtd/nand/am335x_spl_bch.c
+++ b/drivers/mtd/nand/am335x_spl_bch.c
@@ -64,14 +64,16 @@ static int nand_command(int block, int page, uint32_t offs,
NAND_CTRL_ALE | NAND_CTRL_CHANGE); /* A[7:0] */
hwctrl(mtd, (offs 8) 0xff, NAND_CTRL_ALE); /* A[11:9] */
/* Row address */
- hwctrl(mtd, (page_addr 0xff), NAND_CTRL_ALE); /* A[19:12] */
- hwctrl(mtd, ((page_addr 8) 0xff),
- NAND_CTRL_ALE); /* A[27:20] */
-#ifdef CONFIG_SYS_NAND_5_ADDR_CYCLE
- /* One more address cycle for devices 128MiB */
- hwctrl(mtd, (page_addr 16) 0x0f,
- NAND_CTRL_ALE); /* A[31:28] */
-#endif
+ if (cmd != NAND_CMD_RNDOUT) {
+ hwctrl(mtd, (page_addr 0xff), NAND_CTRL_ALE); /* A[19:12] */
+ hwctrl(mtd, ((page_addr 8) 0xff), NAND_CTRL_ALE); /* A[27:20] */
+
+ #ifdef CONFIG_SYS_NAND_5_ADDR_CYCLE
+ /* One more address cycle for devices 128MiB */
+ hwctrl(mtd, (page_addr 16) 0x0f, NAND_CTRL_ALE); /* A[31:28] */
+ #endif
+ }
+
hwctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
Yes, SPL needs to be handled separately in both spl_simple.c and
am335x_spl_bch.c.
Please submit a formal patch for this, so I can test it with multiple devices.
Thanks for fixing this..
with regards, pekon
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Re: [U-Boot] [PATCH 2/3] net/designware: invalidate entire descriptor in dw_eth_send
Hi Ian,
On Thu, 2014-04-24 at 20:14 +0100, Ian Campbell wrote:
On Thu, 2014-04-24 at 17:41 +, Alexey Brodkin wrote:
1. Don't invalidate sizeof(struct dmamacdescr) but only
roundup(sizeof(desc_p-txrx_status), ARCH_DMA_MINALIGN)).
OK. (Although given the realities of the real world values of
ARCH_DMA_MINALIGN on every arch and the sizes of the structs fields
involved this isn't actually buying you anything at all)
Well this particular structure is of size sizeof(uint32_t) * 4 = 16
bytes. And I may suppose that cache lines could be shorter than 16 bytes
even though it could be pretty rare situation. So definitely not a big
deal.
But since we're dealing with macros here all mentioned calculations will
be done by pre-processor and execution performance won't be affected.
2. In the following lines implements rounding as well:
Will fix as well.
3. Check carefully if there're other instances of probably unaligned
cache operations.
I thought a bit more about this situation and now I'm not that sure if
we need to align addresses we pass to cache invalidate/flush functions.
Because IMHO drivers shouldn't care about specifics of particular
platform or architecture. Otherwise we'll need to patch each and every
driver only for cache invalidate/flush functions. I looked how these
functions are used in other drivers and see that in most of cases no
additional alignment precautions were implemented. People just pass
start and end addresses.
In its turn platform and architecture provides cache invalidate/flush
functions implement its functionality depending on hardware specifics.
For example on architectures that may only flush/invalidate with
granularity of 1 cache line cache invalidate/flush functions make sure
to start processing from the start of the cache line to which start
address falls and end processing when cache line where end address falls
is processed.
I may assume that there're architectures that automatically understand
from which cache line to start and at which line to stop processing.
But if your architecture requires cache line aligned addresses to be
used for start/end addresses you may look for examples in ARC
(http://git.denx.de/?p=u-boot/u-boot-arc.git;a=blob;f=arch/arc/cpu/arc700/cache.c),,
MIPS
(http://git.denx.de/?p=u-boot/u-boot-arc.git;a=blob;f=arch/mips/cpu/mips32/cpu.c),
SH
(http://git.denx.de/?p=u-boot/u-boot-arc.git;a=blob;f=arch/sh/cpu/sh4/cache.c),
and what's interesting even implementation you use have semi-proper
start/end addresses handling -
http://git.denx.de/?p=u-boot.git;a=blob;f=arch/arm/lib/cache-pl310.c
Here's your invalidation procedure:
/* invalidate memory from start to stop-1 */
void v7_outer_cache_inval_range(u32 start, u32 stop)
{
/* PL310 currently supports only 32 bytes cache line */
u32 pa, line_size = 32;
/*
* If start address is not aligned to cache-line do not
* invalidate the first cache-line
*/
if (start (line_size - 1)) {
printf(ERROR: %s - start address is not aligned - 0x%08x\n,
__func__, start);
/* move to next cache line */
start = (start + line_size - 1) ~(line_size - 1);
}
/*
* If stop address is not aligned to cache-line do not
* invalidate the last cache-line
*/
if (stop (line_size - 1)) {
printf(ERROR: %s - stop address is not aligned - 0x%08x\n,
__func__, stop);
/* align to the beginning of this cache line */
stop = ~(line_size - 1);
}
for (pa = start; pa stop; pa = pa + line_size)
writel(pa, pl310-pl310_inv_line_pa);
pl310_cache_sync();
}
1. I don't understand why start from the next cache line if start
address is not aligned to cache line boundary? I'd say that you want to
invalidate cache line that contains unaligned start address. Otherwise
first bytes won't be invalidated, right?
2. Why do we throw _error_ message. I may understand if you emit
_warning_ message in case of debug build (with DEBUG defined). Well in
current implementation (see 1) it could be error because behavior is
really dangerous. But if you start from correct cache line only warning
in debug mode makes sense (IMHO).
3. Stop/end address in contrast might need to be extended depending on
HW implementation (see above comment).
And here's your flush procedure:
===
void v7_outer_cache_flush_range(u32 start, u32 stop)
{
/* PL310 currently supports only 32 bytes cache line */
u32 pa, line_size = 32;
/*
* Align to the beginning of cache-line - this ensures that
* the first 5 bits are 0 as required by PL310 TRM
*/
start = ~(line_size - 1);
for (pa = start; pa stop; pa = pa + line_size)
writel(pa, pl310-pl310_clean_inv_line_pa);
[U-Boot] [PATCH v2] powerpc/85xx: add T4080 SoC support
The T4080 SoC is a low-power version of the T4160.
T4080 combines 4 dual-threaded Power Architecture e6500
cores with single cluster and two memory complexes.
Signed-off-by: Shengzhou Liu shengzhou@freescale.com
---
v2: add more comments.
arch/powerpc/cpu/mpc85xx/Makefile | 2 ++
arch/powerpc/cpu/mpc85xx/cpu.c| 24
arch/powerpc/cpu/mpc85xx/cpu_init.c | 9 -
arch/powerpc/cpu/mpc85xx/speed.c | 3 ++-
arch/powerpc/cpu/mpc85xx/t4240_serdes.c | 2 +-
arch/powerpc/cpu/mpc8xxx/cpu.c| 1 +
arch/powerpc/include/asm/config_mpc85xx.h | 16 +++-
arch/powerpc/include/asm/fsl_errata.h | 2 ++
arch/powerpc/include/asm/immap_85xx.h | 6 --
arch/powerpc/include/asm/processor.h | 1 +
drivers/net/fm/Makefile | 1 +
11 files changed, 57 insertions(+), 10 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/Makefile
b/arch/powerpc/cpu/mpc85xx/Makefile
index 4094785..ad26b43 100644
--- a/arch/powerpc/cpu/mpc85xx/Makefile
+++ b/arch/powerpc/cpu/mpc85xx/Makefile
@@ -44,6 +44,7 @@ obj-$(CONFIG_PPC_P5020) += p5020_ids.o
obj-$(CONFIG_PPC_P5040) += p5040_ids.o
obj-$(CONFIG_PPC_T4240) += t4240_ids.o
obj-$(CONFIG_PPC_T4160) += t4240_ids.o
+obj-$(CONFIG_PPC_T4080) += t4240_ids.o
obj-$(CONFIG_PPC_B4420) += b4860_ids.o
obj-$(CONFIG_PPC_B4860) += b4860_ids.o
obj-$(CONFIG_PPC_T1040) += t1040_ids.o
@@ -88,6 +89,7 @@ obj-$(CONFIG_PPC_P5020) += p5020_serdes.o
obj-$(CONFIG_PPC_P5040) += p5040_serdes.o
obj-$(CONFIG_PPC_T4240) += t4240_serdes.o
obj-$(CONFIG_PPC_T4160) += t4240_serdes.o
+obj-$(CONFIG_PPC_T4080) += t4240_serdes.o
obj-$(CONFIG_PPC_B4420) += b4860_serdes.o
obj-$(CONFIG_PPC_B4860) += b4860_serdes.o
obj-$(CONFIG_BSC9132) += bsc9132_serdes.o
diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c
index 12e8e10..684d400 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu.c
@@ -77,6 +77,30 @@ int checkcpu (void)
major = SVR_MAJ(svr);
minor = SVR_MIN(svr);
+#if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) defined(CONFIG_E6500)
+ if (SVR_SOC_VER(svr) == SVR_T4080) {
+ ccsr_rcpm_t *rcpm =
+ (void __iomem *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR);
+
+ setbits_be32(gur-devdisr2, FSL_CORENET_DEVDISR2_DTSEC1_6 ||
+FSL_CORENET_DEVDISR2_DTSEC1_9);
+ setbits_be32(gur-devdisr3, FSL_CORENET_DEVDISR3_PCIE3);
+ setbits_be32(gur-devdisr5, FSL_CORENET_DEVDISR5_DDR3);
+
+ /* It needs SW to disable core4~7 as HW design sake on T4080 */
+ for (i = 4; i 8; i++)
+ cpu_disable(i);
+
+ /* request core4~7 into PH20 state, prior to entering PCL10
+* state, all cores in cluster should be placed in PH20 state.
+*/
+ setbits_be32(rcpm-pcph20setr, 0xf0);
+
+ /* put the 2nd cluster into PCL10 state */
+ setbits_be32(rcpm-clpcl10setr, 1 1);
+ }
+#endif
+
if (cpu_numcores() 1) {
#ifndef CONFIG_MP
puts(Unicore software on multiprocessor system!!\n
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c
b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index 36ef232..7e27464 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -462,10 +462,17 @@ __attribute__((weak, alias(__fsl_serdes__init))) void
fsl_serdes_init(void);
int enable_cluster_l2(void)
{
int i = 0;
- u32 cluster;
+ u32 cluster, svr = get_svr();
ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
struct ccsr_cluster_l2 __iomem *l2cache;
+ /* only the L2 of first cluster should be enabled as expected on T4080,
+* but there is no EOC in the first cluster as HW sake, so return here
+* to skip enabling L2 cache of the 2nd cluster.
+*/
+ if (SVR_SOC_VER(svr) == SVR_T4080)
+ return 0;
+
cluster = in_be32(gur-tp_cluster[i].lower);
if (cluster TP_CLUSTER_EOC)
return 0;
diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c
index d516d4e..3236f6a 100644
--- a/arch/powerpc/cpu/mpc85xx/speed.c
+++ b/arch/powerpc/cpu/mpc85xx/speed.c
@@ -123,7 +123,8 @@ void get_sys_info(sys_info_t *sys_info)
* T4240/T4160 Rev1.0. eg. It's 12 in Rev1.0, however, for Rev2.0
* it uses 6.
*/
-#if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160)
+#if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \
+ defined(CONFIG_PPC_T4080)
if (SVR_MAJ(get_svr()) = 2)
mem_pll_rat *= 2;
#endif
diff --git a/arch/powerpc/cpu/mpc85xx/t4240_serdes.c
b/arch/powerpc/cpu/mpc85xx/t4240_serdes.c
index ff55e3c..1f99a0a 100644
--- a/arch/powerpc/cpu/mpc85xx/t4240_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/t4240_serdes.c
@@
[U-Boot] [PATCH] qe: disable qe when qe-ucode fails to be uploaded
when qe-ucode fails to be uploaded, disable qe.
Signed-off-by: Zhao Qiang b45...@freescale.com
---
drivers/qe/qe.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/qe/qe.c b/drivers/qe/qe.c
index b1da75e..c77cc16 100644
--- a/drivers/qe/qe.c
+++ b/drivers/qe/qe.c
@@ -14,6 +14,8 @@
#include asm/immap_qe.h
#include qe.h
+#define MPC85xx_DEVDISR_QE_DISABLE 0x1
+
qe_map_t *qe_immr = NULL;
static qe_snum_t snums[QE_NUM_OF_SNUM];
@@ -317,6 +319,7 @@ int qe_upload_firmware(const struct qe_firmware *firmware)
size_t calc_size = sizeof(struct qe_firmware);
size_t length;
const struct qe_header *hdr;
+ ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
if (!firmware) {
printf(Invalid address\n);
@@ -330,6 +333,7 @@ int qe_upload_firmware(const struct qe_firmware *firmware)
if ((hdr-magic[0] != 'Q') || (hdr-magic[1] != 'E') ||
(hdr-magic[2] != 'F')) {
printf(Not a microcode\n);
+ setbits_be32(gur-devdisr, MPC85xx_DEVDISR_QE_DISABLE);
return -EPERM;
}
--
1.8.5
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[U-Boot] [PATCH] mtd: nand: omap_gpmc: Fix update of read_ecc in oob
We need to flip only one bit not assign.
Signed-off-by: Marek Belisko marek.beli...@gmail.com
---
drivers/mtd/nand/omap_gpmc.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mtd/nand/omap_gpmc.c b/drivers/mtd/nand/omap_gpmc.c
index 881a636..bf99b8e 100644
--- a/drivers/mtd/nand/omap_gpmc.c
+++ b/drivers/mtd/nand/omap_gpmc.c
@@ -403,7 +403,7 @@ static int omap_correct_data_bch(struct mtd_info *mtd,
uint8_t *dat,
dat[byte_pos] ^= 1 bit_pos;
printf(nand: bit-flip corrected @data=%d\n, byte_pos);
} else if (byte_pos error_max) {
- read_ecc[byte_pos - SECTOR_BYTES] = 1 bit_pos;
+ read_ecc[byte_pos - SECTOR_BYTES] ^= 1 bit_pos;
printf(nand: bit-flip corrected @oob=%d\n, byte_pos -
SECTOR_BYTES);
} else {
--
1.7.9.5
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Re: [U-Boot] [PATCH] mtd: nand: omap_gpmc: Fix update of read_ecc in oob
From: Marek Belisko [mailto:marek.beli...@gmail.com]
We need to flip only one bit not assign.
Signed-off-by: Marek Belisko marek.beli...@gmail.com
---
drivers/mtd/nand/omap_gpmc.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mtd/nand/omap_gpmc.c b/drivers/mtd/nand/omap_gpmc.c
index 881a636..bf99b8e 100644
--- a/drivers/mtd/nand/omap_gpmc.c
+++ b/drivers/mtd/nand/omap_gpmc.c
@@ -403,7 +403,7 @@ static int omap_correct_data_bch(struct mtd_info *mtd,
uint8_t *dat,
dat[byte_pos] ^= 1 bit_pos;
printf(nand: bit-flip corrected @data=%d\n, byte_pos);
} else if (byte_pos error_max) {
- read_ecc[byte_pos - SECTOR_BYTES] = 1 bit_pos;
+ read_ecc[byte_pos - SECTOR_BYTES] ^= 1 bit_pos;
printf(nand: bit-flip corrected @oob=%d\n, byte_pos -
SECTOR_BYTES);
} else {
--
1.7.9.5
Thanks for catching this.
Acked-by: Pekon Gupta pe...@ti.com
with regards, pekon
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[U-Boot] [PATCH v4 3/5] samsung: misc: add env default option to lcd menu
From: Inha Song ideal.s...@samsung.com
This change allows reset device environment to default without using u-boot
console, which is useful for system developers.
Signed-off-by: Inha Song ideal.s...@samsung.com
Acked-by: Przemyslaw Marczak p.marc...@samsung.com
Cc: Minkyu Kang mk7.k...@samsung.com
---
Changes v2:
- extend commit message
Changes v3:
- none
Changes v4:
- none
board/samsung/common/misc.c | 3 +++
include/samsung/misc.h | 1 +
2 files changed, 4 insertions(+)
diff --git a/board/samsung/common/misc.c b/board/samsung/common/misc.c
index 2fd104d..65b5c30 100644
--- a/board/samsung/common/misc.c
+++ b/board/samsung/common/misc.c
@@ -122,6 +122,7 @@ mode_name[BOOT_MODE_EXIT + 1][2] = {
{UMS, ums},
{DFU, dfu},
{GPT, gpt},
+ {ENV, env},
{EXIT, },
};
@@ -132,6 +133,7 @@ mode_info[BOOT_MODE_EXIT + 1] = {
mass storage,
firmware update,
restore,
+ default,
and run normal boot
};
@@ -142,6 +144,7 @@ mode_cmd[BOOT_MODE_EXIT + 1] = {
ums 0 mmc 0,
dfu 0 mmc 0,
gpt write mmc 0 $partitions,
+ env default -a; saveenv,
,
};
diff --git a/include/samsung/misc.h b/include/samsung/misc.h
index c3d844b..10653a1 100644
--- a/include/samsung/misc.h
+++ b/include/samsung/misc.h
@@ -16,6 +16,7 @@ enum {
BOOT_MODE_UMS,
BOOT_MODE_DFU,
BOOT_MODE_GPT,
+ BOOT_MODE_ENV,
BOOT_MODE_EXIT,
};
--
1.9.1
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[U-Boot] [PATCH v4 1/5] samsung: misc: allows using environmental macros as args in menu commands
Function cmd_process() runs commands with directly given list of arguments
but it doesn't expand given environmental variables names as macros.
Command gpt as one of arguments expects expanded macro e.g. $partitions
so it needs to be called by function run_command().
Changes:
- extend array mode_name by lower case commands names - used by find_cmd()
- put each command arguments into one string - used by run_command()
- use run_command() instead of cmd_process()
Signed-off-by: Przemyslaw Marczak p.marc...@samsung.com
Cc: Minkyu Kang mk7.k...@samsung.com
---
Changes v2:
- new commit after separate previous commit
Changes v3:
- none
Changes v4:
- none
board/samsung/common/misc.c | 49 -
1 file changed, 22 insertions(+), 27 deletions(-)
diff --git a/board/samsung/common/misc.c b/board/samsung/common/misc.c
index 3ff4289..95d1758 100644
--- a/board/samsung/common/misc.c
+++ b/board/samsung/common/misc.c
@@ -116,12 +116,12 @@ static int check_keys(void)
* 4 BOOT_MODE_EXIT
*/
static char *
-mode_name[BOOT_MODE_EXIT + 1] = {
- DEVICE,
- THOR,
- UMS,
- DFU,
- EXIT
+mode_name[BOOT_MODE_EXIT + 1][2] = {
+ {DEVICE, },
+ {THOR, thor},
+ {UMS, ums},
+ {DFU, dfu},
+ {EXIT, },
};
static char *
@@ -133,15 +133,13 @@ mode_info[BOOT_MODE_EXIT + 1] = {
and run normal boot
};
-#define MODE_CMD_ARGC 4
-
static char *
-mode_cmd[BOOT_MODE_EXIT + 1][MODE_CMD_ARGC] = {
- {, , , },
- {thor, 0, mmc, 0},
- {ums, 0, mmc, 0},
- {dfu, 0, mmc, 0},
- {, , , },
+mode_cmd[BOOT_MODE_EXIT + 1] = {
+ ,
+ thor 0 mmc 0,
+ ums 0 mmc 0,
+ dfu 0 mmc 0,
+ ,
};
static void display_board_info(void)
@@ -182,11 +180,10 @@ static void display_board_info(void)
static int mode_leave_menu(int mode)
{
char *exit_option;
- char *exit_boot = boot;
+ char *exit_reset = reset;
char *exit_back = back;
cmd_tbl_t *cmd;
int cmd_result;
- int cmd_repeatable;
int leave;
lcd_clear();
@@ -200,31 +197,29 @@ static int mode_leave_menu(int mode)
leave = 0;
break;
default:
- cmd = find_cmd(mode_cmd[mode][0]);
+ cmd = find_cmd(mode_name[mode][1]);
if (cmd) {
- printf(Enter: %s %s\n, mode_name[mode],
+ printf(Enter: %s %s\n, mode_name[mode][0],
mode_info[mode]);
- lcd_printf(\n\n\t%s %s\n, mode_name[mode],
+ lcd_printf(\n\n\t%s %s\n, mode_name[mode][0],
mode_info[mode]);
lcd_puts(\n\tDo not turn off device before finish!\n);
- cmd_result = cmd_process(0, MODE_CMD_ARGC,
-*(mode_cmd + mode),
-cmd_repeatable, NULL);
+ cmd_result = run_command(mode_cmd[mode], 0);
if (cmd_result == CMD_RET_SUCCESS) {
printf(Command finished\n);
lcd_clear();
lcd_printf(\n\n\t%s finished\n,
- mode_name[mode]);
+ mode_name[mode][0]);
- exit_option = exit_boot;
+ exit_option = exit_reset;
leave = 1;
} else {
printf(Command error\n);
lcd_clear();
lcd_printf(\n\n\t%s command error\n,
- mode_name[mode]);
+ mode_name[mode][0]);
exit_option = exit_back;
leave = 0;
@@ -264,7 +259,7 @@ static void display_download_menu(int mode)
for (i = 0; i = BOOT_MODE_EXIT; i++)
lcd_printf(\t%s %s - %s\n\n, selection[i],
- mode_name[i],
+ mode_name[i][0],
mode_info[i]);
}
@@ -305,7 +300,7 @@ static void download_menu(void)
if (run) {
if (mode_leave_menu(mode))
- break;
+ run_command(reset, 0);
display_download_menu(mode);
}
--
1.9.1
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[U-Boot] [PATCH v4 5/5] samsung: misc: remove download mode info screen
This change removes LCD menu download mode info screen.
Now key press timeout is checked in function download_menu()
and menu options are displayed directly after PWR + VOLUP keys.
Signed-off-by: Przemyslaw Marczak p.marc...@samsung.com
---
Changes v4:
- new commit
board/samsung/common/misc.c | 73 +++--
1 file changed, 31 insertions(+), 42 deletions(-)
diff --git a/board/samsung/common/misc.c b/board/samsung/common/misc.c
index 5b43821..c0d8866 100644
--- a/board/samsung/common/misc.c
+++ b/board/samsung/common/misc.c
@@ -265,7 +265,7 @@ static void display_download_menu(int mode)
selection[mode] = [=];
lcd_clear();
- lcd_printf(\n\t\tDownload Mode Menu\n);
+ lcd_printf(\n\n\t\tDownload Mode Menu\n\n);
for (i = 0; i = BOOT_MODE_EXIT; i++)
lcd_printf(\t%s %s - %s\n\n, selection[i],
@@ -278,10 +278,38 @@ static void download_menu(void)
int mode = 0;
int last_mode = 0;
int run;
- int key;
+ int key = 0;
+ int timeout = 15; /* sec */
+ int i;
display_download_menu(mode);
+ lcd_puts(\n);
+
+ /* Start count if no key is pressed */
+ while (check_keys())
+ continue;
+
+ while (timeout--) {
+ lcd_printf(\r\tNormal boot will start in: %2.d seconds.,
+ timeout);
+
+ /* about 1000 ms in for loop */
+ for (i = 0; i 10; i++) {
+ mdelay(100);
+ key = check_keys();
+ if (key)
+ break;
+ }
+ if (key)
+ break;
+ }
+
+ if (!key) {
+ lcd_clear();
+ return;
+ }
+
while (1) {
run = 0;
@@ -319,45 +347,6 @@ static void download_menu(void)
lcd_clear();
}
-static void display_mode_info(void)
-{
- lcd_position_cursor(4, 4);
- lcd_printf(%s\n, U_BOOT_VERSION);
- lcd_puts(\nDownload Mode Menu\n);
-#ifdef CONFIG_SYS_BOARD
- lcd_printf(Board name: %s\n, CONFIG_SYS_BOARD);
-#endif
- lcd_printf(Press POWER KEY to display MENU options.);
-}
-
-static int boot_menu(void)
-{
- int key = 0;
- int timeout = 10;
-
- display_mode_info();
-
- while (timeout--) {
- lcd_printf(\rNormal boot will start in: %d seconds., timeout);
- mdelay(1000);
-
- key = key_pressed(KEY_POWER);
- if (key)
- break;
- }
-
- lcd_clear();
-
- /* If PWR pressed - show download menu */
- if (key) {
- printf(Power pressed - go to download menu\n);
- download_menu();
- printf(Download mode exit.\n);
- }
-
- return 0;
-}
-
void check_boot_mode(void)
{
int pwr_key;
@@ -370,7 +359,7 @@ void check_boot_mode(void)
power_key_pressed(KEY_PWR_INTERRUPT_REG);
if (key_pressed(KEY_VOLUMEUP))
- boot_menu();
+ download_menu();
else if (key_pressed(KEY_VOLUMEDOWN))
mode_leave_menu(BOOT_MODE_THOR);
}
--
1.9.1
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[U-Boot] [PATCH v4 4/5] samsung: misc: keys: fix gpio key bouncing by adding 50 ms delay
This change prevents gpio keys bouncing by adding 50 ms delay when key pressed condition met. Signed-off-by: Przemyslaw Marczak p.marc...@samsung.com Cc: Minkyu Kang mk7.k...@samsung.com --- Changes v2: - new commit Changes v3: - correct commit message Changes v4: - none board/samsung/common/misc.c | 4 1 file changed, 4 insertions(+) diff --git a/board/samsung/common/misc.c b/board/samsung/common/misc.c index 65b5c30..5b43821 100644 --- a/board/samsung/common/misc.c +++ b/board/samsung/common/misc.c @@ -105,6 +105,10 @@ static int check_keys(void) if (key_pressed(KEY_VOLUMEDOWN)) keys += KEY_VOLUMEDOWN; + /* Avoids gpio keys debouncing */ + if (keys) + mdelay(50); + return keys; } -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v4 2/5] samsung: misc: add gpt restore option to lcd menu
This menu option allows restore gpt.
This is usefull and no needs access to the u-boot console.
For proper operation:
- each partition uuid should be set in environment or
- CONFIG_RANDOM_UUID should be defined for automatically uuid setting
After operation success device is going to be reset.
Signed-off-by: Przemyslaw Marczak p.marc...@samsung.com
Cc: Minkyu Kang mk7.k...@samsung.com
---
Changes v2:
- commit separation
Changes v3:
- none
Changes v4:
- none
board/samsung/common/misc.c | 3 +++
include/samsung/misc.h | 1 +
2 files changed, 4 insertions(+)
diff --git a/board/samsung/common/misc.c b/board/samsung/common/misc.c
index 95d1758..2fd104d 100644
--- a/board/samsung/common/misc.c
+++ b/board/samsung/common/misc.c
@@ -121,6 +121,7 @@ mode_name[BOOT_MODE_EXIT + 1][2] = {
{THOR, thor},
{UMS, ums},
{DFU, dfu},
+ {GPT, gpt},
{EXIT, },
};
@@ -130,6 +131,7 @@ mode_info[BOOT_MODE_EXIT + 1] = {
downloader,
mass storage,
firmware update,
+ restore,
and run normal boot
};
@@ -139,6 +141,7 @@ mode_cmd[BOOT_MODE_EXIT + 1] = {
thor 0 mmc 0,
ums 0 mmc 0,
dfu 0 mmc 0,
+ gpt write mmc 0 $partitions,
,
};
diff --git a/include/samsung/misc.h b/include/samsung/misc.h
index ede6c15..c3d844b 100644
--- a/include/samsung/misc.h
+++ b/include/samsung/misc.h
@@ -15,6 +15,7 @@ enum {
BOOT_MODE_THOR,
BOOT_MODE_UMS,
BOOT_MODE_DFU,
+ BOOT_MODE_GPT,
BOOT_MODE_EXIT,
};
--
1.9.1
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[U-Boot] [PATCH] arm: fdt_control: fix a build error with CONFIG_OF_EMBED=y
The build fails if a non-generic ARM board is compiled with CONFIG_OF_EMBED=y. The correct symbol name for embedded FDT is not __dtb_db_begin, but __dtb_dt_begin. (A typo introduced by commit 6ab6b2af) Signed-off-by: Masahiro Yamada yamad...@jp.panasonic.com --- arch/arm/lib/board.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/lib/board.c b/arch/arm/lib/board.c index 92e85c4..d5fabe4 100644 --- a/arch/arm/lib/board.c +++ b/arch/arm/lib/board.c @@ -277,7 +277,7 @@ void board_init_f(ulong bootflag) gd-mon_len = (ulong)__bss_end - (ulong)_start; #ifdef CONFIG_OF_EMBED /* Get a pointer to the FDT */ - gd-fdt_blob = __dtb_db_begin; + gd-fdt_blob = __dtb_dt_begin; #elif defined CONFIG_OF_SEPARATE /* FDT is at end of image */ gd-fdt_blob = _end; -- 1.8.3.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] kbuild: allow null board for spl build
Commit 33a02da0 supported none for the board field of boards.cfg. But it missed to modify spl/Makefile. This commit provides the flexibility so we can use none board in SPL too. --- spl/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/spl/Makefile b/spl/Makefile index 6fec252..db685f9 100644 --- a/spl/Makefile +++ b/spl/Makefile @@ -88,7 +88,7 @@ libs-y += $(CPUDIR)/ ifdef SOC libs-y += $(CPUDIR)/$(SOC)/ endif -libs-y += board/$(BOARDDIR)/ +libs-y += $(if $(BOARDDIR),board/$(BOARDDIR)/) libs-$(HAVE_VENDOR_COMMON_LIB) += board/$(VENDOR)/common/ libs-$(CONFIG_SPL_FRAMEWORK) += common/spl/ -- 1.8.3.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/9] fpga: spartan2: Avoid CamelCase
No functional changes.
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
board/esd/pmc440/fpga.c | 2 +-
board/matrix_vision/mvsmr/fpga.c | 2 +-
drivers/fpga/spartan2.c | 40
drivers/fpga/xilinx.c| 14 +++---
include/spartan2.h | 32
include/xilinx.h | 2 +-
6 files changed, 46 insertions(+), 46 deletions(-)
diff --git a/board/esd/pmc440/fpga.c b/board/esd/pmc440/fpga.c
index b7b62dd..cef2050 100644
--- a/board/esd/pmc440/fpga.c
+++ b/board/esd/pmc440/fpga.c
@@ -47,7 +47,7 @@ Xilinx_Spartan3_Slave_Serial_fns pmc440_fpga_fns = {
};
#endif
-Xilinx_Spartan2_Slave_Serial_fns ngcc_fpga_fns = {
+xilinx_spartan2_slave_serial_fns ngcc_fpga_fns = {
ngcc_fpga_pre_config_fn,
ngcc_fpga_pgm_fn,
ngcc_fpga_clk_fn,
diff --git a/board/matrix_vision/mvsmr/fpga.c b/board/matrix_vision/mvsmr/fpga.c
index 88035a9..639bc7c 100644
--- a/board/matrix_vision/mvsmr/fpga.c
+++ b/board/matrix_vision/mvsmr/fpga.c
@@ -27,7 +27,7 @@ Xilinx_Spartan3_Slave_Serial_fns fpga_fns = {
};
Xilinx_desc spartan3 = {
- Xilinx_Spartan2,
+ xilinx_spartan2,
slave_serial,
XILINX_XC3S200_SIZE,
(void *) fpga_fns,
diff --git a/drivers/fpga/spartan2.c b/drivers/fpga/spartan2.c
index 6eab1b5..bd31709 100644
--- a/drivers/fpga/spartan2.c
+++ b/drivers/fpga/spartan2.c
@@ -31,29 +31,29 @@
#define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ/100 /* 10 ms */
#endif
-static int Spartan2_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize);
-static int Spartan2_sp_dump(Xilinx_desc *desc, const void *buf, size_t bsize);
-/* static int Spartan2_sp_info(Xilinx_desc *desc ); */
+static int spartan2_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize);
+static int spartan2_sp_dump(Xilinx_desc *desc, const void *buf, size_t bsize);
+/* static int spartan2_sp_info(Xilinx_desc *desc ); */
-static int Spartan2_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize);
-static int Spartan2_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize);
-/* static int Spartan2_ss_info(Xilinx_desc *desc ); */
+static int spartan2_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize);
+static int spartan2_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize);
+/* static int spartan2_ss_info(Xilinx_desc *desc ); */
/* - */
/* Spartan-II Generic Implementation */
-int Spartan2_load(Xilinx_desc *desc, const void *buf, size_t bsize)
+int spartan2_load(Xilinx_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL;
switch (desc-iface) {
case slave_serial:
PRINTF (%s: Launching Slave Serial Load\n, __FUNCTION__);
- ret_val = Spartan2_ss_load (desc, buf, bsize);
+ ret_val = spartan2_ss_load(desc, buf, bsize);
break;
case slave_parallel:
PRINTF (%s: Launching Slave Parallel Load\n, __FUNCTION__);
- ret_val = Spartan2_sp_load (desc, buf, bsize);
+ ret_val = spartan2_sp_load(desc, buf, bsize);
break;
default:
@@ -64,19 +64,19 @@ int Spartan2_load(Xilinx_desc *desc, const void *buf,
size_t bsize)
return ret_val;
}
-int Spartan2_dump(Xilinx_desc *desc, const void *buf, size_t bsize)
+int spartan2_dump(Xilinx_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL;
switch (desc-iface) {
case slave_serial:
PRINTF (%s: Launching Slave Serial Dump\n, __FUNCTION__);
- ret_val = Spartan2_ss_dump (desc, buf, bsize);
+ ret_val = spartan2_ss_dump(desc, buf, bsize);
break;
case slave_parallel:
PRINTF (%s: Launching Slave Parallel Dump\n, __FUNCTION__);
- ret_val = Spartan2_sp_dump (desc, buf, bsize);
+ ret_val = spartan2_sp_dump(desc, buf, bsize);
break;
default:
@@ -87,7 +87,7 @@ int Spartan2_dump(Xilinx_desc *desc, const void *buf, size_t
bsize)
return ret_val;
}
-int Spartan2_info( Xilinx_desc *desc )
+int spartan2_info(Xilinx_desc *desc)
{
return FPGA_SUCCESS;
}
@@ -96,10 +96,10 @@ int Spartan2_info( Xilinx_desc *desc )
/* - */
/* Spartan-II Slave Parallel Generic Implementation */
-static int Spartan2_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize)
+static int spartan2_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL;/* assume the worst */
- Xilinx_Spartan2_Slave_Parallel_fns *fn = desc-iface_fns;
+ xilinx_spartan2_slave_parallel_fns *fn = desc-iface_fns;
PRINTF (%s: start with interface functions @ 0x%p\n,
__FUNCTION__, fn);
@@ -248,10
[U-Boot] [PATCH 2/9] fpga: spartan3: Avoid CamelCase
No functional changes.
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
board/armadeus/apf27/fpga.c | 4 ++--
board/astro/mcf5373l/fpga.c | 4 ++--
board/balloon3/balloon3.c| 2 +-
board/esd/pmc440/fpga.c | 4 ++--
board/matrix_vision/mvsmr/fpga.c | 2 +-
board/spear/x600/fpga.c | 2 +-
board/teejet/mt_ventoux/mt_ventoux.c | 2 +-
drivers/fpga/spartan3.c | 40 ++--
drivers/fpga/xilinx.c| 14 ++---
include/spartan3.h | 38 +-
include/xilinx.h | 2 +-
11 files changed, 57 insertions(+), 57 deletions(-)
diff --git a/board/armadeus/apf27/fpga.c b/board/armadeus/apf27/fpga.c
index 0c08c06..56fde20 100644
--- a/board/armadeus/apf27/fpga.c
+++ b/board/armadeus/apf27/fpga.c
@@ -26,7 +26,7 @@
* Spartan2 code is used to download our Spartan 3 :) code is compatible.
* Just take care about the file size
*/
-Xilinx_Spartan3_Slave_Parallel_fns fpga_fns = {
+xilinx_spartan3_slave_parallel_fns fpga_fns = {
fpga_pre_fn,
fpga_pgm_fn,
fpga_init_fn,
@@ -43,7 +43,7 @@ Xilinx_Spartan3_Slave_Parallel_fns fpga_fns = {
};
Xilinx_desc fpga[CONFIG_FPGA_COUNT] = {
- {Xilinx_Spartan3,
+ {xilinx_spartan3,
slave_parallel,
1196128l/8,
(void *)fpga_fns,
diff --git a/board/astro/mcf5373l/fpga.c b/board/astro/mcf5373l/fpga.c
index c679ad7..152ff1f 100644
--- a/board/astro/mcf5373l/fpga.c
+++ b/board/astro/mcf5373l/fpga.c
@@ -363,7 +363,7 @@ int xilinx_fastwr_fn(void *buf, size_t len, int flush, int
cookie)
* relocated at runtime.
* FIXME: relocation not yet working for coldfire, see below!
*/
-Xilinx_Spartan3_Slave_Serial_fns xilinx_fns = {
+xilinx_spartan3_slave_serial_fns xilinx_fns = {
xilinx_pre_config_fn,
xilinx_pgm_fn,
xilinx_clk_fn,
@@ -375,7 +375,7 @@ Xilinx_Spartan3_Slave_Serial_fns xilinx_fns = {
};
Xilinx_desc xilinx_fpga[CONFIG_FPGA_COUNT] = {
- {Xilinx_Spartan3,
+ {xilinx_spartan3,
slave_serial,
XILINX_XC3S4000_SIZE,
(void *)xilinx_fns,
diff --git a/board/balloon3/balloon3.c b/board/balloon3/balloon3.c
index 04e0574..4aa6605 100644
--- a/board/balloon3/balloon3.c
+++ b/board/balloon3/balloon3.c
@@ -191,7 +191,7 @@ int fpga_cs_fn(int assert_clk, int flush, int cookie)
return assert_clk;
}
-Xilinx_Spartan3_Slave_Parallel_fns balloon3_fpga_fns = {
+xilinx_spartan3_slave_parallel_fns balloon3_fpga_fns = {
fpga_pre_config_fn,
fpga_pgm_fn,
fpga_init_fn,
diff --git a/board/esd/pmc440/fpga.c b/board/esd/pmc440/fpga.c
index cef2050..18a1b63 100644
--- a/board/esd/pmc440/fpga.c
+++ b/board/esd/pmc440/fpga.c
@@ -20,7 +20,7 @@ DECLARE_GLOBAL_DATA_PTR;
#define USE_SP_CODE
#ifdef USE_SP_CODE
-Xilinx_Spartan3_Slave_Parallel_fns pmc440_fpga_fns = {
+xilinx_spartan3_slave_parallel_fns pmc440_fpga_fns = {
fpga_pre_config_fn,
fpga_pgm_fn,
fpga_init_fn,
@@ -36,7 +36,7 @@ Xilinx_Spartan3_Slave_Parallel_fns pmc440_fpga_fns = {
fpga_post_config_fn,
};
#else
-Xilinx_Spartan3_Slave_Serial_fns pmc440_fpga_fns = {
+xilinx_spartan3_slave_serial_fns pmc440_fpga_fns = {
fpga_pre_config_fn,
fpga_pgm_fn,
fpga_clk_fn,
diff --git a/board/matrix_vision/mvsmr/fpga.c b/board/matrix_vision/mvsmr/fpga.c
index 639bc7c..b207455 100644
--- a/board/matrix_vision/mvsmr/fpga.c
+++ b/board/matrix_vision/mvsmr/fpga.c
@@ -16,7 +16,7 @@
#include fpga.h
#include mvsmr.h
-Xilinx_Spartan3_Slave_Serial_fns fpga_fns = {
+xilinx_spartan3_slave_serial_fns fpga_fns = {
fpga_pre_config_fn,
fpga_pgm_fn,
fpga_clk_fn,
diff --git a/board/spear/x600/fpga.c b/board/spear/x600/fpga.c
index c06c994..c26eba4 100644
--- a/board/spear/x600/fpga.c
+++ b/board/spear/x600/fpga.c
@@ -163,7 +163,7 @@ static int fpga_wr_fn(int assert_write, int flush, int
cookie)
return assert_write;
}
-static Xilinx_Spartan3_Slave_Serial_fns x600_fpga_fns = {
+static xilinx_spartan3_slave_serial_fns x600_fpga_fns = {
fpga_pre_config_fn,
fpga_pgm_fn,
fpga_clk_fn,
diff --git a/board/teejet/mt_ventoux/mt_ventoux.c
b/board/teejet/mt_ventoux/mt_ventoux.c
index c32d554..a361764 100644
--- a/board/teejet/mt_ventoux/mt_ventoux.c
+++ b/board/teejet/mt_ventoux/mt_ventoux.c
@@ -190,7 +190,7 @@ int fpga_clk_fn(int assert_clk, int flush, int cookie)
return assert_clk;
}
-Xilinx_Spartan3_Slave_Serial_fns mt_ventoux_fpga_fns = {
+xilinx_spartan3_slave_serial_fns mt_ventoux_fpga_fns = {
fpga_pre_config_fn,
fpga_pgm_fn,
fpga_clk_fn,
diff --git a/drivers/fpga/spartan3.c b/drivers/fpga/spartan3.c
index 3edc5c2..e40abbf 100644
--- a/drivers/fpga/spartan3.c
+++ b/drivers/fpga/spartan3.c
@@ -35,29 +35,29 @@
#define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ/100 /* 10 ms */
#endif
-static int
[U-Boot] [PATCH 6/9] fpga: xilinx: Simplify load/dump/info function handling
Connect FPGA version with appropriate operations
to remove huge switch-cases for every FPGA family.
Tested on Zynq. Spartan2/Spartan3/Virtex2 just compile test.
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
Based on http://permalink.gmane.org/gmane.comp.boot-loaders.u-boot/182419
I have checked that symbols are available in u-boot.map.
---
drivers/fpga/spartan2.c | 12 +++-
drivers/fpga/spartan3.c | 12 +++-
drivers/fpga/virtex2.c | 12 +++-
drivers/fpga/xilinx.c | 159 +++-
drivers/fpga/zynqpl.c | 13 ++--
include/spartan2.h | 28 -
include/spartan3.h | 36 +--
include/virtex2.h | 28 -
include/xilinx.h| 7 +++
include/zynqpl.h| 16 +++--
10 files changed, 101 insertions(+), 222 deletions(-)
diff --git a/drivers/fpga/spartan2.c b/drivers/fpga/spartan2.c
index 0796729..7054056 100644
--- a/drivers/fpga/spartan2.c
+++ b/drivers/fpga/spartan2.c
@@ -41,7 +41,7 @@ static int spartan2_ss_dump(xilinx_desc *desc, const void
*buf, size_t bsize);
/* - */
/* Spartan-II Generic Implementation */
-int spartan2_load(xilinx_desc *desc, const void *buf, size_t bsize)
+static int spartan2_load(xilinx_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL;
@@ -64,7 +64,7 @@ int spartan2_load(xilinx_desc *desc, const void *buf, size_t
bsize)
return ret_val;
}
-int spartan2_dump(xilinx_desc *desc, const void *buf, size_t bsize)
+static int spartan2_dump(xilinx_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL;
@@ -87,7 +87,7 @@ int spartan2_dump(xilinx_desc *desc, const void *buf, size_t
bsize)
return ret_val;
}
-int spartan2_info(xilinx_desc *desc)
+static int spartan2_info(xilinx_desc *desc)
{
return FPGA_SUCCESS;
}
@@ -447,3 +447,9 @@ static int spartan2_ss_dump(xilinx_desc *desc, const void
*buf, size_t bsize)
__FUNCTION__);
return FPGA_FAIL;
}
+
+struct xilinx_fpga_op spartan2_op = {
+ .load = spartan2_load,
+ .dump = spartan2_dump,
+ .info = spartan2_info,
+};
diff --git a/drivers/fpga/spartan3.c b/drivers/fpga/spartan3.c
index 1304b4c..5c9412c 100644
--- a/drivers/fpga/spartan3.c
+++ b/drivers/fpga/spartan3.c
@@ -45,7 +45,7 @@ static int spartan3_ss_dump(xilinx_desc *desc, const void
*buf, size_t bsize);
/* - */
/* Spartan-II Generic Implementation */
-int spartan3_load(xilinx_desc *desc, const void *buf, size_t bsize)
+static int spartan3_load(xilinx_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL;
@@ -68,7 +68,7 @@ int spartan3_load(xilinx_desc *desc, const void *buf, size_t
bsize)
return ret_val;
}
-int spartan3_dump(xilinx_desc *desc, const void *buf, size_t bsize)
+static int spartan3_dump(xilinx_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL;
@@ -91,7 +91,7 @@ int spartan3_dump(xilinx_desc *desc, const void *buf, size_t
bsize)
return ret_val;
}
-int spartan3_info(xilinx_desc *desc)
+static int spartan3_info(xilinx_desc *desc)
{
return FPGA_SUCCESS;
}
@@ -465,3 +465,9 @@ static int spartan3_ss_dump(xilinx_desc *desc, const void
*buf, size_t bsize)
__FUNCTION__);
return FPGA_FAIL;
}
+
+struct xilinx_fpga_op spartan3_op = {
+ .load = spartan3_load,
+ .dump = spartan3_dump,
+ .info = spartan3_info,
+};
diff --git a/drivers/fpga/virtex2.c b/drivers/fpga/virtex2.c
index a582bf2..e092147 100644
--- a/drivers/fpga/virtex2.c
+++ b/drivers/fpga/virtex2.c
@@ -90,7 +90,7 @@ static int virtex2_ssm_dump(xilinx_desc *desc, const void
*buf, size_t bsize);
static int virtex2_ss_load(xilinx_desc *desc, const void *buf, size_t bsize);
static int virtex2_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize);
-int virtex2_load(xilinx_desc *desc, const void *buf, size_t bsize)
+static int virtex2_load(xilinx_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL;
@@ -112,7 +112,7 @@ int virtex2_load(xilinx_desc *desc, const void *buf, size_t
bsize)
return ret_val;
}
-int virtex2_dump(xilinx_desc *desc, const void *buf, size_t bsize)
+static int virtex2_dump(xilinx_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL;
@@ -134,7 +134,7 @@ int virtex2_dump(xilinx_desc *desc, const void *buf, size_t
bsize)
return ret_val;
}
-int virtex2_info(xilinx_desc *desc)
+static int virtex2_info(xilinx_desc *desc)
{
return FPGA_SUCCESS;
}
@@ -417,3 +417,9 @@ static int virtex2_ss_dump(xilinx_desc *desc, const void
*buf, size_t bsize)
}
/* vim: set ts=4 tw=78: */
+
+struct xilinx_fpga_op virtex2_op = {
+ .load = virtex2_load,
+ .dump = virtex2_dump,
+ .info = virtex2_info,
+};
diff
[U-Boot] [PATCH 3/9] fpga: virtex2: Avoid CamelCase
No functional changes.
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
board/gen860t/fpga.c | 4 ++--
drivers/fpga/virtex2.c | 34 +-
drivers/fpga/xilinx.c | 14 +++---
include/virtex2.h | 34 +-
include/xilinx.h | 2 +-
5 files changed, 44 insertions(+), 44 deletions(-)
diff --git a/board/gen860t/fpga.c b/board/gen860t/fpga.c
index b7984dd..48a4222 100644
--- a/board/gen860t/fpga.c
+++ b/board/gen860t/fpga.c
@@ -40,7 +40,7 @@ DECLARE_GLOBAL_DATA_PTR;
/* Note that these are pointers to code that is in Flash. They will be
* relocated at runtime.
*/
-Xilinx_Virtex2_Slave_SelectMap_fns fpga_fns = {
+xilinx_virtex2_slave_selectmap_fns fpga_fns = {
fpga_pre_config_fn,
fpga_pgm_fn,
fpga_init_fn,
@@ -57,7 +57,7 @@ Xilinx_Virtex2_Slave_SelectMap_fns fpga_fns = {
};
Xilinx_desc fpga[CONFIG_FPGA_COUNT] = {
- {Xilinx_Virtex2,
+ {xilinx_virtex2,
slave_selectmap,
XILINX_XC2V3000_SIZE,
(void *) fpga_fns,
diff --git a/drivers/fpga/virtex2.c b/drivers/fpga/virtex2.c
index b5a895d..1cd9046 100644
--- a/drivers/fpga/virtex2.c
+++ b/drivers/fpga/virtex2.c
@@ -84,25 +84,25 @@
#define CONFIG_SYS_FPGA_WAIT_CONFIGCONFIG_SYS_HZ/5 /* 200 ms */
#endif
-static int Virtex2_ssm_load(Xilinx_desc *desc, const void *buf, size_t bsize);
-static int Virtex2_ssm_dump(Xilinx_desc *desc, const void *buf, size_t bsize);
+static int virtex2_ssm_load(Xilinx_desc *desc, const void *buf, size_t bsize);
+static int virtex2_ssm_dump(Xilinx_desc *desc, const void *buf, size_t bsize);
-static int Virtex2_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize);
-static int Virtex2_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize);
+static int virtex2_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize);
+static int virtex2_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize);
-int Virtex2_load(Xilinx_desc *desc, const void *buf, size_t bsize)
+int virtex2_load(Xilinx_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL;
switch (desc-iface) {
case slave_serial:
PRINTF (%s: Launching Slave Serial Load\n, __FUNCTION__);
- ret_val = Virtex2_ss_load (desc, buf, bsize);
+ ret_val = virtex2_ss_load(desc, buf, bsize);
break;
case slave_selectmap:
PRINTF (%s: Launching Slave Parallel Load\n, __FUNCTION__);
- ret_val = Virtex2_ssm_load (desc, buf, bsize);
+ ret_val = virtex2_ssm_load(desc, buf, bsize);
break;
default:
@@ -112,19 +112,19 @@ int Virtex2_load(Xilinx_desc *desc, const void *buf,
size_t bsize)
return ret_val;
}
-int Virtex2_dump(Xilinx_desc *desc, const void *buf, size_t bsize)
+int virtex2_dump(Xilinx_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL;
switch (desc-iface) {
case slave_serial:
PRINTF (%s: Launching Slave Serial Dump\n, __FUNCTION__);
- ret_val = Virtex2_ss_dump (desc, buf, bsize);
+ ret_val = virtex2_ss_dump(desc, buf, bsize);
break;
case slave_parallel:
PRINTF (%s: Launching Slave Parallel Dump\n, __FUNCTION__);
- ret_val = Virtex2_ssm_dump (desc, buf, bsize);
+ ret_val = virtex2_ssm_dump(desc, buf, bsize);
break;
default:
@@ -134,7 +134,7 @@ int Virtex2_dump(Xilinx_desc *desc, const void *buf, size_t
bsize)
return ret_val;
}
-int Virtex2_info (Xilinx_desc * desc)
+int virtex2_info(Xilinx_desc *desc)
{
return FPGA_SUCCESS;
}
@@ -153,10 +153,10 @@ int Virtex2_info (Xilinx_desc * desc)
*INIT_B and DONE lines. If both are high, configuration has
*succeeded. Congratulations!
*/
-static int Virtex2_ssm_load(Xilinx_desc *desc, const void *buf, size_t bsize)
+static int virtex2_ssm_load(Xilinx_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL;
- Xilinx_Virtex2_Slave_SelectMap_fns *fn = desc-iface_fns;
+ xilinx_virtex2_slave_selectmap_fns *fn = desc-iface_fns;
PRINTF (%s:%d: Start with interface functions @ 0x%p\n,
__FUNCTION__, __LINE__, fn);
@@ -352,10 +352,10 @@ static int Virtex2_ssm_load(Xilinx_desc *desc, const void
*buf, size_t bsize)
/*
* Read the FPGA configuration data
*/
-static int Virtex2_ssm_dump(Xilinx_desc *desc, const void *buf, size_t bsize)
+static int virtex2_ssm_dump(Xilinx_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL;
- Xilinx_Virtex2_Slave_SelectMap_fns *fn = desc-iface_fns;
+ xilinx_virtex2_slave_selectmap_fns *fn = desc-iface_fns;
if (fn) {
unsigned char *data = (unsigned char *) buf;
@@ -404,13 +404,13 @@ static int Virtex2_ssm_dump(Xilinx_desc *desc, const void
*buf,
[U-Boot] [PATCH 5/9] fpga: xilinx: Fix the rest of CamelCases
No functional changes.
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
include/spartan2.h | 40
include/spartan3.h | 44 ++--
include/virtex2.h | 34 +-
include/xilinx.h | 42 +-
4 files changed, 80 insertions(+), 80 deletions(-)
diff --git a/include/spartan2.h b/include/spartan2.h
index 33b25e6..25db6e7 100644
--- a/include/spartan2.h
+++ b/include/spartan2.h
@@ -16,30 +16,30 @@ int spartan2_info(xilinx_desc *desc);
/* Slave Parallel Implementation function table */
typedef struct {
- Xilinx_pre_fn pre;
- Xilinx_pgm_fn pgm;
- Xilinx_init_fn init;
- Xilinx_err_fn err;
- Xilinx_done_fn done;
- Xilinx_clk_fn clk;
- Xilinx_cs_fncs;
- Xilinx_wr_fnwr;
- Xilinx_rdata_fn rdata;
- Xilinx_wdata_fn wdata;
- Xilinx_busy_fn busy;
- Xilinx_abort_fn abort;
- Xilinx_post_fn post;
+ xilinx_pre_fn pre;
+ xilinx_pgm_fn pgm;
+ xilinx_init_fn init;
+ xilinx_err_fn err;
+ xilinx_done_fn done;
+ xilinx_clk_fn clk;
+ xilinx_cs_fncs;
+ xilinx_wr_fnwr;
+ xilinx_rdata_fn rdata;
+ xilinx_wdata_fn wdata;
+ xilinx_busy_fn busy;
+ xilinx_abort_fn abort;
+ xilinx_post_fn post;
} xilinx_spartan2_slave_parallel_fns;
/* Slave Serial Implementation function table */
typedef struct {
- Xilinx_pre_fn pre;
- Xilinx_pgm_fn pgm;
- Xilinx_clk_fn clk;
- Xilinx_init_fn init;
- Xilinx_done_fn done;
- Xilinx_wr_fnwr;
- Xilinx_post_fn post;
+ xilinx_pre_fn pre;
+ xilinx_pgm_fn pgm;
+ xilinx_clk_fn clk;
+ xilinx_init_fn init;
+ xilinx_done_fn done;
+ xilinx_wr_fnwr;
+ xilinx_post_fn post;
} xilinx_spartan2_slave_serial_fns;
/* Device Image Sizes
diff --git a/include/spartan3.h b/include/spartan3.h
index e06b99b..56698ac 100644
--- a/include/spartan3.h
+++ b/include/spartan3.h
@@ -16,32 +16,32 @@ int spartan3_info(xilinx_desc *desc);
/* Slave Parallel Implementation function table */
typedef struct {
- Xilinx_pre_fn pre;
- Xilinx_pgm_fn pgm;
- Xilinx_init_fn init;
- Xilinx_err_fn err;
- Xilinx_done_fn done;
- Xilinx_clk_fn clk;
- Xilinx_cs_fncs;
- Xilinx_wr_fnwr;
- Xilinx_rdata_fn rdata;
- Xilinx_wdata_fn wdata;
- Xilinx_busy_fn busy;
- Xilinx_abort_fn abort;
- Xilinx_post_fn post;
+ xilinx_pre_fn pre;
+ xilinx_pgm_fn pgm;
+ xilinx_init_fn init;
+ xilinx_err_fn err;
+ xilinx_done_fn done;
+ xilinx_clk_fn clk;
+ xilinx_cs_fncs;
+ xilinx_wr_fnwr;
+ xilinx_rdata_fn rdata;
+ xilinx_wdata_fn wdata;
+ xilinx_busy_fn busy;
+ xilinx_abort_fn abort;
+ xilinx_post_fn post;
} xilinx_spartan3_slave_parallel_fns;
/* Slave Serial Implementation function table */
typedef struct {
- Xilinx_pre_fn pre;
- Xilinx_pgm_fn pgm;
- Xilinx_clk_fn clk;
- Xilinx_init_fn init;
- Xilinx_done_fn done;
- Xilinx_wr_fnwr;
- Xilinx_post_fn post;
- Xilinx_bwr_fn bwr; /* block write function */
- Xilinx_abort_fn abort;
+ xilinx_pre_fn pre;
+ xilinx_pgm_fn pgm;
+ xilinx_clk_fn clk;
+ xilinx_init_fn init;
+ xilinx_done_fn done;
+ xilinx_wr_fnwr;
+ xilinx_post_fn post;
+ xilinx_bwr_fn bwr; /* block write function */
+ xilinx_abort_fn abort;
} xilinx_spartan3_slave_serial_fns;
/* Device Image Sizes
diff --git a/include/virtex2.h b/include/virtex2.h
index dd47965..d39286c 100644
--- a/include/virtex2.h
+++ b/include/virtex2.h
@@ -19,27 +19,27 @@ int virtex2_info(xilinx_desc *desc);
* Slave SelectMap Implementation function table.
*/
typedef struct {
- Xilinx_pre_fn pre;
- Xilinx_pgm_fn pgm;
- Xilinx_init_fn init;
- Xilinx_err_fn err;
- Xilinx_done_fn done;
- Xilinx_clk_fn clk;
- Xilinx_cs_fncs;
- Xilinx_wr_fnwr;
- Xilinx_rdata_fn rdata;
- Xilinx_wdata_fn wdata;
- Xilinx_busy_fn busy;
- Xilinx_abort_fn abort;
- Xilinx_post_fn post;
+ xilinx_pre_fn pre;
+ xilinx_pgm_fn pgm;
+ xilinx_init_fn init;
+ xilinx_err_fn err;
+ xilinx_done_fn done;
+ xilinx_clk_fn clk;
+ xilinx_cs_fncs;
+ xilinx_wr_fnwr;
+ xilinx_rdata_fn rdata;
+ xilinx_wdata_fn wdata;
+ xilinx_busy_fn busy;
+ xilinx_abort_fn abort;
+ xilinx_post_fn post;
} xilinx_virtex2_slave_selectmap_fns;
/* Slave Serial Implementation function table */
typedef struct {
- Xilinx_pgm_fn pgm;
- Xilinx_clk_fn clk;
-
[U-Boot] [PATCH 7/9] fpga: zynq: Remove sparse warnings
Warnings: drivers/fpga/zynqpl.c:150:32: warning: Using plain integer as NULL pointer drivers/fpga/zynqpl.c:152:16: warning: Using plain integer as NULL pointer Signed-off-by: Michal Simek michal.si...@xilinx.com --- drivers/fpga/zynqpl.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/fpga/zynqpl.c b/drivers/fpga/zynqpl.c index dcd3495..0a134e5 100644 --- a/drivers/fpga/zynqpl.c +++ b/drivers/fpga/zynqpl.c @@ -147,9 +147,9 @@ static void *check_data(u8 *buf, size_t bsize, u32 *swap) } /* Loop can be huge - support CTRL + C */ if (ctrlc()) - return 0; + return NULL; } - return 0; + return NULL; } static int zynq_load(xilinx_desc *desc, const void *buf, size_t bsize) -- 1.8.2.3 pgpuPSIKz4XSc.pgp Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v4 4/5] usb/gadget: add the fastboot gadget
On Fri, Apr 25, 2014 at 12:26 AM, Lukasz Majewski l.majew...@samsung.com wrote: Hi Rob, On Wed, Apr 23, 2014 at 6:02 AM, Lukasz Majewski l.majew...@samsung.com wrote: Hi Rob, From: Sebastian Siewior bige...@linutronix.de This patch contains an implementation of the fastboot protocol on the device side and documentation. This is based on USB download gadget infrastructure. The fastboot function implements the getvar, reboot, download and reboot commands. What is missing is the flash handling i.e. writting the image to media. [...] Please consider using dfu_get_buf() from dfu.c to provide dynamically allocated and controlled buffer instead of the CONFIG_USB_FASTBOOT_BUF_ADDR and _SIZE. Another advantage of this code is the ability to set dfu_bufsiz env variable with size of the buffer. I considered this already. I certainly don't like reinventing things which was why I originally used loadaddr and added loadsize to provide a defined load buffer size. The problem is fastboot needs enough RAM to download an entire sparse filesystem. I have no idea what size exactly is typical or required, but it seems that we want to be able to use nearly all free RAM. We can talk all we want about how this is a crappy design, but it is what it is. This is how the protocol works. I understand you :-). The same situation was with DFU on the beginning. Large buffer with starting address defined per board. Then, after some discussion, we come to conclusion that it would be better to increase malloc pool and dynamically allocate buffer. Am I correct, that you don't know beforehand what would be the size of downloaded file - maybe 5 MiB or maybe 512 MiB? Also from your descriptor it seems like fastboot protocol don't want to impose any restrictions about the size. Is it user's responsibility to send data smaller than RAM size? Correct. The client side will check the size which is one of the variables. I searched around some to try to get an idea of what the typical buffer size is without much luck. In the DFU/THOR we store data in buffer size packets (32 MiB). It also has some drawbacks - with large raw data images we cannot download the whole (e.g. rootfs) image and beforehand flashing check integrity. One question - when your board has e.g. 768 MiB of available RAM, then is the size of large rootfs restricted to this size? Yes, but that is not the size of the rootfs partition. The downloaded files are sparse. I would guess only the minimal filesystem is laid down this way and most optional pieces are installed later. The problem with the DFU buffer is it is allocated from the malloc region. If we just increase the malloc region to be close to total RAM size then we will start to break other commands like tftp and fsload which typically just use the RAM u-boot is not using (i.e. all but the end of memory). The only platforms which have more than a few MB for malloc are the ones that enable DFU. Correct. On the other hand when we want to allocate too large buffer we receive error from malloc and flashing is aborted. No harm is done. If increasing your malloc region breaks various load commands, then harm is done. Rob ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 9/9] fpga: zynq: Use helper function zynq_validate_bitstream
From: Siva Durga Prasad Paladugu siva.durga.palad...@xilinx.com
Use helper function zynq_validate_bitstream so that the
code can be reused easily for different cases of dma transfer.
Signed-off-by: Siva Durga Prasad Paladugu siva...@xilinx.com
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
For first 6 patches RFC were sent
---
drivers/fpga/zynqpl.c | 32 +---
1 file changed, 25 insertions(+), 7 deletions(-)
diff --git a/drivers/fpga/zynqpl.c b/drivers/fpga/zynqpl.c
index ef6d1ca..c066f21 100644
--- a/drivers/fpga/zynqpl.c
+++ b/drivers/fpga/zynqpl.c
@@ -320,20 +320,20 @@ static u32 *zynq_align_dma_buffer(u32 *buf, u32 len, u32
swap)
return buf;
}
-static int zynq_load(xilinx_desc *desc, const void *buf, size_t bsize)
+static int zynq_validate_bitstream(xilinx_desc *desc, const void *buf,
+ size_t bsize, u32 blocksize, u32 *swap,
+ u32 *partialbit)
{
- unsigned long ts; /* Timestamp */
- u32 partialbit = 0;
- u32 isr_status, swap, diff;
u32 *buf_start;
+ u32 diff;
/* Detect if we are going working with partial or full bitstream */
if (bsize != desc-size) {
printf(%s: Working with partial bitstream\n, __func__);
- partialbit = 1;
+ *partialbit = 1;
}
+ buf_start = check_data((u8 *)buf, blocksize, swap);
- buf_start = check_data((u8 *)buf, bsize, swap);
if (!buf_start)
return FPGA_FAIL;
@@ -351,7 +351,25 @@ static int zynq_load(xilinx_desc *desc, const void *buf,
size_t bsize)
return FPGA_FAIL;
}
- if (zynq_dma_xfer_init(partialbit))
+ if (zynq_dma_xfer_init(*partialbit))
+ return FPGA_FAIL;
+
+ return 0;
+}
+
+
+static int zynq_load(xilinx_desc *desc, const void *buf, size_t bsize)
+{
+ unsigned long ts; /* Timestamp */
+ u32 partialbit = 0;
+ u32 isr_status, swap;
+
+ /*
+* send bsize inplace of blocksize as it was not a bitstream
+* in chunks
+*/
+ if (zynq_validate_bitstream(desc, buf, bsize, bsize, swap,
+ partialbit))
return FPGA_FAIL;
buf = zynq_align_dma_buffer((u32 *)buf, bsize, swap);
--
1.8.2.3
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[U-Boot] [PATCH 4/9] fpga: xilinx: Avoid CamelCase for in Xilinx_desc
No functional changes.
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
board/armadeus/apf27/fpga.c | 2 +-
board/astro/mcf5373l/fpga.c | 2 +-
board/balloon3/balloon3.c| 2 +-
board/esd/pmc440/fpga.c | 2 +-
board/gen860t/fpga.c | 2 +-
board/matrix_vision/mvsmr/fpga.c | 2 +-
board/spear/x600/fpga.c | 2 +-
board/teejet/mt_ventoux/mt_ventoux.c | 2 +-
board/xilinx/zynq/board.c| 14 +++---
drivers/fpga/spartan2.c | 26 +-
drivers/fpga/spartan3.c | 26 +-
drivers/fpga/virtex2.c | 22 +++---
drivers/fpga/xilinx.c| 14 +++---
drivers/fpga/zynqpl.c| 6 +++---
include/spartan2.h | 6 +++---
include/spartan3.h | 6 +++---
include/virtex2.h| 6 +++---
include/xilinx.h | 10 +-
include/zynqpl.h | 6 +++---
19 files changed, 79 insertions(+), 79 deletions(-)
diff --git a/board/armadeus/apf27/fpga.c b/board/armadeus/apf27/fpga.c
index 56fde20..7d6e1e4 100644
--- a/board/armadeus/apf27/fpga.c
+++ b/board/armadeus/apf27/fpga.c
@@ -42,7 +42,7 @@ xilinx_spartan3_slave_parallel_fns fpga_fns = {
fpga_post_fn,
};
-Xilinx_desc fpga[CONFIG_FPGA_COUNT] = {
+xilinx_desc fpga[CONFIG_FPGA_COUNT] = {
{xilinx_spartan3,
slave_parallel,
1196128l/8,
diff --git a/board/astro/mcf5373l/fpga.c b/board/astro/mcf5373l/fpga.c
index 152ff1f..9dc82c5 100644
--- a/board/astro/mcf5373l/fpga.c
+++ b/board/astro/mcf5373l/fpga.c
@@ -374,7 +374,7 @@ xilinx_spartan3_slave_serial_fns xilinx_fns = {
xilinx_fastwr_fn
};
-Xilinx_desc xilinx_fpga[CONFIG_FPGA_COUNT] = {
+xilinx_desc xilinx_fpga[CONFIG_FPGA_COUNT] = {
{xilinx_spartan3,
slave_serial,
XILINX_XC3S4000_SIZE,
diff --git a/board/balloon3/balloon3.c b/board/balloon3/balloon3.c
index 4aa6605..aa108ca 100644
--- a/board/balloon3/balloon3.c
+++ b/board/balloon3/balloon3.c
@@ -207,7 +207,7 @@ xilinx_spartan3_slave_parallel_fns balloon3_fpga_fns = {
fpga_post_config_fn,
};
-Xilinx_desc fpga = XILINX_XC3S1000_DESC(slave_parallel,
+xilinx_desc fpga = XILINX_XC3S1000_DESC(slave_parallel,
(void *)balloon3_fpga_fns, 0);
/* Initialize the FPGA */
diff --git a/board/esd/pmc440/fpga.c b/board/esd/pmc440/fpga.c
index 18a1b63..f876da8 100644
--- a/board/esd/pmc440/fpga.c
+++ b/board/esd/pmc440/fpga.c
@@ -57,7 +57,7 @@ xilinx_spartan2_slave_serial_fns ngcc_fpga_fns = {
ngcc_fpga_post_config_fn
};
-Xilinx_desc fpga[CONFIG_FPGA_COUNT] = {
+xilinx_desc fpga[CONFIG_FPGA_COUNT] = {
XILINX_XC3S1200E_DESC(
#ifdef USE_SP_CODE
slave_parallel,
diff --git a/board/gen860t/fpga.c b/board/gen860t/fpga.c
index 48a4222..dd0ef70 100644
--- a/board/gen860t/fpga.c
+++ b/board/gen860t/fpga.c
@@ -56,7 +56,7 @@ xilinx_virtex2_slave_selectmap_fns fpga_fns = {
fpga_post_config_fn
};
-Xilinx_desc fpga[CONFIG_FPGA_COUNT] = {
+xilinx_desc fpga[CONFIG_FPGA_COUNT] = {
{xilinx_virtex2,
slave_selectmap,
XILINX_XC2V3000_SIZE,
diff --git a/board/matrix_vision/mvsmr/fpga.c b/board/matrix_vision/mvsmr/fpga.c
index b207455..5189925 100644
--- a/board/matrix_vision/mvsmr/fpga.c
+++ b/board/matrix_vision/mvsmr/fpga.c
@@ -26,7 +26,7 @@ xilinx_spartan3_slave_serial_fns fpga_fns = {
0
};
-Xilinx_desc spartan3 = {
+xilinx_desc spartan3 = {
xilinx_spartan2,
slave_serial,
XILINX_XC3S200_SIZE,
diff --git a/board/spear/x600/fpga.c b/board/spear/x600/fpga.c
index c26eba4..b256222 100644
--- a/board/spear/x600/fpga.c
+++ b/board/spear/x600/fpga.c
@@ -173,7 +173,7 @@ static xilinx_spartan3_slave_serial_fns x600_fpga_fns = {
fpga_post_config_fn,
};
-static Xilinx_desc fpga[CONFIG_FPGA_COUNT] = {
+static xilinx_desc fpga[CONFIG_FPGA_COUNT] = {
XILINX_XC3S1200E_DESC(slave_serial, x600_fpga_fns, 0)
};
diff --git a/board/teejet/mt_ventoux/mt_ventoux.c
b/board/teejet/mt_ventoux/mt_ventoux.c
index a361764..b4a0a72 100644
--- a/board/teejet/mt_ventoux/mt_ventoux.c
+++ b/board/teejet/mt_ventoux/mt_ventoux.c
@@ -200,7 +200,7 @@ xilinx_spartan3_slave_serial_fns mt_ventoux_fpga_fns = {
fpga_post_config_fn,
};
-Xilinx_desc fpga = XILINX_XC6SLX4_DESC(slave_serial,
+xilinx_desc fpga = XILINX_XC6SLX4_DESC(slave_serial,
(void *)mt_ventoux_fpga_fns, 0);
/* Initialize the FPGA */
diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c
index 485a5e4..c8cc2bc 100644
--- a/board/xilinx/zynq/board.c
+++ b/board/xilinx/zynq/board.c
@@ -14,15 +14,15 @@
DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_FPGA
-Xilinx_desc fpga;
+xilinx_desc fpga;
/* It can be done differently */
-Xilinx_desc fpga010 = XILINX_XC7Z010_DESC(0x10);
-Xilinx_desc fpga015 =
[U-Boot] [PATCH 8/9] fpga: zynq: Use helper functions for zynq dma
From: Siva Durga Prasad Paladugu siva.durga.palad...@xilinx.com
Use zynq_dma_xfer_init, zynq_align_dma_buffer,
zynq_dma_transfer helper function performing dma
transfers so that the code can be reused easily for
different cases of dma transfer.
Signed-off-by: Siva Durga Prasad Paladugu siva...@xilinx.com
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
drivers/fpga/zynqpl.c | 201 +-
1 file changed, 115 insertions(+), 86 deletions(-)
diff --git a/drivers/fpga/zynqpl.c b/drivers/fpga/zynqpl.c
index 0a134e5..ef6d1ca 100644
--- a/drivers/fpga/zynqpl.c
+++ b/drivers/fpga/zynqpl.c
@@ -152,70 +152,52 @@ static void *check_data(u8 *buf, size_t bsize, u32 *swap)
return NULL;
}
-static int zynq_load(xilinx_desc *desc, const void *buf, size_t bsize)
+static int zynq_dma_transfer(u32 srcbuf, u32 srclen, u32 dstbuf, u32 dstlen)
{
- unsigned long ts; /* Timestamp */
- u32 partialbit = 0;
- u32 i, control, isr_status, status, swap, diff;
- u32 *buf_start;
+ unsigned long ts;
+ u32 isr_status;
- /* Detect if we are going working with partial or full bitstream */
- if (bsize != desc-size) {
- printf(%s: Working with partial bitstream\n, __func__);
- partialbit = 1;
- }
-
- buf_start = check_data((u8 *)buf, bsize, swap);
- if (!buf_start)
- return FPGA_FAIL;
-
- /* Check if data is postpone from start */
- diff = (u32)buf_start - (u32)buf;
- if (diff) {
- printf(%s: Bitstream is not validated yet (diff %x)\n,
- __func__, diff);
- return FPGA_FAIL;
- }
+ /* Set up the transfer */
+ writel((u32)srcbuf, devcfg_base-dma_src_addr);
+ writel(dstbuf, devcfg_base-dma_dst_addr);
+ writel(srclen, devcfg_base-dma_src_len);
+ writel(dstlen, devcfg_base-dma_dst_len);
- if ((u32)buf SZ_1M) {
- printf(%s: Bitstream has to be placed up to 1MB (%x)\n,
- __func__, (u32)buf);
- return FPGA_FAIL;
- }
+ isr_status = readl(devcfg_base-int_sts);
- if ((u32)buf != ALIGN((u32)buf, ARCH_DMA_MINALIGN)) {
- u32 *new_buf = (u32 *)ALIGN((u32)buf, ARCH_DMA_MINALIGN);
+ /* Polling the PCAP_INIT status for Set */
+ ts = get_timer(0);
+ while (!(isr_status DEVCFG_ISR_DMA_DONE)) {
+ if (isr_status DEVCFG_ISR_ERROR_FLAGS_MASK) {
+ debug(%s: Error: isr = 0x%08X\n, __func__,
+ isr_status);
+ debug(%s: Write count = 0x%08X\n, __func__,
+ readl(devcfg_base-write_count));
+ debug(%s: Read count = 0x%08X\n, __func__,
+ readl(devcfg_base-read_count));
- /*
-* This might be dangerous but permits to flash if
-* ARCH_DMA_MINALIGN is greater than header size
-*/
- if (new_buf buf_start) {
- debug(%s: Aligned buffer is after buffer start\n,
- __func__);
- new_buf -= ARCH_DMA_MINALIGN;
+ return FPGA_FAIL;
}
+ if (get_timer(ts) CONFIG_SYS_FPGA_PROG_TIME) {
+ printf(%s: Timeout wait for DMA to complete\n,
+ __func__);
+ return FPGA_FAIL;
+ }
+ isr_status = readl(devcfg_base-int_sts);
+ }
- printf(%s: Align buffer at %x to %x(swap %d)\n, __func__,
- (u32)buf_start, (u32)new_buf, swap);
-
- for (i = 0; i (bsize/4); i++)
- new_buf[i] = load_word(buf_start[i], swap);
-
- swap = SWAP_DONE;
- buf = new_buf;
- } else if (swap != SWAP_DONE) {
- /* For bitstream which are aligned */
- u32 *new_buf = (u32 *)buf;
+ debug(%s: DMA transfer is done\n, __func__);
- printf(%s: Bitstream is not swapped(%d) - swap it\n, __func__,
- swap);
+ /* Clear out the DMA status */
+ writel(DEVCFG_ISR_DMA_DONE, devcfg_base-int_sts);
- for (i = 0; i (bsize/4); i++)
- new_buf[i] = load_word(buf_start[i], swap);
+ return FPGA_SUCCESS;
+}
- swap = SWAP_DONE;
- }
+static int zynq_dma_xfer_init(u32 partialbit)
+{
+ u32 status, control, isr_status;
+ unsigned long ts;
/* Clear loopback bit */
clrbits_le32(devcfg_base-mctrl, DEVCFG_MCTRL_PCAP_LPBK);
@@ -297,6 +279,83 @@ static int zynq_load(xilinx_desc *desc, const void *buf,
size_t bsize)
writel(DEVCFG_STATUS_DMA_DONE_CNT_MASK, devcfg_base-status);
}
+ return FPGA_SUCCESS;
+}
+
+static u32
[U-Boot] [PATCH 0/18] ARM zynq changes
Hi, I am sending ARM zynq changes. This series is based on FPGA changes I have sent http://lists.denx.de/pipermail/u-boot/2014-April/178204.html (There is small dependency on some patches). My expectation is that fpga series will go to Tom's tree first. Thanks, Michal Michal Simek (12): ARM: zynq: Fix sparse warnings in slcr.c ARM: zynq: Fix sparse warning in ddrc.c ARM: zynq: Remove sparse warnings ARM: zynq: Do not use half memory size for ECC case ARM: zynq: Call zynq board_init() in SPL ARM: zynq: slcr: Fix incorrect commentary ARM: zynq: Setup correct slcr_lock value ARM: zynq: Fix building SPL without FPGA support ARM: zynq: Extend kernel image size to 60MB ARM: zynq: Add MIO detection code ARM: zynq: ehci: Added USB host driver support ARM: zynq: Extend maximum number of command arguments Mike Looijmans (1): ARM: zynq: Fix bootmode mask Siva Durga Prasad Paladugu (5): ARM: zynq: Added efuse status register base address ARM: zynq: Added USB host support for zynq boards ARM: zynq: Enable the FAT write capability ARM: zynq: Move USB/SD/MMC common FAT configs ARM: zynq: Enable EXT4 configs arch/arm/cpu/armv7/zynq/cpu.c | 13 arch/arm/cpu/armv7/zynq/ddrc.c | 5 +- arch/arm/cpu/armv7/zynq/slcr.c | 87 ++-- arch/arm/cpu/armv7/zynq/spl.c | 7 ++ arch/arm/include/asm/arch-zynq/hardware.h | 13 +++- arch/arm/include/asm/arch-zynq/sys_proto.h | 2 + board/xilinx/zynq/board.c | 25 --- drivers/usb/host/Makefile | 1 + drivers/usb/host/ehci-zynq.c | 104 + include/configs/zynq-common.h | 32 +++-- include/configs/zynq_zc70x.h | 1 + include/configs/zynq_zed.h | 1 + 12 files changed, 268 insertions(+), 23 deletions(-) create mode 100644 drivers/usb/host/ehci-zynq.c -- 1.8.2.3 pgpQJyxkTL8vE.pgp Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 01/18] ARM: zynq: Fix sparse warnings in slcr.c
Warnings: arch/arm/cpu/armv7/zynq/slcr.c:21:6: warning: symbol 'zynq_slcr_lock' was not declared. Should it be static? arch/arm/cpu/armv7/zynq/slcr.c:27:6: warning: symbol 'zynq_slcr_unlock' was not declared. Should it be static? arch/arm/cpu/armv7/zynq/slcr.c:34:6: warning: symbol 'zynq_slcr_cpu_reset' was not declared. Should it be static? arch/arm/cpu/armv7/zynq/slcr.c:54:6: warning: symbol 'zynq_slcr_gem_clk_setup' was not declared. Should it be static? arch/arm/cpu/armv7/zynq/slcr.c:81:6: warning: symbol 'zynq_slcr_devcfg_disable' was not declared. Should it be static? arch/arm/cpu/armv7/zynq/slcr.c:94:6: warning: symbol 'zynq_slcr_devcfg_enable' was not declared. Should it be static? arch/arm/cpu/armv7/zynq/slcr.c:107:5: warning: symbol 'zynq_slcr_get_boot_mode' was not declared. Should it be static? arch/arm/cpu/armv7/zynq/slcr.c:113:5: warning: symbol 'zynq_slcr_get_idcode' was not declared. Should it be static? Signed-off-by: Michal Simek michal.si...@xilinx.com --- arch/arm/cpu/armv7/zynq/slcr.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/cpu/armv7/zynq/slcr.c b/arch/arm/cpu/armv7/zynq/slcr.c index d7c1882..c326a4c 100644 --- a/arch/arm/cpu/armv7/zynq/slcr.c +++ b/arch/arm/cpu/armv7/zynq/slcr.c @@ -8,6 +8,7 @@ #include asm/io.h #include malloc.h #include asm/arch/hardware.h +#include asm/arch/sys_proto.h #include asm/arch/clk.h #define SLCR_LOCK_MAGIC0x767B -- 1.8.2.3 pgpGhgO6zpE0A.pgp Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 02/18] ARM: zynq: Fix sparse warning in ddrc.c
Warning:
arch/arm/cpu/armv7/zynq/ddrc.c:43:24: warning: Using plain integer as NULL
pointer
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
arch/arm/cpu/armv7/zynq/ddrc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv7/zynq/ddrc.c b/arch/arm/cpu/armv7/zynq/ddrc.c
index ba6a6ae..302654d 100644
--- a/arch/arm/cpu/armv7/zynq/ddrc.c
+++ b/arch/arm/cpu/armv7/zynq/ddrc.c
@@ -40,7 +40,7 @@ void zynq_ddrc_init(void)
* first stage bootloader. To get ECC to work all memory has
* been initialized by writing any value.
*/
- memset(0, 0, 1 * 1024 * 1024);
+ memset((void *)0, 0, 1 * 1024 * 1024);
} else {
puts(Memory: ECC disabled\n);
}
--
1.8.2.3
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[U-Boot] [PATCH 03/18] ARM: zynq: Remove sparse warnings
Warnings: board/xilinx/zynq/board.c:17:13: warning: symbol 'fpga' was not declared. Should it be static? board/xilinx/zynq/board.c:20:13: warning: symbol 'fpga010' was not declared. Should it be static? board/xilinx/zynq/board.c:21:13: warning: symbol 'fpga015' was not declared. Should it be static? board/xilinx/zynq/board.c:22:13: warning: symbol 'fpga020' was not declared. Should it be static? board/xilinx/zynq/board.c:23:13: warning: symbol 'fpga030' was not declared. Should it be static? board/xilinx/zynq/board.c:24:13: warning: symbol 'fpga045' was not declared. Should it be static? board/xilinx/zynq/board.c:25:13: warning: symbol 'fpga100' was not declared. Should it be static? board/xilinx/zynq/board.c:120:5: warning: symbol 'board_mmc_init' was not declared. Should it be static? Signed-off-by: Michal Simek michal.si...@xilinx.com --- board/xilinx/zynq/board.c | 16 +--- 1 file changed, 9 insertions(+), 7 deletions(-) diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c index c8cc2bc..5190938 100644 --- a/board/xilinx/zynq/board.c +++ b/board/xilinx/zynq/board.c @@ -6,6 +6,8 @@ #include common.h #include fdtdec.h +#include fpga.h +#include mmc.h #include netdev.h #include zynqpl.h #include asm/arch/hardware.h @@ -14,15 +16,15 @@ DECLARE_GLOBAL_DATA_PTR; #ifdef CONFIG_FPGA -xilinx_desc fpga; +static xilinx_desc fpga; /* It can be done differently */ -xilinx_desc fpga010 = XILINX_XC7Z010_DESC(0x10); -xilinx_desc fpga015 = XILINX_XC7Z015_DESC(0x15); -xilinx_desc fpga020 = XILINX_XC7Z020_DESC(0x20); -xilinx_desc fpga030 = XILINX_XC7Z030_DESC(0x30); -xilinx_desc fpga045 = XILINX_XC7Z045_DESC(0x45); -xilinx_desc fpga100 = XILINX_XC7Z100_DESC(0x100); +static xilinx_desc fpga010 = XILINX_XC7Z010_DESC(0x10); +static xilinx_desc fpga015 = XILINX_XC7Z015_DESC(0x15); +static xilinx_desc fpga020 = XILINX_XC7Z020_DESC(0x20); +static xilinx_desc fpga030 = XILINX_XC7Z030_DESC(0x30); +static xilinx_desc fpga045 = XILINX_XC7Z045_DESC(0x45); +static xilinx_desc fpga100 = XILINX_XC7Z100_DESC(0x100); #endif int board_init(void) -- 1.8.2.3 pgparlResJ3NJ.pgp Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 04/18] ARM: zynq: Added efuse status register base address
From: Siva Durga Prasad Paladugu siva.durga.palad...@xilinx.com
Added efuse status register base address. This register
is used for determining whether efuse was blown or not.
Also, added the zynq_get_silicon_version() to get the
silicon version of the zynq board.
Signed-off-by: Siva Durga Prasad Paladugu siva...@xilinx.com
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
arch/arm/cpu/armv7/zynq/cpu.c | 13 +
arch/arm/include/asm/arch-zynq/hardware.h | 9 +
arch/arm/include/asm/arch-zynq/sys_proto.h | 1 +
3 files changed, 23 insertions(+)
diff --git a/arch/arm/cpu/armv7/zynq/cpu.c b/arch/arm/cpu/armv7/zynq/cpu.c
index 7626b5c..816d0c5 100644
--- a/arch/arm/cpu/armv7/zynq/cpu.c
+++ b/arch/arm/cpu/armv7/zynq/cpu.c
@@ -14,6 +14,9 @@ void lowlevel_init(void)
{
}
+#define ZYNQ_SILICON_VER_MASK 0xF000
+#define ZYNQ_SILICON_VER_SHIFT 28
+
int arch_cpu_init(void)
{
zynq_slcr_unlock();
@@ -42,6 +45,16 @@ int arch_cpu_init(void)
return 0;
}
+unsigned int zynq_get_silicon_version(void)
+{
+ unsigned int ver;
+
+ ver = (readl(devcfg_base-mctrl)
+ ZYNQ_SILICON_VER_MASK) ZYNQ_SILICON_VER_SHIFT;
+
+ return ver;
+}
+
void reset_cpu(ulong addr)
{
zynq_slcr_cpu_reset();
diff --git a/arch/arm/include/asm/arch-zynq/hardware.h
b/arch/arm/include/asm/arch-zynq/hardware.h
index 39184da..20f62bf 100644
--- a/arch/arm/include/asm/arch-zynq/hardware.h
+++ b/arch/arm/include/asm/arch-zynq/hardware.h
@@ -22,6 +22,7 @@
#define ZYNQ_SPI_BASEADDR0 0xE0006000
#define ZYNQ_SPI_BASEADDR1 0xE0007000
#define ZYNQ_DDRC_BASEADDR 0xF8006000
+#define ZYNQ_EFUSE_BASEADDR0xF800D000
/* Bootmode setting values */
#define ZYNQ_BM_MASK 0xF
@@ -130,4 +131,12 @@ struct ddrc_regs {
};
#define ddrc_base ((struct ddrc_regs *)ZYNQ_DDRC_BASEADDR)
+struct efuse_reg {
+ u32 reserved1[4];
+ u32 status;
+ u32 reserved2[3];
+};
+
+#define efuse_base ((struct efuse_reg *)ZYNQ_EFUSE_BASEADDR)
+
#endif /* _ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/include/asm/arch-zynq/sys_proto.h
b/arch/arm/include/asm/arch-zynq/sys_proto.h
index a68e1b3..2445a04 100644
--- a/arch/arm/include/asm/arch-zynq/sys_proto.h
+++ b/arch/arm/include/asm/arch-zynq/sys_proto.h
@@ -16,6 +16,7 @@ extern void zynq_slcr_devcfg_enable(void);
extern u32 zynq_slcr_get_boot_mode(void);
extern u32 zynq_slcr_get_idcode(void);
extern void zynq_ddrc_init(void);
+extern unsigned int zynq_get_silicon_version(void);
/* Driver extern functions */
extern int zynq_sdhci_init(u32 regbase);
--
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[U-Boot] [PATCH 05/18] ARM: zynq: Do not use half memory size for ECC case
Memory size should be specified without ECC place.
If you need to have half memory size, please change
u-boot configuration.
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
arch/arm/cpu/armv7/zynq/ddrc.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/arch/arm/cpu/armv7/zynq/ddrc.c b/arch/arm/cpu/armv7/zynq/ddrc.c
index 302654d..e0ed3bf 100644
--- a/arch/arm/cpu/armv7/zynq/ddrc.c
+++ b/arch/arm/cpu/armv7/zynq/ddrc.c
@@ -44,7 +44,4 @@ void zynq_ddrc_init(void)
} else {
puts(Memory: ECC disabled\n);
}
-
- if (width == ZYNQ_DDRC_CTRLREG_BUSWIDTH_16BIT)
- gd-ram_size /= 2;
}
--
1.8.2.3
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[U-Boot] [PATCH 06/18] ARM: zynq: Call zynq board_init() in SPL
From: Michal Simek mon...@monstr.eu
Call board_init() if SPL is configured with CONFIG_SPL_BOARD_INIT.
Signed-off-by: Michal Simek mon...@monstr.eu
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
arch/arm/cpu/armv7/zynq/spl.c | 7 +++
include/configs/zynq-common.h | 1 +
2 files changed, 8 insertions(+)
diff --git a/arch/arm/cpu/armv7/zynq/spl.c b/arch/arm/cpu/armv7/zynq/spl.c
index fcad762..c3ea221 100644
--- a/arch/arm/cpu/armv7/zynq/spl.c
+++ b/arch/arm/cpu/armv7/zynq/spl.c
@@ -28,6 +28,13 @@ void board_init_f(ulong dummy)
board_init_r(NULL, 0);
}
+#ifdef CONFIG_SPL_BOARD_INIT
+void spl_board_init(void)
+{
+ board_init();
+}
+#endif
+
u32 spl_boot_device(void)
{
u32 mode;
diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h
index 731e69b..2080a61 100644
--- a/include/configs/zynq-common.h
+++ b/include/configs/zynq-common.h
@@ -235,6 +235,7 @@
#define CONFIG_SPL_LIBCOMMON_SUPPORT
#define CONFIG_SPL_LIBGENERIC_SUPPORT
#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_BOARD_INIT
#define CONFIG_SPL_LDSCRIPTarch/arm/cpu/armv7/zynq/u-boot-spl.lds
--
1.8.2.3
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[U-Boot] [PATCH 09/18] ARM: zynq: Fix bootmode mask
From: Mike Looijmans mike.looijm...@topic.nl Bootmode mask was defined as 0x0F, but documentation mentions 0x07. Experiments show that bit 3 is the JTAG chain configuration. Change the mask to 7 to allow systems with a different chain configuration to boot correctly. Signed-off-by: Mike Looijmans mike.looijm...@topic.nl Signed-off-by: Michal Simek michal.si...@xilinx.com Acked-by: Siva Durga Prasad Paladugu siva...@xilinx.com --- arch/arm/include/asm/arch-zynq/hardware.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/include/asm/arch-zynq/hardware.h b/arch/arm/include/asm/arch-zynq/hardware.h index 20f62bf..a9d091f 100644 --- a/arch/arm/include/asm/arch-zynq/hardware.h +++ b/arch/arm/include/asm/arch-zynq/hardware.h @@ -25,7 +25,7 @@ #define ZYNQ_EFUSE_BASEADDR0xF800D000 /* Bootmode setting values */ -#define ZYNQ_BM_MASK 0xF +#define ZYNQ_BM_MASK 0x7 #define ZYNQ_BM_NOR0x2 #define ZYNQ_BM_SD 0x5 #define ZYNQ_BM_JTAG 0x0 -- 1.8.2.3 pgpA23cJeeYdN.pgp Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 08/18] ARM: zynq: Setup correct slcr_lock value
The driver should setup slcr state according
to slcr operations.
Reported-by: Andrey Filippov and...@elphel.com
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
arch/arm/cpu/armv7/zynq/slcr.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/arch/arm/cpu/armv7/zynq/slcr.c b/arch/arm/cpu/armv7/zynq/slcr.c
index 1ff1eac..5ba58fa 100644
--- a/arch/arm/cpu/armv7/zynq/slcr.c
+++ b/arch/arm/cpu/armv7/zynq/slcr.c
@@ -21,14 +21,18 @@ static int slcr_lock = 1; /* 1 means locked, 0 means
unlocked */
void zynq_slcr_lock(void)
{
- if (!slcr_lock)
+ if (!slcr_lock) {
writel(SLCR_LOCK_MAGIC, slcr_base-slcr_lock);
+ slcr_lock = 1;
+ }
}
void zynq_slcr_unlock(void)
{
- if (slcr_lock)
+ if (slcr_lock) {
writel(SLCR_UNLOCK_MAGIC, slcr_base-slcr_unlock);
+ slcr_lock = 0;
+ }
}
/* Reset the entire system */
--
1.8.2.3
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[U-Boot] [PATCH 07/18] ARM: zynq: slcr: Fix incorrect commentary
Fix cp error in zynq_slcr_devcfg_enable() commentary
and extending it with description according
to Zynq TRM also in zynq_slcr_devcfg_disable().
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
arch/arm/cpu/armv7/zynq/slcr.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/cpu/armv7/zynq/slcr.c b/arch/arm/cpu/armv7/zynq/slcr.c
index c326a4c..1ff1eac 100644
--- a/arch/arm/cpu/armv7/zynq/slcr.c
+++ b/arch/arm/cpu/armv7/zynq/slcr.c
@@ -83,7 +83,7 @@ void zynq_slcr_devcfg_disable(void)
{
zynq_slcr_unlock();
- /* Disable AXI interface */
+ /* Disable AXI interface by asserting FPGA resets */
writel(0x, slcr_base-fpga_rst_ctrl);
/* Set Level Shifters DT618760 */
@@ -99,7 +99,7 @@ void zynq_slcr_devcfg_enable(void)
/* Set Level Shifters DT618760 */
writel(0xF, slcr_base-lvl_shftr_en);
- /* Disable AXI interface */
+ /* Enable AXI interface by de-asserting FPGA resets */
writel(0x0, slcr_base-fpga_rst_ctrl);
zynq_slcr_lock();
--
1.8.2.3
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[U-Boot] [PATCH 10/18] ARM: zynq: Fix building SPL without FPGA support
When CONFIG_FPGA is defined but CONFIG_SPL_FPGA is not, the build fails:
board.c: In function 'board_init':
board.c:41:3: error: 'fpga' undeclared (first use in this function)
fpga = fpga010;
Fix this by expanding the #if.. around this block to match the other
FPGA checks and don't compile this block when buildign for SPL without
FPGA support.
Tested a bootloader that had CONFIG_FPGA defined without CONFIG_SPL_FPGA,
this now compiles without errors and loading FPGA from u-boot works.
Signed-off-by: Mike Looijmans mike.looijm...@topic.nl
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
board/xilinx/zynq/board.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c
index 5190938..258632e 100644
--- a/board/xilinx/zynq/board.c
+++ b/board/xilinx/zynq/board.c
@@ -15,7 +15,8 @@
DECLARE_GLOBAL_DATA_PTR;
-#ifdef CONFIG_FPGA
+#if (defined(CONFIG_FPGA) !defined(CONFIG_SPL_BUILD)) || \
+(defined(CONFIG_SPL_FPGA_SUPPORT) defined(CONFIG_SPL_BUILD))
static xilinx_desc fpga;
/* It can be done differently */
@@ -29,7 +30,8 @@ static xilinx_desc fpga100 = XILINX_XC7Z100_DESC(0x100);
int board_init(void)
{
-#ifdef CONFIG_FPGA
+#if (defined(CONFIG_FPGA) !defined(CONFIG_SPL_BUILD)) || \
+(defined(CONFIG_SPL_FPGA_SUPPORT) defined(CONFIG_SPL_BUILD))
u32 idcode;
idcode = zynq_slcr_get_idcode();
@@ -56,7 +58,8 @@ int board_init(void)
}
#endif
-#ifdef CONFIG_FPGA
+#if (defined(CONFIG_FPGA) !defined(CONFIG_SPL_BUILD)) || \
+(defined(CONFIG_SPL_FPGA_SUPPORT) defined(CONFIG_SPL_BUILD))
fpga_init();
fpga_add(fpga_xilinx, fpga);
#endif
--
1.8.2.3
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[U-Boot] [PATCH 11/18] ARM: zynq: Extend kernel image size to 60MB
Extend max kernel image size. Gunzip is checking this value. If kernel is larger, message below is shown. Uncompressing Kernel Image ... Error: inflate() returned -5 GUNZIP: uncompress, out-of-mem or overwrite error - must RESET board to recover Signed-off-by: Michal Simek michal.si...@xilinx.com --- include/configs/zynq-common.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index 2080a61..8ee78e4 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -209,7 +209,7 @@ #define CONFIG_RSA /* Extend size of kernel image for uncompression */ -#define CONFIG_SYS_BOOTM_LEN (20 * 1024 * 1024) +#define CONFIG_SYS_BOOTM_LEN (60 * 1024 * 1024) /* Boot FreeBSD/vxWorks from an ELF image */ #if defined(CONFIG_ZYNQ_BOOT_FREEBSD) -- 1.8.2.3 pgpDcRzX5oDPr.pgp Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 15/18] ARM: zynq: Enable the FAT write capability
From: Siva Durga Prasad Paladugu siva.durga.palad...@xilinx.com Enable the FAT write capability for SD/MMC write functionality. Signed-off-by: Siva Durga Prasad Paladugu siva...@xilinx.com Signed-off-by: Michal Simek michal.si...@xilinx.com --- include/configs/zynq-common.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index bcc476e..1cfc963 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -86,6 +86,7 @@ # define CONFIG_CMD_FAT # define CONFIG_SUPPORT_VFAT # define CONFIG_CMD_EXT2 +# define CONFIG_FAT_WRITE # define CONFIG_DOS_PARTITION #endif -- 1.8.2.3 pgp8G1UsTAHs7.pgp Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 12/18] ARM: zynq: Add MIO detection code
From: Michal Simek mon...@monstr.eu
Add run-time MIO pin detection to get actual
pin configuration for specific periphery.
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
arch/arm/cpu/armv7/zynq/slcr.c | 50 ++
arch/arm/include/asm/arch-zynq/sys_proto.h | 1 +
2 files changed, 51 insertions(+)
diff --git a/arch/arm/cpu/armv7/zynq/slcr.c b/arch/arm/cpu/armv7/zynq/slcr.c
index 5ba58fa..51894f9 100644
--- a/arch/arm/cpu/armv7/zynq/slcr.c
+++ b/arch/arm/cpu/armv7/zynq/slcr.c
@@ -17,6 +17,26 @@
#define SLCR_IDCODE_MASK 0x1F000
#define SLCR_IDCODE_SHIFT 12
+/*
+ * zynq_slcr_mio_get_status - Get the status of MIO peripheral.
+ *
+ * @peri_name: Name of the peripheral for checking MIO status
+ * @get_pins: Pointer to array of get pin for this peripheral
+ * @num_pins: Number of pins for this peripheral
+ * @mask: Mask value
+ * @check_val: Required check value to get the status of periph
+ */
+struct zynq_slcr_mio_get_status {
+ const char *peri_name;
+ const int *get_pins;
+ int num_pins;
+ u32 mask;
+ u32 check_val;
+};
+
+static const struct zynq_slcr_mio_get_status mio_periphs[] = {
+};
+
static int slcr_lock = 1; /* 1 means locked, 0 means unlocked */
void zynq_slcr_lock(void)
@@ -120,3 +140,33 @@ u32 zynq_slcr_get_idcode(void)
return (readl(slcr_base-pss_idcode) SLCR_IDCODE_MASK)
SLCR_IDCODE_SHIFT;
}
+
+/*
+ * zynq_slcr_get_mio_pin_status - Get the MIO pin status of peripheral.
+ *
+ * @periph: Name of the peripheral
+ *
+ * Returns count to indicate the number of pins configured for the
+ * given @periph.
+ */
+int zynq_slcr_get_mio_pin_status(const char *periph)
+{
+ const struct zynq_slcr_mio_get_status *mio_ptr;
+ int val, i, j;
+ int mio = 0;
+
+ for (i = 0; i ARRAY_SIZE(mio_periphs); i++) {
+ if (strcmp(periph, mio_periphs[i].peri_name) == 0) {
+ mio_ptr = mio_periphs[i];
+ for (j = 0; j mio_ptr-num_pins; j++) {
+ val = readl(slcr_base-mio_pin
+ [mio_ptr-get_pins[j]]);
+ if ((val mio_ptr-mask) == mio_ptr-check_val)
+ mio++;
+ }
+ break;
+ }
+ }
+
+ return mio;
+}
diff --git a/arch/arm/include/asm/arch-zynq/sys_proto.h
b/arch/arm/include/asm/arch-zynq/sys_proto.h
index 2445a04..53c30ec 100644
--- a/arch/arm/include/asm/arch-zynq/sys_proto.h
+++ b/arch/arm/include/asm/arch-zynq/sys_proto.h
@@ -15,6 +15,7 @@ extern void zynq_slcr_devcfg_disable(void);
extern void zynq_slcr_devcfg_enable(void);
extern u32 zynq_slcr_get_boot_mode(void);
extern u32 zynq_slcr_get_idcode(void);
+extern int zynq_slcr_get_mio_pin_status(const char *periph);
extern void zynq_ddrc_init(void);
extern unsigned int zynq_get_silicon_version(void);
--
1.8.2.3
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[U-Boot] [PATCH 17/18] ARM: zynq: Enable EXT4 configs
From: Siva Durga Prasad Paladugu siva.durga.palad...@xilinx.com Enabled the EXT4 configs. Signed-off-by: Siva Durga Prasad Paladugu siva...@xilinx.com Signed-off-by: Michal Simek michal.si...@xilinx.com --- include/configs/zynq-common.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index 0a7d104..09d6c55 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -102,6 +102,8 @@ # define CONFIG_CMD_EXT2 # define CONFIG_FAT_WRITE # define CONFIG_DOS_PARTITION +# define CONFIG_CMD_EXT4 +# define CONFIG_CMD_EXT4_WRITE #endif #define CONFIG_SYS_I2C_ZYNQ -- 1.8.2.3 pgpqnt8Jkc1xm.pgp Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 13/18] ARM: zynq: ehci: Added USB host driver support
From: Michal Simek mon...@monstr.eu
Added USB host driver for zynq.
Signed-off-by: Siva Durga Prasad Paladugu siva...@xilinx.com
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
arch/arm/cpu/armv7/zynq/slcr.c| 24 +++
arch/arm/include/asm/arch-zynq/hardware.h | 2 +
drivers/usb/host/Makefile | 1 +
drivers/usb/host/ehci-zynq.c | 104 ++
4 files changed, 131 insertions(+)
create mode 100644 drivers/usb/host/ehci-zynq.c
diff --git a/arch/arm/cpu/armv7/zynq/slcr.c b/arch/arm/cpu/armv7/zynq/slcr.c
index 51894f9..934ccc3 100644
--- a/arch/arm/cpu/armv7/zynq/slcr.c
+++ b/arch/arm/cpu/armv7/zynq/slcr.c
@@ -14,6 +14,8 @@
#define SLCR_LOCK_MAGIC0x767B
#define SLCR_UNLOCK_MAGIC 0xDF0D
+#define SLCR_USB_L1_SEL0x04
+
#define SLCR_IDCODE_MASK 0x1F000
#define SLCR_IDCODE_SHIFT 12
@@ -34,7 +36,29 @@ struct zynq_slcr_mio_get_status {
u32 check_val;
};
+static const int usb0_pins[] = {
+ 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39
+};
+
+static const int usb1_pins[] = {
+ 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51
+};
+
static const struct zynq_slcr_mio_get_status mio_periphs[] = {
+ {
+ usb0,
+ usb0_pins,
+ ARRAY_SIZE(usb0_pins),
+ SLCR_USB_L1_SEL,
+ SLCR_USB_L1_SEL,
+ },
+ {
+ usb1,
+ usb1_pins,
+ ARRAY_SIZE(usb1_pins),
+ SLCR_USB_L1_SEL,
+ SLCR_USB_L1_SEL,
+ },
};
static int slcr_lock = 1; /* 1 means locked, 0 means unlocked */
diff --git a/arch/arm/include/asm/arch-zynq/hardware.h
b/arch/arm/include/asm/arch-zynq/hardware.h
index a9d091f..2aede0c 100644
--- a/arch/arm/include/asm/arch-zynq/hardware.h
+++ b/arch/arm/include/asm/arch-zynq/hardware.h
@@ -23,6 +23,8 @@
#define ZYNQ_SPI_BASEADDR1 0xE0007000
#define ZYNQ_DDRC_BASEADDR 0xF8006000
#define ZYNQ_EFUSE_BASEADDR0xF800D000
+#define ZYNQ_USB_BASEADDR0 0xE0002000
+#define ZYNQ_USB_BASEADDR1 0xE0003000
/* Bootmode setting values */
#define ZYNQ_BM_MASK 0x7
diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
index 578b097..bf87204 100644
--- a/drivers/usb/host/Makefile
+++ b/drivers/usb/host/Makefile
@@ -36,6 +36,7 @@ obj-$(CONFIG_USB_EHCI_PCI) += ehci-pci.o
obj-$(CONFIG_USB_EHCI_SPEAR) += ehci-spear.o
obj-$(CONFIG_USB_EHCI_TEGRA) += ehci-tegra.o
obj-$(CONFIG_USB_EHCI_VCT) += ehci-vct.o
+obj-$(CONFIG_USB_EHCI_ZYNQ) += ehci-zynq.o
# xhci
obj-$(CONFIG_USB_XHCI) += xhci.o xhci-mem.o xhci-ring.o
diff --git a/drivers/usb/host/ehci-zynq.c b/drivers/usb/host/ehci-zynq.c
new file mode 100644
index 000..7770d05
--- /dev/null
+++ b/drivers/usb/host/ehci-zynq.c
@@ -0,0 +1,104 @@
+/*
+ * (C) Copyright 2014, Xilinx, Inc
+ *
+ * USB Low level initialization(Specific to zynq)
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include asm/arch/hardware.h
+#include asm/arch/sys_proto.h
+#include asm/io.h
+#include usb.h
+#include usb/ehci-fsl.h
+#include usb/ulpi.h
+
+#include ehci.h
+
+#define ZYNQ_USB_USBCMD_RST0x002
+#define ZYNQ_USB_USBCMD_STOP 0x000
+#define ZYNQ_USB_NUM_MIO 12
+
+/*
+ * Create the appropriate control structures to manage
+ * a new EHCI host controller.
+ */
+int ehci_hcd_init(int index, enum usb_init_type init, struct ehci_hccr **hccr,
+ struct ehci_hcor **hcor)
+{
+ struct usb_ehci *ehci;
+ struct ulpi_viewport ulpi_vp;
+ int ret, mio_usb;
+ /* Used for writing the ULPI data address */
+ struct ulpi_regs *ulpi = (struct ulpi_regs *)0;
+
+ if (!index) {
+ mio_usb = zynq_slcr_get_mio_pin_status(usb0);
+ if (mio_usb != ZYNQ_USB_NUM_MIO) {
+ printf(usb0 wrong num MIO: %d, Index %d\n, mio_usb,
+ index);
+ return -1;
+ }
+ ehci = (struct usb_ehci *)ZYNQ_USB_BASEADDR0;
+ } else {
+ mio_usb = zynq_slcr_get_mio_pin_status(usb1);
+ if (mio_usb != ZYNQ_USB_NUM_MIO) {
+ printf(usb1 wrong num MIO: %d, Index %d\n, mio_usb,
+ index);
+ return -1;
+ }
+ ehci = (struct usb_ehci *)ZYNQ_USB_BASEADDR1;
+ }
+
+ *hccr = (struct ehci_hccr *)((uint32_t)ehci-caplength);
+ *hcor = (struct ehci_hcor *)((uint32_t) *hccr +
+ HC_LENGTH(ehci_readl((*hccr)-cr_capbase)));
+
+ ulpi_vp.viewport_addr = (u32)ehci-ulpi_viewpoint;
+ ulpi_vp.port_num = 0;
+
+ ret = ulpi_init(ulpi_vp);
+ if (ret) {
+ puts(zynq ULPI viewport init failed\n);
+ return -1;
+ }
+
+
[U-Boot] [PATCH 14/18] ARM: zynq: Added USB host support for zynq boards
From: Siva Durga Prasad Paladugu siva.durga.palad...@xilinx.com
Added configs to support USB host for zynq boards.
Also added a command usbboot to boot from usb.
Signed-off-by: Siva Durga Prasad Paladugu siva...@xilinx.com
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
include/configs/zynq-common.h | 20 +++-
include/configs/zynq_zc70x.h | 1 +
include/configs/zynq_zed.h| 1 +
3 files changed, 21 insertions(+), 1 deletion(-)
diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h
index 8ee78e4..bcc476e 100644
--- a/include/configs/zynq-common.h
+++ b/include/configs/zynq-common.h
@@ -89,6 +89,18 @@
# define CONFIG_DOS_PARTITION
#endif
+#ifdef CONFIG_ZYNQ_USB
+# define CONFIG_USB_EHCI
+# define CONFIG_CMD_USB
+# define CONFIG_USB_STORAGE
+# define CONFIG_SUPPORT_VFAT
+# define CONFIG_USB_EHCI_ZYNQ
+# define CONFIG_USB_ULPI_VIEWPORT
+# define CONFIG_USB_ULPI
+# define CONFIG_EHCI_IS_TDI
+# define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+#endif
+
#define CONFIG_SYS_I2C_ZYNQ
/* I2C */
#if defined(CONFIG_SYS_I2C_ZYNQ)
@@ -150,7 +162,13 @@
bootm ${load_addr}\0 \
jtagboot=echo TFTPing FIT to RAM... \
tftpboot ${load_addr} ${fit_image} \
- bootm ${load_addr}\0
+ bootm ${load_addr}\0 \
+ usbboot=if usb start; then \
+ echo Copying FIT from USB to RAM... \
+ fatload usb 0 ${load_addr} ${fit_image} \
+ bootm ${load_addr}\0 \
+ fi\0
+
#define CONFIG_BOOTCOMMAND run $modeboot
#define CONFIG_BOOTDELAY 3 /* -1 to Disable autoboot */
#define CONFIG_SYS_LOAD_ADDR 0 /* default? */
diff --git a/include/configs/zynq_zc70x.h b/include/configs/zynq_zc70x.h
index de0e241..291a5fe 100644
--- a/include/configs/zynq_zc70x.h
+++ b/include/configs/zynq_zc70x.h
@@ -19,6 +19,7 @@
#define CONFIG_SYS_NO_FLASH
#define CONFIG_ZYNQ_SDHCI0
+#define CONFIG_ZYNQ_USB
#define CONFIG_ZYNQ_I2C0
#define CONFIG_ZYNQ_EEPROM
#define CONFIG_ZYNQ_BOOT_FREEBSD
diff --git a/include/configs/zynq_zed.h b/include/configs/zynq_zed.h
index 274140c..ce17d40 100644
--- a/include/configs/zynq_zed.h
+++ b/include/configs/zynq_zed.h
@@ -18,6 +18,7 @@
#define CONFIG_SYS_NO_FLASH
+#define CONFIG_ZYNQ_USB
#define CONFIG_ZYNQ_SDHCI0
#define CONFIG_ZYNQ_BOOT_FREEBSD
#define CONFIG_DEFAULT_DEVICE_TREE zynq-zed
--
1.8.2.3
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[U-Boot] [PATCH 16/18] ARM: zynq: Move USB/SD/MMC common FAT configs
From: Siva Durga Prasad Paladugu siva.durga.palad...@xilinx.com Moved the USB/SD/MMC common FAT configs separately to avoid redefinition warnings. Signed-off-by: Siva Durga Prasad Paladugu siva...@xilinx.com Signed-off-by: Michal Simek michal.si...@xilinx.com --- include/configs/zynq-common.h | 14 -- 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index 1cfc963..0a7d104 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -83,18 +83,12 @@ # define CONFIG_SDHCI # define CONFIG_ZYNQ_SDHCI # define CONFIG_CMD_MMC -# define CONFIG_CMD_FAT -# define CONFIG_SUPPORT_VFAT -# define CONFIG_CMD_EXT2 -# define CONFIG_FAT_WRITE -# define CONFIG_DOS_PARTITION #endif #ifdef CONFIG_ZYNQ_USB # define CONFIG_USB_EHCI # define CONFIG_CMD_USB # define CONFIG_USB_STORAGE -# define CONFIG_SUPPORT_VFAT # define CONFIG_USB_EHCI_ZYNQ # define CONFIG_USB_ULPI_VIEWPORT # define CONFIG_USB_ULPI @@ -102,6 +96,14 @@ # define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #endif +#if defined(CONFIG_ZYNQ_SDHCI) || defined(CONFIG_ZYNQ_USB) +# define CONFIG_SUPPORT_VFAT +# define CONFIG_CMD_FAT +# define CONFIG_CMD_EXT2 +# define CONFIG_FAT_WRITE +# define CONFIG_DOS_PARTITION +#endif + #define CONFIG_SYS_I2C_ZYNQ /* I2C */ #if defined(CONFIG_SYS_I2C_ZYNQ) -- 1.8.2.3 pgpFSNfc6vPHa.pgp Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v9 0/2] S5P: Exynos: Add GPIO numbering feature
Hello, On 04/21/2014 04:25 PM, Akshay Saraswat wrote: Used a script to recheck/verify pin mapping and existing mapping appears to be fine, returning correct bank and pin values. Did ./MAKEALL -a arm and found all Exynos/S5P related boards compiled successfully. Couldn't test booting over all of them. Tested U-Boot bootup over SMDK5420, SMDK5250, Snow. Requesting maintaners to please test over affected SoCs/boards. Changes in V2: - Enabled CMD_GPIO as suggested by Simon Glass and supported same for EXYNOS5. Changes in V3: - New patch added to rename S5P GPIO definitions to S5P_GPIO. - GPIO Table added to calculate the base address of input gpio bank. Changes in V4: - To have consistent 0..n-1 GPIO numbering the banks are divided into different parts where ever they have holes in them. - Function and table to support gpio command moved to s5p-gpio driver. - Rebased on latest u-boot-samsung tree. Changes in V5: - Rebased on latest u-boot-samsung tree. - Removed Exynos5 specific code in gpio driver api to get bank. - Added #define HAVE_GENERIC_GPIO in config file to remove conditinal CPU check in gpio driver. Changes in V6: - Isolated config changes in a new patch. - Updated patches with corresponding changes for Exynos 5420. Changes in V7: - Added changes for other SoCs like Exynos 4412, 4210 etc. Changes in V8: - Changed Subject of patch 2/2 to reflect affected SoCs/boards. - Fixed arndale board compile time errors introduced due to patch-set v7. Changes in V9: - Fixed checkpatch errors. - Fixed naming error in exynos_gpio_data arrays which could be the possible reason behind data abort witnessed over Exynos4 boards. Akshay Saraswat (2): EXYNOS: Add GPIO pin numbering and rename definitions S5P: Exynos: Config: Enable Generic GPIO and CMD configs arch/arm/cpu/armv7/exynos/pinmux.c | 403 +++ arch/arm/include/asm/arch-exynos/cpu.h | 17 +- arch/arm/include/asm/arch-exynos/gpio.h | 1786 +- arch/arm/include/asm/arch-s5pc1xx/gpio.h | 941 +--- board/samsung/arndale/arndale.c | 11 +- board/samsung/goni/goni.c| 26 +- board/samsung/smdk5250/exynos5-dt.c | 20 +- board/samsung/smdk5250/smdk5250.c| 19 +- board/samsung/smdk5420/smdk5420.c| 15 +- board/samsung/smdkc100/smdkc100.c|5 +- board/samsung/smdkv310/smdkv310.c| 17 +- board/samsung/trats/trats.c | 39 +- board/samsung/trats2/trats2.c| 74 +- board/samsung/universal_c210/universal.c | 51 +- drivers/gpio/s5p_gpio.c | 195 +++- include/configs/arndale.h|1 + include/configs/exynos5-dt.h |3 + include/configs/origen.h |1 + include/configs/s5p_goni.h |5 +- include/configs/s5pc210_universal.h | 17 +- include/configs/smdkc100.h |1 + include/configs/smdkv310.h |2 + include/configs/trats.h |9 +- include/configs/trats2.h |5 +- 24 files changed, 2806 insertions(+), 857 deletions(-) I think that you missed my last few comments. You are still using exynos_gpio_get() - what for? It returns some number and next it's interpreted as gpio continuous number - but it isn't continuous. It's because each samsung board has now defined HAVE_GENERIC_GPIO, so gpio numbers are interpreted as linear. We don't need additional macro since you introduce linear numbering. Please read my last comments again. I tried test this on trats2 device but data abort occurs at PMIC init, it's probably because exynos_gpio_get(). Please use just gpio numbering as you defined in this patchset. Thank you -- Przemyslaw Marczak Samsung RD Institute Poland Samsung Electronics p.marc...@samsung.com ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v9 1/2] S5P: Exynos: Add GPIO pin numbering and rename definitions
Hi,
On 04/21/2014 04:25 PM, Akshay Saraswat wrote:
This patch includes following changes :
* Adds gpio pin numbering support for EXYNOS SOCs.
To have consistent 0..n-1 GPIO numbering the banks are divided
into different parts where ever they have holes in them.
* Rename GPIO definitions from GPIO_... to S5P_GPIO_...
These changes were done to enable cmd_gpio for EXYNOS and
cmd_gpio has GPIO_INPUT same as s5p_gpio driver and hence
getting a error during compilation.
* Adds support for name to gpio conversion in s5p_gpio to enable
gpio command EXYNOS SoCs. Function has been added to asm/gpio.h
to decode the input gpio name to gpio number.
Example: SMDK5420 # gpio set gpa00
Signed-off-by: Leela Krishna Amudala l.kris...@samsung.com
Signed-off-by: Rajeshwari Shinde rajeshwar...@samsung.com
Signed-off-by: Akshay Saraswat aksha...@samsung.com
---
arch/arm/cpu/armv7/exynos/pinmux.c | 403 +++
arch/arm/include/asm/arch-exynos/cpu.h | 17 +-
arch/arm/include/asm/arch-exynos/gpio.h | 1786 +-
arch/arm/include/asm/arch-s5pc1xx/gpio.h | 941 +---
board/samsung/arndale/arndale.c | 11 +-
board/samsung/goni/goni.c| 26 +-
board/samsung/smdk5250/exynos5-dt.c | 20 +-
board/samsung/smdk5250/smdk5250.c| 19 +-
board/samsung/smdk5420/smdk5420.c| 15 +-
board/samsung/smdkc100/smdkc100.c|5 +-
board/samsung/smdkv310/smdkv310.c| 17 +-
board/samsung/trats/trats.c | 39 +-
board/samsung/trats2/trats2.c| 74 +-
board/samsung/universal_c210/universal.c | 51 +-
drivers/gpio/s5p_gpio.c | 195 +++-
15 files changed, 2778 insertions(+), 841 deletions(-)
diff --git a/drivers/gpio/s5p_gpio.c b/drivers/gpio/s5p_gpio.c
index 11a0472..a93928a 100644
--- a/drivers/gpio/s5p_gpio.c
+++ b/drivers/gpio/s5p_gpio.c
@@ -8,11 +8,12 @@
#include common.h
#include asm/io.h
#include asm/gpio.h
+#include asm/arch-exynos/gpio.h
This is common driver, so it should be:
#include asm/arch/gpio.h
#define S5P_GPIO_GET_BANK(x) ((x S5P_GPIO_BANK_SHIFT) \
S5P_GPIO_BANK_MASK)
-#define S5P_GPIO_GET_PIN(x)(x S5P_GPIO_PIN_MASK)
+#define S5P_GPIO_GET_PIN(x)((x S5P_GPIO_PIN_MASK) % GPIO_PER_BANK)
And again...we don't need above macros, we can use now linear numbering.
+#ifdef HAVE_GENERIC_GPIO
+struct s5p_gpio_bank *s5p_gpio_get_bank(unsigned int gpio)
+{
+ const struct gpio_info *data;
+ unsigned int upto;
+ int i, count;
+
+ data = get_gpio_data();
+ count = get_bank_num();
+ for (i = upto = 0; i count;
+ i++, upto = data-max_gpio, data++) {
+ debug(i=%d, upto=%d\n, i, upto);
+ if (gpio data-max_gpio) {
+ struct s5p_gpio_bank *bank;
+ bank = (struct s5p_gpio_bank *)data-reg_addr;
+ bank += (gpio - upto) / GPIO_PER_BANK;
+ debug(gpio=%d, bank=%p\n, gpio, bank);
+ return bank;
+ }
+ }
+ return NULL;
+}
+#else
You are using exynos_gpio_get() in code but this function is not
compiled. Again please remove it.
struct s5p_gpio_bank *s5p_gpio_get_bank(unsigned gpio)
{
unsigned bank = S5P_GPIO_GET_BANK(gpio);
@@ -134,6 +252,7 @@ struct s5p_gpio_bank *s5p_gpio_get_bank(unsigned gpio)
return (struct s5p_gpio_bank *)(base + bank);
}
+#endif
Thanks
--
Przemyslaw Marczak
Samsung RD Institute Poland
Samsung Electronics
p.marc...@samsung.com
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[U-Boot] [PATCH 18/18] ARM: zynq: Extend maximum number of command arguments
15 was too small for variables stored in file on MMC. Signed-off-by: Michal Simek michal.si...@xilinx.com --- include/configs/zynq-common.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index 09d6c55..d2149b3 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -188,7 +188,7 @@ #define CONFIG_SYS_LONGHELP #define CONFIG_CLOCKS #define CONFIG_CMD_CLK -#define CONFIG_SYS_MAXARGS 15 /* max number of command args */ +#define CONFIG_SYS_MAXARGS 32 /* max number of command args */ #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ sizeof(CONFIG_SYS_PROMPT) + 16) -- 1.8.2.3 pgpfukUPs3oZC.pgp Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/2] net: zynq: Use predefined macros instead of hardcoded value
MII is used by this driver. Signed-off-by: Michal Simek michal.si...@xilinx.com --- drivers/net/zynq_gem.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c index 101489c..08056a4 100644 --- a/drivers/net/zynq_gem.c +++ b/drivers/net/zynq_gem.c @@ -338,7 +338,8 @@ static int zynq_gem_init(struct eth_device *dev, bd_t * bis) phy_detection(dev); /* interface - look at tsec */ - phydev = phy_connect(priv-bus, priv-phyaddr, dev, 0); + phydev = phy_connect(priv-bus, priv-phyaddr, dev, +PHY_INTERFACE_MODE_MII); phydev-supported = supported | ADVERTISED_Pause | ADVERTISED_Asym_Pause; -- 1.8.2.3 pgpnJRzZVaQcX.pgp Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] sf: params: Added support for Spansion S25FL512S_512K
From: Siva Durga Prasad Paladugu siva.durga.palad...@xilinx.com
Added support for Spansion chip S25FL512S_512K.
Signed-off-by: Siva Durga Prasad Paladugu siva...@xilinx.com
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
drivers/mtd/spi/sf_params.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/mtd/spi/sf_params.c b/drivers/mtd/spi/sf_params.c
index eb372b7..ac886fd 100644
--- a/drivers/mtd/spi/sf_params.c
+++ b/drivers/mtd/spi/sf_params.c
@@ -60,6 +60,7 @@ const struct spi_flash_params spi_flash_params_table[] = {
{S25FL256S_64K, 0x010219, 0x4d01,64 * 1024, 512, RD_FULL,
WR_QPP},
{S25FL512S_256K, 0x010220, 0x4d00, 256 * 1024, 256, RD_FULL,
WR_QPP},
{S25FL512S_64K, 0x010220, 0x4d01,64 * 1024, 1024, RD_FULL,
WR_QPP},
+ {S25FL512S_512K, 0x010220, 0x4f00, 256 * 1024, 256, RD_FULL,
WR_QPP},
#endif
#ifdef CONFIG_SPI_FLASH_STMICRO/* STMICRO */
{M25P10, 0x202011, 0x0, 32 * 1024, 4, 0,
0},
--
1.8.2.3
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[U-Boot] [PATCH] fat: Define MAX_CLUSTSIZE only if not defined in config
From: Siva Durga Prasad Paladugu siva.durga.palad...@xilinx.com Define MAX_CLUSTSIZE only if not defined in board specific config file as this size can be decreased to save memory in some memory constrained cases. Signed-off-by: Siva Durga Prasad Paladugu siva...@xilinx.com Signed-off-by: Michal Simek michal.si...@xilinx.com --- include/fat.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/fat.h b/include/fat.h index c8eb7cc..1213060 100644 --- a/include/fat.h +++ b/include/fat.h @@ -18,7 +18,9 @@ #define VFAT_MAXSEQ9 /* Up to 9 of 13 2-byte UTF-16 entries */ #define PREFETCH_BLOCKS2 +#ifndef MAX_CLUSTSIZE #define MAX_CLUSTSIZE 65536 +#endif #define DIRENTSPERBLOCK(mydata-sect_size / sizeof(dir_entry)) #define DIRENTSPERCLUST((mydata-clust_size * mydata-sect_size) / \ sizeof(dir_entry)) -- 1.8.2.3 pgpdL3jJrZ5E1.pgp Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] env_eeprom: Assign default environment during board_init_f
From: Siva Durga Prasad Paladugu siva.durga.palad...@xilinx.com
Assign default environment and set env valid during board_init_f
before relocation as the actual environment will be read from
eeprom later.
Signed-off-by: Siva Durga Prasad Paladugu siva...@xilinx.com
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
common/env_eeprom.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/common/env_eeprom.c b/common/env_eeprom.c
index 0db2bb6..a4020bc 100644
--- a/common/env_eeprom.c
+++ b/common/env_eeprom.c
@@ -224,6 +224,7 @@ int env_init(void)
#else
int env_init(void)
{
+#ifdef ENV_IS_EMBEDDED
ulong crc, len, new;
unsigned off;
uchar buf[64];
@@ -256,6 +257,10 @@ int env_init(void)
gd-env_addr= 0;
gd-env_valid = 0;
}
+#else
+ gd-env_addr = (ulong)default_environment[0];
+ gd-env_valid = 1;
+#endif
return 0;
}
--
1.8.2.3
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[U-Boot] [PATCH 1/2] serial: zynq: Remove sparse warnings
Warnings:
drivers/serial/serial_zynq.c:181:1: warning: symbol 'uart_zynq0_init' was not
declared. Should it be static?
drivers/serial/serial_zynq.c:181:1: warning: symbol 'uart_zynq0_setbrg' was not
declared. Should it be static?
drivers/serial/serial_zynq.c:181:1: warning: symbol 'uart_zynq0_getc' was not
declared. Should it be static?
drivers/serial/serial_zynq.c:181:1: warning: symbol 'uart_zynq0_tstc' was not
declared. Should it be static?
drivers/serial/serial_zynq.c:181:1: warning: symbol 'uart_zynq0_putc' was not
declared. Should it be static?
drivers/serial/serial_zynq.c:181:1: warning: symbol 'uart_zynq0_puts' was not
declared. Should it be static?
drivers/serial/serial_zynq.c:182:22: warning: symbol 'uart_zynq_serial0_device'
was not declared. Should it be static?
drivers/serial/serial_zynq.c:184:1: warning: symbol 'uart_zynq1_init' was not
declared. Should it be static?
drivers/serial/serial_zynq.c:184:1: warning: symbol 'uart_zynq1_setbrg' was not
declared. Should it be static?
drivers/serial/serial_zynq.c:184:1: warning: symbol 'uart_zynq1_getc' was not
declared. Should it be static?
drivers/serial/serial_zynq.c:184:1: warning: symbol 'uart_zynq1_tstc' was not
declared. Should it be static?
drivers/serial/serial_zynq.c:184:1: warning: symbol 'uart_zynq1_putc' was not
declared. Should it be static?
drivers/serial/serial_zynq.c:184:1: warning: symbol 'uart_zynq1_puts' was not
declared. Should it be static?
drivers/serial/serial_zynq.c:185:22: warning: symbol 'uart_zynq_serial1_device'
was not declared. Should it be static?
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
drivers/serial/serial_zynq.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/serial/serial_zynq.c b/drivers/serial/serial_zynq.c
index 53a8af0..3ce9a27 100644
--- a/drivers/serial/serial_zynq.c
+++ b/drivers/serial/serial_zynq.c
@@ -153,17 +153,17 @@ static int uart_zynq_serial_getc(const int port)
/* Multi serial device functions */
#define DECLARE_PSSERIAL_FUNCTIONS(port) \
- int uart_zynq##port##_init(void) \
+ static int uart_zynq##port##_init(void) \
{ return uart_zynq_serial_init(port); } \
- void uart_zynq##port##_setbrg(void) \
+ static void uart_zynq##port##_setbrg(void) \
{ return uart_zynq_serial_setbrg(port); } \
- int uart_zynq##port##_getc(void) \
+ static int uart_zynq##port##_getc(void) \
{ return uart_zynq_serial_getc(port); } \
- int uart_zynq##port##_tstc(void) \
+ static int uart_zynq##port##_tstc(void) \
{ return uart_zynq_serial_tstc(port); } \
- void uart_zynq##port##_putc(const char c) \
+ static void uart_zynq##port##_putc(const char c) \
{ uart_zynq_serial_putc(c, port); } \
- void uart_zynq##port##_puts(const char *s) \
+ static void uart_zynq##port##_puts(const char *s) \
{ uart_zynq_serial_puts(s, port); }
/* Serial device descriptor */
@@ -179,10 +179,10 @@ static int uart_zynq_serial_getc(const int port)
}
DECLARE_PSSERIAL_FUNCTIONS(0);
-struct serial_device uart_zynq_serial0_device =
+static struct serial_device uart_zynq_serial0_device =
INIT_PSSERIAL_STRUCTURE(0, ttyPS0);
DECLARE_PSSERIAL_FUNCTIONS(1);
-struct serial_device uart_zynq_serial1_device =
+static struct serial_device uart_zynq_serial1_device =
INIT_PSSERIAL_STRUCTURE(1, ttyPS1);
#ifdef CONFIG_OF_CONTROL
--
1.8.2.3
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[U-Boot] [PATCH 2/2] serial: zynq: Fix typo in suffix function name
's/zynq_serial_initalize/zynq_serial_initialize/g'
serial_initialize is used by all serial drivers.
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
drivers/serial/serial.c | 4 ++--
drivers/serial/serial_zynq.c | 2 +-
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/serial/serial.c b/drivers/serial/serial.c
index df05bde..c4fb59c 100644
--- a/drivers/serial/serial.c
+++ b/drivers/serial/serial.c
@@ -117,7 +117,7 @@ serial_initfunc(ns16550_serial_initialize);
serial_initfunc(pxa_serial_initialize);
serial_initfunc(s3c24xx_serial_initialize);
serial_initfunc(s5p_serial_initialize);
-serial_initfunc(zynq_serial_initalize);
+serial_initfunc(zynq_serial_initialize);
serial_initfunc(bfin_serial_initialize);
serial_initfunc(bfin_jtag_initialize);
serial_initfunc(mpc512x_serial_initialize);
@@ -214,7 +214,7 @@ void serial_initialize(void)
bfin_serial_initialize();
bfin_jtag_initialize();
uartlite_serial_initialize();
- zynq_serial_initalize();
+ zynq_serial_initialize();
au1x00_serial_initialize();
asc_serial_initialize();
jz_serial_initialize();
diff --git a/drivers/serial/serial_zynq.c b/drivers/serial/serial_zynq.c
index 3ce9a27..1ff27d5 100644
--- a/drivers/serial/serial_zynq.c
+++ b/drivers/serial/serial_zynq.c
@@ -223,7 +223,7 @@ __weak struct serial_device *default_serial_console(void)
}
#endif
-void zynq_serial_initalize(void)
+void zynq_serial_initialize(void)
{
serial_register(uart_zynq_serial0_device);
serial_register(uart_zynq_serial1_device);
--
1.8.2.3
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[U-Boot] [PATCH 2/2] net: zynq: Fix sparse warnings in gem
Add missing header. Warnings: drivers/net/zynq_gem.c:491:5: warning: symbol 'zynq_gem_initialize' was not declared. Should it be static? drivers/net/zynq_gem.c:542:5: warning: symbol 'zynq_gem_of_init' was not declared. Should it be static? Signed-off-by: Michal Simek michal.si...@xilinx.com --- drivers/net/zynq_gem.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c index 08056a4..3cadd23 100644 --- a/drivers/net/zynq_gem.c +++ b/drivers/net/zynq_gem.c @@ -11,6 +11,7 @@ #include common.h #include net.h +#include netdev.h #include config.h #include fdtdec.h #include libfdt.h -- 1.8.2.3 pgpZGYzdBoFIz.pgp Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] i2c: zynq: Fixed compilation errors when using DEBUG
From: Jesper B. Christensen jesper.christen...@cobham.com Signed-off-by: Jesper B. Christensen jesper.christen...@cobham.com Signed-off-by: Michal Simek michal.si...@xilinx.com --- drivers/i2c/zynq_i2c.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/i2c/zynq_i2c.c b/drivers/i2c/zynq_i2c.c index f1f6513..b3264af 100644 --- a/drivers/i2c/zynq_i2c.c +++ b/drivers/i2c/zynq_i2c.c @@ -142,7 +142,7 @@ static u32 zynq_i2c_wait(struct zynq_i2c_registers *zynq_i2c, u32 mask) break; } #ifdef DEBUG - zynq_i2c_debug_status(zynq_i2c)); + zynq_i2c_debug_status(zynq_i2c); #endif /* Clear interrupt status flags */ writel(int_status mask, zynq_i2c-interrupt_status); @@ -235,7 +235,7 @@ static int zynq_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr, clrbits_le32(zynq_i2c-control, ZYNQ_I2C_CONTROL_HOLD); #ifdef DEBUG - zynq_i2c_debug_status(); + zynq_i2c_debug_status(zynq_i2c); #endif return 0; } -- 1.8.2.3 pgpPSfuw1lsQ5.pgp Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/8] wandboard: Convert to generic board
On 22/04/2014 20:34, Fabio Estevam wrote: Enable CONFIG_SYS_GENERIC_BOARD, so that we get rid of the following warning on boot: Warning: Your board does not use generic board. Please read doc/README.generic-board and take action. Boards not upgraded by the late 2014 may break or be removed. Signed-off-by: Fabio Estevam fabio.este...@freescale.com --- include/configs/wandboard.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/configs/wandboard.h b/include/configs/wandboard.h index 6c74c72..b137d06 100644 --- a/include/configs/wandboard.h +++ b/include/configs/wandboard.h @@ -26,6 +26,8 @@ #define CONFIG_INITRD_TAG #define CONFIG_REVISION_TAG +#define CONFIG_SYS_GENERIC_BOARD + /* Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN(10 * SZ_1M) Put the patchset in my queue, it will be merged in my next iteration. Regards, Stefano -- = DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de = ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] please pull u-boot-arc master
Dear Tom, The following changes since commit adcdeacc3eda1e5949e54062aa99c299e12483be: Merge branch 'master' of git://git.denx.de/u-boot-mips (2014-04-23 11:07:11 -0400) are available in the git repository at: ssh://gu-...@git.denx.de/u-boot-arc master for you to fetch changes up to 0cdd762027340ad82fdc2bf7476e8e791529a251: axs101: bump DDR size from 256 to 512 Mb (2014-04-25 18:00:23 +0400) Alexey Brodkin (2): axs101: increase EEPROM page write delay from 32 to 64 msec axs101: bump DDR size from 256 to 512 Mb include/configs/axs101.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) -- Best regards, Alexey Brodkin ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v9 0/2] S5P: Exynos: Add GPIO numbering feature
Hi Przemyslaw Marczak, Hello, On 04/21/2014 04:25 PM, Akshay Saraswat wrote: Used a script to recheck/verify pin mapping and existing mapping appears to be fine, returning correct bank and pin values. Did ./MAKEALL -a arm and found all Exynos/S5P related boards compiled successfully. Couldn't test booting over all of them. Tested U-Boot bootup over SMDK5420, SMDK5250, Snow. Requesting maintaners to please test over affected SoCs/boards. Changes in V2: - Enabled CMD_GPIO as suggested by Simon Glass and supported same for EXYNOS5. Changes in V3: - New patch added to rename S5P GPIO definitions to S5P_GPIO. - GPIO Table added to calculate the base address of input gpio bank. Changes in V4: - To have consistent 0..n-1 GPIO numbering the banks are divided into different parts where ever they have holes in them. - Function and table to support gpio command moved to s5p-gpio driver. - Rebased on latest u-boot-samsung tree. Changes in V5: - Rebased on latest u-boot-samsung tree. - Removed Exynos5 specific code in gpio driver api to get bank. - Added #define HAVE_GENERIC_GPIO in config file to remove conditinal CPU check in gpio driver. Changes in V6: - Isolated config changes in a new patch. - Updated patches with corresponding changes for Exynos 5420. Changes in V7: - Added changes for other SoCs like Exynos 4412, 4210 etc. Changes in V8: - Changed Subject of patch 2/2 to reflect affected SoCs/boards. - Fixed arndale board compile time errors introduced due to patch-set v7. Changes in V9: - Fixed checkpatch errors. - Fixed naming error in exynos_gpio_data arrays which could be the possible reason behind data abort witnessed over Exynos4 boards. Akshay Saraswat (2): EXYNOS: Add GPIO pin numbering and rename definitions S5P: Exynos: Config: Enable Generic GPIO and CMD configs arch/arm/cpu/armv7/exynos/pinmux.c | 403 +++ arch/arm/include/asm/arch-exynos/cpu.h | 17 +- arch/arm/include/asm/arch-exynos/gpio.h | 1786 +- arch/arm/include/asm/arch-s5pc1xx/gpio.h | 941 +--- board/samsung/arndale/arndale.c | 11 +- board/samsung/goni/goni.c| 26 +- board/samsung/smdk5250/exynos5-dt.c | 20 +- board/samsung/smdk5250/smdk5250.c| 19 +- board/samsung/smdk5420/smdk5420.c| 15 +- board/samsung/smdkc100/smdkc100.c|5 +- board/samsung/smdkv310/smdkv310.c| 17 +- board/samsung/trats/trats.c | 39 +- board/samsung/trats2/trats2.c| 74 +- board/samsung/universal_c210/universal.c | 51 +- drivers/gpio/s5p_gpio.c | 195 +++- include/configs/arndale.h|1 + include/configs/exynos5-dt.h |3 + include/configs/origen.h |1 + include/configs/s5p_goni.h |5 +- include/configs/s5pc210_universal.h | 17 +- include/configs/smdkc100.h |1 + include/configs/smdkv310.h |2 + include/configs/trats.h |9 +- include/configs/trats2.h |5 +- 24 files changed, 2806 insertions(+), 857 deletions(-) I think that you missed my last few comments. You are still using exynos_gpio_get() - what for? It returns some number and next it's interpreted as gpio continuous number - but it isn't continuous. It's because each samsung board has now defined HAVE_GENERIC_GPIO, so gpio numbers are interpreted as linear. We don't need additional macro since you introduce linear numbering. Please read my last comments again. I have read your comments and replied to it. I am sorry may be I was not clear. Please look at the patch-set 2/2 again, I am not introducing I just replaced bank and pin number with sequential pin number. exynos_gpio_get() function was already there. I can't afford to remove it because I2C driver uses it and also I don't have boards to test outcomes of such changes. In opinion it would be better if the maintainer of the board could do these changes. I tried test this on trats2 device but data abort occurs at PMIC init, it's probably because exynos_gpio_get(). Please use just gpio numbering as you defined in this patchset. As far as I could understand, exynos_gpio_get still returns what it used to before this patch because we still extract bank and pin number from linear number to do the needfull. But I will definitely try to look for the bug. Thanks for the suggestion. Thank you -- Przemyslaw Marczak Samsung RD Institute Poland Samsung Electronics p.marc...@samsung.com Regards, Akshay Saraswat ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v9 1/2] S5P: Exynos: Add GPIO pin numbering and rename definitions
Hi Przemyslaw Marczak,
Hi,
On 04/21/2014 04:25 PM, Akshay Saraswat wrote:
This patch includes following changes :
* Adds gpio pin numbering support for EXYNOS SOCs.
To have consistent 0..n-1 GPIO numbering the banks are divided
into different parts where ever they have holes in them.
* Rename GPIO definitions from GPIO_... to S5P_GPIO_...
These changes were done to enable cmd_gpio for EXYNOS and
cmd_gpio has GPIO_INPUT same as s5p_gpio driver and hence
getting a error during compilation.
* Adds support for name to gpio conversion in s5p_gpio to enable
gpio command EXYNOS SoCs. Function has been added to asm/gpio.h
to decode the input gpio name to gpio number.
Example: SMDK5420 # gpio set gpa00
Signed-off-by: Leela Krishna Amudala l.kris...@samsung.com
Signed-off-by: Rajeshwari Shinde rajeshwar...@samsung.com
Signed-off-by: Akshay Saraswat aksha...@samsung.com
---
arch/arm/cpu/armv7/exynos/pinmux.c | 403 +++
arch/arm/include/asm/arch-exynos/cpu.h | 17 +-
arch/arm/include/asm/arch-exynos/gpio.h | 1786
+-
arch/arm/include/asm/arch-s5pc1xx/gpio.h | 941 +---
board/samsung/arndale/arndale.c | 11 +-
board/samsung/goni/goni.c| 26 +-
board/samsung/smdk5250/exynos5-dt.c | 20 +-
board/samsung/smdk5250/smdk5250.c| 19 +-
board/samsung/smdk5420/smdk5420.c| 15 +-
board/samsung/smdkc100/smdkc100.c|5 +-
board/samsung/smdkv310/smdkv310.c| 17 +-
board/samsung/trats/trats.c | 39 +-
board/samsung/trats2/trats2.c| 74 +-
board/samsung/universal_c210/universal.c | 51 +-
drivers/gpio/s5p_gpio.c | 195 +++-
15 files changed, 2778 insertions(+), 841 deletions(-)
diff --git a/drivers/gpio/s5p_gpio.c b/drivers/gpio/s5p_gpio.c
index 11a0472..a93928a 100644
--- a/drivers/gpio/s5p_gpio.c
+++ b/drivers/gpio/s5p_gpio.c
@@ -8,11 +8,12 @@
#include common.h
#include asm/io.h
#include asm/gpio.h
+#include asm/arch-exynos/gpio.h
This is common driver, so it should be:
#include asm/arch/gpio.h
Will fix it in the next patch-set.
#define S5P_GPIO_GET_BANK(x) ((x S5P_GPIO_BANK_SHIFT) \
S5P_GPIO_BANK_MASK)
-#define S5P_GPIO_GET_PIN(x) (x S5P_GPIO_PIN_MASK)
+#define S5P_GPIO_GET_PIN(x) ((x S5P_GPIO_PIN_MASK) % GPIO_PER_BANK)
And again...we don't need above macros, we can use now linear numbering.
Yes, you are right we don't need S5P_GPIO_GET_BANK but we are still using
S5P_GPIO_GET_PIN.
Will fix it.
+#ifdef HAVE_GENERIC_GPIO
+struct s5p_gpio_bank *s5p_gpio_get_bank(unsigned int gpio)
+{
+const struct gpio_info *data;
+unsigned int upto;
+int i, count;
+
+data = get_gpio_data();
+count = get_bank_num();
+for (i = upto = 0; i count;
+i++, upto = data-max_gpio, data++) {
+debug(i=%d, upto=%d\n, i, upto);
+if (gpio data-max_gpio) {
+struct s5p_gpio_bank *bank;
+bank = (struct s5p_gpio_bank *)data-reg_addr;
+bank += (gpio - upto) / GPIO_PER_BANK;
+debug(gpio=%d, bank=%p\n, gpio, bank);
+return bank;
+}
+}
+return NULL;
+}
+#else
You are using exynos_gpio_get() in code but this function is not
compiled. Again please remove it.
Yes, #else part is not being used, I can get rid of this.
But I can't see exynos_gpio_get() call here.
struct s5p_gpio_bank *s5p_gpio_get_bank(unsigned gpio)
{
unsigned bank = S5P_GPIO_GET_BANK(gpio);
@@ -134,6 +252,7 @@ struct s5p_gpio_bank *s5p_gpio_get_bank(unsigned gpio)
return (struct s5p_gpio_bank *)(base + bank);
}
+#endif
Thanks
--
Przemyslaw Marczak
Samsung RD Institute Poland
Samsung Electronics
p.marc...@samsung.com
Regards,
Akshay Saraswat
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[U-Boot] [PATCH] imx6: ventana: fix system-serial dt property
Fix typo in setting of system-serial property causing the prop len to be off by 1. Signed-off-by: Tim Harvey thar...@gateworks.com --- board/gateworks/gw_ventana/gw_ventana.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/gateworks/gw_ventana/gw_ventana.c b/board/gateworks/gw_ventana/gw_ventana.c index f38a777..79b3e01 100644 --- a/board/gateworks/gw_ventana/gw_ventana.c +++ b/board/gateworks/gw_ventana/gw_ventana.c @@ -1278,7 +1278,7 @@ void ft_board_setup(void *blob, bd_t *bd) /* board serial number */ fdt_setprop(blob, 0, system-serial, getenv(serial#), - strlen(getenv(serial#) + 1)); + strlen(getenv(serial#)) + 1); /* board (model contains model from device-tree) */ fdt_setprop(blob, 0, board, info-model, -- 1.8.3.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] ARM: zynq: sdhci clock frequency init question
Hi all - I noticed that in zynq_sdhci.c, responsible for initializing PS SD controller(s), host controller max clock frequency is always set to 52MHz (http://git.denx.de/?p=u-boot.git;a=blob;f=drivers/mmc/zynq_sdhci.c;h=fdce2c2c10ec85c4a291532f927eae4a0b5627c9;hb=master#l34). In cases where user is using EMIO connectivity, max clock speed is limited to 25MHz. This results in out-of-spec operation as the divider calculation logic trusts the input to add_sdhci() and does not check the SLCR itself to confirm what the IO clock to SD controller actually is. I think I saw OF/device-tree support patched in recently (I am on the 2013.4 tag); I think the right way to solve this is add capability in zynq_sdhci_init to read device-tree for 'clock-frequency' property, and use that to populate the arguments to add_sdhci() with that information, defaulting to a safe minimum (25MHz?) if no entry is found. Otherwise, I suppose a config could be added akin to 'ZYNQ_SD0_MIO'/'ZYNQ_SD1_MIO' to populate the correct minimum value. Does this sound sane? I am thinking of implementing that as a patch for ourselves internally, but I think it will be of value to the greater community as well. Thanks, Krunal ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] SPI NOR MTD's
Hi, I am new to u-boot. I have u-boot working on a custom board for the freescale i.MX6 Solo. We have SPI NOR (m25p32) and with sf probe I can see the device. I can also erase/write/read and boot my kernel from SPI NOR. However, I just can not figure out how to use MTD's. I have MTDIDS_DEFAULT nor0=m25p32.0 and I've defined MTDPARTS_DEFAULT. I just don't understand what I need to put in the MTDIDS_DEFAULT. In addition, it's obvious that there is no connection between cmd_sf and cmd_parts. With the MTDIDS_DEFAULT defined as above I get Device nor0 not found. Also. with flinfo I get nothing listed. Any help/guidance setting up MTD's on SPI NOR is greatly appreciated. Thanks, Jeff ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] spl: consolidate arch/arm/include/asm/arch-*/spl.h
On Wed, Apr 16, 2014 at 03:44:36PM +0900, Masahiro Yamada wrote:
arch/arm/include/asm/spl.h requires all SoCs to have
arch/arm/include/asm/arch-*/spl.h.
But many of them just define BOOT_DEVICE_* macros.
Those macros are used in the switch (boot_device) { ... }
statement in common/spl/spl.c.
So they should not be archtecture specific, but described as
a simpile enumeration.
This commit merge most of arch/arm/include/asm/arch-*/spl.h
into arch/arm/include/asm/spl.h.
With a little more effort, arch-zynq/spl.h and arch-socfpga/spl.h
will be merged, while I am not sure about OMAP and Exynos.
The problem is that on TI platforms these values have meaning defined by
ROM (which changes occasionally). When ROM starts us up, we get a
little bit of info that says I found and loaded you on So while
we could move towards moving BOOT_DEVICE_FOO into spl.h we'd need in
arch/arm/cpu/armv7/omap-common/boot-common.c some logic to translate
from ROM numbers to U-Boot numbers.
--
Tom
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[U-Boot] [v2] powerpc/mpc8572ds: Increase u-boot size to 768KB
U-boot image has grown and exceeded the predefined 512KB. Increasing to 768KB to align with other powerpc boards. Tested on MPC8572DS for 32- and 36-bit targets with NOR flash boot. NAND boot is not covered by this patch. Also update board maintainer for these boards. Signed-off-by: York Sun york...@freescale.com --- Change log v2: Drop changes to dlvision, io, iocon and neo. Dirk will fix them. Change subject to 8572ds only. Update maintainer name for these boards. boards.cfg |4 ++-- include/configs/MPC8572DS.h |2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/boards.cfg b/boards.cfg index ad34aa7..68bc45c 100644 --- a/boards.cfg +++ b/boards.cfg @@ -811,8 +811,8 @@ Active powerpc mpc85xx- freescale mpc8568mds Active powerpc mpc85xx- freescale mpc8569mds MPC8569MDS - - Active powerpc mpc85xx- freescale mpc8569mds MPC8569MDS_ATM MPC8569MDS:ATM - Active powerpc mpc85xx- freescale mpc8569mds MPC8569MDS_NAND MPC8569MDS:NAND - -Active powerpc mpc85xx- freescale mpc8572ds MPC8572DS- - -Active powerpc mpc85xx- freescale mpc8572ds MPC8572DS_36BIT MPC8572DS:36BIT - +Active powerpc mpc85xx- freescale mpc8572ds MPC8572DS- York Sun york...@freescale.com +Active powerpc mpc85xx- freescale mpc8572ds MPC8572DS_36BIT MPC8572DS:36BIT York Sun york...@freescale.com Active powerpc mpc85xx- freescale mpc8572ds MPC8572DS_NAND MPC8572DS:NAND - Active powerpc mpc85xx- freescale p1010rdb P1010RDB-PA_36BIT_NAND P1010RDB:P1010RDB_PA,36BIT,NAND - Active powerpc mpc85xx- freescale p1010rdb P1010RDB-PA_36BIT_NAND_SECBOOT P1010RDB:P1010RDB_PA,36BIT,NAND_SECBOOT,SECURE_BOOT - diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h index 7b63945..3a30feb 100644 --- a/include/configs/MPC8572DS.h +++ b/include/configs/MPC8572DS.h @@ -30,7 +30,7 @@ #endif #ifndef CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_TEXT_BASE 0xeff8 +#define CONFIG_SYS_TEXT_BASE 0xeff4 #endif #ifndef CONFIG_RESET_VECTOR_ADDRESS -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] SPI NOR MTD's
Hi Jeff, 2014-04-25 18:18 GMT+02:00 Jeff Horn j...@everlook.net: Hi, I am new to u-boot. I have u-boot working on a custom board for the freescale i.MX6 Solo. We have SPI NOR (m25p32) and with sf probe I can see the device. I can also erase/write/read and boot my kernel from SPI NOR. However, I just can not figure out how to use MTD's. I have MTDIDS_DEFAULT nor0=m25p32.0 and I've defined MTDPARTS_DEFAULT. I just don't understand what I need to put in the MTDIDS_DEFAULT. In addition, it's obvious that there is no connection between cmd_sf and cmd_parts. With the MTDIDS_DEFAULT defined as above I get Device nor0 not found. Also. with flinfo I get nothing listed. Any help/guidance setting up MTD's on SPI NOR is greatly appreciated. MTD with SPI flash is currently not supported. You need a MTD translation layer driver. I have an experimental driver lying around [1] if you want to try it out. You have to set MTDIDS_DEFAULT to nor0=spiBUS.CS. MTDPARTS_DEFAULT could be set to something like mtdparts=spiBUS.CS:512k(uboot),4m(kernel). Adjust BUS and CS to your board. The identifier 'spiBUS.CS' in mtdparts will also be recognized by the kernel m25p80 driver when the MTD cmdline parser is enabled. BTW: the flinfo command is for CFI flash only [1] http://git.denx.de/?p=u-boot/u-boot-mips.git;a=commitdiff;h=bb246819cdc90493dd7089eaa51b9e639765cced -- - Daniel ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [GIT PULL] u-boot-mpc83xx: add support for the ids8313 board
On Wed, Apr 23, 2014 at 07:13:27PM -0500, Kim Phillips wrote:
Hi Tom,
Please pull support for the ids8313 board:
The following changes since commit adcdeacc3eda1e5949e54062aa99c299e12483be:
Merge branch 'master' of git://git.denx.de/u-boot-mips (2014-04-23 11:07:11
-0400)
are available in the git repository at:
git://git.denx.de/u-boot-mpc83xx.git master
for you to fetch changes up to eaf8c986d36e9fadd244093b17a7fe090b0b572a:
mpc83xx: add ids8313 support (2014-04-23 19:07:54 -0500)
Heiko Schocher (3):
powerpc, ids8247: create vendor board dir ids
mpc8313, bootcount: mpc8313 has no qe muram
mpc83xx: add ids8313 support
arch/powerpc/cpu/mpc83xx/cpu.c| 2 +-
arch/powerpc/cpu/mpc83xx/fdt.c| 5 +-
board/{ = ids}/ids8247/Makefile | 0
board/{ = ids}/ids8247/ids8247.c | 0
board/ids/ids8313/Makefile| 11 +
board/ids/ids8313/ids8313.c | 208 ++
boards.cfg| 4 +-
include/configs/ids8313.h | 587
++
8 files changed, 813 insertions(+), 4 deletions(-)
rename board/{ = ids}/ids8247/Makefile (100%)
rename board/{ = ids}/ids8247/ids8247.c (100%)
create mode 100644 board/ids/ids8313/Makefile
create mode 100644 board/ids/ids8313/ids8313.c
create mode 100644 include/configs/ids8313.h
Applied to u-boot/master, thanks!
--
Tom
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Re: [U-Boot] Please pull u-boot-mpc85xx master
On Wed, Apr 23, 2014 at 03:45:05PM -0700, York Sun wrote: Tom, The following changes since commit b149c4c399b111cec1ff7505ca9fabbeeb4fe394: ARM:tegra20: Remove aes debug prints (2014-04-18 16:14:17 -0400) are available in the git repository at: git://git.denx.de/u-boot-mpc85xx.git master for you to fetch changes up to 08ad9b068afb8842df4cd559c327f54a42811a8d: ar8031: modify the config func of ar8031 to ar8021_config (2014-04-22 17:58:53 -0700) Alexander Graf (6): fdt_support: split fdt_getprop_u32_default fdt_support: Add helper function to read ranges property PPC: 85xx: Remove IVOR reset PPC: 85xx: Generalize DDR TLB mapping function PPC 85xx: Add ELF entry point PPC 85xx: Add qemu-ppce500 machine Aneesh Bansal (9): powerpc/p1010rdb: SECURE BOOT enabled for NAND powerpc/p1010rdb: SECURE BOOT- enable workaround for IFC errata A003399 powerpc/mpc8xxx: SECURE BOOT- Disable law 0 for non PBL platforms powerpc/mpc85xx: SECURE BOOT- Add secure boot target for BSC9132QDS powerpc/mpc85xx: SECURE BOOT- Add NAND secure boot target for BSC9132QDS powerpc/mpc85xx: SECURE BOOT- Add secure boot target for B4860QDS powerpc/mpc85xx: SECURE BOOT- Add secure boot target for T4240QDS and T4160QDS powerpc/mpc85xx: SECURE BOOT- Add secure boot target for T2080QDS powerpc/mpc85xx: SECURE BOOT- Add secure boot target for T1040QDS and T1040RDB Codrin Ciubotariu (2): net/phy: Fix PHY id for VSC8514 powerpc/cpu/mpc85xx: Add MAC address for layer 2 switch Haijun.Zhang (1): Powerpc/mpc8536DS: Increase SPI/SD uboot Image size to 768K Nikhil Badola (4): fsl/usb: Fix phy type for Second USB controller fsl/usb: Workaround for USB erratum-A007075 fsl/usb: Increase TXFIFOTHRESH value for usb write in T4 Rev 2.0 powerpc/mpc85xx: Add Differential SYSCLK config support T1040 Prabhakar Kushwaha (19): board/b4860qds:Slow MDC clock to comply IEEE specs in PBI config driver/mmc: fix compile warnings powerpc/T1040: add mtdparts suppport for T104xRDB and T1040QDS board/t104xrdb: Add support of CPLD powerpc/mpc85xx: Remove QE firmware copy from NAND board/t1042rdb_pi: Disable CONFIG_QE and CONFIG_U_QE powerpc/mpc85xx: Move LAW_EN define outside of config powerpc/mpc85xx: Avoid hardcoding in SPL linker script powerpc:Add support of SPL non-relocation powerpc/mpc85xx:Disable non DDR LAWs before init_law driver/ifc: define nand_spl_load_image() for SPL driver/mtd/spi:Read 8KB data chunk during u-boot load in SPL driver: Add support of image load for MMC SPI in SPL Makefile: Add support of CONFIG_SPL_FSL_PBL board/b4qds:Add support of 2 stage NAND boot-loader board/t104xrdb: Add support of NAND, SD, SPI boot for T104xRDB powerpc/mpc85xx:Avoid fix address of bootpg section powerpc/mpc85xx:Update MONITOR_LEN for 768KB u-boot size powerpc/mpc85xx:Update FM1 clock select and shift for B4420 Priyanka Jain (1): driver/net/fm/memac_phy: Initialize mdio_clock for SoCs wih FMANv3 Scott Wood (1): powerpc/85xx: Fix e6500 L2 cache stash IDs Shaohui Xie (3): powerpc/t1040rdb: added a break in switch case powerpc/t4240: updated RCW and PBI for rev2.0 powerpc/T4QDS: add two stage boot of nand/sd Shengzhou Liu (6): powerpc/t208xqds: fix nor chip selection when nand boot powerpc/T208xQDS: add mtdparts suppport powerpc/T208xRDB: add mtdparts suppport board/t208xqds: Add support of 2-stage NAND/SPI/SD boot board/t208xrdb: Add support of 2-stage NAND/SPI/SD boot board/t2080rdb: some update for t2080rdb Tang Yuantian (4): mpc85xx: Add support for the supplement configuration unit register mpc85xx/t104x: Add deep sleep framework support mpc85xx: Add deep sleep support on T1040QDS mpc85xx: Add deep sleep support on T104xRDB York Sun (5): driver/fsl_ifc: Add a function to finalize CS0 address binding driver/ddr/fsl: Add DDR4 support to Freescale DDR driver mpc85xx/T1040QDS_D4: Add DDR4 support powerpc/mpc85xx: Add workaround for erratum A007212 drivers/ddr: Fix possible out of bounds error Zhao Qiang (5): QE/FMAN: modify CONFIG_SYS_QE_FMAN_FW_ADDR to CONFIG_SYS_FMAN_FW_ADDR and CONFIG_SYS_QE_FW_ADDR QE/U-QE: Add U-QE support t1040rdb/qe: add QE support for T1040RDB T1040QDS/U-QE: Add u-qe support to t1040qds ar8031: modify the config func of ar8031 to ar8021_config vijay rai (2): powerpc/t104xrdb: Unification of T104xRDB header files powerpc/85xx: Enhance get_sys_info() to check clocking mode Makefile | 19 + README
Re: [U-Boot] please pull u-boot-arc master
On Fri, Apr 25, 2014 at 02:24:57PM +, Alexey Brodkin wrote: Dear Tom, The following changes since commit adcdeacc3eda1e5949e54062aa99c299e12483be: Merge branch 'master' of git://git.denx.de/u-boot-mips (2014-04-23 11:07:11 -0400) are available in the git repository at: ssh://gu-...@git.denx.de/u-boot-arc master Note we usually use one of the git:// URIs here :) for you to fetch changes up to 0cdd762027340ad82fdc2bf7476e8e791529a251: axs101: bump DDR size from 256 to 512 Mb (2014-04-25 18:00:23 +0400) Alexey Brodkin (2): axs101: increase EEPROM page write delay from 32 to 64 msec axs101: bump DDR size from 256 to 512 Mb include/configs/axs101.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Please pull u-boot-ppc4xx/master
On Thu, Apr 24, 2014 at 01:20:56PM +0200, Stefan Roese wrote: Hi Tom, please pull the following patch: The following changes since commit adcdeacc3eda1e5949e54062aa99c299e12483be: Merge branch 'master' of git://git.denx.de/u-boot-mips (2014-04-23 11:07:11 -0400) are available in the git repository at: git://www.denx.de/git/u-boot-ppc4xx.git master for you to fetch changes up to e634c9dc7a9f2c5a868128e14d8dbc382706e21f: ppc4xx: add support for new PMC440 revision with cleanup (2014-04-24 13:15:53 +0200) Matthias Fuchs (1): ppc4xx: add support for new PMC440 revision with cleanup board/esd/pmc440/pmc440.c | 165 -- 1 file changed, 101 insertions(+), 64 deletions(-) Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] imx: ventana: Convert to generic board
Enable CONFIG_SYS_GENERIC_BOARD on ventana. Signed-off-by: Tim Harvey thar...@gateworks.com --- include/configs/gw_ventana.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h index b984f27..335f2ff 100644 --- a/include/configs/gw_ventana.h +++ b/include/configs/gw_ventana.h @@ -24,6 +24,8 @@ #define CONFIG_SERIAL_TAG #define CONFIG_REVISION_TAG +#define CONFIG_SYS_GENERIC_BOARD + /* Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) -- 1.8.3.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] Start the deprecation process for generic board
On 03/22/2014 04:14 PM, Simon Glass wrote: We should move forward to remove the old board init code. Add a prominent message to encourage maintainers to get started on this work. Signed-off-by: Simon Glass s...@chromium.org --- Simon, How much test has been done on powerpc boards? I randomly pick one MPC8536DS and it doesn't work. I have spent hours to track the difference and I am still struggling. I understand the first one could be more work, but if you have done any, especially 85xx family, please let me know. York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] imx: ventana: add HDMI and LVDS display capability
Signed-off-by: Tim Harvey thar...@gateworks.com
---
board/gateworks/gw_ventana/gw_ventana.c | 134
include/configs/gw_ventana.h| 16
2 files changed, 150 insertions(+)
diff --git a/board/gateworks/gw_ventana/gw_ventana.c
b/board/gateworks/gw_ventana/gw_ventana.c
index 79b3e01..f5b9f90 100644
--- a/board/gateworks/gw_ventana/gw_ventana.c
+++ b/board/gateworks/gw_ventana/gw_ventana.c
@@ -12,6 +12,7 @@
#include asm/arch/imx-regs.h
#include asm/arch/iomux.h
#include asm/arch/mx6-pins.h
+#include asm/arch/mxc_hdmi.h
#include asm/arch/crm_regs.h
#include asm/arch/sys_proto.h
#include asm/gpio.h
@@ -19,6 +20,7 @@
#include asm/imx-common/mxc_i2c.h
#include asm/imx-common/boot_mode.h
#include asm/imx-common/sata.h
+#include asm/imx-common/video.h
#include jffs2/load_kernel.h
#include hwconfig.h
#include i2c.h
@@ -369,6 +371,135 @@ int board_eth_init(bd_t *bis)
return 0;
}
+#if defined(CONFIG_VIDEO_IPUV3)
+
+static void enable_hdmi(struct display_info_t const *dev)
+{
+ imx_enable_hdmi_phy();
+}
+
+static int detect_i2c(struct display_info_t const *dev)
+{
+ return ((0 == i2c_set_bus_num(dev-bus))
+
+ (0 == i2c_probe(dev-addr)));
+}
+
+static void enable_lvds(struct display_info_t const *dev)
+{
+ struct iomuxc *iomux = (struct iomuxc *)
+ IOMUXC_BASE_ADDR;
+
+ /* set CH0 data width to 24bit (IOMUXC_GPR2:5 0=18bit, 1=24bit) */
+ u32 reg = readl(iomux-gpr[2]);
+ reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT;
+ writel(reg, iomux-gpr[2]);
+
+ /* Enable Backlight */
+ imx_iomux_v3_setup_pad(MX6_PAD_SD1_CMD__GPIO1_IO18 |
+ MUX_PAD_CTRL(NO_PAD_CTRL));
+ gpio_direction_output(IMX_GPIO_NR(1, 18), 1);
+}
+
+struct display_info_t const displays[] = {{
+ /* HDMI Output */
+ .bus= -1,
+ .addr = 0,
+ .pixfmt = IPU_PIX_FMT_RGB24,
+ .detect = detect_hdmi,
+ .enable = enable_hdmi,
+ .mode = {
+ .name = HDMI,
+ .refresh= 60,
+ .xres = 1024,
+ .yres = 768,
+ .pixclock = 15385,
+ .left_margin= 220,
+ .right_margin = 40,
+ .upper_margin = 21,
+ .lower_margin = 7,
+ .hsync_len = 60,
+ .vsync_len = 10,
+ .sync = FB_SYNC_EXT,
+ .vmode = FB_VMODE_NONINTERLACED
+} }, {
+ /* Freescale MXC-LVDS1: HannStar HSD100PXN1-A00 w/ egalx_ts cont */
+ .bus= 2,
+ .addr = 0x4,
+ .pixfmt = IPU_PIX_FMT_LVDS666,
+ .detect = detect_i2c,
+ .enable = enable_lvds,
+ .mode = {
+ .name = Hannstar-XGA,
+ .refresh= 60,
+ .xres = 1024,
+ .yres = 768,
+ .pixclock = 15385,
+ .left_margin= 220,
+ .right_margin = 40,
+ .upper_margin = 21,
+ .lower_margin = 7,
+ .hsync_len = 60,
+ .vsync_len = 10,
+ .sync = FB_SYNC_EXT,
+ .vmode = FB_VMODE_NONINTERLACED
+} } };
+size_t display_count = ARRAY_SIZE(displays);
+
+static void setup_display(void)
+{
+ struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+ struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
+ int reg;
+
+ enable_ipu_clock();
+ imx_setup_hdmi();
+ /* Turn on LDB0,IPU,IPU DI0 clocks */
+ reg = __raw_readl(mxc_ccm-CCGR3);
+ reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
+ writel(reg, mxc_ccm-CCGR3);
+
+ /* set LDB0, LDB1 clk select to 011/011 */
+ reg = readl(mxc_ccm-cs2cdr);
+ reg = ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
+|MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
+ reg |= (3MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
+ |(3MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
+ writel(reg, mxc_ccm-cs2cdr);
+
+ reg = readl(mxc_ccm-cscmr2);
+ reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
+ writel(reg, mxc_ccm-cscmr2);
+
+ reg = readl(mxc_ccm-chsccdr);
+ reg |= (CHSCCDR_CLK_SEL_LDB_DI0
+ MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
+ writel(reg, mxc_ccm-chsccdr);
+
+ reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
+|IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
+|IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
+|IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
+|IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
+|IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
+|IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
+|IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
+|IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
+ writel(reg, iomux-gpr[2]);
+
+
[U-Boot] [PATCH] ARM: imx6: nitrogen6x: Enable CONFIG_SYS_GENERIC_BOARD
Signed-off-by: Eric Nelson eric.nel...@boundarydevices.com --- Note that this seems a bit premature until we have some infrastructure around DTB files in place, but we certainly don't want big hairy warning messages on our boards. Is anyone planning on pulling in at least the pinfunc and .dtsi files for i.MX? I'm not sure how much else will be useful in U-Boot. include/configs/nitrogen6x.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/configs/nitrogen6x.h b/include/configs/nitrogen6x.h index f7e7315..895f36f 100644 --- a/include/configs/nitrogen6x.h +++ b/include/configs/nitrogen6x.h @@ -24,6 +24,7 @@ #define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_INITRD_TAG #define CONFIG_REVISION_TAG +#define CONFIG_SYS_GENERIC_BOARD /* Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [RFC] RFC: convert MPC8536DS to use generic board
This patch converts MC8536DS to use generic board. This is for discussion.
Do NOT apply.
To make it work
Add #ifdef CONFIG_OF_CONTROL for reserve_fdt(), setup_fdt(), reloc_fdt().
Set initial value for gd. Powerpc SoCs use locked cache as init RAM.
Change return value for mac_read_from_eeprom() when mismatch happens to
prevent calling hang().
Signed-off-by: York Sun york...@freescale.com
---
board/freescale/common/sys_eeprom.c |2 +-
common/board_f.c| 18 +-
include/configs/MPC8536DS.h |2 ++
3 files changed, 20 insertions(+), 2 deletions(-)
diff --git a/board/freescale/common/sys_eeprom.c
b/board/freescale/common/sys_eeprom.c
index 9c18dd8..a3c37ff 100644
--- a/board/freescale/common/sys_eeprom.c
+++ b/board/freescale/common/sys_eeprom.c
@@ -447,7 +447,7 @@ int mac_read_from_eeprom(void)
crcp = (void *)e + crc_offset;
if (crc != be32_to_cpu(*crcp)) {
printf(CRC mismatch (%08x != %08x)\n, crc,
be32_to_cpu(e.crc));
- return -1;
+ return 0;
}
#ifdef CONFIG_SYS_I2C_EEPROM_NXID
diff --git a/common/board_f.c b/common/board_f.c
index f285bad..b972db8 100644
--- a/common/board_f.c
+++ b/common/board_f.c
@@ -335,6 +335,7 @@ static int setup_ram_buf(void)
}
#endif
+#ifdef CONFIG_OF_CONTROL
static int setup_fdt(void)
{
#ifdef CONFIG_OF_EMBED
@@ -354,6 +355,7 @@ static int setup_fdt(void)
(uintptr_t)gd-fdt_blob);
return 0;
}
+#endif
/* Get the top of usable RAM */
__weak ulong board_get_usable_ram_top(ulong total_size)
@@ -549,6 +551,7 @@ static int reserve_global_data(void)
return 0;
}
+#ifdef CONFIG_OF_CONTROL
static int reserve_fdt(void)
{
/*
@@ -567,6 +570,7 @@ static int reserve_fdt(void)
return 0;
}
+#endif
static int reserve_stacks(void)
{
@@ -584,7 +588,6 @@ static int reserve_stacks(void)
gd-start_addr_sp -= 16;
gd-start_addr_sp = ~0xf;
gd-irq_sp = gd-start_addr_sp;
-
/*
* Handle architecture-specific things here
* TODO(s...@chromium.org): Perhaps create arch_reserve_stack()
@@ -724,6 +727,7 @@ static int setup_dram_config(void)
return 0;
}
+#ifdef CONFIG_OF_CONTROL
static int reloc_fdt(void)
{
if (gd-new_fdt) {
@@ -733,6 +737,7 @@ static int reloc_fdt(void)
return 0;
}
+#endif
static int setup_reloc(void)
{
@@ -789,7 +794,9 @@ static init_fnc_t init_sequence_f[] = {
setup_ram_buf,
#endif
setup_mon_len,
+#ifdef CONFIG_OF_CONTROL
setup_fdt,
+#endif
trace_early_init,
#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
/* TODO: can this go into arch_cpu_init()? */
@@ -945,7 +952,9 @@ static init_fnc_t init_sequence_f[] = {
#endif
setup_machine,
reserve_global_data,
+#ifdef CONFIG_OF_CONTROL
reserve_fdt,
+#endif
reserve_stacks,
setup_dram_config,
show_dram_config,
@@ -960,7 +969,9 @@ static init_fnc_t init_sequence_f[] = {
setup_board_extra,
#endif
INIT_FUNC_WATCHDOG_RESET
+#ifdef CONFIG_OF_CONTROL
reloc_fdt,
+#endif
setup_reloc,
#if !defined(CONFIG_ARM) !defined(CONFIG_SANDBOX)
jump_to_copy,
@@ -976,6 +987,11 @@ void board_init_f(ulong boot_flags)
gd = data;
#endif
+#ifdef CONFIG_PPC
+ gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
+ __asm__ __volatile__(:::memory);
+#endif
+
/*
* Clear global data before it is accessed at debug print
* in initcall_run_list. Otherwise the debug print probably
diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h
index f15e162..c241736 100644
--- a/include/configs/MPC8536DS.h
+++ b/include/configs/MPC8536DS.h
@@ -11,6 +11,8 @@
#ifndef __CONFIG_H
#define __CONFIG_H
+#define CONFIG_SYS_GENERIC_BOARD
+
#include ../board/freescale/common/ics307_clk.h
#ifdef CONFIG_36BIT
--
1.7.9.5
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Re: [U-Boot] [v2] powerpc/mpc8572ds: Increase u-boot size to 768KB
Hello York, Am 25.04.2014 21:06, schrieb York Sun: U-boot image has grown and exceeded the predefined 512KB. Increasing to 768KB to align with other powerpc boards. Tested on MPC8572DS for 32- and 36-bit targets with NOR flash boot. NAND boot is not covered by this patch. Also update board maintainer for these boards. Signed-off-by: York Sunyork...@freescale.com --- Change log v2: Drop changes to dlvision, io, iocon and neo. Dirk will fix them. Change subject to 8572ds only. Update maintainer name for these boards. Thanks! Acked-by: Heiko Schocher h...@denx.de bye, Heiko -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] board/freescale: Move CRC32 offset in NXID v1 data format
According to AN3638, CRC of NXID v1 is at the end of the
256-byte I2C memory. The wrong CRC32 offset prevents Uboot
from reading system information from EEPROM. No NXID v0 is
being used on Freescale boards.
Signed-off-by: Ebony Zhu b45...@freescale.com
---
board/freescale/common/sys_eeprom.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/board/freescale/common/sys_eeprom.c
b/board/freescale/common/sys_eeprom.c
index 9c18dd8..1e212ad 100644
--- a/board/freescale/common/sys_eeprom.c
+++ b/board/freescale/common/sys_eeprom.c
@@ -21,7 +21,7 @@
/* some boards with non-256-bytes EEPROM have special define */
/* for MAX_NUM_PORTS in board-specific file */
#ifndef MAX_NUM_PORTS
-#define MAX_NUM_PORTS 23
+#define MAX_NUM_PORTS 16
#endif
#define NXID_VERSION 1
#endif
@@ -58,8 +58,9 @@ static struct __attribute__ ((__packed__)) eeprom {
u8 res_1[21]; /* 0x2b - 0x3f Reserved */
u8 mac_count; /* 0x40Number of MAC addresses */
u8 mac_flag; /* 0x41MAC table flags */
- u8 mac[MAX_NUM_PORTS][6]; /* 0x42 - x MAC addresses */
- u32 crc; /* x+1 CRC32 checksum */
+ u8 mac[MAX_NUM_PORTS][6]; /* 0x42 - 0xa1 MAC addresses */
+ u8 res_2[90]; /* 0xa2 - 0xfb Reserved */
+ u32 crc; /* 0xfc - 0xff CRC32 checksum */
#endif
} e;
--
1.8.1.4
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[U-Boot] Open Source Organizational Culture
Hi, I would like to request your participation in a survey on Open Source Organizational Culture, which will provide valuable insight into how Open Source projects are run, how their participants act, how they might change going forward, and how particular Open Source projects compare with one another and with traditional business cultures. The survey shouldn't take more than 10-15 minutes to complete. Some of the projects already participating in the survey include Qt, KDE, Chromium, OpenStack, OpenDaylight, FFmpeg, Go, Git, Subversion, Bazaar, LibreOffice, Perl, Python and Ruby on Rails http://bit.ly/OSOCAS2014 Why? The survey will be used as part of my thesis on Open Source Organizational Culture at BI Norwegian Business School (www.bi.no/en, or www.bi.edu), but in true Open Source spirit the raw - but anonymized - results will be open for all. So, your Open Source project will be able to massage and dissect the results any way you wish, and see how you compare with other projects out there. Up until now, most research in Open Source culture has been based on mining mailing lists to find out how people act, who they interact with, and how projects organize themselves. In this research we would rather ask the participants directly about how a project is managed and what should change for the project to be spectacularly successful. When? - The survey is open now through May 1st. Where? -- The bit.ly address above brings you to the following page https://www.surveygizmo.com/s3/1587798/osocas-2014 You can save your progress at any time and come back to the survey at a later point when you have time to finish it. Who are you? My name is Marius Storm-Olsen, and I am currently working on a thesis on Open Source Organizational Culture. I've been an active part of Open Source for years, most notably on the Qt and Git projects. Although I have my own experiences to draw on, they do not qualify for the Open Source community at large. How to help? If you want to help, feel free to send me an email with the name and website of the project, and I will go through the appropriate channels to request permission to send the survey out on their mailing list(s). If you are a prominent member of said project, feel free to forward the survey invitation directly, but please let me know so I can update that survey request overview below. You'll find a wiki containing the current survey request status here: https://github.com/mstormo/OSOCAS/wiki I do hope you can participate, and thank you for your consideration! Best regards, Marius Storm-Olsen ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] hush shell: Avoid string write overflow when entering max cmd length
console_buffer array is defined to be CONFIG_SYS_CBSIZE + 1 long, whereas the_command array only CONFIG_SYS_CBSIZE long. Subsequent use of strcpy(the_command, console_buffer) will write final \0 terminating byte outside the_command array when entering a command of max length. Signed-off-by: Kristian Otnes kotnes at cisco dot com --- common/hush.c |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/common/hush.c b/common/hush.c index df10267..5b43224 100644 --- a/common/hush.c +++ b/common/hush.c @@ -996,7 +996,7 @@ static void get_user_input(struct in_str *i) i-p = the_command; #else int n; - static char the_command[CONFIG_SYS_CBSIZE]; + static char the_command[CONFIG_SYS_CBSIZE + 1]; #ifdef CONFIG_BOOT_RETRY_TIME # ifndef CONFIG_RESET_TO_RETRY -- 1.7.10.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
