Re: [U-Boot] U-boot hangs on imx6 pci driver
Tim Harvey wrote: When enabling PCI support in u-boot my 3.14 kernel hangs somewhere during PCI init or enumeration (can't tell as uart is not up yet) Enabling earlyprintk support may help. David, on your board(s) do you have a PCIe switch as well? Not yet, but this (using a PEX8603) is planned for the near future. Dave ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/3] blackfin: spi: move spi max chip select to spi.h
Signed-off-by: Scott Jiang scott.jiang.li...@gmail.com --- arch/blackfin/include/asm/config-pre.h |3 --- arch/blackfin/include/asm/mach-common/bits/spi.h |1 + 2 files changed, 1 insertion(+), 3 deletions(-) diff --git a/arch/blackfin/include/asm/config-pre.h b/arch/blackfin/include/asm/config-pre.h index d0fd537..0ffa44c 100644 --- a/arch/blackfin/include/asm/config-pre.h +++ b/arch/blackfin/include/asm/config-pre.h @@ -73,9 +73,6 @@ static inline const char *get_bfin_boot_mode(int bfin_boot) # define BFIN_BOOT_SPI_SSEL 1 #endif -/* Define to get a GPIO CS with the Blackfin SPI controller */ -#define MAX_CTRL_CS 8 - /* There is no Blackfin/NetBSD port */ #undef CONFIG_BOOTM_NETBSD diff --git a/arch/blackfin/include/asm/mach-common/bits/spi.h b/arch/blackfin/include/asm/mach-common/bits/spi.h index 869dcb0..180cfaa 100644 --- a/arch/blackfin/include/asm/mach-common/bits/spi.h +++ b/arch/blackfin/include/asm/mach-common/bits/spi.h @@ -64,4 +64,5 @@ #define RXS0x0020 /* SPI_RDBR Data Buffer Status (Full/Empty*) */ #define TXCOL 0x0040 /* Transmit Collision Error (Corrupt Data May Have Been Sent) */ +#define MAX_CTRL_CS 7 #endif -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 3/3] spi: add common spi3 controller driver
SPI3 controller is not only used on BF609 platform. So we add a common
controller
driver and leave machine specific configuration in board drivers.
Remove obsolete spi6xx.h and select new board driver in configuration file.
Signed-off-by: Scott Jiang scott.jiang.li...@gmail.com
---
drivers/spi/Makefile |1 +
drivers/spi/adi_spi3.c | 222
.../bits/spi6xx.h = drivers/spi/adi_spi3.h| 25 +-
drivers/spi/bfin_spi6xx.c | 279 ++--
include/configs/bf609-ezkit.h |1 +
5 files changed, 260 insertions(+), 268 deletions(-)
create mode 100644 drivers/spi/adi_spi3.c
rename arch/blackfin/include/asm/mach-common/bits/spi6xx.h =
drivers/spi/adi_spi3.h (96%)
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 81b6af6..0ce6fc9 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -15,6 +15,7 @@ obj-$(CONFIG_ATMEL_DATAFLASH_SPI) += atmel_dataflash_spi.o
obj-$(CONFIG_ATMEL_SPI) += atmel_spi.o
obj-$(CONFIG_BFIN_SPI) += bfin_spi.o
obj-$(CONFIG_BFIN_SPI6XX) += bfin_spi6xx.o
+obj-$(CONFIG_ADI_SPI3) += adi_spi3.o
obj-$(CONFIG_CF_SPI) += cf_spi.o
obj-$(CONFIG_CF_QSPI) += cf_qspi.o
obj-$(CONFIG_DAVINCI_SPI) += davinci_spi.o
diff --git a/drivers/spi/adi_spi3.c b/drivers/spi/adi_spi3.c
new file mode 100644
index 000..41cd36c
--- /dev/null
+++ b/drivers/spi/adi_spi3.c
@@ -0,0 +1,222 @@
+/*
+ * Analog Devices SPI3 controller driver
+ *
+ * Copyright (c) 2014 Analog Devices Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include common.h
+#include malloc.h
+#include spi.h
+#include asm/io.h
+#include asm/gpio.h
+#include asm/clock.h
+#include adi_spi3.h
+
+#define to_adi_spi_slave(s) container_of(s, struct adi_spi_slave, slave)
+
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+ if (is_gpio_cs(cs))
+ return gpio_is_valid(gpio_cs(cs));
+ else
+ return adi_spi_cs_valid(bus, cs);
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+ struct adi_spi_slave *sdev = to_adi_spi_slave(slave);
+
+ if (is_gpio_cs(slave-cs)) {
+ unsigned int cs = gpio_cs(slave-cs);
+ gpio_set_value(cs, sdev-cs_pol);
+ } else {
+ u32 ssel;
+ ssel = readl(sdev-regs-ssel);
+ ssel |= 1 slave-cs;
+ if (sdev-cs_pol)
+ ssel |= (1 8) slave-cs;
+ else
+ ssel = ~((1 8) slave-cs);
+ writel(ssel, sdev-regs-ssel);
+ }
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+ struct adi_spi_slave *sdev = to_adi_spi_slave(slave);
+
+ if (is_gpio_cs(slave-cs)) {
+ unsigned int cs = gpio_cs(slave-cs);
+ gpio_set_value(cs, !sdev-cs_pol);
+ gpio_set_value(cs, 1);
+ } else {
+ u32 ssel;
+ ssel = readl(sdev-regs-ssel);
+ if (sdev-cs_pol)
+ ssel = ~((1 8) slave-cs);
+ else
+ ssel |= (1 8) slave-cs;
+ /* deassert cs */
+ writel(ssel, sdev-regs-ssel);
+ /* disable cs */
+ ssel = ~(1 slave-cs);
+ writel(ssel, sdev-regs-ssel);
+ }
+}
+
+void spi_init()
+{
+}
+
+void spi_set_speed(struct spi_slave *slave, uint hz)
+{
+ struct adi_spi_slave *sdev = to_adi_spi_slave(slave);
+ u32 clock;
+
+ clock = get_spi_clk() / hz;
+ if (clock)
+ clock--;
+ sdev-clock = clock;
+}
+
+struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
+ unsigned int max_hz, unsigned int mode)
+{
+ struct adi_spi_slave *sdev;
+
+ if (!spi_cs_is_valid(bus, cs))
+ return NULL;
+
+ if (max_hz get_spi_clk())
+ return NULL;
+
+ sdev = adi_spi_setup(bus, cs);
+ if (!sdev)
+ return NULL;
+
+ sdev-control = SPI_CTL_EN | SPI_CTL_MSTR;
+ if (mode SPI_CPHA)
+ sdev-control |= SPI_CTL_CPHA;
+ if (mode SPI_CPOL)
+ sdev-control |= SPI_CTL_CPOL;
+ if (mode SPI_LSB_FIRST)
+ sdev-control |= SPI_CTL_LSBF;
+ sdev-control = ~SPI_CTL_ASSEL;
+ sdev-cs_pol = mode SPI_CS_HIGH ? 1 : 0;
+ spi_set_speed(sdev-slave, max_hz);
+
+ return sdev-slave;
+}
+
+void spi_free_slave(struct spi_slave *slave)
+{
+ struct adi_spi_slave *sdev =
[U-Boot] [PATCH 2/3] blackfin: spi clock is in sysclk1 domain instead of sysclk0
Signed-off-by: Scott Jiang scott.jiang.li...@gmail.com --- arch/blackfin/include/asm/clock.h |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/blackfin/include/asm/clock.h b/arch/blackfin/include/asm/clock.h index 59d3faa..05ae03c 100644 --- a/arch/blackfin/include/asm/clock.h +++ b/arch/blackfin/include/asm/clock.h @@ -78,7 +78,7 @@ extern u_long get_sclk1(void); extern u_long get_dclk(void); # define get_uart_clk get_sclk0 # define get_i2c_clk get_sclk0 -# define get_spi_clk get_sclk0 +# define get_spi_clk get_sclk1 #else # define get_uart_clk get_sclk # define get_i2c_clk get_sclk -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [RESEND PATCH] tools: refactor HOSTLOADLIBES_* options
The tools mkimage, dumpimage, fit_info, fit_check_sign always have the common libraries to be linked, so HOSTLOADLIBES_* can be consolidated a little bit. Signed-off-by: Masahiro Yamada yamad...@jp.panasonic.com Acked-by: Simon Glass s...@chromium.org --- - Resend as a single patch with Simon's Acked tag. tools/Makefile | 19 +-- 1 file changed, 9 insertions(+), 10 deletions(-) diff --git a/tools/Makefile b/tools/Makefile index 7610557..a8c52b1 100644 --- a/tools/Makefile +++ b/tools/Makefile @@ -104,28 +104,27 @@ fit_check_sign$(SFX)-objs := $(dumpimage-mkimage-objs) fit_check_sign.o # TODO(s...@chromium.org): Is this correct on Mac OS? -# MXSImage needs LibSSL ifneq ($(CONFIG_MX23)$(CONFIG_MX28),) -HOSTLOADLIBES_dumpimage$(SFX) := -lssl -lcrypto -HOSTLOADLIBES_mkimage$(SFX) := -lssl -lcrypto -HOSTLOADLIBES_fit_info$(SFX) := -lssl -lcrypto -HOSTLOADLIBES_fit_check_sign$(SFX) := -lssl -lcrypto # Add CONFIG_MXS into host CFLAGS, so we can check whether or not register # the mxsimage support within tools/mxsimage.c . HOSTCFLAGS_mxsimage.o += -DCONFIG_MXS endif ifdef CONFIG_FIT_SIGNATURE -HOSTLOADLIBES_dumpimage$(SFX) := -lssl -lcrypto -HOSTLOADLIBES_mkimage$(SFX) := -lssl -lcrypto -HOSTLOADLIBES_fit_info$(SFX) := -lssl -lcrypto -HOSTLOADLIBES_fit_check_sign$(SFX) := -lssl -lcrypto - # This affects include/image.h, but including the board config file # is tricky, so manually define this options here. HOST_EXTRACFLAGS += -DCONFIG_FIT_SIGNATURE endif +# MXSImage needs LibSSL +ifneq ($(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_FIT_SIGNATURE),) +HOSTLOADLIBES_mkimage$(SFX) += -lssl -lcrypto +endif + +HOSTLOADLIBES_dumpimage$(SFX) := $(HOSTLOADLIBES_mkimage$(SFX)) +HOSTLOADLIBES_fit_info$(SFX) := $(HOSTLOADLIBES_mkimage$(SFX)) +HOSTLOADLIBES_fit_check_sign$(SFX) := $(HOSTLOADLIBES_mkimage$(SFX)) + hostprogs-$(CONFIG_EXYNOS5250) += mkexynosspl$(SFX) hostprogs-$(CONFIG_EXYNOS5420) += mkexynosspl$(SFX) HOSTCFLAGS_mkexynosspl$(SFX).o := -pedantic -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] sdcard with messed up partition table with FAT signature on header
Hi, Darwin On 6/5/2014 11:13 AM, Darwin Dingel wrote: Hi, I have a sdcard with a messed up partition table with a FAT signature on the header. This is readable under linux but not when I do a 'fatls' which results in Partition 1 not valid on device 0. Do you define the CONFIG_DOS_PARTITION in your board config head file (include/configs/.h)? If not defined that macro will cause above error. Best Regards, Josh Wu Before get_device_and_partition() was introduced this was still working because reading the 'fatls' will call fat_register_device(). After it fails to detect a valid partition due to the messed up partition table, it will then search the header for a FAT signature as a fallback and will continue to read it as a PBR. 'fatls' will be able to read it afterward. Unfortunately, this will now fail on the latest code. I have a patch to do the fallback check but under get_partition_info_extended(). However I am unsure if there is really a reason for the absence this FAT signature checking before failing fatls command. Do anyone have ideas on a reason for this FAT signature checking not being implemented in get_device_and_partition() (or get_partition_info_extended())? Thanks, Darwin ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] sdcard with messed up partition table with FAT signature on header
Josh Wu wrote Do you define the CONFIG_DOS_PARTITION in your board config head file (include/configs/.h)? If not defined that macro will cause above error. Yes. CONFIG_DOS_PARTITION is defined. -- View this message in context: http://u-boot.10912.n7.nabble.com/sdcard-with-messed-up-partition-table-with-FAT-signature-on-header-tp181462p181469.html Sent from the U-Boot mailing list archive at Nabble.com. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Zynq bug and fix by generic board
Hi Michal and Albert, On Wed, 4 Jun 2014 12:54:23 +0200 Michal Simek michal.si...@xilinx.com wrote: Hi Albert and Masahiro, surprisingly I have tested zynq in Tom's repo and I am getting stuck in full u-boot. I have also tried SPL with MMC and it is hanging in the same location U-Boot SPL 2014.07-rc2-00063-g3fe1a8545b55 (Jun 04 2014 - 11:57:12) mmc boot reading system.dtb spl_load_image_fat_os: error reading image system.dtb, err - -1 reading u-boot-dtb.img reading u-boot-dtb.img U-Boot 2014.07-rc2-00063-g3fe1a8545b55 (Jun 04 2014 - 11:57:12) I2C: ready Memory: ECC disabled DRAM: 1 GiB Problem is with relocation and it is not related to OF_CONTROL. Yes. I confirmed the same problem as you saw. I did git bisect and figured out the cause of the problem is the following commit: commit 41623c91b09a0c865fab41acdaff30f060f29ad6 Author: Albert ARIBAUD albert.u.b...@aribaud.net Date: Tue Apr 15 16:13:51 2014 +0200 arm: move exception handling out of start.S files Exception handling is basically identical for all ARM targets. Factorize it out of the various start.S files and into a single vectors.S file, and adjust linker scripts accordingly. Signed-off-by: Albert ARIBAUD albert.u.b...@aribaud.net I have added 3 pending patches on the top of current master next and ARM: zynq: Enable generic board for Xilinx Zynq fix the problem. That's why I think that is easier for just apply it to mainline repo because we need to apply this patch anyway. Masahiro: Can you please check if the latest u-boot is working for you? Albert: If Masahiro confirms the same issue, can I send you one more pull request with these 3 fixes? (I have also run buildman on them too) (Enabling generic board, Fix message which is caused by enabling generic board, + one fix from Masahiro regarding compilation out of tree files for SPL). Just try git revert 41623c91b0 on the u-boot/master branch. Everything will work fine. Best Regards Masahiro Yamada ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] checking from uboot
hi, I want to check the whether my ethernet, Mictor, RF interface,high speed link ,DDR from uboot.I want to do it automaticlly by uboot.ie when uboot gets loaded i want to check whether these devices are working by uboot.please tell me about the functions i have to make use of.please help. -- View this message in context: http://u-boot.10912.n7.nabble.com/checking-from-uboot-tp181470.html Sent from the U-Boot mailing list archive at Nabble.com. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Zynq bug and fix by generic board
Hi Albert and Michal,
On Wed, 4 Jun 2014 12:54:23 +0200
Michal Simek michal.si...@xilinx.com wrote:
Hi Albert and Masahiro,
surprisingly I have tested zynq in Tom's repo and
I am getting stuck in full u-boot.
I have also tried SPL with MMC and it is hanging in the same location
U-Boot SPL 2014.07-rc2-00063-g3fe1a8545b55 (Jun 04 2014 - 11:57:12)
mmc boot
reading system.dtb
spl_load_image_fat_os: error reading image system.dtb, err - -1
reading u-boot-dtb.img
reading u-boot-dtb.img
U-Boot 2014.07-rc2-00063-g3fe1a8545b55 (Jun 04 2014 - 11:57:12)
I2C: ready
Memory: ECC disabled
DRAM: 1 GiB
Problem is with relocation and it is not related to OF_CONTROL.
I have added 3 pending patches on the top of current master next
and ARM: zynq: Enable generic board for Xilinx Zynq fix the problem.
That's why I think that is easier for just apply it to mainline repo
because we need to apply this patch anyway.
Masahiro: Can you please check if the latest u-boot is working for you?
Albert: If Masahiro confirms the same issue, can I send you one more pull
request with these 3 fixes? (I have also run buildman on them too)
(Enabling generic board, Fix message which is caused by enabling generic
board,
+ one fix from Masahiro regarding compilation out of tree files for SPL).
I found how to fix the problem.
Add one line to arch/arm/cpu/armv7/zynq/u-boot.lds as follows:
--- a/arch/arm/cpu/armv7/zynq/u-boot.lds
+++ b/arch/arm/cpu/armv7/zynq/u-boot.lds
@@ -18,6 +18,7 @@ SECTIONS
.text :
{
*(.__image_copy_start)
+ *(.vectors)
CPUDIR/start.o (.text*)
*(.text*)
}
It worked on my ZC706 board.
Best Regards
Masahiro Yamada
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Re: [U-Boot] [Patch v4 2/5] ARMv8: Adjust MMU setup
On Wed, Jun 04, 2014 at 05:27:30PM +0100, York Sun wrote:
On 06/02/2014 11:01 AM, Mark Rutland wrote:
On Mon, Jun 02, 2014 at 05:06:13PM +0100, York Sun wrote:
On 06/02/2014 04:34 AM, Mark Rutland wrote:
On Thu, May 29, 2014 at 09:49:05PM +0100, York Sun wrote:
Make MMU functions reusable. Platform code can setup its own MMU tables.
What exactly does platform code need to setup its own tables for?
The general ARMv8 MMU table is not detail enough to control memory
attribute
like cache for all addresses. We have devices mapping to addresses with
different requirement for cache control.
And there are no APIs for creating device mappings rather than exporting
the raw pagetable accessors and hard-coding them differently in every
board file?
That's a good question. At this point, only two platforms are using ARMv8
code.
I am expecting FSL ARMv8 implementation will stay similar, i.e. covered by the
file I added. If that's not the case, or more ARMv8 SoCs need special MMU
table,
we then should introduce such API. Having a full function MMU API may be an
overkill for U-boot. We don't need dynamic MMU anyway.
Maybe. It just seems to me that it would be possible to pre-allocate an
empty table that we could place device (nGnRnE?) mappings in. Then all
you'd need to call from board code is a function to map a range, rather
than having to duplicate logic for creating the tables you want.
Also fix a typo of TCR_EL3_IPS_BITS in cache_v8.c.
Signed-off-by: York Sun york...@freescale.com
CC: David Feng feng...@phytium.com.cn
---
Change log:
v4: new patch, splitted from v3 2/4
Revise set_pgtable_section() to be reused by platform MMU code
Add inline function set_ttbr_tcr_mair() to be used by this and
platform mmu code
arch/arm/cpu/armv8/cache_v8.c| 49
--
arch/arm/include/asm/armv8/mmu.h | 23 ++
2 files changed, 43 insertions(+), 29 deletions(-)
diff --git a/arch/arm/cpu/armv8/cache_v8.c
b/arch/arm/cpu/armv8/cache_v8.c
index a96ecda..67dbd46 100644
--- a/arch/arm/cpu/armv8/cache_v8.c
+++ b/arch/arm/cpu/armv8/cache_v8.c
@@ -12,15 +12,14 @@
DECLARE_GLOBAL_DATA_PTR;
#ifndef CONFIG_SYS_DCACHE_OFF
-
-static void set_pgtable_section(u64 section, u64 memory_type)
+void set_pgtable_section(u64 *page_table, u64 index, u64 section,
+ u64 memory_type)
{
-u64 *page_table = (u64 *)gd-arch.tlb_addr;
u64 value;
-value = (section SECTION_SHIFT) | PMD_TYPE_SECT |
PMD_SECT_AF;
+value = section | PMD_TYPE_SECT | PMD_SECT_AF;
value |= PMD_ATTRINDX(memory_type);
-page_table[section] = value;
+page_table[index] = value;
}
/* to activate the MMU we need to set up virtual memory */
@@ -28,10 +27,13 @@ static void mmu_setup(void)
{
int i, j, el;
bd_t *bd = gd-bd;
+u64 *page_table = (u64 *)gd-arch.tlb_addr;
/* Setup an identity-mapping for all spaces */
-for (i = 0; i (PGTABLE_SIZE 3); i++)
-set_pgtable_section(i, MT_DEVICE_NGNRNE);
+for (i = 0; i (PGTABLE_SIZE 3); i++) {
+set_pgtable_section(page_table, i, i SECTION_SHIFT,
+MT_DEVICE_NGNRNE);
+}
/* Setup an identity-mapping for all RAM space */
for (i = 0; i CONFIG_NR_DRAM_BANKS; i++) {
@@ -39,36 +41,25 @@ static void mmu_setup(void)
ulong end = bd-bi_dram[i].start + bd-bi_dram[i].size;
for (j = start SECTION_SHIFT;
j end SECTION_SHIFT; j++) {
-set_pgtable_section(j, MT_NORMAL);
+set_pgtable_section(page_table, j, j
SECTION_SHIFT,
+MT_NORMAL);
}
}
/* load TTBR0 */
el = current_el();
if (el == 1) {
-asm volatile(msr ttbr0_el1, %0
- : : r (gd-arch.tlb_addr) : memory);
-asm volatile(msr tcr_el1, %0
- : : r (TCR_FLAGS | TCR_EL1_IPS_BITS)
- : memory);
-asm volatile(msr mair_el1, %0
- : : r (MEMORY_ATTRIBUTES) : memory);
+set_ttbr_tcr_mair(el, gd-arch.tlb_addr,
+ TCR_FLAGS | TCR_EL1_IPS_BITS,
+ MEMORY_ATTRIBUTES);
} else if (el == 2) {
-asm volatile(msr ttbr0_el2, %0
- : : r (gd-arch.tlb_addr) : memory);
-asm volatile(msr tcr_el2, %0
- : : r (TCR_FLAGS | TCR_EL2_IPS_BITS)
- : memory);
-
Re: [U-Boot] Zynq bug and fix by generic board
Hi,
On 06/05/2014 10:59 AM, Masahiro Yamada wrote:
Hi Albert and Michal,
On Wed, 4 Jun 2014 12:54:23 +0200
Michal Simek michal.si...@xilinx.com wrote:
Hi Albert and Masahiro,
surprisingly I have tested zynq in Tom's repo and
I am getting stuck in full u-boot.
I have also tried SPL with MMC and it is hanging in the same location
U-Boot SPL 2014.07-rc2-00063-g3fe1a8545b55 (Jun 04 2014 - 11:57:12)
mmc boot
reading system.dtb
spl_load_image_fat_os: error reading image system.dtb, err - -1
reading u-boot-dtb.img
reading u-boot-dtb.img
U-Boot 2014.07-rc2-00063-g3fe1a8545b55 (Jun 04 2014 - 11:57:12)
I2C: ready
Memory: ECC disabled
DRAM: 1 GiB
Problem is with relocation and it is not related to OF_CONTROL.
I have added 3 pending patches on the top of current master next
and ARM: zynq: Enable generic board for Xilinx Zynq fix the problem.
That's why I think that is easier for just apply it to mainline repo
because we need to apply this patch anyway.
Masahiro: Can you please check if the latest u-boot is working for you?
Albert: If Masahiro confirms the same issue, can I send you one more pull
request with these 3 fixes? (I have also run buildman on them too)
(Enabling generic board, Fix message which is caused by enabling generic
board,
+ one fix from Masahiro regarding compilation out of tree files for SPL).
I found how to fix the problem.
Add one line to arch/arm/cpu/armv7/zynq/u-boot.lds as follows:
--- a/arch/arm/cpu/armv7/zynq/u-boot.lds
+++ b/arch/arm/cpu/armv7/zynq/u-boot.lds
@@ -18,6 +18,7 @@ SECTIONS
.text :
{
*(.__image_copy_start)
+ *(.vectors)
CPUDIR/start.o (.text*)
*(.text*)
}
It worked on my ZC706 board.
Interesting that it is not needed for GENERIC_BOARD but anyway
this fix is also works for me.
Masahiro: Can you please send proper patch which Albert or Tom
can directly take? Link to origin commit sha will be also useful
to point where the problem happened.
Please add this to the patch.
Tested-by: Michal Simek mon...@monstr.eu
Thanks,
Michal
--
Michal Simek, Ing. (M.Eng), OpenPGP - KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/
Maintainer of Linux kernel - Xilinx Zynq ARM architecture
Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform
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Re: [U-Boot] U-boot hangs on imx6 pci driver
On Wed, Jun 4, 2014 at 11:30 PM, David Müller (ELSOFT AG) d.muel...@elsoft.ch wrote: Tim Harvey wrote: When enabling PCI support in u-boot my 3.14 kernel hangs somewhere during PCI init or enumeration (can't tell as uart is not up yet) Enabling earlyprintk support may help. David, This is definitely related to PCI_RST# as the delay you inserted is essentially after imx6_pcie_probe() gets the reset_gpio from OF and asserts it low. Moving the delay around I find that it must come before imx6_pcie_assert_core_reset(), specifically before IMOUX_GPR1:18 is set (phy power down request). Enabling earlyprintk to try to debug the 'hang' on my boards further I find that I hang in in imx6_pcie_link_up() during the readl(pp-dbi_base + PCIE_PHY_DEBUG_R1) which is called after setting IOMUXC_GPR12:1 to start LTSSM. If I add a udelay(55) (55us determined via trial and error) directly after setting IOMUXC_GPR12:1 I get passed 'this' hang however during pci_scan_bridge() I find that PCI_PRIMARY_BUS config dword comes back as 0x instead of 0x00010100. This appears to cause the causes the pci code to think the RC is a bridge, tries to scan behind it, and hangs (because its not a bridge and those transactions are not valid). All of this seems to indicate to me that the PLX bridge I have on my boards requires a longer minimum time to be held in reset 'before' the PCIe PHY is powered down 'if' it has already been enumerated (or something to that nature) as I only see this if I enable PCI in uboot. Why I also need the extra udelay after enabling LTSSM in this scenario I can't say. This may correlate with your findings as I believe you say you have an i210 attached to the IMX6 RC and have found an errata indicating the i210 needs a longer time in reset. Do you find that this is the case even if you disable PCI in uboot? My first thought when I read about that i210 errata you pointed out was that it wasn't an issue because we do hold reset low for 100ms in the kernel but if the issue has something to do with holding it in reset with the PHY being powered down then perhaps this explains things. Merek, you've done much more work on IMX6 link than I... any of this make sense to you? I believe you have never encountered this 100% repeatable issue on your board(s) that David and I do encounter, but you have encountered a 1% PCIe link failure rate (which I'm inclined to say is something completely different?). Regards, Tim David, on your board(s) do you have a PCIe switch as well? Not yet, but this (using a PEX8603) is planned for the near future. Dave ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] imx: sata: return failure if not IMX6Q/IMX6D
On Wed, May 7, 2014 at 10:24 PM, Tim Harvey thar...@gateworks.com wrote:
The IMX6QUAD/DUAL have SATA, but the IMX6SOLO/DL do not. Return
instead of configuring the SATA clock and GPR13 registers.
Signed-off-by: Tim Harvey thar...@gateworks.com
---
arch/arm/imx-common/sata.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/arch/arm/imx-common/sata.c b/arch/arm/imx-common/sata.c
index 2e69486..c10dd28 100644
--- a/arch/arm/imx-common/sata.c
+++ b/arch/arm/imx-common/sata.c
@@ -8,13 +8,18 @@
#include asm/arch/iomux.h
#include asm/io.h
#include asm/arch/clock.h
+#include asm/arch/sys_proto.h
int setup_sata(void)
{
struct iomuxc_base_regs *const iomuxc_regs
= (struct iomuxc_base_regs *)IOMUXC_BASE_ADDR;
+ int ret;
- int ret = enable_sata_clock();
+ if (!is_cpu_type(MXC_CPU_MX6Q) !is_cpu_type(MXC_CPU_MX6D))
+ return 1;
+
+ ret = enable_sata_clock();
if (ret)
return ret;
--
1.8.3.2
Stefano,
Any comments?
Regards,
Tim
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Re: [U-Boot] [PATCH v2] Separate EBV Socrates board from Altera Cyclone 5 board and from Virtual Target
Hi Chian, Hi guys, On Fri, 2014-05-30 at 11:41 +0200, Detlev Zundel wrote: Hi Pavel, On Wed 2014-05-28 16:29:50, Wolfgang Denk wrote: In message 20140528124910.ga24...@amd.pavel.ucw.cz you wrote: There are no differences between EBV socrates and socfpga boards, currently. Well, for one thing, the board vendor and the board name differ... I meant from current code in u-boot point of view... But as we all agree, this may change quickly and for multiple boards. Yup, some other board vendors are using different HW configuration. Some of the difference are Altera dev kit have EEPROM and using Micrel PHY for EMAC. I presume Socrates board should have their own board path such as board/socrates/socfpga. We are using a board/vendor scheme, so it should be board/ebv/socrates, but otherwise we agree. AFAICT, one solution would be to put - in that column, and do git mv board/altera/ board/socfpga/. Putting - in the vendor column just doesn't feel right. That's what mx6 did, AFAICT. I think Detlev is right here. We do have specific board vendors directories, and there are a number of reasons to keep this used (just to give one example: say a vendor wants to use a similar look and feel for the default environment settings etc. for all boards). If there is code which is identical for several (or all?) boards we should ask ourself if it really belongs into the board/ directory at all? That might be the case. It seems that current code in board/altera is SoC-specific, as it works on both Altera and EBV boards. Then we are in agreement that it does not belong below board/ ;) Within board/altera, there are 2 types of files as below: 1. HW configuration handoff files (such as pinmux_config, pll_config). Pinmux might be different as certain board might have different routing (normally to optimize the board layout and shorter PCB trace length). 2. Board specific code (socfpga_cyclone5.c) These functions include board_init, board_early_init, checkboard. I believe that the function print_cpuinfo and overwrite _console should goto arch/arm/cpu/armv7/socfpga/misc.c. I will create the patch to change this later (as I already did this at rocketboard.org). Thanks in advance! Actually.. there's nothing Altera specific in board/altera (it works on ebv just fine), so board/socfpga sounds like a better name. But I don't think such rename should be done lightly, so I still believe the patch as submitted is the best way to go. I think board/altera as such makes sense, with Altera being the vendor of that specific board. However, if there is common code there, this code should be moved out of board/ . It seems there's currently 99.99% of SoC-specific code there. What would be the right place for that code? Depends on what exactly it implements. Apart from that we can also take a look at where the code is in a Linux tree and take that as an example. After all, we want people developing the Linux kernel to also feel at home in the U-Boot sources. arch/arm/cpu/armv7/socfpga/ ? But it is not really armv7-specific. drivers/misc ? Do we need to make a soc/ directory? We have arch/arm/imx-common for example, but I'm not so sure if this is a good approach. Maybe there is not a _single_ correct place, but we have to distribute the files to multiple directories? And then... who does the move? It is not going to make merging between rocketboards.org and mainline even trickier than it already is :-(. This is a good question and we should certainly not answer it lightly. Usually we care only to a certain degree for non-mainline code, though. Blocking ourselves because of non-mainline code would allow external control which I think is not really helpful for the project. As above, I can move some common function to arch/arm/cpu/armv7/socfpga/misc.c. Sounds good. Thanks Detlev -- A statistician can have his head in an oven and his feet in ice, and he will say that on the average he feels fine. -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-40 Fax: (+49)-8142-66989-80 Email: d...@denx.de ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2] dwc_ahsata: return failure for MX6 if not IMX6Q/IMX6D
On Wed, May 7, 2014 at 10:23 PM, Tim Harvey thar...@gateworks.com wrote:
The IMX6QUAD/DUAL have SATA, but the IMX6SOLO/DL do not. Return failure
instead of attempting a memory access that results in a data abort and reset.
Signed-off-by: Tim Harvey thar...@gateworks.com
---
v2:
- remove print as this condition isn't really an error just something not
possible
---
drivers/block/dwc_ahsata.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/block/dwc_ahsata.c b/drivers/block/dwc_ahsata.c
index 3569214..15d65d7 100644
--- a/drivers/block/dwc_ahsata.c
+++ b/drivers/block/dwc_ahsata.c
@@ -17,6 +17,7 @@
#include asm/io.h
#include linux/bitops.h
#include asm/arch/clock.h
+#include asm/arch/sys_proto.h
#include dwc_ahsata.h
struct sata_port_regs {
@@ -558,6 +559,10 @@ int init_sata(int dev)
u32 linkmap;
struct ahci_probe_ent *probe_ent = NULL;
+#if defined(CONFIG_MX6)
+ if (!is_cpu_type(MXC_CPU_MX6Q) !is_cpu_type(MXC_CPU_MX6D))
+ return 1;
+#endif
if (dev 0 || dev (CONFIG_SYS_SATA_MAX_DEVICE - 1)) {
printf(The sata index %d is out of ranges\n\r, dev);
return -1;
--
1.8.3.2
Stefano,
Any comments or does anyone else need to review this?
Regards,
Tim
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[U-Boot] [PATCH] arm: zynq: fix a bug in Zynq linker script
Commit 41623c91 moved exception handlers to .vectores section
but it missed to adjust Zynq linker script.
Zynq boards hang up after relocation because _start symbol
does not point to the correct address and gd-relocaddr gets insane.
Signed-off-by: Masahiro Yamada yamad...@jp.panasonic.com
Cc: Albert ARIBAUD albert.u.b...@aribaud.net
Cc: Michal Simek mon...@monstr.eu
Tested-by: Michal Simek mon...@monstr.eu
---
arch/arm/cpu/armv7/zynq/u-boot.lds | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/cpu/armv7/zynq/u-boot.lds
b/arch/arm/cpu/armv7/zynq/u-boot.lds
index 69500a6..4dc9bb0 100644
--- a/arch/arm/cpu/armv7/zynq/u-boot.lds
+++ b/arch/arm/cpu/armv7/zynq/u-boot.lds
@@ -18,6 +18,7 @@ SECTIONS
.text :
{
*(.__image_copy_start)
+ *(.vectors)
CPUDIR/start.o (.text*)
*(.text*)
}
--
1.9.1
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Re: [U-Boot] [PATCH] imx: sata: return failure if not IMX6Q/IMX6D
Hi Tim,
On 05/06/2014 12:44, Tim Harvey wrote:
On Wed, May 7, 2014 at 10:24 PM, Tim Harvey thar...@gateworks.com wrote:
The IMX6QUAD/DUAL have SATA, but the IMX6SOLO/DL do not. Return
instead of configuring the SATA clock and GPR13 registers.
Signed-off-by: Tim Harvey thar...@gateworks.com
---
arch/arm/imx-common/sata.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/arch/arm/imx-common/sata.c b/arch/arm/imx-common/sata.c
index 2e69486..c10dd28 100644
--- a/arch/arm/imx-common/sata.c
+++ b/arch/arm/imx-common/sata.c
@@ -8,13 +8,18 @@
#include asm/arch/iomux.h
#include asm/io.h
#include asm/arch/clock.h
+#include asm/arch/sys_proto.h
int setup_sata(void)
{
struct iomuxc_base_regs *const iomuxc_regs
= (struct iomuxc_base_regs *)IOMUXC_BASE_ADDR;
+ int ret;
- int ret = enable_sata_clock();
+ if (!is_cpu_type(MXC_CPU_MX6Q) !is_cpu_type(MXC_CPU_MX6D))
+ return 1;
+
+ ret = enable_sata_clock();
if (ret)
return ret;
--
1.8.3.2
Stefano,
Any comments?
No comments. In my queue it is ready-to-be-applied. I will do it after
the whole SPL series. My plan is to apply them until the end of the week.
Best regards,
Stefano Babic
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=
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HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de
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Re: [U-Boot] (xilinx-u-boot query) Trying to run FALCON mode on zynq-microzed board.
Hi Uzair, On 06/04/2014 03:24 PM, Uzair Zaidi wrote: I am trying to run u-boot falcon mode on zynq-microzed board and i am following README-falcon. There are two methods with spl export i.e. ATAGS blob and FDT blob. I am using FDT in spl export. Is the DT blob (fdt) needs to get prepard/patched for this board (zynq-microzed)? If yes, when i run run mtdargs addip2 addtty command as given in the README-falcon, i get following error:- ## Error: mtdargs not defined is there any other option instead of run mtdargs addip2 addtty command or it is mandatory? And also i am getting confused about fdt boardsetup command, which is not working. I am not using these commands that's why I can't help you. Thanks, Michal -- Michal Simek, Ing. (M.Eng), OpenPGP - KeyID: FE3D1F91 w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/ Maintainer of Linux kernel - Xilinx Zynq ARM architecture Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform signature.asc Description: OpenPGP digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Zynq bug and fix by generic board
Hi Michal and Albert,
On Thu, 05 Jun 2014 12:12:37 +0200
Michal Simek mon...@monstr.eu wrote:
Hi,
On 06/05/2014 10:59 AM, Masahiro Yamada wrote:
Hi Albert and Michal,
On Wed, 4 Jun 2014 12:54:23 +0200
Michal Simek michal.si...@xilinx.com wrote:
Hi Albert and Masahiro,
surprisingly I have tested zynq in Tom's repo and
I am getting stuck in full u-boot.
I have also tried SPL with MMC and it is hanging in the same location
U-Boot SPL 2014.07-rc2-00063-g3fe1a8545b55 (Jun 04 2014 - 11:57:12)
mmc boot
reading system.dtb
spl_load_image_fat_os: error reading image system.dtb, err - -1
reading u-boot-dtb.img
reading u-boot-dtb.img
U-Boot 2014.07-rc2-00063-g3fe1a8545b55 (Jun 04 2014 - 11:57:12)
I2C: ready
Memory: ECC disabled
DRAM: 1 GiB
Problem is with relocation and it is not related to OF_CONTROL.
I have added 3 pending patches on the top of current master next
and ARM: zynq: Enable generic board for Xilinx Zynq fix the problem.
That's why I think that is easier for just apply it to mainline repo
because we need to apply this patch anyway.
Masahiro: Can you please check if the latest u-boot is working for you?
Albert: If Masahiro confirms the same issue, can I send you one more pull
request with these 3 fixes? (I have also run buildman on them too)
(Enabling generic board, Fix message which is caused by enabling generic
board,
+ one fix from Masahiro regarding compilation out of tree files for SPL).
I found how to fix the problem.
Add one line to arch/arm/cpu/armv7/zynq/u-boot.lds as follows:
--- a/arch/arm/cpu/armv7/zynq/u-boot.lds
+++ b/arch/arm/cpu/armv7/zynq/u-boot.lds
@@ -18,6 +18,7 @@ SECTIONS
.text :
{
*(.__image_copy_start)
+ *(.vectors)
CPUDIR/start.o (.text*)
*(.text*)
}
It worked on my ZC706 board.
Interesting that it is not needed for GENERIC_BOARD but anyway
this fix is also works for me.
I think it is working with GENERIC_BOARD by coincidence.
_start symbol should be 0x0400 (=CONFIG_SYS_TEXT_BASE)
But it is set to 0 without fixing the linker script.
Masahiro: Can you please send proper patch which Albert or Tom
can directly take? Link to origin commit sha will be also useful
to point where the problem happened.
Please add this to the patch.
Tested-by: Michal Simek mon...@monstr.eu
Done.
http://patchwork.ozlabs.org/patch/356300/
Albert,
This is a fatal bug. Please pick it up asap.
And please apply the followings as well:
http://patchwork.ozlabs.org/patch/352484/
http://patchwork.ozlabs.org/patch/352672/
They also fix the bugs you added by commit 41623c91.
Best Regards
Masahiro Yamada
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Re: [U-Boot] (xilinx-u-boot query) Trying to run FALCON mode on zynq-microzed board.
hello Michal, Thankyou for your reply. If you wanted to Falcon, how would you do it? Is there any alternative to those commands ? Are the commands really important? On Thu, Jun 5, 2014 at 4:27 PM, Michal Simek mon...@monstr.eu wrote: Hi Uzair, On 06/04/2014 03:24 PM, Uzair Zaidi wrote: I am trying to run u-boot falcon mode on zynq-microzed board and i am following README-falcon. There are two methods with spl export i.e. ATAGS blob and FDT blob. I am using FDT in spl export. Is the DT blob (fdt) needs to get prepard/patched for this board (zynq-microzed)? If yes, when i run run mtdargs addip2 addtty command as given in the README-falcon, i get following error:- ## Error: mtdargs not defined is there any other option instead of run mtdargs addip2 addtty command or it is mandatory? And also i am getting confused about fdt boardsetup command, which is not working. I am not using these commands that's why I can't help you. Thanks, Michal -- Michal Simek, Ing. (M.Eng), OpenPGP - KeyID: FE3D1F91 w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/ Maintainer of Linux kernel - Xilinx Zynq ARM architecture Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] checking from uboot
Dear andrew_, In message 1401958223509-181470.p...@n7.nabble.com you wrote: I want to check the whether my ethernet, Mictor, RF interface,high speed link ,DDR from uboot.I want to do it automaticlly by uboot.ie when uboot gets loaded i want to check whether these devices are working by uboot.please tell me about the functions i have to make use of.please help. That would be a Power On Self Test (POST), so chekc the code in the post/ directory and read doc/README.POST Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de When a man sits with a pretty girl for an hour, it seems like a minute. But let him sit on a hot stove for a minute -- and it's lon- ger than any hour. That's relativity. -- Albert Einstein ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] checking from uboot
Dear CYRIL P. JOY, please keep the mailing list on Cc: In message caev-wwvx3hc167z4gnu0oz2u0b9ayryrrzt30ews2dcxrtu...@mail.gmail.com you wrote: Thank you very much for the quick reply.I checked the code and i understood the checking of DDR,I2C and ETHERNET.but i didnt find any checks related to Mictor,RF interface and high speed link.Do you have any idea about the checking of these components.thanks in advance. You will have to implement any additional tests you need yourself (or hire someone to do that for you). Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de This is now. Later is later. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] Fwd: checking from uboot
-- Forwarded message -- From: CYRIL P. JOY joycyr...@gmail.com Date: Thu, Jun 5, 2014 at 6:01 PM Subject: Re: [U-Boot] checking from uboot To: Wolfgang Denk w...@denx.de Dear Wolfgang, Thank you very much for the quick reply.I checked the code and i understood the checking of DDR,I2C and ETHERNET.but i didnt find any checks related to Mictor,RF interface and high speed link.Do you have any idea about the checking of these components.thanks in advance. On Thu, Jun 5, 2014 at 5:14 PM, Wolfgang Denk w...@denx.de wrote: Dear andrew_, In message 1401958223509-181470.p...@n7.nabble.com you wrote: I want to check the whether my ethernet, Mictor, RF interface,high speed link ,DDR from uboot.I want to do it automaticlly by uboot.ie when uboot gets loaded i want to check whether these devices are working by uboot.please tell me about the functions i have to make use of.please help. That would be a Power On Self Test (POST), so chekc the code in the post/ directory and read doc/README.POST Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de When a man sits with a pretty girl for an hour, it seems like a minute. But let him sit on a hot stove for a minute -- and it's lon- ger than any hour. That's relativity. -- Albert Einstein ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] checking from uboot
any idea about the inbuilt supporting functions for md and mw command in uboot code.like the i2c probe.thanks. On Thu, Jun 5, 2014 at 6:09 PM, Wolfgang Denk w...@denx.de wrote: Dear CYRIL P. JOY, please keep the mailing list on Cc: In message caev-wwvx3hc167z4gnu0oz2u0b9ayryrrzt30ews2dcxrtu...@mail.gmail.com you wrote: Thank you very much for the quick reply.I checked the code and i understood the checking of DDR,I2C and ETHERNET.but i didnt find any checks related to Mictor,RF interface and high speed link.Do you have any idea about the checking of these components.thanks in advance. You will have to implement any additional tests you need yourself (or hire someone to do that for you). Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de This is now. Later is later. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Building under Cygwin - -ansi flag?
Hi Jeroen, On Thu, May 22, 2014 at 9:27 PM, Jeroen Hofstee dasub...@myspectrum.nl wrote: Hello Vasili, On wo, 2014-05-21 at 11:50 +0300, Vasili Galka wrote: This pattern is a result of the original decision from 2004 to prioritize the host include paths over the paths from U-Boot tree. any reference? This decision is a part of the above mentioned commit: e1a3f6b (July 2004) I don't know how much the original committer was aware of its long term implications. If the only valid reason is Fix host tools building in Cygwin environment as mentioned in the original commit, then I am all in favor of dropping it and finding a decent solution for cygwin. I see this happening again and again with different headers in the future. So here comes the question, is it really the right thing prioritize the include paths this way? Why do host paths MUST come first? I'll try reverting this locally and looking what breaks and what alternative solutions exist. I have no idea why it is the way it is, but keep in mind that e.g. stdio headers in u-boot is quite something different then stdio for the target userland. Sure. I'll keep it in mind while I'm designing a solution here. I'm afraid there is no easy way to fix it though. This is easier than it sounds. U-boot is build with -nostdinc for the binary itself. And it tries to get the compiler related includes back with isystem $(shell $(CC) -print-file-name=include. (and the printf declaration and friends are actually in common.h for the loader, which makes it even harder to do it wrong by accident). Can you check what arm-none-eabi-gcc -print-file-name=include returns on cygwin? mmm, this one might be also be a challenge for cygwin: dirname `arm-none-eabi-gcc -print-libgcc-file-name`, but you will likely get linker errors if that contains spaces / backslashes or simply fails. But perhaps even easier, can you post the problems you encounter if you remove the idirafter. Likely easier then guessing what can go wrong in a cygwin build. Regards, Jeroen Let's suppose there is an application in tools directory that requires both libfdt_env.h (from uboot tree) and errno.h (from host environment). However, as both headers exist at both places, in the uboot tree and on the host environment, there is no way to solve this just by altering the include paths order. For any reshuffling both headers will be taken either from uboot or from host - which is undesired. I can only think of one bulletproof solution that would fix the above problem. Unfortunately it's conceptual and requires much work: * Currently, almost all include derectives in in uboot code use style. I propose to modify this concept. * For each #include directive the developer shall decide from where the header file is obtained - U-Boot source tree or the host environment. * Depending on that, shall be used only for headers from U-Boot tree, shall be used only for all other (host provided in tools folder) * The -iquote compiler flag can be used for adding search paths. The -I flag for adding paths. Of course that's just a draft of the idea. What do you think? Best, Vasili ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] checking from uboot
Dear CYRIL P. JOY, please don't top post / full quote. In message CAEv-wWu_Arqucx2wSyQ=YK=6fs0f9f+pa3ytdufrung2gan...@mail.gmail.com you wrote: any idea about the inbuilt supporting functions for md and mw command in uboot code.like the i2c probe.thanks. I don't understand this question. Content-Type: text/html; charset=UTF-8 Content-Transfer-Encoding: quoted-printable And please, do not post HTML. Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de Testing can show the presense of bugs, but not their absence. -- Edsger Dijkstra ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] powerpc/mpc85xx: Removed support for G4060
G4060 has no PA cores, hence removing its support.
Signed-off-by: Sandeep Singh sand...@freescale.com
Change-Id: Ia9b8760dec9bb890ee87c8b6c947d693aa884b33
Reviewed-on: http://git.am.freescale.net:8181/3808
Reviewed-by: Aggrwal Poonam-B10812 poonam.aggr...@freescale.com
Tested-by: Review Code-CDREVIEW cdrev...@freescale.com
Reviewed-by: York Sun york...@freescale.com
(cherry picked from commit bb94857b91955321afb0c6b836eb79f134600443)
Reviewed-on: http://git.am.freescale.net:8181/7156
Reviewed-by: Yusong Sun york...@freescale.com
(cherry picked from commit baa1bfe297e200fb9823068fa5f0f726621c3c06)
---
arch/powerpc/cpu/mpc8xxx/cpu.c |1 -
arch/powerpc/include/asm/processor.h |1 -
2 files changed, 0 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/cpu/mpc8xxx/cpu.c b/arch/powerpc/cpu/mpc8xxx/cpu.c
index 35795c4..8451cb2 100644
--- a/arch/powerpc/cpu/mpc8xxx/cpu.c
+++ b/arch/powerpc/cpu/mpc8xxx/cpu.c
@@ -64,7 +64,6 @@ static struct cpu_type cpu_type_list[] = {
CPU_TYPE_ENTRY(T4160, T4160, 0),
CPU_TYPE_ENTRY(B4860, B4860, 0),
CPU_TYPE_ENTRY(G4860, G4860, 0),
- CPU_TYPE_ENTRY(G4060, G4060, 0),
CPU_TYPE_ENTRY(B4440, B4440, 0),
CPU_TYPE_ENTRY(G4440, G4440, 0),
CPU_TYPE_ENTRY(B4420, B4420, 0),
diff --git a/arch/powerpc/include/asm/processor.h
b/arch/powerpc/include/asm/processor.h
index 50c9d0a..698622a 100644
--- a/arch/powerpc/include/asm/processor.h
+++ b/arch/powerpc/include/asm/processor.h
@@ -1118,7 +1118,6 @@
#define SVR_C293 0x850030
#define SVR_B4860 0X868000
#define SVR_G4860 0x868001
-#define SVR_G4060 0x868003
#define SVR_B4440 0x868100
#define SVR_G4440 0x868101
#define SVR_B4420 0x868102
--
1.7.6.GIT
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[U-Boot] [PATCH] powerpc/mpc85xx: Add workaround to enable TDM on T1040
This is a workaround for 32 bit hardware limitation of TDM.
T1040 has 36 bit physical addressing, TDM DMAC register
are 32 bit wide but need to store address of CCSR space
which lies beyond 32 bit address range. This workaround
creats a LAW to enable access of TDM DMA to CCSR by
mapping CCSR to overlap with DDR.
A hole of 16M is created in memory using device tree. This
workaround law is set only if tdm is defined in hwconfig.
Also disable POST tests and add LIODN for TDM
Signed-off-by: Sandeep Singh sand...@freescale.com
Cc: York Sun york...@freescale.com
---
arch/powerpc/cpu/mpc85xx/cpu_init.c | 29 +
arch/powerpc/cpu/mpc85xx/fdt.c| 26 ++
arch/powerpc/cpu/mpc85xx/t1040_ids.c |1 +
arch/powerpc/include/asm/fsl_law.h|1 +
arch/powerpc/include/asm/fsl_liodn.h |4
arch/powerpc/include/asm/immap_85xx.h |4 +++-
include/configs/T1040QDS.h|6 ++
include/configs/T104xRDB.h|6 ++
8 files changed, 76 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c
b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index d6cf885..78316a6 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -225,6 +225,32 @@ static void disable_cpc_sram(void)
}
#endif
+#if defined(T1040_TDM_QUIRK_CCSR_BASE)
+#ifdef CONFIG_POST
+#error POST memory test cannot be enabled with TDM
+#endif
+static void enable_tdm_law(void)
+{
+ int ret;
+ char buffer[HWCONFIG_BUFFER_SIZE] = {0};
+ int tdm_hwconfig_enabled = 0;
+
+ /*
+* Extract hwconfig from environment since environment
+* is not setup properly yet. Search for tdm entry in
+* hwconfig.
+*/
+ ret = getenv_f(hwconfig, buffer, sizeof(buffer));
+ if (ret 0) {
+ tdm_hwconfig_enabled = hwconfig_f(tdm, buffer);
+ /* If tdm is defined in hwconfig, set law for tdm workaround */
+ if (tdm_hwconfig_enabled)
+ set_next_law(T1040_TDM_QUIRK_CCSR_BASE, LAW_SIZE_16M,
+LAW_TRGT_IF_CCSR);
+ }
+}
+#endif
+
static void enable_cpc(void)
{
int i;
@@ -729,6 +755,9 @@ skip_l2:
disable_cpc_sram();
#endif
enable_cpc();
+#if defined(T1040_TDM_QUIRK_CCSR_BASE)
+ enable_tdm_law();
+#endif
#ifndef CONFIG_SYS_FSL_NO_SERDES
/* needs to be in ram since code uses global static vars */
diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c
index ed80a84..85dfa5b 100644
--- a/arch/powerpc/cpu/mpc85xx/fdt.c
+++ b/arch/powerpc/cpu/mpc85xx/fdt.c
@@ -14,6 +14,7 @@
#include linux/ctype.h
#include asm/io.h
#include asm/fsl_portals.h
+#include hwconfig.h
#ifdef CONFIG_FSL_ESDHC
#include fsl_esdhc.h
#endif
@@ -35,6 +36,11 @@ void ft_fixup_cpu(void *blob, u64 memory_limit)
u32 bootpg = determine_mp_bootpg(NULL);
u32 id = get_my_id();
const char *enable_method;
+#if defined(T1040_TDM_QUIRK_CCSR_BASE)
+ int ret;
+ int tdm_hwconfig_enabled = 0;
+ char buffer[HWCONFIG_BUFFER_SIZE] = {0};
+#endif
off = fdt_node_offset_by_prop_value(blob, -1, device_type, cpu, 4);
while (off != -FDT_ERR_NOTFOUND) {
@@ -77,6 +83,26 @@ void ft_fixup_cpu(void *blob, u64 memory_limit)
device_type, cpu, 4);
}
+#if defined(T1040_TDM_QUIRK_CCSR_BASE)
+#defineCONFIG_MEM_HOLE_16M 0x100
+ /*
+* Extract hwconfig from environment.
+* Search for tdm entry in hwconfig.
+*/
+ ret = getenv_f(hwconfig, buffer, sizeof(buffer));
+ if (ret 0)
+ tdm_hwconfig_enabled = hwconfig_f(tdm, buffer);
+
+ /* Reserve the memory hole created by TDM LAW, so OSes dont use it */
+ if (tdm_hwconfig_enabled) {
+ off = fdt_add_mem_rsv(blob, T1040_TDM_QUIRK_CCSR_BASE,
+ CONFIG_MEM_HOLE_16M);
+ if (off 0)
+ printf(Failed to reserve memory for tdm: %s\n,
+ fdt_strerror(off));
+ }
+#endif
+
/* Reserve the boot page so OSes dont use it */
if ((u64)bootpg memory_limit) {
off = fdt_add_mem_rsv(blob, bootpg, (u64)4096);
diff --git a/arch/powerpc/cpu/mpc85xx/t1040_ids.c
b/arch/powerpc/cpu/mpc85xx/t1040_ids.c
index 1034cd4..a5dfb81 100644
--- a/arch/powerpc/cpu/mpc85xx/t1040_ids.c
+++ b/arch/powerpc/cpu/mpc85xx/t1040_ids.c
@@ -47,6 +47,7 @@ struct liodn_id_table liodn_tbl[] = {
/* SET_NEXUS_LIODN(557), -- not yet implemented */
SET_QE_LIODN(559),
+ SET_TDM_LIODN(560),
};
int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl);
diff --git a/arch/powerpc/include/asm/fsl_law.h
b/arch/powerpc/include/asm/fsl_law.h
index 37d3a22..3b50487 100644
--- a/arch/powerpc/include/asm/fsl_law.h
+++ b/arch/powerpc/include/asm/fsl_law.h
@@
[U-Boot] [PATCH] powerpc/mpc85xx: Removed support for G4060
G4060 has no PA cores, hence removing its support.
Signed-off-by: Sandeep Singh sand...@freescale.com
Change-Id: Ia9b8760dec9bb890ee87c8b6c947d693aa884b33
Reviewed-on: http://git.am.freescale.net:8181/3808
Reviewed-by: Aggrwal Poonam-B10812 poonam.aggr...@freescale.com
Tested-by: Review Code-CDREVIEW cdrev...@freescale.com
Reviewed-by: York Sun york...@freescale.com
(cherry picked from commit bb94857b91955321afb0c6b836eb79f134600443)
Reviewed-on: http://git.am.freescale.net:8181/7156
Reviewed-by: Yusong Sun york...@freescale.com
(cherry picked from commit baa1bfe297e200fb9823068fa5f0f726621c3c06)
---
arch/powerpc/cpu/mpc8xxx/cpu.c |1 -
arch/powerpc/include/asm/processor.h |1 -
2 files changed, 0 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/cpu/mpc8xxx/cpu.c b/arch/powerpc/cpu/mpc8xxx/cpu.c
index 35795c4..8451cb2 100644
--- a/arch/powerpc/cpu/mpc8xxx/cpu.c
+++ b/arch/powerpc/cpu/mpc8xxx/cpu.c
@@ -64,7 +64,6 @@ static struct cpu_type cpu_type_list[] = {
CPU_TYPE_ENTRY(T4160, T4160, 0),
CPU_TYPE_ENTRY(B4860, B4860, 0),
CPU_TYPE_ENTRY(G4860, G4860, 0),
- CPU_TYPE_ENTRY(G4060, G4060, 0),
CPU_TYPE_ENTRY(B4440, B4440, 0),
CPU_TYPE_ENTRY(G4440, G4440, 0),
CPU_TYPE_ENTRY(B4420, B4420, 0),
diff --git a/arch/powerpc/include/asm/processor.h
b/arch/powerpc/include/asm/processor.h
index 50c9d0a..698622a 100644
--- a/arch/powerpc/include/asm/processor.h
+++ b/arch/powerpc/include/asm/processor.h
@@ -1118,7 +1118,6 @@
#define SVR_C293 0x850030
#define SVR_B4860 0X868000
#define SVR_G4860 0x868001
-#define SVR_G4060 0x868003
#define SVR_B4440 0x868100
#define SVR_G4440 0x868101
#define SVR_B4420 0x868102
--
1.7.6.GIT
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Re: [U-Boot] [Patch v4 2/5] ARMv8: Adjust MMU setup
On 06/05/2014 03:09 AM, Mark Rutland wrote:
On Wed, Jun 04, 2014 at 05:27:30PM +0100, York Sun wrote:
On 06/02/2014 11:01 AM, Mark Rutland wrote:
On Mon, Jun 02, 2014 at 05:06:13PM +0100, York Sun wrote:
On 06/02/2014 04:34 AM, Mark Rutland wrote:
On Thu, May 29, 2014 at 09:49:05PM +0100, York Sun wrote:
Make MMU functions reusable. Platform code can setup its own MMU tables.
What exactly does platform code need to setup its own tables for?
The general ARMv8 MMU table is not detail enough to control memory
attribute
like cache for all addresses. We have devices mapping to addresses with
different requirement for cache control.
And there are no APIs for creating device mappings rather than exporting
the raw pagetable accessors and hard-coding them differently in every
board file?
That's a good question. At this point, only two platforms are using ARMv8
code.
I am expecting FSL ARMv8 implementation will stay similar, i.e. covered by
the
file I added. If that's not the case, or more ARMv8 SoCs need special MMU
table,
we then should introduce such API. Having a full function MMU API may be an
overkill for U-boot. We don't need dynamic MMU anyway.
Maybe. It just seems to me that it would be possible to pre-allocate an
empty table that we could place device (nGnRnE?) mappings in. Then all
you'd need to call from board code is a function to map a range, rather
than having to duplicate logic for creating the tables you want.
It sounds good, but not the case. For the three level tables I am using (level0,
level1, level2), I don't have level2 table for every address, that will be too
many. Instead, I have a lot of blocks for level1. When I need some fine control
within a level1 block range, I have to create a new level2 table. It is doable,
but I will hold on that if I can use static table.
Also fix a typo of TCR_EL3_IPS_BITS in cache_v8.c.
Signed-off-by: York Sun york...@freescale.com
CC: David Feng feng...@phytium.com.cn
---
Change log:
v4: new patch, splitted from v3 2/4
Revise set_pgtable_section() to be reused by platform MMU code
Add inline function set_ttbr_tcr_mair() to be used by this and
platform mmu code
arch/arm/cpu/armv8/cache_v8.c| 49
--
arch/arm/include/asm/armv8/mmu.h | 23 ++
2 files changed, 43 insertions(+), 29 deletions(-)
diff --git a/arch/arm/cpu/armv8/cache_v8.c
b/arch/arm/cpu/armv8/cache_v8.c
index a96ecda..67dbd46 100644
--- a/arch/arm/cpu/armv8/cache_v8.c
+++ b/arch/arm/cpu/armv8/cache_v8.c
@@ -12,15 +12,14 @@
DECLARE_GLOBAL_DATA_PTR;
#ifndef CONFIG_SYS_DCACHE_OFF
-
-static void set_pgtable_section(u64 section, u64 memory_type)
+void set_pgtable_section(u64 *page_table, u64 index, u64 section,
+ u64 memory_type)
{
-u64 *page_table = (u64 *)gd-arch.tlb_addr;
u64 value;
-value = (section SECTION_SHIFT) | PMD_TYPE_SECT |
PMD_SECT_AF;
+value = section | PMD_TYPE_SECT | PMD_SECT_AF;
value |= PMD_ATTRINDX(memory_type);
-page_table[section] = value;
+page_table[index] = value;
}
/* to activate the MMU we need to set up virtual memory */
@@ -28,10 +27,13 @@ static void mmu_setup(void)
{
int i, j, el;
bd_t *bd = gd-bd;
+u64 *page_table = (u64 *)gd-arch.tlb_addr;
/* Setup an identity-mapping for all spaces */
-for (i = 0; i (PGTABLE_SIZE 3); i++)
-set_pgtable_section(i, MT_DEVICE_NGNRNE);
+for (i = 0; i (PGTABLE_SIZE 3); i++) {
+set_pgtable_section(page_table, i, i SECTION_SHIFT,
+MT_DEVICE_NGNRNE);
+}
/* Setup an identity-mapping for all RAM space */
for (i = 0; i CONFIG_NR_DRAM_BANKS; i++) {
@@ -39,36 +41,25 @@ static void mmu_setup(void)
ulong end = bd-bi_dram[i].start + bd-bi_dram[i].size;
for (j = start SECTION_SHIFT;
j end SECTION_SHIFT; j++) {
-set_pgtable_section(j, MT_NORMAL);
+set_pgtable_section(page_table, j, j
SECTION_SHIFT,
+MT_NORMAL);
}
}
/* load TTBR0 */
el = current_el();
if (el == 1) {
-asm volatile(msr ttbr0_el1, %0
- : : r (gd-arch.tlb_addr) : memory);
-asm volatile(msr tcr_el1, %0
- : : r (TCR_FLAGS | TCR_EL1_IPS_BITS)
- : memory);
-asm volatile(msr mair_el1, %0
- : : r (MEMORY_ATTRIBUTES) : memory);
+set_ttbr_tcr_mair(el, gd-arch.tlb_addr,
+ TCR_FLAGS | TCR_EL1_IPS_BITS,
+
[U-Boot] [PATCH 1/4] am43xx: Only read the MPU frequency bits of CTRL_DEV_ATTR
Signed-off-by: Tom Rini tr...@ti.com
---
board/ti/am43xx/board.c |5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c
index d358ad8..e05a50b 100644
--- a/board/ti/am43xx/board.c
+++ b/board/ti/am43xx/board.c
@@ -464,7 +464,10 @@ static u32 get_sys_clk_index(void)
static int get_opp_offset(int max_off, int min_off)
{
struct ctrl_stat *ctrl = (struct ctrl_stat *)CTRL_BASE;
- int opp = readl(ctrl-dev_attr), offset, i;
+ int opp, offset, i;
+
+ /* Bits 0:11 are defined to be the MPU_MAX_FREQ */
+ opp = readl(ctrl-dev_attr) ~0xF000;
for (i = max_off; i = min_off; i--) {
offset = opp (1 i);
--
1.7.9.5
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[U-Boot] [PATCH 2/4] arm:am33xx: Add a scale_vcores() hook
Similar to OMAP4/5 we need to scale the voltage up prior to changing the
clock frequencies up higher. Add a similar hook to start with.
Signed-off-by: Tom Rini tr...@ti.com
---
arch/arm/cpu/armv7/am33xx/clock.c| 11 +++
arch/arm/include/asm/arch-am33xx/clock.h |1 +
2 files changed, 12 insertions(+)
diff --git a/arch/arm/cpu/armv7/am33xx/clock.c
b/arch/arm/cpu/armv7/am33xx/clock.c
index 0672798..ec7d468 100644
--- a/arch/arm/cpu/armv7/am33xx/clock.c
+++ b/arch/arm/cpu/armv7/am33xx/clock.c
@@ -170,8 +170,19 @@ void do_enable_clocks(u32 *const *clk_domains,
};
}
+/*
+ * Before scaling up the clocks we need to have the PMIC scale up the
+ * voltages first. This will be dependent on which PMIC is in use
+ * and in some cases we may not be scaling things up at all and thus not
+ * need to do anything here.
+ */
+__weak void scale_vcores(void)
+{
+}
+
void prcm_init()
{
enable_basic_clocks();
+ scale_vcores();
setup_dplls();
}
diff --git a/arch/arm/include/asm/arch-am33xx/clock.h
b/arch/arm/include/asm/arch-am33xx/clock.h
index f00fad3..4af6b57 100644
--- a/arch/arm/include/asm/arch-am33xx/clock.h
+++ b/arch/arm/include/asm/arch-am33xx/clock.h
@@ -107,6 +107,7 @@ const struct dpll_params *get_dpll_mpu_params(void);
const struct dpll_params *get_dpll_core_params(void);
const struct dpll_params *get_dpll_per_params(void);
const struct dpll_params *get_dpll_ddr_params(void);
+void scale_vcores(void);
void do_setup_dpll(const struct dpll_regs *, const struct dpll_params *);
void prcm_init(void);
void enable_basic_clocks(void);
--
1.7.9.5
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[U-Boot] [PATCH 3/4] power: Add support for the TPS65218 PMIC
Add a driver for the TPS65218 PMIC which is used by TI AM43xx SoCs and
may be used by TI AM335x SoCs.
Signed-off-by: Tom Rini tr...@ti.com
---
drivers/power/pmic/Makefile|1 +
drivers/power/pmic/pmic_tps65218.c | 97
include/power/tps65218.h | 63 +++
3 files changed, 161 insertions(+)
create mode 100644 drivers/power/pmic/pmic_tps65218.c
create mode 100644 include/power/tps65218.h
diff --git a/drivers/power/pmic/Makefile b/drivers/power/pmic/Makefile
index 920bbdc..192df50 100644
--- a/drivers/power/pmic/Makefile
+++ b/drivers/power/pmic/Makefile
@@ -12,4 +12,5 @@ obj-$(CONFIG_POWER_MUIC_MAX8997) += muic_max8997.o
obj-$(CONFIG_POWER_MAX77686) += pmic_max77686.o
obj-$(CONFIG_POWER_PFUZE100) += pmic_pfuze100.o
obj-$(CONFIG_POWER_TPS65217) += pmic_tps65217.o
+obj-$(CONFIG_POWER_TPS65218) += pmic_tps65218.o
obj-$(CONFIG_POWER_TPS65910) += pmic_tps65910.o
diff --git a/drivers/power/pmic/pmic_tps65218.c
b/drivers/power/pmic/pmic_tps65218.c
new file mode 100644
index 000..0952456
--- /dev/null
+++ b/drivers/power/pmic/pmic_tps65218.c
@@ -0,0 +1,97 @@
+/*
+ * (C) Copyright 2011-2013
+ * Texas Instruments, www.ti.com
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include i2c.h
+#include power/tps65218.h
+
+/**
+ * tps65218_reg_write() - Generic function that can write a TPS65218 PMIC
+ *register or bit field regardless of protection
+ *level.
+ *
+ * @prot_level: Register password protection. Use
+ *TPS65218_PROT_LEVEL_NONE,
+ *TPS65218_PROT_LEVEL_1 or TPS65218_PROT_LEVEL_2
+ * @dest_reg:Register address to write.
+ * @dest_val:Value to write.
+ * @mask:Bit mask (8 bits) to be applied. Function will only
+ *change bits that are set in the bit mask.
+ *
+ * @return: 0 for success, not 0 on failure, as per the i2c API
+ */
+int tps65218_reg_write(uchar prot_level, uchar dest_reg, uchar dest_val,
+ uchar mask)
+{
+ uchar read_val;
+ uchar xor_reg;
+ int ret;
+
+ /*
+* If we are affecting only a bit field, read dest_reg and apply the
+* mask
+*/
+ if (mask != TPS65218_MASK_ALL_BITS) {
+ ret = i2c_read(TPS65218_CHIP_PM, dest_reg, 1, read_val, 1);
+ if (ret)
+ return ret;
+ read_val = (~mask);
+ read_val |= (dest_val mask);
+ dest_val = read_val;
+ }
+
+ if (prot_level 0) {
+ xor_reg = dest_reg ^ TPS65218_PASSWORD_UNLOCK;
+ ret = i2c_write(TPS65218_CHIP_PM, TPS65218_PASSWORD, 1,
+ xor_reg, 1);
+ if (ret)
+ return ret;
+ }
+
+ ret = i2c_write(TPS65218_CHIP_PM, dest_reg, 1, dest_val, 1);
+ if (ret)
+ return ret;
+
+ if (prot_level == TPS65218_PROT_LEVEL_2) {
+ ret = i2c_write(TPS65218_CHIP_PM, TPS65218_PASSWORD, 1,
+ xor_reg, 1);
+ if (ret)
+ return ret;
+
+ ret = i2c_write(TPS65218_CHIP_PM, dest_reg, 1, dest_val, 1);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+/**
+ * tps65218_voltage_update() - Function to change a voltage level, as this
+ *is a multi-step process.
+ * @dc_cntrl_reg: DC voltage control register to change.
+ * @volt_sel: New value for the voltage register
+ * @return: 0 for success, not 0 on failure.
+ */
+int tps65218_voltage_update(uchar dc_cntrl_reg, uchar volt_sel)
+{
+ if ((dc_cntrl_reg != TPS65218_DCDC1)
+ (dc_cntrl_reg != TPS65218_DCDC2))
+ return 1;
+
+ /* set voltage level */
+ if (tps65218_reg_write(TPS65218_PROT_LEVEL_2, dc_cntrl_reg, volt_sel,
+ TPS65218_MASK_ALL_BITS))
+ return 1;
+
+ /* set GO bit to initiate voltage transition */
+ if (tps65218_reg_write(TPS65218_PROT_LEVEL_2, TPS65218_SLEW,
+ TPS65218_DCDC_GO, TPS65218_DCDC_GO))
+ return 1;
+
+ return 0;
+}
diff --git a/include/power/tps65218.h b/include/power/tps65218.h
new file mode 100644
index 000..67aa2f8
--- /dev/null
+++ b/include/power/tps65218.h
@@ -0,0 +1,63 @@
+/*
+ * (C) Copyright 2014
+ * Texas Instruments, www.ti.com
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef __POWER_TPS65218_H__
+#define __POWER_TPS65218_H__
+
+/* I2C chip address */
+#define TPS65218_CHIP_PM 0x24
+
+/* Registers */
+enum {
+ TPS65218_CHIPID = 0x00,
+ TPS65218_INT1,
+ TPS65218_INT2,
+
[U-Boot] [PATCH 4/4] arm:am43xx: Add TPS65218 support to scale voltages up
This family is supported by the TPS65218 PMIC. Implement a scale_vcores
to set the MPU and CORE voltage correctly to the max frequency that is
supported (and what we will be scaling them to in setup_dplls()).
Signed-off-by: Tom Rini tr...@ti.com
---
board/ti/am43xx/board.c | 48 --
include/configs/am43xx_evm.h |4
2 files changed, 45 insertions(+), 7 deletions(-)
diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c
index e05a50b..7786903 100644
--- a/board/ti/am43xx/board.c
+++ b/board/ti/am43xx/board.c
@@ -19,6 +19,7 @@
#include asm/arch/gpio.h
#include asm/emif.h
#include board.h
+#include power/tps65218.h
#include miiphy.h
#include cpsw.h
@@ -416,13 +417,6 @@ void emif_get_ext_phy_ctrl_const_regs(const u32 **regs,
u32 *size)
const struct dpll_params *get_dpll_ddr_params(void)
{
- struct am43xx_board_id header;
-
- enable_i2c0_pin_mux();
- i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
- if (read_eeprom(header) 0)
- puts(Could not get board ID.\n);
-
if (board_is_eposevm())
return epos_evm_dpll_ddr;
else if (board_is_gpevm() || board_is_sk())
@@ -500,6 +494,46 @@ const struct dpll_params *get_dpll_per_params(void)
return dpll_per[ind];
}
+void scale_vcores(void)
+{
+ const struct dpll_params *mpu_params;
+ int mpu_vdd;
+ struct am43xx_board_id header;
+
+ enable_i2c0_pin_mux();
+ i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
+ if (read_eeprom(header) 0)
+ puts(Could not get board ID.\n);
+
+ /* Get the frequency */
+ mpu_params = get_dpll_mpu_params();
+
+ if (i2c_probe(TPS65218_CHIP_PM))
+ return;
+
+ if (mpu_params-m == 1000) {
+ mpu_vdd = TPS65218_DCDC_VOLT_SEL_1330MV;
+ } else if (mpu_params-m == 600) {
+ mpu_vdd = TPS65218_DCDC_VOLT_SEL_1100MV;
+ } else {
+ puts(Unknown MPU clock, not scaling\n);
+ return;
+ }
+
+ /* Set DCDC1 (CORE) voltage to 1.1V */
+ if (tps65218_voltage_update(TPS65218_DCDC1,
+ TPS65218_DCDC_VOLT_SEL_1100MV)) {
+ puts(tps65218_voltage_update failure\n);
+ return;
+ }
+
+ /* Set DCDC2 (MPU) voltage */
+ if (tps65218_voltage_update(TPS65218_DCDC2, mpu_vdd)) {
+ puts(tps65218_voltage_update failure\n);
+ return;
+ }
+}
+
void set_uart_mux_conf(void)
{
enable_uart0_pin_mux();
diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h
index 470fa39..2e19c17 100644
--- a/include/configs/am43xx_evm.h
+++ b/include/configs/am43xx_evm.h
@@ -32,11 +32,15 @@
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
#define CONFIG_SYS_I2C_MULTI_EEPROMS
+/* Power */
+#define CONFIG_POWER_TPS65218
+
/* SPL defines. */
#define CONFIG_SPL_TEXT_BASE 0x40300350
#define CONFIG_SPL_MAX_SIZE(220 10) /* 220KB */
#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + \
(128 20))
+#define CONFIG_SPL_POWER_SUPPORT
#define CONFIG_SPL_YMODEM_SUPPORT
/* Enabling L2 Cache */
--
1.7.9.5
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Re: [U-Boot] [PULL] u-boot-avr32/master - u-boot/master
On Mon, May 26, 2014 at 09:28:27PM +0200, Andreas Bießmann wrote: Dear Tom Rini, Please pull the following changes from u-boot-avr32/master into u-boot/master. The following changes since commit 9665fa8f9e1488209d5e01d0792c243e0a220c5a: Merge branch 'master' of git://git.denx.de/u-boot-arm (2014-05-24 06:34:08 -0400) are available in the git repository at: git://git.denx.de/u-boot-avr32.git master for you to fetch changes up to 024cd74174a7ee11e71a430395d9f8ae334fec43: atngw100mkii: add missing CONFIG_SYS_TEXT_BASE (2014-05-26 21:23:54 +0200) Andreas Bießmann (1): atngw100mkii: add missing CONFIG_SYS_TEXT_BASE include/configs/atngw100mkii.h |1 + 1 file changed, 1 insertion(+) Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] U-boot hangs on imx6 pci driver
Tim, On Wed, Jun 4, 2014 at 9:16 PM, Tim Harvey thar...@gateworks.com wrote: work-around the problem on my end as well. Note that I do not see this issue unless I'm using one of our boards with a PCIe switch and If I disable PCI support in u-boot this does not occur. This feels like a Does this help? drivers/pci/pcie_imx.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/pci/pcie_imx.c b/drivers/pci/pcie_imx.c index c48737e..190cdec 100644 --- a/drivers/pci/pcie_imx.c +++ b/drivers/pci/pcie_imx.c @@ -435,8 +435,7 @@ static int imx6_pcie_init_phy(void) clrbits_le32(iomuxc_regs-gpr[12], IOMUXC_GPR12_APPS_LTSSM_ENABLE); clrsetbits_le32(iomuxc_regs-gpr[12], -IOMUXC_GPR12_DEVICE_TYPE_MASK, -IOMUXC_GPR12_DEVICE_TYPE_RC); +IOMUXC_GPR12_DEVICE_TYPE_MASK, 4 12); clrsetbits_le32(iomuxc_regs-gpr[12], IOMUXC_GPR12_LOS_LEVEL_MASK, IOMUXC_GPR12_LOS_LEVEL_9); ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PULL] u-boot-usb/master
On Sun, Jun 01, 2014 at 07:47:35PM +0200, Marek Vasut wrote: The following changes since commit 90b51c33f362926e17d4c07dcef1ce822abaa89f: Merge branch 'master' of git://git.denx.de/u-boot-arm (2014-05-30 11:34:39 -0400) are available in the git repository at: git://git.denx.de/u-boot-usb.git master for you to fetch changes up to 006c7026882011ba49c9a39d27c4aff3ace07847: usb: ci_udc: complete ep0 direction handling (2014-06-01 19:22:40 +0200) Lukasz Majewski (1): dfu: Introduction of the dfu_hash_algo env variable for checksum method setting Stephen Warren (6): usb: hub: fix power good delay timing usb: hub: remove CONFIG_USB_HUB_MIN_POWER_ON_DELAY usb: ci_udc: detect queued requests on ep0 usb: ci_udc: use a single descriptor for ep0 usb: ci_udc: pre-allocate ep0 req usb: ci_udc: complete ep0 direction handling README | 3 --- common/usb_hub.c | 11 +-- drivers/dfu/dfu.c| 52 +++- drivers/usb/gadget/ci_udc.c | 91 ++- drivers/usb/gadget/ci_udc.h | 2 ++ include/configs/cm_t35.h | 2 -- include/configs/gw_ventana.h | 1 - 7 files changed, 128 insertions(+), 34 deletions(-) Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] please pull u-boot-arc master
On Tue, Jun 03, 2014 at 12:19:56PM +, Alexey Brodkin wrote: Dear Tom, The following changes since commit 3fe1a8545b55d31a6db2d9e60d962c4f6e048913: powerpc: hiddendragon: remove orphan board (2014-05-30 14:03:24 -0400) are available in the git repository at: git://git.denx.de/u-boot-arc.git master for you to fetch changes up to d119a2ef7fb3c10b01c64a7da8f3906691166efe: ARC: enable CONFIG_SYS_BOOT_RAMDISK_HIGH (2014-06-03 16:16:57 +0400) Alexey Brodkin (1): ARC: enable CONFIG_SYS_BOOT_RAMDISK_HIGH arch/arc/include/asm/config.h | 1 + 1 file changed, 1 insertion(+) Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH V3] ARM: tegra: enable USB device mode and UMS on some boards
On 05/29/2014 03:29 PM, Stephen Warren wrote: From: Stephen Warren swar...@nvidia.com For each of Jetson TK1, Venice2, and Beaver: - Enable the first USB controller in DT, and describe its configuration. - Enable USB device/gadget support. This allows the user to type e.g. ums 0 mmc 0 at the command-line to cause U-Boot to act a USB device implementing the USB Mass Storage protocol, and expose MMC device 0 that way. This allows a host PC to mount the Tegra device's MMC, partition it, and install a filesystem on it. Tom, could this be applied soon so it makes v2014.07? Thanks. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [Patch v4 2/5] ARMv8: Adjust MMU setup
On Thu, Jun 05, 2014 at 04:07:17PM +0100, York Sun wrote:
On 06/05/2014 03:09 AM, Mark Rutland wrote:
On Wed, Jun 04, 2014 at 05:27:30PM +0100, York Sun wrote:
On 06/02/2014 11:01 AM, Mark Rutland wrote:
On Mon, Jun 02, 2014 at 05:06:13PM +0100, York Sun wrote:
On 06/02/2014 04:34 AM, Mark Rutland wrote:
On Thu, May 29, 2014 at 09:49:05PM +0100, York Sun wrote:
Make MMU functions reusable. Platform code can setup its own MMU
tables.
What exactly does platform code need to setup its own tables for?
The general ARMv8 MMU table is not detail enough to control memory
attribute
like cache for all addresses. We have devices mapping to addresses with
different requirement for cache control.
And there are no APIs for creating device mappings rather than exporting
the raw pagetable accessors and hard-coding them differently in every
board file?
That's a good question. At this point, only two platforms are using ARMv8
code.
I am expecting FSL ARMv8 implementation will stay similar, i.e. covered by
the
file I added. If that's not the case, or more ARMv8 SoCs need special MMU
table,
we then should introduce such API. Having a full function MMU API may be an
overkill for U-boot. We don't need dynamic MMU anyway.
Maybe. It just seems to me that it would be possible to pre-allocate an
empty table that we could place device (nGnRnE?) mappings in. Then all
you'd need to call from board code is a function to map a range, rather
than having to duplicate logic for creating the tables you want.
It sounds good, but not the case. For the three level tables I am using
(level0,
level1, level2), I don't have level2 table for every address, that will be too
many. Instead, I have a lot of blocks for level1. When I need some fine
control
within a level1 block range, I have to create a new level2 table. It is
doable,
but I will hold on that if I can use static table.
While my suggestion might not be the best, I'm not sure I follow, unless
you always want to idmap devices?
If you don't idmap devices, then you can place all of the disparate
physical mappings within a single table unless you have very large
peripherals to map?
Also fix a typo of TCR_EL3_IPS_BITS in cache_v8.c.
Signed-off-by: York Sun york...@freescale.com
CC: David Feng feng...@phytium.com.cn
---
Change log:
v4: new patch, splitted from v3 2/4
Revise set_pgtable_section() to be reused by platform MMU code
Add inline function set_ttbr_tcr_mair() to be used by this and
platform mmu code
arch/arm/cpu/armv8/cache_v8.c| 49
--
arch/arm/include/asm/armv8/mmu.h | 23 ++
2 files changed, 43 insertions(+), 29 deletions(-)
diff --git a/arch/arm/cpu/armv8/cache_v8.c
b/arch/arm/cpu/armv8/cache_v8.c
index a96ecda..67dbd46 100644
--- a/arch/arm/cpu/armv8/cache_v8.c
+++ b/arch/arm/cpu/armv8/cache_v8.c
@@ -12,15 +12,14 @@
DECLARE_GLOBAL_DATA_PTR;
#ifndef CONFIG_SYS_DCACHE_OFF
-
-static void set_pgtable_section(u64 section, u64 memory_type)
+void set_pgtable_section(u64 *page_table, u64 index, u64 section,
+ u64 memory_type)
{
-u64 *page_table = (u64 *)gd-arch.tlb_addr;
u64 value;
-value = (section SECTION_SHIFT) | PMD_TYPE_SECT |
PMD_SECT_AF;
+value = section | PMD_TYPE_SECT | PMD_SECT_AF;
value |= PMD_ATTRINDX(memory_type);
-page_table[section] = value;
+page_table[index] = value;
}
/* to activate the MMU we need to set up virtual memory */
@@ -28,10 +27,13 @@ static void mmu_setup(void)
{
int i, j, el;
bd_t *bd = gd-bd;
+u64 *page_table = (u64 *)gd-arch.tlb_addr;
/* Setup an identity-mapping for all spaces */
-for (i = 0; i (PGTABLE_SIZE 3); i++)
-set_pgtable_section(i, MT_DEVICE_NGNRNE);
+for (i = 0; i (PGTABLE_SIZE 3); i++) {
+set_pgtable_section(page_table, i, i SECTION_SHIFT,
+MT_DEVICE_NGNRNE);
+}
/* Setup an identity-mapping for all RAM space */
for (i = 0; i CONFIG_NR_DRAM_BANKS; i++) {
@@ -39,36 +41,25 @@ static void mmu_setup(void)
ulong end = bd-bi_dram[i].start +
bd-bi_dram[i].size;
for (j = start SECTION_SHIFT;
j end SECTION_SHIFT; j++) {
-set_pgtable_section(j, MT_NORMAL);
+set_pgtable_section(page_table, j, j
SECTION_SHIFT,
+MT_NORMAL);
}
}
/* load TTBR0 */
el = current_el();
if (el == 1) {
-asm volatile(msr ttbr0_el1, %0
- : : r (gd-arch.tlb_addr) : memory);
-
Re: [U-Boot] U-boot hangs on imx6 pci driver
On Thursday, June 05, 2014 at 05:27:08 PM, Fabio Estevam wrote: Tim, On Wed, Jun 4, 2014 at 9:16 PM, Tim Harvey thar...@gateworks.com wrote: work-around the problem on my end as well. Note that I do not see this issue unless I'm using one of our boards with a PCIe switch and If I disable PCI support in u-boot this does not occur. This feels like a Does this help? drivers/pci/pcie_imx.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/pci/pcie_imx.c b/drivers/pci/pcie_imx.c index c48737e..190cdec 100644 --- a/drivers/pci/pcie_imx.c +++ b/drivers/pci/pcie_imx.c @@ -435,8 +435,7 @@ static int imx6_pcie_init_phy(void) clrbits_le32(iomuxc_regs-gpr[12], IOMUXC_GPR12_APPS_LTSSM_ENABLE); clrsetbits_le32(iomuxc_regs-gpr[12], -IOMUXC_GPR12_DEVICE_TYPE_MASK, -IOMUXC_GPR12_DEVICE_TYPE_RC); +IOMUXC_GPR12_DEVICE_TYPE_MASK, 4 12); Is this the setting of RC-mode in GPR12 ? That's wrong in the FSL datasheet, not in the code IIRC ;-) Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 0/6] sunxi: GPIO, AHCI and Cubieboard 2 support.
The following enables AHCI support for sun7i boards, which in turn requires GPIO support. It also adds support for the Cubieboard2 board. This is based on v2 of Hans' sunxi: Bug fixes, sun4i and sun5i support, pmic support and network improvements series[0]. (Other than e.g. boards.cfg and Makefile diff context it only actually depends on sunxi: Add support for using MII phy-s with the GMAC nic). I've also pushed to my gitorious tree. The following changes since commit 59c0bae92aa7491ede8a95a1bd1a1326d5aa938a: sunxi: Add support for using MII phy-s with the GMAC nic (2014-06-03 21:35:05 +0200) are available in the git repository at: git://gitorious.org/ijc/u-boot.git sunxi-gpio-ahci-and-cubieboard2-v2 for you to fetch changes up to 042b84c6857f1492b79bf2261fe8157714b8fa24: ahci: provide sunxi SATA driver using AHCI platform framework (2014-06-05 18:54:08 +0100) Ian Campbell (6): AHCI: Increase link timeout to 200ms board_r: run scsi init() on ARM too sunxi: add Cubieboard2 support sunxi: add gpio driver sunxi: use setbits_le32 to enable the DMA clock ahci: provide sunxi SATA driver using AHCI platform framework arch/arm/cpu/armv7/sunxi/clock_sun4i.c| 7 +- arch/arm/include/asm/arch-sunxi/clock_sun4i.h | 11 ++- arch/arm/include/asm/arch-sunxi/gpio.h| 2 + board/sunxi/Makefile | 2 + board/sunxi/ahci.c| 84 + board/sunxi/dram_cubieboard2.c| 31 boards.cfg| 8 +- common/board_r.c | 6 +- drivers/block/ahci.c | 18 - drivers/gpio/Makefile | 1 + drivers/gpio/sunxi_gpio.c | 102 ++ include/ahci.h| 4 + include/configs/sunxi-common.h| 16 13 files changed, 278 insertions(+), 14 deletions(-) create mode 100644 board/sunxi/ahci.c create mode 100644 board/sunxi/dram_cubieboard2.c create mode 100644 drivers/gpio/sunxi_gpio.c [0] https://github.com/jwrdegoede/u-boot-sunxi/tree/sun4i-upstreaming-v2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/6] AHCI: Increase link timeout to 200ms
In 73545f75b66d ahci: wait longer for link I increased the
timeout to 40ms based on the observed behaviour of a WD disk on a
Cubietruck. Since then Karsten Merker and myself have both
observed timeouts with HGST disks (Karsten on Cubietruck, me on
Cubieboard2). Increasing the timeout to ~175ms fixes this, so go
to 200ms for a bit of headroom.
Signed-off-by: Ian Campbell i...@hellion.org.uk
Acked-by: Hans de Goede hdego...@redhat.com
Cc: Karsten Merker mer...@debian.org
---
drivers/block/ahci.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/block/ahci.c b/drivers/block/ahci.c
index c8f6573..4df8046 100644
--- a/drivers/block/ahci.c
+++ b/drivers/block/ahci.c
@@ -41,7 +41,7 @@ u16 *ataid[AHCI_MAX_PORTS];
#define WAIT_MS_SPINUP 2
#define WAIT_MS_DATAIO 5000
#define WAIT_MS_FLUSH 5000
-#define WAIT_MS_LINKUP 40
+#define WAIT_MS_LINKUP 200
static inline u32 ahci_port_base(u32 base, u32 port)
{
--
1.9.0
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[U-Boot] [PATCH 2/6] board_r: run scsi init() on ARM too
This has been disabled for ARM in initr_scsi since that function was
introduced. However it works fine for me on Cubieboard and Cubietruck (with the
upcoming AHCI glue patch).
I also tested on two random ARM platforms which seem to define CONFIG_CMD_SCSI:
- highbank worked fine (on midway hardware)
- omap5_uevm built OK and I confirmed using objdump that things were as
expected (i.e. the default weak scsi_init nop was used).
While there remove the mismatched comment from the #endif (omitting the comment
seems to be the prevailing style in this file) and add a missing return to
initr_doc which I happened to spot while editing.
Signed-off-by: Ian Campbell i...@hellion.org.uk
Acked-by: Simon Glass s...@chromium.org
Acked-by: Hans de Goede hdego...@redhat.com
---
common/board_r.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/common/board_r.c b/common/board_r.c
index 602a239..427ee67 100644
--- a/common/board_r.c
+++ b/common/board_r.c
@@ -588,21 +588,19 @@ static int initr_status_led(void)
#if defined(CONFIG_CMD_SCSI)
static int initr_scsi(void)
{
- /* Not supported properly on ARM yet */
-#ifndef CONFIG_ARM
puts(SCSI: );
scsi_init();
-#endif
return 0;
}
-#endif /* CONFIG_CMD_NET */
+#endif
#if defined(CONFIG_CMD_DOC)
static int initr_doc(void)
{
puts(DOC: );
doc_init();
+ return 0
}
#endif
--
1.9.0
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[U-Boot] [PATCH 5/6] sunxi: use setbits_le32 to enable the DMA clock
Signed-off-by: Ian Campbell i...@hellion.org.uk --- v2: Split out from ahci: provide sunxi SATA driver using AHCI platform framework --- arch/arm/cpu/armv7/sunxi/clock_sun4i.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm/cpu/armv7/sunxi/clock_sun4i.c b/arch/arm/cpu/armv7/sunxi/clock_sun4i.c index 5a7da3c..b8b16cf 100644 --- a/arch/arm/cpu/armv7/sunxi/clock_sun4i.c +++ b/arch/arm/cpu/armv7/sunxi/clock_sun4i.c @@ -36,8 +36,7 @@ void clock_init_safe(void) CPU_CLK_SRC_PLL1 CPU_CLK_SRC_SHIFT, ccm-cpu_ahb_apb0_cfg); #ifdef CONFIG_SUN7I - writel(0x1 AHB_GATE_OFFSET_DMA | readl(ccm-ahb_gate0), - ccm-ahb_gate0); + setbits_le32(ccm-ahb_gate0, 0x1 AHB_GATE_OFFSET_DMA); #endif writel(PLL6_CFG_DEFAULT, ccm-pll6_cfg); } -- 1.9.0 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 3/6] sunxi: add Cubieboard2 support
This is a sun7i (A20) based followup to the sun4i (A10)
Cubieboard. It has GMAC using MII mode.
Signed-off-by: Ian Campbell i...@hellion.org.uk
Acked-by: Hans de Goede hdego...@redhat.com
---
board/sunxi/Makefile | 1 +
board/sunxi/dram_cubieboard2.c | 31 +++
boards.cfg | 2 ++
3 files changed, 34 insertions(+)
create mode 100644 board/sunxi/dram_cubieboard2.c
diff --git a/board/sunxi/Makefile b/board/sunxi/Makefile
index 7083632..62acb8f 100644
--- a/board/sunxi/Makefile
+++ b/board/sunxi/Makefile
@@ -12,5 +12,6 @@ obj-y += board.o
obj-$(CONFIG_SUNXI_GMAC) += gmac.o
obj-$(CONFIG_A13_OLINUXINOM) += dram_a13_oli_micro.o
obj-$(CONFIG_CUBIEBOARD) += dram_cubieboard.o
+obj-$(CONFIG_CUBIEBOARD2) += dram_cubieboard2.o
obj-$(CONFIG_CUBIETRUCK) += dram_cubietruck.o
obj-$(CONFIG_R7DONGLE) += dram_r7dongle.o
diff --git a/board/sunxi/dram_cubieboard2.c b/board/sunxi/dram_cubieboard2.c
new file mode 100644
index 000..9e75367
--- /dev/null
+++ b/board/sunxi/dram_cubieboard2.c
@@ -0,0 +1,31 @@
+/* this file is generated, don't edit it yourself */
+
+#include common.h
+#include asm/arch/dram.h
+
+static struct dram_para dram_para = {
+ .clock = 480,
+ .type = 3,
+ .rank_num = 1,
+ .density = 4096,
+ .io_width = 16,
+ .bus_width = 32,
+ .cas = 9,
+ .zq = 0x7f,
+ .odt_en = 0,
+ .size = 1024,
+ .tpr0 = 0x42d899b7,
+ .tpr1 = 0xa090,
+ .tpr2 = 0x22a00,
+ .tpr3 = 0x0,
+ .tpr4 = 0x1,
+ .tpr5 = 0x0,
+ .emr1 = 0x4,
+ .emr2 = 0x10,
+ .emr3 = 0x0,
+};
+
+unsigned long sunxi_dram_init(void)
+{
+ return dramc_init(dram_para);
+}
diff --git a/boards.cfg b/boards.cfg
index 18a8400..ddb105e 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -383,6 +383,8 @@ Active arm armv7 s5pc1xx samsung
smdkc100
Active arm armv7 socfpga altera socfpga
socfpga_cyclone5 -
-
Active arm armv7 sunxi - sunxi
A13-OLinuXinoMsun5i:A13_OLINUXINOM,SPL,CONS_INDEX=2
Hans de Goede hdego...@redhat.com
Active arm armv7 sunxi - sunxi
Cubieboard
sun4i:CUBIEBOARD,SPL,AXP209_POWER,SUNXI_EMAC
Hans de Goede
hdego...@redhat.com
+Active arm armv7 sunxi - sunxi
Cubieboard2 sun7i:CUBIEBOARD2,SPL,SUNXI_GMAC
Ian Campbell i...@hellion.org.uk:Hans de Goede
hdego...@redhat.com
+Active arm armv7 sunxi - sunxi
Cubieboard2_FEL sun7i:CUBIEBOARD2,SPL_FEL,SUNXI_GMAC
Ian Campbell i...@hellion.org.uk:Hans de Goede
hdego...@redhat.com
Active arm armv7 sunxi - sunxi
Cubietruck
sun7i:CUBIETRUCK,SPL,AXP209_POWER,SUNXI_GMAC,RGMII
Ian Campbell
i...@hellion.org.uk:Hans de Goede hdego...@redhat.com
Active arm armv7 sunxi - sunxi
Cubietruck_FEL
sun7i:CUBIETRUCK,SPL_FEL,AXP209_POWER,SUNXI_GMAC,RGMII
Ian Campbell
i...@hellion.org.uk:Hans de Goede hdego...@redhat.com
Active arm armv7 sunxi - sunxi
r7-tv-dongle sun5i:R7DONGLE,SPL,AXP152_POWER
Hans de Goede hdego...@redhat.com
--
1.9.0
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[U-Boot] [PATCH 4/6] sunxi: add gpio driver
This patch enables CONFIG_CMD_GPIO for the Allwinner (sunxi) platform as well
as providing the common gpio API (gpio_request/free, direction in/out, get/set
etc).
Signed-off-by: Chen-Yu Tsai w...@csie.org
Signed-off-by: Hans de Goede hdego...@redhat.com
Signed-off-by: Ma Haijun mahaij...@gmail.com
Signed-off-by: Oliver Schinagl oli...@schinagl.nl
Signed-off-by: Ian Campbell i...@hellion.org.uk
Cc: Henrik Nordström hen...@henriknordstrom.net
Cc: Tom Cubie mr.hip...@gmail.com
---
arch/arm/include/asm/arch-sunxi/gpio.h | 2 +
drivers/gpio/Makefile | 1 +
drivers/gpio/sunxi_gpio.c | 102 +
include/configs/sunxi-common.h | 4 ++
4 files changed, 109 insertions(+)
create mode 100644 drivers/gpio/sunxi_gpio.c
diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h
b/arch/arm/include/asm/arch-sunxi/gpio.h
index 892479c..f7f3d8c 100644
--- a/arch/arm/include/asm/arch-sunxi/gpio.h
+++ b/arch/arm/include/asm/arch-sunxi/gpio.h
@@ -143,5 +143,7 @@ int sunxi_gpio_set_cfgpin(u32 pin, u32 val);
int sunxi_gpio_get_cfgpin(u32 pin);
int sunxi_gpio_set_drv(u32 pin, u32 val);
int sunxi_gpio_set_pull(u32 pin, u32 val);
+int sunxi_name_to_gpio(const char *name);
+#define name_to_gpio(name) sunxi_name_to_gpio(name)
#endif /* _SUNXI_GPIO_H */
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 4e001e1..86813b9 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -34,3 +34,4 @@ obj-$(CONFIG_XILINX_GPIO) += xilinx_gpio.o
obj-$(CONFIG_ADI_GPIO2)+= adi_gpio2.o
obj-$(CONFIG_TCA642X) += tca642x.o
oby-$(CONFIG_SX151X) += sx151x.o
+obj-$(CONFIG_SUNXI_GPIO) += sunxi_gpio.o
diff --git a/drivers/gpio/sunxi_gpio.c b/drivers/gpio/sunxi_gpio.c
new file mode 100644
index 000..0c50a8f
--- /dev/null
+++ b/drivers/gpio/sunxi_gpio.c
@@ -0,0 +1,102 @@
+/*
+ * (C) Copyright 2012 Henrik Nordstrom hen...@henriknordstrom.net
+ *
+ * Based on earlier arch/arm/cpu/armv7/sunxi/gpio.c:
+ *
+ * (C) Copyright 2007-2011
+ * Allwinner Technology Co., Ltd. www.allwinnertech.com
+ * Tom Cubie tangli...@allwinnertech.com
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include asm/io.h
+#include asm/gpio.h
+
+static int sunxi_gpio_output(u32 pin, u32 val)
+{
+ u32 dat;
+ u32 bank = GPIO_BANK(pin);
+ u32 num = GPIO_NUM(pin);
+ struct sunxi_gpio *pio = BANK_TO_GPIO(bank);
+
+ dat = readl(pio-dat);
+ if (val)
+ dat |= 0x1 num;
+ else
+ dat = ~(0x1 num);
+
+ writel(dat, pio-dat);
+
+ return 0;
+}
+
+static int sunxi_gpio_input(u32 pin)
+{
+ u32 dat;
+ u32 bank = GPIO_BANK(pin);
+ u32 num = GPIO_NUM(pin);
+ struct sunxi_gpio *pio = BANK_TO_GPIO(bank);
+
+ dat = readl(pio-dat);
+ dat = num;
+
+ return dat 0x1;
+}
+
+int gpio_request(unsigned gpio, const char *label)
+{
+ return 0;
+}
+
+int gpio_free(unsigned gpio)
+{
+ return 0;
+}
+
+int gpio_direction_input(unsigned gpio)
+{
+ sunxi_gpio_set_cfgpin(gpio, SUNXI_GPIO_INPUT);
+
+ return sunxi_gpio_input(gpio);
+}
+
+int gpio_direction_output(unsigned gpio, int value)
+{
+ sunxi_gpio_set_cfgpin(gpio, SUNXI_GPIO_OUTPUT);
+
+ return sunxi_gpio_output(gpio, value);
+}
+
+int gpio_get_value(unsigned gpio)
+{
+ return sunxi_gpio_input(gpio);
+}
+
+int gpio_set_value(unsigned gpio, int value)
+{
+ return sunxi_gpio_output(gpio, value);
+}
+
+int sunxi_name_to_gpio(const char *name)
+{
+ int group = 0;
+ int groupsize = 9 * 32;
+ long pin;
+ char *eptr;
+ if (*name == 'P' || *name == 'p')
+ name++;
+ if (*name = 'A') {
+ group = *name - (*name 'a' ? 'a' : 'A');
+ groupsize = 32;
+ name++;
+ }
+
+ pin = simple_strtol(name, eptr, 10);
+ if (!*name || *eptr)
+ return -1;
+ if (pin 0 || pin groupsize || group = 9)
+ return -1;
+ return group * 32 + pin;
+}
diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h
index a9d104a..ebb9f7a 100644
--- a/include/configs/sunxi-common.h
+++ b/include/configs/sunxi-common.h
@@ -179,6 +179,10 @@
#define CONFIG_CONS_INDEX 1 /* UART0 */
#endif
+/* GPIO */
+#define CONFIG_SUNXI_GPIO
+#define CONFIG_CMD_GPIO
+
/* Ethernet support */
#ifdef CONFIG_SUNXI_EMAC
#define CONFIG_MII /* MII PHY management */
--
1.9.0
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[U-Boot] [PATCH 6/6] ahci: provide sunxi SATA driver using AHCI platform framework
This enables the necessary clocks, in AHB0 and in PLL6_CFG. This is done
for sun7i only since I don't have access to any other sunxi platforms
with sata included.
The PHY setup is derived from the Alwinner releases and Linux, but is mostly
undocumented.
The Allwinner AHCI controller also requires some magic (and, again,
undocumented) DMA initialisation when starting a port. This is added under a
suitable ifdef.
This option is enabled for Cubieboard, Cubieboard2 and Cubietruck based on
contents of Linux DTS files, including SATA power pin config taken from the
DTS. All build tested, but runtime tested on Cubieboard2 and Cubietruck only.
Signed-off-by: Ian Campbell i...@hellion.org.uk
Acked-by: Hans de Goede hdego...@redhat.com
---
arch/arm/cpu/armv7/sunxi/clock_sun4i.c| 4 ++
arch/arm/include/asm/arch-sunxi/clock_sun4i.h | 11 ++--
board/sunxi/Makefile | 1 +
board/sunxi/ahci.c| 84 +++
boards.cfg| 10 ++--
drivers/block/ahci.c | 16 +
include/ahci.h| 4 ++
include/configs/sunxi-common.h| 12
8 files changed, 133 insertions(+), 9 deletions(-)
create mode 100644 board/sunxi/ahci.c
diff --git a/arch/arm/cpu/armv7/sunxi/clock_sun4i.c
b/arch/arm/cpu/armv7/sunxi/clock_sun4i.c
index b8b16cf..ecbdb01 100644
--- a/arch/arm/cpu/armv7/sunxi/clock_sun4i.c
+++ b/arch/arm/cpu/armv7/sunxi/clock_sun4i.c
@@ -39,6 +39,10 @@ void clock_init_safe(void)
setbits_le32(ccm-ahb_gate0, 0x1 AHB_GATE_OFFSET_DMA);
#endif
writel(PLL6_CFG_DEFAULT, ccm-pll6_cfg);
+#ifdef CONFIG_SUNXI_AHCI
+ setbits_le32(ccm-ahb_gate0, 0x1 AHB_GATE_OFFSET_SATA);
+ setbits_le32(ccm-pll6_cfg, 0x1 CCM_PLL6_CTRL_SATA_EN_SHIFT);
+#endif
}
#endif
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h
b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h
index 928f3f2..2531cbd 100644
--- a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h
@@ -218,10 +218,13 @@ struct sunxi_ccm_reg {
#define CCM_PLL5_CTRL_BYPASS (0x1 30)
#define CCM_PLL5_CTRL_EN (0x1 31)
-#define CCM_PLL6_CTRL_N_SHIFT 8
-#define CCM_PLL6_CTRL_N_MASK (0x1f CCM_PLL6_CTRL_N_SHIFT)
-#define CCM_PLL6_CTRL_K_SHIFT 4
-#define CCM_PLL6_CTRL_K_MASK (0x3 CCM_PLL6_CTRL_K_SHIFT)
+#define CCM_PLL6_CTRL_EN 31
+#define CCM_PLL6_CTRL_BYPASS_EN30
+#define CCM_PLL6_CTRL_SATA_EN_SHIFT14
+#define CCM_PLL6_CTRL_N_SHIFT 8
+#define CCM_PLL6_CTRL_N_MASK (0x1f CCM_PLL6_CTRL_N_SHIFT)
+#define CCM_PLL6_CTRL_K_SHIFT 4
+#define CCM_PLL6_CTRL_K_MASK (0x3 CCM_PLL6_CTRL_K_SHIFT)
#define CCM_GPS_CTRL_RESET (0x1 0)
#define CCM_GPS_CTRL_GATE (0x1 1)
diff --git a/board/sunxi/Makefile b/board/sunxi/Makefile
index 62acb8f..03f55cc 100644
--- a/board/sunxi/Makefile
+++ b/board/sunxi/Makefile
@@ -10,6 +10,7 @@
#
obj-y += board.o
obj-$(CONFIG_SUNXI_GMAC) += gmac.o
+obj-$(CONFIG_SUNXI_AHCI) += ahci.o
obj-$(CONFIG_A13_OLINUXINOM) += dram_a13_oli_micro.o
obj-$(CONFIG_CUBIEBOARD) += dram_cubieboard.o
obj-$(CONFIG_CUBIEBOARD2) += dram_cubieboard2.o
diff --git a/board/sunxi/ahci.c b/board/sunxi/ahci.c
new file mode 100644
index 000..0c262ea
--- /dev/null
+++ b/board/sunxi/ahci.c
@@ -0,0 +1,84 @@
+#include common.h
+#include ahci.h
+#include scsi.h
+#include errno.h
+#include asm/io.h
+#include asm/gpio.h
+
+#define AHCI_PHYCS0R 0x00c0
+#define AHCI_PHYCS1R 0x00c4
+#define AHCI_PHYCS2R 0x00c8
+#define AHCI_RWCR0x00fc
+
+/* This magic PHY initialisation was taken from the Allwinner releases
+ * and Linux driver, but is completely undocumented.
+ */
+static int sunxi_ahci_phy_init(u32 base)
+{
+ u8 *reg_base = (u8 *)base;
+ u32 reg_val;
+ int timeout;
+
+ writel(0, reg_base + AHCI_RWCR);
+ mdelay(5);
+
+ setbits_le32(reg_base + AHCI_PHYCS1R, 0x1 19);
+ clrsetbits_le32(reg_base + AHCI_PHYCS0R,
+ (0x7 24),
+ (0x5 24) | (0x1 23) | (0x1 18));
+ clrsetbits_le32(reg_base + AHCI_PHYCS1R,
+ (0x3 16) | (0x1f 8) | (0x3 6),
+ (0x2 16) | (0x6 8) | (0x2 6));
+ setbits_le32(reg_base + AHCI_PHYCS1R, (0x1 28) | (0x1 15));
+ clrbits_le32(reg_base + AHCI_PHYCS1R, (0x1 19));
+ clrsetbits_le32(reg_base + AHCI_PHYCS0R, (0x7 20), (0x3 20));
+ clrsetbits_le32(reg_base + AHCI_PHYCS2R, (0x1f 5), (0x19 5));
+ mdelay(5);
+
+ setbits_le32(reg_base + AHCI_PHYCS0R, (0x1 19));
+
+ timeout = 250; /* Power up takes approx 50 us */
+ for (;;) {
+ reg_val = readl(reg_base + AHCI_PHYCS0R) (0x7 28);
+ if (reg_val == (0x2 28))
+ break;
+ if (--timeout == 0) {
+
[U-Boot] [RESEND PATCH 1/3] Check run_command() return code properly
run_command() returns 0 for success, 1 for failure. Fix places which
assume that failure is indicated by a negative return code.
Signed-off-by: Thomas Betker thomas.bet...@rohde-schwarz.com
---
arch/arm/cpu/arm926ejs/kirkwood/cpu.c | 2 +-
board/gdsys/p1022/controlcenterd.c| 6 +-
common/cmd_bootm.c| 6 +-
3 files changed, 3 insertions(+), 11 deletions(-)
diff --git a/arch/arm/cpu/arm926ejs/kirkwood/cpu.c
b/arch/arm/cpu/arm926ejs/kirkwood/cpu.c
index 0937506..da80240 100644
--- a/arch/arm/cpu/arm926ejs/kirkwood/cpu.c
+++ b/arch/arm/cpu/arm926ejs/kirkwood/cpu.c
@@ -210,7 +210,7 @@ static void kw_sysrst_action(void)
debug(Starting %s process...\n, __FUNCTION__);
ret = run_command(s, 0);
- if (ret 0)
+ if (ret != 0)
debug(Error.. %s failed\n, __FUNCTION__);
else
debug(%s process finished\n, __FUNCTION__);
diff --git a/board/gdsys/p1022/controlcenterd.c
b/board/gdsys/p1022/controlcenterd.c
index 8ccd9ce..642b807 100644
--- a/board/gdsys/p1022/controlcenterd.c
+++ b/board/gdsys/p1022/controlcenterd.c
@@ -221,11 +221,7 @@ void hw_watchdog_reset(void)
#ifdef CONFIG_TRAILBLAZER
int do_bootd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
- int rcode = 0;
-
- if (run_command(getenv(bootcmd), flag) 0)
- rcode = 1;
- return rcode;
+ return run_command(getenv(bootcmd), flag);
}
int board_early_init_r(void)
diff --git a/common/cmd_bootm.c b/common/cmd_bootm.c
index 449bb36..745fc65 100644
--- a/common/cmd_bootm.c
+++ b/common/cmd_bootm.c
@@ -1079,11 +1079,7 @@ U_BOOT_CMD(
#if defined(CONFIG_CMD_BOOTD)
int do_bootd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
- int rcode = 0;
-
- if (run_command(getenv(bootcmd), flag) 0)
- rcode = 1;
- return rcode;
+ return run_command(getenv(bootcmd), flag);
}
U_BOOT_CMD(
--
1.9.3
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[U-Boot] [RESEND PATCH 2/3] Add run_command_repeatable()
run_command() returns 0 on success and 1 on error. However, there are some
invocations which expect 0 or 1 for success (not repeatable or repeatable)
and -1 for error; add run_command_repeatable() for this purpose.
Signed-off-by: Thomas Betker thomas.bet...@rohde-schwarz.com
---
common/cli.c | 24
include/common.h | 1 +
2 files changed, 25 insertions(+)
diff --git a/common/cli.c b/common/cli.c
index ea6bfb3..272b028 100644
--- a/common/cli.c
+++ b/common/cli.c
@@ -41,6 +41,30 @@ int run_command(const char *cmd, int flag)
#endif
}
+/*
+ * Run a command using the selected parser, and check if it is repeatable.
+ *
+ * @param cmd Command to run
+ * @param flag Execution flags (CMD_FLAG_...)
+ * @return 0 (not repeatable) or 1 (repeatable) on success, -1 on error.
+ */
+int run_command_repeatable(const char *cmd, int flag)
+{
+#ifndef CONFIG_SYS_HUSH_PARSER
+ return cli_simple_run_command(cmd, flag);
+#else
+ /*
+* parse_string_outer() returns 1 for failure, so clean up
+* its result.
+*/
+ if (parse_string_outer(cmd,
+ FLAG_PARSE_SEMICOLON | FLAG_EXIT_FROM_LOOP))
+ return -1;
+
+ return 0;
+#endif
+}
+
int run_command_list(const char *cmd, int len, int flag)
{
int need_buff = 1;
diff --git a/include/common.h b/include/common.h
index 91dc0f3..cc74633 100644
--- a/include/common.h
+++ b/include/common.h
@@ -271,6 +271,7 @@ int print_buffer(ulong addr, const void *data, uint width,
uint count,
/* common/main.c */
void main_loop (void);
int run_command(const char *cmd, int flag);
+int run_command_repeatable(const char *cmd, int flag);
/**
* Run a list of commands separated by ; or even \0
--
1.9.3
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[U-Boot] [RESEND PATCH 3/3] Use run_command_repeatable()
Replace run_command() by run_command_repeatable() in places which
depend on the return code to indicate repeatability.
Signed-off-by: Thomas Betker thomas.bet...@rohde-schwarz.com
---
common/cli_simple.c | 2 +-
common/cmd_bedbug.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/common/cli_simple.c b/common/cli_simple.c
index 413c2eb..222e292 100644
--- a/common/cli_simple.c
+++ b/common/cli_simple.c
@@ -295,7 +295,7 @@ void cli_simple_loop(void)
if (len == -1)
puts(INTERRUPT\n);
else
- rc = run_command(lastcommand, flag);
+ rc = run_command_repeatable(lastcommand, flag);
if (rc = 0) {
/* invalid command or not repeatable, forget it */
diff --git a/common/cmd_bedbug.c b/common/cmd_bedbug.c
index bdcf712..57a8a3f 100644
--- a/common/cmd_bedbug.c
+++ b/common/cmd_bedbug.c
@@ -238,7 +238,7 @@ void bedbug_main_loop (unsigned long addr, struct pt_regs
*regs)
if (len == -1)
printf (INTERRUPT\n);
else
- rc = run_command(lastcommand, flag);
+ rc = run_command_repeatable(lastcommand, flag);
if (rc = 0) {
/* invalid command or not repeatable, forget it */
--
1.9.3
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[U-Boot] [RESEND PATCH 0/3] Fix command repeat
I am resending the patches because they didn't make it to Patchwork the first time, probably due to a configuration issue on my side. The intent of these patches is to get command repeat to work again. Currently, successful commands won't be repeated but failed commands will -- neither is as expected. The issue is that run_command() returns 0 on success, 1 on error. In order to get command repeat to work, we need a variant which returns -1 on error and 0/1 (non-repeatable/repeatable) on succcess, the same way as cli_simple_run_command() does. Patch 2 adds the run_command_repeatable() function, and patch 3 replaces run_command() by run_command_repeatable() where necessary. Patch 1 is a cleanup of places which call run_command(), but expect it to return -1 on error. This is actually independent of the other two patches -- it just came up when checking run_command() invocations in general. Best regards, Thomas Betker Thomas Betker (3): Check run_command() return code properly Add run_command_repeatable() Use run_command_repeatable() arch/arm/cpu/arm926ejs/kirkwood/cpu.c | 2 +- board/gdsys/p1022/controlcenterd.c| 6 +- common/cli.c | 24 common/cli_simple.c | 2 +- common/cmd_bedbug.c | 2 +- common/cmd_bootm.c| 6 +- include/common.h | 1 + 7 files changed, 30 insertions(+), 13 deletions(-) -- 1.9.3 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 05/12] sunxi: Add sun4i support
On Tue, 2014-06-03 at 21:41 +0200, Hans de Goede wrote: Add support for the Allwinner A10 SoC also known as the Allwinner sun4i family, and add the Cubieboard board which uses the A10 SoC. Compared to sun7 only the DRAM controller is a bit different: -Controller reset bits are inverted, but only for Rev. A -Different hpcr values -No MBUS on sun4i -Various other initialization changes Signed-off-by: Henrik Nordstrom hen...@henriknordstrom.net Signed-off-by: Stefan Roese s...@denx.de Signed-off-by: Oliver Schinagl oli...@schinagl.nl Signed-off-by: Hans de Goede hdego...@redhat.com Acked-by: Ian Campbell i...@hellion.org.uk ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2] spl: consolidate arch/arm/include/asm/arch-*/spl.h
On Wed, May 28, 2014 at 05:17:33PM +0200, Stefano Babic wrote:
On 23/04/2014 14:20, Masahiro Yamada wrote:
arch/arm/include/asm/spl.h requires all SoCs to have
arch/arm/include/asm/arch-*/spl.h.
But many of them just define BOOT_DEVICE_* macros.
Those macros are used in the switch (boot_device) { ... }
statement in common/spl/spl.c.
So they should not be archtecture specific, but be described as
a simpile enumeration.
This commit merges most of arch/arm/include/asm/arch-*/spl.h
into arch/arm/include/asm/spl.h.
With a little more effort, arch-zynq/spl.h and arch-socfpga/spl.h
will be merged, while I am not sure about OMAP and Exynos.
Signed-off-by: Masahiro Yamada yamad...@jp.panasonic.com
Cc: Tom Rini tr...@ti.com
Cc: Michal Simek michal.si...@xilinx.com
Cc: Andreas Bießmann andreas.de...@googlemail.com
Cc: Stephen Warren swar...@nvidia.com
Cc: Tom Warren twar...@nvidia.com
CC: Stefano Babic sba...@denx.de
CC: Minkyu Kang mk7.k...@samsung.com
Cc: Dinh Nguyen dingu...@altera.com
Acked-by: Andreas Bießmann andreas.de...@googlemail.com
Acked-by: Michal Simek mon...@monstr.eu
Acked-by: Stefano Babic sba...@denx.de
Acked-by: Stephen Warren swar...@nvidia.com
Acked-by: Tim Harvey thar...@gateworks.com
Tested-by: Bo Shen voice.s...@atmel.com [on sama5d3xek board for at91
part]
---
Tested-by: Stefano Babic sba...@denx.de [applying Tim's i.MX6 patches]
Tom, what about this patch ? Tim's patchset for SPL on i.MX6 depends on
this. Is it appliable ?
Acked-by: Tom Rini tr...@ti.com
Go ahead and bring it in via the imx tree.
--
Tom
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Re: [U-Boot] [PATCH v2 06/12] sunxi: Add sun5i support
On Tue, 2014-06-03 at 21:41 +0200, Hans de Goede wrote: Add support for the Allwinner A13 and A10s SoCs also know as the Allwinner sun5i family, and the A13-OLinuXinoM A13 based and r7-tv-dongle A10s based boards. The only differences compared to the already supported sun4i and sun7i families are all in the DRAM controller initialization: -Different hcpr values -Different MBUS settings -Some other small initialization changes Signed-off-by: Henrik Nordstrom hen...@henriknordstrom.net Signed-off-by: Stefan Roese s...@denx.de Signed-off-by: Oliver Schinagl oli...@schinagl.nl Signed-off-by: Hans de Goede hdego...@redhat.com Acked-by: Ian Campbell i...@hellion.org.uk ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [RESEND PATCH 1/3] Check run_command() return code properly
On 5 June 2014 12:07, Thomas Betker thomas.bet...@freenet.de wrote: run_command() returns 0 for success, 1 for failure. Fix places which assume that failure is indicated by a negative return code. Signed-off-by: Thomas Betker thomas.bet...@rohde-schwarz.com This has come through fine to patchwork - it may have been your missing name that was the problem. Acked-by: Simon Glass s...@chromium.org ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [RESEND PATCH 2/3] Add run_command_repeatable()
On 5 June 2014 12:07, Thomas Betker thomas.bet...@freenet.de wrote: run_command() returns 0 on success and 1 on error. However, there are some invocations which expect 0 or 1 for success (not repeatable or repeatable) and -1 for error; add run_command_repeatable() for this purpose. Signed-off-by: Thomas Betker thomas.bet...@rohde-schwarz.com I feel that a separate function is fine for now. Acked-by: Simon Glass s...@chromium.org Tested-by: Simon Glass s...@chromium.org ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [RESEND PATCH 3/3] Use run_command_repeatable()
On 5 June 2014 12:07, Thomas Betker thomas.bet...@freenet.de wrote: Replace run_command() by run_command_repeatable() in places which depend on the return code to indicate repeatability. Signed-off-by: Thomas Betker thomas.bet...@rohde-schwarz.com Acked-by: Simon Glass s...@chromium.org Tested-by: Simon Glass s...@chromium.org ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [RESEND PATCH 1/3] Check run_command() return code properly
On 5 June 2014 12:14, Simon Glass s...@chromium.org wrote: On 5 June 2014 12:07, Thomas Betker thomas.bet...@freenet.de wrote: run_command() returns 0 for success, 1 for failure. Fix places which assume that failure is indicated by a negative return code. Signed-off-by: Thomas Betker thomas.bet...@rohde-schwarz.com This has come through fine to patchwork - it may have been your missing name that was the problem. Acked-by: Simon Glass s...@chromium.org Tested-by: Simon Glass s...@chromium.org ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] error when building env
On Mon, May 19, 2014 at 02:14:03PM +0200, Luka Perkov wrote: Hi Tom, On Fri, May 16, 2014 at 01:58:05PM -0400, Tom Rini wrote: On Fri, May 16, 2014 at 07:26:51PM +0200, Luka Perkov wrote: when trying to build env with -mfloat-abi=hard I'm hitting this error: /opt/openwrt/trunk/staging_dir/toolchain-arm_cortex-a9+neon_gcc-4.8-linaro_uClibc-0.9.33.2_eabi/bin/arm-openwrt-linux-uclibcgnueabi-gcc -o tools/env/fw_printenv_unstripped tools/env/fw_env.o tools/env/fw_env_main.o tools/env/crc32.o tools/env/ctype.o tools/env/linux_string.o tools/env/env_attr.o tools/env/env_flags.o tools/env/aes.o /opt/build/owrt_staging_dir/toolchain-arm_cortex-a9+neon_gcc-4.8-linaro_uClibc-0.9.33.2_eabi/bin/../lib/gcc/arm-openwrt-linux-uclibcgnueabi/4.8.3/../../../../arm-openwrt-linux-uclibcgnueabi/bin/ld: error: tools/env/fw_printenv_unstripped uses VFP register arguments, tools/env/fw_env.o does not Odd. I can build 'tools-only' with my hard float toolchain fine. Can you build with V=1 and see what files are perhaps not getting passed in a -mfloat option? The patch below fixes the problem I was having. Is that good enough for proper patch submission? With it I am able to use replace default HOSTCFLAGS with what was defined in TARGET_CFLAGS. Luka diff --git a/tools/env/Makefile b/tools/env/Makefile index f5368bc..4de1d51 100644 --- a/tools/env/Makefile +++ b/tools/env/Makefile @@ -10,6 +10,10 @@ # with CC here for the maximum code reuse of scripts/Makefile.host. HOSTCC = $(CC) +ifneq ($(TARGET_CFLAGS),) +HOSTCFLAGS = $(TARGET_CFLAGS) +endif + # Compile for a hosted environment on the target HOST_EXTRACFLAGS = $(patsubst -I%,-idirafter%, $(UBOOTINCLUDE)) \ -idirafter $(srctree)/tools/env \ This still seems odd. Masahiro? -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 0/4] Improve/fix tests for commands and trace
A recent bug reported showed that the built-in CLI was not correctly handling repeatable commands. A recent series fixes this. http://patchwork.ozlabs.org/patch/356568/ http://patchwork.ozlabs.org/patch/356569/ http://patchwork.ozlabs.org/patch/356507/ Add a simple test for this. At present we require sandbox's config to be changed to use the hush or the simple parser. In the fullness of time when the parser code allows both to be compiled in, we may be able to adjust the test to do both tests. In order to make this work, we need to skip Ctrl-C in sandbox, so add a CONFIG option and environment variable to deal with this. The trace test is broken due a change done as part of the Kbuild work, so rename that also. Simon Glass (4): Reactivate the tracing feature Add ctrlc_ignore environment variable to ignore Ctrl-C test: Remove tabs from trace test test: Add a test for command repeat README| 3 +++ common/console.c | 28 ++-- config.mk | 4 include/configs/sandbox.h | 1 + include/env_callback.h| 7 +++ test/cmd_repeat.sh| 29 + test/common.sh| 20 test/trace/test-trace.sh | 42 ++ 8 files changed, 100 insertions(+), 34 deletions(-) create mode 100755 test/cmd_repeat.sh create mode 100644 test/common.sh -- 2.0.0.526.g5318336 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 3/4] test: Remove tabs from trace test
These cause U-Boot to print a list of available commands. It doesn't break
the test, but it is best to remove them from the output.
Signed-off-by: Simon Glass s...@chromium.org
---
test/trace/test-trace.sh | 22 +++---
1 file changed, 11 insertions(+), 11 deletions(-)
diff --git a/test/trace/test-trace.sh b/test/trace/test-trace.sh
index aa02f09..973063c 100755
--- a/test/trace/test-trace.sh
+++ b/test/trace/test-trace.sh
@@ -27,17 +27,17 @@ build_uboot() {
run_trace() {
echo Run trace
./${OUTPUT_DIR}/u-boot END
- trace stats
- hash sha256 0 1
- trace pause
- trace stats
- hash sha256 0 1
- trace stats
- trace resume
- hash sha256 0 1
- trace pause
- trace stats
- reset
+trace stats
+hash sha256 0 1
+trace pause
+trace stats
+hash sha256 0 1
+trace stats
+trace resume
+hash sha256 0 1
+trace pause
+trace stats
+reset
END
}
--
2.0.0.526.g5318336
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[U-Boot] [PATCH 4/4] test: Add a test for command repeat
This performs a command, then repeats it, and checks that the repeat
happens.
Signed-off-by: Simon Glass s...@chromium.org
---
test/cmd_repeat.sh | 29 +
test/common.sh | 20
test/trace/test-trace.sh | 20 +++-
3 files changed, 52 insertions(+), 17 deletions(-)
create mode 100755 test/cmd_repeat.sh
create mode 100644 test/common.sh
diff --git a/test/cmd_repeat.sh b/test/cmd_repeat.sh
new file mode 100755
index 000..990e799
--- /dev/null
+++ b/test/cmd_repeat.sh
@@ -0,0 +1,29 @@
+#!/bin/sh
+
+# Test for U-Boot cli including command repeat
+
+BASE=$(dirname $0)
+. $BASE/common.sh
+
+run_test() {
+ ./${OUTPUT_DIR}/u-boot END
+setenv ctrlc_ignore y
+md 0
+
+reset
+END
+}
+check_results() {
+ echo Check results
+
+ grep -q 0100 ${tmp} || fail Command did not repeat
+}
+
+echo Test CLI repeat
+echo
+tmp=$(tempfile)
+build_uboot
+run_test ${tmp}
+check_results ${tmp}
+rm ${tmp}
+echo Test passed
diff --git a/test/common.sh b/test/common.sh
new file mode 100644
index 000..702d1ed
--- /dev/null
+++ b/test/common.sh
@@ -0,0 +1,20 @@
+#!/bin/sh
+
+OUTPUT_DIR=sandbox
+
+fail() {
+ echo Test failed: $1
+ if [ -n ${tmp} ]; then
+ rm ${tmp}
+ fi
+ exit 1
+}
+
+build_uboot() {
+ echo Build sandbox
+ OPTS=O=${OUTPUT_DIR} $1
+ NUM_CPUS=$(grep -c processor /proc/cpuinfo)
+ echo ${OPTS}
+ make ${OPTS} sandbox_config
+ make ${OPTS} -s -j${NUM_CPUS}
+}
diff --git a/test/trace/test-trace.sh b/test/trace/test-trace.sh
index 973063c..3e8651e 100755
--- a/test/trace/test-trace.sh
+++ b/test/trace/test-trace.sh
@@ -5,24 +5,10 @@
# Simple test script for tracing with sandbox
-OUTPUT_DIR=sandbox
TRACE_OPT=FTRACE=1
-fail() {
- echo Test failed: $1
- if [ -n ${tmp} ]; then
- rm ${tmp}
- fi
- exit 1
-}
-
-build_uboot() {
- echo Build sandbox
- OPTS=O=${OUTPUT_DIR} ${TRACE_OPT}
- NUM_CPUS=$(grep -c processor /proc/cpuinfo)
- make ${OPTS} sandbox_config
- make ${OPTS} -s -j${NUM_CPUS}
-}
+BASE=$(dirname $0)/..
+. $BASE/common.sh
run_trace() {
echo Run trace
@@ -69,7 +55,7 @@ check_results() {
echo Simple trace test / sanity check using sandbox
echo
tmp=$(tempfile)
-build_uboot
+build_uboot ${TRACE_OPT}
run_trace ${tmp}
check_results ${tmp}
rm ${tmp}
--
2.0.0.526.g5318336
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[U-Boot] [PATCH 1/4] Reactivate the tracing feature
This was lost sometime in the Kbuild conversion. Add it back. Check that the trace test now passes: $ ./test/trace/test-trace.sh Simple trace test / sanity check using sandbox /tmp/filemHKPGw Build sandbox O=sandbox FTRACE=1 GEN /home/sjg/c/src/third_party/u-boot/files/sandbox/Makefile Configuring for sandbox board... Check results Test passed Signed-off-by: Simon Glass s...@chromium.org --- config.mk | 4 1 file changed, 4 insertions(+) diff --git a/config.mk b/config.mk index 05864aa..0c45c09 100644 --- a/config.mk +++ b/config.mk @@ -46,6 +46,10 @@ ifdefBOARD sinclude $(srctree)/board/$(BOARDDIR)/config.mk# include board specific rules endif +ifdef FTRACE +PLATFORM_CPPFLAGS += -finstrument-functions -DFTRACE +endif + # RELFLAGS := $(PLATFORM_RELFLAGS) -- 2.0.0.526.g5318336 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [Patch v4 2/5] ARMv8: Adjust MMU setup
On 06/05/2014 10:41 AM, Mark Rutland wrote:
On Thu, Jun 05, 2014 at 04:07:17PM +0100, York Sun wrote:
On 06/05/2014 03:09 AM, Mark Rutland wrote:
On Wed, Jun 04, 2014 at 05:27:30PM +0100, York Sun wrote:
On 06/02/2014 11:01 AM, Mark Rutland wrote:
On Mon, Jun 02, 2014 at 05:06:13PM +0100, York Sun wrote:
On 06/02/2014 04:34 AM, Mark Rutland wrote:
On Thu, May 29, 2014 at 09:49:05PM +0100, York Sun wrote:
Make MMU functions reusable. Platform code can setup its own MMU
tables.
What exactly does platform code need to setup its own tables for?
The general ARMv8 MMU table is not detail enough to control memory
attribute
like cache for all addresses. We have devices mapping to addresses with
different requirement for cache control.
And there are no APIs for creating device mappings rather than exporting
the raw pagetable accessors and hard-coding them differently in every
board file?
That's a good question. At this point, only two platforms are using ARMv8
code.
I am expecting FSL ARMv8 implementation will stay similar, i.e. covered by
the
file I added. If that's not the case, or more ARMv8 SoCs need special MMU
table,
we then should introduce such API. Having a full function MMU API may be an
overkill for U-boot. We don't need dynamic MMU anyway.
Maybe. It just seems to me that it would be possible to pre-allocate an
empty table that we could place device (nGnRnE?) mappings in. Then all
you'd need to call from board code is a function to map a range, rather
than having to duplicate logic for creating the tables you want.
It sounds good, but not the case. For the three level tables I am using
(level0,
level1, level2), I don't have level2 table for every address, that will be
too
many. Instead, I have a lot of blocks for level1. When I need some fine
control
within a level1 block range, I have to create a new level2 table. It is
doable,
but I will hold on that if I can use static table.
While my suggestion might not be the best, I'm not sure I follow, unless
you always want to idmap devices?
If you don't idmap devices, then you can place all of the disparate
physical mappings within a single table unless you have very large
peripherals to map?
If you mean identical map as idmap, yes I am creating identical map for devices.
I got your point. For this particular SoC, if I can get it work with these
simple static tables, I will stay with them. But if I need to maintain the
tables for various SoCs, I will convert to dynamic API.
Also fix a typo of TCR_EL3_IPS_BITS in cache_v8.c.
Signed-off-by: York Sun york...@freescale.com
CC: David Feng feng...@phytium.com.cn
---
Change log:
v4: new patch, splitted from v3 2/4
Revise set_pgtable_section() to be reused by platform MMU code
Add inline function set_ttbr_tcr_mair() to be used by this and
platform mmu code
arch/arm/cpu/armv8/cache_v8.c| 49
--
arch/arm/include/asm/armv8/mmu.h | 23 ++
2 files changed, 43 insertions(+), 29 deletions(-)
diff --git a/arch/arm/cpu/armv8/cache_v8.c
b/arch/arm/cpu/armv8/cache_v8.c
index a96ecda..67dbd46 100644
--- a/arch/arm/cpu/armv8/cache_v8.c
+++ b/arch/arm/cpu/armv8/cache_v8.c
@@ -12,15 +12,14 @@
DECLARE_GLOBAL_DATA_PTR;
#ifndef CONFIG_SYS_DCACHE_OFF
-
-static void set_pgtable_section(u64 section, u64 memory_type)
+void set_pgtable_section(u64 *page_table, u64 index, u64 section,
+ u64 memory_type)
{
-u64 *page_table = (u64 *)gd-arch.tlb_addr;
u64 value;
-value = (section SECTION_SHIFT) | PMD_TYPE_SECT |
PMD_SECT_AF;
+value = section | PMD_TYPE_SECT | PMD_SECT_AF;
value |= PMD_ATTRINDX(memory_type);
-page_table[section] = value;
+page_table[index] = value;
}
/* to activate the MMU we need to set up virtual memory */
@@ -28,10 +27,13 @@ static void mmu_setup(void)
{
int i, j, el;
bd_t *bd = gd-bd;
+u64 *page_table = (u64 *)gd-arch.tlb_addr;
/* Setup an identity-mapping for all spaces */
-for (i = 0; i (PGTABLE_SIZE 3); i++)
-set_pgtable_section(i, MT_DEVICE_NGNRNE);
+for (i = 0; i (PGTABLE_SIZE 3); i++) {
+set_pgtable_section(page_table, i, i SECTION_SHIFT,
+MT_DEVICE_NGNRNE);
+}
/* Setup an identity-mapping for all RAM space */
for (i = 0; i CONFIG_NR_DRAM_BANKS; i++) {
@@ -39,36 +41,25 @@ static void mmu_setup(void)
ulong end = bd-bi_dram[i].start +
bd-bi_dram[i].size;
for (j = start SECTION_SHIFT;
j end SECTION_SHIFT; j++) {
-set_pgtable_section(j, MT_NORMAL);
+set_pgtable_section(page_table, j, j
SECTION_SHIFT,
+MT_NORMAL);
[U-Boot] [PATCH 2/4] Add ctrlc_ignore environment variable to ignore Ctrl-C
Sometimes it is useful to ignore Ctrl-C, because checking for it causes the
CLI to drop characters. In particular for tests involving sandbox, where
input commands are piped in, some commands will call ctrlc() which will
drop characters from the test script.
Add a CONFIG_SYS_CTRLC_IGNORE option which enables this variable. If the
variable is present (e.g. setenv ctrlc_ignore ignore) then no checking
for Ctrl-C will be performed.
Signed-off-by: Simon Glass s...@chromium.org
---
README| 3 +++
common/console.c | 28 ++--
include/configs/sandbox.h | 1 +
include/env_callback.h| 7 +++
4 files changed, 33 insertions(+), 6 deletions(-)
diff --git a/README b/README
index 6edb2e7..e25780e 100644
--- a/README
+++ b/README
@@ -3584,6 +3584,9 @@ Configuration Settings:
- CONFIG_SYS_PROMPT: This is what U-Boot prints on the console to
prompt for user input.
+- CONFIG_SYS_CTRLC_IGNORE: If enabled, then the console will only check for
+ Ctrl-C if the 'ctrlc_ignore environment variable is unset.
+
- CONFIG_SYS_CBSIZE: Buffer size for input from the Console
- CONFIG_SYS_PBSIZE: Buffer size for Console output
diff --git a/common/console.c b/common/console.c
index 5453726..607b96f 100644
--- a/common/console.c
+++ b/common/console.c
@@ -520,15 +520,31 @@ int vprintf(const char *fmt, va_list args)
}
/* test if ctrl-c was pressed */
-static int ctrlc_disabled = 0; /* see disable_ctrl() */
-static int ctrlc_was_pressed = 0;
+static bool ctrlc_ignore; /* ctrlc detection always disabled */
+static bool ctrlc_disabled;/* see disable_ctrl() */
+static bool ctrlc_was_pressed;
+
+#ifdef CONFIG_SYS_CTRLC_IGNORE
+static int on_ctrlc_ignore(const char *name, const char *value,
+ enum env_op op, int flags)
+{
+ if (value != NULL)
+ ctrlc_ignore = true;
+ else
+ ctrlc_ignore = false;
+
+ return 0;
+}
+U_BOOT_ENV_CALLBACK(ctrlc_ignore, on_ctrlc_ignore);
+#endif /* CONFIG_SYS_CTRLC_IGNORE */
+
int ctrlc(void)
{
- if (!ctrlc_disabled gd-have_console) {
+ if (!ctrlc_ignore !ctrlc_disabled gd-have_console) {
if (tstc()) {
switch (getc()) {
case 0x03: /* ^C - Control C */
- ctrlc_was_pressed = 1;
+ ctrlc_was_pressed = true;
return 1;
default:
break;
@@ -571,7 +587,7 @@ int disable_ctrlc(int disable)
{
int prev = ctrlc_disabled; /* save previous state */
- ctrlc_disabled = disable;
+ ctrlc_disabled = disable != 0;
return prev;
}
@@ -582,7 +598,7 @@ int had_ctrlc (void)
void clear_ctrlc(void)
{
- ctrlc_was_pressed = 0;
+ ctrlc_was_pressed = false;
}
#ifdef CONFIG_MODEM_SUPPORT_DEBUG
diff --git a/include/configs/sandbox.h b/include/configs/sandbox.h
index 6bb2546..36e92ff 100644
--- a/include/configs/sandbox.h
+++ b/include/configs/sandbox.h
@@ -54,6 +54,7 @@
#define CONFIG_CMD_FS_GENERIC
#define CONFIG_SYS_VSNPRINTF
+#define CONFIG_SYS_CTRLC_IGNORE
#define CONFIG_CMD_GPIO
#define CONFIG_SANDBOX_GPIO
diff --git a/include/env_callback.h b/include/env_callback.h
index f90a7fa..cdd6b1e 100644
--- a/include/env_callback.h
+++ b/include/env_callback.h
@@ -31,6 +31,12 @@
#define SPLASHIMAGE_CALLBACK
#endif
+#ifdef CONFIG_SYS_CTRLC_IGNORE
+#define CTRLC_IGNORE ctrlc_ignore:ctrlc_ignore,
+#else
+#define CTRLC_IGNORE
+#endif
+
/*
* This list of callback bindings is static, but may be overridden by defining
* a new association in the .callbacks environment variable.
@@ -40,6 +46,7 @@
baudrate:baudrate, \
bootfile:bootfile, \
loadaddr:loadaddr, \
+ CTRLC_IGNORE \
SILENT_CALLBACK \
SPLASHIMAGE_CALLBACK \
stdin:console,stdout:console,stderr:console, \
--
2.0.0.526.g5318336
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Re: [U-Boot] [PATCH v2 08/12] sunxi: Add axp209 pmic support
On Tue, 2014-06-03 at 21:41 +0200, Hans de Goede wrote:
+int axp209_set_ldo3(int mvolt)
+{
+ int cfg = axp209_mvolt_to_cfg(mvolt, 700, 2275, 25);
+
+ if (mvolt == -1)
+ cfg = 0x80; /* determined by LDO3IN pin */
Thus would seem more natural as
if (mvolt == -1)
cfg = 0x80; /* comment... */
else
cfg = axp209_mvolt_to_cfg(mvolt, 700, 2275, 25);
BTW, I've just noticed that cfg is often an int but axp209_write etc all
deal in u8's. Do you not want to be dealing with u8's throughout?
+void axp209_poweroff(void)
+{
+ u8 val;
+
+ if (axp209_read(AXP209_SHUTDOWN, val) != 0)
+ return;
+
+ val |= AXP209_POWEROFF;
+
+ if (axp209_write(AXP209_SHUTDOWN, val) != 0)
+ return;
+
+ udelay(1); /* wait for power to drain */
Is this essentially a wait to die loop? i.e. we expect power to
disappear while in the middle of it. In which case shouldn't it be
infinite? What would happen if we were to return from this function?
Nothing actually calls it AFAICT so maybe you can just punt on the whole
thing and drop the function for now...
Ian.
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Re: [U-Boot] error when building env
Hi, On do, 2014-06-05 at 14:25 -0400, Tom Rini wrote: On Mon, May 19, 2014 at 02:14:03PM +0200, Luka Perkov wrote: Hi Tom, On Fri, May 16, 2014 at 01:58:05PM -0400, Tom Rini wrote: On Fri, May 16, 2014 at 07:26:51PM +0200, Luka Perkov wrote: when trying to build env with -mfloat-abi=hard I'm hitting this error: /opt/openwrt/trunk/staging_dir/toolchain-arm_cortex-a9+neon_gcc-4.8-linaro_uClibc-0.9.33.2_eabi/bin/arm-openwrt-linux-uclibcgnueabi-gcc -o tools/env/fw_printenv_unstripped tools/env/fw_env.o tools/env/fw_env_main.o tools/env/crc32.o tools/env/ctype.o tools/env/linux_string.o tools/env/env_attr.o tools/env/env_flags.o tools/env/aes.o /opt/build/owrt_staging_dir/toolchain-arm_cortex-a9+neon_gcc-4.8-linaro_uClibc-0.9.33.2_eabi/bin/../lib/gcc/arm-openwrt-linux-uclibcgnueabi/4.8.3/../../../../arm-openwrt-linux-uclibcgnueabi/bin/ld: error: tools/env/fw_printenv_unstripped uses VFP register arguments, tools/env/fw_env.o does not Odd. I can build 'tools-only' with my hard float toolchain fine. Can you build with V=1 and see what files are perhaps not getting passed in a -mfloat option? The patch below fixes the problem I was having. Is that good enough for proper patch submission? With it I am able to use replace default HOSTCFLAGS with what was defined in TARGET_CFLAGS. Luka diff --git a/tools/env/Makefile b/tools/env/Makefile index f5368bc..4de1d51 100644 --- a/tools/env/Makefile +++ b/tools/env/Makefile @@ -10,6 +10,10 @@ # with CC here for the maximum code reuse of scripts/Makefile.host. HOSTCC = $(CC) +ifneq ($(TARGET_CFLAGS),) +HOSTCFLAGS = $(TARGET_CFLAGS) +endif + # Compile for a hosted environment on the target HOST_EXTRACFLAGS = $(patsubst -I%,-idirafter%, $(UBOOTINCLUDE)) \ -idirafter $(srctree)/tools/env \ This still seems odd. Masahiro? Yes is seems odd indeed, shouldn't it be unconditionally be part of the CROSS_BUILD_TOOLS check below? Since it switches compiler, but not related flags.. Regards, Jeroen ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 09/12] sunxi: Add axp152 pmic support
On Tue, 2014-06-03 at 21:41 +0200, Hans de Goede wrote: Add support for the x-powers axp152 pmic which is found on most A10s boards and enable it for the r7-tv-dongle board. Again just the same comments as on the axp209. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 11/12] sunxi: Add emac glue, enable emac on the cubieboard
On Tue, 2014-06-03 at 21:42 +0200, Hans de Goede wrote: Signed-off-by: Hans de Goede hdego...@redhat.com Acked-by: Ian Campbell i...@hellion.org.uk ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 12/12] sunxi: Add support for using MII phy-s with the GMAC nic
On Tue, 2014-06-03 at 21:42 +0200, Hans de Goede wrote: From: Chen-Yu Tsai w...@csie.org Many A20 boards (ie Cubieboard2, A20-OLinuXino_MICRO) use an 100 Mbit MII phy together with the GMAC nic found in the A20 SoC, add support for this (this will get used when we add these boards in a later patch). Signed-off-by: Chen-Yu Tsai w...@csie.org Signed-off-by: Hans de Goede hdego...@redhat.com Acked-by: Ian Campbell i...@hellion.org.uk ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-Boot, v5, 3/4] lib, fdt: move fdtdec_get_int() out of lib/fdtdec.c
On Wed, May 28, 2014 at 11:33:35AM +0200, Heiko Schocher wrote: move fdtdec_get_int() out of lib/fdtdec.c into lib/fdtdec_common.c as this function is also used, if CONFIG_OF_CONTROL is not used. Poped up on the ids8313 board using signed FIT images, and activating CONFIG_SYS_GENERIC_BOARD. Without this patch it shows on boot: No valid FDT found - please append one to U-Boot binary, use u-boot-dtb.bin or define CONFIG_OF_EMBED. For sandbox, use -d file.dtb With this patch, it boots again with CONFIG_SYS_GENERIC_BOARD enabled. Signed-off-by: Heiko Schocher h...@denx.de Acked-by: Simon Glass s...@chromium.org Cc: Tom Rini tr...@ti.com The problem is that on architectures with old compilers (sparc, blackfin, nds32) this doesn't get discarded due to not being used but instead causes link errors. Can you figure out which option (CONFIG_FIT_SIGNATURE I suspect) drives this need and make sure we include fdtdec_common.o then? Thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] U-boot hangs on imx6 pci driver
On Thu, Jun 5, 2014 at 2:53 PM, Marek Vasut ma...@denx.de wrote: Does this help? drivers/pci/pcie_imx.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/pci/pcie_imx.c b/drivers/pci/pcie_imx.c index c48737e..190cdec 100644 --- a/drivers/pci/pcie_imx.c +++ b/drivers/pci/pcie_imx.c @@ -435,8 +435,7 @@ static int imx6_pcie_init_phy(void) clrbits_le32(iomuxc_regs-gpr[12], IOMUXC_GPR12_APPS_LTSSM_ENABLE); clrsetbits_le32(iomuxc_regs-gpr[12], -IOMUXC_GPR12_DEVICE_TYPE_MASK, -IOMUXC_GPR12_DEVICE_TYPE_RC); +IOMUXC_GPR12_DEVICE_TYPE_MASK, 4 12); Is this the setting of RC-mode in GPR12 ? That's wrong in the FSL datasheet, not in the code IIRC ;-) Yes, RM is wrong. U-boot is setting it to 2. Kernel sets it to 4, which is the correct value. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [Patch v6 2/5] ARMv8: Adjust MMU setup
Make MMU function reusable. Platform code can setup its own MMU tables.
Signed-off-by: York Sun york...@freescale.com
CC: David Feng feng...@phytium.com.cn
---
Change log
v6: Modified from v4. Add dsb sy before setting MMU registers and add isb
after.
v5: Drop the addition of inline function set_pgtable_section() from v4
It is only used twice and causes confusion.
v4: new patch, splitted from v3 2/4
Revise set_pgtable_section() to be reused by platform MMU code
Add inline function set_ttbr_tcr_mair() to be used by this and platform
mmu code
arch/arm/cpu/armv8/cache_v8.c| 50 +++---
arch/arm/include/asm/armv8/mmu.h | 24 ++
2 files changed, 44 insertions(+), 30 deletions(-)
diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c
index a96ecda..af3c494 100644
--- a/arch/arm/cpu/armv8/cache_v8.c
+++ b/arch/arm/cpu/armv8/cache_v8.c
@@ -12,15 +12,14 @@
DECLARE_GLOBAL_DATA_PTR;
#ifndef CONFIG_SYS_DCACHE_OFF
-
-static void set_pgtable_section(u64 section, u64 memory_type)
+void set_pgtable_section(u64 *page_table, u64 index, u64 section,
+u64 memory_type)
{
- u64 *page_table = (u64 *)gd-arch.tlb_addr;
u64 value;
- value = (section SECTION_SHIFT) | PMD_TYPE_SECT | PMD_SECT_AF;
+ value = section | PMD_TYPE_SECT | PMD_SECT_AF;
value |= PMD_ATTRINDX(memory_type);
- page_table[section] = value;
+ page_table[index] = value;
}
/* to activate the MMU we need to set up virtual memory */
@@ -28,10 +27,13 @@ static void mmu_setup(void)
{
int i, j, el;
bd_t *bd = gd-bd;
+ u64 *page_table = (u64 *)gd-arch.tlb_addr;
/* Setup an identity-mapping for all spaces */
- for (i = 0; i (PGTABLE_SIZE 3); i++)
- set_pgtable_section(i, MT_DEVICE_NGNRNE);
+ for (i = 0; i (PGTABLE_SIZE 3); i++) {
+ set_pgtable_section(page_table, i, i SECTION_SHIFT,
+ MT_DEVICE_NGNRNE);
+ }
/* Setup an identity-mapping for all RAM space */
for (i = 0; i CONFIG_NR_DRAM_BANKS; i++) {
@@ -39,38 +41,26 @@ static void mmu_setup(void)
ulong end = bd-bi_dram[i].start + bd-bi_dram[i].size;
for (j = start SECTION_SHIFT;
j end SECTION_SHIFT; j++) {
- set_pgtable_section(j, MT_NORMAL);
+ set_pgtable_section(page_table, j, j SECTION_SHIFT,
+ MT_NORMAL);
}
}
/* load TTBR0 */
el = current_el();
if (el == 1) {
- asm volatile(msr ttbr0_el1, %0
-: : r (gd-arch.tlb_addr) : memory);
- asm volatile(msr tcr_el1, %0
-: : r (TCR_FLAGS | TCR_EL1_IPS_BITS)
-: memory);
- asm volatile(msr mair_el1, %0
-: : r (MEMORY_ATTRIBUTES) : memory);
+ set_ttbr_tcr_mair(el, gd-arch.tlb_addr,
+ TCR_FLAGS | TCR_EL1_IPS_BITS,
+ MEMORY_ATTRIBUTES);
} else if (el == 2) {
- asm volatile(msr ttbr0_el2, %0
-: : r (gd-arch.tlb_addr) : memory);
- asm volatile(msr tcr_el2, %0
-: : r (TCR_FLAGS | TCR_EL2_IPS_BITS)
-: memory);
- asm volatile(msr mair_el2, %0
-: : r (MEMORY_ATTRIBUTES) : memory);
+ set_ttbr_tcr_mair(el, gd-arch.tlb_addr,
+ TCR_FLAGS | TCR_EL2_IPS_BITS,
+ MEMORY_ATTRIBUTES);
} else {
- asm volatile(msr ttbr0_el3, %0
-: : r (gd-arch.tlb_addr) : memory);
- asm volatile(msr tcr_el3, %0
-: : r (TCR_FLAGS | TCR_EL2_IPS_BITS)
-: memory);
- asm volatile(msr mair_el3, %0
-: : r (MEMORY_ATTRIBUTES) : memory);
+ set_ttbr_tcr_mair(el, gd-arch.tlb_addr,
+ TCR_FLAGS | TCR_EL3_IPS_BITS,
+ MEMORY_ATTRIBUTES);
}
-
/* enable the mmu */
set_sctlr(get_sctlr() | CR_M);
}
diff --git a/arch/arm/include/asm/armv8/mmu.h b/arch/arm/include/asm/armv8/mmu.h
index 1193e76..4b7b67b 100644
--- a/arch/arm/include/asm/armv8/mmu.h
+++ b/arch/arm/include/asm/armv8/mmu.h
@@ -108,4 +108,28 @@
TCR_IRGN_WBWA | \
TCR_T0SZ(VA_BITS))
+#ifndef __ASSEMBLY__
+void set_pgtable_section(u64 *page_table, u64 index,
+u64 section, u64 memory_type);
+static inline void set_ttbr_tcr_mair(int el, u64 table, u64 tcr, u64
[U-Boot] [Patch v6 3/5] ARMv8/FSL_LSCH3: Add FSL_LSCH3 SoC
Freescale LayerScape with Chassis Generation 3 is a set of SoCs with
ARMv8 cores and 3rd generation of Chassis. We use different MMU setup
to support memory map and cache attribute for these SoCs. MMU and cache
are enabled very early to bootst performance, especially for early
development on emulators. After u-boot relocates to DDR, a new MMU
table with QBMan cache access is created in DDR. SMMU pagesize is set
in SMMU_sACR register. Both DDR3 and DDR4 are supported.
Signed-off-by: York Sun york...@freescale.com
Signed-off-by: Varun Sethi varun.se...@freescale.com
Signed-off-by: Arnab Basu arnab.b...@freescale.com
---
Change log
v6: Add dsb sy before setting TTBR and add isb after.
v5: Revise the 2nd MMU table code to use the same macros
Only change TTBR to point to new MMU table without rewriting MAIR, TCR
v4: Slit ARMv8 MMU change to another patch, v4 2/5
Add more comment for final MMU table setup
Remove mmu.h added in v3 and v2
Remove GICv2 macro testing in lowlevel.S
Rename function init_type() to initiator_type()
Use ARMv8 generic timer code
v3: Remove blank lines at the of files
Fix cluster PLL GSR register for accessing beyond array size
Update final MMU table to support QBMan memory with cache
Set SMMU pagesize in SMMU_sACR register in lowlevel init.
Add DDR4 support
Remove forcing L3 cache flusing
Update GICv3 redistributor base address
Some of these changes are caused by model change.
arch/arm/cpu/armv8/cache_v8.c |7 +-
arch/arm/cpu/armv8/fsl-lsch3/Makefile |9 +
arch/arm/cpu/armv8/fsl-lsch3/README | 10 +
arch/arm/cpu/armv8/fsl-lsch3/cpu.c| 420 +
arch/arm/cpu/armv8/fsl-lsch3/cpu.h|7 +
arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S | 65
arch/arm/cpu/armv8/fsl-lsch3/speed.c | 176 +
arch/arm/cpu/armv8/fsl-lsch3/speed.h |7 +
arch/arm/include/asm/arch-fsl-lsch3/clock.h | 23 ++
arch/arm/include/asm/arch-fsl-lsch3/config.h | 65
arch/arm/include/asm/arch-fsl-lsch3/gpio.h|9 +
arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h | 116 ++
arch/arm/include/asm/arch-fsl-lsch3/imx-regs.h| 13 +
arch/arm/include/asm/config.h |4 +
arch/arm/include/asm/system.h |2 +
drivers/i2c/mxc_i2c.c |5 +
include/common.h |5 +-
17 files changed, 939 insertions(+), 4 deletions(-)
create mode 100644 arch/arm/cpu/armv8/fsl-lsch3/Makefile
create mode 100644 arch/arm/cpu/armv8/fsl-lsch3/README
create mode 100644 arch/arm/cpu/armv8/fsl-lsch3/cpu.c
create mode 100644 arch/arm/cpu/armv8/fsl-lsch3/cpu.h
create mode 100644 arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S
create mode 100644 arch/arm/cpu/armv8/fsl-lsch3/speed.c
create mode 100644 arch/arm/cpu/armv8/fsl-lsch3/speed.h
create mode 100644 arch/arm/include/asm/arch-fsl-lsch3/clock.h
create mode 100644 arch/arm/include/asm/arch-fsl-lsch3/config.h
create mode 100644 arch/arm/include/asm/arch-fsl-lsch3/gpio.h
create mode 100644 arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h
create mode 100644 arch/arm/include/asm/arch-fsl-lsch3/imx-regs.h
diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c
index af3c494..9dbcdf2 100644
--- a/arch/arm/cpu/armv8/cache_v8.c
+++ b/arch/arm/cpu/armv8/cache_v8.c
@@ -73,12 +73,17 @@ void invalidate_dcache_all(void)
__asm_invalidate_dcache_all();
}
+void __weak flush_l3_cache(void)
+{
+}
+
/*
* Performs a clean invalidation of the entire data cache at all levels
*/
void flush_dcache_all(void)
{
__asm_flush_dcache_all();
+ flush_l3_cache();
}
/*
@@ -211,7 +216,7 @@ void invalidate_icache_all(void)
* Enable dCache iCache, whether cache is actually enabled
* depend on CONFIG_SYS_DCACHE_OFF and CONFIG_SYS_ICACHE_OFF
*/
-void enable_caches(void)
+void __weak enable_caches(void)
{
icache_enable();
dcache_enable();
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/Makefile
b/arch/arm/cpu/armv8/fsl-lsch3/Makefile
new file mode 100644
index 000..9249537
--- /dev/null
+++ b/arch/arm/cpu/armv8/fsl-lsch3/Makefile
@@ -0,0 +1,9 @@
+#
+# Copyright 2014, Freescale Semiconductor
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += cpu.o
+obj-y += lowlevel.o
+obj-y += speed.o
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/README
b/arch/arm/cpu/armv8/fsl-lsch3/README
new file mode 100644
index 000..de34a91
--- /dev/null
+++ b/arch/arm/cpu/armv8/fsl-lsch3/README
@@ -0,0 +1,10 @@
+#
+# Copyright 2014 Freescale Semiconductor
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+Freescale LayerScape with Chassis Generation 3
+
+This architecture supports Freescale ARMv8 SoCs with Chassis generation 3,
+for example LS2100A.
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c
[U-Boot] [Patch v6 1/5] Added 64-bit MMIO accessors for ARMv8
From: J. German Rivera german.riv...@freescale.com
This is needed for accessing peripherals with 64-bit MMIO registers,
from ARMv8 processors.
Signed-off-by: J. German Rivera german.riv...@freescale.com
---
Change log
v6: no change
v5: no change
v4: no change
v3: no change
arch/arm/include/asm/io.h |8
1 file changed, 8 insertions(+)
diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h
index 6a1f05a..95528dd 100644
--- a/arch/arm/include/asm/io.h
+++ b/arch/arm/include/asm/io.h
@@ -70,10 +70,12 @@ static inline phys_addr_t virt_to_phys(void * vaddr)
#define __arch_getb(a) (*(volatile unsigned char *)(a))
#define __arch_getw(a) (*(volatile unsigned short *)(a))
#define __arch_getl(a) (*(volatile unsigned int *)(a))
+#define __arch_getq(a) (*(volatile unsigned long long *)(a))
#define __arch_putb(v,a) (*(volatile unsigned char *)(a) = (v))
#define __arch_putw(v,a) (*(volatile unsigned short *)(a) = (v))
#define __arch_putl(v,a) (*(volatile unsigned int *)(a) = (v))
+#define __arch_putq(v,a) (*(volatile unsigned long long *)(a) =
(v))
extern inline void __raw_writesb(unsigned long addr, const void *data,
int bytelen)
@@ -123,10 +125,12 @@ extern inline void __raw_readsl(unsigned long addr, void
*data, int longlen)
#define __raw_writeb(v,a) __arch_putb(v,a)
#define __raw_writew(v,a) __arch_putw(v,a)
#define __raw_writel(v,a) __arch_putl(v,a)
+#define __raw_writeq(v,a) __arch_putq(v,a)
#define __raw_readb(a) __arch_getb(a)
#define __raw_readw(a) __arch_getw(a)
#define __raw_readl(a) __arch_getl(a)
+#define __raw_readq(a) __arch_getq(a)
/*
* TODO: The kernel offers some more advanced versions of barriers, it might
@@ -139,10 +143,12 @@ extern inline void __raw_readsl(unsigned long addr, void
*data, int longlen)
#define writeb(v,c)({ u8 __v = v; __iowmb(); __arch_putb(__v,c); __v; })
#define writew(v,c)({ u16 __v = v; __iowmb(); __arch_putw(__v,c); __v; })
#define writel(v,c)({ u32 __v = v; __iowmb(); __arch_putl(__v,c); __v; })
+#define writeq(v,c)({ u64 __v = v; __iowmb(); __arch_putq(__v,c); __v; })
#define readb(c) ({ u8 __v = __arch_getb(c); __iormb(); __v; })
#define readw(c) ({ u16 __v = __arch_getw(c); __iormb(); __v; })
#define readl(c) ({ u32 __v = __arch_getl(c); __iormb(); __v; })
+#define readq(c) ({ u64 __v = __arch_getq(c); __iormb(); __v; })
/*
* The compiler seems to be incapable of optimising constants
@@ -168,9 +174,11 @@ extern inline void __raw_readsl(unsigned long addr, void
*data, int longlen)
#define out_arch(type,endian,a,v) __raw_write##type(cpu_to_##endian(v),a)
#define in_arch(type,endian,a) endian##_to_cpu(__raw_read##type(a))
+#define out_le64(a,v) out_arch(q,le64,a,v)
#define out_le32(a,v) out_arch(l,le32,a,v)
#define out_le16(a,v) out_arch(w,le16,a,v)
+#define in_le64(a) in_arch(q,le64,a)
#define in_le32(a) in_arch(l,le32,a)
#define in_le16(a) in_arch(w,le16,a)
--
1.7.9.5
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[U-Boot] [Patch v6 5/5] ARMv8/ls2100a_emu: Add LS2100A emulator and simulator board support
LS2100A is an ARMv8 implementation. This adds board support for emulator
and simulator:
Two DDR controllers
UART2 is used as the console
IFC timing is tightened for speedy booting
Support DDR3 and DDR4 as separated targets
Management Complex (MC) is enabled
Signed-off-by: York Sun york...@freescale.com
Signed-off-by: Arnab Basu arnab.b...@freescale.com
Signed-off-by: J. German Rivera german.riv...@freescale.com
Signed-off-by: Bhupesh Sharma bhupesh.sha...@freescale.com
---
Change log
v6: no change
v5: no change
v4: no change
v3: Add support for DDR4 target and simulator target
Squash Manage complex patch (previous 5/5) into this
Reserve last 512MB memory for MC use
Change MC firmware location in NOR flash
Fix UART clock source speed
Update IFC address mux
Use generic board
Disable DDR memory beyound 39 physical address space due to Linux
limitation
board/freescale/ls2100a/Makefile |8 ++
board/freescale/ls2100a/README| 16 +++
board/freescale/ls2100a/ddr.c | 175
board/freescale/ls2100a/ddr.h | 57 ++
board/freescale/ls2100a/ls2100a.c | 100
boards.cfg|3 +
include/configs/ls2100a_common.h | 226 +
include/configs/ls2100a_emu.h | 19
include/configs/ls2100a_simu.h| 16 +++
9 files changed, 620 insertions(+)
create mode 100644 board/freescale/ls2100a/Makefile
create mode 100644 board/freescale/ls2100a/README
create mode 100644 board/freescale/ls2100a/ddr.c
create mode 100644 board/freescale/ls2100a/ddr.h
create mode 100644 board/freescale/ls2100a/ls2100a.c
create mode 100644 include/configs/ls2100a_common.h
create mode 100644 include/configs/ls2100a_emu.h
create mode 100644 include/configs/ls2100a_simu.h
diff --git a/board/freescale/ls2100a/Makefile b/board/freescale/ls2100a/Makefile
new file mode 100644
index 000..c8da338
--- /dev/null
+++ b/board/freescale/ls2100a/Makefile
@@ -0,0 +1,8 @@
+#
+# Copyright 2014 Freescale Semiconductor
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += ls2100a.o
+obj-y += ddr.o
diff --git a/board/freescale/ls2100a/README b/board/freescale/ls2100a/README
new file mode 100644
index 000..9a8a618
--- /dev/null
+++ b/board/freescale/ls2100a/README
@@ -0,0 +1,16 @@
+Freescale ls2100a_emu
+
+This is a emulator target with limited peripherals.
+
+Memory map from core's view
+
+0x00__ .. 0x00_000F_ Boot Rom
+0x00_0100_ .. 0x00_0FFF_ CCSR
+0x00_1800_ .. 0x00_181F_ OCRAM
+0x00_3000_ .. 0x00_3FFF_ IFC region #1
+0x00_8000_ .. 0x00__ DDR region #1
+0x05_1000_ .. 0x05__ IFC region #2
+0x80_8000_ .. 0xFF__ DDR region #2
+
+Other addresses are either reserved, or not used directly by u-boot.
+This list should be updated when more addresses are used.
diff --git a/board/freescale/ls2100a/ddr.c b/board/freescale/ls2100a/ddr.c
new file mode 100644
index 000..257bc16
--- /dev/null
+++ b/board/freescale/ls2100a/ddr.c
@@ -0,0 +1,175 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include fsl_ddr_sdram.h
+#include fsl_ddr_dimm_params.h
+#include ddr.h
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+ dimm_params_t *pdimm,
+ unsigned int ctrl_num)
+{
+ const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
+ ulong ddr_freq;
+
+ if (ctrl_num 3) {
+ printf(Not supported controller number %d\n, ctrl_num);
+ return;
+ }
+ if (!pdimm-n_ranks)
+ return;
+
+ /*
+* we use identical timing for all slots. If needed, change the code
+* to pbsp = rdimms[ctrl_num] or pbsp = udimms[ctrl_num];
+*/
+ if (popts-registered_dimm_en)
+ pbsp = rdimms[0];
+ else
+ pbsp = udimms[0];
+
+
+ /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr
+* freqency and n_banks specified in board_specific_parameters table.
+*/
+ ddr_freq = get_ddr_freq(0) / 100;
+ while (pbsp-datarate_mhz_high) {
+ if (pbsp-n_ranks == pdimm-n_ranks
+ (pdimm-rank_density 30) = pbsp-rank_gb) {
+ if (ddr_freq = pbsp-datarate_mhz_high) {
+ popts-clk_adjust = pbsp-clk_adjust;
+ popts-wrlvl_start = pbsp-wrlvl_start;
+ popts-wrlvl_ctl_2 = pbsp-wrlvl_ctl_2;
+ popts-wrlvl_ctl_3 = pbsp-wrlvl_ctl_3;
+ goto found;
+ }
+ pbsp_highest = pbsp;
+ }
+ pbsp++;
+
[U-Boot] [Patch v6 4/5] armv8/fsl-lsch3: Add support to load and start MC Firmware
From: J. German Rivera german.riv...@freescale.com
Adding support to load and start the Layerscape Management Complex (MC)
firmware. First, the MC GCR register is set to 0 to reset all cores. MC
firmware and DPL images are copied from their location in NOR flash to
DDR. MC registers are updated with the location of these images.
Deasserting the reset bit of MC GCR register releases core 0 to run.
Core 1 will be released by MC firmware. Stop bits are not touched for
this step. U-boot waits for MC until it boots up. In case of a failure,
device tree is updated accordingly. The MC firmware image uses FIT format.
Signed-off-by: J. German Rivera german.riv...@freescale.com
Signed-off-by: York Sun york...@freescale.com
Signed-off-by: Lijun Pan lijun@freescale.com
Signed-off-by: Shruti Kanetkar shr...@freescale.com
---
Change log
v6: no change
v5: Fix a typo in commit message supoort
Fix variable declaration cause by squashing patches
v4: no change
v3: Add error detection and update device tree if failure
Revise loading address to avoid overlap
Use FIT image for the firmware
Remove blank lines at the end of files
README | 27
arch/arm/cpu/armv8/fsl-lsch3/cpu.c | 11 ++
drivers/net/Makefile |1 +
drivers/net/fsl_mc/Makefile|8 ++
drivers/net/fsl_mc/mc.c| 272
include/fdt_support.h | 14 +-
include/fsl_mc.h | 59
7 files changed, 389 insertions(+), 3 deletions(-)
create mode 100644 drivers/net/fsl_mc/Makefile
create mode 100644 drivers/net/fsl_mc/mc.c
create mode 100644 include/fsl_mc.h
diff --git a/README b/README
index a280435..95a0282 100644
--- a/README
+++ b/README
@@ -4640,6 +4640,33 @@ within that device.
window-master inbound window-master LAW-the ucode address in
master's memory space.
+Freescale Layerscape Management Complex Firmware Support:
+-
+The Freescale Layerscape Management Complex (MC) supports the loading of
+firmware.
+This firmware often needs to be loaded during U-Boot booting, so macros
+are used to identify the storage device (NOR flash, SPI, etc) and the address
+within that device.
+
+- CONFIG_FSL_MC_ENET
+ Enable the MC driver for Layerscape SoCs.
+
+- CONFIG_SYS_LS_MC_FW_ADDR
+ The address in the storage device where the firmware is located. The
+ meaning of this address depends on which CONFIG_SYS_LS_MC_FW_IN_xxx
macro
+ is also specified.
+
+- CONFIG_SYS_LS_MC_FW_LENGTH
+ The maximum possible size of the firmware. The firmware binary format
+ has a field that specifies the actual size of the firmware, but it
+ might not be possible to read any part of the firmware unless some
+ local storage is allocated to hold the entire firmware first.
+
+- CONFIG_SYS_LS_MC_FW_IN_NOR
+ Specifies that MC firmware is located in NOR flash, mapped as
+ normal addressable memory via the LBC. CONFIG_SYS_LS_MC_FW_ADDR is the
+ virtual address in NOR flash.
+
Building the Software:
==
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c
b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c
index e8ce50c..32146ac 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c
@@ -12,6 +12,7 @@
#include asm/arch-fsl-lsch3/immap_lsch3.h
#include cpu.h
#include speed.h
+#include fsl_mc.h
DECLARE_GLOBAL_DATA_PTR;
@@ -418,3 +419,13 @@ int print_cpuinfo(void)
return 0;
}
#endif
+
+int cpu_eth_init(bd_t *bis)
+{
+ int error = 0;
+
+#ifdef CONFIG_FSL_MC_ENET
+ error = mc_init(bis);
+#endif
+ return error;
+}
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 6005f7e..6226cb2 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -64,3 +64,4 @@ obj-$(CONFIG_XILINX_EMACLITE) += xilinx_emaclite.o
obj-$(CONFIG_XILINX_LL_TEMAC) += xilinx_ll_temac.o xilinx_ll_temac_mdio.o \
xilinx_ll_temac_fifo.o xilinx_ll_temac_sdma.o
obj-$(CONFIG_ZYNQ_GEM) += zynq_gem.o
+obj-$(CONFIG_FSL_MC_ENET) += fsl_mc/
diff --git a/drivers/net/fsl_mc/Makefile b/drivers/net/fsl_mc/Makefile
new file mode 100644
index 000..4834086
--- /dev/null
+++ b/drivers/net/fsl_mc/Makefile
@@ -0,0 +1,8 @@
+#
+# Copyright 2014 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+# Layerscape MC driver
+obj-y += mc.o
diff --git a/drivers/net/fsl_mc/mc.c b/drivers/net/fsl_mc/mc.c
new file mode 100644
index 000..056424b
--- /dev/null
+++ b/drivers/net/fsl_mc/mc.c
@@ -0,0 +1,272 @@
+/*
+ * Copyright (C) 2014 Freescale Semiconductor
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+#include errno.h
+#include asm/io.h
+#include fsl_mc.h
+
+DECLARE_GLOBAL_DATA_PTR;
+static int mc_boot_status;
+
+/**
+ * Copying MC firmware or DPL image to DDR
+ */
+static int mc_copy_image(const char *title,
+
[U-Boot] [PATCH] driver/ddr/fsl: Fix printing unspecified module info for DDR4
The offset of module information is at 128, different from DDR3. Signed-off-by: York Sun york...@freescale.com --- drivers/ddr/fsl/interactive.c |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/ddr/fsl/interactive.c b/drivers/ddr/fsl/interactive.c index cfe1e1f..0681933 100644 --- a/drivers/ddr/fsl/interactive.c +++ b/drivers/ddr/fsl/interactive.c @@ -1578,7 +1578,7 @@ void ddr4_spd_dump(const struct ddr4_spd_eeprom_s *spd) printf(%-3d-%3d: , 128, 255); for (i = 128; i = 255; i++) - printf(%02x, spd-mod_section.uc[i - 60]); + printf(%02x, spd-mod_section.uc[i - 128]); break; } -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [GIT] Pull request: u-boot-dfu
On Monday, May 26, 2014 at 07:46:27 AM, Lukasz Majewski wrote: Hi Marek The following changes since commit fc25fa27e5f439705e9ca42182014e2d75d9f0ae: dfu, nand: add medium specific polltimeout function (2014-05-08 10:38:30 +0200) are available in the git repository at: ssh://gu-...@git.denx.de/u-boot-dfu master for you to fetch changes up to 03bc75c206e25e8aeb8070b86424f7860453: dfu: Introduction of the dfu_hash_algo env variable for checksum method setting (2014-05-26 07:31:54 +0200) Lukasz Majewski (1): dfu: Introduction of the dfu_hash_algo env variable for checksum method setting I had merge conflict here, so I picked the one patch by hand. Thanks! Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [Patch v3] powerpc/mpc85xx: Add workaround for DDR erratum A004508
When the DDR controller is initialized below a junction temperature of 0°C and then operated above a junction temperature of 65°C, the DDR controller may cause receive data errors, resulting ECC errors and/or corrupted data. This erratum applies to the following SoCs and their variants: MPC8536, MPC8569, MPC8572, P1010, P1020, P1021, P1022, P1023, P2020. Signed-off-by: York Sun york...@freescale.com --- Change log v3: Fix the error of closing curly bracket caused by v2. v2: Remove warning if workaround is not enabled. arch/powerpc/cpu/mpc85xx/cmd_errata.c |3 +++ arch/powerpc/include/asm/config_mpc85xx.h | 18 ++ drivers/ddr/fsl/ctrl_regs.c |5 + 3 files changed, 26 insertions(+) diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c index 3d37a76..f69c834 100644 --- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c +++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c @@ -231,6 +231,9 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0)) puts(Work-around for Erratum NMG ETSEC129 enabled\n); #endif +#ifdef CONFIG_SYS_FSL_ERRATUM_A004508 + puts(Work-around for Erratum A004508 enabled\n); +#endif #ifdef CONFIG_SYS_FSL_ERRATUM_A004510 puts(Work-around for Erratum A004510 enabled\n); #endif diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 34fc8fb..c9fd2a5 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -38,6 +38,7 @@ #define CONFIG_SYS_PPC_E500_DEBUG_TLB 1 #define CONFIG_SYS_FSL_SEC_COMPAT 2 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff70 +#define CONFIG_SYS_FSL_ERRATUM_A004508 #define CONFIG_SYS_FSL_ERRATUM_A005125 #elif defined(CONFIG_MPC8540) @@ -122,6 +123,7 @@ #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 #define CONFIG_SYS_FSL_RMU #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 +#define CONFIG_SYS_FSL_ERRATUM_A004508 #define CONFIG_SYS_FSL_ERRATUM_A005125 #elif defined(CONFIG_MPC8572) @@ -132,6 +134,7 @@ #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff70 #define CONFIG_SYS_FSL_ERRATUM_DDR_115 #define CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 +#define CONFIG_SYS_FSL_ERRATUM_A004508 #define CONFIG_SYS_FSL_ERRATUM_A005125 #elif defined(CONFIG_P1010) @@ -154,6 +157,7 @@ #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399 #define CONFIG_SYS_FSL_ERRATUM_A005125 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 +#define CONFIG_SYS_FSL_ERRATUM_A004508 #define CONFIG_SYS_FSL_ERRATUM_A007075 #define CONFIG_SYS_FSL_ERRATUM_A006261 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x10 @@ -171,6 +175,7 @@ #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff70 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 +#define CONFIG_SYS_FSL_ERRATUM_A004508 #define CONFIG_SYS_FSL_ERRATUM_A005125 /* P1012 is single core version of P1021 */ @@ -188,6 +193,7 @@ #define QE_MURAM_SIZE 0x6000UL #define MAX_QE_RISC1 #define QE_NUM_OF_SNUM 28 +#define CONFIG_SYS_FSL_ERRATUM_A004508 #define CONFIG_SYS_FSL_ERRATUM_A005125 /* P1013 is single core version of P1022 */ @@ -202,6 +208,7 @@ #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define CONFIG_FSL_SATA_ERRATUM_A001 +#define CONFIG_SYS_FSL_ERRATUM_A004508 #define CONFIG_SYS_FSL_ERRATUM_A005125 #elif defined(CONFIG_P1014) @@ -219,6 +226,7 @@ #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769 #define CONFIG_SYS_FSL_ERRATUM_P1010_A003549 #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399 +#define CONFIG_SYS_FSL_ERRATUM_A004508 /* P1017 is single core version of P1023 */ #elif defined(CONFIG_P1017) @@ -234,6 +242,7 @@ #define CONFIG_SYS_FM_MURAM_SIZE 0x1 #define CONFIG_SYS_FSL_PCIE_COMPAT fsl,qoriq-pcie-v2.2 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff60 +#define CONFIG_SYS_FSL_ERRATUM_A004508 #define CONFIG_SYS_FSL_ERRATUM_A005125 #elif defined(CONFIG_P1020) @@ -246,6 +255,7 @@ #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff70 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 +#define CONFIG_SYS_FSL_ERRATUM_A004508 #define CONFIG_SYS_FSL_ERRATUM_A005125 #ifndef CONFIG_USB_MAX_CONTROLLER_COUNT #define CONFIG_USB_MAX_CONTROLLER_COUNT2 @@ -264,6 +274,7 @@ #define QE_MURAM_SIZE 0x6000UL #define MAX_QE_RISC1 #define QE_NUM_OF_SNUM 28 +#define CONFIG_SYS_FSL_ERRATUM_A004508 #define CONFIG_SYS_FSL_ERRATUM_A005125 #define CONFIG_USB_MAX_CONTROLLER_COUNT1 @@ -278,6 +289,7 @@ #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define CONFIG_FSL_SATA_ERRATUM_A001 +#define CONFIG_SYS_FSL_ERRATUM_A004508 #define CONFIG_SYS_FSL_ERRATUM_A005125 #elif defined(CONFIG_P1023) @@ -293,6 +305,7 @@ #define
[U-Boot] Please pull u-boot-mpc85xx master
Tom, The following changes since commit 9a650bfec34c10baf673f9ab95f00dec7210e8c6: Merge branch 'master' of git://git.denx.de/u-boot-avr32 (2014-06-05 11:22:17 -0400) are available in the git repository at: git://git.denx.de/u-boot-mpc85xx.git master for you to fetch changes up to 353527d527b78297571c05b8a1687c92d42f6d20: driver/ddr/fsl: Fix printing unspecified module info for DDR4 (2014-06-05 13:45:07 -0700) Chunhe Lan (1): powerpc/t4rdb: Add alternate serdes protocols to align with A-007186 Hou Zhiqiang (1): powerpc/espi: remove 80us delay to improve transfer performance Sandeep Singh (1): powerpc/mpc85xx: Add workaround to enable TDM on T1040 Shaohui Xie (1): powerpc/t4qds: Add alternate serdes protocols to align with A-007186 Shaveta Leekha (1): powerpc/serdes: Add the workaround for erratum A-007186 Shengzhou Liu (3): board/t208x: update t2080qds/t2080rdb for errata A-007186 board/t2080qds: some update for ddr powerpc/t2080: add serdes2 protocol 0x27 York Sun (2): powerpc/mpc85xx: Add workaround for DDR erratum A004508 driver/ddr/fsl: Fix printing unspecified module info for DDR4 poonam aggrwal (1): powerpc/B4420: Fixed incomplete handling for 0x9d serdes2 arch/powerpc/cpu/mpc85xx/cmd_errata.c |6 + arch/powerpc/cpu/mpc85xx/cpu_init.c| 29 arch/powerpc/cpu/mpc85xx/fdt.c | 26 arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c | 148 arch/powerpc/cpu/mpc85xx/t1040_ids.c |1 + arch/powerpc/cpu/mpc85xx/t2080_serdes.c| 27 +++- arch/powerpc/cpu/mpc85xx/t4240_serdes.c| 172 arch/powerpc/include/asm/config_mpc85xx.h | 24 arch/powerpc/include/asm/fsl_law.h |1 + arch/powerpc/include/asm/fsl_liodn.h |4 + arch/powerpc/include/asm/immap_85xx.h | 37 - board/freescale/b4860qds/b4860qds.c|6 + board/freescale/t208xqds/ddr.h | 28 ++-- board/freescale/t208xqds/eth_t208xqds.c|8 ++ board/freescale/t208xqds/t2080_rcw.cfg |2 +- board/freescale/t208xqds/t208xqds.c| 12 +- board/freescale/t208xrdb/t2080_rcw.cfg |2 +- board/freescale/t4qds/eth.c| 20 +++ board/freescale/t4qds/t4240qds.c | 27 board/freescale/t4qds/t4_rcw.cfg |4 +- board/freescale/t4rdb/eth.c|2 +- board/freescale/t4rdb/t4_rcw.cfg |4 +- drivers/ddr/fsl/ctrl_regs.c|5 + drivers/ddr/fsl/interactive.c |2 +- drivers/spi/fsl_espi.c | 138 ++- include/configs/T1040QDS.h |6 + include/configs/T104xRDB.h |6 + include/configs/T208xQDS.h |5 +- 28 files changed, 683 insertions(+), 69 deletions(-) Thanks, York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 2/4] Add ctrlc_ignore environment variable to ignore Ctrl-C
Dear Simon Glass, In message 1401992872-31985-3-git-send-email-...@chromium.org you wrote: Sometimes it is useful to ignore Ctrl-C, because checking for it causes the CLI to drop characters. In particular for tests involving sandbox, where input commands are piped in, some commands will call ctrlc() which will drop characters from the test script. Why would that be the case? If this happens, I consider it a bug that should be fixed, and not papered over. Add a CONFIG_SYS_CTRLC_IGNORE option which enables this variable. If the variable is present (e.g. setenv ctrlc_ignore ignore) then no checking for Ctrl-C will be performed. I dislike this idea. It looks wrong to me. Can we not fix the problem at the root cause? Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de Nothing difficult is ever easy. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] U-boot hangs on imx6 pci driver
On Thursday, June 05, 2014 at 09:20:12 PM, Fabio Estevam wrote: On Thu, Jun 5, 2014 at 2:53 PM, Marek Vasut ma...@denx.de wrote: Does this help? drivers/pci/pcie_imx.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/pci/pcie_imx.c b/drivers/pci/pcie_imx.c index c48737e..190cdec 100644 --- a/drivers/pci/pcie_imx.c +++ b/drivers/pci/pcie_imx.c @@ -435,8 +435,7 @@ static int imx6_pcie_init_phy(void) clrbits_le32(iomuxc_regs-gpr[12], IOMUXC_GPR12_APPS_LTSSM_ENABLE); clrsetbits_le32(iomuxc_regs-gpr[12], -IOMUXC_GPR12_DEVICE_TYPE_MASK, -IOMUXC_GPR12_DEVICE_TYPE_RC); +IOMUXC_GPR12_DEVICE_TYPE_MASK, 4 12); Is this the setting of RC-mode in GPR12 ? That's wrong in the FSL datasheet, not in the code IIRC ;-) Yes, RM is wrong. U-boot is setting it to 2. Kernel sets it to 4, which is the correct value. Ah yes, 0x4 is correct, I stand corrected, sorry. Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] U-boot hangs on imx6 pci driver
On Thu, Jun 5, 2014 at 7:04 PM, Marek Vasut ma...@denx.de wrote: Ah yes, 0x4 is correct, I stand corrected, sorry. No problem. I will submit a patch for it soon. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] U-boot hangs on imx6 pci driver
On Friday, June 06, 2014 at 12:14:03 AM, Fabio Estevam wrote: On Thu, Jun 5, 2014 at 7:04 PM, Marek Vasut ma...@denx.de wrote: Ah yes, 0x4 is correct, I stand corrected, sorry. No problem. I will submit a patch for it soon. Thanks! Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] mxs: fixed battery boot on imx233-olinuxino-micro
On Wednesday, May 21, 2014 at 04:01:55 AM, Peter Schumann wrote: This patch makes it possible to boot from battery on olinuxino Boards from Olimex. We should not set DOUBLE_FETS in HW_POWER_MINPWR, it makes my system reset with in seconds while running on battery power. Also mxs_power_enable_4p2() should not be called if running from battery. It switches VDDD and VDDA to LinReg mode and than turns off the VDDIO DCDC supply. At this point the system resets. If we run on battery this is no good idea because the LinRegs are chained behind VDDIO and battery voltage seems not enough to power the system from LinRegs. Also is the power system already running on DCDC after BootROM hands over to u-boot, so no sense in switching back to LinRegs. Sorry for the late reply, I'm somewhat congested recently. In the meantime, I was not able to test this yet. But you're missing Signed-off-by: line, can you please re-send this with a proper SoB line [1] ? [1] http://www.denx.de/wiki/U-Boot/Patches#General_Patch_Submission_Rules Thanks Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] mx6: Fix definition of IOMUXC_GPR12_DEVICE_TYPE_RC
From: Fabio Estevam fabio.este...@freescale.com mx6 reference manual incorrectly states that the DEVICE_TYPE field of IOMUXC_GPR12 register should be configured as '0010' for setting the PCI controller in RC mode. The correct value should be '0100' instead. This also aligns with the same value used in the mx6 pci kernel driver. Signed-off-by: Fabio Estevam fabio.este...@freescale.com --- arch/arm/include/asm/arch-mx6/iomux.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/include/asm/arch-mx6/iomux.h b/arch/arm/include/asm/arch-mx6/iomux.h index f9ee0d9..6a4a632 100644 --- a/arch/arm/include/asm/arch-mx6/iomux.h +++ b/arch/arm/include/asm/arch-mx6/iomux.h @@ -39,7 +39,7 @@ #define IOMUXC_GPR12_LOS_LEVEL_MASK(0x1f 4) #define IOMUXC_GPR12_APPS_LTSSM_ENABLE (1 10) #define IOMUXC_GPR12_DEVICE_TYPE_EP(0x0 12) -#define IOMUXC_GPR12_DEVICE_TYPE_RC(0x2 12) +#define IOMUXC_GPR12_DEVICE_TYPE_RC(0x4 12) #define IOMUXC_GPR12_DEVICE_TYPE_MASK (0xf 12) /* -- 1.8.3.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] arm: fdt_control: fix a build error with CONFIG_OF_EMBED=y
On Fri, Apr 25, 2014 at 09:51:09PM +0900, Masahiro Yamada wrote: The build fails if a non-generic ARM board is compiled with CONFIG_OF_EMBED=y. The correct symbol name for embedded FDT is not __dtb_db_begin, but __dtb_dt_begin. (A typo introduced by commit 6ab6b2af) Signed-off-by: Masahiro Yamada yamad...@jp.panasonic.com Acked-by: Simon Glass s...@chromium.org Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-Boot, v2, 1/2] mkimage : Split out and clean pbl_crc32 for use by other image types
On Wed, May 14, 2014 at 02:45:00PM +1200, Charles Manning wrote: The crc32 used by pblimgae is NOT the same as zlib crc32. The pbl_crc32 is useful for other purposes in mkimage so split it out. While we are about it, clean up redundant and confusing code. Signed-off-by: Charles Manning cdhmann...@gmail.com Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-Boot,1/2] kbuild: remove unused RANLIB
On Mon, May 12, 2014 at 11:45:54AM +0900, Masahiro Yamada wrote: RANLIB was added by commit e221174 (more than a decade ago) but it has been never referenced at all. Signed-off-by: Masahiro Yamada yamad...@jp.panasonic.com Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-Boot, 1/2] openrisc: update SPR registers definition
On Wed, May 21, 2014 at 10:43:49PM +0200, Franck Jullien wrote: The OpenRISC architecture specification v1.0 defines new SPR registers. This patch adds registers definition for group 0 and update bit definitions for the CPU configuration register. Signed-off-by: Franck Jullien franck.jull...@gmail.com Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] phy: fix create_phy_by_mask for when its given an actual search mask
On Wed, May 21, 2014 at 01:08:52PM -0400, Cormier, Jonathan wrote: From: Cormier, Jonathan jcorm...@criticallink.com get_phy_id returns -EIO when it can't read from a phy at a given addr. This would cause create_phy_by_mask to return prematurely before it had tested the other addresses in the provided mask. Example usage: Replace phydev = phy_connect(bus, phy_addr, dev, phy_if) with phydev = phy_find_by_mask(bus, phy_mask, phy_if) if (phydev) phy_connect_dev(phydev, dev); Signed-off-by: Cormier, Jonathan jcorm...@criticallink.com Cc: Joe Hershberger joe.hershber...@gmail.com Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-Boot, v2, 2/2] tools: Refactor mxsimage to use pbl_crc32
On Wed, May 14, 2014 at 02:45:01PM +1200, Charles Manning wrote: Both pblimage and mxsimage use the same crc algorithm, so refactor. Signed-off-by: Charles Manning cdhmann...@gmail.com Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-Boot,2/2] kbuild: add missing PERL definition
On Mon, May 12, 2014 at 11:45:55AM +0900, Masahiro Yamada wrote: checkstack target uses $(PERL) so PERL must be defined. Signed-off-by: Masahiro Yamada yamad...@jp.panasonic.com Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Prevent a stack overflow in fit_check_sign
On Tue, May 20, 2014 at 03:58:58PM +0200, Michael van der Westhuizen wrote: It is trivial to crash fit_check_sign by invoking with an absolute path in a deeply nested directory. This is exposed by vboot_test.sh. Signed-off-by: Michael van der Westhuizen mich...@smart-africa.com Acked-by: Simon Glass s...@chromium.org Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] boards.cfg: fix a configuration error of ep8248 board again
On Mon, May 26, 2014 at 07:42:14PM +0900, Masahiro Yamada wrote: make ep8248_config fails with an error like this: $ make ep8248_config make: *** [ep8248_config] Error 1 Its cause is that there are two entries for ep8248. The first is around line 661 of boards.cfg. (as Active) The second appears around line 1242. (as Orphan) This bug was originally introduced by commit e7e90901 and I fixed it by commit 8ad5d45e. (Refer to git-log of commit 8ad5d45e) But this bug was re-introduced by commit 05d134b0 because the custodian made a mistake when he resolved a merge conflict. Signed-off-by: Masahiro Yamada yamad...@jp.panasonic.com Cc: Albert ARIBAUD albert.u.b...@aribaud.net Cc: Heiko Schocher h...@denx.de Cc: Kim Phillips kim.phill...@linaro.org Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-Boot, v3] fat: Define MAX_CLUSTSIZE using CONFIG_FS_FAT_MAX_CLUSTSIZE
On Mon, May 26, 2014 at 07:18:37PM +0530, Siva Durga Prasad Paladugu wrote: Define the MAX_CLUSTSIZE to default of 65536 only if CONFIG_FS_FAT_MAX_CLUSTSIZE is not defined. This option has been provided to save memory in some memory constrained cases. Signed-off-by: Siva Durga Prasad Paladugu siva...@xilinx.com Acked-by: Michal Simek mon...@monstr.eu Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-Boot, v2] env_eeprom: Assign default environment during board_init_f
On Mon, May 26, 2014 at 07:51:22PM +0530, Siva Durga Prasad Paladugu wrote: Assign default environment and set env valid during board_init_f before relocation as the actual environment will be read from eeprom later. Signed-off-by: Siva Durga Prasad Paladugu siva...@xilinx.com Acked-by: Michal Simek mon...@monstr.eu Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
