Re: [U-Boot] [PATCH] blackfin, powerpc: remove redundant definitions of ARRAY_SIZE
Acked-by: Sonic Zhang sonic.zh...@analog.com Thanks, Sonic -Original Message- From: Masahiro Yamada [mailto:yamad...@jp.panasonic.com] Sent: Thursday, July 03, 2014 12:56 PM To: u-boot@lists.denx.de Cc: Masahiro Yamada; Stefan Roese; Zhang, Sonic Subject: [PATCH] blackfin,powerpc: remove redundant definitions of ARRAY_SIZE Since ARRAY_SIZE macro is defined in include/common.h, re-defining it in arch- specific files is redundant. Signed-off-by: Masahiro Yamada yamad...@jp.panasonic.com Cc: Stefan Roese s...@denx.de Cc: Sonic Zhang sonic.zh...@analog.com --- I built all Blackfin and Powerpc boards. I confirmed this patch has no bad impact. arch/blackfin/include/asm/config-pre.h | 3 --- arch/powerpc/cpu/ppc4xx/speed.c| 2 -- 2 files changed, 5 deletions(-) diff --git a/arch/blackfin/include/asm/config-pre.h b/arch/blackfin/include/asm/config- pre.h index d0fd537..2d8b293 100644 --- a/arch/blackfin/include/asm/config-pre.h +++ b/arch/blackfin/include/asm/config-pre.h @@ -9,9 +9,6 @@ #ifndef __ASM_BLACKFIN_CONFIG_PRE_H__ #define __ASM_BLACKFIN_CONFIG_PRE_H__ -/* Misc helper functions */ -#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) - /* Bootmode defines -- your config needs to select this via CONFIG_BFIN_BOOT_MODE. * Depending on your cpu, some of these may not be valid, check your HRM. * The actual values here are meaningless as long as they're unique. diff --git a/arch/powerpc/cpu/ppc4xx/speed.c b/arch/powerpc/cpu/ppc4xx/speed.c index 7e077d5..4baee77 100644 --- a/arch/powerpc/cpu/ppc4xx/speed.c +++ b/arch/powerpc/cpu/ppc4xx/speed.c @@ -19,8 +19,6 @@ DECLARE_GLOBAL_DATA_PTR; #define DEBUGF(fmt,args...) #endif -#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) - #if defined(CONFIG_405GP) void get_sys_info (PPC4xx_SYS_INFO * sysInfo) -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] U-Boot: Enhancement request to get flash device specific information
Hi U-boot team, I am looking for u-boot command which can give me flash device specific properties. For example, there should be dedicated commands to get the flash memory size, sector size, page size etc. Currently I found there is command sf probe for spi flash device which is returning device properties into text format as below: SF : Detected N25Q128A with page size 256 Bytes, erase size 64 KiB, total 16 MiB Similarly I found there is command nand info for nand device which is also returning device properties into text format. These commands (sf probe and nand info) are giving device information in form of message. Which does not meet my requirement. Actually I would like to integrate u-boot with my tool, where tool will run u-boot command to get the device information. Based on device information tool will react. Here I am looking for some dedicated command which return these property separately. It is difficult to parse the message string to get individual Let say we includes following commands: nand info pagesize/sectorsize/size/device sf info pagesize/sectorsize/size/device for example: nand info pagesize command should return page size ( e.g. *256*) nand info sectorsize command should return sector size (e.g. *65536* which is 64K) nand info size command should return the total size (e.g. *268435456 *which is 16 MB) Could you please consider this enhancement request in u-boot? Please comment. Regards, Heera ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3 0/13] Fixes on gdsys boards and some new functionality
From: Dirk Eibach dirk.eib...@gdsys.cc Changes in v3: - describe ihs_i2c in README Changes in v2: - make sha256 support optional - move ihs_i2c to drivers/i2c - split unrelated changes - use defines for I2C bus numbers Dirk Eibach (13): board: controlcenterd: Fix pci access board: gdsys: Adapt sdhc_boot.c to mmc_get_env_addr API change board: controlcenterd: Use new API for setting i2c bus board: iocon: Support DisplayPort hardware i2c: IHS I2C master driver board: gdsys: Fix dlvision-10g I2C configuration board: gdsys: Increase iocon and dlv10g version string board: gdsys: Configure bridge on DP501 to support DDC only board: gdsys: Make gdsys osd hardware detection more robust board: gdsys: Enable scrambling on DP501 board: iocon: Modify iocon hardware startup board: gdsys: Remove commands to reduce footprint fit: make sha256 support optional README| 15 +++ board/gdsys/405ep/iocon.c | 14 ++- board/gdsys/common/Makefile | 2 +- board/gdsys/common/dp501.c| 35 -- board/gdsys/common/osd.c | 189 +++ board/gdsys/p1022/controlcenterd-id.c | 13 ++- board/gdsys/p1022/controlcenterd.c| 6 +- board/gdsys/p1022/sdhc_boot.c | 2 +- drivers/i2c/Makefile | 1 + drivers/i2c/ihs_i2c.c | 203 ++ include/configs/controlcenterd.h | 7 +- include/configs/dlvision-10g.h| 29 - include/configs/io.h | 8 +- include/configs/iocon.h | 35 -- include/configs/neo.h | 9 +- include/gdsys_fpga.h | 25 ++--- include/image.h | 5 + 17 files changed, 449 insertions(+), 149 deletions(-) create mode 100644 drivers/i2c/ihs_i2c.c -- 1.8.3 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3 02/13] board: gdsys: Adapt sdhc_boot.c to mmc_get_env_addr API change
From: Dirk Eibach dirk.eib...@gdsys.cc
Signed-off-by: Dirk Eibach dirk.eib...@gdsys.cc
---
Changes in v3: None
Changes in v2: None
board/gdsys/p1022/sdhc_boot.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/board/gdsys/p1022/sdhc_boot.c b/board/gdsys/p1022/sdhc_boot.c
index e432318..fd0e910 100644
--- a/board/gdsys/p1022/sdhc_boot.c
+++ b/board/gdsys/p1022/sdhc_boot.c
@@ -32,7 +32,7 @@
#define ESDHC_BOOT_IMAGE_SIZE 0x48
#define ESDHC_BOOT_IMAGE_ADDR 0x50
-int mmc_get_env_addr(struct mmc *mmc, u32 *env_addr)
+int mmc_get_env_addr(struct mmc *mmc, int copy, u32 *env_addr)
{
u8 *tmp_buf;
u32 blklen, code_offset, code_len, n;
--
1.8.3
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[U-Boot] [PATCH v3 03/13] board: controlcenterd: Use new API for setting i2c bus
From: Dirk Eibach dirk.eib...@gdsys.cc
Signed-off-by: Dirk Eibach dirk.eib...@gdsys.cc
---
Changes in v3: None
Changes in v2:
- use defines for I2C bus numbers
board/gdsys/p1022/controlcenterd-id.c | 13 +
1 file changed, 9 insertions(+), 4 deletions(-)
diff --git a/board/gdsys/p1022/controlcenterd-id.c
b/board/gdsys/p1022/controlcenterd-id.c
index 3fca3c5..419fc2e 100644
--- a/board/gdsys/p1022/controlcenterd-id.c
+++ b/board/gdsys/p1022/controlcenterd-id.c
@@ -86,6 +86,11 @@ enum {
ESDHC_BOOT_IMAGE_ENTRY_OFS = 0x60,
};
+enum {
+ I2C_SOC_0 = 0,
+ I2C_SOC_1 = 1,
+};
+
struct key_program {
uint32_t magic;
uint32_t code_crc;
@@ -1156,7 +1161,7 @@ static void ccdm_hang(void)
int j;
#endif
- I2C_SET_BUS(0);
+ I2C_SET_BUS(I2C_SOC_0);
pca9698_direction_output(0x22, 0, 0); /* Finder */
pca9698_direction_output(0x22, 4, 0); /* Status */
@@ -1189,8 +1194,8 @@ int startup_ccdm_id_module(void)
int result = 0;
unsigned int orig_i2c_bus;
- orig_i2c_bus = I2C_GET_BUS();
- I2C_SET_BUS(1);
+ orig_i2c_bus = i2c_get_bus_num();
+ i2c_set_bus_num(I2C_SOC_1);
/* goto end; */
@@ -1216,7 +1221,7 @@ int startup_ccdm_id_module(void)
failure:
result = 1;
end:
- I2C_SET_BUS(orig_i2c_bus);
+ i2c_set_bus_num(orig_i2c_bus);
if (result)
ccdm_hang();
--
1.8.3
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[U-Boot] [PATCH v3 12/13] board: gdsys: Remove commands to reduce footprint
From: Dirk Eibach dirk.eib...@gdsys.cc Commit 2842c1c fit: add sha256 support badly increased memory footprint, so some of our boards did not build anymore. Since monitor base must not be changed I removed some commands to save memory. Maybe making sha256 optional for fit would be an option for the future since it really has some beefy footprint. Signed-off-by: Dirk Eibach dirk.eib...@gdsys.cc --- Changes in v3: None Changes in v2: None include/configs/dlvision-10g.h | 7 ++- include/configs/io.h | 7 ++- include/configs/iocon.h| 4 include/configs/neo.h | 8 ++-- 4 files changed, 22 insertions(+), 4 deletions(-) diff --git a/include/configs/dlvision-10g.h b/include/configs/dlvision-10g.h index 08ab5c3..2567a22 100644 --- a/include/configs/dlvision-10g.h +++ b/include/configs/dlvision-10g.h @@ -64,9 +64,14 @@ /* * Commands additional to the ones defined in amcc-common.h */ -#define CONFIG_CMD_CACHE #define CONFIG_CMD_DTT +#undef CONFIG_CMD_DHCP +#undef CONFIG_CMD_DIAG #undef CONFIG_CMD_EEPROM +#undef CONFIG_CMD_ELF +#undef CONFIG_CMD_I2C +#undef CONFIG_CMD_IRQ +#undef CONFIG_CMD_NFS /* * SDRAM configuration (please see cpu/ppc/sdram.[ch]) diff --git a/include/configs/io.h b/include/configs/io.h index 9da6cc6..649c0fb 100644 --- a/include/configs/io.h +++ b/include/configs/io.h @@ -64,9 +64,14 @@ /* * Commands additional to the ones defined in amcc-common.h */ -#define CONFIG_CMD_CACHE #define CONFIG_CMD_DTT +#undef CONFIG_CMD_DHCP +#undef CONFIG_CMD_DIAG #undef CONFIG_CMD_EEPROM +#undef CONFIG_CMD_ELF +#undef CONFIG_CMD_I2C +#undef CONFIG_CMD_IRQ +#undef CONFIG_CMD_NFS /* * SDRAM configuration (please see cpu/ppc/sdram.[ch]) diff --git a/include/configs/iocon.h b/include/configs/iocon.h index 1836d12..35ba1bd 100644 --- a/include/configs/iocon.h +++ b/include/configs/iocon.h @@ -64,6 +64,10 @@ #define CONFIG_CMD_CACHE #define CONFIG_CMD_FPGAD #undef CONFIG_CMD_EEPROM +#undef CONFIG_CMD_ELF +#undef CONFIG_CMD_I2C +#undef CONFIG_CMD_IRQ +#undef CONFIG_CMD_NFS /* * SDRAM configuration (please see cpu/ppc/sdram.[ch]) diff --git a/include/configs/neo.h b/include/configs/neo.h index d549985..75dc862 100644 --- a/include/configs/neo.h +++ b/include/configs/neo.h @@ -61,10 +61,14 @@ /* * Commands additional to the ones defined in amcc-common.h */ -#define CONFIG_CMD_CACHE -#define CONFIG_CMD_DATE #define CONFIG_CMD_DTT +#undef CONFIG_CMD_DHCP +#undef CONFIG_CMD_DIAG #undef CONFIG_CMD_EEPROM +#undef CONFIG_CMD_ELF +#undef CONFIG_CMD_I2C +#undef CONFIG_CMD_IRQ +#undef CONFIG_CMD_NFS /* * SDRAM configuration (please see cpu/ppc/sdram.[ch]) -- 1.8.3 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3 07/13] board: gdsys: Increase iocon and dlv10g version string
From: Dirk Eibach dirk.eib...@gdsys.cc Signed-off-by: Dirk Eibach dirk.eib...@gdsys.cc --- Changes in v3: None Changes in v2: None include/configs/dlvision-10g.h | 2 +- include/configs/iocon.h| 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/include/configs/dlvision-10g.h b/include/configs/dlvision-10g.h index 16895bf..c2289ce 100644 --- a/include/configs/dlvision-10g.h +++ b/include/configs/dlvision-10g.h @@ -17,7 +17,7 @@ * Include common defines/options for all AMCC eval boards */ #define CONFIG_HOSTNAMEdlvsion-10g -#define CONFIG_IDENT_STRING dlvision-10g 0.05 +#define CONFIG_IDENT_STRING dlvision-10g 0.06 #include amcc-common.h #define CONFIG_BOARD_EARLY_INIT_F diff --git a/include/configs/iocon.h b/include/configs/iocon.h index 36b4b55..1aebab3 100644 --- a/include/configs/iocon.h +++ b/include/configs/iocon.h @@ -17,7 +17,7 @@ * Include common defines/options for all AMCC eval boards */ #define CONFIG_HOSTNAMEiocon -#define CONFIG_IDENT_STRING iocon 0.05 +#define CONFIG_IDENT_STRING iocon 0.06 #include amcc-common.h #define CONFIG_BOARD_EARLY_INIT_F -- 1.8.3 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3 08/13] board: gdsys: Configure bridge on DP501 to support DDC only
From: Dirk Eibach dirk.eib...@gdsys.cc
The I2C bridge on DP501 supports EDID, MCCS and HDCP by default.
Allow EDID only to avoid I2C address conflicts.
Signed-off-by: Dirk Eibach dirk.eib...@gdsys.cc
---
Changes in v3: None
Changes in v2: None
board/gdsys/common/dp501.c | 1 +
include/configs/controlcenterd.h | 7 ---
2 files changed, 5 insertions(+), 3 deletions(-)
diff --git a/board/gdsys/common/dp501.c b/board/gdsys/common/dp501.c
index e00e589..7958bae 100644
--- a/board/gdsys/common/dp501.c
+++ b/board/gdsys/common/dp501.c
@@ -54,6 +54,7 @@ static void dp501_link_training(u8 addr)
void dp501_powerup(u8 addr)
{
dp501_clrbits(addr, 0x0a, 0x30); /* power on encoder */
+ dp501_setbits(addr, 0x0a, 0x0e); /* block HDCP and MCCS on I2C bride*/
i2c_reg_write(addr, 0x27, 0x30); /* Hardware auto detect DVO timing */
dp501_setbits(addr, 0x72, 0x80); /* DPCD read enable */
dp501_setbits(addr, 0x30, 0x20); /* RS polynomial select */
diff --git a/include/configs/controlcenterd.h b/include/configs/controlcenterd.h
index 868813f..ec3145f 100644
--- a/include/configs/controlcenterd.h
+++ b/include/configs/controlcenterd.h
@@ -199,9 +199,10 @@
#define CONFIG_SYS_FSL_I2C2_SPEED 40
#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
-/* Probing DP501 I2C-Bridge will hang */
-#define CONFIG_SYS_I2C_NOPROBES{ {0, 0x30}, {0, 0x37}, {0,
0x3a}, \
- {0, 0x3b}, {0, 0x50} }
+
+#ifndef CONFIG_TRAILBLAZER
+#define CONFIG_CMD_I2C
+#endif
#define CONFIG_PCA9698 /* NXP PCA9698 */
--
1.8.3
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[U-Boot] [PATCH v3 04/13] board: iocon: Support DisplayPort hardware
From: Dirk Eibach dirk.eib...@gdsys.cc
There is a new iocon hardware flavor, supporting DisplayPort finally.
Signed-off-by: Dirk Eibach dirk.eib...@gdsys.cc
---
Changes in v3: None
Changes in v2: None
board/gdsys/405ep/iocon.c | 12 +
board/gdsys/common/Makefile | 2 +-
board/gdsys/common/dp501.c | 33 +
board/gdsys/common/osd.c| 112
include/configs/iocon.h | 9 +++-
5 files changed, 83 insertions(+), 85 deletions(-)
diff --git a/board/gdsys/405ep/iocon.c b/board/gdsys/405ep/iocon.c
index 7a98e41..079dfb2 100644
--- a/board/gdsys/405ep/iocon.c
+++ b/board/gdsys/405ep/iocon.c
@@ -15,6 +15,7 @@
#include 405ep.h
#include gdsys_fpga.h
+#include ../common/dp501.h
#include ../common/osd.h
#include ../common/mclink.h
@@ -98,6 +99,8 @@ enum {
unsigned int mclink_fpgacount;
struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR;
+int dp501_i2c[] = CONFIG_SYS_DP501_I2C;
+
static int setup_88e1518(const char *bus, unsigned char addr);
int fpga_set_reg(u32 fpga, u16 *reg, off_t regoff, u16 data)
@@ -371,9 +374,18 @@ int last_stage_init(void)
u16 fpga_features;
int feature_carrier_speed = fpga_features (14);
bool ch0_rgmii2_present = false;
+ int old_bus = i2c_get_bus_num();
FPGA_GET_REG(0, fpga_features, fpga_features);
+ /* Turn on Parade DP501 */
+ pca9698_direction_output(0x20, 9, 1);
+ udelay(50);
+
+ i2c_set_bus_num(dp501_i2c[0]);
+ dp501_powerup(0x08);
+ i2c_set_bus_num(old_bus);
+
if (!legacy)
ch0_rgmii2_present = !pca9698_get_value(0x20, 30);
diff --git a/board/gdsys/common/Makefile b/board/gdsys/common/Makefile
index fb841e0..7f8b427 100644
--- a/board/gdsys/common/Makefile
+++ b/board/gdsys/common/Makefile
@@ -8,6 +8,6 @@
obj-$(CONFIG_SYS_FPGA_COMMON) += fpga.o
obj-$(CONFIG_IO) += miiphybb.o
obj-$(CONFIG_IO64) += miiphybb.o
-obj-$(CONFIG_IOCON) += osd.o mclink.o
+obj-$(CONFIG_IOCON) += osd.o mclink.o dp501.o
obj-$(CONFIG_DLVISION_10G) += osd.o
obj-$(CONFIG_CONTROLCENTERD) += dp501.o
diff --git a/board/gdsys/common/dp501.c b/board/gdsys/common/dp501.c
index 52f3ea1..e00e589 100644
--- a/board/gdsys/common/dp501.c
+++ b/board/gdsys/common/dp501.c
@@ -60,8 +60,31 @@ void dp501_powerup(u8 addr)
i2c_reg_write(addr, 0x71, 0x20); /* Enable Aux burst write */
dp501_setbits(addr, 0x78, 0x30); /* Disable HPD2 IRQ */
dp501_clrbits(addr, 0x2f, 0x40); /* Link FIFO reset selection */
+
+#ifdef CONFIG_SYS_DP501_VCAPCTRL0
+ i2c_reg_write(addr, 0x24, CONFIG_SYS_DP501_VCAPCTRL0);
+#else
i2c_reg_write(addr, 0x24, 0xc0); /* SDR mode 0, ext. H/VSYNC */
+#endif
+
+#ifdef CONFIG_SYS_DP501_DIFFERENTIAL
+ i2c_reg_write(addr + 2, 0x24, 0x10); /* clock input differential */
+ i2c_reg_write(addr + 2, 0x25, 0x04);
+ i2c_reg_write(addr + 2, 0x26, 0x10);
+#else
i2c_reg_write(addr + 2, 0x24, 0x02); /* clock input single ended */
+#endif
+
+ i2c_reg_write(addr + 2, 0x00, 0x18); /* driving strength */
+ i2c_reg_write(addr + 2, 0x03, 0x06); /* driving strength */
+ i2c_reg_write(addr, 0x2c, 0x00); /* configure N value */
+ i2c_reg_write(addr, 0x2d, 0x00); /* configure N value */
+ i2c_reg_write(addr, 0x2e, 0x0c); /* configure N value */
+ i2c_reg_write(addr, 0x76, 0xff); /* clear all interrupt */
+ dp501_setbits(addr, 0x78, 0x03); /* clear all interrupt */
+ i2c_reg_write(addr, 0x75, 0xf8); /* aux channel reset */
+ i2c_reg_write(addr, 0x75, 0x00); /* clear aux channel reset */
+ i2c_reg_write(addr, 0x87, 0x70); /* set retry counter as 7 */
if (dp501_detect_cable_adapter(addr)) {
printf(DVI/HDMI cable adapter detected\n);
@@ -69,16 +92,6 @@ void dp501_powerup(u8 addr)
dp501_clrbits(addr, 0x00, 0x08); /* DVI/HDMI HDCP operation */
} else {
printf(no DVI/HDMI cable adapter detected\n);
- i2c_reg_write(addr + 2, 0x00, 0x18); /* driving strength */
- i2c_reg_write(addr + 2, 0x03, 0x06); /* driving strength */
- i2c_reg_write(addr, 0x2c, 0x00); /* configure N value */
- i2c_reg_write(addr, 0x2d, 0x00); /* configure N value */
- i2c_reg_write(addr, 0x2e, 0x0c); /* configure N value */
- i2c_reg_write(addr, 0x76, 0xff); /* clear all interrupt */
- dp501_setbits(addr, 0x78, 0x03); /* clear all interrupt */
- i2c_reg_write(addr, 0x75, 0xf8); /* aux channel reset */
- i2c_reg_write(addr, 0x75, 0x00); /* clear aux channel reset */
- i2c_reg_write(addr, 0x87, 0x70); /* set retry counter as 7 */
dp501_setbits(addr, 0x00, 0x08); /* for DP HDCP operation */
dp501_link_training(addr);
diff --git a/board/gdsys/common/osd.c b/board/gdsys/common/osd.c
index c49cd9a..a839a4e 100644
---
[U-Boot] [PATCH v3 11/13] board: iocon: Modify iocon hardware startup
From: Dirk Eibach dirk.eib...@gdsys.cc
To avoid peer ChReceivePathStatus-messages on iocon startup, initialize
PHYs as soon as possible.
Signed-off-by: Dirk Eibach dirk.eib...@gdsys.cc
---
Changes in v3: None
Changes in v2: None
board/gdsys/405ep/iocon.c | 9 -
1 file changed, 4 insertions(+), 5 deletions(-)
diff --git a/board/gdsys/405ep/iocon.c b/board/gdsys/405ep/iocon.c
index 6ae15e1..1bac970 100644
--- a/board/gdsys/405ep/iocon.c
+++ b/board/gdsys/405ep/iocon.c
@@ -377,14 +377,10 @@ int last_stage_init(void)
if (!legacy) {
/* Turn on Parade DP501 */
pca9698_direction_output(0x20, 9, 1);
- udelay(50);
ch0_rgmii2_present = !pca9698_get_value(0x20, 30);
}
- print_fpga_info(0, ch0_rgmii2_present);
- osd_probe(0);
-
/* wait for FPGA done */
for (k = 0; k ARRAY_SIZE(mclink_controllers); ++k) {
unsigned int ctr = 0;
@@ -413,13 +409,16 @@ int last_stage_init(void)
}
}
- /* wait for slave-PLLs to be up and running */
+ /* give slave-PLLs and Parade DP501 some time to be up and running */
udelay(50);
mclink_fpgacount = CONFIG_SYS_MCLINK_MAX;
slaves = mclink_probe();
mclink_fpgacount = 0;
+ print_fpga_info(0, ch0_rgmii2_present);
+ osd_probe(0);
+
if (slaves = 0)
return 0;
--
1.8.3
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[U-Boot] [PATCH v3 09/13] board: gdsys: Make gdsys osd hardware detection more robust
From: Dirk Eibach dirk.eib...@gdsys.cc
Signed-off-by: Dirk Eibach dirk.eib...@gdsys.cc
---
Changes in v3: None
Changes in v2: None
board/gdsys/405ep/iocon.c | 17 ++-
board/gdsys/common/osd.c | 113 +++--
drivers/i2c/ihs_i2c.c | 1 -
include/configs/dlvision-10g.h | 2 -
include/configs/iocon.h| 6 ---
5 files changed, 79 insertions(+), 60 deletions(-)
diff --git a/board/gdsys/405ep/iocon.c b/board/gdsys/405ep/iocon.c
index 079dfb2..6ae15e1 100644
--- a/board/gdsys/405ep/iocon.c
+++ b/board/gdsys/405ep/iocon.c
@@ -15,7 +15,6 @@
#include 405ep.h
#include gdsys_fpga.h
-#include ../common/dp501.h
#include ../common/osd.h
#include ../common/mclink.h
@@ -99,8 +98,6 @@ enum {
unsigned int mclink_fpgacount;
struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR;
-int dp501_i2c[] = CONFIG_SYS_DP501_I2C;
-
static int setup_88e1518(const char *bus, unsigned char addr);
int fpga_set_reg(u32 fpga, u16 *reg, off_t regoff, u16 data)
@@ -374,20 +371,16 @@ int last_stage_init(void)
u16 fpga_features;
int feature_carrier_speed = fpga_features (14);
bool ch0_rgmii2_present = false;
- int old_bus = i2c_get_bus_num();
FPGA_GET_REG(0, fpga_features, fpga_features);
- /* Turn on Parade DP501 */
- pca9698_direction_output(0x20, 9, 1);
- udelay(50);
-
- i2c_set_bus_num(dp501_i2c[0]);
- dp501_powerup(0x08);
- i2c_set_bus_num(old_bus);
+ if (!legacy) {
+ /* Turn on Parade DP501 */
+ pca9698_direction_output(0x20, 9, 1);
+ udelay(50);
- if (!legacy)
ch0_rgmii2_present = !pca9698_get_value(0x20, 30);
+ }
print_fpga_info(0, ch0_rgmii2_present);
osd_probe(0);
diff --git a/board/gdsys/common/osd.c b/board/gdsys/common/osd.c
index a839a4e..1c765e4 100644
--- a/board/gdsys/common/osd.c
+++ b/board/gdsys/common/osd.c
@@ -9,6 +9,7 @@
#include i2c.h
#include malloc.h
+#include dp501.h
#include gdsys_fpga.h
#define CH7301_I2C_ADDR 0x75
@@ -24,6 +25,8 @@
#define SIL1178_MASTER_I2C_ADDRESS 0x38
#define SIL1178_SLAVE_I2C_ADDRESS 0x39
+#define DP501_I2C_ADDR 0x08
+
#define PIXCLK_640_480_60 2518
enum {
@@ -54,18 +57,23 @@ u16 *buf;
unsigned int max_osd_screen = CONFIG_SYS_OSD_SCREENS - 1;
-#ifdef CONFIG_SYS_CH7301
-int ch7301_i2c[] = CONFIG_SYS_CH7301_I2C;
+#ifdef CONFIG_SYS_ICS8N3QV01_I2C
+int ics8n3qv01_i2c[] = CONFIG_SYS_ICS8N3QV01_I2C;
#endif
-#ifdef CONFIG_SYS_ICS8N3QV01
-int ics8n3qv01_i2c[] = CONFIG_SYS_ICS8N3QV01_I2C;
+#ifdef CONFIG_SYS_CH7301_I2C
+int ch7301_i2c[] = CONFIG_SYS_CH7301_I2C;
#endif
-#ifdef CONFIG_SYS_SIL1178
+#ifdef CONFIG_SYS_SIL1178_I2C
int sil1178_i2c[] = CONFIG_SYS_SIL1178_I2C;
#endif
+#ifdef CONFIG_SYS_DP501_I2C
+int dp501_i2c[] = CONFIG_SYS_DP501_I2C;
+#endif
+
+
#ifdef CONFIG_SYS_MPC92469AC
static void mpc92469ac_calc_parameters(unsigned int fout,
unsigned int *post_div, unsigned int *feedback_div)
@@ -118,7 +126,7 @@ static void mpc92469ac_set(unsigned screen, unsigned int
fout)
}
#endif
-#ifdef CONFIG_SYS_ICS8N3QV01
+#ifdef CONFIG_SYS_ICS8N3QV01_I2C
static unsigned int ics8n3qv01_get_fout_calc(unsigned index)
{
@@ -283,6 +291,8 @@ int osd_probe(unsigned screen)
u16 features;
u8 value;
int old_bus = i2c_get_bus_num();
+ bool pixclock_present = false;
+ bool output_driver_present = false;
FPGA_GET_REG(0, osd.version, version);
FPGA_GET_REG(0, osd.features, features);
@@ -297,51 +307,76 @@ int osd_probe(unsigned screen)
printf(OSD%d: Digital-OSD version %01d.%02d, %d x%d characters\n,
screen, version/100, version%100, base_width, base_height);
-#ifdef CONFIG_SYS_CH7301
- i2c_set_bus_num(ch7301_i2c[screen]);
- value = i2c_reg_read(CH7301_I2C_ADDR, CH7301_DID);
- if (value != 0x17) {
- printf( Probing CH7301 failed, DID %02x\n, value);
- i2c_set_bus_num(old_bus);
- return -1;
- }
- i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPCP, 0x08);
- i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPD, 0x16);
- i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPF, 0x60);
- i2c_reg_write(CH7301_I2C_ADDR, CH7301_DC, 0x09);
- i2c_reg_write(CH7301_I2C_ADDR, CH7301_PM, 0xc0);
-#endif
+ /* setup pixclock */
#ifdef CONFIG_SYS_MPC92469AC
+ pixclock_present = true;
mpc92469ac_set(screen, PIXCLK_640_480_60);
#endif
-#ifdef CONFIG_SYS_ICS8N3QV01
+#ifdef CONFIG_SYS_ICS8N3QV01_I2C
i2c_set_bus_num(ics8n3qv01_i2c[screen]);
- ics8n3qv01_set(PIXCLK_640_480_60);
+ if (!i2c_probe(ICS8N3QV01_I2C_ADDR)) {
+ ics8n3qv01_set(PIXCLK_640_480_60);
+ pixclock_present = true;
+ }
#endif
-#ifdef CONFIG_SYS_SIL1178
+ if (!pixclock_present)
+ printf( no pixelclock found\n);
+
+
[U-Boot] [PATCH v3 01/13] board: controlcenterd: Fix pci access
From: Dirk Eibach dirk.eib...@gdsys.cc readl was called with values instead of pointers to these values. Why this ever did work is a mystery... Signed-off-by: Dirk Eibach dirk.eib...@gdsys.cc --- Changes in v3: None Changes in v2: None board/gdsys/p1022/controlcenterd.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/board/gdsys/p1022/controlcenterd.c b/board/gdsys/p1022/controlcenterd.c index 8ccd9ce..0a3517d 100644 --- a/board/gdsys/p1022/controlcenterd.c +++ b/board/gdsys/p1022/controlcenterd.c @@ -386,9 +386,9 @@ static void hydra_initialize(void) fpga = pci_map_bar(devno, PCI_BASE_ADDRESS_0, PCI_REGION_MEM); - versions = readl(fpga-versions); - fpga_version = readl(fpga-fpga_version); - fpga_features = readl(fpga-fpga_features); + versions = readl(fpga-versions); + fpga_version = readl(fpga-fpga_version); + fpga_features = readl(fpga-fpga_features); hardware_version = versions 0xf; feature_uart_channels = (fpga_features 6) 0x1f; -- 1.8.3 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3 10/13] board: gdsys: Enable scrambling on DP501
From: Dirk Eibach dirk.eib...@gdsys.cc For proper displayport performance, scrambling has to be enabled, but is turned off on DP501 by default. Signed-off-by: Dirk Eibach dirk.eib...@gdsys.cc --- Changes in v3: None Changes in v2: None board/gdsys/common/dp501.c | 1 + 1 file changed, 1 insertion(+) diff --git a/board/gdsys/common/dp501.c b/board/gdsys/common/dp501.c index 7958bae..7eb15ed 100644 --- a/board/gdsys/common/dp501.c +++ b/board/gdsys/common/dp501.c @@ -61,6 +61,7 @@ void dp501_powerup(u8 addr) i2c_reg_write(addr, 0x71, 0x20); /* Enable Aux burst write */ dp501_setbits(addr, 0x78, 0x30); /* Disable HPD2 IRQ */ dp501_clrbits(addr, 0x2f, 0x40); /* Link FIFO reset selection */ + dp501_clrbits(addr, 0x60, 0x20); /* Enable scrambling */ #ifdef CONFIG_SYS_DP501_VCAPCTRL0 i2c_reg_write(addr, 0x24, CONFIG_SYS_DP501_VCAPCTRL0); -- 1.8.3 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3 13/13] fit: make sha256 support optional
From: Dirk Eibach dirk.eib...@gdsys.cc
sha256 has some beefy memory footprint.
Make it optional for constrained systems.
Signed-off-by: Dirk Eibach dirk.eib...@gdsys.cc
---
Changes in v3: None
Changes in v2:
- make sha256 support optional
include/configs/dlvision-10g.h | 1 +
include/configs/io.h | 1 +
include/configs/iocon.h| 1 +
include/configs/neo.h | 1 +
include/image.h| 5 +
5 files changed, 9 insertions(+)
diff --git a/include/configs/dlvision-10g.h b/include/configs/dlvision-10g.h
index 2567a22..6153a40 100644
--- a/include/configs/dlvision-10g.h
+++ b/include/configs/dlvision-10g.h
@@ -40,6 +40,7 @@
/* new uImage format support */
#define CONFIG_FIT
#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
+#define CONFIG_FIT_DISABLE_SHA256
#define CONFIG_ENV_IS_IN_FLASH /* use FLASH for environment vars */
diff --git a/include/configs/io.h b/include/configs/io.h
index 649c0fb..8e32c25 100644
--- a/include/configs/io.h
+++ b/include/configs/io.h
@@ -40,6 +40,7 @@
/* new uImage format support */
#define CONFIG_FIT
#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
+#define CONFIG_FIT_DISABLE_SHA256
#define CONFIG_ENV_IS_IN_FLASH /* use FLASH for environment vars */
diff --git a/include/configs/iocon.h b/include/configs/iocon.h
index 35ba1bd..ae05bcb 100644
--- a/include/configs/iocon.h
+++ b/include/configs/iocon.h
@@ -39,6 +39,7 @@
/* new uImage format support */
#define CONFIG_FIT
#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
+#define CONFIG_FIT_DISABLE_SHA256
#define CONFIG_ENV_IS_IN_FLASH /* use FLASH for environment vars */
diff --git a/include/configs/neo.h b/include/configs/neo.h
index 75dc862..4937730 100644
--- a/include/configs/neo.h
+++ b/include/configs/neo.h
@@ -37,6 +37,7 @@
/* new uImage format support */
#define CONFIG_FIT
#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
+#define CONFIG_FIT_DISABLE_SHA256
#define CONFIG_ENV_IS_IN_FLASH /* use FLASH for environment vars */
diff --git a/include/image.h b/include/image.h
index b71e4ba..61d5885 100644
--- a/include/image.h
+++ b/include/image.h
@@ -72,6 +72,11 @@ struct lmb;
# define IMAGE_ENABLE_SHA256 1
# endif
+#ifdef CONFIG_FIT_DISABLE_SHA256
+#undef CONFIG_SHA256
+#undef IMAGE_ENABLE_SHA256
+#endif
+
#ifndef IMAGE_ENABLE_CRC32
#define IMAGE_ENABLE_CRC32 0
#endif
--
1.8.3
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[U-Boot] [PATCH v3 05/13] i2c: IHS I2C master driver
From: Dirk Eibach dirk.eib...@gdsys.cc
IHS I2C master support was merely a hack in the osd driver.
Now it is a proper u-boot I2C framework driver, supporting the
v2.00 master features.
Signed-off-by: Dirk Eibach dirk.eib...@gdsys.cc
---
Changes in v3:
- describe ihs_i2c in README
Changes in v2:
- move ihs_i2c to drivers/i2c
- split unrelated changes
README | 15 +++
drivers/i2c/Makefile | 1 +
drivers/i2c/ihs_i2c.c | 204 +
include/configs/dlvision-10g.h | 11 +++
include/configs/iocon.h| 23 -
include/gdsys_fpga.h | 25 +++--
6 files changed, 261 insertions(+), 18 deletions(-)
create mode 100644 drivers/i2c/ihs_i2c.c
diff --git a/README b/README
index a248ab5..1fc8f00 100644
--- a/README
+++ b/README
@@ -2268,6 +2268,21 @@ CBFS (Coreboot Filesystem) support
9 i2c buses for Exynos4 and 1 for S3C24X0 SoCs from Samsung)
with a fix speed from 10 and the slave addr 0!
+ - drivers/i2c/ihs_i2c.c
+ - activate this driver with CONFIG_SYS_I2C_IHS
+ - CONFIG_SYS_I2C_IHS_CH0 activate hardware channel 0
+ - CONFIG_SYS_I2C_IHS_SPEED_0 speed channel 0
+ - CONFIG_SYS_I2C_IHS_SLAVE_0 slave addr channel 0
+ - CONFIG_SYS_I2C_IHS_CH1 activate hardware channel 1
+ - CONFIG_SYS_I2C_IHS_SPEED_1 speed channel 1
+ - CONFIG_SYS_I2C_IHS_SLAVE_1 slave addr channel 1
+ - CONFIG_SYS_I2C_IHS_CH2 activate hardware channel 2
+ - CONFIG_SYS_I2C_IHS_SPEED_2 speed channel 2
+ - CONFIG_SYS_I2C_IHS_SLAVE_2 slave addr channel 2
+ - CONFIG_SYS_I2C_IHS_CH3 activate hardware channel 3
+ - CONFIG_SYS_I2C_IHS_SPEED_3 speed channel 3
+ - CONFIG_SYS_I2C_IHS_SLAVE_3 slave addr channel 3
+
additional defines:
CONFIG_SYS_NUM_I2C_BUSES
diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile
index e33586d..96bd45d 100644
--- a/drivers/i2c/Makefile
+++ b/drivers/i2c/Makefile
@@ -18,6 +18,7 @@ obj-$(CONFIG_SYS_I2C) += i2c_core.o
obj-$(CONFIG_SYS_I2C_DAVINCI) += davinci_i2c.o
obj-$(CONFIG_SYS_I2C_FSL) += fsl_i2c.o
obj-$(CONFIG_SYS_I2C_FTI2C010) += fti2c010.o
+obj-$(CONFIG_SYS_I2C_IHS) += ihs_i2c.o
obj-$(CONFIG_SYS_I2C_KONA) += kona_i2c.o
obj-$(CONFIG_SYS_I2C_MXC) += mxc_i2c.o
obj-$(CONFIG_SYS_I2C_OMAP24XX) += omap24xx_i2c.o
diff --git a/drivers/i2c/ihs_i2c.c b/drivers/i2c/ihs_i2c.c
new file mode 100644
index 000..ecc5856
--- /dev/null
+++ b/drivers/i2c/ihs_i2c.c
@@ -0,0 +1,204 @@
+/*
+ * (C) Copyright 2013
+ * Dirk Eibach, Guntermann Drunck GmbH, eib...@gdsys.de
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include i2c.h
+#include gdsys_fpga.h
+
+DECLARE_GLOBAL_DATA_PTR;
+
+enum {
+ I2CINT_ERROR_EV = 1 13,
+ I2CINT_TRANSMIT_EV = 1 14,
+ I2CINT_RECEIVE_EV = 1 15,
+};
+
+enum {
+ I2CMB_WRITE = 1 10,
+ I2CMB_2BYTE = 1 11,
+ I2CMB_HOLD_BUS = 1 13,
+ I2CMB_NATIVE = 2 14,
+};
+
+static int wait_for_int(bool read)
+{
+ u16 val;
+ unsigned int ctr = 0;
+
+ FPGA_GET_REG(I2C_ADAP_HWNR, i2c.interrupt_status, val);
+ while (!(val (I2CINT_ERROR_EV
+ | (read ? I2CINT_RECEIVE_EV : I2CINT_TRANSMIT_EV {
+ udelay(10);
+ if (ctr++ 5000) {
+ printf(I2C timeout\n);
+ return 1;
+ }
+ FPGA_GET_REG(I2C_ADAP_HWNR, i2c.interrupt_status, val);
+ }
+
+ return (val I2CINT_ERROR_EV) ? 1 : 0;
+}
+
+static int ihs_i2c_transfer(uchar chip, uchar *buffer, int len, bool read,
+ bool is_last)
+{
+ u16 val;
+
+ FPGA_SET_REG(I2C_ADAP_HWNR, i2c.interrupt_status, I2CINT_ERROR_EV
+| I2CINT_RECEIVE_EV | I2CINT_TRANSMIT_EV);
+ FPGA_GET_REG(I2C_ADAP_HWNR, i2c.interrupt_status, val);
+
+ if (!read len) {
+ val = buffer[0];
+
+ if (len 1)
+ val |= buffer[1] 8;
+ FPGA_SET_REG(I2C_ADAP_HWNR, i2c.write_mailbox_ext, val);
+ }
+
+ FPGA_SET_REG(I2C_ADAP_HWNR, i2c.write_mailbox,
+I2CMB_NATIVE
+| (read ? 0 : I2CMB_WRITE)
+| (chip 1)
+| ((len 1) ? I2CMB_2BYTE : 0)
+| (is_last ? 0 : I2CMB_HOLD_BUS));
+
+ if (wait_for_int(read))
+ return 1;
+
+ if (read) {
+ FPGA_GET_REG(I2C_ADAP_HWNR, i2c.read_mailbox_ext, val);
+ buffer[0] = val 0xff;
+ if (len 1)
+ buffer[1] = val 8;
+ }
+
+ return 0;
+}
+
+static int ihs_i2c_address(uchar chip, uint addr, int alen, bool hold_bus)
+{
+ int shift = (alen-1) * 8;
+
+
[U-Boot] [PATCH v3 06/13] board: gdsys: Fix dlvision-10g I2C configuration
From: Dirk Eibach dirk.eib...@gdsys.cc
PPC4xx config options were not complete.
ICS8N3QV01 and SIL1178 needed some more configuration.
Signed-off-by: Dirk Eibach dirk.eib...@gdsys.cc
---
Changes in v3: None
Changes in v2: None
include/configs/dlvision-10g.h | 10 --
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/include/configs/dlvision-10g.h b/include/configs/dlvision-10g.h
index 05a97bf..16895bf 100644
--- a/include/configs/dlvision-10g.h
+++ b/include/configs/dlvision-10g.h
@@ -97,7 +97,10 @@
/*
* I2C stuff
*/
+#define CONFIG_SYS_I2C_PPC4XX
+#define CONFIG_SYS_I2C_PPC4XX_CH0
#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 10
+#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
#define CONFIG_SYS_I2C_IHS
#define CONFIG_SYS_I2C_IHS_CH0
@@ -118,6 +121,11 @@
{ 54, 27 }, { 56, 31 }, { 58, 36 }, { 60, 40 } }
#define CONFIG_DTT_TACH_LIMIT 0xa10
+#define CONFIG_SYS_ICS8N3QV01
+#define CONFIG_SYS_ICS8N3QV01_I2C {0, 1}
+#define CONFIG_SYS_SIL1178
+#define CONFIG_SYS_SIL1178_I2C {0, 1}
+
/* EBC peripherals */
#define CONFIG_SYS_FLASH_BASE 0xFC00
@@ -317,9 +325,7 @@
/*
* OSD Setup
*/
-#define CONFIG_SYS_ICS8N3QV01
#define CONFIG_SYS_MPC92469AC
-#define CONFIG_SYS_SIL1178
#define CONFIG_SYS_OSD_SCREENS CONFIG_SYS_FPGA_COUNT
#endif /* __CONFIG_H */
--
1.8.3
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Re: [U-Boot] [PATCH v5] arm: Add support for semihosting for armv8 fastmodel targets.
Hi Darwin, On Mon, 9 Jun 2014 11:12:59 -0700, Darwin Rambo dra...@broadcom.com wrote: The armv8 ARM Trusted Firmware (ATF) can be used to load various ATF images and u-boot, and does this for virtual platforms by using semihosting. This commit extends this idea by allowing u-boot to also use semihosting to load the kernel/ramdisk/dtb. This eliminates the need for a bootwrapper and produces a more realistic boot sequence with virtual models. Though the semihosting code is quite generic, support for armv7 in fastmodel is less useful due to the wide range of available silicon and the lack of a free armv7 fastmodel, so this change contains an untested armv7 placeholder for the service trap opcode. Please refer to README.semihosting for a more detailed description of semihosting and how it is used with the armv8 virtual platforms. Signed-off-by: Darwin Rambo dra...@broadcom.com Cc: tr...@ti.com Cc: feng...@phytium.com.cn Cc: bhupesh.sha...@freescale.com --- Applied to u-boot-arm/master, with the change from README... to doc/README... as agreed, thanks! Amicalement, -- Albert. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3 0/13] Fixes on gdsys boards and some new functionality
On 03.07.2014 08:27, dirk.eib...@gdsys.cc wrote: From: Dirk Eibach dirk.eib...@gdsys.cc Looks good for the ppc4xx parts, so: Acked-by: Stefan Roese s...@denx.de Thanks, Stefan ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3 05/13] i2c: IHS I2C master driver
Hello Dirk, Am 03.07.2014 08:27, schrieb dirk.eib...@gdsys.cc: From: Dirk Eibachdirk.eib...@gdsys.cc IHS I2C master support was merely a hack in the osd driver. Now it is a proper u-boot I2C framework driver, supporting the v2.00 master features. Signed-off-by: Dirk Eibachdirk.eib...@gdsys.cc --- Changes in v3: - describe ihs_i2c in README Changes in v2: - move ihs_i2c to drivers/i2c - split unrelated changes README | 15 +++ drivers/i2c/Makefile | 1 + drivers/i2c/ihs_i2c.c | 204 + include/configs/dlvision-10g.h | 11 +++ include/configs/iocon.h| 23 - include/gdsys_fpga.h | 25 +++-- 6 files changed, 261 insertions(+), 18 deletions(-) create mode 100644 drivers/i2c/ihs_i2c.c Thanks! Acked-by: Heiko Schocher h...@denx.de bye, Heiko -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3 13/13] fit: make sha256 support optional
Hello Dirk, Am 03.07.2014 08:27, schrieb dirk.eib...@gdsys.cc: From: Dirk Eibachdirk.eib...@gdsys.cc sha256 has some beefy memory footprint. Make it optional for constrained systems. Signed-off-by: Dirk Eibachdirk.eib...@gdsys.cc --- Changes in v3: None Changes in v2: - make sha256 support optional include/configs/dlvision-10g.h | 1 + include/configs/io.h | 1 + include/configs/iocon.h| 1 + include/configs/neo.h | 1 + include/image.h| 5 + 5 files changed, 9 insertions(+) Sorry, some nitpick. As you introduce here the new define CONFIG_FIT_DISABLE_SHA256, can you please add a short description in the README, thanks! bye, Heiko -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v5 1/4] mx6: Add support for the mx6solox variant
Hi Fabio, On 02/07/2014 20:54, Fabio Estevam wrote: Hi Stefano, On Tue, Jun 24, 2014 at 5:40 PM, Fabio Estevam feste...@gmail.com wrote: From: Fabio Estevam fabio.este...@freescale.com mx6solox is the newest member of the mx6 family. Some of the new features on this variants are: - Cortex M4 microcontroller (besides the CortexA9) - Dual Gigabit Ethernet Add the initial support for it. Signed-off-by: Fabio Estevam fabio.este...@freescale.com Any comments about this series? I have only taken a short look because the series should flow after 2014.07. Anyway, I could push them into -next. Regards, Stefano -- = DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de = ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v4 02/13] board: gdsys: Adapt sdhc_boot.c to mmc_get_env_addr API change
From: Dirk Eibach dirk.eib...@gdsys.cc
Signed-off-by: Dirk Eibach dirk.eib...@gdsys.cc
---
Changes in v4: None
Changes in v3: None
Changes in v2: None
board/gdsys/p1022/sdhc_boot.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/board/gdsys/p1022/sdhc_boot.c b/board/gdsys/p1022/sdhc_boot.c
index e432318..fd0e910 100644
--- a/board/gdsys/p1022/sdhc_boot.c
+++ b/board/gdsys/p1022/sdhc_boot.c
@@ -32,7 +32,7 @@
#define ESDHC_BOOT_IMAGE_SIZE 0x48
#define ESDHC_BOOT_IMAGE_ADDR 0x50
-int mmc_get_env_addr(struct mmc *mmc, u32 *env_addr)
+int mmc_get_env_addr(struct mmc *mmc, int copy, u32 *env_addr)
{
u8 *tmp_buf;
u32 blklen, code_offset, code_len, n;
--
1.8.3
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[U-Boot] [PATCH v4 05/13] i2c: IHS I2C master driver
From: Dirk Eibach dirk.eib...@gdsys.cc
IHS I2C master support was merely a hack in the osd driver.
Now it is a proper u-boot I2C framework driver, supporting the
v2.00 master features.
Signed-off-by: Dirk Eibach dirk.eib...@gdsys.cc
---
Changes in v4: None
Changes in v3:
- describe ihs_i2c in README
Changes in v2:
- move ihs_i2c to drivers/i2c
- split unrelated changes
README | 15 +++
drivers/i2c/Makefile | 1 +
drivers/i2c/ihs_i2c.c | 204 +
include/configs/dlvision-10g.h | 11 +++
include/configs/iocon.h| 23 -
include/gdsys_fpga.h | 25 +++--
6 files changed, 261 insertions(+), 18 deletions(-)
create mode 100644 drivers/i2c/ihs_i2c.c
diff --git a/README b/README
index a248ab5..1fc8f00 100644
--- a/README
+++ b/README
@@ -2268,6 +2268,21 @@ CBFS (Coreboot Filesystem) support
9 i2c buses for Exynos4 and 1 for S3C24X0 SoCs from Samsung)
with a fix speed from 10 and the slave addr 0!
+ - drivers/i2c/ihs_i2c.c
+ - activate this driver with CONFIG_SYS_I2C_IHS
+ - CONFIG_SYS_I2C_IHS_CH0 activate hardware channel 0
+ - CONFIG_SYS_I2C_IHS_SPEED_0 speed channel 0
+ - CONFIG_SYS_I2C_IHS_SLAVE_0 slave addr channel 0
+ - CONFIG_SYS_I2C_IHS_CH1 activate hardware channel 1
+ - CONFIG_SYS_I2C_IHS_SPEED_1 speed channel 1
+ - CONFIG_SYS_I2C_IHS_SLAVE_1 slave addr channel 1
+ - CONFIG_SYS_I2C_IHS_CH2 activate hardware channel 2
+ - CONFIG_SYS_I2C_IHS_SPEED_2 speed channel 2
+ - CONFIG_SYS_I2C_IHS_SLAVE_2 slave addr channel 2
+ - CONFIG_SYS_I2C_IHS_CH3 activate hardware channel 3
+ - CONFIG_SYS_I2C_IHS_SPEED_3 speed channel 3
+ - CONFIG_SYS_I2C_IHS_SLAVE_3 slave addr channel 3
+
additional defines:
CONFIG_SYS_NUM_I2C_BUSES
diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile
index e33586d..96bd45d 100644
--- a/drivers/i2c/Makefile
+++ b/drivers/i2c/Makefile
@@ -18,6 +18,7 @@ obj-$(CONFIG_SYS_I2C) += i2c_core.o
obj-$(CONFIG_SYS_I2C_DAVINCI) += davinci_i2c.o
obj-$(CONFIG_SYS_I2C_FSL) += fsl_i2c.o
obj-$(CONFIG_SYS_I2C_FTI2C010) += fti2c010.o
+obj-$(CONFIG_SYS_I2C_IHS) += ihs_i2c.o
obj-$(CONFIG_SYS_I2C_KONA) += kona_i2c.o
obj-$(CONFIG_SYS_I2C_MXC) += mxc_i2c.o
obj-$(CONFIG_SYS_I2C_OMAP24XX) += omap24xx_i2c.o
diff --git a/drivers/i2c/ihs_i2c.c b/drivers/i2c/ihs_i2c.c
new file mode 100644
index 000..ecc5856
--- /dev/null
+++ b/drivers/i2c/ihs_i2c.c
@@ -0,0 +1,204 @@
+/*
+ * (C) Copyright 2013
+ * Dirk Eibach, Guntermann Drunck GmbH, eib...@gdsys.de
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include i2c.h
+#include gdsys_fpga.h
+
+DECLARE_GLOBAL_DATA_PTR;
+
+enum {
+ I2CINT_ERROR_EV = 1 13,
+ I2CINT_TRANSMIT_EV = 1 14,
+ I2CINT_RECEIVE_EV = 1 15,
+};
+
+enum {
+ I2CMB_WRITE = 1 10,
+ I2CMB_2BYTE = 1 11,
+ I2CMB_HOLD_BUS = 1 13,
+ I2CMB_NATIVE = 2 14,
+};
+
+static int wait_for_int(bool read)
+{
+ u16 val;
+ unsigned int ctr = 0;
+
+ FPGA_GET_REG(I2C_ADAP_HWNR, i2c.interrupt_status, val);
+ while (!(val (I2CINT_ERROR_EV
+ | (read ? I2CINT_RECEIVE_EV : I2CINT_TRANSMIT_EV {
+ udelay(10);
+ if (ctr++ 5000) {
+ printf(I2C timeout\n);
+ return 1;
+ }
+ FPGA_GET_REG(I2C_ADAP_HWNR, i2c.interrupt_status, val);
+ }
+
+ return (val I2CINT_ERROR_EV) ? 1 : 0;
+}
+
+static int ihs_i2c_transfer(uchar chip, uchar *buffer, int len, bool read,
+ bool is_last)
+{
+ u16 val;
+
+ FPGA_SET_REG(I2C_ADAP_HWNR, i2c.interrupt_status, I2CINT_ERROR_EV
+| I2CINT_RECEIVE_EV | I2CINT_TRANSMIT_EV);
+ FPGA_GET_REG(I2C_ADAP_HWNR, i2c.interrupt_status, val);
+
+ if (!read len) {
+ val = buffer[0];
+
+ if (len 1)
+ val |= buffer[1] 8;
+ FPGA_SET_REG(I2C_ADAP_HWNR, i2c.write_mailbox_ext, val);
+ }
+
+ FPGA_SET_REG(I2C_ADAP_HWNR, i2c.write_mailbox,
+I2CMB_NATIVE
+| (read ? 0 : I2CMB_WRITE)
+| (chip 1)
+| ((len 1) ? I2CMB_2BYTE : 0)
+| (is_last ? 0 : I2CMB_HOLD_BUS));
+
+ if (wait_for_int(read))
+ return 1;
+
+ if (read) {
+ FPGA_GET_REG(I2C_ADAP_HWNR, i2c.read_mailbox_ext, val);
+ buffer[0] = val 0xff;
+ if (len 1)
+ buffer[1] = val 8;
+ }
+
+ return 0;
+}
+
+static int ihs_i2c_address(uchar chip, uint addr, int alen, bool hold_bus)
+{
+ int shift =
[U-Boot] [PATCH v4 03/13] board: controlcenterd: Use new API for setting i2c bus
From: Dirk Eibach dirk.eib...@gdsys.cc
Signed-off-by: Dirk Eibach dirk.eib...@gdsys.cc
---
Changes in v4: None
Changes in v3: None
Changes in v2:
- use defines for I2C bus numbers
board/gdsys/p1022/controlcenterd-id.c | 13 +
1 file changed, 9 insertions(+), 4 deletions(-)
diff --git a/board/gdsys/p1022/controlcenterd-id.c
b/board/gdsys/p1022/controlcenterd-id.c
index 3fca3c5..419fc2e 100644
--- a/board/gdsys/p1022/controlcenterd-id.c
+++ b/board/gdsys/p1022/controlcenterd-id.c
@@ -86,6 +86,11 @@ enum {
ESDHC_BOOT_IMAGE_ENTRY_OFS = 0x60,
};
+enum {
+ I2C_SOC_0 = 0,
+ I2C_SOC_1 = 1,
+};
+
struct key_program {
uint32_t magic;
uint32_t code_crc;
@@ -1156,7 +1161,7 @@ static void ccdm_hang(void)
int j;
#endif
- I2C_SET_BUS(0);
+ I2C_SET_BUS(I2C_SOC_0);
pca9698_direction_output(0x22, 0, 0); /* Finder */
pca9698_direction_output(0x22, 4, 0); /* Status */
@@ -1189,8 +1194,8 @@ int startup_ccdm_id_module(void)
int result = 0;
unsigned int orig_i2c_bus;
- orig_i2c_bus = I2C_GET_BUS();
- I2C_SET_BUS(1);
+ orig_i2c_bus = i2c_get_bus_num();
+ i2c_set_bus_num(I2C_SOC_1);
/* goto end; */
@@ -1216,7 +1221,7 @@ int startup_ccdm_id_module(void)
failure:
result = 1;
end:
- I2C_SET_BUS(orig_i2c_bus);
+ i2c_set_bus_num(orig_i2c_bus);
if (result)
ccdm_hang();
--
1.8.3
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[U-Boot] [PATCH v4 07/13] board: gdsys: Increase iocon and dlv10g version string
From: Dirk Eibach dirk.eib...@gdsys.cc Signed-off-by: Dirk Eibach dirk.eib...@gdsys.cc --- Changes in v4: None Changes in v3: None Changes in v2: None include/configs/dlvision-10g.h | 2 +- include/configs/iocon.h| 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/include/configs/dlvision-10g.h b/include/configs/dlvision-10g.h index 16895bf..c2289ce 100644 --- a/include/configs/dlvision-10g.h +++ b/include/configs/dlvision-10g.h @@ -17,7 +17,7 @@ * Include common defines/options for all AMCC eval boards */ #define CONFIG_HOSTNAMEdlvsion-10g -#define CONFIG_IDENT_STRING dlvision-10g 0.05 +#define CONFIG_IDENT_STRING dlvision-10g 0.06 #include amcc-common.h #define CONFIG_BOARD_EARLY_INIT_F diff --git a/include/configs/iocon.h b/include/configs/iocon.h index 36b4b55..1aebab3 100644 --- a/include/configs/iocon.h +++ b/include/configs/iocon.h @@ -17,7 +17,7 @@ * Include common defines/options for all AMCC eval boards */ #define CONFIG_HOSTNAMEiocon -#define CONFIG_IDENT_STRING iocon 0.05 +#define CONFIG_IDENT_STRING iocon 0.06 #include amcc-common.h #define CONFIG_BOARD_EARLY_INIT_F -- 1.8.3 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v4 01/13] board: controlcenterd: Fix pci access
From: Dirk Eibach dirk.eib...@gdsys.cc readl was called with values instead of pointers to these values. Why this ever did work is a mystery... Signed-off-by: Dirk Eibach dirk.eib...@gdsys.cc --- Changes in v4: None Changes in v3: None Changes in v2: None board/gdsys/p1022/controlcenterd.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/board/gdsys/p1022/controlcenterd.c b/board/gdsys/p1022/controlcenterd.c index 8ccd9ce..0a3517d 100644 --- a/board/gdsys/p1022/controlcenterd.c +++ b/board/gdsys/p1022/controlcenterd.c @@ -386,9 +386,9 @@ static void hydra_initialize(void) fpga = pci_map_bar(devno, PCI_BASE_ADDRESS_0, PCI_REGION_MEM); - versions = readl(fpga-versions); - fpga_version = readl(fpga-fpga_version); - fpga_features = readl(fpga-fpga_features); + versions = readl(fpga-versions); + fpga_version = readl(fpga-fpga_version); + fpga_features = readl(fpga-fpga_features); hardware_version = versions 0xf; feature_uart_channels = (fpga_features 6) 0x1f; -- 1.8.3 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v4 13/13] fit: make sha256 support optional
From: Dirk Eibach dirk.eib...@gdsys.cc
sha256 has some beefy memory footprint.
Make it optional for constrained systems.
Signed-off-by: Dirk Eibach dirk.eib...@gdsys.cc
---
Changes in v4:
- describe CONFIG_FIT_DISABLE_SHA256 in README
Changes in v3: None
Changes in v2:
- make sha256 support optional
README | 5 +
include/configs/dlvision-10g.h | 1 +
include/configs/io.h | 1 +
include/configs/iocon.h| 1 +
include/configs/neo.h | 1 +
include/image.h| 5 +
6 files changed, 14 insertions(+)
diff --git a/README b/README
index 1fc8f00..61c66cb 100644
--- a/README
+++ b/README
@@ -3249,6 +3249,11 @@ FIT uImage format:
disabled. If a board need legacy image format support
enable this through CONFIG_IMAGE_FORMAT_LEGACY
+ CONFIG_FIT_DISABLE_SHA256
+ Supporting SHA256 hashes has quite an impact on binary size.
+ For constrained systems sha256 hash support can be disabled
+ with this option.
+
- Standalone program support:
CONFIG_STANDALONE_LOAD_ADDR
diff --git a/include/configs/dlvision-10g.h b/include/configs/dlvision-10g.h
index 2567a22..6153a40 100644
--- a/include/configs/dlvision-10g.h
+++ b/include/configs/dlvision-10g.h
@@ -40,6 +40,7 @@
/* new uImage format support */
#define CONFIG_FIT
#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
+#define CONFIG_FIT_DISABLE_SHA256
#define CONFIG_ENV_IS_IN_FLASH /* use FLASH for environment vars */
diff --git a/include/configs/io.h b/include/configs/io.h
index 649c0fb..8e32c25 100644
--- a/include/configs/io.h
+++ b/include/configs/io.h
@@ -40,6 +40,7 @@
/* new uImage format support */
#define CONFIG_FIT
#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
+#define CONFIG_FIT_DISABLE_SHA256
#define CONFIG_ENV_IS_IN_FLASH /* use FLASH for environment vars */
diff --git a/include/configs/iocon.h b/include/configs/iocon.h
index 35ba1bd..ae05bcb 100644
--- a/include/configs/iocon.h
+++ b/include/configs/iocon.h
@@ -39,6 +39,7 @@
/* new uImage format support */
#define CONFIG_FIT
#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
+#define CONFIG_FIT_DISABLE_SHA256
#define CONFIG_ENV_IS_IN_FLASH /* use FLASH for environment vars */
diff --git a/include/configs/neo.h b/include/configs/neo.h
index 75dc862..4937730 100644
--- a/include/configs/neo.h
+++ b/include/configs/neo.h
@@ -37,6 +37,7 @@
/* new uImage format support */
#define CONFIG_FIT
#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
+#define CONFIG_FIT_DISABLE_SHA256
#define CONFIG_ENV_IS_IN_FLASH /* use FLASH for environment vars */
diff --git a/include/image.h b/include/image.h
index b71e4ba..61d5885 100644
--- a/include/image.h
+++ b/include/image.h
@@ -72,6 +72,11 @@ struct lmb;
# define IMAGE_ENABLE_SHA256 1
# endif
+#ifdef CONFIG_FIT_DISABLE_SHA256
+#undef CONFIG_SHA256
+#undef IMAGE_ENABLE_SHA256
+#endif
+
#ifndef IMAGE_ENABLE_CRC32
#define IMAGE_ENABLE_CRC32 0
#endif
--
1.8.3
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[U-Boot] [PATCH v4 08/13] board: gdsys: Configure bridge on DP501 to support DDC only
From: Dirk Eibach dirk.eib...@gdsys.cc
The I2C bridge on DP501 supports EDID, MCCS and HDCP by default.
Allow EDID only to avoid I2C address conflicts.
Signed-off-by: Dirk Eibach dirk.eib...@gdsys.cc
---
Changes in v4: None
Changes in v3: None
Changes in v2: None
board/gdsys/common/dp501.c | 1 +
include/configs/controlcenterd.h | 7 ---
2 files changed, 5 insertions(+), 3 deletions(-)
diff --git a/board/gdsys/common/dp501.c b/board/gdsys/common/dp501.c
index e00e589..7958bae 100644
--- a/board/gdsys/common/dp501.c
+++ b/board/gdsys/common/dp501.c
@@ -54,6 +54,7 @@ static void dp501_link_training(u8 addr)
void dp501_powerup(u8 addr)
{
dp501_clrbits(addr, 0x0a, 0x30); /* power on encoder */
+ dp501_setbits(addr, 0x0a, 0x0e); /* block HDCP and MCCS on I2C bride*/
i2c_reg_write(addr, 0x27, 0x30); /* Hardware auto detect DVO timing */
dp501_setbits(addr, 0x72, 0x80); /* DPCD read enable */
dp501_setbits(addr, 0x30, 0x20); /* RS polynomial select */
diff --git a/include/configs/controlcenterd.h b/include/configs/controlcenterd.h
index 868813f..ec3145f 100644
--- a/include/configs/controlcenterd.h
+++ b/include/configs/controlcenterd.h
@@ -199,9 +199,10 @@
#define CONFIG_SYS_FSL_I2C2_SPEED 40
#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
-/* Probing DP501 I2C-Bridge will hang */
-#define CONFIG_SYS_I2C_NOPROBES{ {0, 0x30}, {0, 0x37}, {0,
0x3a}, \
- {0, 0x3b}, {0, 0x50} }
+
+#ifndef CONFIG_TRAILBLAZER
+#define CONFIG_CMD_I2C
+#endif
#define CONFIG_PCA9698 /* NXP PCA9698 */
--
1.8.3
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[U-Boot] [PATCH v4 06/13] board: gdsys: Fix dlvision-10g I2C configuration
From: Dirk Eibach dirk.eib...@gdsys.cc
PPC4xx config options were not complete.
ICS8N3QV01 and SIL1178 needed some more configuration.
Signed-off-by: Dirk Eibach dirk.eib...@gdsys.cc
---
Changes in v4: None
Changes in v3: None
Changes in v2: None
include/configs/dlvision-10g.h | 10 --
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/include/configs/dlvision-10g.h b/include/configs/dlvision-10g.h
index 05a97bf..16895bf 100644
--- a/include/configs/dlvision-10g.h
+++ b/include/configs/dlvision-10g.h
@@ -97,7 +97,10 @@
/*
* I2C stuff
*/
+#define CONFIG_SYS_I2C_PPC4XX
+#define CONFIG_SYS_I2C_PPC4XX_CH0
#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 10
+#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
#define CONFIG_SYS_I2C_IHS
#define CONFIG_SYS_I2C_IHS_CH0
@@ -118,6 +121,11 @@
{ 54, 27 }, { 56, 31 }, { 58, 36 }, { 60, 40 } }
#define CONFIG_DTT_TACH_LIMIT 0xa10
+#define CONFIG_SYS_ICS8N3QV01
+#define CONFIG_SYS_ICS8N3QV01_I2C {0, 1}
+#define CONFIG_SYS_SIL1178
+#define CONFIG_SYS_SIL1178_I2C {0, 1}
+
/* EBC peripherals */
#define CONFIG_SYS_FLASH_BASE 0xFC00
@@ -317,9 +325,7 @@
/*
* OSD Setup
*/
-#define CONFIG_SYS_ICS8N3QV01
#define CONFIG_SYS_MPC92469AC
-#define CONFIG_SYS_SIL1178
#define CONFIG_SYS_OSD_SCREENS CONFIG_SYS_FPGA_COUNT
#endif /* __CONFIG_H */
--
1.8.3
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[U-Boot] [PATCH v4 04/13] board: iocon: Support DisplayPort hardware
From: Dirk Eibach dirk.eib...@gdsys.cc
There is a new iocon hardware flavor, supporting DisplayPort finally.
Signed-off-by: Dirk Eibach dirk.eib...@gdsys.cc
---
Changes in v4: None
Changes in v3: None
Changes in v2: None
board/gdsys/405ep/iocon.c | 12 +
board/gdsys/common/Makefile | 2 +-
board/gdsys/common/dp501.c | 33 +
board/gdsys/common/osd.c| 112
include/configs/iocon.h | 9 +++-
5 files changed, 83 insertions(+), 85 deletions(-)
diff --git a/board/gdsys/405ep/iocon.c b/board/gdsys/405ep/iocon.c
index 7a98e41..079dfb2 100644
--- a/board/gdsys/405ep/iocon.c
+++ b/board/gdsys/405ep/iocon.c
@@ -15,6 +15,7 @@
#include 405ep.h
#include gdsys_fpga.h
+#include ../common/dp501.h
#include ../common/osd.h
#include ../common/mclink.h
@@ -98,6 +99,8 @@ enum {
unsigned int mclink_fpgacount;
struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR;
+int dp501_i2c[] = CONFIG_SYS_DP501_I2C;
+
static int setup_88e1518(const char *bus, unsigned char addr);
int fpga_set_reg(u32 fpga, u16 *reg, off_t regoff, u16 data)
@@ -371,9 +374,18 @@ int last_stage_init(void)
u16 fpga_features;
int feature_carrier_speed = fpga_features (14);
bool ch0_rgmii2_present = false;
+ int old_bus = i2c_get_bus_num();
FPGA_GET_REG(0, fpga_features, fpga_features);
+ /* Turn on Parade DP501 */
+ pca9698_direction_output(0x20, 9, 1);
+ udelay(50);
+
+ i2c_set_bus_num(dp501_i2c[0]);
+ dp501_powerup(0x08);
+ i2c_set_bus_num(old_bus);
+
if (!legacy)
ch0_rgmii2_present = !pca9698_get_value(0x20, 30);
diff --git a/board/gdsys/common/Makefile b/board/gdsys/common/Makefile
index fb841e0..7f8b427 100644
--- a/board/gdsys/common/Makefile
+++ b/board/gdsys/common/Makefile
@@ -8,6 +8,6 @@
obj-$(CONFIG_SYS_FPGA_COMMON) += fpga.o
obj-$(CONFIG_IO) += miiphybb.o
obj-$(CONFIG_IO64) += miiphybb.o
-obj-$(CONFIG_IOCON) += osd.o mclink.o
+obj-$(CONFIG_IOCON) += osd.o mclink.o dp501.o
obj-$(CONFIG_DLVISION_10G) += osd.o
obj-$(CONFIG_CONTROLCENTERD) += dp501.o
diff --git a/board/gdsys/common/dp501.c b/board/gdsys/common/dp501.c
index 52f3ea1..e00e589 100644
--- a/board/gdsys/common/dp501.c
+++ b/board/gdsys/common/dp501.c
@@ -60,8 +60,31 @@ void dp501_powerup(u8 addr)
i2c_reg_write(addr, 0x71, 0x20); /* Enable Aux burst write */
dp501_setbits(addr, 0x78, 0x30); /* Disable HPD2 IRQ */
dp501_clrbits(addr, 0x2f, 0x40); /* Link FIFO reset selection */
+
+#ifdef CONFIG_SYS_DP501_VCAPCTRL0
+ i2c_reg_write(addr, 0x24, CONFIG_SYS_DP501_VCAPCTRL0);
+#else
i2c_reg_write(addr, 0x24, 0xc0); /* SDR mode 0, ext. H/VSYNC */
+#endif
+
+#ifdef CONFIG_SYS_DP501_DIFFERENTIAL
+ i2c_reg_write(addr + 2, 0x24, 0x10); /* clock input differential */
+ i2c_reg_write(addr + 2, 0x25, 0x04);
+ i2c_reg_write(addr + 2, 0x26, 0x10);
+#else
i2c_reg_write(addr + 2, 0x24, 0x02); /* clock input single ended */
+#endif
+
+ i2c_reg_write(addr + 2, 0x00, 0x18); /* driving strength */
+ i2c_reg_write(addr + 2, 0x03, 0x06); /* driving strength */
+ i2c_reg_write(addr, 0x2c, 0x00); /* configure N value */
+ i2c_reg_write(addr, 0x2d, 0x00); /* configure N value */
+ i2c_reg_write(addr, 0x2e, 0x0c); /* configure N value */
+ i2c_reg_write(addr, 0x76, 0xff); /* clear all interrupt */
+ dp501_setbits(addr, 0x78, 0x03); /* clear all interrupt */
+ i2c_reg_write(addr, 0x75, 0xf8); /* aux channel reset */
+ i2c_reg_write(addr, 0x75, 0x00); /* clear aux channel reset */
+ i2c_reg_write(addr, 0x87, 0x70); /* set retry counter as 7 */
if (dp501_detect_cable_adapter(addr)) {
printf(DVI/HDMI cable adapter detected\n);
@@ -69,16 +92,6 @@ void dp501_powerup(u8 addr)
dp501_clrbits(addr, 0x00, 0x08); /* DVI/HDMI HDCP operation */
} else {
printf(no DVI/HDMI cable adapter detected\n);
- i2c_reg_write(addr + 2, 0x00, 0x18); /* driving strength */
- i2c_reg_write(addr + 2, 0x03, 0x06); /* driving strength */
- i2c_reg_write(addr, 0x2c, 0x00); /* configure N value */
- i2c_reg_write(addr, 0x2d, 0x00); /* configure N value */
- i2c_reg_write(addr, 0x2e, 0x0c); /* configure N value */
- i2c_reg_write(addr, 0x76, 0xff); /* clear all interrupt */
- dp501_setbits(addr, 0x78, 0x03); /* clear all interrupt */
- i2c_reg_write(addr, 0x75, 0xf8); /* aux channel reset */
- i2c_reg_write(addr, 0x75, 0x00); /* clear aux channel reset */
- i2c_reg_write(addr, 0x87, 0x70); /* set retry counter as 7 */
dp501_setbits(addr, 0x00, 0x08); /* for DP HDCP operation */
dp501_link_training(addr);
diff --git a/board/gdsys/common/osd.c b/board/gdsys/common/osd.c
index c49cd9a..a839a4e
[U-Boot] [PATCH v4 09/13] board: gdsys: Make gdsys osd hardware detection more robust
From: Dirk Eibach dirk.eib...@gdsys.cc
Signed-off-by: Dirk Eibach dirk.eib...@gdsys.cc
---
Changes in v4: None
Changes in v3: None
Changes in v2: None
board/gdsys/405ep/iocon.c | 17 ++-
board/gdsys/common/osd.c | 113 +++--
drivers/i2c/ihs_i2c.c | 1 -
include/configs/dlvision-10g.h | 2 -
include/configs/iocon.h| 6 ---
5 files changed, 79 insertions(+), 60 deletions(-)
diff --git a/board/gdsys/405ep/iocon.c b/board/gdsys/405ep/iocon.c
index 079dfb2..6ae15e1 100644
--- a/board/gdsys/405ep/iocon.c
+++ b/board/gdsys/405ep/iocon.c
@@ -15,7 +15,6 @@
#include 405ep.h
#include gdsys_fpga.h
-#include ../common/dp501.h
#include ../common/osd.h
#include ../common/mclink.h
@@ -99,8 +98,6 @@ enum {
unsigned int mclink_fpgacount;
struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR;
-int dp501_i2c[] = CONFIG_SYS_DP501_I2C;
-
static int setup_88e1518(const char *bus, unsigned char addr);
int fpga_set_reg(u32 fpga, u16 *reg, off_t regoff, u16 data)
@@ -374,20 +371,16 @@ int last_stage_init(void)
u16 fpga_features;
int feature_carrier_speed = fpga_features (14);
bool ch0_rgmii2_present = false;
- int old_bus = i2c_get_bus_num();
FPGA_GET_REG(0, fpga_features, fpga_features);
- /* Turn on Parade DP501 */
- pca9698_direction_output(0x20, 9, 1);
- udelay(50);
-
- i2c_set_bus_num(dp501_i2c[0]);
- dp501_powerup(0x08);
- i2c_set_bus_num(old_bus);
+ if (!legacy) {
+ /* Turn on Parade DP501 */
+ pca9698_direction_output(0x20, 9, 1);
+ udelay(50);
- if (!legacy)
ch0_rgmii2_present = !pca9698_get_value(0x20, 30);
+ }
print_fpga_info(0, ch0_rgmii2_present);
osd_probe(0);
diff --git a/board/gdsys/common/osd.c b/board/gdsys/common/osd.c
index a839a4e..1c765e4 100644
--- a/board/gdsys/common/osd.c
+++ b/board/gdsys/common/osd.c
@@ -9,6 +9,7 @@
#include i2c.h
#include malloc.h
+#include dp501.h
#include gdsys_fpga.h
#define CH7301_I2C_ADDR 0x75
@@ -24,6 +25,8 @@
#define SIL1178_MASTER_I2C_ADDRESS 0x38
#define SIL1178_SLAVE_I2C_ADDRESS 0x39
+#define DP501_I2C_ADDR 0x08
+
#define PIXCLK_640_480_60 2518
enum {
@@ -54,18 +57,23 @@ u16 *buf;
unsigned int max_osd_screen = CONFIG_SYS_OSD_SCREENS - 1;
-#ifdef CONFIG_SYS_CH7301
-int ch7301_i2c[] = CONFIG_SYS_CH7301_I2C;
+#ifdef CONFIG_SYS_ICS8N3QV01_I2C
+int ics8n3qv01_i2c[] = CONFIG_SYS_ICS8N3QV01_I2C;
#endif
-#ifdef CONFIG_SYS_ICS8N3QV01
-int ics8n3qv01_i2c[] = CONFIG_SYS_ICS8N3QV01_I2C;
+#ifdef CONFIG_SYS_CH7301_I2C
+int ch7301_i2c[] = CONFIG_SYS_CH7301_I2C;
#endif
-#ifdef CONFIG_SYS_SIL1178
+#ifdef CONFIG_SYS_SIL1178_I2C
int sil1178_i2c[] = CONFIG_SYS_SIL1178_I2C;
#endif
+#ifdef CONFIG_SYS_DP501_I2C
+int dp501_i2c[] = CONFIG_SYS_DP501_I2C;
+#endif
+
+
#ifdef CONFIG_SYS_MPC92469AC
static void mpc92469ac_calc_parameters(unsigned int fout,
unsigned int *post_div, unsigned int *feedback_div)
@@ -118,7 +126,7 @@ static void mpc92469ac_set(unsigned screen, unsigned int
fout)
}
#endif
-#ifdef CONFIG_SYS_ICS8N3QV01
+#ifdef CONFIG_SYS_ICS8N3QV01_I2C
static unsigned int ics8n3qv01_get_fout_calc(unsigned index)
{
@@ -283,6 +291,8 @@ int osd_probe(unsigned screen)
u16 features;
u8 value;
int old_bus = i2c_get_bus_num();
+ bool pixclock_present = false;
+ bool output_driver_present = false;
FPGA_GET_REG(0, osd.version, version);
FPGA_GET_REG(0, osd.features, features);
@@ -297,51 +307,76 @@ int osd_probe(unsigned screen)
printf(OSD%d: Digital-OSD version %01d.%02d, %d x%d characters\n,
screen, version/100, version%100, base_width, base_height);
-#ifdef CONFIG_SYS_CH7301
- i2c_set_bus_num(ch7301_i2c[screen]);
- value = i2c_reg_read(CH7301_I2C_ADDR, CH7301_DID);
- if (value != 0x17) {
- printf( Probing CH7301 failed, DID %02x\n, value);
- i2c_set_bus_num(old_bus);
- return -1;
- }
- i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPCP, 0x08);
- i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPD, 0x16);
- i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPF, 0x60);
- i2c_reg_write(CH7301_I2C_ADDR, CH7301_DC, 0x09);
- i2c_reg_write(CH7301_I2C_ADDR, CH7301_PM, 0xc0);
-#endif
+ /* setup pixclock */
#ifdef CONFIG_SYS_MPC92469AC
+ pixclock_present = true;
mpc92469ac_set(screen, PIXCLK_640_480_60);
#endif
-#ifdef CONFIG_SYS_ICS8N3QV01
+#ifdef CONFIG_SYS_ICS8N3QV01_I2C
i2c_set_bus_num(ics8n3qv01_i2c[screen]);
- ics8n3qv01_set(PIXCLK_640_480_60);
+ if (!i2c_probe(ICS8N3QV01_I2C_ADDR)) {
+ ics8n3qv01_set(PIXCLK_640_480_60);
+ pixclock_present = true;
+ }
#endif
-#ifdef CONFIG_SYS_SIL1178
+ if (!pixclock_present)
+ printf( no
[U-Boot] [PATCH v4 10/13] board: gdsys: Enable scrambling on DP501
From: Dirk Eibach dirk.eib...@gdsys.cc For proper displayport performance, scrambling has to be enabled, but is turned off on DP501 by default. Signed-off-by: Dirk Eibach dirk.eib...@gdsys.cc --- Changes in v4: None Changes in v3: None Changes in v2: None board/gdsys/common/dp501.c | 1 + 1 file changed, 1 insertion(+) diff --git a/board/gdsys/common/dp501.c b/board/gdsys/common/dp501.c index 7958bae..7eb15ed 100644 --- a/board/gdsys/common/dp501.c +++ b/board/gdsys/common/dp501.c @@ -61,6 +61,7 @@ void dp501_powerup(u8 addr) i2c_reg_write(addr, 0x71, 0x20); /* Enable Aux burst write */ dp501_setbits(addr, 0x78, 0x30); /* Disable HPD2 IRQ */ dp501_clrbits(addr, 0x2f, 0x40); /* Link FIFO reset selection */ + dp501_clrbits(addr, 0x60, 0x20); /* Enable scrambling */ #ifdef CONFIG_SYS_DP501_VCAPCTRL0 i2c_reg_write(addr, 0x24, CONFIG_SYS_DP501_VCAPCTRL0); -- 1.8.3 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v4 11/13] board: iocon: Modify iocon hardware startup
From: Dirk Eibach dirk.eib...@gdsys.cc
To avoid peer ChReceivePathStatus-messages on iocon startup, initialize
PHYs as soon as possible.
Signed-off-by: Dirk Eibach dirk.eib...@gdsys.cc
---
Changes in v4: None
Changes in v3: None
Changes in v2: None
board/gdsys/405ep/iocon.c | 9 -
1 file changed, 4 insertions(+), 5 deletions(-)
diff --git a/board/gdsys/405ep/iocon.c b/board/gdsys/405ep/iocon.c
index 6ae15e1..1bac970 100644
--- a/board/gdsys/405ep/iocon.c
+++ b/board/gdsys/405ep/iocon.c
@@ -377,14 +377,10 @@ int last_stage_init(void)
if (!legacy) {
/* Turn on Parade DP501 */
pca9698_direction_output(0x20, 9, 1);
- udelay(50);
ch0_rgmii2_present = !pca9698_get_value(0x20, 30);
}
- print_fpga_info(0, ch0_rgmii2_present);
- osd_probe(0);
-
/* wait for FPGA done */
for (k = 0; k ARRAY_SIZE(mclink_controllers); ++k) {
unsigned int ctr = 0;
@@ -413,13 +409,16 @@ int last_stage_init(void)
}
}
- /* wait for slave-PLLs to be up and running */
+ /* give slave-PLLs and Parade DP501 some time to be up and running */
udelay(50);
mclink_fpgacount = CONFIG_SYS_MCLINK_MAX;
slaves = mclink_probe();
mclink_fpgacount = 0;
+ print_fpga_info(0, ch0_rgmii2_present);
+ osd_probe(0);
+
if (slaves = 0)
return 0;
--
1.8.3
___
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U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v4 0/13] Fixes on gdsys boards and some new functionality
From: Dirk Eibach dirk.eib...@gdsys.cc Changes in v4: - describe CONFIG_FIT_DISABLE_SHA256 in README Changes in v3: - describe ihs_i2c in README Changes in v2: - make sha256 support optional - move ihs_i2c to drivers/i2c - split unrelated changes - use defines for I2C bus numbers Dirk Eibach (13): board: controlcenterd: Fix pci access board: gdsys: Adapt sdhc_boot.c to mmc_get_env_addr API change board: controlcenterd: Use new API for setting i2c bus board: iocon: Support DisplayPort hardware i2c: IHS I2C master driver board: gdsys: Fix dlvision-10g I2C configuration board: gdsys: Increase iocon and dlv10g version string board: gdsys: Configure bridge on DP501 to support DDC only board: gdsys: Make gdsys osd hardware detection more robust board: gdsys: Enable scrambling on DP501 board: iocon: Modify iocon hardware startup board: gdsys: Remove commands to reduce footprint fit: make sha256 support optional README| 20 board/gdsys/405ep/iocon.c | 14 ++- board/gdsys/common/Makefile | 2 +- board/gdsys/common/dp501.c| 35 -- board/gdsys/common/osd.c | 189 +++ board/gdsys/p1022/controlcenterd-id.c | 13 ++- board/gdsys/p1022/controlcenterd.c| 6 +- board/gdsys/p1022/sdhc_boot.c | 2 +- drivers/i2c/Makefile | 1 + drivers/i2c/ihs_i2c.c | 203 ++ include/configs/controlcenterd.h | 7 +- include/configs/dlvision-10g.h| 29 - include/configs/io.h | 8 +- include/configs/iocon.h | 35 -- include/configs/neo.h | 9 +- include/gdsys_fpga.h | 25 ++--- include/image.h | 5 + 17 files changed, 454 insertions(+), 149 deletions(-) create mode 100644 drivers/i2c/ihs_i2c.c -- 1.8.3 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v4 12/13] board: gdsys: Remove commands to reduce footprint
From: Dirk Eibach dirk.eib...@gdsys.cc Commit 2842c1c fit: add sha256 support badly increased memory footprint, so some of our boards did not build anymore. Since monitor base must not be changed I removed some commands to save memory. Maybe making sha256 optional for fit would be an option for the future since it really has some beefy footprint. Signed-off-by: Dirk Eibach dirk.eib...@gdsys.cc --- Changes in v4: None Changes in v3: None Changes in v2: None include/configs/dlvision-10g.h | 7 ++- include/configs/io.h | 7 ++- include/configs/iocon.h| 4 include/configs/neo.h | 8 ++-- 4 files changed, 22 insertions(+), 4 deletions(-) diff --git a/include/configs/dlvision-10g.h b/include/configs/dlvision-10g.h index 08ab5c3..2567a22 100644 --- a/include/configs/dlvision-10g.h +++ b/include/configs/dlvision-10g.h @@ -64,9 +64,14 @@ /* * Commands additional to the ones defined in amcc-common.h */ -#define CONFIG_CMD_CACHE #define CONFIG_CMD_DTT +#undef CONFIG_CMD_DHCP +#undef CONFIG_CMD_DIAG #undef CONFIG_CMD_EEPROM +#undef CONFIG_CMD_ELF +#undef CONFIG_CMD_I2C +#undef CONFIG_CMD_IRQ +#undef CONFIG_CMD_NFS /* * SDRAM configuration (please see cpu/ppc/sdram.[ch]) diff --git a/include/configs/io.h b/include/configs/io.h index 9da6cc6..649c0fb 100644 --- a/include/configs/io.h +++ b/include/configs/io.h @@ -64,9 +64,14 @@ /* * Commands additional to the ones defined in amcc-common.h */ -#define CONFIG_CMD_CACHE #define CONFIG_CMD_DTT +#undef CONFIG_CMD_DHCP +#undef CONFIG_CMD_DIAG #undef CONFIG_CMD_EEPROM +#undef CONFIG_CMD_ELF +#undef CONFIG_CMD_I2C +#undef CONFIG_CMD_IRQ +#undef CONFIG_CMD_NFS /* * SDRAM configuration (please see cpu/ppc/sdram.[ch]) diff --git a/include/configs/iocon.h b/include/configs/iocon.h index 1836d12..35ba1bd 100644 --- a/include/configs/iocon.h +++ b/include/configs/iocon.h @@ -64,6 +64,10 @@ #define CONFIG_CMD_CACHE #define CONFIG_CMD_FPGAD #undef CONFIG_CMD_EEPROM +#undef CONFIG_CMD_ELF +#undef CONFIG_CMD_I2C +#undef CONFIG_CMD_IRQ +#undef CONFIG_CMD_NFS /* * SDRAM configuration (please see cpu/ppc/sdram.[ch]) diff --git a/include/configs/neo.h b/include/configs/neo.h index d549985..75dc862 100644 --- a/include/configs/neo.h +++ b/include/configs/neo.h @@ -61,10 +61,14 @@ /* * Commands additional to the ones defined in amcc-common.h */ -#define CONFIG_CMD_CACHE -#define CONFIG_CMD_DATE #define CONFIG_CMD_DTT +#undef CONFIG_CMD_DHCP +#undef CONFIG_CMD_DIAG #undef CONFIG_CMD_EEPROM +#undef CONFIG_CMD_ELF +#undef CONFIG_CMD_I2C +#undef CONFIG_CMD_IRQ +#undef CONFIG_CMD_NFS /* * SDRAM configuration (please see cpu/ppc/sdram.[ch]) -- 1.8.3 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] ARM: tegra: Use mem size from MC rather than ODMDATA
Dear Stephen, In message 53b47f6f.1090...@wwwdotorg.org you wrote: Is there a specific reason for not using get_ram_size()? Since we know the exact RAM size, we may as well simply use it directly rather than probing for it. You _think_ you know the size, but you can never be sure that all this RAM is actually present and working. There has been many discussions before why using get_ram_size() makes a lot of sense even in fixed size RAM configurations. Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de You have the capacity to learn from mistakes. You'll learn a lot today. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v4 0/13] Fixes on gdsys boards and some new functionality
patman has decided to send some patches of the v4 series with a v3 label. I am not sure what to do about this. Ideas anybody? Cheers Dirk ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] : Enhancement request to get flash device specific information
Hi U-boot team, I am looking for u-boot command which can give me flash device specific properties. For example, there should be dedicated commands to get the flash memory size, sector size, page size etc. Currently I found there is command sf probe for spi flash device which is returning device properties into text format as below: SF : Detected N25Q128A with page size 256 Bytes, erase size 64 KiB, total 16 MiB Similarly I found there is command nand info for nand device which is also returning device properties into text format. These commands (sf probe and nand info) are giving device information in form of message. Which does not meet my requirement. Actually I would like to integrate u-boot with my tool, where tool will run u-boot command to get the device information. Based on device information tool will react. Here I am looking for some dedicated command which return these property separately. It is difficult to parse the message string to get individual Let say we includes following commands: nand info pagesize/sectorsize/size/device sf info pagesize/sectorsize/size/device for example: nand info pagesize command should return page size ( e.g. *256*) nand info sectorsize command should return sector size (e.g. *65536* which is 64K) nand info size command should return the total size (e.g. *268435456 *which is 16 MB) Could you please consider this enhancement request in u-boot? Please comment. Regards, Heera ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 04/10] arm: ls102xa: Add etsec support for LS102xA
Signed-off-by: Alison Wang alison.w...@freescale.com
---
Change log:
v2: Add private mdio read and write support.
drivers/net/fsl_mdio.c | 24 +++-
drivers/net/tsec.c | 7 +++
include/fsl_mdio.h | 3 +++
include/tsec.h | 7 ++-
4 files changed, 35 insertions(+), 6 deletions(-)
diff --git a/drivers/net/fsl_mdio.c b/drivers/net/fsl_mdio.c
index 8d09f5d..3081228 100644
--- a/drivers/net/fsl_mdio.c
+++ b/drivers/net/fsl_mdio.c
@@ -12,6 +12,15 @@
#include asm/io.h
#include asm/errno.h
+void tsec_mdio_sync(void)
+{
+#if defined(CONFIG_PPC)
+ asm(sync);
+#elif defined(CONFIG_ARM)
+ asm(dsb);
+#endif
+}
+
void tsec_local_mdio_write(struct tsec_mii_mng __iomem *phyregs, int port_addr,
int dev_addr, int regnum, int value)
{
@@ -19,7 +28,7 @@ void tsec_local_mdio_write(struct tsec_mii_mng __iomem
*phyregs, int port_addr,
out_be32(phyregs-miimadd, (port_addr 8) | (regnum 0x1f));
out_be32(phyregs-miimcon, value);
- asm(sync);
+ tsec_mdio_sync();
while ((in_be32(phyregs-miimind) MIIMIND_BUSY) timeout--)
;
@@ -37,11 +46,11 @@ int tsec_local_mdio_read(struct tsec_mii_mng __iomem
*phyregs, int port_addr,
/* Clear the command register, and wait */
out_be32(phyregs-miimcom, 0);
- asm(sync);
+ tsec_mdio_sync();
/* Initiate a read command, and wait */
out_be32(phyregs-miimcom, MIIMCOM_READ_CYCLE);
- asm(sync);
+ tsec_mdio_sync();
/* Wait for the the indication that the read is done */
while ((in_be32(phyregs-miimind) (MIIMIND_NOTVALID | MIIMIND_BUSY))
@@ -98,8 +107,13 @@ int fsl_pq_mdio_init(bd_t *bis, struct fsl_pq_mdio_info
*info)
return -1;
}
- bus-read = tsec_phy_read;
- bus-write = tsec_phy_write;
+ if (info-priv_mdio_read) {
+ bus-read = info-priv_mdio_read;
+ bus-write = info-priv_mdio_write;
+ } else {
+ bus-read = tsec_phy_read;
+ bus-write = tsec_phy_write;
+ }
bus-reset = fsl_pq_mdio_reset;
sprintf(bus-name, info-name);
diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c
index e9138f0..a220221 100644
--- a/drivers/net/tsec.c
+++ b/drivers/net/tsec.c
@@ -20,6 +20,7 @@
#include fsl_mdio.h
#include asm/errno.h
#include asm/processor.h
+#include asm/io.h
DECLARE_GLOBAL_DATA_PTR;
@@ -270,6 +271,9 @@ void redundant_init(struct eth_device *dev)
out_be32(regs-tstat, TSTAT_CLEAR_THALT);
out_be32(regs-rstat, RSTAT_CLEAR_RHALT);
clrbits_be32(regs-dmactrl, DMACTRL_GRS | DMACTRL_GTS);
+#ifdef CONFIG_LS102xA
+ setbits_be32(regs-dmactrl, DMACTRL_LE);
+#endif
do {
uint16_t status;
@@ -366,6 +370,9 @@ static void startup_tsec(struct eth_device *dev)
out_be32(regs-tstat, TSTAT_CLEAR_THALT);
out_be32(regs-rstat, RSTAT_CLEAR_RHALT);
clrbits_be32(regs-dmactrl, DMACTRL_GRS | DMACTRL_GTS);
+#ifdef CONFIG_LS102xA
+ setbits_be32(regs-dmactrl, DMACTRL_LE);
+#endif
}
/* This returns the status bits of the device. The return value
diff --git a/include/fsl_mdio.h b/include/fsl_mdio.h
index a531edf..fb7df08 100644
--- a/include/fsl_mdio.h
+++ b/include/fsl_mdio.h
@@ -57,6 +57,9 @@ int memac_mdio_read(struct mii_dev *bus, int port_addr, int
dev_addr,
struct fsl_pq_mdio_info {
struct tsec_mii_mng __iomem *regs;
char *name;
+ int (*priv_mdio_read)(struct mii_dev *bus, int addr, int devad, int
reg);
+ int (*priv_mdio_write)(struct mii_dev *bus, int addr, int devad, int
reg,
+ u16 val);
};
int fsl_pq_mdio_init(bd_t *bis, struct fsl_pq_mdio_info *info);
diff --git a/include/tsec.h b/include/tsec.h
index 2054715..5b74f67 100644
--- a/include/tsec.h
+++ b/include/tsec.h
@@ -20,10 +20,14 @@
#include net.h
#include config.h
#include phy.h
-#include fsl_mdio.h
+#ifdef CONFIG_LS102xA
+#define TSEC_SIZE 0x4
+#define TSEC_MDIO_OFFSET 0x4
+#else
#define TSEC_SIZE 0x01000
#define TSEC_MDIO_OFFSET 0x01000
+#endif
#define CONFIG_SYS_MDIO_BASE_ADDR (MDIO_BASE_ADDR + 0x520)
@@ -128,6 +132,7 @@
#define DMACTRL_INIT_SETTINGS 0x00c3
#define DMACTRL_GRS0x0010
#define DMACTRL_GTS0x0008
+#define DMACTRL_LE 0x8000
#define TSTAT_CLEAR_THALT 0x8000
#define RSTAT_CLEAR_RHALT 0x0080
--
1.8.0
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[U-Boot] [PATCH v2 01/10] arm: ls102xa: Add Freescale LS102xA SoC support
The QorIQ LS1 family is built on Layerscape architecture,
the industry's first software-aware, core-agnostic networking
architecture to offer unprecedented efficiency and scale.
Freescale LS102xA is a set of SoCs combines two ARM
Cortex-A7 cores that have been optimized for high
reliability and pack the highest level of integration
available for sub-3 W embedded communications processors
with Layerscape architecture and with a comprehensive
enablement model focused on ease of programmability.
Signed-off-by: Alison Wang alison.w...@freescale.com
Signed-off-by: Jason Jin jason@freescale.com
Signed-off-by: Jingchang Lu jingchang...@freescale.com
Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
---
Change log:
v2: Add serdes support.
Update DDR frequency and data rate information.
Fix overflow condition error for the timer.
arch/arm/cpu/armv7/ls102xa/Makefile | 12 +
arch/arm/cpu/armv7/ls102xa/clock.c| 131 ++
arch/arm/cpu/armv7/ls102xa/cpu.c | 103 +
arch/arm/cpu/armv7/ls102xa/fdt.c | 73
arch/arm/cpu/armv7/ls102xa/fsl_ls1_serdes.c | 119 ++
arch/arm/cpu/armv7/ls102xa/fsl_ls1_serdes.h | 12 +
arch/arm/cpu/armv7/ls102xa/ls102xa_serdes.c | 41 ++
arch/arm/cpu/armv7/ls102xa/timer.c| 127 ++
arch/arm/include/asm/arch-ls102xa/clock.h | 23 ++
arch/arm/include/asm/arch-ls102xa/config.h| 69
arch/arm/include/asm/arch-ls102xa/fsl_serdes.h| 33 ++
arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 461 ++
arch/arm/include/asm/arch-ls102xa/imx-regs.h | 53 +++
arch/arm/include/asm/config.h | 4 +
arch/arm/include/asm/io.h | 8 +-
drivers/watchdog/Makefile | 2 +-
16 files changed, 1269 insertions(+), 2 deletions(-)
create mode 100644 arch/arm/cpu/armv7/ls102xa/Makefile
create mode 100644 arch/arm/cpu/armv7/ls102xa/clock.c
create mode 100644 arch/arm/cpu/armv7/ls102xa/cpu.c
create mode 100644 arch/arm/cpu/armv7/ls102xa/fdt.c
create mode 100644 arch/arm/cpu/armv7/ls102xa/fsl_ls1_serdes.c
create mode 100644 arch/arm/cpu/armv7/ls102xa/fsl_ls1_serdes.h
create mode 100644 arch/arm/cpu/armv7/ls102xa/ls102xa_serdes.c
create mode 100644 arch/arm/cpu/armv7/ls102xa/timer.c
create mode 100644 arch/arm/include/asm/arch-ls102xa/clock.h
create mode 100644 arch/arm/include/asm/arch-ls102xa/config.h
create mode 100644 arch/arm/include/asm/arch-ls102xa/fsl_serdes.h
create mode 100644 arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
create mode 100644 arch/arm/include/asm/arch-ls102xa/imx-regs.h
diff --git a/arch/arm/cpu/armv7/ls102xa/Makefile
b/arch/arm/cpu/armv7/ls102xa/Makefile
new file mode 100644
index 000..d82ce8d
--- /dev/null
+++ b/arch/arm/cpu/armv7/ls102xa/Makefile
@@ -0,0 +1,12 @@
+#
+# Copyright 2014 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += cpu.o
+obj-y += clock.o
+obj-y += timer.o
+
+obj-$(CONFIG_OF_LIBFDT) += fdt.o
+obj-$(CONFIG_SYS_HAS_SERDES) += fsl_ls1_serdes.o ls102xa_serdes.o
diff --git a/arch/arm/cpu/armv7/ls102xa/clock.c
b/arch/arm/cpu/armv7/ls102xa/clock.c
new file mode 100644
index 000..75bb0e9
--- /dev/null
+++ b/arch/arm/cpu/armv7/ls102xa/clock.c
@@ -0,0 +1,131 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include asm/io.h
+#include asm/arch/immap_ls102xa.h
+#include asm/arch/clock.h
+#include fsl_ifc.h
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifndef CONFIG_SYS_FSL_NUM_CC_PLLS
+#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
+#endif
+
+void get_sys_info(struct sys_info *sys_info)
+{
+ struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+#ifdef CONFIG_FSL_IFC
+ struct fsl_ifc *ifc_regs = (void *)CONFIG_SYS_IFC_ADDR;
+ u32 ccr;
+#endif
+ struct ccsr_clk *clk = (void *)(CONFIG_SYS_FSL_LS1_CLK_ADDR);
+ unsigned int cpu;
+ const u8 core_cplx_pll[6] = {
+ [0] = 0,/* CC1 PPL / 1 */
+ [1] = 0,/* CC1 PPL / 2 */
+ [4] = 1,/* CC2 PPL / 1 */
+ [5] = 1,/* CC2 PPL / 2 */
+ };
+
+ const u8 core_cplx_pll_div[6] = {
+ [0] = 1,/* CC1 PPL / 1 */
+ [1] = 2,/* CC1 PPL / 2 */
+ [4] = 1,/* CC2 PPL / 1 */
+ [5] = 2,/* CC2 PPL / 2 */
+ };
+
+ uint i;
+ uint freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS];
+ uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS];
+ unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
+
+ sys_info-freq_systembus = sysclk;
+#ifdef CONFIG_DDR_CLK_FREQ
+ sys_info-freq_ddrbus = CONFIG_DDR_CLK_FREQ;
+#else
+ sys_info-freq_ddrbus = sysclk;
+#endif
+
+ sys_info-freq_systembus *= (in_be32(gur-rcwsr[0])
+
[U-Boot] [PATCH v2 05/10] arm: ls102xa: Add esdhc support for LS102xA
Signed-off-by: Alison Wang alison.w...@freescale.com
---
Change log:
v2: no change.
drivers/mmc/fsl_esdhc.c | 4 ++--
include/fsl_esdhc.h | 14 +-
2 files changed, 15 insertions(+), 3 deletions(-)
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index 5541613..aec459f 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -96,7 +96,7 @@ static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct
mmc_data *data)
else if (cmd-resp_type MMC_RSP_PRESENT)
xfertyp |= XFERTYP_RSPTYP_48;
-#if defined(CONFIG_MX53) || defined(CONFIG_PPC_T4240)
+#if defined(CONFIG_MX53) || defined(CONFIG_PPC_T4240) ||
defined(CONFIG_LS102xA)
if (cmd-cmdidx == MMC_CMD_STOP_TRANSMISSION)
xfertyp |= XFERTYP_CMDTYP_ABORT;
#endif
@@ -561,7 +561,7 @@ int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg
*cfg)
memset(cfg-cfg, 0, sizeof(cfg-cfg));
voltage_caps = 0;
- caps = regs-hostcapblt;
+ caps = esdhc_read32(regs-hostcapblt);
#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC135
caps = caps ~(ESDHC_HOSTCAPBLT_SRS |
diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h
index 9814964..c1b6648 100644
--- a/include/fsl_esdhc.h
+++ b/include/fsl_esdhc.h
@@ -162,7 +162,19 @@ struct fsl_esdhc_cfg {
};
/* Select the correct accessors depending on endianess */
-#if __BYTE_ORDER == __LITTLE_ENDIAN
+#if defined CONFIG_SYS_FSL_ESDHC_LE
+#define esdhc_read32 in_le32
+#define esdhc_write32 out_le32
+#define esdhc_clrsetbits32 clrsetbits_le32
+#define esdhc_clrbits32clrbits_le32
+#define esdhc_setbits32setbits_le32
+#elif defined(CONFIG_SYS_FSL_ESDHC_BE)
+#define esdhc_read32in_be32
+#define esdhc_write32 out_be32
+#define esdhc_clrsetbits32 clrsetbits_be32
+#define esdhc_clrbits32 clrbits_be32
+#define esdhc_setbits32 setbits_be32
+#elif __BYTE_ORDER == __LITTLE_ENDIAN
#define esdhc_read32 in_le32
#define esdhc_write32 out_le32
#define esdhc_clrsetbits32 clrsetbits_le32
--
1.8.0
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[U-Boot] [PATCH v2 03/10] net: Merge asm/fsl_enet.h into fsl_mdio.h
From: Claudiu Manoil claudiu.man...@freescale.com
fsl_enet.h defines the mapping of the usual MII management
registers, which are included in the MDIO register block
common to Freescale ethernet controllers. So it shouldn't
depend on the CPU architecture but it should be actually
part of the arch independent fsl_mdio.h.
To remove the arch dependency, merge the content of
asm/fsl_enet.h into fsl_mdio.h.
Some files (like fm_eth.h) were simply including fsl_enet.h
only for phy.h. These were updated to include phy.h instead.
Signed-off-by: Claudiu Manoil claudiu.man...@freescale.com
---
Change log:
v2: no change.
arch/powerpc/include/asm/fsl_enet.h | 24
board/freescale/mpc8360emds/mpc8360emds.c | 2 +-
board/freescale/mpc837xemds/mpc837xemds.c | 1 -
drivers/net/fm/dtsec.c| 1 -
drivers/net/fm/fm.h | 2 +-
drivers/net/fm/init.c | 1 +
drivers/net/fm/memac.c| 1 -
drivers/net/fm/tgec.c | 1 -
drivers/net/fsl_mdio.c| 1 -
drivers/qe/uec.h | 1 -
include/fm_eth.h | 2 +-
include/fsl_mdio.h| 13 -
include/tsec.h| 2 +-
13 files changed, 17 insertions(+), 35 deletions(-)
delete mode 100644 arch/powerpc/include/asm/fsl_enet.h
diff --git a/arch/powerpc/include/asm/fsl_enet.h
b/arch/powerpc/include/asm/fsl_enet.h
deleted file mode 100644
index 96146b6..000
--- a/arch/powerpc/include/asm/fsl_enet.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * Copyright 2010 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier:GPL-2.0+
- */
-
-#ifndef __ASM_PPC_FSL_ENET_H
-#define __ASM_PPC_FSL_ENET_H
-
-#include phy.h
-
-struct tsec_mii_mng {
- u32 miimcfg;/* MII management configuration reg */
- u32 miimcom;/* MII management command reg */
- u32 miimadd;/* MII management address reg */
- u32 miimcon;/* MII management control reg */
- u32 miimstat; /* MII management status reg */
- u32 miimind;/* MII management indication reg */
- u32 ifstat; /* Interface Status Register */
-} __attribute__ ((packed));
-
-int fdt_fixup_phy_connection(void *blob, int offset, phy_interface_t phyc);
-
-#endif /* __ASM_PPC_FSL_ENET_H */
diff --git a/board/freescale/mpc8360emds/mpc8360emds.c
b/board/freescale/mpc8360emds/mpc8360emds.c
index ac96163..5ff9dff 100644
--- a/board/freescale/mpc8360emds/mpc8360emds.c
+++ b/board/freescale/mpc8360emds/mpc8360emds.c
@@ -11,13 +11,13 @@
#include i2c.h
#include miiphy.h
#include phy.h
+#include fsl_mdio.h
#if defined(CONFIG_PCI)
#include pci.h
#endif
#include spd_sdram.h
#include asm/mmu.h
#include asm/io.h
-#include asm/fsl_enet.h
#include asm/mmu.h
#if defined(CONFIG_OF_LIBFDT)
#include libfdt.h
diff --git a/board/freescale/mpc837xemds/mpc837xemds.c
b/board/freescale/mpc837xemds/mpc837xemds.c
index 0a3c972..c749e55 100644
--- a/board/freescale/mpc837xemds/mpc837xemds.c
+++ b/board/freescale/mpc837xemds/mpc837xemds.c
@@ -10,7 +10,6 @@
#include i2c.h
#include asm/io.h
#include asm/fsl_mpc83xx_serdes.h
-#include asm/fsl_enet.h
#include spd_sdram.h
#include tsec.h
#include libfdt.h
diff --git a/drivers/net/fm/dtsec.c b/drivers/net/fm/dtsec.c
index 78bbd43..8d3dc0e 100644
--- a/drivers/net/fm/dtsec.c
+++ b/drivers/net/fm/dtsec.c
@@ -7,7 +7,6 @@
#include common.h
#include asm/types.h
#include asm/io.h
-#include asm/fsl_enet.h
#include asm/fsl_dtsec.h
#include fsl_mdio.h
#include phy.h
diff --git a/drivers/net/fm/fm.h b/drivers/net/fm/fm.h
index 43de114..c8eba4f 100644
--- a/drivers/net/fm/fm.h
+++ b/drivers/net/fm/fm.h
@@ -8,8 +8,8 @@
#define __FM_H__
#include common.h
+#include phy.h
#include fm_eth.h
-#include asm/fsl_enet.h
#include asm/fsl_fman.h
/* Port ID */
diff --git a/drivers/net/fm/init.c b/drivers/net/fm/init.c
index cd787f4..7371dbf 100644
--- a/drivers/net/fm/init.c
+++ b/drivers/net/fm/init.c
@@ -6,6 +6,7 @@
#include common.h
#include asm/io.h
#include asm/fsl_serdes.h
+#include fsl_mdio.h
#include fm.h
diff --git a/drivers/net/fm/memac.c b/drivers/net/fm/memac.c
index 592a67f..9499290 100644
--- a/drivers/net/fm/memac.c
+++ b/drivers/net/fm/memac.c
@@ -12,7 +12,6 @@
#include phy.h
#include asm/types.h
#include asm/io.h
-#include asm/fsl_enet.h
#include asm/fsl_memac.h
#include fm.h
diff --git a/drivers/net/fm/tgec.c b/drivers/net/fm/tgec.c
index f450f80..5017123 100644
--- a/drivers/net/fm/tgec.c
+++ b/drivers/net/fm/tgec.c
@@ -12,7 +12,6 @@
#include phy.h
#include asm/types.h
#include asm/io.h
-#include asm/fsl_enet.h
#include asm/fsl_tgec.h
#include fm.h
diff --git a/drivers/net/fsl_mdio.c b/drivers/net/fsl_mdio.c
index 1d88e65..8d09f5d 100644
--- a/drivers/net/fsl_mdio.c
+++ b/drivers/net/fsl_mdio.c
@@ -11,7 +11,6 @@
#include
[U-Boot] [PATCH v2 0/9] arm: ls102xa: Add Freescale LS102xA SoC and LS1021AQDS/TWR board support
This series contain the support for Freescale LS102xA SoC and LS1021AQDS/TWR board. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 06/10] driver/ddr/freescale: Add support of accumulate ECC
From: York Sun york...@freescale.com If less than 8 ECC pins are used for DDR data bus width smaller than 64 bits, the 8-bit ECC code will be transmitted/received across several beats, and it will be used to check 64-bits of data once 8-bits of ECC are accumulated. Signed-off-by: York Sun york...@freescale.com --- Change log: v2: no change. drivers/ddr/fsl/ctrl_regs.c | 5 + 1 file changed, 5 insertions(+) diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c index dcf6287..fa9c257 100644 --- a/drivers/ddr/fsl/ctrl_regs.c +++ b/drivers/ddr/fsl/ctrl_regs.c @@ -693,6 +693,7 @@ static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr, unsigned int x32_en = 0;/* x32 enable */ unsigned int pchb8 = 0; /* precharge bit 8 enable */ unsigned int hse; /* Global half strength override */ + unsigned int acc_ecc_en = 0;/* Accumulated ECC enable */ unsigned int mem_halt = 0; /* memory controller halt */ unsigned int bi = 0;/* Bypass initialization */ @@ -736,6 +737,9 @@ static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr, ba_intlv_ctl = popts-ba_intlv_ctl; hse = popts-half_strength_driver_enable; + /* set when ddr bus width 64 */ + acc_ecc_en = (dbw != 0 ecc_en == 1) ? 1 : 0; + ddr-ddr_sdram_cfg = (0 | ((mem_en 0x1) 31) | ((sren 0x1) 30) @@ -752,6 +756,7 @@ static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr, | ((x32_en 0x1) 5) | ((pchb8 0x1) 4) | ((hse 0x1) 3) + | ((acc_ecc_en 0x1) 2) | ((mem_halt 0x1) 1) | ((bi 0x1) 0) ); -- 1.8.0 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 10/10] arm: ls102xa: Add basic support for LS1021ATWR board
Signed-off-by: Yuan Yao yao.y...@freescale.com Signed-off-by: Alison Wang alison.w...@freescale.com --- Change log: v2: New file. board/freescale/ls1021atwr/Makefile | 7 + board/freescale/ls1021atwr/README | 109 +++ board/freescale/ls1021atwr/ls1021atwr.c | 499 boards.cfg | 1 + include/configs/ls1021atwr.h| 285 ++ 5 files changed, 901 insertions(+) create mode 100644 board/freescale/ls1021atwr/Makefile create mode 100644 board/freescale/ls1021atwr/README create mode 100644 board/freescale/ls1021atwr/ls1021atwr.c create mode 100644 include/configs/ls1021atwr.h diff --git a/board/freescale/ls1021atwr/Makefile b/board/freescale/ls1021atwr/Makefile new file mode 100644 index 000..b5df668 --- /dev/null +++ b/board/freescale/ls1021atwr/Makefile @@ -0,0 +1,7 @@ +# +# Copyright 2014 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += ls1021atwr.o diff --git a/board/freescale/ls1021atwr/README b/board/freescale/ls1021atwr/README new file mode 100644 index 000..d2821cb --- /dev/null +++ b/board/freescale/ls1021atwr/README @@ -0,0 +1,109 @@ +Overview + +The LS1021ATWR is a Freescale reference board that hosts the LS1021A SoC. + +LS1021A SoC Overview +-- +The QorIQ LS1 family, which includes the LS1021A communications processor, +is built on Layerscape architecture, the industry's first software-aware, +core-agnostic networking architecture to offer unprecedented efficiency +and scale. + +A member of the value-performance tier, the QorIQ LS1021A processor provides +extensive integration and power efficiency for fanless, small form factor +enterprise networking applications. Incorporating dual ARM Cortex-A7 cores +running up to 1.0 GHz, the LS1021A processor delivers pre-silicon CoreMark +performance of over 6,000, as well as virtualization support, advanced +security features and the broadest array of high-speed interconnects and +optimized peripheral features ever offered in a sub-3 W processor. + +The QorIQ LS1021A processor features an integrated LCD controller, +CAN controller for implementing industrial protocols, DDR3L/4 running +up to 1600 MHz, integrated security engine and QUICC Engine, and ECC +protection on both L1 and L2 caches. The LS1021A processor is pin- and +software-compatible with the QorIQ LS1020A and LS1022A processors. + +The LS1021A SoC includes the following function and features: + + - ARM Cortex-A7 MPCore compliant with ARMv7-A architecture + - Dual high-preformance ARM Cortex-A7 cores, each core includes: + - 32 Kbyte L1 Instruction Cache and Data Cache for each core (ECC protection) + - 512 Kbyte shared coherent L2 Cache (with ECC protection) + - NEON Co-processor (per core) + - 40-bit physical addressing + - Vector floating-point support + - ARM Core-Link CCI-400 Cache Coherent Interconnect + - One DDR3L/DDR4 SDRAM memory controller with x8/x16/x32-bit configuration + supporting speeds up to 1600Mtps + - ECC and interleaving support + - VeTSEC Ethernet complex + - Up to 3x virtualized 10/100/1000 Ethernet controllers + - MII, RMII, RGMII, and SGMII support + - QoS, lossless flow control, and IEEE 1588 support + - 4-lane 6GHz SerDes + - High speed interconnect (4 SerDes lanes with are muxed for these protocol) + - Two PCI Express Gen2 controllers running at up to 5 GHz + - One Serial ATA 3.0 supporting 6 GT/s operation + - Two SGMII interfaces supporting 1000 Mbps + - Additional peripheral interfaces + - One high-speed USB 3.0 controller with integrated PHY and one high-speed + USB 2.00 controller with ULPI + - Integrated flash controller (IFC) with 16-bit interface + - Quad SPI NOR Flash + - One enhanced Secure digital host controller + - Display controller unit (DCU) 24-bit RGB (12-bit DDR pin interface) + - Ten UARTs comprised of two 16550 compliant DUARTs, and six low power + UARTs + - Three I2C controllers + - Eight FlexTimers four supporting PWM and four FlexCAN ports + - Four GPIO controllers supporting up to 109 general purpose I/O signals + - Integrated advanced audio block: + - Four synchronous audio interfaces (SAI) + - Sony/Philips Digital Interconnect Format (SPDIF) + - Asynchronous Sample Rate Converter (ASRC) + - Hardware based crypto offload engine + - IPSec forwarding at up to 1Gbps + - QorIQ Trust Architecture, Secure Boot, and ARM TrustZone supported + - Public key hardware accelerator + - True Random Number Generator (NIST Certified) + - Advanced Encryption Standard Accelerators (AESA) + - Data Encryption Standard Accelerators + - QUICC Engine ULite block + - Two universal communication controllers (TDM and HDLC) supporting 64 + multichannels, each running at 64 Kbps + - Support for 256 channels of HDLC + - QorIQ TrustArchitecture with Secure Boot, as well as ARM TrustZone supported + +LS1021ATWR board
[U-Boot] [PATCH v2 08/10] driver/ddr/fsl: Add support of overriding chip select write leveling
From: York Sun york...@freescale.com
JEDEC spec allows DRAM vendors to use prime DQ for write leveling. This
is not an issue unless some DQ pins are not connected. If a platform uses
regular DIMMs but with reduced DDR ECC pins, the prime DQ may end up on
those floating pins for the second rank. The workaround is to use a known
good chip select for this purpose.
Signed-off-by: York Sun york...@freescale.com
---
Change log:
v2: no change.
drivers/ddr/fsl/ctrl_regs.c | 3 +++
drivers/ddr/fsl/interactive.c | 2 ++
include/fsl_ddr_sdram.h | 2 ++
3 files changed, 7 insertions(+)
diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c
index fa9c257..462d471 100644
--- a/drivers/ddr/fsl/ctrl_regs.c
+++ b/drivers/ddr/fsl/ctrl_regs.c
@@ -2273,6 +2273,9 @@ compute_fsl_memctl_config_regs(const memctl_options_t
*popts,
if (ip_rev 0x40400)
unq_mrs_en = 1;
+ if (ip_rev 0x40700)
+ ddr-debug[18] = popts-cswl_override;
+
set_ddr_sdram_cfg_2(ddr, popts, unq_mrs_en);
set_ddr_sdram_mode(ddr, popts, common_dimm,
cas_latency, additive_latency, unq_mrs_en);
diff --git a/drivers/ddr/fsl/interactive.c b/drivers/ddr/fsl/interactive.c
index 7fb4187..6aa16b2 100644
--- a/drivers/ddr/fsl/interactive.c
+++ b/drivers/ddr/fsl/interactive.c
@@ -511,6 +511,7 @@ static void fsl_ddr_options_edit(fsl_ddr_info_t *pinfo,
CTRL_OPTIONS(wrlvl_override),
CTRL_OPTIONS(wrlvl_sample),
CTRL_OPTIONS(wrlvl_start),
+ CTRL_OPTIONS(cswl_override),
CTRL_OPTIONS(rcw_override),
CTRL_OPTIONS(rcw_1),
CTRL_OPTIONS(rcw_2),
@@ -801,6 +802,7 @@ static void print_memctl_options(const memctl_options_t
*popts)
CTRL_OPTIONS(wrlvl_override),
CTRL_OPTIONS(wrlvl_sample),
CTRL_OPTIONS(wrlvl_start),
+ CTRL_OPTIONS_HEX(cswl_override),
CTRL_OPTIONS(rcw_override),
CTRL_OPTIONS(rcw_1),
CTRL_OPTIONS(rcw_2),
diff --git a/include/fsl_ddr_sdram.h b/include/fsl_ddr_sdram.h
index e8a2db9..987119b 100644
--- a/include/fsl_ddr_sdram.h
+++ b/include/fsl_ddr_sdram.h
@@ -281,6 +281,7 @@ typedef struct memctl_options_partial_s {
#define DDR_DATA_BUS_WIDTH_64 0
#define DDR_DATA_BUS_WIDTH_32 1
#define DDR_DATA_BUS_WIDTH_16 2
+#define DDR_CSWL_CS0 0x0401
/*
* Generalized parameters for memory controller configuration,
* might be a little specific to the FSL memory controller
@@ -340,6 +341,7 @@ typedef struct memctl_options_s {
unsigned int cpo_override;
unsigned int write_data_delay; /* DQS adjust */
+ unsigned int cswl_override;
unsigned int wrlvl_override;
unsigned int wrlvl_sample; /* Write leveling */
unsigned int wrlvl_start;
--
1.8.0
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[U-Boot] [PATCH v2 07/10] driver/ddr/freescale: Fix DDR3 driver for ARM
From: York Sun york...@freescale.com Reading DDR register should use ddr_in32() for proper endianess. This patch fixes incorrect waiting time for ARM platforms. Signed-off-by: York Sun york...@freescale.com --- Change log: v2: no change. drivers/ddr/fsl/arm_ddr_gen3.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/ddr/fsl/arm_ddr_gen3.c b/drivers/ddr/fsl/arm_ddr_gen3.c index d4ed9ae..59f2fd6 100644 --- a/drivers/ddr/fsl/arm_ddr_gen3.c +++ b/drivers/ddr/fsl/arm_ddr_gen3.c @@ -194,7 +194,7 @@ step2: * For example, 2GB on 666MT/s 64-bit bus takes about 402ms * Let's wait for 800ms */ - bus_width = 3 - ((ddr-sdram_cfg SDRAM_CFG_DBW_MASK) + bus_width = 3 - ((ddr_in32(ddr-sdram_cfg) SDRAM_CFG_DBW_MASK) SDRAM_CFG_DBW_SHIFT); timeout = ((total_gb_size_per_controller (6 - bus_width)) * 100 / (get_ddr_freq(0) 20)) 1; -- 1.8.0 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 02/10] arm: ls102xa: Add i2c support for LS102xA
Signed-off-by: Alison Wang alison.w...@freescale.com
---
Change log:
v2: no change.
drivers/i2c/mxc_i2c.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c
index 48468d7..792fc40 100644
--- a/drivers/i2c/mxc_i2c.c
+++ b/drivers/i2c/mxc_i2c.c
@@ -423,7 +423,7 @@ static void * const i2c_bases[] = {
(void *)IMX_I2C2_BASE
#elif defined(CONFIG_MX31) || defined(CONFIG_MX35) || \
defined(CONFIG_MX51) || defined(CONFIG_MX53) || \
- defined(CONFIG_MX6)
+ defined(CONFIG_MX6) || defined(CONFIG_LS102xA)
(void *)I2C1_BASE_ADDR,
(void *)I2C2_BASE_ADDR,
(void *)I2C3_BASE_ADDR
--
1.8.0
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[U-Boot] [PATCH v2 09/10] arm: ls102xa: Add basic support for LS1021AQDS board
Signed-off-by: Alison Wang alison.w...@freescale.com Signed-off-by: Jason Jin jason@freescale.com Signed-off-by: York Sun york...@freescale.com Signed-off-by: Yuan Yao yao.y...@freescale.com Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com --- Change log: v2: Remove ethaddr/ipaddr setting. Add board maintainer. Add serdes and multiple ethernet controllers support. board/freescale/ls1021aqds/Makefile | 9 + board/freescale/ls1021aqds/README | 112 +++ board/freescale/ls1021aqds/ddr.c | 169 +++ board/freescale/ls1021aqds/ddr.h | 64 board/freescale/ls1021aqds/eth.c | 129 board/freescale/ls1021aqds/ls1021aqds.c | 244 +++ board/freescale/ls1021aqds/ls1021aqds_qixis.h | 35 +++ boards.cfg| 1 + include/common.h | 5 +- include/configs/ls1021aqds.h | 419 ++ lib/lmb.c | 2 +- 11 files changed, 1185 insertions(+), 4 deletions(-) create mode 100644 board/freescale/ls1021aqds/Makefile create mode 100644 board/freescale/ls1021aqds/README create mode 100644 board/freescale/ls1021aqds/ddr.c create mode 100644 board/freescale/ls1021aqds/ddr.h create mode 100644 board/freescale/ls1021aqds/eth.c create mode 100644 board/freescale/ls1021aqds/ls1021aqds.c create mode 100644 board/freescale/ls1021aqds/ls1021aqds_qixis.h create mode 100644 include/configs/ls1021aqds.h diff --git a/board/freescale/ls1021aqds/Makefile b/board/freescale/ls1021aqds/Makefile new file mode 100644 index 000..3b6903c --- /dev/null +++ b/board/freescale/ls1021aqds/Makefile @@ -0,0 +1,9 @@ +# +# Copyright 2014 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += ls1021aqds.o +obj-y += ddr.o +obj-y += eth.o diff --git a/board/freescale/ls1021aqds/README b/board/freescale/ls1021aqds/README new file mode 100644 index 000..c561776 --- /dev/null +++ b/board/freescale/ls1021aqds/README @@ -0,0 +1,112 @@ +Overview + +The LS1021AQDS is a Freescale reference board that hosts the LS1021A SoC. + +LS1021A SoC Overview +-- +The QorIQ LS1 family, which includes the LS1021A communications processor, +is built on Layerscape architecture, the industry's first software-aware, +core-agnostic networking architecture to offer unprecedented efficiency +and scale. + +A member of the value-performance tier, the QorIQ LS1021A processor provides +extensive integration and power efficiency for fanless, small form factor +enterprise networking applications. Incorporating dual ARM Cortex-A7 cores +running up to 1.0 GHz, the LS1021A processor delivers pre-silicon CoreMark +performance of over 6,000, as well as virtualization support, advanced +security features and the broadest array of high-speed interconnects and +optimized peripheral features ever offered in a sub-3 W processor. + +The QorIQ LS1021A processor features an integrated LCD controller, +CAN controller for implementing industrial protocols, DDR3L/4 running +up to 1600 MHz, integrated security engine and QUICC Engine, and ECC +protection on both L1 and L2 caches. The LS1021A processor is pin- and +software-compatible with the QorIQ LS1020A and LS1022A processors. + +The LS1021A SoC includes the following function and features: + + - ARM Cortex-A7 MPCore compliant with ARMv7-A architecture + - Dual high-preformance ARM Cortex-A7 cores, each core includes: + - 32 Kbyte L1 Instruction Cache and Data Cache for each core (ECC protection) + - 512 Kbyte shared coherent L2 Cache (with ECC protection) + - NEON Co-processor (per core) + - 40-bit physical addressing + - Vector floating-point support + - ARM Core-Link CCI-400 Cache Coherent Interconnect + - One DDR3L/DDR4 SDRAM memory controller with x8/x16/x32-bit configuration + supporting speeds up to 1600Mtps + - ECC and interleaving support + - VeTSEC Ethernet complex + - Up to 3x virtualized 10/100/1000 Ethernet controllers + - MII, RMII, RGMII, and SGMII support + - QoS, lossless flow control, and IEEE 1588 support + - 4-lane 6GHz SerDes + - High speed interconnect (4 SerDes lanes with are muxed for these protocol) + - Two PCI Express Gen2 controllers running at up to 5 GHz + - One Serial ATA 3.0 supporting 6 GT/s operation + - Two SGMII interfaces supporting 1000 Mbps + - Additional peripheral interfaces + - One high-speed USB 3.0 controller with integrated PHY and one high-speed + USB 2.00 controller with ULPI + - Integrated flash controller (IFC) with 16-bit interface + - Quad SPI NOR Flash + - One enhanced Secure digital host controller + - Display controller unit (DCU) 24-bit RGB (12-bit DDR pin interface) + - Ten UARTs comprised of two 16550 compliant DUARTs, and six low power + UARTs + - Three I2C controllers + - Eight FlexTimers four supporting PWM and
Re: [U-Boot] [PATCH v4 0/13] Fixes on gdsys boards and some new functionality
patman has decided to send some patches of the v4 series with a v3 label. I am not sure what to do about this. Ideas anybody? Ooops, sorry for the noise. patman did it right and sent v4 labels. It was just Gmail being extrasmart and grouping them in a thread. So only the first subject is shown. So any ideas how to stop Gmail being extrasmart? ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] SPL broken on i.mx31 platforms
Hi, On 07/03/2014 01:20 AM, Benoît Thébaudeau wrote: )Dear Helmut Raiger, On Wed, Jul 2, 2014 at 9:04 AM, Helmut Raiger helmut.rai...@hale.at wrote: the commit 41623c91 breaks the SPL on i.mx31 platforms. Here, you are talking about mx31pdk, right? Actually im talking TT-01, but it has no contributed NAND boot code (which I was working on), but it should hit mx31pdk in the same way. This should answer Albert's question about the board. The original startup code (start.S) was position independent to allow relocation in board_init_f. This is necessary as the internal RAM used by the IPL to load the first 2kB from NAND is also used by the NAND controller to buffer pages. As far as the issue goes: where and how exactly is the code not position independent now? The first statement is now: ldr pc, _reset _reset: .word reset reset is an address generated by the linker (here 0x87dc0060). Originally this was: b reset which is a relative branch (here 0x60 bytes forward). I have to add, that changing this back does not fix the issue, something else is in disorder. I'm still working on it. Do you mean reverting this commit, or only these two lines? In the former case, where does bisect lead to, and in the latter case, have you checked the assembler code in the linked SPL for this branch? I was bisecting the issue by hand :-! , always rebasing my developement branch to somewhere in the master tree and found commit 41623c91 that way, as stated in the first message of the thread. Reverting the commit fixes it, but it should only be a few offending lines. Does changing the startup code back to PIC generate any drawbacks on other ARM platforms? How would this changing back to PIC be implemented? Not by reverting the patch, I hope. No, it will only be a minor change, I think, but I thought there might have been an additional intention behind the change to position dependent code. One could link the first part to 0xB800 (the original position of the SPL when loaded by the IPL) and the part after the relocation to CONFIG_SPL_TEXT_BASE. Actually, the ROM bootloader first copies the first NAND page to 0xB800. Then, the SPL placed here but linked at CONFIG_SPL_TEXT_BASE copies itself to CONFIG_SPL_TEXT_BASE in order to free the NFC buffer so that it can be used by the SPL. There is no relocation going on at this stage, but only a copy, and the SPL code size is limited to 2 kiB. Then, the SPL does its NAND load job towards CONFIG_SYS_TEXT_BASE and starts executing the non-SPL binary, which then relocates itself according to the heap size, etc. Hence, as you said the code launching board_init_f() must be either PIC or linked at 0xB800, and the rest of the SPL code must be either PIC or linked at CONFIG_SPL_TEXT_BASE. So the fact that this commit breaks the PICness of the initial branch is indeed an issue. As a test, can you try to replace the 2 _reset lines in vectors.S with b _reset after _start:, and a _reset: label at the end of the file? This assumes that start.S starts with the reset: label, and that the start.o .text sections are placed right after the .vectors section in the SPL linker script, both being true for mx31pdk. I was using the word 'relocation' instead of copying. I did what you suggest, but this does not completely fix the issue. At a quick glance at the assembler code of board_init_f it looked PIC to me, but I'll have to check. I'm currently torn between projects, which is why I have no further input right now. Helmut -- Scanned by MailScanner. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] Fwd: Re: [PATCH 2/3] env_mmc: support env partition setup in runtime
Hi Pantelis, Tom,
Apparently, Dmitry has sent the message in html format...
Resending now...
Sorry for that...
Original Message
Subject:Re: [U-Boot] [PATCH 2/3] env_mmc: support env partition setup
in runtime
Date: Wed, 25 Jun 2014 10:42:11 +0300
From: Dmitry Lifshitz lifsh...@compulab.co.il
To: Pantelis Antoniou pantelis.anton...@gmail.com
CC: u-boot@lists.denx.de, Tom Rini tr...@ti.com, Igor Grinberg
grinb...@compulab.co.il
Hi Pantelis,
On 06/12/2014 06:10 PM, Pantelis Antoniou wrote:
Hi Dmitry,
I took a good look at the patch and there's a problem.
On Apr 27, 2014, at 1:18 PM, Dmitry Lifshitz wrote:
Add callback with __weak annotation to allow setup of environment
partition number in runtime from a board file.
Signed-off-by: Dmitry Lifshitz lifsh...@compulab.co.il
Signed-off-by: Igor Grinberg grinb...@compulab.co.il
---
common/env_mmc.c | 35 ++-
1 files changed, 26 insertions(+), 9 deletions(-)
diff --git a/common/env_mmc.c b/common/env_mmc.c
index 045428c..5d4b5f4 100644
--- a/common/env_mmc.c
+++ b/common/env_mmc.c
@@ -62,6 +62,30 @@ int env_init(void)
return 0;
}
+
+#ifdef CONFIG_SYS_MMC_ENV_PART
+__weak uint mmc_get_env_part(struct mmc *mmc)
+{
+return CONFIG_SYS_MMC_ENV_PART;
+}
+
+static int mmc_set_env_part(struct mmc *mmc)
+{
+uint part = mmc_get_env_part(mmc);
+
+if (part != mmc-part_num) {
+if (mmc_switch_part(CONFIG_SYS_MMC_ENV_DEV, part)) {
+puts(MMC partition switch failed\n);
+return -1;
+}
+}
+
+return 0;
+}
+#else
+static inline int mmc_set_env_part(struct mmc *mmc) {return 0; };
+#endif
+
static int init_mmc_for_env(struct mmc *mmc)
{
if (!mmc) {
@@ -74,15 +98,8 @@ static int init_mmc_for_env(struct mmc *mmc)
return -1;
}
Just before this hunk, we have this:
#ifdef CONFIG_SYS_MMC_ENV_PART
int dev = CONFIG_SYS_MMC_ENV_DEV;
#ifdef CONFIG_SPL_BUILD
dev = 0;
#endif
#endif
This appears to be broken for SPL in case that CONFIG_SYS_MMC_ENV_DEV is not
0.
Exactly as it was broken before the patch, right?
SPL hardcoded dev to 0, while mmc_switch_part is implicitly operating on
CONFIG_SYS_MMC_ENV_DEV.
Please rework it so that the SPL case is unaffected.
This patch does not change the behavior and its purpose
is not fixing the current code.
The bug describe can be fixed by later patch and possibly
will require additional review and testing.
Given that this patch does not change the behavior, can it be accepted please ?
Regards,
Dmitry
-#ifdef CONFIG_SYS_MMC_ENV_PART
-if (CONFIG_SYS_MMC_ENV_PART != mmc-part_num) {
-if (mmc_switch_part(CONFIG_SYS_MMC_ENV_DEV,
-CONFIG_SYS_MMC_ENV_PART)) {
-puts(MMC partition switch failed\n);
-return -1;
-}
-}
-#endif
+if (mmc_set_env_part(mmc))
+return -1;
return 0;
}
--
1.7.5.4
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[U-Boot] [PATCH 1/4] ARM: fix the ARCH Timer frequency setting.
For some SoCs, the CONFIG_SYS_CLK_FREQ maybe won't equal the ARCH Timer's frequency. Here using the CONFIG_TIMER_CLK_FREQ instead if the ARCH Timer's frequency need to config here. Signed-off-by: Xiubo Li li.xi...@freescale.com --- arch/arm/cpu/armv7/nonsec_virt.S | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/cpu/armv7/nonsec_virt.S b/arch/arm/cpu/armv7/nonsec_virt.S index 6f90988..e9766c0 100644 --- a/arch/arm/cpu/armv7/nonsec_virt.S +++ b/arch/arm/cpu/armv7/nonsec_virt.S @@ -147,11 +147,11 @@ ENTRY(_nonsec_init) * we do this here instead. * But first check if we have the generic timer. */ -#ifdef CONFIG_SYS_CLK_FREQ +#ifdef CONFIG_TIMER_CLK_FREQ mrc p15, 0, r0, c0, c1, 1 @ read ID_PFR1 and r0, r0, #CPUID_ARM_GENTIMER_MASK@ mask arch timer bits cmp r0, #(1 CPUID_ARM_GENTIMER_SHIFT) - ldreq r1, =CONFIG_SYS_CLK_FREQ + ldreq r1, =CONFIG_TIMER_CLK_FREQ mcreq p15, 0, r1, c14, c0, 0 @ write CNTFRQ #endif -- 1.8.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 2/4] ARM: add the pen address byte reverting support.
For some SoCs, the pen address may has different endianness with the CPUs, so this need the byte revertion for it, Signed-off-by: Xiubo Li li.xi...@freescale.com --- arch/arm/cpu/armv7/nonsec_virt.S | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/cpu/armv7/nonsec_virt.S b/arch/arm/cpu/armv7/nonsec_virt.S index e9766c0..c334a15 100644 --- a/arch/arm/cpu/armv7/nonsec_virt.S +++ b/arch/arm/cpu/armv7/nonsec_virt.S @@ -181,6 +181,9 @@ ENTRY(smp_waitloop) wfi ldr r1, =CONFIG_SMP_PEN_ADDR@ load start address ldr r1, [r1] +#ifdef CONFIG_SOC_BIG_ENDIAN + rev r1, r1 +#endif cmp r0, r1 @ make sure we dont execute this code beq smp_waitloop@ again (due to a spurious wakeup) mov pc, r1 -- 1.8.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 3/4] ARM: LS1021A: enable ARMv7 virt support for LS1021A A7
To enable hypervisors utilizing the ARMv7 virtualization extension
on the LS1021A-QDS/TWR boards with the A7 core tile, we add the
required configuration variable.
Also we define the board specific smp_set_cpu_boot_addr() function to
set the start address for secondary cores in the LS1021A specific
manner.
Signed-off-by: Xiubo Li li.xi...@freescale.com
---
arch/arm/cpu/armv7/ls102xa/cpu.c | 12
include/configs/ls1021aqds.h | 9 +
include/configs/ls1021atwr.h | 9 +
3 files changed, 30 insertions(+)
diff --git a/arch/arm/cpu/armv7/ls102xa/cpu.c b/arch/arm/cpu/armv7/ls102xa/cpu.c
index f9046c6..2268f15 100644
--- a/arch/arm/cpu/armv7/ls102xa/cpu.c
+++ b/arch/arm/cpu/armv7/ls102xa/cpu.c
@@ -101,3 +101,15 @@ int cpu_eth_init(bd_t *bis)
return 0;
}
+
+#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT)
+/* Setting the address at which secondary cores start from.*/
+void smp_set_core_boot_addr(unsigned long addr, int corenr)
+{
+ /* After setting the secondary cores start address, just release
+* them to boot.
+*/
+ out_be32(CONFIG_DCFG_CCSR_SCRATCHRW1, addr);
+ out_be32(CONFIG_DCFG_CCSR_BRR, 0x2);
+}
+#endif
diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h
index d639a6f..f090971 100644
--- a/include/configs/ls1021aqds.h
+++ b/include/configs/ls1021aqds.h
@@ -18,6 +18,15 @@
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_ARCH_EARLY_INIT_R
+#define CONFIG_ARMV7_NONSEC
+#define CONFIG_ARMV7_VIRT
+#define CONFIG_SOC_BIG_ENDIAN
+#define CONFIG_DCFG_CCSR_SCRATCHRW10x01ee0200
+#define CONFIG_DCFG_CCSR_BRR 0x01ee00e4
+#define CONFIG_SMP_PEN_ADDRCONFIG_DCFG_CCSR_SCRATCHRW1
+#define CONFIG_ARM_GIC_BASE_ADDRESS0x0140
+#define CONFIG_TIMER_CLK_FREQ 12500
+
#define CONFIG_HWCONFIG
#define HWCONFIG_BUFFER_SIZE 128
diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h
index a8dc56e..235a862 100644
--- a/include/configs/ls1021atwr.h
+++ b/include/configs/ls1021atwr.h
@@ -18,6 +18,15 @@
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_ARCH_EARLY_INIT_R
+#define CONFIG_ARMV7_NONSEC
+#define CONFIG_ARMV7_VIRT
+#define CONFIG_SOC_BIG_ENDIAN
+#define CONFIG_DCFG_CCSR_SCRATCHRW10x01ee0200
+#define CONFIG_DCFG_CCSR_BRR 0x01ee00e4
+#define CONFIG_SMP_PEN_ADDRCONFIG_DCFG_CCSR_SCRATCHRW1
+#define CONFIG_ARM_GIC_BASE_ADDRESS0x0140
+#define CONFIG_TIMER_CLK_FREQ 12500
+
#define CONFIG_HWCONFIG
#define HWCONFIG_BUFFER_SIZE 128
--
1.8.5
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[U-Boot] [PATCH 0/4] Add LS1021A-QDS/TWR Non-secure and HYP support.
This patch series depends on the following patch: [U-Boot,v4,03/10] ARM: non-sec: reset CNTVOFF to zero Before switching to non-secure, make sure that CNTVOFF is set to zero on all CPUs. Otherwise, kernel running in non-secure without HYP enabled (hence using virtual timers) may observe timers that are not synchronized, effectively seeing time going backward... Patch work: http://patchwork.ozlabs.org/patch/343084/ Xiubo Li (4): ARM: fix the ARCH Timer frequency setting. ARM: add the pen address byte reverting support. ARM: LS1021A: enable ARMv7 virt support for LS1021A A7 ARM: LS1021A: to allow non-secure R/W access for all devices' mapped region arch/arm/cpu/armv7/ls102xa/cpu.c | 12 +++ arch/arm/cpu/armv7/nonsec_virt.S | 7 +- arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 98 +-- board/freescale/ls1021aqds/ls1021aqds.c | 110 +++-- board/freescale/ls1021atwr/ls1021atwr.c | 111 -- include/configs/ls1021aqds.h | 9 ++ include/configs/ls1021atwr.h | 9 ++ 7 files changed, 333 insertions(+), 23 deletions(-) -- 1.8.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 4/4] ARM: LS1021A: to allow non-secure R/W access for all devices' mapped region
Signed-off-by: Xiubo Li li.xi...@freescale.com
---
arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 98 +--
board/freescale/ls1021aqds/ls1021aqds.c | 110 +++--
board/freescale/ls1021atwr/ls1021atwr.c | 111 --
3 files changed, 298 insertions(+), 21 deletions(-)
diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
index 192d389..b959bf5 100644
--- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
+++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
@@ -34,14 +34,98 @@
#define FSL_LS102xA_DEVDISR3_PCIE1 0x8000
#define FSL_LS102xA_DEVDISR3_PCIE2 0x4000
-/* CSU CSL2 register offset */
-#define CSU_CSL2_IFC_REG_OFFSET0x4
-/* Mask of Non secure read/write access in CSU_CL registers */
-#define CSU_CSL2x_NS_SUP_WRITE_ACCESS 0x0080
-#define CSU_CSL2x_NS_USER_WRITE_ACCESS 0x0040
-#define CSU_CSL2x_NS_SUP_READ_ACCESS 0x0008
-#define CSU_CSL2x_NS_USER_READ_ACCESS 0x0004
+enum csu_cslx_access {
+ CSU_NS_SUP_R = 0x08,
+ CSU_NS_SUP_W = 0x80,
+ CSU_NS_SUP_RW = 0x88,
+ CSU_NS_USER_R = 0x04,
+ CSU_NS_USER_W = 0x40,
+ CSU_NS_USER_RW = 0x44,
+};
+enum csu_cslx_ind {
+ CSU_CSLX_PCIE2_IO = 0,
+ CSU_CSLX_PCIE1_IO,
+ CSU_CSLX_MG2TPR_IP,
+ CSU_CSLX_IFC_MEM,
+ CSU_CSLX_OCRAM,
+ CSU_CSLX_GIC,
+ CSU_CSLX_PCIE1,
+ CSU_CSLX_OCRAM2,
+ CSU_CSLX_QSPI_MEM,
+ CSU_CSLX_PCIE2,
+ CSU_CSLX_SATA,
+ CSU_CSLX_USB3,
+ CSU_CSLX_SERDES = 32,
+ CSU_CSLX_QDMA,
+ CSU_CSLX_LPUART2,
+ CSU_CSLX_LPUART1,
+ CSU_CSLX_LPUART4,
+ CSU_CSLX_LPUART3,
+ CSU_CSLX_LPUART6,
+ CSU_CSLX_LPUART5,
+ CSU_CSLX_DSPI2 = 40,
+ CSU_CSLX_DSPI1,
+ CSU_CSLX_QSPI,
+ CSU_CSLX_ESDHC,
+ CSU_CSLX_2D_ACE,
+ CSU_CSLX_IFC,
+ CSU_CSLX_I2C1,
+ CSU_CSLX_USB2,
+ CSU_CSLX_I2C3,
+ CSU_CSLX_I2C2,
+ CSU_CSLX_DUART2 = 50,
+ CSU_CSLX_DUART1,
+ CSU_CSLX_WDT2,
+ CSU_CSLX_WDT1,
+ CSU_CSLX_EDMA,
+ CSU_CSLX_SYS_CNT,
+ CSU_CSLX_DMA_MUX2,
+ CSU_CSLX_DMA_MUX1,
+ CSU_CSLX_DDR,
+ CSU_CSLX_QUICC,
+ CSU_CSLX_DCFG_CCU_RCPM = 60,
+ CSU_CSLX_SECURE_BOOTROM,
+ CSU_CSLX_SFP,
+ CSU_CSLX_TMU,
+ CSU_CSLX_SECURE_MONITOR,
+ CSU_CSLX_RESERVED0,
+ CSU_CSLX_ETSEC1,
+ CSU_CSLX_SEC5_5,
+ CSU_CSLX_ETSEC3,
+ CSU_CSLX_ETSEC2,
+ CSU_CSLX_GPIO2 = 70,
+ CSU_CSLX_GPIO1,
+ CSU_CSLX_GPIO4,
+ CSU_CSLX_GPIO3,
+ CSU_CSLX_PLATFORM_CONT,
+ CSU_CSLX_CSU,
+ CSU_CSLX_ASRC,
+ CSU_CSLX_SPDIF,
+ CSU_CSLX_FLEXCAN2,
+ CSU_CSLX_FLEXCAN1,
+ CSU_CSLX_FLEXCAN4 = 80,
+ CSU_CSLX_FLEXCAN3,
+ CSU_CSLX_SAI2,
+ CSU_CSLX_SAI1,
+ CSU_CSLX_SAI4,
+ CSU_CSLX_SAI3,
+ CSU_CSLX_FTM2,
+ CSU_CSLX_FTM1,
+ CSU_CSLX_FTM4,
+ CSU_CSLX_FTM3,
+ CSU_CSLX_FTM6 = 90,
+ CSU_CSLX_FTM5,
+ CSU_CSLX_FTM8,
+ CSU_CSLX_FTM7,
+ CSU_CSLX_COP_DCSR,
+ CSU_CSLX_EPU,
+ CSU_CSLX_GDI,
+ CSU_CSLX_DDI,
+ CSU_CSLX_RESERVED1,
+ CSU_CSLX_USB3_PHY = 117,
+ CSU_CSLX_RESERVED2,
+};
/*
* Define default values for some CCSR macros to make header files cleaner*
*
diff --git a/board/freescale/ls1021aqds/ls1021aqds.c
b/board/freescale/ls1021aqds/ls1021aqds.c
index fe00421..7444e06 100644
--- a/board/freescale/ls1021aqds/ls1021aqds.c
+++ b/board/freescale/ls1021aqds/ls1021aqds.c
@@ -377,15 +377,111 @@ int board_init(void)
return 0;
}
+struct csu_ns_dev {
+ unsigned long ind;
+ uint32_t val;
+};
-void enable_ifc_ns_read_access(void)
+struct csu_ns_dev ns_dev[] =
{
- uint32_t *csu_csl2 = CONFIG_SYS_FSL_CSU_ADDR + CSU_CSL2_IFC_REG_OFFSET;
- uint32_t reg;
+ CSU_CSLX_PCIE2_IO, CSU_NS_SUP_RW,
+ CSU_CSLX_PCIE1_IO, CSU_NS_SUP_RW,
+ CSU_CSLX_MG2TPR_IP, CSU_NS_SUP_RW,
+ CSU_CSLX_IFC_MEM, CSU_NS_SUP_R | CSU_NS_USER_R,
+ CSU_CSLX_OCRAM, CSU_NS_SUP_RW,
+ CSU_CSLX_GIC, CSU_NS_SUP_RW,
+ CSU_CSLX_PCIE1, CSU_NS_SUP_RW,
+ CSU_CSLX_OCRAM2, CSU_NS_SUP_RW,
+ CSU_CSLX_QSPI_MEM, CSU_NS_SUP_RW,
+ CSU_CSLX_PCIE2, CSU_NS_SUP_RW,
+ CSU_CSLX_SATA, CSU_NS_SUP_RW,
+ CSU_CSLX_USB3, CSU_NS_SUP_RW,
+ CSU_CSLX_SERDES, CSU_NS_SUP_RW,
+ CSU_CSLX_QDMA, CSU_NS_SUP_RW,
+ CSU_CSLX_LPUART2, CSU_NS_SUP_RW,
+ CSU_CSLX_LPUART1, CSU_NS_SUP_RW,
+ CSU_CSLX_LPUART4, CSU_NS_SUP_RW,
+ CSU_CSLX_LPUART3, CSU_NS_SUP_RW,
+ CSU_CSLX_LPUART6, CSU_NS_SUP_RW,
+ CSU_CSLX_LPUART5, CSU_NS_SUP_RW,
+ CSU_CSLX_DSPI2, CSU_NS_SUP_RW,
+ CSU_CSLX_DSPI1, CSU_NS_SUP_RW,
+ CSU_CSLX_QSPI, CSU_NS_SUP_RW,
+ CSU_CSLX_ESDHC, CSU_NS_SUP_RW,
+ CSU_CSLX_2D_ACE,
Re: [U-Boot] [PATCH] ARM: tegra: Use mem size from MC rather than ODMDATA
On Thu, Jul 03, 2014 at 09:45:52AM +0200, Wolfgang Denk wrote: Dear Stephen, In message 53b47f6f.1090...@wwwdotorg.org you wrote: Is there a specific reason for not using get_ram_size()? Since we know the exact RAM size, we may as well simply use it directly rather than probing for it. You _think_ you know the size, but you can never be sure that all this RAM is actually present and working. There has been many discussions before why using get_ram_size() makes a lot of sense even in fixed size RAM configurations. Right which is why the flow in this case is: 1) Read the place that knows 2) Pass that size to get_ram_size(), use returned value as what we really know the size to be. -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 0/4] Add LS1021A-QDS/TWR Non-secure and HYP support.
On 07/03/2014 12:51 PM, Xiubo Li wrote: This patch series depends on the following patch: [U-Boot,v4,03/10] ARM: non-sec: reset CNTVOFF to zero Before switching to non-secure, make sure that CNTVOFF is set to zero on all CPUs. Otherwise, kernel running in non-secure without HYP enabled (hence using virtual timers) may observe But we have HYP enabled. In this case why are the series dependent on this patch? timers that are not synchronized, effectively seeing time going backward... Patch work: http://patchwork.ozlabs.org/patch/343084/ Xiubo Li (4): ARM: fix the ARCH Timer frequency setting. ARM: add the pen address byte reverting support. ARM: LS1021A: enable ARMv7 virt support for LS1021A A7 ARM: LS1021A: to allow non-secure R/W access for all devices' mapped region arch/arm/cpu/armv7/ls102xa/cpu.c | 12 +++ arch/arm/cpu/armv7/nonsec_virt.S | 7 +- arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 98 +-- board/freescale/ls1021aqds/ls1021aqds.c | 110 +++-- board/freescale/ls1021atwr/ls1021atwr.c | 111 -- include/configs/ls1021aqds.h | 9 ++ include/configs/ls1021atwr.h | 9 ++ 7 files changed, 333 insertions(+), 23 deletions(-) Diana ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/4] ARM: fix the ARCH Timer frequency setting.
On 07/03/2014 12:51 PM, Xiubo Li wrote: For some SoCs, the CONFIG_SYS_CLK_FREQ maybe won't equal the ARCH Timer's frequency. Can you give an example? Here using the CONFIG_TIMER_CLK_FREQ instead if the ARCH Timer's frequency need to config here. Signed-off-by: Xiubo Li li.xi...@freescale.com --- arch/arm/cpu/armv7/nonsec_virt.S | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/cpu/armv7/nonsec_virt.S b/arch/arm/cpu/armv7/nonsec_virt.S index 6f90988..e9766c0 100644 --- a/arch/arm/cpu/armv7/nonsec_virt.S +++ b/arch/arm/cpu/armv7/nonsec_virt.S @@ -147,11 +147,11 @@ ENTRY(_nonsec_init) * we do this here instead. * But first check if we have the generic timer. */ -#ifdef CONFIG_SYS_CLK_FREQ +#ifdef CONFIG_TIMER_CLK_FREQ Aren't you breaking the boards which rely on CONFIG_SYS_CLK_FREQ ? mrc p15, 0, r0, c0, c1, 1 @ read ID_PFR1 and r0, r0, #CPUID_ARM_GENTIMER_MASK@ mask arch timer bits cmp r0, #(1 CPUID_ARM_GENTIMER_SHIFT) - ldreq r1, =CONFIG_SYS_CLK_FREQ + ldreq r1, =CONFIG_TIMER_CLK_FREQ mcreq p15, 0, r1, c14, c0, 0 @ write CNTFRQ #endif Diana ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 3/4] ARM: LS1021A: enable ARMv7 virt support for LS1021A A7
On 07/03/2014 12:51 PM, Xiubo Li wrote:
To enable hypervisors utilizing the ARMv7 virtualization extension
on the LS1021A-QDS/TWR boards with the A7 core tile, we add the
required configuration variable.
Also we define the board specific smp_set_cpu_boot_addr() function to
set the start address for secondary cores in the LS1021A specific
manner.
Signed-off-by: Xiubo Li li.xi...@freescale.com
---
arch/arm/cpu/armv7/ls102xa/cpu.c | 12
include/configs/ls1021aqds.h | 9 +
include/configs/ls1021atwr.h | 9 +
3 files changed, 30 insertions(+)
diff --git a/arch/arm/cpu/armv7/ls102xa/cpu.c b/arch/arm/cpu/armv7/ls102xa/cpu.c
index f9046c6..2268f15 100644
--- a/arch/arm/cpu/armv7/ls102xa/cpu.c
+++ b/arch/arm/cpu/armv7/ls102xa/cpu.c
@@ -101,3 +101,15 @@ int cpu_eth_init(bd_t *bis)
return 0;
}
+
+#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT)
+/* Setting the address at which secondary cores start from.*/
+void smp_set_core_boot_addr(unsigned long addr, int corenr)
+{
+ /* After setting the secondary cores start address, just release
+* them to boot.
+*/
+ out_be32(CONFIG_DCFG_CCSR_SCRATCHRW1, addr);
+ out_be32(CONFIG_DCFG_CCSR_BRR, 0x2);
+}
+#endif
diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h
index d639a6f..f090971 100644
--- a/include/configs/ls1021aqds.h
+++ b/include/configs/ls1021aqds.h
@@ -18,6 +18,15 @@
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_ARCH_EARLY_INIT_R
+#define CONFIG_ARMV7_NONSEC
+#define CONFIG_ARMV7_VIRT
+#define CONFIG_SOC_BIG_ENDIAN
+#define CONFIG_DCFG_CCSR_SCRATCHRW10x01ee0200
+#define CONFIG_DCFG_CCSR_BRR 0x01ee00e4
Why are you hardcoding the register addresses in this file? I saw that
all registers are defined in:
arch/arm/include/asm/arch-ls102xa/config.h. Why are these special?
+#define CONFIG_SMP_PEN_ADDRCONFIG_DCFG_CCSR_SCRATCHRW1
+#define CONFIG_ARM_GIC_BASE_ADDRESS0x0140
Why do you need the GIC base address? Can't this be read from CBAR?
+#define CONFIG_TIMER_CLK_FREQ 12500
+
#define CONFIG_HWCONFIG
#define HWCONFIG_BUFFER_SIZE 128
diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h
index a8dc56e..235a862 100644
--- a/include/configs/ls1021atwr.h
+++ b/include/configs/ls1021atwr.h
@@ -18,6 +18,15 @@
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_ARCH_EARLY_INIT_R
+#define CONFIG_ARMV7_NONSEC
+#define CONFIG_ARMV7_VIRT
+#define CONFIG_SOC_BIG_ENDIAN
+#define CONFIG_DCFG_CCSR_SCRATCHRW10x01ee0200
+#define CONFIG_DCFG_CCSR_BRR 0x01ee00e4
+#define CONFIG_SMP_PEN_ADDRCONFIG_DCFG_CCSR_SCRATCHRW1
+#define CONFIG_ARM_GIC_BASE_ADDRESS0x0140
+#define CONFIG_TIMER_CLK_FREQ 12500
+
#define CONFIG_HWCONFIG
#define HWCONFIG_BUFFER_SIZE 128
___
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Re: [U-Boot] [PATCH 4/4] ARM: LS1021A: to allow non-secure R/W access for all devices' mapped region
On 07/03/2014 12:51 PM, Xiubo Li wrote:
Signed-off-by: Xiubo Li li.xi...@freescale.com
---
arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 98 +--
board/freescale/ls1021aqds/ls1021aqds.c | 110 +++--
board/freescale/ls1021atwr/ls1021atwr.c | 111 --
3 files changed, 298 insertions(+), 21 deletions(-)
diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
index 192d389..b959bf5 100644
--- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
+++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
@@ -34,14 +34,98 @@
#define FSL_LS102xA_DEVDISR3_PCIE1 0x8000
#define FSL_LS102xA_DEVDISR3_PCIE2 0x4000
-/* CSU CSL2 register offset */
-#define CSU_CSL2_IFC_REG_OFFSET0x4
-/* Mask of Non secure read/write access in CSU_CL registers */
-#define CSU_CSL2x_NS_SUP_WRITE_ACCESS 0x0080
-#define CSU_CSL2x_NS_USER_WRITE_ACCESS 0x0040
-#define CSU_CSL2x_NS_SUP_READ_ACCESS 0x0008
-#define CSU_CSL2x_NS_USER_READ_ACCESS 0x0004
+enum csu_cslx_access {
+ CSU_NS_SUP_R = 0x08,
+ CSU_NS_SUP_W = 0x80,
+ CSU_NS_SUP_RW = 0x88,
+ CSU_NS_USER_R = 0x04,
+ CSU_NS_USER_W = 0x40,
+ CSU_NS_USER_RW = 0x44,
+};
+enum csu_cslx_ind {
+ CSU_CSLX_PCIE2_IO = 0,
+ CSU_CSLX_PCIE1_IO,
+ CSU_CSLX_MG2TPR_IP,
+ CSU_CSLX_IFC_MEM,
+ CSU_CSLX_OCRAM,
+ CSU_CSLX_GIC,
+ CSU_CSLX_PCIE1,
+ CSU_CSLX_OCRAM2,
+ CSU_CSLX_QSPI_MEM,
+ CSU_CSLX_PCIE2,
+ CSU_CSLX_SATA,
+ CSU_CSLX_USB3,
+ CSU_CSLX_SERDES = 32,
+ CSU_CSLX_QDMA,
+ CSU_CSLX_LPUART2,
+ CSU_CSLX_LPUART1,
+ CSU_CSLX_LPUART4,
+ CSU_CSLX_LPUART3,
+ CSU_CSLX_LPUART6,
+ CSU_CSLX_LPUART5,
+ CSU_CSLX_DSPI2 = 40,
+ CSU_CSLX_DSPI1,
+ CSU_CSLX_QSPI,
+ CSU_CSLX_ESDHC,
+ CSU_CSLX_2D_ACE,
+ CSU_CSLX_IFC,
+ CSU_CSLX_I2C1,
+ CSU_CSLX_USB2,
+ CSU_CSLX_I2C3,
+ CSU_CSLX_I2C2,
+ CSU_CSLX_DUART2 = 50,
+ CSU_CSLX_DUART1,
+ CSU_CSLX_WDT2,
+ CSU_CSLX_WDT1,
+ CSU_CSLX_EDMA,
+ CSU_CSLX_SYS_CNT,
+ CSU_CSLX_DMA_MUX2,
+ CSU_CSLX_DMA_MUX1,
+ CSU_CSLX_DDR,
+ CSU_CSLX_QUICC,
+ CSU_CSLX_DCFG_CCU_RCPM = 60,
+ CSU_CSLX_SECURE_BOOTROM,
+ CSU_CSLX_SFP,
+ CSU_CSLX_TMU,
+ CSU_CSLX_SECURE_MONITOR,
+ CSU_CSLX_RESERVED0,
+ CSU_CSLX_ETSEC1,
+ CSU_CSLX_SEC5_5,
+ CSU_CSLX_ETSEC3,
+ CSU_CSLX_ETSEC2,
+ CSU_CSLX_GPIO2 = 70,
+ CSU_CSLX_GPIO1,
+ CSU_CSLX_GPIO4,
+ CSU_CSLX_GPIO3,
+ CSU_CSLX_PLATFORM_CONT,
+ CSU_CSLX_CSU,
+ CSU_CSLX_ASRC,
+ CSU_CSLX_SPDIF,
+ CSU_CSLX_FLEXCAN2,
+ CSU_CSLX_FLEXCAN1,
+ CSU_CSLX_FLEXCAN4 = 80,
+ CSU_CSLX_FLEXCAN3,
+ CSU_CSLX_SAI2,
+ CSU_CSLX_SAI1,
+ CSU_CSLX_SAI4,
+ CSU_CSLX_SAI3,
+ CSU_CSLX_FTM2,
+ CSU_CSLX_FTM1,
+ CSU_CSLX_FTM4,
+ CSU_CSLX_FTM3,
+ CSU_CSLX_FTM6 = 90,
+ CSU_CSLX_FTM5,
+ CSU_CSLX_FTM8,
+ CSU_CSLX_FTM7,
+ CSU_CSLX_COP_DCSR,
+ CSU_CSLX_EPU,
+ CSU_CSLX_GDI,
+ CSU_CSLX_DDI,
+ CSU_CSLX_RESERVED1,
+ CSU_CSLX_USB3_PHY = 117,
+ CSU_CSLX_RESERVED2,
+};
/*
* Define default values for some CCSR macros to make header files cleaner*
*
diff --git a/board/freescale/ls1021aqds/ls1021aqds.c
b/board/freescale/ls1021aqds/ls1021aqds.c
index fe00421..7444e06 100644
--- a/board/freescale/ls1021aqds/ls1021aqds.c
+++ b/board/freescale/ls1021aqds/ls1021aqds.c
@@ -377,15 +377,111 @@ int board_init(void)
return 0;
}
+struct csu_ns_dev {
+ unsigned long ind;
+ uint32_t val;
+};
-void enable_ifc_ns_read_access(void)
+struct csu_ns_dev ns_dev[] =
{
- uint32_t *csu_csl2 = CONFIG_SYS_FSL_CSU_ADDR + CSU_CSL2_IFC_REG_OFFSET;
- uint32_t reg;
+ CSU_CSLX_PCIE2_IO, CSU_NS_SUP_RW,
+ CSU_CSLX_PCIE1_IO, CSU_NS_SUP_RW,
+ CSU_CSLX_MG2TPR_IP, CSU_NS_SUP_RW,
+ CSU_CSLX_IFC_MEM, CSU_NS_SUP_R | CSU_NS_USER_R,
+ CSU_CSLX_OCRAM, CSU_NS_SUP_RW,
+ CSU_CSLX_GIC, CSU_NS_SUP_RW,
+ CSU_CSLX_PCIE1, CSU_NS_SUP_RW,
+ CSU_CSLX_OCRAM2, CSU_NS_SUP_RW,
+ CSU_CSLX_QSPI_MEM, CSU_NS_SUP_RW,
+ CSU_CSLX_PCIE2, CSU_NS_SUP_RW,
+ CSU_CSLX_SATA, CSU_NS_SUP_RW,
+ CSU_CSLX_USB3, CSU_NS_SUP_RW,
+ CSU_CSLX_SERDES, CSU_NS_SUP_RW,
+ CSU_CSLX_QDMA, CSU_NS_SUP_RW,
+ CSU_CSLX_LPUART2, CSU_NS_SUP_RW,
+ CSU_CSLX_LPUART1, CSU_NS_SUP_RW,
+ CSU_CSLX_LPUART4, CSU_NS_SUP_RW,
+ CSU_CSLX_LPUART3, CSU_NS_SUP_RW,
+ CSU_CSLX_LPUART6, CSU_NS_SUP_RW,
+ CSU_CSLX_LPUART5, CSU_NS_SUP_RW,
+ CSU_CSLX_DSPI2, CSU_NS_SUP_RW,
+ CSU_CSLX_DSPI1, CSU_NS_SUP_RW,
+ CSU_CSLX_QSPI, CSU_NS_SUP_RW,
+
Re: [U-Boot] [PATCH v2 0/9] arm: ls102xa: Add Freescale LS102xA SoC and LS1021AQDS/TWR board support
Hi Alison, On Thu, 3 Jul 2014 15:24:14 +0800, Alison Wang b18...@freescale.com wrote: This series contain the support for Freescale LS102xA SoC and LS1021AQDS/TWR board. The numbering in the cover letter (0/9) does not match that in the individual patches (n/10). Is this normal? Amicalement, -- Albert. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] SPL broken on i.mx31 platforms
Hi Helmut, On Thu, 03 Jul 2014 10:19:39 +0200, Helmut Raiger helmut.rai...@hale.at wrote: Hi, On 07/03/2014 01:20 AM, Benoît Thébaudeau wrote: )Dear Helmut Raiger, On Wed, Jul 2, 2014 at 9:04 AM, Helmut Raiger helmut.rai...@hale.at wrote: the commit 41623c91 breaks the SPL on i.mx31 platforms. Here, you are talking about mx31pdk, right? Actually im talking TT-01, but it has no contributed NAND boot code (which I was working on), but it should hit mx31pdk in the same way. This should answer Albert's question about the board. It does, thanks -- but I fail to see any SPL code built for TT-01. You're getting SPL issues with another target, right? No, it will only be a minor change, I think, but I thought there might have been an additional intention behind the change to position dependent code. One could link the first part to 0xB800 (the original position of the SPL when loaded by the IPL) and the part after the relocation to CONFIG_SPL_TEXT_BASE. Actually, the ROM bootloader first copies the first NAND page to 0xB800. Then, the SPL placed here but linked at CONFIG_SPL_TEXT_BASE copies itself to CONFIG_SPL_TEXT_BASE in order to free the NFC buffer so that it can be used by the SPL. There is no relocation going on at this stage, but only a copy, and the SPL code size is limited to 2 kiB. Then, the SPL does its NAND load job towards CONFIG_SYS_TEXT_BASE and starts executing the non-SPL binary, which then relocates itself according to the heap size, etc. Ok, I think I'm getting it, but actually you don't need PIC (your code won't run at arbitrary locations), you need VMAs vs LMAs (your code will run partly at one location, partly at another, but will be loaded at only one of these locations). Therefore, we should be able to manage this in the linker script, by basically defining two output sections: the first one with a VMA and LMA equal to 0xB800 both, and which would contain the 'copier' code; and the second one with a VMA equal to CONFIG_SPL_TEXT_BASE (so that it links properly for running at that address) and a LMA equal to 0xB80 (so that it gets lumped with the first section in the less-than-2K ELF file produced by the linker. (actually we'd have several output sections with VMA==LMA, but it does not affect the core of the idea.) Does it make sense to you? Helmut Amicalement, -- Albert. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 0/9] arm: ls102xa: Add Freescale LS102xA SoC and LS1021AQDS/TWR board support
Hi, Albert, On Thu, 3 Jul 2014 15:24:14 +0800, Alison Wang wrote: This series contain the support for Freescale LS102xA SoC and LS1021AQDS/TWR board. The numbering in the cover letter (0/9) does not match that in the individual patches (n/10). Is this normal? Sorry, it's my mistake. It should be 0/10 in the cover letter, not 0/9. Best Regards, Alison Wang -- View this message in context: http://u-boot.10912.n7.nabble.com/PATCH-v2-0-9-arm-ls102xa-Add-Freescale-LS102xA-SoC-and-LS1021AQDS-TWR-board-support-tp183468p183492.html Sent from the U-Boot mailing list archive at Nabble.com. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Requesting a custodian tree for sunxi (Allwinner) maintenance
Hi Ian, Hans and I would like to propose the creation of a uboot-sunxi.git custodian tree for things relating to the Allwinner platforms. It would be a downstream of uboot-arm.git tree with responsibility for it shared between us. This was previously mentioned on list[0] but we figured it deserved it's own thread. I have attached the public half of a fresh ssh key generated for this purpose. Hans, you should follow up with yours. A fresh repo has been setup with this key[1]. Let me know if you have any problems. Best wishes Detlev [1] http://git.denx.de/?p=u-boot/u-boot-sunxi.git;a=summary -- Those who do not understand Unix are condemned to reinvent it, poorly. - Henry Spencer, University of Toronto Unix hack -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-40 Fax: (+49)-8142-66989-80 Email: d...@denx.de ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-boot] [Patch 3/3] k2hk_evm: add script to automate NAND flash process
On 07/02/2014 04:36 PM, Ivan Khoronzhuk wrote: Add script to automate NAND flash process. As for now the board has two burn scripts - burn to boot from SPI NOR flash and burn to boot from AEMIF NAND flash, rename burn_uboot script to burn_uboot_spi. Also update README to contain NAND burn U-boot process description. Signed-off-by: Ivan Khoronzhukivan.khoronz...@ti.com --- board/ti/k2hk_evm/README | 27 ++- include/configs/k2hk_evm.h | 4 +++- 2 files changed, 29 insertions(+), 2 deletions(-) diff --git a/board/ti/k2hk_evm/README b/board/ti/k2hk_evm/README index bfeb05b..1da721c 100644 --- a/board/ti/k2hk_evm/README +++ b/board/ti/k2hk_evm/README @@ -43,6 +43,7 @@ Supported image formats:- - u-boot.bin: for loading and running u-boot.bin through Texas instruments code composure studio (CCS) - u-boot-spi.gph: gpimage for programming SPI NOR flash for SPI NOR boot + - u-boot-nand.gph: gpimage for programming AEMIF NAND flash for NAND boot Please also update the supported boot modes to include NAND boot under the section Supported boot modes: Build instructions: === @@ -55,6 +56,10 @@ To build u-boot-spi.gph make k2hk_evm_config make u-boot-spi.gph +To build u-boot-nand.gph +make k2hk_evm_config +make u-boot-nand.gph + Murali ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-boot] [Patch 3/3] k2hk_evm: add script to automate NAND flash process
On 07/03/2014 06:11 PM, Murali Karicheri wrote: On 07/02/2014 04:36 PM, Ivan Khoronzhuk wrote: Add script to automate NAND flash process. As for now the board has two burn scripts - burn to boot from SPI NOR flash and burn to boot from AEMIF NAND flash, rename burn_uboot script to burn_uboot_spi. Also update README to contain NAND burn U-boot process description. Signed-off-by: Ivan Khoronzhukivan.khoronz...@ti.com --- board/ti/k2hk_evm/README | 27 ++- include/configs/k2hk_evm.h | 4 +++- 2 files changed, 29 insertions(+), 2 deletions(-) diff --git a/board/ti/k2hk_evm/README b/board/ti/k2hk_evm/README index bfeb05b..1da721c 100644 --- a/board/ti/k2hk_evm/README +++ b/board/ti/k2hk_evm/README @@ -43,6 +43,7 @@ Supported image formats:- - u-boot.bin: for loading and running u-boot.bin through Texas instruments code composure studio (CCS) - u-boot-spi.gph: gpimage for programming SPI NOR flash for SPI NOR boot + - u-boot-nand.gph: gpimage for programming AEMIF NAND flash for NAND boot Please also update the supported boot modes to include NAND boot under the section Supported boot modes: I'll add Thanks. Build instructions: === @@ -55,6 +56,10 @@ To build u-boot-spi.gph make k2hk_evm_config make u-boot-spi.gph +To build u-boot-nand.gph +make k2hk_evm_config +make u-boot-nand.gph + Murali -- Regards, Ivan Khoronzhuk ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3 13/13] fit: make sha256 support optional
Hi, On 3 July 2014 00:03, Heiko Schocher h...@denx.de wrote: Hello Dirk, Am 03.07.2014 08:27, schrieb dirk.eib...@gdsys.cc: From: Dirk Eibachdirk.eib...@gdsys.cc sha256 has some beefy memory footprint. Make it optional for constrained systems. Signed-off-by: Dirk Eibachdirk.eib...@gdsys.cc --- Changes in v3: None Changes in v2: - make sha256 support optional include/configs/dlvision-10g.h | 1 + include/configs/io.h | 1 + include/configs/iocon.h| 1 + include/configs/neo.h | 1 + include/image.h| 5 + 5 files changed, 9 insertions(+) Sorry, some nitpick. As you introduce here the new define CONFIG_FIT_DISABLE_SHA256, can you please add a short description in the README, thanks! I wonder if it would be better to make the option off by default? You could perhaps use the existing CONFIG_SHA256 option, and check in image.h to enable/disable support. Heiko what do you think? Regards. Simon ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-boot] Does u-boot.bin only include a data section?
Hi, On 22 June 2014 20:31, tiger...@via-alliance.com wrote: Hi, experts: I am studying u-boo.bin format(which is got from u-boot, an ELF format bin). I run the below command: Objdump -h -b binary -m arm u-boot.bin Found only a .data section was displayed. So , does u-boot.bin include only a .data section? u-boot.bin does not really include sections - it is just a binary file, not ELF format. It includes data from the .text, .data. and .rodata sections among others. You are telling objdump that it is an ARM binary file and asking it to print a list of sections. I suspect it creates a .data section just for fun - there aren't really any sections in the file. Of course if you examine the file you will see the contents of .text, .data, .rodata etc. from the original ELF format file, but the header information that distinguishes them is not present in u-boot.bin. Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] U-Boot: Enhancement request to get flash device specific information
Hi, On 2 July 2014 10:05, HEERA NAND BHAGTANI diamond@gmail.com wrote: Hi U-boot team, I am looking for u-boot command which can give me flash device specific properties. For example, there should be dedicated commands to get the flash memory size, sector size, page size etc. Currently I found there is command sf probe for spi flash device which is returning device properties into text format as below: SF : Detected N25Q128A with page size 256 Bytes, erase size 64 KiB, total 16 MiB Similarly I found there is command nand info for nand device which is also returning device properties into text format. These commands (sf probe and nand info) are giving device information in form of message. Which does not meet my requirement. Actually I would like to integrate u-boot with my tool, where tool will run u-boot command to get the device information. Based on device information tool will react. Here I am looking for some dedicated command which return these property separately. It is difficult to parse the message string to get individual Let say we includes following commands: nand info pagesize/sectorsize/size/device sf info pagesize/sectorsize/size/device for example: nand info pagesize command should return page size ( e.g. *256*) nand info sectorsize command should return sector size (e.g. *65536* which is 64K) nand info size command should return the total size (e.g. *268435456 *which is 16 MB) Could you please consider this enhancement request in u-boot? Please comment. What kind of tool? Is it a U-Boot script? How does it get access to the output from U-Boot? You could use a regular expression to extract the information you need. For the commands you suggest, it might be better to put the values in an environment variable. Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v5 1/4] mx6: Add support for the mx6solox variant
Hi Stefano, On Thu, Jul 3, 2014 at 4:15 AM, Stefano Babic sba...@denx.de wrote: I have only taken a short look because the series should flow after 2014.07. Anyway, I could push them into -next. Pushing them into -next would be very helpful, so that we can continue on adding new support for mx6solox. Thanks, Fabio Estevam ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3 13/13] fit: make sha256 support optional
On Thu, Jul 03, 2014 at 09:14:01AM -0700, Simon Glass wrote: Hi, On 3 July 2014 00:03, Heiko Schocher h...@denx.de wrote: Hello Dirk, Am 03.07.2014 08:27, schrieb dirk.eib...@gdsys.cc: From: Dirk Eibachdirk.eib...@gdsys.cc sha256 has some beefy memory footprint. Make it optional for constrained systems. Signed-off-by: Dirk Eibachdirk.eib...@gdsys.cc --- Changes in v3: None Changes in v2: - make sha256 support optional include/configs/dlvision-10g.h | 1 + include/configs/io.h | 1 + include/configs/iocon.h| 1 + include/configs/neo.h | 1 + include/image.h| 5 + 5 files changed, 9 insertions(+) Sorry, some nitpick. As you introduce here the new define CONFIG_FIT_DISABLE_SHA256, can you please add a short description in the README, thanks! I wonder if it would be better to make the option off by default? You could perhaps use the existing CONFIG_SHA256 option, and check in image.h to enable/disable support. Heiko what do you think? I think I like this unless there's a problem... -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v1 01/25] sf: Add M25PX64 SPI NOR flash ID
Reviewed-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
On Fri, Jun 27, 2014 at 3:24 PM, Stefan Roese s...@denx.de wrote:
Add ID for this Numonix / STMicro chip.
Tested on Marvell DB-78460-BP board.
Signed-off-by: Stefan Roese s...@denx.de
Cc: Jagannadha Sutradharudu Teki jaga...@xilinx.com
---
drivers/mtd/spi/sf_params.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/mtd/spi/sf_params.c b/drivers/mtd/spi/sf_params.c
index ac886fd..b8186e9 100644
--- a/drivers/mtd/spi/sf_params.c
+++ b/drivers/mtd/spi/sf_params.c
@@ -71,6 +71,7 @@ const struct spi_flash_params spi_flash_params_table[] = {
{M25P32, 0x202016, 0x0, 64 * 1024,64, 0,
0},
{M25P64, 0x202017, 0x0, 64 * 1024, 128, 0,
0},
{M25P128,0x202018, 0x0, 256 * 1024,64, 0,
0},
+ {M25PX64,0x207117, 0x0, 64 * 1024, 128, 0,
SECT_4K},
{N25Q32, 0x20ba16, 0x0, 64 * 1024,64, RD_FULL,
WR_QPP | SECT_4K},
{N25Q32A,0x20bb16, 0x0, 64 * 1024,64, RD_FULL,
WR_QPP | SECT_4K},
{N25Q64, 0x20ba17, 0x0, 64 * 1024, 128, RD_FULL,
WR_QPP | SECT_4K},
--
2.0.1
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Re: [U-Boot] [PATCH v1 04/25] spi: kirkwood_spi.c: Make global variable static
May possible to include in different patch. Reviewed-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com On Fri, Jun 27, 2014 at 3:24 PM, Stefan Roese s...@denx.de wrote: Signed-off-by: Stefan Roese s...@denx.de Cc: Jagannadha Sutradharudu Teki jaga...@xilinx.com --- drivers/spi/kirkwood_spi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/spi/kirkwood_spi.c b/drivers/spi/kirkwood_spi.c index 449e9f8..7d1c1f9 100644 --- a/drivers/spi/kirkwood_spi.c +++ b/drivers/spi/kirkwood_spi.c @@ -18,7 +18,7 @@ static struct kwspi_registers *spireg = (struct kwspi_registers *)KW_SPI_BASE; -u32 cs_spi_mpp_back[2]; +static u32 cs_spi_mpp_back[2]; struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, unsigned int max_hz, unsigned int mode) -- 2.0.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot -- Jagan. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v1 03/25] spi: kirkwood_spi.c: Some fixes and cleanup
Reviewed-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
On Fri, Jun 27, 2014 at 3:24 PM, Stefan Roese s...@denx.de wrote:
This patch introduces the clrsetbits_le32() accessor functions in the
kirkwood SPI driver. Note that it also includes a fix:
-writel(~KWSPI_CSN_ACT | KWSPI_SMEMRDY, spireg-ctrl);
+writel(KWSPI_SMEMRDY, spireg-ctrl);
Here the bit KWSPI_CSN_ACT (0x1) should have been cleared. Instead
0xfffe is written into this control register. This is the main
reason to use the clrsetbits() functions now. As they make clearing
bits much less error prone.
Additionally KWSPI_IRQUNMASK is not used in spi_cs_activate() and
spi_cs_deactivate() any more. Its the wrong macro but has the same
value as the correct one (KWSPI_CSN_ACT).
This is in preparation for use of this driver on the Marvell Armada XP
platform as well.
Signed-off-by: Stefan Roese s...@denx.de
Cc: Jagannadha Sutradharudu Teki jaga...@xilinx.com
---
drivers/spi/kirkwood_spi.c | 11 +--
1 file changed, 5 insertions(+), 6 deletions(-)
diff --git a/drivers/spi/kirkwood_spi.c b/drivers/spi/kirkwood_spi.c
index 942a208..449e9f8 100644
--- a/drivers/spi/kirkwood_spi.c
+++ b/drivers/spi/kirkwood_spi.c
@@ -37,7 +37,7 @@ struct spi_slave *spi_setup_slave(unsigned int bus,
unsigned int cs,
if (!slave)
return NULL;
- writel(~KWSPI_CSN_ACT | KWSPI_SMEMRDY, spireg-ctrl);
+ writel(KWSPI_SMEMRDY, spireg-ctrl);
/* calculate spi clock prescaller using max_hz */
data = ((CONFIG_SYS_TCLK / 2) / max_hz) + 0x10;
@@ -137,12 +137,12 @@ void spi_init(void)
void spi_cs_activate(struct spi_slave *slave)
{
- writel(readl(spireg-ctrl) | KWSPI_IRQUNMASK, spireg-ctrl);
+ setbits_le32(spireg-ctrl, KWSPI_CSN_ACT);
}
void spi_cs_deactivate(struct spi_slave *slave)
{
- writel(readl(spireg-ctrl) KWSPI_IRQMASK, spireg-ctrl);
+ clrbits_le32(spireg-ctrl, KWSPI_CSN_ACT);
}
int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
@@ -161,8 +161,7 @@ int spi_xfer(struct spi_slave *slave, unsigned int
bitlen, const void *dout,
* handle data in 8-bit chunks
* TBD: 2byte xfer mode to be enabled
*/
- writel(((readl(spireg-cfg) ~KWSPI_XFERLEN_MASK) |
- KWSPI_XFERLEN_1BYTE), spireg-cfg);
+ clrsetbits_le32(spireg-cfg, KWSPI_XFERLEN_MASK,
KWSPI_XFERLEN_1BYTE);
while (bitlen 4) {
debug(loopstart bitlen %d\n, bitlen);
@@ -172,7 +171,7 @@ int spi_xfer(struct spi_slave *slave, unsigned int
bitlen, const void *dout,
if (dout)
tmpdout = *(u32 *) dout 0x0ff;
- writel(~KWSPI_SMEMRDIRQ, spireg-irq_cause);
+ clrbits_le32(spireg-irq_cause, KWSPI_SMEMRDIRQ);
writel(tmpdout, spireg-dout); /* Write the data out */
debug(*** spi_xfer: ... %08x written, bitlen %d\n,
tmpdout, bitlen);
--
2.0.1
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Re: [U-Boot] [PATCH v1 02/25] arm: kirkwood: spi.h: Add some missing parenthesis
Reviewed-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
On Fri, Jun 27, 2014 at 3:24 PM, Stefan Roese s...@denx.de wrote:
Signed-off-by: Stefan Roese s...@denx.de
Cc: Jagannadha Sutradharudu Teki jaga...@xilinx.com
---
arch/arm/include/asm/arch-kirkwood/spi.h | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm/include/asm/arch-kirkwood/spi.h
b/arch/arm/include/asm/arch-kirkwood/spi.h
index b1cf614..e512dce 100644
--- a/arch/arm/include/asm/arch-kirkwood/spi.h
+++ b/arch/arm/include/asm/arch-kirkwood/spi.h
@@ -43,10 +43,10 @@ struct kwspi_registers {
#define KWSPI_XFERLEN_2BYTE(1 5)
#define KWSPI_XFERLEN_MASK (1 5)
#define KWSPI_ADRLEN_1BYTE 0
-#define KWSPI_ADRLEN_2BYTE 1 8
-#define KWSPI_ADRLEN_3BYTE 2 8
-#define KWSPI_ADRLEN_4BYTE 3 8
-#define KWSPI_ADRLEN_MASK 3 8
+#define KWSPI_ADRLEN_2BYTE (1 8)
+#define KWSPI_ADRLEN_3BYTE (2 8)
+#define KWSPI_ADRLEN_4BYTE (3 8)
+#define KWSPI_ADRLEN_MASK (3 8)
#define KWSPI_TIMEOUT 1
#endif /* __KW_SPI_H__ */
--
2.0.1
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Re: [U-Boot] [PATCH] sf: Stop leaking memory
On Fri, Jun 13, 2014 at 2:23 AM, Marek Vasut ma...@denx.de wrote:
It's usually a common pattern to free() the memory that we allocated.
Implement this here to stop leaking memory. Also, add a debug output
when BAR configuration fails to follow suit.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Michal Simek michal.si...@xilinx.com
Cc: Jagannadha Sutradharudu Teki jaga...@xilinx.com
---
drivers/mtd/spi/sf_ops.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
NOTE: I think we can do without the memory allocation here altogether.
Is there any upper limit on the number of dummy bytes that can
go with a SF command? If so, we can just allocate that buffer on
a stack and be done with it.
diff --git a/drivers/mtd/spi/sf_ops.c b/drivers/mtd/spi/sf_ops.c
index ef91b92..29a7867 100644
--- a/drivers/mtd/spi/sf_ops.c
+++ b/drivers/mtd/spi/sf_ops.c
@@ -398,8 +398,10 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32
offset,
#endif
#ifdef CONFIG_SPI_FLASH_BAR
bank_sel = spi_flash_bank(flash, read_addr);
- if (bank_sel 0)
- return ret;
+ if (bank_sel 0) {
+ debug(SF: bank select failed\n);
+ break;
+ }
This may not require, as definition have it already when fail to set bank.
#endif
remain_len = ((SPI_FLASH_16MB_BOUN flash-shift) *
(bank_sel + 1)) - offset;
@@ -421,6 +423,7 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32
offset,
data += read_len;
}
+ free(cmd);
return ret;
}
--
2.0.0.rc2
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Re: [U-Boot] [PATCH v1 05/25] spi: kirkwood_spi.c: cosmetic: Fix minor coding style issues
Reviewed-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
On Fri, Jun 27, 2014 at 3:24 PM, Stefan Roese s...@denx.de wrote:
Signed-off-by: Stefan Roese s...@denx.de
Cc: Jagannadha Sutradharudu Teki jaga...@xilinx.com
---
drivers/spi/kirkwood_spi.c | 14 ++
1 file changed, 6 insertions(+), 8 deletions(-)
diff --git a/drivers/spi/kirkwood_spi.c b/drivers/spi/kirkwood_spi.c
index 7d1c1f9..3d58bcc 100644
--- a/drivers/spi/kirkwood_spi.c
+++ b/drivers/spi/kirkwood_spi.c
@@ -46,7 +46,7 @@ struct spi_slave *spi_setup_slave(unsigned int bus,
unsigned int cs,
/* program spi clock prescaller using max_hz */
writel(KWSPI_ADRLEN_3BYTE | data, spireg-cfg);
- debug(data = 0x%08x \n, data);
+ debug(data = 0x%08x\n, data);
writel(KWSPI_SMEMRDIRQ, spireg-irq_cause);
writel(KWSPI_IRQMASK, spireg-irq_mask);
@@ -100,7 +100,6 @@ int spi_claim_bus(struct spi_slave *slave)
/* set new spi mpp and save current mpp config */
kirkwood_mpp_conf(spi_mpp_config, spi_mpp_backup);
-
#endif
return board_spi_claim_bus(slave);
@@ -127,7 +126,7 @@ void spi_release_bus(struct spi_slave *slave)
*/
int spi_cs_is_valid(unsigned int bus, unsigned int cs)
{
- return (bus == 0 (cs == 0 || cs == 1));
+ return bus == 0 (cs == 0 || cs == 1);
}
#endif
@@ -169,7 +168,7 @@ int spi_xfer(struct spi_slave *slave, unsigned int
bitlen, const void *dout,
/* Shift data so it's msb-justified */
if (dout)
- tmpdout = *(u32 *) dout 0x0ff;
+ tmpdout = *(u32 *)dout 0xff;
clrbits_le32(spireg-irq_cause, KWSPI_SMEMRDIRQ);
writel(tmpdout, spireg-dout); /* Write the data out */
@@ -185,12 +184,11 @@ int spi_xfer(struct spi_slave *slave, unsigned int
bitlen, const void *dout,
if (readl(spireg-irq_cause) KWSPI_SMEMRDIRQ) {
isread = 1;
tmpdin = readl(spireg-din);
- debug
- (spi_xfer: din %p..%08x read\n,
- din, tmpdin);
+ debug(spi_xfer: din %p..%08x read\n,
+ din, tmpdin);
if (din) {
- *((u8 *) din) = (u8) tmpdin;
+ *((u8 *)din) = (u8)tmpdin;
din += 1;
}
if (dout)
--
2.0.1
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[U-Boot] [PATCH] git-mailrc: Add sunxi custodians.
Signed-off-by: Ian Campbell i...@hellion.org.uk Cc: Hans de Goede hdego...@redhat.com --- doc/git-mailrc | 3 +++ 1 file changed, 3 insertions(+) diff --git a/doc/git-mailrc b/doc/git-mailrc index 251586e..d924b26 100644 --- a/doc/git-mailrc +++ b/doc/git-mailrc @@ -17,10 +17,12 @@ alias ag Anatolij Gustschin ag...@denx.de alias galak Kumar Gala ga...@kernel.crashing.org alias gruss Graeme Russ graeme.r...@gmail.com alias hs Heiko Schocher h...@denx.de +alias ijcIan Campbell ijc+ub...@hellion.org.uk alias iwamatsu Nobuhiro Iwamatsu iwama...@nigauri.org alias jagan Jagannadha Sutradharudu Teki jagannadh.t...@gmail.com alias jasonjin Jason Jin jason@freescale.com alias jhersh Joe Hershberger joe.hershber...@gmail.com +alias jwrdegoede Hans de Goede hdego...@redhat.com alias kimphill Kim Phillips kim.phill...@freescale.com alias macpaulMacpaul Lin macp...@andestech.com alias marex Marek Vasut ma...@denx.de @@ -55,6 +57,7 @@ alias rmobileuboot, iwamatsu alias s3csamsung alias s5pc samsung alias samsunguboot, prom +alias sunxi uboot, ijc, jwrdegoede alias tegra uboot, sjg, Tom Warren twar...@nvidia.com, Stephen Warren swar...@nvidia.com alias tegra2 tegra alias ti uboot, trini -- 1.9.0 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] README: document CONFIG_ENV_IS_IN_SPI_FLASH
Thanks! for the document. Reviewed-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com On Tue, Jul 1, 2014 at 5:00 PM, Josh Wu josh...@atmel.com wrote: The option can be used to save the environment in spi flash. Implementation code is already exist in command/env_sf.c. But the documentation is missing. This patch add the details for this option to the README file. Signed-off-by: Josh Wu josh...@atmel.com --- README | 37 + 1 file changed, 37 insertions(+) diff --git a/README b/README index fe5cacb..794cfb0 100644 --- a/README +++ b/README @@ -4069,6 +4069,43 @@ to save the current settings. environment area within the total memory of your DataFlash placed at the specified address. +- CONFIG_ENV_IS_IN_SPI_FLASH: + + Define this if you have a SPI Flash memory device which you + want to use for the environment. + + - CONFIG_ENV_OFFSET: + - CONFIG_ENV_SIZE: + + These two #defines specify the offset and size of the + environment area within the SPI Flash. CONFIG_ENV_OFFSET must be + aligned to an erase sector boundary. + + - CONFIG_ENV_SECT_SIZE: + + Define the SPI flash's sector size. + + - CONFIG_ENV_OFFSET_REDUND (optional): + + This setting describes a second storage area of CONFIG_ENV_SIZE + size used to hold a redundant copy of the environment data, so + that there is a valid backup copy in case there is a power failure + during a saveenv operation. CONFIG_ENV_OFFSET_RENDUND must be + aligned to an erase sector boundary. + + - CONFIG_ENV_SPI_BUS (optional): + - CONFIG_ENV_SPI_CS (optional): + + Define the SPI bus and chip select. If not defined they will be 0. + + - CONFIG_ENV_SPI_MAX_HZ (optional): + + Define the SPI max work clock. If not defined then use 1MHz. + + - CONFIG_ENV_SPI_MODE (optional): + + Define the SPI work mode. If not defined then use SPI_MODE_3. + - CONFIG_ENV_IS_IN_REMOTE: Define this if you have a remote memory space which you -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot -- Jagan. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] git-mailrc: Add sunxi custodians.
Hi, On 07/03/2014 10:25 PM, Ian Campbell wrote: Signed-off-by: Ian Campbell i...@hellion.org.uk Cc: Hans de Goede hdego...@redhat.com ACK. Acked-by: Hans de Goede hdego...@redhat.com Regards, Hans --- doc/git-mailrc | 3 +++ 1 file changed, 3 insertions(+) diff --git a/doc/git-mailrc b/doc/git-mailrc index 251586e..d924b26 100644 --- a/doc/git-mailrc +++ b/doc/git-mailrc @@ -17,10 +17,12 @@ alias ag Anatolij Gustschin ag...@denx.de alias galak Kumar Gala ga...@kernel.crashing.org alias gruss Graeme Russ graeme.r...@gmail.com alias hs Heiko Schocher h...@denx.de +alias ijcIan Campbell ijc+ub...@hellion.org.uk alias iwamatsu Nobuhiro Iwamatsu iwama...@nigauri.org alias jagan Jagannadha Sutradharudu Teki jagannadh.t...@gmail.com alias jasonjin Jason Jin jason@freescale.com alias jhersh Joe Hershberger joe.hershber...@gmail.com +alias jwrdegoede Hans de Goede hdego...@redhat.com alias kimphill Kim Phillips kim.phill...@freescale.com alias macpaulMacpaul Lin macp...@andestech.com alias marex Marek Vasut ma...@denx.de @@ -55,6 +57,7 @@ alias rmobileuboot, iwamatsu alias s3csamsung alias s5pc samsung alias samsunguboot, prom +alias sunxi uboot, ijc, jwrdegoede alias tegra uboot, sjg, Tom Warren twar...@nvidia.com, Stephen Warren swar...@nvidia.com alias tegra2 tegra alias ti uboot, trini ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] SPL broken on i.mx31 platforms
Hi, On Thu, Jul 3, 2014 at 10:19 AM, Helmut Raiger helmut.rai...@hale.at wrote: On 07/03/2014 01:20 AM, Benoît Thébaudeau wrote: )Dear Helmut Raiger, On Wed, Jul 2, 2014 at 9:04 AM, Helmut Raiger helmut.rai...@hale.at wrote: the commit 41623c91 breaks the SPL on i.mx31 platforms. Here, you are talking about mx31pdk, right? Actually im talking TT-01, but it has no contributed NAND boot code (which I was working on), but it should hit mx31pdk in the same way. This should answer Albert's question about the board. Then, since you are out of tree, can you test with the HEAD vs. 41623c91 vs. 41623c91^ mx31pdk codes, replacing the _reset lines with b reset or bl reset after _start: for 41623c91 and HEAD? It would probably run U-Boot on TT-01 too. You can remove board-specific initializations like GPIO outputs from mx31pdk.c in order not to risk damaging the board (just keep a valid UART to see the boot). This is just to make sure that there is nothing wrong in your out-of-tree code that could interfere with the mainline changes, like a custom SPL linker script that would miss the *(.vectors) section. The original startup code (start.S) was position independent to allow relocation in board_init_f. This is necessary as the internal RAM used by the IPL to load the first 2kB from NAND is also used by the NAND controller to buffer pages. As far as the issue goes: where and how exactly is the code not position independent now? The first statement is now: ldr pc, _reset _reset: .word reset reset is an address generated by the linker (here 0x87dc0060). Originally this was: b reset which is a relative branch (here 0x60 bytes forward). I have to add, that changing this back does not fix the issue, something else is in disorder. I'm still working on it. Do you mean reverting this commit, or only these two lines? In the former case, where does bisect lead to, and in the latter case, have you checked the assembler code in the linked SPL for this branch? I was bisecting the issue by hand :-! , always rebasing my developement branch to somewhere in the master tree and found commit 41623c91 that way, as stated in the first message of the thread. Reverting the commit fixes it, but it should only be a few offending lines. You are talking about rebasing, reverting, and testing with modified mainline. Just to make things clear, do you confirm that reverting commit 41623c91 on top of mainline works (not just rebasing before this commit)? You mentioned failing tests with a modified mainline, so I want to make sure that there is no other offending commit after 41623c91 that would interfere with these tests. Does changing the startup code back to PIC generate any drawbacks on other ARM platforms? How would this changing back to PIC be implemented? Not by reverting the patch, I hope. No, it will only be a minor change, I think, but I thought there might have been an additional intention behind the change to position dependent code. One could link the first part to 0xB800 (the original position of the SPL when loaded by the IPL) and the part after the relocation to CONFIG_SPL_TEXT_BASE. Actually, the ROM bootloader first copies the first NAND page to 0xB800. Then, the SPL placed here but linked at CONFIG_SPL_TEXT_BASE copies itself to CONFIG_SPL_TEXT_BASE in order to free the NFC buffer so that it can be used by the SPL. There is no relocation going on at this stage, but only a copy, and the SPL code size is limited to 2 kiB. Then, the SPL does its NAND load job towards CONFIG_SYS_TEXT_BASE and starts executing the non-SPL binary, which then relocates itself according to the heap size, etc. Hence, as you said the code launching board_init_f() must be either PIC or linked at 0xB800, and the rest of the SPL code must be either PIC or linked at CONFIG_SPL_TEXT_BASE. So the fact that this commit breaks the PICness of the initial branch is indeed an issue. As a test, can you try to replace the 2 _reset lines in vectors.S with b _reset after _start:, and a _reset: label at the end of the file? This assumes that start.S starts with the reset: label, and that the start.o .text sections are placed right after the .vectors section in the SPL linker script, both being true for mx31pdk. I was using the word 'relocation' instead of copying. I did what you suggest, but this does not completely fix the issue. If the only wrong commit is 41623c91, I do not see what else could be wrong, hence my questions above. What do you mean by not completely? Is there any progress? At a quick glance at the assembler code of board_init_f it looked PIC to me, but I'll have to check. If you duplicated mx31pdk's, it should be PIC. I'm currently torn between projects, which is why I have no further input right now. No problem. Benoît ___ U-Boot mailing list U-Boot@lists.denx.de
Re: [U-Boot] SPL broken on i.mx31 platforms
Hi Albert, On Thu, Jul 3, 2014 at 3:35 PM, Albert ARIBAUD albert.u.b...@aribaud.net wrote: Hi Helmut, On Thu, 03 Jul 2014 10:19:39 +0200, Helmut Raiger helmut.rai...@hale.at wrote: Hi, On 07/03/2014 01:20 AM, Benoît Thébaudeau wrote: )Dear Helmut Raiger, On Wed, Jul 2, 2014 at 9:04 AM, Helmut Raiger helmut.rai...@hale.at wrote: the commit 41623c91 breaks the SPL on i.mx31 platforms. Here, you are talking about mx31pdk, right? Actually im talking TT-01, but it has no contributed NAND boot code (which I was working on), but it should hit mx31pdk in the same way. This should answer Albert's question about the board. It does, thanks -- but I fail to see any SPL code built for TT-01. You're getting SPL issues with another target, right? Helmut seems to be working on a custom TT-01 variant (or just with a specific hardware configuration using dip switches, or jumpers, etc.) using the i.MX31 NAND internal boot rather than the mainline boot source. No, it will only be a minor change, I think, but I thought there might have been an additional intention behind the change to position dependent code. One could link the first part to 0xB800 (the original position of the SPL when loaded by the IPL) and the part after the relocation to CONFIG_SPL_TEXT_BASE. Actually, the ROM bootloader first copies the first NAND page to 0xB800. Then, the SPL placed here but linked at CONFIG_SPL_TEXT_BASE copies itself to CONFIG_SPL_TEXT_BASE in order to free the NFC buffer so that it can be used by the SPL. There is no relocation going on at this stage, but only a copy, and the SPL code size is limited to 2 kiB. Then, the SPL does its NAND load job towards CONFIG_SYS_TEXT_BASE and starts executing the non-SPL binary, which then relocates itself according to the heap size, etc. Ok, I think I'm getting it, but actually you don't need PIC (your code won't run at arbitrary locations), you need VMAs vs LMAs (your code will run partly at one location, partly at another, but will be loaded at only one of these locations). Therefore, we should be able to manage this in the linker script, by basically defining two output sections: the first one with a VMA and LMA equal to 0xB800 both, and which would contain the 'copier' code; and the second one with a VMA equal to CONFIG_SPL_TEXT_BASE (so that it links properly for running at that address) and a LMA equal to 0xB80 (so that it gets lumped with the first section in the less-than-2K ELF file produced by the linker. (actually we'd have several output sections with VMA==LMA, but it does not affect the core of the idea.) Does it make sense to you? It makes sense to me. That should work, but it'd be better to avoid adding a custom linker script. A simple fix in vectors.S would be preferable if possible. Also, the __image_copy_start stuff should be taken care of with such a change. BTW, I see that you skipped arch/arm/cpu/arm1136/u-boot-spl.lds in commit 41623c91 (addition of *(.vectors)). Was it intentional? It silently changes woodburn_sd because the fallback exception vectors no longer exist. This should not cause a build error because the _start symbol is duplicated in this linker script. The board may also boot correctly with this, but the default vectors can be useful in some cases, especially for debugging exceptions. Cordialement, Benoît ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] sf: Stop leaking memory
On Thursday, July 03, 2014 at 10:24:44 PM, Jagan Teki wrote:
On Fri, Jun 13, 2014 at 2:23 AM, Marek Vasut ma...@denx.de wrote:
It's usually a common pattern to free() the memory that we allocated.
Implement this here to stop leaking memory. Also, add a debug output
when BAR configuration fails to follow suit.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Michal Simek michal.si...@xilinx.com
Cc: Jagannadha Sutradharudu Teki jaga...@xilinx.com
---
drivers/mtd/spi/sf_ops.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
NOTE: I think we can do without the memory allocation here altogether.
Is there any upper limit on the number of dummy bytes that can
go with a SF command? If so, we can just allocate that buffer on
a stack and be done with it.
diff --git a/drivers/mtd/spi/sf_ops.c b/drivers/mtd/spi/sf_ops.c
index ef91b92..29a7867 100644
--- a/drivers/mtd/spi/sf_ops.c
+++ b/drivers/mtd/spi/sf_ops.c
@@ -398,8 +398,10 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash,
u32 offset,
#endif
#ifdef CONFIG_SPI_FLASH_BAR
bank_sel = spi_flash_bank(flash, read_addr);
- if (bank_sel 0)
- return ret;
+ if (bank_sel 0) {
+ debug(SF: bank select failed\n);
+ break;
+ }
This may not require, as definition have it already when fail to set bank.
Feel free to drop this when applying.
Btw. the information printing is quite inconsistent in this stuff.
Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH v1 23/25] tools: Compile kwboot for Marvell Armada XP as those SoCs are now supported
On Fri, Jun 27, 2014 at 11:55:09AM +0200, Stefan Roese wrote: Signed-off-by: Stefan Roese s...@denx.de --- tools/Makefile | 1 + 1 file changed, 1 insertion(+) Tested-by: Luka Perkov l...@openwrt.org Luka ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v1 22/25] tools/kwboot: Sync with latest barebox version to support Armada XP
Hi Stefan,
On Fri, Jun 27, 2014 at 11:55:08AM +0200, Stefan Roese wrote:
The barebox version of the kwboot tool has evolved a bit. To support
Armada XP and Dove. Additionally a few minor fixes have been applied.
So lets sync with the latest barebox version.
Please note that the main difference between both versions now is, that
the U-Boot version still supports the -p option, to dynamically patch
an image for UART boot mode. I didn't test it now though.
Signed-off-by: Stefan Roese s...@denx.de
---
tools/kwboot.c | 97
+-
1 file changed, 83 insertions(+), 14 deletions(-)
...
-#define KWBOOT_MSG_REQ_DELAY 10 /* ms */
-#define KWBOOT_MSG_RSP_TIMEO 50 /* ms */
+static unsigned char kwboot_msg_debug[] = {
+ 0xDD, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77
+};
+
+#define KWBOOT_MSG_REQ_DELAY 1000 /* ms */
+#define KWBOOT_MSG_RSP_TIMEO 1000 /* ms */
This causes problems on kirkwood. The old values should be kept, apply
the patch below to this one. After that chage feel free to add Tested-by
line.
Tested-by: Luka Perkov l...@openwrt.org
Now only to figure out why 21/25 breaks things on kirkwood.
Luka
diff --git a/tools/kwboot.c b/tools/kwboot.c
index c47970e..ccc9d90 100644
--- a/tools/kwboot.c
+++ b/tools/kwboot.c
@@ -42,8 +42,8 @@ static unsigned char kwboot_msg_debug[] = {
0xDD, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77
};
-#define KWBOOT_MSG_REQ_DELAY 1000 /* ms */
-#define KWBOOT_MSG_RSP_TIMEO 1000 /* ms */
+#define KWBOOT_MSG_REQ_DELAY 10 /* ms */
+#define KWBOOT_MSG_RSP_TIMEO 50 /* ms */
/*
* Xmodem Transfers
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Re: [U-Boot] [PATCH v1 24/25] tools: kwbimage: Add image version 1 support for Armada XP / 370
On Fri, Jun 27, 2014 at 11:55:10AM +0200, Stefan Roese wrote: This patch integrates the Barebox version of this kwbimage.c file into U-Boot. As this version supports the image version 1 type for the Armada XP / 370 SoCs. It was easier to integrate the existing and known to be working Barebox source than to update the current U-Boot version to support this v1 image header format. Now all Marvell MVEBU SoCs are supported: Image type 0: Kirkwood Dove Image type 1: Armada 370 Armada XP Please note that the current v1 support has this restuction (same as has Barebox version): Not implemented: support for the register headers and secure headers in v1 images Tested on Marvell DB-78460-BP eval board. Signed-off-by: Stefan Roese s...@denx.de --- tools/kwbimage.c | 1050 -- 1 file changed, 782 insertions(+), 268 deletions(-) Tested-by: Luka Perkov l...@openwrt.org Luka ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3 13/13] fit: make sha256 support optional
Hello Dirk, Tom, Simon, Am 03.07.2014 21:17, schrieb Tom Rini: On Thu, Jul 03, 2014 at 09:14:01AM -0700, Simon Glass wrote: Hi, On 3 July 2014 00:03, Heiko Schocherh...@denx.de wrote: Hello Dirk, Am 03.07.2014 08:27, schrieb dirk.eib...@gdsys.cc: From: Dirk Eibachdirk.eib...@gdsys.cc sha256 has some beefy memory footprint. Make it optional for constrained systems. Signed-off-by: Dirk Eibachdirk.eib...@gdsys.cc --- Changes in v3: None Changes in v2: - make sha256 support optional include/configs/dlvision-10g.h | 1 + include/configs/io.h | 1 + include/configs/iocon.h| 1 + include/configs/neo.h | 1 + include/image.h| 5 + 5 files changed, 9 insertions(+) Sorry, some nitpick. As you introduce here the new define CONFIG_FIT_DISABLE_SHA256, can you please add a short description in the README, thanks! I wonder if it would be better to make the option off by default? You could perhaps use the existing CONFIG_SHA256 option, and check in image.h to enable/disable support. Heiko what do you think? Yes, that would be good, it would safe a lot of code ... I think I like this unless there's a problem... ... IIRC, as I did the sha256-rsa2048, sha256-rsa4096 adaptions, I had this in mind, but there was a problem or just forgot it to do it at the end ... so I just tried to compile the ids8313 board with having this options off by default, precisly on current mainline I did: $ git diff diff --git a/include/image.h b/include/image.h index 0a072f5..389423e 100644 --- a/include/image.h +++ b/include/image.h @@ -72,6 +72,9 @@ struct lmb; # define IMAGE_ENABLE_SHA256 1 # endif +#undef CONFIG_SHA256 +#undef IMAGE_ENABLE_SHA256 + #ifndef IMAGE_ENABLE_CRC32 #define IMAGE_ENABLE_CRC32 0 #endif --- make mrproper make ids8313_config make CROSS_COMPILE=powerpc-linux- env make CROSS_COMPILE=powerpc-linux- cross_tools works without errors, but $ ./MAKEALL ids8313 Configuring for ids8313 - Board: ids8313, Options: SYS_TEXT_BASE=0xFFF0 powerpc-linux-size: './u-boot': No such file lib/built-in.o: In function `sha256_calculate': /home/hs/ids/u-boot/lib/rsa/rsa-checksum.c:159: undefined reference to `sha256_starts' /home/hs/ids/u-boot/lib/rsa/rsa-checksum.c:161: undefined reference to `sha256_update' /home/hs/ids/u-boot/lib/rsa/rsa-checksum.c:162: undefined reference to `sha256_finish' make: *** [u-boot] Fehler 1 same for am335x_boneblack_vboot, sandbox. So there must be also looked at this sha256_calculate() in lib/rsa/rsa-checksum.c and common/image-sig.c checksum_algos[] and image_sig_algos[] must be adjusted, reworked ... If we do this for CONFIG_SHA256 I vote for doing this for all checksum algorithms ... and we must look to the boards, which use FIT support, that we enable all options bayk they use again. bye, Heiko -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 3/4] ARM: LS1021A: enable ARMv7 virt support for LS1021A A7
diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index d639a6f..f090971 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -18,6 +18,15 @@ #define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_ARCH_EARLY_INIT_R +#define CONFIG_ARMV7_NONSEC +#define CONFIG_ARMV7_VIRT +#define CONFIG_SOC_BIG_ENDIAN +#define CONFIG_DCFG_CCSR_SCRATCHRW10x01ee0200 +#define CONFIG_DCFG_CCSR_BRR 0x01ee00e4 Why are you hardcoding the register addresses in this file? I saw that all registers are defined in: arch/arm/include/asm/arch-ls102xa/config.h. Why are these special? No special, and I'll follow your advice. +#define CONFIG_SMP_PEN_ADDRCONFIG_DCFG_CCSR_SCRATCHRW1 +#define CONFIG_ARM_GIC_BASE_ADDRESS0x0140 Why do you need the GIC base address? Can't this be read from CBAR? I'm not very sure, I have tried, but failed, I will do some research later. Thanks, BRs Xiubo +#define CONFIG_TIMER_CLK_FREQ 12500 + #define CONFIG_HWCONFIG #define HWCONFIG_BUFFER_SIZE 128 diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index a8dc56e..235a862 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -18,6 +18,15 @@ #define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_ARCH_EARLY_INIT_R +#define CONFIG_ARMV7_NONSEC +#define CONFIG_ARMV7_VIRT +#define CONFIG_SOC_BIG_ENDIAN +#define CONFIG_DCFG_CCSR_SCRATCHRW10x01ee0200 +#define CONFIG_DCFG_CCSR_BRR 0x01ee00e4 +#define CONFIG_SMP_PEN_ADDRCONFIG_DCFG_CCSR_SCRATCHRW1 +#define CONFIG_ARM_GIC_BASE_ADDRESS0x0140 +#define CONFIG_TIMER_CLK_FREQ 12500 + #define CONFIG_HWCONFIG #define HWCONFIG_BUFFER_SIZE 128 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 0/4] Add LS1021A-QDS/TWR Non-secure and HYP support.
This patch series depends on the following patch: [U-Boot,v4,03/10] ARM: non-sec: reset CNTVOFF to zero Before switching to non-secure, make sure that CNTVOFF is set to zero on all CPUs. Otherwise, kernel running in non-secure without HYP enabled (hence using virtual timers) may observe But we have HYP enabled. In this case why are the series dependent on this patch? Well, if the HYP is enabled, the host OS will use the Physical timer, and these CNTVOFFs could be cleared in kernel too. When and where to clear them is better ? In uboot or in kernel when needed? Thanks, BRs Xiubo timers that are not synchronized, effectively seeing time going backward... Patch work: http://patchwork.ozlabs.org/patch/343084/ Xiubo Li (4): ARM: fix the ARCH Timer frequency setting. ARM: add the pen address byte reverting support. ARM: LS1021A: enable ARMv7 virt support for LS1021A A7 ARM: LS1021A: to allow non-secure R/W access for all devices' mapped region arch/arm/cpu/armv7/ls102xa/cpu.c | 12 +++ arch/arm/cpu/armv7/nonsec_virt.S | 7 +- arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 98 +- - board/freescale/ls1021aqds/ls1021aqds.c | 110 +++-- board/freescale/ls1021atwr/ls1021atwr.c | 111 -- include/configs/ls1021aqds.h | 9 ++ include/configs/ls1021atwr.h | 9 ++ 7 files changed, 333 insertions(+), 23 deletions(-) Diana ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/4] ARM: fix the ARCH Timer frequency setting.
Subject: Re: [PATCH 1/4] ARM: fix the ARCH Timer frequency setting. On 07/03/2014 12:51 PM, Xiubo Li wrote: For some SoCs, the CONFIG_SYS_CLK_FREQ maybe won't equal the ARCH Timer's frequency. Can you give an example? In LS1021A-QDS/TWR, the CONFIG_SYS_CLK_FREQ is 100Mhz and the ARCH timer's Frequency will be 12.5Mhz... Here using the CONFIG_TIMER_CLK_FREQ instead if the ARCH Timer's frequency need to config here. Signed-off-by: Xiubo Li li.xi...@freescale.com --- arch/arm/cpu/armv7/nonsec_virt.S | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/cpu/armv7/nonsec_virt.S b/arch/arm/cpu/armv7/nonsec_virt.S index 6f90988..e9766c0 100644 --- a/arch/arm/cpu/armv7/nonsec_virt.S +++ b/arch/arm/cpu/armv7/nonsec_virt.S @@ -147,11 +147,11 @@ ENTRY(_nonsec_init) * we do this here instead. * But first check if we have the generic timer. */ -#ifdef CONFIG_SYS_CLK_FREQ +#ifdef CONFIG_TIMER_CLK_FREQ Aren't you breaking the boards which rely on CONFIG_SYS_CLK_FREQ ? I hadn't found any board is using this in the upstreamed tree, or may I miss something ? If there exist some, and I will redefined it for them here. In ARMv7, what could I find is that only vexpress_ca15_tc2 board has enabled the CONFIG_ARMV7_VIRT without defining it. Thanks, BRs Xiubo mrc p15, 0, r0, c0, c1, 1 @ read ID_PFR1 and r0, r0, #CPUID_ARM_GENTIMER_MASK@ mask arch timer bits cmp r0, #(1 CPUID_ARM_GENTIMER_SHIFT) - ldreq r1, =CONFIG_SYS_CLK_FREQ + ldreq r1, =CONFIG_TIMER_CLK_FREQ mcreq p15, 0, r1, c14, c0, 0 @ write CNTFRQ #endif Diana ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 4/4] ARM: LS1021A: to allow non-secure R/W access for all devices' mapped region
- reg = in_be32(csu_csl2);
- out_be32(csu_csl2, reg | CSU_CSL2x_NS_SUP_READ_ACCESS |
- CSU_CSL2x_NS_USER_READ_ACCESS);
+void enable_devices_ns_access(void)
This function is identical for twr and qds? Can't be just one in a
common file?
Sure, I will follow your advice.
Thanks,
BRs
Xiubo
+{
+ uint32_t *csu_csl;
+ uint32_t reg;
+ int i;
+
+ for (i = 0; i ARRAY_SIZE(ns_dev); i++) {
+ csu_csl = CONFIG_SYS_FSL_CSU_ADDR + ns_dev[i].ind / 2 * 4;
+ reg = in_be32(csu_csl);
+ if (ns_dev[i].ind % 2 == 0)
+ reg |= ns_dev[i].val 16;
+ else
+ reg |= ns_dev[i].val;
+ out_be32(csu_csl, reg);
+ }
}
int board_late_init(void)
@@ -483,7 +580,7 @@ int board_late_init(void)
ahci_init(AHCI_BASE_ADDR);
scsi_scan(1);
- enable_ifc_ns_read_access();
+ enable_devices_ns_access();
return 0;
}
Diana Craciun
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Re: [U-Boot] [PATCH v3 13/13] fit: make sha256 support optional
Whatever we do: we have some broken boards, so please let us fix it before next release. I am off on vacation now. If necessary simply drop this patch from the series. Cheers Dirk ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v4 02/12] exynos: pinmux: fix the gpio names for exynos4x12 mmc
It's reasonable, looks good to me. Acked-by: Jaehoon Chung jh80.ch...@samsung.com On 07/02/2014 08:50 PM, Przemyslaw Marczak wrote: This change fixes the bad gpio configuration for the exynos dwmmc. Signed-off-by: Przemyslaw Marczak p.marc...@samsung.com Cc: Beomho Seo beomho@samsung.com Cc: Minkyu Kang mk7.k...@samsung.com Cc: Jaehoon Chung jh80.ch...@samsung.com --- arch/arm/cpu/armv7/exynos/pinmux.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/cpu/armv7/exynos/pinmux.c b/arch/arm/cpu/armv7/exynos/pinmux.c index 86a0c75..b929486 100644 --- a/arch/arm/cpu/armv7/exynos/pinmux.c +++ b/arch/arm/cpu/armv7/exynos/pinmux.c @@ -704,8 +704,8 @@ static int exynos4x12_mmc_config(int peripheral, int flags) ext_func = S5P_GPIO_FUNC(0x3); break; case PERIPH_ID_SDMMC4: - start = EXYNOS4_GPIO_K00; - start_ext = EXYNOS4_GPIO_K13; + start = EXYNOS4X12_GPIO_K00; + start_ext = EXYNOS4X12_GPIO_K13; func = S5P_GPIO_FUNC(0x3); ext_func = S5P_GPIO_FUNC(0x4); break; ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v4 04/12] board:samsung: check the boot device and init the right mmc driver.
Hi, Przemyslaw.
On 07/02/2014 08:50 PM, Przemyslaw Marczak wrote:
It is possible to boot device using a micro SD or eMMC slots.
In this situation, boot device should be registered as a block
device 0 in the MMC framework, because CONFIG_SYS_MMC_ENV_DEV
is usually set to 0 in the most config cases.
Signed-off-by: Przemyslaw Marczak p.marc...@samsung.com
---
Changes V3:
- separate two changes into two commits
Changes V4:
- board.c: add functions: init_mmc() and init_dwmmc()
- board_mmc_init(): call get_boot_mode()
---
board/samsung/common/board.c | 37 +++--
1 file changed, 27 insertions(+), 10 deletions(-)
diff --git a/board/samsung/common/board.c b/board/samsung/common/board.c
index 9dc7c83..4d3f216 100644
--- a/board/samsung/common/board.c
+++ b/board/samsung/common/board.c
@@ -240,22 +240,39 @@ int board_eth_init(bd_t *bis)
}
#ifdef CONFIG_GENERIC_MMC
-int board_mmc_init(bd_t *bis)
+static int init_mmc(void)
+{
+#ifdef CONFIG_SDHCI
+ return exynos_mmc_init(gd-fdt_blob);
+#else
+ return 0;
+#endif
+}
+
+static int init_dwmmc(void)
{
- int ret;
#ifdef CONFIG_DWMMC
- /* dwmmc initializattion for available channels */
- ret = exynos_dwmmc_init(gd-fdt_blob);
- if (ret)
- debug(dwmmc init failed\n);
+ return exynos_dwmmc_init(gd-fdt_blob);
+#else
+ return 0;
#endif
+}
+
+int board_mmc_init(bd_t *bis)
+{
+ int ret;
+
+ if (get_boot_mode() == BOOT_MODE_MMC) {
+ ret = init_mmc();
+ ret |= init_dwmmc();
+ } else {
+ ret = init_dwmmc();
+ ret |= init_mmc();
+ }
Well, i have some confusion for this.
Did you consider the case like init_dwmmc() is succeed and init_mmc() is failed?
it's hard to control the error for both.
Best Regards,
Jaehoon Chung
-#ifdef CONFIG_SDHCI
- /* mmc initializattion for available channels */
- ret = exynos_mmc_init(gd-fdt_blob);
if (ret)
debug(mmc init failed\n);
-#endif
+
return ret;
}
#endif
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Re: [U-Boot] [PATCH v4 08/12] samsung: board: enable support of multiple board types
On 07/02/2014 08:50 PM, Przemyslaw Marczak wrote:
This change adds declaration of functions:
- set_board_type() - called at checkboard()
- get_board_type() - called at checkboard()
- get_board_name()
For supporting multiple board types in a one config - it is welcome
to display the current board model. This is what get_board_type()
should return.
Signed-off-by: Przemyslaw Marczak p.marc...@samsung.com
Cc: Piotr Wilczek p.wilc...@samsung.com
Cc: Minkyu Kang mk7.k...@samsung.com
---
Changes v3:
- change the commit order
- include/samsung/misc.h: add new functions declaration
- update a commit message
Changes v4:
- checkboard(): remove redundant variable
---
board/samsung/common/board.c | 12 +---
include/samsung/misc.h | 5 +
2 files changed, 14 insertions(+), 3 deletions(-)
diff --git a/board/samsung/common/board.c b/board/samsung/common/board.c
index a46e87b..3e27130 100644
--- a/board/samsung/common/board.c
+++ b/board/samsung/common/board.c
@@ -280,11 +280,17 @@ int board_mmc_init(bd_t *bis)
#ifdef CONFIG_DISPLAY_BOARDINFO
int checkboard(void)
{
- const char *board_name;
+ const char *board_info;
Is there a reason that it's renaming?
Best Regards,
Jaehoon Chung
- board_name = fdt_getprop(gd-fdt_blob, 0, model, NULL);
- printf(Board: %s\n, board_name ? board_name : unknown);
+ board_info = fdt_getprop(gd-fdt_blob, 0, model, NULL);
+ printf(Board: %s\n, board_info ? board_info : unknown);
+#ifdef CONFIG_BOARD_TYPES
+ set_board_type();
+ board_info = get_board_type();
+
+ printf(Model: %s\n, board_info ? board_info : unknown);
+#endif
return 0;
}
#endif
diff --git a/include/samsung/misc.h b/include/samsung/misc.h
index e82bf32..cc41997 100644
--- a/include/samsung/misc.h
+++ b/include/samsung/misc.h
@@ -33,5 +33,10 @@ char *get_dfu_alt_system(void);
char *get_dfu_alt_boot(void);
void set_dfu_alt_info(void);
#endif
+#ifdef CONFIG_BOARD_TYPES
+void set_board_type(void);
+const char *get_board_type(void);
+const char *get_board_name(void);
+#endif
#endif /* __SAMSUNG_MISC_COMMON_H__ */
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