Hi York,
On 08/12/2014 08:03 PM, York Sun wrote:
On 07/18/2014 02:10 AM, Valentin Longchamp wrote:
Hello Wolfgang,
On 07/17/2014 02:47 PM, Wolfgang Denk wrote:
Dear Valentin,
In message
1405599840-11984-1-git-send-email-valentin.longch...@keymile.com you
wrote:
When u-boot initializes
On 08/12/2014 07:54 PM, York Sun wrote:
On 07/17/2014 05:22 AM, Valentin Longchamp wrote:
There is the requirement on the chassis's backplane that when the clocks
are enabled, they should not disappear. Resetting theses chips at unit
I guess here they means the clocks.
Yes, correct.
Hi Frank,
Well I've got to say, as a User I'd surely like to learn some new tricks
from
time to time. I believe this new mailing list would be the right place
for it.
What is happening now: my Mailbox gets full of messages, that I barely
read
(because they are just too many), most of
Hi Fabio,
On 12/08/2014 22:29, Fabio Estevam wrote:
From: Fabio Estevam fabio.este...@freescale.com
Currently I don't have access to a mx31pdk board.
Magnus was the original maintainer of the board and accepted to take back
this role.
Signed-off-by: Fabio Estevam
Hi Ian,
On 10/06/2014 00:08, Iain Paton wrote:
On MarS usdhc3 is eMMC, on RIoT usdhc3 is uSD and eMMC is usdhc4.
Don't run the MarS specific eMMC reset code on usdhc3 when
board_type == BOARD_IS_RIOTBOARD
Signed-off-by: Iain Paton ipat...@gmail.com
---
Am 2014-08-13 00:58, schrieb Bill Pringlemeir:
On 12 Aug 2014, scottw...@freescale.com wrote:
On Tue, 2014-08-12 at 23:13 +0200, Stefan Agner wrote:
Am 2014-08-12 00:33, schrieb Scott Wood:
On Wed, 2014-08-06 at 10:59 +0200, Stefan Agner wrote:
This adds initial support for Freescale NFC
There is the requirement on the chassis's backplane that when the clocks
have been enabled, they then should not disappear.
Resetting the Zarlink clocking chips at unit reset violates this
requirement because the backplane clocks are not supplied during the
reset time.
To avoid this side effect,
When u-boot initializes the RAM (early in boot) it looks for the pram
env variable to know which is area it cannot use. If the pram env variable
is not found, the default CONFIG_PRAM value is used.
This value used to be 0 (no protection at all). This patch sets it to a
value that covers PHRAM and
On 12 Aug 2014, scottw...@freescale.com wrote:
On Tue, 2014-08-12 at 23:13 +0200, Stefan Agner wrote:
Am 2014-08-12 00:33, schrieb Scott Wood:
On Wed, 2014-08-06 at 10:59 +0200, Stefan Agner wrote:
This adds initial support for Freescale NFC (NAND Flash
Controller). The IP is used in ARM
Hello.
I'm trying to find a way how to pass bootargs to arm64 kernel.
In arm32 kernel, we can pass bootargs with atag from u-boot to kernel. So,
we can overwrite kernel's bootargs with u-boot's bootargs.
But from arm64 kernel, the dtb is the only argument that should be passed
from bootloader
From: Shaohui Xie shaohui@freescale.com
XFI is supported on T4QDS-XFI board, which removed slot3, and four LANEs
of serdes2 are routed to a SFP+ cages, which to house fiber cable or
direct attach cable(copper), the copper cable is used to emulate the
10GBASE-KR scenario.
So, for XFI usage,
From: Shaohui Xie shaohui@freescale.com
1. use Payload length check disable when enable MAC;
2. add XGMII support for setting MAC interface mode;
3. only enable auto negotiation for Non-XGMII mode;
4. return 0x if clause 22 is used to read 10G phy_id;
Signed-off-by: Shaohui Xie
On Wed, Aug 13, 2014 at 11:21:32AM +0900, Youngmin Nam wrote:
Hello.
I'm trying to find a way how to pass bootargs to arm64 kernel.
In arm32 kernel, we can pass bootargs with atag from u-boot to kernel. So,
we can overwrite kernel's bootargs with u-boot's bootargs.
But from arm64 kernel,
From: Shaohui Xie shaohui@freescale.com
NEG bit default is '1' for external MDIOs as per FMAN-v3 RM, but on some
platforms, e.g. T2080QDS, this bit is '0', which leads to MDIO failure
on XAUI PHY, so set this bit definitely to align with the RM.
Signed-off-by: Shaohui Xie
Hi Simon,
On 12/08/14 17:48, Simon Glass wrote:
Hi Nikita,
On 11 August 2014 10:22, Nikita Kiryanov nik...@compulab.co.il wrote:
Add initial support for Compulab CM-FX6 CoM.
Support includes MMC, SPI flash, and SPL with dynamic DRAM detection.
[..snip..]
board/compulab/cm_fx6/common.h
Hi,
Does anyone tested by integrating thor functionality with the ci_udc driver
instead of samsung s3c_udc_otg? I am trying to do the same on my zynq board
then the enumeration was successful but not able to download the file using
lthor.
Any other inputs on this would be fine.
Regards,
DP
Am 2014-08-13 00:58, schrieb Bill Pringlemeir:
[snip]
+static u32 nfc_read(struct mtd_info *mtd, uint reg)
+{
+ struct fsl_nfc *nfc = mtd_to_nfc(mtd);
+
+ if (reg == NFC_FLASH_STATUS1 ||
+ reg == NFC_FLASH_STATUS2 ||
+ reg == NFC_IRQ_STATUS)
+ return __raw_readl(nfc-regs +
Hi Stefano,
On Wed, Aug 13, 2014 at 4:28 AM, Stefano Babic sba...@denx.de wrote:
Hi Fabio,
On 12/08/2014 22:29, Fabio Estevam wrote:
From: Fabio Estevam fabio.este...@freescale.com
Currently I don't have access to a mx31pdk board.
Magnus was the original maintainer of the board and
On 08/05/2014 02:32 PM, Magnus Lilja wrote:
Hi Fabio,
On 5 August 2014 14:28, Fabio Estevam feste...@gmail.com wrote:
Hi Magnus,
On Mon, Aug 4, 2014 at 5:23 PM, Magnus Lilja lilja.mag...@gmail.com wrote:
I have now done some tests on i.MX31 PDK:
* v2013.04 and v2014.04 works
* v2014.07 and
On Wed, Aug 13, 2014 at 09:20:40AM -0300, Fabio Estevam wrote:
Hi Stefano,
On Wed, Aug 13, 2014 at 4:28 AM, Stefano Babic sba...@denx.de wrote:
Hi Fabio,
On 12/08/2014 22:29, Fabio Estevam wrote:
From: Fabio Estevam fabio.este...@freescale.com
Currently I don't have access to a
Hi Nikita,
Several comments below in addition to Simon's.
On 08/11/14 19:22, Nikita Kiryanov wrote:
Add initial support for Compulab CM-FX6 CoM.
Support includes MMC, SPI flash, and SPL with dynamic DRAM detection.
Cc: Igor Grinberg grinb...@compulab.co.il
Cc: Stefano Babic sba...@denx.de
On 08/10/14 20:12, Nikita Kiryanov wrote:
Add ethernet support for Compulab CM-FX6 CoM
Cc: Igor Grinberg grinb...@compulab.co.il
Cc: Stefano Babic sba...@denx.de
Cc: Tom Rini tr...@ti.com
Signed-off-by: Nikita Kiryanov nik...@compulab.co.il
Acked-by: Igor Grinberg grinb...@compulab.co.il
On 08/10/14 20:12, Nikita Kiryanov wrote:
Add USB and USB OTG host support for Compulab CM-FX6 CoM.
Cc: Igor Grinberg grinb...@compulab.co.il
Cc: Stefano Babic sba...@denx.de
Cc: Tom Rini tr...@ti.com
Signed-off-by: Nikita Kiryanov nik...@compulab.co.il
---
Changes in V2:
- No
On 08/10/14 20:12, Nikita Kiryanov wrote:
Add NAND support for Compulab CM-FX6 CoM.
Cc: Igor Grinberg grinb...@compulab.co.il
Cc: Stefano Babic sba...@denx.de
Cc: Tom Rini tr...@ti.com
Signed-off-by: Nikita Kiryanov nik...@compulab.co.il
Acked-by: Igor Grinberg grinb...@compulab.co.il
--
The following changes since commit 5b7d0027c2463101dabf337a7cccd768fc20b85e:
Merge branch 'master' of git://git.denx.de/u-boot-blackfin
(2014-08-12 16:54:55 -0400)
are available in the git repository at:
http://git.denx.de/u-boot-x86.git
for you to fetch changes up to
On Wed, Aug 13, 2014 at 08:46:48AM -0600, Simon Glass wrote:
The following changes since commit 5b7d0027c2463101dabf337a7cccd768fc20b85e:
Merge branch 'master' of git://git.denx.de/u-boot-blackfin
(2014-08-12 16:54:55 -0400)
are available in the git repository at:
On 13 Aug 2014, ste...@agner.ch wrote:
Am 2014-08-13 00:58, schrieb Bill Pringlemeir:
[snip]
+static u32 nfc_read(struct mtd_info *mtd, uint reg)
+{
+struct fsl_nfc *nfc = mtd_to_nfc(mtd);
+
+if (reg == NFC_FLASH_STATUS1 ||
+reg == NFC_FLASH_STATUS2 ||
+
Hi Tom,
On 13 August 2014 09:26, Tom Rini tr...@ti.com wrote:
On Wed, Aug 13, 2014 at 08:46:48AM -0600, Simon Glass wrote:
The following changes since commit 5b7d0027c2463101dabf337a7cccd768fc20b85e:
Merge branch 'master' of git://git.denx.de/u-boot-blackfin
(2014-08-12 16:54:55 -0400)
good morning/afternoon/evening
I have long been aware of my current project's implicit requirement of
building a custom bootloader with repeatable and consistent results, and as
such decided thatI would use U-Boot.
That decision was made months ago however I am still without a bootloader
for my
On 08/13/2014 04:58 AM, S Durga Prasad Paladugu wrote:
Hi,
Does anyone tested by integrating thor functionality with the ci_udc driver
instead of samsung s3c_udc_otg? I am trying to do the same on my zynq board
then the enumeration was successful but not able to download the file using
lthor.
Hello,
i will use CONFIG_PRE_CONSOLE_BUFFER and have some trouble.
myboard.h
#define CONFIG_PRE_CONSOLE_BUFFER
#define CONFIG_PRE_CON_BUF_SZ4096
#ifndef __ASSEMBLY__
extern char preConsoleBuffer[] __attribute__ ((section(.data)));
#define CONFIG_PRE_CON_BUF_ADDR
Hello, A few here may have seen me further up the food chain trying to
learn how to get things working.
I am here asking about video support for the Allwinner A20 soc. If this
is something that will not happen for quite some time, I will leave you
all alone and go off in a corner and sulk.
Am 2014-08-13 17:14, schrieb Bill Pringlemeir:
On 13 Aug 2014, ste...@agner.ch wrote:
Am 2014-08-13 00:58, schrieb Bill Pringlemeir:
[snip]
+static u32 nfc_read(struct mtd_info *mtd, uint reg)
+{
+ struct fsl_nfc *nfc = mtd_to_nfc(mtd);
+
+ if (reg == NFC_FLASH_STATUS1 ||
+
On 08/13/2014 01:17 AM, Valentin Longchamp wrote:
There is the requirement on the chassis's backplane that when the clocks
have been enabled, they then should not disappear.
Resetting the Zarlink clocking chips at unit reset violates this
requirement because the backplane clocks are not
On 08/12/2014 11:24 PM, Hannes Petermaier wrote:
Hi Frank,
Well I've got to say, as a User I'd surely like to learn some new tricks
from
time to time. I believe this new mailing list would be the right place
for it.
What is happening now: my Mailbox gets full of messages, that I barely
DP-DDR is used for DPAA, separated from main memory pool for general
use. It has 32-bit bus width and use a standard DDR4 DIMM (64-bit).
Signed-off-by: York Sun york...@freescale.com
---
Change log:
v2: Fix the controller number in board/freescale/ls2085a/ddr.c.
On 13 Aug 2014, ste...@agner.ch wrote:
Funny is, the size is bigger in the first uninlined case... Maybe GCC
inlined the function only for some calls, I did not checked that...
With if/else
text data bss dec hex filename
2395 2904 0529914b3
Hi Stephen,
Thanks for your reply. I used your patches after 2014.07 and able to test
the DFU successfully using ci_udc,but not thor it looks like that it needs
some patches to work for thor.
Regards,
DP
On Wed, Aug 13, 2014 at 9:38 PM, Stephen Warren swar...@wwwdotorg.org
wrote:
On
Hi all,
The default environment for the wandboard does not specify the speed
for the console. I have an open bug in Fedora[1] I am curious if there
was a particular reason why the speed is not set, or if i should just
send in a patch to change it? I really do not want to carry a patch
around
On Wed, Aug 13, 2014 at 09:31:58AM -0600, Simon Glass wrote:
Hi Tom,
On 13 August 2014 09:26, Tom Rini tr...@ti.com wrote:
On Wed, Aug 13, 2014 at 08:46:48AM -0600, Simon Glass wrote:
The following changes since commit
5b7d0027c2463101dabf337a7cccd768fc20b85e:
Merge branch
On Wed, Aug 13, 2014 at 2:55 PM, Dennis Gilmore den...@ausil.us wrote:
Hi all,
The default environment for the wandboard does not specify the speed
for the console. I have an open bug in Fedora[1] I am curious if there
was a particular reason why the speed is not set, or if i should just
Board specific README file should be moved to board folder.
Signed-off-by: York Sun york...@freescale.com
---
I believe this kind of board specific README should be moved under
board folders. Please correct me if I am wrong.
.../freescale/t4qds/README |0
1 file
On Wed, 13 Aug 2014 15:00:43 -0300
Fabio Estevam feste...@gmail.com wrote:
On Wed, Aug 13, 2014 at 2:55 PM, Dennis Gilmore den...@ausil.us
wrote:
Hi all,
The default environment for the wandboard does not specify the speed
for the console. I have an open bug in Fedora[1] I am curious if
On Wed, Aug 13, 2014 at 3:30 PM, Dennis Gilmore den...@ausil.us wrote:
must have changed recentlyish we are using 2014.04 and it's
console=ttymxc0 im in the process of updating to 2014.10 so i guess
its a non issue anymore
It is the same in 2014.04:
On Wed, 13 Aug 2014 15:33:43 -0300
Fabio Estevam feste...@gmail.com wrote:
On Wed, Aug 13, 2014 at 3:30 PM, Dennis Gilmore den...@ausil.us
wrote:
must have changed recentlyish we are using 2014.04 and it's
console=ttymxc0 im in the process of updating to 2014.10 so i
guess its a non
On Wed, Aug 13, 2014 at 3:42 PM, Dennis Gilmore den...@ausil.us wrote:
check line 112, most boards just use the console variable and not the
way you have it set. in my porting to generic distro configs it seems
that we dropped off the re-configuring of the variable. Ill send in a
patch to
On Wed, 2014-08-13 at 13:20 +0200, Stefan Agner wrote:
IMHO we should use the raw_writel only and hand optimize for functions
which are used often. For the initialization/configuration functions,
there is little value to save some register access.
raw_writel() is itself something that should
On Tue, 2014-08-12 at 18:58 -0400, Bill Pringlemeir wrote:
On 12 Aug 2014, scottw...@freescale.com wrote:
On Tue, 2014-08-12 at 23:13 +0200, Stefan Agner wrote:
Am 2014-08-12 00:33, schrieb Scott Wood:
You should always be using raw I/O accessors. If the intent is to
bypass I/O
On Wed, 2014-08-13 at 17:44 -0400, Bill Pringlemeir wrote:
Regarding can't know in advance, I think that some of the register
values maybe set by the boot rom. This might make more sense for Linux
than U-Boot. However, after the initial configuration, many do need the
'read/modify/write' as
On Tue, 2014-06-03 at 09:05 +0200, Rainer Boschung wrote:
TCR watchdog bit are overwritten when dec interrupt is enabled.
This has been fixed with this patch.
Signed-off-by: Rainer Boschung rainer.bosch...@keymile.com
---
arch/powerpc/cpu/mpc85xx/interrupts.c | 2 +-
1 file changed, 1
On Tue, 2014-06-03 at 09:05 +0200, Rainer Boschung wrote:
For e500mc cores the watchdog timer period has to be set by means of a
6bit value, that defines the bit of the timebase counter used to signal
a watchdog timer exception on its 0 to 1 transition.
The macro used to set the watchdog
On Tue, 2014-06-03 at 09:05 +0200, Rainer Boschung wrote:
Function to inititialize the cpu watchdog added.
Signed-off-by: Rainer Boschung rainer.bosch...@keymile.com
---
arch/powerpc/cpu/mpc85xx/cpu.c | 8
1 file changed, 8 insertions(+)
diff --git
On Tue, 2014-06-03 at 09:05 +0200, Rainer Boschung wrote:
Function to inititialize the cpu watchdog added.
Signed-off-by: Rainer Boschung rainer.bosch...@keymile.com
---
arch/powerpc/cpu/mpc85xx/cpu.c | 8
1 file changed, 8 insertions(+)
diff --git
On Tue, 2014-06-03 at 09:05 +0200, Rainer Boschung wrote:
When CONFIG_WATCHDOG is defined the board initialization just performs
a WATCHDOG_RESET, an initialization of the watchdog is not done.
This has been modified fot the MPC85xx, the board initialization calls
its watchdog initialitzation
Thank you for reply Tom,
Let me ask you some questions.
Can we set kernel's bootargs without re-compiling device tree on arm64
kernel by u-boot?
I mean, I want to set kernel's bootargs by u-boot without re-compiling
device tree.
Is it possible?
2014. 8. 13. 오후 7:39에 Tom Rini tr...@ti.com님이 작성:
This series contain the support for Freescale LS102xA SoC and
LS1021AQDS/TWR board.
The QorIQ LS1 family is built on Layerscape architecture, the
industry's first software-aware, core-agnostic networking
architecture to offer unprecedented efficiency and scale.
Freescale LS102xA is a set of SoCs
From: Wang Huan b18...@freescale.com
The QorIQ LS1 family is built on Layerscape architecture,
the industry's first software-aware, core-agnostic networking
architecture to offer unprecedented efficiency and scale.
Freescale LS102xA is a set of SoCs combines two ARM
Cortex-A7 cores that have
From: Claudiu Manoil claudiu.man...@freescale.com
fsl_enet.h defines the mapping of the usual MII management
registers, which are included in the MDIO register block
common to Freescale ethernet controllers. So it shouldn't
depend on the CPU architecture but it should be actually
part of the arch
Use mb() instead of sync assembly instruction to be
compatible for both ARM and PowerPC.
Signed-off-by: Alison Wang alison.w...@freescale.com
---
Change log:
v3: Use mb() to be compatible for both ARM and PowerPC.
Split from the 0004-arm-ls102xa-Add-etsec-support-for-LS102xA patch.
v2: Add
From: York Sun york...@freescale.com
Reading DDR register should use ddr_in32() for proper endianess.
This patch fixes incorrect waiting time for ARM platforms.
Signed-off-by: York Sun york...@freescale.com
---
Change log:
v3: No change.
v2: No change.
drivers/ddr/fsl/arm_ddr_gen3.c | 2 +-
For LS102xA, the platform is little endian, while esdhc IP is
big endian. So two macros are added, CONFIG_SYS_FSL_ESDHC_LE
and CONFIG_SYS_FSL_ESDHC_BE, to determine the registers'
reading/writing in big or little endian format.
Signed-off-by: Alison Wang alison.w...@freescale.com
---
Change log:
Signed-off-by: Alison Wang alison.w...@freescale.com
---
Change log:
v3: Add I2C 3 support.
v2: No change.
drivers/i2c/mxc_i2c.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c
index c14797c..83a9ffa 100644
---
As extra FPGA settings is needed for MDIO read/write
on LS1021AQDS, private MDIO read/write functions are
created.
Signed-off-by: Alison Wang alison.w...@freescale.com
---
Change log:
v3: Split from the 0004-arm-ls102xa-Add-etsec-support-for-LS102xA patch.
v2: Add private mdio read and write
From: York Sun york...@freescale.com
JEDEC spec allows DRAM vendors to use prime DQ for write leveling. This
is not an issue unless some DQ pins are not connected. If a platform uses
regular DIMMs but with reduced DDR ECC pins, the prime DQ may end up on
those floating pins for the second rank.
For LS102xA, RxBDs and TxBDs are interpreted with little-endian
bytes ordering. The offset for each of eTSECs and MDIOs is
256K bytes.
Signed-off-by: Alison Wang alison.w...@freescale.com
---
Change log:
v3: No change.
v2: Add private mdio read and write support.
drivers/net/tsec.c | 7
From: Claudiu Manoil claudiu.man...@freescale.com
Remove the DMCTRL Tx snooping bits (TDSEN and TBDSEN) as a
workaround for LS1. It has been observed that currently
the Tx stops functioning after a fair amount of Tx traffic
with these settings on. These bits are sticky and once set
they cannot
From: York Sun york...@freescale.com
If less than 8 ECC pins are used for DDR data bus width smaller than 64
bits, the 8-bit ECC code will be transmitted/received across several beats,
and it will be used to check 64-bits of data once 8-bits of ECC are
accumulated.
Signed-off-by: York Sun
From: Wang Huan b18...@freescale.com
This patch is to add basic support for LS1021AQDS board.
For the detail board information, please refer to README.
Signed-off-by: Alison Wang alison.w...@freescale.com
Signed-off-by: Jason Jin jason@freescale.com
Signed-off-by: York Sun
From: Wang Huan b18...@freescale.com
This patch is to add basic support for LS1021ATWR board.
For the detail board information, please refer to README.
Signed-off-by: Chen Lu chen...@freescale.com
Signed-off-by: Yuan Yao yao.y...@freescale.com
Signed-off-by: Alison Wang alison.w...@freescale.com
From: Jingchang Lu jingchang...@freescale.com
Signed-off-by: Jingchang Lu jingchang...@freescale.com
Signed-off-by: Yuan Yao yao.y...@freescale.com
---
Change log:
v3: New file.
drivers/serial/serial_lpuart.c | 122 +
1 file changed, 122 insertions(+)
Signed-off-by: Alison Wang alison.w...@freescale.com
---
Change log:
v3: New file.
board/freescale/common/Makefile | 2 +
board/freescale/common/dcu_sii9022a.c | 153 ++
board/freescale/common/dcu_sii9022a.h | 13 +++
3 files changed, 168 insertions(+)
From: Wang Huan b18...@freescale.com
This patch is to add DCU driver support. DCU also named
2D-ACE(Two Dimensional Animation and Compositing Engine)
is a system master that fetches graphics stored in internal
or external memory and displays them on a TFT LCD panel.
Signed-off-by: Alison Wang
From: Wang Huan b18...@freescale.com
This patch is to add LETECH support for LS1021AQDS/TWR board.
For LETECH, LPUART is used for serial port.
Signed-off-by: Jason Jin jason@freescale.com
Signed-off-by: Yuan Yao yao.y...@freescale.com
Signed-off-by: Alison Wang alison.w...@freescale.com
---
From: Wang Huan b18...@freescale.com
Signed-off-by: Alison Wang alison.w...@freescale.com
---
Change log:
v3: New file.
board/freescale/ls1021atwr/Makefile | 1 +
board/freescale/ls1021atwr/dcu.c| 47 +
board/freescale/ls1021atwr/ls1021atwr.c | 6
Hi,
On 12 August 2014 10:12, Vasili Galka vvv...@gmail.com wrote:
On Sun, Jun 29, 2014 at 6:01 PM, Vasili Galka vvv...@gmail.com wrote:
Hi,
Some of the recent commits on u-boot/master have broken the build of
bf538f-ezkit board. The build was fine for v2014.07-rc3. However, now
there is
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