[U-Boot] [PATCH v3 0/3] exynos config updates
This series rebases my exynos config_distro_*.h patches as requested. Baseline is u-boot.git#master 11ada9225a16 (ahead of current u-boot-samsung). I also included Increase command line buffer size (CONFIG_SYS_CBSIZE) which was previously posted separately. Ian. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3 1/3] exynos: Enable config_distro_defaults.h
From: Ian Campbell ian.campb...@citrix.com ...and remove explicit setting of things which this implies. This is done for all exynos platforms (4 5) so it is added to exynos-common.h I'm mainly interested in CONFIG_CMD_BOOTZ and CONFIG_SUPPORT_RAW_INITRD I have build tested on all exynos platforms (MAKEALL -s exynos), but only boot tested on arndale. Signed-off-by: Ian Campbell ian.campb...@citrix.com Reviewed-by: Simon Glass s...@chromium.org --- include/configs/arndale.h| 2 -- include/configs/exynos-common.h | 13 ++--- include/configs/exynos5-common.h | 11 --- 3 files changed, 2 insertions(+), 24 deletions(-) diff --git a/include/configs/arndale.h b/include/configs/arndale.h index f9ee40f..a87806d 100644 --- a/include/configs/arndale.h +++ b/include/configs/arndale.h @@ -17,8 +17,6 @@ /* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE -#define CONFIG_CMD_EXT2 - /* USB */ #define CONFIG_USB_EHCI #define CONFIG_USB_EHCI_EXYNOS diff --git a/include/configs/exynos-common.h b/include/configs/exynos-common.h index b258cb9..1246305 100644 --- a/include/configs/exynos-common.h +++ b/include/configs/exynos-common.h @@ -30,9 +30,6 @@ #define CONFIG_SKIP_LOWLEVEL_INIT #define CONFIG_BOARD_EARLY_INIT_F -/* Enable fdt support */ -#define CONFIG_OF_LIBFDT - /* Keep L2 Cache Disabled */ #define CONFIG_CMD_CACHE @@ -42,7 +39,6 @@ #define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_CMDLINE_TAG #define CONFIG_INITRD_TAG -#define CONFIG_CMDLINE_EDITING #define CONFIG_ENV_OVERWRITE /* Size of malloc() pool before and after relocation */ @@ -61,7 +57,6 @@ #define CONFIG_EXYNOS_DWMMC #define CONFIG_BOUNCE_BUFFER -#define CONFIG_BOOTDELAY 3 #define CONFIG_ZERO_BOOTDELAY_CHECK /* PWM */ @@ -71,20 +66,14 @@ #include config_cmd_default.h #define CONFIG_CMD_MMC -#define CONFIG_CMD_EXT4 #define CONFIG_CMD_EXT4_WRITE -#define CONFIG_CMD_FAT #define CONFIG_FAT_WRITE #define CONFIG_CMD_FS_GENERIC -#define CONFIG_DOS_PARTITION -#define CONFIG_EFI_PARTITION #define CONFIG_CMD_PART #define CONFIG_PARTITION_UUIDS /* Miscellaneous configurable options */ -#define CONFIG_SYS_LONGHELP/* undef to save memory */ -#define CONFIG_SYS_HUSH_PARSER /* use hush command parser*/ #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ #define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */ #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ @@ -96,4 +85,6 @@ #define CONFIG_SYS_NO_FLASH #undef CONFIG_CMD_IMLS +#include config_distro_defaults.h + #endif /* __CONFIG_H */ diff --git a/include/configs/exynos5-common.h b/include/configs/exynos5-common.h index ba591e7..b03966d 100644 --- a/include/configs/exynos5-common.h +++ b/include/configs/exynos5-common.h @@ -55,9 +55,6 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ EXYNOS_DEVICE_SETTINGS -#define CONFIG_CMD_PING -#define CONFIG_CMD_ELF -#define CONFIG_CMD_NET #define CONFIG_CMD_HASH /* Thermal Management Unit */ @@ -174,12 +171,6 @@ #define CONFIG_ENV_SROM_BANK 1 #endif /*CONFIG_CMD_NET*/ -/* Enable PXE Support */ -#ifdef CONFIG_CMD_NET -#define CONFIG_CMD_PXE -#define CONFIG_MENU -#endif - /* SHA hashing */ #define CONFIG_CMD_HASH #define CONFIG_HASH_VERIFY @@ -189,8 +180,6 @@ /* Enable Time Command */ #define CONFIG_CMD_TIME -#define CONFIG_CMD_BOOTZ - #define CONFIG_CMD_GPIO /* USB boot mode */ -- 2.1.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3 2/3] exynos5: Use config_distro_bootcmd.h
From: Ian Campbell ian.campb...@citrix.com This replaces the existing CONFIG_BOOTCOMMAND for exynos5250 and 5420. exynos4 platforms seem to have existing complex extra env configuration for booting and so are excluded here. Hence the bootcmd.h is added to exynos5-common.h. I have build tested on all exynos platforms (MAKEALL -s exynos), but only boot tested on arndale. Signed-off-by: Ian Campbell ian.campb...@citrix.com Reviewed-by: Simon Glass s...@chromium.org --- include/configs/arndale.h | 3 +++ include/configs/exynos5-common.h| 45 ++--- include/configs/exynos5-dt-common.h | 17 ++ include/configs/exynos5250-common.h | 2 -- include/configs/exynos5420-common.h | 2 -- 5 files changed, 47 insertions(+), 22 deletions(-) diff --git a/include/configs/arndale.h b/include/configs/arndale.h index a87806d..919729d 100644 --- a/include/configs/arndale.h +++ b/include/configs/arndale.h @@ -9,6 +9,9 @@ #ifndef __CONFIG_ARNDALE_H #define __CONFIG_ARNDALE_H +#define EXYNOS_FDTFILE_SETTING \ + fdtfile=exynos5250-arndale.dtb\0 + #include exynos5250-common.h /* SD/MMC configuration */ diff --git a/include/configs/exynos5-common.h b/include/configs/exynos5-common.h index b03966d..8f9b780 100644 --- a/include/configs/exynos5-common.h +++ b/include/configs/exynos5-common.h @@ -47,14 +47,6 @@ #define CONFIG_SYS_CONSOLE_IS_IN_ENV #define CONFIG_CONSOLE_MUX -#define EXYNOS_DEVICE_SETTINGS \ - stdin=serial\0 \ - stdout=serial\0 \ - stderr=serial\0 - -#define CONFIG_EXTRA_ENV_SETTINGS \ - EXYNOS_DEVICE_SETTINGS - #define CONFIG_CMD_HASH /* Thermal Management Unit */ @@ -192,4 +184,41 @@ #define CONFIG_FIT #define CONFIG_FIT_BEST_MATCH + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 1) \ + func(MMC, mmc, 0) \ + func(PXE, pxe, na) \ + func(DHCP, dhcp, na) + +#include config_distro_bootcmd.h + +#ifndef MEM_LAYOUT_ENV_SETTINGS +/* 2GB RAM, bootm size of 256M, load scripts after that */ +#define MEM_LAYOUT_ENV_SETTINGS \ + bootm_size=0x1000\0 \ + kernel_addr_r=0x4200\0 \ + fdt_addr_r=0x4300\0 \ + ramdisk_addr_r=0x4330\0 \ + scriptaddr=0x5000\0 \ + pxefile_addr_r=0x5100\0 +#endif + +#ifndef EXYNOS_DEVICE_SETTINGS +#define EXYNOS_DEVICE_SETTINGS \ + stdin=serial\0 \ + stdout=serial\0 \ + stderr=serial\0 +#endif + +#ifndef EXYNOS_FDTFILE_SETTING +#define EXYNOS_FDTFILE_SETTING +#endif + +#define CONFIG_EXTRA_ENV_SETTINGS \ + EXYNOS_DEVICE_SETTINGS \ + EXYNOS_FDTFILE_SETTING \ + MEM_LAYOUT_ENV_SETTINGS \ + BOOTENV + #endif /* __CONFIG_EXYNOS5_COMMON_H */ diff --git a/include/configs/exynos5-dt-common.h b/include/configs/exynos5-dt-common.h index 66547fa..9cef0b0 100644 --- a/include/configs/exynos5-dt-common.h +++ b/include/configs/exynos5-dt-common.h @@ -9,6 +9,13 @@ #ifndef __CONFIG_EXYNOS5_DT_COMMON_H #define __CONFIG_EXYNOS5_DT_COMMON_H +/* Console configuration */ +#undef EXYNOS_DEVICE_SETTINGS +#define EXYNOS_DEVICE_SETTINGS \ + stdin=serial,cros-ec-keyb\0 \ + stdout=serial,lcd\0 \ + stderr=serial,lcd\0 + #include exynos5-common.h /* PMIC */ @@ -22,14 +29,4 @@ #define CONFIG_CMD_CROS_EC #define CONFIG_KEYBOARD -/* Console configuration */ -#undef EXYNOS_DEVICE_SETTINGS -#define EXYNOS_DEVICE_SETTINGS \ - stdin=serial,cros-ec-keyb\0 \ - stdout=serial,lcd\0 \ - stderr=serial,lcd\0 - -#define CONFIG_EXTRA_ENV_SETTINGS \ - EXYNOS_DEVICE_SETTINGS - #endif diff --git a/include/configs/exynos5250-common.h b/include/configs/exynos5250-common.h index 713614f..a0107e8 100644 --- a/include/configs/exynos5250-common.h +++ b/include/configs/exynos5250-common.h @@ -29,8 +29,6 @@ #define CONFIG_SPL_TEXT_BASE 0x02023400 -#define CONFIG_BOOTCOMMAND mmc read 40007000 451 2000; bootm 40007000 - #define CONFIG_IRAM_STACK 0x0205 #define CONFIG_SYS_INIT_SP_ADDRCONFIG_IRAM_STACK diff --git a/include/configs/exynos5420-common.h b/include/configs/exynos5420-common.h index b0f940c..3cf9f01 100644 --- a/include/configs/exynos5420-common.h +++ b/include/configs/exynos5420-common.h @@ -44,8 +44,6 @@ #define CONFIG_BOARD_REV_GPIO_COUNT2 -#define CONFIG_BOOTCOMMAND mmc read 20007000 451 2000; bootm 20007000 - #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 /* -- 2.1.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3 3/3] exynos: Increase command line buffer size (CONFIG_SYS_CBSIZE)
From: Ian Campbell ian.campb...@citrix.com I was running into this limit with a not overly long PXE append line. Since the PXE code wants to print the resulting command line increase CONFIG_SYS_PBSIZE too. Signed-off-by: Ian Campbell ian.campb...@citrix.com --- v2: Apply to exynos generally since consolidation. --- include/configs/exynos-common.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/configs/exynos-common.h b/include/configs/exynos-common.h index 1246305..1f3ee55 100644 --- a/include/configs/exynos-common.h +++ b/include/configs/exynos-common.h @@ -74,8 +74,8 @@ #define CONFIG_PARTITION_UUIDS /* Miscellaneous configurable options */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */ +#define CONFIG_SYS_CBSIZE 1024/* Console I/O Buffer Size */ +#define CONFIG_SYS_PBSIZE 1024/* Print Buffer Size */ #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ /* Boot Argument Buffer Size */ -- 2.1.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 1/4] x86: Do CPU identification in the early phase
The CPU identification happens in x86_cpu_init_f() and corresponding
fields are saved in the global data for later use.
Signed-off-by: Bin Meng bmeng...@gmail.com
---
Changes for v2:
- Update the patch per review comments from Simon Glass
- cpu_vendor_name() and fill_processor_name() are not static now
arch/x86/cpu/cpu.c | 277 +++--
arch/x86/include/asm/cpu.h | 168 +-
arch/x86/include/asm/global_data.h | 5 +
3 files changed, 402 insertions(+), 48 deletions(-)
diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c
index 6441dde..e3fa21d 100644
--- a/arch/x86/cpu/cpu.c
+++ b/arch/x86/cpu/cpu.c
@@ -13,6 +13,9 @@
* Sysgo Real-Time Solutions, GmbH www.elinos.com
* Alex Zuepke a...@sysgo.de
*
+ * Part of this file is adapted from coreboot
+ * src/arch/x86/lib/cpu.c
+ *
* SPDX-License-Identifier:GPL-2.0+
*/
@@ -27,6 +30,8 @@
#include asm/interrupt.h
#include linux/compiler.h
+DECLARE_GLOBAL_DATA_PTR;
+
/*
* Constructor for a conventional segment GDT (or LDT) entry
* This is a macro so it can be used in initialisers
@@ -43,6 +48,52 @@ struct gdt_ptr {
u32 ptr;
} __packed;
+struct cpu_device_id {
+ unsigned vendor;
+ unsigned device;
+};
+
+struct cpuinfo_x86 {
+uint8_tx86;/* CPU family */
+uint8_tx86_vendor; /* CPU vendor */
+uint8_tx86_model;
+uint8_tx86_mask;
+};
+
+/*
+ * List of cpu vendor strings along with their normalized
+ * id values.
+ */
+static struct {
+ int vendor;
+ const char *name;
+} x86_vendors[] = {
+ { X86_VENDOR_INTEL, GenuineIntel, },
+ { X86_VENDOR_CYRIX, CyrixInstead, },
+ { X86_VENDOR_AMD, AuthenticAMD, },
+ { X86_VENDOR_UMC, UMC UMC UMC , },
+ { X86_VENDOR_NEXGEN,NexGenDriven, },
+ { X86_VENDOR_CENTAUR, CentaurHauls, },
+ { X86_VENDOR_RISE, RiseRiseRise, },
+ { X86_VENDOR_TRANSMETA, GenuineTMx86, },
+ { X86_VENDOR_TRANSMETA, TransmetaCPU, },
+ { X86_VENDOR_NSC, Geode by NSC, },
+ { X86_VENDOR_SIS, SiS SiS SiS , },
+};
+
+static const char *x86_vendor_name[] = {
+ [X86_VENDOR_INTEL] = Intel,
+ [X86_VENDOR_CYRIX] = Cyrix,
+ [X86_VENDOR_AMD] = AMD,
+ [X86_VENDOR_UMC] = UMC,
+ [X86_VENDOR_NEXGEN]= NexGen,
+ [X86_VENDOR_CENTAUR] = Centaur,
+ [X86_VENDOR_RISE] = Rise,
+ [X86_VENDOR_TRANSMETA] = Transmeta,
+ [X86_VENDOR_NSC] = NSC,
+ [X86_VENDOR_SIS] = SiS,
+};
+
static void load_ds(u32 segment)
{
asm volatile(movl %0, %%ds : : r (segment * X86_GDT_ENTRY_SIZE));
@@ -115,6 +166,131 @@ int __weak x86_cleanup_before_linux(void)
return 0;
}
+/*
+ * Cyrix CPUs without cpuid or with cpuid not yet enabled can be detected
+ * by the fact that they preserve the flags across the division of 5/2.
+ * PII and PPro exhibit this behavior too, but they have cpuid available.
+ */
+
+/*
+ * Perform the Cyrix 5/2 test. A Cyrix won't change
+ * the flags, while other 486 chips will.
+ */
+static inline int test_cyrix_52div(void)
+{
+ unsigned int test;
+
+ __asm__ __volatile__(
+sahf\n\t /* clear flags (%eax = 0x0005) */
+div %b2\n\t /* divide 5 by 2 */
+lahf /* store flags into %ah */
+: =a (test)
+: 0 (5), q (2)
+: cc);
+
+ /* AH is 0x02 on Cyrix after the divide.. */
+ return (unsigned char) (test 8) == 0x02;
+}
+
+/*
+ * Detect a NexGen CPU running without BIOS hypercode new enough
+ * to have CPUID. (Thanks to Herbert Oppmann)
+ */
+
+static int deep_magic_nexgen_probe(void)
+{
+ int ret;
+
+ __asm__ __volatile__ (
+ movw$0x, %%ax\n
+ xorw%%dx,%%dx\n
+ movw$2, %%cx\n
+ divw%%cx\n
+ movl$0, %%eax\n
+ jnz 1f\n
+ movl$1, %%eax\n
+ 1:\n
+ : =a (ret) : : cx, dx );
+ return ret;
+}
+
+static bool has_cpuid(void)
+{
+ return flag_is_changeable_p(X86_EFLAGS_ID);
+}
+
+static int build_vendor_name(char *vendor_name)
+{
+ struct cpuid_result result;
+ result = cpuid(0x);
+ unsigned int *name_as_ints = (unsigned int *)vendor_name;
+
+ name_as_ints[0] = result.ebx;
+ name_as_ints[1] = result.edx;
+ name_as_ints[2] = result.ecx;
+
+ return result.eax;
+}
+
+static void identify_cpu(struct cpu_device_id *cpu)
+{
+ char vendor_name[16];
+ int i;
+
+ vendor_name[0] = '\0'; /* Unset */
+
+ /* Find the id and vendor_name */
+ if (!has_cpuid()) {
+ /* Its a 486 if we can modify the AC flag */
+ if
[U-Boot] [PATCH v2 4/4] x86: Save TSC frequency in the global data
Return the saved TSC frequency in get_tbclk_mhz().
Signed-off-by: Bin Meng bmeng...@gmail.com
Acked-by: Simon Glass s...@chromium.org
Tested-by: Simon Glass s...@chromium.org
---
arch/x86/include/asm/global_data.h | 1 +
arch/x86/lib/tsc_timer.c | 4
2 files changed, 5 insertions(+)
diff --git a/arch/x86/include/asm/global_data.h
b/arch/x86/include/asm/global_data.h
index 3e3073a..186b97e 100644
--- a/arch/x86/include/asm/global_data.h
+++ b/arch/x86/include/asm/global_data.h
@@ -21,6 +21,7 @@ struct arch_global_data {
uint64_t tsc_base; /* Initial value returned by rdtsc() */
uint32_t tsc_base_kclocks; /* Initial tsc as a kclocks value */
uint32_t tsc_prev; /* For show_boot_progress() */
+ uint32_t tsc_mhz; /* TSC frequency in MHz */
void *new_fdt; /* Relocated FDT */
uint32_t bist; /* Built-in self test value */
};
diff --git a/arch/x86/lib/tsc_timer.c b/arch/x86/lib/tsc_timer.c
index 8a0abde..b5f0458 100644
--- a/arch/x86/lib/tsc_timer.c
+++ b/arch/x86/lib/tsc_timer.c
@@ -293,6 +293,9 @@ unsigned __attribute__((no_instrument_function)) long
get_tbclk_mhz(void)
{
unsigned long fast_calibrate;
+ if (gd-arch.tsc_mhz)
+ return gd-arch.tsc_mhz;
+
fast_calibrate = try_msr_calibrate_tsc();
if (fast_calibrate)
return fast_calibrate;
@@ -301,6 +304,7 @@ unsigned __attribute__((no_instrument_function)) long
get_tbclk_mhz(void)
if (!fast_calibrate)
panic(TSC frequency is ZERO);
+ gd-arch.tsc_mhz = fast_calibrate;
return fast_calibrate;
}
--
1.8.2.1
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[U-Boot] [PATCH v2 2/4] x86: Do TSC MSR calibration only for known/supported CPUs
Using MSR_PLATFORM_INFO (0xCE) to calibrate TSR will cause #GP on
processors which do not have this MSR. Instead only doing the MSR
calibration for known/supported CPUs.
Signed-off-by: Bin Meng bmeng...@gmail.com
Acked-by: Simon Glass s...@chromium.org
Tested-by: Simon Glass s...@chromium.org
---
arch/x86/lib/tsc_timer.c | 116 ---
1 file changed, 109 insertions(+), 7 deletions(-)
diff --git a/arch/x86/lib/tsc_timer.c b/arch/x86/lib/tsc_timer.c
index 8b38702..fafbbfc 100644
--- a/arch/x86/lib/tsc_timer.c
+++ b/arch/x86/lib/tsc_timer.c
@@ -1,6 +1,9 @@
/*
* Copyright (c) 2012 The Chromium OS Authors.
*
+ * TSC calibration codes are adapted from Linux kernel
+ * arch/x86/kernel/tsc_msr.c and arch/x86/kernel/tsc.c
+ *
* SPDX-License-Identifier:GPL-2.0+
*/
@@ -12,8 +15,108 @@
#include asm/msr.h
#include asm/u-boot-x86.h
+/* CPU reference clock frequency: in KHz */
+#define FREQ_8383200
+#define FREQ_100 99840
+#define FREQ_133 133200
+#define FREQ_166 166400
+
+#define MAX_NUM_FREQS 8
+
DECLARE_GLOBAL_DATA_PTR;
+/*
+ * According to Intel 64 and IA-32 System Programming Guide,
+ * if MSR_PERF_STAT[31] is set, the maximum resolved bus ratio can be
+ * read in MSR_PLATFORM_ID[12:8], otherwise in MSR_PERF_STAT[44:40].
+ * Unfortunately some Intel Atom SoCs aren't quite compliant to this,
+ * so we need manually differentiate SoC families. This is what the
+ * field msr_plat does.
+ */
+struct freq_desc {
+ u8 x86_family; /* CPU family */
+ u8 x86_model; /* model */
+ u8 msr_plat;/* 1: use MSR_PLATFORM_INFO, 0: MSR_IA32_PERF_STATUS */
+ u32 freqs[MAX_NUM_FREQS];
+};
+
+static struct freq_desc freq_desc_tables[] = {
+ /* PNW */
+ { 6, 0x27, 0, { 0, 0, 0, 0, 0, FREQ_100, 0, FREQ_83 } },
+ /* CLV+ */
+ { 6, 0x35, 0, { 0, FREQ_133, 0, 0, 0, FREQ_100, 0, FREQ_83 } },
+ /* TNG */
+ { 6, 0x4a, 1, { 0, FREQ_100, FREQ_133, 0, 0, 0, 0, 0 } },
+ /* VLV2 */
+ { 6, 0x37, 1, { FREQ_83, FREQ_100, FREQ_133, FREQ_166, 0, 0, 0, 0 } },
+ /* ANN */
+ { 6, 0x5a, 1, { FREQ_83, FREQ_100, FREQ_133, FREQ_100, 0, 0, 0, 0 } },
+};
+
+static int match_cpu(u8 family, u8 model)
+{
+ int i;
+
+ for (i = 0; i ARRAY_SIZE(freq_desc_tables); i++) {
+ if ((family == freq_desc_tables[i].x86_family)
+ (model == freq_desc_tables[i].x86_model))
+ return i;
+ }
+
+ return -1;
+}
+
+/* Map CPU reference clock freq ID(0-7) to CPU reference clock freq(KHz) */
+#define id_to_freq(cpu_index, freq_id) \
+ (freq_desc_tables[cpu_index].freqs[freq_id])
+
+/*
+ * Do MSR calibration only for known/supported CPUs.
+ *
+ * Returns the calibration value or 0 if MSR calibration failed.
+ */
+static unsigned long try_msr_calibrate_tsc(void)
+{
+ u32 lo, hi, ratio, freq_id, freq;
+ unsigned long res;
+ int cpu_index;
+
+ cpu_index = match_cpu(gd-arch.x86, gd-arch.x86_model);
+ if (cpu_index 0)
+ return 0;
+
+ if (freq_desc_tables[cpu_index].msr_plat) {
+ rdmsr(MSR_PLATFORM_INFO, lo, hi);
+ ratio = (lo 8) 0x1f;
+ } else {
+ rdmsr(MSR_IA32_PERF_STATUS, lo, hi);
+ ratio = (hi 8) 0x1f;
+ }
+ debug(Maximum core-clock to bus-clock ratio: 0x%x\n, ratio);
+
+ if (!ratio)
+ goto fail;
+
+ /* Get FSB FREQ ID */
+ rdmsr(MSR_FSB_FREQ, lo, hi);
+ freq_id = lo 0x7;
+ freq = id_to_freq(cpu_index, freq_id);
+ debug(Resolved frequency ID: %u, frequency: %u KHz\n,
+ freq_id, freq);
+ if (!freq)
+ goto fail;
+
+ /* TSC frequency = maximum resolved freq * maximum resolved bus ratio */
+ res = freq * ratio / 1000;
+ debug(TSC runs at %lu MHz\n, res);
+
+ return res;
+
+fail:
+ debug(Fast TSC calibration using MSR failed\n);
+ return 0;
+}
+
void timer_set_base(u64 base)
{
gd-arch.tsc_base = base;
@@ -34,17 +137,16 @@ u64 __attribute__((no_instrument_function)) get_ticks(void)
return now_tick - gd-arch.tsc_base;
}
-#define PLATFORM_INFO_MSR 0xce
-
/* Get the speed of the TSC timer in MHz */
unsigned __attribute__((no_instrument_function)) long get_tbclk_mhz(void)
{
- u32 ratio;
- u64 platform_info = native_read_msr(PLATFORM_INFO_MSR);
+ unsigned long fast_calibrate;
+
+ fast_calibrate = try_msr_calibrate_tsc();
+ if (!fast_calibrate)
+ panic(TSC frequency is ZERO);
- /* 100MHz times Max Non Turbo ratio */
- ratio = (platform_info 8) 0xff;
- return 100 * ratio;
+ return fast_calibrate;
}
unsigned long get_tbclk(void)
--
1.8.2.1
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[U-Boot] [PATCH v2 3/4] x86: Add quick TSC calibration via PIT
Use the same way that Linux does for quick TSC calibration via PIT
when calibration via MSR fails.
Signed-off-by: Bin Meng bmeng...@gmail.com
Acked-by: Simon Glass s...@chromium.org
---
arch/x86/include/asm/i8254.h | 3 +
arch/x86/lib/tsc_timer.c | 155 +++
2 files changed, 158 insertions(+)
diff --git a/arch/x86/include/asm/i8254.h b/arch/x86/include/asm/i8254.h
index c3ccd4f..4116de1 100644
--- a/arch/x86/include/asm/i8254.h
+++ b/arch/x86/include/asm/i8254.h
@@ -36,4 +36,7 @@
#define PIT_CMD_MODE4 0x08/* Select mode 4 */
#define PIT_CMD_MODE5 0x0A/* Select mode 5 */
+/* The clock frequency of the i8253/i8254 PIT */
+#define PIT_TICK_RATE 1193182ul
+
#endif
diff --git a/arch/x86/lib/tsc_timer.c b/arch/x86/lib/tsc_timer.c
index fafbbfc..8a0abde 100644
--- a/arch/x86/lib/tsc_timer.c
+++ b/arch/x86/lib/tsc_timer.c
@@ -117,6 +117,157 @@ fail:
return 0;
}
+/*
+ * This reads the current MSB of the PIT counter, and
+ * checks if we are running on sufficiently fast and
+ * non-virtualized hardware.
+ *
+ * Our expectations are:
+ *
+ * - the PIT is running at roughly 1.19MHz
+ *
+ * - each IO is going to take about 1us on real hardware,
+ *but we allow it to be much faster (by a factor of 10) or
+ *_slightly_ slower (ie we allow up to a 2us read+counter
+ *update - anything else implies a unacceptably slow CPU
+ *or PIT for the fast calibration to work.
+ *
+ * - with 256 PIT ticks to read the value, we have 214us to
+ *see the same MSB (and overhead like doing a single TSC
+ *read per MSB value etc).
+ *
+ * - We're doing 2 reads per loop (LSB, MSB), and we expect
+ *them each to take about a microsecond on real hardware.
+ *So we expect a count value of around 100. But we'll be
+ *generous, and accept anything over 50.
+ *
+ * - if the PIT is stuck, and we see *many* more reads, we
+ *return early (and the next caller of pit_expect_msb()
+ *then consider it a failure when they don't see the
+ *next expected value).
+ *
+ * These expectations mean that we know that we have seen the
+ * transition from one expected value to another with a fairly
+ * high accuracy, and we didn't miss any events. We can thus
+ * use the TSC value at the transitions to calculate a pretty
+ * good value for the TSC frequencty.
+ */
+static inline int pit_verify_msb(unsigned char val)
+{
+ /* Ignore LSB */
+ inb(0x42);
+ return inb(0x42) == val;
+}
+
+static inline int pit_expect_msb(unsigned char val, u64 *tscp, unsigned long
*deltap)
+{
+ int count;
+ u64 tsc = 0, prev_tsc = 0;
+
+ for (count = 0; count 5; count++) {
+ if (!pit_verify_msb(val))
+ break;
+ prev_tsc = tsc;
+ tsc = rdtsc();
+ }
+ *deltap = rdtsc() - prev_tsc;
+ *tscp = tsc;
+
+ /*
+* We require _some_ success, but the quality control
+* will be based on the error terms on the TSC values.
+*/
+ return count 5;
+}
+
+/*
+ * How many MSB values do we want to see? We aim for
+ * a maximum error rate of 500ppm (in practice the
+ * real error is much smaller), but refuse to spend
+ * more than 50ms on it.
+ */
+#define MAX_QUICK_PIT_MS 50
+#define MAX_QUICK_PIT_ITERATIONS (MAX_QUICK_PIT_MS * PIT_TICK_RATE / 1000 /
256)
+
+static unsigned long quick_pit_calibrate(void)
+{
+ int i;
+ u64 tsc, delta;
+ unsigned long d1, d2;
+
+ /* Set the Gate high, disable speaker */
+ outb((inb(0x61) ~0x02) | 0x01, 0x61);
+
+ /*
+* Counter 2, mode 0 (one-shot), binary count
+*
+* NOTE! Mode 2 decrements by two (and then the
+* output is flipped each time, giving the same
+* final output frequency as a decrement-by-one),
+* so mode 0 is much better when looking at the
+* individual counts.
+*/
+ outb(0xb0, 0x43);
+
+ /* Start at 0x */
+ outb(0xff, 0x42);
+ outb(0xff, 0x42);
+
+ /*
+* The PIT starts counting at the next edge, so we
+* need to delay for a microsecond. The easiest way
+* to do that is to just read back the 16-bit counter
+* once from the PIT.
+*/
+ pit_verify_msb(0);
+
+ if (pit_expect_msb(0xff, tsc, d1)) {
+ for (i = 1; i = MAX_QUICK_PIT_ITERATIONS; i++) {
+ if (!pit_expect_msb(0xff-i, delta, d2))
+ break;
+
+ /*
+* Iterate until the error is less than 500 ppm
+*/
+ delta -= tsc;
+ if (d1+d2 = delta 11)
+ continue;
+
+ /*
+* Check the PIT one more time to verify that
+* all TSC reads were stable wrt the PIT.
+
[U-Boot] [PATCH 1/7] imx6: add macro define inclusion
add a macro define inclusion to compile the function. iMX6SL doesn't have an MMDC_P1_BASE_ADDR in the header. It will break the build if the SPL features is enabled for iMX6SL. --- arch/arm/cpu/armv7/mx6/ddr.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/cpu/armv7/mx6/ddr.c b/arch/arm/cpu/armv7/mx6/ddr.c index 7a9b03a..3beeded 100644 --- a/arch/arm/cpu/armv7/mx6/ddr.c +++ b/arch/arm/cpu/armv7/mx6/ddr.c @@ -182,6 +182,7 @@ void mx6sdl_dram_iocfg(unsigned width, * For details on each register, refer to the IMX6DQRM and/or IMX6SDLRM * section titled MMDC initialization */ +#if defined(CONFIG_MX6QDL) || defined(CONFIG_MX6Q) || defined(CONFIG_MX6D) #define MR(val, ba, cmd, cs1) \ ((val 16) | (1 15) | (cmd 4) | (cs1 3) | ba) void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo, @@ -489,3 +490,4 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo, /* wait for auto-ZQ calibration to complete */ mdelay(1); } +#endif -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 0/7] *** iMX6SL-evk SPL Support ***
This patch is for SPL support for iMX6SL-evk. The said patches has been tested to work on SD1, SD2 and SD3 ports of the said board. After applying the following patches, it will produces SPL and u-boot.img binary images. You should run the two commands below to store it in your SD or eMMC. sudo dd if=SPL of=/dev/xxx bs=1K seek=1; sync sudo dd if=u-boot.img of=/dev/xxx bs=1K seek=69 John Tobias (7): imx6: add macro define inclusion imx6sl: update DCD configuration file imx6sl: add spl on board configuration imx6: add additional flexibility for defining macros imx6sl: add spl in include header file imx6sl: add SPL support for iMX6SL-evk kconfig: imx6sl: add add SUPPORT_SPL arch/arm/Kconfig | 1 + arch/arm/cpu/armv7/mx6/ddr.c | 2 + board/freescale/mx6slevk/imximage.cfg | 78 +--- board/freescale/mx6slevk/mx6slevk.c | 168 +- configs/mx6slevk_defconfig| 5 +- include/configs/imx6_spl.h| 6 ++ include/configs/mx6slevk.h| 8 ++ 7 files changed, 191 insertions(+), 77 deletions(-) -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 3/7] imx6sl: add spl on board configuration
add spl on build configuration for iMX6SL --- configs/mx6slevk_defconfig | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/configs/mx6slevk_defconfig b/configs/mx6slevk_defconfig index fb8c4de..dfdf54f 100644 --- a/configs/mx6slevk_defconfig +++ b/configs/mx6slevk_defconfig @@ -1,3 +1,4 @@ +CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS=IMX_CONFIG=board/freescale/mx6slevk/imximage.cfg,MX6SL -CONFIG_ARM=y -CONFIG_TARGET_MX6SLEVK=y ++S:CONFIG_ARM=y ++S:CONFIG_TARGET_MX6SLEVK=y -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 2/7] imx6sl: update DCD configuration file
Update the Device Configuration Data file for iMX6SL for SPL support. --- board/freescale/mx6slevk/imximage.cfg | 78 ++- 1 file changed, 4 insertions(+), 74 deletions(-) diff --git a/board/freescale/mx6slevk/imximage.cfg b/board/freescale/mx6slevk/imximage.cfg index 16ea597..3ebd985 100644 --- a/board/freescale/mx6slevk/imximage.cfg +++ b/board/freescale/mx6slevk/imximage.cfg @@ -1,7 +1,10 @@ /* * Copyright (C) 2013 Freescale Semiconductor, Inc. * - * SPDX-License-Identifier:GPL-2.0+ + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License or (at your option) any later version. * * Refer docs/README.imxmage for more details about how-to configure * and create imximage boot image @@ -40,76 +43,3 @@ DATA 4 0x020c4074 0x DATA 4 0x020c4078 0x DATA 4 0x020c407c 0x DATA 4 0x020c4080 0x - -DATA 4 0x020e0344 0x3030 -DATA 4 0x020e0348 0x3030 -DATA 4 0x020e034c 0x3030 -DATA 4 0x020e0350 0x3030 -DATA 4 0x020e030c 0x0030 -DATA 4 0x020e0310 0x0030 -DATA 4 0x020e0314 0x0030 -DATA 4 0x020e0318 0x0030 -DATA 4 0x020e0300 0x0030 -DATA 4 0x020e031c 0x0030 -DATA 4 0x020e0338 0x0028 -DATA 4 0x020e0320 0x0030 -DATA 4 0x020e032c 0x -DATA 4 0x020e033c 0x0008 -DATA 4 0x020e0340 0x0008 -DATA 4 0x020e05c4 0x0030 -DATA 4 0x020e05cc 0x0030 -DATA 4 0x020e05d4 0x0030 -DATA 4 0x020e05d8 0x0030 -DATA 4 0x020e05ac 0x0030 -DATA 4 0x020e05c8 0x0030 -DATA 4 0x020e05b0 0x0002 -DATA 4 0x020e05b4 0x -DATA 4 0x020e05c0 0x0002 -DATA 4 0x020e05d0 0x0008 - -DATA 4 0x021b001c 0x8000 -DATA 4 0x021b085c 0x1b4700c7 -DATA 4 0x021b0800 0xa1390003 -DATA 4 0x021b0890 0x0030 -DATA 4 0x021b08b8 0x0800 -DATA 4 0x021b081c 0x -DATA 4 0x021b0820 0x -DATA 4 0x021b0824 0x -DATA 4 0x021b0828 0x -DATA 4 0x021b082c 0xf333 -DATA 4 0x021b0830 0xf333 -DATA 4 0x021b0834 0xf333 -DATA 4 0x021b0838 0xf333 -DATA 4 0x021b0848 0x4241444a -DATA 4 0x021b0850 0x3030312b -DATA 4 0x021b083c 0x2000 -DATA 4 0x021b0840 0x -DATA 4 0x021b08c0 0x24911492 -DATA 4 0x021b08b8 0x0800 -DATA 4 0x021b000c 0x33374133 -DATA 4 0x021b0004 0x00020024 -DATA 4 0x021b0010 0x00100A82 -DATA 4 0x021b0014 0x0093 -DATA 4 0x021b0018 0x1688 -DATA 4 0x021b002c 0x0f9f26d2 -DATA 4 0x021b0030 0x020e -DATA 4 0x021b0038 0x00190778 -DATA 4 0x021b0008 0x -DATA 4 0x021b0040 0x004f -DATA 4 0x021b 0xc311 -DATA 4 0x021b001c 0x003f8030 -DATA 4 0x021b001c 0xff0a8030 -DATA 4 0x021b001c 0x82018030 -DATA 4 0x021b001c 0x04028030 -DATA 4 0x021b001c 0x02038030 -DATA 4 0x021b001c 0xff0a8038 -DATA 4 0x021b001c 0x82018038 -DATA 4 0x021b001c 0x04028038 -DATA 4 0x021b001c 0x02038038 -DATA 4 0x021b0800 0xa1310003 -DATA 4 0x021b0020 0x1800 -DATA 4 0x021b0818 0x -DATA 4 0x021b08b8 0x0800 -DATA 4 0x021b0004 0x00025564 -DATA 4 0x021b0404 0x00011006 -DATA 4 0x021b001c 0x -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 6/7] imx6sl: add SPL support for iMX6SL-evk
This patch support the SPL features for iMX6SL.
It tested to boot on SD1, SD2 and SD3 mmc ports.
---
board/freescale/mx6slevk/mx6slevk.c | 168 +++-
1 file changed, 167 insertions(+), 1 deletion(-)
diff --git a/board/freescale/mx6slevk/mx6slevk.c
b/board/freescale/mx6slevk/mx6slevk.c
index e76c343..2c11c4a 100644
--- a/board/freescale/mx6slevk/mx6slevk.c
+++ b/board/freescale/mx6slevk/mx6slevk.c
@@ -42,7 +42,7 @@ DECLARE_GLOBAL_DATA_PTR;
int dram_init(void)
{
- gd-ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
+ gd-ram_size = imx_ddr_size();
return 0;
}
@@ -275,3 +275,169 @@ int checkboard(void)
return 0;
}
+
+#ifdef CONFIG_SPL_BUILD
+#include spl.h
+#include libfdt.h
+
+#define BOOT_CFG 0x20D8004
+#define __REG(x)(*((volatile u32 *)(x)))
+
+struct fsl_esdhc_cfg spl_usdhc_cfg;
+/*
+ * Got it from imximage.cfg file
+ */
+static void spl_dram_mx6slevk(void)
+{
+ __REG(0x020e0344) = 0x3030;
+ __REG(0x020e0348) = 0x3030;
+ __REG(0x020e034c) = 0x3030;
+ __REG(0x020e0350) = 0x3030;
+ __REG(0x020e030c) = 0x0030;
+ __REG(0x020e0310) = 0x0030;
+ __REG(0x020e0314) = 0x0030;
+ __REG(0x020e0318) = 0x0030;
+ __REG(0x020e0300) = 0x0030;
+ __REG(0x020e031c) = 0x0030;
+ __REG(0x020e0338) = 0x0028;
+ __REG(0x020e0320) = 0x0030;
+ __REG(0x020e032c) = 0x;
+ __REG(0x020e033c) = 0x0008;
+ __REG(0x020e0340) = 0x0008;
+ __REG(0x020e05c4) = 0x0030;
+ __REG(0x020e05cc) = 0x0030;
+ __REG(0x020e05d4) = 0x0030;
+ __REG(0x020e05d8) = 0x0030;
+ __REG(0x020e05ac) = 0x0030;
+ __REG(0x020e05c8) = 0x0030;
+ __REG(0x020e05b0) = 0x0002;
+ __REG(0x020e05b4) = 0x;
+ __REG(0x020e05c0) = 0x0002;
+ __REG(0x020e05d0) = 0x0008;
+
+ __REG(0x021b001c) = 0x8000;
+ __REG(0x021b085c) = 0x1b4700c7;
+ __REG(0x021b0800) = 0xa1390003;
+ __REG(0x021b0890) = 0x0030;
+ __REG(0x021b08b8) = 0x0800;
+ __REG(0x021b081c) = 0x;
+ __REG(0x021b0820) = 0x;
+ __REG(0x021b0824) = 0x;
+ __REG(0x021b0828) = 0x;
+ __REG(0x021b082c) = 0xf333;
+ __REG(0x021b0830) = 0xf333;
+ __REG(0x021b0834) = 0xf333;
+ __REG(0x021b0838) = 0xf333;
+ __REG(0x021b0848) = 0x4241444a;
+ __REG(0x021b0850) = 0x3030312b;
+ __REG(0x021b083c) = 0x2000;
+ __REG(0x021b0840) = 0x;
+ __REG(0x021b08c0) = 0x24911492;
+ __REG(0x021b08b8) = 0x0800;
+ __REG(0x021b000c) = 0x33374133;
+ __REG(0x021b0004) = 0x00020024;
+ __REG(0x021b0010) = 0x00100A82;
+ __REG(0x021b0014) = 0x0093;
+ __REG(0x021b0018) = 0x1688;
+ __REG(0x021b002c) = 0x0f9f26d2;
+ __REG(0x021b0030) = 0x020e;
+ __REG(0x021b0038) = 0x00190778;
+ __REG(0x021b0008) = 0x;
+ __REG(0x021b0040) = 0x004f;
+ __REG(0x021b) = 0xc311;
+ __REG(0x021b001c) = 0x003f8030;
+ __REG(0x021b001c) = 0xff0a8030;
+ __REG(0x021b001c) = 0x82018030;
+ __REG(0x021b001c) = 0x04028030;
+ __REG(0x021b001c) = 0x02038030;
+ __REG(0x021b001c) = 0xff0a8038;
+ __REG(0x021b001c) = 0x82018038;
+ __REG(0x021b001c) = 0x04028038;
+ __REG(0x021b001c) = 0x02038038;
+ __REG(0x021b0800) = 0xa1310003;
+ __REG(0x021b0020) = 0x1800;
+ __REG(0x021b0818) = 0x;
+ __REG(0x021b08b8) = 0x0800;
+ __REG(0x021b0004) = 0x00025564;
+ __REG(0x021b0404) = 0x00011006;
+ __REG(0x021b001c) = 0x;
+}
+
+/*
+ * This section require the differentiation
+ * between iMX6 SL.
+ * But for now, it will configure only for
+ * iMX6SL-evk.
+ */
+static void spl_dram_init(void)
+{
+ spl_dram_mx6slevk();
+}
+
+int spl_board_mmc_init(bd_t *bis)
+{
+ unsigned reg = readl(BOOT_CFG) 11;
+ /*
+* Upon reading BOOT_CFG register the following map is done:
+* Bit 11 and 12 of BOOT_CFG register can determine the current
+* mmc port
+* 0x0 SD1
+* 0x1 SD2
+* 0x2 SD3
+*/
+
+ switch (reg 0x3) {
+ case 0x0:
+ imx_iomux_v3_setup_multiple_pads(
+ usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
+ spl_usdhc_cfg.esdhc_base = USDHC1_BASE_ADDR;
+ spl_usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+ gd-arch.sdhc_clk = spl_usdhc_cfg.sdhc_clk;
+ break;
+ case 0x1:
+ imx_iomux_v3_setup_multiple_pads(
+ usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
+ spl_usdhc_cfg.esdhc_base = USDHC2_BASE_ADDR;
+
[U-Boot] [PATCH 4/7] imx6: add additional flexibility for defining macros
iMX6SL has a different address value for the following: CONFIG_SPL_BSS_START_ADDR CONFIG_SYS_SPL_MALLOC_START --- include/configs/imx6_spl.h | 6 ++ 1 file changed, 6 insertions(+) diff --git a/include/configs/imx6_spl.h b/include/configs/imx6_spl.h index 4ff37b3..61233c4 100644 --- a/include/configs/imx6_spl.h +++ b/include/configs/imx6_spl.h @@ -64,10 +64,16 @@ #define CONFIG_SPL_LIBDISK_SUPPORT #endif +#ifndef CONFIG_SPL_BSS_START_ADDR #define CONFIG_SPL_BSS_START_ADDR 0x1820 +#endif #define CONFIG_SPL_BSS_MAX_SIZE0x10/* 1 MB */ +#ifndef CONFIG_SYS_SPL_MALLOC_START #define CONFIG_SYS_SPL_MALLOC_START0x1830 +#endif +#ifndef CONFIG_SYS_SPL_MALLOC_SIZE #define CONFIG_SYS_SPL_MALLOC_SIZE 0x320 /* 50 MB */ +#endif #ifndef CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_TEXT_BASE 0x1780 #endif -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 7/7] kconfig: imx6sl: add add SUPPORT_SPL
enable SUPPORT_SPL by default for iMX6SL-evk --- arch/arm/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index ab0d284..40a3604 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -614,6 +614,7 @@ config TARGET_MX6SABRESD config TARGET_MX6SLEVK bool Support mx6slevk select CPU_V7 + select SUPPORT_SPL config TARGET_MX6SXSABRESD bool Support mx6sxsabresd -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 5/7] imx6sl: add spl in include header file
add the SPL macros in include header file for iMX6SL --- include/configs/mx6slevk.h | 8 1 file changed, 8 insertions(+) diff --git a/include/configs/mx6slevk.h b/include/configs/mx6slevk.h index 4fcaf51..afbb81d 100644 --- a/include/configs/mx6slevk.h +++ b/include/configs/mx6slevk.h @@ -14,6 +14,14 @@ #include linux/sizes.h #include mx6_common.h +#ifdef CONFIG_SPL +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SPL_BSS_START_ADDR 0x8200 +#define CONFIG_SYS_SPL_MALLOC_START0x8300 +#include imx6_spl.h +#endif + #define CONFIG_MX6 #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3 7/8] imx6: SPL support for iMX6 SabreSD
Hi John,
On 08/11/2014 22:27, John Tobias wrote:
This patch will enable the support for SPL on iMX6 SabreSD.
It tested on SD2 and SD3 mmc port.
---
board/freescale/mx6sabresd/mx6sabresd.c | 211
+++-
1 file changed, 209 insertions(+), 2 deletions(-)
diff --git a/board/freescale/mx6sabresd/mx6sabresd.c
b/board/freescale/mx6sabresd/mx6sabresd.c
index 3d81fff..f443337 100644
--- a/board/freescale/mx6sabresd/mx6sabresd.c
+++ b/board/freescale/mx6sabresd/mx6sabresd.c
@@ -55,8 +55,7 @@ DECLARE_GLOBAL_DATA_PTR;
int dram_init(void)
{
- gd-ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
-
+ gd-ram_size = imx_ddr_size();
return 0;
}
@@ -607,3 +606,211 @@ int checkboard(void)
puts(Board: MX6-SabreSD\n);
return 0;
}
+
+#ifdef CONFIG_SPL_BUILD
+#include spl.h
+#include libfdt.h
+
+#define BOOT_CFG 0x20D8004
+#define __REG(x)(*((volatile u32 *)(x)))
+
+struct fsl_esdhc_cfg spl_usdhc_cfg;
+/*
+ * Got it from mx6q_4x_mt41j128.cfg file
+ */
+void set_mt41j128_ddr(void)
+{
+ __REG(0x020e05a8) = 0x0028;
+ __REG(0x020e05b0) = 0x0028;
+ __REG(0x020e0524) = 0x0028;
+ __REG(0x020e051c) = 0x0028;
+
+ __REG(0x020e0518) = 0x0028;
+ __REG(0x020e050c) = 0x0028;
+ __REG(0x020e05b8) = 0x0028;
+ __REG(0x020e05c0) = 0x0028;
+
+ __REG(0x020e05ac) = 0x0028;
+ __REG(0x020e05b4) = 0x0028;
+ __REG(0x020e0528) = 0x0028;
+ __REG(0x020e0520) = 0x0028;
+
+ __REG(0x020e0514) = 0x0028;
+ __REG(0x020e0510) = 0x0028;
+ __REG(0x020e05bc) = 0x0028;
+ __REG(0x020e05c4) = 0x0028;
+
+ __REG(0x020e056c) = 0x0030;
+ __REG(0x020e0578) = 0x0030;
+ __REG(0x020e0588) = 0x0030;
+ __REG(0x020e0594) = 0x0030;
+
+ __REG(0x020e057c) = 0x0030;
+ __REG(0x020e0590) = 0x0030;
+ __REG(0x020e0598) = 0x0030;
+ __REG(0x020e058c) = 0x;
+
+ __REG(0x020e059c) = 0x3030;
+ __REG(0x020e05a0) = 0x3030;
+ __REG(0x020e0784) = 0x0028;
+ __REG(0x020e0788) = 0x0028;
+
+ __REG(0x020e0794) = 0x0028;
+ __REG(0x020e079c) = 0x0028;
+ __REG(0x020e07a0) = 0x0028;
+ __REG(0x020e07a4) = 0x0028;
+
+ __REG(0x020e07a8) = 0x0028;
+ __REG(0x020e0748) = 0x0028;
+ __REG(0x020e074c) = 0x0030;
+ __REG(0x020e0750) = 0x0002;
+
+ __REG(0x020e0758) = 0x;
+ __REG(0x020e0774) = 0x0002;
+ __REG(0x020e078c) = 0x0030;
+ __REG(0x020e0798) = 0x000C;
+
+ __REG(0x021b081c) = 0x;
+ __REG(0x021b0820) = 0x;
+ __REG(0x021b0824) = 0x;
+ __REG(0x021b0828) = 0x;
+
+ __REG(0x021b481c) = 0x;
+ __REG(0x021b4820) = 0x;
+ __REG(0x021b4824) = 0x;
+ __REG(0x021b4828) = 0x;
+
+ __REG(0x021b0018) = 0x1740;
+
+ __REG(0x021b001c) = 0x8000;
+ __REG(0x021b000c) = 0x8A8F7975;
+ __REG(0x021b0010) = 0xFF538E64;
+ __REG(0x021b0014) = 0x01FF00DB;
+ __REG(0x021b002c) = 0x26D2;
+
+ __REG(0x021b0030) = 0x008F0E21;
+ __REG(0x021b0008) = 0x09444040;
+ __REG(0x021b0004) = 0x00020036;
+ __REG(0x021b0040) = 0x0047;
+ __REG(0x021b) = 0x841A;
+
+ __REG(0x021b001c) = 0x04088032;
+ __REG(0x021b001c) = 0x8033;
+ __REG(0x021b001c) = 0x00428031;
+ __REG(0x021b001c) = 0x09408030;
+
+ __REG(0x021b001c) = 0x04008040;
+ __REG(0x021b0800) = 0xA1380003;
+ __REG(0x021b0020) = 0x5800;
+ __REG(0x021b0818) = 0x0007;
+ __REG(0x021b4818) = 0x0007;
+
+ /* Calibration values based on ARD and 528MHz */
+ __REG(0x021b083c) = 0x434B0358;
+ __REG(0x021b0840) = 0x033D033C;
+ __REG(0x021b483c) = 0x03520362;
+ __REG(0x021b4840) = 0x03480318;
+ __REG(0x021b0848) = 0x41383A3C;
+ __REG(0x021b4848) = 0x3F3C374A;
+ __REG(0x021b0850) = 0x4243;
+ __REG(0x021b4850) = 0x4932473A;
+
+ __REG(0x021b080c) = 0x001F001F;
+ __REG(0x021b0810) = 0x001F001F;
+
+ __REG(0x021b480c) = 0x001F001F;
+ __REG(0x021b4810) = 0x001F001F;
+
+ __REG(0x021b08b8) = 0x0800;
+ __REG(0x021b48b8) = 0x0800;
+
+ __REG(0x021b0404) = 0x00011006;
+ __REG(0x021b0004) = 0x00025576;
+
+ __REG(0x021b001c) = 0x;
+
+ __REG(0x020c4068) = 0x00C03F3F;
+ __REG(0x020c406c) = 0x0030FC00;
+ __REG(0x020c4070) = 0x0FFFC000;
+ __REG(0x020c4074) = 0x3FF0;
+ __REG(0x020c4078) = 0x00FFF300;
+ __REG(0x020c407c) = 0x0FC3;
+ __REG(0x020c4080) = 0x03FF;
+}
+
This cannot be accepted. Firstly, you cannot use fixed offset. The code
you propose here is very difficult to maintain.
Then, please take a look at the i.MX6 boards that are
Re: [U-Boot] [PATCH v3 6/8] imx6: add data configuration file for SPL
Hi John, On 08/11/2014 22:27, John Tobias wrote: This file is the default DCD configuration file for SPL --- board/freescale/mx6sabresd/mx6sabresd_spl.cfg | 54 +++ 1 file changed, 54 insertions(+) create mode 100644 board/freescale/mx6sabresd/mx6sabresd_spl.cfg diff --git a/board/freescale/mx6sabresd/mx6sabresd_spl.cfg b/board/freescale/mx6sabresd/mx6sabresd_spl.cfg new file mode 100644 index 000..2e2f850 --- /dev/null +++ b/board/freescale/mx6sabresd/mx6sabresd_spl.cfg @@ -0,0 +1,54 @@ +/* + * Maintainer : Richard Hu linux...@technexion.com + * + * Derived from Nitrogen6x code by Boundary Devices + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer doc/README.imximage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + I am expecting that this file is derived from sabresd .cfg file, not from something else. Not only: this file seems to me identical to novena .cfg (setup.cfg), copyrighted by Marek Vasut. Please carefully check copyright and licensing of the file you are taking and maintain the original license. +/* image version */ +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi, sd (the board has no nand neither onenand) + */ +BOOT_FROM sd + +#define __ASSEMBLY__ +#include config.h +#include asm/arch/iomux.h +#include asm/arch/crm_regs.h + +/* set the default clock gate to save power */ +DATA 4 0x020C4068 0x00C03F3F /* CCM_CCGR0 */ +DATA 4 0x020C406c 0x0030FC03 /* CCM_CCGR1 */ +DATA 4 0x020C4070 0x0FFFC000 /* CCM_CCGR2 */ +DATA 4 0x020C4074 0x3FF0 /* CCM_CCGR3 */ +DATA 4 0x020C4078 0xFFF300 /* CCM_CCGR4 */ +DATA 4 0x020C407c 0x0FF3 /* CCM_CCGR5 - enable SATA clocks */ +DATA 4 0x020C4080 0x03FF /* CCM_CCGR6 - enable ushdc and usb clocks */ + +/* enable AXI cache for VDOA/VPU/IPU */ +DATA 4 0x020e0010 0xF0CF /* IOMUXC_GPR4 */ +/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ +DATA 4 0x020e0018 0x007F007F /* IOMUXC_GPR6 */ +DATA 4 0x020e001c 0x007F007F /* IOMUXC_GPR7 */ + +/* + * Setup CCM_CCOSR register as follows: + * + * cko1_en = 1 -- CKO1 enabled + * cko1_div = 111 -- divide by 8 + * cko1_sel = 1011 -- ahb_clk_root + * + * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz + */ +DATA 4 0x020c4060 0x00fb /* CCM_CCOSR */ + + Best regards, Stefano Babic -- = DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de = ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3 4/8] imx6: add some flexibility for defining macros
On 08/11/2014 22:27, John Tobias wrote: iMX6 SabreSD has different stack address compare to the default stack address defined on the file. The CONFIG_SYS_TEXT_BASE is defined in mx6sabre_common.h which is same address defined on file. At the same time to avoid compilation warnings. --- include/configs/imx6_spl.h | 4 1 file changed, 4 insertions(+) diff --git a/include/configs/imx6_spl.h b/include/configs/imx6_spl.h index 5a5f940..4ff37b3 100644 --- a/include/configs/imx6_spl.h +++ b/include/configs/imx6_spl.h @@ -29,7 +29,9 @@ #define CONFIG_SPL_TEXT_BASE 0x00908000 #define CONFIG_SPL_MAX_SIZE 0x1 #define CONFIG_SPL_START_S_PATH arch/arm/cpu/armv7 +#ifndef CONFIG_SPL_STACK #define CONFIG_SPL_STACK 0x0091FFB8 +#endif Why is this required ? #define CONFIG_SPL_LIBCOMMON_SUPPORT #define CONFIG_SPL_LIBGENERIC_SUPPORT #define CONFIG_SPL_SERIAL_SUPPORT @@ -66,7 +68,9 @@ #define CONFIG_SPL_BSS_MAX_SIZE 0x10/* 1 MB */ #define CONFIG_SYS_SPL_MALLOC_START 0x1830 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x320 /* 50 MB */ +#ifndef CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_TEXT_BASE 0x1780 #endif +#endif Why is this required ? Best regards, Stefano Babic -- = DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de = ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 2/7] imx6sl: update DCD configuration file
Hi John, On 09/11/2014 18:51, John Tobias wrote: Update the Device Configuration Data file for iMX6SL for SPL support. --- board/freescale/mx6slevk/imximage.cfg | 78 ++- 1 file changed, 4 insertions(+), 74 deletions(-) diff --git a/board/freescale/mx6slevk/imximage.cfg b/board/freescale/mx6slevk/imximage.cfg index 16ea597..3ebd985 100644 --- a/board/freescale/mx6slevk/imximage.cfg +++ b/board/freescale/mx6slevk/imximage.cfg @@ -1,7 +1,10 @@ /* * Copyright (C) 2013 Freescale Semiconductor, Inc. * - * SPDX-License-Identifier: GPL-2.0+ + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License or (at your option) any later version. NAK. Please take a look at the SPDX. The SPDX identifier substitutes all stuff related to license, avoiding to duplicate the same lines in multiple files. * * Refer docs/README.imxmage for more details about how-to configure * and create imximage boot image @@ -40,76 +43,3 @@ DATA 4 0x020c4074 0x DATA 4 0x020c4078 0x DATA 4 0x020c407c 0x DATA 4 0x020c4080 0x - -DATA 4 0x020e0344 0x3030 -DATA 4 0x020e0348 0x3030 -DATA 4 0x020e034c 0x3030 -DATA 4 0x020e0350 0x3030 -DATA 4 0x020e030c 0x0030 -DATA 4 0x020e0310 0x0030 -DATA 4 0x020e0314 0x0030 -DATA 4 0x020e0318 0x0030 -DATA 4 0x020e0300 0x0030 -DATA 4 0x020e031c 0x0030 -DATA 4 0x020e0338 0x0028 -DATA 4 0x020e0320 0x0030 -DATA 4 0x020e032c 0x -DATA 4 0x020e033c 0x0008 -DATA 4 0x020e0340 0x0008 -DATA 4 0x020e05c4 0x0030 -DATA 4 0x020e05cc 0x0030 -DATA 4 0x020e05d4 0x0030 -DATA 4 0x020e05d8 0x0030 -DATA 4 0x020e05ac 0x0030 -DATA 4 0x020e05c8 0x0030 -DATA 4 0x020e05b0 0x0002 -DATA 4 0x020e05b4 0x -DATA 4 0x020e05c0 0x0002 -DATA 4 0x020e05d0 0x0008 - -DATA 4 0x021b001c 0x8000 -DATA 4 0x021b085c 0x1b4700c7 -DATA 4 0x021b0800 0xa1390003 -DATA 4 0x021b0890 0x0030 -DATA 4 0x021b08b8 0x0800 -DATA 4 0x021b081c 0x -DATA 4 0x021b0820 0x -DATA 4 0x021b0824 0x -DATA 4 0x021b0828 0x -DATA 4 0x021b082c 0xf333 -DATA 4 0x021b0830 0xf333 -DATA 4 0x021b0834 0xf333 -DATA 4 0x021b0838 0xf333 -DATA 4 0x021b0848 0x4241444a -DATA 4 0x021b0850 0x3030312b -DATA 4 0x021b083c 0x2000 -DATA 4 0x021b0840 0x -DATA 4 0x021b08c0 0x24911492 -DATA 4 0x021b08b8 0x0800 -DATA 4 0x021b000c 0x33374133 -DATA 4 0x021b0004 0x00020024 -DATA 4 0x021b0010 0x00100A82 -DATA 4 0x021b0014 0x0093 -DATA 4 0x021b0018 0x1688 -DATA 4 0x021b002c 0x0f9f26d2 -DATA 4 0x021b0030 0x020e -DATA 4 0x021b0038 0x00190778 -DATA 4 0x021b0008 0x -DATA 4 0x021b0040 0x004f -DATA 4 0x021b 0xc311 -DATA 4 0x021b001c 0x003f8030 -DATA 4 0x021b001c 0xff0a8030 -DATA 4 0x021b001c 0x82018030 -DATA 4 0x021b001c 0x04028030 -DATA 4 0x021b001c 0x02038030 -DATA 4 0x021b001c 0xff0a8038 -DATA 4 0x021b001c 0x82018038 -DATA 4 0x021b001c 0x04028038 -DATA 4 0x021b001c 0x02038038 -DATA 4 0x021b0800 0xa1310003 -DATA 4 0x021b0020 0x1800 -DATA 4 0x021b0818 0x -DATA 4 0x021b08b8 0x0800 -DATA 4 0x021b0004 0x00025564 -DATA 4 0x021b0404 0x00011006 -DATA 4 0x021b001c 0x Some comment in the commit message explaining what is happening here can be useful. Best regards, Stefano Babic -- = DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de = ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 0/7] *** iMX6SL-evk SPL Support ***
Hi, Please drop *** from the cover letter template git-format-patch generates. :) Cheers, Andreas -- SUSE LINUX GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 21284 AG Nürnberg ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 0/7] *** iMX6SL-evk SPL Support ***
Thanks for the info. Regards, John On Sunday, November 9, 2014, Andreas Färber afaer...@suse.de wrote: Hi, Please drop *** from the cover letter template git-format-patch generates. :) Cheers, Andreas -- SUSE LINUX GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 21284 AG Nürnberg ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/7] imx6: add macro define inclusion
Hi John, On Sun, Nov 9, 2014 at 3:51 PM, John Tobias john.tobias...@gmail.com wrote: add a macro define inclusion to compile the function. iMX6SL doesn't have an MMDC_P1_BASE_ADDR in the header. It will break the build if the SPL features is enabled for iMX6SL. --- You missed to add the Signed-off-by tag in your patches. Please run ./scripts/checkpatch on your patches. Regards, Fabio Estevam ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/7] imx6: add macro define inclusion
Hi Fabio, I didn't notice that one... Thanks for the info. Regards, john On Sun, Nov 9, 2014 at 3:26 PM, Fabio Estevam feste...@gmail.com wrote: Hi John, On Sun, Nov 9, 2014 at 3:51 PM, John Tobias john.tobias...@gmail.com wrote: add a macro define inclusion to compile the function. iMX6SL doesn't have an MMDC_P1_BASE_ADDR in the header. It will break the build if the SPL features is enabled for iMX6SL. --- You missed to add the Signed-off-by tag in your patches. Please run ./scripts/checkpatch on your patches. Regards, Fabio Estevam ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] verified boot of beaglebone black
Hi Simon
From: s...@google.com s...@google.com on behalf of Simon Glass
s...@chromium.org
Sent: Friday, November 7, 2014 10:18 PM
To: Srinivasan S
Cc: Jagan Teki; U-Boot Mailing List
Subject: Re: [U-Boot] verified boot of beaglebone black
Hi,
On 4 November 2014 00:39, Srinivasan S srinivasa...@tataelxsi.co.in wrote:
Thanks a lot for your replies
The issue was where at symbol was supposed to be changed to @
+ kernel at 1 {
+ data = /incbin/(Image.lzo);
+ type = kernel;
+ arch = arm;
+ os = linux;
+ compression = lzo;
+ load = 0x80008000;
+ entry = 0x80008000;
+ hash at 1 {
+ algo = sha1;
+ };
When I was generating the keys ie., Step 4: Create a key pair
Am facing one more error while generating private key certificate
containing public key used for verification when I execute the below openssl
commands it is saying can't open config file:
srinivasan@tata-HP-Elite-7100-Microtower-PC:~/TUNSTALL/board-support/linux-3.12.10-ti2013.12.01/work$
openssl genrsa -F4 -out keys/dev.key 2048
WARNING: can't open config file:
/tmp///sysroots/i686-arago-linux/usr/lib/ssl/openssl.cnf
Generating RSA private key, 2048 bit long modulus
+++
...+++
e is 65537 (0x10001)
srinivasan@tata-HP-Elite-7100-Microtower-PC:~/TUNSTALL/board-support/linux-3.12.10-ti2013.12.01/work$
openssl req -batch -new -x509 -key keys/dev.key -out keys/dev.crt
WARNING: can't open config file:
/tmp///sysroots/i686-arago-linux/usr/lib/ssl/openssl.cnf
Unable to load config info from
/tmp///sysroots/i686-arago-linux/usr/lib/ssl/openssl.cnf
Did you mkdir keys?
Regards,
Simon
Hi Simon,
As you suggested earlier am using u-boot-2014.07 Am using
~/ti-sdk-am335x-evm-07.00.00.00/bin/create-sdcard.sh for creating the
partitions,
After creating the partitions I tried implementing step 7. Put U-Boot and the
kernel onto the board step 8. Try it, by the following steps,
And when I tried to boot I am facing the below error for which am not able to
get the uboot prompt
U-Boot SPL 2013.10-g78d8ebd (Mar 30 2014 - 20:46:34)
reading args
spl: error reading image args, err - -1
reading u-boot.img
reading u-boot.img
No valid FDT found - please append one to U-Boot binary, use u-boot-dtb.bin or
define CONFIG_OF_EMBED. For sandbox, use -d file.dtb
initcall sequence 808511ec failed at call 80833f84
### ERROR ### Please RESET the board ###
Steps followed by me
1.
As tmp directory was unavailable while mounting /dev/sdc1, so I created tmp
directory while mounting /dev/sdc1 executed the commands as below
sudo mount /dev/sdc1 /mnt/tmp
sudo cp
~/ti-sdk-am335x-evm-07.00.00.00/board-support/u-boot-2014.07/b/am335x_boneblack_vboot/u-boot.img
/mnt/tmp/u-boot.img
sleep 1
sudo umount /dev/sdc1
sudo mount /dev/sdc2 /mnt/tmp
sudo cp
~/ti-sdk-am335x-evm-07.00.00.00/board-support/linux-3.12.10-ti2013.12.01/work/image.fit
/mnt/tmp/boot/image.fit
sleep 1
sudo umount /dev/sdc2
2.
I have even tried copying MLO u-boot.img of as below
sudo cp
~/ti-sdk-am335x-evm-07.00.00.00/board-support/u-boot-2014.07/b/am335x_boneblack_vboot/MLO
/media/boot/
sudo cp
~/ti-sdk-am335x-evm-07.00.00.00/board-support/u-boot-2014.07/b/am335x_boneblack_vboot/u-boot.img
/media/boot/
appusony@appusony-laptop:~/ti-sdk-am335x-evm-07.00.00.00/board-support/linux-3.12.10-ti2013.12.01/work$
ls
am335x-boneblack.dtb am335x-boneblack-pubkey.dtb Image image.fit Image.lzo
keys sign.its u-boot-dtb.img
appusony@appusony-laptop:~/ti-sdk-am335x-evm-07.00.00.00/board-support/linux-3.12.10-ti2013.12.01/work$
sudo image.fit /media/rootfs/boot/
Could you please do the needful in resolving the above issue as am stuck with
this last steps
Kindly do the needful as early as possible,
Many Thanks in advance
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Re: [U-Boot] [PATCH 7/9] board/renesas/ecovec/ecovec.c: fix buffer overflow
2014-11-06 22:03 GMT+09:00 Wolfgang Denk w...@denx.de:
Fix error detected by cppcheck:
[board/renesas/ecovec/ecovec.c:66]: (error) Buffer is accessed out of
bounds.
Signed-off-by: Wolfgang Denk w...@denx.de
Cc: Nobuhiro Iwamatsu iwamatsu.nobuh...@renesas.com
---
board/renesas/ecovec/ecovec.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/board/renesas/ecovec/ecovec.c b/board/renesas/ecovec/ecovec.c
index 2804d91..d862d99 100644
--- a/board/renesas/ecovec/ecovec.c
+++ b/board/renesas/ecovec/ecovec.c
@@ -41,7 +41,7 @@ static void debug_led(u8 led)
int board_late_init(void)
{
u8 mac[6];
- char env_mac[17];
+ char env_mac[18];
udelay(1000);
--
1.8.3.1
Applied, thanks.
Best regards,
Nobuhiro
--
Nobuhiro Iwamatsu
iwamatsu at {nigauri.org / debian.org}
GPG ID: 40AD1FA6
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Re: [U-Boot] [PATCH v3 4/8] imx6: add some flexibility for defining macros
Hi Stefano, On Sun, Nov 9, 2014 at 1:24 PM, Stefano Babic sba...@denx.de wrote: On 08/11/2014 22:27, John Tobias wrote: iMX6 SabreSD has different stack address compare to the default stack address defined on the file. The CONFIG_SYS_TEXT_BASE is defined in mx6sabre_common.h which is same address defined on file. At the same time to avoid compilation warnings. --- include/configs/imx6_spl.h | 4 1 file changed, 4 insertions(+) diff --git a/include/configs/imx6_spl.h b/include/configs/imx6_spl.h index 5a5f940..4ff37b3 100644 --- a/include/configs/imx6_spl.h +++ b/include/configs/imx6_spl.h @@ -29,7 +29,9 @@ #define CONFIG_SPL_TEXT_BASE 0x00908000 #define CONFIG_SPL_MAX_SIZE 0x1 #define CONFIG_SPL_START_S_PATH arch/arm/cpu/armv7 +#ifndef CONFIG_SPL_STACK #define CONFIG_SPL_STACK 0x0091FFB8 +#endif Why is this required ? Other iMX6 chip has different STACK address and the current defined address does not compatibile for the iMX6 SabreSD. The intention is to use as much as possible the said header and it should have the ability to change the value of it. e.g defined in mx6sabresd.h #ifdef CONFIG_SPL #define CONFIG_SPL_LIBCOMMON_SUPPORT #define CONFIG_SPL_MMC_SUPPORT #define CONFIG_SPL_STACK 0x0093FFB8 #include imx6_spl.h #endif #define CONFIG_SPL_LIBCOMMON_SUPPORT #define CONFIG_SPL_LIBGENERIC_SUPPORT #define CONFIG_SPL_SERIAL_SUPPORT @@ -66,7 +68,9 @@ #define CONFIG_SPL_BSS_MAX_SIZE 0x10/* 1 MB */ #define CONFIG_SYS_SPL_MALLOC_START 0x1830 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x320 /* 50 MB */ +#ifndef CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_TEXT_BASE 0x1780 #endif +#endif Why is this required ? mentioned above. Addition to that, on my recent submission for iMX6SL. It requires to change the value of the following: CONFIG_SPL_BSS_START_ADDR CONFIG_SYS_SPL_MALLOC_START Regards, john Best regards, Stefano Babic -- = DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de = ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3 6/8] imx6: add data configuration file for SPL
Thanks for the info. I'll double check it again. Regards, john On Sun, Nov 9, 2014 at 1:22 PM, Stefano Babic sba...@denx.de wrote: Hi John, On 08/11/2014 22:27, John Tobias wrote: This file is the default DCD configuration file for SPL --- board/freescale/mx6sabresd/mx6sabresd_spl.cfg | 54 +++ 1 file changed, 54 insertions(+) create mode 100644 board/freescale/mx6sabresd/mx6sabresd_spl.cfg diff --git a/board/freescale/mx6sabresd/mx6sabresd_spl.cfg b/board/freescale/mx6sabresd/mx6sabresd_spl.cfg new file mode 100644 index 000..2e2f850 --- /dev/null +++ b/board/freescale/mx6sabresd/mx6sabresd_spl.cfg @@ -0,0 +1,54 @@ +/* + * Maintainer : Richard Hu linux...@technexion.com + * + * Derived from Nitrogen6x code by Boundary Devices + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer doc/README.imximage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + I am expecting that this file is derived from sabresd .cfg file, not from something else. Not only: this file seems to me identical to novena .cfg (setup.cfg), copyrighted by Marek Vasut. Please carefully check copyright and licensing of the file you are taking and maintain the original license. +/* image version */ +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi, sd (the board has no nand neither onenand) + */ +BOOT_FROM sd + +#define __ASSEMBLY__ +#include config.h +#include asm/arch/iomux.h +#include asm/arch/crm_regs.h + +/* set the default clock gate to save power */ +DATA 4 0x020C4068 0x00C03F3F /* CCM_CCGR0 */ +DATA 4 0x020C406c 0x0030FC03 /* CCM_CCGR1 */ +DATA 4 0x020C4070 0x0FFFC000 /* CCM_CCGR2 */ +DATA 4 0x020C4074 0x3FF0 /* CCM_CCGR3 */ +DATA 4 0x020C4078 0xFFF300 /* CCM_CCGR4 */ +DATA 4 0x020C407c 0x0FF3 /* CCM_CCGR5 - enable SATA clocks */ +DATA 4 0x020C4080 0x03FF /* CCM_CCGR6 - enable ushdc and usb clocks */ + +/* enable AXI cache for VDOA/VPU/IPU */ +DATA 4 0x020e0010 0xF0CF /* IOMUXC_GPR4 */ +/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ +DATA 4 0x020e0018 0x007F007F /* IOMUXC_GPR6 */ +DATA 4 0x020e001c 0x007F007F /* IOMUXC_GPR7 */ + +/* + * Setup CCM_CCOSR register as follows: + * + * cko1_en = 1 -- CKO1 enabled + * cko1_div = 111 -- divide by 8 + * cko1_sel = 1011 -- ahb_clk_root + * + * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz + */ +DATA 4 0x020c4060 0x00fb /* CCM_CCOSR */ + + Best regards, Stefano Babic -- = DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de = ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 3/8] imx6: add spl on board configuration
On Sat, Nov 8, 2014 at 4:22 PM, John Tobias john.tobias...@gmail.com wrote: add the spl on build configuration of iMX6 SabreSD --- include/configs/mx6sabresd.h | 7 +++ 1 file changed, 7 insertions(+) diff --git a/include/configs/mx6sabresd.h b/include/configs/mx6sabresd.h index 938030d..4d2e54a 100644 --- a/include/configs/mx6sabresd.h +++ b/include/configs/mx6sabresd.h @@ -12,6 +12,13 @@ #include asm/arch/imx-regs.h #include asm/imx-common/gpio.h +#ifdef CONFIG_SPL +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SPL_STACK 0x0093FFB8 +#include imx6_spl.h +#endif I am wondering if it would be better to create a separate target for the spl version, so that the people could still use the standard DCD approach as they are used to. Regards, Fabio Estevam ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] verified boot of beaglebone black
Hi Simon,
Hi Simon,
As you suggested earlier am using u-boot-2014.07 Am using
~/ti-sdk-am335x-evm-07.00.00.00/bin/create-sdcard.sh for creating the
partitions,
After creating the partitions I tried implementing step 7. Put U-Boot and the
kernel onto the board step 8. Try it, by the following steps,
And when I tried to boot I am facing the below error for which am not able to
get the uboot prompt
U-Boot SPL 2013.10-g78d8ebd (Mar 30 2014 - 20:46:34)
reading args
spl: error reading image args, err - -1
reading u-boot.img
reading u-boot.img
No valid FDT found - please append one to U-Boot binary, use u-boot-dtb.bin or
define CONFIG_OF_EMBED. For sandbox, use -d file.dtb
initcall sequence 808511ec failed at call 80833f84
### ERROR ### Please RESET the board ###
Steps followed by me
1.
As tmp directory was unavailable while mounting /dev/sdc1, so I created tmp
directory while mounting /dev/sdc1 executed the commands as below
sudo mount /dev/sdc1 /mnt/tmp
sudo cp
~/ti-sdk-am335x-evm-07.00.00.00/board-support/u-boot-2014.07/b/am335x_boneblack_vboot/u-boot.img
/mnt/tmp/u-boot.img
sleep 1
sudo umount /dev/sdc1
sudo mount /dev/sdc2 /mnt/tmp
sudo cp
~/ti-sdk-am335x-evm-07.00.00.00/board-support/linux-3.12.10-ti2013.12.01/work/image.fit
/mnt/tmp/boot/image.fit
sleep 1
sudo umount /dev/sdc2
2.
I have even tried copying MLO u-boot.img of as below, but still the same
error where unable to get uboot prompt
sudo cp
~/ti-sdk-am335x-evm-07.00.00.00/board-support/u-boot-2014.07/b/am335x_boneblack_vboot/MLO
/media/boot/
sudo cp
~/ti-sdk-am335x-evm-07.00.00.00/board-support/u-boot-2014.07/b/am335x_boneblack_vboot/u-boot.img
/media/boot/
appusony@appusony-laptop:~/ti-sdk-am335x-evm-07.00.00.00/board-support/linux-3.12.10-ti2013.12.01/work$
ls
am335x-boneblack.dtb am335x-boneblack-pubkey.dtb Image image.fit Image.lzo
keys sign.its u-boot-dtb.img
appusony@appusony-laptop:~/ti-sdk-am335x-evm-07.00.00.00/board-support/linux-3.12.10-ti2013.12.01/work$
sudo image.fit /media/rootfs/boot/
Please do the needful in resolving the above issue as this is the last steps
Many Thanks in Advance again,
From: s...@google.com s...@google.com on behalf of Simon Glass
s...@chromium.org
Sent: Friday, November 7, 2014 10:18 PM
To: Srinivasan S
Cc: Jagan Teki; U-Boot Mailing List
Subject: Re: [U-Boot] verified boot of beaglebone black
Hi,
On 4 November 2014 00:39, Srinivasan S srinivasa...@tataelxsi.co.in wrote:
Thanks a lot for your replies
The issue was where at symbol was supposed to be changed to @
+ kernel at 1 {
+ data = /incbin/(Image.lzo);
+ type = kernel;
+ arch = arm;
+ os = linux;
+ compression = lzo;
+ load = 0x80008000;
+ entry = 0x80008000;
+ hash at 1 {
+ algo = sha1;
+ };
When I was generating the keys ie., Step 4: Create a key pair
Am facing one more error while generating private key certificate
containing public key used for verification when I execute the below openssl
commands it is saying can't open config file:
srinivasan@tata-HP-Elite-7100-Microtower-PC:~/TUNSTALL/board-support/linux-3.12.10-ti2013.12.01/work$
openssl genrsa -F4 -out keys/dev.key 2048
WARNING: can't open config file:
/tmp///sysroots/i686-arago-linux/usr/lib/ssl/openssl.cnf
Generating RSA private key, 2048 bit long modulus
+++
...+++
e is 65537 (0x10001)
srinivasan@tata-HP-Elite-7100-Microtower-PC:~/TUNSTALL/board-support/linux-3.12.10-ti2013.12.01/work$
openssl req -batch -new -x509 -key keys/dev.key -out keys/dev.crt
WARNING: can't open config file:
/tmp///sysroots/i686-arago-linux/usr/lib/ssl/openssl.cnf
Unable to load config info from
/tmp///sysroots/i686-arago-linux/usr/lib/ssl/openssl.cnf
Did you mkdir keys?
Regards,
Simon
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[U-Boot] [PATCH 1/3] arm: rmobile: alt: Enable channel 1 of sh-i2c
Alt board was connected Power IC to channel 1 of sh-i2c. Source code that controls this is already included, but channel 1 of sh-i2c is not enabled. This enables channel 1 of sh-i2c, and can use. Signed-off-by: Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com --- board/renesas/alt/alt.c | 7 +++ 1 file changed, 7 insertions(+) diff --git a/board/renesas/alt/alt.c b/board/renesas/alt/alt.c index cf6d64c..083e007 100644 --- a/board/renesas/alt/alt.c +++ b/board/renesas/alt/alt.c @@ -49,6 +49,10 @@ void s_init(void) #define SMSTPCR8 0xE6150990 #define ETHER_MSTP813 (1 13) +#define MSTPSR30xE6150048 +#define SMSTPCR3 0xE615013C +#define IIC1_MSTP323 (1 23) + #define mstp_setbits(type, addr, saddr, set) \ out_##type((saddr), in_##type(addr) | (set)) #define mstp_clrbits(type, addr, saddr, clear) \ @@ -69,6 +73,9 @@ int board_early_init_f(void) /* ETHER */ mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813); + /* IIC1 / sh-i2c ch1 */ + mstp_clrbits_le32(MSTPSR3, SMSTPCR3, IIC1_MSTP323); + return 0; } -- 2.1.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 3/3] arm: rmobile: alt: Remove i2c_init function
The i2c_init function is no longer necessary. Signed-off-by: Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com --- board/renesas/alt/alt.c | 1 - 1 file changed, 1 deletion(-) diff --git a/board/renesas/alt/alt.c b/board/renesas/alt/alt.c index 68ae937..039cb37 100644 --- a/board/renesas/alt/alt.c +++ b/board/renesas/alt/alt.c @@ -167,7 +167,6 @@ void reset_cpu(ulong addr) u8 val; i2c_set_bus_num(1); /* PowerIC connected to ch1 */ - i2c_init(40, 0); i2c_read(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, val, 1); val |= 0x02; i2c_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, val, 1); -- 2.1.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 2/3] arm: rmobile: alt: Fix typo in comment for sh-i2c
PowerIC connected to channel 1 of sh-i2c, not channel 2.
Signed-off-by: Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com
---
board/renesas/alt/alt.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/board/renesas/alt/alt.c b/board/renesas/alt/alt.c
index 083e007..68ae937 100644
--- a/board/renesas/alt/alt.c
+++ b/board/renesas/alt/alt.c
@@ -166,7 +166,7 @@ void reset_cpu(ulong addr)
{
u8 val;
- i2c_set_bus_num(1); /* PowerIC connected to ch3 */
+ i2c_set_bus_num(1); /* PowerIC connected to ch1 */
i2c_init(40, 0);
i2c_read(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, val, 1);
val |= 0x02;
--
2.1.1
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Re: [U-Boot] [PATCH v3 7/8] imx6: SPL support for iMX6 SabreSD
Hi Stefano,
On Sun, Nov 9, 2014 at 1:16 PM, Stefano Babic sba...@denx.de wrote:
Hi John,
On 08/11/2014 22:27, John Tobias wrote:
This patch will enable the support for SPL on iMX6 SabreSD.
It tested on SD2 and SD3 mmc port.
---
board/freescale/mx6sabresd/mx6sabresd.c | 211
+++-
1 file changed, 209 insertions(+), 2 deletions(-)
diff --git a/board/freescale/mx6sabresd/mx6sabresd.c
b/board/freescale/mx6sabresd/mx6sabresd.c
index 3d81fff..f443337 100644
--- a/board/freescale/mx6sabresd/mx6sabresd.c
+++ b/board/freescale/mx6sabresd/mx6sabresd.c
@@ -55,8 +55,7 @@ DECLARE_GLOBAL_DATA_PTR;
int dram_init(void)
{
- gd-ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
-
+ gd-ram_size = imx_ddr_size();
return 0;
}
@@ -607,3 +606,211 @@ int checkboard(void)
puts(Board: MX6-SabreSD\n);
return 0;
}
+
+#ifdef CONFIG_SPL_BUILD
+#include spl.h
+#include libfdt.h
+
+#define BOOT_CFG 0x20D8004
+#define __REG(x)(*((volatile u32 *)(x)))
+
+struct fsl_esdhc_cfg spl_usdhc_cfg;
+/*
+ * Got it from mx6q_4x_mt41j128.cfg file
+ */
+void set_mt41j128_ddr(void)
+{
+ __REG(0x020e05a8) = 0x0028;
+ __REG(0x020e05b0) = 0x0028;
+ __REG(0x020e0524) = 0x0028;
+ __REG(0x020e051c) = 0x0028;
+
+ __REG(0x020e0518) = 0x0028;
+ __REG(0x020e050c) = 0x0028;
+ __REG(0x020e05b8) = 0x0028;
+ __REG(0x020e05c0) = 0x0028;
+
+ __REG(0x020e05ac) = 0x0028;
+ __REG(0x020e05b4) = 0x0028;
+ __REG(0x020e0528) = 0x0028;
+ __REG(0x020e0520) = 0x0028;
+
+ __REG(0x020e0514) = 0x0028;
+ __REG(0x020e0510) = 0x0028;
+ __REG(0x020e05bc) = 0x0028;
+ __REG(0x020e05c4) = 0x0028;
+
+ __REG(0x020e056c) = 0x0030;
+ __REG(0x020e0578) = 0x0030;
+ __REG(0x020e0588) = 0x0030;
+ __REG(0x020e0594) = 0x0030;
+
+ __REG(0x020e057c) = 0x0030;
+ __REG(0x020e0590) = 0x0030;
+ __REG(0x020e0598) = 0x0030;
+ __REG(0x020e058c) = 0x;
+
+ __REG(0x020e059c) = 0x3030;
+ __REG(0x020e05a0) = 0x3030;
+ __REG(0x020e0784) = 0x0028;
+ __REG(0x020e0788) = 0x0028;
+
+ __REG(0x020e0794) = 0x0028;
+ __REG(0x020e079c) = 0x0028;
+ __REG(0x020e07a0) = 0x0028;
+ __REG(0x020e07a4) = 0x0028;
+
+ __REG(0x020e07a8) = 0x0028;
+ __REG(0x020e0748) = 0x0028;
+ __REG(0x020e074c) = 0x0030;
+ __REG(0x020e0750) = 0x0002;
+
+ __REG(0x020e0758) = 0x;
+ __REG(0x020e0774) = 0x0002;
+ __REG(0x020e078c) = 0x0030;
+ __REG(0x020e0798) = 0x000C;
+
+ __REG(0x021b081c) = 0x;
+ __REG(0x021b0820) = 0x;
+ __REG(0x021b0824) = 0x;
+ __REG(0x021b0828) = 0x;
+
+ __REG(0x021b481c) = 0x;
+ __REG(0x021b4820) = 0x;
+ __REG(0x021b4824) = 0x;
+ __REG(0x021b4828) = 0x;
+
+ __REG(0x021b0018) = 0x1740;
+
+ __REG(0x021b001c) = 0x8000;
+ __REG(0x021b000c) = 0x8A8F7975;
+ __REG(0x021b0010) = 0xFF538E64;
+ __REG(0x021b0014) = 0x01FF00DB;
+ __REG(0x021b002c) = 0x26D2;
+
+ __REG(0x021b0030) = 0x008F0E21;
+ __REG(0x021b0008) = 0x09444040;
+ __REG(0x021b0004) = 0x00020036;
+ __REG(0x021b0040) = 0x0047;
+ __REG(0x021b) = 0x841A;
+
+ __REG(0x021b001c) = 0x04088032;
+ __REG(0x021b001c) = 0x8033;
+ __REG(0x021b001c) = 0x00428031;
+ __REG(0x021b001c) = 0x09408030;
+
+ __REG(0x021b001c) = 0x04008040;
+ __REG(0x021b0800) = 0xA1380003;
+ __REG(0x021b0020) = 0x5800;
+ __REG(0x021b0818) = 0x0007;
+ __REG(0x021b4818) = 0x0007;
+
+ /* Calibration values based on ARD and 528MHz */
+ __REG(0x021b083c) = 0x434B0358;
+ __REG(0x021b0840) = 0x033D033C;
+ __REG(0x021b483c) = 0x03520362;
+ __REG(0x021b4840) = 0x03480318;
+ __REG(0x021b0848) = 0x41383A3C;
+ __REG(0x021b4848) = 0x3F3C374A;
+ __REG(0x021b0850) = 0x4243;
+ __REG(0x021b4850) = 0x4932473A;
+
+ __REG(0x021b080c) = 0x001F001F;
+ __REG(0x021b0810) = 0x001F001F;
+
+ __REG(0x021b480c) = 0x001F001F;
+ __REG(0x021b4810) = 0x001F001F;
+
+ __REG(0x021b08b8) = 0x0800;
+ __REG(0x021b48b8) = 0x0800;
+
+ __REG(0x021b0404) = 0x00011006;
+ __REG(0x021b0004) = 0x00025576;
+
+ __REG(0x021b001c) = 0x;
+
+ __REG(0x020c4068) = 0x00C03F3F;
+ __REG(0x020c406c) = 0x0030FC00;
+ __REG(0x020c4070) = 0x0FFFC000;
+ __REG(0x020c4074) = 0x3FF0;
+ __REG(0x020c4078) = 0x00FFF300;
+ __REG(0x020c407c) = 0x0FC3;
+ __REG(0x020c4080) = 0x03FF;
+}
+
This cannot be accepted. Firstly, you cannot use fixed offset. The code
you propose here is
[U-Boot] [PATCH] arm: rmobile: kconfig: Remove '+S:' prefix from defconfig files
'+S' is unnecessary because boards of rmobile do not use SPL. Signed-off-by: Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com CC: Masahiro Yamada yamad...@jp.panasonic.com --- configs/alt_defconfig | 2 +- configs/koelsch_defconfig | 2 +- configs/lager_defconfig | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/configs/alt_defconfig b/configs/alt_defconfig index 0655e60..d722306 100644 --- a/configs/alt_defconfig +++ b/configs/alt_defconfig @@ -1,3 +1,3 @@ CONFIG_ARM=y -+S:CONFIG_RMOBILE=y +CONFIG_RMOBILE=y CONFIG_TARGET_ALT=y diff --git a/configs/koelsch_defconfig b/configs/koelsch_defconfig index d59ff3d..35f605c 100644 --- a/configs/koelsch_defconfig +++ b/configs/koelsch_defconfig @@ -1,3 +1,3 @@ CONFIG_ARM=y -+S:CONFIG_RMOBILE=y +CONFIG_RMOBILE=y CONFIG_TARGET_KOELSCH=y diff --git a/configs/lager_defconfig b/configs/lager_defconfig index 9a32d6b..8b4aeea 100644 --- a/configs/lager_defconfig +++ b/configs/lager_defconfig @@ -1,3 +1,3 @@ CONFIG_ARM=y -+S:CONFIG_RMOBILE=y +CONFIG_RMOBILE=y CONFIG_TARGET_LAGER=y -- 2.1.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] arm: rmobile: alt: Change clock of SCIF to external clock
Change clock of SCIF for Alt board is used to external clock. This changes to using external clock. Signed-off-by: Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com --- include/configs/alt.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/configs/alt.h b/include/configs/alt.h index 67e41f8..c679be9 100644 --- a/include/configs/alt.h +++ b/include/configs/alt.h @@ -88,6 +88,7 @@ /* SCIF */ #define CONFIG_SCIF_CONSOLE #define CONFIG_CONS_SCIF2 +#define CONFIG_SCIF_USE_EXT_CLK #undef CONFIG_SYS_CONSOLE_INFO_QUIET #undef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE #undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE -- 2.1.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 3/8] imx6: add spl on board configuration
That's exactly that I am going to ask you. Because, some people in the community doesn't need the SPL. I think this will need a separate config files (e.g mx6slevk_spl_defconfig, mx6qsabresd_spl_defconfig) Regards, john On Sun, Nov 9, 2014 at 4:03 PM, Fabio Estevam feste...@gmail.com wrote: On Sat, Nov 8, 2014 at 4:22 PM, John Tobias john.tobias...@gmail.com wrote: add the spl on build configuration of iMX6 SabreSD --- include/configs/mx6sabresd.h | 7 +++ 1 file changed, 7 insertions(+) diff --git a/include/configs/mx6sabresd.h b/include/configs/mx6sabresd.h index 938030d..4d2e54a 100644 --- a/include/configs/mx6sabresd.h +++ b/include/configs/mx6sabresd.h @@ -12,6 +12,13 @@ #include asm/arch/imx-regs.h #include asm/imx-common/gpio.h +#ifdef CONFIG_SPL +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SPL_STACK 0x0093FFB8 +#include imx6_spl.h +#endif I am wondering if it would be better to create a separate target for the spl version, so that the people could still use the standard DCD approach as they are used to. Regards, Fabio Estevam ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 3/8] imx6: add spl on board configuration
On Sun, Nov 9, 2014 at 10:27 PM, John Tobias john.tobias...@gmail.com wrote: That's exactly that I am going to ask you. Because, some people in the community doesn't need the SPL. I think this will need a separate config files (e.g mx6slevk_spl_defconfig, mx6qsabresd_spl_defconfig) Yes, exacly, but I would prefere mx6sabresd_spl (without the 'q'), so that in the future we can support imx6q-sabresd and imx6dl-sabresd with a single binary using SPL. Thanks, Fabio Estevam ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 2/7] imx6sl: update DCD configuration file
My mistake, I should use what's in the mx6q_4x_mt41j128.cfg. Regards, john On Sun, Nov 9, 2014 at 1:31 PM, Stefano Babic sba...@denx.de wrote: Hi John, On 09/11/2014 18:51, John Tobias wrote: Update the Device Configuration Data file for iMX6SL for SPL support. --- board/freescale/mx6slevk/imximage.cfg | 78 ++- 1 file changed, 4 insertions(+), 74 deletions(-) diff --git a/board/freescale/mx6slevk/imximage.cfg b/board/freescale/mx6slevk/imximage.cfg index 16ea597..3ebd985 100644 --- a/board/freescale/mx6slevk/imximage.cfg +++ b/board/freescale/mx6slevk/imximage.cfg @@ -1,7 +1,10 @@ /* * Copyright (C) 2013 Freescale Semiconductor, Inc. * - * SPDX-License-Identifier: GPL-2.0+ + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License or (at your option) any later version. NAK. Please take a look at the SPDX. The SPDX identifier substitutes all stuff related to license, avoiding to duplicate the same lines in multiple files. * * Refer docs/README.imxmage for more details about how-to configure * and create imximage boot image @@ -40,76 +43,3 @@ DATA 4 0x020c4074 0x DATA 4 0x020c4078 0x DATA 4 0x020c407c 0x DATA 4 0x020c4080 0x - -DATA 4 0x020e0344 0x3030 -DATA 4 0x020e0348 0x3030 -DATA 4 0x020e034c 0x3030 -DATA 4 0x020e0350 0x3030 -DATA 4 0x020e030c 0x0030 -DATA 4 0x020e0310 0x0030 -DATA 4 0x020e0314 0x0030 -DATA 4 0x020e0318 0x0030 -DATA 4 0x020e0300 0x0030 -DATA 4 0x020e031c 0x0030 -DATA 4 0x020e0338 0x0028 -DATA 4 0x020e0320 0x0030 -DATA 4 0x020e032c 0x -DATA 4 0x020e033c 0x0008 -DATA 4 0x020e0340 0x0008 -DATA 4 0x020e05c4 0x0030 -DATA 4 0x020e05cc 0x0030 -DATA 4 0x020e05d4 0x0030 -DATA 4 0x020e05d8 0x0030 -DATA 4 0x020e05ac 0x0030 -DATA 4 0x020e05c8 0x0030 -DATA 4 0x020e05b0 0x0002 -DATA 4 0x020e05b4 0x -DATA 4 0x020e05c0 0x0002 -DATA 4 0x020e05d0 0x0008 - -DATA 4 0x021b001c 0x8000 -DATA 4 0x021b085c 0x1b4700c7 -DATA 4 0x021b0800 0xa1390003 -DATA 4 0x021b0890 0x0030 -DATA 4 0x021b08b8 0x0800 -DATA 4 0x021b081c 0x -DATA 4 0x021b0820 0x -DATA 4 0x021b0824 0x -DATA 4 0x021b0828 0x -DATA 4 0x021b082c 0xf333 -DATA 4 0x021b0830 0xf333 -DATA 4 0x021b0834 0xf333 -DATA 4 0x021b0838 0xf333 -DATA 4 0x021b0848 0x4241444a -DATA 4 0x021b0850 0x3030312b -DATA 4 0x021b083c 0x2000 -DATA 4 0x021b0840 0x -DATA 4 0x021b08c0 0x24911492 -DATA 4 0x021b08b8 0x0800 -DATA 4 0x021b000c 0x33374133 -DATA 4 0x021b0004 0x00020024 -DATA 4 0x021b0010 0x00100A82 -DATA 4 0x021b0014 0x0093 -DATA 4 0x021b0018 0x1688 -DATA 4 0x021b002c 0x0f9f26d2 -DATA 4 0x021b0030 0x020e -DATA 4 0x021b0038 0x00190778 -DATA 4 0x021b0008 0x -DATA 4 0x021b0040 0x004f -DATA 4 0x021b 0xc311 -DATA 4 0x021b001c 0x003f8030 -DATA 4 0x021b001c 0xff0a8030 -DATA 4 0x021b001c 0x82018030 -DATA 4 0x021b001c 0x04028030 -DATA 4 0x021b001c 0x02038030 -DATA 4 0x021b001c 0xff0a8038 -DATA 4 0x021b001c 0x82018038 -DATA 4 0x021b001c 0x04028038 -DATA 4 0x021b001c 0x02038038 -DATA 4 0x021b0800 0xa1310003 -DATA 4 0x021b0020 0x1800 -DATA 4 0x021b0818 0x -DATA 4 0x021b08b8 0x0800 -DATA 4 0x021b0004 0x00025564 -DATA 4 0x021b0404 0x00011006 -DATA 4 0x021b001c 0x Some comment in the commit message explaining what is happening here can be useful. Best regards, Stefano Babic -- = DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de = ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 3/8] imx6: add spl on board configuration
Oh okay, I'll do it again. Regards, John On Sun, Nov 9, 2014 at 4:32 PM, Fabio Estevam feste...@gmail.com wrote: On Sun, Nov 9, 2014 at 10:27 PM, John Tobias john.tobias...@gmail.com wrote: That's exactly that I am going to ask you. Because, some people in the community doesn't need the SPL. I think this will need a separate config files (e.g mx6slevk_spl_defconfig, mx6qsabresd_spl_defconfig) Yes, exacly, but I would prefere mx6sabresd_spl (without the 'q'), so that in the future we can support imx6q-sabresd and imx6dl-sabresd with a single binary using SPL. Thanks, Fabio Estevam ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v4 0/3] Add board level usb support for mxsxsabresd and mx6slevk
Changes v4: - Take Marek's suggestions, implement usb_phy_mode function and introduce a weak function board_usb_phy_mode. - change usb_phy_enable's return value with 0. - reimplement board_usb_phy_mode in board code. - add prototype type for board_usb_phy_mode and usb_phy_mode Changes v3: - Take Marek's suggestions, replace 'return val USBPHY_CTRL_OTG_ID' with this new function like 'return board_usb_phy_mode(index);' Detailed discussion here: http://lists.denx.de/pipermail/u-boot/2014-November/194131.html Changes v2: - Introduce a new weak function to let board have a choice to decide which mode to work at. - move pinmux setting into board_init - add otg polarity setting in board_ehci_hcd_init - set pinmux struct static Peng Fan (3): usb:ehci-mx6 add phy mode query function imx:mx6sxsabresd add board level support for usb imx:mx6slevk add board level support for usb arch/arm/include/asm/arch-mx6/mx6sl_pins.h | 5 +++ board/freescale/mx6slevk/mx6slevk.c | 49 + board/freescale/mx6sxsabresd/mx6sxsabresd.c | 49 + drivers/usb/host/ehci-mx6.c | 27 ++-- include/configs/mx6slevk.h | 14 + include/configs/mx6sxsabresd.h | 14 + include/usb/ehci-fsl.h | 2 ++ 7 files changed, 158 insertions(+), 2 deletions(-) -- 1.8.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v4 2/3] imx:mx6sxsabresd add board level support for usb
Add pinmux settings, implement board_ehci_hcd_init, board_usb_phy_mode
There are two usb port on mx6sxsabresd board:
1. otg port
2. host port
The following are the connection between usb controller and board usb
interface, host port has not ID pin set:
otg1 core --- board otg port
otg2 core --- board host port
In order to make host port work, board_usb_phy_mode return USB_INIT_HOST
to make host port work in HOST mode.
Signed-off-by: Peng Fan peng@freescale.com
Signed-off-by: Ye Li b37...@freescale.com
---
Changes v4:
reimplement board_usb_phy_mode.
Changes v3:
Take Marek's suggestions, replace 'return val USBPHY_CTRL_OTG_ID' with
this new function like 'return board_usb_phy_mode(index);'
Here board_usb_phy_mode only has one parameter 'index' as board_ehci_power and
board_echi_hcd_init do.
http://lists.denx.de/pipermail/u-boot/2014-November/194183.html; has detailed
discussion.
Changes v2:
Introduce a new weak function to let board have a choice to decide which mode
to work at.
board/freescale/mx6sxsabresd/mx6sxsabresd.c | 49 +
include/configs/mx6sxsabresd.h | 14 +
2 files changed, 63 insertions(+)
diff --git a/board/freescale/mx6sxsabresd/mx6sxsabresd.c
b/board/freescale/mx6sxsabresd/mx6sxsabresd.c
index 256ea29..5aed8d2 100644
--- a/board/freescale/mx6sxsabresd/mx6sxsabresd.c
+++ b/board/freescale/mx6sxsabresd/mx6sxsabresd.c
@@ -25,6 +25,8 @@
#include netdev.h
#include power/pmic.h
#include power/pfuze100_pmic.h
+#include usb.h
+#include usb/ehci-fsl.h
DECLARE_GLOBAL_DATA_PTR;
@@ -271,6 +273,49 @@ int board_mmc_init(bd_t *bis)
return fsl_esdhc_initialize(bis, usdhc_cfg[0]);
}
+#ifdef CONFIG_USB_EHCI_MX6
+#define USB_OTHERREGS_OFFSET 0x800
+#define UCTRL_PWR_POL (1 9)
+
+static iomux_v3_cfg_t const usb_otg_pads[] = {
+ /* OGT1 */
+ MX6_PAD_GPIO1_IO09__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_GPIO1_IO10__ANATOP_OTG1_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* OTG2 */
+ MX6_PAD_GPIO1_IO12__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)
+};
+
+static void setup_usb(void)
+{
+ imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
+ARRAY_SIZE(usb_otg_pads));
+}
+
+int board_usb_phy_mode(int port)
+{
+ if (port == 1)
+ return USB_INIT_HOST;
+ else
+ return usb_phy_mode(port);
+}
+
+int board_ehci_hcd_init(int port)
+{
+ u32 *usbnc_usb_ctrl;
+
+ if (port 1)
+ return -EINVAL;
+
+ usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
+port * 4);
+
+ /* Set Power polarity */
+ setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
+
+ return 0;
+}
+#endif
+
int board_init(void)
{
/* Address of boot parameters */
@@ -280,6 +325,10 @@ int board_init(void)
setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, i2c_pad_info1);
#endif
+#ifdef CONFIG_USB_EHCI_MX6
+ setup_usb();
+#endif
+
return 0;
}
diff --git a/include/configs/mx6sxsabresd.h b/include/configs/mx6sxsabresd.h
index e02ea18..8edf187 100644
--- a/include/configs/mx6sxsabresd.h
+++ b/include/configs/mx6sxsabresd.h
@@ -198,6 +198,20 @@
#define CONFIG_PHYLIB
#define CONFIG_PHY_ATHEROS
+
+#define CONFIG_CMD_USB
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_MX6
+#define CONFIG_USB_STORAGE
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_ASIX
+#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS 0
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+#endif
+
#define CONFIG_CMD_PCI
#ifdef CONFIG_CMD_PCI
#define CONFIG_PCI
--
1.8.4
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[U-Boot] [PATCH v4 1/3] usb:ehci-mx6 add phy mode query function
usb_phy_enable should return status bit, but not phy mode bit, thus
add a new function usb_phy_mode to query the PHY for it's mode and
make usb_phy_enable just return 0 but not 'phy_ctrl USBPHY_CTRL_OTG_ID'.
Include a new board weak function board_usb_phy_mode. If board code
does not reimplement this function, it just call usb_phy_mode and return
usb_phy_mode's return value. The reason to include such a weak function
is: SOC OTG core --connect-- board HOST port, but no pin id for
the board host port, so board can not use usb_phy_mode to return the
phy mode, but define it's own rule.
Signed-off-by: Peng Fan peng@freescale.com
Signed-off-by: Ye Li b37...@freescale.com
---
Changes v4:
- Take Marek's suggestions, implement usb_phy_mode function and
introduce a weak function board_usb_phy_mode.
- change usb_phy_enable's return value with 0.
- add prototype for board_usb_phy_mode and usb_phy_mode
Changes v3:
- Take Marek's suggestions, replace 'return val USBPHY_CTRL_OTG_ID' with
this new function like 'return board_usb_phy_mode(index);'
Here board_usb_phy_mode only has one parameter 'index' as board_ehci_power and
board_echi_hcd_init do.
http://lists.denx.de/pipermail/u-boot/2014-November/194183.html; has detailed
discussion.
Changes v2:
- Introduce a new weak function to let board have a choice to decide which mode
to work at.
drivers/usb/host/ehci-mx6.c | 27 +--
include/usb/ehci-fsl.h | 2 ++
2 files changed, 27 insertions(+), 2 deletions(-)
diff --git a/drivers/usb/host/ehci-mx6.c b/drivers/usb/host/ehci-mx6.c
index 9ec5a0a..951dd3b 100644
--- a/drivers/usb/host/ehci-mx6.c
+++ b/drivers/usb/host/ehci-mx6.c
@@ -160,7 +160,7 @@ static int usb_phy_enable(int index, struct usb_ehci *ehci)
val |= (USBPHY_CTRL_ENUTMILEVEL2 | USBPHY_CTRL_ENUTMILEVEL3);
__raw_writel(val, phy_ctrl);
- return val USBPHY_CTRL_OTG_ID;
+ return 0;
}
/* Base address for this IP block is 0x02184800 */
@@ -193,6 +193,28 @@ static void usb_oc_config(int index)
__raw_writel(val, ctrl);
}
+int usb_phy_mode(int port)
+{
+ void __iomem *phy_reg;
+ void __iomem *phy_ctrl;
+ u32 val;
+
+ phy_reg = (void __iomem *)phy_bases[port];
+ phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL);
+
+ val = __raw_readl(phy_ctrl);
+
+ if (val USBPHY_CTRL_OTG_ID)
+ return USB_INIT_DEVICE;
+ else
+ return USB_INIT_HOST;
+}
+
+int __weak board_usb_phy_mode(int port)
+{
+ return usb_phy_mode(port);
+}
+
int __weak board_ehci_hcd_init(int port)
{
return 0;
@@ -221,7 +243,8 @@ int ehci_hcd_init(int index, enum usb_init_type init,
usb_power_config(index);
usb_oc_config(index);
usb_internal_phy_clock_gate(index, 1);
- type = usb_phy_enable(index, ehci) ? USB_INIT_DEVICE : USB_INIT_HOST;
+ usb_phy_enable(index, ehci);
+ type = board_usb_phy_mode(index);
*hccr = (struct ehci_hccr *)((uint32_t)ehci-caplength);
*hcor = (struct ehci_hcor *)((uint32_t)*hccr +
diff --git a/include/usb/ehci-fsl.h b/include/usb/ehci-fsl.h
index dd77ad6..22114c1 100644
--- a/include/usb/ehci-fsl.h
+++ b/include/usb/ehci-fsl.h
@@ -277,7 +277,9 @@ struct usb_ehci {
#define MXC_EHCI_IPPUE_DOWN(1 10)
#define MXC_EHCI_IPPUE_UP (1 11)
+int usb_phy_mode(int port);
/* Board-specific initialization */
int board_ehci_hcd_init(int port);
+int board_usb_phy_mode(int port);
#endif /* _EHCI_FSL_H */
--
1.8.4
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[U-Boot] [PATCH 3/3] imx:mx6slevk add board level support for usb
Add pinmux settings, implement board_ehci_hcd_init, board_usb_phy_mode
There are two usb port on mx6slevk board:
1. otg port
2. host port
The following are the connection between usb controller and board usb
interface, host port has not ID pin set:
otg1 core --- board otg port
otg2 core --- board host port
In order to make host port work, board_usb_phy_mode return USB_INIT_HOST
to let host port work in host mode.
Signed-off-by: Peng Fan peng@freescale.com
Signed-off-by: Ye Li b37...@freescale.com
---
Changes v4:
reimplement board_usb_phy_mode
Changes v3:
implement board_usb_phy_mode
Changes v2:
Add otg polarity setting
move pinmux into board_init
set pinmux setting static
arch/arm/include/asm/arch-mx6/mx6sl_pins.h | 5 +++
board/freescale/mx6slevk/mx6slevk.c| 49 ++
include/configs/mx6slevk.h | 14 +
3 files changed, 68 insertions(+)
diff --git a/arch/arm/include/asm/arch-mx6/mx6sl_pins.h
b/arch/arm/include/asm/arch-mx6/mx6sl_pins.h
index d9db58c..9ded3d8 100644
--- a/arch/arm/include/asm/arch-mx6/mx6sl_pins.h
+++ b/arch/arm/include/asm/arch-mx6/mx6sl_pins.h
@@ -53,5 +53,10 @@ enum {
MX6_PAD_FEC_REF_CLK__FEC_REF_OUT=
IOMUX_PAD(0x424, 0x134, 0x10, 0x000, 0, 0),
MX6_PAD_FEC_RX_ER__GPIO_4_19=
IOMUX_PAD(0x0428, 0x0138, 5, 0x, 0, 0),
MX6_PAD_FEC_TX_CLK__GPIO_4_21 =
IOMUX_PAD(0x0434, 0x0144, 5, 0x, 0, 0),
+
+ MX6_PAD_EPDC_PWRCOM__ANATOP_USBOTG1_ID =
IOMUX_PAD(0x03D0, 0x00E0, 4, 0x05DC, 0, 0),
+
+ MX6_PAD_KEY_COL4__USB_USBOTG1_PWR =
IOMUX_PAD(0x0484, 0x017C, 6, 0x, 0, 0),
+ MX6_PAD_KEY_COL5__USB_USBOTG2_PWR =
IOMUX_PAD(0x0488, 0x0180, 6, 0x, 0, 0),
};
#endif /* __ASM_ARCH_MX6_MX6SL_PINS_H__ */
diff --git a/board/freescale/mx6slevk/mx6slevk.c
b/board/freescale/mx6slevk/mx6slevk.c
index e76c343..3ae2c46 100644
--- a/board/freescale/mx6slevk/mx6slevk.c
+++ b/board/freescale/mx6slevk/mx6slevk.c
@@ -20,6 +20,8 @@
#include fsl_esdhc.h
#include mmc.h
#include netdev.h
+#include usb.h
+#include usb/ehci-fsl.h
DECLARE_GLOBAL_DATA_PTR;
@@ -243,6 +245,48 @@ static int setup_fec(void)
}
#endif
+#ifdef CONFIG_USB_EHCI_MX6
+#define USB_OTHERREGS_OFFSET 0x800
+#define UCTRL_PWR_POL (1 9)
+
+static iomux_v3_cfg_t const usb_otg_pads[] = {
+ /* OTG1 */
+ MX6_PAD_KEY_COL4__USB_USBOTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_EPDC_PWRCOM__ANATOP_USBOTG1_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* OTG2 */
+ MX6_PAD_KEY_COL5__USB_USBOTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)
+};
+
+static void setup_usb(void)
+{
+ imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
+ARRAY_SIZE(usb_otg_pads));
+}
+
+int board_usb_phy_mode(int port)
+{
+ if (port == 1)
+ return USB_INIT_HOST;
+ else
+ return usb_phy_mode(port);
+}
+
+int board_ehci_hcd_init(int port)
+{
+ u32 *usbnc_usb_ctrl;
+
+ if (port 1)
+ return -EINVAL;
+
+ usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
+port * 4);
+
+ /* Set Power polarity */
+ setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
+
+ return 0;
+}
+#endif
int board_early_init_f(void)
{
@@ -261,6 +305,11 @@ int board_init(void)
#ifdef CONFIG_FEC_MXC
setup_fec();
#endif
+
+#ifdef CONFIG_USB_EHCI_MX6
+ setup_usb();
+#endif
+
return 0;
}
diff --git a/include/configs/mx6slevk.h b/include/configs/mx6slevk.h
index 4fcaf51..bd57159 100644
--- a/include/configs/mx6slevk.h
+++ b/include/configs/mx6slevk.h
@@ -209,6 +209,20 @@
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
#endif
+/* USB Configs */
+#define CONFIG_CMD_USB
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_MX6
+#define CONFIG_USB_STORAGE
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_ASIX
+#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS 0
+#define CONFIG_USB_MAX_CONTROLLER_COUNT2
+#endif
+
#define CONFIG_SYS_FSL_USDHC_NUM 3
#if defined(CONFIG_ENV_IS_IN_MMC)
#define CONFIG_SYS_MMC_ENV_DEV 1 /* SDHC2*/
--
1.8.4
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Re: [U-Boot] [PATCH v3 1/3] usb:ehci-mx6 add board_usb_phy_mode function
On 11/8/2014 7:33 PM, Marek Vasut wrote:
On Saturday, November 08, 2014 at 05:07:21 AM, Peng Fan wrote:
在 11/7/2014 8:17 PM, Marek Vasut 写道:
On Friday, November 07, 2014 at 12:45:51 PM, Peng Fan wrote:
在 11/7/2014 7:09 PM, Marek Vasut 写道:
On Friday, November 07, 2014 at 12:03:30 PM, Peng Fan wrote:
[...]
@@ -160,7 +174,7 @@ static int usb_phy_enable(int index, struct
usb_ehci *ehci) val |= (USBPHY_CTRL_ENUTMILEVEL2 |
USBPHY_CTRL_ENUTMILEVEL3);
__raw_writel(val, phy_ctrl);
- return val USBPHY_CTRL_OTG_ID;
+ return board_usb_phy_mode(index);
This should be called from ehci_hcd_init() right after
usb_phy_enable(). Afterall, the mode detection has nothing to do with
the PHY enabling.
This back to what I did in patch v2. right after usb_phy_enable(),
just paste that piece of code here:
The weak function:
+int __weak board_ehci_usb_mode(int index, enum usb_init_type *type)
+{
+ return 0;
+}
+
type = usb_phy_enable(index, ehci) ? USB_INIT_DEVICE :
USB_INIT_HOST;
+ board_usb_phy_mode(index, type);
+
The usb_phy_enable() should not return the PHY mode at all though.
It should be the board_usb_phy_mode() which adjusts the PHY type.
The usb_phy_enable() should return just a success/failure return
value.
ok. got it.
What need to do is to let board can modify the `type` like following:
+int board_usb_phy_mode(int port, enum usb_init_type *type)
+{
+ if (port == 1)
+ /* port1 works in HOST Mode */
+ *type = USB_INIT_HOST;
+
+ return 0;
+}
+
This is the way that I did in patch v2. If this is fine, I'll resent
this patch set.
It should really explicitly set it, not modify it, see above.
I have an idea about this patch:
1. usb_phy_enable will not be touched.
2. replace type = usb_phy_enable(index, ehci) ? USB_INIT_DEVICE :
USB_INIT_HOST; with usb_phy_enable(index, ehci).
3. right after usb_phy_enable, add this line type =
board_usb_phy_mode(index) or type = board_usb_phy_mode((struct usb_phy
*)PHY_ADDRESS). Here I also think pass phy register definition to board
level code is not fine just as what we talked about passing ehci struct
to board level code in patch v2.
4. in ehci-mx6.c, implement the weak function int __weak
board_usb_phy_mode(xxx), and it's return value is the mode, HOST or
DEVICE. If the board code want to implement this function, just return
what the board want.
After all, this patch may looks like this:
In ehci-mx6.c
+int __weak board_usb_phy_mode(int port)
+{
+ void __iomem *phy_reg;
+ void __iomem *phy_ctrl;
+ u32 val;
+
+ phy_reg = (void __iomem *)phy_bases[port];
+ phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL);
+
+ val = __raw_readl(phy_ctrl);
+
+ return val USBPHY_CTRL_OTG_ID;
+}
+
- type = usb_phy_enable(index, ehci) ? USB_INIT_DEVICE : USB_INIT_HOST;
+ usb_phy_enable(index, ehci);
+ type = board_usb_phy_mode(index);
in board code, which is not in this patch, just list here:
+int board_usb_phy_mode(int port)
+{
+ if (port == 1)
+ return USB_INIT_HOST;
+ else
+ return USB_INIT_DEVICE;
+}
I just want to keep it simple and do not want to touch usb phy register
in board code.
Any ideas?
This seems OKish for all but the part where usb_phy_enable() shouldn't be
touched. The return value of usb_phy_enable() should really be a regular
return code, not the PHY mode.
ok. I'll fix this.
You can also still implement a function to query a PHY for it's mode, so
you don't need to explicitly read the USBPHY_CTRL_OTG_ID in the board
code.
I am not sure whether this following way is fine or not.
+int board_usb_phy_mode(int index)
+ __attribute__((weak, alias(usb_phy_mode)));
__weak board_usb_phy_mode(int index) is fine.
+
in usb_phy_mode, query a PHY for it's mode.
And righter after usb_phy_enable in ehci-mx6.c.
- type = usb_phy_enable(index, ehci) ? USB_INIT_DEVICE :
USB_INIT_HOST;
+ usb_phy_enable(index, ehci);
+ type = usb_phy_mode(index);
usb_phy_enable return 0 but not return val USBPHY_CTRL_OTG_ID. There
is no status bit for query enabled or not, so just return 0.
In board file:
int board_usb_phy_mode(int port)
{
if (port == 1)
return USB_INIT_HOST;
else
return usb_phy_mode(port);
}
I think this is better way then previous patch, but i did not find where
to put the usb_phy_mode prototype type, since board file will use it.
Looks OK otherwise.
Sent out v4 patch, please review.
Thanks,
Peng.
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[U-Boot] [PATCH v6 3/3] Odroid-XU3: Add documentation for Odroid-XU3
This patch adds documentation for Odroid-XU3. This documentation is based on that of Odroid (doc/README-odroid) made by Przemyslaw Marczak. The documentation includes basic information about boot media layout, environment, partition layout, and the instruction to burn the u-boot image to boot media. Signed-off-by: Hyungwon Hwang human.hw...@samsung.com Cc: Minkyu Kang mk7.k...@samsung.com Cc: Lukasz Majewski l.majew...@samsung.com --- Changes for v6: - Newly added doc/README.odroid-xu3 | 134 ++ 1 file changed, 134 insertions(+) create mode 100644 doc/README.odroid-xu3 diff --git a/doc/README.odroid-xu3 b/doc/README.odroid-xu3 new file mode 100644 index 000..8e1f333 --- /dev/null +++ b/doc/README.odroid-xu3 @@ -0,0 +1,134 @@ + U-boot for Odroid XU3 + + +1. Summary +== +This is a quick instruction for setup Odroid boards based on Exynos5422. +Exynos5422 is almost same with Exynos5800 which is a variant of Exynos5422 for +Chromebook. + +Board config: odroid-xu3_config + +2. Supported devices + +This U-BOOT config can be used on the board: +- Odroid XU3 +with CPU Exynos 5422 and 2GB of RAM + +3. Boot sequence + +iROM-BL1-(BL2 + TrustZone)-U-BOOT + +To boot up, this version of U-BOOT needs BL1, BL2, and TrustZone binary. +It can be downloaded from: +https://github.com/hardkernel/u-boot/tree/odroidxu3-v2012.07/sd_fuse/hardkernel + +4. Boot media layout + +The table below shows SD/eMMC cards layout for U-boot. +The block offset is starting from 0 and the block size is 512B. + - +| Binary | Block offset| part type | +| name| SD | eMMC |(eMMC only)| + - +| Bl1 | 1| 0| 1 (boot) | +| Bl2 | 31 | 30 | 1 (boot) | +| U-boot| 63 | 62 | 1 (boot) | +| Tzsw | 2111 | 2110 | 1 (boot) | +| Uboot Env | 2500 | 2500 | 0 (user) | + - + +5. Prepare the SD boot card - with SD card reader += +To prepare bootable media you need boot binaries provided by hardkernel. +The files from the link in point 3. +- bl1.bin.hardkernel +- bl2.bin.hardkernel +- tzsw.bin.hardkernel +- u-boot.bin.hardkernel + +This is all you need to boot this board. You can write the binaries to SD card +just by executiog sd_fusing.sh. You cannot use this script to write binaries to +eMMC card.It is valid only for SD card. + +*note +You cannot access the eMMC protected part (the first 8MB roughly) using an +ordinary eMMC reader. + +*note: +If you build u-boot by yourself, you will find u-boot.bin and u-boot-dtb.bin +as the build result. You have to use u-boot-dtb.bin instead of u-boot.bin. + +quick steps for Linux: +- Download all files from the link at point 3. +- put any SD card into the SD reader +- check the device with dmesg +- run ./sd_fusing.sh /dev/sdX - where X is SD card device (but not a partition) +Check if Hardkernel U-boot is booting, and next do the same with your U-boot. + +6. Prepare the eMMC boot card + with a eMMC card reader (boot from eMMC card slot) += +To boot the device from the eMMC slot you should use a special card reader +which supports eMMC partition switch. All of the boot binaries are stored +on the eMMC boot partition which is normally hidden. + +The sd_fusing.sh script can be used after updating offsets of binaries +according to the table from point 4. Be sure that you are working on the right +eMMC partition - its size is usually very small, about 1-4 MiB. + +7. Prepare the eMMC boot card + with a SD card reader (boot from SD card slot) += +If you have an eMMC-microSD adapter you can prepare the card as in point 5. +But then the device can boot only from the SD card slot. + +8. Prepare the boot media using Hardkernel U-boot += +You can update the U-boot to the custom one if you have an working bootloader +delivered with the board on a eMMC/SD card. Then follow the steps: +- install the android fastboot tool +- connect a micro usb cable to the board +- on the U-boot prompt, run command: fastboot (as a root) +- on the host, run command: fastboot flash bootloader u-boot-dtb.bin +- the custom U-boot should start after the board resets. + +9. Partition layout + +Default U-boot environment is setup for fixed partition layout. + +Partition table: MSDOS. Disk layout and files as listed in the table below. + - -- -- -- - +| Num | Name | FS | Size | Offset | Reguired files | +| | | Type | MiB | MiB | | + - -- -- -- - +| 1 | BOOT | fat | 100 | 2
[U-Boot] [PATCH v6 0/3] Adds support for Exynos5422 odroid xu3 board
This is v6 of the patchset adding support Odroud XU3 board.
link to the previous version:
v2: https://www.mail-archive.com/u-boot@lists.denx.de/msg152275.html
v3: https://www.mail-archive.com/u-boot%40lists.denx.de/msg152677.html
v4: https://patchwork.ozlabs.org/patch/407411/
v5: https://patchwork.ozlabs.org/patch/407941/
This patchset fixes GPIO information of Exynos5420 which is needed to
support Exynos5422 Odroid XU3 board. On the base of the fixes, this
patchset adds support for Exynos5422 Odroid XU3 board. I have done this
work on the master branch in http://git.denx.de/u-boot-samsung.git (sha1:
26f195c71252e98aebfffd5cfa994a4475559370) with patches by Akshay Saraswat.
link: https://patchwork.ozlabs.org/patch/405246/ (updated)
How to test this patch:
1. git clone http://git.denx.de/u-boot-samsung.git
2. git reset --hard 26f195c71252e98aebfffd5cfa994a4475559370
3. Get and apply the patchset of Akshay Saraswat
https://patchwork.ozlabs.org/patch/405246/
https://patchwork.ozlabs.org/patch/405247/
https://patchwork.ozlabs.org/patch/405248/
https://patchwork.ozlabs.org/patch/405249/
https://patchwork.ozlabs.org/patch/405250/
https://patchwork.ozlabs.org/patch/405251/
https://patchwork.ozlabs.org/patch/405252/
4. Apply this patchset
5. make ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf- odroid-xu3_config
6. make ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf- -j8
7. Now you can use u-boot-dtb.bin for your downloading
Note: If you use micro SD card for your test you have to apply the below
patch additionally. This patch is needed, because micro sd card is
recognized as MMC1 instead of MMC0. Additional work is needed to make it
work regardless of device id.
diff --git a/include/configs/exynos5-common.h b/include/configs/exynos5-common.h
index ba591e7..437eaae 100644
--- a/include/configs/exynos5-common.h
+++ b/include/configs/exynos5-common.h
@@ -109,7 +109,7 @@
#define CONFIG_SYS_MONITOR_BASE0x
-#define CONFIG_SYS_MMC_ENV_DEV 0
+#define CONFIG_SYS_MMC_ENV_DEV 1
#define CONFIG_SECURE_BL1_ONLY
diff --git a/include/configs/odroid_xu3.h b/include/configs/odroid_xu3.h
index cda4f26..b46ccad 100644
--- a/include/configs/odroid_xu3.h
+++ b/include/configs/odroid_xu3.h
@@ -110,15 +110,15 @@
run kernel_args; \
bootz ${kerneladdr} ${initrd_addr} ${fdt_addr};\0 \
autoboot= \
- if test -e mmc 0 Image.itb; then; \
+ if test -e mmc 1 Image.itb; then; \
run boot_fit; \
- elif test -e mmc 0 zImage; then; \
+ elif test -e mmc 1 zImage; then; \
run boot_zimg; \
- elif test -e mmc 0 uImage; then; \
+ elif test -e mmc 1 uImage; then; \
run boot_uimg; \
fi;\0 \
console= CONFIG_DEFAULT_CONSOLE \
- mmcbootdev=0\0 \
+ mmcbootdev=1\0 \
mmcbootpart=1\0 \
mmcrootdev=0\0 \
mmcrootpart=2\0 \
Changes for v2:
- Add a patch to add new common setup header file for Odroid X2/U3
and Odroid XU3
Changes for v3:
- Remove the patch which adds new common setup header file from v2
- Remove the wrong patch to fix GPIO information of Exynos 5800
- Remove unnecessary node from DT file
- Remove unnecessary features from config file
- Fix some trivial typos in comments
Changes for v4:
- Add MMC FIFO buffer's configuration to DT file
- Make CONFIG_OF_CONTROL be set by the target information
- Add basic document to doc/README.odroid-xu3
- Add CONFIG_CMD_EXT4 to config file
- Add environment size and offset to config file
- Add extra default environment to make bootable without modification
- Remove unnecessary features from config file
Changes for v5:
- Add the specific build instruction
- Update the information of patchset by Akshay Saraswat
- Convert /include/ to #include in DT file
Chagnes for v6:
- Separate out the documentation to new commit
- Remove unnecessary header file inclusuib from the board-specific setup file
- Make the function board_clock_init be declared, only when
CONFIG_BOARD_EARLY_INIT_F is defined
Hyungwon Hwang (3):
exynos5: fix GPIO information of exynos5420
Odroid-XU3: Add support for Odroid-XU3
Odroid-XU3: Add documentation for Odroid-XU3
arch/arm/cpu/armv7/exynos/Kconfig | 5 +
arch/arm/dts/Makefile | 3 +-
arch/arm/dts/exynos5422-odroidxu3.dts | 60 +
arch/arm/include/asm/arch-exynos/cpu.h | 11 +-
arch/arm/include/asm/arch-exynos/gpio.h | 232 +++-
board/samsung/odroid-xu3/Kconfig| 12 ++
board/samsung/odroid-xu3/MAINTAINERS| 6 +
board/samsung/odroid-xu3/Makefile | 7 +
board/samsung/odroid-xu3/odroid-xu3.c | 122 +
board/samsung/odroid-xu3/setup.h| 95 +
configs/odroid-xu3_defconfig| 4 +
doc/README.odroid-xu3
[U-Boot] [PATCH v6 1/3] exynos5: fix GPIO information of exynos5420
This patch fixes wrong GPIO information such as GPIO bank, table which
is used to convert GPIO name to index, bank base address, and etc.
Signed-off-by: Hyungwon Hwang human.hw...@samsung.com
Cc: Minkyu Kang mk7.k...@samsung.com
Cc: Lukasz Majewski l.majew...@samsung.com
---
Changes for v4:
- None
Changes for v5:
- None
Changes for v6:
- None
arch/arm/include/asm/arch-exynos/cpu.h | 11 +-
arch/arm/include/asm/arch-exynos/gpio.h | 232 +++-
2 files changed, 117 insertions(+), 126 deletions(-)
diff --git a/arch/arm/include/asm/arch-exynos/cpu.h
b/arch/arm/include/asm/arch-exynos/cpu.h
index 29674ad..48936de 100644
--- a/arch/arm/include/asm/arch-exynos/cpu.h
+++ b/arch/arm/include/asm/arch-exynos/cpu.h
@@ -148,7 +148,7 @@
/* EXYNOS5420 */
#define EXYNOS5420_AUDIOSS_BASE0x0381
-#define EXYNOS5420_GPIO_PART6_BASE 0x0386
+#define EXYNOS5420_GPIO_PART5_BASE 0x0386
#define EXYNOS5420_PRO_ID 0x1000
#define EXYNOS5420_CLOCK_BASE 0x1001
#define EXYNOS5420_POWER_BASE 0x1004
@@ -170,11 +170,10 @@
#define EXYNOS5420_I2S_BASE0x12D6
#define EXYNOS5420_PWMTIMER_BASE 0x12DD
#define EXYNOS5420_SPI_ISP_BASE0x131A
-#define EXYNOS5420_GPIO_PART2_BASE 0x1340
-#define EXYNOS5420_GPIO_PART3_BASE 0x13400C00
-#define EXYNOS5420_GPIO_PART4_BASE 0x1341
-#define EXYNOS5420_GPIO_PART5_BASE 0x1400
-#define EXYNOS5420_GPIO_PART1_BASE 0x1401
+#define EXYNOS5420_GPIO_PART1_BASE 0x1340
+#define EXYNOS5420_GPIO_PART2_BASE 0x1341
+#define EXYNOS5420_GPIO_PART3_BASE 0x1400
+#define EXYNOS5420_GPIO_PART4_BASE 0x1401
#define EXYNOS5420_MIPI_DSIM_BASE 0x1450
#define EXYNOS5420_DP_BASE 0x145B
diff --git a/arch/arm/include/asm/arch-exynos/gpio.h
b/arch/arm/include/asm/arch-exynos/gpio.h
index 9699954..aef897d 100644
--- a/arch/arm/include/asm/arch-exynos/gpio.h
+++ b/arch/arm/include/asm/arch-exynos/gpio.h
@@ -1042,83 +1042,7 @@ enum exynos5_gpio_pin {
};
enum exynos5420_gpio_pin {
- /* GPIO_PART1_STARTS */
- EXYNOS5420_GPIO_A00,/* 0 */
- EXYNOS5420_GPIO_A01,
- EXYNOS5420_GPIO_A02,
- EXYNOS5420_GPIO_A03,
- EXYNOS5420_GPIO_A04,
- EXYNOS5420_GPIO_A05,
- EXYNOS5420_GPIO_A06,
- EXYNOS5420_GPIO_A07,
- EXYNOS5420_GPIO_A10,/* 8 */
- EXYNOS5420_GPIO_A11,
- EXYNOS5420_GPIO_A12,
- EXYNOS5420_GPIO_A13,
- EXYNOS5420_GPIO_A14,
- EXYNOS5420_GPIO_A15,
- EXYNOS5420_GPIO_A16,
- EXYNOS5420_GPIO_A17,
- EXYNOS5420_GPIO_A20,/* 16 0x10 */
- EXYNOS5420_GPIO_A21,
- EXYNOS5420_GPIO_A22,
- EXYNOS5420_GPIO_A23,
- EXYNOS5420_GPIO_A24,
- EXYNOS5420_GPIO_A25,
- EXYNOS5420_GPIO_A26,
- EXYNOS5420_GPIO_A27,
- EXYNOS5420_GPIO_B00,/* 24 0x18 */
- EXYNOS5420_GPIO_B01,
- EXYNOS5420_GPIO_B02,
- EXYNOS5420_GPIO_B03,
- EXYNOS5420_GPIO_B04,
- EXYNOS5420_GPIO_B05,
- EXYNOS5420_GPIO_B06,
- EXYNOS5420_GPIO_B07,
- EXYNOS5420_GPIO_B10,/* 32 0x20 */
- EXYNOS5420_GPIO_B11,
- EXYNOS5420_GPIO_B12,
- EXYNOS5420_GPIO_B13,
- EXYNOS5420_GPIO_B14,
- EXYNOS5420_GPIO_B15,
- EXYNOS5420_GPIO_B16,
- EXYNOS5420_GPIO_B17,
- EXYNOS5420_GPIO_B20,/* 40 0x28 */
- EXYNOS5420_GPIO_B21,
- EXYNOS5420_GPIO_B22,
- EXYNOS5420_GPIO_B23,
- EXYNOS5420_GPIO_B24,
- EXYNOS5420_GPIO_B25,
- EXYNOS5420_GPIO_B26,
- EXYNOS5420_GPIO_B27,
- EXYNOS5420_GPIO_B30,/* 48 0x30 */
- EXYNOS5420_GPIO_B31,
- EXYNOS5420_GPIO_B32,
- EXYNOS5420_GPIO_B33,
- EXYNOS5420_GPIO_B34,
- EXYNOS5420_GPIO_B35,
- EXYNOS5420_GPIO_B36,
- EXYNOS5420_GPIO_B37,
- EXYNOS5420_GPIO_B40,/* 56 0x38 */
- EXYNOS5420_GPIO_B41,
- EXYNOS5420_GPIO_B42,
- EXYNOS5420_GPIO_B43,
- EXYNOS5420_GPIO_B44,
- EXYNOS5420_GPIO_B45,
- EXYNOS5420_GPIO_B46,
- EXYNOS5420_GPIO_B47,
- EXYNOS5420_GPIO_H00,/* 64 0x40 */
- EXYNOS5420_GPIO_H01,
- EXYNOS5420_GPIO_H02,
- EXYNOS5420_GPIO_H03,
- EXYNOS5420_GPIO_H04,
- EXYNOS5420_GPIO_H05,
- EXYNOS5420_GPIO_H06,
- EXYNOS5420_GPIO_H07,
-
- /* GPIO PART 2 STARTS*/
- EXYNOS5420_GPIO_MAX_PORT_PART_1,/* 72 0x48 */
- EXYNOS5420_GPIO_Y70 = EXYNOS5420_GPIO_MAX_PORT_PART_1,
+ EXYNOS5420_GPIO_Y70,
EXYNOS5420_GPIO_Y71,
EXYNOS5420_GPIO_Y72,
EXYNOS5420_GPIO_Y73,
@@ -1126,10 +1050,7 @@ enum exynos5420_gpio_pin {
EXYNOS5420_GPIO_Y75,
EXYNOS5420_GPIO_Y76,
EXYNOS5420_GPIO_Y77,
-
- /* GPIO PART 3 STARTS*/
- EXYNOS5420_GPIO_MAX_PORT_PART_2,/* 80 0x50 */
-
[U-Boot] [PATCH v6 2/3] Odroid-XU3: Add support for Odroid-XU3
This patch adds support for Odroid-XU3.
Signed-off-by: Hyungwon Hwang human.hw...@samsung.com
Cc: Minkyu Kang mk7.k...@samsung.com
Cc: Lukasz Majewski l.majew...@samsung.com
---
Changes for v3:
- Remove unnecessary node from DT file
- Remove unnecessary features from config file
- Remove unnecessary macros from board-specific header file
- Fix some trivial typos in comments
Changes for v4:
- Add MMC FIFO buffer's configuration to DT file
- Make CONFIG_OF_CONTROL be set by the target information
- Add basic document to doc/README.odroid-xu3
- Add CONFIG_CMD_EXT4 to config file
- Add environment size and offset to config file
- Add extra default environment to make bootable without modification
- Remove unnecessary features from config file
Changes for v5:
- Convert /include/ to #include in DT file
Changes for v6:
- Separate out the documentation to new commit
- Remove unnecessary header file inclusions from the board-specific setup file
- Make the function board_clock_init be declared, only when
CONFIG_BOARD_EARLY_INIT_F is defined
arch/arm/cpu/armv7/exynos/Kconfig | 5 ++
arch/arm/dts/Makefile | 3 +-
arch/arm/dts/exynos5422-odroidxu3.dts | 60 ++
board/samsung/odroid-xu3/Kconfig | 12 +++
board/samsung/odroid-xu3/MAINTAINERS | 6 ++
board/samsung/odroid-xu3/Makefile | 7 ++
board/samsung/odroid-xu3/odroid-xu3.c | 122
board/samsung/odroid-xu3/setup.h | 95 ++
configs/odroid-xu3_defconfig | 4 +
include/configs/odroid_xu3.h | 144 ++
10 files changed, 457 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/dts/exynos5422-odroidxu3.dts
create mode 100644 board/samsung/odroid-xu3/Kconfig
create mode 100644 board/samsung/odroid-xu3/MAINTAINERS
create mode 100644 board/samsung/odroid-xu3/Makefile
create mode 100644 board/samsung/odroid-xu3/odroid-xu3.c
create mode 100644 board/samsung/odroid-xu3/setup.h
create mode 100644 configs/odroid-xu3_defconfig
create mode 100644 include/configs/odroid_xu3.h
diff --git a/arch/arm/cpu/armv7/exynos/Kconfig
b/arch/arm/cpu/armv7/exynos/Kconfig
index 13dbd95..8fe530c 100644
--- a/arch/arm/cpu/armv7/exynos/Kconfig
+++ b/arch/arm/cpu/armv7/exynos/Kconfig
@@ -24,6 +24,10 @@ config TARGET_TRATS2
config TARGET_ODROID
bool Exynos4412 Odroid board
+config TARGET_ODROID_XU3
+ bool Exynos5422 Odroid board
+ select OF_CONTROL if !SPL_BUILD
+
config TARGET_ARNDALE
bool Exynos5250 Arndale board
select SUPPORT_SPL
@@ -65,6 +69,7 @@ source board/samsung/universal_c210/Kconfig
source board/samsung/origen/Kconfig
source board/samsung/trats2/Kconfig
source board/samsung/odroid/Kconfig
+source board/samsung/odroid-xu3/Kconfig
source board/samsung/arndale/Kconfig
source board/samsung/smdk5250/Kconfig
source board/samsung/smdk5420/Kconfig
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 2b9bd93..d984f34 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -12,7 +12,8 @@ dtb-$(CONFIG_EXYNOS5) += exynos5250-arndale.dtb \
exynos5250-smdk5250.dtb \
exynos5420-smdk5420.dtb \
exynos5420-peach-pit.dtb \
- exynos5800-peach-pi.dtb
+ exynos5800-peach-pi.dtb \
+ exynos5422-odroidxu3.dtb
dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \
tegra20-medcom-wide.dtb \
tegra20-paz00.dtb \
diff --git a/arch/arm/dts/exynos5422-odroidxu3.dts
b/arch/arm/dts/exynos5422-odroidxu3.dts
new file mode 100644
index 000..52199d9
--- /dev/null
+++ b/arch/arm/dts/exynos5422-odroidxu3.dts
@@ -0,0 +1,60 @@
+/*
+ * Odroid XU3 device tree source
+ *
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+/dts-v1/;
+#include exynos54xx.dtsi
+
+/ {
+ model = Odroid XU3 based on EXYNOS5422;
+ compatible = samsung,odroidxu3, samsung,exynos5;
+
+ aliases {
+ serial0 = /serial@12C0;
+ console = /serial@12C2;
+ };
+
+ memory {
+ device_type = memory;
+ reg = 0x4000 0x1000
+ 0x5000 0x1000
+ 0x6000 0x1000
+ 0x7000 0x1000
+ 0x8000 0x1000
+ 0x9000 0x1000
+ 0xa000 0x1000
+ 0xb000 0xea0;
+ };
+
+ serial@12C2 {
+ status=okay;
+ };
+
+ mmc@1220 {
+ samsung,bus-width = 8;
+ samsung,timing = 1 3 3;
+ samsung,removable = 0;
+ samsung,pre-init;
+ fifoth_val = 0x200f0020;
+ };
+
+ mmc@1221 {
+ status = disabled;
+ };
+
+ mmc@1222 {
+ samsung,bus-width = 4;
+
Re: [U-Boot] [PATCH 31/39] x86: ivybridge: Check BIST value on boot
Hi Simon,
On Fri, Nov 7, 2014 at 4:20 AM, Simon Glass s...@chromium.org wrote:
The built-in self test value should be checked before we continue booting.
Refuse to continue if there is something wrong.
Signed-off-by: Simon Glass s...@chromium.org
---
arch/x86/cpu/ivybridge/cpu.c | 16
1 file changed, 16 insertions(+)
diff --git a/arch/x86/cpu/ivybridge/cpu.c b/arch/x86/cpu/ivybridge/cpu.c
index aa825c7..e73ccb7 100644
--- a/arch/x86/cpu/ivybridge/cpu.c
+++ b/arch/x86/cpu/ivybridge/cpu.c
@@ -177,10 +177,26 @@ int arch_cpu_init(void)
return 0;
}
+static int report_bist_failure(void)
+{
+ if (gd-arch.bist != 0) {
+ printf(BIST failed: %08x\n, gd-arch.bist);
+ return -EFAULT;
+ }
+
+ return 0;
+}
+
int print_cpuinfo(void)
{
I don't see patch that moves print_cpuinfo() from arch/x86/cpu/cpu.c
to this. Is there anything I missed?
[snip]
Regards,
Bin
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Re: [U-Boot] [PATCH 32/39] x86: ivybridge: Perform Intel microcode update on boot
Hi Simon, On Fri, Nov 7, 2014 at 4:20 AM, Simon Glass s...@chromium.org wrote: Microcode updates are stored in the device tree. Work through these and apply any that are needed. Signed-off-by: Simon Glass s...@chromium.org --- arch/x86/cpu/ivybridge/Makefile | 1 + arch/x86/cpu/ivybridge/cpu.c| 5 + arch/x86/cpu/ivybridge/microcode_intel.c| 150 arch/x86/include/asm/arch-ivybridge/microcode.h | 20 include/fdtdec.h| 1 + lib/fdtdec.c| 1 + 6 files changed, 178 insertions(+) create mode 100644 arch/x86/cpu/ivybridge/microcode_intel.c create mode 100644 arch/x86/include/asm/arch-ivybridge/microcode.h diff --git a/arch/x86/cpu/ivybridge/Makefile b/arch/x86/cpu/ivybridge/Makefile index ce16697..a3ea566 100644 --- a/arch/x86/cpu/ivybridge/Makefile +++ b/arch/x86/cpu/ivybridge/Makefile @@ -7,4 +7,5 @@ obj-y += car.o obj-y += cpu.o obj-y += lpc.o +obj-y += microcode_intel.o obj-y += sdram.o diff --git a/arch/x86/cpu/ivybridge/cpu.c b/arch/x86/cpu/ivybridge/cpu.c index e73ccb7..bd2660f 100644 --- a/arch/x86/cpu/ivybridge/cpu.c +++ b/arch/x86/cpu/ivybridge/cpu.c @@ -19,6 +19,7 @@ #include asm/post.h #include asm/processor.h #include asm/arch/model_206ax.h +#include asm/arch/microcode.h #include asm/arch/pch.h DECLARE_GLOBAL_DATA_PTR; @@ -198,6 +199,10 @@ int print_cpuinfo(void) if (ret) return ret; + ret = microcode_update_intel(); + if (ret ret != -ENOENT ret != -EEXIST) + return ret; + /* Print processor name */ name = cpu_get_name(processor_name); printf(CPU: %s\n, name); diff --git a/arch/x86/cpu/ivybridge/microcode_intel.c b/arch/x86/cpu/ivybridge/microcode_intel.c new file mode 100644 index 000..fbb55f2 --- /dev/null +++ b/arch/x86/cpu/ivybridge/microcode_intel.c @@ -0,0 +1,150 @@ +/* + * Copyright (c) 2014 Google, Inc + * Copyright (C) 2000 Ronald G. Minnich + * + * Microcode update for Intel PIII and later CPUs This comment suggests that the code is generic for all Intel CPUs, so should we move this code to arch/x86/lib? [snip] Regards, Bin ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 33/39] RFC: x86: dts: Add microcode updates for ivybridge CPU
Hi Simon,
On Fri, Nov 7, 2014 at 4:20 AM, Simon Glass s...@chromium.org wrote:
Add two microcode updates that are provided for this CPU. The updates
have been converted to a device tree form.
(The license needs to be converted to SPDX)
Signed-off-by: Simon Glass s...@chromium.org
---
arch/x86/dts/link.dts | 10 +
arch/x86/dts/m12206a7_0028.dtsi | 622 ++
arch/x86/dts/m12306a9_0017.dtsi | 750
3 files changed, 1382 insertions(+)
create mode 100644 arch/x86/dts/m12206a7_0028.dtsi
create mode 100644 arch/x86/dts/m12306a9_0017.dtsi
diff --git a/arch/x86/dts/link.dts b/arch/x86/dts/link.dts
index 2e91631..ea4b0ba 100644
--- a/arch/x86/dts/link.dts
+++ b/arch/x86/dts/link.dts
@@ -67,4 +67,14 @@
};
};
};
+
+ microcode {
+ update@0 {
+#include m12206a7_0028.dtsi
+ };
+ update@1 {
+#include m12306a9_0017.dtsi
+ };
+ };
+
};
diff --git a/arch/x86/dts/m12206a7_0028.dtsi
b/arch/x86/dts/m12206a7_0028.dtsi
new file mode 100644
index 000..bcd5248
--- /dev/null
+++ b/arch/x86/dts/m12206a7_0028.dtsi
@@ -0,0 +1,622 @@
+/*
+ * Copyright (c) 1995-2013, Intel Corporation.
+ * All rights reserved.
+ *
+ * Redistribution. Redistribution and use in binary form, without
modification, are
+ * permitted provided that the following conditions are met:
+ * .Redistributions must reproduce the above copyright notice and the
following
+ * disclaimer in the documentation and/or other materials provided with the
+ * distribution.
+ * Neither the name of Intel Corporation nor the names of its suppliers may
be used
+ * to endorse or promote products derived from this software without
specific prior
+ * written permission.
+ * .No reverse engineering, decompilation, or disassembly of this
software is
+ * permitted.
+ * .Binary form includes any format commonly used for electronic
conveyance
+ * which is a reversible, bit-exact translation of binary representation to
ASCII or
+ * ISO text, for example, uuencode.
+ *
+ * DISCLAIMER. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
+ * HOLDERS AND CONTRIBUTORS AS IS AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER
+ * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *---
+ * This is a device tree fragment. Use #include to add these properties to a
+ * node.
+ */
+
+compatible = intel,microcode;
+intel,header-version = 1;
+intel,update-revision = 0x28;
+intel,date-code = 0x04242012;
+intel,processor-signature = 0x000206a7;
+intel,checksum = 0xf3e9935d;
+intel,loader-revision = 1;
+intel,processor-flags = 0x12;
+
+/* The 48-byte public header is omitted. */
+data =
+ 0x 0x00a1 0x00020001 0x0028
+ 0x 0x 0x20120423 0x08f1
+ 0x0001 0x000206a7 0x 0x
+ 0x 0x 0x 0x
+ 0x 0x08f1 0x 0x
+ 0x 0x 0x 0x
Do you plan to create a tool to convert the Intel released microcode
file to dts automatically? Or if not, we need document on how to
convert the Intel version to dts manually, maybe in the dts-bindings
documentation.
[snip]
Regards,
Bin
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[U-Boot] Pull request: u-boot-blackfin
Hi Tom, Please pull the following patches for Blackfin from u-boot-blackfin into your tree. Thanks Sonic Zhang The following changes since commit 11ada9225a16ed2d8ddbf0715a2416245a777cbc: Merge branch 'rmobile' of git://www.denx.de/git/u-boot-sh (2014-11-05 13:11:18 -0500) are available in the git repository at: git://git.denx.de/u-boot-blackfin.git master for you to fetch changes up to 6721bb5ad8744cae647cad9e917df649524ac54d: bfin: the max bfin sdh block count is 127 (2014-11-10 12:11:00 +0800) Sonic Zhang (2): bfin: make the CPU macro of LDR target more genenric bfin: the max bfin sdh block count is 127 Makefile | 2 +- arch/blackfin/include/asm/config.h | 2 ++ include/configs/bfin_adi_common.h | 1 + 3 files changed, 4 insertions(+), 1 deletion(-) ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 39/39] x86: ivybridge: Implement SDRAM init
Hi Simon, On Fri, Nov 7, 2014 at 4:20 AM, Simon Glass s...@chromium.org wrote: Implement SDRAM init using the Memory Reference Code (mrc.bin) provided in the board directory and the SDRAM SPD information in the device tree. This also needs the Intel Management Engine (me.bin) to work. Binary blobs everywhere: so far we have MRC, ME and microcode. SDRAM init works by setting up various parameters and calling the MRC. This in turn does some sort of magic to work out how much memory there is and the timing parameters to use. It also sets up the DRAM controllers. When the MRC returns, we use the information it provides to map out the available memory in U-Boot. U-Boot normally moves itself to the top of RAM. On x86 the RAM is not generally contiguous, and anyway some RAM may be above 4GB which doesn't work in 32-bit mode. So we relocate to the top of the largest block of RAM we can find below 4GB. Memory above 4GB is accessible with special functions (see physmem). It would be possible to build U-Boot in 64-bit mode but this wouldn't necessarily provide any more memory, since the largest block is often below 4GB. Anyway U-Boot doesn't need huge amounts of memory - even a very large ramdisk seldom exceeds 100-200MB. U-Boot has support for booting 64-bit kernels directly so this does not pose a limitation in that area. Also there are probably parts of U-Boot that will not work correctly in 64-bit mode. The MRC is one. There is some work remaining in this area. Since memory init is very slow (over 500ms) it is possible to save the parameters in SPI flash to speed it up next time. Suspend/resume support is not fully implemented, or at least it is not efficient. With this patch, link boots to a prompt. Signed-off-by: Simon Glass s...@chromium.org --- Makefile | 5 + arch/x86/Kconfig | 11 + arch/x86/cpu/ivybridge/Makefile | 3 + arch/x86/cpu/ivybridge/early_me.c | 191 arch/x86/cpu/ivybridge/me_status.c| 195 arch/x86/cpu/ivybridge/report_platform.c | 98 arch/x86/cpu/ivybridge/sdram.c| 553 +- arch/x86/cpu/start.S | 10 +- arch/x86/dts/link.dts | 111 + arch/x86/include/asm/arch-ivybridge/me.h | 357 ++ arch/x86/include/asm/arch-ivybridge/pch.h | 113 + arch/x86/include/asm/arch-ivybridge/pei_data.h| 121 + arch/x86/include/asm/arch-ivybridge/sandybridge.h | 2 + arch/x86/include/asm/config.h | 1 + arch/x86/include/asm/global_data.h| 13 + arch/x86/include/asm/post.h | 5 + arch/x86/include/asm/u-boot-x86.h | 2 + arch/x86/lib/Makefile | 1 + arch/x86/lib/ramtest.c| 79 include/configs/chromebook_link.h | 5 + include/configs/x86-common.h | 2 +- include/fdtdec.h | 1 + lib/fdtdec.c | 1 + 23 files changed, 1874 insertions(+), 6 deletions(-) create mode 100644 arch/x86/cpu/ivybridge/early_me.c create mode 100644 arch/x86/cpu/ivybridge/me_status.c create mode 100644 arch/x86/cpu/ivybridge/report_platform.c create mode 100644 arch/x86/include/asm/arch-ivybridge/me.h create mode 100644 arch/x86/include/asm/arch-ivybridge/pei_data.h create mode 100644 arch/x86/lib/ramtest.c diff --git a/Makefile b/Makefile index 86d0510..4f0260f 100644 --- a/Makefile +++ b/Makefile @@ -956,9 +956,14 @@ u-boot.rom: u-boot-x86-16bit.bin u-boot-dtb.bin \ $(srctree)/board/$(BOARDDIR)/descriptor.bin $(objtree)/tools/ifdtool -c -r $(CONFIG_ROM_SIZE) \ -D $(srctree)/board/$(BOARDDIR)/descriptor.bin u-boot.tmp + $(objtree)/tools/ifdtool \ + -i ME:$(srctree)/board/$(BOARDDIR)/me.bin u-boot.tmp $(objtree)/tools/ifdtool -w \ $(CONFIG_SYS_TEXT_BASE):$(objtree)/u-boot-dtb.bin u-boot.tmp $(objtree)/tools/ifdtool -w \ + $(CONFIG_X86_MRC_START):$(srctree)/board/$(BOARDDIR)/mrc.bin \ + u-boot.tmp + $(objtree)/tools/ifdtool -w \ $(CONFIG_SYS_X86_START16):$(objtree)/u-boot-x86-16bit.bin \ u-boot.tmp mv u-boot.tmp $@ diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 73fe8b2..e992610 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -50,6 +50,17 @@ config CPU_ADDR_BITS int default 36 +config HPET_ADDRESS + hex + default 0xfed0 if !HPET_ADDRESS_OVERRIDE + +config SMM_TSEG + bool + default n + +config SMM_TSEG_SIZE + hex + config ROM_SIZE hex
[U-Boot] [PATCH] arm: rmobile: alt: Change clock of SCIF to external clock
Change clock of SCIF for Alt board is used to external clock. This changes to using external clock. Signed-off-by: Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com --- V2: Change CONFIG_SH_SCIF_CLK_FREQ. include/configs/alt.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/include/configs/alt.h b/include/configs/alt.h index 3f6737c..e99f100 100644 --- a/include/configs/alt.h +++ b/include/configs/alt.h @@ -88,6 +88,7 @@ /* SCIF */ #define CONFIG_SCIF_CONSOLE #define CONFIG_CONS_SCIF2 +#define CONFIG_SCIF_USE_EXT_CLK #undef CONFIG_SYS_CONSOLE_INFO_QUIET #undef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE #undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE @@ -149,7 +150,7 @@ #define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2) /* EXT / 2 */ #define CONFIG_PLL1_CLK_FREQ(CONFIG_SYS_CLK_FREQ * 156 / 2) #define CONFIG_P_CLK_FREQ (CONFIG_PLL1_CLK_FREQ / 24) -#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_P_CLK_FREQ +#define CONFIG_SH_SCIF_CLK_FREQ14745600 /* External Clock */ #define CONFIG_SYS_TMU_CLK_DIV 4 -- 2.1.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] MAINTAINERS: add me as a maintainer of MTD
Add MAINTAINERS and doc/git-mailrc entry. Signed-off-by: Heiko Schocher h...@denx.de --- as discussed this step here and there first of all with Scott Wood for example here: http://lists.denx.de/pipermail/u-boot/2014-August/186005.html I am now ready for taking over the ownership for MTD ... Scott guesses he could continue with NAND custodianship, thanks! So no need for taking this into the MTD custodianship ... puuh ;-) @all: Please send me a list of pending patches, so I can go through them, thanks! Changes in v2: add comment from Jagan Teki and Masahiro Yamada: correct files entry in MAINTAINERS MAINTAINERS| 8 doc/git-mailrc | 1 + 2 files changed, 9 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 4e2f8a9..2ac55f8 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -258,6 +258,14 @@ S: Maintained T: git git://git.denx.de/u-boot-mmc.git F: drivers/mmc/ +MTD +M: Heiko Schocher h...@denx.de +S: Maintained +T: git git://git.denx.de/u-boot-mtd.git +F: drivers/mtd/ +F: include/linux/mtd/ +F: include/mtd/ + OPENRISC M: Stefan Kristiansson stefan.kristians...@saunalahti.fi S: Maintained diff --git a/doc/git-mailrc b/doc/git-mailrc index ad22763..166fe37 100644 --- a/doc/git-mailrc +++ b/doc/git-mailrc @@ -116,6 +116,7 @@ alias fdtuboot, sjg alias i2cuboot, hs alias kconfiguboot, masahiro alias mmcuboot, panto +alias mtduboot, hs alias nand uboot, scottwood alias netuboot, jhersh alias spi uboot, jagan -- 1.8.3.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [RFC PATCH 03/12] dm: i2c: Add a uclass for I2C
Hello Simon,
Am 13.10.2014 07:39, schrieb Simon Glass:
The uclass implements the same operations as the current I2C framework but
makes some changes to make it fit driver model better:
- Remove the chip address from API calls
- Remove the address length from API calls
- Remove concept of 'current' I2C bus
- Drop all existing init functions
Signed-off-by: Simon Glass s...@chromium.org
---
drivers/i2c/Makefile | 1 +
drivers/i2c/i2c-uclass.c | 177 +++
include/config_fallbacks.h | 6 ++
include/dm/uclass-id.h | 1 +
include/i2c.h | 252 +
5 files changed, 437 insertions(+)
create mode 100644 drivers/i2c/i2c-uclass.c
only nitpick ...
[...]
diff --git a/drivers/i2c/i2c-uclass.c b/drivers/i2c/i2c-uclass.c
new file mode 100644
index 000..6bdce8c
--- /dev/null
+++ b/drivers/i2c/i2c-uclass.c
@@ -0,0 +1,177 @@
+/*
+ * Copyright (c) 2014 Google, Inc
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include dm.h
+#include errno.h
+#include fdtdec.h
+#include i2c.h
+#include dm/device-internal.h
+#include dm/root.h
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int i2c_read(struct udevice *dev, uint addr, uint8_t *buffer, int len)
+{
+ struct dm_i2c_chip *chip = dev_get_parentdata(dev);
+ struct udevice *bus = dev_get_parent(dev);
+ struct dm_i2c_ops *ops = i2c_get_ops(bus);
+
+ if (!ops-read)
+ return -ENOSYS;
+
+ return ops-read(bus, chip-chip_addr, addr, chip-addr_len, buffer,
+len);
+}
+
+int i2c_write(struct udevice *dev, uint addr, const uint8_t *buffer, int len)
+{
+ struct dm_i2c_chip *chip = dev_get_parentdata(dev);
+ struct udevice *bus = dev_get_parent(dev);
+ struct dm_i2c_ops *ops = i2c_get_ops(bus);
+
+ if (!ops-write)
+ return -ENOSYS;
+
+ return ops-write(bus, chip-chip_addr, addr, chip-addr_len, buffer,
+ len);
+}
+
+int i2c_get_chip(struct udevice *bus, uint chip_addr, struct udevice **devp)
+{
+ struct udevice *dev;
+
+ for (device_find_first_child(bus, dev); dev;
+ device_find_next_child(dev)) {
+ struct dm_i2c_chip store;
+ struct dm_i2c_chip *chip = dev_get_parentdata(dev);
+ int ret;
+
+ if (!chip) {
+ chip = store;
+ i2c_chip_ofdata_to_platdata(gd-fdt_blob,
+ dev-of_offset, chip);
+ }
+ if (chip-chip_addr == chip_addr) {
+ ret = device_probe(dev);
+ if (ret)
+ return ret;
+ *devp = dev;
+ return 0;
+ }
+ }
+
+ return -ENODEV;
+}
+
+int i2c_probe(struct udevice *bus, uint chip)
+{
+ struct dm_i2c_ops *ops = i2c_get_ops(bus);
+ struct udevice *dev;
+ int ret;
+
+ if (!ops-probe)
+ return -ENODEV;
+
+ /* First probe that chip */
+ ret = ops-probe(bus, chip);
+ if (ret)
+ return ret;
+
+ /* The cihp was found, see if we have a driver, and probe it */
s/cihp/chip
[...]
bye,
Heiko
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Re: [U-Boot] [PATCH 19/39] x86: Build a .rom file which can be flashed to an x86 machine
Hi Simon,
On Fri, Nov 7, 2014 at 4:20 AM, Simon Glass s...@chromium.org wrote:
On x86 machines U-Boot needs to be added to a large ROM image which is
then flashed onto the target board. The ROM has a particular format so it
makes sense for U-Boot to build this image automatically. Unfortunately
it relies on binary blobs so we cannot require this for the default
build as yet.
Create a u-boot.rom output file for this purpose.
Signed-off-by: Simon Glass s...@chromium.org
---
Makefile | 27 ++-
arch/x86/Kconfig | 4
include/configs/chromebook_link.h | 2 ++
3 files changed, 32 insertions(+), 1 deletion(-)
diff --git a/Makefile b/Makefile
index 9c8a580..86d0510 100644
--- a/Makefile
+++ b/Makefile
@@ -743,6 +743,9 @@ ALL-$(CONFIG_SPL) += $(CONFIG_SPL_TARGET:%=%)
endif
ALL-$(CONFIG_REMAKE_ELF) += u-boot.elf
+# We can't do this yet due to the need for binary blobs
+# ALL-$(CONFIG_X86_RESET_VECTOR) += u-boot.rom
+
# enable combined SPL/u-boot/dtb rules for tegra
ifneq ($(CONFIG_TEGRA),)
ifeq ($(CONFIG_SPL),y)
@@ -804,7 +807,8 @@ OBJCOPYFLAGS_u-boot.srec := -O srec
u-boot.hex u-boot.srec: u-boot FORCE
$(call if_changed,objcopy)
-OBJCOPYFLAGS_u-boot.bin := -O binary
+OBJCOPYFLAGS_u-boot.bin := -O binary \
+ $(if $(CONFIG_X86_RESET_VECTOR),-R .start16 -R .resetvec)
binary_size_check: u-boot.bin FORCE
@file_size=$(shell wc -c u-boot.bin | awk '{print $$1}') ; \
@@ -943,6 +947,27 @@ u-boot-nand.gph: u-boot.bin FORCE
$(call if_changed,mkimage)
@dd if=/dev/zero bs=8 count=1 2/dev/null $@
+# x86 uses a large ROM. We fill it with 0xff, put the 16-bit stuff (including
+# reset vector) at the top, Intel ME at the bottom, and U-Boot in the middle.
+ifneq ($(CONFIG_X86_RESET_VECTOR),)
+rom: u-boot.rom FORCE
+
+u-boot.rom: u-boot-x86-16bit.bin u-boot-dtb.bin \
The u-boot-dtb.bin means we have to use device tree for all x86 board
port. Is this a must-have?
+ $(srctree)/board/$(BOARDDIR)/descriptor.bin
I don't see where the descriptor.bin is created?
+ $(objtree)/tools/ifdtool -c -r $(CONFIG_ROM_SIZE) \
+ -D $(srctree)/board/$(BOARDDIR)/descriptor.bin u-boot.tmp
+ $(objtree)/tools/ifdtool -w \
+ $(CONFIG_SYS_TEXT_BASE):$(objtree)/u-boot-dtb.bin u-boot.tmp
+ $(objtree)/tools/ifdtool -w \
+ $(CONFIG_SYS_X86_START16):$(objtree)/u-boot-x86-16bit.bin \
+ u-boot.tmp
+ mv u-boot.tmp $@
+
+OBJCOPYFLAGS_u-boot-x86-16bit.bin := -O binary -j .start16 -j .resetvec
+u-boot-x86-16bit.bin: u-boot FORCE
+ $(call if_changed,objcopy)
+endif
+
[snip]
Regards,
Bin
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Re: [U-Boot] [PATCH] MAINTAINERS: add me as a maintainer of MTD
On 10 November 2014 11:45, Heiko Schocher h...@denx.de wrote: Add MAINTAINERS and doc/git-mailrc entry. Signed-off-by: Heiko Schocher h...@denx.de --- as discussed this step here and there first of all with Scott Wood for example here: http://lists.denx.de/pipermail/u-boot/2014-August/186005.html I am now ready for taking over the ownership for MTD ... Scott guesses he could continue with NAND custodianship, thanks! So no need for taking this into the MTD custodianship ... puuh ;-) @all: Please send me a list of pending patches, so I can go through them, thanks! Changes in v2: add comment from Jagan Teki and Masahiro Yamada: correct files entry in MAINTAINERS MAINTAINERS| 8 doc/git-mailrc | 1 + 2 files changed, 9 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 4e2f8a9..2ac55f8 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -258,6 +258,14 @@ S: Maintained T: git git://git.denx.de/u-boot-mmc.git F: drivers/mmc/ +MTD +M: Heiko Schocher h...@denx.de +S: Maintained +T: git git://git.denx.de/u-boot-mtd.git +F: drivers/mtd/ +F: include/linux/mtd/ +F: include/mtd/ + This approach, I feel it's sounds not good to me. [1] as per my comments, it's good to add the maintainers who belongs to drivers/mtd as MTD maintainer so-that it is more defined way for any one in opensource to understand it - Linux is operating same i guess. Comments? [1] http://u-boot.10912.n7.nabble.com/PATCH-MAINTAINERS-add-me-as-a-maintainer-of-MTD-td194237.html#a194619 OPENRISC M: Stefan Kristiansson stefan.kristians...@saunalahti.fi S: Maintained diff --git a/doc/git-mailrc b/doc/git-mailrc index ad22763..166fe37 100644 --- a/doc/git-mailrc +++ b/doc/git-mailrc @@ -116,6 +116,7 @@ alias fdtuboot, sjg alias i2cuboot, hs alias kconfiguboot, masahiro alias mmcuboot, panto +alias mtduboot, hs alias nand uboot, scottwood alias netuboot, jhersh alias spi uboot, jagan -- 1.8.3.1 thanks! -- Jagan. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 39/39] x86: ivybridge: Implement SDRAM init
Hi Simon, On Fri, Nov 7, 2014 at 4:20 AM, Simon Glass s...@chromium.org wrote: Implement SDRAM init using the Memory Reference Code (mrc.bin) provided in the board directory and the SDRAM SPD information in the device tree. This also needs the Intel Management Engine (me.bin) to work. Binary blobs everywhere: so far we have MRC, ME and microcode. [snip] diff --git a/Makefile b/Makefile index 86d0510..4f0260f 100644 --- a/Makefile +++ b/Makefile @@ -956,9 +956,14 @@ u-boot.rom: u-boot-x86-16bit.bin u-boot-dtb.bin \ $(srctree)/board/$(BOARDDIR)/descriptor.bin $(objtree)/tools/ifdtool -c -r $(CONFIG_ROM_SIZE) \ -D $(srctree)/board/$(BOARDDIR)/descriptor.bin u-boot.tmp + $(objtree)/tools/ifdtool \ + -i ME:$(srctree)/board/$(BOARDDIR)/me.bin u-boot.tmp Can we make the ME injection depend on something like CONFIG_X86_HAVE_ME? $(objtree)/tools/ifdtool -w \ $(CONFIG_SYS_TEXT_BASE):$(objtree)/u-boot-dtb.bin u-boot.tmp $(objtree)/tools/ifdtool -w \ + $(CONFIG_X86_MRC_START):$(srctree)/board/$(BOARDDIR)/mrc.bin \ + u-boot.tmp Ditto. + $(objtree)/tools/ifdtool -w \ $(CONFIG_SYS_X86_START16):$(objtree)/u-boot-x86-16bit.bin \ u-boot.tmp mv u-boot.tmp $@ Regards, Bin ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [RFC PATCH 04/12] dm: i2c: Implement driver model support in the i2c command
Hello Simon,
Am 13.10.2014 07:39, schrieb Simon Glass:
The concept of a 'current bus' is now implemented in the command line
rather than in the uclass. Also the address length does not need to
be specified with each command - really we should consider dropping
this from most commands but it works OK for now.
Signed-off-by: Simon Glass s...@chromium.org
---
common/cmd_i2c.c | 312 +++
1 file changed, 267 insertions(+), 45 deletions(-)
diff --git a/common/cmd_i2c.c b/common/cmd_i2c.c
index c266b88..6766856 100644
--- a/common/cmd_i2c.c
+++ b/common/cmd_i2c.c
@@ -69,8 +69,10 @@
#include bootretry.h
#include cli.h
#include command.h
+#include dm.h
#include edid.h
#include environment.h
+#include errno.h
#include i2c.h
#include malloc.h
#include asm/byteorder.h
@@ -117,6 +119,60 @@ static uchar i2c_no_probes[] = CONFIG_SYS_I2C_NOPROBES;
#define DISP_LINE_LEN 16
+/*
+ * Default for driver model is to use the chip's existing address length.
+ * For legacy code, this is not stored, so we need to use a suitable
+ * default.
+ */
+#ifdef CONFIG_DM_I2C
+#define DEFAULT_ADDR_LEN (-1)
+#else
+#define DEFAULT_ADDR_LEN 1
+#endif
+
+#ifdef CONFIG_DM_I2C
+static struct udevice *i2c_cur_bus;
+
+static int i2c_set_bus_num(unsigned int busnum)
+{
+ struct udevice *bus;
+ int ret;
+
+ ret = uclass_get_device_by_seq(UCLASS_I2C, busnum, bus);
+ if (ret) {
+ debug(%s: No bus %d\n, __func__, busnum);
+ return ret;
+ }
+ i2c_cur_bus = bus;
+
+ return 0;
+}
+
+static int i2c_get_cur_bus(struct udevice **busp)
+{
+ if (!i2c_cur_bus) {
+ puts(No I2C bus selected\n);
+ return -ENODEV;
+ }
+ *busp = i2c_cur_bus;
+
+ return 0;
+}
+
+static int i2c_get_cur_bus_chip(uint chip_addr, struct udevice **devp)
+{
+ struct udevice *bus;
+ int ret;
+
+ ret = i2c_get_cur_bus(bus);
+ if (ret)
+ return ret;
+
+ return i2c_get_chip(bus, chip_addr, devp);
+}
+
+#endif
+
/**
* i2c_init_board() - Board-specific I2C bus init
*
@@ -143,7 +199,7 @@ void i2c_init_board(void)
*
* Returns I2C bus speed in Hz.
*/
-#if !defined(CONFIG_SYS_I2C)
+#if !defined(CONFIG_SYS_I2C) !defined(CONFIG_DM_I2C)
/*
* TODO: Implement architecture-specific get/set functions
* Should go away, if we switched completely to new multibus support
@@ -182,12 +238,12 @@ int i2c_set_bus_speed(unsigned int speed)
*
* Returns the address length.
*/
-static uint get_alen(char *arg)
+static uint get_alen(char *arg, int default_len)
{
int j;
int alen;
- alen = 1;
+ alen = default_len;
for (j = 0; j 8; j++) {
if (arg[j] == '.') {
alen = arg[j+1] - '0';
@@ -229,6 +285,10 @@ static int do_i2c_read ( cmd_tbl_t *cmdtp, int flag, int
argc, char * const argv
u_char chip;
uintdevaddr, alen, length;
u_char *memaddr;
+ int ret;
+#ifdef CONFIG_DM_I2C
+ struct udevice *dev;
+#endif
if (argc != 5)
return CMD_RET_USAGE;
@@ -243,7 +303,7 @@ static int do_i2c_read ( cmd_tbl_t *cmdtp, int flag, int
argc, char * const argv
* 2 bytes long. Some day it might be 3 bytes long :-).
*/
devaddr = simple_strtoul(argv[2], NULL, 16);
- alen = get_alen(argv[2]);
+ alen = get_alen(argv[2], DEFAULT_ADDR_LEN);
if (alen 3)
return CMD_RET_USAGE;
@@ -257,10 +317,18 @@ static int do_i2c_read ( cmd_tbl_t *cmdtp, int flag, int
argc, char * const argv
*/
memaddr = (u_char *)simple_strtoul(argv[4], NULL, 16);
- if (i2c_read(chip, devaddr, alen, memaddr, length) != 0) {
- i2c_report_err(-1, I2C_ERR_READ);
- return 1;
- }
+#ifdef CONFIG_DM_I2C
+ ret = i2c_get_cur_bus_chip(chip, dev);
+ if (!ret alen != -1)
+ ret = i2c_set_addr_len(dev, alen);
+ if (!ret)
+ ret = i2c_read(dev, devaddr, memaddr, length);
+#else
+ ret = i2c_read(chip, devaddr, alen, memaddr, length);
+#endif
+ if (ret)
+ return i2c_report_err(ret, I2C_ERR_READ);
+
return 0;
}
@@ -269,6 +337,10 @@ static int do_i2c_write(cmd_tbl_t *cmdtp, int flag, int
argc, char * const argv[
u_char chip;
uintdevaddr, alen, length;
u_char *memaddr;
+ int ret;
+#ifdef CONFIG_DM_I2C
+ struct udevice *dev;
+#endif
if (argc != 5)
return cmd_usage(cmdtp);
@@ -288,7 +360,7 @@ static int do_i2c_write(cmd_tbl_t *cmdtp, int flag, int
argc, char * const argv[
* 2 bytes long. Some day it might be 3 bytes long :-).
*/
devaddr = simple_strtoul(argv[3], NULL, 16);
- alen = get_alen(argv[3]);
+ alen = get_alen(argv[3], DEFAULT_ADDR_LEN);
if
Re: [U-Boot] [RFC PATCH 0/12] RFC: dm: Add I2C support
Hello Simon, sorry for the long delay... Am 13.10.2014 07:39, schrieb Simon Glass: (Note this is RFC since the uclass interface needs discussion and also because only sandbox is implemented so far. But I thought it best to get this out there as soon as I wrote it as it may influence the PMIC library, etc.) This series is an initial attempt to add I2C support to driver model. It has become apparent that this is a high priority as it is widely used. It follows along to some extent from the SPI conversion. Several changes are made from the original I2C implementations. Firstly It is not necessary to specify the chip address with every call, since each chip knows its own address - it is stored in struct dm_i2c_chip which is attached to each chip on the I2C bus. However, this information *is* passed to the driver since I presume most drivers need it and it would be cumbersome to look up in every call. Secondly there is no concept of a 'current' I2C bus so all associated logic is removed. With driver model i2c_set_bus_num() and i2c_get_bus_num() are not available. Since the chip device specifies both the bus and the chip address, there is no need for this concept. It also causes problems when one driver changes the current bus and forgets to change it back. Thirdly initialisation is handled by driver model's normal probe() method on each device so there should be no need for i2c_init_all(), i2c_init(), i2c_init_board(), i2c_board_late_init() and board_i2c_init(). Great! I2C muxes are not yet supported. To support these we will need to maintain state of the current mux settings to avoid resetting every mux every time. Probably we need to add a sandbox I2C mux driver to permit testing of this. This can probably be done later. Currently only the keymile boards really use i2c muxes, so I am fine with doing this in a second step. Platform data is not yet supported either, only device tree. The U_BOOT_I2C_MKENT_COMPLETE() and U_BOOT_I2C_ADAP_COMPLETE() macros are not used. Also struct i2c_adapter is not defined anymore. This will need to be addressed, perhaps as part of converting over a board that does not use device tree. Ok for this in the first step... The question raised if we only would support Device tree with DM ... so maybe we do not need to do this step. I am not really sure, if we should really support Device Tree only with DM, because: - do all archs switch to Device Tree in the near future? - in SPL we have really on some SoCs small memory (like I just work on some AT91 boards which have 4k only!) To get DM with Device Tree into 4k is a big challenge ... so in my opinion, it would be good to have the possibility of Platform data ... so we prevent to make dirty hacks for the SPL case (I hope) ... This series is available at u-boot-dm/i2c-working. Thanks for your great work. I looked through your patchset and have no real objection against it ... To the i2c deblocking subject ... we should add at least the deblock() in struct dm_i2c_ops and call it do_i2c_reset if defined ... beside of this, you can add my Acked-by: Heiko Schocher h...@denx.de to the hole series. bye, Heiko -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v4 0/3] ARM: atmel: add sama5d4ek board support
This patch series add sama5d4ek board support which supports following features: - Boot media support: NAND flash/SD card/SPI flash - Support LCD display - Support ethernet - Support USB mass storage Changes in v4: - rebase to the mainline master (11ada92) - Select CPU_V7 in Kconfig. - Drop CONFIG_ARMV7 in board head file. Series-changes: 3 - Rewrite the h32mxdiv related code according to Andreas's suggestion. Series-changes: 2 - Add sama5d4_devices.c to hold soc related code (e.g: get_cpu_name) - rewrite the clock with H32MXDIV Changes in v2: - rewrite the gf table build function by Josh. Bo Shen (2): net: macb: enable GMAC IP without GE feature support ARM: atmel: add sama5d4ek board support Josh Wu (1): mtd: atmel_nand: runtime to build gf table for pmecc arch/arm/Kconfig | 5 + arch/arm/cpu/armv7/at91/Makefile | 1 + arch/arm/cpu/armv7/at91/sama5d4_devices.c | 30 +++ arch/arm/cpu/armv7/at91/timer.c | 3 +- arch/arm/include/asm/arch-at91/at91_pmc.h | 8 +- arch/arm/include/asm/arch-at91/clk.h | 48 - arch/arm/include/asm/arch-at91/hardware.h | 2 + arch/arm/include/asm/arch-at91/sama5d4.h | 206 +++ board/atmel/sama5d4ek/Kconfig | 18 ++ board/atmel/sama5d4ek/MAINTAINERS | 8 + board/atmel/sama5d4ek/Makefile| 8 + board/atmel/sama5d4ek/sama5d4ek.c | 317 ++ configs/sama5d4ek_mmc_defconfig | 3 + configs/sama5d4ek_nandflash_defconfig | 3 + configs/sama5d4ek_spiflash_defconfig | 3 + drivers/mtd/nand/atmel_nand.c | 75 ++- drivers/mtd/nand/atmel_nand_ecc.h | 4 + drivers/net/macb.c| 8 +- include/configs/sama5d4ek.h | 214 19 files changed, 953 insertions(+), 11 deletions(-) create mode 100644 arch/arm/cpu/armv7/at91/sama5d4_devices.c create mode 100644 arch/arm/include/asm/arch-at91/sama5d4.h create mode 100644 board/atmel/sama5d4ek/Kconfig create mode 100644 board/atmel/sama5d4ek/MAINTAINERS create mode 100644 board/atmel/sama5d4ek/Makefile create mode 100644 board/atmel/sama5d4ek/sama5d4ek.c create mode 100644 configs/sama5d4ek_mmc_defconfig create mode 100644 configs/sama5d4ek_nandflash_defconfig create mode 100644 configs/sama5d4ek_spiflash_defconfig create mode 100644 include/configs/sama5d4ek.h -- 2.1.0.24.g4109c28 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v4 2/3] net: macb: enable GMAC IP without GE feature support
The User Register in GMAC IP is used to select interface type.
When with GE feature, it is used to select interface between
RGMII and GMII. If without GE feature, it is used to select
interface between MII and RMII.
Signed-off-by: Bo Shen voice.s...@atmel.com
---
Changes in v4: None
Changes in v2: None
drivers/net/macb.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/net/macb.c b/drivers/net/macb.c
index 375c8a4..6d48252 100644
--- a/drivers/net/macb.c
+++ b/drivers/net/macb.c
@@ -565,7 +565,13 @@ static int macb_init(struct eth_device *netdev, bd_t *bd)
macb_writel(macb, TBQP, macb-tx_ring_dma);
if (macb_is_gem(macb)) {
-#ifdef CONFIG_RGMII
+ /*
+* When the GMAC IP with GE feature, this bit is used to
+* select interface between RGMII and GMII.
+* When the GMAC IP without GE feature, this bit is used
+* to select interface between RMII and MII.
+*/
+#if defined(CONFIG_RGMII) || defined(CONFIG_RMII)
gem_writel(macb, UR, GEM_BIT(RGMII));
#else
gem_writel(macb, UR, 0);
--
2.1.0.24.g4109c28
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[U-Boot] [PATCH v4 3/3] ARM: atmel: add sama5d4ek board support
The code for this board supports following features:
- Boot media support: NAND flash/SD card/SPI flash
- Support LCD display
- Support ethernet
- Support USB mass storage
Signed-off-by: Bo Shen voice.s...@atmel.com
---
Changes in v4:
- rebase to the mainline master (11ada92)
- Select CPU_V7 in Kconfig.
- Drop CONFIG_ARMV7 in board head file.
Series-changes: 3
- Rewrite the h32mxdiv related code according to Andreas's suggestion.
Series-changes: 2
- Add sama5d4_devices.c to hold soc related code (e.g: get_cpu_name)
- rewrite the clock with H32MXDIV
Changes in v2: None
arch/arm/Kconfig | 5 +
arch/arm/cpu/armv7/at91/Makefile | 1 +
arch/arm/cpu/armv7/at91/sama5d4_devices.c | 30 +++
arch/arm/cpu/armv7/at91/timer.c | 3 +-
arch/arm/include/asm/arch-at91/at91_pmc.h | 8 +-
arch/arm/include/asm/arch-at91/clk.h | 48 -
arch/arm/include/asm/arch-at91/hardware.h | 2 +
arch/arm/include/asm/arch-at91/sama5d4.h | 206 +++
board/atmel/sama5d4ek/Kconfig | 18 ++
board/atmel/sama5d4ek/MAINTAINERS | 8 +
board/atmel/sama5d4ek/Makefile| 8 +
board/atmel/sama5d4ek/sama5d4ek.c | 317 ++
configs/sama5d4ek_mmc_defconfig | 3 +
configs/sama5d4ek_nandflash_defconfig | 3 +
configs/sama5d4ek_spiflash_defconfig | 3 +
include/configs/sama5d4ek.h | 214
16 files changed, 868 insertions(+), 9 deletions(-)
create mode 100644 arch/arm/cpu/armv7/at91/sama5d4_devices.c
create mode 100644 arch/arm/include/asm/arch-at91/sama5d4.h
create mode 100644 board/atmel/sama5d4ek/Kconfig
create mode 100644 board/atmel/sama5d4ek/MAINTAINERS
create mode 100644 board/atmel/sama5d4ek/Makefile
create mode 100644 board/atmel/sama5d4ek/sama5d4ek.c
create mode 100644 configs/sama5d4ek_mmc_defconfig
create mode 100644 configs/sama5d4ek_nandflash_defconfig
create mode 100644 configs/sama5d4ek_spiflash_defconfig
create mode 100644 include/configs/sama5d4ek.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 22eb2d5..1bcd440 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -504,6 +504,10 @@ config TARGET_SAMA5D3XEK
select CPU_V7
select SUPPORT_SPL
+config TARGET_SAMA5D4EK
+ bool Support sama5d4ek
+ select CPU_V7
+
config TARGET_BCM28155_AP
bool Support bcm28155_ap
select CPU_V7
@@ -835,6 +839,7 @@ source board/atmel/at91sam9rlek/Kconfig
source board/atmel/at91sam9x5ek/Kconfig
source board/atmel/sama5d3_xplained/Kconfig
source board/atmel/sama5d3xek/Kconfig
+source board/atmel/sama5d4ek/Kconfig
source board/bachmann/ot1200/Kconfig
source board/balloon3/Kconfig
source board/barco/titanium/Kconfig
diff --git a/arch/arm/cpu/armv7/at91/Makefile b/arch/arm/cpu/armv7/at91/Makefile
index 0a2e48d..f4f35a4 100644
--- a/arch/arm/cpu/armv7/at91/Makefile
+++ b/arch/arm/cpu/armv7/at91/Makefile
@@ -9,6 +9,7 @@
#
obj-$(CONFIG_SAMA5D3) += sama5d3_devices.o
+obj-$(CONFIG_SAMA5D4) += sama5d4_devices.o
obj-y += clock.o
obj-y += cpu.o
obj-y += reset.o
diff --git a/arch/arm/cpu/armv7/at91/sama5d4_devices.c
b/arch/arm/cpu/armv7/at91/sama5d4_devices.c
new file mode 100644
index 000..2708097
--- /dev/null
+++ b/arch/arm/cpu/armv7/at91/sama5d4_devices.c
@@ -0,0 +1,30 @@
+/*
+ * Copyright (C) 2014 Atmel
+ * Bo Shen voice.s...@atmel.com
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include asm/arch/sama5d4.h
+
+char *get_cpu_name()
+{
+ unsigned int extension_id = get_extension_chip_id();
+
+ if (cpu_is_sama5d4())
+ switch (extension_id) {
+ case ARCH_EXID_SAMA5D41:
+ return SAMA5D41;
+ case ARCH_EXID_SAMA5D42:
+ return SAMA5D42;
+ case ARCH_EXID_SAMA5D43:
+ return SAMA5D43;
+ case ARCH_EXID_SAMA5D44:
+ return SAMA5D44;
+ default:
+ return Unknown CPU type;
+ }
+ else
+ return Unknown CPU type;
+}
diff --git a/arch/arm/cpu/armv7/at91/timer.c b/arch/arm/cpu/armv7/at91/timer.c
index e3ebfe0..19bf80b 100644
--- a/arch/arm/cpu/armv7/at91/timer.c
+++ b/arch/arm/cpu/armv7/at91/timer.c
@@ -65,7 +65,8 @@ int timer_init(void)
/* Enable PITC */
writel(TIMER_LOAD_VAL | AT91_PIT_MR_EN , pit-mr);
- gd-arch.timer_rate_hz = gd-arch.mck_rate_hz / 16;
+ gd-arch.timer_rate_hz = get_pit_clk_rate() / 16;
+
gd-arch.tbu = 0;
gd-arch.tbl = 0;
diff --git a/arch/arm/include/asm/arch-at91/at91_pmc.h
b/arch/arm/include/asm/arch-at91/at91_pmc.h
index 27331ff..7c1578c 100644
--- a/arch/arm/include/asm/arch-at91/at91_pmc.h
+++ b/arch/arm/include/asm/arch-at91/at91_pmc.h
@@ -78,7 +78,7 @@ typedef struct at91_pmc {
#define AT91_PMC_PLLXR_DIV(x) (x 0xFF)
[U-Boot] [PATCH v4 1/3] mtd: atmel_nand: runtime to build gf table for pmecc
From: Josh Wu josh...@atmel.com
As in SAMA5D4 SoC, the gf table in ROM code can not be seen.
So, when we try to use PMECC, we need to build it when do
initialization.
Add a macro NO_GALOIS_TABLE_IN_ROM in soc header file. If it
is defined we will build gf table runtime.
The PMECC use the BCH algorithm, so based on the build_gf_tables()
function in lib/bch.c, we can build the Galois Field lookup table.
Signed-off-by: Josh Wu josh...@atmel.com
Signed-off-by: Bo Shen voice.s...@atmel.com
---
Changes in v4: None
Changes in v2:
- rewrite the gf table build function by Josh.
drivers/mtd/nand/atmel_nand.c | 75 ++-
drivers/mtd/nand/atmel_nand_ecc.h | 4 +++
2 files changed, 78 insertions(+), 1 deletion(-)
diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c
index 9114a86..20fcecb 100644
--- a/drivers/mtd/nand/atmel_nand.c
+++ b/drivers/mtd/nand/atmel_nand.c
@@ -762,6 +762,62 @@ static int pmecc_choose_ecc(struct atmel_nand_host *host,
}
#endif
+#if defined(NO_GALOIS_TABLE_IN_ROM)
+static uint16_t *pmecc_galois_table;
+static inline int deg(unsigned int poly)
+{
+ /* polynomial degree is the most-significant bit index */
+ return fls(poly) - 1;
+}
+
+static int build_gf_tables(int mm, unsigned int poly,
+ int16_t *index_of, int16_t *alpha_to)
+{
+ unsigned int i, x = 1;
+ const unsigned int k = 1 deg(poly);
+ unsigned int nn = (1 mm) - 1;
+
+ /* primitive polynomial must be of degree m */
+ if (k != (1u mm))
+ return -EINVAL;
+
+ for (i = 0; i nn; i++) {
+ alpha_to[i] = x;
+ index_of[x] = i;
+ if (i (x == 1))
+ /* polynomial is not primitive (a^i=1 with 0i2^m-1) */
+ return -EINVAL;
+ x = 1;
+ if (x k)
+ x ^= poly;
+ }
+
+ alpha_to[nn] = 1;
+ index_of[0] = 0;
+
+ return 0;
+}
+
+static uint16_t *create_lookup_table(int sector_size)
+{
+ int degree = (sector_size == 512) ?
+ PMECC_GF_DIMENSION_13 :
+ PMECC_GF_DIMENSION_14;
+ unsigned int poly = (sector_size == 512) ?
+ PMECC_GF_13_PRIMITIVE_POLY :
+ PMECC_GF_14_PRIMITIVE_POLY;
+ int table_size = (sector_size == 512) ?
+ PMECC_INDEX_TABLE_SIZE_512 :
+ PMECC_INDEX_TABLE_SIZE_1024;
+
+ int16_t *addr = kzalloc(2 * table_size * sizeof(uint16_t), GFP_KERNEL);
+ if (addr build_gf_tables(degree, poly, addr, addr + table_size))
+ return NULL;
+
+ return (uint16_t *)addr;
+}
+#endif
+
static int atmel_pmecc_nand_init_params(struct nand_chip *nand,
struct mtd_info *mtd)
{
@@ -809,11 +865,18 @@ static int atmel_pmecc_nand_init_params(struct nand_chip
*nand,
sector_size = host-pmecc_sector_size;
/* TODO: need check whether cap sector_size is validate */
-
+#if defined(NO_GALOIS_TABLE_IN_ROM)
+ /*
+* As pmecc_rom_base is the begin of the gallois field table, So the
+* index offset just set as 0.
+*/
+ host-pmecc_index_table_offset = 0;
+#else
if (host-pmecc_sector_size == 512)
host-pmecc_index_table_offset = ATMEL_PMECC_INDEX_OFFSET_512;
else
host-pmecc_index_table_offset = ATMEL_PMECC_INDEX_OFFSET_1024;
+#endif
MTDDEBUG(MTD_DEBUG_LEVEL1,
Initialize PMECC params, cap: %d, sector: %d\n,
@@ -822,7 +885,17 @@ static int atmel_pmecc_nand_init_params(struct nand_chip
*nand,
host-pmecc = (struct pmecc_regs __iomem *) ATMEL_BASE_PMECC;
host-pmerrloc = (struct pmecc_errloc_regs __iomem *)
ATMEL_BASE_PMERRLOC;
+#if defined(NO_GALOIS_TABLE_IN_ROM)
+ pmecc_galois_table = create_lookup_table(host-pmecc_sector_size);
+ if (!pmecc_galois_table) {
+ dev_err(host-dev, out of memory\n);
+ return -ENOMEM;
+ }
+
+ host-pmecc_rom_base = (void __iomem *)pmecc_galois_table;
+#else
host-pmecc_rom_base = (void __iomem *) ATMEL_BASE_ROM;
+#endif
/* ECC is calculated for the whole page (1 step) */
nand-ecc.size = mtd-writesize;
diff --git a/drivers/mtd/nand/atmel_nand_ecc.h
b/drivers/mtd/nand/atmel_nand_ecc.h
index 92d4ec5..eac860d 100644
--- a/drivers/mtd/nand/atmel_nand_ecc.h
+++ b/drivers/mtd/nand/atmel_nand_ecc.h
@@ -141,6 +141,10 @@ struct pmecc_errloc_regs {
#define PMECC_GF_DIMENSION_13 13
#define PMECC_GF_DIMENSION_14 14
+/* Primitive Polynomial used by PMECC */
+#define PMECC_GF_13_PRIMITIVE_POLY 0x201b
+#define PMECC_GF_14_PRIMITIVE_POLY 0x4443
+
#define PMECC_INDEX_TABLE_SIZE_512 0x2000
#define PMECC_INDEX_TABLE_SIZE_10240x4000
--
Re: [U-Boot] [PATCH] MAINTAINERS: add me as a maintainer of MTD
Hello Jagan, Am 10.11.2014 07:38, schrieb Jagan Teki: On 10 November 2014 11:45, Heiko Schocher h...@denx.de wrote: Add MAINTAINERS and doc/git-mailrc entry. Signed-off-by: Heiko Schocher h...@denx.de --- as discussed this step here and there first of all with Scott Wood for example here: http://lists.denx.de/pipermail/u-boot/2014-August/186005.html I am now ready for taking over the ownership for MTD ... Scott guesses he could continue with NAND custodianship, thanks! So no need for taking this into the MTD custodianship ... puuh ;-) @all: Please send me a list of pending patches, so I can go through them, thanks! Changes in v2: add comment from Jagan Teki and Masahiro Yamada: correct files entry in MAINTAINERS MAINTAINERS| 8 doc/git-mailrc | 1 + 2 files changed, 9 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 4e2f8a9..2ac55f8 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -258,6 +258,14 @@ S: Maintained T: git git://git.denx.de/u-boot-mmc.git F: drivers/mmc/ +MTD +M: Heiko Schocher h...@denx.de +S: Maintained +T: git git://git.denx.de/u-boot-mtd.git +F: drivers/mtd/ +F: include/linux/mtd/ +F: include/mtd/ + This approach, I feel it's sounds not good to me. [1] as per my comments, it's good to add the maintainers who belongs to Hups... sorry. Seems I missed this EMail ... drivers/mtd as MTD maintainer so-that it is more defined way for any one in opensource to understand it - Linux is operating same i guess. I could not parse you here ... Looking in linux MAINTAINERS: MEMORY TECHNOLOGY DEVICES (MTD) M: David Woodhouse dw...@infradead.org M: Brian Norris computersforpe...@gmail.com L: linux-...@lists.infradead.org W: http://www.linux-mtd.infradead.org/ Q: http://patchwork.ozlabs.org/project/linux-mtd/list/ T: git git://git.infradead.org/linux-mtd.git S: Maintained F: drivers/mtd/ F: include/linux/mtd/ F: include/uapi/mtd/ [...] ONENAND FLASH DRIVER M: Kyungmin Park kyungmin.p...@samsung.com L: linux-...@lists.infradead.org S: Maintained F: drivers/mtd/onenand/ F: include/linux/mtd/onenand*.h [...] PHRAM MTD DRIVER M: Joern Engel jo...@lazybastard.org L: linux-...@lists.infradead.org S: Maintained F: drivers/mtd/devices/phram.c ... and a lot more ... So where is the difference? The mtd mailinglist? I am sure we do not want to introduce a seperate mailinglist... I do not want to maintain your parts! Comments? @Kyungmin Park: Could you comment here too, espacially for ubi/ubifs IIRC I see no comments for the MTD/UBI/UBIFS sync with Linux 3.14 patches from me ... do you have longer time for maintaining this? There are also patches (some here for example which are pending, and seeing no comments from you ...) for example 2 examples from me: [U-Boot] mtd, ubi: errormessage handling http://patchwork.ozlabs.org/patch/405259/ [U-Boot,v2] ubi: enable error reporting in initialization http://patchwork.ozlabs.org/patch/407136/ bye, Heiko [1] http://u-boot.10912.n7.nabble.com/PATCH-MAINTAINERS-add-me-as-a-maintainer-of-MTD-td194237.html#a194619 OPENRISC M: Stefan Kristiansson stefan.kristians...@saunalahti.fi S: Maintained diff --git a/doc/git-mailrc b/doc/git-mailrc index ad22763..166fe37 100644 --- a/doc/git-mailrc +++ b/doc/git-mailrc @@ -116,6 +116,7 @@ alias fdtuboot, sjg alias i2cuboot, hs alias kconfiguboot, masahiro alias mmcuboot, panto +alias mtduboot, hs alias nand uboot, scottwood alias netuboot, jhersh alias spi uboot, jagan -- 1.8.3.1 thanks! -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [i2c] Pull request
Hello Tom, please pull from u-boot-i2c.git The following changes since commit 11ada9225a16ed2d8ddbf0715a2416245a777cbc: Merge branch 'rmobile' of git://www.denx.de/git/u-boot-sh (2014-11-05 13:11:18 -0500) are available in the git repository at: git://git.denx.de/u-boot-i2c.git master for you to fetch changes up to cd818a381ddcdc2440a167757394298f28b70240: i2c: rcar_i2c: Fix order of restart and clear status (2014-11-10 06:47:37 +0100) Dirk Eibach (2): ppc4xx: Fix i2c repeated start ppc4xx: Handle i2c stuck on combined xfer Nobuhiro Iwamatsu (1): i2c: rcar_i2c: Fix order of restart and clear status Shaveta Leekha (1): drivers/i2c/fsl_i2c: Change CONFIG_I2C_TIMEOUT to 100ms arch/powerpc/include/asm/ppc4xx-i2c.h | 2 ++ drivers/i2c/fsl_i2c.c | 2 +- drivers/i2c/ppc4xx_i2c.c | 30 ++ drivers/i2c/rcar_i2c.c| 4 ++-- 4 files changed, 31 insertions(+), 7 deletions(-) bye, Heiko -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2] ARM: atmel: add sama5d4 xplained ultra board support
The code for this board supports following features:
- Boot media support: NAND flash/SD card/SPI flash
- Support LCD display (optional, disabled by default)
- Support ethernet
- Support USB mass storage
Signed-off-by: Bo Shen voice.s...@atmel.com
---
This patch based on the patch to add sama5d4ek board support.
Changes in v2:
- Select CPU_V7 in Kconfig
arch/arm/Kconfig| 5 +
board/atmel/sama5d4_xplained/Kconfig| 18 ++
board/atmel/sama5d4_xplained/MAINTAINERS| 8 +
board/atmel/sama5d4_xplained/Makefile | 8 +
board/atmel/sama5d4_xplained/sama5d4_xplained.c | 319
configs/sama5d4_xplained_mmc_defconfig | 3 +
configs/sama5d4_xplained_nandflash_defconfig| 3 +
configs/sama5d4_xplained_spiflash_defconfig | 3 +
include/configs/sama5d4_xplained.h | 216
9 files changed, 583 insertions(+)
create mode 100644 board/atmel/sama5d4_xplained/Kconfig
create mode 100644 board/atmel/sama5d4_xplained/MAINTAINERS
create mode 100644 board/atmel/sama5d4_xplained/Makefile
create mode 100644 board/atmel/sama5d4_xplained/sama5d4_xplained.c
create mode 100644 configs/sama5d4_xplained_mmc_defconfig
create mode 100644 configs/sama5d4_xplained_nandflash_defconfig
create mode 100644 configs/sama5d4_xplained_spiflash_defconfig
create mode 100644 include/configs/sama5d4_xplained.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 1bcd440..0dde1b3 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -504,6 +504,10 @@ config TARGET_SAMA5D3XEK
select CPU_V7
select SUPPORT_SPL
+config TARGET_SAMA5D4_XPLAINED
+ bool Support sama5d4_xplained
+ select CPU_V7
+
config TARGET_SAMA5D4EK
bool Support sama5d4ek
select CPU_V7
@@ -839,6 +843,7 @@ source board/atmel/at91sam9rlek/Kconfig
source board/atmel/at91sam9x5ek/Kconfig
source board/atmel/sama5d3_xplained/Kconfig
source board/atmel/sama5d3xek/Kconfig
+source board/atmel/sama5d4_xplained/Kconfig
source board/atmel/sama5d4ek/Kconfig
source board/bachmann/ot1200/Kconfig
source board/balloon3/Kconfig
diff --git a/board/atmel/sama5d4_xplained/Kconfig
b/board/atmel/sama5d4_xplained/Kconfig
new file mode 100644
index 000..f6440c0
--- /dev/null
+++ b/board/atmel/sama5d4_xplained/Kconfig
@@ -0,0 +1,18 @@
+if TARGET_SAMA5D4_XPLAINED
+
+config SYS_CPU
+ default armv7
+
+config SYS_BOARD
+ default sama5d4_xplained
+
+config SYS_VENDOR
+ default atmel
+
+config SYS_SOC
+ default at91
+
+config SYS_CONFIG_NAME
+ default sama5d4_xplained
+
+endif
diff --git a/board/atmel/sama5d4_xplained/MAINTAINERS
b/board/atmel/sama5d4_xplained/MAINTAINERS
new file mode 100644
index 000..035f64c
--- /dev/null
+++ b/board/atmel/sama5d4_xplained/MAINTAINERS
@@ -0,0 +1,8 @@
+SAMA5D4 XPLAINED ULTRA BOARD
+M: Bo Shen voice.s...@atmel.com
+S: Maintained
+F: board/atmel/sama5d4_xplained/
+F: include/configs/sama5d4_xplained.h
+F: configs/sama5d4_xplained_mmc_defconfig
+F: configs/sama5d4_xplained_nandflash_defconfig
+F: configs/sama5d4_xplained_spiflash_defconfig
diff --git a/board/atmel/sama5d4_xplained/Makefile
b/board/atmel/sama5d4_xplained/Makefile
new file mode 100644
index 000..c59b12d
--- /dev/null
+++ b/board/atmel/sama5d4_xplained/Makefile
@@ -0,0 +1,8 @@
+#
+# Copyright (C) 2014 Atmel
+# Bo Shen voice.s...@atmel.com
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += sama5d4_xplained.o
diff --git a/board/atmel/sama5d4_xplained/sama5d4_xplained.c
b/board/atmel/sama5d4_xplained/sama5d4_xplained.c
new file mode 100644
index 000..de0baad
--- /dev/null
+++ b/board/atmel/sama5d4_xplained/sama5d4_xplained.c
@@ -0,0 +1,319 @@
+/*
+ * Copyright (C) 2014 Atmel
+ * Bo Shen voice.s...@atmel.com
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include asm/io.h
+#include asm/arch/at91_common.h
+#include asm/arch/at91_pmc.h
+#include asm/arch/at91_rstc.h
+#include asm/arch/gpio.h
+#include asm/arch/clk.h
+#include asm/arch/sama5d3_smc.h
+#include asm/arch/sama5d4.h
+#include atmel_lcdc.h
+#include atmel_mci.h
+#include lcd.h
+#include mmc.h
+#include net.h
+#include netdev.h
+#include nand.h
+#include spi.h
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_ATMEL_SPI
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+ return bus == 0 cs == 0;
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+ at91_set_pio_output(AT91_PIO_PORTC, 3, 0);
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+ at91_set_pio_output(AT91_PIO_PORTC, 3, 1);
+}
+
+static void sama5d4_xplained_spi0_hw_init(void)
+{
+ at91_set_a_periph(AT91_PIO_PORTC, 0, 0);/* SPI0_MISO */
+ at91_set_a_periph(AT91_PIO_PORTC, 1, 0);/* SPI0_MOSI */
+ at91_set_a_periph(AT91_PIO_PORTC, 2, 0);/* SPI0_SPCK */
+
+
