Re: [U-Boot] [PATCH v1] fastboot: handle flash write to GPT partition
Hi Steve,
Hi Lukasz,
On 14-12-08 03:21 AM, Lukasz Majewski wrote:
Hi Steve,
Implement a feature to allow fastboot to write the downloaded image
to the space reserved for the Protective MBR and the Primary GUID
Partition Table.
Signed-off-by: Steve Rae s...@broadcom.com
---
README | 7 +++
common/fb_mmc.c | 19 ---
2 files changed, 23 insertions(+), 3 deletions(-)
diff --git a/README b/README
index 66770b6..3b6ef7f 100644
--- a/README
+++ b/README
@@ -1769,6 +1769,13 @@ The following options need to be configured:
regarding the non-volatile storage device. Define
this to the eMMC device that fastboot should use to store the
image.
+ CONFIG_FASTBOOT_GPT_NAME
+ The fastboot flash command supports writing the
downloaded
+ image to the Protective MBR and the Primary GUID
Partition
+ Table. This occurs when the specified partition
name on the
+ fastboot flash command line matches this value.
+ Default is GPT_ENTRY_NAME (currently gpt) if
undefined. +
- Journaling Flash filesystem support:
CONFIG_JFFS2_NAND, CONFIG_JFFS2_NAND_OFF,
CONFIG_JFFS2_NAND_SIZE, CONFIG_JFFS2_NAND_DEV
diff --git a/common/fb_mmc.c b/common/fb_mmc.c
index fb06d8a..89fbf23 100644
--- a/common/fb_mmc.c
+++ b/common/fb_mmc.c
@@ -4,12 +4,17 @@
* SPDX-License-Identifier: GPL-2.0+
*/
+#include config.h
#include common.h
#include fb_mmc.h
#include part.h
#include aboot.h
#include sparse_format.h
+#ifndef CONFIG_FASTBOOT_GPT_NAME
+#define CONFIG_FASTBOOT_GPT_NAME GPT_ENTRY_NAME
+#endif
+
/* The 64 defined bytes plus the '\0' */
#define RESPONSE_LEN (64 + 1)
@@ -62,9 +67,9 @@ static void write_raw_image(block_dev_desc_t
*dev_desc, disk_partition_t *info, void fb_mmc_flash_write(const
char *cmd, void *download_buffer, unsigned int download_bytes, char
*response) {
- int ret;
block_dev_desc_t *dev_desc;
disk_partition_t info;
+ lbaint_t blksz;
/* initialize the response buffer */
response_str = response;
@@ -76,8 +81,16 @@ void fb_mmc_flash_write(const char *cmd, void
*download_buffer, return;
}
- ret = get_partition_info_efi_by_name(dev_desc, cmd,
info);
- if (ret) {
+ if (strcmp(cmd, CONFIG_FASTBOOT_GPT_NAME) == 0) {
+ printf(%s: updating GUID Partition Table
(including MBR)\n,
+ __func__);
+ /* start at Protective MBR */
+ info.start = (GPT_PRIMARY_PARTITION_TABLE_LBA -
1);
+ blksz = dev_desc-blksz;
+ info.blksz = blksz;
+ /* assume that the Partition Entry Array starts in
LBA 2 */
+ info.size = (2 + (GPT_ENTRY_NUMBERS *
GPT_ENTRY_SIZE) / blksz);
+ } else if (get_partition_info_efi_by_name(dev_desc, cmd,
info)) { error(cannot find partition: '%s'\n, cmd);
fastboot_fail(cannot find partition);
return;
Sorry for a late reply. I've just come back from a short holidays.
I'm curious if you have encountered any problems with GPT replaced
in that way?
No -- this technique seems to be fine (for the Primary GPT)
It seems strange to me that you only change primary GPT partition
without taking care of the secondary (backup) one.
It seems that the device operates correctly with or without the
Backup GPT, and it doesn't seem to matter if they are the same or not.
Thus, we have gone back and forth on this one - should we
automatically update the Backup GPT whenever the Primary GPT is
updated, or should there be a second step (possibly a fastboot oem
command) to update the Backup GPT... (currently, we are proposing the
latter) What would you suggest?
I'd suggest updating both of them.
However, it is important to check all available CRC's in the received
image.
In my opinion a separate command for Secondary GPT - fastboot oem -
seems like an overkill.
From my experience when you export your eMMC to Host PC via UMS,
host's PC tools will complain about mismatch in the GPT tables.
( I have never done this - what tools are you using? Could you
provide instructions for me to try? Thanks! )
For Exynos based boards (e.g. Odroid-U3, Trats2) it is possible to use
USB mass storage gadget (ums command in u-boot prompt), which exports
the content of eMMC to host PC and is treated as an ordinary USB stick.
Also you can try parted linux utility.
Moreover, I would suggest transactional update of GPT by checking
GPT image CRC before writing. In this way you can always perform
recovery if needed.
This is a good idea - I'll look into it - Thanks!
Thanks, Steve
--
Best regards,
Lukasz Majewski
Samsung RD Institute Poland (SRPOL) | Linux Platform Group
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Re: [U-Boot] ti, am3517: errata 430973 workaround
Hi, On 12/08/2014 11:19 PM, Jeroen Hofstee wrote: Hi, A while ago [1], a RFC was posted to disable workaround for besides others, errata 430973. It is a bit unclear to me which revision actually need this workaround, but as suggested in [2] also enabling this workaround in Linux seem to make some weird problems go away in linux (signal 4, bad instruction, 11 segfaults etc). As said, I am a bit in doubt why this works. The board in question is a tam3517 derived one: cat /proc/cpuinfo Processor: ARMv7 Processor rev 7 (v7l) BogoMIPS: 397.57 Features: swp half thumb fastmult vfp edsp neon vfpv3 tls CPU implementer: 0x41 CPU architecture: 7 CPU variant: 0x1 CPU part: 0xc08 CPU revision: 7 Which makes this a r1p7 I assume, and hence the workaround of linux, CONFIG_ARM_ERRATA_430973, This option enables the workaround for the 430973 Cortex-A8 (r1p0..r1p2) erratum, should not be needed it seems. On the other hand Andreas Bießman, wrote at [3] I have rev 20.0 from 13-Apr-10. The three mentioned errata should be fixed in r2p1. note, this mentions r2p1 not r1p2! Since I don't have access to ARM Core Cortex-A8 (AT400/AT401) errata, I cannot look this up. Hence the question, is u-boot wrong by enabling this workaround for a r1p7 revision or is the comment in the kernel flawed? (or am I missing something else..) my AT400/AT401/AT490 r20.0 (13-Apr-10) says #430973 affects r1p1,m r1p2, r1p3, r1p7 but none since r2p1. So it seems the kernel is wrong here. Best regards Andreas Bießmann [1] http://lists.denx.de/pipermail/u-boot/2013-July/158377.html [2] http://lists.denx.de/pipermail/u-boot/2013-July/158404.html [3] http://lists.denx.de/pipermail/u-boot/2013-July/158386.html ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] sun6i: Add new board Merrii Hummingbird A31
The Merrii Hummingbird A31 is a A31 based development board with 1G RAM, 8G NAND, AP6210 WiFi+BT, gigabit ethernet, USB OTG, 2 USB 2.0 ports connected to a USB hub chip, HDMI, VGA, TV and stereo in/out. Signed-off-by: Chen-Yu Tsai w...@csie.org --- board/sunxi/Kconfig | 4 configs/Hummingbird_A31_defconfig | 19 +++ 2 files changed, 23 insertions(+) create mode 100644 configs/Hummingbird_A31_defconfig diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig index 6162227..5bb2f58 100644 --- a/board/sunxi/Kconfig +++ b/board/sunxi/Kconfig @@ -112,6 +112,10 @@ config TARGET_CUBIETRUCK bool CUBIETRUCK depends on MACH_SUN7I +config TARGET_HUMMINGBIRD_A31 + bool HUMMINGBIRD_A31 + depends on MACH_SUN6I + config TARGET_IPPO_Q8H_V5 bool IPPO_Q8H_V5 depends on MACH_SUN8I diff --git a/configs/Hummingbird_A31_defconfig b/configs/Hummingbird_A31_defconfig new file mode 100644 index 000..73855c5 --- /dev/null +++ b/configs/Hummingbird_A31_defconfig @@ -0,0 +1,19 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS=USB_EHCI,SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPA(21) +CONFIG_FDTFILE=sun6i-a31-hummingbird.dtb ++S:CONFIG_ARM=y ++S:CONFIG_ARCH_SUNXI=y ++S:CONFIG_MACH_SUN6I=y ++S:CONFIG_TARGET_MERRII_HUMMINGBIRD_A31=y ++S:CONFIG_DRAM_CLK=312 ++S:CONFIG_DRAM_ZQ=251 +# Wifi power ++S:CONFIG_AXP221_ALDO1_VOLT=3300 +# PM-CPUS GPIO power ++S:CONFIG_AXP221_ALDO2_VOLT=1800 +# SoC IR, PLL and Analog power (must be 3.0V) ++S:CONFIG_AXP221_ALDO3_VOLT=3000 +# Vbus gpio for usb1 ++S:CONFIG_USB1_VBUS_PIN=PH24 +# No Vbus gpio for usb2 ++S:CONFIG_USB2_VBUS_PIN= -- 2.1.3 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2] fastboot: handle flash write to GPT partition
Hi Steve,
Implement a feature to allow fastboot to write the downloaded image
to the space reserved for the Protective MBR and the Primary GUID
Partition Table.
Signed-off-by: Steve Rae s...@broadcom.com
---
Changes in v2:
add validation of the GPT before writing to flash
(suggested by: Lukasz Majewski l.majew...@samsung.com)
README | 7 +++
common/fb_mmc.c | 26 +++---
disk/part_efi.c | 37 +
include/part.h | 10 ++
4 files changed, 77 insertions(+), 3 deletions(-)
diff --git a/README b/README
index 4ca04d0..5f50cdd 100644
--- a/README
+++ b/README
@@ -1773,6 +1773,13 @@ The following options need to be configured:
regarding the non-volatile storage device. Define
this to the eMMC device that fastboot should use to store the image.
+ CONFIG_FASTBOOT_GPT_NAME
+ The fastboot flash command supports writing the
downloaded
+ image to the Protective MBR and the Primary GUID
Partition
+ Table. This occurs when the specified partition
name on the
+ fastboot flash command line matches this value.
+ Default is GPT_ENTRY_NAME (currently gpt) if
undefined. +
- Journaling Flash filesystem support:
CONFIG_JFFS2_NAND, CONFIG_JFFS2_NAND_OFF,
CONFIG_JFFS2_NAND_SIZE, CONFIG_JFFS2_NAND_DEV
diff --git a/common/fb_mmc.c b/common/fb_mmc.c
index fb06d8a..a646a7b 100644
--- a/common/fb_mmc.c
+++ b/common/fb_mmc.c
@@ -4,12 +4,17 @@
* SPDX-License-Identifier: GPL-2.0+
*/
+#include config.h
#include common.h
#include fb_mmc.h
#include part.h
#include aboot.h
#include sparse_format.h
+#ifndef CONFIG_FASTBOOT_GPT_NAME
+#define CONFIG_FASTBOOT_GPT_NAME GPT_ENTRY_NAME
+#endif
+
/* The 64 defined bytes plus the '\0' */
#define RESPONSE_LEN (64 + 1)
@@ -62,9 +67,9 @@ static void write_raw_image(block_dev_desc_t
*dev_desc, disk_partition_t *info, void fb_mmc_flash_write(const char
*cmd, void *download_buffer, unsigned int download_bytes, char
*response) {
- int ret;
block_dev_desc_t *dev_desc;
disk_partition_t info;
+ lbaint_t blksz;
/* initialize the response buffer */
response_str = response;
@@ -76,8 +81,23 @@ void fb_mmc_flash_write(const char *cmd, void
*download_buffer, return;
}
- ret = get_partition_info_efi_by_name(dev_desc, cmd, info);
- if (ret) {
+ if (strcmp(cmd, CONFIG_FASTBOOT_GPT_NAME) == 0) {
+ printf(%s: updating GUID Partition Table (including
MBR)\n,
+__func__);
+ /* start at Protective MBR */
+ info.start = (GPT_PRIMARY_PARTITION_TABLE_LBA - 1);
+ blksz = dev_desc-blksz;
+ info.blksz = blksz;
+ /* assume that the Partition Entry Array starts in
LBA 2 */
+ info.size = (2 + (GPT_ENTRY_NUMBERS *
GPT_ENTRY_SIZE) / blksz); +
+ if (is_valid_gpt_primary(download_buffer,
dev_desc-blksz)) {
+ printf(%s: invalid GPT - refusing to write
to flash\n,
+__func__);
+ fastboot_fail(invalid GPT partition);
+ return;
+ }
IMHO some extra code to update secondary (backup) GPT is needed here.
A good example may be at part_efi.c - print_part_efi() function [1].
+ } else if (get_partition_info_efi_by_name(dev_desc, cmd,
info)) { error(cannot find partition: '%s'\n, cmd);
fastboot_fail(cannot find partition);
return;
diff --git a/disk/part_efi.c b/disk/part_efi.c
index efed58f..86cb160 100644
--- a/disk/part_efi.c
+++ b/disk/part_efi.c
@@ -455,6 +455,43 @@ err:
free(gpt_h);
return ret;
}
+
+int is_valid_gpt_primary(void *buf, unsigned long blksz)
The name is a bit misleading - I rather though about something like
is_valid_gpt_buf() and write it in a similar way to is_valid_gpt()
which would allow using it for both primary and secondary GPTs (like in
[1]).
+{
+ int rc = 0;
+ gpt_header *gpt_h;
+ gpt_entry *gpt_e;
+ gpt_header gpt_hdr;
+ uint32_t calc_crc32;
+
+ /* GPT Header starts at LBA[1] in the buffer */
+ gpt_h = buf + blksz;
+ if (gpt_h-signature != cpu_to_le64(GPT_HEADER_SIGNATURE)) {
+ printf(%s: 'signature' is invalid\n, __func__);
+ rc += 1;
+ }
+
+ memcpy(gpt_hdr, gpt_h, sizeof(gpt_header));
+ gpt_hdr.header_crc32 = 0;
+ calc_crc32 = efi_crc32((const unsigned char *)gpt_hdr,
+le32_to_cpu(gpt_h-header_size));
+ if (gpt_h-header_crc32 != cpu_to_le32(calc_crc32)) {
+ printf(%s: 'header_crc32' is invalid\n, __func__);
+ rc += 1;
+ }
+
+ /* GPT Entries start at LBA[2] in the buffer */
+ gpt_e = buf + (2 * blksz);
+ calc_crc32 = efi_crc32((const
Re: [U-Boot] [ANN] U-Boot v2015.01-rc3 released
On 12/09/2014 04:57 AM, Tom Rini wrote: On Mon, Dec 08, 2014 at 07:52:10PM -0600, Robert Nelson wrote: On Mon, Dec 8, 2014 at 3:44 PM, Tom Rini tr...@ti.com wrote: Hey all, I've pushed v2015.01-rc3 out to the repository and tarballs should exist soon. So, we're nearing the end now, relatively speaking, so things should start getting quieter. I'd like everyone to please build their respective areas and make sure everything is building right. As always, if anything else is broken please speak up. On mx53loco_defconfig I'm getting: [snip] Which has a fix: http://git.denx.de/?p=u-boot/u-boot-imx.git;a=summary Yes, but I don't _think_ I missed a pull request. That said, I see: I don't think there ever was a pull request with that fix. Cc-ing Stefano Babic -- Regards, Nikita Kiryanov ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] p5040ds: changed liodn offsets
Offsets were overlaping, causing pamu access violations in
hypervised scenarios.
Signed-off-by: Cristian Sovaiala cristian.sovai...@freescale.com
Signed-off-by: Laurentiu Tudor laurentiu.tu...@freescale.com
Reviewed-by: Fleming Andrew-AFLEMING aflem...@freescale.com
Reviewed-by: Sun Yusong-R58495 york...@freescale.com
---
arch/powerpc/cpu/mpc85xx/p5040_ids.c | 24
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/p5040_ids.c
b/arch/powerpc/cpu/mpc85xx/p5040_ids.c
index d4343ef..98a568f 100644
--- a/arch/powerpc/cpu/mpc85xx/p5040_ids.c
+++ b/arch/powerpc/cpu/mpc85xx/p5040_ids.c
@@ -49,23 +49,23 @@ int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl);
#ifdef CONFIG_SYS_DPAA_FMAN
struct liodn_id_table fman1_liodn_tbl[] = {
- SET_FMAN_RX_1G_LIODN(1, 0, 6),
- SET_FMAN_RX_1G_LIODN(1, 1, 7),
- SET_FMAN_RX_1G_LIODN(1, 2, 8),
- SET_FMAN_RX_1G_LIODN(1, 3, 9),
- SET_FMAN_RX_1G_LIODN(1, 4, 10),
- SET_FMAN_RX_10G_LIODN(1, 0, 11),
+ SET_FMAN_RX_1G_LIODN(1, 0, 11),
+ SET_FMAN_RX_1G_LIODN(1, 1, 12),
+ SET_FMAN_RX_1G_LIODN(1, 2, 13),
+ SET_FMAN_RX_1G_LIODN(1, 3, 14),
+ SET_FMAN_RX_1G_LIODN(1, 4, 15),
+ SET_FMAN_RX_10G_LIODN(1, 0, 16),
};
int fman1_liodn_tbl_sz = ARRAY_SIZE(fman1_liodn_tbl);
#if (CONFIG_SYS_NUM_FMAN == 2)
struct liodn_id_table fman2_liodn_tbl[] = {
- SET_FMAN_RX_1G_LIODN(2, 0, 12),
- SET_FMAN_RX_1G_LIODN(2, 1, 13),
- SET_FMAN_RX_1G_LIODN(2, 2, 14),
- SET_FMAN_RX_1G_LIODN(2, 3, 15),
- SET_FMAN_RX_1G_LIODN(2, 4, 16),
- SET_FMAN_RX_10G_LIODN(2, 0, 17),
+ SET_FMAN_RX_1G_LIODN(2, 0, 17),
+ SET_FMAN_RX_1G_LIODN(2, 1, 18),
+ SET_FMAN_RX_1G_LIODN(2, 2, 19),
+ SET_FMAN_RX_1G_LIODN(2, 3, 20),
+ SET_FMAN_RX_1G_LIODN(2, 4, 21),
+ SET_FMAN_RX_10G_LIODN(2, 0, 22),
};
int fman2_liodn_tbl_sz = ARRAY_SIZE(fman2_liodn_tbl);
#endif
--
1.8.3.1
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Re: [U-Boot] [PATCH] sun6i: Add new board Merrii Hummingbird A31
Hi, On 09-12-14 09:56, Chen-Yu Tsai wrote: The Merrii Hummingbird A31 is a A31 based development board with 1G RAM, 8G NAND, AP6210 WiFi+BT, gigabit ethernet, USB OTG, 2 USB 2.0 ports connected to a USB hub chip, HDMI, VGA, TV and stereo in/out. Signed-off-by: Chen-Yu Tsai w...@csie.org Thanks, queued up for v2015.04 in u-boot-sunxi/next . Regards, Hans --- board/sunxi/Kconfig | 4 configs/Hummingbird_A31_defconfig | 19 +++ 2 files changed, 23 insertions(+) create mode 100644 configs/Hummingbird_A31_defconfig diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig index 6162227..5bb2f58 100644 --- a/board/sunxi/Kconfig +++ b/board/sunxi/Kconfig @@ -112,6 +112,10 @@ config TARGET_CUBIETRUCK bool CUBIETRUCK depends on MACH_SUN7I +config TARGET_HUMMINGBIRD_A31 + bool HUMMINGBIRD_A31 + depends on MACH_SUN6I + config TARGET_IPPO_Q8H_V5 bool IPPO_Q8H_V5 depends on MACH_SUN8I diff --git a/configs/Hummingbird_A31_defconfig b/configs/Hummingbird_A31_defconfig new file mode 100644 index 000..73855c5 --- /dev/null +++ b/configs/Hummingbird_A31_defconfig @@ -0,0 +1,19 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS=USB_EHCI,SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPA(21) +CONFIG_FDTFILE=sun6i-a31-hummingbird.dtb ++S:CONFIG_ARM=y ++S:CONFIG_ARCH_SUNXI=y ++S:CONFIG_MACH_SUN6I=y ++S:CONFIG_TARGET_MERRII_HUMMINGBIRD_A31=y ++S:CONFIG_DRAM_CLK=312 ++S:CONFIG_DRAM_ZQ=251 +# Wifi power ++S:CONFIG_AXP221_ALDO1_VOLT=3300 +# PM-CPUS GPIO power ++S:CONFIG_AXP221_ALDO2_VOLT=1800 +# SoC IR, PLL and Analog power (must be 3.0V) ++S:CONFIG_AXP221_ALDO3_VOLT=3000 +# Vbus gpio for usb1 ++S:CONFIG_USB1_VBUS_PIN=PH24 +# No Vbus gpio for usb2 ++S:CONFIG_USB2_VBUS_PIN= ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/2] sun6i: Update Colombus defconfig settings
Hi, On 08-12-14 12:04, Ian Campbell wrote: On Mon, 2014-12-08 at 11:59 +0100, Hans de Goede wrote: Hi, On 08-12-14 10:31, Ian Campbell wrote: On Mon, 2014-12-08 at 09:26 +, Ian Campbell wrote: On Sun, 2014-12-07 at 21:23 +0100, Hans de Goede wrote: The Colombus defconfig settings are missing a number of settings for recently added features, because we did not know exactly how things were hooked up. Maxime Ripard has run various tests to get us the necessary details, this commit updates the defconfig with this info. This commit also updates the dram clk and zq values with values verified by Maxime to be the ones used by the original firmware for this board. Signed-off-by: Hans de Goede hdego...@redhat.com Acked-by: Ian Campbell ian.campb...@citrix.com Ooops, rather make that i...@hellion.org.uk, as usual... Thanks for the reviews, I've queued both of these up in u-boot-sunxi/next (also rebased on latest origin/master, so I've done a forced push). I would also like to queue these 2 up, if you've some time can you please review them ? : http://patchwork.ozlabs.org/patch/415109/ http://patchwork.ozlabs.org/patch/415110/ Ack to both of those too. Thanks, I've queued both of them up in u-boot-sunxi/next (Also rebased on rc3, so I did another forced push) Regards, Hans ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [ANN] U-Boot v2015.01-rc3 released
On 09/12/2014 10:14, Nikita Kiryanov wrote: On 12/09/2014 04:57 AM, Tom Rini wrote: On Mon, Dec 08, 2014 at 07:52:10PM -0600, Robert Nelson wrote: On Mon, Dec 8, 2014 at 3:44 PM, Tom Rini tr...@ti.com wrote: Hey all, I've pushed v2015.01-rc3 out to the repository and tarballs should exist soon. So, we're nearing the end now, relatively speaking, so things should start getting quieter. I'd like everyone to please build their respective areas and make sure everything is building right. As always, if anything else is broken please speak up. On mx53loco_defconfig I'm getting: [snip] Which has a fix: http://git.denx.de/?p=u-boot/u-boot-imx.git;a=summary Yes, but I don't _think_ I missed a pull request. That said, I see: I don't think there ever was a pull request with that fix. Cc-ing Stefano Babic Fix is in u-boot-imx. I will still merge a couple of patches and then I send a PR to Tom. Thanks, Stefano -- = DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de = ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v5] arm: ls102xa: Add NAND boot support for LS1021AQDS board
This patch adds NAND boot support for LS1021AQDS board. SPL
framework is used. PBL initialize the internal RAM and copy
SPL to it, then SPL initialize DDR using SPD and copy u-boot
from NAND flash to DDR, finally SPL transfer control to u-boot.
Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
Signed-off-by: Alison Wang alison.w...@freescale.com
---
Change log:
v2: Rebase the patch.
Add CONFIG_SYS_DCSR_DCFG_ADDR instead of CONFIG_SYS_DCSRBAR.
arch/arm/include/asm/arch-ls102xa/config.h| 3 +
arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 5 ++
board/freescale/ls1021aqds/MAINTAINERS| 1 +
board/freescale/ls1021aqds/ls1021aqds.c | 16 +
board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg | 7 +++
configs/ls1021aqds_nand_defconfig | 4 ++
drivers/mtd/nand/fsl_ifc_spl.c| 10
include/configs/ls1021aqds.h | 72 +++
8 files changed, 118 insertions(+)
create mode 100644 board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg
create mode 100644 configs/ls1021aqds_nand_defconfig
diff --git a/arch/arm/include/asm/arch-ls102xa/config.h
b/arch/arm/include/asm/arch-ls102xa/config.h
index 4d484f5..b79d190 100644
--- a/arch/arm/include/asm/arch-ls102xa/config.h
+++ b/arch/arm/include/asm/arch-ls102xa/config.h
@@ -17,6 +17,9 @@
#define CONFIG_SYS_IMMR0x0100
#define CONFIG_SYS_DCSRBAR 0x2000
+#define CONFIG_SYS_DCSR_DCFG_ADDR \
+ (CONFIG_SYS_DCSRBAR + 0x0022)
+
#define CONFIG_SYS_FSL_DDR_ADDR(CONFIG_SYS_IMMR +
0x0008)
#define CONFIG_SYS_CCI400_ADDR (CONFIG_SYS_IMMR + 0x0018)
#define CONFIG_SYS_FSL_CSU_ADDR (CONFIG_SYS_IMMR + 0x0051)
diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
index d965426..697d4ca 100644
--- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
+++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
@@ -32,6 +32,11 @@
#define ARCH_TIMER_CTRL_ENABLE (1 0)
#define SYS_COUNTER_CTRL_ENABLE(1 24)
+#define DCFG_CCSR_PORSR1_RCW_MASK 0xff80
+#define DCFG_CCSR_PORSR1_RCW_SRC_I2C 0x2480
+
+#define DCFG_DCSR_PORCR1 0
+
struct sys_info {
unsigned long freq_processor[CONFIG_MAX_CPUS];
unsigned long freq_systembus;
diff --git a/board/freescale/ls1021aqds/MAINTAINERS
b/board/freescale/ls1021aqds/MAINTAINERS
index 7a704cf..638833d 100644
--- a/board/freescale/ls1021aqds/MAINTAINERS
+++ b/board/freescale/ls1021aqds/MAINTAINERS
@@ -8,3 +8,4 @@ F: configs/ls1021aqds_ddr4_nor_defconfig
F: configs/ls1021aqds_nor_SECURE_BOOT_defconfig
F: configs/ls1021aqds_sdcard_defconfig
F: configs/ls1021aqds_qspi_defconfig
+F: configs/ls1021aqds_nand_defconfig
diff --git a/board/freescale/ls1021aqds/ls1021aqds.c
b/board/freescale/ls1021aqds/ls1021aqds.c
index 56635f9..f08e54f 100644
--- a/board/freescale/ls1021aqds/ls1021aqds.c
+++ b/board/freescale/ls1021aqds/ls1021aqds.c
@@ -203,6 +203,22 @@ void board_init_f(ulong dummy)
{
struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
+#ifdef CONFIG_NAND_BOOT
+ struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+ u32 porsr1, pinctl;
+
+ /*
+* There is LS1 SoC issue where NOR, FPGA are inaccessible during
+* NAND boot because IFC signals IFC_AD7 are not enabled.
+* This workaround changes RCW source to make all signals enabled.
+*/
+ porsr1 = in_be32(gur-porsr1);
+ pinctl = ((porsr1 ~(DCFG_CCSR_PORSR1_RCW_MASK)) |
+DCFG_CCSR_PORSR1_RCW_SRC_I2C);
+ out_be32((unsigned int *)(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1),
+pinctl);
+#endif
+
/* Set global data pointer */
gd = gdata;
diff --git a/board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg
b/board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg
new file mode 100644
index 000..222c71d
--- /dev/null
+++ b/board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg
@@ -0,0 +1,7 @@
+#PBL preamble and RCW header
+aa55aa55 01ee0100
+# serdes protocol
+0608000a
+6000 00407900 e0106a00 21046000
+ 00038000
+ 001b7200
diff --git a/configs/ls1021aqds_nand_defconfig
b/configs/ls1021aqds_nand_defconfig
new file mode 100644
index 000..dad5274
--- /dev/null
+++ b/configs/ls1021aqds_nand_defconfig
@@ -0,0 +1,4 @@
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS=RAMBOOT_PBL,SPL_FSL_PBL,NAND_BOOT
++S:CONFIG_ARM=y
++S:CONFIG_TARGET_LS1021AQDS=y
diff --git a/drivers/mtd/nand/fsl_ifc_spl.c b/drivers/mtd/nand/fsl_ifc_spl.c
index e336cb1..fb827c5 100644
--- a/drivers/mtd/nand/fsl_ifc_spl.c
+++ b/drivers/mtd/nand/fsl_ifc_spl.c
@@ -254,3 +254,13 @@ void nand_boot(void)
uboot = (void
[U-Boot] [PATCH v2] arm: ls102xa: Add QSPI boot support for LS1021AQDS/TWR board
This patch adds QSPI boot support for LS1021AQDS/TWR board.
The QSPI boot image need to be programmed into the QSPI flash
first. Then the booting will start from QSPI memory space.
Signed-off-by: Alison Wang alison.w...@freescale.com
---
Change log:
v2: Rebase the patch.
arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 1 +
board/freescale/ls1021aqds/MAINTAINERS| 1 +
board/freescale/ls1021aqds/ls1021aqds.c | 8 ++
board/freescale/ls1021atwr/MAINTAINERS| 1 +
board/freescale/ls1021atwr/ls1021atwr.c | 14 ++
configs/ls1021aqds_qspi_defconfig | 3 ++
configs/ls1021atwr_qspi_defconfig | 3 ++
include/configs/ls1021aqds.h | 34 +++
include/configs/ls1021atwr.h | 28 +++
9 files changed, 93 insertions(+)
create mode 100644 configs/ls1021aqds_qspi_defconfig
create mode 100644 configs/ls1021atwr_qspi_defconfig
diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
index 44a2c86..d965426 100644
--- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
+++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
@@ -101,6 +101,7 @@ struct ccsr_gur {
#define SCFG_ETSECDMAMCR_LE_BD_FR 0xf8001a0f
#define SCFG_ETSECCMCR_GE2_CLK125 0x0400
#define SCFG_PIXCLKCR_PXCKEN 0x8000
+#define SCFG_QSPI_CLKSEL 0xc010
/* Supplemental Configuration Unit */
struct ccsr_scfg {
diff --git a/board/freescale/ls1021aqds/MAINTAINERS
b/board/freescale/ls1021aqds/MAINTAINERS
index 962176b..7a704cf 100644
--- a/board/freescale/ls1021aqds/MAINTAINERS
+++ b/board/freescale/ls1021aqds/MAINTAINERS
@@ -7,3 +7,4 @@ F: configs/ls1021aqds_nor_defconfig
F: configs/ls1021aqds_ddr4_nor_defconfig
F: configs/ls1021aqds_nor_SECURE_BOOT_defconfig
F: configs/ls1021aqds_sdcard_defconfig
+F: configs/ls1021aqds_qspi_defconfig
diff --git a/board/freescale/ls1021aqds/ls1021aqds.c
b/board/freescale/ls1021aqds/ls1021aqds.c
index 3d6292e..56635f9 100644
--- a/board/freescale/ls1021aqds/ls1021aqds.c
+++ b/board/freescale/ls1021aqds/ls1021aqds.c
@@ -50,7 +50,9 @@ enum {
int checkboard(void)
{
+#ifndef CONFIG_QSPI_BOOT
char buf[64];
+#endif
#if !defined(CONFIG_SD_BOOT) !defined(CONFIG_QSPI_BOOT)
u8 sw;
#endif
@@ -77,12 +79,14 @@ int checkboard(void)
printf(invalid setting of SW%u\n, QIXIS_LBMAP_SWITCH);
#endif
+#ifndef CONFIG_QSPI_BOOT
printf(Sys ID:0x%02x, Sys Ver: 0x%02x\n,
QIXIS_READ(id), QIXIS_READ(arch));
printf(FPGA: v%d (%s), build %d\n,
(int)QIXIS_READ(scver), qixis_read_tag(buf),
(int)qixis_read_minor());
+#endif
return 0;
}
@@ -180,6 +184,10 @@ int board_early_init_f(void)
init_early_memctl_regs();
#endif
+#ifdef CONFIG_FSL_QSPI
+ out_be32(scfg-qspi_cfg, SCFG_QSPI_CLKSEL);
+#endif
+
/* Workaround for the issue that DDR could not respond to
* barrier transaction which is generated by executing DSB/ISB
* instruction. Set CCI-400 control override register to
diff --git a/board/freescale/ls1021atwr/MAINTAINERS
b/board/freescale/ls1021atwr/MAINTAINERS
index 2312e00..9176706 100644
--- a/board/freescale/ls1021atwr/MAINTAINERS
+++ b/board/freescale/ls1021atwr/MAINTAINERS
@@ -6,3 +6,4 @@ F: include/configs/ls1021atwr.h
F: configs/ls1021atwr_nor_defconfig
F: configs/ls1021atwr_nor_SECURE_BOOT_defconfig
F: configs/ls1021atwr_sdcard_defconfig
+F: configs/ls1021atwr_qspi_defconfig
diff --git a/board/freescale/ls1021atwr/ls1021atwr.c
b/board/freescale/ls1021atwr/ls1021atwr.c
index 6f6196b..8ab229d 100644
--- a/board/freescale/ls1021atwr/ls1021atwr.c
+++ b/board/freescale/ls1021atwr/ls1021atwr.c
@@ -74,6 +74,7 @@ struct cpld_data {
u8 rev2;/* Reserved */
};
+#ifndef CONFIG_QSPI_BOOT
static void convert_serdes_mux(int type, int need_reset);
void cpld_show(void)
@@ -109,11 +110,14 @@ void cpld_show(void)
in_8(cpld_data-serdes_mux));
#endif
}
+#endif
int checkboard(void)
{
puts(Board: LS1021ATWR\n);
+#ifndef CONFIG_QSPI_BOOT
cpld_show();
+#endif
return 0;
}
@@ -222,6 +226,7 @@ int board_eth_init(bd_t *bis)
}
#endif
+#ifndef CONFIG_QSPI_BOOT
int config_serdes_mux(void)
{
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
@@ -253,6 +258,7 @@ int config_serdes_mux(void)
return 0;
}
+#endif
int board_early_init_f(void)
{
@@ -271,6 +277,10 @@ int board_early_init_f(void)
out_be32(scfg-pixclkcr, SCFG_PIXCLKCR_PXCKEN);
#endif
+#ifdef CONFIG_FSL_QSPI
+ out_be32(scfg-qspi_cfg, SCFG_QSPI_CLKSEL);
+#endif
+
return 0;
}
@@ -410,8 +420,10 @@ int board_init(void)
#ifndef CONFIG_SYS_FSL_NO_SERDES
fsl_serdes_init();
+#ifndef
Re: [U-Boot] [PATCH] sun6i: Add new board Merrii Hummingbird A31
p.s. On 09-12-14 09:56, Chen-Yu Tsai wrote: The Merrii Hummingbird A31 is a A31 based development board with 1G RAM, 8G NAND, AP6210 WiFi+BT, gigabit ethernet, USB OTG, 2 USB 2.0 ports connected to a USB hub chip, HDMI, VGA, TV and stereo in/out. Signed-off-by: Chen-Yu Tsai w...@csie.org --- board/sunxi/Kconfig | 4 configs/Hummingbird_A31_defconfig | 19 +++ 2 files changed, 23 insertions(+) create mode 100644 configs/Hummingbird_A31_defconfig diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig index 6162227..5bb2f58 100644 --- a/board/sunxi/Kconfig +++ b/board/sunxi/Kconfig @@ -112,6 +112,10 @@ config TARGET_CUBIETRUCK bool CUBIETRUCK depends on MACH_SUN7I +config TARGET_HUMMINGBIRD_A31 + bool HUMMINGBIRD_A31 + depends on MACH_SUN6I + config TARGET_IPPO_Q8H_V5 bool IPPO_Q8H_V5 depends on MACH_SUN8I diff --git a/configs/Hummingbird_A31_defconfig b/configs/Hummingbird_A31_defconfig new file mode 100644 index 000..73855c5 --- /dev/null +++ b/configs/Hummingbird_A31_defconfig @@ -0,0 +1,19 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS=USB_EHCI,SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPA(21) +CONFIG_FDTFILE=sun6i-a31-hummingbird.dtb ++S:CONFIG_ARM=y ++S:CONFIG_ARCH_SUNXI=y ++S:CONFIG_MACH_SUN6I=y ++S:CONFIG_TARGET_MERRII_HUMMINGBIRD_A31=y ++S:CONFIG_DRAM_CLK=312 ++S:CONFIG_DRAM_ZQ=251 +# Wifi power ++S:CONFIG_AXP221_ALDO1_VOLT=3300 +# PM-CPUS GPIO power Interesting where did you get this info from ? ++S:CONFIG_AXP221_ALDO2_VOLT=1800 +# SoC IR, PLL and Analog power (must be 3.0V) Idem, I think we should probably make 3000 the default in Kconfig then, agreed ? ++S:CONFIG_AXP221_ALDO3_VOLT=3000 +# Vbus gpio for usb1 ++S:CONFIG_USB1_VBUS_PIN=PH24 +# No Vbus gpio for usb2 ++S:CONFIG_USB2_VBUS_PIN= Regards, Hans ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] sun6i: Add new board Merrii Hummingbird A31
Hi, On Tue, Dec 9, 2014 at 5:10 PM, Hans de Goede hdego...@redhat.com wrote: p.s. On 09-12-14 09:56, Chen-Yu Tsai wrote: The Merrii Hummingbird A31 is a A31 based development board with 1G RAM, 8G NAND, AP6210 WiFi+BT, gigabit ethernet, USB OTG, 2 USB 2.0 ports connected to a USB hub chip, HDMI, VGA, TV and stereo in/out. Signed-off-by: Chen-Yu Tsai w...@csie.org --- board/sunxi/Kconfig | 4 configs/Hummingbird_A31_defconfig | 19 +++ 2 files changed, 23 insertions(+) create mode 100644 configs/Hummingbird_A31_defconfig diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig index 6162227..5bb2f58 100644 --- a/board/sunxi/Kconfig +++ b/board/sunxi/Kconfig @@ -112,6 +112,10 @@ config TARGET_CUBIETRUCK bool CUBIETRUCK depends on MACH_SUN7I +config TARGET_HUMMINGBIRD_A31 + bool HUMMINGBIRD_A31 + depends on MACH_SUN6I + config TARGET_IPPO_Q8H_V5 bool IPPO_Q8H_V5 depends on MACH_SUN8I diff --git a/configs/Hummingbird_A31_defconfig b/configs/Hummingbird_A31_defconfig new file mode 100644 index 000..73855c5 --- /dev/null +++ b/configs/Hummingbird_A31_defconfig @@ -0,0 +1,19 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS=USB_EHCI,SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPA(21) +CONFIG_FDTFILE=sun6i-a31-hummingbird.dtb ++S:CONFIG_ARM=y ++S:CONFIG_ARCH_SUNXI=y ++S:CONFIG_MACH_SUN6I=y ++S:CONFIG_TARGET_MERRII_HUMMINGBIRD_A31=y ++S:CONFIG_DRAM_CLK=312 ++S:CONFIG_DRAM_ZQ=251 +# Wifi power ++S:CONFIG_AXP221_ALDO1_VOLT=3300 +# PM-CPUS GPIO power Interesting where did you get this info from ? I have the schematics for the board, downloaded from Merrii's forum. It has all the outputs of the PMIC, what they're connected to, assigned voltage, etc.. ++S:CONFIG_AXP221_ALDO2_VOLT=1800 +# SoC IR, PLL and Analog power (must be 3.0V) Idem, I think we should probably make 3000 the default in Kconfig then, agreed ? I think it's a safe bet. That part of the schematic matches the one found in Olimex's repository. ++S:CONFIG_AXP221_ALDO3_VOLT=3000 +# Vbus gpio for usb1 ++S:CONFIG_USB1_VBUS_PIN=PH24 +# No Vbus gpio for usb2 ++S:CONFIG_USB2_VBUS_PIN= ChenYu ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2] arm: ls1021a: Add CONFIG_DOS_PARTITION and CONFIG_CMD_FAT support
This patch will fix the bug that the partitions on the SD card could not be accessed and add the support for the FAT fs. Signed-off-by: Alison Wang alison.w...@freescale.com --- Change log: v2: Rebase the patch. include/configs/ls1021aqds.h | 3 +++ include/configs/ls1021atwr.h | 3 +++ 2 files changed, 6 insertions(+) diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index e49abe5..f906215 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -312,6 +312,9 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_FSL_ESDHC #define CONFIG_GENERIC_MMC +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION + /* * USB */ diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index e84a1b5..db93201 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -240,6 +240,9 @@ #define CONFIG_FSL_ESDHC #define CONFIG_GENERIC_MMC +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION + /* * Video */ -- 2.1.0.27.g96db324 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v1] arm: ls102xa: Fix SD/NAND/QSPI boot defination error for QE support
The SD/NAND/QSPI boot definations are wrong for QE support, this patch is to fix this error. Signed-off-by: Alison Wang alison.w...@freescale.com --- include/configs/ls1021aqds.h | 3 ++- include/configs/ls1021atwr.h | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index f906215..6a6f620 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -104,7 +104,8 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_FSL_CAAM/* Enable CAAM */ -#if !defined(CONFIG_SDCARD) !defined(CONFIG_NAND) !defined(CONFIG_SPI) +#if !defined(CONFIG_SD_BOOT) !defined(CONFIG_NAND_BOOT) \ + !defined(CONFIG_QSPI_BOOT) #define CONFIG_U_QE #endif diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index db93201..9a497a6 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -110,7 +110,8 @@ #define CONFIG_FSL_CAAM/* Enable CAAM */ -#if !defined(CONFIG_SDCARD) !defined(CONFIG_NAND) !defined(CONFIG_SPI) +#if !defined(CONFIG_SD_BOOT) !defined(CONFIG_NAND_BOOT) \ + !defined(CONFIG_QSPI_BOOT) #define CONFIG_U_QE #endif -- 2.1.0.27.g96db324 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v1] ls102xa: etsec: Select ge0_clk125 for eTSEC clock muxing as default
This patch reverts to use ge0_clk125 for eTSEC clock muxing. For SAI and
CAN which are pin multiplexed with RGMII1 in EC1 of RCW, ge2_clk125 will
be used via hwconfig.
Signed-off-by: Bhupesh Sharma bhupesh.sha...@freescale.com
Signed-off-by: Alison Wang alison.w...@freescale.com
---
arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 2 ++
board/freescale/ls1021aqds/ls1021aqds.c | 35 ++-
2 files changed, 36 insertions(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
index 697d4ca..afdccdc 100644
--- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
+++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
@@ -105,6 +105,8 @@ struct ccsr_gur {
#define SCFG_ETSECDMAMCR_LE_BD_FR 0xf8001a0f
#define SCFG_ETSECCMCR_GE2_CLK125 0x0400
+#define SCFG_ETSECCMCR_GE0_CLK125 0x
+#define SCFG_ETSECCMCR_GE1_CLK125 0x0800
#define SCFG_PIXCLKCR_PXCKEN 0x8000
#define SCFG_QSPI_CLKSEL 0xc010
diff --git a/board/freescale/ls1021aqds/ls1021aqds.c
b/board/freescale/ls1021aqds/ls1021aqds.c
index f08e54f..f4a5dda 100644
--- a/board/freescale/ls1021aqds/ls1021aqds.c
+++ b/board/freescale/ls1021aqds/ls1021aqds.c
@@ -48,6 +48,12 @@ enum {
MUX_TYPE_SD_PC_SG_SG,
};
+enum {
+ GE0_CLK125,
+ GE2_CLK125,
+ GE1_CLK125,
+};
+
int checkboard(void)
{
#ifndef CONFIG_QSPI_BOOT
@@ -177,7 +183,6 @@ int board_early_init_f(void)
#ifdef CONFIG_TSEC_ENET
out_be32(scfg-etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
- out_be32(scfg-etsecmcr, SCFG_ETSECCMCR_GE2_CLK125);
#endif
#ifdef CONFIG_FSL_IFC
@@ -244,6 +249,32 @@ void board_init_f(ulong dummy)
}
#endif
+void config_etseccm_source(int etsec_gtx_125_mux)
+{
+ struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
+
+ switch (etsec_gtx_125_mux) {
+ case GE0_CLK125:
+ out_be32(scfg-etsecmcr, SCFG_ETSECCMCR_GE0_CLK125);
+ debug(etseccm set to GE0_CLK125\n);
+ break;
+
+ case GE2_CLK125:
+ out_be32(scfg-etsecmcr, SCFG_ETSECCMCR_GE2_CLK125);
+ debug(etseccm set to GE2_CLK125\n);
+ break;
+
+ case GE1_CLK125:
+ out_be32(scfg-etsecmcr, SCFG_ETSECCMCR_GE1_CLK125);
+ debug(etseccm set to GE1_CLK125\n);
+ break;
+
+ default:
+ printf(Error! trying to set etseccm to invalid value\n);
+ break;
+ }
+}
+
int config_board_mux(int ctrl_type)
{
u8 reg12, reg14;
@@ -253,6 +284,7 @@ int config_board_mux(int ctrl_type)
switch (ctrl_type) {
case MUX_TYPE_CAN:
+ config_etseccm_source(GE2_CLK125);
reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_CAN);
break;
case MUX_TYPE_IIC2:
@@ -262,6 +294,7 @@ int config_board_mux(int ctrl_type)
reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_RGMII);
break;
case MUX_TYPE_SAI:
+ config_etseccm_source(GE2_CLK125);
reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_SAI);
break;
case MUX_TYPE_SDHC:
--
2.1.0.27.g96db324
___
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Re: [U-Boot] [PATCH v9 2/2] Odroid-XU3: Add documentation for Odroid-XU3
Hi Kevin, Lukasz Majewski l.majew...@majess.pl writes: [...] On 28 November 2014 at 06:46, Lukasz Majewski l.majew...@majess.pl wrote: Hello Javier, Hello Lukasz, On Fri, Nov 28, 2014 at 9:39 AM, Lukasz Majewski l.majew...@majess.pl wrote: I have yet to take him up on that offer though, but it sounds like a good way forward. The current layout really isn't practical. It indeed isn't very practical, but this is what you received from HardKernel when you buy XU3 board. Of course you can grab their sources, modify the layout, prepare u-boot's SPL and send it to them to be signed. However, it is not the way the normal user do things. He or she would like to replace standard (and outdated) HardKernel u-boot on their SD card and go forward with booting kernel. I agree with Sjoed that normal users don't replace the low-level components that are provided by the board vendor. After all you can boot a mainline kernel using the vendor u-boot, just append the DTB and create a uImage. The practical reason why someone would want to replace the vendor u-boot is to have more features but is very hard to do if there is a constraint in the maximum u-boot image size (even harder if the maximum is such small like in the XU3). I agree that 328 KiB size for u-boot is a constraint. I don't know HardKernel's justification for this. For now we _must_ focus on supporting XU3 with default BL1/BL2 and hence we are obliged to have u-boot size smaller than 328 KiB. It is challenging but for sure doable. It is doable but I don't see why the default BL2 _must_ be used. For practical/pragmatic reasons: 1. It is difficult to have signed BL2 - each time we need to ask HardKernel for signing it. It is impractical and hampers usage of mainline SPL (BL2) with XU3. 2. All the documentation on the HardKernel wiki site refers to the default BL2. 3. We will have new BL2, which source code is based on 2012.07 mainline u-boot. 4. Two BL2 binaries - IMHO will hurt (i.e. brick) some device sooner or latter. A user that wants to replace the kernel or u-boot is already tech-savy and can for sure replace the BL2 as well if it's publicly available. Sorry, but I'm a bit sceptical about updating such low level code. Bad things do happen. Maybe hardkernel folks can even make the modified BL2 available on their website and the link added in the comment explaining the layout? We would then require HardKernel to: 1. Provide updated BL2.img 2. Update their wiki to reflect the new BL2. Also, it is an artificial constraint after all and can be easily modified. In fact I think we should push hardkernel to change that layout by default and use a BL2/SPL that has more sensible size for the u-boot binary even if they don't need it for their vendor u-boot which seems to be quite small. I totally agree. I'd like to propose a following plan: 1. Accept Hyungwon's patches to have XU3 u-boot 328 KiB (with link to default BL2) to have XU3 support in place (and treat it as a starting point) 2. If u-boot's size less than 328 KiB is _really_ a problem to somebody then ask hardkernel to change BL2 or: - modify their sources to change the layout (I regard this as a quick hack solution) - with a lot of pain develop BL2/SPL (by whom?) which base on newest mainline (then for each test hardkernel must sign the binary). My 2p worth... The current Hardkernel BL1 looks broken to me - it is just too old. +1 FWIW, the XU3 firmware is broken in other ways as well which have a major impact on power management. First, with mainline kernels using MCPM, only 6 of 8 CPUs come online. However, even with that fixed[1], it turns out that the kernel can't properly manage CCI due to secure firmware[2], which means that MCPM (multi-cluster power management) can't work, and thus the low-power cluster-idle states can't work, the big.LITTLE switcher cannot work, and the ongoing work on energy-aware scheduling will not be useful on this platform. I've stumbled upon the imprecise aborts in Exynos5422. Moreover I've heard about problems with bringing up all 8 CPUs on that platform. Anyone know what are the chances of getting a non-secure version of the firmware for this platform. The Samsung Chromebook2 with basically the same SoC (5800 compared to the 5422 on the XU3) ships with non-secure firmware so all of the above mentioned features are working just fine. You can look into the HardKernle's u-boot from their github: https://github.com/hardkernel/u-boot then tune it and send to hardkernel to be signed. I guess that the described above problem might be with TZSW software - the one from Chromebook2 might be
Re: [U-Boot] [PATCH ] MMC: add MMC_VERSION_5_0
Am 18.11.2014 um 15:13 schrieb Markus Niebel: Ping - any comments? From: Markus Niebel markus.nie...@tq-group.com Signed-off-by: Markus Niebel markus.nie...@tq-group.com --- drivers/mmc/mmc.c | 3 +++ include/mmc.h | 1 + 2 files changed, 4 insertions(+) diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index 24b0989..144c7f7 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -1001,6 +1001,9 @@ static int mmc_startup(struct mmc *mmc) case 6: mmc-version = MMC_VERSION_4_5; break; + case 7: + mmc-version = MMC_VERSION_5_0; + break; } /* diff --git a/include/mmc.h b/include/mmc.h index cb91565..51ee24b 100644 --- a/include/mmc.h +++ b/include/mmc.h @@ -31,6 +31,7 @@ #define MMC_VERSION_4_3 (MMC_VERSION_MMC | 0x403) #define MMC_VERSION_4_41 (MMC_VERSION_MMC | 0x429) #define MMC_VERSION_4_5 (MMC_VERSION_MMC | 0x405) +#define MMC_VERSION_5_0 (MMC_VERSION_MMC | 0x500) #define MMC_MODE_HS (1 0) #define MMC_MODE_HS_52MHz(1 1) ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] A23 u-boot with SPL / dram init available in my personal git repo
Hi, On Tue, Dec 9, 2014 at 2:53 AM, Hans de Goede hdego...@redhat.com wrote: Hi, On 08-12-14 15:28, Chen-Yu Tsai wrote: On Mon, Dec 8, 2014 at 4:27 AM, Hans de Goede hdego...@redhat.com wrote: Hi, This is still a bit rough around the edges, I'll clean it up as time permits and then post it upstream. In the mean time people interested can find $subject here: https://github.com/jwrdegoede/u-boot-sunxi/commits/sunxi-wip Hopefully I'll get around to testing this. BTW, what tablet do you have? I've an Ippo q8h v1.2, there are at least 2 differences from the v5 you've. The dram clk speed and zq value are different, and the wifi is different. The wifi does not matter for u-boot, but does mean we need separate dtb files for the 2. My u-boot sunxi-wip branch has a defconfig for the v1.2, you should be able to copy that over to the v5 defconfig, adjust dram clk and zq values with the ones from the v5 fix, change v1.2 to v5 in the CONFIG_FDTFILE setting and thats it. Let me know if this works, then I'll also include an update for the v5 defconfig to enable the SPL when I send this upstream. Just gave it a spin, and it works. The dram clock and zq can be found in sunxi-boards. Note that the actual settings fetched from stock u-boot has the highest bit of tpr13 set, disabling auto detection AFAICU. As you've not implemented that part, I used auto detection and it seems to work. The only problem I have now is it has no connectivity to the outside world lol. I would've liked a v2, with a Realtek USB WiFi chip. What chip does the v1.2 have? ChenYu, this also has a mmc fix which you may find interesting, it may explain some of the problems with mmc you've been having on both the A80 board, as well as the A31 dev board you've. Yes. With that fix my Hummingbird A31 boots properly without raising DCDC1 to 3.3V. Thanks! I'll send the defconfig out later. Good, so I guess this means that DCDC1 should be 3V for your board, since that is what the factory firmware uses, right ? I guess it is time to make DCDC1 voltage configurable. 3V seems to be the lowest tolerable voltage for some bits. Making it 3.3V might be a bit better. But with my light usage, I don't see any stability issues. ChenYu ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] A23 u-boot with SPL / dram init available in my personal git repo
Hi, On 09-12-14 11:17, Chen-Yu Tsai wrote: Hi, On Tue, Dec 9, 2014 at 2:53 AM, Hans de Goede hdego...@redhat.com wrote: Hi, On 08-12-14 15:28, Chen-Yu Tsai wrote: On Mon, Dec 8, 2014 at 4:27 AM, Hans de Goede hdego...@redhat.com wrote: Hi, This is still a bit rough around the edges, I'll clean it up as time permits and then post it upstream. In the mean time people interested can find $subject here: https://github.com/jwrdegoede/u-boot-sunxi/commits/sunxi-wip Hopefully I'll get around to testing this. BTW, what tablet do you have? I've an Ippo q8h v1.2, there are at least 2 differences from the v5 you've. The dram clk speed and zq value are different, and the wifi is different. The wifi does not matter for u-boot, but does mean we need separate dtb files for the 2. My u-boot sunxi-wip branch has a defconfig for the v1.2, you should be able to copy that over to the v5 defconfig, adjust dram clk and zq values with the ones from the v5 fix, change v1.2 to v5 in the CONFIG_FDTFILE setting and thats it. Let me know if this works, then I'll also include an update for the v5 defconfig to enable the SPL when I send this upstream. Just gave it a spin, and it works. The dram clock and zq can be found in sunxi-boards. Good, I'll update my patch-set to reflect this. Note that the actual settings fetched from stock u-boot has the highest bit of tpr13 set, disabling auto detection AFAICU. As you've not implemented that part, I used auto detection and it seems to work. It is implemented in the actual dram_init code, but for now I've all the dram_paras hardcoded except the clk and the zq value. If autodetect works I see no reason to change this, but for future models, if necessary the code for dealing with manual config is there, to test just put the values directly in the dram_para struct at the top of dram_sun8i.c . The only problem I have now is it has no connectivity to the outside world lol. I would've liked a v2, with a Realtek USB WiFi chip. What chip does the v1.2 have? An sdio based chip, the RDA RDA5990P, as mentioned here: http://linux-sunxi.org/Ippo_q8h#Q8H-V1.2 It does have an empty spot on the pcb for a usb wifi module, I plan to hookup a usb connector to that one of these days, and see if I can get a USB host working this way. ChenYu, this also has a mmc fix which you may find interesting, it may explain some of the problems with mmc you've been having on both the A80 board, as well as the A31 dev board you've. Yes. With that fix my Hummingbird A31 boots properly without raising DCDC1 to 3.3V. Thanks! I'll send the defconfig out later. Good, so I guess this means that DCDC1 should be 3V for your board, since that is what the factory firmware uses, right ? I guess it is time to make DCDC1 voltage configurable. 3V seems to be the lowest tolerable voltage for some bits. Making it 3.3V might be a bit better. But with my light usage, I don't see any stability issues. Right, I guess 3V is used to safe battery, which makes sense (in tablets / phones) As said I'll make this configurable making 3V the default and set 3V3 in the defconfig where the original firmware does that. Regards, Hans ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] A23 u-boot with SPL / dram init available in my personal git repo
On Tue, Dec 9, 2014 at 6:25 PM, Hans de Goede hdego...@redhat.com wrote: On 09-12-14 11:17, Chen-Yu Tsai wrote: On Tue, Dec 9, 2014 at 2:53 AM, Hans de Goede hdego...@redhat.com wrote: On 08-12-14 15:28, Chen-Yu Tsai wrote: On Mon, Dec 8, 2014 at 4:27 AM, Hans de Goede hdego...@redhat.com wrote: Hi, This is still a bit rough around the edges, I'll clean it up as time permits and then post it upstream. In the mean time people interested can find $subject here: https://github.com/jwrdegoede/u-boot-sunxi/commits/sunxi-wip Hopefully I'll get around to testing this. BTW, what tablet do you have? I've an Ippo q8h v1.2, there are at least 2 differences from the v5 you've. The dram clk speed and zq value are different, and the wifi is different. The wifi does not matter for u-boot, but does mean we need separate dtb files for the 2. My u-boot sunxi-wip branch has a defconfig for the v1.2, you should be able to copy that over to the v5 defconfig, adjust dram clk and zq values with the ones from the v5 fix, change v1.2 to v5 in the CONFIG_FDTFILE setting and thats it. Let me know if this works, then I'll also include an update for the v5 defconfig to enable the SPL when I send this upstream. Just gave it a spin, and it works. The dram clock and zq can be found in sunxi-boards. Good, I'll update my patch-set to reflect this. Note that the actual settings fetched from stock u-boot has the highest bit of tpr13 set, disabling auto detection AFAICU. As you've not implemented that part, I used auto detection and it seems to work. It is implemented in the actual dram_init code, but for now I've all the dram_paras hardcoded except the clk and the zq value. If autodetect works I see no reason to change this, but for future models, if necessary the code for dealing with manual config is there, to test just put the values directly in the dram_para struct at the top of dram_sun8i.c . The only problem I have now is it has no connectivity to the outside world lol. I would've liked a v2, with a Realtek USB WiFi chip. What chip does the v1.2 have? An sdio based chip, the RDA RDA5990P, as mentioned here: http://linux-sunxi.org/Ippo_q8h#Q8H-V1.2 Not sure this would require a different DT. Probably the GPIOs are different. It does have an empty spot on the pcb for a usb wifi module, I plan to hookup a usb connector to that one of these days, and see if I can get a USB host working this way. I should do that too. Nice way to hook up ethernet. Small problem would be getting 5V from the board for VBUS. Also I have a schematic file for A23 that someone provided me. I don't remember who... It lists: - ALDO2 connected to VCC-DLL @ 2.5V - ALDO3 to VCC-PLL and AVCC (analog power) @ 3.0V - DCDC1 to all the normal stuff @ 3V - DCDC2 to VDD-SYS @ 1.1V - DCDC3 to VDD-CPU (main cpu) @ 1.1V (1.26V in my fex file) - DCDC5 to VCC-DRAM @ 1.1V (1.5V in my fex file) - DC5LDO to VDD-CPUS (special cpu) ChenYu, this also has a mmc fix which you may find interesting, it may explain some of the problems with mmc you've been having on both the A80 board, as well as the A31 dev board you've. Yes. With that fix my Hummingbird A31 boots properly without raising DCDC1 to 3.3V. Thanks! I'll send the defconfig out later. Good, so I guess this means that DCDC1 should be 3V for your board, since that is what the factory firmware uses, right ? I guess it is time to make DCDC1 voltage configurable. 3V seems to be the lowest tolerable voltage for some bits. Making it 3.3V might be a bit better. But with my light usage, I don't see any stability issues. Right, I guess 3V is used to safe battery, which makes sense (in tablets / phones) As said I'll make this configurable making 3V the default and set 3V3 in the defconfig where the original firmware does that. Thanks! ChenYu ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v9 2/2] Odroid-XU3: Add documentation for Odroid-XU3
Hi, On 8 December 2014 at 18:27, Kevin Hilman khil...@kernel.org wrote: Hi Simon, Simon Glass s...@chromium.org writes: On 8 December 2014 at 10:58, Kevin Hilman khil...@kernel.org wrote: [...] FWIW, the XU3 firmware is broken in other ways as well which have a major impact on power management. First, with mainline kernels using MCPM, only 6 of 8 CPUs come online. However, even with that fixed[1], it turns out that the kernel can't properly manage CCI due to secure firmware[2], which means that MCPM (multi-cluster power management) can't work, and thus the low-power cluster-idle states can't work, the big.LITTLE switcher cannot work, and the ongoing work on energy-aware scheduling will not be useful on this platform. Anyone know what are the chances of getting a non-secure version of the firmware for this platform. The Samsung Chromebook2 with basically the same SoC (5800 compared to the 5422 on the XU3) ships with non-secure firmware so all of the above mentioned features are working just fine. I have pushed on this but apparently it is not possible - they need to sign every BL2. The only implementation I've seen sets up the chip in BL2 (U-Boot SPL) so I don't think we can work around it. Not quite sure I'm following... So is secure-mode enabled before BL2 is started? Or do you mean BL2 is where secure-mode is enabled? If it's done in BL2, and if the hardkernel folks are willing to sign BL2 images (which I gathered from discussions elsewhere in this series) then it seems possible to turn off secure-mode. Yes it is possible - and easy - to do in BL2 / U-Boot SPL. This is what the Chromebooks do. So I went to look in the u-boot-samsung repo and didn't see the code for the SPL there. Is the BL2 source (which I understood to be u-boot SPL) in some other repo? It's in mainline U-Boot so no particular need to go to the Samsung tree. See arch/arm/cpu/armv7/exynos/spl_boot.c and tzpc.c for the TrustZone stuff. It takes us back to the 1960s where we sent off our code at night to run it :-) I think the best bet is the current effort to mainline the rest of the Chromebook code then try to build it for XU3. What's the status of that effort? Coming along but the big/little support is still not there. The display works and most core peripherals. Needs more SPL work. I'm working on getting these same features working on the XU3, but this broken firmware as brought a halt to any real progress. Agreed, but I think this is feasible once U-Boot on XU3 is sorted out. Let's hope so. Kevin Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 2/2] Kconfig: Move CONFIG_SYS_MALLOC_F_LEN to Kconfig
Move this option to Kconfig and update all boards. Signed-off-by: Simon Glass s...@chromium.org --- Kconfig | 9 + arch/arm/cpu/armv7/tegra-common/Kconfig | 3 +++ arch/arm/cpu/armv7/uniphier/Kconfig | 3 +++ arch/x86/Kconfig| 3 +++ include/configs/cm_fx6.h| 3 --- include/configs/exynos-common.h | 1 - include/configs/mx6sabre_common.h | 1 - include/configs/rpi.h | 1 - include/configs/s5p_goni.h | 1 - include/configs/sandbox.h | 1 - include/configs/smdkc100.h | 3 --- include/configs/snapper9260.h | 1 - include/configs/sunxi-common.h | 1 - include/configs/tegra-common.h | 1 - include/configs/ti_am335x_common.h | 1 - include/configs/ti_omap3_common.h | 1 - include/configs/uniphier-common.h | 2 -- include/configs/x86-common.h| 1 - 18 files changed, 18 insertions(+), 19 deletions(-) diff --git a/Kconfig b/Kconfig index d4ca152..9208d40 100644 --- a/Kconfig +++ b/Kconfig @@ -56,6 +56,15 @@ config CC_OPTIMIZE_FOR_SIZE This option is enabled by default for U-Boot. +config SYS_MALLOC_F_LEN + hex Size of malloc() pool before relocation + default 0x400 + help + Before relocation memory is very limited on many platforms. Still, + we can provide a small malloc() pool if needed. Driver model in + particular needs this to operate, so that it can allocate the + initial serial device and any others that are needed. + endmenu# General setup menuconfig EXPERT diff --git a/arch/arm/cpu/armv7/tegra-common/Kconfig b/arch/arm/cpu/armv7/tegra-common/Kconfig index 898e86d..9c98d19 100644 --- a/arch/arm/cpu/armv7/tegra-common/Kconfig +++ b/arch/arm/cpu/armv7/tegra-common/Kconfig @@ -17,6 +17,9 @@ config TEGRA124 endchoice +config SYS_MALLOC_F_LEN + default 0x1800 + config USE_PRIVATE_LIBGCC default y if SPL_BUILD diff --git a/arch/arm/cpu/armv7/uniphier/Kconfig b/arch/arm/cpu/armv7/uniphier/Kconfig index 36b7f11..d68a262 100644 --- a/arch/arm/cpu/armv7/uniphier/Kconfig +++ b/arch/arm/cpu/armv7/uniphier/Kconfig @@ -23,6 +23,9 @@ config MACH_PH1_SLD8 endchoice +config SYS_MALLOC_F_LEN + default 0x2000 + config CMD_PINMON bool Enable boot mode pins monitor command depends on !SPL_BUILD diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index b523f25..969634f 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -43,6 +43,9 @@ config DM_GPIO config DM_SERIAL default y +config SYS_MALLOC_F_LEN + default 0x800 + config RAMBASE hex default 0x10 diff --git a/include/configs/cm_fx6.h b/include/configs/cm_fx6.h index 0a4d93f..94ef7ab 100644 --- a/include/configs/cm_fx6.h +++ b/include/configs/cm_fx6.h @@ -21,10 +21,7 @@ #define CONFIG_MACH_TYPE 4273 #ifndef CONFIG_SPL_BUILD - #define CONFIG_CMD_GPIO - -#define CONFIG_SYS_MALLOC_F_LEN(1 10) #endif /* Display information on boot */ diff --git a/include/configs/exynos-common.h b/include/configs/exynos-common.h index 2c4f35a..59676ae 100644 --- a/include/configs/exynos-common.h +++ b/include/configs/exynos-common.h @@ -36,7 +36,6 @@ #define CONFIG_ENV_OVERWRITE /* Size of malloc() pool before and after relocation */ -#define CONFIG_SYS_MALLOC_F_LEN(1 10) #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (80 20)) /* select serial console configuration */ diff --git a/include/configs/mx6sabre_common.h b/include/configs/mx6sabre_common.h index 379a25d..d174f97 100644 --- a/include/configs/mx6sabre_common.h +++ b/include/configs/mx6sabre_common.h @@ -25,7 +25,6 @@ #define CONFIG_INITRD_TAG #define CONFIG_REVISION_TAG -#define CONFIG_SYS_MALLOC_F_LEN(1 10) #define CONFIG_IMX6_THERMAL #define CONFIG_SYS_GENERIC_BOARD diff --git a/include/configs/rpi.h b/include/configs/rpi.h index ea19ad8..7ad8d08 100644 --- a/include/configs/rpi.h +++ b/include/configs/rpi.h @@ -46,7 +46,6 @@ CONFIG_SYS_SDRAM_SIZE - \ GENERATED_GBL_DATA_SIZE) #define CONFIG_SYS_MALLOC_LEN SZ_4M -#define CONFIG_SYS_MALLOC_F_LEN(1 10) #define CONFIG_SYS_MEMTEST_START 0x0010 #define CONFIG_SYS_MEMTEST_END 0x0020 #define CONFIG_LOADADDR0x0020 diff --git a/include/configs/s5p_goni.h b/include/configs/s5p_goni.h index 26167a4..8fadc68 100644 --- a/include/configs/s5p_goni.h +++ b/include/configs/s5p_goni.h @@ -40,7 +40,6 @@ #define CONFIG_CMDLINE_EDITING /* Size of malloc() pool before and after relocation */ -#define CONFIG_SYS_MALLOC_F_LEN(1 10) #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (80 20)) /* diff --git a/include/configs/sandbox.h
[U-Boot] [PATCH 1/2] RFC: dm: Kconfig: Move all driver model CONFIGs to Kconfig
Kconfig has been available for a while but there are still driver model CONFIG options. Move all of these to Kconfig. This patch isn't final - I need to wait until the SPL series can be fully applied, which is in turn waiting on some ARM SPL problems. So for now it is just a placeholder. But it needs to be sent out otherwise we will never move over. Signed-off-by: Simon Glass s...@chromium.org --- Kconfig | 2 + arch/arm/Kconfig | 2 + arch/arm/cpu/arm1176/bcm2835/Kconfig | 12 +++ arch/arm/cpu/armv7/exynos/Kconfig | 15 arch/arm/cpu/armv7/tegra-common/Kconfig | 21 + arch/sandbox/Kconfig | 39 ++ arch/x86/Kconfig | 9 +++ board/isee/igep0033/Kconfig | 9 +++ board/isee/igep00x0/Kconfig | 9 +++ board/logicpd/am3517evm/Kconfig | 9 +++ board/logicpd/omap3som/Kconfig| 9 +++ board/logicpd/zoom1/Kconfig | 9 +++ board/overo/Kconfig | 9 +++ board/samsung/goni/Kconfig| 9 +++ board/samsung/smdk5420/Kconfig| 6 ++ board/samsung/smdkc100/Kconfig| 9 +++ board/ti/am335x/Kconfig | 10 +++ common/Kconfig| 23 ++ configs/Linksprite_pcDuino3_fdt_defconfig | 2 + configs/cm_fx6_defconfig | 3 + configs/mx6qsabreauto_defconfig | 2 + configs/mx6sabresd_spl_defconfig | 3 +- configs/omap3_beagle_defconfig| 3 + configs/omap3_pandora_defconfig | 3 + configs/snapper9260_defconfig | 3 + configs/snapper9g20_defconfig | 3 + doc/driver-model/spi-howto.txt| 4 +- drivers/Kconfig | 4 + drivers/core/Kconfig | 122 +- drivers/demo/Kconfig | 26 +++ drivers/thermal/Kconfig | 7 ++ include/config_defaults.h | 6 -- include/configs/cm_fx6.h | 4 - include/configs/exynos-common.h | 6 -- include/configs/mx6sabre_common.h | 2 - include/configs/peach-pi.h| 1 - include/configs/peach-pit.h | 1 - include/configs/rpi.h | 6 -- include/configs/s5p_goni.h| 4 - include/configs/sandbox.h | 13 include/configs/smdkc100.h| 4 - include/configs/snapper9260.h | 4 - include/configs/sunxi-common.h| 3 - include/configs/tegra-common.h| 9 --- include/configs/ti_am335x_common.h| 4 - include/configs/ti_omap3_common.h | 4 - include/configs/x86-common.h | 5 -- test/dm/Kconfig | 8 ++ 48 files changed, 399 insertions(+), 81 deletions(-) create mode 100644 arch/arm/cpu/arm1176/bcm2835/Kconfig create mode 100644 drivers/demo/Kconfig create mode 100644 drivers/thermal/Kconfig create mode 100644 test/dm/Kconfig diff --git a/Kconfig b/Kconfig index 153ee2b..d4ca152 100644 --- a/Kconfig +++ b/Kconfig @@ -158,3 +158,5 @@ source drivers/Kconfig source fs/Kconfig source lib/Kconfig + +source test/dm/Kconfig diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 7a64b66..d46362c 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -799,6 +799,8 @@ endchoice source arch/arm/cpu/arm926ejs/davinci/Kconfig +source arch/arm/cpu/arm1176/bcm2835/Kconfig + source arch/arm/cpu/armv7/exynos/Kconfig source arch/arm/cpu/armv7/highbank/Kconfig diff --git a/arch/arm/cpu/arm1176/bcm2835/Kconfig b/arch/arm/cpu/arm1176/bcm2835/Kconfig new file mode 100644 index 000..cb88664 --- /dev/null +++ b/arch/arm/cpu/arm1176/bcm2835/Kconfig @@ -0,0 +1,12 @@ +if TARGET_RPI_B + +config DM + default y + +config DM_SERIAL + default y + +config DM_GPIO + default y + +endif diff --git a/arch/arm/cpu/armv7/exynos/Kconfig b/arch/arm/cpu/armv7/exynos/Kconfig index f3eadb4..a5748ad 100644 --- a/arch/arm/cpu/armv7/exynos/Kconfig +++ b/arch/arm/cpu/armv7/exynos/Kconfig @@ -61,6 +61,21 @@ endchoice config SYS_SOC default exynos +config DM + default y + +config DM_SERIAL + default y + +config DM_SPI + default y + +config DM_SPI_FLASH + default y + +config DM_GPIO + default y + source board/samsung/smdkv310/Kconfig source board/samsung/trats/Kconfig source board/samsung/universal_c210/Kconfig diff --git a/arch/arm/cpu/armv7/tegra-common/Kconfig b/arch/arm/cpu/armv7/tegra-common/Kconfig index 1446452..898e86d 100644 --- a/arch/arm/cpu/armv7/tegra-common/Kconfig +++ b/arch/arm/cpu/armv7/tegra-common/Kconfig @@ -20,6 +20,27 @@ endchoice config USE_PRIVATE_LIBGCC default y if SPL_BUILD +config DM + default y + +config SPL_DM + default y +
Re: [U-Boot] [PATCH 4/5] exynos5420: Add LCD and LED powerup settings for peach-pi
Hi Ajay,
On 7 December 2014 at 23:45, Ajay kumar ajayn...@gmail.com wrote:
Hi,
On Fri, Dec 5, 2014 at 10:12 PM, Simon Glass s...@google.com wrote:
Hi,
On 5 December 2014 at 08:42, Sjoerd Simons
sjoerd.sim...@collabora.co.uk wrote:
On Fri, 2014-12-05 at 19:43 +0530, Ajay Kumar wrote:
Add code to support powerup sequence for peach-pi LCD.
Signed-off-by: Ajay Kumar ajaykumar...@samsung.com
---
board/samsung/smdk5420/smdk5420.c | 32 +---
1 file changed, 21 insertions(+), 11 deletions(-)
diff --git a/board/samsung/smdk5420/smdk5420.c
b/board/samsung/smdk5420/smdk5420.c
index a691222..915125e 100644
--- a/board/samsung/smdk5420/smdk5420.c
+++ b/board/samsung/smdk5420/smdk5420.c
@@ -73,19 +73,24 @@ void exynos_lcd_power_on(void)
mdelay(5);
- /* TODO(ajaykumar...@samsung.com): Use device tree */
- gpio_request(EXYNOS5420_GPIO_X35, edp_slp#);
- gpio_direction_output(EXYNOS5420_GPIO_X35, 1); /* EDP_SLP# */
- mdelay(10);
- gpio_request(EXYNOS5420_GPIO_Y77, edp_rst#);
- gpio_direction_output(EXYNOS5420_GPIO_Y77, 1); /* EDP_RST# */
- gpio_request(EXYNOS5420_GPIO_X26, edp_hpd);
- gpio_direction_input(EXYNOS5420_GPIO_X26); /* EDP_HPD */
- gpio_set_pull(EXYNOS5420_GPIO_X26, S5P_GPIO_PULL_NONE);
-
- if (has_edp_bridge())
+ if (has_edp_bridge()) {
+ /* TODO(ajaykumar...@samsung.com): Use device tree */
+ gpio_request(EXYNOS5420_GPIO_X35, edp_slp#);
+ gpio_direction_output(EXYNOS5420_GPIO_X35, 1); /* EDP_SLP#
*/
+ mdelay(10);
+ gpio_request(EXYNOS5420_GPIO_Y77, edp_rst#);
+ gpio_direction_output(EXYNOS5420_GPIO_Y77, 1); /* EDP_RST#
*/
+ gpio_request(EXYNOS5420_GPIO_X26, edp_hpd);
+ gpio_direction_input(EXYNOS5420_GPIO_X26); /* EDP_HPD */
+ gpio_set_pull(EXYNOS5420_GPIO_X26, S5P_GPIO_PULL_NONE);
+
if (parade_init(gd-fdt_blob))
printf(%s: ps8625_init() failed\n, __func__);
+ } else {
+ gpio_request(EXYNOS5420_GPIO_X26, edp_hpd);
+ gpio_direction_input(EXYNOS5420_GPIO_X26); /* EDP_HPD */
+ gpio_set_pull(EXYNOS5420_GPIO_X26, S5P_GPIO_PULL_NONE);
+ }
Any chance you could switch to using device-tree while changing this
area. On SMDK5420 and XU3 EXYNOS5420_GPIO_X26 is used for USB so there
is a bit of a potentially nastly clash there.
Yes we should really do that.
I am trying to consolidate what all needs to be done for Exynos5250
and Exynos5420,
in order to remove LCD routines from the board files.
Here are my observations:
1) A separate driver for ptn3460 should be created.
2) Need a place holder for tps65090 FET settings.
3) I am planning to move all the LCD_EN/BACKLIGHT_EN GPIOs
to the weak function definitions in exynos_fb.c.
In that case, we have a limitation. All boards under a specific
SOC should conform
to use only device tree or use only define board level LCD routines.
ex: smdk5250 and snow - both need to use device tree to specify LCD
details,
or both need to define LCD powerup routines. It cannot be
like snow uses device tree,
and smdk5250 defines LCD routines in smdk5250 board file.
Do any boards exist which don't use device tree? I think we can drop
that old support.
For a recent Tegra series I used the kernel device tree binding and
just picked out information about the regulators. It might be possible
to do the same on Exynos. See for example get_backlight_info() in this
patch: http://patchwork.ozlabs.org/patch/416675/
Regards,
Simon
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Re: [U-Boot] [PATCH 4/5] exynos5420: Add LCD and LED powerup settings for peach-pi
Hi Ajay,
(resending sorry)
On 7 December 2014 at 23:45, Ajay kumar ajayn...@gmail.com wrote:
Hi,
On Fri, Dec 5, 2014 at 10:12 PM, Simon Glass s...@google.com wrote:
Hi,
On 5 December 2014 at 08:42, Sjoerd Simons
sjoerd.sim...@collabora.co.uk wrote:
On Fri, 2014-12-05 at 19:43 +0530, Ajay Kumar wrote:
Add code to support powerup sequence for peach-pi LCD.
Signed-off-by: Ajay Kumar ajaykumar...@samsung.com
---
board/samsung/smdk5420/smdk5420.c | 32 +---
1 file changed, 21 insertions(+), 11 deletions(-)
diff --git a/board/samsung/smdk5420/smdk5420.c
b/board/samsung/smdk5420/smdk5420.c
index a691222..915125e 100644
--- a/board/samsung/smdk5420/smdk5420.c
+++ b/board/samsung/smdk5420/smdk5420.c
@@ -73,19 +73,24 @@ void exynos_lcd_power_on(void)
mdelay(5);
- /* TODO(ajaykumar...@samsung.com): Use device tree */
- gpio_request(EXYNOS5420_GPIO_X35, edp_slp#);
- gpio_direction_output(EXYNOS5420_GPIO_X35, 1); /* EDP_SLP# */
- mdelay(10);
- gpio_request(EXYNOS5420_GPIO_Y77, edp_rst#);
- gpio_direction_output(EXYNOS5420_GPIO_Y77, 1); /* EDP_RST# */
- gpio_request(EXYNOS5420_GPIO_X26, edp_hpd);
- gpio_direction_input(EXYNOS5420_GPIO_X26); /* EDP_HPD */
- gpio_set_pull(EXYNOS5420_GPIO_X26, S5P_GPIO_PULL_NONE);
-
- if (has_edp_bridge())
+ if (has_edp_bridge()) {
+ /* TODO(ajaykumar...@samsung.com): Use device tree */
+ gpio_request(EXYNOS5420_GPIO_X35, edp_slp#);
+ gpio_direction_output(EXYNOS5420_GPIO_X35, 1); /* EDP_SLP#
*/
+ mdelay(10);
+ gpio_request(EXYNOS5420_GPIO_Y77, edp_rst#);
+ gpio_direction_output(EXYNOS5420_GPIO_Y77, 1); /* EDP_RST#
*/
+ gpio_request(EXYNOS5420_GPIO_X26, edp_hpd);
+ gpio_direction_input(EXYNOS5420_GPIO_X26); /* EDP_HPD */
+ gpio_set_pull(EXYNOS5420_GPIO_X26, S5P_GPIO_PULL_NONE);
+
if (parade_init(gd-fdt_blob))
printf(%s: ps8625_init() failed\n, __func__);
+ } else {
+ gpio_request(EXYNOS5420_GPIO_X26, edp_hpd);
+ gpio_direction_input(EXYNOS5420_GPIO_X26); /* EDP_HPD */
+ gpio_set_pull(EXYNOS5420_GPIO_X26, S5P_GPIO_PULL_NONE);
+ }
Any chance you could switch to using device-tree while changing this
area. On SMDK5420 and XU3 EXYNOS5420_GPIO_X26 is used for USB so there
is a bit of a potentially nastly clash there.
Yes we should really do that.
I am trying to consolidate what all needs to be done for Exynos5250
and Exynos5420,
in order to remove LCD routines from the board files.
Here are my observations:
1) A separate driver for ptn3460 should be created.
2) Need a place holder for tps65090 FET settings.
3) I am planning to move all the LCD_EN/BACKLIGHT_EN GPIOs
to the weak function definitions in exynos_fb.c.
In that case, we have a limitation. All boards under a specific
SOC should conform
to use only device tree or use only define board level LCD routines.
ex: smdk5250 and snow - both need to use device tree to specify LCD
details,
or both need to define LCD powerup routines. It cannot be
like snow uses device tree,
and smdk5250 defines LCD routines in smdk5250 board file.
Do any boards exist which don't use device tree? I think we can drop
that old support.
For a recent Tegra series I used the kernel device tree binding and
just picked out information about the regulators. It might be possible
to do the same on Exynos. See for example get_backlight_info() in this
patch: http://patchwork.ozlabs.org/patch/416675/
Regards,
Simon
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Re: [U-Boot] [PATCH v5 01/11] dm: i2c: Add a uclass for I2C
Hi Heiko, On 8 December 2014 at 23:17, Heiko Schocher h...@denx.de wrote: Hello Simon, Am 09.12.2014 06:31, schrieb Simon Glass: Hi, On Dec 5, 2014 8:32 AM, Simon Glass s...@chromium.org wrote: The uclass implements the same operations as the current I2C framework but makes some changes to make it fit driver model better: - Remove the chip address from API calls - Remove the address length from API calls - Remove concept of 'current' I2C bus - Drop all existing init functions Acked-by: Heiko Schocher h...@denx.de Signed-off-by: Simon Glass s...@chromium.org --- Changes in v5: - Add a function comment for i2c_probe_chip() - Add an assert for offset_len in i2c_setup_offset() - Add more detail to return value comment on get_buf_speed() - Add more detail to return value comment on xfer() method - Fix -INVAL typo - Make i2c_get_bus_speed() independent of i2c_set_bus_speed() - Split DM_I2C_CHIP_RD_ADDRESS into read and write varaints - Update comments in struct i2c_msg to allow buf to be NULL - Use a NULL buffer in i2c_probe_chip() Any. Ore comments please? Otherwise I will retest and apply this version. I am fine with it. Thanks for your and Masahiros work! I hope I find some time to look into using platform data, as I have no board which uses DT support in U-Boot ... What platform do you use? Stefan gave me a Glacier board and I have that running with DT and driver model. Will send some patches before long. Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH V3 09/12] lcd: introduce getters for bg/fg color
On 8 December 2014 at 08:14, Nikita Kiryanov nik...@compulab.co.il wrote: Introduce lcd_getbgcolor() and lcd_getfgcolor(), and use them where applicable. This is a preparatory step for extracting lcd console code into its own file. Signed-off-by: Nikita Kiryanov nik...@compulab.co.il Cc: Anatolij Gustschin ag...@denx.de Cc: Simon Glass s...@chromium.org Acked-by: Simon Glass s...@chromium.org --- Changes in V3: - Instead of invoking lcd_get(bg|fg)color() each time, do it only once and cache the value. This is done in console_scrollup(), lcd_drawchars(), and drv_lcd_init(). Changes in V2: - New patch. common/lcd.c | 31 ++- include/lcd.h | 14 ++ 2 files changed, 36 insertions(+), 9 deletions(-) ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Hi Simon, Problems about RSA public exponents for verified boot
(sorry, forgot to cc list) On 9 December 2014 at 07:17, Simon Glass s...@chromium.org wrote: Hi, On 8 December 2014 at 01:54, Duxiaoqiang duxiaoqi...@huawei.com wrote: Hi Michael, Thanks for your information. My working result show that public exponent is not the only problem caused by 64bit alignment, there are also some other problems caused by it, for example: load image after verify step. If you post your console output then perhaps we might be able to suggest a fix. May be we should add a patch to cover all 64 bit platform's alignment. For we need verified boot feature to solve some problems, I also spent some time trying to solve the problem. But I am not very familiar with uboot FDT'S design, it may spend me long time so not very convenient for me to solve this problem. So I want to know do you have time to fix this problem recently, and what's your plan. I haven't tried this on 64-bit ARM. I may be able to do so later in the month. Thanks very much. Sincerely Jason Hi All, Apologies for the delayed response, I’ve been on vacation. Since this was working for you (Duxiaoqiang) previously it suggests that you are using the default public exponent. If this is still the case you could, as a temporary workaround, remove the public exponent from your public key data to avoid executing the code causing the abort. Simon: Yes, we’ll need an alignment-safe version of fdt64_to_cpu. Michael On 02 Dec 2014, at 12:31 AM, Simon Glass s...@chromium.org wrote: +Michael, U-Boot mailing list Hi, On 30 November 2014 at 19:26, Duxiaoqiang duxiaoqi...@huawei.com wrote: Hi Simon When I test verified boot with new version of U-boot and new version of mkimage, I encountered a alignment problem about RSA public key exponents. I tested verified boot successful few months ago with version of 2014.07-rc4, but failed with the same configuration and operations this time. Problem logs as below: I debug this problem and noticed that the problem was caused by pulic_exponent’s address: 0xff78a04c, this address was not aligned to 8 byte, but this address was pointed by a uint64 * type of pointer. Panic happened in function rsa_verify_with_keynode, just as below: By compared the u-boot.dtb file that signed with RSA public key, I noticed that there are differences about PUBLIC_EXPONENT. With the older version of mkimage, there’s no public exponent section. And this problem only happens when I use the new version of mkimage tool. I also checked uboot’s code, it seems that there’s lack of mechanism to guarantee the alignment about public exponent section. Can you give some suggestions about this problem. Appreciate your time. Copying Michael. Perhaps we need a safer version of fdt64_to_cpu()? But you might be the first to run this on aarch64. I have not tried it yet, but I do now have a platform. REgards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 16/25] x86: Integrate Tunnel Creek processor microcode
Hi Simon, On Fri, Dec 5, 2014 at 11:12 PM, Simon Glass s...@chromium.org wrote: Hi Bin, On 5 December 2014 at 02:14, Bin Meng bmeng...@gmail.com wrote: Hi Simon, On Fri, Dec 5, 2014 at 7:43 AM, Simon Glass s...@chromium.org wrote: Hi Bin, On 4 December 2014 at 08:02, Bin Meng bmeng...@gmail.com wrote: Integrate the processor microcode version 1.05 for Tunnel Creek, CPUID device 20661h. Signed-off-by: Bin Meng bmeng...@gmail.com --- arch/x86/cpu/queensbay/M0220661105.inc | 1288 1 file changed, 1288 insertions(+) create mode 100644 arch/x86/cpu/queensbay/M0220661105.inc Can we put this into the device tree? Unfortunately the microcode is required by the call to TempRamInit in FSP in car_init, where the device tree functionality is not available. We can of course duplicate one in device tree for reference, not sure if it is necessary. OK I was hoping you weren't going to say that. There is not even a stack at this stage so device tree is out of the question. I wonder how common this is. Is there any way to provide a 'NULL' microcode update and then do it later? I tested this, by providing a 'NULL' microcode to FSP. However the FSP TempRamInit() will just fail. So we may have to do it this way. This is some of the pain of dealing with binary blobs. Let's see where this lands but we may want to change things around in start.S to provide for this more nicely. Regards, Simon Regards, Bin ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 01/27] x86: Make ROM_SIZE configurable in Kconfig
Currently the ROM_SIZE is hardcoded to 8MB in arch/x86/Kconfig. This will not be the case when adding additional board support. Hence we make ROM_SIZE configurable (512KB/1MB/2MB/4MB/8MB/16MB) and have the board Kconfig file select the default ROM_SIZE. Signed-off-by: Bin Meng bmeng...@gmail.com Acked-by: Simon Glass s...@chromium.org --- Changes in v2: None arch/x86/Kconfig | 78 +++- board/google/chromebook_link/Kconfig | 1 + 2 files changed, 78 insertions(+), 1 deletion(-) diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 4f5ce38..fdfb618 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -61,9 +61,85 @@ config SMM_TSEG config SMM_TSEG_SIZE hex +config BOARD_ROMSIZE_KB_512 + bool +config BOARD_ROMSIZE_KB_1024 + bool +config BOARD_ROMSIZE_KB_2048 + bool +config BOARD_ROMSIZE_KB_4096 + bool +config BOARD_ROMSIZE_KB_8192 + bool +config BOARD_ROMSIZE_KB_16384 + bool + +choice + prompt ROM chip size + default UBOOT_ROMSIZE_KB_512 if BOARD_ROMSIZE_KB_512 + default UBOOT_ROMSIZE_KB_1024 if BOARD_ROMSIZE_KB_1024 + default UBOOT_ROMSIZE_KB_2048 if BOARD_ROMSIZE_KB_2048 + default UBOOT_ROMSIZE_KB_4096 if BOARD_ROMSIZE_KB_4096 + default UBOOT_ROMSIZE_KB_8192 if BOARD_ROMSIZE_KB_8192 + default UBOOT_ROMSIZE_KB_16384 if BOARD_ROMSIZE_KB_16384 + help + Select the size of the ROM chip you intend to flash U-Boot on. + + The build system will take care of creating a u-boot.rom file + of the matching size. + +config UBOOT_ROMSIZE_KB_512 + bool 512 KB + help + Choose this option if you have a 512 KB ROM chip. + +config UBOOT_ROMSIZE_KB_1024 + bool 1024 KB (1 MB) + help + Choose this option if you have a 1024 KB (1 MB) ROM chip. + +config UBOOT_ROMSIZE_KB_2048 + bool 2048 KB (2 MB) + help + Choose this option if you have a 2048 KB (2 MB) ROM chip. + +config UBOOT_ROMSIZE_KB_4096 + bool 4096 KB (4 MB) + help + Choose this option if you have a 4096 KB (4 MB) ROM chip. + +config UBOOT_ROMSIZE_KB_8192 + bool 8192 KB (8 MB) + help + Choose this option if you have a 8192 KB (8 MB) ROM chip. + +config UBOOT_ROMSIZE_KB_16384 + bool 16384 KB (16 MB) + help + Choose this option if you have a 16384 KB (16 MB) ROM chip. + +endchoice + +# Map the config names to an integer (KB). +config UBOOT_ROMSIZE_KB + int + default 512 if UBOOT_ROMSIZE_KB_512 + default 1024 if UBOOT_ROMSIZE_KB_1024 + default 2048 if UBOOT_ROMSIZE_KB_2048 + default 4096 if UBOOT_ROMSIZE_KB_4096 + default 8192 if UBOOT_ROMSIZE_KB_8192 + default 16384 if UBOOT_ROMSIZE_KB_16384 + +# Map the config names to a hex value (bytes). config ROM_SIZE hex - default 0x80 + default 0x8 if UBOOT_ROMSIZE_KB_512 + default 0x10 if UBOOT_ROMSIZE_KB_1024 + default 0x20 if UBOOT_ROMSIZE_KB_2048 + default 0x40 if UBOOT_ROMSIZE_KB_4096 + default 0x80 if UBOOT_ROMSIZE_KB_8192 + default 0xc0 if UBOOT_ROMSIZE_KB_12288 + default 0x100 if UBOOT_ROMSIZE_KB_16384 config HAVE_INTEL_ME bool Platform requires Intel Management Engine diff --git a/board/google/chromebook_link/Kconfig b/board/google/chromebook_link/Kconfig index 3a4f557..7f79fd2 100644 --- a/board/google/chromebook_link/Kconfig +++ b/board/google/chromebook_link/Kconfig @@ -19,6 +19,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOUTHBRIDGE_INTEL_C216 select HAVE_ACPI_RESUME select MARK_GRAPHICS_MEM_WRCOMB + select BOARD_ROMSIZE_KB_8192 config MMCONF_BASE_ADDRESS hex -- 1.8.2.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 03/27] x86: Refactor u-boot.rom build rules
Refactor u-boot.rom build rules by utilizing quiet_cmd_ and cmd_ macros. Also make writing mrc.bin and pci option rom to u-boot.rom optional and remove mrc.bin from its dependent file list as not every x86 board port needs mrc binary blob. Signed-off-by: Bin Meng bmeng...@gmail.com Acked-by: Simon Glass s...@chromium.org --- Changes in v2: None Makefile | 48 +++- 1 file changed, 27 insertions(+), 21 deletions(-) diff --git a/Makefile b/Makefile index 44d468e..c9ae77b 100644 --- a/Makefile +++ b/Makefile @@ -963,27 +963,33 @@ u-boot-nand.gph: u-boot.bin FORCE ifneq ($(CONFIG_X86_RESET_VECTOR),) rom: u-boot.rom FORCE -u-boot.rom: u-boot-x86-16bit.bin u-boot-dtb.bin \ - $(srctree)/board/$(BOARDDIR)/mrc.bin - $(objtree)/tools/ifdtool -c -r $(CONFIG_ROM_SIZE) u-boot.tmp - if [ -n $(CONFIG_HAVE_INTEL_ME) ]; then \ - $(objtree)/tools/ifdtool -D \ - $(srctree)/board/$(BOARDDIR)/descriptor.bin u-boot.tmp; \ - $(objtree)/tools/ifdtool \ - -i ME:$(srctree)/board/$(BOARDDIR)/me.bin u-boot.tmp; \ - fi - $(objtree)/tools/ifdtool -w \ - $(CONFIG_SYS_TEXT_BASE):$(objtree)/u-boot-dtb.bin u-boot.tmp - $(objtree)/tools/ifdtool -w \ - $(CONFIG_X86_MRC_START):$(srctree)/board/$(BOARDDIR)/mrc.bin \ - u-boot.tmp - $(objtree)/tools/ifdtool -w \ - $(CONFIG_SYS_X86_START16):$(objtree)/u-boot-x86-16bit.bin \ - u-boot.tmp - $(objtree)/tools/ifdtool -w \ - $(CONFIG_X86_OPTION_ROM_ADDR):$(srctree)/board/$(BOARDDIR)/$(CONFIG_X86_OPTION_ROM_FILENAME) \ - u-boot.tmp - mv u-boot.tmp $@ +IFDTOOL=$(objtree)/tools/ifdtool +IFDTOOL_FLAGS = -w $(CONFIG_SYS_TEXT_BASE):$(objtree)/u-boot-dtb.bin +IFDTOOL_FLAGS += -w $(CONFIG_SYS_X86_START16):$(objtree)/u-boot-x86-16bit.bin + +ifneq ($(CONFIG_HAVE_INTEL_ME),) +IFDTOOL_ME_FLAGS = -D $(srctree)/board/$(BOARDDIR)/descriptor.bin +IFDTOOL_ME_FLAGS += -i ME:$(srctree)/board/$(BOARDDIR)/me.bin +endif + +ifneq ($(CONFIG_HAVE_MRC),) +IFDTOOL_FLAGS += -w $(CONFIG_X86_MRC_START):$(srctree)/board/$(BOARDDIR)/mrc.bin +endif + +ifneq ($(CONFIG_X86_OPTION_ROM_ADDR),) +IFDTOOL_FLAGS += -w $(CONFIG_X86_OPTION_ROM_ADDR):$(srctree)/board/$(BOARDDIR)/$(CONFIG_X86_OPTION_ROM_FILENAME) +endif + +quiet_cmd_ifdtool = IFDTOOL $@ +cmd_ifdtool = $(IFDTOOL) -c -r $(CONFIG_ROM_SIZE) u-boot.tmp; +ifneq ($(CONFIG_HAVE_INTEL_ME),) +cmd_ifdtool += $(IFDTOOL) $(IFDTOOL_ME_FLAGS) u-boot.tmp; +endif +cmd_ifdtool += $(IFDTOOL) $(IFDTOOL_FLAGS) u-boot.tmp; +cmd_ifdtool += mv u-boot.tmp $@ + +u-boot.rom: u-boot-x86-16bit.bin u-boot-dtb.bin + $(call if_changed,ifdtool) OBJCOPYFLAGS_u-boot-x86-16bit.bin := -O binary -j .start16 -j .resetvec u-boot-x86-16bit.bin: u-boot FORCE -- 1.8.2.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 04/27] x86: Clean up asm-offsets
Move GD_BIST from lib/asm-offsets.c to arch/x86/lib/asm-offsets.c
as it is x86 arch specific stuff. Also remove GENERATED_GD_RELOC_OFF
which is not referenced anymore.
Signed-off-by: Bin Meng bmeng...@gmail.com
Acked-by: Simon Glass s...@chromium.org
---
Changes in v2: None
arch/x86/cpu/start.S | 3 ++-
arch/x86/lib/asm-offsets.c | 2 +-
lib/asm-offsets.c | 3 ---
3 files changed, 3 insertions(+), 5 deletions(-)
diff --git a/arch/x86/cpu/start.S b/arch/x86/cpu/start.S
index b0d0ac0..f9662fb 100644
--- a/arch/x86/cpu/start.S
+++ b/arch/x86/cpu/start.S
@@ -1,5 +1,5 @@
/*
- * U-boot - x86 Startup Code
+ * U-Boot - x86 Startup Code
*
* (C) Copyright 2008-2011
* Graeme Russ, graeme.r...@gmail.com
@@ -17,6 +17,7 @@
#include asm/processor.h
#include asm/processor-flags.h
#include generated/generic-asm-offsets.h
+#include generated/asm-offsets.h
.section .text
.code32
diff --git a/arch/x86/lib/asm-offsets.c b/arch/x86/lib/asm-offsets.c
index d65c6ab..50a488f 100644
--- a/arch/x86/lib/asm-offsets.c
+++ b/arch/x86/lib/asm-offsets.c
@@ -17,6 +17,6 @@
int main(void)
{
- DEFINE(GENERATED_GD_RELOC_OFF, offsetof(gd_t, reloc_off));
+ DEFINE(GD_BIST, offsetof(gd_t, arch.bist));
return 0;
}
diff --git a/lib/asm-offsets.c b/lib/asm-offsets.c
index 580f763..129bc3e 100644
--- a/lib/asm-offsets.c
+++ b/lib/asm-offsets.c
@@ -31,9 +31,6 @@ int main(void)
#ifdef CONFIG_SYS_MALLOC_F_LEN
DEFINE(GD_MALLOC_BASE, offsetof(struct global_data, malloc_base));
#endif
-#ifdef CONFIG_X86
- DEFINE(GD_BIST, offsetof(struct global_data, arch.bist));
-#endif
#if defined(CONFIG_ARM)
--
1.8.2.1
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[U-Boot] [PATCH v2 0/27] x86: Add Intel Queensbay platform support
This patch series add the Intel Queensbay platform support. The Queensbay platform includes an Atom E6xx processor (codename Tunnel Creek) and a Platform Controller Hub EG20T (codename Topcliff). The support depends on Intel Firmware Support Package (FSP) to initialize the processor and chipset including system memory. With this patch series, U-Boot boots to Linux kernel. Validated on an Intel Crown Bay board with kernel 3.17. Changes in v2: - tools/ifdtool: Change WRITE_NUM to WRITE_MAX - tools/ifdtool: Remove the unnecessary initialiser of addr and wr_fname - Move setup_pch_gpios() to board support codes instead of making it a weak function - Add a comment to describe PNP_DEV - Change pnp device inline routine parameters to use proper size - Apply U-Boot coding convention to the FSP support codes - Update the codes to use U-Boot coding style - Move FspInit call from start.S to car_init - Use ARRAY_SIZE to indicate the maximum number of HOB tyeps - Remove some unnecessary spaces in the do_hob command output - Replace 0xcf9 with macro PORT_RESET from processor.h - Move FspInit call from start.S to car_init - Add UART0_BASE and UART1_BASE to ibmpc.h - Add a comment to explain we don't need check bit0 in GPIO base address register - Add setup_pch_gpios() in crownbay.c - Fix several typos in queensbay/Kconfig - Change FSP_FILE and CMC_FILE description to indicate the file is in the board directory - Add help for FSP_TEMP_RAM_ADDR - Add more help for CMC_FILE - Update ifdtool flags to indicate FSP and CMC files are in the board directory - Use consistent XXX_FILE name for binary blob file - Move PCH_LPC_DEV to arch/x86/include/asm/arch-queensbay/tnc.h - Check return value of x86_cpu_init_f() - Use ARRAY_SIZE(mmc_supported) instead of 2 - Check return value of add_sdhci() - Remove the 'make menuconfig' in the crownbay build instructions - Indicate all the binary blobs should be put in the board directory - New patch (#21) to use consistent name XXX_ADDR for binary blobs - New patch (#26) to rename coreboot-serial to x86-serial Bin Meng (27): x86: Make ROM_SIZE configurable in Kconfig tools/ifdtool: Support writing multiple files (-w) simultaneously x86: Refactor u-boot.rom build rules x86: Clean up asm-offsets x86: ich6-gpio: Move setup_pch_gpios() to board support codes x86: Add Intel Crown Bay board dts file x86: Add a simple superio driver for SMSC LPC47M x86: Add Intel Topcliff PCH device IDs x86: ich-spi: Add Intel Tunnel Creek SPI controller support x86: Initial import from Intel FSP release for Queensbay platform x86: queensbay: Adapt FSP support codes x86: Add post failure codes for bist and car x86: Support Intel FSP initialization path in start.S x86: Add a simple command to show FSP HOB information x86: Integrate Tunnel Creek processor microcode x86: Add basic support to queensbay platform and crownbay board x86: ich6-gpio: Add Intel Tunnel Creek GPIO support x86: Enable the queensbay cpu directory build x86: Add queensbay and crownbay Kconfig files x86: Add crownbay defconfig and config.h x86: Use consistent name XXX_ADDR for binary blob flash address x86: Include FSP and CMC binary in the u-boot.rom build rules x86: crownbay: Add SPI flash support x86: crownbay: Enable Intel E1000 NIC support x86: crownbay: Add SDHCI support x86: Rename coreboot-serial to x86-serial x86: Add a README.x86 for U-Boot on x86 support Makefile | 56 +- arch/x86/Kconfig | 91 +- arch/x86/cpu/Makefile |1 + arch/x86/cpu/ivybridge/cpu.c |1 + arch/x86/cpu/ivybridge/sdram.c |2 +- arch/x86/cpu/queensbay/Kconfig | 79 ++ arch/x86/cpu/queensbay/M0220661105.inc | 1288 arch/x86/cpu/queensbay/Makefile|9 + arch/x86/cpu/queensbay/fsp_configs.c | 27 + arch/x86/cpu/queensbay/fsp_support.c | 416 +++ arch/x86/cpu/queensbay/tnc.c | 72 ++ arch/x86/cpu/queensbay/tnc_car.S | 103 ++ arch/x86/cpu/queensbay/tnc_dram.c | 78 ++ arch/x86/cpu/queensbay/tnc_pci.c | 61 + arch/x86/cpu/queensbay/topcliff.c | 47 + arch/x86/cpu/start.S | 17 +- arch/x86/dts/Makefile |3 +- arch/x86/dts/coreboot.dtsi |2 +- arch/x86/dts/crownbay.dts | 53 + arch/x86/include/asm/arch-coreboot/gpio.h |3 + arch/x86/include/asm/arch-ivybridge/gpio.h |3 + arch/x86/include/asm/arch-queensbay/fsp/fsp_api.h | 56 + .../include/asm/arch-queensbay/fsp/fsp_bootmode.h | 24 + arch/x86/include/asm/arch-queensbay/fsp/fsp_ffs.h | 166 +++
[U-Boot] [PATCH v2 07/27] x86: Add a simple superio driver for SMSC LPC47M
On most x86 boards, the legacy serial ports (io address 0x3f8/0x2f8)
are provided by a superio chip connected to the LPC bus. We must
program the superio chip so that serial ports are available for us.
Signed-off-by: Bin Meng bmeng...@gmail.com
---
Changes in v2:
- Add a comment to describe PNP_DEV
- Change pnp device inline routine parameters to use proper size
arch/x86/include/asm/pnp_def.h | 90 ++
drivers/misc/Makefile | 1 +
drivers/misc/smsc_lpc47m.c | 33
include/smsc_lpc47m.h | 19 +
4 files changed, 143 insertions(+)
create mode 100644 arch/x86/include/asm/pnp_def.h
create mode 100644 drivers/misc/smsc_lpc47m.c
create mode 100644 include/smsc_lpc47m.h
diff --git a/arch/x86/include/asm/pnp_def.h b/arch/x86/include/asm/pnp_def.h
new file mode 100644
index 000..24b038d
--- /dev/null
+++ b/arch/x86/include/asm/pnp_def.h
@@ -0,0 +1,90 @@
+/*
+ * Copyright (C) 2014, Bin Meng bmeng...@gmail.com
+ *
+ * Adapted from coreboot src/include/device/pnp_def.h
+ * and arch/x86/include/arch/io.h
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef _ASM_PNP_DEF_H_
+#define _ASM_PNP_DEF_H_
+
+#include asm/io.h
+
+#define PNP_IDX_EN 0x30
+#define PNP_IDX_IO0 0x60
+#define PNP_IDX_IO1 0x62
+#define PNP_IDX_IO2 0x64
+#define PNP_IDX_IO3 0x66
+#define PNP_IDX_IRQ0 0x70
+#define PNP_IDX_IRQ1 0x72
+#define PNP_IDX_DRQ0 0x74
+#define PNP_IDX_DRQ1 0x75
+#define PNP_IDX_MSC0 0xf0
+#define PNP_IDX_MSC1 0xf1
+
+/* Generic functions for pnp devices */
+
+/*
+ * pnp device is a 16-bit integer composed of its i/o port address at high byte
+ * and logic function number at low byte.
+ */
+#define PNP_DEV(PORT, FUNC) (((PORT) 8) | (FUNC))
+
+static inline void pnp_write_config(uint16_t dev, uint8_t reg, uint8_t value)
+{
+ uint8_t port = dev 8;
+
+ outb(reg, port);
+ outb(value, port + 1);
+}
+
+static inline uint8_t pnp_read_config(uint16_t dev, uint8_t reg)
+{
+ uint8_t port = dev 8;
+
+ outb(reg, port);
+ return inb(port + 1);
+}
+
+static inline void pnp_set_logical_device(uint16_t dev)
+{
+ uint8_t device = dev 0xff;
+
+ pnp_write_config(dev, 0x07, device);
+}
+
+static inline void pnp_set_enable(uint16_t dev, int enable)
+{
+ pnp_write_config(dev, PNP_IDX_EN, enable ? 1 : 0);
+}
+
+static inline int pnp_read_enable(uint16_t dev)
+{
+ return !!pnp_read_config(dev, PNP_IDX_EN);
+}
+
+static inline void pnp_set_iobase(uint16_t dev, uint8_t index, uint16_t iobase)
+{
+ pnp_write_config(dev, index + 0, (iobase 8) 0xff);
+ pnp_write_config(dev, index + 1, iobase 0xff);
+}
+
+static inline uint16_t pnp_read_iobase(uint16_t dev, uint8_t index)
+{
+ return ((uint16_t)(pnp_read_config(dev, index)) 8) |
+ pnp_read_config(dev, index + 1);
+}
+
+static inline void pnp_set_irq(uint16_t dev, uint8_t index, unsigned irq)
+{
+ pnp_write_config(dev, index, irq);
+}
+
+static inline void pnp_set_drq(uint16_t dev, uint8_t index, unsigned drq)
+{
+ pnp_write_config(dev, index, drq 0xff);
+}
+
+#endif /* _ASM_PNP_DEF_H_ */
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index 2f2e48f..eb57497 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -20,6 +20,7 @@ obj-$(CONFIG_MXC_OCOTP) += mxc_ocotp.o
obj-$(CONFIG_MXS_OCOTP) += mxs_ocotp.o
obj-$(CONFIG_NS87308) += ns87308.o
obj-$(CONFIG_PDSP188x) += pdsp188x.o
+obj-$(CONFIG_SMSC_LPC47M) += smsc_lpc47m.o
obj-$(CONFIG_STATUS_LED) += status_led.o
obj-$(CONFIG_TWL4030_LED) += twl4030_led.o
obj-$(CONFIG_FSL_IFC) += fsl_ifc.o
diff --git a/drivers/misc/smsc_lpc47m.c b/drivers/misc/smsc_lpc47m.c
new file mode 100644
index 000..d51f8e3
--- /dev/null
+++ b/drivers/misc/smsc_lpc47m.c
@@ -0,0 +1,33 @@
+/*
+ * Copyright (C) 2014, Bin Meng bmeng...@gmail.com
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include asm/io.h
+#include asm/pnp_def.h
+
+static void pnp_enter_conf_state(u16 dev)
+{
+ u16 port = dev 8;
+
+ outb(0x55, port);
+}
+
+static void pnp_exit_conf_state(u16 dev)
+{
+ u16 port = dev 8;
+
+ outb(0xaa, port);
+}
+
+void lpc47m_enable_serial(u16 dev, u16 iobase)
+{
+ pnp_enter_conf_state(dev);
+ pnp_set_logical_device(dev);
+ pnp_set_enable(dev, 0);
+ pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
+ pnp_set_enable(dev, 1);
+ pnp_exit_conf_state(dev);
+}
diff --git a/include/smsc_lpc47m.h b/include/smsc_lpc47m.h
new file mode 100644
index 000..bffd622
--- /dev/null
+++ b/include/smsc_lpc47m.h
@@ -0,0 +1,19 @@
+/*
+ * Copyright (C) 2014, Bin Meng bmeng...@gmail.com
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef _SMSC_LPC47M_H_
+#define _SMSC_LPC47M_H_
+
+/**
+ * Configure the base I/O port of the specified serial device and enable the
+ * serial device.
+ *
+ * @dev: High 8 bits = Super I/O port, low 8 bits = logical device number.
+ * @iobase:
[U-Boot] [PATCH v2 05/27] x86: ich6-gpio: Move setup_pch_gpios() to board support codes
Movie setup_pch_gpios() in the ich6-gpio driver to the board support
codes, so that the driver does not need to know any platform specific
stuff (ie: include the platform specifc chipset header file).
Signed-off-by: Bin Meng bmeng...@gmail.com
---
Changes in v2:
- Move setup_pch_gpios() to board support codes instead of
making it a weak function
arch/x86/include/asm/arch-coreboot/gpio.h | 3 ++
arch/x86/include/asm/arch-ivybridge/gpio.h | 3 ++
arch/x86/include/asm/gpio.h| 1 +
board/coreboot/coreboot/coreboot.c | 6
board/google/chromebook_link/link.c| 40 ++
drivers/gpio/intel_ich6_gpio.c | 53 ++
6 files changed, 55 insertions(+), 51 deletions(-)
diff --git a/arch/x86/include/asm/arch-coreboot/gpio.h
b/arch/x86/include/asm/arch-coreboot/gpio.h
index 4951a8c..31edef9 100644
--- a/arch/x86/include/asm/arch-coreboot/gpio.h
+++ b/arch/x86/include/asm/arch-coreboot/gpio.h
@@ -7,4 +7,7 @@
#ifndef _X86_ARCH_GPIO_H_
#define _X86_ARCH_GPIO_H_
+/* Where in config space is the register that points to the GPIO registers? */
+#define PCI_CFG_GPIOBASE 0x48
+
#endif /* _X86_ARCH_GPIO_H_ */
diff --git a/arch/x86/include/asm/arch-ivybridge/gpio.h
b/arch/x86/include/asm/arch-ivybridge/gpio.h
index 4951a8c..31edef9 100644
--- a/arch/x86/include/asm/arch-ivybridge/gpio.h
+++ b/arch/x86/include/asm/arch-ivybridge/gpio.h
@@ -7,4 +7,7 @@
#ifndef _X86_ARCH_GPIO_H_
#define _X86_ARCH_GPIO_H_
+/* Where in config space is the register that points to the GPIO registers? */
+#define PCI_CFG_GPIOBASE 0x48
+
#endif /* _X86_ARCH_GPIO_H_ */
diff --git a/arch/x86/include/asm/gpio.h b/arch/x86/include/asm/gpio.h
index 5540d42..1787e52 100644
--- a/arch/x86/include/asm/gpio.h
+++ b/arch/x86/include/asm/gpio.h
@@ -147,6 +147,7 @@ struct pch_gpio_map {
} set3;
};
+void setup_pch_gpios(u32 gpiobase, const struct pch_gpio_map *gpio);
void ich_gpio_set_gpio_map(const struct pch_gpio_map *map);
#endif /* _X86_GPIO_H_ */
diff --git a/board/coreboot/coreboot/coreboot.c
b/board/coreboot/coreboot/coreboot.c
index 0240c34..b260f9a 100644
--- a/board/coreboot/coreboot/coreboot.c
+++ b/board/coreboot/coreboot/coreboot.c
@@ -6,6 +6,7 @@
#include common.h
#include cros_ec.h
+#include asm/gpio.h
int arch_early_init_r(void)
{
@@ -14,3 +15,8 @@ int arch_early_init_r(void)
return 0;
}
+
+void setup_pch_gpios(u32 gpiobase, const struct pch_gpio_map *gpio)
+{
+ return;
+}
diff --git a/board/google/chromebook_link/link.c
b/board/google/chromebook_link/link.c
index 1822237..4d95c1c 100644
--- a/board/google/chromebook_link/link.c
+++ b/board/google/chromebook_link/link.c
@@ -7,6 +7,9 @@
#include common.h
#include cros_ec.h
#include asm/gpio.h
+#include asm/io.h
+#include asm/pci.h
+#include asm/arch/pch.h
int arch_early_init_r(void)
{
@@ -121,3 +124,40 @@ int board_early_init_f(void)
return 0;
}
+
+void setup_pch_gpios(u32 gpiobase, const struct pch_gpio_map *gpio)
+{
+ /* GPIO Set 1 */
+ if (gpio-set1.level)
+ outl(*((u32 *)gpio-set1.level), gpiobase + GP_LVL);
+ if (gpio-set1.mode)
+ outl(*((u32 *)gpio-set1.mode), gpiobase + GPIO_USE_SEL);
+ if (gpio-set1.direction)
+ outl(*((u32 *)gpio-set1.direction), gpiobase + GP_IO_SEL);
+ if (gpio-set1.reset)
+ outl(*((u32 *)gpio-set1.reset), gpiobase + GP_RST_SEL1);
+ if (gpio-set1.invert)
+ outl(*((u32 *)gpio-set1.invert), gpiobase + GPI_INV);
+ if (gpio-set1.blink)
+ outl(*((u32 *)gpio-set1.blink), gpiobase + GPO_BLINK);
+
+ /* GPIO Set 2 */
+ if (gpio-set2.level)
+ outl(*((u32 *)gpio-set2.level), gpiobase + GP_LVL2);
+ if (gpio-set2.mode)
+ outl(*((u32 *)gpio-set2.mode), gpiobase + GPIO_USE_SEL2);
+ if (gpio-set2.direction)
+ outl(*((u32 *)gpio-set2.direction), gpiobase + GP_IO_SEL2);
+ if (gpio-set2.reset)
+ outl(*((u32 *)gpio-set2.reset), gpiobase + GP_RST_SEL2);
+
+ /* GPIO Set 3 */
+ if (gpio-set3.level)
+ outl(*((u32 *)gpio-set3.level), gpiobase + GP_LVL3);
+ if (gpio-set3.mode)
+ outl(*((u32 *)gpio-set3.mode), gpiobase + GPIO_USE_SEL3);
+ if (gpio-set3.direction)
+ outl(*((u32 *)gpio-set3.direction), gpiobase + GP_IO_SEL3);
+ if (gpio-set3.reset)
+ outl(*((u32 *)gpio-set3.reset), gpiobase + GP_RST_SEL3);
+}
diff --git a/drivers/gpio/intel_ich6_gpio.c b/drivers/gpio/intel_ich6_gpio.c
index b095d17..1f0d9df 100644
--- a/drivers/gpio/intel_ich6_gpio.c
+++ b/drivers/gpio/intel_ich6_gpio.c
@@ -34,16 +34,9 @@
#include asm/gpio.h
#include asm/io.h
#include asm/pci.h
-#ifdef CONFIG_X86_RESET_VECTOR
-#include asm/arch/pch.h
-#define SUPPORT_GPIO_SETUP
-#endif
#define GPIO_PER_BANK 32
-/* Where in config space is the register that points to
[U-Boot] [PATCH v2 02/27] tools/ifdtool: Support writing multiple files (-w) simultaneously
Currently ifdtool only supports writing one file (-w) at a time.
This looks verbose when generating u-boot.rom for x86 targets.
This change allows at most 16 files to be written simultaneously.
Signed-off-by: Bin Meng bmeng...@gmail.com
---
Changes in v2:
- tools/ifdtool: Change WRITE_NUM to WRITE_MAX
- tools/ifdtool: Remove the unnecessary initialiser of addr and wr_fname
tools/ifdtool.c | 31 ---
tools/ifdtool.h | 2 ++
2 files changed, 26 insertions(+), 7 deletions(-)
diff --git a/tools/ifdtool.c b/tools/ifdtool.c
index a4b481f..f81e5c8 100644
--- a/tools/ifdtool.c
+++ b/tools/ifdtool.c
@@ -732,6 +732,7 @@ static void print_usage(const char *name)
-x | --extract: extract intel fd modules\n
-i | --inject region:module inject file module into
region region\n
-w | --write addr:filewrite file to appear at
memory address addr\n
+ multiple files can be
written simultaneously\n
-s | --spifreq 20|33|50 set the SPI frequency\n
-e | --em100 set SPI frequency to 20MHz
and disable\n
Dual Output Fast Read
Support\n
@@ -782,7 +783,9 @@ int main(int argc, char *argv[])
char *addr_str = NULL;
int region_type = -1, inputfreq = 0;
enum spi_frequency spifreq = SPI_FREQUENCY_20MHZ;
- unsigned int addr = 0;
+ unsigned int addr[WRITE_MAX];
+ char *wr_fname[WRITE_MAX];
+ unsigned char wr_idx, wr_num = 0;
int rom_size = -1;
bool write_it;
char *filename;
@@ -886,11 +889,19 @@ int main(int argc, char *argv[])
break;
case 'w':
mode_write = 1;
- if (get_two_words(optarg, addr_str, src_fname)) {
- print_usage(argv[0]);
- exit(EXIT_FAILURE);
+ if (wr_num WRITE_MAX) {
+ if (get_two_words(optarg, addr_str,
+ wr_fname[wr_num])) {
+ print_usage(argv[0]);
+ exit(EXIT_FAILURE);
+ }
+ addr[wr_num] = strtol(optarg, NULL, 0);
+ wr_num++;
+ } else {
+ fprintf(stderr,
+ The number of files to write
simultaneously exceeds the limitation (%d)\n,
+ WRITE_MAX);
}
- addr = strtol(optarg, NULL, 0);
break;
case 'x':
mode_extract = 1;
@@ -1002,8 +1013,14 @@ int main(int argc, char *argv[])
if (mode_inject)
ret = inject_region(image, size, region_type, src_fname);
- if (mode_write)
- ret = write_data(image, size, addr, src_fname);
+ if (mode_write) {
+ for (wr_idx = 0; wr_idx wr_num; wr_idx++) {
+ ret = write_data(image, size,
+addr[wr_idx], wr_fname[wr_idx]);
+ if (ret)
+ break;
+ }
+ }
if (mode_spifreq)
set_spi_frequency(image, size, spifreq);
diff --git a/tools/ifdtool.h b/tools/ifdtool.h
index fbec421..0d0cc36 100644
--- a/tools/ifdtool.h
+++ b/tools/ifdtool.h
@@ -14,6 +14,8 @@
#define IFDTOOL_VERSION 1.1-U-Boot
+#define WRITE_MAX 16
+
enum spi_frequency {
SPI_FREQUENCY_20MHZ = 0,
SPI_FREQUENCY_33MHZ = 1,
--
1.8.2.1
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[U-Boot] [PATCH v2 06/27] x86: Add Intel Crown Bay board dts file
Signed-off-by: Bin Meng bmeng...@gmail.com
Acked-by: Simon Glass s...@chromium.org
---
Changes in v2: None
arch/x86/dts/Makefile | 3 ++-
arch/x86/dts/crownbay.dts | 53 +++
2 files changed, 55 insertions(+), 1 deletion(-)
create mode 100644 arch/x86/dts/crownbay.dts
diff --git a/arch/x86/dts/Makefile b/arch/x86/dts/Makefile
index bb3b116..3b5d6da 100644
--- a/arch/x86/dts/Makefile
+++ b/arch/x86/dts/Makefile
@@ -1,6 +1,7 @@
dtb-y += link.dtb \
chromebook_link.dtb \
- alex.dtb
+ alex.dtb \
+ crownbay.dtb
targets += $(dtb-y)
diff --git a/arch/x86/dts/crownbay.dts b/arch/x86/dts/crownbay.dts
new file mode 100644
index 000..399dafb
--- /dev/null
+++ b/arch/x86/dts/crownbay.dts
@@ -0,0 +1,53 @@
+/*
+ * Copyright (C) 2014, Bin Meng bmeng...@gmail.com
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+/dts-v1/;
+
+/include/ coreboot.dtsi
+
+/ {
+ #address-cells = 1;
+ #size-cells = 1;
+ model = Intel Crown Bay;
+ compatible = intel,crownbay, intel,queensbay;
+
+ config {
+ silent_console = 0;
+ };
+
+ gpioa {
+ compatible = intel,ich6-gpio;
+ u-boot,dm-pre-reloc;
+ reg = 0 0x20;
+ bank-name = A;
+ };
+
+ gpiob {
+ compatible = intel,ich6-gpio;
+ u-boot,dm-pre-reloc;
+ reg = 0x20 0x20;
+ bank-name = B;
+ };
+
+ serial {
+ reg = 0x3f8 8;
+ clock-frequency = 115200;
+ };
+
+ chosen { };
+ memory { device_type = memory; reg = 0 0; };
+
+ spi {
+ #address-cells = 1;
+ #size-cells = 0;
+ compatible = intel,ich7;
+ spi-flash@0 {
+ reg = 0;
+ compatible = sst,25vf016b, spi-flash;
+ memory-map = 0xffe0 0x0020;
+ };
+ };
+};
--
1.8.2.1
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[U-Boot] [PATCH v2 08/27] x86: Add Intel Topcliff PCH device IDs
Signed-off-by: Bin Meng bmeng...@gmail.com Acked-by: Simon Glass s...@chromium.org --- Changes in v2: None include/pci_ids.h | 8 1 file changed, 8 insertions(+) diff --git a/include/pci_ids.h b/include/pci_ids.h index ee98bee..26f4748 100644 --- a/include/pci_ids.h +++ b/include/pci_ids.h @@ -2998,6 +2998,14 @@ #define PCI_DEVICE_ID_INTEL_82454NX 0x84cb #define PCI_DEVICE_ID_INTEL_84460GX0x84ea #define PCI_DEVICE_ID_INTEL_IXP4XX 0x8500 +#define PCI_DEVICE_ID_INTEL_TCF_GBE0x8802 +#define PCI_DEVICE_ID_INTEL_TCF_SDIO_0 0x8809 +#define PCI_DEVICE_ID_INTEL_TCF_SDIO_1 0x880a +#define PCI_DEVICE_ID_INTEL_TCF_SATA 0x880b +#define PCI_DEVICE_ID_INTEL_TCF_UART_0 0x8811 +#define PCI_DEVICE_ID_INTEL_TCF_UART_1 0x8812 +#define PCI_DEVICE_ID_INTEL_TCF_UART_2 0x8813 +#define PCI_DEVICE_ID_INTEL_TCF_UART_3 0x8814 #define PCI_DEVICE_ID_INTEL_IXP28000x9004 #define PCI_DEVICE_ID_INTEL_S21152BB 0xb152 -- 1.8.2.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 10/27] x86: Initial import from Intel FSP release for Queensbay platform
This is the initial import from Intel FSP release for Queensbay
platform (Tunnel Creek processor and Topcliff Platform Controller
Hub), which can be downloaded from Intel website.
For more details, check http://www.intel.com/fsp.
Note: U-Boot coding convention was applied to these codes, so it
looks completely different from the original Intel release.
Signed-off-by: Bin Meng bmeng...@gmail.com
---
Changes in v2:
- Apply U-Boot coding convention to the FSP support codes
arch/x86/cpu/queensbay/fsp_configs.c | 51 +++
arch/x86/cpu/queensbay/fsp_support.c | 428 +
arch/x86/include/asm/arch-queensbay/fsp/fsp_api.h | 79
.../include/asm/arch-queensbay/fsp/fsp_bootmode.h | 47 +++
arch/x86/include/asm/arch-queensbay/fsp/fsp_ffs.h | 189 +
arch/x86/include/asm/arch-queensbay/fsp/fsp_fv.h | 213 ++
arch/x86/include/asm/arch-queensbay/fsp/fsp_hob.h | 341
.../asm/arch-queensbay/fsp/fsp_infoheader.h| 59 +++
.../include/asm/arch-queensbay/fsp/fsp_platform.h | 42 ++
.../include/asm/arch-queensbay/fsp/fsp_support.h | 219 +++
.../x86/include/asm/arch-queensbay/fsp/fsp_types.h | 171
arch/x86/include/asm/arch-queensbay/fsp/fsp_vpd.h | 81
12 files changed, 1920 insertions(+)
create mode 100644 arch/x86/cpu/queensbay/fsp_configs.c
create mode 100644 arch/x86/cpu/queensbay/fsp_support.c
create mode 100644 arch/x86/include/asm/arch-queensbay/fsp/fsp_api.h
create mode 100644 arch/x86/include/asm/arch-queensbay/fsp/fsp_bootmode.h
create mode 100644 arch/x86/include/asm/arch-queensbay/fsp/fsp_ffs.h
create mode 100644 arch/x86/include/asm/arch-queensbay/fsp/fsp_fv.h
create mode 100644 arch/x86/include/asm/arch-queensbay/fsp/fsp_hob.h
create mode 100644 arch/x86/include/asm/arch-queensbay/fsp/fsp_infoheader.h
create mode 100644 arch/x86/include/asm/arch-queensbay/fsp/fsp_platform.h
create mode 100644 arch/x86/include/asm/arch-queensbay/fsp/fsp_support.h
create mode 100644 arch/x86/include/asm/arch-queensbay/fsp/fsp_types.h
create mode 100644 arch/x86/include/asm/arch-queensbay/fsp/fsp_vpd.h
diff --git a/arch/x86/cpu/queensbay/fsp_configs.c
b/arch/x86/cpu/queensbay/fsp_configs.c
new file mode 100644
index 000..1d1f43b
--- /dev/null
+++ b/arch/x86/cpu/queensbay/fsp_configs.c
@@ -0,0 +1,51 @@
+/** @file
+
+Copyright (C) 2013, Intel Corporation
+
+Redistribution and use in source and binary forms, with or without
modification,
+are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+* Redistributions in binary form must reproduce the above copyright notice,
this
+ list of conditions and the following disclaimer in the documentation and/or
+ other materials provided with the distribution.
+* Neither the name of Intel Corporation nor the names of its contributors may
+ be used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS AS IS
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ THE POSSIBILITY OF SUCH DAMAGE.
+
+**/
+
+#include types.h
+#include string.h
+#include fsp_support.h
+
+/**
+ * This function overrides the default configurations in the UPD data region.
+ *
+ * @fsp_upd: A pointer to the UPD_DATA_REGION data strcture
+ *
+ * @return: None
+ */
+void update_fsp_upd(UPD_DATA_REGION *fsp_upd)
+{
+ /* Override any UPD setting if required */
+
+ /* Uncomment the line below to enable DEBUG message */
+ /* fsp_upd-serial_dbgport_type = 1; */
+
+ /* Examples on how to initialize the pointers in UPD region */
+ /* fsp_upd-pcd_example = (EXAMPLE_DATA *)example; */
+}
diff --git a/arch/x86/cpu/queensbay/fsp_support.c
b/arch/x86/cpu/queensbay/fsp_support.c
new file mode 100644
index 000..804a63d
--- /dev/null
+++ b/arch/x86/cpu/queensbay/fsp_support.c
@@ -0,0 +1,428 @@
+/** @file
+
+Copyright (C) 2013, Intel Corporation
+
+Redistribution and use in source and binary forms, with or without
modification,
+are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice, this
+ list of
[U-Boot] [PATCH v2 09/27] x86: ich-spi: Add Intel Tunnel Creek SPI controller support
Add Intel Tunnel Creek SPI controller support which is an ICH7
compatible device.
Signed-off-by: Bin Meng bmeng...@gmail.com
Acked-by: Simon Glass s...@chromium.org
---
Changes in v2: None
drivers/spi/ich.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c
index f5c6f3e..0e00edf 100644
--- a/drivers/spi/ich.c
+++ b/drivers/spi/ich.c
@@ -158,7 +158,8 @@ void spi_free_slave(struct spi_slave *slave)
*/
static int get_ich_version(uint16_t device_id)
{
- if (device_id == PCI_DEVICE_ID_INTEL_TGP_LPC)
+ if (device_id == PCI_DEVICE_ID_INTEL_TGP_LPC ||
+ device_id == PCI_DEVICE_ID_INTEL_ITC_LPC)
return 7;
if ((device_id = PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MIN
--
1.8.2.1
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[U-Boot] [PATCH v2 11/27] x86: queensbay: Adapt FSP support codes
Use inline assembly codes to call FspNotify() to make sure parameters are passed on the stack as required by the FSP calling convention. Also update FSP support codes license header to use SPDX ID. Signed-off-by: Bin Meng bmeng...@gmail.com --- Changes in v2: - Update the codes to use U-Boot coding style arch/x86/cpu/queensbay/fsp_configs.c | 40 +++- arch/x86/cpu/queensbay/fsp_support.c | 76 +- arch/x86/include/asm/arch-queensbay/fsp/fsp_api.h | 35 ++ .../include/asm/arch-queensbay/fsp/fsp_bootmode.h | 35 ++ arch/x86/include/asm/arch-queensbay/fsp/fsp_ffs.h | 35 ++ arch/x86/include/asm/arch-queensbay/fsp/fsp_fv.h | 35 ++ arch/x86/include/asm/arch-queensbay/fsp/fsp_hob.h | 35 ++ .../asm/arch-queensbay/fsp/fsp_infoheader.h| 35 ++ .../include/asm/arch-queensbay/fsp/fsp_platform.h | 35 ++ .../include/asm/arch-queensbay/fsp/fsp_support.h | 37 ++- .../x86/include/asm/arch-queensbay/fsp/fsp_types.h | 35 ++ arch/x86/include/asm/arch-queensbay/fsp/fsp_vpd.h | 37 ++- 12 files changed, 101 insertions(+), 369 deletions(-) diff --git a/arch/x86/cpu/queensbay/fsp_configs.c b/arch/x86/cpu/queensbay/fsp_configs.c index 1d1f43b..8e3ce83 100644 --- a/arch/x86/cpu/queensbay/fsp_configs.c +++ b/arch/x86/cpu/queensbay/fsp_configs.c @@ -1,36 +1,12 @@ -/** @file - -Copyright (C) 2013, Intel Corporation - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -* Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. -* Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. -* Neither the name of Intel Corporation nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS AS IS - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - THE POSSIBILITY OF SUCH DAMAGE. - -**/ +/* + * Copyright (C) 2013, Intel Corporation + * Copyright (C) 2014, Bin Meng bmeng...@gmail.com + * + * SPDX-License-Identifier:Intel + */ -#include types.h -#include string.h -#include fsp_support.h +#include common.h +#include asm/arch/fsp/fsp_support.h /** * This function overrides the default configurations in the UPD data region. diff --git a/arch/x86/cpu/queensbay/fsp_support.c b/arch/x86/cpu/queensbay/fsp_support.c index 804a63d..58a30de 100644 --- a/arch/x86/cpu/queensbay/fsp_support.c +++ b/arch/x86/cpu/queensbay/fsp_support.c @@ -1,36 +1,13 @@ -/** @file - -Copyright (C) 2013, Intel Corporation - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -* Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. -* Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. -* Neither the name of Intel Corporation nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS AS IS - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS
[U-Boot] [PATCH v2 12/27] x86: Add post failure codes for bist and car
Signed-off-by: Bin Meng bmeng...@gmail.com
Acked-by: Simon Glass s...@chromium.org
---
Changes in v2: None
arch/x86/cpu/ivybridge/cpu.c | 1 +
arch/x86/include/asm/post.h | 2 ++
2 files changed, 3 insertions(+)
diff --git a/arch/x86/cpu/ivybridge/cpu.c b/arch/x86/cpu/ivybridge/cpu.c
index 60976db..969b07b 100644
--- a/arch/x86/cpu/ivybridge/cpu.c
+++ b/arch/x86/cpu/ivybridge/cpu.c
@@ -263,6 +263,7 @@ static void enable_usb_bar(void)
static int report_bist_failure(void)
{
if (gd-arch.bist != 0) {
+ post_code(POST_BIST_FAILURE);
printf(BIST failed: %08x\n, gd-arch.bist);
return -EFAULT;
}
diff --git a/arch/x86/include/asm/post.h b/arch/x86/include/asm/post.h
index 6d2ae5d..f49ce99 100644
--- a/arch/x86/include/asm/post.h
+++ b/arch/x86/include/asm/post.h
@@ -33,6 +33,8 @@
#define POST_LAPIC 0x30
#define POST_RAM_FAILURE 0xea
+#define POST_BIST_FAILURE 0xeb
+#define POST_CAR_FAILURE 0xec
/* Output a post code using al - value must be 0 to 0xff */
#ifdef __ASSEMBLY__
--
1.8.2.1
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[U-Boot] [PATCH v2 14/27] x86: Add a simple command to show FSP HOB information
FSP builds a series of data structures called the Hand-Off-Blocks
(HOBs) as it progresses through initializing the silicon. These data
structures conform to the HOB format as described in the Platform
Initialization (PI) specification Volume 3 Shared Architectual
Elements specification, which is part of the UEFI specification.
Create a simple command to parse the HOB list to display the HOB
address, type and length in bytes.
Signed-off-by: Bin Meng bmeng...@gmail.com
---
Changes in v2:
- Use ARRAY_SIZE to indicate the maximum number of HOB tyeps
- Remove some unnecessary spaces in the do_hob command output
arch/x86/lib/Makefile | 1 +
arch/x86/lib/cmd_hob.c | 67 ++
2 files changed, 68 insertions(+)
create mode 100644 arch/x86/lib/cmd_hob.c
diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile
index 55de788..73262d7 100644
--- a/arch/x86/lib/Makefile
+++ b/arch/x86/lib/Makefile
@@ -10,6 +10,7 @@ obj-y += bios_asm.o
obj-y += bios_interrupts.o
obj-$(CONFIG_CMD_BOOTM) += bootm.o
obj-y += cmd_boot.o
+obj-$(CONFIG_HAVE_FSP) += cmd_hob.o
obj-y += gcc.o
obj-y += init_helpers.o
obj-y += interrupts.o
diff --git a/arch/x86/lib/cmd_hob.c b/arch/x86/lib/cmd_hob.c
new file mode 100644
index 000..7dfa1a1
--- /dev/null
+++ b/arch/x86/lib/cmd_hob.c
@@ -0,0 +1,67 @@
+/*
+ * Copyright (C) 2014, Bin Meng bmeng...@gmail.com
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include command.h
+#include linux/compiler.h
+#include asm/arch/fsp/fsp_support.h
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static char *hob_type[] = {
+ reserved,
+ Hand-off,
+ Memory Allocation,
+ Resource Descriptor,
+ GUID Extension,
+ Firmware Volumn,
+ CPU,
+ Memory Pool,
+ reserved,
+ Firmware Volumn 2,
+ Load PEIM Unused,
+ UEFI Capsule,
+};
+
+int do_hob(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ EFI_PEI_HOB_POINTERS hob;
+ UINT16 type;
+ char *desc;
+ int i = 0;
+
+ hob.raw = (UINT8 *)gd-arch.hob_list;
+
+ printf(HOB list address: 0x%08x\n\n, (unsigned int)hob.raw);
+
+ printf(No. | Address | Type| Length in Bytes\n);
+ printf(|--|-|\n);
+ while (!END_OF_HOB(hob)) {
+ printf(%-3d | %08x | , i, (unsigned int)hob.raw);
+ type = hob.hdr-type;
+ if (type == HOB_TYPE_UNUSED)
+ desc = *Unused*;
+ else if (type == HOB_TYPE_EOH)
+ desc = **END OF HOB**;
+ else if (type = 0 type = ARRAY_SIZE(hob_type))
+ desc = hob_type[type];
+ else
+ desc = !!!Invalid Type!!!;
+ printf(%-19s | %-15d\n, desc, hob.hdr-len);
+ hob.raw = GET_NEXT_HOB(hob);
+ i++;
+ }
+
+ return 0;
+}
+
+/* */
+
+U_BOOT_CMD(
+ hob,1, 1, do_hob,
+ print FSP Hand-Off Block information,
+
+);
--
1.8.2.1
___
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U-Boot@lists.denx.de
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[U-Boot] [PATCH v2 13/27] x86: Support Intel FSP initialization path in start.S
Per Intel FSP architecture specification, FSP provides 3 routines
for bootloader to call. The first one is the TempRamInit (aka
Cache-As-Ram initialization) and the second one is the FspInit
which does the memory bring up (like MRC for other x86 targets)
and chipset initialization. Those two routines have to be called
before U-Boot jumping to board_init_f in start.S.
The FspInit() will return several memory blocks called Hand Off
Blocks (HOBs) whose format is described in Platform Initialization
(PI) specification (part of the UEFI specication) to the bootloader.
Save this HOB address to the U-Boot global data for later use.
Signed-off-by: Bin Meng bmeng...@gmail.com
---
Changes in v2:
- Move FspInit call from start.S to car_init
arch/x86/cpu/start.S | 14 ++
arch/x86/include/asm/global_data.h | 3 +++
arch/x86/lib/asm-offsets.c | 3 +++
3 files changed, 20 insertions(+)
diff --git a/arch/x86/cpu/start.S b/arch/x86/cpu/start.S
index f9662fb..125782c 100644
--- a/arch/x86/cpu/start.S
+++ b/arch/x86/cpu/start.S
@@ -75,6 +75,7 @@ early_board_init_ret:
jmp car_init
.globl car_init_ret
car_init_ret:
+#ifndef CONFIG_HAVE_FSP
/*
* We now have CONFIG_SYS_CAR_SIZE bytes of Cache-As-RAM (or SRAM,
* or fully initialised SDRAM - we really don't care which)
@@ -95,6 +96,12 @@ car_init_ret:
#ifdef CONFIG_DCACHE_RAM_MRC_VAR_SIZE
subl$CONFIG_DCACHE_RAM_MRC_VAR_SIZE, %esp
#endif
+#else
+ /*
+* When we get here after car_init, esp points to a temporary stack
+* and esi holds the HOB list address returned by the FSP.
+*/
+#endif
/* Reserve space on stack for global data */
subl$GENERATED_GBL_DATA_SIZE, %esp
@@ -109,6 +116,13 @@ car_init_ret:
movl%esp, %edi
rep stosb
+#ifdef CONFIG_HAVE_FSP
+ /* Store HOB list */
+ movl%esp, %edx
+ addl$GD_HOB_LIST, %edx
+ movl%esi, (%edx)
+#endif
+
/* Setup first parameter to setup_gdt, pointer to global_data */
movl%esp, %eax
diff --git a/arch/x86/include/asm/global_data.h
b/arch/x86/include/asm/global_data.h
index 48bbd1a..03d491a 100644
--- a/arch/x86/include/asm/global_data.h
+++ b/arch/x86/include/asm/global_data.h
@@ -47,6 +47,9 @@ struct arch_global_data {
enum pei_boot_mode_t pei_boot_mode;
const struct pch_gpio_map *gpio_map;/* board GPIO map */
struct memory_info meminfo; /* Memory information */
+#ifdef CONFIG_HAVE_FSP
+ void*hob_list; /* FSP HOB list */
+#endif
};
#endif
diff --git a/arch/x86/lib/asm-offsets.c b/arch/x86/lib/asm-offsets.c
index 50a488f..70ccf1b 100644
--- a/arch/x86/lib/asm-offsets.c
+++ b/arch/x86/lib/asm-offsets.c
@@ -18,5 +18,8 @@
int main(void)
{
DEFINE(GD_BIST, offsetof(gd_t, arch.bist));
+#ifdef CONFIG_HAVE_FSP
+ DEFINE(GD_HOB_LIST, offsetof(gd_t, arch.hob_list));
+#endif
return 0;
}
--
1.8.2.1
___
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[U-Boot] [PATCH v2 15/27] x86: Integrate Tunnel Creek processor microcode
Integrate the processor microcode version 1.05 for Tunnel Creek, CPUID device 20661h. Signed-off-by: Bin Meng bmeng...@gmail.com --- Changes in v2: None arch/x86/cpu/queensbay/M0220661105.inc | 1288 1 file changed, 1288 insertions(+) create mode 100644 arch/x86/cpu/queensbay/M0220661105.inc diff --git a/arch/x86/cpu/queensbay/M0220661105.inc b/arch/x86/cpu/queensbay/M0220661105.inc new file mode 100644 index 000..f2b2b4e --- /dev/null +++ b/arch/x86/cpu/queensbay/M0220661105.inc @@ -0,0 +1,1288 @@ +/* + * Copyright (C) 2013, Intel Corporation + * + * SPDX-License-Identifier:Intel + */ + +/* External Header */ +.long 0x0001 /* Header Version */ +.long 0x0105 /* Update Revision */ +.long 0x07182011 /* Date */ +.long 0x00020661 /* Processor Signature */ +.long 0x52558795 /* Checksum */ +.long 0x0001 /* Loader Revision */ +.long 0x0002 /* Processor Flags */ +.long 0x13d0 /* Data Size (excluding headers) */ +.long 0x1400 /* Total Size (including headers) */ +.long 0x /* Reserved */ +.long 0x /* Reserved */ +.long 0x /* Reserved */ +/* Data */ +.long 0x +.long 0x00a1 +.long 0x00020001 +.long 0x0105 +.long 0x0019 +.long 0x00050100 +.long 0x20110715 +.long 0x0401 +.long 0x0001 +.long 0x00020661 +.long 0x +.long 0x +.long 0x +.long 0x +.long 0x +.long 0x +.long 0x +.long 0x +.long 0x +.long 0x +.long 0x +.long 0x +.long 0x +.long 0x +.long 0x57a55795 +.long 0xe30f7a7d +.long 0x53be2f8e +.long 0x46e3b90d +.long 0xd6005cd3 +.long 0xb734bb21 +.long 0x06642b66 +.long 0x355042a0 +.long 0x0882023d +.long 0x953684cb +.long 0x0abe06ee +.long 0xa7ef1798 +.long 0x160d6cb8 +.long 0x930cf745 +.long 0xafc3fd79 +.long 0xa70df3d5 +.long 0xb0620f46 +.long 0x70048a23 +.long 0xbf95ecf0 +.long 0x76c1b997 +.long 0x5128616d +.long 0xb6b4b969 +.long 0xcc69f71d +.long 0xdf7416e1 +.long 0xdf9a571b +.long 0x50c0bcc8 +.long 0x85e2b3cd +.long 0xc1927532 +.long 0x7a04b6be +.long 0xe56b7f97 +.long 0x524085c4 +.long 0x668bf327 +.long 0xb3eaa54c +.long 0xccde06f8 +.long 0x09b4e42b +.long 0x033b0a46 +.long 0x0f6e2fde +.long 0xb308ce53 +.long 0x93eff03e +.long 0x8830014e +.long 0x5c8a6f22 +.long 0x91d2f757 +.long 0xf70b648d +.long 0x0789998a +.long 0xd84d4640 +.long 0xe5f34e80 +.long 0xf3357e64 +.long 0xd1e2beea +.long 0xc7e95c3a +.long 0x30e57e4d +.long 0xec214356 +.long 0x7e10859e +.long 0x1d5895d5 +.long 0xdeeff6cb +.long 0xed1030ed +.long 0x827e603d +.long 0x6b4b2de3 +.long 0x83ec6fd0 +.long 0xa64092f3 +.long 0x8d9887e4 +.long 0xbefcbedd +.long 0x2111afef +.long 0xcb9abf96 +.long 0x5c79ceac +.long 0x9bf8a57f +.long 0x5d0e44be +.long 0xdca3d3b6 +.long 0x9072d1ca +.long 0x48e73a50 +.long 0x8d0bc804 +.long 0x6aea94d3 +.long 0xc372403e +.long 0x0011 +.long 0x5de60a0b +.long 0xbd3cc5c6 +.long 0x2d6c2ad5 +.long 0x2f19cc84 +.long 0x7d8e4989 +.long 0x86062789 +.long 0xe00581e6 +.long 0x70a57340 +.long 0x8e8d33d3 +.long 0x52311951 +.long 0x2f186672 +.long 0xfa530598 +.long 0x909cb851 +.long 0x51613bd1 +.long 0x910ae4e6 +.long 0xd897b90a +.long 0x3b440a2d +.long 0x6d563d9d +.long 0xd1020482 +.long 0xcc9fe7db +.long 0x450b5e7c +.long 0x6d2194af +.long 0x507971bf +.long 0xd43d0b52 +.long 0x96336a56 +.long 0x4f796f0b +.long 0xa5eddfc5 +.long 0x020fba71 +.long 0xeda53948 +.long 0xa6e4a439 +.long 0x52c667e5 +.long 0x9749040e +.long 0xfdefa084 +.long 0x7871c609 +.long 0xc815a889 +.long 0x551582ac +.long 0x039371d6 +.long 0x4e962b58 +.long 0xf6533afe +.long 0x8b9b1b24 +.long 0x5754e6c6 +.long 0x0a4e3a62 +.long 0x037d0d59 +.long 0xe17c0ee5 +.long 0x0047ca4b +.long 0xff5e4ff2 +.long 0xd9201b1f +.long 0x7e22e377 +.long 0x5d5e9b69 +.long 0x21f6a59a +.long 0xa0bb08ff +.long 0x16e77cf1 +.long 0xf536530f +.long 0xa755e0bc +.long 0xac9dea8c +.long 0x6cd2098e +.long 0xf0ddc366 +.long 0x6016c7be +.long 0xd28c2475 +.long 0x8dcfaf29 +.long 0xcee5ada5 +.long 0xe5ac8bf6 +.long 0xcd13b563 +.long 0x42a83647 +.long 0xdf80bf4d +.long 0xdffb854e +.long 0x563dce4d +.long 0xdc0f15f2 +.long 0x092723c4 +.long 0x3a3edcff +.long 0x3d2ab792 +.long 0x15e7fc9f +.long 0xd1592968 +.long 0x3ca31b09 +.long 0x29c71d0f +.long 0x24a9292f +.long 0x2924f71d +.long 0x5d36b019 +.long 0xd83c5a2d +.long 0x51736120 +.long 0xf9749010 +.long 0x4a8732f2 +.long 0x6995d740 +.long 0xc6e4db97 +.long 0x4568b6a3 +.long 0xaa2f4da0 +.long 0x969ace6d +.long 0x673c96d4 +.long 0x766f51d4 +.long 0x4db0a064 +.long 0xfedd870b +.long 0x5d30a5d8 +.long 0x67cf7e71 +.long 0x35901877 +.long 0xd42e5440 +.long 0xf10f185a +.long 0x2c2e04b2 +.long 0x9b813966 +.long 0xc356070f +.long 0x70bd39f9 +.long 0xd6e0ef25 +.long 0xe95ab63e +.long 0xd257a039 +.long 0x555659b2 +.long 0xfdb408f8 +.long 0x93052de2 +.long 0x00652576 +.long 0xeee6ee0e +.long 0xcfd19568 +.long 0xa717c19f +.long 0x155f9ed1 +.long 0x85f077f6 +.long 0x0db3cd1e +.long 0x75094d70 +.long 0x2ef49990 +.long 0xb2e01b42 +.long
[U-Boot] [PATCH v2 17/27] x86: ich6-gpio: Add Intel Tunnel Creek GPIO support
Intel Tunnel Creek GPIO register block is compatible with current
ich6-gpio driver, except the offset and content of GPIO block base
address register in the LPC PCI configuration space are different.
Use u16 instead of u32 to store the 16-bit I/O address of the GPIO
registers so that it could support both Ivybridge and Tunnel Creek.
Signed-off-by: Bin Meng bmeng...@gmail.com
---
Changes in v2:
- Add a comment to explain we don't need check bit0 in GPIO base
address register
- Add setup_pch_gpios() in crownbay.c
arch/x86/include/asm/arch-queensbay/gpio.h | 13 +
arch/x86/include/asm/gpio.h| 4 ++--
board/coreboot/coreboot/coreboot.c | 2 +-
board/google/chromebook_link/link.c| 2 +-
board/intel/crownbay/crownbay.c| 5 +
drivers/gpio/intel_ich6_gpio.c | 20
6 files changed, 34 insertions(+), 12 deletions(-)
create mode 100644 arch/x86/include/asm/arch-queensbay/gpio.h
diff --git a/arch/x86/include/asm/arch-queensbay/gpio.h
b/arch/x86/include/asm/arch-queensbay/gpio.h
new file mode 100644
index 000..ab4e059
--- /dev/null
+++ b/arch/x86/include/asm/arch-queensbay/gpio.h
@@ -0,0 +1,13 @@
+/*
+ * Copyright (C) 2014, Bin Meng bmeng...@gmail.com
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef _X86_ARCH_GPIO_H_
+#define _X86_ARCH_GPIO_H_
+
+/* Where in config space is the register that points to the GPIO registers? */
+#define PCI_CFG_GPIOBASE 0x44
+
+#endif /* _X86_ARCH_GPIO_H_ */
diff --git a/arch/x86/include/asm/gpio.h b/arch/x86/include/asm/gpio.h
index 1787e52..1099427 100644
--- a/arch/x86/include/asm/gpio.h
+++ b/arch/x86/include/asm/gpio.h
@@ -11,7 +11,7 @@
#include asm-generic/gpio.h
struct ich6_bank_platdata {
- uint32_t base_addr;
+ uint16_t base_addr;
const char *bank_name;
};
@@ -147,7 +147,7 @@ struct pch_gpio_map {
} set3;
};
-void setup_pch_gpios(u32 gpiobase, const struct pch_gpio_map *gpio);
+void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio);
void ich_gpio_set_gpio_map(const struct pch_gpio_map *map);
#endif /* _X86_GPIO_H_ */
diff --git a/board/coreboot/coreboot/coreboot.c
b/board/coreboot/coreboot/coreboot.c
index b260f9a..154faf6 100644
--- a/board/coreboot/coreboot/coreboot.c
+++ b/board/coreboot/coreboot/coreboot.c
@@ -16,7 +16,7 @@ int arch_early_init_r(void)
return 0;
}
-void setup_pch_gpios(u32 gpiobase, const struct pch_gpio_map *gpio)
+void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio)
{
return;
}
diff --git a/board/google/chromebook_link/link.c
b/board/google/chromebook_link/link.c
index 4d95c1c..9978e92 100644
--- a/board/google/chromebook_link/link.c
+++ b/board/google/chromebook_link/link.c
@@ -125,7 +125,7 @@ int board_early_init_f(void)
return 0;
}
-void setup_pch_gpios(u32 gpiobase, const struct pch_gpio_map *gpio)
+void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio)
{
/* GPIO Set 1 */
if (gpio-set1.level)
diff --git a/board/intel/crownbay/crownbay.c b/board/intel/crownbay/crownbay.c
index 8c6df98..54670d3 100644
--- a/board/intel/crownbay/crownbay.c
+++ b/board/intel/crownbay/crownbay.c
@@ -19,3 +19,8 @@ int board_early_init_f(void)
return 0;
}
+
+void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio)
+{
+ return;
+}
diff --git a/drivers/gpio/intel_ich6_gpio.c b/drivers/gpio/intel_ich6_gpio.c
index 1f0d9df..5f67b3f 100644
--- a/drivers/gpio/intel_ich6_gpio.c
+++ b/drivers/gpio/intel_ich6_gpio.c
@@ -39,9 +39,9 @@
struct ich6_bank_priv {
/* These are I/O addresses */
- uint32_t use_sel;
- uint32_t io_sel;
- uint32_t lvl;
+ uint16_t use_sel;
+ uint16_t io_sel;
+ uint16_t lvl;
};
/* TODO: Move this to device tree, or platform data */
@@ -57,7 +57,7 @@ static int gpio_ich6_ofdata_to_platdata(struct udevice *dev)
u8 tmpbyte;
u16 tmpword;
u32 tmplong;
- u32 gpiobase;
+ u16 gpiobase;
int offset;
/* Where should it be? */
@@ -116,11 +116,15 @@ static int gpio_ich6_ofdata_to_platdata(struct udevice
*dev)
/*
* GPIOBASE moved to its current offset with ICH6, but prior to
* that it was unused (or undocumented). Check that it looks
-* okay: not all ones or zeros, and mapped to I/O space (bit 0).
+* okay: not all ones or zeros.
+*
+* Note we don't need check bit0 here, because the Tunnel Creek
+* GPIO base address register bit0 is reserved (read returns 0),
+* while on the Ivybridge the bit0 is used to indicate it is an
+* I/O space.
*/
tmplong = pci_read_config32(pci_dev, PCI_CFG_GPIOBASE);
- if (tmplong == 0x || tmplong == 0x ||
- !(tmplong 0x0001)) {
+ if (tmplong == 0x || tmplong == 0x) {
debug(%s: unexpected GPIOBASE
[U-Boot] [PATCH v2 16/27] x86: Add basic support to queensbay platform and crownbay board
Implement minimum required functions for the basic support to
queensbay platform and crownbay board.
Signed-off-by: Bin Meng bmeng...@gmail.com
---
Changes in v2:
- Replace 0xcf9 with macro PORT_RESET from processor.h
- Move FspInit call from start.S to car_init
- Add UART0_BASE and UART1_BASE to ibmpc.h
arch/x86/cpu/queensbay/Makefile | 9
arch/x86/cpu/queensbay/tnc.c | 48 ++
arch/x86/cpu/queensbay/tnc_car.S | 103 ++
arch/x86/cpu/queensbay/tnc_dram.c | 78 +
arch/x86/cpu/queensbay/tnc_pci.c | 61 ++
arch/x86/include/asm/ibmpc.h | 3 ++
board/intel/crownbay/MAINTAINERS | 6 +++
board/intel/crownbay/Makefile | 7 +++
board/intel/crownbay/crownbay.c | 21
board/intel/crownbay/start.S | 9
10 files changed, 345 insertions(+)
create mode 100644 arch/x86/cpu/queensbay/Makefile
create mode 100644 arch/x86/cpu/queensbay/tnc.c
create mode 100644 arch/x86/cpu/queensbay/tnc_car.S
create mode 100644 arch/x86/cpu/queensbay/tnc_dram.c
create mode 100644 arch/x86/cpu/queensbay/tnc_pci.c
create mode 100644 board/intel/crownbay/MAINTAINERS
create mode 100644 board/intel/crownbay/Makefile
create mode 100644 board/intel/crownbay/crownbay.c
create mode 100644 board/intel/crownbay/start.S
diff --git a/arch/x86/cpu/queensbay/Makefile b/arch/x86/cpu/queensbay/Makefile
new file mode 100644
index 000..ace04ca
--- /dev/null
+++ b/arch/x86/cpu/queensbay/Makefile
@@ -0,0 +1,9 @@
+#
+# Copyright (C) 2014, Bin Meng bmeng...@gmail.com
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += tnc_car.o tnc_dram.o tnc.o
+obj-y += fsp_configs.o fsp_support.o
+obj-$(CONFIG_PCI) += tnc_pci.o
diff --git a/arch/x86/cpu/queensbay/tnc.c b/arch/x86/cpu/queensbay/tnc.c
new file mode 100644
index 000..b1df57a
--- /dev/null
+++ b/arch/x86/cpu/queensbay/tnc.c
@@ -0,0 +1,48 @@
+/*
+ * Copyright (C) 2014, Bin Meng bmeng...@gmail.com
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include asm/io.h
+#include asm/post.h
+#include asm/arch/fsp/fsp_support.h
+#include asm/processor.h
+
+int arch_cpu_init(void)
+{
+ post_code(POST_CPU_INIT);
+#ifdef CONFIG_SYS_X86_TSC_TIMER
+ timer_set_base(rdtsc());
+#endif
+
+ return x86_cpu_init_f();
+}
+
+int print_cpuinfo(void)
+{
+ post_code(POST_CPU_INFO);
+ return default_print_cpuinfo();
+}
+
+void reset_cpu(ulong addr)
+{
+ /* cold reset */
+ outb(0x06, PORT_RESET);
+}
+
+void board_final_cleanup(void)
+{
+ EFI_STATUS status;
+
+ /* call into FspNotify */
+ debug(Calling into FSP (notify phase INIT_PHASE_BOOT): );
+ status = fsp_notify(NULL, INIT_PHASE_BOOT);
+ if (status != FSP_SUCCESS)
+ debug(fail, error code %x\n, status);
+ else
+ debug(OK\n);
+
+ return;
+}
diff --git a/arch/x86/cpu/queensbay/tnc_car.S b/arch/x86/cpu/queensbay/tnc_car.S
new file mode 100644
index 000..4f39e42
--- /dev/null
+++ b/arch/x86/cpu/queensbay/tnc_car.S
@@ -0,0 +1,103 @@
+/*
+ * Copyright (C) 2014, Bin Meng bmeng...@gmail.com
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include config.h
+#include asm/post.h
+
+.globl car_init
+car_init:
+ /*
+* Note: ebp holds the BIST value (built-in self test) so far, but ebp
+* will be destroyed through the FSP call, thus we have to test the
+* BIST value here before we call into FSP.
+*/
+ test%ebp, %ebp
+ jz car_init_start
+ post_code(POST_BIST_FAILURE)
+ jmp die
+
+car_init_start:
+ post_code(POST_CAR_START)
+ lea find_fsp_header_stack, %esp
+ jmp find_fsp_header
+
+find_fsp_header_ret:
+ /* EAX points to FSP_INFO_HEADER */
+ mov %eax, %ebp
+
+ /* sanity test */
+ cmp $CONFIG_FSP_LOCATION, %eax
+ jb die
+
+ /* calculate TempRamInitEntry address */
+ mov 0x30(%ebp), %eax
+ add 0x1c(%ebp), %eax
+
+ /* call FSP TempRamInitEntry to setup temporary stack */
+ lea temp_ram_init_stack, %esp
+ jmp *%eax
+
+temp_ram_init_ret:
+ addl$4, %esp
+ cmp $0, %eax
+ jz continue
+ post_code(POST_CAR_FAILURE)
+
+die:
+ hlt
+ jmp die
+ hlt
+
+continue:
+ post_code(POST_CAR_CPU_CACHE)
+
+ /*
+* The FSP TempRamInit initializes the ecx and edx registers to
+* point to a temporary but writable memory range (Cache-As-RAM).
+* ecx: the start of this temporary memory range,
+* edx: the end of this range.
+*/
+
+ /* stack grows down from top of CAR */
+ movl%edx, %esp
+
+ movl$CONFIG_FSP_TEMP_RAM_ADDR, %eax
+ xorl%edx, %edx
+ xorl%ecx, %ecx
+ callfsp_init
+
+.global fsp_init_done
+fsp_init_done:
+ /*
+* We come here from
[U-Boot] [PATCH v2 18/27] x86: Enable the queensbay cpu directory build
Signed-off-by: Bin Meng bmeng...@gmail.com Acked-by: Simon Glass s...@chromium.org --- Changes in v2: None arch/x86/cpu/Makefile | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/x86/cpu/Makefile b/arch/x86/cpu/Makefile index 7f09db5..5033d2b 100644 --- a/arch/x86/cpu/Makefile +++ b/arch/x86/cpu/Makefile @@ -15,6 +15,7 @@ obj-y += interrupts.o cpu.o call64.o obj-$(CONFIG_SYS_COREBOOT) += coreboot/ obj-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) += ivybridge/ obj-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) += ivybridge/ +obj-$(CONFIG_INTEL_QUEENSBAY) += queensbay/ obj-y += lapic.o obj-$(CONFIG_PCI) += pci.o obj-y += turbo.o -- 1.8.2.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 22/27] x86: Include FSP and CMC binary in the u-boot.rom build rules
Signed-off-by: Bin Meng bmeng...@gmail.com
---
Changes in v2:
- Update ifdtool flags to indicate FSP and CMC files are in
the board directory
- Use consistent XXX_FILE name for binary blob file
Makefile | 10 +-
include/configs/chromebook_link.h | 2 +-
2 files changed, 10 insertions(+), 2 deletions(-)
diff --git a/Makefile b/Makefile
index ff4c4aa..81d27cf 100644
--- a/Makefile
+++ b/Makefile
@@ -976,8 +976,16 @@ ifneq ($(CONFIG_HAVE_MRC),)
IFDTOOL_FLAGS += -w $(CONFIG_X86_MRC_ADDR):$(srctree)/board/$(BOARDDIR)/mrc.bin
endif
+ifneq ($(CONFIG_HAVE_FSP),)
+IFDTOOL_FLAGS += -w
$(CONFIG_FSP_ADDR):$(srctree)/board/$(BOARDDIR)/$(CONFIG_FSP_FILE)
+endif
+
+ifneq ($(CONFIG_HAVE_CMC),)
+IFDTOOL_FLAGS += -w
$(CONFIG_CMC_ADDR):$(srctree)/board/$(BOARDDIR)/$(CONFIG_CMC_FILE)
+endif
+
ifneq ($(CONFIG_X86_OPTION_ROM_ADDR),)
-IFDTOOL_FLAGS += -w
$(CONFIG_X86_OPTION_ROM_ADDR):$(srctree)/board/$(BOARDDIR)/$(CONFIG_X86_OPTION_ROM_FILENAME)
+IFDTOOL_FLAGS += -w
$(CONFIG_X86_OPTION_ROM_ADDR):$(srctree)/board/$(BOARDDIR)/$(CONFIG_X86_OPTION_ROM_FILE)
endif
quiet_cmd_ifdtool = IFDTOOL $@
diff --git a/include/configs/chromebook_link.h
b/include/configs/chromebook_link.h
index c9d84e4..b311f4c 100644
--- a/include/configs/chromebook_link.h
+++ b/include/configs/chromebook_link.h
@@ -39,7 +39,7 @@
{PCI_VENDOR_ID_INTEL, \
PCI_DEVICE_ID_INTEL_PANTHERPOINT_AHCI_MOBILE}
-#define CONFIG_X86_OPTION_ROM_FILENAME pci8086,0166.bin
+#define CONFIG_X86_OPTION_ROM_FILE pci8086,0166.bin
#define CONFIG_X86_OPTION_ROM_ADDR 0xfff9
#define CONFIG_VIDEO_X86
--
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[U-Boot] [PATCH v2 21/27] x86: Use consistent name XXX_ADDR for binary blob flash address
Signed-off-by: Bin Meng bmeng...@gmail.com
---
Changes in v2:
- New patch to use consistent name XXX_ADDR for binary blobs
Makefile | 2 +-
arch/x86/cpu/ivybridge/sdram.c | 2 +-
arch/x86/cpu/queensbay/Kconfig | 4 ++--
arch/x86/cpu/queensbay/fsp_support.c | 2 +-
arch/x86/cpu/queensbay/tnc_car.S | 2 +-
include/configs/chromebook_link.h| 2 +-
6 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/Makefile b/Makefile
index c9ae77b..ff4c4aa 100644
--- a/Makefile
+++ b/Makefile
@@ -973,7 +973,7 @@ IFDTOOL_ME_FLAGS += -i
ME:$(srctree)/board/$(BOARDDIR)/me.bin
endif
ifneq ($(CONFIG_HAVE_MRC),)
-IFDTOOL_FLAGS += -w
$(CONFIG_X86_MRC_START):$(srctree)/board/$(BOARDDIR)/mrc.bin
+IFDTOOL_FLAGS += -w $(CONFIG_X86_MRC_ADDR):$(srctree)/board/$(BOARDDIR)/mrc.bin
endif
ifneq ($(CONFIG_X86_OPTION_ROM_ADDR),)
diff --git a/arch/x86/cpu/ivybridge/sdram.c b/arch/x86/cpu/ivybridge/sdram.c
index df2b990..b95e781 100644
--- a/arch/x86/cpu/ivybridge/sdram.c
+++ b/arch/x86/cpu/ivybridge/sdram.c
@@ -177,7 +177,7 @@ int sdram_initialise(struct pei_data *pei_data)
debug(PEI data at %p, size %x:\n, pei_data, sizeof(*pei_data));
- data = (char *)CONFIG_X86_MRC_START;
+ data = (char *)CONFIG_X86_MRC_ADDR;
if (data) {
int rv;
int (*func)(struct pei_data *);
diff --git a/arch/x86/cpu/queensbay/Kconfig b/arch/x86/cpu/queensbay/Kconfig
index 56fe85c..f6b5201 100644
--- a/arch/x86/cpu/queensbay/Kconfig
+++ b/arch/x86/cpu/queensbay/Kconfig
@@ -29,7 +29,7 @@ config FSP_FILE
The filename of the file to use as Firmware Support Package binary
in the board directory.
-config FSP_LOCATION
+config FSP_ADDR
hex Firmware Support Package binary location
depends on HAVE_FSP
default 0xfffc
@@ -65,7 +65,7 @@ config CMC_FILE
The filename of the file to use as Chipset Micro Code state machine
binary in the board directory.
-config CMC_LOCATION
+config CMC_ADDR
hex Chipset Micro Code state machine binary location
depends on HAVE_CMC
default 0xfffb
diff --git a/arch/x86/cpu/queensbay/fsp_support.c
b/arch/x86/cpu/queensbay/fsp_support.c
index 58a30de..e85f823 100644
--- a/arch/x86/cpu/queensbay/fsp_support.c
+++ b/arch/x86/cpu/queensbay/fsp_support.c
@@ -64,7 +64,7 @@ UINT32 __attribute__((optimize(O0))) find_fsp_header(void)
volatile register UINT8 * fsp asm(eax);
/* Initalize the FSP base */
- fsp = (UINT8 *)CONFIG_FSP_LOCATION;
+ fsp = (UINT8 *)CONFIG_FSP_ADDR;
/* Check the FV signature, _FVH */
if (((EFI_FIRMWARE_VOLUME_HEADER *)fsp)-signature == 0x4856465F) {
diff --git a/arch/x86/cpu/queensbay/tnc_car.S b/arch/x86/cpu/queensbay/tnc_car.S
index 4f39e42..344597b 100644
--- a/arch/x86/cpu/queensbay/tnc_car.S
+++ b/arch/x86/cpu/queensbay/tnc_car.S
@@ -29,7 +29,7 @@ find_fsp_header_ret:
mov %eax, %ebp
/* sanity test */
- cmp $CONFIG_FSP_LOCATION, %eax
+ cmp $CONFIG_FSP_ADDR, %eax
jb die
/* calculate TempRamInitEntry address */
diff --git a/include/configs/chromebook_link.h
b/include/configs/chromebook_link.h
index 645b31c..c9d84e4 100644
--- a/include/configs/chromebook_link.h
+++ b/include/configs/chromebook_link.h
@@ -25,7 +25,7 @@
#define CONFIG_X86_RESET_VECTOR
#define CONFIG_NR_DRAM_BANKS 8
-#define CONFIG_X86_MRC_START 0xfffa
+#define CONFIG_X86_MRC_ADDR0xfffa
#define CONFIG_CACHE_MRC_SIZE_KB 512
#define CONFIG_COREBOOT_SERIAL
--
1.8.2.1
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[U-Boot] [PATCH v2 20/27] x86: Add crownbay defconfig and config.h
Signed-off-by: Bin Meng bmeng...@gmail.com
---
Changes in v2: None
configs/crownbay_defconfig | 6 ++
include/configs/crownbay.h | 52 ++
2 files changed, 58 insertions(+)
create mode 100644 configs/crownbay_defconfig
create mode 100644 include/configs/crownbay.h
diff --git a/configs/crownbay_defconfig b/configs/crownbay_defconfig
new file mode 100644
index 000..ce90553
--- /dev/null
+++ b/configs/crownbay_defconfig
@@ -0,0 +1,6 @@
+CONFIG_SYS_EXTRA_OPTIONS=SYS_TEXT_BASE=0xfff0
+CONFIG_X86=y
+CONFIG_TARGET_CROWNBAY=y
+CONFIG_OF_CONTROL=y
+CONFIG_OF_SEPARATE=y
+CONFIG_DEFAULT_DEVICE_TREE=crownbay
diff --git a/include/configs/crownbay.h b/include/configs/crownbay.h
new file mode 100644
index 000..2314e62
--- /dev/null
+++ b/include/configs/crownbay.h
@@ -0,0 +1,52 @@
+/*
+ * Copyright (C) 2014, Bin Meng bmeng...@gmail.com
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include configs/x86-common.h
+
+#define CONFIG_SYS_MONITOR_LEN (1 20)
+#define CONFIG_SYS_X86_START16 0xf800
+#define CONFIG_BOARD_EARLY_INIT_F
+
+#define CONFIG_X86_RESET_VECTOR
+#define CONFIG_NR_DRAM_BANKS 1
+
+#define CONFIG_COREBOOT_SERIAL
+#define CONFIG_SMSC_LPC47M
+
+#define CONFIG_PCI_MEM_BUS 0x4000
+#define CONFIG_PCI_MEM_PHYSCONFIG_PCI_MEM_BUS
+#define CONFIG_PCI_MEM_SIZE0x8000
+
+#define CONFIG_PCI_PREF_BUS0xc000
+#define CONFIG_PCI_PREF_PHYS CONFIG_PCI_PREF_BUS
+#define CONFIG_PCI_PREF_SIZE 0x2000
+
+#define CONFIG_PCI_IO_BUS 0x2000
+#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
+#define CONFIG_PCI_IO_SIZE 0xe000
+
+#define CONFIG_SYS_EARLY_PCI_INIT
+#define CONFIG_PCI_PNP
+
+#define CONFIG_STD_DEVICES_SETTINGS stdin=serial\0 \
+ stdout=serial\0 \
+ stderr=serial\0
+
+#define CONFIG_SCSI_DEV_LIST\
+ {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TCF_SATA}
+
+/* Video is not supported */
+#undef CONFIG_VIDEO
+#undef CONFIG_CFB_CONSOLE
+
+#endif /* __CONFIG_H */
--
1.8.2.1
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[U-Boot] [PATCH v2 19/27] x86: Add queensbay and crownbay Kconfig files
Signed-off-by: Bin Meng bmeng...@gmail.com --- Changes in v2: - Fix several typos in queensbay/Kconfig - Change FSP_FILE and CMC_FILE description to indicate the file is in the board directory - Add help for FSP_TEMP_RAM_ADDR - Add more help for CMC_FILE arch/x86/Kconfig | 13 +++ arch/x86/cpu/queensbay/Kconfig | 79 ++ board/intel/crownbay/Kconfig | 20 +++ 3 files changed, 112 insertions(+) create mode 100644 arch/x86/cpu/queensbay/Kconfig create mode 100644 board/intel/crownbay/Kconfig diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index fdfb618..ebf72b3 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -32,6 +32,15 @@ config TARGET_CHROMEBOOK_LINK and it provides a 2560x1700 high resolution touch-enabled LCD display. +config TARGET_CROWNBAY + bool Support Intel Crown Bay CRB + help + This is the Intel Crown Bay Customer Reference Board. It contains + the Intel Atom Processor E6xx populated on the COM Express module + with 1GB DDR2 soldered down memory and a carrier board with the + Intel Platform Controller Hub EG20T, other system components and + peripheral connectors for PCIe/SATA/USB/LAN/SD/UART/Audio/LVDS. + endchoice config RAMBASE @@ -310,8 +319,12 @@ endmenu source arch/x86/cpu/ivybridge/Kconfig +source arch/x86/cpu/queensbay/Kconfig + source board/coreboot/coreboot/Kconfig source board/google/chromebook_link/Kconfig +source board/intel/crownbay/Kconfig + endmenu diff --git a/arch/x86/cpu/queensbay/Kconfig b/arch/x86/cpu/queensbay/Kconfig new file mode 100644 index 000..56fe85c --- /dev/null +++ b/arch/x86/cpu/queensbay/Kconfig @@ -0,0 +1,79 @@ +# +# Copyright (C) 2014, Bin Meng bmeng...@gmail.com +# +# SPDX-License-Identifier: GPL-2.0+ +# + +config INTEL_QUEENSBAY + bool + select HAVE_FSP + select HAVE_CMC + +if INTEL_QUEENSBAY + +config HAVE_FSP + bool Add an Firmware Support Package binary + help + Select this option to add an Firmware Support Package binary to + the resulting U-Boot image. It is a binary blob which U-Boot uses + to set up SDRAM and other chipset specific initialization. + + Note: Without this binary U-Boot will not be able to set up its + SDRAM so will not boot. + +config FSP_FILE + string Firmware Support Package binary filename + depends on HAVE_FSP + default fsp.bin + help + The filename of the file to use as Firmware Support Package binary + in the board directory. + +config FSP_LOCATION + hex Firmware Support Package binary location + depends on HAVE_FSP + default 0xfffc + help + FSP is not Position Independent Code (PIC) and the whole FSP has to + be rebased if it is placed at a location which is different from the + perferred base address specified during the FSP build. Use Intel's + Binary Configuration Tool (BCT) to do the rebase. + + The default base address of 0xfffc indicates that the binary must + be located at offset 0xc from the beginning of a 1MB flash device. + +config FSP_TEMP_RAM_ADDR + hex + default 0x200 + help + Stack top address which is used in FspInit after DRAM is ready and + CAR is disabled. + +config HAVE_CMC + bool Add a Chipset Micro Code state machine binary + help + Select this option to add a Chipset Micro Code state machine binary + to the resulting U-Boot image. It is a 64K data block of machine + specific code which must be put in the flash for the processor to + access when powered up before system BIOS is executed. + +config CMC_FILE + string Chipset Micro Code state machine filename + depends on HAVE_CMC + default cmc.bin + help + The filename of the file to use as Chipset Micro Code state machine + binary in the board directory. + +config CMC_LOCATION + hex Chipset Micro Code state machine binary location + depends on HAVE_CMC + default 0xfffb + help + The location of the CMC binary is determined by a strap. It must be + put in flash at a location matching the strap-determined base address. + + The default base address of 0xfffb indicates that the binary must + be located at offset 0xb from the beginning of a 1MB flash device. + +endif diff --git a/board/intel/crownbay/Kconfig b/board/intel/crownbay/Kconfig new file mode 100644 index 000..4709f9b --- /dev/null +++ b/board/intel/crownbay/Kconfig @@ -0,0 +1,20 @@ +if TARGET_CROWNBAY + +config SYS_BOARD + default crownbay + +config SYS_VENDOR + default intel + +config SYS_SOC + default queensbay + +config SYS_CONFIG_NAME + default crownbay + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y +
[U-Boot] [PATCH v2 23/27] x86: crownbay: Add SPI flash support
Signed-off-by: Bin Meng bmeng...@gmail.com
---
Changes in v2:
- Move PCH_LPC_DEV to arch/x86/include/asm/arch-queensbay/tnc.h
- Check return value of x86_cpu_init_f()
arch/x86/cpu/queensbay/tnc.c | 26 +-
arch/x86/include/asm/arch-queensbay/tnc.h | 15 +++
include/configs/crownbay.h| 2 ++
3 files changed, 42 insertions(+), 1 deletion(-)
create mode 100644 arch/x86/include/asm/arch-queensbay/tnc.h
diff --git a/arch/x86/cpu/queensbay/tnc.c b/arch/x86/cpu/queensbay/tnc.c
index b1df57a..8a0e04e 100644
--- a/arch/x86/cpu/queensbay/tnc.c
+++ b/arch/x86/cpu/queensbay/tnc.c
@@ -6,18 +6,42 @@
#include common.h
#include asm/io.h
+#include asm/pci.h
#include asm/post.h
+#include asm/arch/tnc.h
#include asm/arch/fsp/fsp_support.h
#include asm/processor.h
+static void unprotect_spi_flash(void)
+{
+ u32 bc;
+
+ bc = pci_read_config32(PCH_LPC_DEV, 0xd8);
+ bc |= 0x1; /* unprotect the flash */
+ pci_write_config32(PCH_LPC_DEV, 0xd8, bc);
+}
+
int arch_cpu_init(void)
{
+ struct pci_controller *hose;
+ int ret;
+
post_code(POST_CPU_INIT);
#ifdef CONFIG_SYS_X86_TSC_TIMER
timer_set_base(rdtsc());
#endif
- return x86_cpu_init_f();
+ ret = x86_cpu_init_f();
+ if (ret)
+ return ret;
+
+ ret = pci_early_init_hose(hose);
+ if (ret)
+ return ret;
+
+ unprotect_spi_flash();
+
+ return 0;
}
int print_cpuinfo(void)
diff --git a/arch/x86/include/asm/arch-queensbay/tnc.h
b/arch/x86/include/asm/arch-queensbay/tnc.h
new file mode 100644
index 000..67c5e05
--- /dev/null
+++ b/arch/x86/include/asm/arch-queensbay/tnc.h
@@ -0,0 +1,15 @@
+/*
+ * Copyright (C) 2014, Bin Meng bmeng...@gmail.com
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef _X86_ARCH_TNC_H_
+#define _X86_ARCH_TNC_H_
+
+#include pci.h
+
+/* PCI Configuration Space (D31:F0): LPC */
+#define PCH_LPC_DEVPCI_BDF(0, 0x1f, 0)
+
+#endif /* _X86_ARCH_TNC_H_ */
diff --git a/include/configs/crownbay.h b/include/configs/crownbay.h
index 2314e62..a051b11 100644
--- a/include/configs/crownbay.h
+++ b/include/configs/crownbay.h
@@ -45,6 +45,8 @@
#define CONFIG_SCSI_DEV_LIST\
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TCF_SATA}
+#define CONFIG_SPI_FLASH_SST
+
/* Video is not supported */
#undef CONFIG_VIDEO
#undef CONFIG_CFB_CONSOLE
--
1.8.2.1
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[U-Boot] [PATCH v2 26/27] x86: Rename coreboot-serial to x86-serial
Signed-off-by: Bin Meng bmeng...@gmail.com
---
Changes in v2:
- New patch to rename coreboot-serial to x86-serial
arch/x86/dts/coreboot.dtsi | 2 +-
drivers/serial/Makefile| 2 +-
drivers/serial/{serial_coreboot.c = serial_x86.c} | 12 ++--
include/configs/chromebook_link.h | 2 +-
include/configs/coreboot.h | 2 +-
include/configs/crownbay.h | 2 +-
6 files changed, 11 insertions(+), 11 deletions(-)
rename drivers/serial/{serial_coreboot.c = serial_x86.c} (67%)
diff --git a/arch/x86/dts/coreboot.dtsi b/arch/x86/dts/coreboot.dtsi
index c8dc4ce..65a93ac 100644
--- a/arch/x86/dts/coreboot.dtsi
+++ b/arch/x86/dts/coreboot.dtsi
@@ -6,7 +6,7 @@
};
serial {
- compatible = coreboot-uart;
+ compatible = x86-uart;
reg = 0x3f8 0x10;
reg-shift = 0;
io-mapped = 1;
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index 8c84942..4cc00cd 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -43,7 +43,7 @@ obj-$(CONFIG_ARC_SERIAL) += serial_arc.o
obj-$(CONFIG_TEGRA_SERIAL) += serial_tegra.o
obj-$(CONFIG_UNIPHIER_SERIAL) += serial_uniphier.o
obj-$(CONFIG_OMAP_SERIAL) += serial_omap.o
-obj-$(CONFIG_COREBOOT_SERIAL) += serial_coreboot.o
+obj-$(CONFIG_X86_SERIAL) += serial_x86.o
ifndef CONFIG_SPL_BUILD
obj-$(CONFIG_USB_TTY) += usbtty.o
diff --git a/drivers/serial/serial_coreboot.c b/drivers/serial/serial_x86.c
similarity index 67%
rename from drivers/serial/serial_coreboot.c
rename to drivers/serial/serial_x86.c
index 5c6a76c..e81e035 100644
--- a/drivers/serial/serial_coreboot.c
+++ b/drivers/serial/serial_x86.c
@@ -9,12 +9,12 @@
#include ns16550.h
#include serial.h
-static const struct udevice_id coreboot_serial_ids[] = {
- { .compatible = coreboot-uart },
+static const struct udevice_id x86_serial_ids[] = {
+ { .compatible = x86-uart },
{ }
};
-static int coreboot_serial_ofdata_to_platdata(struct udevice *dev)
+static int x86_serial_ofdata_to_platdata(struct udevice *dev)
{
struct ns16550_platdata *plat = dev_get_platdata(dev);
int ret;
@@ -27,10 +27,10 @@ static int coreboot_serial_ofdata_to_platdata(struct
udevice *dev)
return 0;
}
U_BOOT_DRIVER(serial_ns16550) = {
- .name = serial_coreboot,
+ .name = serial_x86,
.id = UCLASS_SERIAL,
- .of_match = coreboot_serial_ids,
- .ofdata_to_platdata = coreboot_serial_ofdata_to_platdata,
+ .of_match = x86_serial_ids,
+ .ofdata_to_platdata = x86_serial_ofdata_to_platdata,
.platdata_auto_alloc_size = sizeof(struct ns16550_platdata),
.priv_auto_alloc_size = sizeof(struct NS16550),
.probe = ns16550_serial_probe,
diff --git a/include/configs/chromebook_link.h
b/include/configs/chromebook_link.h
index b311f4c..8930210 100644
--- a/include/configs/chromebook_link.h
+++ b/include/configs/chromebook_link.h
@@ -28,7 +28,7 @@
#define CONFIG_X86_MRC_ADDR0xfffa
#define CONFIG_CACHE_MRC_SIZE_KB 512
-#define CONFIG_COREBOOT_SERIAL
+#define CONFIG_X86_SERIAL
#define CONFIG_SCSI_DEV_LIST {PCI_VENDOR_ID_INTEL, \
PCI_DEVICE_ID_INTEL_NM10_AHCI}, \
diff --git a/include/configs/coreboot.h b/include/configs/coreboot.h
index 2581380..990a2d1 100644
--- a/include/configs/coreboot.h
+++ b/include/configs/coreboot.h
@@ -49,7 +49,7 @@
{PCI_VENDOR_ID_INTEL, \
PCI_DEVICE_ID_INTEL_PANTHERPOINT_AHCI_MOBILE}
-#define CONFIG_COREBOOT_SERIAL
+#define CONFIG_X86_SERIAL
#define CONFIG_STD_DEVICES_SETTINGS stdin=usbkbd,vga,serial\0 \
stdout=vga,serial,cbmem\0 \
diff --git a/include/configs/crownbay.h b/include/configs/crownbay.h
index b9db6b7..eadb339 100644
--- a/include/configs/crownbay.h
+++ b/include/configs/crownbay.h
@@ -20,7 +20,7 @@
#define CONFIG_X86_RESET_VECTOR
#define CONFIG_NR_DRAM_BANKS 1
-#define CONFIG_COREBOOT_SERIAL
+#define CONFIG_X86_SERIAL
#define CONFIG_SMSC_LPC47M
#define CONFIG_PCI_MEM_BUS 0x4000
--
1.8.2.1
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[U-Boot] [PATCH v2 24/27] x86: crownbay: Enable Intel E1000 NIC support
We don't have driver for the Intel Topcliff PCH Gigabit Ethernet
controller for now, so enable the Intle E1000 NIC support, which
can be plugged into any PCIe slot on the Crown Bay board.
Signed-off-by: Bin Meng bmeng...@gmail.com
Acked-by: Simon Glass s...@chromium.org
---
Changes in v2: None
board/intel/crownbay/crownbay.c | 6 ++
include/configs/crownbay.h | 1 +
2 files changed, 7 insertions(+)
diff --git a/board/intel/crownbay/crownbay.c b/board/intel/crownbay/crownbay.c
index 54670d3..2a254ef 100644
--- a/board/intel/crownbay/crownbay.c
+++ b/board/intel/crownbay/crownbay.c
@@ -7,6 +7,7 @@
#include common.h
#include asm/ibmpc.h
#include asm/pnp_def.h
+#include netdev.h
#include smsc_lpc47m.h
#define SERIAL_DEV PNP_DEV(0x2e, 4)
@@ -24,3 +25,8 @@ void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map
*gpio)
{
return;
}
+
+int board_eth_init(bd_t *bis)
+{
+ return pci_eth_init(bis);
+}
diff --git a/include/configs/crownbay.h b/include/configs/crownbay.h
index a051b11..09a52ab 100644
--- a/include/configs/crownbay.h
+++ b/include/configs/crownbay.h
@@ -37,6 +37,7 @@
#define CONFIG_SYS_EARLY_PCI_INIT
#define CONFIG_PCI_PNP
+#define CONFIG_E1000
#define CONFIG_STD_DEVICES_SETTINGS stdin=serial\0 \
stdout=serial\0 \
--
1.8.2.1
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[U-Boot] [PATCH v2 25/27] x86: crownbay: Add SDHCI support
There are two standard SD card slots on the Crown Bay board, which
are connected to the Topcliff PCH SDIO controllers. Enable the SDHC
support so that we can use them.
Signed-off-by: Bin Meng bmeng...@gmail.com
---
Changes in v2:
- Use ARRAY_SIZE(mmc_supported) instead of 2
- Check return value of add_sdhci()
arch/x86/cpu/queensbay/Makefile | 2 +-
arch/x86/cpu/queensbay/topcliff.c | 47 +++
include/configs/crownbay.h| 6 +
3 files changed, 54 insertions(+), 1 deletion(-)
create mode 100644 arch/x86/cpu/queensbay/topcliff.c
diff --git a/arch/x86/cpu/queensbay/Makefile b/arch/x86/cpu/queensbay/Makefile
index ace04ca..2c2ec01 100644
--- a/arch/x86/cpu/queensbay/Makefile
+++ b/arch/x86/cpu/queensbay/Makefile
@@ -4,6 +4,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
-obj-y += tnc_car.o tnc_dram.o tnc.o
+obj-y += tnc_car.o tnc_dram.o tnc.o topcliff.o
obj-y += fsp_configs.o fsp_support.o
obj-$(CONFIG_PCI) += tnc_pci.o
diff --git a/arch/x86/cpu/queensbay/topcliff.c
b/arch/x86/cpu/queensbay/topcliff.c
new file mode 100644
index 000..b01422a
--- /dev/null
+++ b/arch/x86/cpu/queensbay/topcliff.c
@@ -0,0 +1,47 @@
+/*
+ * Copyright (C) 2014, Bin Meng bmeng...@gmail.com
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include errno.h
+#include malloc.h
+#include pci.h
+#include pci_ids.h
+#include sdhci.h
+
+static struct pci_device_id mmc_supported[] = {
+ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TCF_SDIO_0 },
+ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TCF_SDIO_1 },
+ { }
+};
+
+int cpu_mmc_init(bd_t *bis)
+{
+ struct sdhci_host *mmc_host;
+ pci_dev_t devbusfn;
+ u32 iobase;
+ int ret;
+ int i;
+
+ for (i = 0; i ARRAY_SIZE(mmc_supported); i++) {
+ devbusfn = pci_find_devices(mmc_supported, i);
+ if (devbusfn == -1)
+ return -ENODEV;
+
+ mmc_host = (struct sdhci_host *)malloc(sizeof(struct
sdhci_host));
+ if (!mmc_host)
+ return -ENOMEM;
+
+ mmc_host-name = Topcliff SDHCI;
+ pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, iobase);
+ mmc_host-ioaddr = (void *)iobase;
+ mmc_host-quirks = 0;
+ ret = add_sdhci(mmc_host, 0, 0);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
diff --git a/include/configs/crownbay.h b/include/configs/crownbay.h
index 09a52ab..b9db6b7 100644
--- a/include/configs/crownbay.h
+++ b/include/configs/crownbay.h
@@ -48,6 +48,12 @@
#define CONFIG_SPI_FLASH_SST
+#define CONFIG_MMC
+#define CONFIG_SDHCI
+#define CONFIG_GENERIC_MMC
+#define CONFIG_MMC_SDMA
+#define CONFIG_CMD_MMC
+
/* Video is not supported */
#undef CONFIG_VIDEO
#undef CONFIG_CFB_CONSOLE
--
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[U-Boot] [PATCH v2 27/27] x86: Add a README.x86 for U-Boot on x86 support
Signed-off-by: Bin Meng bmeng...@gmail.com --- Changes in v2: - Remove the 'make menuconfig' in the crownbay build instructions - Indicate all the binary blobs should be put in the board directory doc/README.x86 | 126 + 1 file changed, 126 insertions(+) create mode 100644 doc/README.x86 diff --git a/doc/README.x86 b/doc/README.x86 new file mode 100644 index 000..902aa7e --- /dev/null +++ b/doc/README.x86 @@ -0,0 +1,126 @@ +# +# Copyright (C) 2014, Simon Glass s...@chromium.org +# Copyright (C) 2014, Bin Meng bmeng...@gmail.com +# +# SPDX-License-Identifier: GPL-2.0+ +# + +U-Boot on x86 += + +This document describes the information about U-Boot running on x86 targets, +including supported boards, build instructions, todo list, etc. + +Status +-- +U-Boot supports running as a coreboot [1] payload on x86. So far only link +(Chromebook pixel) has been tested, but it should work with minimal adjustments +on other x86 boards since coreboot deals with most of the low-level details. + +U-Boot also supports booting directly from x86 reset vector without coreboot, +aka raw support or bare support. Currently Google Chromebook link and Intel +Crown Bay board support running U-Boot 'bare metal'. + +As for loading OS, U-Boot supports directly booting a 32-bit or 64-bit Linux +kernel as part of a FIT image. It also supports a compressed zImage. + +Build Instructions +-- +Building U-Boot as a coreboot payload is just like building U-Boot for targets +on other architectures, like below: + +$ make coreboot-x86_defconfig +$ make all + +Building rom version U-Boot (hereafter referred to as u-boot.rom) is a little +bit tricky, as generally it requires several binary blobs which are not shipped +in the U-Boot source tree. Due to this reason, the u-boot.rom build is not +turned on by default in the U-Boot source tree. Firstly, you need turn it on +by uncommenting the following line in the main U-Boot Makefile: + +# ALL-$(CONFIG_X86_RESET_VECTOR) += u-boot.rom + +Google Chromebook link specific instructions: + +Firstly, you need the following binary blobs: + +* descriptor.bin - Intel flash descriptor +* me.bin - Intel Management Engine +* mrc.bin - Memory Reference Code, which sets up SDRAM +* video ROM - sets up the display + +You can get these binary blobs by: + +$ git clone http://review.coreboot.org/p/blobs.git +$ cd blobs + +Find the following files: + +* ./mainboard/google/link/descriptor.bin +* ./mainboard/google/link/me.bin +* ./northbridge/intel/sandybridge/systemagent-ivybridge.bin + +The 3rd one should be renamed to mrc.bin. +As for the video ROM, you can get it here [2]. +Make sure all these binary blobs are put in the board directory. + +Now you can build U-Boot and obtain u-boot.rom: + +$ make chromebook_link_defconfig +$ make all + +Intel Crown Bay specific instructions: + +U-Boot support of Intel Crown Bay board [3] relies on a binary blob called +Firmware Support Package [4] to perform all the necessary initialization steps +as documented in the BIOS Writer Guide including initialization of the CPU, +memory controller, chipset and certain bus interfaces. + +Downalod the Intel FSP for Atom E6xx series and Platform Controller Hub EG20T, +install it on your host and locate the FSP binary blob. Note this platform +also requires a Chipset Micro Code (CMC) state machine binary to be present in +the SPI flash where u-boot.rom resides, and this CMC binary blob can be found +in this FSP package too. + +* ./FSP/QUEENSBAY_FSP_GOLD_001_20-DECEMBER-2013.fd +* ./Microcode/C0_22211.BIN + +Rename the first one to fsp.bin and second one to cmc.bin and put them in the +board directory. + +Now you can build U-Boot and obtaim u-boot.rom + +$ make crownbay_defconfig +$ make all + +CPU Microcode +- +Modern CPU usually requires a special bit stream called microcode [5] to be +loaded on the processor after power up in order to function properly. U-Boot +has already integrated these as hex dumps in the source tree. + +Driver Model + +x86 has been converted to use driver model for serial and GPIO. + +Device Tree +--- +x86 uses device tree to configure the board thus requires CONFIG_OF_CONTROL to +be turned on. Not every device on the board is configured via devie tree, but +more and more devices will be added as time goes by. Check out the directory +arch/x86/dts/ for these device tree source files. + +TODO List +- +- MTRR support (for performance) +- Audio +- Chrome OS verified boot +- SMI and ACPI support, to provide platform info and facilities to Linux + +References +-- +[1] http://www.coreboot.org +[2] http://www.coreboot.org/~stepan/pci8086,0166.rom +[3] http://www.intel.com/content/www/us/en/embedded/design-tools/evaluation-platforms/atom-e660-eg20t-development-kit.html +[4] http://www.intel.com/fsp +[5] http://en.wikipedia.org/wiki/Microcode -- 1.8.2.1
[U-Boot] [PATCH 0/4] sf: SST changes, Byte program
This patch-set added byte program support for sst flashes and some implementation changes in sf to support array slow and byte program specific controllers. Bin Meng (1): spi: sf: Support byte program for sst spi flash Jagannadha Sutradharudu Teki (2): sf: Fix look for the fastest read command sf: Enable byte program support Simon Glass (1): spi: Fix flag collision for SST_WP drivers/mtd/spi/sf_internal.h | 22 ++--- drivers/mtd/spi/sf_ops.c | 31 + drivers/mtd/spi/sf_params.c | 102 +- drivers/mtd/spi/sf_probe.c| 9 +++- include/spi.h | 1 + 5 files changed, 105 insertions(+), 60 deletions(-) -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 2/4] spi: Fix flag collision for SST_WP
From: Simon Glass s...@chromium.org
At present SECT_4K is the same as SST_WP so we cannot tell these apart. Fix
this so that the table in sf_params.c can be used correctly.
Reported-by: Jens Rottmann jens.rottm...@adlinktech.com
Signed-off-by: Simon Glass s...@chromium.org
Reviewed-by: Jagannadha Sutradharudu Teki jagannadh.t...@gmail.com
---
drivers/mtd/spi/sf_internal.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h
index e159f04..7218e69 100644
--- a/drivers/mtd/spi/sf_internal.h
+++ b/drivers/mtd/spi/sf_internal.h
@@ -41,6 +41,7 @@ enum {
SECT_32K= 1 1,
E_FSR = 1 2,
WR_QPP = 1 3,
+ SST_WP = 1 4,
};
#define SPI_FLASH_3B_ADDR_LEN 3
@@ -104,7 +105,6 @@ enum {
/* SST specific */
#ifdef CONFIG_SPI_FLASH_SST
-# define SST_WP0x01/* Supports AAI word program */
# define CMD_SST_BP0x02/* Byte Program */
# define CMD_SST_AAI_WP0xAD/* Auto Address Incr Word Program */
--
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[U-Boot] [PATCH 4/4] sf: Enable byte program support
Enabled byte program support for sst flashes in sf.
Few controllers will only support BP, so this patch
gives a rx transfer flag to set the BP so-that sf
will operate on byte program transfer.
Signed-off-by: Jagannadha Sutradharudu Teki jagannadh.t...@gmail.com
---
drivers/mtd/spi/sf_internal.h | 5 -
drivers/mtd/spi/sf_params.c | 18 +-
drivers/mtd/spi/sf_probe.c| 8 ++--
include/spi.h | 1 +
4 files changed, 20 insertions(+), 12 deletions(-)
diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h
index fb53cb0..785f7a9 100644
--- a/drivers/mtd/spi/sf_internal.h
+++ b/drivers/mtd/spi/sf_internal.h
@@ -40,10 +40,13 @@ enum {
SECT_4K = 1 0,
SECT_32K= 1 1,
E_FSR = 1 2,
- WR_QPP = 1 3,
+ SST_BP = 1 3,
SST_WP = 1 4,
+ WR_QPP = 1 5,
};
+#define SST_WR (SST_BP | SST_WP)
+
#define SPI_FLASH_3B_ADDR_LEN 3
#define SPI_FLASH_CMD_LEN (1 + SPI_FLASH_3B_ADDR_LEN)
#define SPI_FLASH_16MB_BOUN0x100
diff --git a/drivers/mtd/spi/sf_params.c b/drivers/mtd/spi/sf_params.c
index 0f1f837..30875b3 100644
--- a/drivers/mtd/spi/sf_params.c
+++ b/drivers/mtd/spi/sf_params.c
@@ -89,16 +89,16 @@ const struct spi_flash_params spi_flash_params_table[] = {
{N25Q1024A, 0x20bb21, 0x0, 64 * 1024, 2048, RD_FULL,
WR_QPP | E_FSR | SECT_4K},
#endif
#ifdef CONFIG_SPI_FLASH_SST/* SST */
- {SST25VF040B,0xbf258d, 0x0, 64 * 1024, 8, RD_NORM,
SECT_4K | SST_WP},
- {SST25VF080B,0xbf258e, 0x0, 64 * 1024,16, RD_NORM,
SECT_4K | SST_WP},
- {SST25VF016B,0xbf2541, 0x0, 64 * 1024,32, RD_NORM,
SECT_4K | SST_WP},
- {SST25VF032B,0xbf254a, 0x0, 64 * 1024,64, RD_NORM,
SECT_4K | SST_WP},
+ {SST25VF040B,0xbf258d, 0x0, 64 * 1024, 8, RD_NORM,
SECT_4K | SST_WR},
+ {SST25VF080B,0xbf258e, 0x0, 64 * 1024,16, RD_NORM,
SECT_4K | SST_WR},
+ {SST25VF016B,0xbf2541, 0x0, 64 * 1024,32, RD_NORM,
SECT_4K | SST_WR},
+ {SST25VF032B,0xbf254a, 0x0, 64 * 1024,64, RD_NORM,
SECT_4K | SST_WR},
{SST25VF064C,0xbf254b, 0x0, 64 * 1024, 128, RD_NORM,
SECT_4K},
- {SST25WF512, 0xbf2501, 0x0, 64 * 1024, 1, RD_NORM,
SECT_4K | SST_WP},
- {SST25WF010, 0xbf2502, 0x0, 64 * 1024, 2, RD_NORM,
SECT_4K | SST_WP},
- {SST25WF020, 0xbf2503, 0x0, 64 * 1024, 4, RD_NORM,
SECT_4K | SST_WP},
- {SST25WF040, 0xbf2504, 0x0, 64 * 1024, 8, RD_NORM,
SECT_4K | SST_WP},
- {SST25WF080, 0xbf2505, 0x0, 64 * 1024,16, RD_NORM,
SECT_4K | SST_WP},
+ {SST25WF512, 0xbf2501, 0x0, 64 * 1024, 1, RD_NORM,
SECT_4K | SST_WR},
+ {SST25WF010, 0xbf2502, 0x0, 64 * 1024, 2, RD_NORM,
SECT_4K | SST_WR},
+ {SST25WF020, 0xbf2503, 0x0, 64 * 1024, 4, RD_NORM,
SECT_4K | SST_WR},
+ {SST25WF040, 0xbf2504, 0x0, 64 * 1024, 8, RD_NORM,
SECT_4K | SST_WR},
+ {SST25WF080, 0xbf2505, 0x0, 64 * 1024,16, RD_NORM,
SECT_4K | SST_WR},
#endif
#ifdef CONFIG_SPI_FLASH_WINBOND/* WINBOND */
{W25P80, 0xef2014, 0x0, 64 * 1024,16, RD_NORM,
0},
diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c
index 7cde4c0..ce9987f 100644
--- a/drivers/mtd/spi/sf_probe.c
+++ b/drivers/mtd/spi/sf_probe.c
@@ -136,8 +136,12 @@ static int spi_flash_validate_params(struct spi_slave
*spi, u8 *idcode,
#ifndef CONFIG_DM_SPI_FLASH
flash-write = spi_flash_cmd_write_ops;
#if defined(CONFIG_SPI_FLASH_SST)
- if (params-flags SST_WP)
- flash-write = sst_write_wp;
+ if (params-flags SST_WR) {
+ if (flash-spi-op_mode_tx SPI_OPM_TX_BP)
+ flash-write = sst_write_bp;
+ else
+ flash-write = sst_write_wp;
+ }
#endif
flash-erase = spi_flash_cmd_erase_ops;
flash-read = spi_flash_cmd_read_ops;
diff --git a/include/spi.h b/include/spi.h
index 5b78271..ec17bd0 100644
--- a/include/spi.h
+++ b/include/spi.h
@@ -34,6 +34,7 @@
/* SPI TX operation modes */
#define SPI_OPM_TX_QPP (1 0)
+#define SPI_OPM_TX_BP (1 1)
/* SPI RX operation modes */
#define SPI_OPM_RX_AS (1 0)
--
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[U-Boot] [PATCH 1/4] sf: Fix look for the fastest read command
Few of the spi controllers are only supports array slow
read which is quite different behaviour compared to others.
So this fix on sf will correctly handle the slow read supported
controllers.
Signed-off-by: Jagannadha Sutradharudu Teki jagannadh.t...@gmail.com
---
drivers/mtd/spi/sf_internal.h | 13 +++---
drivers/mtd/spi/sf_params.c | 102 +-
drivers/mtd/spi/sf_probe.c| 1 +
3 files changed, 60 insertions(+), 56 deletions(-)
diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h
index 5b7670c..e159f04 100644
--- a/drivers/mtd/spi/sf_internal.h
+++ b/drivers/mtd/spi/sf_internal.h
@@ -23,13 +23,16 @@ enum spi_dual_flash {
/* Enum list - Full read commands */
enum spi_read_cmds {
ARRAY_SLOW = 1 0,
- DUAL_OUTPUT_FAST= 1 1,
- DUAL_IO_FAST= 1 2,
- QUAD_OUTPUT_FAST= 1 3,
- QUAD_IO_FAST= 1 4,
+ ARRAY_FAST = 1 1,
+ DUAL_OUTPUT_FAST= 1 2,
+ DUAL_IO_FAST= 1 3,
+ QUAD_OUTPUT_FAST= 1 4,
+ QUAD_IO_FAST= 1 5,
};
-#define RD_EXTN(ARRAY_SLOW | DUAL_OUTPUT_FAST | DUAL_IO_FAST)
+/* Normal - Extended - Full command set */
+#define RD_NORM(ARRAY_SLOW | ARRAY_FAST)
+#define RD_EXTN(RD_NORM | DUAL_OUTPUT_FAST | DUAL_IO_FAST)
#define RD_FULL(RD_EXTN | QUAD_OUTPUT_FAST | QUAD_IO_FAST)
/* sf param flags */
diff --git a/drivers/mtd/spi/sf_params.c b/drivers/mtd/spi/sf_params.c
index 61545ca..0f1f837 100644
--- a/drivers/mtd/spi/sf_params.c
+++ b/drivers/mtd/spi/sf_params.c
@@ -15,42 +15,42 @@
/* SPI/QSPI flash device params structure */
const struct spi_flash_params spi_flash_params_table[] = {
#ifdef CONFIG_SPI_FLASH_ATMEL /* ATMEL */
- {AT45DB011D, 0x1f2200, 0x0, 64 * 1024, 4, 0,
SECT_4K},
- {AT45DB021D, 0x1f2300, 0x0, 64 * 1024, 8, 0,
SECT_4K},
- {AT45DB041D, 0x1f2400, 0x0, 64 * 1024, 8, 0,
SECT_4K},
- {AT45DB081D, 0x1f2500, 0x0, 64 * 1024,16, 0,
SECT_4K},
- {AT45DB161D, 0x1f2600, 0x0, 64 * 1024,32, 0,
SECT_4K},
- {AT45DB321D, 0x1f2700, 0x0, 64 * 1024,64, 0,
SECT_4K},
- {AT45DB641D, 0x1f2800, 0x0, 64 * 1024, 128, 0,
SECT_4K},
- {AT25DF321, 0x1f4701, 0x0, 64 * 1024,64, 0,
SECT_4K},
+ {AT45DB011D, 0x1f2200, 0x0, 64 * 1024, 4, RD_NORM,
SECT_4K},
+ {AT45DB021D, 0x1f2300, 0x0, 64 * 1024, 8, RD_NORM,
SECT_4K},
+ {AT45DB041D, 0x1f2400, 0x0, 64 * 1024, 8, RD_NORM,
SECT_4K},
+ {AT45DB081D, 0x1f2500, 0x0, 64 * 1024,16, RD_NORM,
SECT_4K},
+ {AT45DB161D, 0x1f2600, 0x0, 64 * 1024,32, RD_NORM,
SECT_4K},
+ {AT45DB321D, 0x1f2700, 0x0, 64 * 1024,64, RD_NORM,
SECT_4K},
+ {AT45DB641D, 0x1f2800, 0x0, 64 * 1024, 128, RD_NORM,
SECT_4K},
+ {AT25DF321, 0x1f4701, 0x0, 64 * 1024,64, RD_NORM,
SECT_4K},
#endif
#ifdef CONFIG_SPI_FLASH_EON/* EON */
- {EN25Q32B, 0x1c3016, 0x0, 64 * 1024,64, 0,
0},
- {EN25Q64,0x1c3017, 0x0, 64 * 1024, 128, 0,
SECT_4K},
- {EN25Q128B, 0x1c3018, 0x0, 64 * 1024, 256, 0,
0},
- {EN25S64,0x1c3817, 0x0, 64 * 1024, 128, 0,
0},
+ {EN25Q32B, 0x1c3016, 0x0, 64 * 1024,64, RD_NORM,
0},
+ {EN25Q64,0x1c3017, 0x0, 64 * 1024, 128, RD_NORM,
SECT_4K},
+ {EN25Q128B, 0x1c3018, 0x0, 64 * 1024, 256, RD_NORM,
0},
+ {EN25S64,0x1c3817, 0x0, 64 * 1024, 128, RD_NORM,
0},
#endif
#ifdef CONFIG_SPI_FLASH_GIGADEVICE /* GIGADEVICE */
- {GD25Q64B, 0xc84017, 0x0, 64 * 1024, 128, 0,
SECT_4K},
- {GD25LQ32, 0xc86016, 0x0, 64 * 1024,64, 0,
SECT_4K},
+ {GD25Q64B, 0xc84017, 0x0, 64 * 1024, 128, RD_NORM,
SECT_4K},
+ {GD25LQ32, 0xc86016, 0x0, 64 * 1024,64, RD_NORM,
SECT_4K},
#endif
#ifdef CONFIG_SPI_FLASH_MACRONIX /* MACRONIX */
- {MX25L2006E, 0xc22012, 0x0, 64 * 1024, 4, 0,
0},
- {MX25L4005, 0xc22013, 0x0,
[U-Boot] [PATCH 3/4] spi: sf: Support byte program for sst spi flash
From: Bin Meng bmeng...@gmail.com
Currently if SST flash advertises SST_WP flag in the params table
the word program command (ADh) with auto address increment will be
used for the flash write op. However some SPI controllers do not
support the word program command (like the Intel ICH 7), the byte
programm command (02h) has to be used.
A new TX operation mode SPI_OPM_TX_BP is introduced for such SPI
controller to use byte program op for SST flash.
Signed-off-by: Bin Meng bmeng...@gmail.com
Acked-by: Simon Glass s...@chromium.org
Tested-by: Simon Glass s...@chromium.org
---
drivers/mtd/spi/sf_internal.h | 2 ++
drivers/mtd/spi/sf_ops.c | 31 +++
2 files changed, 33 insertions(+)
diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h
index 7218e69..fb53cb0 100644
--- a/drivers/mtd/spi/sf_internal.h
+++ b/drivers/mtd/spi/sf_internal.h
@@ -110,6 +110,8 @@ enum {
int sst_write_wp(struct spi_flash *flash, u32 offset, size_t len,
const void *buf);
+int sst_write_bp(struct spi_flash *flash, u32 offset, size_t len,
+ const void *buf);
#endif
/**
diff --git a/drivers/mtd/spi/sf_ops.c b/drivers/mtd/spi/sf_ops.c
index 759231f..34bc54e 100644
--- a/drivers/mtd/spi/sf_ops.c
+++ b/drivers/mtd/spi/sf_ops.c
@@ -517,4 +517,35 @@ int sst_write_wp(struct spi_flash *flash, u32 offset,
size_t len,
spi_release_bus(flash-spi);
return ret;
}
+
+int sst_write_bp(struct spi_flash *flash, u32 offset, size_t len,
+ const void *buf)
+{
+ size_t actual;
+ int ret;
+
+ ret = spi_claim_bus(flash-spi);
+ if (ret) {
+ debug(SF: Unable to claim SPI bus\n);
+ return ret;
+ }
+
+ for (actual = 0; actual len; actual++) {
+ ret = sst_byte_write(flash, offset, buf + actual);
+ if (ret) {
+ debug(SF: sst byte program failed\n);
+ break;
+ }
+ offset++;
+ }
+
+ if (!ret)
+ ret = spi_flash_cmd_write_disable(flash);
+
+ debug(SF: sst: program %s %zu bytes @ 0x%zx\n,
+ ret ? failure : success, len, offset - actual);
+
+ spi_release_bus(flash-spi);
+ return ret;
+}
#endif
--
1.9.1
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Re: [U-Boot] [PATCH 0/4] sf: SST changes, Byte program
Hi Bin, On 9 December 2014 at 20:59, Jagannadha Sutradharudu Teki jagannadh.t...@gmail.com wrote: This patch-set added byte program support for sst flashes and some implementation changes in sf to support array slow and byte program specific controllers. Bin Meng (1): spi: sf: Support byte program for sst spi flash Jagannadha Sutradharudu Teki (2): sf: Fix look for the fastest read command sf: Enable byte program support Simon Glass (1): spi: Fix flag collision for SST_WP Please re-base your previous patch-set on top of this series and send the same. drivers/mtd/spi/sf_internal.h | 22 ++--- drivers/mtd/spi/sf_ops.c | 31 + drivers/mtd/spi/sf_params.c | 102 +- drivers/mtd/spi/sf_probe.c| 9 +++- include/spi.h | 1 + 5 files changed, 105 insertions(+), 60 deletions(-) -- 1.9.1 thanks! -- Jagan. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] mxsldr: add status read after firmware upload
Hi, I created a patch for mxsldr, which adds a status read after the firmware upload. This is necessary, if the last instruction is 'hab jump' in the sb file, otherwise it is not working. The sb_loader is doing the same. Best regards, Robert Hodaszi 0001-Add-status-read-after-firmware-download.patch Description: 0001-Add-status-read-after-firmware-download.patch ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v4] Export redesign
On 8 December 2014 at 00:23, Martin Dorwig dor...@tetronik.com wrote: this is an atempt to make the export of functions typesafe. I replaced the jumptable void ** by a struct (jt_funcs) with function pointers. The EXPORT_FUNC macro now has 3 fixed parameters and one variadic parameter The first is the name of the exported function, the rest of the parameters are used to format a functionpointer in the jumptable, the EXPORT_FUNC macros are expanded three times, 1. to declare the members of the struct 2. to initialize the structmember pointers 3. to call the functions in stubs.c Signed-off-by: Martin Dorwig dor...@tetronik.com Acked-by: Simon Glass s...@chromium.org Tested on Pit (ARM-based) and chromebook_link (x86). Tested-by: Simon Glass s...@chromium.org Everything seems to build OK but for two 'exceeding area limit' problems which I assume we can ignore. --- Changes in v4: - add forward decl. for struct spi_slave to export.h Changes in v3: - install_hdlr/free_hdlr must be dummy, since they do not exist - blackfin cpu.c must include exports.h - rebased to master - take CONFIG_DM_SPI into account Changes in v2: - redesign the way functions are exported to standalone applications ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] mtd: nand: mxs: Add support for multiple NAND chips
On Tuesday, December 09, 2014 at 08:20:51 AM, Stefan Roese wrote: On 08.12.2014 23:53, Scott Wood wrote: = nand device Device 0: 2x nand0, sector size 128 KiB Page size 2048 b OOB size 64 b Erase size 131072 b Shouldn't you see Device 0 and Device 1 ? The 2x indicates that there are two identical chips being treated as a single device (chip-numchips). Is that correct ? What if I have two different NAND chips on this controller? Then they need to be represented as separate NAND devices, rather than multiple chips on one device. Gee, I wouldn't have though of that, really ;-) Well, you asked a vague question... So is this patch correct or not ? In all its details? I don't know, as I'm not familiar with the hardware. With regards to the question about non-identical devices, this patch doesn't add support for that. So it's a question of what the requirements are, and whether it's being used in the right circumstances. If you have non-identical NAND chips, make sure CONFIG_SYS_NAND_MAX_CHIPS is 1. Correct. Using CONFIG_SYS_NAND_MAX_CHIPS support identical chips. This is exactly what I need in my case. And is also needed for NAND devices that have multiple NAND chips embedded on one die. You then need this possibility to support multiple chips. Otherwise not the whole device can be accessed. A better question might be, does this approach make sense, versus implementing support for multiple devices? What does Linux support? Linux does it exactly in the same way: [1.089439] nand: device found, Manufacturer ID: 0x2c, Chip ID: 0xdc [1.095864] nand: Micron MT29F4G08ABADAH4 [1.099896] nand: 512MiB, SLC, page size: 2048, OOB size: 64 [1.105871] nand: 2 chips detected ... And exposes those 2 chips as one NAND device. By using this patch we also use the same MTD partitioning in U-Boot and Linux (mtdparts environment). I hope now all is clear. Yes, it is now. Thank you both for the detailed explanation! Acked-by: Marek Vasut ma...@denx.de Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] U-Boot on nyan-big via legacy boot
Hi Simon, On 04/12/14 15:53, Simon Glass wrote: [715.979284 HC 0xd2] This is a reboot command - EC_CMD_REBOOT_EC. I wonder how/why your U-Boot might issue that command? From my investigation, Coreboot is issuing this reboot command, because the Coreboot payload (which in my case is U-Boot) for some reason isn't valid. With CONFIG_PANIC_HANG defined there is no UART output from the EC at all. Is a prepended SPL needed before the U-Boot+DTB payload? When flashing U-Boot from the Chromium OS branch it gives some UART output but freezes because SPI and MMC driver are not working properly (emerge-nyan chromeos-u-boot). Is this the best starting point to develop a working U-Boot? Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] arm:ls1021a:configure ls1021 scfg for QSPI
On 10/29/2014 11:26 PM, Chao Fu wrote: From: Chao Fu b44...@freescale.com Configure ls1021a scfg register for QSPI clock initalization. Signed-off-by: Chao Fu b44...@freescale.com Signed-off-by: Alison Wang alison.w...@freescale.com --- arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 1 + board/freescale/ls1021aqds/ls1021aqds.c | 4 board/freescale/ls1021atwr/ls1021atwr.c | 4 3 files changed, 9 insertions(+) Looks like this patch can be dropped as the change is in http://patchwork.ozlabs.org/patch/418986/. York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [U-boot PATCH] keystone: set default pci mode to root complex
pci ports are used as root complex in Linux. So set this as default
in u-boot for keystone devices
Signed-off-by: Murali Karicheri m-kariche...@ti.com
---
arch/arm/cpu/armv7/keystone/init.c| 33 +
arch/arm/include/asm/arch-keystone/hardware.h |1 +
2 files changed, 34 insertions(+)
diff --git a/arch/arm/cpu/armv7/keystone/init.c
b/arch/arm/cpu/armv7/keystone/init.c
index c2b9478..c96845c 100644
--- a/arch/arm/cpu/armv7/keystone/init.c
+++ b/arch/arm/cpu/armv7/keystone/init.c
@@ -15,6 +15,16 @@
#include asm/arch/hardware.h
#include asm/arch/psc_defs.h
+#define MAX_PCI_PORTS 2
+enum pci_mode {
+ ENDPOINT,
+ LEGACY_ENDPOINT,
+ ROOTCOMPLEX,
+};
+
+#define DEVCFG_MODE_MASK (BIT(2) | BIT(1))
+#define DEVCFG_MODE_SHIFT 1
+
void chip_configuration_unlock(void)
{
__raw_writel(KS2_KICK0_MAGIC, KS2_KICK0);
@@ -68,6 +78,24 @@ void osr_init(void)
}
#endif
+/* Function to set up PCIe mode */
+static void config_pcie_mode(int pcie_port, enum pci_mode mode)
+{
+ u32 val = __raw_readl(KS2_DEVCFG);
+
+ if (pcie_port = MAX_PCI_PORTS)
+ return;
+
+ /**
+* each pci port has two bits for mode and it starts at
+* bit 1. So use port number to get the right bit position.
+*/
+ pcie_port = 1;
+ val = ~(DEVCFG_MODE_MASK pcie_port);
+ val |= ((mode DEVCFG_MODE_SHIFT) pcie_port);
+ __raw_writel(val, KS2_DEVCFG);
+}
+
int arch_cpu_init(void)
{
chip_configuration_unlock();
@@ -77,8 +105,13 @@ int arch_cpu_init(void)
msmc_share_all_segments(KS2_MSMC_SEGMENT_NETCP);
msmc_share_all_segments(KS2_MSMC_SEGMENT_QM_PDSP);
msmc_share_all_segments(KS2_MSMC_SEGMENT_PCIE0);
+
+ /* Initialize the PCIe-0 to work as Root Complex */
+ config_pcie_mode(0, ROOTCOMPLEX);
#if defined(CONFIG_SOC_K2E) || defined(CONFIG_SOC_K2L)
msmc_share_all_segments(KS2_MSMC_SEGMENT_PCIE1);
+ /* Initialize the PCIe-1 to work as Root Complex */
+ config_pcie_mode(1, ROOTCOMPLEX);
#endif
#ifdef CONFIG_SOC_K2L
osr_init();
diff --git a/arch/arm/include/asm/arch-keystone/hardware.h
b/arch/arm/include/asm/arch-keystone/hardware.h
index be22bdb..16cbcee 100644
--- a/arch/arm/include/asm/arch-keystone/hardware.h
+++ b/arch/arm/include/asm/arch-keystone/hardware.h
@@ -144,6 +144,7 @@ typedef volatile unsigned int *dv_reg_p;
#define KS2_DEVICE_STATE_CTRL_BASE 0x0262
#define KS2_JTAG_ID_REG(KS2_DEVICE_STATE_CTRL_BASE +
0x18)
#define KS2_DEVSTAT(KS2_DEVICE_STATE_CTRL_BASE + 0x20)
+#define KS2_DEVCFG (KS2_DEVICE_STATE_CTRL_BASE + 0x14c)
/* PSC */
#define KS2_PSC_BASE 0x0235
--
1.7.9.5
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Re: [U-Boot] [PATCH v2] bcm281xx: add support for USB OTG clock
On 14-12-07 05:30 PM, Michael Trimarchi wrote:
Hi
Il 07/dic/2014 02:24 Steve Rae s...@broadcom.com ha scritto:
enable this clock with the following:
clk_usb_otg_enable((void *)HSOTG_BASE_ADDR)
Signed-off-by: Steve Rae s...@broadcom.com
---
Changes in v2:
removed unrelated changes as per Felipe Balbi ba...@ti.com
arch/arm/cpu/armv7/bcm281xx/Makefile| 1 +
arch/arm/cpu/armv7/bcm281xx/clk-bcm281xx.c | 16 +++
arch/arm/cpu/armv7/bcm281xx/clk-usb-otg.c | 32
+
arch/arm/cpu/armv7/kona-common/clk-stubs.c | 5 +
arch/arm/include/asm/arch-bcm281xx/sysmap.h | 2 ++
arch/arm/include/asm/kona-common/clk.h | 1 +
6 files changed, 57 insertions(+)
create mode 100644 arch/arm/cpu/armv7/bcm281xx/clk-usb-otg.c
diff --git a/arch/arm/cpu/armv7/bcm281xx/Makefile
b/arch/arm/cpu/armv7/bcm281xx/Makefile
index bd867a2..f24aeb3 100644
--- a/arch/arm/cpu/armv7/bcm281xx/Makefile
+++ b/arch/arm/cpu/armv7/bcm281xx/Makefile
@@ -10,3 +10,4 @@ obj-y += clk-bcm281xx.o
obj-y += clk-sdio.o
obj-y += clk-bsc.o
obj-$(CONFIG_BCM_SF2_ETH) += clk-eth.o
+obj-y += clk-usb-otg.o
diff --git a/arch/arm/cpu/armv7/bcm281xx/clk-bcm281xx.c
b/arch/arm/cpu/armv7/bcm281xx/clk-bcm281xx.c
index d16b99f..7e25255 100644
--- a/arch/arm/cpu/armv7/bcm281xx/clk-bcm281xx.c
+++ b/arch/arm/cpu/armv7/bcm281xx/clk-bcm281xx.c
@@ -209,6 +209,10 @@ static struct peri_clk_data sdio4_sleep_data = {
.gate = SW_ONLY_GATE(0x0360, 20, 4),
};
+static struct bus_clk_data usb_otg_ahb_data = {
+ .gate = HW_SW_GATE_AUTO(0x0348, 16, 0, 1),
+};
+
static struct bus_clk_data sdio1_ahb_data = {
.gate = HW_SW_GATE_AUTO(0x0358, 16, 0, 1),
};
@@ -331,6 +335,17 @@ static struct ccu_clock esub_ccu_clk = {
*/
/* KPM bus clocks */
+static struct bus_clock usb_otg_ahb_clk = {
+ .clk = {
+ .name = usb_otg_ahb_clk,
+ .parent = kpm_ccu_clk.clk,
+ .ops = bus_clk_ops,
+ .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
+ },
+ .freq_tbl = master_ahb_freq_tbl,
+ .data = usb_otg_ahb_data,
+};
+
static struct bus_clock sdio1_ahb_clk = {
.clk = {
.name = sdio1_ahb_clk,
@@ -541,6 +556,7 @@ struct clk_lookup arch_clk_tbl[] = {
CLK_LK(bsc2),
CLK_LK(bsc3),
/* Bus clocks */
+ CLK_LK(usb_otg_ahb),
CLK_LK(sdio1_ahb),
CLK_LK(sdio2_ahb),
CLK_LK(sdio3_ahb),
diff --git a/arch/arm/cpu/armv7/bcm281xx/clk-usb-otg.c
b/arch/arm/cpu/armv7/bcm281xx/clk-usb-otg.c
new file mode 100644
index 000..b7efd8e
--- /dev/null
+++ b/arch/arm/cpu/armv7/bcm281xx/clk-usb-otg.c
@@ -0,0 +1,32 @@
+/*
+ * Copyright 2014 Broadcom Corporation.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include asm/errno.h
+#include asm/arch/sysmap.h
+#include clk-core.h
+
+/* Enable appropriate clocks for the USB OTG port */
+int clk_usb_otg_enable(void *base)
+{
+ int ret;
+ char *ahbstr;
+
+ switch ((u32) base) {
+ case HSOTG_BASE_ADDR:
+ ahbstr = usb_otg_ahb_clk;
+ break;
+ default:
+ printf(%s: base 0x%p not found\n, __func__, base);
+ return -EINVAL;
+ }
+
+ ret = clk_get_and_enable(ahbstr);
return clk_get. ?
Thanks - see [v3]
+ if (ret)
+ return ret;
+
+ return 0;
+}
What is usage of this file?
Why don't enable with the string?
this USB OTG clk is enabled by the fastboot initialization code -
which is in a parallel set of patches.
(I'm trying to not submit an overwhelming set of changes)
Thanks, Steve
Michael
diff --git a/arch/arm/cpu/armv7/kona-common/clk-stubs.c
b/arch/arm/cpu/armv7/kona-common/clk-stubs.c
index 338e0e4..fa10802 100644
--- a/arch/arm/cpu/armv7/kona-common/clk-stubs.c
+++ b/arch/arm/cpu/armv7/kona-common/clk-stubs.c
@@ -19,3 +19,8 @@ int __weak clk_bsc_enable(void *base, u32 rate, u32
*actual_ratep)
{
return 0;
}
+
+int __weak clk_usb_otg_enable(void *base)
+{
+ return 0;
+}
diff --git a/arch/arm/include/asm/arch-bcm281xx/sysmap.h
b/arch/arm/include/asm/arch-bcm281xx/sysmap.h
index 350e7f6..93ebf34 100644
--- a/arch/arm/include/asm/arch-bcm281xx/sysmap.h
+++ b/arch/arm/include/asm/arch-bcm281xx/sysmap.h
@@ -13,6 +13,8 @@
#define ESUB_CLK_BASE_ADDR 0x3800
#define ESW_CONTRL_BASE_ADDR 0x3820
#define GPIO2_BASE_ADDR0x35003000
+#define HSOTG_BASE_ADDR0x3f12
+#define HSOTG_CTRL_BASE_ADDR 0x3f13
#define KONA_MST_CLK_BASE_ADDR 0x3f001000
#define KONA_SLV_CLK_BASE_ADDR 0x3e011000
#define PMU_BSC_BASE_ADDR 0x3500d000
diff --git a/arch/arm/include/asm/kona-common/clk.h
b/arch/arm/include/asm/kona-common/clk.h
index 2c7e829..a5e2fd9 100644
--- a/arch/arm/include/asm/kona-common/clk.h
+++ b/arch/arm/include/asm/kona-common/clk.h
@@ -25,5
[U-Boot] [PATCH v3] bcm281xx: add support for USB OTG clock
enable this clock with the following:
clk_usb_otg_enable((void *)HSOTG_BASE_ADDR)
Signed-off-by: Steve Rae s...@broadcom.com
---
Changes in v3:
clean up return statement as per Michael Trimarchi
mich...@amarulasolutions.com
Changes in v2:
removed unrelated changes as per Felipe Balbi ba...@ti.com
arch/arm/cpu/armv7/bcm281xx/Makefile| 1 +
arch/arm/cpu/armv7/bcm281xx/clk-bcm281xx.c | 16
arch/arm/cpu/armv7/bcm281xx/clk-usb-otg.c | 27 +++
arch/arm/cpu/armv7/kona-common/clk-stubs.c | 5 +
arch/arm/include/asm/arch-bcm281xx/sysmap.h | 2 ++
arch/arm/include/asm/kona-common/clk.h | 1 +
6 files changed, 52 insertions(+)
create mode 100644 arch/arm/cpu/armv7/bcm281xx/clk-usb-otg.c
diff --git a/arch/arm/cpu/armv7/bcm281xx/Makefile
b/arch/arm/cpu/armv7/bcm281xx/Makefile
index bd867a2..f24aeb3 100644
--- a/arch/arm/cpu/armv7/bcm281xx/Makefile
+++ b/arch/arm/cpu/armv7/bcm281xx/Makefile
@@ -10,3 +10,4 @@ obj-y += clk-bcm281xx.o
obj-y += clk-sdio.o
obj-y += clk-bsc.o
obj-$(CONFIG_BCM_SF2_ETH) += clk-eth.o
+obj-y += clk-usb-otg.o
diff --git a/arch/arm/cpu/armv7/bcm281xx/clk-bcm281xx.c
b/arch/arm/cpu/armv7/bcm281xx/clk-bcm281xx.c
index d16b99f..7e25255 100644
--- a/arch/arm/cpu/armv7/bcm281xx/clk-bcm281xx.c
+++ b/arch/arm/cpu/armv7/bcm281xx/clk-bcm281xx.c
@@ -209,6 +209,10 @@ static struct peri_clk_data sdio4_sleep_data = {
.gate = SW_ONLY_GATE(0x0360, 20, 4),
};
+static struct bus_clk_data usb_otg_ahb_data = {
+ .gate = HW_SW_GATE_AUTO(0x0348, 16, 0, 1),
+};
+
static struct bus_clk_data sdio1_ahb_data = {
.gate = HW_SW_GATE_AUTO(0x0358, 16, 0, 1),
};
@@ -331,6 +335,17 @@ static struct ccu_clock esub_ccu_clk = {
*/
/* KPM bus clocks */
+static struct bus_clock usb_otg_ahb_clk = {
+ .clk = {
+ .name = usb_otg_ahb_clk,
+ .parent = kpm_ccu_clk.clk,
+ .ops = bus_clk_ops,
+ .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
+ },
+ .freq_tbl = master_ahb_freq_tbl,
+ .data = usb_otg_ahb_data,
+};
+
static struct bus_clock sdio1_ahb_clk = {
.clk = {
.name = sdio1_ahb_clk,
@@ -541,6 +556,7 @@ struct clk_lookup arch_clk_tbl[] = {
CLK_LK(bsc2),
CLK_LK(bsc3),
/* Bus clocks */
+ CLK_LK(usb_otg_ahb),
CLK_LK(sdio1_ahb),
CLK_LK(sdio2_ahb),
CLK_LK(sdio3_ahb),
diff --git a/arch/arm/cpu/armv7/bcm281xx/clk-usb-otg.c
b/arch/arm/cpu/armv7/bcm281xx/clk-usb-otg.c
new file mode 100644
index 000..1d7c5af
--- /dev/null
+++ b/arch/arm/cpu/armv7/bcm281xx/clk-usb-otg.c
@@ -0,0 +1,27 @@
+/*
+ * Copyright 2014 Broadcom Corporation.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include asm/errno.h
+#include asm/arch/sysmap.h
+#include clk-core.h
+
+/* Enable appropriate clocks for the USB OTG port */
+int clk_usb_otg_enable(void *base)
+{
+ char *ahbstr;
+
+ switch ((u32) base) {
+ case HSOTG_BASE_ADDR:
+ ahbstr = usb_otg_ahb_clk;
+ break;
+ default:
+ printf(%s: base 0x%p not found\n, __func__, base);
+ return -EINVAL;
+ }
+
+ return clk_get_and_enable(ahbstr);
+}
diff --git a/arch/arm/cpu/armv7/kona-common/clk-stubs.c
b/arch/arm/cpu/armv7/kona-common/clk-stubs.c
index 338e0e4..fa10802 100644
--- a/arch/arm/cpu/armv7/kona-common/clk-stubs.c
+++ b/arch/arm/cpu/armv7/kona-common/clk-stubs.c
@@ -19,3 +19,8 @@ int __weak clk_bsc_enable(void *base, u32 rate, u32
*actual_ratep)
{
return 0;
}
+
+int __weak clk_usb_otg_enable(void *base)
+{
+ return 0;
+}
diff --git a/arch/arm/include/asm/arch-bcm281xx/sysmap.h
b/arch/arm/include/asm/arch-bcm281xx/sysmap.h
index 350e7f6..93ebf34 100644
--- a/arch/arm/include/asm/arch-bcm281xx/sysmap.h
+++ b/arch/arm/include/asm/arch-bcm281xx/sysmap.h
@@ -13,6 +13,8 @@
#define ESUB_CLK_BASE_ADDR 0x3800
#define ESW_CONTRL_BASE_ADDR 0x3820
#define GPIO2_BASE_ADDR0x35003000
+#define HSOTG_BASE_ADDR0x3f12
+#define HSOTG_CTRL_BASE_ADDR 0x3f13
#define KONA_MST_CLK_BASE_ADDR 0x3f001000
#define KONA_SLV_CLK_BASE_ADDR 0x3e011000
#define PMU_BSC_BASE_ADDR 0x3500d000
diff --git a/arch/arm/include/asm/kona-common/clk.h
b/arch/arm/include/asm/kona-common/clk.h
index 2c7e829..a5e2fd9 100644
--- a/arch/arm/include/asm/kona-common/clk.h
+++ b/arch/arm/include/asm/kona-common/clk.h
@@ -25,5 +25,6 @@ int clk_set_parent(struct clk *clk, struct clk *parent);
struct clk *clk_get_parent(struct clk *clk);
int clk_sdio_enable(void *base, u32 rate, u32 *actual_ratep);
int clk_bsc_enable(void *base);
+int clk_usb_otg_enable(void *base);
#endif
--
1.8.5
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Re: [U-Boot] [U-Boot,v5,2/3] stv0991: enable ethernet support
On Tue, Nov 18, 2014 at 10:42:23AM -0800, Vikas Manocha wrote: Signed-off-by: Vikas Manocha vikas.mano...@st.com Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-Boot, v5, 1/3] stv0991: Add basic stv0991 architecture support
On Tue, Nov 18, 2014 at 10:42:22AM -0800, Vikas Manocha wrote: stv0991 architecture support added. It contains the support for following blocks - Timer - uart Signed-off-by: Vikas Manocha vikas.mano...@st.com Applied to u-boot/master after adding a hunk to arch/arm/cpu/armv7/Makefile, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-Boot,2/2] dm: stv0991: Move serial to driver model
On Mon, Dec 01, 2014 at 12:27:54PM -0800, Vikas Manocha wrote: Signed-off-by: Vikas Manocha vikas.mano...@st.com Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-Boot, v5, 3/3] stv0991: enable default and misc command configs
On Tue, Nov 18, 2014 at 10:42:24AM -0800, Vikas Manocha wrote: Signed-off-by: Vikas Manocha vikas.mano...@st.com Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-Boot, 1/2] stv0991: increase the initial ram size config
On Mon, Dec 01, 2014 at 12:27:53PM -0800, Vikas Manocha wrote: It is done to make space available for driver model memory. Signed-off-by: Vikas Manocha vikas.mano...@st.com Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] compiling error for rc3
Tom, I found a compiling error for board mx53loco, undefined reference to `disable_sata_clock'. Not sure if this is related to recent patches from Nikita. York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3] bcm281xx: add support for USB OTG clock
On Tue, Dec 09, 2014 at 11:40:11AM -0800, Steve Rae wrote:
enable this clock with the following:
clk_usb_otg_enable((void *)HSOTG_BASE_ADDR)
Signed-off-by: Steve Rae s...@broadcom.com
my reviewed by remains :-)
Reviewed-by: Felipe Balbi ba...@ti.com
---
Changes in v3:
clean up return statement as per Michael Trimarchi
mich...@amarulasolutions.com
Changes in v2:
removed unrelated changes as per Felipe Balbi ba...@ti.com
arch/arm/cpu/armv7/bcm281xx/Makefile| 1 +
arch/arm/cpu/armv7/bcm281xx/clk-bcm281xx.c | 16
arch/arm/cpu/armv7/bcm281xx/clk-usb-otg.c | 27 +++
arch/arm/cpu/armv7/kona-common/clk-stubs.c | 5 +
arch/arm/include/asm/arch-bcm281xx/sysmap.h | 2 ++
arch/arm/include/asm/kona-common/clk.h | 1 +
6 files changed, 52 insertions(+)
create mode 100644 arch/arm/cpu/armv7/bcm281xx/clk-usb-otg.c
diff --git a/arch/arm/cpu/armv7/bcm281xx/Makefile
b/arch/arm/cpu/armv7/bcm281xx/Makefile
index bd867a2..f24aeb3 100644
--- a/arch/arm/cpu/armv7/bcm281xx/Makefile
+++ b/arch/arm/cpu/armv7/bcm281xx/Makefile
@@ -10,3 +10,4 @@ obj-y += clk-bcm281xx.o
obj-y+= clk-sdio.o
obj-y+= clk-bsc.o
obj-$(CONFIG_BCM_SF2_ETH) += clk-eth.o
+obj-y+= clk-usb-otg.o
diff --git a/arch/arm/cpu/armv7/bcm281xx/clk-bcm281xx.c
b/arch/arm/cpu/armv7/bcm281xx/clk-bcm281xx.c
index d16b99f..7e25255 100644
--- a/arch/arm/cpu/armv7/bcm281xx/clk-bcm281xx.c
+++ b/arch/arm/cpu/armv7/bcm281xx/clk-bcm281xx.c
@@ -209,6 +209,10 @@ static struct peri_clk_data sdio4_sleep_data = {
.gate = SW_ONLY_GATE(0x0360, 20, 4),
};
+static struct bus_clk_data usb_otg_ahb_data = {
+ .gate = HW_SW_GATE_AUTO(0x0348, 16, 0, 1),
+};
+
static struct bus_clk_data sdio1_ahb_data = {
.gate = HW_SW_GATE_AUTO(0x0358, 16, 0, 1),
};
@@ -331,6 +335,17 @@ static struct ccu_clock esub_ccu_clk = {
*/
/* KPM bus clocks */
+static struct bus_clock usb_otg_ahb_clk = {
+ .clk = {
+ .name = usb_otg_ahb_clk,
+ .parent = kpm_ccu_clk.clk,
+ .ops = bus_clk_ops,
+ .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
+ },
+ .freq_tbl = master_ahb_freq_tbl,
+ .data = usb_otg_ahb_data,
+};
+
static struct bus_clock sdio1_ahb_clk = {
.clk = {
.name = sdio1_ahb_clk,
@@ -541,6 +556,7 @@ struct clk_lookup arch_clk_tbl[] = {
CLK_LK(bsc2),
CLK_LK(bsc3),
/* Bus clocks */
+ CLK_LK(usb_otg_ahb),
CLK_LK(sdio1_ahb),
CLK_LK(sdio2_ahb),
CLK_LK(sdio3_ahb),
diff --git a/arch/arm/cpu/armv7/bcm281xx/clk-usb-otg.c
b/arch/arm/cpu/armv7/bcm281xx/clk-usb-otg.c
new file mode 100644
index 000..1d7c5af
--- /dev/null
+++ b/arch/arm/cpu/armv7/bcm281xx/clk-usb-otg.c
@@ -0,0 +1,27 @@
+/*
+ * Copyright 2014 Broadcom Corporation.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include common.h
+#include asm/errno.h
+#include asm/arch/sysmap.h
+#include clk-core.h
+
+/* Enable appropriate clocks for the USB OTG port */
+int clk_usb_otg_enable(void *base)
+{
+ char *ahbstr;
+
+ switch ((u32) base) {
+ case HSOTG_BASE_ADDR:
+ ahbstr = usb_otg_ahb_clk;
+ break;
+ default:
+ printf(%s: base 0x%p not found\n, __func__, base);
+ return -EINVAL;
+ }
+
+ return clk_get_and_enable(ahbstr);
+}
diff --git a/arch/arm/cpu/armv7/kona-common/clk-stubs.c
b/arch/arm/cpu/armv7/kona-common/clk-stubs.c
index 338e0e4..fa10802 100644
--- a/arch/arm/cpu/armv7/kona-common/clk-stubs.c
+++ b/arch/arm/cpu/armv7/kona-common/clk-stubs.c
@@ -19,3 +19,8 @@ int __weak clk_bsc_enable(void *base, u32 rate, u32
*actual_ratep)
{
return 0;
}
+
+int __weak clk_usb_otg_enable(void *base)
+{
+ return 0;
+}
diff --git a/arch/arm/include/asm/arch-bcm281xx/sysmap.h
b/arch/arm/include/asm/arch-bcm281xx/sysmap.h
index 350e7f6..93ebf34 100644
--- a/arch/arm/include/asm/arch-bcm281xx/sysmap.h
+++ b/arch/arm/include/asm/arch-bcm281xx/sysmap.h
@@ -13,6 +13,8 @@
#define ESUB_CLK_BASE_ADDR 0x3800
#define ESW_CONTRL_BASE_ADDR 0x3820
#define GPIO2_BASE_ADDR 0x35003000
+#define HSOTG_BASE_ADDR 0x3f12
+#define HSOTG_CTRL_BASE_ADDR 0x3f13
#define KONA_MST_CLK_BASE_ADDR 0x3f001000
#define KONA_SLV_CLK_BASE_ADDR 0x3e011000
#define PMU_BSC_BASE_ADDR0x3500d000
diff --git a/arch/arm/include/asm/kona-common/clk.h
b/arch/arm/include/asm/kona-common/clk.h
index 2c7e829..a5e2fd9 100644
--- a/arch/arm/include/asm/kona-common/clk.h
+++ b/arch/arm/include/asm/kona-common/clk.h
@@ -25,5 +25,6 @@ int clk_set_parent(struct clk *clk, struct clk *parent);
struct clk *clk_get_parent(struct clk *clk);
int clk_sdio_enable(void *base, u32 rate, u32 *actual_ratep);
int clk_bsc_enable(void *base);
+int
Re: [U-Boot] ti, am3517: errata 430973 workaround
On Mon, Dec 8, 2014 at 4:19 PM, Jeroen Hofstee jer...@myspectrum.nl wrote: Hi, A while ago [1], a RFC was posted to disable workaround for besides others, errata 430973. It is a bit unclear to me which revision actually need this workaround, but as suggested in [2] also enabling this workaround in Linux seem to make some weird problems go away in linux (signal 4, bad instruction, 11 segfaults etc). As said, I am a bit in doubt why this works. The board in question is a tam3517 derived one: cat /proc/cpuinfo Processor: ARMv7 Processor rev 7 (v7l) BogoMIPS: 397.57 Features: swp half thumb fastmult vfp edsp neon vfpv3 tls CPU implementer: 0x41 CPU architecture: 7 CPU variant: 0x1 CPU part: 0xc08 CPU revision: 7 Which makes this a r1p7 I assume, and hence the workaround of linux, CONFIG_ARM_ERRATA_430973, This option enables the workaround for the 430973 Cortex-A8 (r1p0..r1p2) erratum, should not be needed it seems. Digging thru my old beagle notes 430973 is also needed for r1p3 (dm3730/bb-xm), so that config option was never updated since the errata was first discovered in r1p2 devices.. Fixed in r2p1 sounds about right, as i know for sure it works fine in 'r3p2' (am335x/bbb) Regards, -- Robert Nelson http://www.rcn-ee.com/ ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] common/board_f.c: fix compile error when tracing disabled
From: Kevin Hilman khil...@linaro.org
When CONFIG_TRACE is disabled, linking fails with:
common/built-in.o:(.data.init_sequence_f+0x8): undefined reference to
`trace_early_init'
To fix, wrap the call to trace_early_init() with #ifdef CONFIG_TRACE.
Cc: Simon Glass s...@chromium.org
Cc: Tom Rini tr...@ti.com
Signed-off-by: Kevin Hilman khil...@linaro.org
---
Applies to v2015.01-rc3
common/board_f.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/common/board_f.c b/common/board_f.c
index 98c9c728ce73..cfd77f865361 100644
--- a/common/board_f.c
+++ b/common/board_f.c
@@ -813,7 +813,9 @@ static init_fnc_t init_sequence_f[] = {
#endif
setup_mon_len,
setup_fdt,
+#ifdef CONFIG_TRACE
trace_early_init,
+#endif
initf_malloc,
#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
/* TODO: can this go into arch_cpu_init()? */
--
2.1.3
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Re: [U-Boot] [PATCH v11 0/3] Adds support for Exynos5422 odroid xu3 board
Hyungwon Hwang human.hw...@samsung.com writes: This is v11 of the patchset adding support Odroud XU3 board. I finally got around to testing this on top of v2015.01-rc3 on my XU3. As I mentioned earlier, I had to enable the USB and networking options so I could dhcp/tftp but after that it works for me. Feel free to add: Tested-by: Kevin Hilman khil...@linaro.org [...] Note: If you use micro SD card for your test you have to apply the below patch additionally. This patch is needed, because micro sd card is recognized as MMC1 instead of MMC0. Additional work is needed to make it work regardless of device id. FYI, with or without your MMC ID patch, I wasn't able to save the environment to the SD card I'm booting from: ODROID-XU3 # saveenv Saving Environment to MMC... dwmci_send_cmd: Timeout. MMC init failed Kevin ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v9 2/2] Odroid-XU3: Add documentation for Odroid-XU3
Simon Glass s...@chromium.org writes: On 8 December 2014 at 18:27, Kevin Hilman khil...@kernel.org wrote: [...] So is secure-mode enabled before BL2 is started? Or do you mean BL2 is where secure-mode is enabled? If it's done in BL2, and if the hardkernel folks are willing to sign BL2 images (which I gathered from discussions elsewhere in this series) then it seems possible to turn off secure-mode. Yes it is possible - and easy - to do in BL2 / U-Boot SPL. This is what the Chromebooks do. OK, good. So I went to look in the u-boot-samsung repo and didn't see the code for the SPL there. Is the BL2 source (which I understood to be u-boot SPL) in some other repo? It's in mainline U-Boot so no particular need to go to the Samsung tree. I went to the samsung tree since the cover letter for this series pointed me there. But I just tried the latest version of this series (v11) using mainlin u-boot. Thanks for the pointer. See arch/arm/cpu/armv7/exynos/spl_boot.c and tzpc.c for the TrustZone stuff. OK, thanks. Any pointers on how to get this building with mainline u-boot? Just adding CONFIG_SPL to odroid_xu3.h doesn't seem to work (compile errors.) I'm quite comfortable in the kernel, but I'm not very familiar with u-boot, especially SPL. It takes us back to the 1960s where we sent off our code at night to run it :-) I think the best bet is the current effort to mainline the rest of the Chromebook code then try to build it for XU3. What's the status of that effort? Coming along but the big/little support is still not there. The display works and most core peripherals. Needs more SPL work. OK, I'll be glad to be a beta tester if/when you get to that point. Thanks, Kevin ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v9 2/2] Odroid-XU3: Add documentation for Odroid-XU3
Hi Kevin, On 9 December 2014 at 17:03, Kevin Hilman khil...@kernel.org wrote: Simon Glass s...@chromium.org writes: On 8 December 2014 at 18:27, Kevin Hilman khil...@kernel.org wrote: [...] So is secure-mode enabled before BL2 is started? Or do you mean BL2 is where secure-mode is enabled? If it's done in BL2, and if the hardkernel folks are willing to sign BL2 images (which I gathered from discussions elsewhere in this series) then it seems possible to turn off secure-mode. Yes it is possible - and easy - to do in BL2 / U-Boot SPL. This is what the Chromebooks do. OK, good. So I went to look in the u-boot-samsung repo and didn't see the code for the SPL there. Is the BL2 source (which I understood to be u-boot SPL) in some other repo? It's in mainline U-Boot so no particular need to go to the Samsung tree. I went to the samsung tree since the cover letter for this series pointed me there. But I just tried the latest version of this series (v11) using mainlin u-boot. Thanks for the pointer. See arch/arm/cpu/armv7/exynos/spl_boot.c and tzpc.c for the TrustZone stuff. OK, thanks. Any pointers on how to get this building with mainline u-boot? Just adding CONFIG_SPL to odroid_xu3.h doesn't seem to work (compile errors.) I'm quite comfortable in the kernel, but I'm not very familiar with u-boot, especially SPL. It's normally automatic unless some special disabling was done - see spl/u-boot-spl.bin in the output. You need to sign it though :-( It takes us back to the 1960s where we sent off our code at night to run it :-) I think the best bet is the current effort to mainline the rest of the Chromebook code then try to build it for XU3. What's the status of that effort? Coming along but the big/little support is still not there. The display works and most core peripherals. Needs more SPL work. OK, I'll be glad to be a beta tester if/when you get to that point. Thanks, Kevin Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Problem converting da850evm to generic board and use libfdt
On Wed, 2014-12-03 at 14:20 -0800, Simon Glass wrote:
Hi Peter,
On 3 December 2014 at 13:53, Peter Howard p...@northern-ridge.com.au wrote:
On Wed, 2014-12-03 at 06:38 -0700, Simon Glass wrote:
Hi Peter,
On 2 December 2014 at 14:59, Peter Howard p...@northern-ridge.com.au
wrote:
I'm trying to make two changes to building u-boot for the da850evm.
* Use the generic board code to get rid of the warning, and
* Enable libfdt to allow booting of linux with a standalone dtb
image.
The first part appears to be simple. Just adding
#define CONFIG_SYS_GENERIC_BOARD
in include/configs/da850evm.h works with no obvious side-effects.
However, adding
#define CONFIG_OF_LIBFDT
is a different story. It appears to introduce memory corruption when
loading the environment. On first boot it gives the bad CRC! warning
and uses the default environment. If you *don't* save the environment
you can boot fine (including manual editing of the environment). However
if you save the environment via saveenv bad things happen on the next
boot. An example log:
U-Boot SPL 2015.01-rc1 (Nov 27 2014 - 14:30:26)
U-Boot 2015.01-rc1 (Nov 27 2014 - 14:30:26)
I2C: ready
DRAM: 64 MiB
WARNING: Caches not enabled
MMC: davinci: 0
SF: Detected M25P64 with page size 256 Bytes, erase size 64 KiB, total 8
MiB
In:serial
Out: serial
Err: serial
SF: Detected M25P64 with page size 256 Bytes, erase size 64 KiB, total 8
MiB
Warning: Invalid MAC address read from SPI flash
Net: DaVinci-EMAC
Error: DaVinci-EMAC address not set.
U-Boot help
data abort
pc : [c108ffd8] lr : [c10900b4]
sp : c3e5f838 ip : fp : c3e5fda4
r10: c10b1f28 r9 : c3e5ff08 r8 : 000e
r7 : c10b22c4 r6 : c10aa2a0 r5 : r4 : 001b
r3 : c10b8f70 r2 : 0001 r1 : c3e5f840 r0 :
Flags: Nzcv IRQs off FIQs off Mode SVC_32
Resetting CPU ...
If I rebuild with CONFIG_OF_LIBFDT removed again from da850evm.h the
problem disappears. And you can see that the saveenv worked (i.e. the
environment is what was saved before the reboot and data abort).
I've traced the problem as far as the inline version of console_puts()
in common/console.c. The table dispatch there and the fact that the
problem appears only when you load the environment makes me think it's
memory corruption.
Note: if you do *not* specify CONFIG_SYS_GENERIC_BOARD you still get the
data abort, however it takes a bit more effort to trigger (like actually
looking at the environment :-) )
(Note: This is building against the u-boot-2015.01-rc1 tree)
Suggestions?
In case it helps, I got the same symptom (help crashes) and it was due
to BSS not being cleared. Stefan (on cc) found this problem - he said
something to do with GDT calculation or handling. However it is just a
guess and probably has nothing to do with your issue.
I may be missing something, but the GDT appears to be x86-specific
whereas I'm building for ARMv5.
OK for some reason I thought this was PPC!
Maybe you can find your pc in System.map and work out where it is
going wrong? Are you hitting some image size limit?
pc : [c108ffd8]
Sorry, been distracted on other stuff for a few days.
First, I now understand the global descriptor a bit better. For ARMv5
It's stored in r9 and still looks sane. The relevant info:
(gdb) print/x *((gd_t *)$r9)
$1 = {bd = 0xc3e5ffb0, flags = 0x183, baudrate = 0x1c200, cpu_clk = 0x0,
bus_clk = 0x0, pci_clk = 0x0, mem_clk = 0x0, have_console = 0x1,
env_addr = 0xc10a8fcc, env_valid = 0x1, ram_top = 0xc400,
relocaddr = 0xc3f8, ram_size = 0x400, mon_len = 0x6ffb0,
irq_sp = 0xc3e5fef0, start_addr_sp = 0xc3e5fee0, reloc_off = 0x2f0,
new_gd = 0xc3e5ff08, fdt_blob = 0x0, new_fdt = 0x0, fdt_size = 0x0,
jt = 0xc3e601c0, env_buf = {0x31, 0x31, 0x35, 0x32, 0x30, 0x30,
0x0 repeats 26 times}, cur_i2c_bus = 0x0, timebase_h = 0x0,
timebase_l = 0x0, arch = {timer_rate_hz = 0x16e360, tbu = 0x0,
tbl = 0x4cc62, lastinc = 0x0, timer_reset_value = 0x0,
tlb_addr = 0xc3ff, tlb_size = 0x4000}}
The pc is definitely bogus. The reloc address is 0xc3f8 whereas
that would be a pre-reloc address (starting at 0xc108). And it's
definitely relocated by the time of failure. The only other bit of
information I have right now is that adding CONFIG_OF_LIBFDT drops the
reloc address from 0xc3f85000 to 0xc3f8.
Don't know if any of that gives additional insight. Meanwhile I
continue tracing.
--
Peter Howard p...@northern-ridge.com.au
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Re: [U-Boot] Problem converting da850evm to generic board and use libfdt
Hi Peter,
On 9 December 2014 at 17:13, Peter Howard p...@northern-ridge.com.au wrote:
On Wed, 2014-12-03 at 14:20 -0800, Simon Glass wrote:
Hi Peter,
On 3 December 2014 at 13:53, Peter Howard p...@northern-ridge.com.au
wrote:
On Wed, 2014-12-03 at 06:38 -0700, Simon Glass wrote:
Hi Peter,
On 2 December 2014 at 14:59, Peter Howard p...@northern-ridge.com.au
wrote:
I'm trying to make two changes to building u-boot for the da850evm.
* Use the generic board code to get rid of the warning, and
* Enable libfdt to allow booting of linux with a standalone dtb
image.
The first part appears to be simple. Just adding
#define CONFIG_SYS_GENERIC_BOARD
in include/configs/da850evm.h works with no obvious side-effects.
However, adding
#define CONFIG_OF_LIBFDT
is a different story. It appears to introduce memory corruption when
loading the environment. On first boot it gives the bad CRC! warning
and uses the default environment. If you *don't* save the environment
you can boot fine (including manual editing of the environment).
However
if you save the environment via saveenv bad things happen on the next
boot. An example log:
U-Boot SPL 2015.01-rc1 (Nov 27 2014 - 14:30:26)
U-Boot 2015.01-rc1 (Nov 27 2014 - 14:30:26)
I2C: ready
DRAM: 64 MiB
WARNING: Caches not enabled
MMC: davinci: 0
SF: Detected M25P64 with page size 256 Bytes, erase size 64 KiB, total
8 MiB
In:serial
Out: serial
Err: serial
SF: Detected M25P64 with page size 256 Bytes, erase size 64 KiB, total
8 MiB
Warning: Invalid MAC address read from SPI flash
Net: DaVinci-EMAC
Error: DaVinci-EMAC address not set.
U-Boot help
data abort
pc : [c108ffd8] lr : [c10900b4]
sp : c3e5f838 ip : fp : c3e5fda4
r10: c10b1f28 r9 : c3e5ff08 r8 : 000e
r7 : c10b22c4 r6 : c10aa2a0 r5 : r4 : 001b
r3 : c10b8f70 r2 : 0001 r1 : c3e5f840 r0 :
Flags: Nzcv IRQs off FIQs off Mode SVC_32
Resetting CPU ...
If I rebuild with CONFIG_OF_LIBFDT removed again from da850evm.h the
problem disappears. And you can see that the saveenv worked (i.e. the
environment is what was saved before the reboot and data abort).
I've traced the problem as far as the inline version of console_puts()
in common/console.c. The table dispatch there and the fact that the
problem appears only when you load the environment makes me think it's
memory corruption.
Note: if you do *not* specify CONFIG_SYS_GENERIC_BOARD you still get
the
data abort, however it takes a bit more effort to trigger (like
actually
looking at the environment :-) )
(Note: This is building against the u-boot-2015.01-rc1 tree)
Suggestions?
In case it helps, I got the same symptom (help crashes) and it was due
to BSS not being cleared. Stefan (on cc) found this problem - he said
something to do with GDT calculation or handling. However it is just a
guess and probably has nothing to do with your issue.
I may be missing something, but the GDT appears to be x86-specific
whereas I'm building for ARMv5.
OK for some reason I thought this was PPC!
Maybe you can find your pc in System.map and work out where it is
going wrong? Are you hitting some image size limit?
pc : [c108ffd8]
Sorry, been distracted on other stuff for a few days.
First, I now understand the global descriptor a bit better. For ARMv5
It's stored in r9 and still looks sane. The relevant info:
(gdb) print/x *((gd_t *)$r9)
$1 = {bd = 0xc3e5ffb0, flags = 0x183, baudrate = 0x1c200, cpu_clk = 0x0,
bus_clk = 0x0, pci_clk = 0x0, mem_clk = 0x0, have_console = 0x1,
env_addr = 0xc10a8fcc, env_valid = 0x1, ram_top = 0xc400,
relocaddr = 0xc3f8, ram_size = 0x400, mon_len = 0x6ffb0,
irq_sp = 0xc3e5fef0, start_addr_sp = 0xc3e5fee0, reloc_off = 0x2f0,
new_gd = 0xc3e5ff08, fdt_blob = 0x0, new_fdt = 0x0, fdt_size = 0x0,
jt = 0xc3e601c0, env_buf = {0x31, 0x31, 0x35, 0x32, 0x30, 0x30,
0x0 repeats 26 times}, cur_i2c_bus = 0x0, timebase_h = 0x0,
timebase_l = 0x0, arch = {timer_rate_hz = 0x16e360, tbu = 0x0,
tbl = 0x4cc62, lastinc = 0x0, timer_reset_value = 0x0,
tlb_addr = 0xc3ff, tlb_size = 0x4000}}
The pc is definitely bogus. The reloc address is 0xc3f8 whereas
that would be a pre-reloc address (starting at 0xc108). And it's
definitely relocated by the time of failure. The only other bit of
information I have right now is that adding CONFIG_OF_LIBFDT drops the
reloc address from 0xc3f85000 to 0xc3f8.
Don't know if any of that gives additional insight. Meanwhile I
continue tracing.
Yes, continue tracing.
If ram_size is 0x4000 and
Re: [U-Boot] [PATCH] common/board_f.c: fix compile error when tracing disabled
Hi Kevin,
On 9 December 2014 at 16:03, Kevin Hilman khil...@kernel.org wrote:
From: Kevin Hilman khil...@linaro.org
When CONFIG_TRACE is disabled, linking fails with:
common/built-in.o:(.data.init_sequence_f+0x8): undefined reference to
`trace_early_init'
To fix, wrap the call to trace_early_init() with #ifdef CONFIG_TRACE.
Cc: Simon Glass s...@chromium.org
Cc: Tom Rini tr...@ti.com
Signed-off-by: Kevin Hilman khil...@linaro.org
---
Applies to v2015.01-rc3
common/board_f.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/common/board_f.c b/common/board_f.c
index 98c9c728ce73..cfd77f865361 100644
--- a/common/board_f.c
+++ b/common/board_f.c
@@ -813,7 +813,9 @@ static init_fnc_t init_sequence_f[] = {
#endif
setup_mon_len,
setup_fdt,
+#ifdef CONFIG_TRACE
trace_early_init,
+#endif
initf_malloc,
#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
/* TODO: can this go into arch_cpu_init()? */
Thanks - can you please also try removing the static inline stuff for
this in trace.h? It doesn't work.
Regards,
Simon
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Re: [U-Boot] U-Boot on nyan-big via legacy boot
Hi, On 9 December 2014 at 11:19, SimonH simon.hoin...@codethink.co.uk wrote: Hi Simon, On 04/12/14 15:53, Simon Glass wrote: [715.979284 HC 0xd2] This is a reboot command - EC_CMD_REBOOT_EC. I wonder how/why your U-Boot might issue that command? From my investigation, Coreboot is issuing this reboot command, because the Coreboot payload (which in my case is U-Boot) for some reason isn't valid. Normally you would hope for lots of AP serial output in this case. With CONFIG_PANIC_HANG defined there is no UART output from the EC at all. Is a prepended SPL needed before the U-Boot+DTB payload? I don't think so, but I have not tried. When flashing U-Boot from the Chromium OS branch it gives some UART output but freezes because SPI and MMC driver are not working properly (emerge-nyan chromeos-u-boot). Is this the best starting point to develop a working U-Boot? Yes, and I'm not sure of the state in the branch. Which branch? See u-boot-dm/nyan-working for an upstream version. It boots (at least from USB A-A) and the display comes up. To do: EC, keyboard, USB, maybe other things. Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v11 0/3] Adds support for Exynos5422 odroid xu3 board
Dear Kevin, On Tue, 09 Dec 2014 15:36:00 -0800 Kevin Hilman khil...@kernel.org wrote: Hyungwon Hwang human.hw...@samsung.com writes: This is v11 of the patchset adding support Odroud XU3 board. I finally got around to testing this on top of v2015.01-rc3 on my XU3. As I mentioned earlier, I had to enable the USB and networking options so I could dhcp/tftp but after that it works for me. Feel free to add: Tested-by: Kevin Hilman khil...@linaro.org Thanks for yout review. Sjoerd is waiting for his patch merged (title: Exynos: Move down common USB configuration). So the features related USB and networking will be enabled after this patchset and his patch are merged. [...] Note: If you use micro SD card for your test you have to apply the below patch additionally. This patch is needed, because micro sd card is recognized as MMC1 instead of MMC0. Additional work is needed to make it work regardless of device id. FYI, with or without your MMC ID patch, I wasn't able to save the environment to the SD card I'm booting from: ODROID-XU3 # saveenv Saving Environment to MMC... dwmci_send_cmd: Timeout. MMC init failed Actually I just tested it again. But it works for me. Saving Environment to MMC... Writing to MMC(1)... done I applied my patchset and MMC ID patch to commit 38cd8c4253013ccdd4052ee021f6066fe9a52551 in http://git.denx.de/u-boot-samsung.git (branch: master). I don't know why it does't work for you. Please feel free to need my help for this, if you need. Kevin Best regards, Hyungwon Hwang ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2] arm: ls102xa: Add QSPI boot support for LS1021AQDS/TWR board
On 12/09/2014 01:38 AM, Alison Wang wrote: This patch adds QSPI boot support for LS1021AQDS/TWR board. The QSPI boot image need to be programmed into the QSPI flash first. Then the booting will start from QSPI memory space. Signed-off-by: Alison Wang alison.w...@freescale.com --- Change log: v2: Rebase the patch. snip diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index 6a6f620..653dbef 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h snip @@ -315,7 +334,11 @@ #define CONFIG_CMDLINE_TAG #define CONFIG_CMDLINE_EDITING +#ifdef CONFIG_QSPI_BOOT +#undef CONFIG_CMD_IMLS +#else #define CONFIG_CMD_IMLS +#endif Is it necessary to undef? York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v11 0/3] Adds support for Exynos5422 odroid xu3 board
Hello Hyungwon Hwang, On Tue, Dec 9, 2014 at 4:58 PM, Hyungwon Hwang human.hw...@samsung.com wrote: Dear Kevin, On Tue, 09 Dec 2014 15:36:00 -0800 Kevin Hilman khil...@kernel.org wrote: Hyungwon Hwang human.hw...@samsung.com writes: This is v11 of the patchset adding support Odroud XU3 board. I finally got around to testing this on top of v2015.01-rc3 on my XU3. As I mentioned earlier, I had to enable the USB and networking options so I could dhcp/tftp but after that it works for me. Feel free to add: Tested-by: Kevin Hilman khil...@linaro.org Thanks for yout review. Sjoerd is waiting for his patch merged (title: Exynos: Move down common USB configuration). So the features related USB and networking will be enabled after this patchset and his patch are merged. [...] Note: If you use micro SD card for your test you have to apply the below patch additionally. This patch is needed, because micro sd card is recognized as MMC1 instead of MMC0. Additional work is needed to make it work regardless of device id. FYI, with or without your MMC ID patch, I wasn't able to save the environment to the SD card I'm booting from: ODROID-XU3 # saveenv Saving Environment to MMC... dwmci_send_cmd: Timeout. MMC init failed Actually I just tested it again. But it works for me. Saving Environment to MMC... Writing to MMC(1)... done I applied my patchset and MMC ID patch to commit 38cd8c4253013ccdd4052ee021f6066fe9a52551 in http://git.denx.de/u-boot-samsung.git (branch: master). I don't know why it does't work for you. Please feel free to need my help for this, if you need. Just like Kevin, I have to say that mmc is erratic. For example, if you let the boot process go all along (and not interrupt it), and let it fail in the pxe load commands. Then if you do a, ls mmc 1:1 / it will give a timeout error (Assuming you do have a valid 1st partition) But, if you interrupt the boot during the count down, and issue the same, it will work. I had mentioned this before, that if you enable *MMC_TRACE, it again stops working. Also, I found if you do a couple of mmc 1:1 commands, and do some other commands (say mmc rescan etc), and retry it will fail. Regards - Suriyan Kevin Best regards, Hyungwon Hwang ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2] arm: ls102xa: Add QSPI boot support for LS1021AQDS/TWR board
Hi, York, On 12/09/2014 01:38 AM, Alison Wang wrote: This patch adds QSPI boot support for LS1021AQDS/TWR board. The QSPI boot image need to be programmed into the QSPI flash first. Then the booting will start from QSPI memory space. Signed-off-by: Alison Wang alison.w...@freescale.com --- Change log: v2: Rebase the patch. snip diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index 6a6f620..653dbef 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h snip @@ -315,7 +334,11 @@ #define CONFIG_CMDLINE_TAG #define CONFIG_CMDLINE_EDITING +#ifdef CONFIG_QSPI_BOOT +#undef CONFIG_CMD_IMLS +#else #define CONFIG_CMD_IMLS +#endif Is it necessary to undef? [Alison Wang] It is necessary, because this file includes include/config_cmd_default.h. In include/config_cmd_default.h, CONFIG_CMD_IMLS is defined. Thanks. Best Regards, Alison Wang ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2] arm: ls102xa: Add QSPI boot support for LS1021AQDS/TWR board
York, On 12/09/2014 01:38 AM, Alison Wang wrote: This patch adds QSPI boot support for LS1021AQDS/TWR board. The QSPI boot image need to be programmed into the QSPI flash first. Then the booting will start from QSPI memory space. Signed-off-by: Alison Wang alison.w...@freescale.com --- Change log: v2: Rebase the patch. snip diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index 6a6f620..653dbef 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h snip @@ -315,7 +334,11 @@ #define CONFIG_CMDLINE_TAG #define CONFIG_CMDLINE_EDITING +#ifdef CONFIG_QSPI_BOOT +#undef CONFIG_CMD_IMLS +#else #define CONFIG_CMD_IMLS +#endif Is it necessary to undef? [Alison Wang] It is necessary, because this file includes include/config_cmd_default.h. In include/config_cmd_default.h, CONFIG_CMD_IMLS is defined. Thanks. [Alison Wang] I may misunderstand your meaning. For QSPI boot, IFC is disabled because IFC and QSPI are pin multiplexed, so CONFIG_CMD_IMLS should not be defined too. Best Regards, Alison Wang ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] arm:ls1021a:configure ls1021 scfg for QSPI
Hi, York, On 10/29/2014 11:26 PM, Chao Fu wrote: From: Chao Fu b44...@freescale.com Configure ls1021a scfg register for QSPI clock initalization. Signed-off-by: Chao Fu b44...@freescale.com Signed-off-by: Alison Wang alison.w...@freescale.com --- arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 1 + board/freescale/ls1021aqds/ls1021aqds.c | 4 board/freescale/ls1021atwr/ls1021atwr.c | 4 3 files changed, 9 insertions(+) Looks like this patch can be dropped as the change is in http://patchwork.ozlabs.org/patch/418986/. [Alison Wang] Yes. Thanks. Best Regards, Alison Wang ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [RFC PATCH v1 0/1] net: Support for Broadcom Tigon 3 NICs
I should probably explain the people involved here. Joshua did most of the porting work. I (Chris) picked it up to finish things off and to do some more testing. I'll also be the one trying to get this accepted upstream. Because my employer paid for us to do the work I've signed with my work email address. But because I'm already subscribed I'll send the patches using my gmail account. Joshua Scott (1): net: Add support for Tigon3 based Ethernet NICs drivers/net/Makefile |1 + drivers/net/tg3.c| 6119 ++ drivers/net/tg3.h| 3217 ++ include/netdev.h |4 + 4 files changed, 9341 insertions(+) create mode 100644 drivers/net/tg3.c create mode 100644 drivers/net/tg3.h -- 2.2.0.rc0 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v11 0/3] Adds support for Exynos5422 odroid xu3 board
Dear Suriyan, On Tue, 09 Dec 2014 18:29:56 -0800 Suriyan Ramasami suriya...@gmail.com wrote: Hello Hyungwon Hwang, On Tue, Dec 9, 2014 at 4:58 PM, Hyungwon Hwang human.hw...@samsung.com wrote: Dear Kevin, On Tue, 09 Dec 2014 15:36:00 -0800 Kevin Hilman khil...@kernel.org wrote: Hyungwon Hwang human.hw...@samsung.com writes: This is v11 of the patchset adding support Odroud XU3 board. I finally got around to testing this on top of v2015.01-rc3 on my XU3. As I mentioned earlier, I had to enable the USB and networking options so I could dhcp/tftp but after that it works for me. Feel free to add: Tested-by: Kevin Hilman khil...@linaro.org Thanks for yout review. Sjoerd is waiting for his patch merged (title: Exynos: Move down common USB configuration). So the features related USB and networking will be enabled after this patchset and his patch are merged. [...] Note: If you use micro SD card for your test you have to apply the below patch additionally. This patch is needed, because micro sd card is recognized as MMC1 instead of MMC0. Additional work is needed to make it work regardless of device id. FYI, with or without your MMC ID patch, I wasn't able to save the environment to the SD card I'm booting from: ODROID-XU3 # saveenv Saving Environment to MMC... dwmci_send_cmd: Timeout. MMC init failed Actually I just tested it again. But it works for me. Saving Environment to MMC... Writing to MMC(1)... done I applied my patchset and MMC ID patch to commit 38cd8c4253013ccdd4052ee021f6066fe9a52551 in http://git.denx.de/u-boot-samsung.git (branch: master). I don't know why it does't work for you. Please feel free to need my help for this, if you need. Just like Kevin, I have to say that mmc is erratic. For example, if you let the boot process go all along (and not interrupt it), and let it fail in the pxe load commands. Then if you do a, ls mmc 1:1 / it will give a timeout error (Assuming you do have a valid 1st partition) But, if you interrupt the boot during the count down, and issue the same, it will work. I had mentioned this before, that if you enable *MMC_TRACE, it again stops working. Also, I found if you do a couple of mmc 1:1 commands, and do some other commands (say mmc rescan etc), and retry it will fail. I tested all sinarios that you told me. But in all cases, it works for me. That's awkward. You are using Micro SD card. Right? Regards - Suriyan Kevin Best regards, Hyungwon Hwang ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot Best regards, Hyungwon Hwang ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCHv1] powerpc/p2041rdb: Convert to generic board
Add the following configuration: o CONFIG_SYS_GENERIC_BOARD o CONFIG_DISPLAY_BOARDINFO Signed-off-by: Chris Packham judge.pack...@gmail.com --- Builds, pings and boots a kernel. Any other testing needed? include/configs/P2041RDB.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index 2357791..22a1513 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -13,6 +13,8 @@ #define CONFIG_P2041RDB #define CONFIG_PHYS_64BIT +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO #define CONFIG_PPC_P2041 #ifdef CONFIG_RAMBOOT_PBL -- 2.2.0.rc0 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/2] x86: move arch-specific asmlinkage to asm/linkage.h
Hi Tom, On 7 December 2014 at 19:01, Masahiro Yamada yamad...@jp.panasonic.com wrote: Hi Simon, On Sun, 7 Dec 2014 14:44:21 -0700 Simon Glass s...@chromium.org wrote: #endif diff --git a/arch/x86/include/asm/linkage.h b/arch/x86/include/asm/linkage.h new file mode 100644 index 000..bdca72e --- /dev/null +++ b/arch/x86/include/asm/linkage.h @@ -0,0 +1,6 @@ +#ifndef _ASM_X86_LINKAGE_H +#define _ASM_X86_LINKAGE_H + +#define asmlinkage CPP_ASMLINKAGE __attribute__((regparm(0))) Why CPP_ASMLINKAGE here? The intention of the generic asmlinkage (defined in linux/linkage.h) is to add 'extern C' if __cplusplus is defined. The x86-specific asmlinkage should be supposed to add __attribute__((regparm(0))) onto that rather than replacing it. Tested on chromebook_link: Tested-by: Simon Glass s...@chromium.org With the above question answered, I'd like to apply this as it is a clean-up. Is it OK to so this independently of the ARM patch? It must be accompanied with the ARM patch, otherwise the latter will get a conflict. Will you apply both to u-boot-x86? I think it is OK because 2/2 is trivial enough. Do you agree with this? Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v4 04/23] ARM: tegra: Implement powergate support
From: Thierry Reding tred...@nvidia.com
Implement the powergate API that allows various power partitions to be
power up and down.
Signed-off-by: Thierry Reding tred...@nvidia.com
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v4: None
Changes in v3: None
arch/arm/cpu/tegra-common/Makefile | 1 +
arch/arm/cpu/tegra-common/powergate.c | 102 +
arch/arm/include/asm/arch-tegra/powergate.h| 38 +
arch/arm/include/asm/arch-tegra114/powergate.h | 6 ++
arch/arm/include/asm/arch-tegra124/powergate.h | 6 ++
arch/arm/include/asm/arch-tegra20/powergate.h | 6 ++
arch/arm/include/asm/arch-tegra30/powergate.h | 6 ++
7 files changed, 165 insertions(+)
create mode 100644 arch/arm/cpu/tegra-common/powergate.c
create mode 100644 arch/arm/include/asm/arch-tegra/powergate.h
create mode 100644 arch/arm/include/asm/arch-tegra114/powergate.h
create mode 100644 arch/arm/include/asm/arch-tegra124/powergate.h
create mode 100644 arch/arm/include/asm/arch-tegra20/powergate.h
create mode 100644 arch/arm/include/asm/arch-tegra30/powergate.h
diff --git a/arch/arm/cpu/tegra-common/Makefile
b/arch/arm/cpu/tegra-common/Makefile
index a18c318..c7603ee 100644
--- a/arch/arm/cpu/tegra-common/Makefile
+++ b/arch/arm/cpu/tegra-common/Makefile
@@ -13,5 +13,6 @@ obj-y += cache.o
obj-y += clock.o
obj-y += lowlevel_init.o
obj-y += pinmux-common.o
+obj-y += powergate.o
obj-$(CONFIG_DISPLAY_CPUINFO) += sys_info.o
obj-$(CONFIG_TEGRA124) += vpr.o
diff --git a/arch/arm/cpu/tegra-common/powergate.c
b/arch/arm/cpu/tegra-common/powergate.c
new file mode 100644
index 000..439cff3
--- /dev/null
+++ b/arch/arm/cpu/tegra-common/powergate.c
@@ -0,0 +1,102 @@
+/*
+ * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include common.h
+#include errno.h
+
+#include asm/io.h
+#include asm/types.h
+
+#include asm/arch/powergate.h
+#include asm/arch/tegra.h
+
+#define PWRGATE_TOGGLE 0x30
+#define PWRGATE_TOGGLE_START (1 8)
+
+#define REMOVE_CLAMPING 0x34
+
+#define PWRGATE_STATUS 0x38
+
+static int tegra_powergate_set(enum tegra_powergate id, bool state)
+{
+ u32 value, mask = state ? (1 id) : 0, old_mask;
+ unsigned long start, timeout = 25;
+
+ value = readl(NV_PA_PMC_BASE + PWRGATE_STATUS);
+ old_mask = value (1 id);
+
+ if (mask == old_mask)
+ return 0;
+
+ writel(PWRGATE_TOGGLE_START | id, NV_PA_PMC_BASE + PWRGATE_TOGGLE);
+
+ start = get_timer(0);
+
+ while (get_timer(start) timeout) {
+ value = readl(NV_PA_PMC_BASE + PWRGATE_STATUS);
+ if ((value (1 id)) == mask)
+ return 0;
+ }
+
+ return -ETIMEDOUT;
+}
+
+static int tegra_powergate_power_on(enum tegra_powergate id)
+{
+ return tegra_powergate_set(id, true);
+}
+
+int tegra_powergate_power_off(enum tegra_powergate id)
+{
+ return tegra_powergate_set(id, false);
+}
+
+static int tegra_powergate_remove_clamping(enum tegra_powergate id)
+{
+ unsigned long value;
+
+ /*
+* The REMOVE_CLAMPING register has the bits for the PCIE and VDEC
+* partitions reversed. This was originally introduced on Tegra20 but
+* has since been carried forward for backwards-compatibility.
+*/
+ if (id == TEGRA_POWERGATE_VDEC)
+ value = 1 TEGRA_POWERGATE_PCIE;
+ else if (id == TEGRA_POWERGATE_PCIE)
+ value = 1 TEGRA_POWERGATE_VDEC;
+ else
+ value = 1 id;
+
+ writel(value, NV_PA_PMC_BASE + REMOVE_CLAMPING);
+
+ return 0;
+}
+
+int tegra_powergate_sequence_power_up(enum tegra_powergate id,
+ enum periph_id periph)
+{
+ int err;
+
+ reset_set_enable(periph, 1);
+
+ err = tegra_powergate_power_on(id);
+ if (err 0)
+ return err;
+
+ clock_enable(periph);
+
+ udelay(10);
+
+ err = tegra_powergate_remove_clamping(id);
+ if (err 0)
+ return err;
+
+ udelay(10);
+
+ reset_set_enable(periph, 0);
+
+ return 0;
+}
diff --git a/arch/arm/include/asm/arch-tegra/powergate.h
b/arch/arm/include/asm/arch-tegra/powergate.h
new file mode 100644
index 000..130b58b
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra/powergate.h
@@ -0,0 +1,38 @@
+#ifndef _TEGRA_POWERGATE_H_
+#define _TEGRA_POWERGATE_H_
+
+#include asm/arch/clock.h
+
+enum tegra_powergate {
+ TEGRA_POWERGATE_CPU,
+ TEGRA_POWERGATE_3D,
+ TEGRA_POWERGATE_VENC,
+ TEGRA_POWERGATE_PCIE,
+ TEGRA_POWERGATE_VDEC,
+ TEGRA_POWERGATE_L2,
+ TEGRA_POWERGATE_MPE,
+ TEGRA_POWERGATE_HEG,
+ TEGRA_POWERGATE_SATA,
+ TEGRA_POWERGATE_CPU1,
+ TEGRA_POWERGATE_CPU2,
+ TEGRA_POWERGATE_CPU3,
+ TEGRA_POWERGATE_CELP,
+ TEGRA_POWERGATE_3D1,
+ TEGRA_POWERGATE_CPU0,
+
[U-Boot] [PATCH v4 10/23] ARM: tegra: Enable PCIe on TrimSlice
From: Thierry Reding tred...@nvidia.com
The TrimSlice has an ethernet NIC connected to the PCIe bus. Enable the
PCIe controller and the network driver so that the device can boot over
the network.
Signed-off-by: Thierry Reding tred...@nvidia.com
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v4: None
Changes in v3: None
arch/arm/dts/tegra20-trimslice.dts | 69
board/compulab/trimslice/trimslice.c | 8 +
include/configs/trimslice.h | 10 ++
3 files changed, 87 insertions(+)
diff --git a/arch/arm/dts/tegra20-trimslice.dts
b/arch/arm/dts/tegra20-trimslice.dts
index 74e8a16..1637cbd 100644
--- a/arch/arm/dts/tegra20-trimslice.dts
+++ b/arch/arm/dts/tegra20-trimslice.dts
@@ -47,6 +47,20 @@
status = disabled;
};
+ pcie-controller@80003000 {
+ status = okay;
+
+ avdd-pex-supply = pci_vdd_reg;
+ vdd-pex-supply = pci_vdd_reg;
+ avdd-pex-pll-supply = pci_vdd_reg;
+ avdd-plle-supply = pci_vdd_reg;
+ vddio-pex-clk-supply = pci_clk_reg;
+
+ pci@1,0 {
+ status = okay;
+ };
+ };
+
usb@c500 {
nvidia,vbus-gpio = gpio 170 0; /* PV2 */
};
@@ -66,4 +80,59 @@
wp-gpios = gpio 122 0; /* gpio PP2 */
bus-width = 4;
};
+
+ regulators {
+ compatible = simple-bus;
+ #address-cells = 1;
+ #size-cells = 0;
+
+ hdmi_vdd_reg: regulator@0 {
+ compatible = regulator-fixed;
+ reg = 0;
+ regulator-name = avdd_hdmi;
+ regulator-min-microvolt = 330;
+ regulator-max-microvolt = 330;
+ regulator-always-on;
+ };
+
+ hdmi_pll_reg: regulator@1 {
+ compatible = regulator-fixed;
+ reg = 1;
+ regulator-name = avdd_hdmi_pll;
+ regulator-min-microvolt = 180;
+ regulator-max-microvolt = 180;
+ regulator-always-on;
+ };
+
+ vbus_reg: regulator@2 {
+ compatible = regulator-fixed;
+ reg = 2;
+ regulator-name = usb1_vbus;
+ regulator-min-microvolt = 500;
+ regulator-max-microvolt = 500;
+ enable-active-high;
+ gpio = gpio TEGRA_GPIO(V, 2) 0;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ pci_clk_reg: regulator@3 {
+ compatible = regulator-fixed;
+ reg = 3;
+ regulator-name = pci_clk;
+ regulator-min-microvolt = 330;
+ regulator-max-microvolt = 330;
+ regulator-always-on;
+ };
+
+ pci_vdd_reg: regulator@4 {
+ compatible = regulator-fixed;
+ reg = 4;
+ regulator-name = pci_vdd;
+ regulator-min-microvolt = 105;
+ regulator-max-microvolt = 105;
+ regulator-always-on;
+ };
+ };
+
};
diff --git a/board/compulab/trimslice/trimslice.c
b/board/compulab/trimslice/trimslice.c
index 723293f..c9da80d 100644
--- a/board/compulab/trimslice/trimslice.c
+++ b/board/compulab/trimslice/trimslice.c
@@ -13,6 +13,7 @@
#include asm/arch/pinmux.h
#include asm/gpio.h
#include i2c.h
+#include netdev.h
void pin_mux_usb(void)
{
@@ -40,3 +41,10 @@ void pin_mux_mmc(void)
/* For CD GPIO PP1 */
pinmux_tristate_disable(PMUX_PINGRP_DAP3);
}
+
+#ifdef CONFIG_PCI
+int board_eth_init(bd_t *bis)
+{
+ return pci_eth_init(bis);
+}
+#endif
diff --git a/include/configs/trimslice.h b/include/configs/trimslice.h
index a254f86..59f4f67 100644
--- a/include/configs/trimslice.h
+++ b/include/configs/trimslice.h
@@ -60,6 +60,16 @@
#define CONFIG_USB_HOST_ETHER
#define CONFIG_USB_ETHER_ASIX
+/* PCI host support */
+#define CONFIG_PCI
+#define CONFIG_PCI_TEGRA
+#define CONFIG_PCI_PNP
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PCI_ENUM
+
+/* PCI networking support */
+#define CONFIG_RTL8169
+
/* General networking support */
#define CONFIG_CMD_NET
#define CONFIG_CMD_DHCP
--
2.2.0.rc0.207.ga3a616c
___
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