Hi Simon,
-Original Message-
From: s...@google.com [mailto:s...@google.com] On Behalf Of Simon Glass
Sent: Saturday, January 03, 2015 3:54 AM
To: Gupta Ruchika-R66431
Cc: U-Boot Mailing List; Sun York-R58495; Wolfgang Denk
Subject: Re: [PATCH 8/9] [v4] hash: Add function to find
Hi Simon,
-Original Message-
From: s...@google.com [mailto:s...@google.com] On Behalf Of Simon Glass
Sent: Saturday, January 03, 2015 3:54 AM
To: Gupta Ruchika-R66431
Cc: U-Boot Mailing List; Sun York-R58495
Subject: Re: [PATCH 7/9] [v4] lib/rsa: Add Kconfig for devices supporting
Hi Simon,
-Original Message-
From: s...@google.com [mailto:s...@google.com] On Behalf Of Simon Glass
Sent: Saturday, January 03, 2015 3:55 AM
To: Gupta Ruchika-R66431
Cc: U-Boot Mailing List; Sun York-R58495
Subject: Re: [PATCH 9/9] [v4] rsa: Use checksum algorithms from struct
This commit is already in my branch, I'm afraid.
On 05/01/15 20:30, York Sun wrote:
On 01/05/2015 12:27 PM, Fabio Estevam wrote:
[Adding more folks on Cc]
On Mon, Jan 5, 2015 at 3:35 PM, Ian Molton imol...@ad-holdings.co.uk wrote:
Hi folks,
I'm attempting to bring up a custom board with an
On 06.01.2015 01:08, Axel Lin wrote:
Current code tries to find the highest valid fifo depth by checking the value
it wrote to DW_SPI_TXFLTR. There are a few problems in current code:
1) There is an off-by-one in dws-fifo_len setting because it assumes the latest
register write fails so the
Hi,
On 06-01-15 01:09, Zoltan HERPAI wrote:
Add support for a sun4i board built by Linksprite. This addition covers
both v1 and v2 versions. As the board has been working with 408MHz memory
setting in the u-boot-sunxi branch, and has been proven to be running stable
during my tests as well, a
On 6 January 2015 at 15:28, Stefan Roese s...@denx.de wrote:
On 06.01.2015 01:08, Axel Lin wrote:
Current code tries to find the highest valid fifo depth by checking the
value
it wrote to DW_SPI_TXFLTR. There are a few problems in current code:
1) There is an off-by-one in dws-fifo_len
Hi all,
ping ? current master still has this regression, it is not fatal, but it is not
pretty either.
Regards,
Hans
On 30-12-14 11:55, Hans de Goede wrote:
Hi,
I noticed $subject while doing a MAKEALL.
It seems that this commit:
Hi Tom,
Siarhei Siamashka pointed out a small, but nasty error in the
axp221 driver, this pull-req fixes this, can you please include
this fix in the upcoming v2015.01 release ?
The following changes since commit d622ac39274a949b6445f1bfd92dc1644014388b:
powerpc: mpc824x: remove MPC824X cpu
Hi,
On 05-01-15 18:09, Ian Campbell wrote:
On Mon, 2015-01-05 at 17:18 +0100, Hans de Goede wrote:
This fixes us never programming ALDO2, and programming the ALDO2 voltage
into ALDo1.
Reported-by: Siarhei Siamashka siarhei.siamas...@gmail.com
Signed-off-by: Hans de Goede hdego...@redhat.com
On 4 January 2015 at 14:37, Peng Fan peng@freescale.com wrote:
To support bigger than 16MB size qspi flashes, spi framework uses bank
switch to access higher bank or lower bank.
In this patch, QSPI_CMD_BRRD, QSPI_CMD_BRWR, QSPI_CMD_WREAR, QSPI_CMD_RDEAR
is initialized in LUT register with
On 4 January 2015 at 14:37, Peng Fan peng@freescale.com wrote:
mx6sxsabresd revb board uses 32MB qspi flash, reva board uses 16MB qspi
flash. Currently, the default supported platform is revb board.
If want to configure for reva board, just define CONFIG_MX6SX_SABRESD_REVA
in
On 3 January 2015 at 21:15, Pavel Machek pa...@denx.de wrote:
On Wed 2014-12-31 20:14:55, Marek Vasut wrote:
Linux now also contains SPI driver, yet the name is 'snps,dw-apb-ssi'.
Fix the naming before we have to support both names.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See
On Tuesday 23 December 2014 03:56 AM, Felipe Balbi wrote:
This regulator is used with AM437x IDK to feed
VDD_MPU, without means to scale VDD_MPU we can't
support higher frequencies.
Signed-off-by: Felipe Balbi ba...@ti.com
---
drivers/power/pmic/Makefile| 1 +
On 01/05/2015 07:47 PM, Tom Rini wrote:
On Tue, Dec 23, 2014 at 02:08:57PM +0100, Valentin Longchamp wrote:
This is not used anymore since the procedure was split into a simple
read function and a later alaysis.
The ivm_read_eeprom name is now used for the previous
ivm_simple_read_eeprom
Hi Tom,
On Jan 5, 2015, at 22:29 , Tom Rini tr...@ti.com wrote:
On Mon, Jan 05, 2015 at 10:11:41PM +0200, Pantelis Antoniou wrote:
On Jan 5, 2015, at 22:10 , Fabio Estevam feste...@gmail.com wrote:
On Mon, Jan 5, 2015 at 6:08 PM, Pantelis Antoniou
pa...@antoniou-consulting.com wrote:
On 11/24/2014 11:58 AM, Holger Brunck wrote:
On 07/17/2014 11:15 AM, Holger Brunck wrote:
From: Christoph Dietrich christoph.dietr...@keymile.com
This board is similar to TUXX1, but it has a different FPGA connected to
chipselect 2. Therefore we need a different configuration for this
Hi,
On 06-01-15 12:57, Yassin Jaffer wrote:
Hi Hans
I was working on utilizing the DM framework for the nand driver, but this
is going to take sometime , anyway I will try to submit the driver based on
bbrezillon work.
Ok, thanks. I'm looking forward to the posting of the next version of
Now that usb start will only start usb if not already started, we can simply
call usb start whenever we (may) need access to usb devices, and it will only
actually scan the bus at the first call.
Signed-off-by: Hans de Goede hdego...@redhat.com
---
include/config_distro_bootcmd.h | 12
Currently we've this magic in include/config_distro_bootcmd.h to avoid
scanning the usb bus multiple times.
And it does not work when also using an usb keyboard because then the
preboot command has already scanned the bus, so we're still scanning it
twice.
This commit makes usb start only start
Hi Marek Stephen,
As discussed before we've a problem where our standard bootcmds sometimes
scan usb more then once, causing a large boot delay.
Marek, as discussed with you before, this patch-set tackles this differently
then previous sets, by simply making usb start a oneshot command (atleast
Hi Bin,
On 6 January 2015 at 07:14, Bin Meng bmeng...@gmail.com wrote:
In theory U-Boot built for coreboot is supposed to run as a payload
to be loaded by coreboot on every board that coreboot supports.
The U-Boot build process uses SYS_CONFIG_NAME and DEFAULT_DEVICE_TREE
which are hardcoded
On 6 January 2015 at 07:14, Bin Meng bmeng...@gmail.com wrote:
There are many places in the U-Boot source tree which refer to
CONFIG_SYS_COREBOOT, CONFIG_CBMEM_CONSOLE and CONFIG_VIDEO_COREBOOT
that is currently defined in coreboot.h.
Move them to arch/x86/cpu/coreboot/Kconfig so that we can
On 6 January 2015 at 07:14, Bin Meng bmeng...@gmail.com wrote:
Change SYS_CONFIG_NAME and DEFAULT_DEVICE_TREE to chromebook_link
which is currently the only real board officially supported to run
U-Boot loaded by coreboot.
Note the symbolic link file chromebook_link.dts is deleted and
On 6 January 2015 at 07:14, Bin Meng bmeng...@gmail.com wrote:
Update README.x86 to include new build instructions for U-Boot as
the coreboot payload and testing considerations with coreboot.
Signed-off-by: Bin Meng bmeng...@gmail.com
Acked-by: Simon Glass s...@chromium.org
---
Changes in
On 5 January 2015 at 23:35, Bin Meng bmeng...@gmail.com wrote:
CONFIG_DISPLAY_CPUINFO is already defined in x86-common.h, so remove
it to avoid duplication.
Signed-off-by: Bin Meng bmeng...@gmail.com
---
include/configs/chromebook_link.h | 1 -
1 file changed, 1 deletion(-)
Acked-by:
Hi Simon,
On Tue, Jan 6, 2015 at 10:21 PM, Simon Glass s...@chromium.org wrote:
Hi Bin,
On 6 January 2015 at 07:14, Bin Meng bmeng...@gmail.com wrote:
In theory U-Boot built for coreboot is supposed to run as a payload
to be loaded by coreboot on every board that coreboot supports.
The
Hi Bin,
On 6 January 2015 at 07:35, Bin Meng bmeng...@gmail.com wrote:
Hi Simon,
On Tue, Jan 6, 2015 at 10:21 PM, Simon Glass s...@chromium.org wrote:
Hi Bin,
On 6 January 2015 at 07:14, Bin Meng bmeng...@gmail.com wrote:
In theory U-Boot built for coreboot is supposed to run as a payload
Since we already swtiched to use the new mechanism for building
U-Boot for coreboot, coreboot.h is no longer needed so remove it.
Signed-off-by: Bin Meng bmeng...@gmail.com
Acked-by: Simon Glass s...@chromium.org
---
Changes in v4: None
Changes in v3: None
Changes in v2:
- New patch to remove
Change SYS_CONFIG_NAME and DEFAULT_DEVICE_TREE to chromebook_link
which is currently the only real board officially supported to run
U-Boot loaded by coreboot.
Note the symbolic link file chromebook_link.dts is deleted and
link.dts is renamed to chromebook_link.dts.
To avoid multiple definition
There are many places in the U-Boot source tree which refer to
CONFIG_SYS_COREBOOT, CONFIG_CBMEM_CONSOLE and CONFIG_VIDEO_COREBOOT
that is currently defined in coreboot.h.
Move them to arch/x86/cpu/coreboot/Kconfig so that we can switch
to board configuration file to build U-Boot later.
On 5 January 2015 at 23:04, Bin Meng bmeng...@gmail.com wrote:
These two are not worth having separate inline functions as they are
really simple, so drop them.
Also changed 'type' parameter of fsp_get_next_hob() from u16 to uint.
Suggested-by: Simon Glass s...@chromium.org
Signed-off-by:
Move CONFIG_SYS_CAR_ADDR and CONFIG_SYS_CAR_SIZE to Kconfig so that
we don't need them in the board configuration file thus the same
board configuratoin file can be used to build both coreboot version
and bare version.
Signed-off-by: Bin Meng bmeng...@gmail.com
Acked-by: Simon Glass
cros_ec_board_init() should be called only when CONFIG_CROS_EC is
enabled.
Signed-off-by: Bin Meng bmeng...@gmail.com
Acked-by: Simon Glass s...@chromium.org
---
Changes in v4: None
Changes in v3: None
Changes in v2:
- Leave CROS_EC defines unchanged in coreboot.h
Convert CONFIG_X86_RESET_VECTOR and CONFIG_SYS_X86_START16 to Kconfig
options so that we can remove them from board configuration file.
Signed-off-by: Bin Meng bmeng...@gmail.com
Acked-by: Simon Glass s...@chromium.org
---
Changes in v4: None
Changes in v3: None
Changes in v2:
- New patch to
In theory U-Boot built for coreboot is supposed to run as a payload
to be loaded by coreboot on every board that coreboot supports.
The U-Boot build process uses SYS_CONFIG_NAME and DEFAULT_DEVICE_TREE
which are hardcoded in board defconfig and Kconfig files. For better
support of coreboot, we
In theory U-Boot built for coreboot is supposed to run as a payload
to be loaded by coreboot on every board that coreboot supports.
The U-Boot build process uses SYS_CONFIG_NAME and DEFAULT_DEVICE_TREE
which are hardcoded in board defconfig and Kconfig files. For better
support of coreboot, we
If coreboot is built with CONFIG_COLLECT_TIMESTAMPS, use the value
of base_time in coreboot's timestamp table as our timer base,
otherwise TSC counter value will be used.
Sometimes even coreboot is built with CONFIG_COLLECT_TIMESTAMPS,
the value of base_time in the timestamp table is still zero,
By default U-Boot automatically calibrates TSC running frequency via
MSR and PIT. The calibration may not work on every x86 processor, so
a new Kconfig option CONFIG_TSC_CALIBRATION_BYPASS is introduced to
allow bypassing the calibration and assign a hardcoded TSC frequency
CONFIG_TSC_FREQ_IN_MHZ.
When CONFIG_X86_RESET_VECTOR is not selected, specifying the ROM chip
size is meaningless, hence hide it.
Signed-off-by: Bin Meng bmeng...@gmail.com
Acked-by: Simon Glass s...@chromium.org
---
Changes in v4:
- Hide XIP_ROM_SIZE too after rebase
Changes in v3: None
Changes in v2:
- New patch to
Configure coreboot pci memory regions so that pci device drivers
could work correctly.
Signed-off-by: Bin Meng bmeng...@gmail.com
Acked-by: Simon Glass s...@chromium.org
---
Changes in v4: None
Changes in v3: None
Changes in v2:
- New patch to configure pci memory regions
Update README.x86 to include new build instructions for U-Boot as
the coreboot payload and testing considerations with coreboot.
Signed-off-by: Bin Meng bmeng...@gmail.com
Acked-by: Simon Glass s...@chromium.org
---
Changes in v4: None
Changes in v3:
- Fix several typos in README.x86
Changes
From: Fabio Estevam fabio.este...@freescale.com
Since commit 3ff46cc42b9d73d0 (arm: relocate the exception vectors) mx25pdk
hangs like this:
CPU: Freescale i.MX25 rev1.2 at 399 MHz
Reset cause: WDOG
Board: MX25PDK
I2C: ready
DRAM: 64 MiB
(hangs)
Add a specific relocate_vectors macro that
On Tue, Jan 06, 2015 at 02:28:23PM +0530, Mugunthan V N wrote:
On Tuesday 23 December 2014 03:56 AM, Felipe Balbi wrote:
This regulator is used with AM437x IDK to feed
VDD_MPU, without means to scale VDD_MPU we can't
support higher frequencies.
Signed-off-by: Felipe Balbi ba...@ti.com
This regulator is used with AM437x IDK to feed
VDD_MPU, without means to scale VDD_MPU we can't
support higher frequencies.
Signed-off-by: Felipe Balbi ba...@ti.com
---
Changes since v1:
- git add the header which I had missed originally
drivers/power/pmic/Makefile| 1 +
Hi Ruchika,
On 6 January 2015 at 02:37, Ruchika Gupta ruchika.gu...@freescale.com
wrote:
Hi Simon,
-Original Message-
From: s...@google.com [mailto:s...@google.com] On Behalf Of Simon Glass
Sent: Saturday, January 03, 2015 3:54 AM
To: Gupta Ruchika-R66431
Cc: U-Boot Mailing
From: Arnab Basu arnab.b...@freescale.com
U-Boot should only add enable-method and cpu-release-address
properties to the cpu node of the online cores.
Signed-off-by: Arnab Basu arnab.b...@freescale.com
Signed-off-by: York Sun york...@freescale.com
---
arch/arm/cpu/armv8/fsl-lsch3/fdt.c | 23
From: Bhupesh Sharma bhupesh.sha...@freescale.com
This patch enusres that right banners are printed for LS2085A
emulator and simulator platforms.
Signed-off-by: Bhupesh Sharma bhupesh.sha...@freescale.com
---
include/configs/ls2085a_common.h |3 ---
include/configs/ls2085a_emu.h|3
Erratum A008514 workround requires writing register eddrtqcr1 with
value 0x63b20002.
Signed-off-by: York Sun york...@freescale.com
---
drivers/ddr/fsl/fsl_ddr_gen4.c | 22 +-
1 file changed, 17 insertions(+), 5 deletions(-)
diff --git a/drivers/ddr/fsl/fsl_ddr_gen4.c
Erratum A008514 appleis to ls2085a.
Signed-off-by: York Sun york...@freescale.com
---
arch/arm/include/asm/arch-fsl-lsch3/config.h |1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/include/asm/arch-fsl-lsch3/config.h
b/arch/arm/include/asm/arch-fsl-lsch3/config.h
index
From: Stuart Yoder stuart.yo...@freescale.com
Move the load address of the kernel image to get it away from the
region of the uncompressed kernel.
Signed-off-by: Stuart Yoder stuart.yo...@freescale.com
---
include/configs/ls2085a_common.h |2 +-
1 file changed, 1 insertion(+), 1
LS2085A and its variants can have up to four clusters. It is safe
to enable timebase for all even some may be disabled.
Signed-off-by: York Sun york...@freescale.com
---
board/freescale/ls2085a/ls2085a.c | 11 +--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git
Add sync of refresh for multiple DDR controllers. DDRC initialization
needs to complete first. Code is re-ordered to keep refresh close.
Signed-off-by: York Sun york...@freescale.com
---
README |3 +++
drivers/ddr/fsl/main.c |4
drivers/ddr/fsl/util.c | 55
Erratum A008336 requires setting EDDRTQCR1[2] in DDRC DCSR space
for 64-bit DDR controllers.
Signed-off-by: York Sun york...@freescale.com
---
arch/arm/include/asm/arch-fsl-lsch3/config.h |5 +
drivers/ddr/fsl/fsl_ddr_gen4.c | 22 ++
2 files changed,
Commit 73c25753 fixed the common issue that binutil packages (tool/organization
that packaged or built the bin-utils) are included in brackets and this may
falsely be recognized as a version. However, some tools do not provide a
'package' and previously we add the 'Gnu assembler..' to the
On Sat 2015-01-03 21:30:56, Marek Vasut wrote:
On Friday, January 02, 2015 at 06:19:24 AM, Pavel Machek wrote:
On Wed 2014-12-31 20:14:51, Marek Vasut wrote:
Sync SoCFPGA Cyclone V development kit pinmux configuration with
Rocketboard U-Boot v2013.01.01-114-g9381569
(CCing Dennis so he can comment from a distro perspective re: partition
table bootable flags v.s. scanning all partitions)
On 01/06/2015 10:07 AM, Sjoerd Simons wrote:
On Mon, 2015-01-05 at 13:24 -0700, Stephen Warren wrote:
On 01/05/2015 10:13 AM, Sjoerd Simons wrote:
Not all devices use
Fix several spelling errors and replace the invalid word
architectured with designed.
Signed-off-by: Jeremiah Mahler jmmah...@gmail.com
---
board/ti/am335x/README | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/board/ti/am335x/README b/board/ti/am335x/README
index
DP-DDR benefits from auto precharge because of its specific
application.
Signed-off-by: York Sun york...@freescale.com
---
board/freescale/ls2085a/ddr.c |1 +
1 file changed, 1 insertion(+)
diff --git a/board/freescale/ls2085a/ddr.c b/board/freescale/ls2085a/ddr.c
index b4a3fc9..4884fa2
Controller number is passed for function calls to support individual
DDR clock, depending on SoC implementation. It is backward compatible
with exising platforms. Multiple clocks have been verifyed on LS2085A
emulator.
Signed-off-by: York Sun york...@freescale.com
---
Hi Pali Rohár,
The prefetch abort exception occurs in the function
do_omap3_emu_romcode_call (in arch/arm/cpu/armv7/omap3/lowlevel_init.S)
when executing the instruction SMC #1.
I can't figure out what makes the difference between the working and the
not-working versions.
Maybe we should
From: Bhupesh Sharma bhupesh.sha...@freescale.com
This patch ensures that the TZPC (BP147) and TZASC-400 programming
happens for LS2085A SoC only when the desired config flags are
enabled and ensures that the TZPC programming is done to allow Non-secure
(NS) + secure (S) transactions only for
According to hardware implementation, a single outer shareable global
coherence group is defined. Inner shareable has not bee enabled.
Signed-off-by: York Sun york...@freescale.com
---
arch/arm/cpu/armv8/fsl-lsch3/cpu.c |6 +++---
arch/arm/include/asm/armv8/mmu.h |3 ++-
2 files
Add bit opearation accessors to DDR driver for little- and big-endian.
Signed-off-by: York Sun york...@freescale.com
---
include/fsl_ddr.h |6 ++
1 file changed, 6 insertions(+)
diff --git a/include/fsl_ddr.h b/include/fsl_ddr.h
index 675557a..3286c95 100644
--- a/include/fsl_ddr.h
+++
FSL-LSCH3 platforms can have multiple DDR clocks. LS2085A has one clock for
general DDR controlers, and another clock for DP-DDR. DDR driver needs to
change to support multiple clocks.
Signed-off-by: York Sun york...@freescale.com
---
arch/arm/cpu/armv8/fsl-lsch3/cpu.c|1 +
From: J. German Rivera german.riv...@freescale.com
Upgrade Manage Complex (MC) flib API to 0.5.2. Rename directory
fsl_mc to fsl-mc. Change the fsl-mc node in Linux device tree
from fsl,dprcr to fsl-mc. Print MC version info when
appropriate.
Signed-off-by: J. German Rivera
From: Arnab Basu arnab.b...@freescale.com
Since Linux v3.16-rc1 earlyprintk has been removed for arm64.
Switch to using earlycon.
Signed-off-by: Arnab Basu arnab.b...@freescale.com
Signed-off-by: York Sun york...@freescale.com
---
include/configs/ls2085a_common.h |8
1 file
Enable sync of DDR refresh for LS2085a platform. GPP DDR controllers
stay in sync. DP-DDR has only one controller so it does no harm.
Signed-off-by: York Sun york...@freescale.com
---
include/configs/ls2085a_emu.h |1 +
1 file changed, 1 insertion(+)
diff --git
Commit 73c25753 fixed the common issue that binutil packages (tool/organization
that packaged or built the bin-utils) are included in brackets and this may
falsely be recognized as a version. However, some tools do not provide a
'package' and previously we add the 'Gnu assembler..' to the
Hi Pali Rohár,
Le 06/01/2015 23:19, Pali Rohár a écrit :
ooo, thanks very much for help!
On non omap HS devices that SMC instruction must not be called.
Qemu emulate omap GP device (not HS), so here is must not be
called too. I remember that linux kernel crashed when called
similar function in
From: Bhupesh Sharma bhupesh.sha...@freescale.com
This patch adds the fdt-fixup logic for the clock frequency of the
NS16550A related device tree nodes.
Signed-off-by: Bhupesh Sharma bhupesh.sha...@freescale.com
---
arch/arm/cpu/armv8/fsl-lsch3/fdt.c |5 +
1 file changed, 5
wwt_bg should match rrt_bg. It was a typo in driver.
Signed-off-by: York Sun york...@freescale.com
---
drivers/ddr/fsl/ctrl_regs.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c
index 713c3ed..690e73d 100644
---
Erratum A008336 applied to LS2085A.
Signed-off-by: York Sun york...@freescale.com
---
arch/arm/include/asm/arch-fsl-lsch3/config.h |4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/include/asm/arch-fsl-lsch3/config.h
b/arch/arm/include/asm/arch-fsl-lsch3/config.h
index
From: Kuldip Giroh kuldip.gi...@freescale.com
LS NADK memory manager by default works on HugeTLB. Hence bootargs
must include parameters default_hugepagesz (default hugepagesize,
hugepagesz (hugepage size) and hugepages (number of hugepages to be
reserved in kernel for the given size).
On 6 Jan 2015, tr...@ti.com wrote:
On Tue, Jan 06, 2015 at 11:27:43AM +0100, Hans de Goede wrote:
Hi all,
ping ? current master still has this regression, it is not fatal,
but it is not
pretty either.
Did you see my earlier reply? It's OK with vanilla toolchains (see
ELDK) and Linaro
On Tue, Jan 06, 2015 at 05:01:22PM -0500, Bill Pringlemeir wrote:
On Tue, Jan 06, 2015 at 11:27:43AM +0100, Hans de Goede wrote:
ping ? current master still has this regression, it is not fatal,
but it is not
pretty either.
On 6 Jan 2015, tr...@ti.com wrote:
Did you see my
ooo, thanks very much for help!
On non omap HS devices that SMC instruction must not be called.
Qemu emulate omap GP device (not HS), so here is must not be
called too. I remember that linux kernel crashed when called
similar function in qemu.
I temporary commented do_omap3_emu_romcode_call
This set update LS2085a for both emulator and simulator boards. There
are also changes to DDR driver to accomodate new features and bug fix.
U-boot still runs at EL3. This will change when we have the security
monitor in place later. lowlevel.S will be trimmed down once both security
monitor and
Flushing L3 cache in CCN-504 requries d-cache to be disabled. Using
assembly function to guarantee stack is not used before flushing is
completed. Timeout is needed for simualtor on which CCN-504 is not
implemented. Return value can be checked for timeout situation.
Change bootm.c to disable
On ZeBu emulator, CAS to preamble overrides need to be set to
satisfy the timing. This only impact platforms with CONFIG_EMU.
These should be set before MEM_EN is set.
Signed-off-by: York Sun york...@freescale.com
---
drivers/ddr/fsl/ctrl_regs.c |6 +-
1 file changed, 5 insertions(+),
Set system clock to 100MHz and DDR clock to 133MHz.
Signed-off-by: York Sun york...@freescale.com
---
include/configs/ls2085a_common.h |3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/include/configs/ls2085a_common.h b/include/configs/ls2085a_common.h
index
On Tue, Jan 06, 2015 at 11:27:43AM +0100, Hans de Goede wrote:
ping ? current master still has this regression, it is not fatal,
but it is not
pretty either.
On 6 Jan 2015, tr...@ti.com wrote:
Did you see my earlier reply? It's OK with vanilla toolchains (see
ELDK) and Linaro ones, but
On 6 January 2015 at 07:14, Bin Meng bmeng...@gmail.com wrote:
Convert CONFIG_X86_RESET_VECTOR and CONFIG_SYS_X86_START16 to Kconfig
options so that we can remove them from board configuration file.
Signed-off-by: Bin Meng bmeng...@gmail.com
Acked-by: Simon Glass s...@chromium.org
---
On 6 January 2015 at 07:14, Bin Meng bmeng...@gmail.com wrote:
In theory U-Boot built for coreboot is supposed to run as a payload
to be loaded by coreboot on every board that coreboot supports.
The U-Boot build process uses SYS_CONFIG_NAME and DEFAULT_DEVICE_TREE
which are hardcoded in board
On 6 January 2015 at 07:28, Simon Glass s...@chromium.org wrote:
On 6 January 2015 at 07:14, Bin Meng bmeng...@gmail.com wrote:
There are many places in the U-Boot source tree which refer to
CONFIG_SYS_COREBOOT, CONFIG_CBMEM_CONSOLE and CONFIG_VIDEO_COREBOOT
that is currently defined in
On 6 January 2015 at 07:14, Bin Meng bmeng...@gmail.com wrote:
By default U-Boot automatically calibrates TSC running frequency via
MSR and PIT. The calibration may not work on every x86 processor, so
a new Kconfig option CONFIG_TSC_CALIBRATION_BYPASS is introduced to
allow bypassing the
On 6 January 2015 at 07:14, Bin Meng bmeng...@gmail.com wrote:
Move CONFIG_SYS_CAR_ADDR and CONFIG_SYS_CAR_SIZE to Kconfig so that
we don't need them in the board configuration file thus the same
board configuratoin file can be used to build both coreboot version
and bare version.
On 6 January 2015 at 07:14, Bin Meng bmeng...@gmail.com wrote:
Since we already swtiched to use the new mechanism for building
U-Boot for coreboot, coreboot.h is no longer needed so remove it.
Signed-off-by: Bin Meng bmeng...@gmail.com
Acked-by: Simon Glass s...@chromium.org
---
Changes
On 6 January 2015 at 07:14, Bin Meng bmeng...@gmail.com wrote:
When CONFIG_X86_RESET_VECTOR is not selected, specifying the ROM chip
size is meaningless, hence hide it.
Signed-off-by: Bin Meng bmeng...@gmail.com
Acked-by: Simon Glass s...@chromium.org
---
Changes in v4:
- Hide
On 6 January 2015 at 07:15, Simon Glass s...@chromium.org wrote:
On 5 January 2015 at 23:04, Bin Meng bmeng...@gmail.com wrote:
These two are not worth having separate inline functions as they are
really simple, so drop them.
Also changed 'type' parameter of fsp_get_next_hob() from u16 to
On 6 January 2015 at 07:30, Simon Glass s...@chromium.org wrote:
On 6 January 2015 at 07:14, Bin Meng bmeng...@gmail.com wrote:
Change SYS_CONFIG_NAME and DEFAULT_DEVICE_TREE to chromebook_link
which is currently the only real board officially supported to run
U-Boot loaded by coreboot.
Note
On 6 January 2015 at 07:30, Simon Glass s...@chromium.org wrote:
On 6 January 2015 at 07:14, Bin Meng bmeng...@gmail.com wrote:
Update README.x86 to include new build instructions for U-Boot as
the coreboot payload and testing considerations with coreboot.
Signed-off-by: Bin Meng
On 6 January 2015 at 07:14, Bin Meng bmeng...@gmail.com wrote:
If coreboot is built with CONFIG_COLLECT_TIMESTAMPS, use the value
of base_time in coreboot's timestamp table as our timer base,
otherwise TSC counter value will be used.
Sometimes even coreboot is built with
fdt_first_subnode() returns -FDT_ERR_NOTFOUND if no subnode found.
0 is supposed to be a valid offset returns from fdt_first_subnode().
Signed-off-by: Axel Lin axel@ingics.com
---
drivers/spi/cadence_qspi.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
On Wednesday, January 07, 2015 at 12:08:13 AM, Pavel Machek wrote:
On Sat 2015-01-03 21:30:56, Marek Vasut wrote:
On Friday, January 02, 2015 at 06:19:24 AM, Pavel Machek wrote:
On Wed 2014-12-31 20:14:51, Marek Vasut wrote:
Sync SoCFPGA Cyclone V development kit pinmux configuration
On 6 January 2015 at 07:14, Bin Meng bmeng...@gmail.com wrote:
Configure coreboot pci memory regions so that pci device drivers
could work correctly.
Signed-off-by: Bin Meng bmeng...@gmail.com
Acked-by: Simon Glass s...@chromium.org
---
Changes in v4: None
Changes in v3: None
Changes in
On 6 January 2015 at 07:32, Simon Glass s...@chromium.org wrote:
On 5 January 2015 at 23:35, Bin Meng bmeng...@gmail.com wrote:
CONFIG_DISPLAY_CPUINFO is already defined in x86-common.h, so remove
it to avoid duplication.
Signed-off-by: Bin Meng bmeng...@gmail.com
---
On 6 January 2015 at 07:14, Bin Meng bmeng...@gmail.com wrote:
cros_ec_board_init() should be called only when CONFIG_CROS_EC is
enabled.
Signed-off-by: Bin Meng bmeng...@gmail.com
Acked-by: Simon Glass s...@chromium.org
---
Changes in v4: None
Changes in v3: None
Changes in v2:
-
Hi Ruchika,
On 6 January 2015 at 02:38, Ruchika Gupta ruchika.gu...@freescale.com wrote:
Hi Simon,
-Original Message-
From: s...@google.com [mailto:s...@google.com] On Behalf Of Simon Glass
Sent: Saturday, January 03, 2015 3:54 AM
To: Gupta Ruchika-R66431
Cc: U-Boot Mailing List;
Hi Hans
I was working on utilizing the DM framework for the nand driver, but this
is going to take sometime , anyway I will try to submit the driver based on
bbrezillon work.
I'm quite happy if Daniel wants to pickup my work, besides Daniel patches
are for the SPL nand driver.
Regards
On
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