[U-Boot] [PATCH v3 03/12] ARM: Factor out reusable psci_get_cpu_stack_top
This algorithm will be useful on Tegra as well, plus we will need it for making _psci_target_pc per-CPU. Signed-off-by: Jan Kiszka jan.kis...@siemens.com --- arch/arm/cpu/armv7/psci.S | 14 ++ arch/arm/cpu/armv7/sunxi/psci.S | 17 +++-- 2 files changed, 21 insertions(+), 10 deletions(-) diff --git a/arch/arm/cpu/armv7/psci.S b/arch/arm/cpu/armv7/psci.S index e916d71..da47934 100644 --- a/arch/arm/cpu/armv7/psci.S +++ b/arch/arm/cpu/armv7/psci.S @@ -170,6 +170,20 @@ ENTRY(psci_cpu_off_common) bx lr ENDPROC(psci_cpu_off_common) +@ expects CPU ID in r4 (will be overwritten) and returns stack top in r5 +ENTRY(psci_get_cpu_stack_top) + mov r5, #0x400 @ 1kB of stack per CPU + mul r4, r4, r5 + + ldr r5, =psci_text_end @ end of monitor text + add r5, r5, #0x2000 @ Skip two pages + lsr r5, r5, #12 @ Align to start of page + lsl r5, r5, #12 + sub r5, r5, r4 @ here's our stack! + + bx lr +ENDPROC(psci_get_cpu_stack_top) + ENTRY(psci_cpu_entry) @ Set SMP bit mrc p15, 0, r0, c1, c0, 1 @ ACTLR diff --git a/arch/arm/cpu/armv7/sunxi/psci.S b/arch/arm/cpu/armv7/sunxi/psci.S index c3a8dc1..4372022 100644 --- a/arch/arm/cpu/armv7/sunxi/psci.S +++ b/arch/arm/cpu/armv7/sunxi/psci.S @@ -213,6 +213,8 @@ psci_cpu_off: .globl psci_arch_init psci_arch_init: + mov r6, lr + movwr4, #(GICD_BASE 0x) movtr4, #(GICD_BASE 16) @@ -240,16 +242,11 @@ psci_arch_init: mrc p15, 0, r4, c0, c0, 5 @ MPIDR and r4, r4, #3 @ cpu number in cluster - mov r5, #0x400 @ 1kB of stack per CPU - mul r4, r4, r5 - - adr r5, text_end@ end of text - add r5, r5, #0x2000 @ Skip two pages - lsr r5, r5, #12 @ Align to start of page - lsl r5, r5, #12 - sub sp, r5, r4 @ here's our stack! + bl psci_get_cpu_stack_top + mov sp, r5 - bx lr + bx r6 -text_end: + .globl psci_text_end +psci_text_end: .popsection -- 2.1.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3 04/12] ARM: Put target PC for PSCI CPU_ON on per-CPU stack
Use a per-CPU variable for saving the target PC during CPU_ON
operations. This allows us to run this service independently on targets
that have more than 2 cores and also core-local power control.
Signed-off-by: Jan Kiszka jan.kis...@siemens.com
---
arch/arm/cpu/armv7/psci.S | 8 ++--
arch/arm/cpu/armv7/sunxi/psci.S | 9 ++---
2 files changed, 8 insertions(+), 9 deletions(-)
diff --git a/arch/arm/cpu/armv7/psci.S b/arch/arm/cpu/armv7/psci.S
index da47934..9674503 100644
--- a/arch/arm/cpu/armv7/psci.S
+++ b/arch/arm/cpu/armv7/psci.S
@@ -179,6 +179,7 @@ ENTRY(psci_get_cpu_stack_top)
add r5, r5, #0x2000 @ Skip two pages
lsr r5, r5, #12 @ Align to start of page
lsl r5, r5, #12
+ sub r5, r5, #4 @ reserve 1 word for target PC
sub r5, r5, r4 @ here's our stack!
bx lr
@@ -194,13 +195,8 @@ ENTRY(psci_cpu_entry)
bl _nonsec_init
bl psci_arch_init
- adr r0, _psci_target_pc
- ldr r0, [r0]
+ ldr r0, [sp]@ target PC at stack top
b _do_nonsec_entry
ENDPROC(psci_cpu_entry)
-.globl _psci_target_pc
-_psci_target_pc:
- .word 0
-
.popsection
diff --git a/arch/arm/cpu/armv7/sunxi/psci.S b/arch/arm/cpu/armv7/sunxi/psci.S
index 4372022..8d964d0 100644
--- a/arch/arm/cpu/armv7/sunxi/psci.S
+++ b/arch/arm/cpu/armv7/sunxi/psci.S
@@ -138,8 +138,11 @@ out: mcr p15, 0, r7, c1, c1, 0
@ r2 = target PC
.globl psci_cpu_on
psci_cpu_on:
- ldr r0, =_psci_target_pc
- str r2, [r0]
+ push{lr}
+
+ mov r4, r1
+ bl psci_get_cpu_stack_top @ get stack top of target CPU
+ str r2, [r5]@ store target PC at stack top
dsb
movwr0, #(SUN7I_CPUCFG_BASE 0x)
@@ -194,7 +197,7 @@ psci_cpu_on:
str r6, [r0, #0x1e4]
mov r0, #ARM_PSCI_RET_SUCCESS @ Return PSCI_RET_SUCCESS
- mov pc, lr
+ pop {pc}
.globl psci_cpu_off
psci_cpu_off:
--
2.1.4
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3 09/12] tegra124: Add PSCI support for Tegra124
This is based on Thierry Reding's work and uses Ian Campell's
preparatory patches. It comes with full support for CPU_ON/OFF PSCI
services. The algorithm used in this version for turning CPUs on and
off was proposed by Thierry Reding in
http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/210881. It
consists of first enabling CPU1..3 via the PMC, just to powergate them
again with the help of the Flow Controller. Once the Flow Controller is
in place, we can leave the PMC alone while processing CPU_ON and CPU_OFF
PSCI requests.
Signed-off-by: Jan Kiszka jan.kis...@siemens.com
---
arch/arm/cpu/armv7/Makefile | 1 +
arch/arm/cpu/armv7/tegra-common/Makefile | 1 +
arch/arm/cpu/armv7/tegra-common/psci.S| 101 ++
arch/arm/cpu/armv7/tegra124/Makefile | 7 +++
arch/arm/cpu/armv7/tegra124/ap.c | 44 +
arch/arm/include/asm/arch-tegra124/flow.h | 5 ++
6 files changed, 159 insertions(+)
create mode 100644 arch/arm/cpu/armv7/tegra-common/psci.S
create mode 100644 arch/arm/cpu/armv7/tegra124/Makefile
create mode 100644 arch/arm/cpu/armv7/tegra124/ap.c
diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile
index 409e6f5..616b6cc 100644
--- a/arch/arm/cpu/armv7/Makefile
+++ b/arch/arm/cpu/armv7/Makefile
@@ -59,6 +59,7 @@ obj-$(CONFIG_SOCFPGA) += socfpga/
obj-$(if $(filter stv0991,$(SOC)),y) += stv0991/
obj-$(CONFIG_ARCH_SUNXI) += sunxi/
obj-$(CONFIG_TEGRA20) += tegra20/
+obj-$(CONFIG_TEGRA124) += tegra124/
obj-$(CONFIG_U8500) += u8500/
obj-$(CONFIG_ARCH_UNIPHIER) += uniphier/
obj-$(CONFIG_VF610) += vf610/
diff --git a/arch/arm/cpu/armv7/tegra-common/Makefile
b/arch/arm/cpu/armv7/tegra-common/Makefile
index 463c260..89355ca 100644
--- a/arch/arm/cpu/armv7/tegra-common/Makefile
+++ b/arch/arm/cpu/armv7/tegra-common/Makefile
@@ -7,4 +7,5 @@
# SPDX-License-Identifier: GPL-2.0+
#
+obj-$(CONFIG_ARMV7_PSCI) += psci.o
obj-$(CONFIG_CMD_ENTERRCM) += cmd_enterrcm.o
diff --git a/arch/arm/cpu/armv7/tegra-common/psci.S
b/arch/arm/cpu/armv7/tegra-common/psci.S
new file mode 100644
index 000..b7501fb
--- /dev/null
+++ b/arch/arm/cpu/armv7/tegra-common/psci.S
@@ -0,0 +1,101 @@
+/*
+ * Copyright (C) 2014, NVIDIA
+ * Copyright (C) 2015, Siemens AG
+ *
+ * Authors:
+ * Thierry Reding tred...@nvidia.com
+ * Jan Kiszka jan.kis...@siemens.com
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include linux/linkage.h
+#include asm/psci.h
+
+ .pushsection ._secure.text, ax
+ .arch_extension sec
+
+#define TEGRA_SB_CSR_0 0x6000c200
+#define NS_RST_VEC_WR_DIS (1 1)
+
+#define TEGRA_RESET_EXCEPTION_VECTOR 0x6000f100
+
+#define TEGRA_FLOW_CTRL_BASE 0x60007000
+#define FLOW_CTRL_CPU_CSR 0x08
+#define CSR_ENABLE (1 0)
+#define CSR_IMMEDIATE_WAKE (1 3)
+#define CSR_WAIT_WFI_SHIFT 8
+#define FLOW_CTRL_CPU1_CSR 0x18
+
+@ converts CPU ID into FLOW_CTRL_CPUn_CSR offset
+.macro get_csr_reg cpu, ofs, tmp
+ cmp \cpu, #0@ CPU0?
+ lsl \tmp, \cpu, #3 @ multiple by 8 (register offset CPU1-3)
+ moveq \ofs, #FLOW_CTRL_CPU_CSR
+ addne \ofs, \tmp, #FLOW_CTRL_CPU1_CSR - 8
+.endm
+
+ENTRY(psci_arch_init)
+ mov r6, lr
+
+ mrc p15, 0, r5, c1, c1, 0 @ Read SCR
+ bic r5, r5, #1 @ Secure mode
+ mcr p15, 0, r5, c1, c1, 0 @ Write SCR
+ isb
+
+ @ lock reset vector
+ ldr r4, =TEGRA_SB_CSR_0
+ ldr r5, [r4]
+ orr r5, r5, #NS_RST_VEC_WR_DIS
+ str r5, [r4]
+
+ mrc p15, 0, r4, c0, c0, 5 @ MPIDR
+ and r4, r4, #7 @ number of CPUs in cluster
+ bl psci_get_cpu_stack_top
+ mov sp, r5
+
+ bx r6
+ENDPROC(psci_arch_init)
+
+ENTRY(psci_cpu_off)
+ bl psci_cpu_off_common
+
+ mrc p15, 0, r1, c0, c0, 5 @ MPIDR
+ and r1, r1, #7 @ number of CPUs in cluster
+
+ get_csr_reg r1, r2, r3
+
+ ldr r6, =TEGRA_FLOW_CTRL_BASE
+ mov r5, #(CSR_ENABLE)
+ add r5, r1, lsl #CSR_WAIT_WFI_SHIFT
+ str r5, [r6, r2]
+
+_loop: wfi
+ b _loop
+ENDPROC(psci_cpu_off)
+
+ENTRY(psci_cpu_on)
+ push{lr}
+
+ mov r4, r1
+ bl psci_get_cpu_stack_top @ get stack top of target CPU
+ str r2, [r5]@ store target PC at stack top
+ dsb
+
+ ldr r6, =TEGRA_RESET_EXCEPTION_VECTOR
+ ldr r5, =psci_cpu_entry
+ str r5, [r6]
+
+ get_csr_reg r1, r2, r3
+
+ ldr r6, =TEGRA_FLOW_CTRL_BASE
+ mov r5, #(CSR_IMMEDIATE_WAKE | CSR_ENABLE)
+ str r5, [r6, r2]
+
+ mov r0, #ARM_PSCI_RET_SUCCESS @ Return PSCI_RET_SUCCESS
+ pop {pc}
+ENDPROC(psci_cpu_on)
+
+ .globl psci_text_end
+psci_text_end:
+
[U-Boot] [PATCH v3 06/12] virt-dt: Allow reservation of secure region when in a RAM carveout
In this case the secure code lives in RAM, and hence the memory node in
the device tree needs to be adjusted. This avoids that the OS will map
and possibly access the reservation.
Add support for setting CONFIG_ARMV7_SECURE_RESERVE_SIZE to carve out
such a region. We only support cutting off memory from the beginning or
the end of a RAM bank as we do not want to increase their number (which
would happen if punching a hole) for simplicity reasons
This will be used in a subsequent patch for Jetson-TK1.
Signed-off-by: Jan Kiszka jan.kis...@siemens.com
---
arch/arm/cpu/armv7/virt-dt.c | 27 +++
arch/arm/include/asm/armv7.h | 1 +
arch/arm/lib/bootm-fdt.c | 5 +
3 files changed, 33 insertions(+)
diff --git a/arch/arm/cpu/armv7/virt-dt.c b/arch/arm/cpu/armv7/virt-dt.c
index ad19e4c..1d24437 100644
--- a/arch/arm/cpu/armv7/virt-dt.c
+++ b/arch/arm/cpu/armv7/virt-dt.c
@@ -16,6 +16,7 @@
*/
#include common.h
+#include errno.h
#include stdio_dev.h
#include linux/ctype.h
#include linux/types.h
@@ -88,6 +89,32 @@ static int fdt_psci(void *fdt)
return 0;
}
+int armv7_apply_memory_carveout(u64 *start, u64 *size)
+{
+#ifdef CONFIG_ARMV7_SECURE_RESERVE_SIZE
+ if (*start + *size CONFIG_ARMV7_SECURE_BASE ||
+ *start = (u64)CONFIG_ARMV7_SECURE_BASE +
+ CONFIG_ARMV7_SECURE_RESERVE_SIZE)
+ return 0;
+
+ /* carveout must be at the beginning or the end of the bank */
+ if (*start == CONFIG_ARMV7_SECURE_BASE ||
+ *start + *size == (u64)CONFIG_ARMV7_SECURE_BASE +
+ CONFIG_ARMV7_SECURE_RESERVE_SIZE) {
+ if (*size CONFIG_ARMV7_SECURE_RESERVE_SIZE) {
+ debug(Secure monitor larger than RAM bank!?\n);
+ return -EINVAL;
+ }
+ *size -= CONFIG_ARMV7_SECURE_RESERVE_SIZE;
+ if (*start == CONFIG_ARMV7_SECURE_BASE)
+ *start += CONFIG_ARMV7_SECURE_RESERVE_SIZE;
+ return 0;
+ }
+ debug(Secure monitor not located at beginning or end of RAM bank\n);
+ return -EINVAL;
+#endif
+}
+
int armv7_update_dt(void *fdt)
{
if (!armv7_boot_nonsec())
diff --git a/arch/arm/include/asm/armv7.h b/arch/arm/include/asm/armv7.h
index a13da23..e06dfc9 100644
--- a/arch/arm/include/asm/armv7.h
+++ b/arch/arm/include/asm/armv7.h
@@ -79,6 +79,7 @@ void v7_outer_cache_inval_range(u32 start, u32 end);
#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT)
int armv7_init_nonsec(void);
+int armv7_apply_memory_carveout(u64 *start, u64 *size);
int armv7_update_dt(void *fdt);
bool armv7_boot_nonsec(void);
diff --git a/arch/arm/lib/bootm-fdt.c b/arch/arm/lib/bootm-fdt.c
index d4f1578..7b88739 100644
--- a/arch/arm/lib/bootm-fdt.c
+++ b/arch/arm/lib/bootm-fdt.c
@@ -31,6 +31,11 @@ int arch_fixup_fdt(void *blob)
for (bank = 0; bank CONFIG_NR_DRAM_BANKS; bank++) {
start[bank] = bd-bi_dram[bank].start;
size[bank] = bd-bi_dram[bank].size;
+#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT)
+ ret = armv7_apply_memory_carveout(start[bank], size[bank]);
+ if (ret)
+ return ret;
+#endif
}
ret = fdt_fixup_memory_banks(blob, start, size, CONFIG_NR_DRAM_BANKS);
--
2.1.4
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3 07/12] tegra: Make tegra_powergate_power_on public
Will be used for unpowergating CPUs.
Signed-off-by: Jan Kiszka jan.kis...@siemens.com
---
arch/arm/cpu/tegra-common/powergate.c | 2 +-
arch/arm/include/asm/arch-tegra/powergate.h | 1 +
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/cpu/tegra-common/powergate.c
b/arch/arm/cpu/tegra-common/powergate.c
index 439cff3..6331cd4 100644
--- a/arch/arm/cpu/tegra-common/powergate.c
+++ b/arch/arm/cpu/tegra-common/powergate.c
@@ -44,7 +44,7 @@ static int tegra_powergate_set(enum tegra_powergate id, bool
state)
return -ETIMEDOUT;
}
-static int tegra_powergate_power_on(enum tegra_powergate id)
+int tegra_powergate_power_on(enum tegra_powergate id)
{
return tegra_powergate_set(id, true);
}
diff --git a/arch/arm/include/asm/arch-tegra/powergate.h
b/arch/arm/include/asm/arch-tegra/powergate.h
index 130b58b..2e491f1 100644
--- a/arch/arm/include/asm/arch-tegra/powergate.h
+++ b/arch/arm/include/asm/arch-tegra/powergate.h
@@ -33,6 +33,7 @@ enum tegra_powergate {
int tegra_powergate_sequence_power_up(enum tegra_powergate id,
enum periph_id periph);
+int tegra_powergate_power_on(enum tegra_powergate id);
int tegra_powergate_power_off(enum tegra_powergate id);
#endif
--
2.1.4
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3 08/12] tegra: Add ap_pm_init hook
This function will be used to initialize CPU power management for Tegra
SOCs. For now it does nothing.
Signed-off-by: Jan Kiszka jan.kis...@siemens.com
---
arch/arm/include/asm/arch-tegra/ap.h | 5 +
board/nvidia/common/board.c | 4
2 files changed, 9 insertions(+)
diff --git a/arch/arm/include/asm/arch-tegra/ap.h
b/arch/arm/include/asm/arch-tegra/ap.h
index 5c8be94..208db90 100644
--- a/arch/arm/include/asm/arch-tegra/ap.h
+++ b/arch/arm/include/asm/arch-tegra/ap.h
@@ -63,6 +63,11 @@ int tegra_get_chip(void);
*/
int tegra_get_sku_info(void);
+/**
+ * Initialize power management for application processors
+ */
+void ap_pm_init(void);
+
/* Do any chip-specific cache config */
void config_cache(void);
diff --git a/board/nvidia/common/board.c b/board/nvidia/common/board.c
index 80ef8fd..c62b3da 100644
--- a/board/nvidia/common/board.c
+++ b/board/nvidia/common/board.c
@@ -21,6 +21,7 @@
#include asm/arch/pwm.h
#endif
#include asm/arch/tegra.h
+#include asm/arch-tegra/ap.h
#include asm/arch-tegra/board.h
#include asm/arch-tegra/clk_rst.h
#include asm/arch-tegra/pmc.h
@@ -56,6 +57,7 @@ const struct tegra_sysinfo sysinfo = {
CONFIG_TEGRA_BOARD_STRING
};
+__weak void ap_pm_init(void) {}
__weak void pinmux_init(void) {}
__weak void pin_mux_usb(void) {}
__weak void pin_mux_spi(void) {}
@@ -96,6 +98,8 @@ int board_init(void)
clock_init();
clock_verify();
+ ap_pm_init();
+
#ifdef CONFIG_TEGRA_SPI
pin_mux_spi();
#endif
--
2.1.4
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3 10/12] jetson-tk1: Add PSCI configuration options and reserve secure code
From: Ian Campbell i...@hellion.org.uk The secure world code is relocated to the MB just below the top of 4G, we reserve it in the FDT (by setting CONFIG_ARMV7_SECURE_RESERVE_SIZE) but it is not protected in h/w. See next patch. Signed-off-by: Ian Campbell i...@hellion.org.uk Signed-off-by: Jan Kiszka jan.kis...@siemens.com --- arch/arm/cpu/armv7/tegra124/Kconfig | 2 ++ include/configs/jetson-tk1.h| 5 + 2 files changed, 7 insertions(+) diff --git a/arch/arm/cpu/armv7/tegra124/Kconfig b/arch/arm/cpu/armv7/tegra124/Kconfig index 88f627c..5114299 100644 --- a/arch/arm/cpu/armv7/tegra124/Kconfig +++ b/arch/arm/cpu/armv7/tegra124/Kconfig @@ -5,6 +5,8 @@ choice config TARGET_JETSON_TK1 bool NVIDIA Tegra124 Jetson TK1 board + select CPU_V7_HAS_NONSEC if !SPL_BUILD + select CPU_V7_HAS_VIRT if !SPL_BUILD config TARGET_NYAN_BIG bool Google/NVIDIA Nyan-big Chrombook diff --git a/include/configs/jetson-tk1.h b/include/configs/jetson-tk1.h index 0a79c7c..80c2952 100644 --- a/include/configs/jetson-tk1.h +++ b/include/configs/jetson-tk1.h @@ -81,4 +81,9 @@ #include tegra-common-usb-gadget.h #include tegra-common-post.h +#define CONFIG_ARMV7_PSCI 1 +/* Reserve top 1M for secure RAM */ +#define CONFIG_ARMV7_SECURE_BASE 0xfff0 +#define CONFIG_ARMV7_SECURE_RESERVE_SIZE 0x0010 + #endif /* __CONFIG_H */ -- 2.1.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3 12/12] tegra: Set CNTFRQ for secondary CPUs
We only set CNTFRQ in arch_timer_init for the boot CPU. But this has to happen for all cores. Fixing this resolves problems of KVM with emulating the generic timer/counter. Signed-off-by: Jan Kiszka jan.kis...@siemens.com --- arch/arm/cpu/armv7/tegra-common/psci.S | 13 + 1 file changed, 13 insertions(+) diff --git a/arch/arm/cpu/armv7/tegra-common/psci.S b/arch/arm/cpu/armv7/tegra-common/psci.S index b7501fb..63c9786 100644 --- a/arch/arm/cpu/armv7/tegra-common/psci.S +++ b/arch/arm/cpu/armv7/tegra-common/psci.S @@ -51,12 +51,25 @@ ENTRY(psci_arch_init) mrc p15, 0, r4, c0, c0, 5 @ MPIDR and r4, r4, #7 @ number of CPUs in cluster + + adr r5, _sys_clock_freq + cmp r4, #0 + + mrceq p15, 0, r7, c14, c0, 0 @ read CNTFRQ from CPU0 + streq r7, [r5] + + ldrne r7, [r5] + mcrne p15, 0, r7, c14, c0, 0 @ write CNTFRQ to CPU1..3 + bl psci_get_cpu_stack_top mov sp, r5 bx r6 ENDPROC(psci_arch_init) +_sys_clock_freq: + .word + ENTRY(psci_cpu_off) bl psci_cpu_off_common -- 2.1.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3 11/12] tegra124: Reserve secure RAM using MC_SECURITY_CFG{0, 1}_0
From: Ian Campbell i...@hellion.org.uk
These registers can be used to prevent non-secure world from accessing a
megabyte aligned region of RAM, use them to protect the u-boot secure monitor
code.
At first I tried to do this from s_init(), however this inexplicably causes
u-boot's networking (e.g. DHCP) to fail, while networking under Linux was fine.
So instead I have added a new weak arch function protect_secure_section()
called from relocate_secure_section() and reserved the region there. This is
better overall since it defers the reservation until after the sec vs. non-sec
decision (which can be influenced by an envvar) has been made when booting the
os.
Signed-off-by: Ian Campbell i...@hellion.org.uk
[Jan: tiny style adjustment]
Signed-off-by: Jan Kiszka jan.kis...@siemens.com
---
arch/arm/cpu/armv7/virt-v7.c | 5 +
arch/arm/cpu/tegra-common/ap.c | 15 +++
arch/arm/include/asm/system.h | 1 +
3 files changed, 21 insertions(+)
diff --git a/arch/arm/cpu/armv7/virt-v7.c b/arch/arm/cpu/armv7/virt-v7.c
index b69fd37..eb6195c 100644
--- a/arch/arm/cpu/armv7/virt-v7.c
+++ b/arch/arm/cpu/armv7/virt-v7.c
@@ -46,6 +46,10 @@ static unsigned long get_gicd_base_address(void)
#endif
}
+/* Define a specific version of this function to enable any available
+ * hardware protections for the reserved region */
+void __weak protect_secure_section(void) {}
+
static void relocate_secure_section(void)
{
#ifdef CONFIG_ARMV7_SECURE_BASE
@@ -54,6 +58,7 @@ static void relocate_secure_section(void)
memcpy((void *)CONFIG_ARMV7_SECURE_BASE, __secure_start, sz);
flush_dcache_range(CONFIG_ARMV7_SECURE_BASE,
CONFIG_ARMV7_SECURE_BASE + sz + 1);
+ protect_secure_section();
invalidate_icache_all();
#endif
}
diff --git a/arch/arm/cpu/tegra-common/ap.c b/arch/arm/cpu/tegra-common/ap.c
index a17dfd1..869a2ed 100644
--- a/arch/arm/cpu/tegra-common/ap.c
+++ b/arch/arm/cpu/tegra-common/ap.c
@@ -10,6 +10,7 @@
#include common.h
#include asm/io.h
#include asm/arch/gp_padctrl.h
+#include asm/arch/mc.h
#include asm/arch-tegra/ap.h
#include asm/arch-tegra/clock.h
#include asm/arch-tegra/fuse.h
@@ -154,6 +155,20 @@ static void init_pmc_scratch(void)
writel(odmdata, pmc-pmc_scratch20);
}
+#ifdef CONFIG_ARMV7_SECURE_RESERVE_SIZE
+void protect_secure_section(void)
+{
+ struct mc_ctlr *mc = (struct mc_ctlr *)NV_PA_MC_BASE;
+
+ /* Must be MB aligned */
+ BUILD_BUG_ON(CONFIG_ARMV7_SECURE_BASE 0xF);
+ BUILD_BUG_ON(CONFIG_ARMV7_SECURE_RESERVE_SIZE 0xF);
+
+ writel(CONFIG_ARMV7_SECURE_BASE, mc-mc_security_cfg0);
+ writel(CONFIG_ARMV7_SECURE_RESERVE_SIZE 20, mc-mc_security_cfg1);
+}
+#endif
+
void s_init(void)
{
/* Init PMC scratch memory */
diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
index 89f2294..21be69d 100644
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -76,6 +76,7 @@ void armv8_switch_to_el1(void);
void gic_init(void);
void gic_send_sgi(unsigned long sgino);
void wait_for_wakeup(void);
+void protect_secure_region(void);
void smp_kick_all_cpus(void);
void flush_l3_cache(void);
--
2.1.4
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3 01/12] ARM: Factor out reusable psci_cpu_off_common
Move parts of sunxi's psci_cpu_off into psci_cpu_off_common, namely
cache disabling and flushing, clrex and the disabling of SMP for the
dying CPU. These steps are apparently generic for ARMv7 and will be
reused for Tegra124 support.
Signed-off-by: Jan Kiszka jan.kis...@siemens.com
---
arch/arm/cpu/armv7/psci.S | 71 +
arch/arm/cpu/armv7/sunxi/psci.S | 63 +---
2 files changed, 72 insertions(+), 62 deletions(-)
diff --git a/arch/arm/cpu/armv7/psci.S b/arch/arm/cpu/armv7/psci.S
index bf11a34..d688607 100644
--- a/arch/arm/cpu/armv7/psci.S
+++ b/arch/arm/cpu/armv7/psci.S
@@ -99,4 +99,75 @@ _smc_psci:
pop {r4-r7, lr}
movspc, lr @ Return to the kernel
+/* Imported from Linux kernel */
+LENTRY(v7_flush_dcache_all)
+ dmb @ ensure ordering with previous
memory accesses
+ mrc p15, 1, r0, c0, c0, 1 @ read clidr
+ andsr3, r0, #0x700 @ extract loc from clidr
+ mov r3, r3, lsr #23 @ left align loc bit field
+ beq finished@ if loc is 0, then no need to
clean
+ mov r10, #0 @ start clean at cache level 0
+flush_levels:
+ add r2, r10, r10, lsr #1@ work out 3x current cache
level
+ mov r1, r0, lsr r2 @ extract cache type bits from
clidr
+ and r1, r1, #7 @ mask of the bits for current
cache only
+ cmp r1, #2 @ see what cache we have at
this level
+ blt skip@ skip if no cache, or just
i-cache
+ mrs r9, cpsr@ make cssrcsidr read atomic
+ mcr p15, 2, r10, c0, c0, 0 @ select current cache level in
cssr
+ isb @ isb to sych the new cssrcsidr
+ mrc p15, 1, r1, c0, c0, 0 @ read the new csidr
+ msr cpsr_c, r9
+ and r2, r1, #7 @ extract the length of the
cache lines
+ add r2, r2, #4 @ add 4 (line length offset)
+ ldr r4, =0x3ff
+ andsr4, r4, r1, lsr #3 @ find maximum number on the
way size
+ clz r5, r4 @ find bit position of way size
increment
+ ldr r7, =0x7fff
+ andsr7, r7, r1, lsr #13 @ extract max number of the
index size
+loop1:
+ mov r9, r7 @ create working copy of max
index
+loop2:
+ orr r11, r10, r4, lsl r5@ factor way and cache number
into r11
+ orr r11, r11, r9, lsl r2@ factor index number into r11
+ mcr p15, 0, r11, c7, c14, 2 @ clean invalidate by set/way
+ subsr9, r9, #1 @ decrement the index
+ bge loop2
+ subsr4, r4, #1 @ decrement the way
+ bge loop1
+skip:
+ add r10, r10, #2@ increment cache number
+ cmp r3, r10
+ bgt flush_levels
+finished:
+ mov r10, #0 @ swith back to cache level 0
+ mcr p15, 2, r10, c0, c0, 0 @ select current cache level in
cssr
+ dsb st
+ isb
+ bx lr
+ENDPROC(v7_flush_dcache_all)
+
+ENTRY(psci_cpu_off_common)
+ push{lr}
+
+ mrc p15, 0, r0, c1, c0, 0 @ SCTLR
+ bic r0, r0, #(1 2) @ Clear C bit
+ mcr p15, 0, r0, c1, c0, 0 @ SCTLR
+ isb
+ dsb
+
+ bl v7_flush_dcache_all
+
+ clrex @ Why???
+
+ mrc p15, 0, r0, c1, c0, 1 @ ACTLR
+ bic r0, r0, #(1 6) @ Clear SMP bit
+ mcr p15, 0, r0, c1, c0, 1 @ ACTLR
+ isb
+ dsb
+
+ pop {lr}
+ bx lr
+ENDPROC(psci_cpu_off_common)
+
.popsection
diff --git a/arch/arm/cpu/armv7/sunxi/psci.S b/arch/arm/cpu/armv7/sunxi/psci.S
index 5be497b..6785fdd 100644
--- a/arch/arm/cpu/armv7/sunxi/psci.S
+++ b/arch/arm/cpu/armv7/sunxi/psci.S
@@ -199,53 +199,6 @@ psci_cpu_on:
_target_pc:
.word 0
-/* Imported from Linux kernel */
-v7_flush_dcache_all:
- dmb @ ensure ordering with previous
memory accesses
- mrc p15, 1, r0, c0, c0, 1 @ read clidr
- andsr3, r0, #0x700 @ extract loc from clidr
- mov r3, r3, lsr #23 @ left align loc bit field
- beq finished@ if loc is 0, then no need to
clean
- mov r10, #0 @ start clean at cache level 0
-flush_levels:
- add r2, r10, r10, lsr #1@ work out
[U-Boot] [PATCH v3 05/12] tegra124: Add more registers to struct mc_ctlr
From: Ian Campbell i...@hellion.org.uk
I will need mc_security_cfg0/1 in a future patch and I added the rest while
debugging, so thought I might as well commit them.
Signed-off-by: Ian Campbell i...@hellion.org.uk
Signed-off-by: Jan Kiszka jan.kis...@siemens.com
---
arch/arm/include/asm/arch-tegra124/mc.h | 35 +++--
1 file changed, 33 insertions(+), 2 deletions(-)
diff --git a/arch/arm/include/asm/arch-tegra124/mc.h
b/arch/arm/include/asm/arch-tegra124/mc.h
index d526dfe..5557732 100644
--- a/arch/arm/include/asm/arch-tegra124/mc.h
+++ b/arch/arm/include/asm/arch-tegra124/mc.h
@@ -35,9 +35,40 @@ struct mc_ctlr {
u32 mc_emem_adr_cfg;/* offset 0x54 */
u32 mc_emem_adr_cfg_dev0; /* offset 0x58 */
u32 mc_emem_adr_cfg_dev1; /* offset 0x5C */
- u32 reserved3[12]; /* offset 0x60 - 0x8C */
+ u32 reserved3[4]; /* offset 0x60 - 0x6C */
+ u32 mc_security_cfg0; /* offset 0x70 */
+ u32 mc_security_cfg1; /* offset 0x74 */
+ u32 reserved4[6]; /* offset 0x7C - 0x8C */
u32 mc_emem_arb_reserved[28]; /* offset 0x90 - 0xFC */
- u32 reserved4[338]; /* offset 0x100 - 0x644 */
+ u32 reserved5[74]; /* offset 0x100 - 0x224 */
+ u32 mc_smmu_translation_enable_0; /* offset 0x228 */
+ u32 mc_smmu_translation_enable_1; /* offset 0x22C */
+ u32 mc_smmu_translation_enable_2; /* offset 0x230 */
+ u32 mc_smmu_translation_enable_3; /* offset 0x234 */
+ u32 mc_smmu_afi_asid; /* offset 0x238 */
+ u32 mc_smmu_avpc_asid; /* offset 0x23C */
+ u32 mc_smmu_dc_asid;/* offset 0x240 */
+ u32 mc_smmu_dcb_asid; /* offset 0x244 */
+ u32 reserved6[2]; /* offset 0x248 - 0x24C */
+ u32 mc_smmu_hc_asid;/* offset 0x250 */
+ u32 mc_smmu_hda_asid; /* offset 0x254 */
+ u32 mc_smmu_isp2_asid; /* offset 0x258 */
+ u32 reserved7[2]; /* offset 0x25C - 0x260 */
+ u32 mc_smmu_msenc_asid; /* offset 0x264 */
+ u32 mc_smmu_nv_asid;/* offset 0x268 */
+ u32 mc_smmu_nv2_asid; /* offset 0x26C */
+ u32 mc_smmu_ppcs_asid; /* offset 0x270 */
+ u32 mc_smmu_sata_asid; /* offset 0x274 */
+ u32 reserved8[1]; /* offset 0x278 */
+ u32 mc_smmu_vde_asid; /* offset 0x27C */
+ u32 mc_smmu_vi_asid;/* offset 0x280 */
+ u32 mc_smmu_vic_asid; /* offset 0x284 */
+ u32 mc_smmu_xusb_host_asid; /* offset 0x288 */
+ u32 mc_smmu_xusb_dev_asid; /* offset 0x28C */
+ u32 reserved9[1]; /* offset 0x290 */
+ u32 mc_smmu_tsec_asid; /* offset 0x294 */
+ u32 mc_smmu_ppcs1_asid; /* offset 0x298 */
+ u32 reserved10[235];/* offset 0x29C - 0x644 */
u32 mc_video_protect_bom; /* offset 0x648 */
u32 mc_video_protect_size_mb; /* offset 0x64c */
u32 mc_video_protect_reg_ctrl; /* offset 0x650 */
--
2.1.4
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3 02/12] ARM: Factor out reusable psci_cpu_entry
_sunxi_cpu_entry can be converted completely into a reusable psci_cpu_entry. Tegra124 will use it as well. Signed-off-by: Jan Kiszka jan.kis...@siemens.com --- arch/arm/cpu/armv7/psci.S | 19 +++ arch/arm/cpu/armv7/sunxi/psci.S | 21 ++--- 2 files changed, 21 insertions(+), 19 deletions(-) diff --git a/arch/arm/cpu/armv7/psci.S b/arch/arm/cpu/armv7/psci.S index d688607..e916d71 100644 --- a/arch/arm/cpu/armv7/psci.S +++ b/arch/arm/cpu/armv7/psci.S @@ -170,4 +170,23 @@ ENTRY(psci_cpu_off_common) bx lr ENDPROC(psci_cpu_off_common) +ENTRY(psci_cpu_entry) + @ Set SMP bit + mrc p15, 0, r0, c1, c0, 1 @ ACTLR + orr r0, r0, #(1 6) @ Set SMP bit + mcr p15, 0, r0, c1, c0, 1 @ ACTLR + isb + + bl _nonsec_init + bl psci_arch_init + + adr r0, _psci_target_pc + ldr r0, [r0] + b _do_nonsec_entry +ENDPROC(psci_cpu_entry) + +.globl _psci_target_pc +_psci_target_pc: + .word 0 + .popsection diff --git a/arch/arm/cpu/armv7/sunxi/psci.S b/arch/arm/cpu/armv7/sunxi/psci.S index 6785fdd..c3a8dc1 100644 --- a/arch/arm/cpu/armv7/sunxi/psci.S +++ b/arch/arm/cpu/armv7/sunxi/psci.S @@ -138,7 +138,7 @@ out:mcr p15, 0, r7, c1, c1, 0 @ r2 = target PC .globl psci_cpu_on psci_cpu_on: - adr r0, _target_pc + ldr r0, =_psci_target_pc str r2, [r0] dsb @@ -150,7 +150,7 @@ psci_cpu_on: mov r4, #1 lsl r4, r4, r1 - adr r6, _sunxi_cpu_entry + ldr r6, =psci_cpu_entry str r6, [r0, #0x1a4] @ PRIVATE_REG (boot vector) @ Assert reset on target CPU @@ -196,23 +196,6 @@ psci_cpu_on: mov r0, #ARM_PSCI_RET_SUCCESS @ Return PSCI_RET_SUCCESS mov pc, lr -_target_pc: - .word 0 - -_sunxi_cpu_entry: - @ Set SMP bit - mrc p15, 0, r0, c1, c0, 1 - orr r0, r0, #0x40 - mcr p15, 0, r0, c1, c0, 1 - isb - - bl _nonsec_init - bl psci_arch_init - - adr r0, _target_pc - ldr r0, [r0] - b _do_nonsec_entry - .globl psci_cpu_off psci_cpu_off: bl psci_cpu_off_common -- 2.1.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3 00/12] Add PSCI support for Jetson TK1/Tegra124 + CNTFRQ fix
Changes in v3:
- use memory node adjustment for RAM carveout instead of reservation
- style fixes
Find patches also under
https://github.com/siemens/u-boot/tree/jetson-tk1-v3
Jan
CC: Ian Campbell i...@hellion.org.uk
Ian Campbell (3):
tegra124: Add more registers to struct mc_ctlr
jetson-tk1: Add PSCI configuration options and reserve secure code
tegra124: Reserve secure RAM using MC_SECURITY_CFG{0, 1}_0
Jan Kiszka (9):
ARM: Factor out reusable psci_cpu_off_common
ARM: Factor out reusable psci_cpu_entry
ARM: Factor out reusable psci_get_cpu_stack_top
ARM: Put target PC for PSCI CPU_ON on per-CPU stack
virt-dt: Allow reservation of secure region when in a RAM carveout
tegra: Make tegra_powergate_power_on public
tegra: Add ap_pm_init hook
tegra124: Add PSCI support for Tegra124
tegra: Set CNTFRQ for secondary CPUs
arch/arm/cpu/armv7/Makefile | 1 +
arch/arm/cpu/armv7/psci.S | 100
arch/arm/cpu/armv7/sunxi/psci.S | 108 --
arch/arm/cpu/armv7/tegra-common/Makefile| 1 +
arch/arm/cpu/armv7/tegra-common/psci.S | 114
arch/arm/cpu/armv7/tegra124/Kconfig | 2 +
arch/arm/cpu/armv7/tegra124/Makefile| 7 ++
arch/arm/cpu/armv7/tegra124/ap.c| 44 +++
arch/arm/cpu/armv7/virt-dt.c| 27 +++
arch/arm/cpu/armv7/virt-v7.c| 5 ++
arch/arm/cpu/tegra-common/ap.c | 15
arch/arm/cpu/tegra-common/powergate.c | 2 +-
arch/arm/include/asm/arch-tegra/ap.h| 5 ++
arch/arm/include/asm/arch-tegra/powergate.h | 1 +
arch/arm/include/asm/arch-tegra124/flow.h | 5 ++
arch/arm/include/asm/arch-tegra124/mc.h | 35 -
arch/arm/include/asm/armv7.h| 1 +
arch/arm/include/asm/system.h | 1 +
arch/arm/lib/bootm-fdt.c| 5 ++
board/nvidia/common/board.c | 4 +
include/configs/jetson-tk1.h| 5 ++
21 files changed, 392 insertions(+), 96 deletions(-)
create mode 100644 arch/arm/cpu/armv7/tegra-common/psci.S
create mode 100644 arch/arm/cpu/armv7/tegra124/Makefile
create mode 100644 arch/arm/cpu/armv7/tegra124/ap.c
--
2.1.4
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3 03/11] Exynos542x: Add workaround for ARM errata 798870
On Wed, 18 Feb 2015 15:16:27 +0530
Akshay Saraswat aksha...@samsung.com wrote:
This patch adds workaround for ARM errata 798870 which says
If back-to-back speculative cache line fills (fill A and fill B) are
issued from the L1 data cache of a CPU to the L2 cache, the second
request (fill B) is then cancelled, and the second request would have
detected a hazard against a recent write or eviction (write B) to the
same cache line as fill B then the L2 logic might deadlock.
Signed-off-by: Kimoon Kim kimoon@samsung.com
Signed-off-by: Akshay Saraswat aksha...@samsung.com
Reviewed-by: Simon Glass s...@chromium.org
Tested-by: Simon Glass s...@chromium.org
---
Changes since v2:
- No change.
Changes since v1:
- Added Reviewed-by Tested-by.
- Added space before */ on line # 40.
arch/arm/cpu/armv7/exynos/lowlevel_init.c | 22 ++
1 file changed, 22 insertions(+)
diff --git a/arch/arm/cpu/armv7/exynos/lowlevel_init.c
b/arch/arm/cpu/armv7/exynos/lowlevel_init.c
index e36f2fa..7335a1e 100644
--- a/arch/arm/cpu/armv7/exynos/lowlevel_init.c
+++ b/arch/arm/cpu/armv7/exynos/lowlevel_init.c
@@ -46,6 +46,28 @@ enum {
#ifdef CONFIG_EXYNOS5420
/*
+ * Set L2ACTLR[7] to reissue any memory transaction in the L2 that has been
+ * stalled for 1024 cycles to verify that its hazard condition still exists.
+ */
Having the ARM errata number mentioned in the comment here would make
the purpose of this code much more clear to anyone looking at it later
in the future.
Also isn't this a general purpose Cortex-A15 r2pX workaround,
also potentially useful for the other non-Exynos SoCs too?
+void set_l2cache(void)
+{
+ uint32_t val;
+
+ /* Read MIDR for Primary Part Number */
+ mrc_midr(val);
+ val = (val 4);
+ val = 0xf;
+
+ /* L2ACTLR[7]: Enable hazard detect timeout for A15 */
+ if (val == 0xf) {
+ mrc_l2_aux_ctlr(val);
+ val |= (1 7);
+ mcr_l2_aux_ctlr(val);
+ mrc_l2_ctlr(val);
+ }
+}
+
+/*
* Pointer to this function is stored in iRam which is used
* for jump and power down of a specific core.
*/
--
Best regards,
Siarhei Siamashka
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH RFC 6/6] configs: smdk5250: Enable using XHCI and EHCI together
With driver model now we can enable both EHCI and XHCI on Exynos5250. Signed-off-by: Vivek Gautam gautam.vi...@samsung.com --- include/configs/exynos5-common.h|3 +++ include/configs/exynos5250-common.h |3 +++ include/configs/smdk5250.h |2 ++ 3 files changed, 8 insertions(+) diff --git a/include/configs/exynos5-common.h b/include/configs/exynos5-common.h index 0ba39a2..6f0e7f8 100644 --- a/include/configs/exynos5-common.h +++ b/include/configs/exynos5-common.h @@ -173,8 +173,11 @@ #define CONFIG_CMD_GPIO +#define CONFIG_DM + /* USB */ #define CONFIG_CMD_USB +#define CONFIG_DM_USB #define CONFIG_USB_STORAGE #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 diff --git a/include/configs/exynos5250-common.h b/include/configs/exynos5250-common.h index ae0e5ff..1843e25 100644 --- a/include/configs/exynos5250-common.h +++ b/include/configs/exynos5250-common.h @@ -41,6 +41,9 @@ /* I2C */ #define CONFIG_MAX_I2C_NUM 8 +/* USB */ +#define CONFIG_USB_MAX_CONTROLLER_COUNT2 + /* Display */ #define CONFIG_LCD #ifdef CONFIG_LCD diff --git a/include/configs/smdk5250.h b/include/configs/smdk5250.h index 3b06d30..27ba454 100644 --- a/include/configs/smdk5250.h +++ b/include/configs/smdk5250.h @@ -24,6 +24,8 @@ #define CONFIG_BOARD_COMMON #define CONFIG_ARCH_EARLY_INIT_R +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_EXYNOS #define CONFIG_USB_XHCI #define CONFIG_USB_XHCI_EXYNOS -- 1.7.10.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH RFC 5/6] arm: exynos5: Enable EHCI and XHCI hcds through device tree.
Add devices for XHCI-HCD and EHCI-HCD in exynos5 family.
Signed-off-by: Vivek Gautam gautam.vi...@samsung.com
---
arch/arm/dts/exynos5.dtsi |8
1 file changed, 8 insertions(+)
diff --git a/arch/arm/dts/exynos5.dtsi b/arch/arm/dts/exynos5.dtsi
index 238acb8..5cdf406 100644
--- a/arch/arm/dts/exynos5.dtsi
+++ b/arch/arm/dts/exynos5.dtsi
@@ -157,6 +157,14 @@
};
};
+ ehcihcd {
+ compatible = ehci-hcd;
+ };
+
+ xhcihcd {
+ compatible = xhci-hcd;
+ };
+
tmu@1006 {
compatible = samsung,exynos-tmu;
reg = 0x1006 0x1;
--
1.7.10.4
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3 02/11] Exynos542x: CPU: Power down all secondary cores
Hi Akshay,
This patch adds code to shutdown secondary cores.
When U-boot comes up, all secondary cores appear powered on,
which is undesirable and causes side effects while
initializing these cores in kernel.
Secondary core power down happens in following steps:
Step-1: After Exynos power-on, primary core starts executing first.
Step-2: In iROM code every core has to check 2 flags i.e.
addresses 0x02020028 0x02020004.
Could you provide exact names of those registers? I'm familiar with
Samsung SoCs but I cannot recall which one those are.
It would provide more readability to this commit message. Please fix it
globally.
Step-3: Initially 0x02020028 is 0 for all cores and 0x02020004 has a
jump address for primary core and 0 for all secondary cores.
Step-4: Therefore, primary core follows normal iROM execution and
jumps to BL1 eventually, whereas all secondary cores enter WFE.
Step-5: When primary core comes into function
secondary_cores_configure, it puts pointer to function
power_down_core into 0x02020004 and provides DSB and SEV for all
cores so that they may come out of WFE and jump to power_down_core
function. Step-6: And ultimately because of power_down_core all
secondary cores shut-down.
Signed-off-by: Kimoon Kim kimoon@samsung.com
Signed-off-by: Akshay Saraswat aksha...@samsung.com
---
Changes since v2:
- No change.
Changes since v1:
- Removed unnecessary macros.
- Changed names of few macros for better understanding.
- Added MPIDR bit assignment info comment in power_down_core.
arch/arm/cpu/armv7/exynos/exynos5_setup.h | 3 ++
arch/arm/cpu/armv7/exynos/lowlevel_init.c | 69
arch/arm/include/asm/arch-exynos/cpu.h|
5 ++ arch/arm/include/asm/arch-exynos/system.h | 87
+++ 4 files changed, 164 insertions(+)
diff --git a/arch/arm/cpu/armv7/exynos/exynos5_setup.h
b/arch/arm/cpu/armv7/exynos/exynos5_setup.h index 2eea48a..9073f50
100644 --- a/arch/arm/cpu/armv7/exynos/exynos5_setup.h
+++ b/arch/arm/cpu/armv7/exynos/exynos5_setup.h
@@ -700,6 +700,9 @@
#define CLK_DIV_CPERI1_VAL NOT_AVAILABLE
#else
+
+#define CPU_CONFIG_STATUS_OFFSET 0x80
+#define CPU_RST_FLAG_VAL 0xFCBA0D10
#define PAD_RETENTION_DRAM_COREBLK_VAL 0x1000
/* APLL_CON1 */
diff --git a/arch/arm/cpu/armv7/exynos/lowlevel_init.c
b/arch/arm/cpu/armv7/exynos/lowlevel_init.c index 83e1dcf..e36f2fa
100644 --- a/arch/arm/cpu/armv7/exynos/lowlevel_init.c
+++ b/arch/arm/cpu/armv7/exynos/lowlevel_init.c
@@ -31,7 +31,9 @@
#include asm/arch/tzpc.h
#include asm/arch/periph.h
#include asm/arch/pinmux.h
+#include asm/arch/system.h
#include common_setup.h
+#include exynos5_setup.h
/* These are the things we can do during low-level init */
enum {
@@ -42,6 +44,68 @@ enum {
DO_POWER= 1 4,
};
+#ifdef CONFIG_EXYNOS5420
+/*
+ * Pointer to this function is stored in iRam which is used
+ * for jump and power down of a specific core.
+ */
+static void power_down_core(void)
+{
+ uint32_t tmp, core_id, core_config;
+
+ /* Get the unique core id */
+ /*
+ * Multiprocessor Affinity Register
+ * [11:8] Cluster ID
+ * [1:0]CPU ID
+ */
+ mrc_mpafr(core_id);
+ tmp = core_id 0x3;
+ core_id = (core_id 6) ~3;
+ core_id |= tmp;
+ core_id = 0x3f;
+
+ /* Set the status of the core to low */
+ core_config = (core_id * CPU_CONFIG_STATUS_OFFSET);
+ core_config += EXYNOS5420_CPU_CONFIG_BASE;
+ writel(0x0, core_config);
+
+ /* Core enter WFI */
+ wfi();
+}
+
+/*
+ * Configurations for secondary cores are inapt at this stage.
+ * Reconfigure secondary cores. Shutdown and change the status
+ * of all cores except the primary core.
+ */
+static void secondary_cores_configure(void)
+{
+ uint32_t core_id;
+
+ /* Store jump address for power down of secondary cores */
+ writel((uint32_t)power_down_core, CONFIG_PHY_IRAM_BASE +
0x4); +
+ /* Need all core power down check */
+ dsb();
+ sev();
+
+ /*
+ * Power down all cores(secondary) while primary core must
+ * wait for all cores to go down.
+ */
+ for (core_id = 1; core_id != CONFIG_CORE_COUNT; core_id++) {
+ while ((readl(EXYNOS5420_CPU_STATUS_BASE
+ + (core_id * CPU_CONFIG_STATUS_OFFSET))
+ 0xff) != 0x0) {
+ isb();
+ sev();
+ }
+ isb();
+ }
+}
+#endif
+
int do_lowlevel_init(void)
{
uint32_t reset_status;
@@ -49,6 +113,11 @@ int do_lowlevel_init(void)
arch_cpu_init();
+#ifdef CONFIG_EXYNOS5420
+ /* Reconfigure secondary cores */
+ secondary_cores_configure();
+#endif
+
reset_status = get_reset_status();
switch (reset_status) {
diff
Re: [U-Boot] [PATCH 3/4] sunxi: video: Add support for tl059wv5c0 lcd panels
On Mon, 2015-02-16 at 23:25 +0100, Hans de Goede wrote:
Add support for the 6 480x800 tl059wv5c0 panel used on e.g. Utoo P66 and
Aigo M60/M608/M606 tablets.
Signed-off-by: Hans de Goede hdego...@redhat.com
All 4 patches: Acked-by: Ian Campbell i...@hellion.org.uk
I a couple of small comments on this one, which you can either ignore or
fixup as you commit:
---
board/sunxi/Kconfig | 8
drivers/video/sunxi_display.c | 7 +++
2 files changed, 15 insertions(+)
diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig
index ef59e21..19e7286 100644
--- a/board/sunxi/Kconfig
+++ b/board/sunxi/Kconfig
@@ -411,6 +411,14 @@ config VIDEO_LCD_PANEL_HITACHI_TX18D42VM
---help---
7.85 1024x768 Hitachi tx18d42vm LCD panel support
+config VIDEO_LCD_TL059WV5C0
+ bool tl059wv5c0 LCD panel
+ select VIDEO_LCD_PANEL_I2C
+ select VIDEO_LCD_IF_PARALLEL
+ ---help---
+ Say Y here to add support for the 6 480x800 tl059wv5c0 panel used
+ on e.g. Utoo P66 and Aigo M60/M608/M606 tablets.
Say Y doesn't really make sense within a choice option. Better to
follow the lead of the Hitachi panel above and '6 480x800 tl059wv5c0
panel'. I'm not sure a non-exhaustive list of boards/tablets is useful
either -- presumably if we know to list them here we also know to enable
the option in the defconfig.
@@ -1030,6 +1031,12 @@ static void sunxi_mode_set(const struct ctfb_res_modes
*mode,
mdelay(50); /* Wait for lcd controller power on */
hitachi_tx18d42vm_init();
}
+ if (IS_ENABLED(CONFIG_VIDEO_LCD_TL059WV5C0)) {
+ unsigned int orig_i2c_bus = i2c_get_bus_num();
+ i2c_set_bus_num(CONFIG_VIDEO_LCD_I2C_BUS);
I see that you save and restore the value but it might be nice for the
relevant axp drivers to also call this using CONFIG_SYS_SPD_BUS_NUM?
(I'm assuming it is set initially to this via i2c_init_all()?)
Ian.
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3 01/11] Exynos542x: Config: Add various configs
This patch adds iRAM, CPU state and low power configs which are the addresses acting as flag registers. iROM code checks CONFIG_LOWPOWER_FLAG address. If it is equal to CONFIG_LOWPOWER_EN then it jumps to the address (0x0202+CPUID*4). This is a part of iROM logic. Rest other flags are being used at various places during kernel switching and reset. They are nowhere documented because they are part programming. These configs are serving as flags for us because they are representing the addresses in iRAM which we are using for storing and extracting CPU Status and GIC status. Signed-off-by: Akshay Saraswat aksha...@samsung.com Reviewed-by: Simon Glass s...@chromium.org Tested-by: Simon Glass s...@chromium.org --- Changes since v2: - No change. Changes since v1: - Added Reviewed-by Tested-by. - Removed unnecessary CONFIGS. include/configs/exynos5420-common.h | 16 1 file changed, 16 insertions(+) diff --git a/include/configs/exynos5420-common.h b/include/configs/exynos5420-common.h index fe72bd0..b42dab7 100644 --- a/include/configs/exynos5420-common.h +++ b/include/configs/exynos5420-common.h @@ -38,4 +38,20 @@ #define CONFIG_BOARD_REV_GPIO_COUNT2 +#define CONFIG_PHY_IRAM_BASE 0x0202 + +/* Address for relocating helper code (Last 4 KB of IRAM) */ +#define CONFIG_EXYNOS_RELOCATE_CODE_BASE (CONFIG_IRAM_TOP - 0x1000) + +/* + * Low Power settings + */ +#define CONFIG_LOWPOWER_FLAG 0x02020028 +#define CONFIG_LOWPOWER_ADDR 0x0202002C + +/* + * Number of CPUs available + */ +#define CONFIG_CORE_COUNT 0x8 + #endif /* __CONFIG_EXYNOS5420_H */ -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH RFC 1/6] usb: Rename usb_submit_int_msg() API to usb_int_msg()
Until yet usb_**_msg() APIs don't contain the string 'submit'.
Rename it to make things uniform. This is also helping while
adding a host translational layer wherein we are using
usb_submit_**_msg string to name APIs.
Signed-off-by: Vivek Gautam gautam.vi...@samsung.com
---
common/usb.c |4 ++--
common/usb_kbd.c |4 ++--
common/usb_storage.c |2 +-
include/usb.h|2 +-
4 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/common/usb.c b/common/usb.c
index 32e15cd..849df27 100644
--- a/common/usb.c
+++ b/common/usb.c
@@ -162,10 +162,10 @@ int usb_disable_asynch(int disable)
/*
* submits an Interrupt Message
*/
-int usb_submit_int_msg(struct usb_device *dev, unsigned long pipe,
+int usb_int_msg(struct usb_device *dev, unsigned long pipe,
void *buffer, int transfer_len, int interval)
{
- return submit_int_msg(dev, pipe, buffer, transfer_len, interval);
+ return usb_submit_int_msg(dev, pipe, buffer, transfer_len, interval);
}
/*
diff --git a/common/usb_kbd.c b/common/usb_kbd.c
index ecc3085..d5d33a5 100644
--- a/common/usb_kbd.c
+++ b/common/usb_kbd.c
@@ -313,7 +313,7 @@ static inline void usb_kbd_poll_for_event(struct usb_device
*dev)
struct usb_kbd_pdata *data = dev-privptr;
/* Submit a interrupt transfer request */
- usb_submit_int_msg(dev, data-intpipe, data-new[0], data-intpktsize,
+ usb_int_msg(dev, data-intpipe, data-new[0], data-intpktsize,
data-intinterval);
usb_kbd_irq_worker(dev);
@@ -458,7 +458,7 @@ static int usb_kbd_probe(struct usb_device *dev, unsigned
int ifnum)
data-intinterval);
if (!data-intq) {
#else
- if (usb_submit_int_msg(dev, data-intpipe, data-new, data-intpktsize,
+ if (usb_int_msg(dev, data-intpipe, data-new, data-intpktsize,
data-intinterval) 0) {
#endif
printf(Failed to get keyboard state from device %04x:%04x\n,
diff --git a/common/usb_storage.c b/common/usb_storage.c
index 1411737..7094eea 100644
--- a/common/usb_storage.c
+++ b/common/usb_storage.c
@@ -599,7 +599,7 @@ static int usb_stor_CBI_get_status(ccb *srb, struct us_data
*us)
int timeout;
us-ip_wanted = 1;
- submit_int_msg(us-pusb_dev, us-irqpipe,
+ usb_int_msg(us-pusb_dev, us-irqpipe,
(void *) us-ip_data, us-irqmaxp, us-irqinterval);
timeout = 1000;
while (timeout--) {
diff --git a/include/usb.h b/include/usb.h
index a8fee0b..d1576b2 100644
--- a/include/usb.h
+++ b/include/usb.h
@@ -252,7 +252,7 @@ int usb_control_msg(struct usb_device *dev, unsigned int
pipe,
void *data, unsigned short size, int timeout);
int usb_bulk_msg(struct usb_device *dev, unsigned int pipe,
void *data, int len, int *actual_length, int timeout);
-int usb_submit_int_msg(struct usb_device *dev, unsigned long pipe,
+int usb_int_msg(struct usb_device *dev, unsigned long pipe,
void *buffer, int transfer_len, int interval);
int usb_disable_asynch(int disable);
int usb_maxpacket(struct usb_device *dev, unsigned long pipe);
--
1.7.10.4
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH RFC 2/6] dm: usb: Make necessary changes in framework for driver model
Add wrapper functions for usb layer operations for control, bulk,
interrupt transfers to accomodate support for driver model.
Signed-off-by: Vivek Gautam gautam.vi...@samsung.com
---
common/usb.c | 99
common/usb_hub.c |2 +-
include/dm/uclass-id.h |1 +
include/usb.h | 60 +++--
4 files changed, 142 insertions(+), 20 deletions(-)
diff --git a/common/usb.c b/common/usb.c
index 849df27..407cc30 100644
--- a/common/usb.c
+++ b/common/usb.c
@@ -29,6 +29,7 @@
#include common.h
#include command.h
#include asm/processor.h
+#include dm/uclass.h
#include linux/compiler.h
#include linux/ctype.h
#include asm/byteorder.h
@@ -45,12 +46,83 @@ static struct usb_device usb_dev[USB_MAX_DEVICE];
static int dev_index;
static int asynch_allowed;
+static struct udevice *udev_usb;
+
char usb_started; /* flag for the started/stopped USB status */
#ifndef CONFIG_USB_MAX_CONTROLLER_COUNT
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
#endif
+#ifdef CONFIG_DM_USB
+/* Wrappers for Driver model */
+static inline int _usb_lowlevel_init(int index, enum usb_init_type init,
+ void **ctrl)
+{
+ return usb_lowlevel_init(index, USB_INIT_HOST, ctrl, udev_usb);
+}
+
+static inline int _usb_lowlevel_stop(int index)
+{
+ return usb_lowlevel_stop(index, udev_usb);
+}
+
+static inline int _usb_submit_control_msg(struct usb_device *dev,
+ unsigned long pipe, void *data,
+ int transfer_len, struct devrequest *setup)
+{
+ return usb_submit_control_msg(dev, pipe, data, transfer_len,
+ setup, dev-udev_usb);
+}
+
+static inline int _usb_submit_bulk_msg(struct usb_device *dev,
+ unsigned int pipe, void *data, int transfer_len)
+{
+ return usb_submit_bulk_msg(dev, pipe, data, transfer_len,
+ dev-udev_usb);
+}
+
+static inline int _usb_submit_int_msg(struct usb_device *dev,
+ unsigned long pipe, void *data,
+ int transfer_len, int interval)
+{
+ return usb_submit_int_msg(dev, pipe, data, transfer_len,
+ interval, dev-udev_usb);
+}
+#else
+static inline int _usb_lowlevel_init(int index, enum usb_init_type init,
+ void **ctrl)
+{
+ return usb_lowlevel_init(index, USB_INIT_HOST, ctrl);
+}
+
+static inline int _usb_lowlevel_stop(int index)
+{
+ return usb_lowlevel_stop(index);
+}
+
+static inline int _usb_submit_control_msg(struct usb_device *dev,
+ unsigned long pipe, void *data,
+ int transfer_len, struct devrequest *setup)
+{
+ return usb_submit_control_msg(dev, pipe, data, transfer_len, setup);
+}
+
+static inline int _usb_submit_bulk_msg(struct usb_device *dev,
+ unsigned int pipe, void *data, int transfer_len)
+{
+ return usb_submit_bulk_msg(dev, pipe, data, transfer_len);
+}
+
+static inline int _usb_submit_int_msg(struct usb_device *dev,
+ unsigned long pipe, void *data,
+ int transfer_len, int interval)
+{
+ return usb_submit_int_msg(dev, pipe, data, transfer_len, interval);
+}
+#endif
+
+
/***
* Init USB Device
*/
@@ -74,9 +146,20 @@ int usb_init(void)
/* init low_level USB */
for (i = 0; i CONFIG_USB_MAX_CONTROLLER_COUNT; i++) {
+#ifdef CONFIG_DM_USB
+ /* Get the udevice here for given index */
+ uclass_get_device(UCLASS_USB, i, udev_usb);
+#else
+ udev_usb = -ERR_PTR(ENOSYS);
+#endif
+
+ /* Now this udev is a pointer to the particular controller
+* driver, which we can use now.
+*/
+
/* init low_level USB */
printf(USB%d: , i);
- ret = usb_lowlevel_init(i, USB_INIT_HOST, ctrl);
+ ret = _usb_lowlevel_init(i, USB_INIT_HOST, ctrl);
if (ret == -ENODEV) { /* No such device. */
puts(Port not available.\n);
controllers_initialized++;
@@ -94,7 +177,7 @@ int usb_init(void)
controllers_initialized++;
start_index = dev_index;
printf(scanning bus %d for devices... , i);
- dev = usb_alloc_new_device(ctrl);
+ dev = usb_alloc_new_device(ctrl, udev_usb);
/*
* device 0 is always present
* (root hub, so let it analyze)
@@ -132,7 +215,7 @@ int usb_stop(void)
usb_hub_reset();
for (i = 0; i
[U-Boot] [PATCH RFC 3/6] dm: usb-host: Add UCLASS driver for USB
Adding a UCLASS driver for USB based on driver-model, to facilitate
binding mutiple host-controllers to their respective drivers, and
thereby enable using mutiple controllers simultaneously on a platform.
Signed-off-by: Vivek Gautam gautam.vi...@samsung.com
---
drivers/usb/host/Kconfig |9
drivers/usb/host/Makefile |3 ++
drivers/usb/host/usb-uclass.c | 107 +
3 files changed, 119 insertions(+)
create mode 100644 drivers/usb/host/usb-uclass.c
diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index 30d1457..fceacbb 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -3,6 +3,15 @@
#
comment USB Host Controller Drivers
+config DM_USB
+ bool USB Driver model support
+ ---help---
+ Driver model support for USB host controller drivers.
+ This will allow use of mutiple kinds of host controllers viz. OHCI,
+ EHCI, XHCI, etc simultaneously which was not possible till now.
+ Say 'y' if you have mutiple types of controllers on your boards
+ and would like to enable support for all of them.
+
config USB_XHCI_HCD
bool xHCI HCD (USB 3.0) support
---help---
diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
index 66d6e9a..d54e2a7 100644
--- a/drivers/usb/host/Makefile
+++ b/drivers/usb/host/Makefile
@@ -5,6 +5,9 @@
# SPDX-License-Identifier: GPL-2.0+
#
+# usb driver-model
+obj-$(CONFIG_DM_USB) += usb-uclass.o
+
# ohci
obj-$(CONFIG_USB_OHCI_NEW) += ohci-hcd.o
obj-$(CONFIG_USB_ATMEL) += ohci-at91.o
diff --git a/drivers/usb/host/usb-uclass.c b/drivers/usb/host/usb-uclass.c
new file mode 100644
index 000..e7a97ec
--- /dev/null
+++ b/drivers/usb/host/usb-uclass.c
@@ -0,0 +1,107 @@
+/*
+ * Copyright (C) 2014 Samsung Electronics Co.Ltd
+ *
+ * Provides a smooth translation from usb_*() APIs from
+ * core usb drivers to controller drivers, enabling simultaneous
+ * use of different types of controller at once.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+
+#include common.h
+#include dm.h
+#include errno.h
+#include linux/err.h
+#include asm/io.h
+#include usb.h
+//#include linux/list.h
+
+//DECLARE_GLOBAL_DATA_PTR;
+
+UCLASS_DRIVER(usb) = {
+ .name = usb,
+ .id = UCLASS_USB,
+};
+
+int usb_lowlevel_init(int index, enum usb_init_type init,
+ void **controller, struct udevice *udev_usb)
+{
+ const struct usb_ops *ops;
+
+ if (IS_ERR(udev_usb))
+ return -EINVAL;
+
+ ops = device_get_ops(udev_usb);
+
+ if (!ops-lowlevel_init)
+ return -ENOSYS;
+
+ return ops-lowlevel_init(index, init, controller);
+}
+
+int usb_lowlevel_stop(int index, struct udevice *udev_usb)
+{
+ const struct usb_ops *ops;
+
+ if (IS_ERR(udev_usb))
+ return -EINVAL;
+
+ ops = device_get_ops(udev_usb);
+
+ if (!ops-lowlevel_stop)
+ return -ENOSYS;
+
+ return ops-lowlevel_stop(index);
+}
+
+int usb_submit_bulk_msg(struct usb_device *dev, unsigned long pipe,
+ void *buffer, int transfer_len,
+ struct udevice *udev_usb)
+{
+ const struct usb_ops *ops;
+
+ if (IS_ERR(udev_usb))
+ return -EINVAL;
+
+ ops = device_get_ops(udev_usb);
+
+ if (!ops-submit_bulk_msg)
+ return -ENOSYS;
+
+ return ops-submit_bulk_msg(dev, pipe, buffer, transfer_len);
+}
+
+int usb_submit_control_msg(struct usb_device *dev, unsigned long pipe,
+ void *buffer, int transfer_len,
+ struct devrequest *setup, struct udevice *udev_usb)
+{
+ const struct usb_ops *ops;
+
+ if (IS_ERR(udev_usb))
+ return -EINVAL;
+
+ ops = device_get_ops(udev_usb);
+
+ if (!ops-submit_ctrl_msg)
+ return -ENOSYS;
+
+ return ops-submit_ctrl_msg(dev,pipe, buffer, transfer_len, setup);
+}
+
+int usb_submit_int_msg(struct usb_device *dev, unsigned long pipe,
+ void *buffer, int transfer_len,
+ int interval, struct udevice *udev_usb)
+{
+ const struct usb_ops *ops;
+
+ if (IS_ERR(udev_usb))
+ return -EINVAL;
+
+ ops = device_get_ops(udev_usb);
+
+ if (!ops-submit_int_msg)
+ return -ENOSYS;
+
+ return ops-submit_int_msg(dev, pipe, buffer, transfer_len, interval);
+}
--
1.7.10.4
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH RFC 4/6] dm: usb-host: Add support for driver model in o/e/xhci.
Adding support for driver model and necessary callbacks
in ohci/ehci/xhci.
Signed-off-by: Vivek Gautam gautam.vi...@samsung.com
---
drivers/usb/host/ehci-hcd.c | 36
drivers/usb/host/ohci-hcd.c | 35 ---
drivers/usb/host/xhci.c | 34 +++---
3 files changed, 83 insertions(+), 22 deletions(-)
diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c
index f1fb190..6320b98 100644
--- a/drivers/usb/host/ehci-hcd.c
+++ b/drivers/usb/host/ehci-hcd.c
@@ -930,13 +930,13 @@ unknown:
return -1;
}
-int usb_lowlevel_stop(int index)
+int ehci_lowlevel_stop(int index)
{
ehci_shutdown(ehcic[index]);
return ehci_hcd_stop(index);
}
-int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
+int ehci_lowlevel_init(int index, enum usb_init_type init, void **controller)
{
uint32_t reg;
uint32_t cmd;
@@ -1065,8 +1065,8 @@ done:
}
int
-submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
- int length)
+ehci_submit_bulk_msg(struct usb_device *dev, unsigned long pipe,
+ void *buffer, int length)
{
if (usb_pipetype(pipe) != PIPE_BULK) {
@@ -1077,8 +1077,8 @@ submit_bulk_msg(struct usb_device *dev, unsigned long
pipe, void *buffer,
}
int
-submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
- int length, struct devrequest *setup)
+ehci_submit_control_msg(struct usb_device *dev, unsigned long pipe,
+ void *buffer, int length, struct devrequest *setup)
{
struct ehci_ctrl *ctrl = dev-controller;
@@ -1387,8 +1387,8 @@ out:
}
int
-submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
- int length, int interval)
+ehci_submit_int_msg(struct usb_device *dev, unsigned long pipe,
+ void *buffer, int length, int interval)
{
void *backbuffer;
struct int_queue *queue;
@@ -1423,3 +1423,23 @@ submit_int_msg(struct usb_device *dev, unsigned long
pipe, void *buffer,
/* everything worked out fine */
return result;
}
+
+static const struct udevice_id ehci_hcd_id[] = {
+ { ehci-hcd, 0 },
+ { },
+};
+
+static const struct usb_ops ehci_ops = {
+ .lowlevel_init = ehci_lowlevel_init,
+ .lowlevel_stop = ehci_lowlevel_stop,
+ .submit_ctrl_msg = ehci_submit_control_msg,
+ .submit_bulk_msg = ehci_submit_bulk_msg,
+ .submit_int_msg = ehci_submit_int_msg,
+};
+
+U_BOOT_DRIVER(ehci_hcd_drv) = {
+ .name = ehci_hcd_drv,
+ .of_match = ehci_hcd_id,
+ .id = UCLASS_USB,
+ .ops= ehci_ops,
+};
diff --git a/drivers/usb/host/ohci-hcd.c b/drivers/usb/host/ohci-hcd.c
index 97a7ede..3bfc295 100644
--- a/drivers/usb/host/ohci-hcd.c
+++ b/drivers/usb/host/ohci-hcd.c
@@ -1465,15 +1465,15 @@ int submit_common_msg(struct usb_device *dev, unsigned
long pipe, void *buffer,
}
/* submit routines called from usb.c */
-int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
- int transfer_len)
+int ohci_submit_bulk_msg(struct usb_device *dev, unsigned long pipe,
+ void *buffer, int transfer_len)
{
info(submit_bulk_msg);
return submit_common_msg(dev, pipe, buffer, transfer_len, NULL, 0);
}
-int submit_control_msg(struct usb_device *dev, unsigned long pipe, void
*buffer,
- int transfer_len, struct devrequest *setup)
+int ohci_submit_control_msg(struct usb_device *dev, unsigned long pipe,
+ void *buffer, int transfer_len, struct devrequest *setup)
{
int maxsize = usb_maxpacket(dev, pipe);
@@ -1499,7 +1499,7 @@ int submit_control_msg(struct usb_device *dev, unsigned
long pipe, void *buffer,
return submit_common_msg(dev, pipe, buffer, transfer_len, setup, 0);
}
-int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
+int ohci_submit_int_msg(struct usb_device *dev, unsigned long pipe, void
*buffer,
int transfer_len, int interval)
{
info(submit_int_msg);
@@ -1748,7 +1748,8 @@ static void hc_release_ohci(ohci_t *ohci)
*/
static char ohci_inited = 0;
-int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
+int ohci_lowlevel_init(int index, enum usb_init_type init,
+ void **controller)
{
#ifdef CONFIG_PCI_OHCI
pci_dev_t pdev;
@@ -1854,7 +1855,7 @@ int usb_lowlevel_init(int index, enum usb_init_type init,
void **controller)
return 0;
}
-int usb_lowlevel_stop(int index)
+int ohci_lowlevel_stop(int index)
{
/* this gets called really early - before the controller has */
/* even been initialized! */
@@ -1880,3 +1881,23 @@ int usb_lowlevel_stop(int index)
ohci_inited = 0;
return 0;
}
+
+static const struct udevice_id
[U-Boot] [PATCH RFC v2 0/6] usb: host: Add driver model support
Hi Marek, Simon, This patch-series comes as a update for an earlier posted series[1] [PATCH RFC 0/2] usb: host: Add a wrapper layer for mutiple host support which was posted long back. We had discussion to introduce the driver model instead of the approach used in [1]. The driver model seems pretty straight-forward and easier to implement besides giving a clean approach to use multiple host controller types, viz. EHCI, XHCI or OHCI simultaneously on a platform which has such provision. It's rather bad on my side that it took so long to post the updated version. Got busy with the projects. :-( So here's the RFC-v2 which implements the driver model approach. I have added support on OHCI, EHCI and XHCI and enabled EHCI and XHCI on Exynos5250 machines. Though not tested thoroughly, i can see EHCI and XHCI working together (enumerating the Root hubs). Let me know you comments on what you think of current approach. Thanks Vivek [1] [PATCH RFC 0/2] usb: host: Add a wrapper layer for mutiple host support http://lists.denx.de/pipermail/u-boot/2014-June/182559.html Vivek Gautam (6): usb: Rename usb_submit_int_msg() API to usb_int_msg() dm: usb: Make necessary changes in framework for driver model dm: usb-host: Add UCLASS driver for USB dm: usb-host: Add support for driver model in o/e/xhci. arm: exynos5: Enable EHCI and XHCI hcds through device tree. configs: smdk5250: Enable using XHCI and EHCI together arch/arm/dts/exynos5.dtsi |8 +++ common/usb.c| 101 ++--- common/usb_hub.c|2 +- common/usb_kbd.c|4 +- common/usb_storage.c|2 +- drivers/usb/host/Kconfig|9 +++ drivers/usb/host/Makefile |3 + drivers/usb/host/ehci-hcd.c | 36 +--- drivers/usb/host/ohci-hcd.c | 35 +--- drivers/usb/host/usb-uclass.c | 107 +++ drivers/usb/host/xhci.c | 34 --- include/configs/exynos5-common.h|3 + include/configs/exynos5250-common.h |3 + include/configs/smdk5250.h |2 + include/dm/uclass-id.h |1 + include/usb.h | 62 +++- 16 files changed, 365 insertions(+), 47 deletions(-) create mode 100644 drivers/usb/host/usb-uclass.c -- 1.7.10.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/4] dm: gpio: extend gpio api by dm_gpio_set_pull()
Hello,
On 02/18/2015 06:01 AM, Simon Glass wrote:
+Stephen who might have an opinion on this.
Hi Przemyslaw,
On 17 February 2015 at 06:09, Przemyslaw Marczak p.marc...@samsung.com wrote:
This commits extends:
- dm gpio ops by: 'set_pull' call
- dm gpio uclass by: dm_gpio_set_pull() function
The pull mode is not defined so should be driver specific.
It's good to implement this, but I think you should try to have a
standard interface. You could define the options you want to support
and pass in a standard value.
Otherwise we are not really providing a driver abstraction, only an interface.
Ok, I will change this.
Signed-off-by: Przemyslaw Marczak p.marc...@samsung.com
CC: Simon Glass s...@chromium.org
---
drivers/gpio/gpio-uclass.c | 12
include/asm-generic/gpio.h | 12
2 files changed, 24 insertions(+)
diff --git a/drivers/gpio/gpio-uclass.c b/drivers/gpio/gpio-uclass.c
index a69bbd2..48b31c2 100644
--- a/drivers/gpio/gpio-uclass.c
+++ b/drivers/gpio/gpio-uclass.c
@@ -321,6 +321,18 @@ int dm_gpio_set_value(struct gpio_desc *desc, int value)
return 0;
}
+int dm_gpio_set_pull(struct gpio_desc *desc, int pull)
+{
+ int ret;
+
+ ret = check_reserved(desc, set_pull);
+ if (ret)
+ return ret;
+
+ gpio_get_ops(desc-dev)-set_pull(desc-dev, desc-offset, pull);
Should return this value.
Ok.
+ return 0;
+}
+
int dm_gpio_set_dir_flags(struct gpio_desc *desc, ulong flags)
{
struct udevice *dev = desc-dev;
diff --git a/include/asm-generic/gpio.h b/include/asm-generic/gpio.h
index 3b96b82..7e0d426 100644
--- a/include/asm-generic/gpio.h
+++ b/include/asm-generic/gpio.h
@@ -241,6 +241,7 @@ struct dm_gpio_ops {
int value);
int (*get_value)(struct udevice *dev, unsigned offset);
int (*set_value)(struct udevice *dev, unsigned offset, int value);
+ int (*set_pull)(struct udevice *dev, unsigned offset, int pull);
/**
* get_function() Get the GPIO function
*
@@ -479,6 +480,7 @@ int gpio_free_list_nodev(struct gpio_desc *desc, int count);
/**
* dm_gpio_get_value() - Get the value of a GPIO
+
*
* This is the driver model version of the existing gpio_get_value() function
* and should be used instead of that.
@@ -495,6 +497,16 @@ int dm_gpio_get_value(struct gpio_desc *desc);
int dm_gpio_set_value(struct gpio_desc *desc, int value);
/**
+ * dm_gpio_set_pull() - Set the pull-up/down value of a GPIO
+ *
+ * @desc: GPIO description containing device, offset and flags,
+ * previously returned by gpio_request_by_name()
+ * @pull: GPIO pull value - driver specific
+ * @return 0 on success or -ve on error
+*/
+int dm_gpio_set_pull(struct gpio_desc *desc, int pull);
+
+/**
* dm_gpio_set_dir() - Set the direction for a GPIO
*
* This sets up the direction according tot the provided flags. It will do
--
1.9.1
Regards,
Simon
Sorry for the mess with this patchset (gpio+mmc).
I was testing the mmc detection by checking one of emmc pin INPUT value,
after set some pull value. And such detection works, but if no card is
detected, then unfortunately mmc channel is not registered and mmc
rescan command will not work for it, so I dropped this code.
Best regards,
--
Przemyslaw Marczak
Samsung RD Institute Poland
Samsung Electronics
p.marc...@samsung.com
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3 02/11] Exynos542x: CPU: Power down all secondary cores
This patch adds code to shutdown secondary cores.
When U-boot comes up, all secondary cores appear powered on,
which is undesirable and causes side effects while
initializing these cores in kernel.
Secondary core power down happens in following steps:
Step-1: After Exynos power-on, primary core starts executing first.
Step-2: In iROM code every core has to check 2 flags i.e.
addresses 0x02020028 0x02020004.
Step-3: Initially 0x02020028 is 0 for all cores and 0x02020004 has a
jump address for primary core and 0 for all secondary cores.
Step-4: Therefore, primary core follows normal iROM execution and jumps
to BL1 eventually, whereas all secondary cores enter WFE.
Step-5: When primary core comes into function secondary_cores_configure,
it puts pointer to function power_down_core into 0x02020004
and provides DSB and SEV for all cores so that they may come out
of WFE and jump to power_down_core function.
Step-6: And ultimately because of power_down_core all
secondary cores shut-down.
Signed-off-by: Kimoon Kim kimoon@samsung.com
Signed-off-by: Akshay Saraswat aksha...@samsung.com
---
Changes since v2:
- No change.
Changes since v1:
- Removed unnecessary macros.
- Changed names of few macros for better understanding.
- Added MPIDR bit assignment info comment in power_down_core.
arch/arm/cpu/armv7/exynos/exynos5_setup.h | 3 ++
arch/arm/cpu/armv7/exynos/lowlevel_init.c | 69
arch/arm/include/asm/arch-exynos/cpu.h| 5 ++
arch/arm/include/asm/arch-exynos/system.h | 87 +++
4 files changed, 164 insertions(+)
diff --git a/arch/arm/cpu/armv7/exynos/exynos5_setup.h
b/arch/arm/cpu/armv7/exynos/exynos5_setup.h
index 2eea48a..9073f50 100644
--- a/arch/arm/cpu/armv7/exynos/exynos5_setup.h
+++ b/arch/arm/cpu/armv7/exynos/exynos5_setup.h
@@ -700,6 +700,9 @@
#define CLK_DIV_CPERI1_VAL NOT_AVAILABLE
#else
+
+#define CPU_CONFIG_STATUS_OFFSET 0x80
+#define CPU_RST_FLAG_VAL 0xFCBA0D10
#define PAD_RETENTION_DRAM_COREBLK_VAL 0x1000
/* APLL_CON1 */
diff --git a/arch/arm/cpu/armv7/exynos/lowlevel_init.c
b/arch/arm/cpu/armv7/exynos/lowlevel_init.c
index 83e1dcf..e36f2fa 100644
--- a/arch/arm/cpu/armv7/exynos/lowlevel_init.c
+++ b/arch/arm/cpu/armv7/exynos/lowlevel_init.c
@@ -31,7 +31,9 @@
#include asm/arch/tzpc.h
#include asm/arch/periph.h
#include asm/arch/pinmux.h
+#include asm/arch/system.h
#include common_setup.h
+#include exynos5_setup.h
/* These are the things we can do during low-level init */
enum {
@@ -42,6 +44,68 @@ enum {
DO_POWER= 1 4,
};
+#ifdef CONFIG_EXYNOS5420
+/*
+ * Pointer to this function is stored in iRam which is used
+ * for jump and power down of a specific core.
+ */
+static void power_down_core(void)
+{
+ uint32_t tmp, core_id, core_config;
+
+ /* Get the unique core id */
+ /*
+* Multiprocessor Affinity Register
+* [11:8] Cluster ID
+* [1:0]CPU ID
+*/
+ mrc_mpafr(core_id);
+ tmp = core_id 0x3;
+ core_id = (core_id 6) ~3;
+ core_id |= tmp;
+ core_id = 0x3f;
+
+ /* Set the status of the core to low */
+ core_config = (core_id * CPU_CONFIG_STATUS_OFFSET);
+ core_config += EXYNOS5420_CPU_CONFIG_BASE;
+ writel(0x0, core_config);
+
+ /* Core enter WFI */
+ wfi();
+}
+
+/*
+ * Configurations for secondary cores are inapt at this stage.
+ * Reconfigure secondary cores. Shutdown and change the status
+ * of all cores except the primary core.
+ */
+static void secondary_cores_configure(void)
+{
+ uint32_t core_id;
+
+ /* Store jump address for power down of secondary cores */
+ writel((uint32_t)power_down_core, CONFIG_PHY_IRAM_BASE + 0x4);
+
+ /* Need all core power down check */
+ dsb();
+ sev();
+
+ /*
+* Power down all cores(secondary) while primary core must
+* wait for all cores to go down.
+*/
+ for (core_id = 1; core_id != CONFIG_CORE_COUNT; core_id++) {
+ while ((readl(EXYNOS5420_CPU_STATUS_BASE
+ + (core_id * CPU_CONFIG_STATUS_OFFSET))
+0xff) != 0x0) {
+ isb();
+ sev();
+ }
+ isb();
+ }
+}
+#endif
+
int do_lowlevel_init(void)
{
uint32_t reset_status;
@@ -49,6 +113,11 @@ int do_lowlevel_init(void)
arch_cpu_init();
+#ifdef CONFIG_EXYNOS5420
+ /* Reconfigure secondary cores */
+ secondary_cores_configure();
+#endif
+
reset_status = get_reset_status();
switch (reset_status) {
diff --git a/arch/arm/include/asm/arch-exynos/cpu.h
b/arch/arm/include/asm/arch-exynos/cpu.h
index 29674ad..e739520 100644
--- a/arch/arm/include/asm/arch-exynos/cpu.h
+++ b/arch/arm/include/asm/arch-exynos/cpu.h
@@ -153,6 +153,10
[U-Boot] [PATCH v3 00/11] Add support for booting multiple cores
This patch series introduces changes for booting secondary CPUs on Exynos5420 and Exynos5800. Changes since v2: - Patch 7 8 : Replaced #ifdef and #ifndef - if(proid_is_soc()). - Patch 11 : Removed #ifdef from enum definition. Changes since v1: - Added Reviewed-by Tested-by in the acked patches. - Removed unnecessary CONFIGS and macros. - Changed names of few macros for better understanding in patch 2. - Added MPIDR bit assignment info comment in power_down_core in patch 2. - Changed to SPDX header in sec_boot.S in patch 5. - Fixed compilation error for snow build in patch 11. Akshay Saraswat (10): Exynos542x: Config: Add various configs Exynos542x: CPU: Power down all secondary cores Exynos542x: Add workaround for ARM errata 798870 Exynos542x: Add workaround for ARM errata 799270 Exynos542x: Add workaround for exynos iROM errata Exynos542x: Change ambiguous function name set_l2cache Exynos542x: cache: Disable clean/evict push to external Exynos542x: add L2 control register configuration Exynos542x: Fix secondary core booting for thumb Exynos542x: Make A7s boot with thumb-mode U-Boot on warm reset Doug Anderson (1): Exynos: Fix L2 cache timings on Exynos5420 and Exynos5800 arch/arm/cpu/armv7/exynos/Makefile| 2 + arch/arm/cpu/armv7/exynos/common_setup.h | 63 arch/arm/cpu/armv7/exynos/exynos5_setup.h | 3 + arch/arm/cpu/armv7/exynos/lowlevel_init.c | 166 ++ arch/arm/cpu/armv7/exynos/sec_boot.S | 128 +++ arch/arm/cpu/armv7/exynos/soc.c | 35 --- arch/arm/include/asm/arch-exynos/cpu.h| 5 + arch/arm/include/asm/arch-exynos/system.h | 88 include/configs/exynos5420-common.h | 16 +++ 9 files changed, 471 insertions(+), 35 deletions(-) create mode 100644 arch/arm/cpu/armv7/exynos/sec_boot.S -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3 04/11] Exynos542x: Add workaround for ARM errata 799270
This patch adds workaround for the ARM errata 799270 which says
If the L2 cache logic clock is stopped because of L2 inactivity,
setting or clearing the ACTLR.SMP bit might not be effective. The bit is
modified in the ACTLR, meaning a read of the register returns the
updated value. However the logic that uses that bit retains the previous
value.
Signed-off-by: Kimoon Kim kimoon@samsung.com
Signed-off-by: Akshay Saraswat aksha...@samsung.com
Reviewed-by: Simon Glass s...@chromium.org
Tested-by: Simon Glass s...@chromium.org
---
Changes since v2:
- No change.
Changes since v1:
- Added Reviewed-by Tested-by.
arch/arm/cpu/armv7/exynos/lowlevel_init.c | 22 ++
1 file changed, 22 insertions(+)
diff --git a/arch/arm/cpu/armv7/exynos/lowlevel_init.c
b/arch/arm/cpu/armv7/exynos/lowlevel_init.c
index 7335a1e..bbcae4c 100644
--- a/arch/arm/cpu/armv7/exynos/lowlevel_init.c
+++ b/arch/arm/cpu/armv7/exynos/lowlevel_init.c
@@ -46,6 +46,28 @@ enum {
#ifdef CONFIG_EXYNOS5420
/*
+ * Ensure that the L2 logic has been used within the previous 256 cycles
+ * before modifying the ACTLR.SMP bit. This is required during boot before
+ * MMU has been enabled, or during a specified reset or power down sequence.
+ */
+void enable_smp(void)
+{
+ uint32_t temp, val;
+
+ /* Enable SMP mode */
+ mrc_auxr(temp);
+ temp |= (1 6);
+
+ /* Dummy read to assure L2 access */
+ val = readl(EXYNOS5420_INFORM_BASE);
+ val = 0;
+ temp |= val;
+ mcr_auxr(temp);
+ dsb();
+ isb();
+}
+
+/*
* Set L2ACTLR[7] to reissue any memory transaction in the L2 that has been
* stalled for 1024 cycles to verify that its hazard condition still exists.
*/
--
1.9.1
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3 05/11] Exynos542x: Add workaround for exynos iROM errata
iROM logic provides undesired jump address for CPU2.
This patch adds a programmable susbstitute for a part of
iROM logic which wakes up cores and provides jump addresses.
This patch creates a logic to make all secondary cores jump
to a particular address which evades the possibility of CPU2
jumping to wrong address and create undesired results.
Logic of the workaround:
Step-1: iROM code checks value at address 0x2020028.
Step-2: If value is 0xc9cfcfcf, it jumps to the address (0x202000+CPUid*4),
else, it continues executing normally.
Step-3: Primary core puts secondary cores in WFE and store 0xc9cfcfcf in
0x2020028 and jump address (pointer to function low_power_start)
in (0x202000+CPUid*4).
Step-4: When secondary cores recieve event signal they jump to this address
and continue execution.
Signed-off-by: Kimoon Kim kimoon@samsung.com
Signed-off-by: Akshay Saraswat aksha...@samsung.com
Reviewed-by: Simon Glass s...@chromium.org
Tested-by: Simon Glass s...@chromium.org
---
Changes since v2:
- No change.
Changes since v1:
- Added Reviewed-by Tested-by.
- Changed to SPDX header in sec_boot.S.
arch/arm/cpu/armv7/exynos/Makefile| 2 +
arch/arm/cpu/armv7/exynos/lowlevel_init.c | 90 -
arch/arm/cpu/armv7/exynos/sec_boot.S | 128 ++
3 files changed, 202 insertions(+), 18 deletions(-)
create mode 100644 arch/arm/cpu/armv7/exynos/sec_boot.S
diff --git a/arch/arm/cpu/armv7/exynos/Makefile
b/arch/arm/cpu/armv7/exynos/Makefile
index e207bd6..8542f89 100644
--- a/arch/arm/cpu/armv7/exynos/Makefile
+++ b/arch/arm/cpu/armv7/exynos/Makefile
@@ -7,6 +7,8 @@
obj-y += clock.o power.o soc.o system.o pinmux.o tzpc.o
+obj-$(CONFIG_EXYNOS5420) += sec_boot.o
+
ifdef CONFIG_SPL_BUILD
obj-$(CONFIG_EXYNOS5) += clock_init_exynos5.o
obj-$(CONFIG_EXYNOS5) += dmc_common.o dmc_init_ddr3.o
diff --git a/arch/arm/cpu/armv7/exynos/lowlevel_init.c
b/arch/arm/cpu/armv7/exynos/lowlevel_init.c
index bbcae4c..9714af8 100644
--- a/arch/arm/cpu/armv7/exynos/lowlevel_init.c
+++ b/arch/arm/cpu/armv7/exynos/lowlevel_init.c
@@ -50,7 +50,7 @@ enum {
* before modifying the ACTLR.SMP bit. This is required during boot before
* MMU has been enabled, or during a specified reset or power down sequence.
*/
-void enable_smp(void)
+static void enable_smp(void)
{
uint32_t temp, val;
@@ -71,7 +71,7 @@ void enable_smp(void)
* Set L2ACTLR[7] to reissue any memory transaction in the L2 that has been
* stalled for 1024 cycles to verify that its hazard condition still exists.
*/
-void set_l2cache(void)
+static void set_l2cache(void)
{
uint32_t val;
@@ -90,6 +90,62 @@ void set_l2cache(void)
}
/*
+ * Power up secondary CPUs.
+ */
+static void secondary_cpu_start(void)
+{
+ enable_smp();
+ svc32_mode_en();
+ set_pc(CONFIG_EXYNOS_RELOCATE_CODE_BASE);
+}
+
+/*
+ * This is the entry point of hotplug-in and
+ * cluster switching.
+ */
+static void low_power_start(void)
+{
+ uint32_t val, reg_val;
+
+ reg_val = readl(EXYNOS5420_SPARE_BASE);
+ if (reg_val != CPU_RST_FLAG_VAL) {
+ writel(0x0, CONFIG_LOWPOWER_FLAG);
+ set_pc(0x0);
+ }
+
+ reg_val = readl(CONFIG_PHY_IRAM_BASE + 0x4);
+ if (reg_val != (uint32_t)low_power_start) {
+ /* Store jump address as low_power_start if not present */
+ writel((uint32_t)low_power_start, CONFIG_PHY_IRAM_BASE + 0x4);
+ dsb();
+ sev();
+ }
+
+ /* Set the CPU to SVC32 mode */
+ svc32_mode_en();
+ set_l2cache();
+
+ /* Invalidate L1 TLB */
+ val = 0x0;
+ mcr_tlb(val);
+ mcr_icache(val);
+
+ /* Disable MMU stuff and caches */
+ mrc_sctlr(val);
+
+ val = ~((0x2 12) | 0x7);
+ val |= ((0x1 12) | (0x8 8) | 0x2);
+ mcr_sctlr(val);
+
+ /* CPU state is hotplug or reset */
+ secondary_cpu_start();
+
+ /* Core should not enter into WFI here */
+ wfi();
+
+}
+
+/*
* Pointer to this function is stored in iRam which is used
* for jump and power down of a specific core.
*/
@@ -125,29 +181,25 @@ static void power_down_core(void)
*/
static void secondary_cores_configure(void)
{
- uint32_t core_id;
+ /* Setup L2 cache */
+ set_l2cache();
- /* Store jump address for power down of secondary cores */
+ /* Clear secondary boot iRAM base */
+ writel(0x0, (CONFIG_EXYNOS_RELOCATE_CODE_BASE + 0x1C));
+
+ /* set lowpower flag and address */
+ writel(CPU_RST_FLAG_VAL, CONFIG_LOWPOWER_FLAG);
+ writel((uint32_t)low_power_start, CONFIG_LOWPOWER_ADDR);
+ writel(CPU_RST_FLAG_VAL, EXYNOS5420_SPARE_BASE);
+ /* Store jump address for power down */
writel((uint32_t)power_down_core, CONFIG_PHY_IRAM_BASE + 0x4);
/* Need all core power down check */
dsb();
[U-Boot] [PATCH v3 03/11] Exynos542x: Add workaround for ARM errata 798870
This patch adds workaround for ARM errata 798870 which says
If back-to-back speculative cache line fills (fill A and fill B) are
issued from the L1 data cache of a CPU to the L2 cache, the second
request (fill B) is then cancelled, and the second request would have
detected a hazard against a recent write or eviction (write B) to the
same cache line as fill B then the L2 logic might deadlock.
Signed-off-by: Kimoon Kim kimoon@samsung.com
Signed-off-by: Akshay Saraswat aksha...@samsung.com
Reviewed-by: Simon Glass s...@chromium.org
Tested-by: Simon Glass s...@chromium.org
---
Changes since v2:
- No change.
Changes since v1:
- Added Reviewed-by Tested-by.
- Added space before */ on line # 40.
arch/arm/cpu/armv7/exynos/lowlevel_init.c | 22 ++
1 file changed, 22 insertions(+)
diff --git a/arch/arm/cpu/armv7/exynos/lowlevel_init.c
b/arch/arm/cpu/armv7/exynos/lowlevel_init.c
index e36f2fa..7335a1e 100644
--- a/arch/arm/cpu/armv7/exynos/lowlevel_init.c
+++ b/arch/arm/cpu/armv7/exynos/lowlevel_init.c
@@ -46,6 +46,28 @@ enum {
#ifdef CONFIG_EXYNOS5420
/*
+ * Set L2ACTLR[7] to reissue any memory transaction in the L2 that has been
+ * stalled for 1024 cycles to verify that its hazard condition still exists.
+ */
+void set_l2cache(void)
+{
+ uint32_t val;
+
+ /* Read MIDR for Primary Part Number */
+ mrc_midr(val);
+ val = (val 4);
+ val = 0xf;
+
+ /* L2ACTLR[7]: Enable hazard detect timeout for A15 */
+ if (val == 0xf) {
+ mrc_l2_aux_ctlr(val);
+ val |= (1 7);
+ mcr_l2_aux_ctlr(val);
+ mrc_l2_ctlr(val);
+ }
+}
+
+/*
* Pointer to this function is stored in iRam which is used
* for jump and power down of a specific core.
*/
--
1.9.1
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH V2 2/4] s5p: gpio: add implementation of dm_gpio_set_pull()
This commit adds implementation of driver model gpio pull
setting to s5p gpio driver.
Signed-off-by: Przemyslaw Marczak p.marc...@samsung.com
Cc: Simon Glass s...@chromium.org
Cc: Minkyu Kang mk7.k...@samsung.com
Reviewed-by: Simon Glass s...@chromium.org
---
Changes v2:
- adjust code after added gpio pull enum to gpio api
---
drivers/gpio/s5p_gpio.c | 28
1 file changed, 28 insertions(+)
diff --git a/drivers/gpio/s5p_gpio.c b/drivers/gpio/s5p_gpio.c
index 0a245ba..ed531c6 100644
--- a/drivers/gpio/s5p_gpio.c
+++ b/drivers/gpio/s5p_gpio.c
@@ -129,6 +129,7 @@ static void s5p_gpio_set_pull(struct s5p_gpio_bank *bank,
int gpio, int mode)
value = ~PULL_MASK(gpio);
switch (mode) {
+ case S5P_GPIO_PULL_NONE:
case S5P_GPIO_PULL_DOWN:
case S5P_GPIO_PULL_UP:
value |= PULL_MODE(gpio, mode);
@@ -231,6 +232,32 @@ static int exynos_gpio_set_value(struct udevice *dev,
unsigned offset,
return 0;
}
+
+static int exynos_gpio_set_pull(struct udevice *dev, unsigned offset,
+ int pull)
+{
+ struct exynos_bank_info *state = dev_get_priv(dev);
+ int gpio_pull;
+
+ switch (pull) {
+ case GPIOP_NONE:
+ gpio_pull = S5P_GPIO_PULL_NONE;
+ break;
+ case GPIOP_DOWN:
+ gpio_pull = S5P_GPIO_PULL_DOWN;
+ break;
+ case GPIOP_UP:
+ gpio_pull = S5P_GPIO_PULL_UP;
+ break;
+ default:
+ return -EINVAL;
+ break;
+ }
+
+ s5p_gpio_set_pull(state-bank, offset, gpio_pull);
+
+ return 0;
+}
#endif /* nCONFIG_SPL_BUILD */
/*
@@ -290,6 +317,7 @@ static const struct dm_gpio_ops gpio_exynos_ops = {
.direction_output = exynos_gpio_direction_output,
.get_value = exynos_gpio_get_value,
.set_value = exynos_gpio_set_value,
+ .set_pull = exynos_gpio_set_pull,
.get_function = exynos_gpio_get_function,
.xlate = exynos_gpio_xlate,
};
--
1.9.1
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3 09/11] Exynos542x: Fix secondary core booting for thumb
When compiled SPL for Thumb secondary cores failed to boot
at the kernel boot up. Only one core came up out of 4.
This was happening because the code relocated to the
address 0x02073000 by the primary core was an ARM asm
code which was executed by the secondary cores as if it
was a thumb code.
This patch fixes the issue of secondary cores considering
relocated code as Thumb instructions and not ARM instructions
by jumping to the relocated with the help of bx ARM instruction.
bx instruction changes the 5th bit of CPSR which allows
execution unit to consider the following instructions as ARM
instructions.
Signed-off-by: Akshay Saraswat aksha...@samsung.com
Reviewed-by: Simon Glass s...@chromium.org
Tested-by: Simon Glass s...@chromium.org
---
Changes since v2:
- No change.
Changes since v1:
- Added Reviewed-by Tested-by.
arch/arm/cpu/armv7/exynos/lowlevel_init.c | 2 +-
arch/arm/include/asm/arch-exynos/system.h | 3 +++
2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv7/exynos/lowlevel_init.c
b/arch/arm/cpu/armv7/exynos/lowlevel_init.c
index aba6462..fc7e6f5 100644
--- a/arch/arm/cpu/armv7/exynos/lowlevel_init.c
+++ b/arch/arm/cpu/armv7/exynos/lowlevel_init.c
@@ -111,7 +111,7 @@ static void secondary_cpu_start(void)
{
enable_smp();
svc32_mode_en();
- set_pc(CONFIG_EXYNOS_RELOCATE_CODE_BASE);
+ branch_bx(CONFIG_EXYNOS_RELOCATE_CODE_BASE);
}
/*
diff --git a/arch/arm/include/asm/arch-exynos/system.h
b/arch/arm/include/asm/arch-exynos/system.h
index 86903c3..a9fd5e6 100644
--- a/arch/arm/include/asm/arch-exynos/system.h
+++ b/arch/arm/include/asm/arch-exynos/system.h
@@ -75,6 +75,9 @@ struct exynos5_sysreg {
/* Set program counter with the given value */
#define set_pc(x) __asm__ __volatile__ (mov pc, %0\n\t : : r(x))
+/* Branch to the given location */
+#define branch_bx(x) __asm__ __volatile__ (bx %0\n\t : : r(x))
+
/* Read Main Id register */
#define mrc_midr(x) __asm__ __volatile__ \
(mrc p15, 0, %0, c0, c0, 0\n\t : =r(x) : )
--
1.9.1
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3 07/11] Exynos542x: cache: Disable clean/evict push to external
L2 Auxiliary Control Register provides configuration
and control options for the L2 memory system. Bit 3
of L2ACTLR stands for clean/evict push to external.
Setting bit 3 disables clean/evict which is what
this patch intends to do.
Signed-off-by: Akshay Saraswat aksha...@samsung.com
Reviewed-by: Simon Glass s...@chromium.org
Tested-by: Simon Glass s...@chromium.org
---
Changes since v2:
- Replaced #ifdef with if(proid_id_soc()) check.
Changes since v1:
- Added Reviewed-by Tested-by.
arch/arm/cpu/armv7/exynos/soc.c | 18 +-
1 file changed, 17 insertions(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv7/exynos/soc.c b/arch/arm/cpu/armv7/exynos/soc.c
index 8c7d7d8..427f54c 100644
--- a/arch/arm/cpu/armv7/exynos/soc.c
+++ b/arch/arm/cpu/armv7/exynos/soc.c
@@ -13,7 +13,9 @@ enum l2_cache_params {
CACHE_TAG_RAM_SETUP = (1 9),
CACHE_DATA_RAM_SETUP = (1 5),
CACHE_TAG_RAM_LATENCY = (2 6),
- CACHE_DATA_RAM_LATENCY = (2 0)
+ CACHE_DATA_RAM_LATENCY = (2 0),
+ CACHE_ENABLE_CLEAN_EVICT = (0 3),
+ CACHE_DISABLE_CLEAN_EVICT = (1 3)
};
void reset_cpu(ulong addr)
@@ -37,14 +39,28 @@ static void exynos5_set_l2cache_params(void)
{
unsigned int val = 0;
+ /* Read L2CTLR value */
asm volatile(mrc p15, 1, %0, c9, c0, 2\n : =r(val));
+ /* Set cache setup and latency cycles */
val |= CACHE_TAG_RAM_SETUP |
CACHE_DATA_RAM_SETUP |
CACHE_TAG_RAM_LATENCY |
CACHE_DATA_RAM_LATENCY;
+ /* Write new vlaue to L2CTLR */
asm volatile(mcr p15, 1, %0, c9, c0, 2\n : : r(val));
+
+ if (proid_is_exynos5420() || proid_is_exynos5800()) {
+ /* Read L2ACTLR value */
+ asm volatile(mrc p15, 1, %0, c15, c0, 0 : =r (val));
+
+ /* Disable clean/evict push to external */
+ val |= CACHE_DISABLE_CLEAN_EVICT;
+
+ /* Write new vlaue to L2ACTLR */
+ asm volatile(mcr p15, 1, %0, c15, c0, 0 : : r (val));
+ }
}
/*
--
1.9.1
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3 11/11] Exynos: Fix L2 cache timings on Exynos5420 and Exynos5800
From: Doug Anderson diand...@chromium.org
It was found that the L2 cache timings that we had before could cause
freezes and hangs. We should make things more robust with better
timings. Currently the production ChromeOS kernel applies these
timings, but it's nice to fixup firmware too (and upstream probably
won't take our kernel hacks).
This also provides a big cleanup of the L2 cache init code avoiding
some duplication. The way things used to work:
* low_power_start() was installed by the SPL (both at boot and resume
time) and left resident in iRAM for the kernel to use when bringing
up additional CPUs. It used configure_l2_ctlr() and
configure_l2_actlr() when it detected it was on an A15. This was
needed (despite the L2 cache registers being shared among all A15s)
because we might have been the first man in after the whole A15
cluster was shutdown.
* secondary_cores_configure() was called on at boot time and at resume
time. Strangely this called configure_l2_ctlr() but not
configure_l2_actlr() which was almost certainly wrong. Given that
we'll call both (see next bullet) later in the boot process it
didn't matter for normal boot, but I guess this is how L2 cache
settings got set on 5420/5800 (but not 5250?) at resume time.
* exynos5_set_l2cache_params() was called as part of cache enablement.
This should happen at boot time (normally in the SPL except for USB
boot where it happens in main U-Boot).
Note that the old code wasn't setting ECC/parity in the cache
enablement code but we happened to get it anyway because we'd call
secondary_cores_configure() at boot time. For resume time we'd get it
anyway when the 2nd A15 core came up.
Let's make this a whole lot simpler. Now we always set these
parameters in the same place for all boots and use the same code for
setting up secondary CPUs.
Intended net effects of this change (other than cleanup):
* Timings go from before:
data: 0 cycle setup, 3 cycles (0x2) latency
tag: 0 cycle setup, 3 cycles (0x2) latency
after:
data: 1 cycle setup, 4 cycles (0x3) latency
tag: 1 cycle setup, 4 cycles (0x3) latency
* L2ACTLR is properly initted on 5420/5800 in all cases.
One note is that we're still relying on luck to keep low_power_start()
working. The compiler is being nice and not storing anything on the
stack.
Another note is that on its own this patch won't help to fix cache
settings in an RW U-Boot update where we still have the RO SPL. The
plan for that is:
* Have RW U-Boot re-init the cache right before calling the kernel
(after it has turned the L2 cache off). This is why the functions
are in a header file instead of lowlevel_init.c.
* Have the kernel save the L2 cache settings of the boot CPU and apply
them to all other CPUs. We get a little lucky here because the old
code was using |= to modify the registers and all of the bits that
it's setting are also present in the new settings (!). That means
that when the 2nd CPU in the A15 cluster comes up it doesn't
actually mess up the settings of the 1st CPU in the A15 cluster. An
alternative option is to have the kernel write its own
low_power_start() code.
Signed-off-by: Doug Anderson diand...@chromium.org
Signed-off-by: Akshay Saraswat aksha...@samsung.com
---
Changes since v2:
- Removed #ifdef from enum definition.
Changes since v1:
- Fixed compilation error for snow build.
arch/arm/cpu/armv7/exynos/common_setup.h | 63 +++
arch/arm/cpu/armv7/exynos/lowlevel_init.c | 55 ---
arch/arm/cpu/armv7/exynos/soc.c | 54 --
arch/arm/include/asm/arch-exynos/system.h | 2 -
4 files changed, 78 insertions(+), 96 deletions(-)
diff --git a/arch/arm/cpu/armv7/exynos/common_setup.h
b/arch/arm/cpu/armv7/exynos/common_setup.h
index e6318c0..b9fe60b 100644
--- a/arch/arm/cpu/armv7/exynos/common_setup.h
+++ b/arch/arm/cpu/armv7/exynos/common_setup.h
@@ -23,6 +23,8 @@
* MA 02111-1307 USA
*/
+#include asm/arch/system.h
+
#define DMC_OFFSET 0x1
/*
@@ -43,3 +45,64 @@ void system_clock_init(void);
int do_lowlevel_init(void);
void sdelay(unsigned long);
+
+enum l2_cache_params {
+ CACHE_DATA_RAM_LATENCY_2_CYCLES = (2 0),
+ CACHE_DATA_RAM_LATENCY_3_CYCLES = (3 0),
+ CACHE_DISABLE_CLEAN_EVICT = (1 3),
+ CACHE_DATA_RAM_SETUP = (1 5),
+ CACHE_TAG_RAM_LATENCY_2_CYCLES = (2 6),
+ CACHE_TAG_RAM_LATENCY_3_CYCLES = (3 6),
+ CACHE_ENABLE_HAZARD_DETECT = (1 7),
+ CACHE_TAG_RAM_SETUP = (1 9),
+ CACHE_ECC_AND_PARITY = (1 21),
+ CACHE_ENABLE_FORCE_L2_LOGIC = (1 27)
+};
+
+
+#ifndef CONFIG_SYS_L2CACHE_OFF
+/*
+ * Configure L2CTLR to get timings that keep us from hanging/crashing.
+ *
+ * Must be inline here since low_power_start() is called without a
+ * stack (!).
+ */
+static inline void configure_l2_ctlr(void)
+{
+ uint32_t val;
+
+ mrc_l2_ctlr(val);
+
+
[U-Boot] [PATCH v3 06/11] Exynos542x: Change ambiguous function name set_l2cache
1. Renaming set_l2cache to configure_l2actlr in order to avoid
misleading comprehensions. Apparently this name suggests
that L2 cache is being set or initialized which is incorrect
as per the code in this function.
2. Cleaning missed mrc for L2 control register.
Signed-off-by: Akshay Saraswat aksha...@samsung.com
Reviewed-by: Simon Glass s...@chromium.org
Tested-by: Simon Glass s...@chromium.org
---
Changes since v2:
- No change.
Changes since v1:
- Added Reviewed-by Tested-by.
arch/arm/cpu/armv7/exynos/lowlevel_init.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/arch/arm/cpu/armv7/exynos/lowlevel_init.c
b/arch/arm/cpu/armv7/exynos/lowlevel_init.c
index 9714af8..0893b0b 100644
--- a/arch/arm/cpu/armv7/exynos/lowlevel_init.c
+++ b/arch/arm/cpu/armv7/exynos/lowlevel_init.c
@@ -71,7 +71,7 @@ static void enable_smp(void)
* Set L2ACTLR[7] to reissue any memory transaction in the L2 that has been
* stalled for 1024 cycles to verify that its hazard condition still exists.
*/
-static void set_l2cache(void)
+static void configure_l2actlr(void)
{
uint32_t val;
@@ -85,7 +85,6 @@ static void set_l2cache(void)
mrc_l2_aux_ctlr(val);
val |= (1 7);
mcr_l2_aux_ctlr(val);
- mrc_l2_ctlr(val);
}
}
@@ -123,7 +122,7 @@ static void low_power_start(void)
/* Set the CPU to SVC32 mode */
svc32_mode_en();
- set_l2cache();
+ configure_l2actlr();
/* Invalidate L1 TLB */
val = 0x0;
@@ -182,7 +181,7 @@ static void power_down_core(void)
static void secondary_cores_configure(void)
{
/* Setup L2 cache */
- set_l2cache();
+ configure_l2actlr();
/* Clear secondary boot iRAM base */
writel(0x0, (CONFIG_EXYNOS_RELOCATE_CODE_BASE + 0x1C));
--
1.9.1
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3 08/11] Exynos542x: add L2 control register configuration
This patch does 3 things:
1. Enables ECC by setting 21st bit of L2CTLR.
2. Restore data and tag RAM latencies to 3 cycles because iROM sets
0x3000400 L2CTLR value during switching.
3. Disable clean/evict push to external by setting 3rd bit of L2ACTLR.
We need to restore this here due to switching.
Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com
Signed-off-by: Akshay Saraswat aksha...@samsung.com
Reviewed-by: Simon Glass s...@chromium.org
Tested-by: Simon Glass s...@chromium.org
---
Changes since v2:
- Replaced #ifndef with if(proid_is_soc()) check.
Changes since v1:
- Added Reviewed-by Tested-by.
arch/arm/cpu/armv7/exynos/lowlevel_init.c | 53 +++
arch/arm/cpu/armv7/exynos/soc.c | 27 +---
2 files changed, 54 insertions(+), 26 deletions(-)
diff --git a/arch/arm/cpu/armv7/exynos/lowlevel_init.c
b/arch/arm/cpu/armv7/exynos/lowlevel_init.c
index 0893b0b..aba6462 100644
--- a/arch/arm/cpu/armv7/exynos/lowlevel_init.c
+++ b/arch/arm/cpu/armv7/exynos/lowlevel_init.c
@@ -68,24 +68,40 @@ static void enable_smp(void)
}
/*
+ * Enable ECC by setting L2CTLR[21].
+ * Set L2CTLR[7] to make tag ram latency 3 cycles and
+ * set L2CTLR[1] to make data ram latency 3 cycles.
+ * We need to make RAM latency of 3 cycles here because cores
+ * power ON and OFF while switching. And everytime a core powers
+ * ON, iROM provides it a default L2CTLR value 0x400 which stands
+ * for TAG RAM setup of 1 cycle. Hence, we face a need of
+ * restoring data and tag latency values.
+ */
+static void configure_l2_ctlr(void)
+{
+ uint32_t val;
+
+ mrc_l2_ctlr(val);
+ val |= (1 21);
+ val |= (1 7);
+ val |= (1 1);
+ mcr_l2_ctlr(val);
+}
+
+/*
* Set L2ACTLR[7] to reissue any memory transaction in the L2 that has been
* stalled for 1024 cycles to verify that its hazard condition still exists.
+ * Disable clean/evict push to external by setting L2ACTLR[3].
*/
-static void configure_l2actlr(void)
+static void configure_l2_actlr(void)
{
uint32_t val;
- /* Read MIDR for Primary Part Number */
- mrc_midr(val);
- val = (val 4);
- val = 0xf;
-
- /* L2ACTLR[7]: Enable hazard detect timeout for A15 */
- if (val == 0xf) {
- mrc_l2_aux_ctlr(val);
- val |= (1 7);
- mcr_l2_aux_ctlr(val);
- }
+ mrc_l2_aux_ctlr(val);
+ val |= (1 27);
+ val |= (1 7);
+ val |= (1 3);
+ mcr_l2_aux_ctlr(val);
}
/*
@@ -122,7 +138,16 @@ static void low_power_start(void)
/* Set the CPU to SVC32 mode */
svc32_mode_en();
- configure_l2actlr();
+
+ /* Read MIDR for Primary Part Number */
+ mrc_midr(val);
+ val = (val 4);
+ val = 0xf;
+
+ if (val == 0xf) {
+ configure_l2_ctlr();
+ configure_l2_actlr();
+ }
/* Invalidate L1 TLB */
val = 0x0;
@@ -181,7 +206,7 @@ static void power_down_core(void)
static void secondary_cores_configure(void)
{
/* Setup L2 cache */
- configure_l2actlr();
+ configure_l2_ctlr();
/* Clear secondary boot iRAM base */
writel(0x0, (CONFIG_EXYNOS_RELOCATE_CODE_BASE + 0x1C));
diff --git a/arch/arm/cpu/armv7/exynos/soc.c b/arch/arm/cpu/armv7/exynos/soc.c
index 427f54c..77d3875 100644
--- a/arch/arm/cpu/armv7/exynos/soc.c
+++ b/arch/arm/cpu/armv7/exynos/soc.c
@@ -37,30 +37,33 @@ void enable_caches(void)
*/
static void exynos5_set_l2cache_params(void)
{
- unsigned int val = 0;
+ unsigned int l2ctlr = 0, l2actlr = 0;
/* Read L2CTLR value */
- asm volatile(mrc p15, 1, %0, c9, c0, 2\n : =r(val));
+ asm volatile(mrc p15, 1, %0, c9, c0, 2\n : =r(l2ctlr));
- /* Set cache setup and latency cycles */
- val |= CACHE_TAG_RAM_SETUP |
- CACHE_DATA_RAM_SETUP |
- CACHE_TAG_RAM_LATENCY |
+ /* Set cache latency cycles */
+ l2ctlr |= CACHE_TAG_RAM_LATENCY |
CACHE_DATA_RAM_LATENCY;
- /* Write new vlaue to L2CTLR */
- asm volatile(mcr p15, 1, %0, c9, c0, 2\n : : r(val));
-
if (proid_is_exynos5420() || proid_is_exynos5800()) {
+
/* Read L2ACTLR value */
- asm volatile(mrc p15, 1, %0, c15, c0, 0 : =r (val));
+ asm volatile(mrc p15, 1, %0, c15, c0, 0 : =r
(l2actlr));
/* Disable clean/evict push to external */
- val |= CACHE_DISABLE_CLEAN_EVICT;
+ l2actlr |= CACHE_DISABLE_CLEAN_EVICT;
/* Write new vlaue to L2ACTLR */
- asm volatile(mcr p15, 1, %0, c15, c0, 0 : : r (val));
+ asm volatile(mcr p15, 1, %0, c15, c0, 0 : : r
(l2actlr));
+ } else {
+ /* Set cache setup cycles */
+ l2ctlr |= CACHE_TAG_RAM_SETUP |
+ CACHE_DATA_RAM_SETUP;
}
+
+
[U-Boot] [PATCH v3 10/11] Exynos542x: Make A7s boot with thumb-mode U-Boot on warm reset
On warm reset, all cores jump to the low_power_start function because iRAM
data is retained and because while executing iROM code all cores find
the jump flag 0x02020028 set. In low_power_start, cores check the reset
status and if true they clear the jump flag and jump back to 0x0.
The A7 cores do jump to 0x0 but consider following instructions as a Thumb
instructions which in turn makes them loop inside the iROM code instead of
jumping to power_down_core.
This issue is fixed by replacing the mov pc instruction with a bx
instruction which switches state along with the jump to make the execution
unit consider the branch target as an ARM instruction.
Signed-off-by: Akshay Saraswat aksha...@samsung.com
Reviewed-by: Simon Glass s...@chromium.org
Tested-by: Simon Glass s...@chromium.org
---
Changes since v2:
- No change.
Changes since v1:
- Added Reviewed-by Tested-by.
arch/arm/cpu/armv7/exynos/lowlevel_init.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv7/exynos/lowlevel_init.c
b/arch/arm/cpu/armv7/exynos/lowlevel_init.c
index fc7e6f5..36a008a 100644
--- a/arch/arm/cpu/armv7/exynos/lowlevel_init.c
+++ b/arch/arm/cpu/armv7/exynos/lowlevel_init.c
@@ -125,7 +125,7 @@ static void low_power_start(void)
reg_val = readl(EXYNOS5420_SPARE_BASE);
if (reg_val != CPU_RST_FLAG_VAL) {
writel(0x0, CONFIG_LOWPOWER_FLAG);
- set_pc(0x0);
+ branch_bx(0x0);
}
reg_val = readl(CONFIG_PHY_IRAM_BASE + 0x4);
--
1.9.1
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 3/4] mmc: exynos dwmmc: check boot mode before init dwmmc
Hello Simon,
On 02/18/2015 06:02 AM, Simon Glass wrote:
Hi Przemyslaw,
On 17 February 2015 at 06:09, Przemyslaw Marczak p.marc...@samsung.com wrote:
Before this commit, the mmc devices were always registered
in the same order. So dwmmc channel 0 was registered as mmc 0,
channel 1 as mmc 1, etc.
In case of possibility to boot from more then one device,
the CONFIG_SYS_MMC_ENV_DEV should always point to right mmc device.
This can be achieved by init boot device as first, so it will be
always registered as mmc 0. Thanks to this, the 'saveenv' command
will work fine for all mmc boot devices.
Exynos based boards usually uses mmc host channels configuration:
- 0, or 0+1 for 8 bit - as a default boot device (usually eMMC)
- 2 for 4bit - as an optional boot device (usually SD card slot)
And usually the boot order is defined by OM pin configuration,
which can be changed in a few ways, eg.
- Odroid U3 - eMMC card insertion - first boot from eMMC
- Odroid X2/XU3 - boot priority jumper
By this commit, Exynos dwmmc driver will check the OM pin configuration,
and then try to init the boot device and register it as mmc 0.
I think a better way to do this would be to make
CONFIG_SYS_MMC_ENV_DEV support an option where the device can be
selected at run-time.
However that would probably be better done when the drive rmodel
conversion is complete.
So this seems a reasonable patch given where we are.
Reviewed-by: Simon Glass s...@chromium.org
This was just a quick solution to solve the issue on XU3, when the same
binary can boot from sd or eMMC slots.
Signed-off-by: Przemyslaw Marczak p.marc...@samsung.com
Cc: Minkyu Kang mk7.k...@samsung.com
Cc: Jaehoon Chung jh80.ch...@samsung.com
Cc: Pantelis Antoniou pa...@intracom.gr
Cc: Simon Glass s...@chromium.org
Cc: Akshay Saraswat aksha...@samsung.com
---
drivers/mmc/exynos_dw_mmc.c | 11 ++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/drivers/mmc/exynos_dw_mmc.c b/drivers/mmc/exynos_dw_mmc.c
index dfa209b..91f0163 100644
--- a/drivers/mmc/exynos_dw_mmc.c
+++ b/drivers/mmc/exynos_dw_mmc.c
@@ -13,6 +13,7 @@
#include asm/arch/dwmmc.h
#include asm/arch/clk.h
#include asm/arch/pinmux.h
+#include asm/arch/power.h
#include asm/gpio.h
#include asm-generic/errno.h
@@ -166,7 +167,6 @@ static int exynos_dwmci_get_config(const void *blob, int
node,
if (host-dev_index == host-dev_id)
host-dev_index = host-dev_id - PERIPH_ID_SDMMC0;
-
/* Get the bus width from the device node */
host-buswidth = fdtdec_get_int(blob, node, samsung,bus-width, 0);
if (host-buswidth = 0) {
@@ -229,12 +229,21 @@ int exynos_dwmmc_init(const void *blob)
{
int compat_id;
int node_list[DWMMC_MAX_CH_NUM];
+ int boot_dev_node;
int err = 0, count;
compat_id = COMPAT_SAMSUNG_EXYNOS_DWMMC;
count = fdtdec_find_aliases_for_id(blob, mmc,
compat_id, node_list, DWMMC_MAX_CH_NUM);
+
+ /* For DWMMC always set boot device as mmc 0 */
+ if (count = 3 get_boot_mode() == BOOT_MODE_SD) {
+ boot_dev_node = node_list[2];
+ node_list[2] = node_list[0];
+ node_list[0] = boot_dev_node;
+ }
+
err = exynos_dwmci_process_node(blob, node_list, count);
return err;
--
1.9.1
Regards,
Simon
Thank you for the review. I will send the second version soon.
Best regards,
--
Przemyslaw Marczak
Samsung RD Institute Poland
Samsung Electronics
p.marc...@samsung.com
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH V2 3/4] mmc: exynos dwmmc: check boot mode before init dwmmc
Before this commit, the mmc devices were always registered
in the same order. So dwmmc channel 0 was registered as mmc 0,
channel 1 as mmc 1, etc.
In case of possibility to boot from more then one device,
the CONFIG_SYS_MMC_ENV_DEV should always point to right mmc device.
This can be achieved by init boot device as first, so it will be
always registered as mmc 0. Thanks to this, the 'saveenv' command
will work fine for all mmc boot devices.
Exynos based boards usually uses mmc host channels configuration:
- 0, or 0+1 for 8 bit - as a default boot device (usually eMMC)
- 2 for 4bit - as an optional boot device (usually SD card slot)
And usually the boot order is defined by OM pin configuration,
which can be changed in a few ways, eg.
- Odroid U3 - eMMC card insertion - first boot from eMMC
- Odroid X2/XU3 - boot priority jumper
By this commit, Exynos dwmmc driver will check the OM pin configuration,
and then try to init the boot device and register it as mmc 0.
Signed-off-by: Przemyslaw Marczak p.marc...@samsung.com
Cc: Minkyu Kang mk7.k...@samsung.com
Cc: Jaehoon Chung jh80.ch...@samsung.com
Cc: Pantelis Antoniou pa...@intracom.gr
Cc: Simon Glass s...@chromium.org
Cc: Akshay Saraswat aksha...@samsung.com
Reviewed-by: Simon Glass s...@chromium.org
---
Changes v2:
- none
---
drivers/mmc/exynos_dw_mmc.c | 11 ++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/drivers/mmc/exynos_dw_mmc.c b/drivers/mmc/exynos_dw_mmc.c
index dfa209b..91f0163 100644
--- a/drivers/mmc/exynos_dw_mmc.c
+++ b/drivers/mmc/exynos_dw_mmc.c
@@ -13,6 +13,7 @@
#include asm/arch/dwmmc.h
#include asm/arch/clk.h
#include asm/arch/pinmux.h
+#include asm/arch/power.h
#include asm/gpio.h
#include asm-generic/errno.h
@@ -166,7 +167,6 @@ static int exynos_dwmci_get_config(const void *blob, int
node,
if (host-dev_index == host-dev_id)
host-dev_index = host-dev_id - PERIPH_ID_SDMMC0;
-
/* Get the bus width from the device node */
host-buswidth = fdtdec_get_int(blob, node, samsung,bus-width, 0);
if (host-buswidth = 0) {
@@ -229,12 +229,21 @@ int exynos_dwmmc_init(const void *blob)
{
int compat_id;
int node_list[DWMMC_MAX_CH_NUM];
+ int boot_dev_node;
int err = 0, count;
compat_id = COMPAT_SAMSUNG_EXYNOS_DWMMC;
count = fdtdec_find_aliases_for_id(blob, mmc,
compat_id, node_list, DWMMC_MAX_CH_NUM);
+
+ /* For DWMMC always set boot device as mmc 0 */
+ if (count = 3 get_boot_mode() == BOOT_MODE_SD) {
+ boot_dev_node = node_list[2];
+ node_list[2] = node_list[0];
+ node_list[0] = boot_dev_node;
+ }
+
err = exynos_dwmci_process_node(blob, node_list, count);
return err;
--
1.9.1
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH V2 1/4] dm: gpio: extend gpio api by dm_gpio_set_pull()
This commits extends:
- dm gpio ops by: 'set_pull' call
- dm gpio uclass by: dm_gpio_set_pull() function
The pull modes are defined by proper enum and can be:
- UP
- DOWN
- NONE
- UNKNOWN
Signed-off-by: Przemyslaw Marczak p.marc...@samsung.com
CC: Simon Glass s...@chromium.org
Reviewed-by: Simon Glass s...@chromium.org
---
Changes v2:
- add enum with gpio pull mode
---
drivers/gpio/gpio-uclass.c | 11 +++
include/asm-generic/gpio.h | 22 ++
2 files changed, 33 insertions(+)
diff --git a/drivers/gpio/gpio-uclass.c b/drivers/gpio/gpio-uclass.c
index a69bbd2..10f600b 100644
--- a/drivers/gpio/gpio-uclass.c
+++ b/drivers/gpio/gpio-uclass.c
@@ -321,6 +321,17 @@ int dm_gpio_set_value(struct gpio_desc *desc, int value)
return 0;
}
+int dm_gpio_set_pull(struct gpio_desc *desc, int pull)
+{
+ int ret;
+
+ ret = check_reserved(desc, set_pull);
+ if (ret)
+ return ret;
+
+ return gpio_get_ops(desc-dev)-set_pull(desc-dev, desc-offset, pull);
+}
+
int dm_gpio_set_dir_flags(struct gpio_desc *desc, ulong flags)
{
struct udevice *dev = desc-dev;
diff --git a/include/asm-generic/gpio.h b/include/asm-generic/gpio.h
index 3b96b82..b353f80 100644
--- a/include/asm-generic/gpio.h
+++ b/include/asm-generic/gpio.h
@@ -108,6 +108,16 @@ enum gpio_func_t {
GPIOF_COUNT,
};
+/* State of a GPIO pull */
+enum gpio_pull_t {
+ GPIOP_DOWN = 0,
+ GPIOP_UP,
+ GPIOP_NONE,
+ GPIOP_UNKNOWN,
+
+ GPIOP_COUNT,
+};
+
struct udevice;
struct gpio_desc {
@@ -241,6 +251,7 @@ struct dm_gpio_ops {
int value);
int (*get_value)(struct udevice *dev, unsigned offset);
int (*set_value)(struct udevice *dev, unsigned offset, int value);
+ int (*set_pull)(struct udevice *dev, unsigned offset, int pull);
/**
* get_function() Get the GPIO function
*
@@ -479,6 +490,7 @@ int gpio_free_list_nodev(struct gpio_desc *desc, int count);
/**
* dm_gpio_get_value() - Get the value of a GPIO
+
*
* This is the driver model version of the existing gpio_get_value() function
* and should be used instead of that.
@@ -495,6 +507,16 @@ int dm_gpio_get_value(struct gpio_desc *desc);
int dm_gpio_set_value(struct gpio_desc *desc, int value);
/**
+ * dm_gpio_set_pull() - Set the pull-up/down value of a GPIO
+ *
+ * @desc: GPIO description containing device, offset and flags,
+ * previously returned by gpio_request_by_name()
+ * @pull: GPIO pull value - one of enum gpio_pull_t
+ * @return 0 on success or -ve on error
+*/
+int dm_gpio_set_pull(struct gpio_desc *desc, int pull);
+
+/**
* dm_gpio_set_dir() - Set the direction for a GPIO
*
* This sets up the direction according tot the provided flags. It will do
--
1.9.1
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH V2 0/4] exynos-dwmmc: check set init priority for boot channel
The dw mmc driver init priority was always the same: ch 0, ch 1, ch 2. On some boards (e.g. Odroid XU3) the dwmmc driver is enabled for all mmc channels. In this case, when boot device is switchable (SD/eMMC), the default MMC device will be 0 or 1. Change the init priority to boot device, always init the boot device as mmc 0. This fixes the issue with 'saveenv' command, because the MMC env device number is always the same. The patchset also adds gpio set pull option to gpio api. Przemyslaw Marczak (4): dm: gpio: extend gpio api by dm_gpio_set_pull() s5p: gpio: add implementation of dm_gpio_set_pull() mmc: exynos dwmmc: check boot mode before init dwmmc mmc: print SD/eMMC type for inited mmc devices drivers/gpio/gpio-uclass.c | 11 +++ drivers/gpio/s5p_gpio.c | 28 drivers/mmc/exynos_dw_mmc.c | 11 ++- drivers/mmc/mmc.c | 8 include/asm-generic/gpio.h | 22 ++ 5 files changed, 79 insertions(+), 1 deletion(-) -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH V2 4/4] mmc: print SD/eMMC type for inited mmc devices
Depending on the boot priority, the eMMC/SD cards,
can be initialized with the same numbers for each boot.
To be sure which mmc device is SD and which is eMMC,
this info is printed by 'mmc list' command, when
the init is done.
Signed-off-by: Przemyslaw Marczak p.marc...@samsung.com
Cc: Pantelis Antoniou pa...@intracom.gr
Reviewed-by: Simon Glass s...@chromium.org
---
Changes v2:
- none
---
drivers/mmc/mmc.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index b8039cd..a13769e 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -1693,11 +1693,19 @@ void print_mmc_devices(char separator)
{
struct mmc *m;
struct list_head *entry;
+ char *mmc_type;
list_for_each(entry, mmc_devices) {
m = list_entry(entry, struct mmc, link);
+ if (m-has_init)
+ mmc_type = IS_SD(m) ? SD : eMMC;
+ else
+ mmc_type = NULL;
+
printf(%s: %d, m-cfg-name, m-block_dev.dev);
+ if (mmc_type)
+ printf( (%s), mmc_type);
if (entry-next != mmc_devices) {
printf(%c, separator);
--
1.9.1
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3 04/11] Exynos542x: Add workaround for ARM errata 799270
On Wed, 18 Feb 2015 15:16:28 +0530
Akshay Saraswat aksha...@samsung.com wrote:
This patch adds workaround for the ARM errata 799270 which says
If the L2 cache logic clock is stopped because of L2 inactivity,
setting or clearing the ACTLR.SMP bit might not be effective. The bit is
modified in the ACTLR, meaning a read of the register returns the
updated value. However the logic that uses that bit retains the previous
value.
Signed-off-by: Kimoon Kim kimoon@samsung.com
Signed-off-by: Akshay Saraswat aksha...@samsung.com
Reviewed-by: Simon Glass s...@chromium.org
Tested-by: Simon Glass s...@chromium.org
---
Changes since v2:
- No change.
Changes since v1:
- Added Reviewed-by Tested-by.
arch/arm/cpu/armv7/exynos/lowlevel_init.c | 22 ++
1 file changed, 22 insertions(+)
diff --git a/arch/arm/cpu/armv7/exynos/lowlevel_init.c
b/arch/arm/cpu/armv7/exynos/lowlevel_init.c
index 7335a1e..bbcae4c 100644
--- a/arch/arm/cpu/armv7/exynos/lowlevel_init.c
+++ b/arch/arm/cpu/armv7/exynos/lowlevel_init.c
@@ -46,6 +46,28 @@ enum {
#ifdef CONFIG_EXYNOS5420
/*
+ * Ensure that the L2 logic has been used within the previous 256 cycles
+ * before modifying the ACTLR.SMP bit. This is required during boot before
+ * MMU has been enabled, or during a specified reset or power down sequence.
+ */
+void enable_smp(void)
+{
+ uint32_t temp, val;
+
+ /* Enable SMP mode */
+ mrc_auxr(temp);
+ temp |= (1 6);
+
+ /* Dummy read to assure L2 access */
+ val = readl(EXYNOS5420_INFORM_BASE);
+ val = 0;
+ temp |= val;
Wouldn't the compiler happily optimize out some parts of this code?
+ mcr_auxr(temp);
+ dsb();
+ isb();
+}
This looks like a general purpose ARM Cortex-A15 workaround too. Except
that the EXYNOS5420_INFORM_BASE address is Exynos specific.
--
Best regards,
Siarhei Siamashka
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] u-boot tftp problem
Hi, Here's what I think happens: When working with large TFTP packets (probably 4096 bytes, as set in your board config file), U-Boot TFTP code sends wrong acknowledges for the TFTP packets. If the TFTP server implementation is too strict (the OpenBSD server is a good example), the transfer will inevitably fail very soon after start. Here's an example: 1. TFTP server sends block 0 2. Board acknowledges block 0 3. TFTP server sends block 1 4. Board acknowledges block 0 At this point you can see either proper or very obscure error messages in the TFTP server logs, so trust only to network dumps for diagnostics. What can you do to resolve your issue: 1. Fix the bug in U-Boot tftp networking code and submit a patch. 2. Reduce your TFTP blksize, by commenting CONFIG_TFTPBLOCKSIZE in your board config. The default value is 1468, which should work fine. U-Boot behaves nicer with smaller packets. Hope this helps. Regards, Nikolay ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] omap_gpmc: Do not default to HAM1 when SW ECC is selected
Hi Andreas, for OMAP3 and AM35xx boards, it would have been ok omitting the
CONFIG_BCH check and simply use CONFIG_NAND_OMAP_ECCSCHEME.
Those boards use the ecc scheme config already. However I just wasn't 100%
sure if I could rely on this config for all TI OMAP/AM based boards. I know
OMAP3
and AM35xx board configs already have CONFIG_NAND_OMAP_ECCSCHEME.
Should I check for other OMAP and AM series? The original ecc detection
function
seems to be written with an assumption that config is nonexistent - hence
defaulting
to HAM1.
That said, I agree that the whole omap_nand_switch_ecc() could be improved.
However, to me, the confusion arised from the fact that OMAP3 can do BCH8
hw ECC
calculation but needs software to do the correction. Hence my patch changes
the
software part of the omap_nand_switch_ecc(), and not the hardware part.
Just to clarify, what you are saying is that I should leave the software
part as it was (defaulting
to HAM1), and in the hardware part I should check for ELM support and
choose a BCH8
scheme accordingly, regardless of what's defined by
CONFIG_NAND_OMAP_ECCSCHEME?
In other words, I will run 'nandecc hw' to enable BCH8?
Let me know,
Thanks,
Adam
On Wed, Feb 18, 2015 at 6:14 AM, Andreas Bießmann
andreas.de...@googlemail.com wrote:
Hi Adam,
On 02/18/2015 03:58 AM, Adam YH Lee wrote:
The ECC scheme selection algorithm in OMAP GPMC appears to be left
untested when
BCH8 handling code was added. Running 'nandecc sw' defaults to HAM1 even
if
the board is using another scheme (ex.
OMAP_ECC_BCH8_CODE_HW_DETECTION_SW on
OMAP3). This results in unrecoverable ECC errors when reading data. This
commit
fixes the behavior by checking for CONFIG_BCH and using the scheme
defined by
CONFIG_NAND_OMAP_ECCSCHEME in the board configuration file.
This has been tested on Gumstix Overo (OMAP3).
Signed-off-by: Adam YH Lee adam.yh@gmail.com
---
drivers/mtd/nand/omap_gpmc.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/mtd/nand/omap_gpmc.c b/drivers/mtd/nand/omap_gpmc.c
index fc64f48..5daf932 100644
--- a/drivers/mtd/nand/omap_gpmc.c
+++ b/drivers/mtd/nand/omap_gpmc.c
@@ -901,8 +901,13 @@ int __maybe_unused omap_nand_switch_ecc(uint32_t
hardware, uint32_t eccstrength)
return -EINVAL;
}
} else {
+ #ifdef CONFIG_BCH
+ err = omap_select_ecc_scheme(nand,
CONFIG_NAND_OMAP_ECCSCHEME,
+ mtd-writesize, mtd-oobsize);
+ #else
err = omap_select_ecc_scheme(nand, OMAP_ECC_HAM1_CODE_SW,
mtd-writesize, mtd-oobsize);
Couldn't we just use the CONFIG_NAND_OMAP_ECCSCHEME instead of
OMAP_ECC_HAM1_CODE_SW here and omit the CONFIG_BCH define?
On the other hand I think the whole function omap_nand_switch_ecc() is
wrong. AFAIR it should only be used on omap3 aka am35xx/dm37xx devices
witch the nandecc command.
These SoC do not have a ELM. Therefore I decided to say BCH8 on those
devices is always 'HW ECC' when introduced BCH8 on omap3 first. Nowadays
it is the so called BCH8_CODE_HW_DETECTION_SW. Coming from this mindset
the right solution is to use some detection if the ELM is supported or
not and switch in the HW part of omap_nand_switch_ecc() between
OMAP_ECC_BCH8_CODE_HW and OMAP_ECC_BCH8_CODE_HW_DETECTION_SW.
Best regards
Andreas Bießmann
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3 06/13] ARM: HYP/non-sec: allow relocation to secure RAM
I am trying to bring up xen suing u-boot that has this patch. Unfortunately as soon as the code tries to call _nonsec_init through secure_ram_addr in arm7_init_nonsec function in virt-v7.c I get an undefined instruction exception. I suspect the CONFIG_ARMV7_SECURE_BASE needs to be defined to a particular value. What should that be defined to for omap5432? Surya On Saturday, February 15, 2014 at 5:36:30 AM UTC-8, Marc Zyngier wrote: The current non-sec switching code suffers from one major issue: it cannot run in secure RAM, as a large part of u-boot still needs to be run while we're switched to non-secure. This patch reworks the whole HYP/non-secure strategy by: - making sure the secure code is the *last* thing u-boot executes before entering the payload - performing an exception return from secure mode directly into the payload - allowing the code to be dynamically relocated to secure RAM before switching to non-secure. This involves quite a bit of horrible code, specially as u-boot relocation is quite primitive. Signed-off-by: Marc Zyngier marc.zyng...@arm.com --- arch/arm/cpu/armv7/nonsec_virt.S | 161 +++ arch/arm/cpu/armv7/virt-v7.c | 59 +- arch/arm/include/asm/armv7.h | 10 ++- arch/arm/include/asm/secure.h| 26 +++ arch/arm/lib/bootm.c | 22 +++--- 5 files changed, 138 insertions(+), 140 deletions(-) create mode 100644 arch/arm/include/asm/secure.h diff --git a/arch/arm/cpu/armv7/nonsec_virt.S b/arch/arm/cpu/armv7/nonsec_virt.S index b5c946f..2a43e3c 100644 --- a/arch/arm/cpu/armv7/nonsec_virt.S +++ b/arch/arm/cpu/armv7/nonsec_virt.S @@ -10,10 +10,13 @@ #include linux/linkage.h #include asm/gic.h #include asm/armv7.h +#include asm/proc-armv/ptrace.h .arch_extension sec .arch_extension virt + .pushsection ._secure.text, ax + .align 5 /* the vector table for secure state and HYP mode */ _monitor_vectors: @@ -22,51 +25,86 @@ _monitor_vectors: adr pc, _secure_monitor .word 0 .word 0 - adr pc, _hyp_trap + .word 0 .word 0 .word 0 +.macro is_cpu_virt_capable tmp + mrc p15, 0, \tmp, c0, c1, 1 @ read ID_PFR1 + and \tmp, \tmp, #CPUID_ARM_VIRT_MASK@ mask virtualization bits + cmp \tmp, #(1 CPUID_ARM_VIRT_SHIFT) +.endm + /* * secure monitor handler * U-boot calls this software interrupt in start.S * This is executed on a smc instruction, we use a smc #0 to switch * to non-secure state. - * We use only r0 and r1 here, due to constraints in the caller. + * r0, r1, r2: passed to the callee + * ip: target PC */ _secure_monitor: - mrc p15, 0, r1, c1, c1, 0 @ read SCR - bic r1, r1, #0x4e @ clear IRQ, FIQ, EA, nET bits - orr r1, r1, #0x31 @ enable NS, AW, FW bits + mrc p15, 0, r5, c1, c1, 0 @ read SCR + bic r5, r5, #0x4e @ clear IRQ, FIQ, EA, nET bits + orr r5, r5, #0x31 @ enable NS, AW, FW bits - mrc p15, 0, r0, c0, c1, 1 @ read ID_PFR1 - and r0, r0, #CPUID_ARM_VIRT_MASK@ mask virtualization bits - cmp r0, #(1 CPUID_ARM_VIRT_SHIFT) + mov r6, #SVC_MODE @ default mode is SVC + is_cpu_virt_capable r4 #ifdef CONFIG_ARMV7_VIRT - orreq r1, r1, #0x100 @ allow HVC instruction + orreq r5, r5, #0x100 @ allow HVC instruction + moveq r6, #HYP_MODE @ Enter the kernel as HYP #endif - mcr p15, 0, r1, c1, c1, 0 @ write SCR (with NS bit set) + mcr p15, 0, r5, c1, c1, 0 @ write SCR (with NS bit set) isb -#ifdef CONFIG_ARMV7_VIRT - mrceq p15, 0, r0, c12, c0, 1 @ get MVBAR value - mcreq p15, 4, r0, c12, c0, 0 @ write HVBAR -#endif bne 1f @ Reset CNTVOFF to 0 before leaving monitor mode - mrc p15, 0, r0, c0, c1, 1 @ read ID_PFR1 - andsr0, r0, #CPUID_ARM_GENTIMER_MASK@ test arch timer bits - movne r0, #0 - mcrrne p15, 4, r0, r0, c14 @ Reset CNTVOFF to zero + mrc p15, 0, r4, c0, c1, 1 @ read ID_PFR1 + andsr4, r4, #CPUID_ARM_GENTIMER_MASK@ test arch timer bits + movne r4, #0 + mcrrne p15, 4, r4, r4, c14 @ Reset CNTVOFF to zero 1: - movspc, lr @ return to non-secure SVC - -_hyp_trap: - mrs lr, elr_hyp @ for older asm: .byte 0x00, 0xe3, 0x0e, 0xe1 - mov pc, lr @ do no switch modes, but - @ return to caller - + mov lr, ip + mov ip, #(F_BIT | I_BIT | A_BIT)@ Set A, I and F + tst lr,
Re: [U-Boot] [PATCH] gpt: support random UUIDs without setting environment variables
Hello Rob,
Sorry for delay.
On 01/26/2015 04:44 PM, Rob Herring wrote:
Currently, an environment variable must be used to store the randomly
generated UUID for each partition. This is not necessary, so make storing
the UUID optional. Now passing uuid_disk and uuid are optional when random
UUIDs are enabled.
Signed-off-by: Rob Herring r...@kernel.org
---
common/cmd_gpt.c | 48 ++--
doc/README.gpt | 8 +---
2 files changed, 35 insertions(+), 21 deletions(-)
diff --git a/common/cmd_gpt.c b/common/cmd_gpt.c
index 75df3fe..c56fe15 100644
--- a/common/cmd_gpt.c
+++ b/common/cmd_gpt.c
@@ -154,17 +154,24 @@ static int set_gpt_info(block_dev_desc_t *dev_desc,
/* extract disk guid */
s = str;
- tok = strsep(s, ;);
- val = extract_val(tok, uuid_disk);
+ val = extract_val(str, uuid_disk);
if (!val) {
The code below is not required, since the same thing is done inside the
extract_env() function.
+#ifdef CONFIG_RANDOM_UUID
+ *str_disk_guid = malloc(UUID_STR_LEN + 1);
+ gen_rand_uuid_str(*str_disk_guid, UUID_STR_FORMAT_STD);
+#else
free(str);
return -2;
+#endif
+ } else {
+ val = strsep(val, ;);
+ if (extract_env(val, p))
+ p = val;
+ *str_disk_guid = strdup(p);
+ free(val);
+ /* Move s to first partition */
+ strsep(s, ;);
}
- if (extract_env(val, p))
- p = val;
- *str_disk_guid = strdup(p);
- free(val);
-
if (strlen(s) == 0)
return -3;
@@ -192,20 +199,25 @@ static int set_gpt_info(block_dev_desc_t *dev_desc,
/* uuid */
val = extract_val(tok, uuid);
- if (!val) { /* 'uuid' is mandatory */
- errno = -4;
- goto err;
- }
- if (extract_env(val, p))
- p = val;
- if (strlen(p) = sizeof(parts[i].uuid)) {
- printf(Wrong uuid format for partition %d\n, i);
+ if (!val) {
The same in this place - code duplication.
+ /* 'uuid' is optional if random uuid's are enabled */
+#ifdef CONFIG_RANDOM_UUID
+ gen_rand_uuid_str(parts[i].uuid, UUID_STR_FORMAT_STD);
+#else
errno = -4;
goto err;
+#endif
+ } else {
+ if (extract_env(val, p))
+ p = val;
+ if (strlen(p) = sizeof(parts[i].uuid)) {
+ printf(Wrong uuid format for partition %d\n,
i);
+ errno = -4;
+ goto err;
+ }
+ strcpy((char *)parts[i].uuid, p);
+ free(val);
}
- strcpy((char *)parts[i].uuid, p);
- free(val);
-
/* name */
val = extract_val(tok, name);
if (!val) { /* name is mandatory */
diff --git a/doc/README.gpt b/doc/README.gpt
index ec0156d..59fdeeb 100644
--- a/doc/README.gpt
+++ b/doc/README.gpt
@@ -157,11 +157,13 @@ To restore GUID partition table one needs to:
partitions=uuid_disk=${uuid_gpt_disk};name=${uboot_name},
size=${uboot_size},uuid=${uboot_uuid};
- Fields 'name', 'size' and 'uuid' are mandatory for every partition.
+ The fields 'name' and 'size' are mandatory for every partition.
The field 'start' is optional.
- option: CONFIG_RANDOM_UUID
- If any partition UUID no exists then it is randomly generated.
+ The fields 'uuid' and 'uuid_disk' are optional if CONFIG_RANDOM_UUID is
+ enabled. A random uuid will be used if omitted or they point to an empty/
+ non-existent environment variable. The environment variable will be set to
+ the generated UUID.
The things from the above comment are implemented at present in mainline.
2. Define 'CONFIG_EFI_PARTITION' and 'CONFIG_CMD_GPT'
If you want drop saving the uuid to env, then you can do it by modify
the extract_env() function (diff):
+#ifdef CONFIG_RANDOM_UUID_SKIP_SETENV
+ e = strdup(uuid_str);
+#else
setenv(s, uuid_str);
-
e = getenv(s);
+#endif
I would prefer introduce the new config like *SKIP_SETENV*, rather than
drop this feature at all, since somebody could use it.
Best regards,
--
Przemyslaw Marczak
Samsung RD Institute Poland
Samsung Electronics
p.marc...@samsung.com
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] gpt: fix error reporting on partition table write failures
Hello Rob, On 01/26/2015 04:43 PM, Rob Herring wrote: The gpt command always reports success even if writing the partition table failed. Propagate the return value of gpt_restore so we get proper status reported. Signed-off-by: Rob Herring r...@kernel.org --- common/cmd_gpt.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/common/cmd_gpt.c b/common/cmd_gpt.c index e38422d..75df3fe 100644 --- a/common/cmd_gpt.c +++ b/common/cmd_gpt.c @@ -281,11 +281,11 @@ static int gpt_default(block_dev_desc_t *blk_dev_desc, const char *str_part) } /* save partitions layout to disk */ - gpt_restore(blk_dev_desc, str_disk_guid, partitions, part_count); + ret = gpt_restore(blk_dev_desc, str_disk_guid, partitions, part_count); free(str_disk_guid); free(partitions); - return 0; + return ret; } /** This one commit, is ok. Reviewed-by: Przemyslaw Marczak p.marc...@samsung.com Best regards, -- Przemyslaw Marczak Samsung RD Institute Poland Samsung Electronics p.marc...@samsung.com ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Question on the max size of SPL and OMAP3 SRAM
On Tue, Feb 17, 2015 at 04:47:14PM -0800, Adam Lee wrote: I have a Gumstix Overo (OMAP3) with a 512MiB NAND. I have been validating BCH8 ecc scheme and one of the problems I ran into is this: arm-linux-gnueabi-ld.bfd: u-boot-spl section `.rodata' will not fit in region `.sram' arm-linux-gnueabi-ld.bfd: region `.sram' overflowed by 4092 bytes This happens because BCH8 support increases the size of my SPL to larger than 54KiB defined by CONFIG_SPL_MAX_SIZE in ti_omap3_common.h. My plan at the moment is to strip out unnecessary and unpopular features from SPL to save space. If I fail to fit my SPL under 54kiB, I'd like to know if it is safe to increase the size defined by config. This is probably your best bet. My hope is that as part of moving to Kconfig we can make these support choices easier. As per README.omap3, there is about 9KB (0x4020E000 - 0x4020BBFF) of unallocated space between the SPL data and SPL stack: Option 2 (SPL or X-Loader): 0x40200800 - 0x4020BBFF: Area for SPL text, data and rodata 0x4020E000 - 0x4020FFFC: Area for the SPL stack. Is this space being used for something? I'm sure there have been a good reason for this division. I would like to have some insight as to how and why. Well, the best answer is to check the TRM and see what it says about the ROM memory map. My recollection is that 0x40200800 - 0x4020BBFF is the download area and 0x4020E000 - 0x4020FFFC is what it calls the public stack and we decide to use it for our stack (rather than keeping it in the download area). The range inbetween (0x4020BC00 - 0x4020DFFF) is claimed by the ROM and we shouldn't touch it. Unless the TRM says something different of course. Thanks, Adam ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] omap_gpmc: Do not default to HAM1 when SW ECC is selected
Had a conversation with Ash @ Gumstix and he pointed out relying on
CONFIG_NAND_OMAP_ECCSCHEME could be dangerous as it could be anything other
than the two SW ECC schemes available for OMAP3.
Also it looks like making a selection between OMAP_ECC_BCH8_CODE_HW and
OMAP_ECC_BCH8_CODE_HW_DETECTION_SW may not make sense as the latter
clearly requires CONFIG_BCH, which enables software library for BCH.
On Wed, Feb 18, 2015 at 9:33 AM, Adam Lee adam.yh@gmail.com wrote:
Hi Andreas, for OMAP3 and AM35xx boards, it would have been ok omitting
the
CONFIG_BCH check and simply use CONFIG_NAND_OMAP_ECCSCHEME.
Those boards use the ecc scheme config already. However I just wasn't 100%
sure if I could rely on this config for all TI OMAP/AM based boards. I
know OMAP3
and AM35xx board configs already have CONFIG_NAND_OMAP_ECCSCHEME.
Should I check for other OMAP and AM series? The original ecc detection
function
seems to be written with an assumption that config is nonexistent - hence
defaulting
to HAM1.
That said, I agree that the whole omap_nand_switch_ecc() could be improved.
However, to me, the confusion arised from the fact that OMAP3 can do BCH8
hw ECC
calculation but needs software to do the correction. Hence my patch
changes the
software part of the omap_nand_switch_ecc(), and not the hardware part.
Just to clarify, what you are saying is that I should leave the software
part as it was (defaulting
to HAM1), and in the hardware part I should check for ELM support and
choose a BCH8
scheme accordingly, regardless of what's defined by
CONFIG_NAND_OMAP_ECCSCHEME?
In other words, I will run 'nandecc hw' to enable BCH8?
Let me know,
Thanks,
Adam
On Wed, Feb 18, 2015 at 6:14 AM, Andreas Bießmann
andreas.de...@googlemail.com wrote:
Hi Adam,
On 02/18/2015 03:58 AM, Adam YH Lee wrote:
The ECC scheme selection algorithm in OMAP GPMC appears to be left
untested when
BCH8 handling code was added. Running 'nandecc sw' defaults to HAM1
even if
the board is using another scheme (ex.
OMAP_ECC_BCH8_CODE_HW_DETECTION_SW on
OMAP3). This results in unrecoverable ECC errors when reading data.
This commit
fixes the behavior by checking for CONFIG_BCH and using the scheme
defined by
CONFIG_NAND_OMAP_ECCSCHEME in the board configuration file.
This has been tested on Gumstix Overo (OMAP3).
Signed-off-by: Adam YH Lee adam.yh@gmail.com
---
drivers/mtd/nand/omap_gpmc.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/mtd/nand/omap_gpmc.c b/drivers/mtd/nand/omap_gpmc.c
index fc64f48..5daf932 100644
--- a/drivers/mtd/nand/omap_gpmc.c
+++ b/drivers/mtd/nand/omap_gpmc.c
@@ -901,8 +901,13 @@ int __maybe_unused omap_nand_switch_ecc(uint32_t
hardware, uint32_t eccstrength)
return -EINVAL;
}
} else {
+ #ifdef CONFIG_BCH
+ err = omap_select_ecc_scheme(nand,
CONFIG_NAND_OMAP_ECCSCHEME,
+ mtd-writesize, mtd-oobsize);
+ #else
err = omap_select_ecc_scheme(nand, OMAP_ECC_HAM1_CODE_SW,
mtd-writesize, mtd-oobsize);
Couldn't we just use the CONFIG_NAND_OMAP_ECCSCHEME instead of
OMAP_ECC_HAM1_CODE_SW here and omit the CONFIG_BCH define?
On the other hand I think the whole function omap_nand_switch_ecc() is
wrong. AFAIR it should only be used on omap3 aka am35xx/dm37xx devices
witch the nandecc command.
These SoC do not have a ELM. Therefore I decided to say BCH8 on those
devices is always 'HW ECC' when introduced BCH8 on omap3 first. Nowadays
it is the so called BCH8_CODE_HW_DETECTION_SW. Coming from this mindset
the right solution is to use some detection if the ELM is supported or
not and switch in the HW part of omap_nand_switch_ecc() between
OMAP_ECC_BCH8_CODE_HW and OMAP_ECC_BCH8_CODE_HW_DETECTION_SW.
Best regards
Andreas Bießmann
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v1 1/1] fastboot: Update getvar command to get 'userdata' partition size
This patch adds functionality to getvar command to get the userdata partition
size.
Signed-off-by: Dileep Katta dileep.ka...@linaro.org
---
common/fb_mmc.c | 38 ++
drivers/usb/gadget/f_fastboot.c | 2 ++
include/fb_mmc.h| 2 ++
3 files changed, 42 insertions(+)
diff --git a/common/fb_mmc.c b/common/fb_mmc.c
index 6ea3938..1bb6335 100644
--- a/common/fb_mmc.c
+++ b/common/fb_mmc.c
@@ -32,6 +32,44 @@ void fastboot_okay(const char *s)
strncat(response_str, s, RESPONSE_LEN - 4 - 1);
}
+void fb_mmc_get_ptn_size(const char *cmd, char *response)
+{
+ int ret;
+ block_dev_desc_t *dev_desc;
+ disk_partition_t info;
+ u32 sz_mb;
+ u64 sz = 0;
+ char buf[RESPONSE_LEN];
+
+ /* initialize the response buffer */
+ response_str = response;
+
+ dev_desc = get_dev(mmc, CONFIG_FASTBOOT_FLASH_MMC_DEV);
+ if (!dev_desc || dev_desc-type == DEV_TYPE_UNKNOWN) {
+ error(invalid mmc device);
+ fastboot_fail(invalid mmc device);
+ return;
+ }
+
+ ret = get_partition_info_efi_by_name(dev_desc, cmd, info);
+ if (ret) {
+ error(cannot find partition: '%s', cmd);
+ fastboot_fail(cannot find partition);
+ return;
+ }
+
+ sz = (info.size * (u64)info.blksz) 10;
+
+ if (sz = 0x) {
+ sz_mb = (u32)(sz 10);
+ sprintf(buf, 0x%d MB, sz_mb);
+ fastboot_okay(buf);
+ } else {
+ sprintf(buf, %d KB, (u32)sz);
+ fastboot_okay(buf);
+ }
+}
+
static void write_raw_image(block_dev_desc_t *dev_desc, disk_partition_t *info,
const char *part_name, void *buffer,
unsigned int download_bytes)
diff --git a/drivers/usb/gadget/f_fastboot.c b/drivers/usb/gadget/f_fastboot.c
index 310175a..17b64ef 100644
--- a/drivers/usb/gadget/f_fastboot.c
+++ b/drivers/usb/gadget/f_fastboot.c
@@ -363,6 +363,8 @@ static void cb_getvar(struct usb_ep *ep, struct usb_request
*req)
strncat(response, s, chars_left);
else
strcpy(response, FAILValue not set);
+ } else if (!strcmp_l1(userdata_size, cmd)) {
+ fb_mmc_get_ptn_size(userdata, response);
} else {
error(unknown variable: %s\n, cmd);
strcpy(response, FAILVariable not implemented);
diff --git a/include/fb_mmc.h b/include/fb_mmc.h
index 1ad1d13..353f325 100644
--- a/include/fb_mmc.h
+++ b/include/fb_mmc.h
@@ -4,5 +4,7 @@
* SPDX-License-Identifier:GPL-2.0+
*/
+void fb_mmc_get_ptn_size(const char *cmd, char *response);
+
void fb_mmc_flash_write(const char *cmd, void *download_buffer,
unsigned int download_bytes, char *response);
--
1.8.3.2
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 0/3] Add generic early debug UART feature
On Tue, Feb 17, 2015 at 08:22:17PM -0700, Simon Glass wrote: +tom, and pruning the cc list a little Hi, On 26 January 2015 at 18:27, Simon Glass s...@chromium.org wrote: This series adds debug UART infrastructure which can in principle be used on any architecture. It works best with those that don't need a stack to call functions (e.g. ARM, PowerPC). I'd really quite like to apply this series. I have used it on PowerPC and x86 and found it quite useful. Any objections? No, lets take it and work from there. -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 13/22] dm: pci: Add a uclass for PCI
Add a uclass for PCI controllers and a generic one for PCI devices. Adjust
the 'pci' command and the existing PCI support to work with this new uclass.
Keep most of the compatibility code in a separate file so that it can be
removed one day.
TODO: Add more header file comments to the new parts of pci.h
Signed-off-by: Simon Glass s...@chromium.org
---
common/board_r.c | 2 +
common/cmd_pci.c | 14 +-
doc/driver-model/pci-info.txt | 70 +
drivers/pci/Kconfig | 12 +
drivers/pci/Makefile | 8 +-
drivers/pci/pci-uclass.c | 639 ++
drivers/pci/pci_auto.c| 16 +-
drivers/pci/pci_compat.c | 43 +++
include/dm/uclass-id.h| 2 +
include/pci.h | 289 ++-
10 files changed, 1081 insertions(+), 14 deletions(-)
create mode 100644 doc/driver-model/pci-info.txt
create mode 100644 drivers/pci/pci-uclass.c
create mode 100644 drivers/pci/pci_compat.c
diff --git a/common/board_r.c b/common/board_r.c
index 907b33c..19e3f3c 100644
--- a/common/board_r.c
+++ b/common/board_r.c
@@ -224,7 +224,9 @@ static int initr_unlock_ram_in_cache(void)
#ifdef CONFIG_PCI
static int initr_pci(void)
{
+#ifndef CONFIG_DM_PCI
pci_init();
+#endif
return 0;
}
diff --git a/common/cmd_pci.c b/common/cmd_pci.c
index e3a77e3..dcecef8 100644
--- a/common/cmd_pci.c
+++ b/common/cmd_pci.c
@@ -48,6 +48,7 @@ void pciinfo(int BusNum, int ShortPCIListing)
unsigned char HeaderType;
unsigned short VendorID;
pci_dev_t dev;
+ int ret;
if (!hose)
return;
@@ -74,7 +75,10 @@ void pciinfo(int BusNum, int ShortPCIListing)
if (pci_skip_dev(hose, dev))
continue;
- pci_read_config_word(dev, PCI_VENDOR_ID, VendorID);
+ ret = pci_read_config_word(dev, PCI_VENDOR_ID,
+ VendorID);
+ if (ret)
+ goto error;
if ((VendorID == 0x) || (VendorID == 0x))
continue;
@@ -91,8 +95,12 @@ void pciinfo(int BusNum, int ShortPCIListing)
BusNum, Device, Function);
pci_header_show(dev);
}
- }
-}
+ }
+ }
+
+ return;
+error:
+ printf(Cannot read bus configuration: %d\n, ret);
}
diff --git a/doc/driver-model/pci-info.txt b/doc/driver-model/pci-info.txt
new file mode 100644
index 000..63efcb7
--- /dev/null
+++ b/doc/driver-model/pci-info.txt
@@ -0,0 +1,70 @@
+PCI with Driver Model
+=
+
+How busses are scanned
+--
+
+Any config read will end up at pci_read_config(). This uses
+uclass_get_device_by_seq() to get the PCI bus for a particular bus number.
+Bus number 0 will need to be requested first, and the alias in the device
+tree file will point to the correct device:
+
+
+ aliases {
+ pci0 = pci;
+ };
+
+ pci: pci-controller {
+ compatible = sandbox,pci;
+ ...
+ };
+
+
+If there is no alias the devices will be numbered sequentially in the device
+tree.
+
+The call to uclass_get_device by seq() will cause the PCI bus to be probed.
+This does a scan of the bus to locate available devices. These devices are
+bound to their appropriate driver if available. If there is no driver, then
+they are bound to a generic PCI driver which does nothing.
+
+After probing a bus, the available devices will appear in the device tree
+under that bus.
+
+Note that this is all done on a lazy basis, as needed, so until something is
+touched on PCI it will not be probed.
+
+PCI devices can appear in the device tree. If they do this serves to specify
+the driver to use for the device. In this case they will be bound at
+start-up.
+
+
+Sandbox
+---
+
+With sandbox we need a device emulator for each device on the bus since there
+is no real PCI bus. This works by looking in the device tree node for a
+driver. For example:
+
+
+ pci@1f,0 {
+ compatible = pci-generic;
+ reg = 0xf800 0 0 0 0;
+ emul@1f,0 {
+ compatible = sandbox,swap-case;
+ };
+ };
+
+This means that there is a 'sandbox,swap-case' driver at that bus position.
+Note that the first cell in the 'reg' value is the bus/device/function. See
+PCI_BDF() for the encoding (it is also specified in the IEEE Std 1275-1994
+PCI bus binding document, v2.1)
+
+When this bus is scanned we will end up with something like this:
+
+`- * pci-controller @ 05c660c8, 0
+ `- pci@1f,0 @ 05c661c8, 63488
+ `- emul@1f,0 @ 05c662c8
+
+When accesses go to the pci@1f,0 device they are forwarded to its child, the
+emulator.
diff --git
[U-Boot] [PATCH 16/22] dm: sandbox: pci: Add a PCI emulation uclass
Since sandbox does not have real devices (unless it borrows those from the
host) it must use emulations. Provide a uclass which permits PCI operations
to be passed through to an emulation device.
Signed-off-by: Simon Glass s...@chromium.org
---
drivers/pci/Makefile | 1 +
drivers/pci/pci-emul-uclass.c | 67 ++
include/dm/uclass-id.h| 1 +
include/pci.h | 108 ++
4 files changed, 177 insertions(+)
create mode 100644 drivers/pci/pci-emul-uclass.c
diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
index 9e2e5f9..c1c2ae3 100644
--- a/drivers/pci/Makefile
+++ b/drivers/pci/Makefile
@@ -8,6 +8,7 @@
ifneq ($(CONFIG_DM_PCI),)
obj-$(CONFIG_PCI) += pci-uclass.o pci_compat.o
obj-$(CONFIG_PCI_SANDBOX) += pci_sandbox.o
+obj-$(CONFIG_SANDBOX) += pci-emul-uclass.o
else
obj-$(CONFIG_PCI) += pci.o
endif
diff --git a/drivers/pci/pci-emul-uclass.c b/drivers/pci/pci-emul-uclass.c
new file mode 100644
index 000..0f8e3c9
--- /dev/null
+++ b/drivers/pci/pci-emul-uclass.c
@@ -0,0 +1,67 @@
+/*
+ * Copyright (c) 2014 Google, Inc
+ * Written by Simon Glass s...@chromium.org
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include dm.h
+#include fdtdec.h
+#include libfdt.h
+#include pci.h
+#include dm/lists.h
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct sandbox_pci_priv {
+ int dev_count;
+};
+
+int sandbox_pci_get_emul(struct udevice *bus, pci_dev_t find_devfn,
+struct udevice **emulp)
+{
+ struct udevice *dev;
+ int ret;
+
+ ret = pci_bus_find_devfn(bus, find_devfn, dev);
+ if (ret) {
+ debug(%s: Could not find emulator for dev %x\n, __func__,
+ find_devfn);
+ return ret;
+ }
+
+ ret = device_find_first_child(dev, emulp);
+ if (ret)
+ return ret;
+
+ return *emulp ? 0 : -ENODEV;
+}
+
+static int sandbox_pci_emul_post_probe(struct udevice *dev)
+{
+ struct sandbox_pci_priv *priv = dev-uclass-priv;
+
+ priv-dev_count++;
+ sandbox_set_enable_pci_map(true);
+
+ return 0;
+}
+
+static int sandbox_pci_emul_pre_remove(struct udevice *dev)
+{
+ struct sandbox_pci_priv *priv = dev-uclass-priv;
+
+ priv-dev_count--;
+ sandbox_set_enable_pci_map(priv-dev_count 0);
+
+ return 0;
+}
+
+UCLASS_DRIVER(pci_emul) = {
+ .id = UCLASS_PCI_EMUL,
+ .name = pci_emul,
+ .post_probe = sandbox_pci_emul_post_probe,
+ .pre_remove = sandbox_pci_emul_pre_remove,
+ .priv_auto_alloc_size = sizeof(struct sandbox_pci_priv),
+};
diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h
index b984407..0b6e850 100644
--- a/include/dm/uclass-id.h
+++ b/include/dm/uclass-id.h
@@ -20,6 +20,7 @@ enum uclass_id {
UCLASS_TEST_BUS,
UCLASS_SPI_EMUL,/* sandbox SPI device emulator */
UCLASS_I2C_EMUL,/* sandbox I2C device emulator */
+ UCLASS_PCI_EMUL,/* sandbox PCI device emulator */
UCLASS_SIMPLE_BUS,
/* U-Boot uclasses start here */
diff --git a/include/pci.h b/include/pci.h
index 07345fd..07b1e9a 100644
--- a/include/pci.h
+++ b/include/pci.h
@@ -992,6 +992,114 @@ static inline int pci_read_config_byte(pci_dev_t pcidev,
int offset,
return pci_read_config8(pcidev, offset, valuep);
}
+/**
+ * struct dm_pci_emul_ops - PCI device emulator operations
+ */
+struct dm_pci_emul_ops {
+ /**
+* get_devfn(): Check which device and function this emulators
+*
+* @dev:device to check
+* @return the device and function this emulates, or -ve on error
+*/
+ int (*get_devfn)(struct udevice *dev);
+ /**
+* read_config() - Read a PCI configuration value
+*
+* @dev:Emulated device to read from
+* @offset: Byte offset within the device's configuration space
+* @valuep: Place to put the returned value
+* @size: Access size
+* @return 0 if OK, -ve on error
+*/
+ int (*read_config)(struct udevice *dev, uint offset, ulong *valuep,
+ enum pci_size_t size);
+ /**
+* write_config() - Write a PCI configuration value
+*
+* @dev:Emulated device to write to
+* @offset: Byte offset within the device's configuration space
+* @value: Value to write
+* @size: Access size
+* @return 0 if OK, -ve on error
+*/
+ int (*write_config)(struct udevice *dev, uint offset, ulong value,
+ enum pci_size_t size);
+ /**
+* read_io() - Read a PCI I/O value
+*
+* @dev:Emulated device to read from
+* @addr: I/O address to read
+* @valuep: Place to put the returned value
+* @size:
[U-Boot] [PATCH 20/22] dm: x86: pci: Convert coreboot to use driver model for pci
Move coreboot-x86 over to driver model for PCI.
Signed-off-by: Simon Glass s...@chromium.org
---
arch/x86/cpu/coreboot/pci.c | 63 ++---
arch/x86/dts/chromebook_link.dts| 7 +
board/google/chromebook_link/link.c | 9 ++
configs/coreboot-x86_defconfig | 1 +
include/dm/uclass-id.h | 1 +
5 files changed, 34 insertions(+), 47 deletions(-)
diff --git a/arch/x86/cpu/coreboot/pci.c b/arch/x86/cpu/coreboot/pci.c
index c9983f1..fa415dd 100644
--- a/arch/x86/cpu/coreboot/pci.c
+++ b/arch/x86/cpu/coreboot/pci.c
@@ -10,58 +10,27 @@
*/
#include common.h
+#include dm.h
+#include errno.h
#include pci.h
+#include asm/io.h
#include asm/pci.h
DECLARE_GLOBAL_DATA_PTR;
-static void config_pci_bridge(struct pci_controller *hose, pci_dev_t dev,
- struct pci_config_table *table)
-{
- u8 secondary;
- hose-read_byte(hose, dev, PCI_SECONDARY_BUS, secondary);
- hose-last_busno = max(hose-last_busno, (int)secondary);
- pci_hose_scan_bus(hose, secondary);
-}
-
-static struct pci_config_table pci_coreboot_config_table[] = {
- /* vendor, device, class, bus, dev, func */
- { PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_BRIDGE_PCI,
- PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, config_pci_bridge },
- {}
+static const struct dm_pci_ops pci_x86_ops = {
+ .read_config= pci_x86_read_config,
+ .write_config = pci_x86_write_config,
};
-void board_pci_setup_hose(struct pci_controller *hose)
-{
- hose-config_table = pci_coreboot_config_table;
- hose-first_busno = 0;
- hose-last_busno = 0;
-
- /* PCI memory space */
- pci_set_region(hose-regions + 0,
- CONFIG_PCI_MEM_BUS,
- CONFIG_PCI_MEM_PHYS,
- CONFIG_PCI_MEM_SIZE,
- PCI_REGION_MEM);
-
- /* PCI IO space */
- pci_set_region(hose-regions + 1,
- CONFIG_PCI_IO_BUS,
- CONFIG_PCI_IO_PHYS,
- CONFIG_PCI_IO_SIZE,
- PCI_REGION_IO);
-
- pci_set_region(hose-regions + 2,
- CONFIG_PCI_PREF_BUS,
- CONFIG_PCI_PREF_PHYS,
- CONFIG_PCI_PREF_SIZE,
- PCI_REGION_PREFETCH);
-
- pci_set_region(hose-regions + 3,
- 0,
- 0,
- gd-ram_size,
- PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
+static const struct udevice_id pci_x86_ids[] = {
+ { .compatible = pci-x86 },
+ { }
+};
- hose-region_count = 4;
-}
+U_BOOT_DRIVER(pci_x86_drv) = {
+ .name = pci_x86,
+ .id = UCLASS_PCI,
+ .of_match = pci_x86_ids,
+ .ops= pci_x86_ops,
+};
diff --git a/arch/x86/dts/chromebook_link.dts b/arch/x86/dts/chromebook_link.dts
index 45ada61..cdbdb68 100644
--- a/arch/x86/dts/chromebook_link.dts
+++ b/arch/x86/dts/chromebook_link.dts
@@ -172,6 +172,13 @@
};
pci {
+ compatible = intel,pci-ivybridge, pci-x86;
+ #address-cells = 3;
+ #size-cells = 2;
+ u-boot,dm-pre-reloc;
+ ranges = 0x0200 0x0 0xe000 0xe000 0 0x1000
+ 0x4200 0x0 0xd000 0xd000 0 0x1000
+ 0x0100 0x0 0x1000 0x1000 0 0xefff;
sata {
compatible = intel,pantherpoint-ahci;
intel,sata-mode = ahci;
diff --git a/board/google/chromebook_link/link.c
b/board/google/chromebook_link/link.c
index 9ebbb9f..5158e3b 100644
--- a/board/google/chromebook_link/link.c
+++ b/board/google/chromebook_link/link.c
@@ -6,6 +6,7 @@
#include common.h
#include cros_ec.h
+#include dm.h
#include asm/gpio.h
#include asm/io.h
#include asm/pci.h
@@ -13,6 +14,14 @@
int arch_early_init_r(void)
{
+ struct udevice *dev;
+ int ret;
+
+ /* Make sure the platform controller hub is up and running */
+ ret = uclass_get_device(UCLASS_PCH, 0, dev);
+ if (ret)
+ return ret;
+
if (cros_ec_board_init())
return -1;
diff --git a/configs/coreboot-x86_defconfig b/configs/coreboot-x86_defconfig
index 3cc034a..0249172 100644
--- a/configs/coreboot-x86_defconfig
+++ b/configs/coreboot-x86_defconfig
@@ -2,3 +2,4 @@ CONFIG_SYS_EXTRA_OPTIONS=SYS_TEXT_BASE=0x0111
CONFIG_X86=y
CONFIG_TARGET_COREBOOT=y
CONFIG_OF_CONTROL=y
+CONFIG_DM_PCI=y
diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h
index 0b6e850..047ac15 100644
--- a/include/dm/uclass-id.h
+++ b/include/dm/uclass-id.h
@@ -37,6 +37,7 @@ enum uclass_id {
UCLASS_MOD_EXP, /* RSA Mod Exp device */
UCLASS_PCI, /* PCI bus */
UCLASS_PCI_GENERIC, /* Generic PCI bus device */
+ UCLASS_PCH,
[U-Boot] [PATCH 07/22] fdt: Tighten up error handling in fdtdec_get_pci_addr()
This function returns -ENOENT when the property is missing (which the caller
might forgive) and also when the property is present but incorrectly
formatted (which many callers would like to report).
Update the error return value to allow these different situations to be
distinguished.
Signed-off-by: Simon Glass s...@chromium.org
---
include/fdtdec.h | 4 +++-
lib/fdtdec.c | 4 +++-
2 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/include/fdtdec.h b/include/fdtdec.h
index 2a96a0a..3213895 100644
--- a/include/fdtdec.h
+++ b/include/fdtdec.h
@@ -326,7 +326,9 @@ fdt_addr_t fdtdec_get_addr_size(const void *blob, int node,
* @param type pci address type (FDT_PCI_SPACE_xxx)
* @param prop_namename of property to find
* @param addr returns pci address in the form of fdt_pci_addr
- * @return 0 if ok, negative on error
+ * @return 0 if ok, -ENOENT if the property did not exist, -EINVAL if the
+ * format of the property was invalid, -ENXIO if the requested
+ * address type was not found
*/
int fdtdec_get_pci_addr(const void *blob, int node, enum fdt_pci_space type,
const char *prop_name, struct fdt_pci_addr *addr);
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index d4bc8b4..922b299 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -159,8 +159,10 @@ int fdtdec_get_pci_addr(const void *blob, int node, enum
fdt_pci_space type,
}
}
- if (i == num)
+ if (i == num) {
+ ret = ENXIO;
goto fail;
+ }
return 0;
} else {
--
2.2.0.rc0.207.ga3a616c
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 11/22] dm: Show both allocated and requested seq numbers in 'dm uclass'
Both of these values are useful for understanding what is going on, so show them both. The requested number comes from a device tree alias. The allocated one is set up when the device is activated, and is unique throughout the uclass. Signed-off-by: Simon Glass s...@chromium.org --- test/dm/cmd_dm.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/test/dm/cmd_dm.c b/test/dm/cmd_dm.c index 79a674e..507f260 100644 --- a/test/dm/cmd_dm.c +++ b/test/dm/cmd_dm.c @@ -77,8 +77,8 @@ static void dm_display_line(struct udevice *dev) printf(- %c %s @ %08lx, dev-flags DM_FLAG_ACTIVATED ? '*' : ' ', dev-name, (ulong)map_to_sysmem(dev)); - if (dev-req_seq != -1) - printf(, %d, dev-req_seq); + if (dev-seq != -1 || dev-req_seq != -1) + printf(, seq-%d, (req=%d), dev-seq, dev-req_seq); puts(\n); } -- 2.2.0.rc0.207.ga3a616c ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 06/22] Correct map_sysmem() logic in do_mem_mw()
This function does not unmap what it maps. Correct it.
Signed-off-by: Simon Glass s...@chromium.org
---
common/cmd_mem.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/common/cmd_mem.c b/common/cmd_mem.c
index bcb3ee3..855aa57 100644
--- a/common/cmd_mem.c
+++ b/common/cmd_mem.c
@@ -165,7 +165,7 @@ static int do_mem_mw(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
#endif
ulong addr, count;
int size;
- void *buf;
+ void *buf, *start;
ulong bytes;
if ((argc 3) || (argc 4))
@@ -197,7 +197,8 @@ static int do_mem_mw(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
}
bytes = size * count;
- buf = map_sysmem(addr, bytes);
+ start = map_sysmem(addr, bytes);
+ buf = start;
while (count-- 0) {
if (size == 4)
*((u32 *)buf) = (u32)writeval;
@@ -211,7 +212,7 @@ static int do_mem_mw(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
*((u8 *)buf) = (u8)writeval;
buf += size;
}
- unmap_sysmem(buf);
+ unmap_sysmem(start);
return 0;
}
--
2.2.0.rc0.207.ga3a616c
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 22/22] dm: pci: Add driver model tests for PCI
Add some basic tests to check that things work as expected with sandbox.
Signed-off-by: Simon Glass s...@chromium.org
---
test/dm/Makefile | 1 +
test/dm/pci.c| 59
test/dm/test.dts | 17
3 files changed, 77 insertions(+)
create mode 100644 test/dm/pci.c
diff --git a/test/dm/Makefile b/test/dm/Makefile
index 612aa95..8281779 100644
--- a/test/dm/Makefile
+++ b/test/dm/Makefile
@@ -21,4 +21,5 @@ obj-$(CONFIG_DM_GPIO) += gpio.o
obj-$(CONFIG_DM_SPI) += spi.o
obj-$(CONFIG_DM_SPI_FLASH) += sf.o
obj-$(CONFIG_DM_I2C) += i2c.o
+obj-$(CONFIG_DM_PCI) += pci.o
endif
diff --git a/test/dm/pci.c b/test/dm/pci.c
new file mode 100644
index 000..6c63fa4
--- /dev/null
+++ b/test/dm/pci.c
@@ -0,0 +1,59 @@
+/*
+ * Copyright (C) 2015 Google, Inc
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include dm.h
+#include asm/io.h
+#include dm/test.h
+#include dm/ut.h
+
+/* Test that sandbox PCI works correctly */
+static int dm_test_pci_base(struct dm_test_state *dms)
+{
+ struct udevice *bus;
+
+ ut_assertok(uclass_get_device(UCLASS_PCI, 0, bus));
+
+ return 0;
+}
+DM_TEST(dm_test_pci_base, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
+
+/* Test that we can use the swapcase device correctly */
+static int dm_test_pci_swapcase(struct dm_test_state *dms)
+{
+ pci_dev_t pci_dev = PCI_BDF(0, 0x1f, 0);
+ struct pci_controller *hose;
+ struct udevice *bus, *swap;
+ ulong io_addr, mem_addr;
+ char *ptr;
+
+ /* Check that asking for the device automatically fires up PCI */
+ ut_assertok(uclass_get_device(UCLASS_PCI_EMUL, 0, swap));
+
+ ut_assertok(uclass_get_device(UCLASS_PCI, 0, bus));
+ hose = dev_get_uclass_priv(bus);
+
+ /* First test I/O */
+ io_addr = pci_read_bar32(hose, pci_dev, 0);
+ outb(2, io_addr);
+ ut_asserteq(2, inb(io_addr));
+
+ /*
+* Now test memory mapping - note we must unmap and remap to cause
+* the swapcase emulation to see our data and response.
+*/
+ mem_addr = pci_read_bar32(hose, pci_dev, 1);
+ ptr = map_sysmem(mem_addr, 20);
+ strcpy(ptr, This is a TesT);
+ unmap_sysmem(ptr);
+
+ ptr = map_sysmem(mem_addr, 20);
+ ut_asserteq_str(tHIS IS A tESt, ptr);
+ unmap_sysmem(ptr);
+
+ return 0;
+}
+DM_TEST(dm_test_pci_swapcase, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
diff --git a/test/dm/test.dts b/test/dm/test.dts
index 84024a4..96775e1 100644
--- a/test/dm/test.dts
+++ b/test/dm/test.dts
@@ -10,6 +10,7 @@
console = uart0;
i2c0 = /i2c@0;
spi0 = /spi@0;
+ pci0 = pci;
testfdt6 = /e-test;
testbus3 = /some-bus;
testfdt0 = /some-bus/c-test@0;
@@ -135,6 +136,22 @@
};
};
+ pci: pci-controller {
+ compatible = sandbox,pci;
+ device_type = pci;
+ #address-cells = 3;
+ #size-cells = 2;
+ ranges = 0x0200 0 0x1000 0x1000 0 0x2000
+ 0x0100 0 0x2000 0x2000 0 0x2000;
+ pci@1f,0 {
+ compatible = pci-generic;
+ reg = 0xf800 0 0 0 0;
+ emul@1f,0 {
+ compatible = sandbox,swap-case;
+ };
+ };
+ };
+
spi@0 {
#address-cells = 1;
#size-cells = 0;
--
2.2.0.rc0.207.ga3a616c
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PULL] u-boot-socfpga/master
On Wednesday, February 18, 2015 at 04:04:07 AM, Tom Rini wrote:
On Tue, Feb 17, 2015 at 09:11:01PM +0100, Marek Vasut wrote:
Hi Tom,
SoCFPGA stuff for current release.
The following changes since commit 7f641d53bbb3a426a3bfb132d8346153e86a9d08:
Merge branch 'master' of git://git.denx.de/u-boot-ubi (2015-02-04
13:30:00
-0500)
are available in the git repository at:
git://git.denx.de/u-boot-socfpga.git HEAD
for you to fetch changes up to 6da3e0c1758f7316025e342ef0801efba9bd7f23:
dt: socfpga: Import and enable Arria V DK DTS (2015-02-09 20:10:22
+0100)
I see:
$ ./tools/buildman/buildman -ve socfpga_arria5
boards.cfg is up to date. Nothing to do.
Building current source for 1 boards (1 thread, 6 jobs per thread)
arm: + socfpga_arria5
+ priv-qspi_calibrated_cs = spi_chip_select(bus);
+ ^
+drivers/spi/cadence_qspi.c: At top level:
+drivers/spi/cadence_qspi.c:320:21: error: variable 'cadence_spi_ops' has
initializer but incomplete type + static const struct dm_spi_ops
cadence_spi_ops = {
+ ^
+drivers/spi/cadence_qspi.c:321:2: error: unknown field 'xfer' specified in
initializer + .xfer = cadence_spi_xfer,
+drivers/spi/cadence_qspi.c:322:2: error: unknown field 'set_speed'
specified in initializer + .set_speed = cadence_spi_set_speed,
+drivers/spi/cadence_qspi.c:323:2: error: unknown field 'set_mode'
specified in initializer + .set_mode = cadence_spi_set_mode,
+make[2]: *** [drivers/spi/cadence_qspi.o] Error 1
+make[1]: *** [drivers/spi] Error 2
+make: *** [sub-make] Error 2
w+drivers/spi/cadence_qspi.c: In function 'spi_calibration':
w+drivers/spi/cadence_qspi.c:115:2: warning: implicit declaration of
function 'spi_chip_select' [-Wimplicit-function-declaration]
w+drivers/spi/cadence_qspi.c:321:2: warning: excess elements in struct
initializer [enabled by default] w+drivers/spi/cadence_qspi.c:321:2:
warning: (near initialization for 'cadence_spi_ops') [enabled by default]
w+drivers/spi/cadence_qspi.c:322:2: warning: excess elements in struct
initializer [enabled by default] w+drivers/spi/cadence_qspi.c:322:2:
warning: (near initialization for 'cadence_spi_ops') [enabled by default]
w+drivers/spi/cadence_qspi.c:323:2: warning: excess elements in struct
initializer [enabled by default] w+drivers/spi/cadence_qspi.c:323:2:
warning: (near initialization for 'cadence_spi_ops') [enabled by default]
001 /1 socfpga_arria5
$
Damn. I'll send fixes for this.
Best regards,
Marek Vasut
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/2] dm: Protect device_unbind() with CONFIG_DM_DEVICE_REMOVE
Since device_unbind() is also defined in device-remove.c,
which is compiled in only in case CONFIG_DM_DEVICE_REMOVE
is defined, protect the device_unbind() prototype with the
same CONFIG_DM_DEVICE_REMOVE check.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Simon Glass s...@chromium.org
Cc: Stefan Roese s...@denx.de
Cc: Tom Rini tr...@ti.com
---
include/dm/device-internal.h | 4
1 file changed, 4 insertions(+)
diff --git a/include/dm/device-internal.h b/include/dm/device-internal.h
index f0cc794..e2418fe 100644
--- a/include/dm/device-internal.h
+++ b/include/dm/device-internal.h
@@ -101,7 +101,11 @@ static inline int device_remove(struct udevice *dev) {
return 0; }
* @dev: Pointer to device to unbind
* @return 0 if OK, -ve on error
*/
+#ifdef CONFIG_DM_DEVICE_REMOVE
int device_unbind(struct udevice *dev);
+#else
+static inline int device_unbind(struct udevice *dev) { return 0; }
+#endif
#ifdef CONFIG_DM_DEVICE_REMOVE
void device_free(struct udevice *dev);
--
2.1.3
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 2/2] arm: socfpga: Enable DM for Cadence and DW SPI
Enable DM in case these two drivers are enabled, since these two drivers depend on DM. Signed-off-by: Marek Vasut ma...@denx.de Cc: Simon Glass s...@chromium.org Cc: Stefan Roese s...@denx.de Cc: Tom Rini tr...@ti.com --- include/configs/socfpga_common.h | 4 1 file changed, 4 insertions(+) diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index 6d93472..28fcbf3 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -190,6 +190,8 @@ unsigned int cm_get_l4_sp_clk_hz(void); */ #ifdef CONFIG_OF_CONTROL /* QSPI is controlled via DT */ #define CONFIG_CADENCE_QSPI +#define CONFIG_DM +#define CONFIG_DM_SPI /* Enable multiple SPI NOR flash manufacturers */ #define CONFIG_SPI_FLASH /* SPI flash subsystem */ #define CONFIG_SPI_FLASH_STMICRO /* Micron/Numonyx flash */ @@ -207,6 +209,8 @@ unsigned int cm_get_qspi_controller_clk_hz(void); #ifdef CONFIG_OF_CONTROL /* DW SPI is controlled via DT */ #define CONFIG_DESIGNWARE_SPI #define CONFIG_CMD_SPI +#define CONFIG_DM +#define CONFIG_DM_SPI #endif /* -- 2.1.3 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 0/22] Add driver model support for PCI
This series is a collection of changes in core DM, sandbox, x86 and PCI code to implement a PCI uclass and associated operations. Some basic tests are provided as well. As is becoming common with DM conversions, the existing structure (here struct pci_controller) becomes per-bus uclass data. This allows the concept of a 'hose' (generally a PCI host controller and a bus) to continue to exist in the interim, even if it should not be needed in the end. This makes it much easier to convert over existing code. PCI buses are not scanned in the bind() method but only later when probe() is called. This will be automatic if you access a bus, but it does mean that if PCI is not used it will not be touched, in keeping with U-Boot's lazy- init philosophy. The existing 'pciauto' bus configuration code is still used, although it now uses DM underneath. It works exclusively by reading and writing PCI config and does not refer to DM data structures. The one change is to drop use of the hose-current_busno field which is no longer required. The fact that file works largely as before is an indication that a good level of compatibility is achieved between DM and legacy PCI. In order to support testing of PCI I/O and memory space, support has been added to sandbox to allow mapping of these. This allows commands like 'md' and 'iod' to display data from mapped PCI devices. Similarly, it is possible to make changes to this space. This support relies on the existing map_sysmem() and unmap_sysmem() calls which are now fairly widespread in U-Boot. Apart from the driver model tests (run with ./test/dm/test-dm.sh) you can try out these commands which use the new 'swap_case' test device: ../u-boot -d b/sandbox/u-boot.dtb = iow.b 2000 2 = iod.b 2000 : 02 = mw.l 1000 64436241 = md.l 1000 1 1000: 44634261 aBcD = This shows an I/O access to 2000, setting the value 2 which means to swap the case. Then 'AbCd' is written to the memory space at 1000 and 'aBcD' is read back. The 'pci' command can be used as before. Most existing PCI functions (in pci.h) still work, but route through driver model. The file drivers/pci/pci.c is replaced when driver model is enabled so not everything is present. A new pci_common.c file holds functions common to driver model and the old system, and pci_compat.c contains functions I would like to eventually deprecate. Two x86 boards (coreboot and chromebook_link) are converted over to use driver model for PCI. Core driver model changes include: - Addition of a new pre_probe() method for the uclass to set up devices just before the device's probe() method is called - A change in the ordering of when a device is marked as probed - A dev_get_uclass_priv() accessor - A tweak to the 'dm uclass' command to improve sequence number display Notably missing from this series are functions to access PCI devices using a 'struct udevice *'. Where there is no device tree entry for a bus device, a generic PCI device is created in driver model to mirror the device, as with I2C and SPI. Future work could add more real devices to x86 and create a demand for these sorts of functions. Also we might store things like the PCI base address registers (BARs) in data structures if there is a need. These things are probably best developed as a need arises to avoid creating infrastructure and overhead that may not be used. This series is available at u-boot-dm.git branch pci-working. Simon Glass (22): dm: i2c: Add a missing memory allocaton check sandbox: Correct device tree 'reg' properties for I2C and SPI fdt: Export fdtdec_get_number() for general use x86: Add a x86_ prefix to the x86-specific PCI functions RFC: x86: Split up arch_cpu_init() Correct map_sysmem() logic in do_mem_mw() fdt: Tighten up error handling in fdtdec_get_pci_addr() dm: core: Add dev_get_uclass_priv() to access uclass private data dm: core: Mark device as active before calling its probe() method dm: core: Add a uclass pre_probe() method for devices dm: Show both allocated and requested seq numbers in 'dm uclass' dm: pci: Move common PCI functions into their own file dm: pci: Add a uclass for PCI dm: sandbox: pci: Add PCI support for sandbox dm: sandbox: Add a simple PCI driver dm: sandbox: pci: Add a PCI emulation uclass dm: sandbox: Add a emulated PCI device as an example dm: sandbox: pci: Enable PCI for sandbox dm: x86: pci: Add a PCI driver for driver model dm: x86: pci: Convert coreboot to use driver model for pci dm: x86: pci: Convert chromebook_link to use driver model for pci dm: pci: Add driver model tests for PCI arch/sandbox/Kconfig | 7 + arch/sandbox/cpu/cpu.c| 37 +- arch/sandbox/dts/sandbox.dts | 26 +- arch/sandbox/include/asm/io.h | 16 +- arch/sandbox/include/asm/processor.h | 12 + arch/sandbox/include/asm/test.h |
[U-Boot] [PATCH 15/22] dm: sandbox: Add a simple PCI driver
Add a driver which can access emulations of devices and make them available
in sandbox.
Signed-off-by: Simon Glass s...@chromium.org
---
drivers/pci/Kconfig | 10 ++
drivers/pci/Makefile | 1 +
drivers/pci/pci_sandbox.c | 79 +++
3 files changed, 90 insertions(+)
create mode 100644 drivers/pci/pci_sandbox.c
diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
index 8b7e2ee..167d405 100644
--- a/drivers/pci/Kconfig
+++ b/drivers/pci/Kconfig
@@ -9,4 +9,14 @@ config DM_PCI
available PCI devices, allows scanning of PCI buses and provides
device configuration support.
+config PCI_SANDBOX
+ bool Sandbox PCI support
+ depends on SANDBOX DM_PCI
+ help
+ Support PCI on sandbox, as an emulated bus. This permits testing of
+ PCI feature such as bus scanning, device configuration and device
+ access. The available (emulated) devices are defined statically in
+ the device tree but the normal PCI scan technique is used to find
+ then.
+
endmenu
diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
index db82786..9e2e5f9 100644
--- a/drivers/pci/Makefile
+++ b/drivers/pci/Makefile
@@ -7,6 +7,7 @@
ifneq ($(CONFIG_DM_PCI),)
obj-$(CONFIG_PCI) += pci-uclass.o pci_compat.o
+obj-$(CONFIG_PCI_SANDBOX) += pci_sandbox.o
else
obj-$(CONFIG_PCI) += pci.o
endif
diff --git a/drivers/pci/pci_sandbox.c b/drivers/pci/pci_sandbox.c
new file mode 100644
index 000..6de5130
--- /dev/null
+++ b/drivers/pci/pci_sandbox.c
@@ -0,0 +1,79 @@
+/*
+ * Copyright (c) 2014 Google, Inc
+ * Written by Simon Glass s...@chromium.org
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include dm.h
+#include fdtdec.h
+#include inttypes.h
+#include pci.h
+#include dm/root.h
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static int sandbox_pci_write_config(struct udevice *bus, pci_dev_t devfn,
+ uint offset, ulong value,
+ enum pci_size_t size)
+{
+ struct dm_pci_emul_ops *ops;
+ struct udevice *emul;
+ int ret;
+
+ ret = sandbox_pci_get_emul(bus, devfn, emul);
+ if (ret)
+ return ret == -ENODEV ? 0 : ret;
+ ops = pci_get_emul_ops(emul);
+ if (!ops || !ops-write_config)
+ return -ENOSYS;
+
+ return ops-write_config(emul, offset, value, size);
+}
+
+static int sandbox_pci_read_config(struct udevice *bus, pci_dev_t devfn,
+ uint offset, ulong *valuep,
+ enum pci_size_t size)
+{
+ struct dm_pci_emul_ops *ops;
+ struct udevice *emul;
+ int ret;
+
+ /* Prepare the default response */
+ *valuep = pci_get_ff(size);
+ ret = sandbox_pci_get_emul(bus, devfn, emul);
+ if (ret)
+ return ret == -ENODEV ? 0 : ret;
+ ops = pci_get_emul_ops(emul);
+ if (!ops || !ops-read_config)
+ return -ENOSYS;
+
+ return ops-read_config(emul, offset, valuep, size);
+}
+
+static int sandbox_pci_child_post_bind(struct udevice *dev)
+{
+ /* Attach an emulator if we can */
+ return dm_scan_fdt_node(dev, gd-fdt_blob, dev-of_offset, false);
+}
+
+static const struct dm_pci_ops sandbox_pci_ops = {
+ .read_config = sandbox_pci_read_config,
+ .write_config = sandbox_pci_write_config,
+};
+
+static const struct udevice_id sandbox_pci_ids[] = {
+ { .compatible = sandbox,pci },
+ { }
+};
+
+U_BOOT_DRIVER(pci_sandbox) = {
+ .name = pci_sandbox,
+ .id = UCLASS_PCI,
+ .of_match = sandbox_pci_ids,
+ .ops= sandbox_pci_ops,
+ .child_post_bind = sandbox_pci_child_post_bind,
+ .per_child_platdata_auto_alloc_size =
+ sizeof(struct pci_child_platdata),
+};
--
2.2.0.rc0.207.ga3a616c
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 04/22] x86: Add a x86_ prefix to the x86-specific PCI functions
These functions currently use a generic name, but they are for x86 only.
This may introduce confusion and prevents U-Boot from using these names
more widely.
In fact it should be possible to remove these at some point and use
generic functions, but for now, rename them.
Signed-off-by: Simon Glass s...@chromium.org
---
arch/x86/cpu/baytrail/early_uart.c | 5 ++-
arch/x86/cpu/ivybridge/bd82x6x.c | 32 +++---
arch/x86/cpu/ivybridge/cpu.c | 38
arch/x86/cpu/ivybridge/early_init.c | 58 +
arch/x86/cpu/ivybridge/early_me.c| 12 +++---
arch/x86/cpu/ivybridge/gma.c | 4 +-
arch/x86/cpu/ivybridge/lpc.c | 74
arch/x86/cpu/ivybridge/northbridge.c | 6 +--
arch/x86/cpu/ivybridge/pch.c | 4 +-
arch/x86/cpu/ivybridge/pci.c | 4 +-
arch/x86/cpu/ivybridge/report_platform.c | 4 +-
arch/x86/cpu/ivybridge/sata.c| 61 +-
arch/x86/cpu/ivybridge/sdram.c | 20 -
arch/x86/cpu/ivybridge/usb_ehci.c| 4 +-
arch/x86/cpu/ivybridge/usb_xhci.c| 8 ++--
arch/x86/cpu/pci.c | 12 +++---
arch/x86/cpu/quark/quark.c | 4 +-
arch/x86/cpu/queensbay/tnc.c | 4 +-
arch/x86/include/asm/pci.h | 12 +++---
arch/x86/lib/bios_interrupts.c | 12 +++---
drivers/gpio/intel_ich6_gpio.c | 16 +++
21 files changed, 199 insertions(+), 195 deletions(-)
diff --git a/arch/x86/cpu/baytrail/early_uart.c
b/arch/x86/cpu/baytrail/early_uart.c
index 4199210..b64a3a9 100644
--- a/arch/x86/cpu/baytrail/early_uart.c
+++ b/arch/x86/cpu/baytrail/early_uart.c
@@ -50,7 +50,7 @@ static void score_select_func(int pad, int func)
writel(reg, pconf0_addr);
}
-static void pci_write_config32(int dev, unsigned int where, u32 value)
+static void x86_pci_write_config32(int dev, unsigned int where, u32 value)
{
unsigned long addr;
@@ -62,7 +62,8 @@ static void pci_write_config32(int dev, unsigned int where,
u32 value)
int setup_early_uart(void)
{
/* Enable the legacy UART hardware. */
- pci_write_config32(PCI_DEV_CONFIG(0, LPC_DEV, LPC_FUNC), UART_CONT, 1);
+ x86_pci_write_config32(PCI_DEV_CONFIG(0, LPC_DEV, LPC_FUNC), UART_CONT,
+ 1);
/*
* Set up the pads to the UART function. This allows the signals to
diff --git a/arch/x86/cpu/ivybridge/bd82x6x.c b/arch/x86/cpu/ivybridge/bd82x6x.c
index 65a17d3..56b19e3 100644
--- a/arch/x86/cpu/ivybridge/bd82x6x.c
+++ b/arch/x86/cpu/ivybridge/bd82x6x.c
@@ -22,36 +22,36 @@ void bd82x6x_pci_init(pci_dev_t dev)
debug(bd82x6x PCI init.\n);
/* Enable Bus Master */
- reg16 = pci_read_config16(dev, PCI_COMMAND);
+ reg16 = x86_pci_read_config16(dev, PCI_COMMAND);
reg16 |= PCI_COMMAND_MASTER;
- pci_write_config16(dev, PCI_COMMAND, reg16);
+ x86_pci_write_config16(dev, PCI_COMMAND, reg16);
/* This device has no interrupt */
- pci_write_config8(dev, INTR, 0xff);
+ x86_pci_write_config8(dev, INTR, 0xff);
/* disable parity error response and SERR */
- reg16 = pci_read_config16(dev, BCTRL);
+ reg16 = x86_pci_read_config16(dev, BCTRL);
reg16 = ~(1 0);
reg16 = ~(1 1);
- pci_write_config16(dev, BCTRL, reg16);
+ x86_pci_write_config16(dev, BCTRL, reg16);
/* Master Latency Count must be set to 0x04! */
- reg8 = pci_read_config8(dev, SMLT);
+ reg8 = x86_pci_read_config8(dev, SMLT);
reg8 = 0x07;
reg8 |= (0x04 3);
- pci_write_config8(dev, SMLT, reg8);
+ x86_pci_write_config8(dev, SMLT, reg8);
/* Will this improve throughput of bus masters? */
- pci_write_config8(dev, PCI_MIN_GNT, 0x06);
+ x86_pci_write_config8(dev, PCI_MIN_GNT, 0x06);
/* Clear errors in status registers */
- reg16 = pci_read_config16(dev, PSTS);
+ reg16 = x86_pci_read_config16(dev, PSTS);
/* reg16 |= 0xf900; */
- pci_write_config16(dev, PSTS, reg16);
+ x86_pci_write_config16(dev, PSTS, reg16);
- reg16 = pci_read_config16(dev, SECSTS);
+ reg16 = x86_pci_read_config16(dev, SECSTS);
/* reg16 |= 0xf900; */
- pci_write_config16(dev, SECSTS, reg16);
+ x86_pci_write_config16(dev, SECSTS, reg16);
}
#define PCI_BRIDGE_UPDATE_COMMAND
@@ -59,7 +59,7 @@ void bd82x6x_pci_dev_enable_resources(pci_dev_t dev)
{
uint16_t command;
- command = pci_read_config16(dev, PCI_COMMAND);
+ command = x86_pci_read_config16(dev, PCI_COMMAND);
command |= PCI_COMMAND_IO;
#ifdef PCI_BRIDGE_UPDATE_COMMAND
/*
@@ -67,7 +67,7 @@ void bd82x6x_pci_dev_enable_resources(pci_dev_t dev)
* ROM and APICs to become invisible.
*/
debug(%x cmd - %02x\n, dev, command);
-
[U-Boot] [PATCH 08/22] dm: core: Add dev_get_uclass_priv() to access uclass private data
Add a convenience function to access the private data that a uclass stores
for each of its devices. Convert over most existing uses for consistency
and to provide an example for others.
Signed-off-by: Simon Glass s...@chromium.org
---
common/cmd_sf.c| 2 +-
common/cros_ec.c | 2 +-
drivers/core/device.c | 10 ++
drivers/gpio/at91_gpio.c | 2 +-
drivers/gpio/bcm2835_gpio.c| 2 +-
drivers/gpio/gpio-uclass.c | 22 +++---
drivers/gpio/intel_ich6_gpio.c | 2 +-
drivers/gpio/mxc_gpio.c| 2 +-
drivers/gpio/omap_gpio.c | 2 +-
drivers/gpio/s5p_gpio.c| 2 +-
drivers/gpio/sandbox.c | 6 +++---
drivers/gpio/sunxi_gpio.c | 2 +-
drivers/gpio/tegra_gpio.c | 2 +-
drivers/i2c/i2c-uclass.c | 6 +++---
drivers/i2c/sandbox_i2c.c | 2 +-
drivers/misc/cros_ec.c | 6 +++---
drivers/misc/cros_ec_i2c.c | 2 +-
drivers/misc/cros_ec_sandbox.c | 2 +-
drivers/misc/cros_ec_spi.c | 4 ++--
drivers/mtd/spi/sf-uclass.c| 2 +-
drivers/mtd/spi/sf_probe.c | 8
drivers/serial/serial-uclass.c | 4 ++--
drivers/spi/spi-uclass.c | 4 ++--
include/dm/device.h| 10 ++
include/i2c.h | 8
test/dm/core.c | 2 +-
test/dm/test-uclass.c | 4 ++--
27 files changed, 71 insertions(+), 51 deletions(-)
diff --git a/common/cmd_sf.c b/common/cmd_sf.c
index 5c788e9..20f14d3 100644
--- a/common/cmd_sf.c
+++ b/common/cmd_sf.c
@@ -130,7 +130,7 @@ static int do_spi_flash_probe(int argc, char * const argv[])
return 1;
}
- flash = new-uclass_priv;
+ flash = dev_get_uclass_priv(new);
#else
new = spi_flash_probe(bus, cs, speed, mode);
if (!new) {
diff --git a/common/cros_ec.c b/common/cros_ec.c
index bb299bc..64b4679 100644
--- a/common/cros_ec.c
+++ b/common/cros_ec.c
@@ -35,7 +35,7 @@ struct cros_ec_dev *board_get_cros_ec_dev(void)
debug(%s: Error %d\n, __func__, ret);
return NULL;
}
- return dev-uclass_priv;
+ return dev_get_uclass_priv(dev);
#else
return local.cros_ec_dev;
#endif
diff --git a/drivers/core/device.c b/drivers/core/device.c
index 73c3e07..92e8a57 100644
--- a/drivers/core/device.c
+++ b/drivers/core/device.c
@@ -305,6 +305,16 @@ void *dev_get_priv(struct udevice *dev)
return dev-priv;
}
+void *dev_get_uclass_priv(struct udevice *dev)
+{
+ if (!dev) {
+ dm_warn(%s: null device\n, __func__);
+ return NULL;
+ }
+
+ return dev-uclass_priv;
+}
+
void *dev_get_parentdata(struct udevice *dev)
{
if (!dev) {
diff --git a/drivers/gpio/at91_gpio.c b/drivers/gpio/at91_gpio.c
index 22fbd63..75a32ee 100644
--- a/drivers/gpio/at91_gpio.c
+++ b/drivers/gpio/at91_gpio.c
@@ -511,7 +511,7 @@ static int at91_gpio_probe(struct udevice *dev)
{
struct at91_port_priv *port = dev_get_priv(dev);
struct at91_port_platdata *plat = dev_get_platdata(dev);
- struct gpio_dev_priv *uc_priv = dev-uclass_priv;
+ struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
uc_priv-bank_name = plat-bank_name;
uc_priv-gpio_count = GPIO_PER_BANK;
diff --git a/drivers/gpio/bcm2835_gpio.c b/drivers/gpio/bcm2835_gpio.c
index 0244c01..fbc641d 100644
--- a/drivers/gpio/bcm2835_gpio.c
+++ b/drivers/gpio/bcm2835_gpio.c
@@ -105,7 +105,7 @@ static int bcm2835_gpio_probe(struct udevice *dev)
{
struct bcm2835_gpios *gpios = dev_get_priv(dev);
struct bcm2835_gpio_platdata *plat = dev_get_platdata(dev);
- struct gpio_dev_priv *uc_priv = dev-uclass_priv;
+ struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
uc_priv-bank_name = GPIO;
uc_priv-gpio_count = BCM2835_GPIO_COUNT;
diff --git a/drivers/gpio/gpio-uclass.c b/drivers/gpio/gpio-uclass.c
index a69bbd2..b6e1058 100644
--- a/drivers/gpio/gpio-uclass.c
+++ b/drivers/gpio/gpio-uclass.c
@@ -34,7 +34,7 @@ static int gpio_to_device(unsigned int gpio, struct gpio_desc
*desc)
for (ret = uclass_first_device(UCLASS_GPIO, dev);
dev;
ret = uclass_next_device(dev)) {
- uc_priv = dev-uclass_priv;
+ uc_priv = dev_get_uclass_priv(dev);
if (gpio = uc_priv-gpio_base
gpio uc_priv-gpio_base + uc_priv-gpio_count) {
desc-dev = dev;
@@ -65,7 +65,7 @@ int gpio_lookup_name(const char *name, struct udevice **devp,
ret = uclass_next_device(dev)) {
int len;
- uc_priv = dev-uclass_priv;
+ uc_priv = dev_get_uclass_priv(dev);
if (numeric != -1) {
offset = numeric - uc_priv-gpio_base;
/* Allow GPIOs to be numbered from 0 */
@@ -116,7 +116,7 @@ static int dm_gpio_request(struct gpio_desc *desc,
[U-Boot] [PATCH 18/22] dm: sandbox: pci: Enable PCI for sandbox
Enable PCI options so that sandbox can be used for testing this bus with driver model. Signed-off-by: Simon Glass s...@chromium.org --- configs/sandbox_defconfig | 3 +++ include/configs/sandbox.h | 4 2 files changed, 7 insertions(+) diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig index 0bf5ea3..5c2fe7f 100644 --- a/configs/sandbox_defconfig +++ b/configs/sandbox_defconfig @@ -7,3 +7,6 @@ CONFIG_DM=y CONFIG_DEFAULT_DEVICE_TREE=sandbox CONFIG_SYS_MALLOC_F=y CONFIG_SYS_MALLOC_F_LEN=0x400 +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_PCI_SANDBOX=y diff --git a/include/configs/sandbox.h b/include/configs/sandbox.h index 5c11650..6a4b701 100644 --- a/include/configs/sandbox.h +++ b/include/configs/sandbox.h @@ -34,6 +34,10 @@ #define CONFIG_CMD_FDT #define CONFIG_ANDROID_BOOT_IMAGE +#define CONFIG_CMD_PCI +#define CONFIG_PCI_PNP +#define CONFIG_CMD_IO + #define CONFIG_FS_FAT #define CONFIG_FAT_WRITE #define CONFIG_FS_EXT4 -- 2.2.0.rc0.207.ga3a616c ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 09/22] dm: core: Mark device as active before calling its probe() method
At present the device is not active when the probe() method is called. But
some probe() methods want to set up the device and this can involve
accessing it through normal methods. For example a PCI bus may wish to
set up its PCI parameters using calls to pci_hose_write_config_dword() and
similar.
At present this does not work because every such call within the probe()
method sees that the device is not active and attempts to probe it.
Already we mark the device as probed before calling the uclass post_probe()
method. This is a subtle change but I believe the new approach is better.
Since the scope of the change is only the probe() method and all its callees
it should still be within the control of the board author.
Signed-off-by: Simon Glass s...@chromium.org
---
drivers/core/device.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/core/device.c b/drivers/core/device.c
index 92e8a57..6bd4b26 100644
--- a/drivers/core/device.c
+++ b/drivers/core/device.c
@@ -243,14 +243,15 @@ int device_probe_child(struct udevice *dev, void
*parent_priv)
goto fail;
}
+ dev-flags |= DM_FLAG_ACTIVATED;
if (drv-probe) {
ret = drv-probe(dev);
- if (ret)
+ if (ret) {
+ dev-flags = ~DM_FLAG_ACTIVATED;
goto fail;
+ }
}
- dev-flags |= DM_FLAG_ACTIVATED;
-
ret = uclass_post_probe_device(dev);
if (ret) {
dev-flags = ~DM_FLAG_ACTIVATED;
--
2.2.0.rc0.207.ga3a616c
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 21/22] dm: x86: pci: Convert chromebook_link to use driver model for pci
Move chromebook_link over to driver model for PCI.
This involves:
- adding a uclass for platform controller hub
- removing most of the existing PCI driver
- adjusting how CPU init works to use driver model instead
- rename the lpc compatible string (it will be removed later)
This does not really take advantage of driver model fully, but it does work.
Furture work will improve the code structure to remove many of the explicit
calls to init the board.
Signed-off-by: Simon Glass s...@chromium.org
---
arch/x86/cpu/ivybridge/bd82x6x.c | 24 +++-
arch/x86/cpu/ivybridge/cpu.c | 16 +++---
arch/x86/cpu/ivybridge/lpc.c | 1 +
arch/x86/cpu/ivybridge/pci.c | 81 ---
arch/x86/dts/chromebook_link.dts | 3 +-
arch/x86/include/asm/arch-ivybridge/bd82x6x.h | 1 -
configs/chromebook_link_defconfig | 1 +
configs/chromebox_panther_defconfig | 1 +
lib/fdtdec.c | 2 +-
9 files changed, 62 insertions(+), 68 deletions(-)
diff --git a/arch/x86/cpu/ivybridge/bd82x6x.c b/arch/x86/cpu/ivybridge/bd82x6x.c
index 56b19e3..7b74282 100644
--- a/arch/x86/cpu/ivybridge/bd82x6x.c
+++ b/arch/x86/cpu/ivybridge/bd82x6x.c
@@ -5,6 +5,7 @@
*/
#include common.h
+#include dm.h
#include errno.h
#include fdtdec.h
#include malloc.h
@@ -86,7 +87,7 @@ void bd82x6x_pci_bus_enable_resources(pci_dev_t dev)
bd82x6x_pci_dev_enable_resources(dev);
}
-int bd82x6x_init_pci_devices(void)
+static int bd82x6x_probe(struct udevice *dev)
{
const void *blob = gd-fdt_blob;
struct pci_controller *hose;
@@ -144,3 +145,24 @@ int bd82x6x_init(void)
return 0;
}
+
+static const struct udevice_id bd82x6x_ids[] = {
+ { .compatible = intel,bd82x6x },
+ { }
+};
+
+U_BOOT_DRIVER(bd82x6x_drv) = {
+ .name = bd82x6x,
+ .id = UCLASS_PCH,
+ .of_match = bd82x6x_ids,
+ .probe = bd82x6x_probe,
+};
+
+/*
+ * TODO(s...@chromium.org): Move this to arch/x86/lib or similar when other
+ * boards also use a PCH
+ */
+UCLASS_DRIVER(pch) = {
+ .id = UCLASS_PCH,
+ .name = pch,
+};
diff --git a/arch/x86/cpu/ivybridge/cpu.c b/arch/x86/cpu/ivybridge/cpu.c
index 2796314..795787d 100644
--- a/arch/x86/cpu/ivybridge/cpu.c
+++ b/arch/x86/cpu/ivybridge/cpu.c
@@ -12,6 +12,7 @@
*/
#include common.h
+#include dm.h
#include errno.h
#include fdtdec.h
#include asm/cpu.h
@@ -126,19 +127,20 @@ int x86_post_cpu_init(void)
{
const void *blob = gd-fdt_blob;
struct pci_controller *hose;
+ struct udevice *bus;
int node;
int ret;
- post_code(POST_CPU_INIT);
- timer_set_base(rdtsc());
-
- ret = x86_cpu_init_f();
+ post_code(0x70);
+ ret = uclass_get_device(UCLASS_PCI, 0, bus);
+ post_code(0x71);
if (ret)
return ret;
+ post_code(0x72);
+ hose = dev_get_uclass_priv(bus);
- ret = pci_early_init_hose(hose);
- if (ret)
- return ret;
+ /* TODO(s...@chromium.org): Get rid of gd-hose */
+ gd-hose = hose;
node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_LPC);
if (node 0)
diff --git a/arch/x86/cpu/ivybridge/lpc.c b/arch/x86/cpu/ivybridge/lpc.c
index 33b11a1..c20e180 100644
--- a/arch/x86/cpu/ivybridge/lpc.c
+++ b/arch/x86/cpu/ivybridge/lpc.c
@@ -7,6 +7,7 @@
*/
#include common.h
+#include dm.h
#include errno.h
#include fdtdec.h
#include rtc.h
diff --git a/arch/x86/cpu/ivybridge/pci.c b/arch/x86/cpu/ivybridge/pci.c
index 7f62a86..5e90f30 100644
--- a/arch/x86/cpu/ivybridge/pci.c
+++ b/arch/x86/cpu/ivybridge/pci.c
@@ -10,63 +10,24 @@
*/
#include common.h
+#include dm.h
#include pci.h
#include asm/pci.h
+#include asm/post.h
#include asm/arch/bd82x6x.h
#include asm/arch/pch.h
-static void config_pci_bridge(struct pci_controller *hose, pci_dev_t dev,
- struct pci_config_table *table)
-{
- u8 secondary;
-
- hose-read_byte(hose, dev, PCI_SECONDARY_BUS, secondary);
- if (secondary != 0)
- pci_hose_scan_bus(hose, secondary);
-}
-
-static struct pci_config_table pci_ivybridge_config_table[] = {
- /* vendor, device, class, bus, dev, func */
- { PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_BRIDGE_PCI,
- PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, config_pci_bridge },
- {}
-};
-
-void board_pci_setup_hose(struct pci_controller *hose)
-{
- hose-config_table = pci_ivybridge_config_table;
- hose-first_busno = 0;
- hose-last_busno = 0;
-
- /* PCI memory space */
- pci_set_region(hose-regions + 0,
- CONFIG_PCI_MEM_BUS,
- CONFIG_PCI_MEM_PHYS,
- CONFIG_PCI_MEM_SIZE,
- PCI_REGION_MEM);
-
- /* PCI IO space */
-
[U-Boot] [PATCH 05/22] RFC: x86: Split up arch_cpu_init()
At present we do more in this function than we should. Create a new
x86_post_cpu_init() which can be called from the board file when needed
(e.g. in board_early_init_f(). This allows us to use driver model for
our x86_post_cpu_init() function.
It is likely that some future refactoring will improve this and reduce
the number of steps, using driver model's probing features.
Note: this needs more discussion - e.g. I believe it breaks other x86
boards. We may want to plumb this in differently (e.g. promote
x86_post_cpu_init() to the board_init_f() boot sequence).
Signed-off-by: Simon Glass s...@chromium.org
---
arch/x86/cpu/ivybridge/cpu.c| 8
arch/x86/include/asm/u-boot-x86.h | 1 +
board/google/chromebook_link/link.c | 6 ++
3 files changed, 15 insertions(+)
diff --git a/arch/x86/cpu/ivybridge/cpu.c b/arch/x86/cpu/ivybridge/cpu.c
index 5fd3753..2796314 100644
--- a/arch/x86/cpu/ivybridge/cpu.c
+++ b/arch/x86/cpu/ivybridge/cpu.c
@@ -116,6 +116,14 @@ static void set_spi_speed(void)
int arch_cpu_init(void)
{
+ post_code(POST_CPU_INIT);
+ timer_set_base(rdtsc());
+
+ return x86_cpu_init_f();
+}
+
+int x86_post_cpu_init(void)
+{
const void *blob = gd-fdt_blob;
struct pci_controller *hose;
int node;
diff --git a/arch/x86/include/asm/u-boot-x86.h
b/arch/x86/include/asm/u-boot-x86.h
index c743efd..d5a9535 100644
--- a/arch/x86/include/asm/u-boot-x86.h
+++ b/arch/x86/include/asm/u-boot-x86.h
@@ -38,6 +38,7 @@ void reset_cpu(ulong addr);
ulong board_get_usable_ram_top(ulong total_size);
void dram_init_banksize(void);
int default_print_cpuinfo(void);
+int x86_post_cpu_init(void);
/* Set up a UART which can be used with printch(), printhex8(), etc. */
int setup_early_uart(void);
diff --git a/board/google/chromebook_link/link.c
b/board/google/chromebook_link/link.c
index 9978e92..9ebbb9f 100644
--- a/board/google/chromebook_link/link.c
+++ b/board/google/chromebook_link/link.c
@@ -120,6 +120,12 @@ static const struct pch_gpio_map link_gpio_map = {
int board_early_init_f(void)
{
+ int ret;
+
+ ret = x86_post_cpu_init();
+ if (ret)
+ return ret;
+
ich_gpio_set_gpio_map(link_gpio_map);
return 0;
--
2.2.0.rc0.207.ga3a616c
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 19/22] dm: x86: pci: Add a PCI driver for driver model
Add a simple x86 PCI driver which uses standard functions provided by the
architecture.
Signed-off-by: Simon Glass s...@chromium.org
---
arch/x86/cpu/pci.c | 40
arch/x86/include/asm/pci.h | 8
arch/x86/lib/Makefile | 2 ++
drivers/pci/Makefile | 1 +
drivers/pci/pci_x86.c | 24
5 files changed, 75 insertions(+)
create mode 100644 drivers/pci/pci_x86.c
diff --git a/arch/x86/cpu/pci.c b/arch/x86/cpu/pci.c
index c6c5267..e23b233 100644
--- a/arch/x86/cpu/pci.c
+++ b/arch/x86/cpu/pci.c
@@ -10,9 +10,11 @@
*/
#include common.h
+#include dm.h
#include errno.h
#include malloc.h
#include pci.h
+#include asm/io.h
#include asm/pci.h
DECLARE_GLOBAL_DATA_PTR;
@@ -111,3 +113,41 @@ void x86_pci_write_config32(pci_dev_t dev, unsigned where,
unsigned value)
{
pci_hose_write_config_dword(get_hose(), dev, where, value);
}
+
+int pci_x86_read_config(struct udevice *bus, pci_dev_t bdf, uint offset,
+ ulong *valuep, enum pci_size_t size)
+{
+ outl(bdf | (offset 0xfc) | PCI_CFG_EN, PCI_REG_ADDR);
+ switch (size) {
+ case PCI_SIZE_8:
+ *valuep = inb(PCI_REG_DATA + (offset 3));
+ break;
+ case PCI_SIZE_16:
+ *valuep = inw(PCI_REG_DATA + (offset 2));
+ break;
+ case PCI_SIZE_32:
+ *valuep = inl(PCI_REG_DATA);
+ break;
+ }
+
+ return 0;
+}
+
+int pci_x86_write_config(struct udevice *bus, pci_dev_t bdf, uint offset,
+ulong value, enum pci_size_t size)
+{
+ outl(bdf | (offset 0xfc) | PCI_CFG_EN, PCI_REG_ADDR);
+ switch (size) {
+ case PCI_SIZE_8:
+ outb(value, PCI_REG_DATA + (offset 3));
+ break;
+ case PCI_SIZE_16:
+ outw(value, PCI_REG_DATA + (offset 2));
+ break;
+ case PCI_SIZE_32:
+ outl(value, PCI_REG_DATA);
+ break;
+ }
+
+ return 0;
+}
diff --git a/arch/x86/include/asm/pci.h b/arch/x86/include/asm/pci.h
index b277b3d..a1969ed 100644
--- a/arch/x86/include/asm/pci.h
+++ b/arch/x86/include/asm/pci.h
@@ -8,6 +8,8 @@
#ifndef _PCI_I386_H_
#define _PCI_I386_H_
+#include pci.h
+
/* bus mapping constants (used for PCI core initialization) */
#define PCI_REG_ADDR 0xcf8
#define PCI_REG_DATA 0xcfc
@@ -56,6 +58,12 @@ void x86_pci_write_config8(pci_dev_t dev, unsigned where,
unsigned value);
void x86_pci_write_config16(pci_dev_t dev, unsigned where, unsigned value);
void x86_pci_write_config32(pci_dev_t dev, unsigned where, unsigned value);
+int pci_x86_read_config(struct udevice *bus, pci_dev_t bdf, uint offset,
+ ulong *valuep, enum pci_size_t size);
+
+int pci_x86_write_config(struct udevice *bus, pci_dev_t bdf, uint offset,
+ulong value, enum pci_size_t size);
+
#endif /* __ASSEMBLY__ */
#endif /* _PCI_I386_H_ */
diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile
index c17f7f0..67a34d8 100644
--- a/arch/x86/lib/Makefile
+++ b/arch/x86/lib/Makefile
@@ -17,7 +17,9 @@ obj-y += interrupts.o
obj-y += cmd_mtrr.o
obj-$(CONFIG_SYS_PCAT_INTERRUPTS) += pcat_interrupts.o
obj-$(CONFIG_SYS_PCAT_TIMER) += pcat_timer.o
+ifndef CONFIG_DM_PCI
obj-$(CONFIG_PCI) += pci_type1.o
+endif
obj-y += relocate.o
obj-y += physmem.o
obj-$(CONFIG_X86_RAMTEST) += ramtest.o
diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
index c1c2ae3..adc238f 100644
--- a/drivers/pci/Makefile
+++ b/drivers/pci/Makefile
@@ -9,6 +9,7 @@ ifneq ($(CONFIG_DM_PCI),)
obj-$(CONFIG_PCI) += pci-uclass.o pci_compat.o
obj-$(CONFIG_PCI_SANDBOX) += pci_sandbox.o
obj-$(CONFIG_SANDBOX) += pci-emul-uclass.o
+obj-$(CONFIG_X86) += pci_x86.o
else
obj-$(CONFIG_PCI) += pci.o
endif
diff --git a/drivers/pci/pci_x86.c b/drivers/pci/pci_x86.c
new file mode 100644
index 000..901bdca
--- /dev/null
+++ b/drivers/pci/pci_x86.c
@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2015 Google, Inc
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include dm.h
+#include pci.h
+
+static const struct dm_pci_ops x86_pci_ops = {
+};
+
+static const struct udevice_id x86_pci_ids[] = {
+ { .compatible = x86,pci },
+ { }
+};
+
+U_BOOT_DRIVER(pci_x86) = {
+ .name = pci_x86,
+ .id = UCLASS_PCI,
+ .of_match = x86_pci_ids,
+ .ops= x86_pci_ops,
+};
--
2.2.0.rc0.207.ga3a616c
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 17/22] dm: sandbox: Add a emulated PCI device as an example
This device sits on the sandbox PCI bus and provides a case-swapping
service for sandbox. It illustrates the use of both PCI I/O and PCI
memory accesses.
Signed-off-by: Simon Glass s...@chromium.org
---
drivers/misc/Makefile| 1 +
drivers/misc/swap_case.c | 285 +++
2 files changed, 286 insertions(+)
create mode 100644 drivers/misc/swap_case.c
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index a34972d..7783b72 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -26,5 +26,6 @@ obj-$(CONFIG_SANDBOX) += i2c_eeprom_emul.o
endif
obj-$(CONFIG_SMSC_LPC47M) += smsc_lpc47m.o
obj-$(CONFIG_STATUS_LED) += status_led.o
+obj-$(CONFIG_SANDBOX) += swap_case.o
obj-$(CONFIG_TWL4030_LED) += twl4030_led.o
obj-$(CONFIG_FSL_IFC) += fsl_ifc.o
diff --git a/drivers/misc/swap_case.c b/drivers/misc/swap_case.c
new file mode 100644
index 000..f6028ba
--- /dev/null
+++ b/drivers/misc/swap_case.c
@@ -0,0 +1,285 @@
+/*
+ * PCI emulation device which swaps the case of text
+ *
+ * Copyright (c) 2014 Google, Inc
+ * Written by Simon Glass s...@chromium.org
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include dm.h
+#include pci.h
+#include asm/test.h
+#include linux/ctype.h
+
+/**
+ * struct swap_case_platdata - platform data for this device
+ *
+ * @command: Current PCI command value
+ * @bar: Current base address values
+ */
+struct swap_case_platdata {
+ u16 command;
+ u32 bar[2];
+};
+
+#define offset_to_barnum(offset) \
+ (((offset) - PCI_BASE_ADDRESS_0) / sizeof(u32))
+
+enum {
+ MEM_TEXT_SIZE = 0x100,
+};
+
+enum swap_case_op {
+ OP_TO_LOWER,
+ OP_TO_UPPER,
+ OP_SWAP,
+};
+
+static struct pci_bar {
+ int type;
+ u32 size;
+} barinfo[] = {
+ { PCI_BASE_ADDRESS_SPACE_IO, 1 },
+ { PCI_BASE_ADDRESS_MEM_TYPE_32, MEM_TEXT_SIZE },
+ { 0, 0 },
+ { 0, 0 },
+ { 0, 0 },
+ { 0, 0 },
+};
+
+struct swap_case_priv {
+ enum swap_case_op op;
+ char mem_text[MEM_TEXT_SIZE];
+};
+
+static int sandbox_swap_case_get_devfn(struct udevice *dev)
+{
+ struct pci_child_platdata *plat = dev_get_parent_platdata(dev);
+
+ return plat-devfn;
+}
+
+static int sandbox_swap_case_read_config(struct udevice *emul, uint offset,
+ulong *valuep, enum pci_size_t size)
+{
+ struct swap_case_platdata *plat = dev_get_platdata(emul);
+
+ switch (offset) {
+ case PCI_COMMAND:
+ *valuep = plat-command;
+ break;
+ case PCI_HEADER_TYPE:
+ *valuep = 0;
+ break;
+ case PCI_VENDOR_ID:
+ *valuep = SANDBOX_PCI_VENDOR_ID;
+ break;
+ case PCI_DEVICE_ID:
+ *valuep = SANDBOX_PCI_DEVICE_ID;
+ break;
+ case PCI_CLASS_DEVICE:
+ if (size == PCI_SIZE_8) {
+ *valuep = SANDBOX_PCI_CLASS_SUB_CODE;
+ } else {
+ *valuep = (SANDBOX_PCI_CLASS_CODE 8) |
+ SANDBOX_PCI_CLASS_SUB_CODE;
+ }
+ break;
+ case PCI_CLASS_CODE:
+ *valuep = SANDBOX_PCI_CLASS_CODE;
+ break;
+ case PCI_BASE_ADDRESS_0:
+ case PCI_BASE_ADDRESS_1:
+ case PCI_BASE_ADDRESS_2:
+ case PCI_BASE_ADDRESS_3:
+ case PCI_BASE_ADDRESS_4:
+ case PCI_BASE_ADDRESS_5: {
+ int barnum;
+ u32 *bar, result;
+
+ barnum = offset_to_barnum(offset);
+ bar = plat-bar[barnum];
+
+ result = *bar;
+ if (*bar == 0x) {
+ if (barinfo[barnum].type) {
+ result = (~(barinfo[barnum].size - 1)
+ PCI_BASE_ADDRESS_IO_MASK) |
+ PCI_BASE_ADDRESS_SPACE_IO;
+ } else {
+ result = (~(barinfo[barnum].size - 1)
+ PCI_BASE_ADDRESS_MEM_MASK) |
+ PCI_BASE_ADDRESS_MEM_TYPE_32;
+ }
+ }
+ debug(r bar %d=%x\n, barnum, result);
+ *valuep = result;
+ break;
+ }
+ }
+
+ return 0;
+}
+
+static int sandbox_swap_case_write_config(struct udevice *emul, uint offset,
+ ulong value, enum pci_size_t size)
+{
+ struct swap_case_platdata *plat = dev_get_platdata(emul);
+
+ switch (offset) {
+ case PCI_COMMAND:
+ plat-command = value;
+ break;
+ case PCI_BASE_ADDRESS_0:
+ case PCI_BASE_ADDRESS_1: {
+ int barnum;
+ u32 *bar;
+
+ barnum = offset_to_barnum(offset);
+
[U-Boot] [PATCH 10/22] dm: core: Add a uclass pre_probe() method for devices
Some uclasses want to set up a device before it is probed. Add a method
for this.
An example is with PCI, where a PCI uclass wants to set up its private
data for later use. This allows the device's uclass() method to make calls
whcih use that data (for example, read PCI memory regions from device
tree, set up bus numbers).
Signed-off-by: Simon Glass s...@chromium.org
---
drivers/core/device.c| 2 +-
drivers/core/uclass.c| 10 +-
include/dm/test.h| 1 +
include/dm/uclass-internal.h | 7 ---
include/dm/uclass.h | 2 ++
test/dm/core.c | 7 ++-
test/dm/test-uclass.c| 12
7 files changed, 35 insertions(+), 6 deletions(-)
diff --git a/drivers/core/device.c b/drivers/core/device.c
index 6bd4b26..7483405 100644
--- a/drivers/core/device.c
+++ b/drivers/core/device.c
@@ -227,7 +227,7 @@ int device_probe_child(struct udevice *dev, void
*parent_priv)
}
dev-seq = seq;
- ret = uclass_pre_probe_child(dev);
+ ret = uclass_pre_probe_device(dev);
if (ret)
goto fail;
diff --git a/drivers/core/uclass.c b/drivers/core/uclass.c
index 289a5d2..98c15e5 100644
--- a/drivers/core/uclass.c
+++ b/drivers/core/uclass.c
@@ -391,9 +391,17 @@ int uclass_resolve_seq(struct udevice *dev)
return seq;
}
-int uclass_pre_probe_child(struct udevice *dev)
+int uclass_pre_probe_device(struct udevice *dev)
{
struct uclass_driver *uc_drv;
+ int ret;
+
+ uc_drv = dev-uclass-uc_drv;
+ if (uc_drv-pre_probe) {
+ ret = uc_drv-pre_probe(dev);
+ if (ret)
+ return ret;
+ }
if (!dev-parent)
return 0;
diff --git a/include/dm/test.h b/include/dm/test.h
index 707c69e..b310e5f 100644
--- a/include/dm/test.h
+++ b/include/dm/test.h
@@ -44,6 +44,7 @@ enum {
/* For uclass */
DM_TEST_OP_POST_BIND,
DM_TEST_OP_PRE_UNBIND,
+ DM_TEST_OP_PRE_PROBE,
DM_TEST_OP_POST_PROBE,
DM_TEST_OP_PRE_REMOVE,
DM_TEST_OP_INIT,
diff --git a/include/dm/uclass-internal.h b/include/dm/uclass-internal.h
index f2f254a..ae2a93d 100644
--- a/include/dm/uclass-internal.h
+++ b/include/dm/uclass-internal.h
@@ -44,15 +44,16 @@ int uclass_bind_device(struct udevice *dev);
int uclass_unbind_device(struct udevice *dev);
/**
- * uclass_pre_probe_child() - Deal with a child that is about to be probed
+ * uclass_pre_probe_device() - Deal with a device that is about to be probed
*
* Perform any pre-processing that is needed by the uclass before it can be
- * probed.
+ * probed. This includes the uclass' pre-probe() method and the parent
+ * uclass' child_pre_probe() method.
*
* @dev: Pointer to the device
* #return 0 on success, -ve on error
*/
-int uclass_pre_probe_child(struct udevice *dev);
+int uclass_pre_probe_device(struct udevice *dev);
/**
* uclass_post_probe_device() - Deal with a device that has just been probed
diff --git a/include/dm/uclass.h b/include/dm/uclass.h
index d6c40c6..d57d804 100644
--- a/include/dm/uclass.h
+++ b/include/dm/uclass.h
@@ -53,6 +53,7 @@ struct udevice;
* @id: ID number of this uclass
* @post_bind: Called after a new device is bound to this uclass
* @pre_unbind: Called before a device is unbound from this uclass
+ * @pre_probe: Called before a new device is probed
* @post_probe: Called after a new device is probed
* @pre_remove: Called before a device is removed
* @child_post_bind: Called after a child is bound to a device in this uclass
@@ -80,6 +81,7 @@ struct uclass_driver {
enum uclass_id id;
int (*post_bind)(struct udevice *dev);
int (*pre_unbind)(struct udevice *dev);
+ int (*pre_probe)(struct udevice *dev);
int (*post_probe)(struct udevice *dev);
int (*pre_remove)(struct udevice *dev);
int (*child_post_bind)(struct udevice *dev);
diff --git a/test/dm/core.c b/test/dm/core.c
index 7be28e4..990d390 100644
--- a/test/dm/core.c
+++ b/test/dm/core.c
@@ -141,6 +141,7 @@ static int dm_test_autoprobe(struct dm_test_state *dms)
ut_assert(uc);
ut_asserteq(1, dm_testdrv_op_count[DM_TEST_OP_INIT]);
+ ut_asserteq(0, dm_testdrv_op_count[DM_TEST_OP_PRE_PROBE]);
ut_asserteq(0, dm_testdrv_op_count[DM_TEST_OP_POST_PROBE]);
/* The root device should not be activated until needed */
@@ -167,8 +168,12 @@ static int dm_test_autoprobe(struct dm_test_state *dms)
ut_assert(dms-root-flags DM_FLAG_ACTIVATED);
}
- /* Our 3 dm_test_infox children should be passed to post_probe */
+ /*
+* Our 3 dm_test_info children should be passed to pre_probe and
+* post_probe
+*/
ut_asserteq(3, dm_testdrv_op_count[DM_TEST_OP_POST_PROBE]);
+ ut_asserteq(3, dm_testdrv_op_count[DM_TEST_OP_PRE_PROBE]);
/* Also we can check the per-device data */
[U-Boot] [PATCH V2 1/2] ARM: tegra: add function to clear pinmux CLAMPING bit
From: Stephen Warren swar...@nvidia.com
This is needed to correctly apply the new Jetson TK1 pinmux config.
Signed-off-by: Stephen Warren swar...@nvidia.com
---
v2:
* Use clrbits_le32() rather than open-code read/modify/write statements.
* Update pinmux_set_tristate_input_clamping to match.
---
arch/arm/cpu/tegra-common/pinmux-common.c | 12
arch/arm/include/asm/arch-tegra/pinmux.h | 3 ++-
2 files changed, 10 insertions(+), 5 deletions(-)
diff --git a/arch/arm/cpu/tegra-common/pinmux-common.c
b/arch/arm/cpu/tegra-common/pinmux-common.c
index 6e3ab0c14ca2..64baed45d591 100644
--- a/arch/arm/cpu/tegra-common/pinmux-common.c
+++ b/arch/arm/cpu/tegra-common/pinmux-common.c
@@ -94,11 +94,15 @@
void pinmux_set_tristate_input_clamping(void)
{
u32 *reg = _R(APB_MISC_PP_PINMUX_GLOBAL_0);
- u32 val;
- val = readl(reg);
- val |= CLAMP_INPUTS_WHEN_TRISTATED;
- writel(val, reg);
+ setbits_le32(reg, CLAMP_INPUTS_WHEN_TRISTATED);
+}
+
+void pinmux_clear_tristate_input_clamping(void)
+{
+ u32 *reg = _R(APB_MISC_PP_PINMUX_GLOBAL_0);
+
+ clrbits_le32(reg, CLAMP_INPUTS_WHEN_TRISTATED);
}
#endif
diff --git a/arch/arm/include/asm/arch-tegra/pinmux.h
b/arch/arm/include/asm/arch-tegra/pinmux.h
index da477697bf02..ab764960fa7f 100644
--- a/arch/arm/include/asm/arch-tegra/pinmux.h
+++ b/arch/arm/include/asm/arch-tegra/pinmux.h
@@ -81,8 +81,9 @@ struct pmux_pingrp_config {
};
#if !defined(CONFIG_TEGRA20) !defined(CONFIG_TEGRA30)
-/* Set the pinmux CLAMP_INPUTS_WHEN_TRISTATED bit */
+/* Set/clear the pinmux CLAMP_INPUTS_WHEN_TRISTATED bit */
void pinmux_set_tristate_input_clamping(void);
+void pinmux_clear_tristate_input_clamping(void);
#endif
/* Set the mux function for a pin group */
--
1.9.1
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH V2 2/2] ARM: tegra: import latest Jetson TK1 pinmux
From: Stephen Warren swar...@nvidia.com
Syseng has revamped the Jetson TK1 pinmux spreadsheet, basing the content
completely on correct configuration for the board/schematic, rather than
the previous version which was based on the bare minimum changes relative
to another reference board.
The new spreadsheet sets TRISTATE for any input-only pins. This only works
correctly if the global CLAMP bit is not set, so the Jetson TK1 board code
has been adjusted accordingly. Apparently syseng have changed their mind
since the previous advice that this needed to be set:-/
This content comes from Jetson_TK1_customer_pinmux.xlsm (v09) downloaded
from https://developer.nvidia.com/hardware-design-and-development.
Signed-off-by: Stephen Warren swar...@nvidia.com
---
board/nvidia/jetson-tk1/jetson-tk1.c | 2 +-
board/nvidia/jetson-tk1/pinmux-config-jetson-tk1.h | 303 +
2 files changed, 136 insertions(+), 169 deletions(-)
diff --git a/board/nvidia/jetson-tk1/jetson-tk1.c
b/board/nvidia/jetson-tk1/jetson-tk1.c
index daa74a4be02f..52425a8f6dea 100644
--- a/board/nvidia/jetson-tk1/jetson-tk1.c
+++ b/board/nvidia/jetson-tk1/jetson-tk1.c
@@ -22,7 +22,7 @@ DECLARE_GLOBAL_DATA_PTR;
*/
void pinmux_init(void)
{
- pinmux_set_tristate_input_clamping();
+ pinmux_clear_tristate_input_clamping();
gpio_config_table(jetson_tk1_gpio_inits,
ARRAY_SIZE(jetson_tk1_gpio_inits));
diff --git a/board/nvidia/jetson-tk1/pinmux-config-jetson-tk1.h
b/board/nvidia/jetson-tk1/pinmux-config-jetson-tk1.h
index de4eb355982c..863721b2a330 100644
--- a/board/nvidia/jetson-tk1/pinmux-config-jetson-tk1.h
+++ b/board/nvidia/jetson-tk1/pinmux-config-jetson-tk1.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
*
* SPDX-License-Identifier: GPL-2.0+
*/
@@ -15,77 +15,47 @@
static const struct tegra_gpio_config jetson_tk1_gpio_inits[] = {
/*gpio, init_val */
- GPIO_INIT(C7, IN),
- GPIO_INIT(G0, OUT0),
- GPIO_INIT(G1, OUT0),
+ GPIO_INIT(G0, IN),
+ GPIO_INIT(G1, IN),
GPIO_INIT(G2, IN),
GPIO_INIT(G3, IN),
+ GPIO_INIT(G4, IN),
GPIO_INIT(H2, OUT0),
- GPIO_INIT(H3, OUT0),
GPIO_INIT(H4, IN),
- GPIO_INIT(H5, OUT0),
- GPIO_INIT(H6, IN),
- GPIO_INIT(H7, OUT0),
+ GPIO_INIT(H7, IN),
GPIO_INIT(I0, OUT0),
- GPIO_INIT(I2, OUT0),
- GPIO_INIT(I4, OUT0),
- GPIO_INIT(I5, IN),
+ GPIO_INIT(I1, IN),
GPIO_INIT(I6, IN),
GPIO_INIT(J0, IN),
- GPIO_INIT(J2, IN),
GPIO_INIT(K1, OUT0),
GPIO_INIT(K2, IN),
- GPIO_INIT(K3, IN),
GPIO_INIT(K4, OUT0),
- GPIO_INIT(K5, OUT0),
GPIO_INIT(K6, OUT0),
GPIO_INIT(N7, IN),
- GPIO_INIT(O0, IN),
GPIO_INIT(O1, IN),
- GPIO_INIT(O2, IN),
- GPIO_INIT(O3, IN),
GPIO_INIT(O4, IN),
- GPIO_INIT(O5, IN),
- GPIO_INIT(O6, OUT0),
- GPIO_INIT(O7, IN),
- GPIO_INIT(P0, OUT0),
- GPIO_INIT(P1, OUT0),
GPIO_INIT(P2, OUT0),
GPIO_INIT(Q0, IN),
- GPIO_INIT(Q1, IN),
- GPIO_INIT(Q2, IN),
+ GPIO_INIT(Q3, IN),
GPIO_INIT(Q5, IN),
- GPIO_INIT(Q6, IN),
- GPIO_INIT(Q7, IN),
GPIO_INIT(R0, OUT0),
- GPIO_INIT(R1, OUT0),
GPIO_INIT(R2, OUT0),
GPIO_INIT(R4, IN),
- GPIO_INIT(R5, OUT0),
GPIO_INIT(R7, IN),
- GPIO_INIT(S0, IN),
- GPIO_INIT(S3, OUT0),
- GPIO_INIT(S4, OUT0),
- GPIO_INIT(S5, IN),
- GPIO_INIT(S6, OUT0),
+ GPIO_INIT(S7, IN),
GPIO_INIT(T0, OUT0),
- GPIO_INIT(T1, OUT0),
- GPIO_INIT(U0, OUT0),
+ GPIO_INIT(T1, IN),
+ GPIO_INIT(U0, IN),
GPIO_INIT(U1, IN),
GPIO_INIT(U2, IN),
- GPIO_INIT(U3, OUT0),
- GPIO_INIT(U4, OUT0),
+ GPIO_INIT(U3, IN),
+ GPIO_INIT(U4, IN),
GPIO_INIT(U5, IN),
GPIO_INIT(U6, IN),
GPIO_INIT(V0, IN),
GPIO_INIT(V1, IN),
- GPIO_INIT(W2, IN),
- GPIO_INIT(W3, IN),
- GPIO_INIT(X1, OUT0),
- GPIO_INIT(X3, IN),
- GPIO_INIT(X4, OUT0),
- GPIO_INIT(X5, IN),
- GPIO_INIT(X6, IN),
+ GPIO_INIT(X1, IN),
+ GPIO_INIT(X4, IN),
GPIO_INIT(X7, OUT0),
GPIO_INIT(BB3, OUT0),
GPIO_INIT(BB5, OUT0),
@@ -93,10 +63,7 @@ static const struct tegra_gpio_config
jetson_tk1_gpio_inits[] = {
GPIO_INIT(BB7, OUT0),
GPIO_INIT(CC1, IN),
GPIO_INIT(CC2, IN),
- GPIO_INIT(CC5, OUT0),
- GPIO_INIT(EE1, OUT0),
- GPIO_INIT(FF1, OUT0),
- GPIO_INIT(FF2, IN),
+ GPIO_INIT(EE2, OUT1),
};
#define
[U-Boot] [PATCH 14/22] dm: sandbox: pci: Add PCI support for sandbox
Add the required header information, device tree nodes and I/O accessor
functions to support PCI on sandbox. All devices are emulated by drivers
which can be added as required for testing or development.
Signed-off-by: Simon Glass s...@chromium.org
---
arch/sandbox/Kconfig | 7 ++
arch/sandbox/cpu/cpu.c| 37 +++-
arch/sandbox/dts/sandbox.dts | 22 -
arch/sandbox/include/asm/io.h | 16 +++-
arch/sandbox/include/asm/processor.h | 12 +++
arch/sandbox/include/asm/test.h | 7 +-
arch/sandbox/include/asm/u-boot-sandbox.h | 48 +++
arch/sandbox/lib/Makefile | 2 +-
arch/sandbox/lib/pci_io.c | 138 ++
9 files changed, 281 insertions(+), 8 deletions(-)
create mode 100644 arch/sandbox/include/asm/processor.h
create mode 100644 arch/sandbox/lib/pci_io.c
diff --git a/arch/sandbox/Kconfig b/arch/sandbox/Kconfig
index 2098b9c..477a20a 100644
--- a/arch/sandbox/Kconfig
+++ b/arch/sandbox/Kconfig
@@ -34,4 +34,11 @@ config DM_I2C
config DM_TEST
default y
+config PCI
+ bool PCI support
+ help
+ Enable support for PCI (Peripheral Interconnect Bus), a type of bus
+ used on some devices to allow the CPU to communicate with its
+ peripherals.
+
endmenu
diff --git a/arch/sandbox/cpu/cpu.c b/arch/sandbox/cpu/cpu.c
index 1aa397c..1e67a31 100644
--- a/arch/sandbox/cpu/cpu.c
+++ b/arch/sandbox/cpu/cpu.c
@@ -2,7 +2,7 @@
* Copyright (c) 2011 The Chromium OS Authors.
* SPDX-License-Identifier:GPL-2.0+
*/
-
+#define DEBUG
#include common.h
#include dm/root.h
#include os.h
@@ -10,6 +10,13 @@
DECLARE_GLOBAL_DATA_PTR;
+/* Enable access to PCI memory with map_sysmem() */
+static bool enable_pci_map;
+
+/* Last device that was mapped into memory, and length of mapping */
+static struct udevice *map_dev;
+unsigned long map_len;
+
void reset_cpu(ulong ignored)
{
if (state_uninit())
@@ -59,9 +66,37 @@ int cleanup_before_linux(void)
void *map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags)
{
+#ifdef CONFIG_PCI
+ unsigned long plen = len;
+ void *ptr;
+
+ map_dev = NULL;
+ if (enable_pci_map !pci_map_physmem(paddr, len, map_dev, ptr)) {
+ if (plen != len) {
+ printf(%s: Warning: partial map at %x, wanted %lx, got
%lx\n,
+ __func__, paddr, len, plen);
+ }
+ map_len = len;
+ return ptr;
+ }
+#endif
+
return (void *)(gd-arch.ram_buf + paddr);
}
+void unmap_physmem(const void *vaddr, unsigned long flags)
+{
+ if (map_dev) {
+ pci_unmap_physmem(vaddr, map_len, map_dev);
+ map_dev = NULL;
+ }
+}
+
+void sandbox_set_enable_pci_map(int enable)
+{
+ enable_pci_map = enable;
+}
+
phys_addr_t map_to_sysmem(const void *ptr)
{
return (u8 *)ptr - gd-arch.ram_buf;
diff --git a/arch/sandbox/dts/sandbox.dts b/arch/sandbox/dts/sandbox.dts
index 1ccfdee..42a1f21 100644
--- a/arch/sandbox/dts/sandbox.dts
+++ b/arch/sandbox/dts/sandbox.dts
@@ -2,7 +2,11 @@
/ {
#address-cells = 1;
- #size-cells = 0;
+ #size-cells = 1;
+
+ aliases {
+ pci0 = pci;
+ };
chosen {
stdout-path = /serial;
@@ -181,4 +185,20 @@
};
};
+ pci: pci-controller {
+ compatible = sandbox,pci;
+ device_type = pci;
+ #address-cells = 3;
+ #size-cells = 2;
+ ranges = 0x0200 0 0x1000 0x1000 0 0x2000
+ 0x0100 0 0x2000 0x2000 0 0x2000;
+ pci@1f,0 {
+ compatible = pci-generic;
+ reg = 0xf800 0 0 0 0;
+ emul@1f,0 {
+ compatible = sandbox,swap-case;
+ };
+ };
+ };
+
};
diff --git a/arch/sandbox/include/asm/io.h b/arch/sandbox/include/asm/io.h
index 895fcb8..5b87fde 100644
--- a/arch/sandbox/include/asm/io.h
+++ b/arch/sandbox/include/asm/io.h
@@ -22,10 +22,7 @@ void *map_physmem(phys_addr_t paddr, unsigned long len,
unsigned long flags);
/*
* Take down a mapping set up by map_physmem().
*/
-static inline void unmap_physmem(void *vaddr, unsigned long flags)
-{
-
-}
+void unmap_physmem(const void *vaddr, unsigned long flags);
/* For sandbox, we want addresses to point into our RAM buffer */
static inline void *map_sysmem(phys_addr_t paddr, unsigned long len)
@@ -33,8 +30,10 @@ static inline void *map_sysmem(phys_addr_t paddr, unsigned
long len)
return map_physmem(paddr, len, MAP_WRBACK);
}
+/* Remove a previous mapping */
static inline void unmap_sysmem(const void *vaddr)
{
+ unmap_physmem(vaddr, MAP_WRBACK);
}
/* Map from a
[U-Boot] [PATCH] omap: gpmc: 'nandecc sw' can use HAM1 or BCH8
The 'nandecc sw' command selects a software-based error correction
algorithm. By default, this is OMAP_ECC_HAM1_CODE_SW but some
platforms use OMAP_ECC_BCH8_CODE_HW_DETECTION_SW as their
software-based correction algorithm. Allow a user to be specific e.g.
# nandecc sw hamming|bch8
where 'hamming' is still the default.
Note: we don't just use CONFIG_NAND_OMAP_ECCSCHEME as it might be set
to a hardware-based ECC scheme---a little strange when the user
has requested 'sw' ECC.
Signed-off-by: Ash Charles ashchar...@gmail.com
---
arch/arm/cpu/armv7/omap3/board.c | 11 ++-
drivers/mtd/nand/omap_gpmc.c | 12 +++-
2 files changed, 21 insertions(+), 2 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap3/board.c b/arch/arm/cpu/armv7/omap3/board.c
index 667e77f..b4e29ab 100644
--- a/arch/arm/cpu/armv7/omap3/board.c
+++ b/arch/arm/cpu/armv7/omap3/board.c
@@ -327,7 +327,16 @@ static int do_switch_ecc(cmd_tbl_t * cmdtp, int flag, int
argc, char * const arg
goto usage;
}
} else if (strncmp(argv[1], sw, 2) == 0) {
- omap_nand_switch_ecc(0, 0);
+ if (argc == 2) {
+ omap_nand_switch_ecc(0, 1);
+ } else {
+ if (strncmp(argv[2], hamming, 7) == 0)
+ omap_nand_switch_ecc(0, 1);
+ else if (strncmp(argv[2], bch8, 4) == 0)
+ omap_nand_switch_ecc(0, 8);
+ else
+ goto usage;
+ }
} else {
goto usage;
}
diff --git a/drivers/mtd/nand/omap_gpmc.c b/drivers/mtd/nand/omap_gpmc.c
index db1599e..d6a28e6 100644
--- a/drivers/mtd/nand/omap_gpmc.c
+++ b/drivers/mtd/nand/omap_gpmc.c
@@ -794,8 +794,18 @@ int __maybe_unused omap_nand_switch_ecc(uint32_t hardware,
uint32_t eccstrength)
return -EINVAL;
}
} else {
- err = omap_select_ecc_scheme(nand, OMAP_ECC_HAM1_CODE_SW,
+ if (eccstrength == 1) {
+ err = omap_select_ecc_scheme(nand,
+ OMAP_ECC_HAM1_CODE_SW,
+ mtd-writesize, mtd-oobsize);
+ } else if (eccstrength == 8) {
+ err = omap_select_ecc_scheme(nand,
+ OMAP_ECC_BCH8_CODE_HW_DETECTION_SW,
mtd-writesize, mtd-oobsize);
+ } else {
+ printf(nand: error: unsupported ECC scheme\n);
+ return -EINVAL;
+ }
}
/* Update NAND handling after ECC mode switch */
--
2.1.0
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 01/22] dm: i2c: Add a missing memory allocaton check
This strdup() is missing a check. Add it. Signed-off-by: Simon Glass s...@chromium.org --- drivers/i2c/i2c-uclass.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/i2c/i2c-uclass.c b/drivers/i2c/i2c-uclass.c index a6991bf..b890806 100644 --- a/drivers/i2c/i2c-uclass.c +++ b/drivers/i2c/i2c-uclass.c @@ -230,6 +230,8 @@ static int i2c_bind_driver(struct udevice *bus, uint chip_addr, uint offset_len, snprintf(name, sizeof(name), generic_%x, chip_addr); str = strdup(name); + if (!str) + return -ENOMEM; ret = device_bind_driver(bus, i2c_generic_chip_drv, str, dev); debug(%s: device_bind_driver: ret=%d\n, __func__, ret); if (ret) -- 2.2.0.rc0.207.ga3a616c ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 12/22] dm: pci: Move common PCI functions into their own file
Driver model will share many functions with the existing PCI implementation.
Move these into their own file to avoid duplication and confusion.
Signed-off-by: Simon Glass s...@chromium.org
---
drivers/pci/Makefile | 2 +-
drivers/pci/pci.c| 281 +
drivers/pci/pci_common.c | 292 +++
include/pci.h| 14 +++
4 files changed, 313 insertions(+), 276 deletions(-)
create mode 100644 drivers/pci/pci_common.c
diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
index 50b7be5..856a5f5 100644
--- a/drivers/pci/Makefile
+++ b/drivers/pci/Makefile
@@ -6,7 +6,7 @@
#
obj-$(CONFIG_FSL_PCI_INIT) += fsl_pci_init.o
-obj-$(CONFIG_PCI) += pci.o pci_auto.o pci_rom.o
+obj-$(CONFIG_PCI) += pci.o pci_common.o pci_auto.o pci_rom.o
obj-$(CONFIG_PCI_INDIRECT_BRIDGE) += pci_indirect.o
obj-$(CONFIG_PCI_GT64120) += pci_gt64120.o
obj-$(CONFIG_PCI_MSC01) += pci_msc01.o
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index e1296ca..3babd94 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -101,25 +101,6 @@ PCI_READ_VIA_DWORD_OP(word, u16 *, 0x02)
PCI_WRITE_VIA_DWORD_OP(byte, u8, 0x03, 0x00ff)
PCI_WRITE_VIA_DWORD_OP(word, u16, 0x02, 0x)
-/* Get a virtual address associated with a BAR region */
-void *pci_map_bar(pci_dev_t pdev, int bar, int flags)
-{
- pci_addr_t pci_bus_addr;
- u32 bar_response;
-
- /* read BAR address */
- pci_read_config_dword(pdev, bar, bar_response);
- pci_bus_addr = (pci_addr_t)(bar_response ~0xf);
-
- /*
-* Pass 0 as the length argument to pci_bus_to_virt. The arg
-* isn't actualy used on any platform because u-boot assumes a static
-* linear mapping. In the future, this could read the BAR size
-* and pass that as the size if needed.
-*/
- return pci_bus_to_virt(pdev, pci_bus_addr, flags, 0, MAP_NOCACHE);
-}
-
/*
*
*/
@@ -187,106 +168,22 @@ int pci_last_busno(void)
pci_dev_t pci_find_devices(struct pci_device_id *ids, int index)
{
struct pci_controller * hose;
- u16 vendor, device;
- u8 header_type;
pci_dev_t bdf;
- int i, bus, found_multi = 0;
+ int bus;
for (hose = pci_get_hose_head(); hose; hose = hose-next) {
#ifdef CONFIG_SYS_SCSI_SCAN_BUS_REVERSE
- for (bus = hose-last_busno; bus = hose-first_busno; bus--)
+ for (bus = hose-last_busno; bus = hose-first_busno; bus--) {
#else
- for (bus = hose-first_busno; bus = hose-last_busno; bus++)
+ for (bus = hose-first_busno; bus = hose-last_busno; bus++) {
#endif
- for (bdf = PCI_BDF(bus, 0, 0);
-bdf PCI_BDF(bus + 1, 0, 0);
-bdf += PCI_BDF(0, 0, 1)) {
- if (pci_skip_dev(hose, bdf))
- continue;
-
- if (!PCI_FUNC(bdf)) {
- pci_read_config_byte(bdf,
-PCI_HEADER_TYPE,
-header_type);
-
- found_multi = header_type 0x80;
- } else {
- if (!found_multi)
- continue;
- }
-
- pci_read_config_word(bdf,
-PCI_VENDOR_ID,
-vendor);
- pci_read_config_word(bdf,
-PCI_DEVICE_ID,
-device);
-
- for (i = 0; ids[i].vendor != 0; i++) {
- if (vendor == ids[i].vendor
- device == ids[i].device) {
- if (index = 0)
- return bdf;
-
- index--;
- }
- }
- }
- }
-
- return -1;
-}
-
-pci_dev_t pci_find_class(uint find_class, int index)
-{
- int bus;
- int devnum;
- pci_dev_t bdf;
- uint32_t class;
-
- for (bus = 0; bus = pci_last_busno(); bus++) {
- for (devnum = 0; devnum PCI_MAX_PCI_DEVICES - 1; devnum++) {
- pci_read_config_dword(PCI_BDF(bus, devnum, 0),
- PCI_CLASS_REVISION, class);
- if (class 16 == 0x)
- continue;
-
- for (bdf =
[U-Boot] [PATCH 02/22] sandbox: Correct device tree 'reg' properties for I2C and SPI
These are missing a size value. Add one in each case.
Signed-off-by: Simon Glass s...@chromium.org
---
arch/sandbox/dts/sandbox.dts | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/sandbox/dts/sandbox.dts b/arch/sandbox/dts/sandbox.dts
index 9ce31bf..1ccfdee 100644
--- a/arch/sandbox/dts/sandbox.dts
+++ b/arch/sandbox/dts/sandbox.dts
@@ -144,7 +144,7 @@
i2c@0 {
#address-cells = 1;
#size-cells = 0;
- reg = 0;
+ reg = 0 0;
compatible = sandbox,i2c;
clock-frequency = 40;
eeprom@2c {
@@ -161,7 +161,7 @@
spi@0 {
#address-cells = 1;
#size-cells = 0;
- reg = 0;
+ reg = 0 0;
compatible = sandbox,spi;
cs-gpios = 0, gpio_a 0;
flash@0 {
--
2.2.0.rc0.207.ga3a616c
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 03/22] fdt: Export fdtdec_get_number() for general use
This function is missing a prototype but is more widey useful. Add it.
Signed-off-by: Simon Glass s...@chromium.org
---
include/fdtdec.h | 11 +++
lib/fdtdec.c | 2 +-
2 files changed, 12 insertions(+), 1 deletion(-)
diff --git a/include/fdtdec.h b/include/fdtdec.h
index 1bc70db..2a96a0a 100644
--- a/include/fdtdec.h
+++ b/include/fdtdec.h
@@ -385,6 +385,17 @@ s32 fdtdec_get_int(const void *blob, int node, const char
*prop_name,
s32 default_val);
/**
+ * Get a variable-sized number from a property
+ *
+ * This reads a number from one or more cells.
+ *
+ * @param ptr Pointer to property
+ * @param cellsNumber of cells containing the number
+ * @return the value in the cells
+ */
+u64 fdtdec_get_number(const fdt32_t *ptr, unsigned int cells);
+
+/**
* Look up a 64-bit integer property in a node and return it. The property
* must have at least 8 bytes of data (2 cells). The first two cells are
* concatenated to form a 8 bytes value, where the first cell is top half and
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index dd58bbb..d4bc8b4 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -917,7 +917,7 @@ int fdtdec_read_fmap_entry(const void *blob, int node,
const char *name,
return 0;
}
-static u64 fdtdec_get_number(const fdt32_t *ptr, unsigned int cells)
+u64 fdtdec_get_number(const fdt32_t *ptr, unsigned int cells)
{
u64 number = 0;
--
2.2.0.rc0.207.ga3a616c
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PULL v2] u-boot-avr32/master - u-boot/master
On Wed, Feb 18, 2015 at 12:20:25AM +0100, Andreas Bießmann wrote: Hi Tom, reworked pull request for avr32 generic board support. The following changes since commit 5745f8c4fd5807becf7f246625e153388293aedc: Merge git://git.denx.de/u-boot-marvell (2015-02-16 08:44:03 -0500) are available in the git repository at: git://git.denx.de/u-boot-avr32.git master for you to fetch changes up to 5c98d7ffb0b11c9e3909f56ec5ce9dff682f1e30: atstk1002: enable generic board (2015-02-17 22:54:41 +0100) Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Please pull u-boot-fdt
On Wed, Feb 18, 2015 at 06:09:28AM -0700, Simon Glass wrote: Hi Tom, The following changes since commit 5745f8c4fd5807becf7f246625e153388293aedc: Merge git://git.denx.de/u-boot-marvell (2015-02-16 08:44:03 -0500) are available in the git repository at: http://git.denx.de/u-boot-fdt.git for you to fetch changes up to c71a0164d9b23e624552fb614bcb426a9b57: cmd_fdt: Print the control fdt in terms of virtual memory (2015-02-17 20:19:16 -0700) Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH V3 3/3] rpi: add support for Raspberry Pi 2 model B
On 02/17/2015 01:22 PM, Tom Rini wrote: On Tue, Feb 17, 2015 at 12:35:41PM -0700, Stephen Warren wrote: On 02/16/2015 06:03 PM, Tom Rini wrote: On Mon, Feb 16, 2015 at 12:16:15PM -0700, Stephen Warren wrote: USB doesn't seem to work yet; the controller detects the on-board Hub/ Ethernet device but can't read the descriptors from it. I haven't investigated yet. Signed-off-by: Stephen Warren swar...@wwwdotorg.org --- v3: Rebased on top of u-boot-dm merge. v2: Implement new board_rev decoding scheme, to avoid hard-coding the board revision onthe RPi 2. +(rpi_2) make[3]: *** No rule to make target `arch/arm/cpu/armv7/bcm2835/../../arm1176/bcm2835//init.o', needed by `arch/arm/cpu/armv7/bcm2835/built-in.o'. Stop. +(rpi_2) make[2]: *** [arch/arm/cpu/armv7/bcm2835] Error 2 +(rpi_2) make[1]: *** [arch/arm/cpu/armv7] Error 2 When I try and build it with buildman. Something get left out somewhere? Thanks! I've reproduced this error on my machine at work, where I previously worked out the right stuff to put into ~/.buildman. Now that I try the regular build process (in-tree build using just make) multiple times after a git clean -f -d -x , I see the same error that way too, sometimes, so it's nothing to do with buildman. However, I don't always get the error with either plain make or with buildman, and it doesn't always complain about the same file: +make[1]: *** No rule to make target `arch//cpu/u-boot.lds', needed by `u-boot.lds'. Stop. +make[3]: *** No rule to make target `arch/arm/cpu/armv7/bcm2835/../../arm1176/bcm2835//init.o', needed by `arch/arm/cpu/armv7/bcm2835/built-in.o'. Stop. This isn't anything to do with these patches; I can see the exact same issue building the following existing boards in unmodified u-boot/master: rpi (arm1176, no SPL) tnetv107x_evm_defconfigs (arm1176 no SPL) mx35pdk_defconfig (arm1136, no SPL) nhk8815_defconfig (arm926ejs, no SPL) imx27lite_defconfig (arm926ejs, SPL) vexpress_ca15_tc2_defconfig (ARMv7, no SPL) Strangely I don't see the issue for: seaboard (ARMv7, SPL) maxbcm_defconfig (ARMv7, SPL) I wonder if bisecting would show up where this issue was introduced. I bet it will and I bet it's when we switch to Kconfig. Masahiro, any ideas? Yes, a git bisect (running up to 100 successful builds to test each commit, or failing on the first failure) says: first bad commit: [51148790f26e42ef1fd4a1a8d056bf0252539525] kconfig: switch to Kconfig (which was applied at the end of July last year) Interesting: The problem never seems to happen on my laptop (where I do all my rpi dev work), but is quite easy to reproduce on my faster machine at work. I would guess it only affects parallel builds in certain timing circumstances, but haven't checked that. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 01/22] dm: i2c: Add a missing memory allocaton check
Hello Simon, Am 18.02.2015 22:10, schrieb Simon Glass: This strdup() is missing a check. Add it. Signed-off-by: Simon Glass s...@chromium.org --- drivers/i2c/i2c-uclass.c | 2 ++ 1 file changed, 2 insertions(+) Good catch, Thanks! Acked-by: Heiko Schocher h...@denx.de bye, Heiko diff --git a/drivers/i2c/i2c-uclass.c b/drivers/i2c/i2c-uclass.c index a6991bf..b890806 100644 --- a/drivers/i2c/i2c-uclass.c +++ b/drivers/i2c/i2c-uclass.c @@ -230,6 +230,8 @@ static int i2c_bind_driver(struct udevice *bus, uint chip_addr, uint offset_len, snprintf(name, sizeof(name), generic_%x, chip_addr); str = strdup(name); + if (!str) + return -ENOMEM; ret = device_bind_driver(bus, i2c_generic_chip_drv, str, dev); debug(%s: device_bind_driver: ret=%d\n, __func__, ret); if (ret) -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 0/4] kconfig: turnaround into single .config
Masahiro Yamada (4): ARM: UniPhier: set CONFIG_SYS_MALLOC_F to the global default value malloc_f: fix broken .config caused by CONFIG_SYS_MALLOC_F kconfig: switch to single .config configuration kconfig: remove unneeded dependency on !SPL_BUILD Kconfig | 27 +--- arch/arm/Kconfig| 7 +- arch/arm/cpu/arm1176/bcm2835/Kconfig| 6 +- arch/arm/cpu/armv7/exynos/Kconfig | 29 ++-- arch/arm/cpu/armv7/omap3/Kconfig| 11 +- arch/arm/cpu/armv7/s5pc1xx/Kconfig | 4 +- arch/arm/cpu/armv7/tegra-common/Kconfig | 18 ++- arch/arm/cpu/armv7/uniphier/Kconfig | 5 - arch/x86/Kconfig| 4 +- board/amcc/canyonlands/Kconfig | 4 - board/compulab/cm_t335/Kconfig | 6 +- board/gumstix/pepper/Kconfig| 6 +- board/isee/igep0033/Kconfig | 6 +- board/phytec/pcm051/Kconfig | 6 +- board/samsung/goni/Kconfig | 6 +- board/samsung/smdkc100/Kconfig | 6 +- board/silica/pengwyn/Kconfig| 6 +- board/ti/am335x/Kconfig | 11 +- common/Kconfig | 1 - config.mk | 5 + configs/ph1_ld4_defconfig | 2 +- configs/ph1_pro4_defconfig | 2 +- configs/ph1_sld8_defconfig | 2 +- doc/README.kconfig | 128 drivers/core/Kconfig| 16 +- drivers/mtd/nand/Kconfig| 6 +- dts/Kconfig | 1 - include/config_uncmd_spl.h | 13 ++ scripts/Makefile.autoconf | 36 +++-- scripts/Makefile.build | 3 +- scripts/Makefile.spl| 10 +- scripts/Makefile.uncmd_spl | 18 +++ scripts/multiconfig.sh | 261 +--- 33 files changed, 182 insertions(+), 490 deletions(-) create mode 100644 scripts/Makefile.uncmd_spl -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 2/4] malloc_f: fix broken .config caused by CONFIG_SYS_MALLOC_F
Since commit b724bd7d6349 (dm: Kconfig: Move CONFIG_SYS_MALLOC_F_LEN to Kconfig), the .config created by the configuration has been wrong. For example, the following is a snippet of the .config generated by make beaver_defconfig: ---8- CONFIG_CC_OPTIMIZE_FOR_SIZE=y # CONFIG_SYS_MALLOC_F is not set CONFIG_SYS_MALLOC_F_LEN=0x1800 # CONFIG_EXPERT is not set ---8- CONFIG_SYS_MALLOC_F_LEN is supposed to depend on CONFIG_SYS_MALLOC_F (see the top level Kconfig), but the .config above is not actually following that dependency. This is caused by two mistakes of commit b724bd7d6349. [1] Wrong default value of CONFIG_SYS_MALLOC_F CONFIG_SYS_MALLOC_F is a boolean option, but its default value is set to 0x400. [2] Missing if SYS_MALLOC_F in the default setting in each Kconfig For example, arch/arm/cpu/armv7/tegra-common/Kconfig has the line default 0x1800 for SYS_MALLOC_F_LEN. It must be described as default 0x1800 if SYS_MALLOC_F to follow the dependency. Those two bugs together create such a broken .config. Unfortunately, even if we correct both [1] and [2], the value of CONFIG_SYS_MALLOC_F_LEN is not set as we expect. The default 0x1800 if SYS_MALLOC_F would be simply ignored because the default 0x400 in the top level Kconfig is parsed first. Notice that if multiple default lines appear for the same CONFIG, the first one takes precedence. So, this commit correct [1] and [2], also leaves some comments in arch/arm/cpu/armv7/tegra-common/Kconfig and arch/x86/Kconfig to notify not-working default values. If you want to change the default value of CONFIG_SYS_MALLOC_F_LEN, the easiest way would be to specify it in each *_defconfig. It is true that describing SoC-common default values in each Kconfig seems handy, but it often introduces nasty problems. If you do not understand well how Kconfig works, as you see above, you could easily create a broken .config file. The default value 0x400 is redundant for OMAP, Exynos, UniPhier, etc. They can be simply removed. There are still redundant CONFIG_SYS_MALLOC_F_LEN=0x400 in many defconfig files, but this commit is not touching them. Signed-off-by: Masahiro Yamada yamad...@jp.panasonic.com --- Changes in v2: None Kconfig | 1 - arch/arm/cpu/armv7/exynos/Kconfig | 3 --- arch/arm/cpu/armv7/omap3/Kconfig| 3 --- arch/arm/cpu/armv7/tegra-common/Kconfig | 4 +++- arch/arm/cpu/armv7/uniphier/Kconfig | 3 --- arch/x86/Kconfig| 4 +++- board/amcc/canyonlands/Kconfig | 4 board/ti/am335x/Kconfig | 3 --- 8 files changed, 6 insertions(+), 19 deletions(-) diff --git a/Kconfig b/Kconfig index 75bab7f..d40f9ec 100644 --- a/Kconfig +++ b/Kconfig @@ -58,7 +58,6 @@ config CC_OPTIMIZE_FOR_SIZE config SYS_MALLOC_F bool Enable malloc() pool before relocation - default 0x400 help Before relocation memory is very limited on many platforms. Still, we can provide a small malloc() pool if needed. Driver model in diff --git a/arch/arm/cpu/armv7/exynos/Kconfig b/arch/arm/cpu/armv7/exynos/Kconfig index 2064efa..23869ce 100644 --- a/arch/arm/cpu/armv7/exynos/Kconfig +++ b/arch/arm/cpu/armv7/exynos/Kconfig @@ -83,9 +83,6 @@ config DM_GPIO config SYS_MALLOC_F default y if !SPL_BUILD -config SYS_MALLOC_F_LEN - default 0x400 if !SPL_BUILD - source board/samsung/smdkv310/Kconfig source board/samsung/trats/Kconfig source board/samsung/universal_c210/Kconfig diff --git a/arch/arm/cpu/armv7/omap3/Kconfig b/arch/arm/cpu/armv7/omap3/Kconfig index 4644098..2e193ab 100644 --- a/arch/arm/cpu/armv7/omap3/Kconfig +++ b/arch/arm/cpu/armv7/omap3/Kconfig @@ -105,9 +105,6 @@ config DM_SERIAL config SYS_MALLOC_F default y if DM !SPL_BUILD -config SYS_MALLOC_F_LEN - default 0x400 if DM !SPL_BUILD - config SYS_SOC default omap3 diff --git a/arch/arm/cpu/armv7/tegra-common/Kconfig b/arch/arm/cpu/armv7/tegra-common/Kconfig index ee32469..0de13ae 100644 --- a/arch/arm/cpu/armv7/tegra-common/Kconfig +++ b/arch/arm/cpu/armv7/tegra-common/Kconfig @@ -20,8 +20,10 @@ endchoice config SYS_MALLOC_F default y +# This is meaningless. +# default 0x400 in the top level Kconfig is used in stead. config SYS_MALLOC_F_LEN - default 0x1800 + default 0x1800 if SYS_MALLOC_F config USE_PRIVATE_LIBGCC default y if SPL_BUILD diff --git a/arch/arm/cpu/armv7/uniphier/Kconfig b/arch/arm/cpu/armv7/uniphier/Kconfig index 8fdef28..371b274 100644 --- a/arch/arm/cpu/armv7/uniphier/Kconfig +++ b/arch/arm/cpu/armv7/uniphier/Kconfig @@ -51,9 +51,6 @@ endchoice config SYS_MALLOC_F default y -config SYS_MALLOC_F_LEN - default 0x400 - config CMD_PINMON bool Enable boot mode pins monitor command default y diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 35d24e4..2275374 100644 ---
[U-Boot] [PATCH v2 1/4] ARM: UniPhier: set CONFIG_SYS_MALLOC_F to the global default value
It is true that malloc is necessary for Driver Model before relocation, but there is no good reason to reserve the malloc space more than enough. The default value 0x400 works well. Signed-off-by: Masahiro Yamada yamad...@jp.panasonic.com --- Changes in v2: None arch/arm/cpu/armv7/uniphier/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/cpu/armv7/uniphier/Kconfig b/arch/arm/cpu/armv7/uniphier/Kconfig index 1a47ac9..8fdef28 100644 --- a/arch/arm/cpu/armv7/uniphier/Kconfig +++ b/arch/arm/cpu/armv7/uniphier/Kconfig @@ -52,7 +52,7 @@ config SYS_MALLOC_F default y config SYS_MALLOC_F_LEN - default 0x2000 + default 0x400 config CMD_PINMON bool Enable boot mode pins monitor command -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 3/4] kconfig: switch to single .config configuration
When Kconfig for U-boot was examined, one of the biggest issues was how to support multiple images (Normal, SPL, TPL). There were actually two options, single .config and multiple .config. After some discussions and thought experiments, I chose the latter, i.e. to create .config, spl/.config, tpl/.config for Normal, SPL, TPL, respectively. It is true that the multiple .config strategy provided us the maximum flexibility and helped to avoid duplicating CONFIGs among Normal, SPL, TPL, but I have noticed some fatal problems: [1] It is impossible to share CONFIG options across the images. If you change the configuration of Main image, you often have to adjust some SPL configurations correspondingly. Currently, we cannot handle the dependencies between them. It means one of the biggest advantages of Kconfig is lost. [2] It is too painful to change both .config and spl/.config. Sunxi guys started to work around this problem by creating a new configuration target. Commit cbdd9a9737cc (sunxi: kconfig: Add %_felconfig rule to enable FEL build of sunxi platforms.) added make *_felconfig to enable CONFIG_SPL_FEL on both images. Changing the configuration of multiple images in one command is a generic demand. The current implementation cannot propose any good solution about this. [3] Kconfig files are getting ugly and difficult to undestand. Commit b724bd7d6349 (dm: Kconfig: Move CONFIG_SYS_MALLOC_F_LEN to Kconfig) has sprinkled if !SPL_BUILD over the Kconfig files. [4] The build system got more complicated than it should be. To adjust Linux-originated Kconfig to U-Boot, the helper script scripts/multiconfig.sh was introduced. Writing a complicated text processor is a shell script sometimes caused problems. Now I believe the single .config will serve us better. With it, all the problems above would go away. Instead, we will have to add some CONFIG_SPL_* (and CONFIG_TPL_*) options such as CONFIG_SPL_DM, but we will not have much. Anyway, this is what we do now in scripts/Makefile.spl. I admit my mistake with my apology and this commit switches to the single .config configuration. It is not so difficult to do that: - Remove unnecessary processing from scripts/multiconfig.sh This file will remain for a while to support the current defconfig format. It will be removed after more cleanups. - Adjust some makefiles and Kconfigs - Add some entries to include/config_uncmd_spl.h and a new file scripts/Makefile.uncmd_spl. Some CONFIG options that are not supported on SPL must be disabled because one .config is shared between SPL and U-Boot proper going forward. I know this is not a beatiful solution and I think we can do better, but let's see how much we will have to describe them. - update doc/README.kconfig More cleaning up patches will follow this. Signed-off-by: Masahiro Yamada yamad...@jp.panasonic.com --- Kconfig | 14 -- arch/arm/cpu/armv7/tegra-common/Kconfig | 2 +- arch/arm/cpu/armv7/uniphier/Kconfig | 1 - config.mk | 5 + configs/ph1_ld4_defconfig | 2 +- configs/ph1_pro4_defconfig | 2 +- configs/ph1_sld8_defconfig | 2 +- doc/README.kconfig | 128 drivers/mtd/nand/Kconfig| 2 +- include/config_uncmd_spl.h | 9 ++ scripts/Makefile.autoconf | 36 +++-- scripts/Makefile.build | 3 +- scripts/Makefile.spl| 10 +- scripts/Makefile.uncmd_spl | 16 ++ scripts/multiconfig.sh | 261 +--- 15 files changed, 106 insertions(+), 387 deletions(-) create mode 100644 scripts/Makefile.uncmd_spl diff --git a/Kconfig b/Kconfig index d40f9ec..d3b8b69 100644 --- a/Kconfig +++ b/Kconfig @@ -8,10 +8,6 @@ config UBOOTVERSION string option env=UBOOTVERSION -config KCONFIG_OBJDIR - string - option env=KCONFIG_OBJDIR - menu General setup config LOCALVERSION @@ -86,16 +82,6 @@ endmenu # General setup menu Boot images -config SPL_BUILD - bool - depends on $KCONFIG_OBJDIR=spl || $KCONFIG_OBJDIR=tpl - default y - -config TPL_BUILD - bool - depends on $KCONFIG_OBJDIR=tpl - default y - config SUPPORT_SPL bool diff --git a/arch/arm/cpu/armv7/tegra-common/Kconfig b/arch/arm/cpu/armv7/tegra-common/Kconfig index 0de13ae..c9e8919 100644 --- a/arch/arm/cpu/armv7/tegra-common/Kconfig +++ b/arch/arm/cpu/armv7/tegra-common/Kconfig @@ -26,7 +26,7 @@ config SYS_MALLOC_F_LEN default 0x1800 if SYS_MALLOC_F config USE_PRIVATE_LIBGCC - default y if SPL_BUILD + default y config DM default y if !SPL_BUILD diff --git a/arch/arm/cpu/armv7/uniphier/Kconfig b/arch/arm/cpu/armv7/uniphier/Kconfig index 371b274..afb3c55 100644 ---
[U-Boot] [PATCH 2/4] malloc_f: fix broken .config caused by CONFIG_SYS_MALLOC_F
Since commit b724bd7d6349 (dm: Kconfig: Move CONFIG_SYS_MALLOC_F_LEN to Kconfig), the .config created by the configuration has been wrong. For example, the following is a snippet of the .config generated by make beaver_defconfig: ---8- CONFIG_CC_OPTIMIZE_FOR_SIZE=y # CONFIG_SYS_MALLOC_F is not set CONFIG_SYS_MALLOC_F_LEN=0x1800 # CONFIG_EXPERT is not set ---8- CONFIG_SYS_MALLOC_F_LEN is supposed to depend on CONFIG_SYS_MALLOC_F (see the top level Kconfig), but the .config above is not actually following that dependency. This is caused by two mistakes of commit b724bd7d6349. [1] Wrong default value of CONFIG_SYS_MALLOC_F CONFIG_SYS_MALLOC_F is a boolean option, but its default value is set to 0x400. [2] Missing if SYS_MALLOC_F in the default setting in each Kconfig For example, arch/arm/cpu/armv7/tegra-common/Kconfig has the line default 0x1800 for SYS_MALLOC_F_LEN. It must be described as default 0x1800 if SYS_MALLOC_F to follow the dependency. Those two bugs together create such a broken .config. Unfortunately, even if we correct both [1] and [2], the value of CONFIG_SYS_MALLOC_F_LEN is not set as we expect. The default 0x1800 if SYS_MALLOC_F would be simply ignored because the default 0x400 in the top level Kconfig is parsed first. Notice that if multiple default lines appear for the same CONFIG, the first one takes precedence. So, this commit correct [1] and [2], also leaves some comments in arch/arm/cpu/armv7/tegra-common/Kconfig and arch/x86/Kconfig to notify not-working default values. If you want to change the default value of CONFIG_SYS_MALLOC_F_LEN, the easiest way would be to specify it in each *_defconfig. It is true that describing SoC-common default values in each Kconfig seems handy, but it often introduces nasty problems. If you do not understand well how Kconfig works, as you see above, you could easily create a broken .config file. The default value 0x400 is redundant for OMAP, Exynos, UniPhier, etc. They can be simply removed. There are still redundant CONFIG_SYS_MALLOC_F_LEN=0x400 in many defconfig files, but this commit is not touching them. Signed-off-by: Masahiro Yamada yamad...@jp.panasonic.com --- Kconfig | 1 - arch/arm/cpu/armv7/exynos/Kconfig | 3 --- arch/arm/cpu/armv7/omap3/Kconfig| 3 --- arch/arm/cpu/armv7/tegra-common/Kconfig | 4 +++- arch/arm/cpu/armv7/uniphier/Kconfig | 3 --- arch/x86/Kconfig| 4 +++- board/amcc/canyonlands/Kconfig | 4 board/ti/am335x/Kconfig | 3 --- 8 files changed, 6 insertions(+), 19 deletions(-) diff --git a/Kconfig b/Kconfig index 75bab7f..d40f9ec 100644 --- a/Kconfig +++ b/Kconfig @@ -58,7 +58,6 @@ config CC_OPTIMIZE_FOR_SIZE config SYS_MALLOC_F bool Enable malloc() pool before relocation - default 0x400 help Before relocation memory is very limited on many platforms. Still, we can provide a small malloc() pool if needed. Driver model in diff --git a/arch/arm/cpu/armv7/exynos/Kconfig b/arch/arm/cpu/armv7/exynos/Kconfig index 2064efa..23869ce 100644 --- a/arch/arm/cpu/armv7/exynos/Kconfig +++ b/arch/arm/cpu/armv7/exynos/Kconfig @@ -83,9 +83,6 @@ config DM_GPIO config SYS_MALLOC_F default y if !SPL_BUILD -config SYS_MALLOC_F_LEN - default 0x400 if !SPL_BUILD - source board/samsung/smdkv310/Kconfig source board/samsung/trats/Kconfig source board/samsung/universal_c210/Kconfig diff --git a/arch/arm/cpu/armv7/omap3/Kconfig b/arch/arm/cpu/armv7/omap3/Kconfig index 4644098..2e193ab 100644 --- a/arch/arm/cpu/armv7/omap3/Kconfig +++ b/arch/arm/cpu/armv7/omap3/Kconfig @@ -105,9 +105,6 @@ config DM_SERIAL config SYS_MALLOC_F default y if DM !SPL_BUILD -config SYS_MALLOC_F_LEN - default 0x400 if DM !SPL_BUILD - config SYS_SOC default omap3 diff --git a/arch/arm/cpu/armv7/tegra-common/Kconfig b/arch/arm/cpu/armv7/tegra-common/Kconfig index ee32469..0de13ae 100644 --- a/arch/arm/cpu/armv7/tegra-common/Kconfig +++ b/arch/arm/cpu/armv7/tegra-common/Kconfig @@ -20,8 +20,10 @@ endchoice config SYS_MALLOC_F default y +# This is meaningless. +# default 0x400 in the top level Kconfig is used in stead. config SYS_MALLOC_F_LEN - default 0x1800 + default 0x1800 if SYS_MALLOC_F config USE_PRIVATE_LIBGCC default y if SPL_BUILD diff --git a/arch/arm/cpu/armv7/uniphier/Kconfig b/arch/arm/cpu/armv7/uniphier/Kconfig index 8fdef28..371b274 100644 --- a/arch/arm/cpu/armv7/uniphier/Kconfig +++ b/arch/arm/cpu/armv7/uniphier/Kconfig @@ -51,9 +51,6 @@ endchoice config SYS_MALLOC_F default y -config SYS_MALLOC_F_LEN - default 0x400 - config CMD_PINMON bool Enable boot mode pins monitor command default y diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 35d24e4..2275374 100644 --- a/arch/x86/Kconfig +++
[U-Boot] [PATCH 1/4] ARM: UniPhier: set CONFIG_SYS_MALLOC_F to the global default value
It is true that malloc is necessary for Driver Model before relocation, but there is no good reason to reserve the malloc space more than enough. The default value 0x400 works well. Signed-off-by: Masahiro Yamada yamad...@jp.panasonic.com --- arch/arm/cpu/armv7/uniphier/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/cpu/armv7/uniphier/Kconfig b/arch/arm/cpu/armv7/uniphier/Kconfig index 1a47ac9..8fdef28 100644 --- a/arch/arm/cpu/armv7/uniphier/Kconfig +++ b/arch/arm/cpu/armv7/uniphier/Kconfig @@ -52,7 +52,7 @@ config SYS_MALLOC_F default y config SYS_MALLOC_F_LEN - default 0x2000 + default 0x400 config CMD_PINMON bool Enable boot mode pins monitor command -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 4/4] kconfig: remove unneeded dependency on !SPL_BUILD
Now CONFIG_SPL_BUILD is not defined in Kconfig, so !depends on SPL_BUILD arn if !SPL_BUILD are redundant. Signed-off-by: Masahiro Yamada yamad...@jp.panasonic.com --- Kconfig | 12 ++-- arch/arm/Kconfig| 7 +++ arch/arm/cpu/arm1176/bcm2835/Kconfig| 6 +++--- arch/arm/cpu/armv7/exynos/Kconfig | 26 +- arch/arm/cpu/armv7/omap3/Kconfig| 8 arch/arm/cpu/armv7/s5pc1xx/Kconfig | 4 ++-- arch/arm/cpu/armv7/tegra-common/Kconfig | 12 ++-- arch/arm/cpu/armv7/uniphier/Kconfig | 1 - board/compulab/cm_t335/Kconfig | 6 +++--- board/gumstix/pepper/Kconfig| 6 +++--- board/isee/igep0033/Kconfig | 6 +++--- board/phytec/pcm051/Kconfig | 6 +++--- board/samsung/goni/Kconfig | 6 +++--- board/samsung/smdkc100/Kconfig | 6 +++--- board/silica/pengwyn/Kconfig| 6 +++--- board/ti/am335x/Kconfig | 8 common/Kconfig | 1 - drivers/core/Kconfig| 16 ++-- drivers/mtd/nand/Kconfig| 4 dts/Kconfig | 1 - include/config_uncmd_spl.h | 4 scripts/Makefile.uncmd_spl | 4 +++- 22 files changed, 71 insertions(+), 85 deletions(-) diff --git a/Kconfig b/Kconfig index d3b8b69..e6a8e48 100644 --- a/Kconfig +++ b/Kconfig @@ -12,7 +12,6 @@ menu General setup config LOCALVERSION string Local version - append to U-Boot release - depends on !SPL_BUILD help Append an extra string to the end of your U-Boot version. This will show up on your boot log, for example. @@ -23,7 +22,6 @@ config LOCALVERSION config LOCALVERSION_AUTO bool Automatically append version information to the version string - depends on !SPL_BUILD default y help This will try to automatically determine if the current tree is a @@ -44,7 +42,6 @@ config LOCALVERSION_AUTO config CC_OPTIMIZE_FOR_SIZE bool Optimize for size - depends on !SPL_BUILD default y help Enabling this option will pass -Os instead of -O2 to gcc @@ -91,23 +88,19 @@ config SUPPORT_TPL config SPL bool depends on SUPPORT_SPL - prompt Enable SPL if !SPL_BUILD - default y if SPL_BUILD + prompt Enable SPL help If you want to build SPL as well as the normal image, say Y. config TPL bool depends on SPL SUPPORT_TPL - prompt Enable TPL if !SPL_BUILD - default y if TPL_BUILD - default n + prompt Enable TPL help If you want to build TPL as well as the normal image and SPL, say Y. config FIT bool Support Flattened Image Tree - depends on !SPL_BUILD help This option allows to boot the new uImage structrure, Flattened Image Tree. FIT is formally a FDT, which can include @@ -131,7 +124,6 @@ config FIT_SIGNATURE config SYS_EXTRA_OPTIONS string Extra Options (DEPRECATED) - depends on !SPL_BUILD help The old configuration infrastructure (= mkconfig + boards.cfg) provided the extra options field. If you have something like diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 41f3220..700e2a8 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -739,9 +739,8 @@ config TEGRA bool NVIDIA Tegra select SUPPORT_SPL select SPL - select OF_CONTROL if !SPL_BUILD - select CPU_ARM720T if SPL_BUILD - select CPU_V7 if !SPL_BUILD + select OF_CONTROL + select CPU_V7 config TARGET_VEXPRESS64_AEMV8A bool Support vexpress_aemv8a @@ -833,7 +832,7 @@ config ARCH_UNIPHIER select CPU_V7 select SUPPORT_SPL select SPL - select OF_CONTROL if !SPL_BUILD + select OF_CONTROL endchoice diff --git a/arch/arm/cpu/arm1176/bcm2835/Kconfig b/arch/arm/cpu/arm1176/bcm2835/Kconfig index 94f57d7..7d0fc67 100644 --- a/arch/arm/cpu/arm1176/bcm2835/Kconfig +++ b/arch/arm/cpu/arm1176/bcm2835/Kconfig @@ -1,12 +1,12 @@ if TARGET_RPI config DM - default y if !SPL_BUILD + default y config DM_SERIAL - default y if !SPL_BUILD + default y config DM_GPIO - default y if !SPL_BUILD + default y endif diff --git a/arch/arm/cpu/armv7/exynos/Kconfig b/arch/arm/cpu/armv7/exynos/Kconfig index 23869ce..9e47ed3 100644 --- a/arch/arm/cpu/armv7/exynos/Kconfig +++ b/arch/arm/cpu/armv7/exynos/Kconfig @@ -6,7 +6,7 @@ choice config TARGET_SMDKV310 select SUPPORT_SPL bool Exynos4210 SMDKV310 board - select OF_CONTROL if !SPL_BUILD + select OF_CONTROL config TARGET_TRATS bool Exynos4210 Trats board @@ -33,32 +33,32 @@ config TARGET_ARNDALE select CPU_V7_HAS_NONSEC
[U-Boot] Question about Arndale Octa board (Exynos 5420) and HYP mode
Hello, I have a Samsung Exynos 5420 Arndale Octa Board and I am trying to run Xen 4.5 on it. I have successfully managed to configure and patch XEN and the kernel for the board. The problem is that XEN doesn't match the correct CPU mode for its boot. -XEN early debug- Starting kernel ... - UART enabled - - CPU booting - - Xen must be entered in NS Hyp mode - - Boot failed - --- As far as I know, the only currently working U-Boot for the octa board is a signed 2012.07 version which starts the booting CPU in a NS SVC mode. I patched it, adding all the modules needed to bring the CPU to HYP mode, as in: http://lists.denx.de/pipermail/u-boot/2013-September/163019.html However, CPU does not seem to switch properly to HYP mode, as it hangs on an assembly instruction (hvc #0) when calling the function _switch_to_hyp(), just like in: http://markmail.org/thread/dhiknm25xfbsrlo6 I am than asking you if there is something I can do to overcome this problem or if there is someone working on it who can help me out. Any help or suggestion would be greatly appreciated. Regards, F.C. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 2/8] arm: relocation: clear .bss section with arch memset if defined
Hello, On 02/18/2015 05:32 AM, Simon Glass wrote: Hi Przemyslaw, On 16 February 2015 at 08:21, Przemyslaw Marczak p.marc...@samsung.com wrote: Hello, On 02/16/2015 04:13 PM, Przemyslaw Marczak wrote: For ARM architecture, enable the CONFIG_USE_ARCH_MEMSET/MEMCPY, will highly increase the memset/memcpy performance. This is able thanks to the ARM multiple register instructions. Unfortunatelly the relocation is done without the cache enabled, so it takes some time, but zeroing the BSS memory takes much more longer, especially for the configs with big static buffers. A quick test confirms, that the boot time improvement after using the arch memcpy for relocation has no significant meaning. The same test confirms that enable the memset for zeroing BSS, reduces the boot time. So this patch enables the arch memset for zeroing the BSS after the relocation process. For ARM boards, this can be enabled in board configs by defining: 'CONFIG_USE_ARCH_MEMSET'. This was tested on Trats2. A quick test with trace. Boot time from start to main_loop() entry: - ~1384ms - before this change - ~888ms - after this change Signed-off-by: Przemyslaw Marczak p.marc...@samsung.com Cc: Albert Aribaud albert.u.b...@aribaud.net Cc: Tom Rini tr...@ti.com --- arch/arm/lib/crt0.S | 10 +- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/arch/arm/lib/crt0.S b/arch/arm/lib/crt0.S index 22df3e5..fab3d2c 100644 --- a/arch/arm/lib/crt0.S +++ b/arch/arm/lib/crt0.S @@ -115,14 +115,22 @@ here: bl c_runtime_cpu_setup /* we still call old routine here */ ldr r0, =__bss_start/* this is auto-relocated! */ - ldr r1, =__bss_end /* this is auto-relocated! */ +#ifdef CONFIG_USE_ARCH_MEMSET + ldr r3, =__bss_end /* this is auto-relocated! */ + mov r1, #0x /* prepare zero to clear BSS */ + + subsr2, r3, r0 /* r2 = memset len */ + bl memset +#else + ldr r1, =__bss_end /* this is auto-relocated! */ mov r2, #0x /* prepare zero to clear BSS */ clbss_l:cmp r0, r1 /* while not at end of BSS */ strlo r2, [r0]/* clear 32-bit BSS word */ addlo r0, r0, #4 /* move to next */ blo clbss_l +#endif bl coloured_LED_init bl red_led_on This commit left unchanged. After boot time test using oscilloscope and the clock cycle counter I didn't noticed a time difference in more then one ms. In this case I think that insert a duplicated code here, has no sense. I don't understand this comment, sorry. Regards, Simon Sorry for the misleading message. When I send this patch set, I forgot about adding the message-id of the previous thread as in-reply-to. There was a discussion about insert the memory zeroing routines as an asm here, instead of using the 'memset' call. But I tested that there is no difference in the performance. So in this case, it's better to use the common lib and this commit is the same as it was in the first version. (I missed the changelog) Best regards, -- Przemyslaw Marczak Samsung RD Institute Poland Samsung Electronics p.marc...@samsung.com ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 6/8] kconfig: malloc: add option for skip memset at malloc init
Hi Simon, On 02/18/2015 05:32 AM, Simon Glass wrote: Hi Przemyslaw, On 16 February 2015 at 08:13, Przemyslaw Marczak p.marc...@samsung.com wrote: Signed-off-by: Przemyslaw Marczak p.marc...@samsung.com --- Kconfig | 26 +++--- 1 file changed, 19 insertions(+), 7 deletions(-) diff --git a/Kconfig b/Kconfig index 4157da3..e08e44a 100644 --- a/Kconfig +++ b/Kconfig @@ -57,13 +57,25 @@ config CC_OPTIMIZE_FOR_SIZE This option is enabled by default for U-Boot. Ah, you have done this. Then I think you can merge this patch with the dlmalloc patch and drop the README one. Shouldn't we keep both, README and Kconfig help? Kconfig is just a configuration tool, README is a documentation. Sometimes it could be faster to find something in the text instead of config. menuconfig EXPERT -bool Configure standard U-Boot features (expert users) -help - This option allows certain base U-Boot options and settings - to be disabled or tweaked. This is for specialized - environments which can tolerate a non-standard U-Boot. - Only use this if you really know what you are doing. - + bool Configure standard U-Boot features (expert users) + help + This option allows certain base U-Boot options and settings + to be disabled or tweaked. This is for specialized + environments which can tolerate a non-standard U-Boot. + Only use this if you really know what you are doing. + +if EXPERT + config SYS_MALLOC_INIT_SKIP_ZEROING + bool Skip memset at malloc init (reduce boot time) + help +This avoids zeroing memory reserved for malloc at malloc init. +Significant boot time reduction is visible for configs in which +CONFIG_SYS_MALLOC_LEN value, has more than few MiB. +Useful for bzip2, bmp logo. +Warning: +When enable, make sure that calloc() is used when zeroed +memory is needed. +endif endmenu# General setup menu Boot images -- 1.9.1 Regards, Simon Best regards, -- Przemyslaw Marczak Samsung RD Institute Poland Samsung Electronics p.marc...@samsung.com ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] Please pull u-boot-fdt
Hi Tom, The following changes since commit 5745f8c4fd5807becf7f246625e153388293aedc: Merge git://git.denx.de/u-boot-marvell (2015-02-16 08:44:03 -0500) are available in the git repository at: http://git.denx.de/u-boot-fdt.git for you to fetch changes up to c71a0164d9b23e624552fb614bcb426a9b57: cmd_fdt: Print the control fdt in terms of virtual memory (2015-02-17 20:19:16 -0700) Joe Hershberger (2): cmd_fdt: Actually fix fdt command in sandbox cmd_fdt: Print the control fdt in terms of virtual memory common/bootm.c| 2 +- common/cmd_fdt.c | 10 +- common/image-fdt.c| 2 +- include/fdt_support.h | 2 +- 4 files changed, 8 insertions(+), 8 deletions(-) Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 1/8] exynos: config: enable arch memcpy and arch memset
Hello, On 02/18/2015 05:23 AM, Simon Glass wrote: On 16 February 2015 at 08:13, Przemyslaw Marczak p.marc...@samsung.com wrote: This commit enables the following configs: - CONFIG_USE_ARCH_MEMCPY - CONFIG_USE_ARCH_MEMSET This increases the performance of memcpy/memset and also reduces the boot time. This was tested on Trats2. A quick test with trace. Boot time from start to main_loop() entry: - ~1527ms - before this change (arch memset enabled for .bss clear) - ~1384ms - after this change Signed-off-by: Przemyslaw Marczak p.marc...@samsung.com Cc: Minkyu Kang mk7.k...@samsung.com Cc: Akshay Saraswat aksha...@samsung.com Cc: Simon Glass s...@chromium.org Cc: Sjoerd Simons sjoerd.sim...@collabora.co.uk --- include/configs/exynos-common.h | 3 +++ 1 file changed, 3 insertions(+) Reviewed-by: Simon Glass s...@chromium.org BTW in case you are interested, in the Chromium U-Boot tree (chromeos-v2013.06 branch) we have exynos support for turning on the cache in SPL and leaving it on through to the end of U-Boot. It runs two SPLs and two U-Boots (with verified boot and kernel verification) in a total of about 750ms. This shipped last year with Pit and Pi (Samsung Chromebook 2). Might be some interesting patches there... Regards, Simon This is very interesting. Some time ago I made some tests witch the cache on/off cases for s-boot(bl1/Bl2 for trats2). Enabling the cache incredible improve the performance. Since it is easy to break the Trats2, such changes in the s-boot has no sense. But it could be easy in the future to modify the bl2 for Odroid. Best regards, -- Przemyslaw Marczak Samsung RD Institute Poland Samsung Electronics p.marc...@samsung.com ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 0/8] arm: a few steps to reduce the boot time
Hello Stephen, On 02/17/2015 11:39 PM, Stephen Warren wrote: On 02/17/2015 02:43 PM, Stephen Warren wrote: On 02/16/2015 08:13 AM, Przemyslaw Marczak wrote: This patchset reduces the boot time for ARM architecture, Exynos boards, and boards with DFU enabled. I tested this series on NVIDIA's Jetson TK1 board. It doesn't seem to introduce any new issues, but I did find a couple have crept in recently: I'm running the following in U-Boot: setenv dfu_alt_info /dfu_test.bin ext4 0 1;/dfudummy.bin ext4 0 1 dfu 0 mmc 0 1) Whenever any file is uploaded through DFU, I see: #File System is consistent file found deleting update journal finished File System is consistent update journal finished 18425346722729591336 bytes written in 4070 ms (3.9 EiB/s) Notice that the byte count is way off (that's from a 4KB file). The byte count is always the same invalid number. I'm not sure if this message comes from the ext4 or DFU code. For the record in this thread, this is fixed by: [PATCH] fs: ext4 write: return file len on success Thank you for testing. I should add the ext4 fix to this patchset, so it will be linked in the next version. Best regards, -- Przemyslaw Marczak Samsung RD Institute Poland Samsung Electronics p.marc...@samsung.com ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH RFC v2 0/6] usb: host: Add driver model support
Hi Simon, On Wed, Feb 18, 2015 at 6:45 PM, Simon Glass s...@chromium.org wrote: +mailing list On 18 February 2015 at 06:14, Simon Glass s...@chromium.org wrote: Hi Vivek, On 18 February 2015 at 03:40, Vivek Gautam gautam.vi...@samsung.com wrote: Hi Marek, Simon, This patch-series comes as a update for an earlier posted series[1] [PATCH RFC 0/2] usb: host: Add a wrapper layer for mutiple host support which was posted long back. We had discussion to introduce the driver model instead of the approach used in [1]. The driver model seems pretty straight-forward and easier to implement besides giving a clean approach to use multiple host controller types, viz. EHCI, XHCI or OHCI simultaneously on a platform which has such provision. It's rather bad on my side that it took so long to post the updated version. Got busy with the projects. :-( So here's the RFC-v2 which implements the driver model approach. I have added support on OHCI, EHCI and XHCI and enabled EHCI and XHCI on Exynos5250 machines. Though not tested thoroughly, i can see EHCI and XHCI working together (enumerating the Root hubs). Let me know you comments on what you think of current approach. Great to see this - will take a look. Did you see my RFC on 30th Jan? E.g. this: sorry i did not check that patch earlier. Thanks for pointing out. https://patchwork.ozlabs.org/patch/434995/ Will take a look at the series. Regards, Simon Thanks Vivek [1] [PATCH RFC 0/2] usb: host: Add a wrapper layer for mutiple host support http://lists.denx.de/pipermail/u-boot/2014-June/182559.html Vivek Gautam (6): usb: Rename usb_submit_int_msg() API to usb_int_msg() dm: usb: Make necessary changes in framework for driver model dm: usb-host: Add UCLASS driver for USB dm: usb-host: Add support for driver model in o/e/xhci. arm: exynos5: Enable EHCI and XHCI hcds through device tree. configs: smdk5250: Enable using XHCI and EHCI together arch/arm/dts/exynos5.dtsi |8 +++ common/usb.c| 101 ++--- common/usb_hub.c|2 +- common/usb_kbd.c|4 +- common/usb_storage.c|2 +- drivers/usb/host/Kconfig|9 +++ drivers/usb/host/Makefile |3 + drivers/usb/host/ehci-hcd.c | 36 +--- drivers/usb/host/ohci-hcd.c | 35 +--- drivers/usb/host/usb-uclass.c | 107 +++ drivers/usb/host/xhci.c | 34 --- include/configs/exynos5-common.h|3 + include/configs/exynos5250-common.h |3 + include/configs/smdk5250.h |2 + include/dm/uclass-id.h |1 + include/usb.h | 62 +++- 16 files changed, 365 insertions(+), 47 deletions(-) create mode 100644 drivers/usb/host/usb-uclass.c -- 1.7.10.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot -- Best Regards Vivek Gautam Samsung RD Institute, Bangalore India ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] please pull u-boot-arc master
Hi Tom, On Wed, 2015-02-18 at 15:35 +0300, Alexey Brodkin wrote: Hi Tom, Could you please pull those changes? Just realized you already pulled my the changes. Probably I missed your reply and was too lazy to check latest changes in U-Boot at say http://git.denx.de/?p=u-boot.git;a=shortlog which I did right now. Sorry for this noise. -Alexey ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
