Hi Marek,
-Original Message-
From: Marek Vasut [mailto:ma...@denx.de]
Sent: Wednesday, April 15, 2015 5:17 PM
To: Michal Simek
Cc: Lukasz Majewski; u-boot@lists.denx.de; Siva Durga Prasad Paladugu; Tom
Rini
Subject: Re: [RESEND PATCH] f_thor: Dont perform reset at the end of thor
On Tue, Apr 14, 2015 at 05:50:50AM +0200, Marek Vasut wrote:
The following changes since commit f33cdaa4c3da4a8fd35aa2f9a3172f31cc887b35:
Prepare v2015.04 (2015-04-13 10:53:03 -0400)
are available in the git repository at:
git://git.denx.de/u-boot-usb.git HEAD
for you to fetch
Add support for Veloce - zynqmp emulation platform.
Platform doesn't support SDHCI.
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
arch/arm/cpu/armv8/zynqmp/clk.c | 3 +++
arch/arm/cpu/armv8/zynqmp/cpu.c | 2 ++
arch/arm/include/asm/arch-zynqmp/hardware.h | 1 +
From: Siva Durga Prasad Paladugu siva.durga.palad...@xilinx.com
Enable the i2c driver for ZynqMP
Also enable the eeprom for read and writes
to eeprom on ZynqMP
ZynqMP uses the same i2c controller as in Zynq
Signed-off-by: Siva Durga Prasad Paladugu siva...@xilinx.com
Signed-off-by: Michal Simek
Hi Michal,
On Wed, Apr 15, 2015 at 5:50 AM, Michal Simek michal.si...@xilinx.com
wrote:
From: Siva Durga Prasad Paladugu siva.durga.palad...@xilinx.com
Based on rfc951 transaction ID has 4 bytes which is not the case when
ulong type is used on ARM64.
Use u32 type which is well defined for
On Wed, Apr 15, 2015 at 12:33:43PM +0200, Kamil Lulko wrote:
2015-04-14 20:07 GMT+02:00 Matt Porter mpor...@konsulko.com:
On ARM v7M, the processor will return to ARM mode when executing
a blx instruction with bit 0 of the address == 0. Always set it
to 1 to stay in thumb mode.
On 04/15/2015 02:35 PM, Marek Vasut wrote:
On Wednesday, April 15, 2015 at 02:03:50 PM, Siva Durga Prasad Paladugu wrote:
Hi Marek,
Hi!
-Original Message-
From: Marek Vasut [mailto:ma...@denx.de]
Sent: Wednesday, April 15, 2015 5:17 PM
To: Michal Simek
Cc: Lukasz Majewski;
Enable SDHCI0 for zynqmp.
Add empty gpio.h because of sdhci requirement.
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
There will be gpio driver anyway that's why it should be fine to add
empty file.
---
arch/arm/include/asm/arch-zynqmp/gpio.h | 12
Add support for EMMC bootmode.
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
arch/arm/include/asm/arch-zynqmp/hardware.h | 3 ++-
board/xilinx/zynqmp/zynqmp.c| 1 +
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git
From: Siva Durga Prasad Paladugu siva.durga.palad...@xilinx.com
Define the mmu table till 2MB granularity
enable dcaches for zynqmp.
Signed-off-by: Siva Durga Prasad Paladugu siva...@xilinx.com
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
arch/arm/cpu/armv8/zynqmp/cpu.c | 164
From: Siva Durga Prasad Paladugu siva.durga.palad...@xilinx.com
Remove the quirk SDHCI_QUIRK_NO_CD as it is not
required.
Signed-off-by: Siva Durga Prasad Paladugu siva...@xilinx.com
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
drivers/mmc/zynq_sdhci.c | 2 +-
1 file changed, 1
On Wed, Apr 15, 2015 at 12:50:59PM +0200, Michal Simek wrote:
From: Siva Durga Prasad Paladugu siva.durga.palad...@xilinx.com
Based on rfc951 transaction ID has 4 bytes which is not the case when
ulong type is used on ARM64.
Use u32 type which is well defined for all archs.
From: Siva Durga Prasad Paladugu siva.durga.palad...@xilinx.com
Added the SPI driver support for ZynqMP
The controller is same as zynq SPI controller
Signed-off-by: Siva Durga Prasad Paladugu siva...@xilinx.com
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
Add support for loading sw for R5 with enabling for zynqmp.
Signed-off-by: Michal Simek michal.si...@xilinx.com
Signed-off-by: Siva Durga Prasad Paladugu siva...@xilinx.com
---
arch/arm/cpu/armv8/zynqmp/Makefile | 1 +
arch/arm/cpu/armv8/zynqmp/mp.c | 242
From: Siva Durga Prasad Paladugu siva.durga.palad...@xilinx.com
Provide an option to write filesystem independend commands.
Signed-off-by: Siva Durga Prasad Paladugu siva...@xilinx.com
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
include/configs/xilinx_zynqmp.h | 5 +++--
1 file
On Tue, Apr 14, 2015 at 10:22:37AM +0200, Lukasz Majewski wrote:
The following changes since commit
7704fdbda3afb3d3bb0749378f444c71f92fb9ca:
usb: gadget: thor: Claim EP after allocating it in thor gadget
(2015-04-14 05:48:12 +0200)
are available in the git repository at:
On Wednesday, April 15, 2015 at 01:43:03 PM, Michal Simek wrote:
From: Siva Durga Prasad Paladugu siva.durga.palad...@xilinx.com
Dont perform reset at the end of thor download
if configured to do reset off.
Reset may not be required in all cases and hence
provided an option to do so.
Hi,
Hi Tom,
On 15 April 2015 at 07:08, Tom Rini tr...@konsulko.com wrote:
On Tue, Apr 14, 2015 at 05:50:50AM +0200, Marek Vasut wrote:
The following changes since commit f33cdaa4c3da4a8fd35aa2f9a3172f31cc887b35:
Prepare v2015.04 (2015-04-13 10:53:03 -0400)
are available in the git
On Wed, Apr 15, 2015 at 07:29:41AM -0600, Simon Glass wrote:
Hi Tom,
On 15 April 2015 at 07:08, Tom Rini tr...@konsulko.com wrote:
On Tue, Apr 14, 2015 at 05:50:50AM +0200, Marek Vasut wrote:
The following changes since commit
f33cdaa4c3da4a8fd35aa2f9a3172f31cc887b35:
On Wednesday, April 15, 2015 at 02:03:50 PM, Siva Durga Prasad Paladugu wrote:
Hi Marek,
Hi!
-Original Message-
From: Marek Vasut [mailto:ma...@denx.de]
Sent: Wednesday, April 15, 2015 5:17 PM
To: Michal Simek
Cc: Lukasz Majewski; u-boot@lists.denx.de; Siva Durga Prasad
On Wed, Apr 15, 2015 at 12:33:00PM +0100, Michal Simek wrote:
From: Siva Durga Prasad Paladugu siva.durga.palad...@xilinx.com
Always disable dcache after the flush operation
The following sequence is advisable while disabling d-cache:
1. disable_dcache() - flushes and disables d-cache
2.
Hi Tom,
Please pull u-boot-sunxi/master into master for the first series of sunxi
patches for v2015.07. This consists of a mix of bug-fixes, improvements
and new boards.
The following changes since commit f33cdaa4c3da4a8fd35aa2f9a3172f31cc887b35:
Prepare v2015.04 (2015-04-13 10:53:03 -0400)
Hi,
On 10-04-15 23:09, Paul Kocialkowski wrote:
Changes since v4:
* Got rid of Kconfig after all
* Only build mvtwsi when at least one controller is enabled on sunxi
* Controller 0 doesn't have to be enabled in particular
Changes since v3:
* Kconfig support for MVTWSI
* Only enable twsi0 by
Did v2015.04 get released?I didn't see a release announcement on this email
list.
The information on the web site about it is inconsistent:
The ReleaseCycle web page (http://www.denx.de/wiki/view/U-Boot/ReleaseCycle)
says this:
- U-Boot v2015.04 was released on Mon, 13 Apr 2015.
- The
Hi,
Thanks I've queued up the entire set into u-boot-sunxi/next, I'm running
some tests now once those are done I'll send a pullreq to get the
current u-boot-sunxi/next merged into master.
p.s. In the future if you add new board defconfig files please add a short
comment block at the top
Hi Michal,
On 14 April 2015 at 16:10, Michal Suchanek hramr...@gmail.com wrote:
Hello,
On 4 March 2015 at 00:46, Simon Glass s...@chromium.org wrote:
Hi Michal,
On 2 March 2015 at 04:25, Michal Suchanek hramr...@gmail.com wrote:
Hello,
On 18 February 2015 at 06:24, Michal Suchanek
On Wed, Apr 15, 2015 at 08:34:30AM -0400, Tom Rini wrote:
On Wed, Apr 15, 2015 at 12:33:43PM +0200, Kamil Lulko wrote:
2015-04-14 20:07 GMT+02:00 Matt Porter mpor...@konsulko.com:
On ARM v7M, the processor will return to ARM mode when executing
a blx instruction with bit 0 of the
Hi Rob,
On Wed, 15 Apr 2015 10:23:24 -0400
Rob Westfall rob.westf...@gmail.com wrote:
Did v2015.04 get released?I didn't see a release announcement on this email
list.
yes, here is the announcement email:
http://lists.denx.de/pipermail/u-boot/2015-April/210765.html
The information on the
On 15 April 2015 at 17:00, Simon Glass s...@chromium.org wrote:
Hi Michal,
On 14 April 2015 at 16:10, Michal Suchanek hramr...@gmail.com wrote:
Hello,
On 4 March 2015 at 00:46, Simon Glass s...@chromium.org wrote:
Hi Michal,
On 2 March 2015 at 04:25, Michal Suchanek hramr...@gmail.com
On 04/15/2015 03:45 PM, Joe Hershberger wrote:
Hi Michal,
On Wed, Apr 15, 2015 at 5:50 AM, Michal Simek michal.si...@xilinx.com
wrote:
From: Siva Durga Prasad Paladugu siva.durga.palad...@xilinx.com
Based on rfc951 transaction ID has 4 bytes which is not the case when
ulong type is used
Hi Michal,
On Wed, Apr 15, 2015 at 6:31 AM, Michal Simek michal.si...@xilinx.com
wrote:
Use phys_addr_t which is used in function prototype
in system.h.
Signed-off-by: Michal Simek michal.si...@xilinx.com
Applied to u-boot-net/next, thanks!
-Joe
On Wednesday, April 15, 2015 at 03:43:37 PM, Tom Rini wrote:
On Wed, Apr 15, 2015 at 07:29:41AM -0600, Simon Glass wrote:
Hi Tom,
On 15 April 2015 at 07:08, Tom Rini tr...@konsulko.com wrote:
On Tue, Apr 14, 2015 at 05:50:50AM +0200, Marek Vasut wrote:
The following changes since
On 04/02/2015 08:54 PM, Marek Vasut wrote:
On Tuesday, March 31, 2015 at 12:01:16 AM, dingu...@opensource.altera.com
wrote:
From: Dinh Nguyen dingu...@opensource.altera.com
This sets the CPU clocks to 925MHz and DDR to 400MHz, and the correct
CONFIG_HPS_MAINPLLGRP_VCO_NUMER should be 79.
Le mercredi 15 avril 2015 à 16:36 +0200, Hans de Goede a écrit :
Hi,
Thanks I've queued up the entire set into u-boot-sunxi/next, I'm running
some tests now once those are done I'll send a pullreq to get the
current u-boot-sunxi/next merged into master.
p.s. In the future if you add new
New QorIQ p1020 based board support from Arcturus Networks Inc.
http://www.arcturusnetworks.com/products/ucp1020/
Signed-off-by: Michael Durrant mdurr...@arcturusnetworks.com
Signed-off-by: Oleksandr G Zhadan ol...@arcturusnetworks.com
---
arch/powerpc/cpu/mpc85xx/Kconfig |4 +
On Wed, 2015-04-15 at 10:45 +0200, Michal Suchanek wrote:
It is not obvious which MACH_SUN?I are ARCH_SUN6I derived. So if you
can come up with a descriptive name for 'a number of things in common,
such as having separate ahb reset registers in the ccm' that's fine
otherwise this obfuscates
On Tue, 2015-04-14 at 18:06 +0200, Hans de Goede wrote:
This is a preparation patch for adding A33 support, which will have a mach
name of sun8i-a33.
And, presumably, differs substantially from sun8i-a23, to the extent it
should likely have been a new sunNi but we are stuck with what AW did,
On Tue, 2015-04-14 at 18:06 +0200, Hans de Goede wrote:
Add support for the new second DRAM PLL found on the A33 SoC.
Signed-off-by: Hans de Goede hdego...@redhat.com
Acked-by: Ian Campbell i...@hellion.org.uk
___
U-Boot mailing list
On Tue, 2015-04-14 at 18:06 +0200, Hans de Goede wrote:
From: Vishnu Patekar vishnupatekar0...@gmail.com
A quick comment on what basic here means, i.e. prcm, rsb, clocks as
per sun6i, etc would be good.
Signed-off-by: Vishnu Patekar vishnupatekar0...@gmail.com
Signed-off-by: Hans de Goede
On Tue, 2015-04-14 at 18:07 +0200, Hans de Goede wrote:
From: Vishnu Patekar vishnupatekar0...@gmail.com
The Astar MID756 is a 7 tablet using the A33 SoC with a 800x480 LCD screen,
512M RAM, 8G ROM and integrated sdio wifi.
Also see: http://linux-sunxi.org/Softwinner_astar-rda
On Tue, 2015-04-14 at 18:07 +0200, Hans de Goede wrote:
Add a defconfig for generic 7 tablets using the Ippo q8h v1.2 pcb,
with an A33 SoC (the pcb can take an A23 or an A33), and a 1024x600 LCD.
Signed-off-by: Hans de Goede hdego...@redhat.com
Acked-by: Ian Campbell i...@hellion.org.uk
On Tue, 2015-04-14 at 18:06 +0200, Hans de Goede wrote:
From: Vishnu Patekar vishnupatekar0...@gmail.com
Based on Allwinner dram init code from the a33 bsp:
https://github.com/allwinner-zh/bootloader/blob/master/basic_loader/bsp/bsp_for_a33/init_dram/mctl_hal.c
Initial u-boot port by
On Tue, 2015-04-14 at 18:06 +0200, Hans de Goede wrote:
For unknown reasons the A33 needs the end of the memory we report to the
kernel to be aligned to a multiple of 4 MiB.
Do you really mean the A33 needs (as in the processor itself) or do
you actually mean the A33 kernel port?
If the latter
1. Include asm/mpc85xx_gpio.h into asm/gpio.h
2. Fix Incompatibility in functions gpio_free() and gpio_set_value()
definitions between asm/mpc85xx_gpio.h and asm-generic/gpio.h
Signed-off-by: Michael Durrant mdurr...@arcturusnetworks.com
Signed-off-by: Oleksandr G Zhadan
On Tue, 2015-04-14 at 18:06 +0200, Hans de Goede wrote:
There is no reason not to and this make the #ifdef-ery easier to read.
Signed-off-by: Hans de Goede hdego...@redhat.com
Acked-by: Ian Campbell ian.campb...@citrix.com
___
U-Boot mailing list
On Tue, 2015-04-14 at 18:06 +0200, Hans de Goede wrote:
We do not use irqs in u-boot so remove the unused irq field, and all the
#ifdef-ery around the irq initialization.
Signed-off-by: Hans de Goede hdego...@redhat.com
Acked-by: Ian Campbell i...@hellion.org.uk
Hi Fabio,
On 04/15/2015 11:57 PM, Fabio Estevam wrote:
From: Fabio Estevam fabio.este...@freescale.com
Add the initial SPL support for HummingBoard-i2eX, which is based on a
MX6 Dual.
For more information about HummingBoard, please check:
http://www.solid-run.com/products/hummingboard/
Based
Hi. I make u-boot for olimex a20-som. I configured it with *_defconfig.
Which options I must add to defconfig for change BOOTDELAY from 2 to
0.(When boot running - it is waiting 2 seconds for press any key. I want
that it isn't waiting press any key.) Or How can I do it othater way.
My
Is it possible to have fat file write support in the Uboot 2009.11 version?
If anybody has faced this issue, give your advise or any patch is available
to this version?
--
View this message in context:
On Wed, Apr 15, 2015 at 05:57:55PM -0300, Fabio Estevam wrote:
From: Fabio Estevam fabio.este...@freescale.com
Add the initial SPL support for HummingBoard-i2eX, which is based on a
MX6 Dual.
For more information about HummingBoard, please check:
From: Dinh Nguyen dingu...@opensource.altera.com
commit 0d13a0051b2c arm: socfpga: Sync Cyclone V DK PLL configuration
mistakenly changed CONFIG_HPS_MAINPLLGRP_VCO_NUMER to 39, the correct
value should be 79.
Signed-off-by: Dinh Nguyen dingu...@opensource.altera.com
---
From: Dinh Nguyen dingu...@opensource.altera.com
Add a stub s_init function in the board file. The reason why the stub function
is needed is that most of the work is now being done in board_init_f(), there
is no need for the SPL to do anything s_init(). However, since lowlevel_init()
is still
From: Dinh Nguyen dingu...@opensource.altera.com
Remap SDRAM to 0x0, and clear OCRAM's ECC in board_init_f().
Signed-off-by: Dinh Nguyen dingu...@opensource.altera.com
Reviewed-by: Marek Vasut ma...@denx.de
---
v4: remove CONFIG_SPL_BUILD and add a comment
v3: Move the code from s_init to
From: Dinh Nguyen dingu...@opensource.altera.com
Hello,
The following 3 patches are updates to SPL patches that Marek has already
applied to his tree. I have split out the DDR driver patches into a separate
patch series to make it more convenient to review.
Thanks,
Dinh Nguyen (3):
arm:
Hi,
On Wed, Apr 15, 2015 at 8:51 PM, Ivan Metla metlai...@gmail.com wrote:
Hi. I make u-boot for olimex a20-som. I configured it with *_defconfig.
Which options I must add to defconfig for change BOOTDELAY from 2 to
0.(When boot running - it is waiting 2 seconds for press any key. I want
that
This C function should be used to do the early memory layout and init. This
is beyond my powers, so just add a TODO for the maintainer.
Signed-off-by: Simon Glass s...@chromium.org
---
arch/microblaze/cpu/start.S | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/microblaze/cpu/start.S
This reverts commit 321f86e18d6aae9f7b7ba3ef1eb0cec769481874.
The original bug has been fixed.
Signed-off-by: Simon Glass s...@chromium.org
---
configs/zynq_microzed_defconfig| 1 -
configs/zynq_zc70x_defconfig | 1 -
configs/zynq_zc770_xm010_defconfig | 1 -
Hi Heiko,
On 04/12/2015 01:19 AM, Heiko Schocher wrote:
make the ldb_clock configurable through the new define
CONFIG_SYS_LDB_CLOCK. This is needed as the ldb clock is not
always 65000, for example on the aristainetos2 board,
where the ldb clock derives from PLL5 clock.
Signed-off-by:
Hi Heiko,
On 04/12/2015 01:19 AM, Heiko Schocher wrote:
the ldb clock can be setup in board code (for example set through PLL5).
Update the ldb_clock rate also through board code.
This should be removed, if a clock framework is availiable.
Any chance you're up to the task?
Searching for
Unfortunately memset() is not always available, so provide a substitute when
needed.
Signed-off-by: Simon Glass s...@chromium.org
---
common/init/global_data.c | 8
1 file changed, 8 insertions(+)
diff --git a/common/init/global_data.c b/common/init/global_data.c
index
Hi Tom,
On Wed, Apr 15, 2015 at 7:35 PM, Tom Rini tr...@konsulko.com wrote:
If you add:
diff --git a/include/configs/mx6cuboxi.h b/include/configs/mx6cuboxi.h
index 7ded5bc..6ba04b2 100644
--- a/include/configs/mx6cuboxi.h
+++ b/include/configs/mx6cuboxi.h
@@ -238,6 +238,7 @@
#ifdef
Hi Nikolay,
On Wed, Apr 15, 2015 at 10:24 PM, Nikolay Dimitrov picmas...@mail.bg wrote:
imx6 supports up to 528 MHz DDR3 clock as per datasheet, which makes
1058 MT/s data rate. Unfortunately such comments (like above) in the
code doesn't help to clarify the differences. Which is a nice way
Hi,
I found a buffer overflow
in console_clear() which result in a system reset in my case.
F
u
nction console_clear_line() uses 2 when calling memsetl.
Function console_scrollup()
uses 2
when calling memcpyl.
Function
video_clear()
uses
/ size(int)
when calling memsetl
This function will be used by both SPL and U-Boot proper. So move it into
a common place.
Signed-off-by: Simon Glass s...@chromium.org
---
Makefile | 1 +
common/board_f.c | 22 +-
common/init/Makefile | 7 +++
common/init/global_data.c |
Adding the code to support early malloc and global data setup to every
arch's assembler start-up is a pain. Also this code is not actually
architecture-specific. We can use common code for all architectures and
with a bit of care we can write this code in C.
This code is now in board_init_f_mem()
Hi Nikolay,
On Wed, Apr 15, 2015 at 8:18 PM, Nikolay Dimitrov picmas...@mail.bg wrote:
This mem_speed (1600) means that the MMDC imx6 code will calculate
timings for 1600 MT/s, but in reality the memory clock will be 528 or
532 MHz. It would be better to override the speed to 1066 to make
Hi Fabio,
On 04/16/2015 03:48 AM, Fabio Estevam wrote:
Hi Nikolay,
On Wed, Apr 15, 2015 at 8:18 PM, Nikolay Dimitrov picmas...@mail.bg wrote:
This mem_speed (1600) means that the MMDC imx6 code will calculate
timings for 1600 MT/s, but in reality the memory clock will be 528 or
532 MHz. It
Hi Mark.
-Original Message-
From: Mark Rutland [mailto:mark.rutl...@arm.com]
Sent: Wednesday, April 15, 2015 6:41 PM
To: Michal Simek
Cc: u-boot@lists.denx.de; Tom Rini; Siva Durga Prasad Paladugu; Varun Sethi;
Arnab Basu; York Sun
Subject: Re: [U-Boot] [PATCH 1/2] armv8: caches:
We can use this C function to do the early memory layout and init.
Signed-off-by: Simon Glass s...@chromium.org
---
arch/arm/lib/crt0.S | 20
1 file changed, 4 insertions(+), 16 deletions(-)
diff --git a/arch/arm/lib/crt0.S b/arch/arm/lib/crt0.S
index 92d3732..871e2b0
We should not init the console this early and there is no need to. If we want
to do early init it can be done in spl_board_init(). Move the
preloader_console_init() call from board_init_f() to board_init_r().
Signed-off-by: Simon Glass s...@chromium.org
---
arch/arm/cpu/armv7/zynq/spl.c | 2 +-
Change the #ifdef so that the early malloc() area is not set up in SPL if
CONFIG_SYS_SPL_MALLOC_START is defined. In that case it would never actually
be used, and just chews up stack space.
Signed-off-by: Simon Glass s...@chromium.org
---
common/init/global_data.c | 3 ++-
1 file changed, 2
This C function should be used to do the early memory layout and init. For
now, add a TODO, as it involves some trickery.
Signed-off-by: Simon Glass s...@chromium.org
---
arch/x86/cpu/start.S | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/x86/cpu/start.S b/arch/x86/cpu/start.S
index
We have plenty of stack space for this little function, but just to be safe,
round the stack pointer down instead of up. This may also reduce confusion
for later readers of the code.
Signed-off-by: Simon Glass s...@chromium.org
---
common/init/global_data.c | 2 +-
1 file changed, 1
We can use this C function to do the early memory layout and init.
Signed-off-by: Simon Glass s...@chromium.org
---
arch/arm/lib/crt0_64.S | 19 ++-
1 file changed, 6 insertions(+), 13 deletions(-)
diff --git a/arch/arm/lib/crt0_64.S b/arch/arm/lib/crt0_64.S
index
Dear Simon Glass,
In message 1429146849-11994-3-git-send-email-...@chromium.org you wrote:
Unfortunately memset() is not always available, so provide a substitute when
needed.
+#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBGENERIC_SUPPORT)
memset((void *)gd, '\0',
From: Fabio Estevam fabio.este...@freescale.com
Add the initial SPL support for HummingBoard-i2eX, which is based on a
MX6 Dual.
For more information about HummingBoard, please check:
http://www.solid-run.com/products/hummingboard/
Based on the work from Jon Nettleton and Rabeeh Khoury.
U-Boot on this board grew a long time ago past the 384 KiB that
it reserves for the U-Boot image, before the environment. Thus,
saveenv overwrites the U-Boot image and bricks the board.
I tried to find out when U-Boot grew beyond this point, but there is a
long stretch in the history where this
From: Dinh Nguyen dingu...@opensource.altera.com
This patch enables the SDRAM controller that is used on Altera's SoCFPGA
family. This patch configures the SDRAM controller based on a configuration
file that is generated from the Quartus tool, sdram_config.h.
Signed-off-by: Dinh Nguyen
From: Dinh Nguyen dingu...@opensource.altera.com
Hello,
The following 2 patches adds the DDR controller driver that is in the Altera
SoCFPGA platform. This driver is needed for the SPL on the platform.
Thanks,
Dinh Nguyen (2):
driver/ddr/altera: Add DDR driver for Altera's SDRAM controller
On 13 April 2015 at 05:03, Bin Meng bmeng...@gmail.com wrote:
The prefix PCH was taken from ivybridge port. However Queensbay
platform official document does not mention PCH. It is composed
of TunnelCreek processor and Topcliff IOH chipset. For accuracy,
avoid using PCH prefix in the macro.
On 13 April 2015 at 05:05, Bin Meng bmeng...@gmail.com wrote:
CONFIG_VIDEO_X86 has been replaced by CONFIG_VIDEO_VESA.
Signed-off-by: Bin Meng bmeng...@gmail.com
---
configs/minnowmax_defconfig | 1 -
1 file changed, 1 deletion(-)
Acked-by: Simon Glass s...@chromium.org
This is only used by Nvidia boards, so move it into nvidia/common to
simplify things.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v6: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
arch/arm/mach-tegra/board.c | 8
board/nvidia/common/board.c | 13
Hello Jörg,
Am 14.04.2015 17:32, schrieb Jörg Krause:
Hello Heiko,
On Di, 2015-04-14 at 10:02 +0200, Heiko Schocher wrote:
Hello Jörg,
Am 14.04.2015 08:29, schrieb Jörg Krause:
Hello Heiko,
On Di, 2015-04-14 at 08:12 +0200, Heiko Schocher wrote:
Hello Jörg,
Am 13.04.2015 22:17, schrieb
The get_pll() function can do the wrong thing if passed values that are
out of range. Add checks for this and add a function which can return
a 'simple' PLL. This can be defined by SoCs with their own clocks.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v6: None
Changes in v4:
Add full link training as a fallback in case the fast link training
fails.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v6:
- Add a comment about tegra_dc_dp_check_sink()
- Improve retry logic in tegra_dc_dp_check_sink()
Changes in v4:
- Rebase on u-boot-dm/next since this series
Instead of CONFIG_VIDEO_TEGRA, use CONFIG_LCD to determine whether an LCD
is present. Tegra124 uses a different driver.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v6: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
include/configs/tegra-common-post.h | 2 +-
1
The name pch_gbe.%x exceeds the limit of the name in the
'struct eth_device'. Rename it as just pch_gbe.
Signed-off-by: Bin Meng bmeng...@gmail.com
---
drivers/net/pch_gbe.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/pch_gbe.c b/drivers/net/pch_gbe.c
index
On Tuesday, April 14, 2015 at 12:18:46 PM, maitysancha...@gmail.com wrote:
Hello,
Hi!
[...]
Yeah. Is the PHY MXS/IMX/VF specific or can that PHY be found even on
other SoCs not manufactured by Freescale ?
This mxs PHY is from SigmaTel, I only see this PHY is used at FSL SoCs,
but
Hi Simon,
On 04/15/2015 05:02 AM, Simon Glass wrote:
(Correcting address for Masahiro)
On 14 April 2015 at 21:00, Simon Glass s...@chromium.org wrote:
Hi,
On 3 February 2015 at 03:08, Michal Simek mon...@monstr.eu wrote:
Hi Simon and Masahiro,
On 02/03/2015 08:32 AM, Masahiro Yamada
On 14 April 2015 at 18:06, Hans de Goede hdego...@redhat.com wrote:
sun6i and newer (derived) SoCs such as the sun8i-a23, sun8i-a33 and sun9i
have a various things in common, like having separate ahb reset control
registers, the SID living inside the pmic, custom pmic busses, new style
On 14 April 2015 at 18:06, Hans de Goede hdego...@redhat.com wrote:
--- a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
+++ b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
@@ -37,7 +37,7 @@
#define SUNXI_MMC1_BASE0x01c1
#define SUNXI_MMC2_BASE
On 14 April 2015 at 08:59, Stephen Warren swar...@wwwdotorg.org wrote:
From: Stephen Warren swar...@nvidia.com
On systems with caches enabled, NAND I/O may need to flush/invalidate
the cache during read/write operations. For this to work correctly, all
buffers must be cache-aligned. Fix
Hello,
On 4 March 2015 at 00:46, Simon Glass s...@chromium.org wrote:
Hi Michal,
On 2 March 2015 at 04:25, Michal Suchanek hramr...@gmail.com wrote:
Hello,
On 18 February 2015 at 06:24, Michal Suchanek hramr...@gmail.com wrote:
On 18 February 2015 at 03:27, Simon Glass s...@chromium.org
On Tue, Apr 14, 2015 at 04:57:04PM +0900, Masahiro Yamada wrote:
With FIT boot, U-boot puts a device tree and an initramdisk at the
tail of the memory.
Some UniPhier boards have a large amount of memory. For those
boards, a device tree and an initramdisk are located out of reach of
the
On 14 April 2015 at 08:41, Stephen Warren swar...@wwwdotorg.org wrote:
From: Stephen Warren swar...@nvidia.com
At the very least when USB keyboard support is enabled, we need to enable
CONFIG_SYS_STDIO_DEREGISTER, so the usb reset is able to re-scan USB
ports and find new devices. Enable it
gpio_get_values_as_int() should return an error if something goes wrong.
Also provide gpio_claim_vector(), a function to request the GPIOs and set
them to input mode. Otherwise callers have to do this themselves.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v6: None
Changes in v4:
Hi Jagan,
On Fri, Mar 6, 2015 at 6:21 PM, Jagan Teki jagannadh.t...@gmail.com wrote:
On 6 March 2015 at 06:30, Bin Meng bmeng...@gmail.com wrote:
Hi Jagan,
On Fri, Mar 6, 2015 at 1:43 AM, Jagan Teki jagannadh.t...@gmail.com wrote:
On 4 March 2015 at 09:02, Bin Meng bmeng...@gmail.com wrote:
This series adds eDP support for nyan-big so that the display works.
Nyan-big is based on tegra124.
Some support is added for new clocks to make this work. The drm_dp_helper.h
file is brought in from Linux since many of the DisplayPort constants are
generic. A very simple uclass is added for
Hi Bin,
On 13 April 2015 at 05:05, Bin Meng bmeng...@gmail.com wrote:
CONFIG_VIDEO_VGA is no longer needed thus remove it.
Signed-off-by: Bin Meng bmeng...@gmail.com
---
README| 6 --
arch/x86/lib/Makefile | 1 -
arch/x86/lib/video.c | 205
Hi Simon,
On Wed, Apr 15, 2015 at 7:35 AM, Simon Glass s...@chromium.org wrote:
Hi Bin,
On 13 April 2015 at 05:05, Bin Meng bmeng...@gmail.com wrote:
CONFIG_VIDEO_VGA is no longer needed thus remove it.
Signed-off-by: Bin Meng bmeng...@gmail.com
---
README| 6 --
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