Hi Stefan,
-Original Message-
From: Stefan Roese [mailto:s...@denx.de]
Sent: Friday, June 12, 2015 5:10 AM
To: Vikas MANOCHA; u-boot@lists.denx.de;
grmo...@opensource.altera.com; dingu...@opensource.altera.com
Subject: Re: [PATCH 0/3] spi: cadence_qspi: sram depth from DT fix for
Hi Wolfgang,
Thanks for the quick reply!
On 06/23/15 16:31, Wolfgang Denk wrote:
Dear Igor,
In message 55894d63@compulab.co.il you wrote:
While running git fsck --full, I've noticed the following:
---cut-
$ git fsck
On Mon, Jun 22, 2015 at 11:17:39AM +0200, Michal Simek wrote:
Use one command for showing overall CPU status than several without
knowing how many cpus is available in the system.
Signed-off-by: Michal Simek michal.si...@xilinx.com
Reviewed-by: Tom Rini tr...@konsulko.com
--
Tom
On Mon, Jun 22, 2015 at 04:15:30PM -0500, Joe Hershberger wrote:
This sets the default commands Kconfig to match
include/config_cmd_default.h commands in the common/Kconfig and removes
them from include/configs.
[snip]
diff --git a/common/Kconfig b/common/Kconfig
index cb14592..2976cd7
Hi Tom,
Please pull this request, few importent feature list on spi-flash front
like data flash and spi flash MTD supports.
thanks!
Jagan.
The following changes since commit c6265f7f3410b5e5763181cdd123a3f6fcd9fd58:
CPCI4052: Remove CONFIG_SYS_LONGHELP (2015-06-18 16:19:00 -0400)
are
Hi Graham,
-Original Message-
From: Graham Moore [mailto:grmo...@opensource.altera.com]
Sent: Tuesday, June 23, 2015 7:37 AM
To: Vikas MANOCHA
Cc: Stefan Roese; u-boot@lists.denx.de; dingu...@opensource.altera.com;
jt...@openedev.com
Subject: Re: [PATCH RESEND 0/7] spi:
-Original Message-
From: Marek Vasut [mailto:ma...@denx.de]
Sent: Tuesday, June 23, 2015 4:30 PM
To: Badola Nikhil-B46172
Cc: u-boot@lists.denx.de
Subject: Re: [PATCH 4/4] include: usb: Map USB controller base addresses for
LS2085A
On Tuesday, June 23, 2015 at 05:48:20 AM, Nikhil
Dear Igor,
In message 55894d63@compulab.co.il you wrote:
While running git fsck --full, I've noticed the following:
---cut-
$ git fsck --full
Checking object directories: 100% (256/256), done.
error in tag
On Tue, Jun 23, 2015 at 08:24:23AM -0400, Vitaly Andrianov wrote:
On 06/18/2015 11:57 AM, Tom Rini wrote:
On Mon, Jun 15, 2015 at 12:42:49PM -0400, Vitaly Andrianov wrote:
On 06/15/2015 10:17 AM, Tom Rini wrote:
On Mon, Jun 15, 2015 at 08:48:01AM -0400, Vitaly Andrianov wrote:
KS2
On Mon, Jun 22, 2015 at 04:15:27PM -0500, Joe Hershberger wrote:
This config defined a CONS_INDEX as a config but did not define it in
any Kconfig, so savedefconfig will delete that entry. Use
CONFIG_SYS_EXTRA_OPTIONS for now until that is added to Kconfig.
Signed-off-by: Joe Hershberger
Hi Anton,
On 23.06.2015 13:23, Bin Meng wrote:
On Tue, Jun 23, 2015 at 5:35 PM, Anton Schubert anton.schub...@gmx.de wrote:
Hello,
we are trying to replace an old marvell uboot on mv78260 with the current
version,
Great. Welcome. :)
but noticed that there doesn't seem to be a driver for
On 06/18/2015 11:57 AM, Tom Rini wrote:
On Mon, Jun 15, 2015 at 12:42:49PM -0400, Vitaly Andrianov wrote:
On 06/15/2015 10:17 AM, Tom Rini wrote:
On Mon, Jun 15, 2015 at 08:48:01AM -0400, Vitaly Andrianov wrote:
KS2 u-boot detects the ddr3a size installed to EVM. The detected size can
be
On Tuesday, June 23, 2015 at 02:37:08 PM, Badola Nikhil wrote:
-Original Message-
From: Marek Vasut [mailto:ma...@denx.de]
Sent: Tuesday, June 23, 2015 4:30 PM
To: Badola Nikhil-B46172
Cc: u-boot@lists.denx.de
Subject: Re: [PATCH 4/4] include: usb: Map USB controller base
Hi guys,
While running git fsck --full, I've noticed the following:
---cut-
$ git fsck --full
Checking object directories: 100% (256/256), done.
error in tag 9bf86baaa3b35b25baa2d664e2f7f6cafad689ee: unterminated header
error in tag
The command:
ethsw [port port_no] learning { [help] | show | auto | disable }
can be used to enable/disable HW learning on a port.
Signed-off-by: Johnson Leung johnson.le...@freescale.com
Signed-off-by: Codrin Ciubotariu codrin.ciubota...@freescale.com
---
Changes for v2:
- removed
This patch set adds several features for VSC9953 L2 Switch:
- VLAN configuration;
- port statistics;
- FDB table operations;
- enable/disable HW learning;
- private/shared VLAN learning.
Also, the parser needed to be changed to allow commands
with optional
At startup, the default configuration should be:
- enable HW learning on all ports (HW default);
- all ports are VLAN aware;
- all ports are members of VLAN 1;
- all ports have Port-based VLAN 1;
- on all ports, the switch is allowed to remove
maximum one VLAN tag,
- on egress, the switch
This patch groups some macros defined for registers and
replaces some magic numbers from vsc9953 with macros. Also,
port and port_nr keywords are replaced with port_no.
Also, in some places, this patch replaces in_le32 and out_le32
with clrbits_le32 and setbits_le32 to reduce the number of code
In order to support multiple commands to configure the VSC9953
L2 Switch, the parser needs to be changed to be more flexible and
to support more complex commands. This patch adds a parser that
searches for defined keywords in the command and calls the proper
function when a match is found. Also,
The new added command:
ethsw [port port_no] statistics { [help] | [clear] }
will print counters like the number of Rx/Tx frames,
number of Rx/Tx bytes, number of Rx/Tx unicast frames, etc.
Signed-off-by: Codrin Ciubotariu codrin.ciubota...@freescale.com
---
Changes for v2:
- removed
The VSC9953 DS reserves a register between vlan_mask and anag_efil
registers.
Signed-off-by: Johnson Leung johnson.le...@freescale.com
---
Changes for v2:
- removed Change-id field;
include/vsc9953.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/vsc9953.h
The new command:
ethsw [port port_no] [vlan vid] fdb
{ [help] | show | flush | { add | del } mac }
Can be used to add and delete FDB entries. Also, the command can be used
to show entries from the FDB tables. When used with [port port_no]
and [vlan vid], only the matching the FDB entries
Signed-off-by: Codrin Ciubotariu codrin.ciubota...@freescale.com
---
Changes for v2:
- fixed the Copyright years from 2014-2015 to 2013, 2015;
- removed Change-id field;
include/vsc9953.h | 11 +++
1 file changed, 3 insertions(+), 8 deletions(-)
diff --git
The new added commands can be used to configure VLANs for a port
on both ingress and egress.
The new commands are:
ethsw [port port_no] pvid { [help] | show | pvid }
- set/show PVID (ingress and egress VLAN tagging) for a port;
ethsw [port port_no] vlan { [help] | show | add vid | del vid }
-
The command:
ethsw [port port_no] ingress filtering
{ [help] | show | enable | disable }
- enable/disable VLAN ingress filtering on port
can be used to enable/disable/show VLAN ingress filtering on a port.
Signed-off-by: Johnson Leung johnson.le...@freescale.com
Signed-off-by: Codrin
The command:
ethsw vlan fdb { [help] | show | shared | private }
- make VLAN learning shared or private
configures the FDB to share the FDB entries learned on multiple VLANs
or to keep them separated. By default, the FBD uses private VLAN
learning.
Signed-off-by: Johnson Leung
On 06/22/2015 06:31 PM, Vikas MANOCHA wrote:
...
The point is if after applying above mentioned patch (...: fix
indirect read/write start address), Read/write are working fine, then
trigger_base value of 0xFFA00_ should also work fine.
Can you please modify the trigger_base value from 0x0
On Tue, Jun 23, 2015 at 07:57:24PM +0800, Chen-Yu Tsai wrote:
The original code was configuring the external pins after enabling
the R_PIO clock, which meant the configuration never made it to
the pin controller the first time in SPL.
Why this was working before is uncertain. Maybe the state
This does not actually help any current arch. For x86 it makes it harder
to call (requires stack) and for ARM it has no effect. Drop it.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v3: None
Changes in v2: None
include/debug_uart.h | 22 ++
1 file changed, 10
This is checking the wrong method. Fix it.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v3: None
Changes in v2: None
drivers/cpu/cpu-uclass.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/cpu/cpu-uclass.c b/drivers/cpu/cpu-uclass.c
index
The SPL device tree size must be minimised to save memory. Only include
properties that are needed by SPL - this is determined by the presence
of the u-boot,dm-pre-reloc property. Also remove a predefined list of
unused properties from the nodes that remain.
Signed-off-by: Simon Glass
The regulator_autoset() function mixes printf() output and PMIC adjustment
code. It provides a boolean to control the output. It is better to avoid
missing logic and output, and this permits a smaller SPL code size. So
split the output into a separate function.
Also rename the function to have a
Provide a driver-model function to look up a GPIO name. Make the standard
function use it.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v3: None
Changes in v2: None
drivers/gpio/gpio-uclass.c | 34 ++
include/asm-generic/gpio.h | 13 +
Add support for a driver which sets up DRAM and can return information about
the amount of RAM available. This is a first step towards moving RAM init
to driver model.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v3: None
Changes in v2: None
drivers/Kconfig | 2 ++
Add a uclass which permits pin multiplexing to be configured for a
particular function. It uses the concept of a peripheral ID to specify
the peripheral to adjust. Typically peripheral IDs are SPI0, SPI1,
MMC0, etc.
The uclass provides two methods:
- get_periph_id() - returns the peripheral ID
Add a few messages to indicate progress and failure.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v3: None
Changes in v2: None
common/spl/spl_mmc.c | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/common/spl/spl_mmc.c b/common/spl/spl_mmc.c
index
Some functions called by mkimage would like to know the output file size.
Initially this is the same as the input file size, but it may be affected by
adding headers, etc.
Add this information to the image parameters.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v3: None
Changes
The device tree provides information about which regulators should be
on at boot, or always on. Use this to set them up automatically.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v3: None
Changes in v2: None
drivers/power/regulator/regulator-uclass.c | 22 ++
This bloats the code size quite a bit and is less useful in SPL where there
is no command line.
Avoid including this code in SPL.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v3: None
Changes in v2: None
lib/Makefile | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff
Add a simple implementaton of register maps, supporting only direct I/O
for now. This can be enhanced later to support buses which have registers,
such as I2C, SPI and PCI.
It allows drivers which can operate with multiple buses to avoid dealing
with the particulars of register access on that
It took a little while to figure this out, so this patch adds documentation
to help the next person who needs to do this.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v3: None
Changes in v2: None
include/dwmmc.h | 18 +-
1 file changed, 17 insertions(+), 1
Hi Simon,
I'm calling spi_chip_select(bus) from set_speed or claim_bus
to get the cs value from sf probe.
Seems like it returns the maximum number as 254, when I debug
further seems like slave_platdata returns NULL
int spi_chip_select(struct udevice *dev)
{
struct dm_spi_slave_platdata
This function can be used for testing to manually request a GPIO for use,
without resorting to the legacy GPIO API.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v3: None
Changes in v2: None
drivers/gpio/gpio-uclass.c | 2 +-
include/asm-generic/gpio.h | 12
2 files
This tool allows us to extract subsets of a device tree file. It is used by
the SPL vuild, which needs to cut down the device tree size for use in
limited memory.
This tool was originally written for libfdt but it has not been accepted
upstream, so for now, include it in U-Boot. Several utilfdt
In SPL it is sometimes useful to be able to obtain a dump of the current
driver model state. Since commands are not available, provide a way to
directly call the functions to output this information.
Adjust the existing commands to use these functions.
Signed-off-by: Simon Glass
In some rare cases it is useful to be able to locate a device given a device
tree node offset. An example is when you have an alias that points to a node
and you want to find the associated device. The device may be SPI, MMC or
something else, but you don't need to know the uclass to find it.
Add
Split out the code in fdtdec which finds a number at the end of a string. It
can be useful in other situations.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v3: None
Changes in v2: None
include/vsprintf.h | 26 ++
lib/fdtdec.c | 14 ++
Many SoCs have a number of system controllers which are dealt with as a
group by a single driver. It is a pain to have to add lots of compatible
strings and/or separate drivers for each. Instead we can identify the
controllers by a number and request the address of the one we want.
Add a simple
Add an spl_init() function that does basic init such that board_init_f() can
use simple malloc(), device tree and driver model. Each one is set up only
if enabled for SPL.
Note: We really should refactor SPL such that there is a single
board_init_f() and rename the existing weak board_init_f()
It is common for system reset to be available at multiple levels in modern
hardware. For example, an SoC may provide a reset option, and a board may
provide its own reset for reasons of security or thoroughness. It is useful
to be able to model this hardware without hard-coding the behaviour in
It is a common requirement to update some PMIC registers. Provide some
simple convenience functions to do this.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v3: None
Changes in v2: None
drivers/power/pmic/pmic-uclass.c | 32
include/power/pmic.h
To reduce unnecessary code size in an uncommon code path, use debug()
where possible(). The driver returns an error which indicates failure.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v3: None
Changes in v2: None
drivers/power/regulator/regulator-uclass.c | 2 +-
1 file
Allow read errors to be diagnosed more easily.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v3: None
Changes in v2: None
drivers/mmc/mmc.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index 4eab274..da47037
Provide access to the dhrystone benchmark command.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v3: None
Changes in v2: None
configs/sandbox_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig
index 31fe2f9..3953ec3
Drystone provides a convenient sanity check that the CPU is running at full
speed. Add this as a command which can be enabled as needed.
Note: I investigated using Coremark for this but there was a license
agreement and I could not work out if it was GPL-compatible.
Signed-off-by: Simon Glass
Property names are stored in a string table. When a node property is
removed, the string table is not updated since other nodes may have a
property with the same name.
Thus it is possible for the string table to build up a number of unused
strings. Add a function to remove these. This works by
Offer to display the available image types in help. Also, rather than
hacking the genimg_get_type_id() function to display a list of types,
do this in the tool. Also, sort the list.
The list of image types is quite long, and hard to discover. Print it out
when we show help information.
These have been sent upstream but not accepted to libfdt. For now, bring
these into U-Boot to enable fdtgrep to operate. We will use fdtgrep to
cut device tree files down for SPL.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v3: None
Changes in v2:
- Add new patch with
U-Boot uses structures for hardware access so it is important that these
structures are correct. Add a way of asserting that a structure member is
at a particular offset. This can be created using the datasheet for the
hardware.
This implementation uses Static_assert() since BUILD_BUG_ON() only
Since we want clk_ops to be used in U-Boot as a whole, rename the Zynq
version until it can be converted to driver model.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v3: None
Changes in v2: None
arch/arm/mach-zynq/clk.c | 6 +++---
1 file changed, 3 insertions(+), 3
Since Rockchip requires 32-bit serial access, add this to the driver.
Refactor a little to make this easier.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v3: None
Changes in v2: None
drivers/serial/ns16550.c | 36 +---
1 file changed, 21
It can be quite confusing with a new platform to figure out why the device
tree cannot be located. Add some debug information for this case.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v3: None
Changes in v2: None
lib/fdtdec.c | 7 +++
1 file changed, 7 insertions(+)
diff
Use the common function to obtain the number from the end of the string,
instead of a local function. Also tweak the position of a debug() statement.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v3:
- Split this series apart from the Rockchip series
Changes in v2: None
This is not user input (i.e. from the command line). It should be possible
to get the case correct and avoid the case-insensitive match. This will
help avoid sloppy device tree setups.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v3: None
Changes in v2: None
This functionality may be useful for setting up regulators early during
boot.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v3: None
Changes in v2: None
scripts/Makefile.spl | 1 +
1 file changed, 1 insertion(+)
diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl
index
As a debug option, add positive confirmation that SPL has completed
execution. This can help with diagnosing the location of unexpected hangs.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v3: None
Changes in v2: None
common/spl/spl.c | 1 +
1 file changed, 1 insertion(+)
diff
Add a simple uclass for LEDs, so that these can be controlled by the device
tree and activated when needed. LEDs are referred to by their label.
This implementation requires a driver for each type of LED (e.g GPIO, I2C).
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v3: None
Add a simple driver which allows use of LEDs attached to GPIOs. The linux
device tree binding is used.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v3: None
Changes in v2: None
doc/device-tree-bindings/leds/leds-gpio.txt | 52 ++
drivers/led/Kconfig
Now that we support driver model in SPL, allow GPIO drivers to be used there
also.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v3: None
Changes in v2: None
drivers/gpio/Makefile | 4
1 file changed, 4 deletions(-)
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
Clocks are an important feature of platforms and have become increasing
complex with time. Most modern SoCs have multiple PLLs and dozens of clock
dividers which distribute clocks to on-chip peripherals.
Some SoC implementations have a clock API which is private to that SoC family,
e.g. Tegra and
Decide when the regulator is set up whether we want to auto-set the voltage
or current. This avoids the complex logic spilling into the processing code.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v3: None
Changes in v2: None
drivers/power/regulator/regulator-uclass.c | 12
Some SoCs want to adjust the input clock to the DWMMC block as a way of
controlling the MMC bus clock. Update the get_mmc_clk() method to support
this.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v3: None
Changes in v2: None
drivers/mmc/dw_mmc.c| 2 +-
We can calculate this. Add code to do this if it is not provided.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v3: None
Changes in v2: None
drivers/mmc/dw_mmc.c | 10 --
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/drivers/mmc/dw_mmc.c
At present printf() skips output if it can see there is no console. This
is really just an optimisation, and is not necessary. Also it is currently
incorrect in some cases. Rather than update the logic, just remove it so
that we don't need to keep it in sync.
Signed-off-by: Simon Glass
Driver-model I2C drivers can be picked up by the linker script rule for
legacy drivers. Change the order to avoid this.
We could make the legacy code depend on !CONFIG_DM_I2C but that is not
necessary and it is good to keep conditions to a minimum.
Signed-off-by: Simon Glass s...@chromium.org
When there is no console ready, allow the debug UART to be used for output.
This makes debugging of early code considerably easier.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v3: None
Changes in v2: None
common/console.c | 19 +++
1 file changed, 19
These bloat the code and cause problems for SPL. Use debug() where possible
and try to return a useful error code instead.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v3: None
Changes in v2: None
drivers/mmc/dw_mmc.c | 21 +++--
1 file changed, 11 insertions(+),
This parameter is named 'seq' but should be named 'of_offset'.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v3: None
Changes in v2: None
drivers/core/device.c | 4 ++--
include/dm/device.h | 2 +-
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git
Enable MMC using driver model in SPL for consistency with U-Boot proper.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v3: None
Changes in v2: None
common/spl/spl_mmc.c | 17 +++--
1 file changed, 15 insertions(+), 2 deletions(-)
diff --git a/common/spl/spl_mmc.c
To avoid bloating SPL code, use debug() where possible in the driver model
core code. The error code is already returned, and can be investigated as
needed.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v3: None
Changes in v2: None
drivers/core/lists.c | 6 +++---
1 file changed,
Add an implementation of RC4. This will be used by Rockchip booting but may
be useful in other situations.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v3: None
Changes in v2: None
include/rc4.h | 21 +
lib/Makefile | 1 +
lib/rc4.c | 49
Several functions in this file should be marked as static. Update them.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v3: None
Changes in v2: None
drivers/spi/spi-uclass.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/spi/spi-uclass.c
Add basic support for MMC, providing a uclass which can set up an MMC
device. This allows MMC drivers to move to using driver model.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v3: None
Changes in v2: None
drivers/mmc/Kconfig | 10 ++
drivers/mmc/Makefile | 2
The original code was configuring the external pins after enabling
the R_PIO clock, which meant the configuration never made it to
the pin controller the first time in SPL.
Why this was working before is uncertain. Maybe the state was left
from a previous boot sequence, or RSB just happened to be
The A33 adds a pinmux function for UART0 in the PB pin group.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/cpu/armv7/sunxi/board.c | 4
arch/arm/include/asm/arch-sunxi/gpio.h | 1 +
2 files changed, 5 insertions(+)
diff --git a/arch/arm/cpu/armv7/sunxi/board.c
Sinlinx SinA33 is a core/daughter board SDK kit from Sinlinx. It has
the A33 SoC, USB host, USB OTG, audio input/output, LCD, camera, SDIO
and GPIO headers.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/dts/Makefile| 3 ++-
board/sunxi/MAINTAINERS | 6 ++
Copy over all the latest dts changes from mripard/sunxi/dt-for-4.2.
This adds a dts file for Sinlinx SinA33 dev board, and the required
changes in the .dtsi files.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/dts/sun8i-a23-a33.dtsi| 10 ++
...sun8i-a33.dtsi =
Hi,
This series adds support for Sinlinx SinA33, an A33 devboard, while
also fixing some things I encountered along the way.
Patch 1 fixes build break when using PORT F UART0. (It seems no one
uses it now that we have LCD support.)
Patch 2 fixes the RSB errors I ran into on my A33 devices.
Commit 487b327 (sunxi: GPIO pin mux hardware-feature-specific function
index defines) renamed all GPIO index defines, but missed the PORT F
UART0 setup functions.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/cpu/armv7/sunxi/board.c | 8
1 file changed, 4 insertions(+), 4
Hi Saket,
Some more comments below.
On Wed, Jun 17, 2015 at 10:25 AM, Saket Sinha saket.sinh...@gmail.com wrote:
This patchset is an initial attempt to support ACPI Tables for qemu-x86
target.
Changes in v2:
Dynamic generation of AML code for DSDT table.
Reading PCI
It needs to flush D-cache before 'mmc read' so that
we can see the right data in DDR. And fix parameter
for invalidate_dcache_range() after 'mmc read'.
Signed-off-by: Yangbo Lu yangbo...@freescale.com
Cc: York Sun york...@freescale.com
---
drivers/mmc/fsl_esdhc.c | 21 +++--
1
Hi,
On 4 June 2015 at 10:32, Joakim Tjernlund joakim.tjernl...@transmode.se wrote:
I have seen btrfs patches for u-boot flying around a year ago or so then
it went silent. Is there any efforts ongoing to add btrfs support to u-boot?
Jocke
I'm not sure. It would be good to get that in - if
Hi Bin,
On 7 June 2015 at 20:15, Bin Meng bmeng...@gmail.com wrote:
Hi Simon,
On Sun, Jun 7, 2015 at 10:50 PM, Simon Glass s...@chromium.org wrote:
This driver should use the x86 PCI configuration functions. Also adjust its
compatible string to something generic (i.e. without a vendor name).
Hi,
On 8 June 2015 at 06:32, Andrew Bradford and...@bradfordembedded.com wrote:
Hi Bin / Simon,
On 06/08 10:57, Bin Meng wrote:
Hi Simon,
On Sun, Jun 7, 2015 at 10:50 PM, Simon Glass s...@chromium.org wrote:
Commit afbbd413a fixed this for non-driver-model. Make sure that the driver
Hi Tom,
On Tue, Jun 23, 2015 at 9:23 AM, Tom Rini tr...@konsulko.com wrote:
On Mon, Jun 22, 2015 at 04:15:27PM -0500, Joe Hershberger wrote:
This config defined a CONS_INDEX as a config but did not define it in
any Kconfig, so savedefconfig will delete that entry. Use
On 7 June 2015 at 08:50, Simon Glass s...@chromium.org wrote:
The sub-bus passed to pciauto_prescan_setup_bridge() is incorrect. Fix it
so that sub-buses are numbered correctly.
Signed-off-by: Simon Glass s...@chromium.org
---
drivers/pci/pci-uclass.c | 2 +-
1 file changed, 1
On 7 June 2015 at 08:50, Simon Glass s...@chromium.org wrote:
Only the PCI controller has access to the PCI region information. Make sure
to use the controller (rather than any attached bridges) when configuring
devices.
This corrects a failure to scan and configure devices when driver model
Hi Tom,
On Tue, Jun 23, 2015 at 9:33 AM, Tom Rini tr...@konsulko.com wrote:
On Mon, Jun 22, 2015 at 04:15:30PM -0500, Joe Hershberger wrote:
This sets the default commands Kconfig to match
include/config_cmd_default.h commands in the common/Kconfig and removes
them from include/configs.
Hi Simon,
On Wed, Jun 24, 2015 at 11:18 AM, Simon Glass s...@chromium.org wrote:
Hi Bin,
On 7 June 2015 at 20:15, Bin Meng bmeng...@gmail.com wrote:
Hi Simon,
On Sun, Jun 7, 2015 at 10:50 PM, Simon Glass s...@chromium.org wrote:
This driver should use the x86 PCI configuration functions.
On 24 June 2015 at 04:59, Simon Glass s...@chromium.org wrote:
Add a SPI driver for the Rockchip RK3288, using driver model. It should work
for other Rockchip SoCs also.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v3: None
Changes in v2: None
drivers/spi/Kconfig | 10
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