Re: [U-Boot] [PATCH 2/4] mmc: dw_mmc: Zap endless timeout

[Alexey Brodkin]

Hi Marek,

On Fri, 2015-09-11 at 13:49 +0200, Marek Vasut wrote:
> On Friday, September 11, 2015 at 09:59:32 AM, Alexey Brodkin wrote:
> > Hi Marek,
> 
> Hi!

> btw Is your mailer totally broken by any chance ?

Hm, I'm not sure what happened but as I may see here
https://patchwork.ozlabs.org/patch/516618/ my message looks good :)

> > It turned out that patch breaks functionality in some cases.
> > For me on every attempt to download something significant (at least I see
> > it on 5/7 Mb files) from SD I'm seeing timeout firing too early.
> > 
> > I added a bit of extra instrumentation to see where time is spent and why.
> 
> Check this patch:
> 
> [PATCH 1/2] mmc: dw_mmc: Increase timeout to 20 seconds
> 
> https://patchwork.ozlabs.org/patch/511899/
> 
> Does it fix things for you ?

Well this might fix my particular test-case, but are you sure there's
no chance for this timeout to be not long enough?

And vice versa why wait 20 seconds if problem has happened on short
transfer? Really wait 20 seconds on boot of say TV-set just because
USB-drive is broken?

So I would say that we need to rely on amount of data to be transferred
instead of having any random number of seconds for all.

-Alexey
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Re: [U-Boot] [PATCH 1/2] nitrogen6x: Fix the error handling in board_eth_init()

[Troy Kisky]

On 9/10/2015 8:53 PM, Fabio Estevam wrote:
> From: Fabio Estevam 
> 
> We should not return 0 on failure, so return a negative error code 
> instead.
> 
> Also centralize the error path so that is easier to follow.
> 
> Cc: Troy Kisky 
> Signed-off-by: Fabio Estevam 
> ---
>  board/boundary/nitrogen6x/nitrogen6x.c | 19 +++
>  1 file changed, 11 insertions(+), 8 deletions(-)

Acked-by: Troy Kisky 
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[U-Boot] [PATCH 4/5] ARM: uniphier: move CONFIG_SUPPORT_CARD_* macros to local file

[Masahiro Yamada]

It is no longer necessary to define CONFIG_SUPPORT_CARD_* globally.
Move them to a C file as local macros.  Also, rename the C file.

Signed-off-by: Masahiro Yamada 
---

 arch/arm/mach-uniphier/Makefile   |  2 +-
 .../{support_card.c => micro-support-card.c}  | 15 +--
 include/configs/uniphier.h| 11 ++-
 3 files changed, 12 insertions(+), 16 deletions(-)
 rename arch/arm/mach-uniphier/{support_card.c => micro-support-card.c} (90%)

diff --git a/arch/arm/mach-uniphier/Makefile b/arch/arm/mach-uniphier/Makefile
index 5f17557..df6a569 100644
--- a/arch/arm/mach-uniphier/Makefile
+++ b/arch/arm/mach-uniphier/Makefile
@@ -29,7 +29,7 @@ endif
 
 obj-y += timer.o
 
-obj-$(CONFIG_MICRO_SUPPORT_CARD) += support_card.o
+obj-$(CONFIG_MICRO_SUPPORT_CARD) += micro-support-card.o
 
 obj-$(CONFIG_MACH_PH1_SLD3)+= ph1-sld3/
 obj-$(CONFIG_MACH_PH1_LD4) += ph1-ld4/
diff --git a/arch/arm/mach-uniphier/support_card.c 
b/arch/arm/mach-uniphier/micro-support-card.c
similarity index 90%
rename from arch/arm/mach-uniphier/support_card.c
rename to arch/arm/mach-uniphier/micro-support-card.c
index e2a8c1f..28dbfca 100644
--- a/arch/arm/mach-uniphier/support_card.c
+++ b/arch/arm/mach-uniphier/micro-support-card.c
@@ -9,10 +9,13 @@
 #include 
 #include 
 
-#define MICRO_SUPPORT_CARD_RESET   \
-   ((CONFIG_SUPPORT_CARD_BASE) + 0x000D0034)
-#define MICRO_SUPPORT_CARD_REVISION\
-   ((CONFIG_SUPPORT_CARD_BASE) + 0x000D00E0)
+#define MICRO_SUPPORT_CARD_BASE0x43f0
+#define SMC911X_BASE   ((MICRO_SUPPORT_CARD_BASE) + 0x0)
+#define LED_BASE   ((MICRO_SUPPORT_CARD_BASE) + 0x9)
+#define NS16550A_BASE  ((MICRO_SUPPORT_CARD_BASE) + 0xb)
+#define MICRO_SUPPORT_CARD_RESET   ((MICRO_SUPPORT_CARD_BASE) + 0xd0034)
+#define MICRO_SUPPORT_CARD_REVISION((MICRO_SUPPORT_CARD_BASE) + 0xd00E0)
+
 /*
  * 0: reset deassert, 1: reset
  *
@@ -60,7 +63,7 @@ void support_card_init(void)
 
 int board_eth_init(bd_t *bis)
 {
-   return smc911x_initialize(0, CONFIG_SMC911X_BASE);
+   return smc911x_initialize(0, SMC911X_BASE);
 }
 #endif
 
@@ -224,5 +227,5 @@ void led_puts(const char *s)
s++;
}
 
-   writel(~val, CONFIG_SUPPORT_CARD_LED_BASE);
+   writel(~val, LED_BASE);
 }
diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h
index a15838b..6405961 100644
--- a/include/configs/uniphier.h
+++ b/include/configs/uniphier.h
@@ -59,14 +59,6 @@
 #define CONFIG_I2C_EEPROM
 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS  10
 
-/*
- * Support card address map
- */
-#define CONFIG_SUPPORT_CARD_BASE   0x43f0
-#define CONFIG_SUPPORT_CARD_ETHER_BASE (CONFIG_SUPPORT_CARD_BASE + 0x)
-#define CONFIG_SUPPORT_CARD_LED_BASE   (CONFIG_SUPPORT_CARD_BASE + 0x0009)
-#define CONFIG_SUPPORT_CARD_UART_BASE  (CONFIG_SUPPORT_CARD_BASE + 0x000b)
-
 #ifdef CONFIG_SYS_NS16550_SERIAL
 #define CONFIG_SYS_NS16550
 #define CONFIG_SYS_NS16550_COM1CONFIG_SUPPORT_CARD_UART_BASE
@@ -81,7 +73,8 @@
 
 #define CONFIG_SMC911X
 
-#define CONFIG_SMC911X_BASECONFIG_SUPPORT_CARD_ETHER_BASE
+/* dummy: referenced by examples/standalone/smc911x_eeprom.c */
+#define CONFIG_SMC911X_BASE0
 #define CONFIG_SMC911X_32_BIT
 
 /*---
-- 
1.9.1

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[U-Boot] [PATCH 2/5] ARM: uniphier: remove useless wrapper functions

[Masahiro Yamada]

The wrapper functions, uniphier_board_*, are just making function
calls complex.  Remove them.

Also, use empty inline functions in case CONFIG_MICRO_SUPPORT_CARD
is disabled, so that prototype checking works.

Signed-off-by: Masahiro Yamada 
---

 arch/arm/mach-uniphier/board_early_init_r.c |  5 ++---
 arch/arm/mach-uniphier/include/mach/board.h | 18 ++
 arch/arm/mach-uniphier/spl.c|  4 ++--
 3 files changed, 10 insertions(+), 17 deletions(-)

diff --git a/arch/arm/mach-uniphier/board_early_init_r.c 
b/arch/arm/mach-uniphier/board_early_init_r.c
index 579fe70..7d4830a 100644
--- a/arch/arm/mach-uniphier/board_early_init_r.c
+++ b/arch/arm/mach-uniphier/board_early_init_r.c
@@ -1,6 +1,5 @@
 /*
- * Copyright (C) 2014 Panasonic Corporation
- *   Author: Masahiro Yamada 
+ * Copyright (C) 2014-2015 Masahiro Yamada 
  *
  * SPDX-License-Identifier:GPL-2.0+
  */
@@ -10,6 +9,6 @@
 
 int board_early_init_r(void)
 {
-   uniphier_board_late_init();
+   support_card_late_init();
return 0;
 }
diff --git a/arch/arm/mach-uniphier/include/mach/board.h 
b/arch/arm/mach-uniphier/include/mach/board.h
index c039d80..5b9af22 100644
--- a/arch/arm/mach-uniphier/include/mach/board.h
+++ b/arch/arm/mach-uniphier/include/mach/board.h
@@ -13,28 +13,22 @@ void support_card_init(void);
 void support_card_late_init(void);
 int check_support_card(void);
 #else
-#define support_card_reset() do {} while (0)
-#define support_card_init()  do {} while (0)
-#define support_card_late_init()  do {} while (0)
-static inline int check_support_card(void)
+static inline void support_card_reset(void)
 {
-   return 0;
 }
-#endif
 
-static inline void uniphier_board_reset(void)
+static inline void support_card_init(void)
 {
-   support_card_reset();
 }
 
-static inline void uniphier_board_init(void)
+static inline void support_card_late_init(void)
 {
-   support_card_init();
 }
 
-static inline void uniphier_board_late_init(void)
+static inline int check_support_card(void)
 {
-   support_card_late_init();
+   return 0;
 }
+#endif
 
 #endif /* ARCH_BOARD_H */
diff --git a/arch/arm/mach-uniphier/spl.c b/arch/arm/mach-uniphier/spl.c
index 78534fc..661d73a 100644
--- a/arch/arm/mach-uniphier/spl.c
+++ b/arch/arm/mach-uniphier/spl.c
@@ -40,11 +40,11 @@ void spl_board_init(void)
 
sg_init();
 
-   uniphier_board_reset();
+   support_card_reset();
 
pll_init();
 
-   uniphier_board_init();
+   support_card_init();
 
led_write(L, 0, , );
 
-- 
1.9.1

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[U-Boot] [PATCH 1/2] tqma6_mba6: Fix the error handling in board_eth_init()

[Fabio Estevam]

From: Fabio Estevam 

We should not return 0 on failure, so return a negative error code 
instead.

Also centralize the error path so that is easier to follow.

Cc: Markus Niebel 
Signed-off-by: Fabio Estevam 
---
 board/tqc/tqma6/tqma6_mba6.c | 20 +++-
 1 file changed, 11 insertions(+), 9 deletions(-)

diff --git a/board/tqc/tqma6/tqma6_mba6.c b/board/tqc/tqma6/tqma6_mba6.c
index 6f4cffd..e58b714 100644
--- a/board/tqc/tqma6/tqma6_mba6.c
+++ b/board/tqc/tqma6/tqma6_mba6.c
@@ -309,24 +309,26 @@ int board_eth_init(bd_t *bis)
 
bus = fec_get_miibus(base, -1);
if (!bus)
-   return 0;
+   return -EINVAL;
/* scan phy */
phydev = phy_find_by_mask(bus, (0xf << CONFIG_FEC_MXC_PHYADDR),
PHY_INTERFACE_MODE_RGMII);
 
if (!phydev) {
-   free(bus);
-   puts("No phy found\n");
-   return 0;
+   ret = -EINVAL;
+   goto free_bus;
}
ret  = fec_probe(bis, -1, base, bus, phydev);
-   if (ret) {
-   puts("FEC MXC: probe failed\n");
-   free(phydev);
-   free(bus);
-   }
+   if (ret)
+   goto free_phydev;
 
return 0;
+
+free_phydev:
+   free(phydev);
+free_bus:
+   free(bus);
+   return ret;
 }
 
 int tqma6_bb_board_early_init_f(void)
-- 
1.9.1

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[U-Boot] [PATCH 2/2] udoo: Fix the error handling in board_eth_init()

[Fabio Estevam]

From: Fabio Estevam 

We should not return 0 on failure, so return a negative error code 
instead.

Also centralize the error path so that is easier to follow.

Signed-off-by: Fabio Estevam 
---
 board/udoo/udoo.c | 19 +++
 1 file changed, 11 insertions(+), 8 deletions(-)

diff --git a/board/udoo/udoo.c b/board/udoo/udoo.c
index a8bd90a..a574a2f 100644
--- a/board/udoo/udoo.c
+++ b/board/udoo/udoo.c
@@ -191,23 +191,26 @@ int board_eth_init(bd_t *bis)
 #ifdef CONFIG_FEC_MXC
bus = fec_get_miibus(base, -1);
if (!bus)
-   return 0;
+   return -EINVAL;
/* scan phy 4,5,6,7 */
phydev = phy_find_by_mask(bus, (0xf << 4), PHY_INTERFACE_MODE_RGMII);
 
if (!phydev) {
-   free(bus);
-   return 0;
+   ret = -EINVAL;
+   goto free_bus;
}
printf("using phy at %d\n", phydev->addr);
ret  = fec_probe(bis, -1, base, bus, phydev);
-   if (ret) {
-   printf("FEC MXC: %s:failed\n", __func__);
-   free(phydev);
-   free(bus);
-   }
+   if (ret)
+   goto free_phydev;
 #endif
return 0;
+
+free_phydev:
+   free(phydev);
+free_bus:
+   free(bus);
+   return ret;
 }
 
 int board_mmc_init(bd_t *bis)
-- 
1.9.1

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[U-Boot] [PATCH v6 5/5] spi: cadence_qspi: get fifo width from device tree

[Vikas Manocha]

Fifo width could be different on different socs, e.g. stv0991 & altera soc
have different fifo width.

Signed-off-by: Vikas Manocha 
---

Changes in v6: none
Changes in v5: none
Changes in v4: alligned to linux device tree binding.
Changes in v3: none
Changes in v2: Rebased to master

 arch/arm/dts/socfpga.dtsi  |1 +
 arch/arm/dts/stv0991.dts   |1 +
 drivers/spi/cadence_qspi.c |1 +
 drivers/spi/cadence_qspi.h |1 +
 drivers/spi/cadence_qspi_apb.c |   24 ++--
 5 files changed, 14 insertions(+), 14 deletions(-)

diff --git a/arch/arm/dts/socfpga.dtsi b/arch/arm/dts/socfpga.dtsi
index 9756544..5f0b0fa 100644
--- a/arch/arm/dts/socfpga.dtsi
+++ b/arch/arm/dts/socfpga.dtsi
@@ -640,6 +640,7 @@
num-cs = <4>;
fifo-depth = <128>;
cdns,trigger-address = <0x>;
+   cdns,fifo-width = <4>;
sram-size = <128>;
bus-num = <2>;
status = "disabled";
diff --git a/arch/arm/dts/stv0991.dts b/arch/arm/dts/stv0991.dts
index 6bc5372..0a88b69 100644
--- a/arch/arm/dts/stv0991.dts
+++ b/arch/arm/dts/stv0991.dts
@@ -34,6 +34,7 @@
clocks = <375>;
sram-size = <256>;
cdns,trigger-address = <0x4000>;
+   cdns,fifo-width = <8>;
status = "okay";
 
flash0: n25q32@0 {
diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c
index c63f583..0430218 100644
--- a/drivers/spi/cadence_qspi.c
+++ b/drivers/spi/cadence_qspi.c
@@ -312,6 +312,7 @@ static int cadence_spi_ofdata_to_platdata(struct udevice 
*bus)
plat->tchsh_ns = fdtdec_get_int(blob, subnode, "tchsh-ns", 20);
plat->tslch_ns = fdtdec_get_int(blob, subnode, "tslch-ns", 20);
plat->sram_size = fdtdec_get_int(blob, node, "sram-size", 128);
+   plat->fifo_width = fdtdec_get_int(blob, node, "cdns,fifo-width", 4);
 
debug("%s: regbase=%p flashbase=%p trigger_base=%p max-frequency=%d 
page-size=%d\n",
  __func__, plat->regbase, plat->flashbase, plat->trigger_base,
diff --git a/drivers/spi/cadence_qspi.h b/drivers/spi/cadence_qspi.h
index 7341339..91f38f1 100644
--- a/drivers/spi/cadence_qspi.h
+++ b/drivers/spi/cadence_qspi.h
@@ -27,6 +27,7 @@ struct cadence_spi_platdata {
u32 tchsh_ns;
u32 tslch_ns;
u32 sram_size;
+   u32 fifo_width;
 };
 
 struct cadence_spi_priv {
diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c
index 2638f00..478b5a0 100644
--- a/drivers/spi/cadence_qspi_apb.c
+++ b/drivers/spi/cadence_qspi_apb.c
@@ -34,8 +34,6 @@
 #define CQSPI_REG_RETRY(1)
 #define CQSPI_POLL_IDLE_RETRY  (3)
 
-#define CQSPI_FIFO_WIDTH   (4)
-
 #define CQSPI_REG_SRAM_THRESHOLD_WORDS (50)
 
 /* Transfer mode */
@@ -48,9 +46,6 @@
 #define CQSPI_DUMMY_CLKS_PER_BYTE  (8)
 #define CQSPI_DUMMY_BYTES_MAX  (4)
 
-
-#define CQSPI_REG_SRAM_FILL_THRESHOLD  \
-   ((CQSPI_REG_SRAM_SIZE_WORD / 2) * CQSPI_FIFO_WIDTH)
 /
  * Controller's configuration and status register (offset from QSPI_BASE)
  /
@@ -214,7 +209,7 @@ static void cadence_qspi_apb_read_fifo_data(void *dest,
 }
 
 static void cadence_qspi_apb_write_fifo_data(const void *dest_ahb_addr,
-   const void *src, unsigned int bytes)
+   const void *src, unsigned int fifo_width, unsigned int bytes)
 {
unsigned int temp = 0;
int i;
@@ -222,11 +217,11 @@ static void cadence_qspi_apb_write_fifo_data(const void 
*dest_ahb_addr,
unsigned int *dest_ptr = (unsigned int *)dest_ahb_addr;
unsigned int *src_ptr = (unsigned int *)src;
 
-   while (remaining >= CQSPI_FIFO_WIDTH) {
-   for (i = CQSPI_FIFO_WIDTH/sizeof(src_ptr) - 1; i >= 0; i--)
+   while (remaining >= fifo_width) {
+   for (i = fifo_width/sizeof(src_ptr) - 1; i >= 0; i--)
writel(*(src_ptr+i), dest_ptr+i);
-   src_ptr += CQSPI_FIFO_WIDTH/sizeof(src_ptr);
-   remaining -= CQSPI_FIFO_WIDTH;
+   src_ptr += fifo_width/sizeof(src_ptr);
+   remaining -= fifo_width;
}
if (remaining) {
/* dangling bytes */
@@ -241,7 +236,7 @@ static void cadence_qspi_apb_write_fifo_data(const void 
*dest_ahb_addr,
 
 /* Read from SRAM FIFO with polling SRAM fill level. */
 static int qspi_read_sram_fifo_poll(const void *reg_base, void *dest_addr,
-   const void *src_addr,  unsigned int num_bytes)
+   const void *src_addr, unsigned int 

[U-Boot] [PATCH v6 3/5] spi: cadence_qspi: fix base trigger address & transfer start address

[Vikas Manocha]

This patch is to separate the base trigger from the read/write transfer start
addresses.

Base trigger register address (0x1c register) corresponds to the address which
should be put on AHB bus to handle indirect transfer triggered before.

To handle indirect transfer we need to issue addresses from (value of 0x1c) to
(value of 0x1c) + 15*4 ("4" corresponds to size of SRAM location).
There are no obstacles in issuing const address just equal to 0x1c. Important
thing to note is that indirect trigger address has nothing in common with your
physical or mapped NOR Flash address.

Transfer read/write start addresses (offset 0x68/0x78)should be programmed with
the absolute flash address to be read/written.

plat->triggerbase is added in device tree for mapped spi flash address.

Signed-off-by: Vikas Manocha 
---

Changes in v6: fixed binding for trigger-address.
Changes in v5: None.
Changes in v4:
- fifo-width & trigger address alligned to linux device tree binding.
- renaming of one parameter moved to separate patch.
- trigger address of socfpga reverted back to 0x0.

Changes in v3: formatted string breaking fixed.
Changes in v2: Rebased to master

 arch/arm/dts/socfpga.dtsi  |1 +
 arch/arm/dts/stv0991.dts   |1 +
 drivers/spi/cadence_qspi.c |9 +
 drivers/spi/cadence_qspi.h |1 +
 drivers/spi/cadence_qspi_apb.c |7 +++
 5 files changed, 11 insertions(+), 8 deletions(-)

diff --git a/arch/arm/dts/socfpga.dtsi b/arch/arm/dts/socfpga.dtsi
index 9b12420..9756544 100644
--- a/arch/arm/dts/socfpga.dtsi
+++ b/arch/arm/dts/socfpga.dtsi
@@ -639,6 +639,7 @@
ext-decoder = <0>;  /* external decoder */
num-cs = <4>;
fifo-depth = <128>;
+   cdns,trigger-address = <0x>;
sram-size = <128>;
bus-num = <2>;
status = "disabled";
diff --git a/arch/arm/dts/stv0991.dts b/arch/arm/dts/stv0991.dts
index fa3fd64..6bc5372 100644
--- a/arch/arm/dts/stv0991.dts
+++ b/arch/arm/dts/stv0991.dts
@@ -33,6 +33,7 @@
<0x4000 0x100>;
clocks = <375>;
sram-size = <256>;
+   cdns,trigger-address = <0x4000>;
status = "okay";
 
flash0: n25q32@0 {
diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c
index 34a0f46..0d1abc8 100644
--- a/drivers/spi/cadence_qspi.c
+++ b/drivers/spi/cadence_qspi.c
@@ -290,6 +290,8 @@ static int cadence_spi_ofdata_to_platdata(struct udevice 
*bus)
 
plat->regbase = (void *)data[0];
plat->ahbbase = (void *)data[2];
+   plat->trigger_base = (u32 *)fdtdec_get_addr(blob, node,
+   "cdns,trigger-address");
 
/* Use 500KHz as a suitable default */
plat->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency",
@@ -311,10 +313,9 @@ static int cadence_spi_ofdata_to_platdata(struct udevice 
*bus)
plat->tslch_ns = fdtdec_get_int(blob, subnode, "tslch-ns", 20);
plat->sram_size = fdtdec_get_int(blob, node, "sram-size", 128);
 
-   debug("%s: regbase=%p ahbbase=%p max-frequency=%d page-size=%d\n",
- __func__, plat->regbase, plat->ahbbase, plat->max_hz,
- plat->page_size);
-
+   debug("%s: regbase=%p ahbbase=%p trigger_base=%p max-frequency=%d 
page-size=%d\n",
+ __func__, plat->regbase, plat->ahbbase, plat->trigger_base,
+ plat->max_hz, plat->page_size);
return 0;
 }
 
diff --git a/drivers/spi/cadence_qspi.h b/drivers/spi/cadence_qspi.h
index 98e57aa..2f1bd92 100644
--- a/drivers/spi/cadence_qspi.h
+++ b/drivers/spi/cadence_qspi.h
@@ -18,6 +18,7 @@ struct cadence_spi_platdata {
unsigned intmax_hz;
void*regbase;
void*ahbbase;
+   void*trigger_base;
 
u32 page_size;
u32 block_size;
diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c
index c5b14c5..8156b2b 100644
--- a/drivers/spi/cadence_qspi_apb.c
+++ b/drivers/spi/cadence_qspi_apb.c
@@ -44,7 +44,6 @@
 #define CQSPI_INST_TYPE_QUAD   (2)
 
 #define CQSPI_STIG_DATA_LEN_MAX(8)
-#define CQSPI_INDIRECTTRIGGER_ADDR_MASK(0xF)
 
 #define CQSPI_DUMMY_CLKS_PER_BYTE  (8)
 #define CQSPI_DUMMY_BYTES_MAX  (4)
@@ -281,7 +280,7 @@ static int qpsi_write_sram_fifo_push(struct 
cadence_spi_platdata *plat,
const void *src_addr, unsigned int num_bytes)
 {
const void *reg_base = plat->regbase;
-   void *dest_addr = plat->ahbbase;
+   void *dest_addr = plat->trigger_base;
unsigned int retry = CQSPI_REG_RETRY;
unsigned int sram_level;
unsigned int 

[U-Boot] [PATCH 5/5] ARM: uniphier: allow to disable CONFIG_MICRO_SUPPORT_CARD

[Masahiro Yamada]

Without this, build fails if CONFIG_MICRO_SUPPORT_CARD is disabled.

Signed-off-by: Masahiro Yamada 
---

 arch/arm/mach-uniphier/spl.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/mach-uniphier/spl.c b/arch/arm/mach-uniphier/spl.c
index 75d2989..2267b13 100644
--- a/arch/arm/mach-uniphier/spl.c
+++ b/arch/arm/mach-uniphier/spl.c
@@ -13,6 +13,10 @@ void __weak bcu_init(void)
 {
 };
 
+void __weak sbc_init(void)
+{
+};
+
 void __weak sg_init(void)
 {
 };
-- 
1.9.1

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[U-Boot] [PATCH 0/5] ARM: uniphier: further cleanup

[Masahiro Yamada]

Masahiro Yamada (5):
  ARM: uniphier: remove unused header file
  ARM: uniphier: remove useless wrapper functions
  ARM: uniphier: refactor LED function
  ARM: uniphier: move CONFIG_SUPPORT_CARD_* macros to local file
  ARM: uniphier: allow to disable CONFIG_MICRO_SUPPORT_CARD

 arch/arm/mach-uniphier/Makefile|   2 +-
 arch/arm/mach-uniphier/board_common.c  |  11 +--
 arch/arm/mach-uniphier/board_early_init_f.c|  10 +--
 arch/arm/mach-uniphier/board_early_init_r.c|   5 +-
 arch/arm/mach-uniphier/include/mach/board.h|  23 +++--
 arch/arm/mach-uniphier/include/mach/led.h  | 100 -
 arch/arm/mach-uniphier/include/mach/platdevice.h   |  24 -
 arch/arm/mach-uniphier/lowlevel_init.S |   1 -
 .../{support_card.c => micro-support-card.c}   |  84 +++--
 arch/arm/mach-uniphier/spl.c   |  24 ++---
 include/configs/uniphier.h |  11 +--
 11 files changed, 116 insertions(+), 179 deletions(-)
 delete mode 100644 arch/arm/mach-uniphier/include/mach/led.h
 delete mode 100644 arch/arm/mach-uniphier/include/mach/platdevice.h
 rename arch/arm/mach-uniphier/{support_card.c => micro-support-card.c} (68%)

-- 
1.9.1

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Re: [U-Boot] [PATCH 1/2] mmc: dw_mmc: Increase timeout to 20 seconds

[Alexey Brodkin]

Hi Marek, Lukasz,

> On Wednesday, September 09, 2015 at 09:01:30 AM, Lukasz Majewski wrote:
> > Hi,
> > 
> > > The commit: d9dbb97be0e4a550457aec5f11afefb446169c90
> > > "mmc: dw_mmc: Zap endless timeout" removed endless loop waiting for
> > > end of dw mmc transfer.
> > > 
> > > For some workloads - dfu test @ Odroid XU3 (sending 8MiB file) -
> > > and SD cards (e.g. MicroSD Kingston 4GiB, Adata 4GiB)
> > > the default timeout is to short.
> > > 
> > > The new value - 20 seconds - takes into account the situation when SD
> > > card triggers internal clean up. Such process may take more than 10
> > > seconds on some cards.
> > > 
> > > Signed-off-by: Lukasz Majewski 
> > > Cc: Marek Vasut 
> > > Cc: Pantelis Antoniou 
> > > Cc: Tom Rini 
> > 
> > Are there any more questions regarding this patch or is it ready for
> > submission as fix for v2015.10?
> 
> No comments, just apply this.
> 
> But this should really be fixed properly in the next MW.
> 
> Best regards,
> Marek Vasut

FWIW I faced similar problem even reading data.
At least on one of my boards reading of ~8Mb file
took ~1.7 seconds and so 1 second timeout was interrupting data
exchange.

So indeed we need to have some dirty hack for upcoming release
like bumping timeout to something really huge but later we
need to fix that problem properly.

I though proper solution would be to set timeout depending of amount
of data to be exchanged... something like take slowest speed of SD/MMC
that is allowed by spec and calculate delay based on how much time it
might take for that slow device and for safety multiply it by say 2.

Now from this thread I see that there're other reasons that might affect
length of at least write operation. In other words it could be
complicated unfortunately.

Still we need to fix regression first with virtually infinite timeout :)
I would even thing that simple revert of Marek's patch may make sense for
now. From both points of view for keeping history clean (compared to
stacked fixes/workarounds) and from removal of regression root cause.

It's not that I like to have infinite loops but given previous
implementation worked fine for people in the previous U-Boot release.

-Alexey
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Re: [U-Boot] [PATCH 1/4 v3] mtd: nand: fsmc: Add BCH4 SW ECC support for SPEAr600

[Scott Wood]

On Fri, 2015-09-11 at 08:23 +0200, Stefan Roese wrote:
> This patch adds support for 4-bit ECC BCH4 for the SPEAr600 SoC. This can
> be used by boards equipped with a NAND chip that requires 4-bit ECC 
> strength.
> The SPEAr600 HW ECC only supports 1-bit ECC strength.
> 
> To enable SW BCH4, you need to specify this in your config header:
> 
> And use the command "nandecc bch4" to select this ECC scheme upon runtime.
> 
> Tested on SPEAr600 x600 board.
> 
> Signed-off-by: Stefan Roese 
> Cc: Scott Wood 
> Acked-by: Viresh Kumar 
> ---
> v3:
> - Don't set .caclulate, .correct, and .bytes for NAND_ECC_SOFT_BCH as this
>   will be done in nand_scan_tail()
> - Set .caclulate back to fsmc_read_hwecc() in the HW case
> - Added comment that this function will only be called on SPEAr platforms,
>   not supporting the BCH8 HW ECC (FSMC_VER8)
> 
> v2:
> - Removed err = 0 initialization as suggested by Viresh
> - Completed the commit text
> - Added Viresh's Acked-by
> 
>  drivers/mtd/nand/fsmc_nand.c | 47 
> 
>  1 file changed, 47 insertions(+)
> 
> diff --git a/drivers/mtd/nand/fsmc_nand.c b/drivers/mtd/nand/fsmc_nand.c
> index 567eff0..fe57b16 100644
> --- a/drivers/mtd/nand/fsmc_nand.c
> +++ b/drivers/mtd/nand/fsmc_nand.c
> @@ -390,6 +390,53 @@ static int fsmc_read_page_hwecc(struct mtd_info *mtd, 
> struct nand_chip *chip,
>   return 0;
>  }
>  
> +#ifndef CONFIG_SPL_BUILD
> +/*
> + * fsmc_nand_switch_ecc - switch the ECC operation between different 
> engines
> + *
> + * @eccstrength  - the number of bits that could be corrected
> + * (1 - HW, 4 - SW BCH4)
> + */
> +int __maybe_unused fsmc_nand_switch_ecc(uint32_t eccstrength)

Why do you need __maybe_unused on a non-static function?

> +{
> + struct nand_chip *nand;
> + struct mtd_info *mtd;
> + int err;
> +
> + /*
> +  * This functions is only called on SPEAr600 platforms, supporting
> +  * 1 bit HW ECC. The BCH8 HW ECC (FSMC_VER8) from the ST-Ericsson
> +  * Nomadik SoC is currently supporting this fsmc_nand_switch_ecc()
> +  * function, as it doesn't need to switch to a different ECC layout.
> +  */
> + mtd = _info[nand_curr_device];
> + nand = mtd->priv;
> +
> + /* Setup the ecc configurations again */
> + if (eccstrength == 1) {
> + nand->ecc.mode = NAND_ECC_HW;
> + nand->ecc.bytes = 3;
> + nand->ecc.strength = 1;
> + nand->ecc.layout = _ecc1_layout;
> + nand->ecc.calculate = fsmc_read_hwecc;
> + nand->ecc.correct = nand_correct_data;
> + } else {
> + /*
> +  * .calculate .correct and .bytes will be set in
> +  * nand_scan_tail()
> +  */
> + nand->ecc.mode = NAND_ECC_SOFT_BCH;
> + nand->ecc.strength = 4;
> + nand->ecc.layout = NULL;
> + }

Even though you say this function will currently not be called on systems 
with BCH8 hardware, it would be good to at least test explicitly for 
eccstrength == 4 and error out if something other than 1 or 4 is requested.

-Scott

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[U-Boot] [PATCH v6 4/5] spi: cadence_qspi: rename ahbbase to flashbase for clarity

[Vikas Manocha]

plat->ahbbase renamed to plat->flashbase for better clarity.

Signed-off-by: Vikas Manocha 
---

Changes in v6: none
Changes in v5: none
Changes in v4: new

 drivers/spi/cadence_qspi.c |8 
 drivers/spi/cadence_qspi.h |4 ++--
 drivers/spi/cadence_qspi_apb.c |4 ++--
 3 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c
index 0d1abc8..c63f583 100644
--- a/drivers/spi/cadence_qspi.c
+++ b/drivers/spi/cadence_qspi.c
@@ -150,7 +150,7 @@ static int cadence_spi_probe(struct udevice *bus)
struct cadence_spi_priv *priv = dev_get_priv(bus);
 
priv->regbase = plat->regbase;
-   priv->ahbbase = plat->ahbbase;
+   priv->flashbase = plat->flashbase;
 
if (!priv->qspi_is_init) {
cadence_qspi_apb_controller_init(plat);
@@ -289,7 +289,7 @@ static int cadence_spi_ofdata_to_platdata(struct udevice 
*bus)
}
 
plat->regbase = (void *)data[0];
-   plat->ahbbase = (void *)data[2];
+   plat->flashbase = (void *)data[2];
plat->trigger_base = (u32 *)fdtdec_get_addr(blob, node,
"cdns,trigger-address");
 
@@ -313,8 +313,8 @@ static int cadence_spi_ofdata_to_platdata(struct udevice 
*bus)
plat->tslch_ns = fdtdec_get_int(blob, subnode, "tslch-ns", 20);
plat->sram_size = fdtdec_get_int(blob, node, "sram-size", 128);
 
-   debug("%s: regbase=%p ahbbase=%p trigger_base=%p max-frequency=%d 
page-size=%d\n",
- __func__, plat->regbase, plat->ahbbase, plat->trigger_base,
+   debug("%s: regbase=%p flashbase=%p trigger_base=%p max-frequency=%d 
page-size=%d\n",
+ __func__, plat->regbase, plat->flashbase, plat->trigger_base,
  plat->max_hz, plat->page_size);
return 0;
 }
diff --git a/drivers/spi/cadence_qspi.h b/drivers/spi/cadence_qspi.h
index 2f1bd92..7341339 100644
--- a/drivers/spi/cadence_qspi.h
+++ b/drivers/spi/cadence_qspi.h
@@ -17,7 +17,7 @@
 struct cadence_spi_platdata {
unsigned intmax_hz;
void*regbase;
-   void*ahbbase;
+   void*flashbase;
void*trigger_base;
 
u32 page_size;
@@ -31,7 +31,7 @@ struct cadence_spi_platdata {
 
 struct cadence_spi_priv {
void*regbase;
-   void*ahbbase;
+   void*flashbase;
size_t  cmd_len;
u8  cmd_buf[32];
size_t  data_len;
diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c
index 8156b2b..2638f00 100644
--- a/drivers/spi/cadence_qspi_apb.c
+++ b/drivers/spi/cadence_qspi_apb.c
@@ -704,7 +704,7 @@ int cadence_qspi_apb_indirect_read_setup(struct 
cadence_spi_platdata *plat,
 
/* Get address */
addr_value = cadence_qspi_apb_cmd2addr([1], addr_bytes);
-   writel((u32)plat->ahbbase + addr_value,
+   writel((u32)plat->flashbase + addr_value,
   plat->regbase + CQSPI_REG_INDIRECTRDSTARTADDR);
 
/* The remaining lenght is dummy bytes. */
@@ -795,7 +795,7 @@ int cadence_qspi_apb_indirect_write_setup(struct 
cadence_spi_platdata *plat,
 
/* Setup write address. */
reg = cadence_qspi_apb_cmd2addr([1], addr_bytes);
-   writel((u32)plat->ahbbase + reg,
+   writel((u32)plat->flashbase + reg,
   plat->regbase + CQSPI_REG_INDIRECTWRSTARTADDR);
 
reg = readl(plat->regbase + CQSPI_REG_SIZE);
-- 
1.7.9.5

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[U-Boot] [PATCH v6 2/5] spi: cadence_qspi: fix indirect read/write start address

[Vikas Manocha]

Indirect read/write start addresses are flash start addresses for indirect read
or write transfers. These should be absolute flash addresses instead of
offsets.

Signed-off-by: Vikas Manocha 
---

Changes in v6: none
Changes in v5: fixed type cast compilation warnings.
Changes in v4: removed extra type casts.
Changes in v3: none
Changes in v2: Rebased to master

 drivers/spi/cadence_qspi_apb.c |6 --
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c
index d377ad1..c5b14c5 100644
--- a/drivers/spi/cadence_qspi_apb.c
+++ b/drivers/spi/cadence_qspi_apb.c
@@ -705,7 +705,8 @@ int cadence_qspi_apb_indirect_read_setup(struct 
cadence_spi_platdata *plat,
 
/* Get address */
addr_value = cadence_qspi_apb_cmd2addr([1], addr_bytes);
-   writel(addr_value, plat->regbase + CQSPI_REG_INDIRECTRDSTARTADDR);
+   writel((u32)plat->ahbbase + addr_value,
+  plat->regbase + CQSPI_REG_INDIRECTRDSTARTADDR);
 
/* The remaining lenght is dummy bytes. */
dummy_bytes = cmdlen - addr_bytes - 1;
@@ -795,7 +796,8 @@ int cadence_qspi_apb_indirect_write_setup(struct 
cadence_spi_platdata *plat,
 
/* Setup write address. */
reg = cadence_qspi_apb_cmd2addr([1], addr_bytes);
-   writel(reg, plat->regbase + CQSPI_REG_INDIRECTWRSTARTADDR);
+   writel((u32)plat->ahbbase + reg,
+  plat->regbase + CQSPI_REG_INDIRECTWRSTARTADDR);
 
reg = readl(plat->regbase + CQSPI_REG_SIZE);
reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
-- 
1.7.9.5

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[U-Boot] [PATCH v6 1/5] spi: cadence_qspi: move trigger base configuration in init

[Vikas Manocha]

No need to configure indirect trigger address for every read/write.

Signed-off-by: Vikas Manocha 
---

Changes in v6: None
Changes in v5: fixed type cast compilation warnings.
Changes in v4: removed extra type casts.
Changes in v3: added commit message & removed extra bracket.
Changes in v2: Rebased to master

 drivers/spi/cadence_qspi_apb.c |9 ++---
 1 file changed, 2 insertions(+), 7 deletions(-)

diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c
index d053407..d377ad1 100644
--- a/drivers/spi/cadence_qspi_apb.c
+++ b/drivers/spi/cadence_qspi_apb.c
@@ -534,6 +534,8 @@ void cadence_qspi_apb_controller_init(struct 
cadence_spi_platdata *plat)
 
/* Indirect mode configurations */
writel((plat->sram_size/2), plat->regbase + CQSPI_REG_SRAMPARTITION);
+   writel((u32)plat->ahbbase & CQSPI_INDIRECTTRIGGER_ADDR_MASK,
+  plat->regbase + CQSPI_REG_INDIRECTTRIGGER);
 
/* Disable all interrupts */
writel(0, plat->regbase + CQSPI_REG_IRQMASK);
@@ -693,10 +695,6 @@ int cadence_qspi_apb_indirect_read_setup(struct 
cadence_spi_platdata *plat,
/* for normal read (only ramtron as of now) */
addr_bytes = cmdlen - 1;
 
-   /* Setup the indirect trigger address */
-   writel(((u32)plat->ahbbase & CQSPI_INDIRECTTRIGGER_ADDR_MASK),
-  plat->regbase + CQSPI_REG_INDIRECTTRIGGER);
-
/* Configure the opcode */
rd_reg = cmdbuf[0] << CQSPI_REG_RD_INSTR_OPCODE_LSB;
 
@@ -790,9 +788,6 @@ int cadence_qspi_apb_indirect_write_setup(struct 
cadence_spi_platdata *plat,
   cmdlen, (unsigned int)cmdbuf);
return -EINVAL;
}
-   /* Setup the indirect trigger address */
-   writel(((u32)plat->ahbbase & CQSPI_INDIRECTTRIGGER_ADDR_MASK),
-  plat->regbase + CQSPI_REG_INDIRECTTRIGGER);
 
/* Configure the opcode */
reg = cmdbuf[0] << CQSPI_REG_WR_INSTR_OPCODE_LSB;
-- 
1.7.9.5

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[U-Boot] [PATCH v6 0/5] spi: cadence_qspi: optimize & fix indirect rd-writes

[Vikas Manocha]

This patchset:
- fixes trigger base & transfer start address register programming. This fix
superseeds the previous patch "spi: cadence_qspi: Fix the indirect ahb trigger
address setting".
- adds support to get fifo width from device tree

Changes in v6:
- fixed binding for trigger-address.

Changes in v5:
- fixed compilation warnings.

Changes in v4:
- fifo-width & trigger address alligned to linux device tree binding.
- removed un-necessary casting.
- renaming of one parameter splitted to separate patch.
- trigger address of socfpga reverted back to 0x0.
- code formatting done to avoid checkpatch CHECKS.

Changes in v3:
- removed two patches which were bypassing the sram level check.
- format string in patch corrected 3/4
- added commit message in patch 1/4

Changes in v2:
- rebased to master.
- removed patch "spi: cadence_qspi: read can be independent of fifo width", it
  was implemented in other patchset, in mainline now.

Vikas Manocha (5):
  spi: cadence_qspi: move trigger base configuration in init
  spi: cadence_qspi: fix indirect read/write start address
  spi: cadence_qspi: fix base trigger address & transfer start address
  spi: cadence_qspi: rename ahbbase to flashbase for clarity
  spi: cadence_qspi: get fifo width from device tree

 arch/arm/dts/socfpga.dtsi  |2 ++
 arch/arm/dts/stv0991.dts   |2 ++
 drivers/spi/cadence_qspi.c |   14 --
 drivers/spi/cadence_qspi.h |6 --
 drivers/spi/cadence_qspi_apb.c |   42 
 5 files changed, 33 insertions(+), 33 deletions(-)

-- 
1.7.9.5

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Re: [U-Boot] [PATCH] fat: handle paths that include ../

[Stephen Warren]

On 09/10/2015 03:26 PM, Tom Rini wrote:
> On Thu, Sep 10, 2015 at 10:22:35AM -0700, Stephen Warren wrote:
>> On 07/28/2015 08:55 PM, Stephen Warren wrote:
>>> The FAT code contains a special case to parse the root
>>> directory. This is needed since the root directory
>>> location/layout on disk is special cased for FAT12/16. In
>>> particular, the location and size of the FAT12/16 root
>>> directory is hard-coded and contiguous, whereas all FAT12/16
>>> non-root directories, and all FAT32 directories, are stored in
>>> a non-contiguous fashion, with the layout represented by a
>>> linked-list of clusters in the FAT.
>>> 
>>> If a file path contains ../ (for example
>>> /extlinux/../bcm2835-rpi-cm.dtb), it is possible to need to
>>> parse the root directory for the first element in the path
>>> (requiring application of the special case), then a sub- 
>>> directory (in the general way), then re-parse the root
>>> directory (again requiring the special case). However, the
>>> current code in U-Boot only applies the special case for the
>>> very first path element, and never for any later path element.
>>> When reparsing the root directory without applying the special
>>> case, any file in a sector (or cluster?) other than the first
>>> sector/cluster of the root directory will not be found.
>>> 
>>> This change modifies the non-root-dir-parsing loop of
>>> do_fat_read_at() to detect if it's walked back to the root
>>> directory, and if so, jumps back to the special case code that
>>> handles parsing of the root directory.
>> 
>> Is this change slated for v2015.10, or is the plan to leave this
>> issue in place until the FAT implementation replacement is
>> accepted for the release after that?
> 
> I believe I shall grab this.  Did you see the email from Lukasz
> saying the new FAT didn't pass the DFU test suite?

Yes. I'll try testing that when I get back from travel.
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Re: [U-Boot] [PATCH] dm: core: Enable optional use of fdt_translate_address()

[Stefan Roese]

Hi Simon,

On 11.09.2015 02:42, Simon Glass wrote:

On Thursday, 3 September 2015, Stefan Roese  wrote:



The current "simple" address translation simple_bus_translate() is not
working on some platforms (e.g. MVEBU). As here more complex "ranges"
properties are used in many nodes (multiple tuples etc). This patch
enables the optional use of the common fdt_translate_address() function
which handles this translation correctly.

Signed-off-by: Stefan Roese 
Cc: Simon Glass 
Cc: Bin Meng 
Cc: Marek Vasut 
Cc: Masahiro Yamada 
---
v2:
- Rework code a bit as suggested by Simon. Also added some comments
to make the use of the code paths more clear.




While this works I'm reluctant to commit it as is. The call to
fdt_parent_offset() is very slow.



You've mentioned this before. But how slow could this function really be?


It scans the tree from the start. There is no back link.


And it should not be called that often via dev_get_addr(). Usually only once
for each driver in the probe function. Or am I missing something?


Sounds correct.


So it really shouldn't make a big difference.




I wonder if this code should be copied into a new file in
drivers/core/, tidied up and updated to use dev->parent?



You mean fdt_translate_address()? It references many functions from
fdt_support.c though which we would need to duplicate here as well.



Right. Seems like a pain.


Other options:
- Add a library to unflatten the tree - but this would not be very
useful in SPL or before relocation due to memory/speed constraints
- Add a helper to find a node parent which uses a cached tree scan to
build a table of previous nodes (or some other means to go backwards
in the tree)
- Worry about it later and go ahead with this patch



I see no problems to defer this patch (or a "better" version of it) to after
this release. The Marvell mvebu DM patches are also not targeted for this
release.


OK - and if the time slowdown is not too large then we can just use
this patch, particularly as it is an optional CONFIG. Can you check
how much slower it is to use your new case versus the original code?


Marvell MVEBU won't boot without this option enabled. So I can't really 
compare it here. Someone with a platform that doesn't need this option 
enabled can definitely better do this test and compare the results.


Thanks,
Stefan

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Re: [U-Boot] [PATCH 1/4 v2] mtd: nand: fsmc: Add BCH4 SW ECC support for SPEAr600

[Stefan Roese]

Hi Scott,

On 11.09.2015 00:31, Scott Wood wrote:

On Wed, 2015-09-02 at 14:29 +0200, Stefan Roese wrote:

This patch adds support for 4-bit ECC BCH4 for the SPEAr600 SoC. This can
be used by boards equipped with a NAND chip that requires 4-bit ECC
strength.
The SPEAr600 HW ECC only supports 1-bit ECC strength.

To enable SW BCH4, you need to specify this in your config header:

#define CONFIG_NAND_ECC_BCH
#define CONFIG_BCH

And use the command "nandecc bch4" to select this ECC scheme upon runtime.

Tested on SPEAr600 x600 board.

Signed-off-by: Stefan Roese 
Cc: Scott Wood 
Acked-by: Viresh Kumar 
---
v2:
- Removed err = 0 initialization as suggested by Viresh
- Completed the commit text
- Added Viresh's Acked-by

  drivers/mtd/nand/fsmc_nand.c | 40 
  1 file changed, 40 insertions(+)

diff --git a/drivers/mtd/nand/fsmc_nand.c b/drivers/mtd/nand/fsmc_nand.c
index 567eff0..0976a67 100644
--- a/drivers/mtd/nand/fsmc_nand.c
+++ b/drivers/mtd/nand/fsmc_nand.c
@@ -13,6 +13,7 @@
  #include 
  #include 
  #include 
+#include 
  #include 
  #include 
  #include 
@@ -390,6 +391,45 @@ static int fsmc_read_page_hwecc(struct mtd_info *mtd,
struct nand_chip *chip,
   return 0;
  }

+#ifndef CONFIG_SPL_BUILD
+/*
+ * fsmc_nand_switch_ecc - switch the ECC operation between different
engines
+ *
+ * @eccstrength  - the number of bits that could be corrected
+ * (1 - HW, 4 - SW BCH4)
+ */
+int __maybe_unused fsmc_nand_switch_ecc(uint32_t eccstrength)


What calls this function?  You didn't CC me on the rest of the patchset...
I'm guessing it's a copy-and-paste of what arch/arm/cpu/armv7/omap3/board.c
does?


Yes.


+{
+ struct nand_chip *nand;
+ struct mtd_info *mtd;
+ int err;
+
+ mtd = _info[nand_curr_device];
+ nand = mtd->priv;
+
+ /* Setup the ecc configurations again */
+ if (eccstrength == 1) {
+ nand->ecc.mode = NAND_ECC_HW;
+ nand->ecc.bytes = 3;
+ nand->ecc.strength = 1;
+ nand->ecc.layout = _ecc1_layout;
+ nand->ecc.correct = nand_correct_data;
+ } else {
+ nand->ecc.mode = NAND_ECC_SOFT_BCH;
+ nand->ecc.calculate = nand_bch_calculate_ecc;
+ nand->ecc.correct = nand_bch_correct_data;
+ nand->ecc.bytes = 7;
+ nand->ecc.strength = 4;
+ nand->ecc.layout = NULL;
+ }


nand_scan_tail() should already set .caclulate, .correct, and .bytes for
NAND_ECC_SOFT_BCH.


Yes, thanks for pointing this out.


When switching from BCH to HW, how does .calculate get set back to
fsmc_read_hwecc?


Probably not at all. I must have missed testing this.


What stops this from being called with FSMC_VER8 which appears to have BCH8
hw ecc?


This function will not be called by any platform that supports FSMC_VER8 
- only from SPEArxxx. Which unfortunately only supports 1 bit HW ECC. I 
could add a comment to make this clear.


Thanks,
Stefan

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[U-Boot] [PATCH 2/2] ot1200: Fix the error handling in board_eth_init()

[Fabio Estevam]

From: Fabio Estevam 

We should not return 0 on failure, so return a negative error code 
instead.

Also centralize the error path so that is easier to follow.

Cc: Christian Gmeiner 
Signed-off-by: Fabio Estevam 
---
 board/bachmann/ot1200/ot1200.c | 20 
 1 file changed, 12 insertions(+), 8 deletions(-)

diff --git a/board/bachmann/ot1200/ot1200.c b/board/bachmann/ot1200/ot1200.c
index 2237b7a..eeced79 100644
--- a/board/bachmann/ot1200/ot1200.c
+++ b/board/bachmann/ot1200/ot1200.c
@@ -305,13 +305,13 @@ int board_eth_init(bd_t *bis)
 
bus = fec_get_miibus(base, -1);
if (!bus)
-   return 0;
+   return -EINVAL;
 
/* scan phy 0 and 5 */
phydev = phy_find_by_mask(bus, 0x21, PHY_INTERFACE_MODE_RGMII);
if (!phydev) {
-   free(bus);
-   return 0;
+   ret = -EINVAL;
+   goto free_bus;
}
 
/* depending on the phy address we can detect our board version */
@@ -322,12 +322,16 @@ int board_eth_init(bd_t *bis)
 
printf("using phy at %d\n", phydev->addr);
ret = fec_probe(bis, -1, base, bus, phydev);
-   if (ret) {
-   printf("FEC MXC: %s:failed\n", __func__);
-   free(phydev);
-   free(bus);
-   }
+   if (ret)
+   goto free_phydev;
+
return 0;
+
+free_phydev:
+   free(phydev);
+free_bus:
+   free(bus);
+   return ret;
 }
 
 int board_init(void)
-- 
1.9.1

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Re: [U-Boot] [PATCH 1/5] net: mdio: Add mdio_free() and mdio_unregister() API

[Joe Hershberger]

On Fri, Sep 4, 2015 at 9:53 AM, Bin Meng  wrote:
> Currently there is no API to uninitialize mdio. Add two APIs for this.
>
> Signed-off-by: Bin Meng 

Acked-by: Joe Hershberger 
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[U-Boot] [PATCH 1/4 v3] mtd: nand: fsmc: Add BCH4 SW ECC support for SPEAr600

[Stefan Roese]

This patch adds support for 4-bit ECC BCH4 for the SPEAr600 SoC. This can
be used by boards equipped with a NAND chip that requires 4-bit ECC strength.
The SPEAr600 HW ECC only supports 1-bit ECC strength.

To enable SW BCH4, you need to specify this in your config header:

And use the command "nandecc bch4" to select this ECC scheme upon runtime.

Tested on SPEAr600 x600 board.

Signed-off-by: Stefan Roese 
Cc: Scott Wood 
Acked-by: Viresh Kumar 
---
v3:
- Don't set .caclulate, .correct, and .bytes for NAND_ECC_SOFT_BCH as this
  will be done in nand_scan_tail()
- Set .caclulate back to fsmc_read_hwecc() in the HW case
- Added comment that this function will only be called on SPEAr platforms,
  not supporting the BCH8 HW ECC (FSMC_VER8)

v2:
- Removed err = 0 initialization as suggested by Viresh
- Completed the commit text
- Added Viresh's Acked-by

 drivers/mtd/nand/fsmc_nand.c | 47 
 1 file changed, 47 insertions(+)

diff --git a/drivers/mtd/nand/fsmc_nand.c b/drivers/mtd/nand/fsmc_nand.c
index 567eff0..fe57b16 100644
--- a/drivers/mtd/nand/fsmc_nand.c
+++ b/drivers/mtd/nand/fsmc_nand.c
@@ -390,6 +390,53 @@ static int fsmc_read_page_hwecc(struct mtd_info *mtd, 
struct nand_chip *chip,
return 0;
 }
 
+#ifndef CONFIG_SPL_BUILD
+/*
+ * fsmc_nand_switch_ecc - switch the ECC operation between different engines
+ *
+ * @eccstrength- the number of bits that could be corrected
+ *   (1 - HW, 4 - SW BCH4)
+ */
+int __maybe_unused fsmc_nand_switch_ecc(uint32_t eccstrength)
+{
+   struct nand_chip *nand;
+   struct mtd_info *mtd;
+   int err;
+
+   /*
+* This functions is only called on SPEAr600 platforms, supporting
+* 1 bit HW ECC. The BCH8 HW ECC (FSMC_VER8) from the ST-Ericsson
+* Nomadik SoC is currently supporting this fsmc_nand_switch_ecc()
+* function, as it doesn't need to switch to a different ECC layout.
+*/
+   mtd = _info[nand_curr_device];
+   nand = mtd->priv;
+
+   /* Setup the ecc configurations again */
+   if (eccstrength == 1) {
+   nand->ecc.mode = NAND_ECC_HW;
+   nand->ecc.bytes = 3;
+   nand->ecc.strength = 1;
+   nand->ecc.layout = _ecc1_layout;
+   nand->ecc.calculate = fsmc_read_hwecc;
+   nand->ecc.correct = nand_correct_data;
+   } else {
+   /*
+* .calculate .correct and .bytes will be set in
+* nand_scan_tail()
+*/
+   nand->ecc.mode = NAND_ECC_SOFT_BCH;
+   nand->ecc.strength = 4;
+   nand->ecc.layout = NULL;
+   }
+
+   /* Update NAND handling after ECC mode switch */
+   err = nand_scan_tail(mtd);
+
+   return err;
+}
+#endif /* CONFIG_SPL_BUILD */
+
 int fsmc_nand_init(struct nand_chip *nand)
 {
static int chip_nr;
-- 
2.5.1

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Re: [U-Boot] Please pull u-boot-x86.git

[Tom Rini]

On Thu, Sep 10, 2015 at 03:50:36PM -0700, Simon Glass wrote:

> Hi Tom,
> 
> Here are a few more driver model PCI fixes, the tftp revert and some
> driver model conversions for x86, as well as a few other minor fixes.
> There are a few more patches in flight but I could not apply them due
> to problems. I thought it best to get this out in the interim since
> the hour is late.
> 
> 
> The following changes since commit efde6a579fe3c172d214fb3047b02c827779738a:
> 
>   Prepare v2015.10-rc3 (2015-09-07 08:56:35 -0400)
> 
> are available in the git repository at:
> 
>   git://git.denx.de/u-boot-x86.git
> 
> for you to fetch changes up to f0dc73c090317c7d0660443bc933d612a4c0c699:
> 
>   net: designware: Fix build warnings (2015-09-09 07:48:03 -0600)
> 

Applied to u-boot/master, thanks!

-- 
Tom


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[U-Boot] [PATCH 1/2] nitrogen6x: Fix the error handling in board_eth_init()

[Fabio Estevam]

From: Fabio Estevam 

We should not return 0 on failure, so return a negative error code 
instead.

Also centralize the error path so that is easier to follow.

Cc: Troy Kisky 
Signed-off-by: Fabio Estevam 
---
 board/boundary/nitrogen6x/nitrogen6x.c | 19 +++
 1 file changed, 11 insertions(+), 8 deletions(-)

diff --git a/board/boundary/nitrogen6x/nitrogen6x.c 
b/board/boundary/nitrogen6x/nitrogen6x.c
index d46b8db..104d71f 100644
--- a/board/boundary/nitrogen6x/nitrogen6x.c
+++ b/board/boundary/nitrogen6x/nitrogen6x.c
@@ -387,20 +387,17 @@ int board_eth_init(bd_t *bis)
 #ifdef CONFIG_FEC_MXC
bus = fec_get_miibus(base, -1);
if (!bus)
-   return 0;
+   return -EINVAL;
/* scan phy 4,5,6,7 */
phydev = phy_find_by_mask(bus, (0xf << 4), PHY_INTERFACE_MODE_RGMII);
if (!phydev) {
-   free(bus);
-   return 0;
+   ret = -EINVAL;
+   goto free_bus;
}
printf("using phy at %d\n", phydev->addr);
ret  = fec_probe(bis, -1, base, bus, phydev);
-   if (ret) {
-   printf("FEC MXC: %s:failed\n", __func__);
-   free(phydev);
-   free(bus);
-   }
+   if (ret)
+   goto free_phydev;
 #endif
 
 #ifdef CONFIG_CI_UDC
@@ -408,6 +405,12 @@ int board_eth_init(bd_t *bis)
usb_eth_initialize(bis);
 #endif
return 0;
+
+free_phydev:
+   free(phydev);
+free_bus:
+   free(bus);
+   return ret;
 }
 
 static void setup_buttons(void)
-- 
1.9.1

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Re: [U-Boot] [PATCH v3 3/5] spi: cadence_qspi: Ensure check for max frequency in place

[Pavel Machek]

On Thu 2015-09-10 00:01:42, Chin Liang See wrote:
> Ensure the intended SCLK frequency not exceeding the maximum
> frequency. If that happen, SCLK will set to maximum frequency.

-> that happens, SCLK will be set to the maximum frequency.

Acked-by: Pavel Machek 

-- 
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(cesky, pictures) 
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Re: [U-Boot] [U-Boot,v3] arm, at91: add axm extensions

[Andreas Bießmann]

Dear Heiko Schocher,

Heiko Schocher  writes:
>add extensions for the axm board:
>- power on LED on power up
>- press both recovery buttons on power up to enter
>  recovery mode
>- detect 64 MiB and 128 MiB ramsize
>- PHY rest at reboot because of ATMEL bug
>- use siemens update concept
>- add axm default environment
>- set CONFIG_SPL_MAX_SIZE to 15k
>
>Signed-off-by: Heiko Schocher 
>---
>
>Changes in v3:
>- add comments from Andreas Biessmann:
>  - remove compile error
>
>Changes in v2:
>- add comments from Andreas Biessmann:
>  - set stack into second sram segment
>  - fix some Coding Style issues
>  - reworked "suspect code indent" warning
>  - reworked update concept
>  - rebase against 0d339cf9a969f0c249713d3697e735184f1bd955
>
> board/siemens/taurus/taurus.c | 196 ++
> include/configs/taurus.h  |  71 ++-
> 2 files changed, 249 insertions(+), 18 deletions(-)

applied to u-boot-atmel/master, thanks!

Best regards,
Andreas Bießmann
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Re: [U-Boot] [U-Boot,v3,1/2] at91: corvus: board updates

[Andreas Bießmann]

Dear Heiko Schocher,

Heiko Schocher  writes:
>- rename at91_spl_board_init into spl_board_init
>- use SZ_1X defines for sizes
>
>Signed-off-by: Heiko Schocher 
>---
>
>Changes in v3:
>- add cover letter and post this patch in a patchserie
>  with the DFU support
>
>Changes in v2:
>- rebase to 0d339cf9a969f0c249713d3697e735184f1bd955
>- use SZ_xM defines as Lukasz Majewski suggested
>
> board/siemens/corvus/board.c |  2 +-
> include/configs/corvus.h | 20 +++-
> 2 files changed, 12 insertions(+), 10 deletions(-)

applied to u-boot-atmel/master, thanks!

Best regards,
Andreas Bießmann
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Re: [U-Boot] [U-Boot,v3] taurus: board updates

[Andreas Bießmann]

Dear Heiko Schocher,

Heiko Schocher  writes:
>taurus changes:
>- rename at91_spl_board_init to spl_board_init
>  fixes problems with recovery button and nand erase sector 0
>- adapt CONFIG_SPL_MAX_SIZE and CONFIG_SPL_BSS_MAX_SIZE
>- add CONFIG_AT91_HW_WDT_TIMEOUT 15
>- CONFIG_SF_DEFAULT_MODE SPI_MODE_3 not mode 0
>
>Signed-off-by: Heiko Schocher 
>---
>
>Changes in v3:
>- use SZ_X defines for sizes
>
>Changes in v2:
>- add comments from Andreas Biessmann:
>  - rebase to 0d339cf9a969f0c249713d3697e735184f1bd955
>
> board/siemens/taurus/taurus.c |  6 +++---
> include/configs/taurus.h  | 21 +++--
> 2 files changed, 14 insertions(+), 13 deletions(-)

applied to u-boot-atmel/master, thanks!

Best regards,
Andreas Bießmann
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Re: [U-Boot] [U-Boot,v3,2/2] corvus, dfu: add dfu support

[Andreas Bießmann]

Dear Heiko Schocher,

Heiko Schocher  writes:
>add support for DFU on the corvus board.
>
>Signed-off-by: Heiko Schocher 
>---
>
>Changes in v3:
>- add a cover letter and post this patch with the board
>  updates patch in a patchserie
>
>Changes in v2:
>- rebase to 0d339cf9a969f0c249713d3697e735184f1bd955
>- fix changes introduced through commit:
>  01acd6abbdd5: usb: USB download gadget and functions config options coherent 
> naming
>
> board/siemens/corvus/board.c | 21 +
> include/configs/corvus.h | 26 +-
> 2 files changed, 46 insertions(+), 1 deletion(-)

applied to u-boot-atmel/master, thanks!

Best regards,
Andreas Bießmann
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[U-Boot] [PULL] u-boot-atmel/master -> u-boot/master

[Andreas Bießmann]

Hi Tom,

hopefully the last pull request for 2015.10 from atmel side. It finally
contains a fix for two siemens boards (axm, taurus) for SPL size check, a DFU
series for armv5 at91 devices acked by Łukasz Majewski and some trivial fixes.

The following changes since commit f0dc73c090317c7d0660443bc933d612a4c0c699:

  net: designware: Fix build warnings (2015-09-09 07:48:03 -0600)

are available in the git repository at:

  git://git.denx.de/u-boot-atmel.git master

for you to fetch changes up to e8b81eef4499c32b11d5f120171f39f67db0db59:

  at91, taurus, smartweb: add dfu support (2015-09-11 09:35:40 +0200)


Bo Shen (1):
  ARM: atmel: boards: use default CONFIG_SYS_PBSIZE

Daniel Gorsulowski (1):
  arm: at91: convert meesc board to generic board

Heiko Schocher (7):
  at91: corvus: board updates
  corvus, dfu: add dfu support
  arm, at91: add axm extensions
  taurus: board updates
  usb: gadget: at91_udc: port linux driver at91_udc
  usb: gadget: at91_udc: add at91_udc into U-Boot
  at91, taurus, smartweb: add dfu support

 board/siemens/corvus/board.c|   23 +-
 board/siemens/smartweb/smartweb.c   |   29 +
 board/siemens/taurus/taurus.c   |  229 -
 drivers/usb/gadget/Makefile |1 +
 drivers/usb/gadget/at91_udc.c   | 1625 +++
 drivers/usb/gadget/at91_udc.h   |  171 
 include/configs/at91-sama5_common.h |2 -
 include/configs/at91sam9260ek.h |1 -
 include/configs/at91sam9261ek.h |1 -
 include/configs/at91sam9263ek.h |1 -
 include/configs/at91sam9m10g45ek.h  |1 -
 include/configs/at91sam9n12ek.h |2 -
 include/configs/at91sam9rlek.h  |1 -
 include/configs/at91sam9x5ek.h  |2 -
 include/configs/corvus.h|   44 +-
 include/configs/meesc.h |2 +
 include/configs/smartweb.h  |   53 +-
 include/configs/taurus.h|  120 ++-
 include/linux/usb/at91_udc.h|   20 +
 19 files changed, 2262 insertions(+), 66 deletions(-)
 create mode 100644 drivers/usb/gadget/at91_udc.c
 create mode 100644 drivers/usb/gadget/at91_udc.h
 create mode 100644 include/linux/usb/at91_udc.h
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Re: [U-Boot] [PATCH 2/4] mmc: dw_mmc: Zap endless timeout

[Alexey Brodkin]

Hi Marek,

On Mon, 2015-07-27 at 22:39 +0200, Marek Vasut wrote:
> Endless timeouts are bad, since if we get stuck in one, we have no
> way out. Zap this one by implementing proper timeout.
> 
> Signed-off-by: Marek Vasut 
> Cc: Dinh Nguyen 
> Cc: Pantelis Antoniou 
> Cc: Tom Rini 
> ---
>  drivers/mmc/dw_mmc.c | 19 +--
>  1 file changed, 17 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c
> index 3fffa71..0f61f16 100644
> --- a/drivers/mmc/dw_mmc.c
> +++ b/drivers/mmc/dw_mmc.c
> @@ -211,14 +211,29 @@ static int dwmci_send_cmd(struct mmc *mmc, struct 
> mmc_cmd *cmd,
>   }
>  
>   if (data) {
> - do {
> + start = get_timer(0);
> + timeout = 1000;
> + for (;;) {
>   mask = dwmci_readl(host, DWMCI_RINTSTS);
> + /* Error during data transfer. */
>   if (mask & (DWMCI_DATA_ERR | DWMCI_DATA_TOUT)) {
>   printf("%s: DATA ERROR!\n", __func__);
>   bounce_buffer_stop();
>   return -1;
>   }
> - } while (!(mask & DWMCI_INTMSK_DTO));
> +
> + /* Data arrived correctly. */
> + if (mask & DWMCI_INTMSK_DTO)
> + break;
> +
> + /* Check for timeout. */
> + if (get_timer(start) > timeout) {
> + printf("%s: Timeout waiting for data!\n",
> +__func__);
> + bounce_buffer_stop();
> + return TIMEOUT;
> + }
> + }
>  
>   dwmci_writel(host, DWMCI_RINTSTS, mask);
>  

It turned out that patch breaks functionality in some cases.
For me on every attempt to download something significant (at least I see it on
5/7 Mb files) from SD I'm seeing timeout firing too early.

I added a bit of extra instrumentation to see where time is spent and why.

So my diff is:
--->8
diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c
index 77b87e0..2da77a7 100644
--- a/drivers/mmc/dw_mmc.c
+++ b/drivers/mmc/dw_mmc.c
@@ -213,7 +213,7 @@ static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd 
*cmd,
 
if (data) {
start = get_timer(0);
-   timeout = 1000;
+   timeout = 1; // That's required to get to the end of the 
transfer
for (;;) {
mask = dwmci_readl(host, DWMCI_RINTSTS);
/* Error during data transfer. */
@@ -226,6 +226,7 @@ static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd 
*cmd,
/* Data arrived correctly. */
if (mask & DWMCI_INTMSK_DTO) {
ret = 0;
+   printf(" * time spent: %d, data size: %d, 
blocks: %d\n", (int)get_timer(start), data
->blocksize * data->blocks, data->blocks);
break;
}
--->8

And that's what I see then:
--->8
AXS# fatload mmc 0
 * time spent: 0, data size: 8, blocks: 1
 * time spent: 0, data size: 512, blocks: 1
 * time spent: 0, data size: 512, blocks: 1
 * time spent: 0, data size: 512, blocks: 1
reading uImage
 * time spent: 1, data size: 512, blocks: 1
 * time spent: 0, data size: 1024, blocks: 2
 * time spent: 1, data size: 3072, blocks: 6
 * time spent: 1, data size: 3072, blocks: 6
 * time spent: 1, data size: 3072, blocks: 6
 * time spent: 0, data size: 3072, blocks: 6
 * time spent: 0, data size: 3072, blocks: 6
 * time spent: 1599, data size: 13338112, blocks: 26051
 * time spent: 0, data size: 512, blocks: 1
13338188 bytes read in 1651 ms (7.7 MiB/s)
--->8

So you see real data transfer takes  ~1.7 seconds when getting 26k blocks.

In other words timeout check has to be a bit smarter, for example
taking into account number of blocks to be transferred.

Any thoughts?

-Alexey
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Re: [U-Boot] [PATCH] sunxi: (mksunxiboot) signature to indicate "sunxi" SPL variant

[Bernhard Nortmann]

Hello Hans!

Thanks for looking into this.

Am 10.09.2015 um 20:29 schrieb Hans de Goede:


I believe these 2 should be renamed to:

uint32_t fel_boot_script_address;
uint32_t fel_boot_script_size;

To properly reflect what they are (they are not some abstract
data, they are specifically a boot.scr image)

With that changed and Siarhei's ack for the series (I'm assuming
Sairhei will take care of the sunxi-tools side of things),
I'm ok with merging this.

Regards,

Hans


Sure, I can rename them accordingly. With Siarhei's change to clear the
entire image area upfront, setting individual header fields to zero will
also be no longer required.

Regards, B. Nortmann
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Re: [U-Boot] [PATCH 4/5] dm: usb: Add support for USB keyboards with driver model

[Hans de Goede]

Hi,

On 09/11/2015 02:43 AM, Simon Glass wrote:

Hi Marek,

On 10 September 2015 at 04:40, Marek Vasut  wrote:

On Thursday, September 10, 2015 at 04:45:53 AM, Simon Glass wrote:

Hi Marek,

On 8 September 2015 at 12:33, Marek Vasut  wrote:

On Tuesday, September 08, 2015 at 07:15:11 PM, Simon Glass wrote:

Switch USB keyboards over to use driver model instead of scanning with
the horrible usb_get_dev_index() function. This involves creating a new
uclass for keyboards, although so far there is no API.


Hi,

Why don't you create an UCLASS for generic input device instead ?


I sent a series that does that later. My intent with this series is to
get something applied for this release.


Hi!

Aren't we pretty much post-RC3 now ?


Yes. It's not critical and I am late - let's see what Hans says.


I have looking into the RFC patchset on my todo, not sure if I will
get around to it this weekend though, and after that I'm travelling
for a week. Even if I get around to testing this I would prefer for
this to be delayed to post v2015.10. I'm fine with the concept of
the set but this needs some careful testing.

Regards,

Hans
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Re: [U-Boot] [ANN] U-Boot v2015.10-rc3 released

[Wolfgang Denk]

Dear Tom,

In message <20150908001955.GF26226@bill-the-cat> you wrote:
> 
> I've pushed v2015.10-rc3 out to the repository and tarballs should exist
> soon.

Tarballs are inplace, both on FTP [1] and ACD [2].

[1] ftp://ftp.denx.de/pub/u-boot/
[2] 
https://www.amazon.com/clouddrive/share/MjxAmOsCwXJ0gDTX94u5ptSWRZIAbpcsqvBwHfsAUUK?ref_=cd_share_link_copy

Best regards,

Wolfgang Denk

-- 
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HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de
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work of our family, then our community, then the world. - Lao-tzu
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Re: [U-Boot] [U-Boot, v5, 1/3] usb: gadget: at91_udc: port linux driver at91_udc

[Andreas Bießmann]

Dear Heiko Schocher,

Heiko Schocher  writes:
>port at91_udc driver from linux:
>
>original commit Message:
>commit c94e289f195e0e13cf34d27f9338d28221a85751
>Author: Arnd Bergmann 
>Date:   Sat Apr 11 00:14:21 2015 +0200
>
>usb: gadget: remove incorrect __init/__exit annotations
>
>A recent change introduced a link error for the composite
>printer gadget driver:
>
>`printer_unbind' referenced in section `.ref.data' of drivers/built-in.o: 
> defined in discarded section `.exit.text' of drivers/built-in.o
>
>Evidently the unbind function should not be marked __exit here,
>because it is called through a callback pointer that is not necessarily
>discarded, __composite_unbind() is indeed called from the error path of
>composite_bind(), which can never work for a built-in driver.
>
>Looking at the surrounding code, I found the same problem in all other
>composite gadget drivers in both the bind and unbind functions, as
>well as the udc platform driver 'remove' functions. Those will break
>if anyone uses the 'unbind' sysfs attribute to detach a device from a
>built-in driver.
>
>This patch removes the incorrect annotations from all the gadget
>drivers.
>
>Signed-off-by: Heiko Schocher 
>---
>checkpatch detects a lot of errors, but as this code is copied
>from linux, I tend to not fix them, so later updates with
>linux code is easier.
>
>Changes in v5: None
>Changes in v4: None
>Changes in v3:
>- add comments from Alexandre Belloni
>  get rid of cpu_is_at91*, use newer linux version as
>  base for the port to U-Boot.
>
>Changes in v2:
>- add comments from Lukasz Majewski
>  - seperate usb gadget driver port from linux into 2 commits
>  - first patch original from linux (with complete commit message)
>  - second adds U-Boot changes without "#ifdef __UBOOT__"
>
> drivers/usb/gadget/at91_udc.c | 2036 +
> drivers/usb/gadget/at91_udc.h |  175 
> 2 files changed, 2211 insertions(+)
> create mode 100644 drivers/usb/gadget/at91_udc.c
> create mode 100644 drivers/usb/gadget/at91_udc.h

applied to u-boot-atmel/master, thanks!

Best regards,
Andreas Bießmann
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Re: [U-Boot] ARM: atmel: boards: use default CONFIG_SYS_PBSIZE

[Andreas Bießmann]

Dear Josh Wu,

Josh Wu  writes:
>From: Bo Shen 
>
>Entering the maximum number of characters defined by CONFIG_SYS_CBSIZE
>into the console and hitting enter afterwards, causes a hang in the
>system because CONFIG_SYS_PBSIZE is not capable of storing the extra
>characters of the error message:
>"Unknown command '' - try 'help'".
>
>Use the default CONFIG_SYS_PBSIZE definition from config_fallbacks.h
>to solve this problem.
>
>Signed-off-by: Bo Shen 
>Signed-off-by: Josh Wu 
>---
>
> include/configs/at91-sama5_common.h | 2 --
> include/configs/at91sam9260ek.h | 1 -
> include/configs/at91sam9261ek.h | 1 -
> include/configs/at91sam9263ek.h | 1 -
> include/configs/at91sam9m10g45ek.h  | 1 -
> include/configs/at91sam9n12ek.h | 2 --
> include/configs/at91sam9rlek.h  | 1 -
> include/configs/at91sam9x5ek.h  | 2 --
> 8 files changed, 11 deletions(-)

applied to u-boot-atmel/master, thanks!

Best regards,
Andreas Bießmann
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Re: [U-Boot] [U-Boot, 1/1] arm: at91: convert meesc board to generic board

[Andreas Bießmann]

Dear Daniel Gorsulowski,

Daniel Gorsulowski  writes:
>Signed-off-by: Daniel Gorsulowski 
>Reviewed-by: Simon Glass 
>[fix corrupt line wraps in patch]
>Signed-off-by: Andreas Bießmann 
>---
>  include/configs/meesc.h | 2 ++
>  1 file changed, 2 insertions(+)

applied to u-boot-atmel/master, thanks!

Fixed patch while applying.

Best regards,
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Re: [U-Boot] [U-Boot, v5, 3/3] at91, taurus, smartweb: add dfu support

[Andreas Bießmann]

Dear Heiko Schocher,

Heiko Schocher  writes:
>[root@pollux dfu-util]# ./src/dfu-util -l
>dfu-util 0.8
>
>Copyright 2005-2009 Weston Schmidt, Harald Welte and OpenMoko Inc.
>Copyright 2010-2014 Tormod Volden and Stefan Schmidt
>This program is Free Software and has ABSOLUTELY NO WARRANTY
>Please report bugs to dfu-u...@lists.gnumonks.org
>
>Found DFU: [0908:02d2] ver=0212, devnum=119, cfg=1, intf=0, alt=0, 
>name="Linux", serial="UNKNOWN"
>[root@pollux dfu-util]#
>
>Signed-off-by: Heiko Schocher 
>Acked-by: Lukasz Majewski 
>---
>
>Changes in v5:
>- rebase with current mainline
>  commit efde6a579fe: "Prepare v2015.10-rc3"
>
>Changes in v4:
>- rebase after taurus board changes
>
>Changes in v3: None
>Changes in v2:
>- rebase to bd48c0617b5c7212e5bf22169e716da878842da4
>- fix changes introduced through commit:
>  01acd6abbdd5: usb: USB download gadget and functions config options coherent 
> naming
>- add comments from Lukasz Majewski 
>- use SZ_X defines
>
> board/siemens/smartweb/smartweb.c | 29 +
> board/siemens/taurus/taurus.c | 27 
> include/configs/smartweb.h| 53 +--
> include/configs/taurus.h  | 30 --
> 4 files changed, 124 insertions(+), 15 deletions(-)

applied to u-boot-atmel/master, thanks!

Best regards,
Andreas Bießmann
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Re: [U-Boot] [U-Boot, v5, 2/3] usb: gadget: at91_udc: add at91_udc into U-Boot

[Andreas Bießmann]

Dear Heiko Schocher,

Heiko Schocher  writes:
>add U-Boot specific changes to the at91_udc linux driver,
>so it works with U-Boot.
>
>Signed-off-by: Heiko Schocher 
>---
>
>Changes in v5:
>- add comment from Andreas Biessmann:
>  remove BIT() usage in driver, also removed patch
>  which introduced it for U-Boot
>
>Changes in v4: None
>Changes in v3:
>- adapt changes for U-Boot, as newer linux version is
>  used.
>
>Changes in v2:
>- new in version 2, contains U-Boot changes
>
> drivers/usb/gadget/Makefile   |   1 +
> drivers/usb/gadget/at91_udc.c | 603 +++---
> drivers/usb/gadget/at91_udc.h |  16 +-
> include/linux/usb/at91_udc.h  |  20 ++
> 4 files changed, 123 insertions(+), 517 deletions(-)
> create mode 100644 include/linux/usb/at91_udc.h

applied to u-boot-atmel/master, thanks!

Best regards,
Andreas Bießmann
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Re: [U-Boot] [RFC PATCH 2/2] sunxi: add "fel" boot target

[Bernhard Nortmann]

Hi!

Am 10.09.2015 um 20:36 schrieb Hans de Goede:

Hi,

I would prefer to have this like this:

"bootcmd_fel=" \
"if test -n ${fel_booted} && test -n ${fel_data_addr}; then " \
"echo '(FEL boot)';" \
"source ${fel_data_addr}; " \
"fi\0"



Sure, we could do that. I wanted to make clear that ${fel_booted} is
independent of a script being present (and thus ${fel_data_addr} set).
If the user feels inclined to do so, he might e.g. tweak bootcmd_fel
to override some defaults even with no boot.scr involved.


Also if we are not using fel_data_size, then why do we even
have it ?



I thought it unnecessary to restrict ourselves to not being able to
pass the size information, and kept it optional deliberately.

Admittedly it's pointless in the "standard" case of boot.scr, as that
is expected to be an image with a well-defined header (including data
size). I could imagine other uses, e.g. a customized fel utility
passing uEnv.txt-style data, and integrating that via bootcmd_fel
"import -t ${fel_data_addr} ${fel_data_size}". Personally I like to
do this when testing; I find it easier to simply edit a text file
(without having to go through a mkimage .scr on each cycle).

Regards, B. Nortmann
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Re: [U-Boot] [PATCH] arm: at91: clock: Add the generated clock support

[Yang, Wenyou]

Hi Bo Shen,

Thank you for your review.

> -Original Message-
> From: Bo Shen [mailto:voice.s...@gmail.com]
> Sent: 2015年9月10日 6:51
> To: Yang, Wenyou; U-Boot Mailing List
> Subject: Re: [U-Boot] [PATCH] arm: at91: clock: Add the generated clock 
> support
> 
> Hi Wenyou,
> 
> On 09/09/2015 10:29 AM, Wenyou Yang wrote:
> > Some peripherals may need a second clock source that may be different
> > from the system clock. This second clock is the generated clock (GCK)
> > and is managed by the PMC via PMC_PCR.
> >
> > For simplicity, the source of the GCK is fixed to PLLA_CLK.
> >
> > Signed-off-by: Wenyou Yang 
> > ---
> >
> >   arch/arm/mach-at91/armv7/clock.c   |   57
> 
> >   arch/arm/mach-at91/include/mach/at91_pmc.h |   13 +++
> >   arch/arm/mach-at91/include/mach/clk.h  |3 ++
> >   3 files changed, 73 insertions(+)
> >
> > diff --git a/arch/arm/mach-at91/armv7/clock.c
> > b/arch/arm/mach-at91/armv7/clock.c
> > index 0bf453e..84418a3 100644
> > --- a/arch/arm/mach-at91/armv7/clock.c
> > +++ b/arch/arm/mach-at91/armv7/clock.c
> > @@ -5,6 +5,7 @@
> >* Copyright (C) 2005 Ivan Kokshaysky
> >* Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD
> 
> >* Copyright (C) 2013 Bo Shen 
> > + * Copyright (C) 2015 Wenyou Yang 
> >*
> >* SPDX-License-Identifier:   GPL-2.0+
> >*/
> > @@ -173,3 +174,59 @@ void at91_periph_clk_disable(int id)
> >
> > writel(regval, >pcr);
> >   }
> > +
> > +void at91_enable_periph_generated_clk(u32 id) {
> > +   struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
> > +   u32 regval;
> > +
> > +   if (id > AT91_PMC_PCR_PID_MASK)
> > +   return;
> > +
> > +   writel(id, >pcr);
> > +   regval = readl(>pcr);
> > +   regval &= ~AT91_PMC_PCR_GCKCSS;
> > +   regval &= ~AT91_PMC_PCR_GCKDIV;
> > +   regval |= AT91_PMC_PCR_GCKCSS_PLLA_CLK |
> > + AT91_PMC_PCR_CMD_WRITE |
> > + AT91_PMC_PCR_GCKDIV_(1) |
> > + AT91_PMC_PCR_GCKEN;
> > +
> > +   writel(regval, >pcr);
> > +
> > +   while (!(readl(>sr) & AT91_PMC_GCKRDY))
> > +   ;
> 
> Here, do we need to hang the whole system?
Do you mean, add the timeout to while()? 

But we think if the clock can't reach to a stable state, the system must be in 
wrong condition.
So, I don't think this timeout is necessary.

Thanks.

> 
> > +}
> > +
> > +u32 at91_get_periph_generated_clk(u32 id) {
> > +   struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
> > +   u32 regval, clk_source, div;
> > +   u32 freq = 0;
> > +
> > +   if (id > AT91_PMC_PCR_PID_MASK)
> > +   return 0;
> > +
> > +   writel(id, >pcr);
> > +   regval = readl(>pcr);
> > +
> > +   clk_source = regval & AT91_PMC_PCR_GCKCSS;
> > +   switch (clk_source) {
> > +   case AT91_PMC_PCR_GCKCSS_SLOW_CLK:
> > +   freq = CONFIG_SYS_AT91_SLOW_CLOCK;
> > +   break;
> > +   case AT91_PMC_PCR_GCKCSS_MAIN_CLK:
> > +   freq = gd->arch.main_clk_rate_hz;
> > +   break;
> > +   case AT91_PMC_PCR_GCKCSS_PLLA_CLK:
> > +   freq = gd->arch.plla_rate_hz;
> > +   break;
> > +   default:
> > +   break;
> 
> For the default, is it valuable to add error information? Or return an 
> invalid value?
Error information is useful, it will be added in next version. Thanks

If reach to default, "freq" will use the initial value(i.e, 0), it can be as an 
invalid value.

> 
> > +   }
> > +
> > +   div = ((regval & AT91_PMC_PCR_GCKDIV) >>
> AT91_PMC_PCR_GCKDIV_OFFSET);
> > +   div += 1;
> > +
> > +   return freq / div;
> > +}
> > diff --git a/arch/arm/mach-at91/include/mach/at91_pmc.h
> > b/arch/arm/mach-at91/include/mach/at91_pmc.h
> > index 8a3fb94..dcd6e36 100644
> > --- a/arch/arm/mach-at91/include/mach/at91_pmc.h
> > +++ b/arch/arm/mach-at91/include/mach/at91_pmc.h
> > @@ -153,8 +153,20 @@ typedef struct at91_pmc {
> >   #define AT91_PMC_IXR_MOSCSELS 0x0001
> >
> >   #define AT91_PMC_PCR_PID_MASK (0x3f)
> > +#define AT91_PMC_PCR_GCKCSS(0x7 << 8)
> > +#defineAT91_PMC_PCR_GCKCSS_SLOW_CLK(0x0 << 8)
> > +#defineAT91_PMC_PCR_GCKCSS_MAIN_CLK(0x1 << 8)
> > +#defineAT91_PMC_PCR_GCKCSS_PLLA_CLK(0x2 << 8)
> > +#defineAT91_PMC_PCR_GCKCSS_UPLL_CLK(0x3 << 8)
> > +#defineAT91_PMC_PCR_GCKCSS_MCK_CLK (0x4 << 8)
> > +#defineAT91_PMC_PCR_GCKCSS_AUDIO_CLK   (0x5 << 8)
> >   #define AT91_PMC_PCR_CMD_WRITE(0x1 << 12)
> > +#define AT91_PMC_PCR_DIV   (0x3 << 16)
> > +#define AT91_PMC_PCR_GCKDIV(0xff << 20)
> > +#defineAT91_PMC_PCR_GCKDIV_(x) ((x) << 20)
> 
> It is dangerous here, if "x = 0xfff", then what will happen?
You mean add "& 0xff" after (x). it will added in next version.

Thanks.

> 
> > +#defineAT91_PMC_PCR_GCKDIV_OFFSET  20
> >   

Re: [U-Boot] [PATCH 1/5] net: mdio: Add mdio_free() and mdio_unregister() API

[Bin Meng]

Hi Joe,

On Fri, Sep 11, 2015 at 6:30 AM, Joe Hershberger
 wrote:
> Hi Bin,
>
> On Fri, Sep 4, 2015 at 9:53 AM, Bin Meng  wrote:
>> Currently there is no API to uninitialize mdio. Add two APIs for this.
>
> Is this causing some failure in the short term? The plan is to move
> eth phy support to driver model in the next year. If it is not needed
> for a device to function then it would be nice to not spend effort on
> this API.

Good to know we have plan to convert PHY support to driver model.

>
> If it is needed short term, then the approach looks fine.
>

Yes, it is needed, otherwise for ethernet device which depends on this
PHY support it will fail to probe() for the 2nd time as the MDIO
resource are not cleaned up.
In the future when we convert PHY support to driver model, we won't
miss this part if these are added now.

[snip]

Regards,
Bin
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Re: [U-Boot] [RFC PATCH 1/2] sunxi: retrieve FEL-provided values to environment variables

[Bernhard Nortmann]

Hi Hans!

Am 10.09.2015 um 20:34 schrieb Hans de Goede:


What if the user interrupts auto-boot with a fel provided boot.scr
and then does "saveenv" ?

Then we end up with a fel_data_addr and fel_data_size permanently
in the env.

At a minimum this function must always do:

setenv("fel_data_addr", NULL);
setenv("fel_data_size", NULL);

(rather then only when we've a spl fel header but no addr / size)

So that we do not end up trying to interpret old values ever.


Good point.



Ideally though we would find another way not involving putting these
in the environment (not sure if that is easily doable).


I also have no idea how to achieve that, especially if we want to keep
the FEL case "in line" with other, more conventional ways of booting.


Maybe clear all env variables here?

Or even better clear them all unconditionally, and then set
them when the checks succeed ?



That's something that may be best aligned somehow with the NAND and
MMC boot handling, if possible? I.e. have some centralized piece of
code that determines the active boot method and retrieves/presets the
environments accordingly. I'll have to re-examine that more closely.

Regards, B. Nortmann
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Re: [U-Boot] [PATCH v4 11/16] common/env_flags.c: Add function to validate a MAC address

[Joe Hershberger]

Hi Codrin,

On Wed, Sep 9, 2015 at 10:00 AM, Codrin Ciubotariu
 wrote:
> The code that checks if a string has the format of a MAC address has been
> moved to a separate function called eth_validate_ethaddr_str().
>
> This has been done to allow other components (such as vsc9953 driver)
> to validate a MAC address.
>
> Signed-off-by: Codrin Ciubotariu 

Acked-by: Joe Hershberger 
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Re: [U-Boot] [PATCH 1/3] net: phy: Don't create phy device when there is no phy

[Joe Hershberger]

Hi Bin,

On Fri, Sep 4, 2015 at 6:56 AM, Bin Meng  wrote:
> In get_phy_device_by_mask(), when no phy is found, we should not
> create any phy device.
>
> Signed-off-by: Bin Meng 

Acked-by: Joe Hershberger 
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Re: [U-Boot] [PATCH v4 12/16] drivers/net/vsc9953: Add commands to manipulate the FDB for VSC9953

[Joe Hershberger]

Hi Codrin,

On Wed, Sep 9, 2015 at 10:00 AM, Codrin Ciubotariu
 wrote:
> The new command:
> ethsw [port ] [vlan ] fdb
> { [help] | show | flush | { add | del }  }
>
> Can be used to add and delete FDB entries. Also, the command can be used
> to show entries from the FDB tables. When used with [port ]
> and [vlan ], only the matching the FDB entries can be seen or
> flushed. The command has also been added to the generic ethsw parser
> from cmd_ethsw.c.
>
> Signed-off-by: Johnson Leung 
> Signed-off-by: Codrin Ciubotariu 

Acked-by: Joe Hershberger 
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Re: [U-Boot] Condition in bootcmd to run bootz else bootm

[DaveKucharczyk]

Turns out what I have works once I turn on the hush parser...

#define CONFIG_SYS_HUSH_PARSER  /* use "hush" command parser */



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Re: [U-Boot] [PATCH] arm: at91: clock: Add the generated clock support

[Bo Shen]

Hi Wenyou,

On 09/11/2015 10:01 AM, Yang, Wenyou wrote:

+
> >+void at91_enable_periph_generated_clk(u32 id) {
> >+  struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
> >+  u32 regval;
> >+
> >+  if (id > AT91_PMC_PCR_PID_MASK)
> >+  return;
> >+
> >+  writel(id, >pcr);
> >+  regval = readl(>pcr);
> >+  regval &= ~AT91_PMC_PCR_GCKCSS;
> >+  regval &= ~AT91_PMC_PCR_GCKDIV;
> >+  regval |= AT91_PMC_PCR_GCKCSS_PLLA_CLK |
> >+AT91_PMC_PCR_CMD_WRITE |
> >+AT91_PMC_PCR_GCKDIV_(1) |
> >+AT91_PMC_PCR_GCKEN;
> >+
> >+  writel(regval, >pcr);
> >+
> >+  while (!(readl(>sr) & AT91_PMC_GCKRDY))
> >+  ;

>
>Here, do we need to hang the whole system?

Do you mean, add the timeout to while()?


Yes, something like that.


But we think if the clock can't reach to a stable state, the system must be in 
wrong condition.
So, I don't think this timeout is necessary.


As no datasheet for this. According to the code, the clock is for the 
peripheral which want to use the generated clock. So, it only affect 
this peripheral while not whole system, am I right?


Best Regards,
Bo Shen
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Re: [U-Boot] U-boot roadmap?

[Lukasz Majewski]

Hi Blibbet,

> Hi,
> 
> First post on list.I'm mostly UEFI-centric, currently trying to learn
> u-boot...
> 
> Is there any roadmap/plan for upcoming architectural changes to
> U-Boot? 

Please look into ELCE2014 slides from u-boot mini summit at Dusseldorf
(slides are available at denx.de webpage).

There was a presentation from Simon Glass regarding device model road
map.

> I recently saw the below comment on a Debian ARM list. I'm
> hoping u-boot has something like that, but more detailed, for newbies
> like me to understand upcoming feature changes better. Discussion on
> driver models, in particular.

There will be u-boot Mini Summit held at ELCE 2015 in Dublin. I think
that the road map issue is a good topic for our overall discussion
panel.

> 
> On 09/11/2015 11:13 AM, Karsten Merker wrote:
> > Mainline u-boot is currently in the process of slowly converting
> > a large number of drivers and boards to the new driver model,
> > which allows deriving platform configuration from device-trees.
> > Whether and how it might be possible to adapt the kernel
> > overlay model for u-boot as well is still open; work on
> > u-boot in that area depends on the kernel side being settled
> > first.
> 
> PS: BTW, nice to see the "U-Boot Verified Boot" feature!

And even better - it does work :-)

> 
> Thanks,
> Lee Fisher
> RSS: http://firmwareescurity.com/feed
> 
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Best regards,
Lukasz Majewski


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Re: [U-Boot] [PATCH 1/2] mmc: dw_mmc: Increase timeout to 20 seconds

[Lukasz Majewski]

Hi Alexey,

> Hi Marek, Lukasz,
> 
> > On Wednesday, September 09, 2015 at 09:01:30 AM, Lukasz Majewski
> > wrote:
> > > Hi,
> > > 
> > > > The commit: d9dbb97be0e4a550457aec5f11afefb446169c90
> > > > "mmc: dw_mmc: Zap endless timeout" removed endless loop waiting
> > > > for end of dw mmc transfer.
> > > > 
> > > > For some workloads - dfu test @ Odroid XU3 (sending 8MiB file) -
> > > > and SD cards (e.g. MicroSD Kingston 4GiB, Adata 4GiB)
> > > > the default timeout is to short.
> > > > 
> > > > The new value - 20 seconds - takes into account the situation
> > > > when SD card triggers internal clean up. Such process may take
> > > > more than 10 seconds on some cards.
> > > > 
> > > > Signed-off-by: Lukasz Majewski 
> > > > Cc: Marek Vasut 
> > > > Cc: Pantelis Antoniou 
> > > > Cc: Tom Rini 
> > > 
> > > Are there any more questions regarding this patch or is it ready
> > > for submission as fix for v2015.10?
> > 
> > No comments, just apply this.
> > 
> > But this should really be fixed properly in the next MW.
> > 
> > Best regards,
> > Marek Vasut
> 
> FWIW I faced similar problem even reading data.
> At least on one of my boards reading of ~8Mb file
> took ~1.7 seconds and so 1 second timeout was interrupting data
> exchange.

Was it SD card or eMMC device?

> 
> So indeed we need to have some dirty hack for upcoming release
> like bumping timeout to something really huge but later we
> need to fix that problem properly.
> 
> I though proper solution would be to set timeout depending of amount
> of data to be exchanged... something like take slowest speed of SD/MMC
> that is allowed by spec and calculate delay based on how much time it
> might take for that slow device and for safety multiply it by say 2.

As fair as I remember, card provide this kind of information. We can
try to investigate this possibility.

> 
> Now from this thread I see that there're other reasons that might
> affect length of at least write operation. In other words it could be
> complicated unfortunately.

My gut feeling is that proper handling of eMMC would require quite a
fair mmc subsystem rework.

> 
> Still we need to fix regression first with virtually infinite
> timeout :) I would even thing that simple revert of Marek's patch may
> make sense for now. 

+1 - unfortunately there were some other patches applied to this
particular patch. Simple revert might be a bit tricky here.

> From both points of view for keeping history
> clean (compared to stacked fixes/workarounds) and from removal of
> regression root cause.

As I said before - +1 from me.

> 
> It's not that I like to have infinite loops but given previous
> implementation worked fine for people in the previous U-Boot release.

Good justification


Best regards,
Lukasz Majewski

> 
> -Alexey
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[U-Boot] U-boot roadmap?

[Blibbet]

Hi,

First post on list.I'm mostly UEFI-centric, currently trying to learn
u-boot...

Is there any roadmap/plan for upcoming architectural changes to U-Boot?
I recently saw the below comment on a Debian ARM list. I'm hoping u-boot
has something like that, but more detailed, for newbies like me to
understand upcoming feature changes better. Discussion on driver models,
in particular.

On 09/11/2015 11:13 AM, Karsten Merker wrote:
> Mainline u-boot is currently in the process of slowly converting
> a large number of drivers and boards to the new driver model,
> which allows deriving platform configuration from device-trees.
> Whether and how it might be possible to adapt the kernel
> overlay model for u-boot as well is still open; work on
> u-boot in that area depends on the kernel side being settled
> first.

PS: BTW, nice to see the "U-Boot Verified Boot" feature!

Thanks,
Lee Fisher
RSS: http://firmwareescurity.com/feed

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[U-Boot] [PATCH] usb: ci_udc: fix emissions of ZLPs

[Stephen Warren]

From: Stephen Warren 

Commit 6a132416359e "ci_udc: Update the ci_udc driver to support bulk
transfers" caused the value of "len" to change without updating subsquent
users of that variable in ci_ep_submit_next_request(). This caused the
code that detects when to emit ZLPs (Zero Length Packets) never to
trigger, which in turn caused host timeouts when a ZLP was required,
which in turn broke tests/dfu/, even despite the assertion in that
commit's description that "These changes are tested for both the DFU and
lthor."

Fix this by modifying the added dtd iteration code not to modify "len",
but rather to keep state in a separate variable. Rename the variables
while we're at it so they describe their purpose better.

Fixes: 6a132416359e ("ci_udc: Update the ci_udc driver to support bulk 
transfers")
Cc: Siva Durga Prasad Paladugu 
Signed-off-by: Stephen Warren 
---
 drivers/usb/gadget/ci_udc.c | 18 --
 1 file changed, 8 insertions(+), 10 deletions(-)

diff --git a/drivers/usb/gadget/ci_udc.c b/drivers/usb/gadget/ci_udc.c
index 3e8eb8799f4e..b875c5c148b4 100644
--- a/drivers/usb/gadget/ci_udc.c
+++ b/drivers/usb/gadget/ci_udc.c
@@ -424,7 +424,7 @@ static void ci_ep_submit_next_request(struct ci_ep *ci_ep)
int bit, num, len, in;
struct ci_req *ci_req;
u8 *buf;
-   uint32_t length, actlen;
+   uint32_t len_left, len_this_dtd;
struct ept_queue_item *dtd, *qtd;
 
ci_ep->req_primed = true;
@@ -442,25 +442,23 @@ static void ci_ep_submit_next_request(struct ci_ep *ci_ep)
 
ci_req->dtd_count = 0;
buf = ci_req->hw_buf;
-   actlen = 0;
+   len_left = len;
dtd = item;
 
do {
-   length = min(ci_req->req.length - actlen,
-(unsigned)EP_MAX_LENGTH_TRANSFER);
+   len_this_dtd = min(len_left, (unsigned)EP_MAX_LENGTH_TRANSFER);
 
-   dtd->info = INFO_BYTES(length) | INFO_ACTIVE;
+   dtd->info = INFO_BYTES(len_this_dtd) | INFO_ACTIVE;
dtd->page0 = (unsigned long)buf;
dtd->page1 = ((unsigned long)buf & 0xf000) + 0x1000;
dtd->page2 = ((unsigned long)buf & 0xf000) + 0x2000;
dtd->page3 = ((unsigned long)buf & 0xf000) + 0x3000;
dtd->page4 = ((unsigned long)buf & 0xf000) + 0x4000;
 
-   len -= length;
-   actlen += length;
-   buf += length;
+   len_left -= len_this_dtd;
+   buf += len_this_dtd;
 
-   if (len) {
+   if (len_left) {
qtd = (struct ept_queue_item *)
   memalign(ILIST_ALIGN, ILIST_ENT_SZ);
dtd->next = (unsigned long)qtd;
@@ -469,7 +467,7 @@ static void ci_ep_submit_next_request(struct ci_ep *ci_ep)
}
 
ci_req->dtd_count++;
-   } while (len);
+   } while (len_left);
 
item = dtd;
/*
-- 
1.9.1

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[U-Boot] [PATCH 13/14] armv8/ls1043ardb: Add sd boot support

[Gong Qianyu]

Signed-off-by: Gong Qianyu 
---
 board/freescale/ls1043ardb/ls1043ardb.c  |  8 +++
 board/freescale/ls1043ardb/ls1043ardb_rcw_sd.cfg |  7 ++
 configs/ls1043ardb_sdcard_defconfig  |  4 
 include/configs/ls1043a_common.h | 30 
 include/configs/ls1043ardb.h | 13 --
 5 files changed, 60 insertions(+), 2 deletions(-)

diff --git a/board/freescale/ls1043ardb/ls1043ardb.c 
b/board/freescale/ls1043ardb/ls1043ardb.c
index 81dd271..991404a 100644
--- a/board/freescale/ls1043ardb/ls1043ardb.c
+++ b/board/freescale/ls1043ardb/ls1043ardb.c
@@ -12,11 +12,13 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
 #include 
 #include 
+#include 
 #include "cpld.h"
 #include "../common/ns_access.h"
 
@@ -25,12 +27,17 @@ DECLARE_GLOBAL_DATA_PTR;
 int checkboard(void)
 {
static const char *freq[3] = {"100.00MHZ", "156.25MHZ"};
+#ifndef CONFIG_SD_BOOT
u8 cfg_rcw_src1, cfg_rcw_src2;
u32 cfg_rcw_src;
+#endif
u32 sd1refclk_sel;
 
printf("Board: LS1043ARDB, boot from ");
 
+#ifdef CONFIG_SD_BOOT
+   puts("SD\n");
+#else
cfg_rcw_src1 = CPLD_READ(cfg_rcw_src1);
cfg_rcw_src2 = CPLD_READ(cfg_rcw_src2);
cpld_rev_bit(_rcw_src1);
@@ -43,6 +50,7 @@ int checkboard(void)
puts("NAND\n");
else
printf("Invalid setting of SW4\n");
+#endif
 
printf("CPLD:  V%x.%x\nPCBA:  V%x.0\n", CPLD_READ(cpld_ver),
   CPLD_READ(cpld_ver_sub), CPLD_READ(pcba_ver));
diff --git a/board/freescale/ls1043ardb/ls1043ardb_rcw_sd.cfg 
b/board/freescale/ls1043ardb/ls1043ardb_rcw_sd.cfg
new file mode 100644
index 000..28cd958
--- /dev/null
+++ b/board/freescale/ls1043ardb/ls1043ardb_rcw_sd.cfg
@@ -0,0 +1,7 @@
+#PBL preamble and RCW header
+aa55aa55 01ee0100
+# RCW
+081f 0c00  
+14550002 80004012 6004 61002000
+   00038800
+ 1100 0096 0001
diff --git a/configs/ls1043ardb_sdcard_defconfig 
b/configs/ls1043ardb_sdcard_defconfig
new file mode 100644
index 000..5fe0470
--- /dev/null
+++ b/configs/ls1043ardb_sdcard_defconfig
@@ -0,0 +1,4 @@
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT,SYS_FSL_DDR4"
+CONFIG_ARM=y
+CONFIG_TARGET_LS1043ARDB=y
diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h
index bf1ddc7..1e726fb 100644
--- a/include/configs/ls1043a_common.h
+++ b/include/configs/ls1043a_common.h
@@ -60,6 +60,36 @@
 #define CONFIG_BAUDRATE115200
 #define CONFIG_SYS_BAUDRATE_TABLE  { 9600, 19200, 38400, 57600, 115200 }
 
+/* SD boot SPL */
+#ifdef CONFIG_SD_BOOT
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_LDSCRIPT"arch/arm/cpu/armv8/u-boot-spl.lds"
+#define CONFIG_SPL_TARGET  "u-boot-with-spl.bin"
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_ENV_SUPPORT
+#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
+#define CONFIG_SPL_WATCHDOG_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR0xf0
+#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x500
+
+#define CONFIG_SPL_TEXT_BASE   0x1000
+#define CONFIG_SPL_MAX_SIZE0x1d000
+#define CONFIG_SPL_STACK   0x1001e000
+#define CONFIG_SPL_PAD_TO  0x1d000
+
+#define CONFIG_SYS_SPL_MALLOC_START(CONFIG_SYS_TEXT_BASE + \
+   CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_SYS_SPL_MALLOC_SIZE 0x10
+#define CONFIG_SPL_BSS_START_ADDR  0x8010
+#define CONFIG_SPL_BSS_MAX_SIZE0x8
+#define CONFIG_SYS_MONITOR_LEN 0xa
+#endif
+
 /* NAND SPL */
 #ifdef CONFIG_NAND_BOOT
 #define CONFIG_SPL_PBL_PAD
diff --git a/include/configs/ls1043ardb.h b/include/configs/ls1043ardb.h
index e612cee..4565500 100644
--- a/include/configs/ls1043ardb.h
+++ b/include/configs/ls1043ardb.h
@@ -12,7 +12,7 @@
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
 
-#if defined(CONFIG_NAND_BOOT)
+#if defined(CONFIG_NAND_BOOT) || defined(CONFIG_SD_BOOT)
 #define CONFIG_SYS_TEXT_BASE   0x8200
 #else
 #define CONFIG_SYS_TEXT_BASE   0x6010
@@ -45,6 +45,10 @@
 #define CONFIG_SYS_FSL_PBL_RCW 
board/freescale/ls1043ardb/ls1043ardb_rcw_nand.cfg
 #endif
 
+#ifdef CONFIG_SD_BOOT
+#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043ardb/ls1043ardb_rcw_sd.cfg
+#endif
+
 /*
  * NOR Flash Definitions
  */
@@ -217,7 +221,12 @@
  */
 #define CONFIG_ENV_OVERWRITE
 
-#if defined(CONFIG_NAND_BOOT)
+#if defined(CONFIG_SD_BOOT)
+#define CONFIG_ENV_OFFSET  (1024 * 1024)
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV 0
+#define 

[U-Boot] [PATCH 12/14] armv8/ls1043ardb: esdhc: Add esdhc support for ls1043ardb

[Gong Qianyu]

From: Yangbo Lu 

This patch adds esdhc support for ls1043ardb.

Signed-off-by: Yangbo Lu 
Signed-off-by: Gong Qianyu 
---
 arch/arm/cpu/armv8/fsl-lsch2/cpu.c   | 10 ++
 arch/arm/cpu/armv8/fsl-lsch2/fdt.c   |  6 ++
 arch/arm/cpu/armv8/fsl-lsch2/speed.c | 18 +-
 drivers/mmc/fsl_esdhc.c  | 13 +++--
 include/configs/ls1043a_common.h | 11 +++
 include/fsl_esdhc.h  |  2 +-
 6 files changed, 52 insertions(+), 8 deletions(-)

diff --git a/arch/arm/cpu/armv8/fsl-lsch2/cpu.c 
b/arch/arm/cpu/armv8/fsl-lsch2/cpu.c
index c358534..238cc68 100644
--- a/arch/arm/cpu/armv8/fsl-lsch2/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-lsch2/cpu.c
@@ -12,6 +12,9 @@
 #include 
 #include 
 #include 
+#ifdef CONFIG_FSL_ESDHC
+#include 
+#endif
 #include "speed.h"
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -382,6 +385,13 @@ int print_cpuinfo(void)
 }
 #endif
 
+#ifdef CONFIG_FSL_ESDHC
+int cpu_mmc_init(bd_t *bis)
+{
+   return fsl_esdhc_mmc_init(bis);
+}
+#endif
+
 /*
  * Initializes on-chip ethernet controllers.
  * to override, implement board_eth_init()
diff --git a/arch/arm/cpu/armv8/fsl-lsch2/fdt.c 
b/arch/arm/cpu/armv8/fsl-lsch2/fdt.c
index fd9063d..2650107 100644
--- a/arch/arm/cpu/armv8/fsl-lsch2/fdt.c
+++ b/arch/arm/cpu/armv8/fsl-lsch2/fdt.c
@@ -8,6 +8,9 @@
 #include 
 #include 
 #include 
+#ifdef CONFIG_FSL_ESDHC
+#include 
+#endif
 
 int fdt_fixup_phy_connection(void *blob, int offset, phy_interface_t phyc)
 {
@@ -17,4 +20,7 @@ int fdt_fixup_phy_connection(void *blob, int offset, 
phy_interface_t phyc)
 
 void ft_cpu_setup(void *blob, bd_t *bd)
 {
+#if defined(CONFIG_FSL_ESDHC)
+   fdt_fixup_esdhc(blob, bd);
+#endif
 }
diff --git a/arch/arm/cpu/armv8/fsl-lsch2/speed.c 
b/arch/arm/cpu/armv8/fsl-lsch2/speed.c
index f5a7f73..e12d485 100644
--- a/arch/arm/cpu/armv8/fsl-lsch2/speed.c
+++ b/arch/arm/cpu/armv8/fsl-lsch2/speed.c
@@ -25,7 +25,7 @@ void get_sys_info(struct sys_info *sys_info)
struct fsl_ifc ifc_regs = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
u32 ccr;
 #endif
-#ifdef CONFIG_SYS_DPAA_FMAN
+#if defined(CONFIG_FSL_ESDHC) || defined(CONFIG_SYS_DPAA_FMAN)
u32 rcw_tmp;
 #endif
struct ccsr_clk *clk = (void *)(CONFIG_SYS_FSL_CLK_ADDR);
@@ -105,6 +105,11 @@ void get_sys_info(struct sys_info *sys_info)
 
 #define HWA_CGA_M2_CLK_SEL 0x0007
 #define HWA_CGA_M2_CLK_SHIFT   0
+#if defined(CONFIG_FSL_ESDHC)
+   rcw_tmp = in_be32(>rcwsr[15]);
+   rcw_tmp = (rcw_tmp & HWA_CGA_M2_CLK_SEL) >> HWA_CGA_M2_CLK_SHIFT;
+   sys_info->freq_sdhc = freq_c_pll[1] / rcw_tmp;
+#endif
 
 #if defined(CONFIG_FSL_IFC)
ccr = in_le32(_regs.gregs->ifc_ccr);
@@ -123,6 +128,10 @@ int get_clocks(void)
gd->bus_clk = sys_info.freq_systembus;
gd->mem_clk = sys_info.freq_ddrbus;
 
+#if defined(CONFIG_FSL_ESDHC)
+   gd->arch.sdhc_clk = sys_info.freq_sdhc;
+#endif
+
if (gd->cpu_clk != 0)
return 0;
else
@@ -139,6 +148,11 @@ ulong get_ddr_freq(ulong dummy)
return gd->mem_clk;
 }
 
+int get_sdhc_freq(ulong dummy)
+{
+   return gd->arch.sdhc_clk;
+}
+
 int get_serial_clock(void)
 {
return gd->bus_clk;
@@ -149,6 +163,8 @@ unsigned int mxc_get_clock(enum mxc_clock clk)
switch (clk) {
case MXC_I2C_CLK:
return get_bus_freq(0);
+   case MXC_ESDHC_CLK:
+   return get_sdhc_freq(0);
case MXC_DSPI_CLK:
return get_bus_freq(0);
case MXC_UART_CLK:
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index 0b37002..0a22874 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -106,7 +106,8 @@ static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct 
mmc_data *data)
xfertyp |= XFERTYP_RSPTYP_48;
 
 #if defined(CONFIG_MX53) || defined(CONFIG_PPC_T4240) || \
-   defined(CONFIG_LS102XA) || defined(CONFIG_LS2085A)
+   defined(CONFIG_LS102XA) || defined(CONFIG_LS2085A) || \
+   defined(CONFIG_LS1043A)
if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
xfertyp |= XFERTYP_CMDTYP_ABORT;
 #endif
@@ -184,7 +185,7 @@ static int esdhc_setup_data(struct mmc *mmc, struct 
mmc_data *data)
int timeout;
struct fsl_esdhc_cfg *cfg = mmc->priv;
struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
-#ifdef CONFIG_LS2085A
+#if defined(CONFIG_LS2085A) || defined(CONFIG_LS1043A)
dma_addr_t addr;
 #endif
uint wml_value;
@@ -197,7 +198,7 @@ static int esdhc_setup_data(struct mmc *mmc, struct 
mmc_data *data)
 
esdhc_clrsetbits32(>wml, WML_RD_WML_MASK, wml_value);
 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
-#ifdef CONFIG_LS2085A
+#if defined(CONFIG_LS2085A) || defined(CONFIG_LS1043A)
addr = virt_to_phys((void *)(data->dest));
if (upper_32_bits(addr))
printf("Error found for 

[U-Boot] [PATCH 14/14] armv8/ls1043ardb: Add cpld command to boot from sd

[Gong Qianyu]

Signed-off-by: Gong Qianyu 
---
 board/freescale/ls1043ardb/cpld.c | 17 +
 board/freescale/ls1043ardb/cpld.h |  1 +
 2 files changed, 18 insertions(+)

diff --git a/board/freescale/ls1043ardb/cpld.c 
b/board/freescale/ls1043ardb/cpld.c
index 5acb97d..faa0de8 100644
--- a/board/freescale/ls1043ardb/cpld.c
+++ b/board/freescale/ls1043ardb/cpld.c
@@ -60,6 +60,20 @@ void cpld_set_nand(void)
CPLD_WRITE(system_rst, 1);
 }
 
+void cpld_set_sd(void)
+{
+   u16 reg = CPLD_CFG_RCW_SRC_SD;
+   u8 reg5 = (u8)(reg >> 1);
+   u8 reg6 = (u8)(reg & 1);
+   cpld_rev_bit();
+
+   CPLD_WRITE(soft_mux_on, 1);
+
+   CPLD_WRITE(cfg_rcw_src1, reg5);
+   CPLD_WRITE(cfg_rcw_src2, reg6);
+
+   CPLD_WRITE(system_rst, 1);
+}
 #ifdef DEBUG
 static void cpld_dump_regs(void)
 {
@@ -108,6 +122,8 @@ int do_cpld(cmd_tbl_t *cmdtp, int flag, int argc, char * 
const argv[])
cpld_set_altbank();
else if (strcmp(argv[2], "nand") == 0)
cpld_set_nand();
+   else if (strcmp(argv[2], "sd") == 0)
+   cpld_set_sd();
else
cpld_set_defbank();
 #ifdef DEBUG
@@ -127,6 +143,7 @@ U_BOOT_CMD(
"reset: reset to default bank\n"
"cpld reset altbank: reset to alternate bank\n"
"cpld reset nand: reset to boot from NAND flash\n"
+   "cpld reset sd: reset to boot from SD card\n"
 #ifdef DEBUG
"cpld dump - display the CPLD registers\n"
 #endif
diff --git a/board/freescale/ls1043ardb/cpld.h 
b/board/freescale/ls1043ardb/cpld.h
index 5f43a8a..bd59c0e 100644
--- a/board/freescale/ls1043ardb/cpld.h
+++ b/board/freescale/ls1043ardb/cpld.h
@@ -41,4 +41,5 @@ void cpld_rev_bit(unsigned char *value);
 #define CPLD_BANK_SEL_MASK 0x07
 #define CPLD_BANK_SEL_ALTBANK  0x04
 #define CPLD_CFG_RCW_SRC_NAND  0x106
+#define CPLD_CFG_RCW_SRC_SD0x040
 #endif
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH v2 14/18] ARM: uniphier: drop DCC micro support card support

[Masahiro Yamada]

Historically (for compatibility with very old platforms), two
different types of micro support cards have been used with the
UniPhier SoC development boards.  It has been painful to maintain
both.  Having one of them is enough.

Signed-off-by: Masahiro Yamada 
Reviewed-by: Simon Glass 
---

Changes in v2: None

 arch/arm/mach-uniphier/Kconfig | 23 ++-
 arch/arm/mach-uniphier/Makefile|  3 +-
 arch/arm/mach-uniphier/include/mach/board.h|  6 +-
 arch/arm/mach-uniphier/ph1-ld4/Makefile|  3 +-
 arch/arm/mach-uniphier/ph1-ld4/sbc_init_3cs.c  | 49 ---
 arch/arm/mach-uniphier/ph1-pro4/Makefile   |  3 +-
 arch/arm/mach-uniphier/ph1-pro4/sbc_init_3cs.c | 42 -
 arch/arm/mach-uniphier/ph1-sld3/Makefile   |  3 +-
 arch/arm/mach-uniphier/ph1-sld3/sbc_init_3cs.c | 37 ---
 arch/arm/mach-uniphier/ph1-sld8/sbc_init_3cs.c | 57 -
 arch/arm/mach-uniphier/support_card.c  | 87 +++---
 configs/ph1_ld4_defconfig  |  2 +-
 configs/ph1_pro4_defconfig |  2 +-
 configs/ph1_sld3_defconfig |  2 +-
 configs/ph1_sld8_defconfig |  2 +-
 include/configs/uniphier.h | 19 ++
 16 files changed, 29 insertions(+), 311 deletions(-)
 delete mode 100644 arch/arm/mach-uniphier/ph1-ld4/sbc_init_3cs.c
 delete mode 100644 arch/arm/mach-uniphier/ph1-pro4/sbc_init_3cs.c
 delete mode 100644 arch/arm/mach-uniphier/ph1-sld3/sbc_init_3cs.c
 delete mode 100644 arch/arm/mach-uniphier/ph1-sld8/sbc_init_3cs.c

diff --git a/arch/arm/mach-uniphier/Kconfig b/arch/arm/mach-uniphier/Kconfig
index 7b49ad3..28d574f 100644
--- a/arch/arm/mach-uniphier/Kconfig
+++ b/arch/arm/mach-uniphier/Kconfig
@@ -26,29 +26,14 @@ config MACH_PH1_SLD8
 
 endchoice
 
-choice
-   prompt "UniPhier Support Card select"
-   optional
-
-config PFC_MICRO_SUPPORT_CARD
-   bool "Support card with PFC CPLD"
-   help
- This option provides support for the expansion board with PFC
- original address mapping.
-
- Say Y to use the on-board UART, Ether, LED devices.
-
-config DCC_MICRO_SUPPORT_CARD
-   bool "Support card with DCC CPLD"
+config MICRO_SUPPORT_CARD
+   bool "Use Micro Support Card"
help
- This option provides support for the expansion board with DCC-
- arranged address mapping that is compatible with legacy UniPhier
- reference boards.
+ This option provides support for the expansion board, available
+ on some UniPhier reference boards.
 
  Say Y to use the on-board UART, Ether, LED devices.
 
-endchoice
-
 config CMD_PINMON
bool "Enable boot mode pins monitor command"
default y
diff --git a/arch/arm/mach-uniphier/Makefile b/arch/arm/mach-uniphier/Makefile
index 103db6d..5f17557 100644
--- a/arch/arm/mach-uniphier/Makefile
+++ b/arch/arm/mach-uniphier/Makefile
@@ -29,8 +29,7 @@ endif
 
 obj-y += timer.o
 
-obj-$(CONFIG_PFC_MICRO_SUPPORT_CARD) += support_card.o
-obj-$(CONFIG_DCC_MICRO_SUPPORT_CARD) += support_card.o
+obj-$(CONFIG_MICRO_SUPPORT_CARD) += support_card.o
 
 obj-$(CONFIG_MACH_PH1_SLD3)+= ph1-sld3/
 obj-$(CONFIG_MACH_PH1_LD4) += ph1-ld4/
diff --git a/arch/arm/mach-uniphier/include/mach/board.h 
b/arch/arm/mach-uniphier/include/mach/board.h
index e3cba5b..c039d80 100644
--- a/arch/arm/mach-uniphier/include/mach/board.h
+++ b/arch/arm/mach-uniphier/include/mach/board.h
@@ -1,6 +1,5 @@
 /*
- * Copyright (C) 2012-2014 Panasonic Corporation
- *   Author: Masahiro Yamada 
+ * Copyright (C) 2012-2015 Masahiro Yamada 
  *
  * SPDX-License-Identifier:GPL-2.0+
  */
@@ -8,8 +7,7 @@
 #ifndef ARCH_BOARD_H
 #define ARCH_BOARD_H
 
-#if defined(CONFIG_PFC_MICRO_SUPPORT_CARD) || \
-   defined(CONFIG_DCC_MICRO_SUPPORT_CARD)
+#if defined(CONFIG_MICRO_SUPPORT_CARD)
 void support_card_reset(void);
 void support_card_init(void);
 void support_card_late_init(void);
diff --git a/arch/arm/mach-uniphier/ph1-ld4/Makefile 
b/arch/arm/mach-uniphier/ph1-ld4/Makefile
index 0c198c6..4a2c944 100644
--- a/arch/arm/mach-uniphier/ph1-ld4/Makefile
+++ b/arch/arm/mach-uniphier/ph1-ld4/Makefile
@@ -6,8 +6,7 @@ ifdef CONFIG_SPL_BUILD
 obj-$(CONFIG_DEBUG_LL) += lowlevel_debug.o
 obj-y += bcu_init.o pll_init.o early_clkrst_init.o \
pll_spectrum.o umc_init.o ddrphy_init.o
-obj-$(CONFIG_PFC_MICRO_SUPPORT_CARD) += sbc_init.o
-obj-$(CONFIG_DCC_MICRO_SUPPORT_CARD) += sbc_init_3cs.o
+obj-$(CONFIG_MICRO_SUPPORT_CARD) += sbc_init.o
 else
 obj-$(CONFIG_BOARD_EARLY_INIT_F) += pinctrl.o clkrst_init.o
 endif
diff --git a/arch/arm/mach-uniphier/ph1-ld4/sbc_init_3cs.c 
b/arch/arm/mach-uniphier/ph1-ld4/sbc_init_3cs.c
deleted file mode 100644
index 5b5958b..000
--- a/arch/arm/mach-uniphier/ph1-ld4/sbc_init_3cs.c
+++ /dev/null
@@ -1,49 +0,0 @@
-/*
- * 

Re: [U-Boot] arm: mvebu: u-boot does not start on db-88f6820-gp

[Stefan Eichenberger]

Hi Stefan,

On 09/11/2015 04:24 PM, Stefan Roese wrote:

Hi Stefan,

On 11.09.2015 15:50, Stefan Eichenberger wrote:

On 09/04/2015 06:44 PM, Stefan Roese wrote:


Unfortunately u-boot now hangs if I try to load an image from the
SD-Card:
e.g. if I run the following command u-boot hangs:
ext4load mmc 0:2 0x200 /boot/kernel.bin

I don't see why exactly it crashes, it seems for me that it's 
always at

a different position.

Here are two backtraces, always at a different positions:

Here u-boot stopped automatically:
Program received signal SIGTRAP, Trace/breakpoint trap.
0x7ff65d84 in ?? ()
(gdb) backtrace
#0  0x7ff65d84 in ?? ()
#1  0x803663d0 in ?? ()
#2  0x803663d0 in ?? ()
Backtrace stopped: previous frame identical to this frame (corrupt
stack?)

And here I've got perhaps some more information?
Program received signal SIGSTOP, Stopped (signal).
v7_inval_dcache_level_setway (log2_line_len=,
way_shift=, num_ways=,
 num_sets=, level=) at
arch/arm/cpu/armv7/cache_v7.c:62
62  for (set = num_sets - 1; set >= 0; set--) {
(gdb) backtrace
#0  v7_inval_dcache_level_setway (log2_line_len=,
way_shift=,
 num_ways=, num_sets=,
level=) at arch/arm/cpu/armv7/cache_v7.c:62
#1  v7_maint_dcache_level_setway (operation=, 
level=9) at

arch/arm/cpu/armv7/cache_v7.c:129
#2  v7_maint_dcache_all (operation=2146852864) at
arch/arm/cpu/armv7/cache_v7.c:147
#3  0xfbe2 in ?? ()
#4  0xfbe2 in ?? ()

Could it be that there is something wrong with cache/dram setup?


Maybe. Hard to tell. Why don't you use "dcache off" before you start
the command. If this works, then we still have a problem with cache
(L1 / L2)...


I now did some tests, it seems that the kernel only crashes if I access
the SD-Card, I'm able to load the kernel from an USB-Device. I tried to
disable the dcache but the problem still remains.

Another problem I have is that if I try to start a mainline kernel, it
will crash with the following trace, I think it doesn't find the
devicetree for some reasons:


Didn't you mention above, that booting Linux does work when booted via 
USB? Is this crash below a caused by accessing the SD-card?


Sorry that was unclear. I can load the Linux kernel from USB into RAM 
and jump to the load address but then Linux crashes. The SD-card access 
seems totally broken.





## Booting kernel from Legacy Image at 0200 ...
Image Name:
Image Type:   ARM Linux Kernel Image (uncompressed)
Data Size:7258976 Bytes = 6.9 MiB
Load Address: 8000
Entry Point:  8000
Verifying Checksum ... OK
## Flattened Device Tree blob at 0300
Booting using the fdt blob at 0x300
Loading Kernel Image ... OK
Loading Device Tree to 7fb49000, end 7fb4ee70 ... OK

Starting kernel ...

[0.00] Booting Linux on physical CPU 0x0
[0.00] Linux version 4.2.0 (eichenberger@gruene) (gcc version
4.6.4 (Marvell GCC release 20150204-c4af733b 645
[0.00] CPU: ARMv7 Processor [414fc091] revision 1 (ARMv7),
cr=10c5387d
[0.00] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing
instruction cache
[0.00] Machine model: Marvell Armada 385 Development Board
[0.00] bootconsole [earlycon0] enabled
[0.00] Memory policy: Data cache writealloc
[0.00] Unable to handle kernel paging request at virtual address
3fb49000
[0.00] pgd = c0004000
[0.00] [3fb49000] *pgd=
[0.00] Internal error: Oops: 5 [#1] SMP ARM
[0.00] Modules linked in:
[0.00] CPU: 0 PID: 0 Comm: swapper Not tainted 4.2.0 #67
[0.00] Hardware name: Marvell Armada 380/385 (Device Tree)
[0.00] task: c06bd528 ti: c06b8000 task.ti: c06b8000
[0.00] PC is at fdt_check_header+0x0/0x78
[0.00] LR is at __unflatten_device_tree+0x1c/0x12c
[0.00] pc : []lr : [] psr: 21d3
[0.00] sp : c06b9f38  ip :   fp : ef7fce40
[0.00] r10: c071d2f0  r9 : c05c4d7c  r8 : 3fb49000
[0.00] r7 : c069454c  r6 : c06be514  r5 : c0712f68  r4 : 
c069454c
[0.00] r3 : c071d308  r2 : c069454c  r1 : c071d2f0  r0 : 
3fb49000

[0.00] Flags: nzCv  IRQs off  FIQs off  Mode SVC_32  ISA ARM
Segment kernel
[0.00] Control: 10c5387d  Table: 404a  DAC: 0015
[0.00] Process swapper (pid: 0, stack limit = 0xc06b8220)
[0.00] Stack: (0xc06b9f38 to 0xc06ba000)
[0.00]
9f20: 
c070
[0.00] 9f40: 1000 0002f7ff 1000 0007 c069e348
c069454c c0712f68 c06be514
[0.00] 9f60: c06c2dc0 c06be514 000c c069514c c069e348
c0679448  10c5387d
[0.00] 9f80: 414fc091   c005aa68 c05c38cc
c06b9fb4  
[0.00] 9fa0: 0001  c06f4380  414fc091
  c067693c
[0.00] 9fc0:     
c06a9288  c06f4614
[0.00] 9fe0: c06ba4c0 c06a9284 c06be624 406a 
807c  
[

[U-Boot] [PATCH] Powerpc: eSDHC: expand a fix to T4160

[shh.xie]

From: Shaohui Xie 

commit b8e5b07225 "Powerpc: eSDHC: Fix mmc read write err in uboot of
T4240QDS board", T4160 also needs this fix.

Signed-off-by: Shaohui Xie 
---
 drivers/mmc/fsl_esdhc.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index 0b37002..73730b3 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -106,7 +106,8 @@ static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct 
mmc_data *data)
xfertyp |= XFERTYP_RSPTYP_48;
 
 #if defined(CONFIG_MX53) || defined(CONFIG_PPC_T4240) || \
-   defined(CONFIG_LS102XA) || defined(CONFIG_LS2085A)
+   defined(CONFIG_LS102XA) || defined(CONFIG_LS2085A) || \
+   defined(CONFIG_PPC_T4160)
if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
xfertyp |= XFERTYP_CMDTYP_ABORT;
 #endif
-- 
2.1.0.27.g96db324

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Re: [U-Boot] arm: mvebu: u-boot does not start on db-88f6820-gp

[Stefan Eichenberger]

Hi Stefan,

On 09/04/2015 06:44 PM, Stefan Roese wrote:

Unfortunately u-boot now hangs if I try to load an image from the 
SD-Card:

e.g. if I run the following command u-boot hangs:
ext4load mmc 0:2 0x200 /boot/kernel.bin

I don't see why exactly it crashes, it seems for me that it's always at
a different position.

Here are two backtraces, always at a different positions:

Here u-boot stopped automatically:
Program received signal SIGTRAP, Trace/breakpoint trap.
0x7ff65d84 in ?? ()
(gdb) backtrace
#0  0x7ff65d84 in ?? ()
#1  0x803663d0 in ?? ()
#2  0x803663d0 in ?? ()
Backtrace stopped: previous frame identical to this frame (corrupt 
stack?)


And here I've got perhaps some more information?
Program received signal SIGSTOP, Stopped (signal).
v7_inval_dcache_level_setway (log2_line_len=,
way_shift=, num_ways=,
 num_sets=, level=) at
arch/arm/cpu/armv7/cache_v7.c:62
62  for (set = num_sets - 1; set >= 0; set--) {
(gdb) backtrace
#0  v7_inval_dcache_level_setway (log2_line_len=,
way_shift=,
 num_ways=, num_sets=,
level=) at arch/arm/cpu/armv7/cache_v7.c:62
#1  v7_maint_dcache_level_setway (operation=, level=9) at
arch/arm/cpu/armv7/cache_v7.c:129
#2  v7_maint_dcache_all (operation=2146852864) at
arch/arm/cpu/armv7/cache_v7.c:147
#3  0xfbe2 in ?? ()
#4  0xfbe2 in ?? ()

Could it be that there is something wrong with cache/dram setup?


Maybe. Hard to tell. Why don't you use "dcache off" before you start 
the command. If this works, then we still have a problem with cache 
(L1 / L2)...


I now did some tests, it seems that the kernel only crashes if I access 
the SD-Card, I'm able to load the kernel from an USB-Device. I tried to 
disable the dcache but the problem still remains.


Another problem I have is that if I try to start a mainline kernel, it 
will crash with the following trace, I think it doesn't find the 
devicetree for some reasons:

## Booting kernel from Legacy Image at 0200 ...
   Image Name:
   Image Type:   ARM Linux Kernel Image (uncompressed)
   Data Size:7258976 Bytes = 6.9 MiB
   Load Address: 8000
   Entry Point:  8000
   Verifying Checksum ... OK
## Flattened Device Tree blob at 0300
   Booting using the fdt blob at 0x300
   Loading Kernel Image ... OK
   Loading Device Tree to 7fb49000, end 7fb4ee70 ... OK

Starting kernel ...

[0.00] Booting Linux on physical CPU 0x0
[0.00] Linux version 4.2.0 (eichenberger@gruene) (gcc version 
4.6.4 (Marvell GCC release 20150204-c4af733b 645
[0.00] CPU: ARMv7 Processor [414fc091] revision 1 (ARMv7), 
cr=10c5387d
[0.00] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing 
instruction cache

[0.00] Machine model: Marvell Armada 385 Development Board
[0.00] bootconsole [earlycon0] enabled
[0.00] Memory policy: Data cache writealloc
[0.00] Unable to handle kernel paging request at virtual address 
3fb49000

[0.00] pgd = c0004000
[0.00] [3fb49000] *pgd=
[0.00] Internal error: Oops: 5 [#1] SMP ARM
[0.00] Modules linked in:
[0.00] CPU: 0 PID: 0 Comm: swapper Not tainted 4.2.0 #67
[0.00] Hardware name: Marvell Armada 380/385 (Device Tree)
[0.00] task: c06bd528 ti: c06b8000 task.ti: c06b8000
[0.00] PC is at fdt_check_header+0x0/0x78
[0.00] LR is at __unflatten_device_tree+0x1c/0x12c
[0.00] pc : []lr : [] psr: 21d3
[0.00] sp : c06b9f38  ip :   fp : ef7fce40
[0.00] r10: c071d2f0  r9 : c05c4d7c  r8 : 3fb49000
[0.00] r7 : c069454c  r6 : c06be514  r5 : c0712f68  r4 : c069454c
[0.00] r3 : c071d308  r2 : c069454c  r1 : c071d2f0  r0 : 3fb49000
[0.00] Flags: nzCv  IRQs off  FIQs off  Mode SVC_32  ISA ARM  
Segment kernel

[0.00] Control: 10c5387d  Table: 404a  DAC: 0015
[0.00] Process swapper (pid: 0, stack limit = 0xc06b8220)
[0.00] Stack: (0xc06b9f38 to 0xc06ba000)
[0.00] 
9f20:    
c070
[0.00] 9f40: 1000 0002f7ff 1000 0007 c069e348 
c069454c c0712f68 c06be514
[0.00] 9f60: c06c2dc0 c06be514 000c c069514c c069e348 
c0679448  10c5387d
[0.00] 9f80: 414fc091   c005aa68 c05c38cc 
c06b9fb4  
[0.00] 9fa0: 0001  c06f4380  414fc091 
  c067693c
[0.00] 9fc0:      
c06a9288  c06f4614
[0.00] 9fe0: c06ba4c0 c06a9284 c06be624 406a  
807c  
[0.00] [] (fdt_check_header) from [] 
(__unflatten_device_tree+0x1c/0x12c)
[0.00] [] (__unflatten_device_tree) from [] 
(unflatten_device_tree+0x1c/0x34)
[0.00] [] (unflatten_device_tree) from [] 
(setup_arch+0x6e8/0x970)
[0.00] [] (setup_arch) from [] 
(start_kernel+0x88/0x3c0)

[0.00] [] (start_kernel) from 

Re: [U-Boot] [PATCH] dm: core: Enable optional use of fdt_translate_address()

[Stephen Warren]

On 09/09/2015 11:07 AM, Simon Glass wrote:
> +Stephen
> 
> Hi Stefan,
> 
> On Thursday, 3 September 2015, Stefan Roese  wrote:
>>
>> The current "simple" address translation simple_bus_translate() is not
>> working on some platforms (e.g. MVEBU). As here more complex "ranges"
>> properties are used in many nodes (multiple tuples etc). This patch
>> enables the optional use of the common fdt_translate_address() function
>> which handles this translation correctly.
>>
>> Signed-off-by: Stefan Roese 
>> Cc: Simon Glass 
>> Cc: Bin Meng 
>> Cc: Marek Vasut 
>> Cc: Masahiro Yamada 
>> ---
>> v2:
>> - Rework code a bit as suggested by Simon. Also added some comments
>>   to make the use of the code paths more clear.
> 
> 
> While this works I'm reluctant to commit it as is. The call to
> fdt_parent_offset() is very slow.
> 
> I wonder if this code should be copied into a new file in
> drivers/core/, tidied up and updated to use dev->parent?
> 
> Other options:
> - Add a library to unflatten the tree - but this would not be very
> useful in SPL or before relocation due to memory/speed constraints
> - Add a helper to find a node parent which uses a cached tree scan to
> build a table of previous nodes (or some other means to go backwards
> in the tree)
> - Worry about it later and go ahead with this patch

I haven't looked at the code in detail, but I'm surprised there's a
Kconfig option for this, for either SPL or main U-Boot. In general, this
feature is simply a required part of parsing DT, so surely the code
should always be enabled. Without it, we're only getting lucky if DT
works (lucky the DT doesn't happen to contain a ranges property). Sure
the code does some searching through the DT, and that's slower than not
doing it, but I don't see how we can support DT without parsing DT
correctly. Now admittedly some platforms' DTs happen not to contain
ranges that require this code in practice. However, I feel that's a bit
of a micro-optimization, and a rather error-prone one at that. What if
someone pulls a more complete DT into U-Boot and suddenly the code is
required and they have to spend ages tracking down their problem to
missing functionality in a core DT parsing API - something they'd be
unlikely to initially suspect.
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[U-Boot] [PATCH 01/14] net/fm: Fix the endian issue of ucode uploading to IRAM

[Gong Qianyu]

From: Shaohui Xie 

Remove the redundant byte swap of the ucode before uploading to IRAM.

Signed-off-by: Hou Zhiqiang 
Signed-off-by: Shaohui Xie 
Signed-off-by: Mingkai Hu 
Signed-off-by: Gong Qianyu 
---
 drivers/net/fm/eth.c | 69 +++-
 drivers/net/fm/fm.c  | 11 +
 2 files changed, 42 insertions(+), 38 deletions(-)

diff --git a/drivers/net/fm/eth.c b/drivers/net/fm/eth.c
index 6702f5a..cd05dbc 100644
--- a/drivers/net/fm/eth.c
+++ b/drivers/net/fm/eth.c
@@ -109,7 +109,7 @@ static int tgec_is_fibre(struct eth_device *dev)
 static u16 muram_readw(u16 *addr)
 {
u32 base = (u32)addr & ~0x3;
-   u32 val32 = *(u32 *)base;
+   u32 val32 = in_be32((u32 *)base);
int byte_pos;
u16 ret;
 
@@ -125,7 +125,7 @@ static u16 muram_readw(u16 *addr)
 static void muram_writew(u16 *addr, u16 val)
 {
u32 base = (u32)addr & ~0x3;
-   u32 org32 = *(u32 *)base;
+   u32 org32 = in_be32((u32 *)base);
u32 val32;
int byte_pos;
 
@@ -135,7 +135,7 @@ static void muram_writew(u16 *addr, u16 val)
else
val32 = (org32 & 0x) | ((u32)val << 16);
 
-   *(u32 *)base = val32;
+   out_be32((u32 *)base, val32);
 }
 
 static void bmi_rx_port_disable(struct fm_bmi_rx_port *rx_port)
@@ -213,10 +213,10 @@ static int fm_eth_rx_port_parameter_init(struct fm_eth 
*fm_eth)
pram_page_offset = (u32)pram - fm_muram_base(fm_eth->fm_index);
 
/* enable global mode- snooping data buffers and BDs */
-   pram->mode = PRAM_MODE_GLOBAL;
+   out_be32(>mode, PRAM_MODE_GLOBAL);
 
/* init the Rx queue descriptor pionter */
-   pram->rxqd_ptr = pram_page_offset + 0x20;
+   out_be32(>rxqd_ptr, pram_page_offset + 0x20);
 
/* set the max receive buffer length, power of 2 */
muram_writew(>mrblr, MAX_RXBUF_LOG2);
@@ -243,10 +243,10 @@ static int fm_eth_rx_port_parameter_init(struct fm_eth 
*fm_eth)
/* init Rx BDs ring */
rxbd = (struct fm_port_bd *)rx_bd_ring_base;
for (i = 0; i < RX_BD_RING_SIZE; i++) {
-   rxbd->status = RxBD_EMPTY;
-   rxbd->len = 0;
-   rxbd->buf_ptr_hi = 0;
-   rxbd->buf_ptr_lo = (u32)rx_buf_pool + i * MAX_RXBUF_LEN;
+   muram_writew(>status, RxBD_EMPTY);
+   muram_writew(>len, 0);
+   muram_writew(>buf_ptr_hi, 0);
+   out_be32(>buf_ptr_lo, (u32)rx_buf_pool + i * 
MAX_RXBUF_LEN);
rxbd++;
}
 
@@ -254,7 +254,7 @@ static int fm_eth_rx_port_parameter_init(struct fm_eth 
*fm_eth)
rxqd = >rxqd;
muram_writew(>gen, 0);
muram_writew(>bd_ring_base_hi, 0);
-   rxqd->bd_ring_base_lo = (u32)rx_bd_ring_base;
+   out_be32(>bd_ring_base_lo, (u32)rx_bd_ring_base);
muram_writew(>bd_ring_size, sizeof(struct fm_port_bd)
* RX_BD_RING_SIZE);
muram_writew(>offset_in, 0);
@@ -285,10 +285,10 @@ static int fm_eth_tx_port_parameter_init(struct fm_eth 
*fm_eth)
pram_page_offset = (u32)pram - fm_muram_base(fm_eth->fm_index);
 
/* enable global mode- snooping data buffers and BDs */
-   pram->mode = PRAM_MODE_GLOBAL;
+   out_be32(>mode, PRAM_MODE_GLOBAL);
 
/* init the Tx queue descriptor pionter */
-   pram->txqd_ptr = pram_page_offset + 0x40;
+   out_be32(>txqd_ptr, pram_page_offset + 0x40);
 
/* alloc Tx buffer descriptors from main memory */
tx_bd_ring_base = malloc(sizeof(struct fm_port_bd)
@@ -304,16 +304,17 @@ static int fm_eth_tx_port_parameter_init(struct fm_eth 
*fm_eth)
/* init Tx BDs ring */
txbd = (struct fm_port_bd *)tx_bd_ring_base;
for (i = 0; i < TX_BD_RING_SIZE; i++) {
-   txbd->status = TxBD_LAST;
-   txbd->len = 0;
-   txbd->buf_ptr_hi = 0;
-   txbd->buf_ptr_lo = 0;
+   muram_writew(>status, TxBD_LAST);
+   muram_writew(>len, 0);
+   muram_writew(>buf_ptr_hi, 0);
+   out_be32(>buf_ptr_lo, 0);
+   txbd++;
}
 
/* set the Tx queue decriptor */
txqd = >txqd;
muram_writew(>bd_ring_base_hi, 0);
-   txqd->bd_ring_base_lo = (u32)tx_bd_ring_base;
+   out_be32(>bd_ring_base_lo, (u32)tx_bd_ring_base);
muram_writew(>bd_ring_size, sizeof(struct fm_port_bd)
* TX_BD_RING_SIZE);
muram_writew(>offset_in, 0);
@@ -368,7 +369,7 @@ static void fmc_tx_port_graceful_stop_enable(struct fm_eth 
*fm_eth)
 
pram = fm_eth->tx_pram;
/* graceful stop transmission of frames */
-   pram->mode |= PRAM_MODE_GRACEFUL_STOP;
+   setbits_be32(>mode, PRAM_MODE_GRACEFUL_STOP);
sync();
 }
 
@@ -378,7 +379,7 @@ static void 

[U-Boot] [PATCH 04/14] net/fm: Add QSGMII PCS init

[Gong Qianyu]

From: Shaohui Xie 

QSGMII PCS needed to be programmed same as SGMII PCS, and there are
four ports in QSGMII PCS, port 0, 1, 2, 3, all the four ports shared
port 0's MDIO controller, so when programming port 0, we continue to
program other three ports.

Signed-off-by: Shaohui Xie 
Signed-off-by: Mingkai Hu 
Signed-off-by: Gong Qianyu 
---
 drivers/net/fm/eth.c | 22 +-
 1 file changed, 17 insertions(+), 5 deletions(-)

diff --git a/drivers/net/fm/eth.c b/drivers/net/fm/eth.c
index a768a90..12eb9b8 100644
--- a/drivers/net/fm/eth.c
+++ b/drivers/net/fm/eth.c
@@ -41,28 +41,39 @@ static void dtsec_configure_serdes(struct fm_eth *priv)
bus.priv = priv->mac->phyregs;
bool sgmii_2500 = (priv->enet_if ==
PHY_INTERFACE_MODE_SGMII_2500) ? true : false;
+   int i = 0;
+
+qsgmii_loop:
+   if ((priv->enet_if == PHY_INTERFACE_MODE_QSGMII) &&
+   ((priv->phyaddr % 4) != 0))
+   return;
 
/* SGMII IF mode + AN enable only for 1G SGMII, not for 2.5G */
value = PHY_SGMII_IF_MODE_SGMII;
if (!sgmii_2500)
value |= PHY_SGMII_IF_MODE_AN;
 
-   memac_mdio_write(, 0, MDIO_DEVAD_NONE, 0x14, value);
+   memac_mdio_write(, i, MDIO_DEVAD_NONE, 0x14, value);
 
/* Dev ability according to SGMII specification */
value = PHY_SGMII_DEV_ABILITY_SGMII;
-   memac_mdio_write(, 0, MDIO_DEVAD_NONE, 0x4, value);
+   memac_mdio_write(, i, MDIO_DEVAD_NONE, 0x4, value);
 
/* Adjust link timer for SGMII  -
1.6 ms in units of 8 ns = 2 * 10^5 = 0x30d40 */
-   memac_mdio_write(, 0, MDIO_DEVAD_NONE, 0x13, 0x3);
-   memac_mdio_write(, 0, MDIO_DEVAD_NONE, 0x12, 0xd40);
+   memac_mdio_write(, i, MDIO_DEVAD_NONE, 0x13, 0x3);
+   memac_mdio_write(, i, MDIO_DEVAD_NONE, 0x12, 0xd40);
 
/* Restart AN */
value = PHY_SGMII_CR_DEF_VAL;
if (!sgmii_2500)
value |= PHY_SGMII_CR_RESET_AN;
-   memac_mdio_write(, 0, MDIO_DEVAD_NONE, 0, value);
+   memac_mdio_write(, i, MDIO_DEVAD_NONE, 0, value);
+
+   if ((priv->enet_if == PHY_INTERFACE_MODE_QSGMII) && (i < 3)) {
+   i++;
+   goto qsgmii_loop;
+   }
 #else
struct dtsec *regs = priv->mac->base;
struct tsec_mii_mng *phyregs = priv->mac->phyregs;
@@ -91,6 +102,7 @@ static void dtsec_init_phy(struct eth_device *dev)
 #endif
 
if (fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII ||
+   fm_eth->enet_if == PHY_INTERFACE_MODE_QSGMII ||
fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII_2500)
dtsec_configure_serdes(fm_eth);
 }
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH v2 08/18] ARM: uniphier: enable simple-bus driver for SPL

[Masahiro Yamada]

In UniPhier device trees, pinctrl device nodes are located under the
simple-bus (AMBA).

This is needed to bind pinctrl devices in SPL.

Signed-off-by: Masahiro Yamada 
---

Changes in v2: None

 configs/ph1_ld4_defconfig  | 1 +
 configs/ph1_pro4_defconfig | 1 +
 configs/ph1_sld8_defconfig | 1 +
 3 files changed, 3 insertions(+)

diff --git a/configs/ph1_ld4_defconfig b/configs/ph1_ld4_defconfig
index 56c215f..74e759a 100644
--- a/configs/ph1_ld4_defconfig
+++ b/configs/ph1_ld4_defconfig
@@ -17,6 +17,7 @@ CONFIG_CMD_PING=y
 CONFIG_CMD_TIME=y
 # CONFIG_CMD_MISC is not set
 CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_SIMPLE_BUS=y
 CONFIG_NAND_DENALI=y
 CONFIG_SYS_NAND_DENALI_64BIT=y
 CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8
diff --git a/configs/ph1_pro4_defconfig b/configs/ph1_pro4_defconfig
index 7624c54..714339a 100644
--- a/configs/ph1_pro4_defconfig
+++ b/configs/ph1_pro4_defconfig
@@ -16,6 +16,7 @@ CONFIG_CMD_PING=y
 CONFIG_CMD_TIME=y
 # CONFIG_CMD_MISC is not set
 CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_SIMPLE_BUS=y
 CONFIG_NAND_DENALI=y
 CONFIG_SYS_NAND_DENALI_64BIT=y
 CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8
diff --git a/configs/ph1_sld8_defconfig b/configs/ph1_sld8_defconfig
index 1a35a77..df0e005 100644
--- a/configs/ph1_sld8_defconfig
+++ b/configs/ph1_sld8_defconfig
@@ -17,6 +17,7 @@ CONFIG_CMD_PING=y
 CONFIG_CMD_TIME=y
 # CONFIG_CMD_MISC is not set
 CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_SIMPLE_BUS=y
 CONFIG_NAND_DENALI=y
 CONFIG_SYS_NAND_DENALI_64BIT=y
 CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8
-- 
1.9.1

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[U-Boot] [PATCH v2 02/18] pinctrl: uniphier: add UniPhier PH1-LD4 pinctrl driver

[Masahiro Yamada]

Add pin configuration and pinmux support for UniPhier PH1-LD4 SoC.

Signed-off-by: Masahiro Yamada 
---

Changes in v2:
  - Add input-enable settings
  - Sync pin-mux table with Linux pinctrl driver

 drivers/pinctrl/uniphier/Kconfig   |   6 ++
 drivers/pinctrl/uniphier/Makefile  |   2 +
 drivers/pinctrl/uniphier/pinctrl-ph1-ld4.c | 133 +
 3 files changed, 141 insertions(+)
 create mode 100644 drivers/pinctrl/uniphier/pinctrl-ph1-ld4.c

diff --git a/drivers/pinctrl/uniphier/Kconfig b/drivers/pinctrl/uniphier/Kconfig
index 29a623d..03593cd 100644
--- a/drivers/pinctrl/uniphier/Kconfig
+++ b/drivers/pinctrl/uniphier/Kconfig
@@ -3,4 +3,10 @@ if ARCH_UNIPHIER
 config PINCTRL_UNIPHIER_CORE
bool
 
+config PINCTRL_UNIPHIER_PH1_LD4
+   bool "UniPhier PH1-LD4 SoC pinctrl driver"
+   depends on MACH_PH1_LD4
+   default y
+   select PINCTRL_UNIPHIER_CORE
+
 endif
diff --git a/drivers/pinctrl/uniphier/Makefile 
b/drivers/pinctrl/uniphier/Makefile
index 748aa1b..b4bd042 100644
--- a/drivers/pinctrl/uniphier/Makefile
+++ b/drivers/pinctrl/uniphier/Makefile
@@ -1 +1,3 @@
 obj-$(CONFIG_PINCTRL_UNIPHIER_CORE)+= pinctrl-uniphier-core.o
+
+obj-$(CONFIG_PINCTRL_UNIPHIER_PH1_LD4) += pinctrl-ph1-ld4.o
diff --git a/drivers/pinctrl/uniphier/pinctrl-ph1-ld4.c 
b/drivers/pinctrl/uniphier/pinctrl-ph1-ld4.c
new file mode 100644
index 000..7c7cfe6
--- /dev/null
+++ b/drivers/pinctrl/uniphier/pinctrl-ph1-ld4.c
@@ -0,0 +1,133 @@
+/*
+ * Copyright (C) 2015 Masahiro Yamada 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+
+#include "pinctrl-uniphier.h"
+
+static const struct uniphier_pinctrl_pin ph1_ld4_pins[] = {
+   UNIPHIER_PINCTRL_PIN(53, 0),
+   UNIPHIER_PINCTRL_PIN(54, 0),
+   UNIPHIER_PINCTRL_PIN(55, 0),
+   UNIPHIER_PINCTRL_PIN(56, 0),
+   UNIPHIER_PINCTRL_PIN(67, 0),
+   UNIPHIER_PINCTRL_PIN(68, 0),
+   UNIPHIER_PINCTRL_PIN(69, 0),
+   UNIPHIER_PINCTRL_PIN(70, 0),
+   UNIPHIER_PINCTRL_PIN(85, 0),
+   UNIPHIER_PINCTRL_PIN(88, 0),
+   UNIPHIER_PINCTRL_PIN(156, 0),
+};
+
+static const unsigned emmc_pins[] = {21, 22, 23, 24, 25, 26, 27};
+static const unsigned emmc_muxvals[] = {0, 1, 1, 1, 1, 1, 1};
+static const unsigned emmc_dat8_pins[] = {28, 29, 30, 31};
+static const unsigned emmc_dat8_muxvals[] = {1, 1, 1, 1};
+static const unsigned i2c0_pins[] = {102, 103};
+static const unsigned i2c0_muxvals[] = {0, 0};
+static const unsigned i2c1_pins[] = {104, 105};
+static const unsigned i2c1_muxvals[] = {0, 0};
+static const unsigned i2c2_pins[] = {108, 109};
+static const unsigned i2c2_muxvals[] = {2, 2};
+static const unsigned i2c3_pins[] = {108, 109};
+static const unsigned i2c3_muxvals[] = {3, 3};
+static const unsigned nand_pins[] = {24, 25, 26, 27, 28, 29, 30, 31, 158, 159,
+160, 161, 162, 163, 164};
+static const unsigned nand_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+   0, 0};
+static const unsigned nand_cs1_pins[] = {22, 23};
+static const unsigned nand_cs1_muxvals[] = {0, 0};
+static const unsigned uart0_pins[] = {85, 88};
+static const unsigned uart0_muxvals[] = {1, 1};
+static const unsigned uart1_pins[] = {155, 156};
+static const unsigned uart1_muxvals[] = {13, 13};
+static const unsigned uart1b_pins[] = {69, 70};
+static const unsigned uart1b_muxvals[] = {23, 23};
+static const unsigned uart2_pins[] = {128, 129};
+static const unsigned uart2_muxvals[] = {13, 13};
+static const unsigned uart3_pins[] = {110, 111};
+static const unsigned uart3_muxvals[] = {1, 1};
+static const unsigned usb0_pins[] = {53, 54};
+static const unsigned usb0_muxvals[] = {0, 0};
+static const unsigned usb1_pins[] = {55, 56};
+static const unsigned usb1_muxvals[] = {0, 0};
+static const unsigned usb2_pins[] = {155, 156};
+static const unsigned usb2_muxvals[] = {4, 4};
+static const unsigned usb2b_pins[] = {67, 68};
+static const unsigned usb2b_muxvals[] = {23, 23};
+static const unsigned sd_pins[] = {44, 45, 46, 47, 48, 49, 50, 51, 52};
+static const unsigned sd_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0};
+
+static const struct uniphier_pinctrl_group ph1_ld4_groups[] = {
+   UNIPHIER_PINCTRL_GROUP(emmc),
+   UNIPHIER_PINCTRL_GROUP(emmc_dat8),
+   UNIPHIER_PINCTRL_GROUP(i2c0),
+   UNIPHIER_PINCTRL_GROUP(i2c1),
+   UNIPHIER_PINCTRL_GROUP(i2c2),
+   UNIPHIER_PINCTRL_GROUP(i2c3),
+   UNIPHIER_PINCTRL_GROUP(nand),
+   UNIPHIER_PINCTRL_GROUP(nand_cs1),
+   UNIPHIER_PINCTRL_GROUP(uart0),
+   UNIPHIER_PINCTRL_GROUP(uart1),
+   UNIPHIER_PINCTRL_GROUP(uart1b),
+   UNIPHIER_PINCTRL_GROUP(uart2),
+   UNIPHIER_PINCTRL_GROUP(uart3),
+   UNIPHIER_PINCTRL_GROUP(usb0),
+   UNIPHIER_PINCTRL_GROUP(usb1),
+   UNIPHIER_PINCTRL_GROUP(usb2),
+   UNIPHIER_PINCTRL_GROUP(usb2b),
+   

[U-Boot] [PATCH v2 07/18] pinctrl: uniphier: add UniPhier PH1-LD6b pinctrl driver

[Masahiro Yamada]

Add pin configuration and pinmux support for UniPhier PH1-LD6b SoC.

Signed-off-by: Masahiro Yamada 
---

Changes in v2:
  - Add input-enable settings
  - Sync pin-mux table with Linux pinctrl driver

 drivers/pinctrl/uniphier/Kconfig|   6 ++
 drivers/pinctrl/uniphier/Makefile   |   1 +
 drivers/pinctrl/uniphier/pinctrl-ph1-ld6b.c | 133 
 3 files changed, 140 insertions(+)
 create mode 100644 drivers/pinctrl/uniphier/pinctrl-ph1-ld6b.c

diff --git a/drivers/pinctrl/uniphier/Kconfig b/drivers/pinctrl/uniphier/Kconfig
index 7f729b6..757edce 100644
--- a/drivers/pinctrl/uniphier/Kconfig
+++ b/drivers/pinctrl/uniphier/Kconfig
@@ -33,4 +33,10 @@ config PINCTRL_UNIPHIER_PROXSTREAM2
default y
select PINCTRL_UNIPHIER_CORE
 
+config PINCTRL_UNIPHIER_PH1_LD6B
+   bool "UniPhier PH1-LD6b SoC pinctrl driver"
+   depends on MACH_PH1_LD6B
+   default y
+   select PINCTRL_UNIPHIER_CORE
+
 endif
diff --git a/drivers/pinctrl/uniphier/Makefile 
b/drivers/pinctrl/uniphier/Makefile
index aed038c..e215b10 100644
--- a/drivers/pinctrl/uniphier/Makefile
+++ b/drivers/pinctrl/uniphier/Makefile
@@ -5,3 +5,4 @@ obj-$(CONFIG_PINCTRL_UNIPHIER_PH1_PRO4) += 
pinctrl-ph1-pro4.o
 obj-$(CONFIG_PINCTRL_UNIPHIER_PH1_SLD8)+= pinctrl-ph1-sld8.o
 obj-$(CONFIG_PINCTRL_UNIPHIER_PH1_PRO5)+= pinctrl-ph1-pro5.o
 obj-$(CONFIG_PINCTRL_UNIPHIER_PROXSTREAM2) += pinctrl-proxstream2.o
+obj-$(CONFIG_PINCTRL_UNIPHIER_PH1_LD6B)+= pinctrl-ph1-ld6b.o
diff --git a/drivers/pinctrl/uniphier/pinctrl-ph1-ld6b.c 
b/drivers/pinctrl/uniphier/pinctrl-ph1-ld6b.c
new file mode 100644
index 000..2ad16c3
--- /dev/null
+++ b/drivers/pinctrl/uniphier/pinctrl-ph1-ld6b.c
@@ -0,0 +1,133 @@
+/*
+ * Copyright (C) 2015 Masahiro Yamada 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+
+#include "pinctrl-uniphier.h"
+
+static const struct uniphier_pinctrl_pin ph1_ld6b_pins[] = {
+   UNIPHIER_PINCTRL_PIN(113, 0),
+   UNIPHIER_PINCTRL_PIN(114, 0),
+   UNIPHIER_PINCTRL_PIN(115, 0),
+   UNIPHIER_PINCTRL_PIN(116, 0),
+   UNIPHIER_PINCTRL_PIN(217, 0),
+   UNIPHIER_PINCTRL_PIN(218, 0),
+   UNIPHIER_PINCTRL_PIN(219, 0),
+   UNIPHIER_PINCTRL_PIN(220, 0),
+};
+
+static const unsigned emmc_pins[] = {36, 37, 38, 39, 40, 41, 42};
+static const unsigned emmc_muxvals[] = {1, 1, 1, 1, 1, 1, 1};
+static const unsigned emmc_dat8_pins[] = {43, 44, 45, 46};
+static const unsigned emmc_dat8_muxvals[] = {1, 1, 1, 1};
+static const unsigned i2c0_pins[] = {109, 110};
+static const unsigned i2c0_muxvals[] = {0, 0};
+static const unsigned i2c1_pins[] = {111, 112};
+static const unsigned i2c1_muxvals[] = {0, 0};
+static const unsigned i2c2_pins[] = {115, 116};
+static const unsigned i2c2_muxvals[] = {1, 1};
+static const unsigned i2c3_pins[] = {118, 119};
+static const unsigned i2c3_muxvals[] = {1, 1};
+static const unsigned nand_pins[] = {30, 31, 32, 33, 34, 35, 36, 39, 40, 41,
+42, 43, 44, 45, 46};
+static const unsigned nand_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+   0, 0};
+static const unsigned nand_cs1_pins[] = {37, 38};
+static const unsigned nand_cs1_muxvals[] = {0, 0};
+static const unsigned uart0_pins[] = {135, 136};
+static const unsigned uart0_muxvals[] = {3, 3};
+static const unsigned uart0b_pins[] = {11, 12};
+static const unsigned uart0b_muxvals[] = {2, 2};
+static const unsigned uart1_pins[] = {115, 116};
+static const unsigned uart1_muxvals[] = {0, 0};
+static const unsigned uart1b_pins[] = {113, 114};
+static const unsigned uart1b_muxvals[] = {1, 1};
+static const unsigned uart2_pins[] = {113, 114};
+static const unsigned uart2_muxvals[] = {2, 2};
+static const unsigned uart2b_pins[] = {86, 87};
+static const unsigned uart2b_muxvals[] = {1, 1};
+static const unsigned usb0_pins[] = {56, 57};
+static const unsigned usb0_muxvals[] = {0, 0};
+static const unsigned usb1_pins[] = {58, 59};
+static const unsigned usb1_muxvals[] = {0, 0};
+static const unsigned usb2_pins[] = {60, 61};
+static const unsigned usb2_muxvals[] = {0, 0};
+static const unsigned usb3_pins[] = {62, 63};
+static const unsigned usb3_muxvals[] = {0, 0};
+static const unsigned sd_pins[] = {47, 48, 49, 50, 51, 52, 53, 54, 55};
+static const unsigned sd_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0};
+
+static const struct uniphier_pinctrl_group ph1_ld6b_groups[] = {
+   UNIPHIER_PINCTRL_GROUP(emmc),
+   UNIPHIER_PINCTRL_GROUP(emmc_dat8),
+   UNIPHIER_PINCTRL_GROUP(i2c0),
+   UNIPHIER_PINCTRL_GROUP(i2c1),
+   UNIPHIER_PINCTRL_GROUP(i2c2),
+   UNIPHIER_PINCTRL_GROUP(i2c3),
+   UNIPHIER_PINCTRL_GROUP(nand),
+   UNIPHIER_PINCTRL_GROUP(nand_cs1),
+   UNIPHIER_PINCTRL_GROUP(uart0),
+   UNIPHIER_PINCTRL_GROUP(uart0b),
+   UNIPHIER_PINCTRL_GROUP(uart1),
+  

[U-Boot] [PATCH v2 04/18] pinctrl: uniphier: add UniPhier PH1-sLD8 pinctrl driver

[Masahiro Yamada]

Add pin configuration and pinmux support for UniPhier PH1-sLD8 SoC.

Signed-off-by: Masahiro Yamada 
---

Changes in v2:
  - Add input-enable settings
  - Sync pin-mux table with Linux pinctrl driver

 drivers/pinctrl/uniphier/Kconfig|   6 ++
 drivers/pinctrl/uniphier/Makefile   |   1 +
 drivers/pinctrl/uniphier/pinctrl-ph1-sld8.c | 141 
 3 files changed, 148 insertions(+)
 create mode 100644 drivers/pinctrl/uniphier/pinctrl-ph1-sld8.c

diff --git a/drivers/pinctrl/uniphier/Kconfig b/drivers/pinctrl/uniphier/Kconfig
index c417a9f..a156a28 100644
--- a/drivers/pinctrl/uniphier/Kconfig
+++ b/drivers/pinctrl/uniphier/Kconfig
@@ -15,4 +15,10 @@ config PINCTRL_UNIPHIER_PH1_PRO4
default y
select PINCTRL_UNIPHIER_CORE
 
+config PINCTRL_UNIPHIER_PH1_SLD8
+   bool "UniPhier PH1-sLD8 SoC pinctrl driver"
+   depends on MACH_PH1_SLD8
+   default y
+   select PINCTRL_UNIPHIER_CORE
+
 endif
diff --git a/drivers/pinctrl/uniphier/Makefile 
b/drivers/pinctrl/uniphier/Makefile
index b1b597e..3349fff 100644
--- a/drivers/pinctrl/uniphier/Makefile
+++ b/drivers/pinctrl/uniphier/Makefile
@@ -2,3 +2,4 @@ obj-$(CONFIG_PINCTRL_UNIPHIER_CORE) += 
pinctrl-uniphier-core.o
 
 obj-$(CONFIG_PINCTRL_UNIPHIER_PH1_LD4) += pinctrl-ph1-ld4.o
 obj-$(CONFIG_PINCTRL_UNIPHIER_PH1_PRO4)+= pinctrl-ph1-pro4.o
+obj-$(CONFIG_PINCTRL_UNIPHIER_PH1_SLD8)+= pinctrl-ph1-sld8.o
diff --git a/drivers/pinctrl/uniphier/pinctrl-ph1-sld8.c 
b/drivers/pinctrl/uniphier/pinctrl-ph1-sld8.c
new file mode 100644
index 000..ccc1ac0
--- /dev/null
+++ b/drivers/pinctrl/uniphier/pinctrl-ph1-sld8.c
@@ -0,0 +1,141 @@
+/*
+ * Copyright (C) 2015 Masahiro Yamada 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+
+#include "pinctrl-uniphier.h"
+
+static const struct uniphier_pinctrl_pin ph1_sld8_pins[] = {
+   UNIPHIER_PINCTRL_PIN(32, 8),
+   UNIPHIER_PINCTRL_PIN(33, 8),
+   UNIPHIER_PINCTRL_PIN(34, 8),
+   UNIPHIER_PINCTRL_PIN(35, 8),
+   UNIPHIER_PINCTRL_PIN(36, 8),
+   UNIPHIER_PINCTRL_PIN(37, 8),
+   UNIPHIER_PINCTRL_PIN(38, 8),
+   UNIPHIER_PINCTRL_PIN(39, 8),
+   UNIPHIER_PINCTRL_PIN(40, 9),
+   UNIPHIER_PINCTRL_PIN(41, 0),
+   UNIPHIER_PINCTRL_PIN(42, 0),
+   UNIPHIER_PINCTRL_PIN(43, 0),
+   UNIPHIER_PINCTRL_PIN(44, 0),
+   UNIPHIER_PINCTRL_PIN(70, 0),
+   UNIPHIER_PINCTRL_PIN(71, 0),
+   UNIPHIER_PINCTRL_PIN(102, 10),
+   UNIPHIER_PINCTRL_PIN(103, 10),
+   UNIPHIER_PINCTRL_PIN(104, 11),
+   UNIPHIER_PINCTRL_PIN(105, 11),
+   UNIPHIER_PINCTRL_PIN(108, 13),
+   UNIPHIER_PINCTRL_PIN(109, 13),
+   UNIPHIER_PINCTRL_PIN(112, 0),
+   UNIPHIER_PINCTRL_PIN(113, 0),
+   UNIPHIER_PINCTRL_PIN(114, 0),
+   UNIPHIER_PINCTRL_PIN(115, 0),
+};
+
+static const unsigned emmc_pins[] = {21, 22, 23, 24, 25, 26, 27};
+static const unsigned emmc_muxvals[] = {1, 1, 1, 1, 1, 1, 1};
+static const unsigned emmc_dat8_pins[] = {28, 29, 30, 31};
+static const unsigned emmc_dat8_muxvals[] = {1, 1, 1, 1};
+static const unsigned i2c0_pins[] = {102, 103};
+static const unsigned i2c0_muxvals[] = {0, 0};
+static const unsigned i2c1_pins[] = {104, 105};
+static const unsigned i2c1_muxvals[] = {0, 0};
+static const unsigned i2c2_pins[] = {108, 109};
+static const unsigned i2c2_muxvals[] = {2, 2};
+static const unsigned i2c3_pins[] = {108, 109};
+static const unsigned i2c3_muxvals[] = {3, 3};
+static const unsigned nand_pins[] = {15, 16, 17, 18, 19, 20, 21, 24, 25, 26,
+27, 28, 29, 30, 31};
+static const unsigned nand_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+   0, 0};
+static const unsigned nand_cs1_pins[] = {22, 23};
+static const unsigned nand_cs1_muxvals[] = {0, 0};
+static const unsigned uart0_pins[] = {70, 71};
+static const unsigned uart0_muxvals[] = {3, 3};
+static const unsigned uart1_pins[] = {114, 115};
+static const unsigned uart1_muxvals[] = {0, 0};
+static const unsigned uart2_pins[] = {112, 113};
+static const unsigned uart2_muxvals[] = {1, 1};
+static const unsigned uart3_pins[] = {110, 111};
+static const unsigned uart3_muxvals[] = {1, 1};
+static const unsigned usb0_pins[] = {41, 42};
+static const unsigned usb0_muxvals[] = {0, 0};
+static const unsigned usb1_pins[] = {43, 44};
+static const unsigned usb1_muxvals[] = {0, 0};
+static const unsigned usb2_pins[] = {114, 115};
+static const unsigned usb2_muxvals[] = {1, 1};
+static const unsigned sd_pins[] = {32, 33, 34, 35, 36, 37, 38, 39, 40};
+static const unsigned sd_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0};
+
+static const struct uniphier_pinctrl_group ph1_sld8_groups[] = {
+   UNIPHIER_PINCTRL_GROUP(emmc),
+   UNIPHIER_PINCTRL_GROUP(emmc_dat8),
+   UNIPHIER_PINCTRL_GROUP(i2c0),
+   UNIPHIER_PINCTRL_GROUP(i2c1),
+   

[U-Boot] [PATCH v5 4/4] x86: quark: Add PCIe/USB static register programming after memory init

[Bin Meng]

This adds static register programming for PCIe and USB after memory
init as required by Quark firmware writer guide. Although not doing
this did not cause any malfunction, just do it for safety.

Signed-off-by: Bin Meng 
Acked-by: Simon Glass 

---

Changes in v5: None
Changes in v3: None
Changes in v2:
- New patch to add PCIe/USB static register programming after memory init

 arch/x86/cpu/quark/quark.c  | 64 +
 arch/x86/include/asm/arch-quark/quark.h | 22 
 include/configs/galileo.h   |  1 +
 3 files changed, 87 insertions(+)

diff --git a/arch/x86/cpu/quark/quark.c b/arch/x86/cpu/quark/quark.c
index caa3875..934250b 100644
--- a/arch/x86/cpu/quark/quark.c
+++ b/arch/x86/cpu/quark/quark.c
@@ -223,6 +223,53 @@ void reset_cpu(ulong addr)
x86_full_reset();
 }
 
+static void quark_pcie_init(void)
+{
+   u32 val;
+
+   /* PCIe upstream non-posted & posted request size */
+   qrk_pci_write_config_dword(QUARK_PCIE0, PCIE_RP_CCFG,
+  CCFG_UPRS | CCFG_UNRS);
+   qrk_pci_write_config_dword(QUARK_PCIE1, PCIE_RP_CCFG,
+  CCFG_UPRS | CCFG_UNRS);
+
+   /* PCIe packet fast transmit mode (IPF) */
+   qrk_pci_write_config_dword(QUARK_PCIE0, PCIE_RP_MPC2, MPC2_IPF);
+   qrk_pci_write_config_dword(QUARK_PCIE1, PCIE_RP_MPC2, MPC2_IPF);
+
+   /* PCIe message bus idle counter (SBIC) */
+   qrk_pci_read_config_dword(QUARK_PCIE0, PCIE_RP_MBC, );
+   val |= MBC_SBIC;
+   qrk_pci_write_config_dword(QUARK_PCIE0, PCIE_RP_MBC, val);
+   qrk_pci_read_config_dword(QUARK_PCIE1, PCIE_RP_MBC, );
+   val |= MBC_SBIC;
+   qrk_pci_write_config_dword(QUARK_PCIE1, PCIE_RP_MBC, val);
+}
+
+static void quark_usb_init(void)
+{
+   u32 bar;
+
+   /* Change USB EHCI packet buffer OUT/IN threshold */
+   qrk_pci_read_config_dword(QUARK_USB_EHCI, PCI_BASE_ADDRESS_0, );
+   writel((0x7f << 16) | 0x7f, bar + EHCI_INSNREG01);
+
+   /* Disable USB device interrupts */
+   qrk_pci_read_config_dword(QUARK_USB_DEVICE, PCI_BASE_ADDRESS_0, );
+   writel(0x7f, bar + USBD_INT_MASK);
+   writel((0xf << 16) | 0xf, bar + USBD_EP_INT_MASK);
+   writel((0xf << 16) | 0xf, bar + USBD_EP_INT_STS);
+}
+
+int arch_early_init_r(void)
+{
+   quark_pcie_init();
+
+   quark_usb_init();
+
+   return 0;
+}
+
 int cpu_mmc_init(bd_t *bis)
 {
return pci_mmc_init("Quark SDHCI", mmc_supported,
@@ -256,3 +303,20 @@ int arch_misc_init(void)
 {
return pirq_init();
 }
+
+void board_final_cleanup(void)
+{
+   struct quark_rcba *rcba;
+   u32 base, val;
+
+   qrk_pci_read_config_dword(QUARK_LEGACY_BRIDGE, LB_RCBA, );
+   base &= ~MEM_BAR_EN;
+   rcba = (struct quark_rcba *)base;
+
+   /* Initialize 'Component ID' to zero */
+   val = readl(>esd);
+   val &= ~0xff;
+   writel(val, >esd);
+
+   return;
+}
diff --git a/arch/x86/include/asm/arch-quark/quark.h 
b/arch/x86/include/asm/arch-quark/quark.h
index 5d81976..eb3afbf 100644
--- a/arch/x86/include/asm/arch-quark/quark.h
+++ b/arch/x86/include/asm/arch-quark/quark.h
@@ -88,6 +88,20 @@
 /* 64KiB of RMU binary in flash */
 #define RMU_BINARY_SIZE0x1
 
+/* PCIe Root Port Configuration Registers */
+
+#define PCIE_RP_CCFG   0xd0
+#define CCFG_UPRS  (1 << 14)
+#define CCFG_UNRS  (1 << 15)
+#define CCFG_UNSD  (1 << 23)
+#define CCFG_UPSD  (1 << 24)
+
+#define PCIE_RP_MPC2   0xd4
+#define MPC2_IPF   (1 << 11)
+
+#define PCIE_RP_MBC0xf4
+#define MBC_SBIC   (3 << 16)
+
 /* Legacy Bridge PCI Configuration Registers */
 #define LB_GBA 0x44
 #define LB_PM1BLK  0x48
@@ -100,6 +114,14 @@
 #define LB_BC  0xd8
 #define LB_RCBA0xf0
 
+/* USB EHCI memory-mapped registers */
+#define EHCI_INSNREG01 0x94
+
+/* USB device memory-mapped registers */
+#define USBD_INT_MASK  0x410
+#define USBD_EP_INT_STS0x414
+#define USBD_EP_INT_MASK   0x418
+
 #ifndef __ASSEMBLY__
 
 /* Root Complex Register Block */
diff --git a/include/configs/galileo.h b/include/configs/galileo.h
index b7ec279..ba6c8f1 100644
--- a/include/configs/galileo.h
+++ b/include/configs/galileo.h
@@ -15,6 +15,7 @@
 
 #define CONFIG_SYS_MONITOR_LEN (1 << 20)
 #define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_ARCH_EARLY_INIT_R
 #define CONFIG_ARCH_MISC_INIT
 
 /* ns16550 UART is memory-mapped in Quark SoC */
-- 
1.8.2.1

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[U-Boot] [PATCH v5 1/4] dm: pci: Add an inline API to test if a device is on a PCI bus

[Bin Meng]

Introduce device_is_on_pci_bus() which can be utilized by driver
to test if a device is on a PCI bus.

Signed-off-by: Bin Meng 

---

Changes in v5:
- Move the inline API from include/pci.h to include/dm/device.h to
  resolve the cyclic dependency

Changes in v3: None
Changes in v2:
- New patch to add an inline API to test if a device is on a PCI bus

 drivers/pci/pci-uclass.c |  4 ++--
 include/dm/device.h  | 11 +++
 2 files changed, 13 insertions(+), 2 deletions(-)

diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c
index ea70853..0756bbe 100644
--- a/drivers/pci/pci-uclass.c
+++ b/drivers/pci/pci-uclass.c
@@ -238,7 +238,7 @@ int dm_pci_write_config(struct udevice *dev, int offset, 
unsigned long value,
 {
struct udevice *bus;
 
-   for (bus = dev; device_get_uclass_id(bus->parent) == UCLASS_PCI;)
+   for (bus = dev; device_is_on_pci_bus(bus);)
bus = bus->parent;
return pci_bus_write_config(bus, pci_get_bdf(dev), offset, value, size);
 }
@@ -303,7 +303,7 @@ int dm_pci_read_config(struct udevice *dev, int offset, 
unsigned long *valuep,
 {
struct udevice *bus;
 
-   for (bus = dev; device_get_uclass_id(bus->parent) == UCLASS_PCI;)
+   for (bus = dev; device_is_on_pci_bus(bus);)
bus = bus->parent;
return pci_bus_read_config(bus, pci_get_bdf(dev), offset, valuep,
   size);
diff --git a/include/dm/device.h b/include/dm/device.h
index a239be6..8519612 100644
--- a/include/dm/device.h
+++ b/include/dm/device.h
@@ -485,6 +485,17 @@ bool device_is_last_sibling(struct udevice *dev);
  */
 int device_set_name(struct udevice *dev, const char *name);
 
+/**
+ * device_is_on_pci_bus - Test if a device is on a PCI bus
+ *
+ * @dev:   device to test
+ * @return:true if it is on a PCI bus, false otherwise
+ */
+static inline bool device_is_on_pci_bus(struct udevice *dev)
+{
+   return device_get_uclass_id(dev->parent) == UCLASS_PCI;
+}
+
 /* device resource management */
 typedef void (*dr_release_t)(struct udevice *dev, void *res);
 typedef int (*dr_match_t)(struct udevice *dev, void *res, void *match_data);
-- 
1.8.2.1

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[U-Boot] [PATCH v5 3/4] x86: Convert to use driver model eth on quark/galileo

[Bin Meng]

Convert to use DM version of Designware ethernet driver on Intel
quark/galileo.

Signed-off-by: Bin Meng 
Acked-by: Simon Glass 

---

Changes in v5: None
Changes in v3: None
Changes in v2: None

 arch/x86/cpu/quark/quark.c | 19 ---
 configs/galileo_defconfig  |  2 +-
 2 files changed, 1 insertion(+), 20 deletions(-)

diff --git a/arch/x86/cpu/quark/quark.c b/arch/x86/cpu/quark/quark.c
index 637c370..caa3875 100644
--- a/arch/x86/cpu/quark/quark.c
+++ b/arch/x86/cpu/quark/quark.c
@@ -6,8 +6,6 @@
 
 #include 
 #include 
-#include 
-#include 
 #include 
 #include 
 #include 
@@ -231,23 +229,6 @@ int cpu_mmc_init(bd_t *bis)
ARRAY_SIZE(mmc_supported));
 }
 
-int cpu_eth_init(bd_t *bis)
-{
-   u32 base;
-   int ret0, ret1;
-
-   qrk_pci_read_config_dword(QUARK_EMAC0, PCI_BASE_ADDRESS_0, );
-   ret0 = designware_initialize(base, PHY_INTERFACE_MODE_RMII);
-
-   qrk_pci_read_config_dword(QUARK_EMAC1, PCI_BASE_ADDRESS_0, );
-   ret1 = designware_initialize(base, PHY_INTERFACE_MODE_RMII);
-
-   if (ret0 < 0 && ret1 < 0)
-   return -1;
-   else
-   return 0;
-}
-
 void cpu_irq_init(void)
 {
struct quark_rcba *rcba;
diff --git a/configs/galileo_defconfig b/configs/galileo_defconfig
index d05154e..9623986 100644
--- a/configs/galileo_defconfig
+++ b/configs/galileo_defconfig
@@ -12,7 +12,7 @@ CONFIG_BOOTSTAGE_REPORT=y
 CONFIG_CMD_BOOTSTAGE=y
 CONFIG_OF_CONTROL=y
 CONFIG_SPI_FLASH=y
-CONFIG_NETDEVICES=y
+CONFIG_DM_ETH=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_DM_PCI=y
 CONFIG_DM_RTC=y
-- 
1.8.2.1

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[U-Boot] [PATCH v5 2/4] net: designware: Add support to PCI designware devices

[Bin Meng]

The Designware ethernet controller is also seen on PCI bus, e.g.
on Intel Quark SoC. Add this support in the DM version driver.

Signed-off-by: Bin Meng 

---

Changes in v5:
- Wrap PCI device support with CONFIG_DM_PCI

Changes in v3:
- Change to use dm_pci_read_config32()

Changes in v2:
- Change to use device_is_on_pci_bus()

 drivers/net/designware.c | 42 ++
 1 file changed, 42 insertions(+)

diff --git a/drivers/net/designware.c b/drivers/net/designware.c
index ae78d21..6433896 100644
--- a/drivers/net/designware.c
+++ b/drivers/net/designware.c
@@ -14,6 +14,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -558,6 +559,22 @@ static int designware_eth_write_hwaddr(struct udevice *dev)
return _dw_write_hwaddr(priv, pdata->enetaddr);
 }
 
+static int designware_eth_bind(struct udevice *dev)
+{
+#ifdef CONFIG_DM_PCI
+   static int num_cards;
+   char name[20];
+
+   /* Create a unique device name for PCI type devices */
+   if (device_is_on_pci_bus(dev)) {
+   sprintf(name, "eth_designware#%u", num_cards++);
+   device_set_name(dev, name);
+   }
+#endif
+
+   return 0;
+}
+
 static int designware_eth_probe(struct udevice *dev)
 {
struct eth_pdata *pdata = dev_get_platdata(dev);
@@ -565,6 +582,23 @@ static int designware_eth_probe(struct udevice *dev)
u32 iobase = pdata->iobase;
int ret;
 
+#ifdef CONFIG_DM_PCI
+   /*
+* If we are on PCI bus, either directly attached to a PCI root port,
+* or via a PCI bridge, fill in platdata before we probe the hardware.
+*/
+   if (device_is_on_pci_bus(dev)) {
+   pci_dev_t bdf = pci_get_bdf(dev);
+
+   dm_pci_read_config32(dev, PCI_BASE_ADDRESS_0, );
+   iobase &= PCI_BASE_ADDRESS_MEM_MASK;
+   iobase = pci_mem_to_phys(bdf, iobase);
+
+   pdata->iobase = iobase;
+   pdata->phy_interface = PHY_INTERFACE_MODE_RMII;
+   }
+#endif
+
debug("%s, iobase=%x, priv=%p\n", __func__, iobase, priv);
priv->mac_regs_p = (struct eth_mac_regs *)iobase;
priv->dma_regs_p = (struct eth_dma_regs *)(iobase + DW_DMA_BASE_OFFSET);
@@ -617,10 +651,18 @@ U_BOOT_DRIVER(eth_designware) = {
.id = UCLASS_ETH,
.of_match = designware_eth_ids,
.ofdata_to_platdata = designware_eth_ofdata_to_platdata,
+   .bind   = designware_eth_bind,
.probe  = designware_eth_probe,
.ops= _eth_ops,
.priv_auto_alloc_size = sizeof(struct dw_eth_dev),
.platdata_auto_alloc_size = sizeof(struct eth_pdata),
.flags = DM_FLAG_ALLOC_PRIV_DMA,
 };
+
+static struct pci_device_id supported[] = {
+   { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QRK_EMAC) },
+   { }
+};
+
+U_BOOT_PCI_DEVICE(eth_designware, supported);
 #endif
-- 
1.8.2.1

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[U-Boot] [PATCH 06/14] net/fm: fix compile warnings for 64-bit platform

[Gong Qianyu]

This patch fixes such compile warnings:

drivers/net/fm/eth.c: In function 'fm_eth_recv':
drivers/net/fm/eth.c:549:11: warning: cast to pointer from integer of
different size [-Wint-to-pointer-cast]
data = (u8 *)in_be32(>buf_ptr_lo);
drivers/net/fm/fm.c: In function 'fm_muram_alloc':
drivers/net/fm/fm.c:52:9: warning: cast to pointer from integer of
different size [-Wint-to-pointer-cast]
memset((void *)ret, 0, size);
drivers/net/fm/fm.c: In function 'fm_init_muram':
drivers/net/fm/fm.c:59:13: warning: cast from pointer to integer of
different size [-Wpointer-to-int-cast]
u32 base = (u32)reg;

Just make the cast explicit for them.

Signed-off-by: Gong Qianyu 
---
 drivers/net/fm/eth.c | 31 ---
 drivers/net/fm/fm.c  |  4 ++--
 2 files changed, 18 insertions(+), 17 deletions(-)

diff --git a/drivers/net/fm/eth.c b/drivers/net/fm/eth.c
index 12eb9b8..6ef0afb 100644
--- a/drivers/net/fm/eth.c
+++ b/drivers/net/fm/eth.c
@@ -120,12 +120,12 @@ static int tgec_is_fibre(struct eth_device *dev)
 
 static u16 muram_readw(u16 *addr)
 {
-   u32 base = (u32)addr & ~0x3;
+   ulong base = (ulong)addr & ~0x3;
u32 val32 = in_be32((u32 *)base);
int byte_pos;
u16 ret;
 
-   byte_pos = (u32)addr & 0x3;
+   byte_pos = (ulong)addr & 0x3;
if (byte_pos)
ret = (u16)(val32 & 0x);
else
@@ -136,12 +136,12 @@ static u16 muram_readw(u16 *addr)
 
 static void muram_writew(u16 *addr, u16 val)
 {
-   u32 base = (u32)addr & ~0x3;
+   ulong base = (ulong)addr & ~0x3;
u32 org32 = in_be32((u32 *)base);
u32 val32;
int byte_pos;
 
-   byte_pos = (u32)addr & 0x3;
+   byte_pos = (ulong)addr & 0x3;
if (byte_pos)
val32 = (org32 & 0x) | val;
else
@@ -217,12 +217,12 @@ static int fm_eth_rx_port_parameter_init(struct fm_eth 
*fm_eth)
int i;
 
/* alloc global parameter ram at MURAM */
-   pram = (struct fm_port_global_pram *)fm_muram_alloc(fm_eth->fm_index,
-   FM_PRAM_SIZE, FM_PRAM_ALIGN);
+   pram = (struct fm_port_global_pram *)(ulong)fm_muram_alloc(
+   fm_eth->fm_index, FM_PRAM_SIZE, FM_PRAM_ALIGN);
fm_eth->rx_pram = pram;
 
/* parameter page offset to MURAM */
-   pram_page_offset = (u32)pram - fm_muram_base(fm_eth->fm_index);
+   pram_page_offset = (u32)(ulong)pram - fm_muram_base(fm_eth->fm_index);
 
/* enable global mode- snooping data buffers and BDs */
out_be32(>mode, PRAM_MODE_GLOBAL);
@@ -258,7 +258,8 @@ static int fm_eth_rx_port_parameter_init(struct fm_eth 
*fm_eth)
muram_writew(>status, RxBD_EMPTY);
muram_writew(>len, 0);
muram_writew(>buf_ptr_hi, 0);
-   out_be32(>buf_ptr_lo, (u32)rx_buf_pool + i * 
MAX_RXBUF_LEN);
+   out_be32(>buf_ptr_lo, (u32)(ulong)rx_buf_pool +
+   i * MAX_RXBUF_LEN);
rxbd++;
}
 
@@ -266,7 +267,7 @@ static int fm_eth_rx_port_parameter_init(struct fm_eth 
*fm_eth)
rxqd = >rxqd;
muram_writew(>gen, 0);
muram_writew(>bd_ring_base_hi, 0);
-   out_be32(>bd_ring_base_lo, (u32)rx_bd_ring_base);
+   out_be32(>bd_ring_base_lo, (u32)(ulong)rx_bd_ring_base);
muram_writew(>bd_ring_size, sizeof(struct fm_port_bd)
* RX_BD_RING_SIZE);
muram_writew(>offset_in, 0);
@@ -289,12 +290,12 @@ static int fm_eth_tx_port_parameter_init(struct fm_eth 
*fm_eth)
int i;
 
/* alloc global parameter ram at MURAM */
-   pram = (struct fm_port_global_pram *)fm_muram_alloc(fm_eth->fm_index,
-   FM_PRAM_SIZE, FM_PRAM_ALIGN);
+   pram = (struct fm_port_global_pram *)(ulong)fm_muram_alloc(
+   fm_eth->fm_index, FM_PRAM_SIZE, FM_PRAM_ALIGN);
fm_eth->tx_pram = pram;
 
/* parameter page offset to MURAM */
-   pram_page_offset = (u32)pram - fm_muram_base(fm_eth->fm_index);
+   pram_page_offset = (u32)(ulong)pram - fm_muram_base(fm_eth->fm_index);
 
/* enable global mode- snooping data buffers and BDs */
out_be32(>mode, PRAM_MODE_GLOBAL);
@@ -326,7 +327,7 @@ static int fm_eth_tx_port_parameter_init(struct fm_eth 
*fm_eth)
/* set the Tx queue decriptor */
txqd = >txqd;
muram_writew(>bd_ring_base_hi, 0);
-   out_be32(>bd_ring_base_lo, (u32)tx_bd_ring_base);
+   out_be32(>bd_ring_base_lo, (u32)(ulong)tx_bd_ring_base);
muram_writew(>bd_ring_size, sizeof(struct fm_port_bd)
* TX_BD_RING_SIZE);
muram_writew(>offset_in, 0);
@@ -494,7 +495,7 @@ static int fm_eth_send(struct eth_device *dev, void *buf, 
int len)
}
/* setup TxBD */
muram_writew(>buf_ptr_hi, 0);
-   out_be32(>buf_ptr_lo, (u32)buf);
+   out_be32(>buf_ptr_lo, 

[U-Boot] [PATCH 05/14] net/fm: fix MDIO controller base on FMAN2

[Gong Qianyu]

From: Shaohui Xie 

MDIO controller base on FMAN2 was defined as CONFIG_SYS_FSL_FM2_ADDR
plus offset, but CONFIG_SYS_FSL_FM2_ADDR only defined when there are two
FMANs, so we should only define MDIO controller base on FMAN2 when there
is FMAN2.

Signed-off-by: Shaohui Xie 
Signed-off-by: Mingkai Hu 
Signed-off-by: Gong Qianyu 
---
 include/fm_eth.h | 17 +
 1 file changed, 17 insertions(+)

diff --git a/include/fm_eth.h b/include/fm_eth.h
index 3e1b9f4..d43f801 100644
--- a/include/fm_eth.h
+++ b/include/fm_eth.h
@@ -45,8 +45,10 @@ enum fm_eth_type {
 #ifdef CONFIG_SYS_FMAN_V3
 #define CONFIG_SYS_FM1_DTSEC_MDIO_ADDR (CONFIG_SYS_FSL_FM1_ADDR + 0xfc000)
 #define CONFIG_SYS_FM1_TGEC_MDIO_ADDR  (CONFIG_SYS_FSL_FM1_ADDR + 0xfd000)
+#if (CONFIG_SYS_NUM_FMAN == 2)
 #define CONFIG_SYS_FM2_DTSEC_MDIO_ADDR (CONFIG_SYS_FSL_FM2_ADDR + 0xfc000)
 #define CONFIG_SYS_FM2_TGEC_MDIO_ADDR  (CONFIG_SYS_FSL_FM2_ADDR + 0xfd000)
+#endif
 #else
 #define CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR(CONFIG_SYS_FSL_FM1_ADDR + 
0xe1120)
 #define CONFIG_SYS_FM1_TGEC_MDIO_ADDR  (CONFIG_SYS_FSL_FM1_ADDR + 0xf1000)
@@ -89,6 +91,7 @@ enum fm_eth_type {
 offsetof(struct ccsr_fman, memac[n-1]),\
 }
 #else
+#if (CONFIG_SYS_NUM_FMAN == 2)
 #define FM_TGEC_INFO_INITIALIZER(idx, n) \
 {  \
FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM2_TGEC_MDIO_ADDR) \
@@ -101,6 +104,20 @@ enum fm_eth_type {
.compat_offset  = CONFIG_SYS_FSL_FM##idx##_OFFSET + \
offsetof(struct ccsr_fman, memac[n-1+8]),\
 }
+#else
+#define FM_TGEC_INFO_INITIALIZER(idx, n) \
+{  \
+   FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM1_TGEC_MDIO_ADDR) \
+   .index  = idx,  \
+   .num= n - 1,\
+   .type   = FM_ETH_10G_E, \
+   .port   = FM##idx##_10GEC##n,   \
+   .rx_port_id = RX_PORT_10G_BASE + n - 1, \
+   .tx_port_id = TX_PORT_10G_BASE + n - 1, \
+   .compat_offset  = CONFIG_SYS_FSL_FM##idx##_OFFSET + \
+   offsetof(struct ccsr_fman, memac[n-1+8]),\
+}
+#endif
 #endif
 
 #if (CONFIG_SYS_NUM_FM1_10GEC >= 3)
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH v2 17/18] ARM: uniphier: remove ifdef CONFIG_{SOC} conditionals from sg-regs.h

[Masahiro Yamada]

To achieve the complete run-time configuration by device trees, ifdef
conditionals in header files are not preferable.

Signed-off-by: Masahiro Yamada 
---

Changes in v2: None

 arch/arm/mach-uniphier/include/mach/sg-regs.h| 40 +++
 arch/arm/mach-uniphier/ph1-ld4/lowlevel_debug.S  |  4 +-
 arch/arm/mach-uniphier/ph1-ld4/pinctrl.c | 46 +++---
 arch/arm/mach-uniphier/ph1-pro4/lowlevel_debug.S |  4 +-
 arch/arm/mach-uniphier/ph1-pro4/pinctrl.c| 50 
 arch/arm/mach-uniphier/ph1-sld3/early_pinctrl.c  | 12 +++---
 arch/arm/mach-uniphier/ph1-sld3/lowlevel_debug.S |  4 +-
 arch/arm/mach-uniphier/ph1-sld3/pinctrl.c| 16 
 arch/arm/mach-uniphier/ph1-sld3/sbc_init.c   |  2 +-
 arch/arm/mach-uniphier/ph1-sld8/lowlevel_debug.S |  4 +-
 arch/arm/mach-uniphier/ph1-sld8/pinctrl.c| 46 +++---
 11 files changed, 109 insertions(+), 119 deletions(-)

diff --git a/arch/arm/mach-uniphier/include/mach/sg-regs.h 
b/arch/arm/mach-uniphier/include/mach/sg-regs.h
index 43a6c35..c886e1c 100644
--- a/arch/arm/mach-uniphier/include/mach/sg-regs.h
+++ b/arch/arm/mach-uniphier/include/mach/sg-regs.h
@@ -53,24 +53,6 @@
 /* Pin Control */
 #define SG_PINCTRL_BASE(SG_CTRL_BASE | 0x1000)
 
-#if defined(CONFIG_MACH_PH1_PRO4)
-# define SG_PINCTRL(n) (SG_PINCTRL_BASE + (n) * 8)
-#elif defined(CONFIG_MACH_PH1_SLD3) || defined(CONFIG_MACH_PH1_LD4) || \
-   defined(CONFIG_MACH_PH1_SLD8)
-# define SG_PINCTRL(n) (SG_PINCTRL_BASE + (n) * 4)
-#endif
-
-#if defined(CONFIG_MACH_PH1_SLD3) || defined(CONFIG_MACH_PH1_PRO4)
-#define SG_PINSELBITS  4
-#elif defined(CONFIG_MACH_PH1_LD4) || defined(CONFIG_MACH_PH1_SLD8)
-#define SG_PINSELBITS  8
-#endif
-
-#define SG_PINSEL_ADDR(n)  (SG_PINCTRL((n) * (SG_PINSELBITS) / 32))
-#define SG_PINSEL_MASK(n)  (~(((1 << (SG_PINSELBITS)) - 1) << \
-   ((n) * (SG_PINSELBITS) % 32)))
-#define SG_PINSEL_MODE(n, mode)((mode) << ((n) * 
(SG_PINSELBITS) % 32))
-
 /* Only for PH1-Pro4 */
 #define SG_LOADPINCTRL (SG_CTRL_BASE | 0x1700)
 
@@ -98,11 +80,11 @@
 
 #ifdef __ASSEMBLY__
 
-   .macro  set_pinsel, n, value, ra, rd
-   ldr \ra, =SG_PINSEL_ADDR(\n)
+   .macro  sg_set_pinsel, pin, muxval, mux_bits, reg_stride, ra, rd
+   ldr \ra, =(SG_PINCTRL_BASE + \pin * \mux_bits / 32 * \reg_stride)
ldr \rd, [\ra]
-   and \rd, \rd, #SG_PINSEL_MASK(\n)
-   orr \rd, \rd, #SG_PINSEL_MODE(\n, \value)
+   and \rd, \rd, #~(((1 << \mux_bits) - 1) << (\pin * \mux_bits % 32))
+   orr \rd, \rd, #(\muxval << (\pin * \mux_bits % 32))
str \rd, [\ra]
.endm
 
@@ -111,10 +93,18 @@
 #include 
 #include 
 
-static inline void sg_set_pinsel(int n, int value)
+static inline void sg_set_pinsel(unsigned pin, unsigned muxval,
+unsigned mux_bits, unsigned reg_stride)
 {
-   writel((readl(SG_PINSEL_ADDR(n)) & SG_PINSEL_MASK(n))
-  | SG_PINSEL_MODE(n, value), SG_PINSEL_ADDR(n));
+   unsigned shift = pin * mux_bits % 32;
+   unsigned reg = SG_PINCTRL_BASE + pin * mux_bits / 32 * reg_stride;
+   u32 mask = (1U << mux_bits) - 1;
+   u32 tmp;
+
+   tmp = readl(reg);
+   tmp &= ~(mask << shift);
+   tmp |= (mask & muxval) << shift;
+   writel(tmp, reg);
 }
 
 #endif /* __ASSEMBLY__ */
diff --git a/arch/arm/mach-uniphier/ph1-ld4/lowlevel_debug.S 
b/arch/arm/mach-uniphier/ph1-ld4/lowlevel_debug.S
index 7928c5c..fd393dc 100644
--- a/arch/arm/mach-uniphier/ph1-ld4/lowlevel_debug.S
+++ b/arch/arm/mach-uniphier/ph1-ld4/lowlevel_debug.S
@@ -17,8 +17,8 @@ ENTRY(setup_lowlevel_debug)
init_debug_uart r0, r1, r2
 
/* UART Port 0 */
-   set_pinsel  85, 1, r0, r1
-   set_pinsel  88, 1, r0, r1
+   sg_set_pinsel   85, 1, 8, 4, r0, r1
+   sg_set_pinsel   88, 1, 8, 4, r0, r1
 
ldr r0, =SG_IECTRL
ldr r1, [r0]
diff --git a/arch/arm/mach-uniphier/ph1-ld4/pinctrl.c 
b/arch/arm/mach-uniphier/ph1-ld4/pinctrl.c
index 20cc7b3..293a6ab 100644
--- a/arch/arm/mach-uniphier/ph1-ld4/pinctrl.c
+++ b/arch/arm/mach-uniphier/ph1-ld4/pinctrl.c
@@ -14,32 +14,32 @@ void pin_init(void)
/* Comment format:PAD Name -> Function Name */
 
 #ifdef CONFIG_NAND_DENALI
-   sg_set_pinsel(158, 0);  /* XNFRE -> XNFRE_GB */
-   sg_set_pinsel(159, 0);  /* XNFWE -> XNFWE_GB */
-   sg_set_pinsel(160, 0);  /* XFALE -> NFALE_GB */
-   sg_set_pinsel(161, 0);  /* XFCLE -> NFCLE_GB */
-   sg_set_pinsel(162, 0);  /* XNFWP -> XFNWP_GB */
-   sg_set_pinsel(163, 0);  /* XNFCE0 -> XNFCE0_GB */
-   sg_set_pinsel(164, 0);  /* NANDRYBY0 -> NANDRYBY0_GB 

[U-Boot] [PATCH v2 10/18] ARM: dts: uniphier: prepare device trees to use pinctrl in SPL

[Masahiro Yamada]

Add "u-boot,dm-pre-reloc" for device nodes we want in SPL DTB
(spl/u-boot-spl.dtb).

The "soc" node (this is simple-bus node) also needs the property
to bind the pinctrl node located under it.

I am collecting this U-Boot specific hack to the bottom of board
DTS rather than inserting "u-boot,dm-pre-reloc" into SoC DTSI.
My goal is to sync DTSI with Linux for easier maintenance.

Signed-off-by: Masahiro Yamada 
Reviewed-by: Simon Glass 
---

Changes in v2: None

 arch/arm/dts/uniphier-ph1-ld4-ref.dts  | 16 +++-
 arch/arm/dts/uniphier-ph1-ld6b-ref.dts | 16 +++-
 arch/arm/dts/uniphier-ph1-pro4-ref.dts | 16 +++-
 arch/arm/dts/uniphier-ph1-sld8-ref.dts | 16 +++-
 4 files changed, 60 insertions(+), 4 deletions(-)

diff --git a/arch/arm/dts/uniphier-ph1-ld4-ref.dts 
b/arch/arm/dts/uniphier-ph1-ld4-ref.dts
index 20f2e9a..9d697c1 100644
--- a/arch/arm/dts/uniphier-ph1-ld4-ref.dts
+++ b/arch/arm/dts/uniphier-ph1-ld4-ref.dts
@@ -61,6 +61,20 @@
 };
 
 /* for U-boot only */
+/ {
+   soc {
+   u-boot,dm-pre-reloc;
+   };
+};
+
  {
-   u-boot,dm-pre-reloc;
+   u-boot,dm-pre-reloc;
+};
+
+ {
+   u-boot,dm-pre-reloc;
+};
+
+_uart0 {
+   u-boot,dm-pre-reloc;
 };
diff --git a/arch/arm/dts/uniphier-ph1-ld6b-ref.dts 
b/arch/arm/dts/uniphier-ph1-ld6b-ref.dts
index 58dc20e..ca68930 100644
--- a/arch/arm/dts/uniphier-ph1-ld6b-ref.dts
+++ b/arch/arm/dts/uniphier-ph1-ld6b-ref.dts
@@ -54,6 +54,20 @@
 };
 
 /* for U-boot only */
+/ {
+   soc {
+   u-boot,dm-pre-reloc;
+   };
+};
+
  {
-   u-boot,dm-pre-reloc;
+   u-boot,dm-pre-reloc;
+};
+
+ {
+   u-boot,dm-pre-reloc;
+};
+
+_uart0 {
+   u-boot,dm-pre-reloc;
 };
diff --git a/arch/arm/dts/uniphier-ph1-pro4-ref.dts 
b/arch/arm/dts/uniphier-ph1-pro4-ref.dts
index ec1117d..a825069 100644
--- a/arch/arm/dts/uniphier-ph1-pro4-ref.dts
+++ b/arch/arm/dts/uniphier-ph1-pro4-ref.dts
@@ -68,6 +68,20 @@
 };
 
 /* for U-boot only */
+/ {
+   soc {
+   u-boot,dm-pre-reloc;
+   };
+};
+
  {
-   u-boot,dm-pre-reloc;
+   u-boot,dm-pre-reloc;
+};
+
+ {
+   u-boot,dm-pre-reloc;
+};
+
+_uart0 {
+   u-boot,dm-pre-reloc;
 };
diff --git a/arch/arm/dts/uniphier-ph1-sld8-ref.dts 
b/arch/arm/dts/uniphier-ph1-sld8-ref.dts
index 6269f9a..2cfcaff 100644
--- a/arch/arm/dts/uniphier-ph1-sld8-ref.dts
+++ b/arch/arm/dts/uniphier-ph1-sld8-ref.dts
@@ -65,6 +65,20 @@
 };
 
 /* for U-boot only */
+/ {
+   soc {
+   u-boot,dm-pre-reloc;
+   };
+};
+
  {
-   u-boot,dm-pre-reloc;
+   u-boot,dm-pre-reloc;
+};
+
+ {
+   u-boot,dm-pre-reloc;
+};
+
+_uart0 {
+   u-boot,dm-pre-reloc;
 };
-- 
1.9.1

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[U-Boot] [PATCH v2 16/18] ARM: uniphier: change the external bus address mapping

[Masahiro Yamada]

In UniPhier SoCs before ProXstream2 and PH1-LD6b, two address spaces
 0x - 0x0fff
 0x4000 - 0x4fff
are both mapped to the external bus (also called system bus),
so either was OK.

In the newest two SoCs, the former (0x - 0x0fff) is
assigned for the serial NOR interface.

Going forward, use the latter for the external bus.

Signed-off-by: Masahiro Yamada 
Reviewed-by: Simon Glass 
---

Changes in v2: None

 arch/arm/mach-uniphier/ph1-ld4/sbc_init.c  | 12 ++--
 arch/arm/mach-uniphier/ph1-pro4/sbc_init.c | 12 ++--
 arch/arm/mach-uniphier/ph1-sld3/sbc_init.c | 12 ++--
 arch/arm/mach-uniphier/support_card.c  |  2 +-
 include/configs/uniphier.h |  7 ++-
 5 files changed, 25 insertions(+), 20 deletions(-)

diff --git a/arch/arm/mach-uniphier/ph1-ld4/sbc_init.c 
b/arch/arm/mach-uniphier/ph1-ld4/sbc_init.c
index 8e25792..4435a47 100644
--- a/arch/arm/mach-uniphier/ph1-ld4/sbc_init.c
+++ b/arch/arm/mach-uniphier/ph1-ld4/sbc_init.c
@@ -30,18 +30,18 @@ void sbc_init(void)
if (boot_is_swapped()) {
/*
 * Boot Swap On: boot from external NOR/SRAM
-* 0x0200-0x03ff is a mirror of 0x-0x01ff.
+* 0x4200-0x43ff is a mirror of 0x4000-0x41ff.
 *
-* 0x-0x01ef, 0x0200-0x03ef: memory bank
-* 0x01f0-0x01ff, 0x03f0-0x03ff: peripherals
+* 0x4000-0x41ef, 0x4200-0x43ef: memory bank
+* 0x41f0-0x41ff, 0x43f0-0x43ff: peripherals
 */
writel(0xbc01, SBBASE0);
} else {
/*
 * Boot Swap Off: boot from mask ROM
-* 0x-0x01ff: mask ROM
-* 0x0200-0x03ef: memory bank (31MB)
-* 0x03f0-0x03ff: peripherals (1MB)
+* 0x4000-0x41ff: mask ROM
+* 0x4200-0x43ef: memory bank (31MB)
+* 0x43f0-0x43ff: peripherals (1MB)
 */
writel(0xbe01, SBBASE0); /* dummy */
writel(0x0200be01, SBBASE1);
diff --git a/arch/arm/mach-uniphier/ph1-pro4/sbc_init.c 
b/arch/arm/mach-uniphier/ph1-pro4/sbc_init.c
index 533739c..685f9c7 100644
--- a/arch/arm/mach-uniphier/ph1-pro4/sbc_init.c
+++ b/arch/arm/mach-uniphier/ph1-pro4/sbc_init.c
@@ -23,18 +23,18 @@ void sbc_init(void)
if (boot_is_swapped()) {
/*
 * Boot Swap On: boot from external NOR/SRAM
-* 0x0200-0x03ff is a mirror of 0x-0x01ff.
+* 0x4200-0x43ff is a mirror of 0x4000-0x41ff.
 *
-* 0x-0x01ef, 0x0200-0x03ef: memory bank
-* 0x01f0-0x01ff, 0x03f0-0x03ff: peripherals
+* 0x4000-0x41ef, 0x4200-0x43ef: memory bank
+* 0x41f0-0x41ff, 0x43f0-0x43ff: peripherals
 */
writel(0xbc01, SBBASE0);
} else {
/*
 * Boot Swap Off: boot from mask ROM
-* 0x-0x01ff: mask ROM
-* 0x0200-0x03ef: memory bank (31MB)
-* 0x03f0-0x03ff: peripherals (1MB)
+* 0x4000-0x41ff: mask ROM
+* 0x4200-0x43ef: memory bank (31MB)
+* 0x43f0-0x43ff: peripherals (1MB)
 */
writel(0xbe01, SBBASE0); /* dummy */
writel(0x0200be01, SBBASE1);
diff --git a/arch/arm/mach-uniphier/ph1-sld3/sbc_init.c 
b/arch/arm/mach-uniphier/ph1-sld3/sbc_init.c
index d66f89e..bafab4b 100644
--- a/arch/arm/mach-uniphier/ph1-sld3/sbc_init.c
+++ b/arch/arm/mach-uniphier/ph1-sld3/sbc_init.c
@@ -24,18 +24,18 @@ void sbc_init(void)
if (boot_is_swapped()) {
/*
 * Boot Swap On: boot from external NOR/SRAM
-* 0x0200-0x03ff is a mirror of 0x-0x01ff.
+* 0x4200-0x43ff is a mirror of 0x4000-0x41ff.
 *
-* 0x-0x01ef, 0x0200-0x03ef: memory bank
-* 0x01f0-0x01ff, 0x03f0-0x03ff: peripherals
+* 0x4000-0x41ef, 0x4200-0x43ef: memory bank
+* 0x41f0-0x41ff, 0x43f0-0x43ff: peripherals
 */
writel(0xbc01, SBBASE0);
} else {
/*
 * Boot Swap Off: boot from mask ROM
-* 0x-0x01ff: mask ROM
-* 0x0200-0x03ef: memory bank (31MB)
-* 0x03f0-0x03ff: peripherals 

[U-Boot] [PATCH v2 12/18] ARM: uniphier: drop ad-hoc early pin-muxing settings

[Masahiro Yamada]

As the UniPhier serial driver had already switched to Drive Model
and the pinctrl drivers are now enabled, these pin-muxing settings
are properly handled by the pinctrl drivers.

Signed-off-by: Masahiro Yamada 
Reviewed-by: Simon Glass 
---

Changes in v2: None

 arch/arm/mach-uniphier/ph1-ld4/Makefile |  2 +-
 arch/arm/mach-uniphier/ph1-ld4/early_pinctrl.c  | 27 -
 arch/arm/mach-uniphier/ph1-pro4/Makefile|  2 +-
 arch/arm/mach-uniphier/ph1-pro4/early_pinctrl.c | 26 
 arch/arm/mach-uniphier/ph1-sld8/early_pinctrl.c | 27 -
 arch/arm/mach-uniphier/spl.c|  5 +
 6 files changed, 7 insertions(+), 82 deletions(-)
 delete mode 100644 arch/arm/mach-uniphier/ph1-ld4/early_pinctrl.c
 delete mode 100644 arch/arm/mach-uniphier/ph1-pro4/early_pinctrl.c
 delete mode 100644 arch/arm/mach-uniphier/ph1-sld8/early_pinctrl.c

diff --git a/arch/arm/mach-uniphier/ph1-ld4/Makefile 
b/arch/arm/mach-uniphier/ph1-ld4/Makefile
index 1410b12..789820e 100644
--- a/arch/arm/mach-uniphier/ph1-ld4/Makefile
+++ b/arch/arm/mach-uniphier/ph1-ld4/Makefile
@@ -5,7 +5,7 @@
 ifdef CONFIG_SPL_BUILD
 obj-$(CONFIG_DEBUG_LL) += lowlevel_debug.o
 obj-y += bcu_init.o sg_init.o pll_init.o early_clkrst_init.o \
-   early_pinctrl.o pll_spectrum.o umc_init.o ddrphy_init.o
+   pll_spectrum.o umc_init.o ddrphy_init.o
 obj-$(CONFIG_PFC_MICRO_SUPPORT_CARD) += sbc_init.o
 obj-$(CONFIG_DCC_MICRO_SUPPORT_CARD) += sbc_init_3cs.o
 else
diff --git a/arch/arm/mach-uniphier/ph1-ld4/early_pinctrl.c 
b/arch/arm/mach-uniphier/ph1-ld4/early_pinctrl.c
deleted file mode 100644
index e5e86bb..000
--- a/arch/arm/mach-uniphier/ph1-ld4/early_pinctrl.c
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- * Copyright (C) 2011-2015 Panasonic Corporation
- * Copyright (C) 2015  Socionext Inc.
- *
- * SPDX-License-Identifier:GPL-2.0+
- */
-
-#include 
-
-void early_pin_init(void)
-{
-   /* Comment format:PAD Name -> Function Name */
-
-#ifdef CONFIG_UNIPHIER_SERIAL
-   sg_set_pinsel(85, 1);   /* HSDOUT3 -> RXD0 */
-   sg_set_pinsel(88, 1);   /* HDDOUT6 -> TXD0 */
-
-   sg_set_pinsel(69, 23);  /* PCIOWR -> TXD1 */
-   sg_set_pinsel(70, 23);  /* PCIORD -> RXD1 */
-
-   sg_set_pinsel(128, 13); /* XIRQ6 -> TXD2 */
-   sg_set_pinsel(129, 13); /* XIRQ7 -> RXD2 */
-
-   sg_set_pinsel(110, 1);  /* SBO0 -> TXD3 */
-   sg_set_pinsel(111, 1);  /* SBI0 -> RXD3 */
-#endif
-}
diff --git a/arch/arm/mach-uniphier/ph1-pro4/Makefile 
b/arch/arm/mach-uniphier/ph1-pro4/Makefile
index 229f443..7fdb36a 100644
--- a/arch/arm/mach-uniphier/ph1-pro4/Makefile
+++ b/arch/arm/mach-uniphier/ph1-pro4/Makefile
@@ -5,7 +5,7 @@
 ifdef CONFIG_SPL_BUILD
 obj-$(CONFIG_DEBUG_LL) += lowlevel_debug.o
 obj-y += sg_init.o pll_init.o early_clkrst_init.o \
-   early_pinctrl.o pll_spectrum.o umc_init.o ddrphy_init.o
+   pll_spectrum.o umc_init.o ddrphy_init.o
 obj-$(CONFIG_PFC_MICRO_SUPPORT_CARD) += sbc_init.o
 obj-$(CONFIG_DCC_MICRO_SUPPORT_CARD) += sbc_init_3cs.o
 else
diff --git a/arch/arm/mach-uniphier/ph1-pro4/early_pinctrl.c 
b/arch/arm/mach-uniphier/ph1-pro4/early_pinctrl.c
deleted file mode 100644
index e78d6ab..000
--- a/arch/arm/mach-uniphier/ph1-pro4/early_pinctrl.c
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * Copyright (C) 2011-2015 Masahiro Yamada 
- *
- * SPDX-License-Identifier:GPL-2.0+
- */
-
-#include 
-#include 
-
-void early_pin_init(void)
-{
-   /* Comment format:PAD Name -> Function Name */
-
-#ifdef CONFIG_UNIPHIER_SERIAL
-   sg_set_pinsel(127, 0);  /* RXD0 -> RXD0 */
-   sg_set_pinsel(128, 0);  /* TXD0 -> TXD0 */
-   sg_set_pinsel(129, 0);  /* RXD1 -> RXD1 */
-   sg_set_pinsel(130, 0);  /* TXD1 -> TXD1 */
-   sg_set_pinsel(131, 0);  /* RXD2 -> RXD2 */
-   sg_set_pinsel(132, 0);  /* TXD2 -> TXD2 */
-   sg_set_pinsel(88, 2);   /* CH6CLK -> RXD3 */
-   sg_set_pinsel(89, 2);   /* CH6VAL -> TXD3 */
-#endif
-
-   writel(1, SG_LOADPINCTRL);
-}
diff --git a/arch/arm/mach-uniphier/ph1-sld8/early_pinctrl.c 
b/arch/arm/mach-uniphier/ph1-sld8/early_pinctrl.c
deleted file mode 100644
index 28cc429..000
--- a/arch/arm/mach-uniphier/ph1-sld8/early_pinctrl.c
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- * Copyright (C) 2011-2015 Panasonic Corporation
- * Copyright (C) 2015  Socionext Inc.
- *
- * SPDX-License-Identifier:GPL-2.0+
- */
-
-#include 
-
-void early_pin_init(void)
-{
-   /* Comment format:PAD Name -> Function Name */
-
-#ifdef CONFIG_UNIPHIER_SERIAL
-   sg_set_pinsel(70, 3);   /* HDDOUT0 -> TXD0 */
-   sg_set_pinsel(71, 3);   /* HSDOUT1 -> RXD0 */
-
-   sg_set_pinsel(114, 0);  /* TXD1 -> TXD1 */
-   sg_set_pinsel(115, 0);  /* RXD1 -> RXD1 */
-
-   sg_set_pinsel(112, 1);  /* SBO1 -> TXD2 */
-   sg_set_pinsel(113, 1);  /* SBI1 -> RXD2 */
-
-   sg_set_pinsel(110, 1);  /* SBO0 -> TXD3 

[U-Boot] [PATCH v2 09/18] ARM: uniphier: increase CONFIG_SYS_MALLOC_F_LEN to bind all nodes

[Masahiro Yamada]

In the next commit, I will add "u-boot,dm-pre-reloc" to the "soc"
(simple-bus) nodes in UniPhier device trees.  But, before that,
CONFIG_SYS_MALLOC_F_LEN must be increased.

Adding "u-boot,dm-pre-reloc" to a simple-bus node causes it to bind
all of its child nodes.  (See simple_bus_post_bind() function)

Actually, I want only UART0 and pinctrl to be bound in SPL and before
relocation in U-boot proper.  But, with "u-boot,dm-pre-reloc" in the
simple-bus node, all the other unwanted nodes are also bound.  The
default value for CONFIG_SYS_MALLOC_F_LEN, 0x400, is not enough for
that.  Increase the pre-reloc malloc size to 0x2000, hoping the root
cause will be fixed later.

Signed-off-by: Masahiro Yamada 
---

Changes in v2: None

 configs/ph1_ld4_defconfig  | 1 +
 configs/ph1_pro4_defconfig | 1 +
 configs/ph1_sld8_defconfig | 1 +
 3 files changed, 3 insertions(+)

diff --git a/configs/ph1_ld4_defconfig b/configs/ph1_ld4_defconfig
index 74e759a..61eb037 100644
--- a/configs/ph1_ld4_defconfig
+++ b/configs/ph1_ld4_defconfig
@@ -1,5 +1,6 @@
 CONFIG_ARM=y
 CONFIG_ARCH_UNIPHIER=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_MACH_PH1_LD4=y
 CONFIG_PFC_MICRO_SUPPORT_CARD=y
 CONFIG_SYS_TEXT_BASE=0x8400
diff --git a/configs/ph1_pro4_defconfig b/configs/ph1_pro4_defconfig
index 714339a..7582fdf 100644
--- a/configs/ph1_pro4_defconfig
+++ b/configs/ph1_pro4_defconfig
@@ -1,5 +1,6 @@
 CONFIG_ARM=y
 CONFIG_ARCH_UNIPHIER=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_PFC_MICRO_SUPPORT_CARD=y
 CONFIG_SYS_TEXT_BASE=0x8400
 CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-pro4-ref"
diff --git a/configs/ph1_sld8_defconfig b/configs/ph1_sld8_defconfig
index df0e005..236e673 100644
--- a/configs/ph1_sld8_defconfig
+++ b/configs/ph1_sld8_defconfig
@@ -1,5 +1,6 @@
 CONFIG_ARM=y
 CONFIG_ARCH_UNIPHIER=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_MACH_PH1_SLD8=y
 CONFIG_PFC_MICRO_SUPPORT_CARD=y
 CONFIG_SYS_TEXT_BASE=0x8400
-- 
1.9.1

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[U-Boot] [PATCH v2 01/18] pinctrl: uniphier: add UniPhier pinctrl core support

[Masahiro Yamada]

The core support for the pinctrl drivers for all the UniPhier SoCs.

Signed-off-by: Masahiro Yamada 
Reviewed-by: Simon Glass 
---

Changes in v2:
  - add comments to structures
  - re-design to maximize code re-use of Linux pinctrl drivers
  - implement input enabling

 drivers/pinctrl/Kconfig  |   2 +
 drivers/pinctrl/Makefile |   2 +
 drivers/pinctrl/uniphier/Kconfig |   6 +
 drivers/pinctrl/uniphier/Makefile|   1 +
 drivers/pinctrl/uniphier/pinctrl-uniphier-core.c | 154 +++
 drivers/pinctrl/uniphier/pinctrl-uniphier.h  | 113 +
 6 files changed, 278 insertions(+)
 create mode 100644 drivers/pinctrl/uniphier/Kconfig
 create mode 100644 drivers/pinctrl/uniphier/Makefile
 create mode 100644 drivers/pinctrl/uniphier/pinctrl-uniphier-core.c
 create mode 100644 drivers/pinctrl/uniphier/pinctrl-uniphier.h

diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index b8146df..3b6e3b7 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -124,4 +124,6 @@ config PINCTRL_SANDBOX
 
 endif
 
+source "drivers/pinctrl/uniphier/Kconfig"
+
 endmenu
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index f537df4..e56a17f 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -3,3 +3,5 @@ obj-$(CONFIG_$(SPL_)PINCTRL_GENERIC)+= pinctrl-generic.o
 
 obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
 obj-$(CONFIG_PINCTRL_SANDBOX)  += pinctrl-sandbox.o
+
+obj-$(CONFIG_ARCH_UNIPHIER)+= uniphier/
diff --git a/drivers/pinctrl/uniphier/Kconfig b/drivers/pinctrl/uniphier/Kconfig
new file mode 100644
index 000..29a623d
--- /dev/null
+++ b/drivers/pinctrl/uniphier/Kconfig
@@ -0,0 +1,6 @@
+if ARCH_UNIPHIER
+
+config PINCTRL_UNIPHIER_CORE
+   bool
+
+endif
diff --git a/drivers/pinctrl/uniphier/Makefile 
b/drivers/pinctrl/uniphier/Makefile
new file mode 100644
index 000..748aa1b
--- /dev/null
+++ b/drivers/pinctrl/uniphier/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_PINCTRL_UNIPHIER_CORE)+= pinctrl-uniphier-core.o
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c 
b/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c
new file mode 100644
index 000..37a920c
--- /dev/null
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c
@@ -0,0 +1,154 @@
+/*
+ * Copyright (C) 2015 Masahiro Yamada 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "pinctrl-uniphier.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static int uniphier_pinctrl_get_groups_count(struct udevice *dev)
+{
+   struct uniphier_pinctrl_priv *priv = dev_get_priv(dev);
+
+   return priv->socdata->groups_count;
+}
+
+static const char *uniphier_pinctrl_get_group_name(struct udevice *dev,
+  unsigned selector)
+{
+   struct uniphier_pinctrl_priv *priv = dev_get_priv(dev);
+
+   return priv->socdata->groups[selector].name;
+}
+
+static int uniphier_pinmux_get_functions_count(struct udevice *dev)
+{
+   struct uniphier_pinctrl_priv *priv = dev_get_priv(dev);
+
+   return priv->socdata->functions_count;
+}
+
+static const char *uniphier_pinmux_get_function_name(struct udevice *dev,
+unsigned selector)
+{
+   struct uniphier_pinctrl_priv *priv = dev_get_priv(dev);
+
+   return priv->socdata->functions[selector];
+}
+
+static void uniphier_pinconf_input_enable(struct udevice *dev, unsigned pin)
+{
+   struct uniphier_pinctrl_priv *priv = dev_get_priv(dev);
+   int pins_count = priv->socdata->pins_count;
+   const struct uniphier_pinctrl_pin *pins = priv->socdata->pins;
+   int i;
+
+   for (i = 0; i < pins_count; i++) {
+   if (pins[i].number == pin) {
+   unsigned int iectrl;
+   u32 tmp;
+
+   iectrl = uniphier_pin_get_iectrl(pins[i].data);
+   tmp = readl(priv->base + UNIPHIER_PINCTRL_IECTRL);
+   tmp |= 1 << iectrl;
+   writel(tmp, priv->base + UNIPHIER_PINCTRL_IECTRL);
+   }
+   }
+}
+
+static void uniphier_pinmux_set_one(struct udevice *dev, unsigned pin,
+   unsigned muxval)
+{
+   struct uniphier_pinctrl_priv *priv = dev_get_priv(dev);
+   unsigned mux_bits = priv->socdata->mux_bits;
+   unsigned reg_stride = priv->socdata->reg_stride;
+   unsigned reg, reg_end, shift, mask;
+   u32 tmp;
+
+   reg = UNIPHIER_PINCTRL_PINMUX_BASE + pin * mux_bits / 32 * reg_stride;
+   reg_end = reg + reg_stride;
+   shift = pin * mux_bits % 32;
+   mask = (1U << mux_bits) - 1;
+
+   /*
+* If reg_stride is greater than 4, the MSB of each pinsel shall be
+* stored in the 

[U-Boot] [PATCH v2 13/18] ARM: uniphier: drop ad-hoc input enable settings

[Masahiro Yamada]

These input enable settings are handled by the pinctrl drivers.

Because the external bus pins are input-enabled by default, on-board
devices such as LED still work fine even with this delayed input
enabling.

Signed-off-by: Masahiro Yamada 
---

Changes in v2:
  - Newly added

 arch/arm/mach-uniphier/ph1-ld4/Makefile   |  2 +-
 arch/arm/mach-uniphier/ph1-ld4/sg_init.c  | 18 --
 arch/arm/mach-uniphier/ph1-pro4/Makefile  |  2 +-
 arch/arm/mach-uniphier/ph1-pro4/sg_init.c | 18 --
 arch/arm/mach-uniphier/ph1-sld8/pinctrl.c |  9 -
 arch/arm/mach-uniphier/ph1-sld8/sg_init.c |  1 -
 arch/arm/mach-uniphier/spl.c  |  8 +---
 7 files changed, 7 insertions(+), 51 deletions(-)
 delete mode 100644 arch/arm/mach-uniphier/ph1-ld4/sg_init.c
 delete mode 100644 arch/arm/mach-uniphier/ph1-pro4/sg_init.c
 delete mode 100644 arch/arm/mach-uniphier/ph1-sld8/sg_init.c

diff --git a/arch/arm/mach-uniphier/ph1-ld4/Makefile 
b/arch/arm/mach-uniphier/ph1-ld4/Makefile
index 789820e..0c198c6 100644
--- a/arch/arm/mach-uniphier/ph1-ld4/Makefile
+++ b/arch/arm/mach-uniphier/ph1-ld4/Makefile
@@ -4,7 +4,7 @@
 
 ifdef CONFIG_SPL_BUILD
 obj-$(CONFIG_DEBUG_LL) += lowlevel_debug.o
-obj-y += bcu_init.o sg_init.o pll_init.o early_clkrst_init.o \
+obj-y += bcu_init.o pll_init.o early_clkrst_init.o \
pll_spectrum.o umc_init.o ddrphy_init.o
 obj-$(CONFIG_PFC_MICRO_SUPPORT_CARD) += sbc_init.o
 obj-$(CONFIG_DCC_MICRO_SUPPORT_CARD) += sbc_init_3cs.o
diff --git a/arch/arm/mach-uniphier/ph1-ld4/sg_init.c 
b/arch/arm/mach-uniphier/ph1-ld4/sg_init.c
deleted file mode 100644
index dab56e9..000
--- a/arch/arm/mach-uniphier/ph1-ld4/sg_init.c
+++ /dev/null
@@ -1,18 +0,0 @@
-/*
- * Copyright (C) 2011-2015 Masahiro Yamada 
- *
- * SPDX-License-Identifier:GPL-2.0+
- */
-
-#include 
-#include 
-
-void sg_init(void)
-{
-   u32 tmp;
-
-   /* Input ports must be enabled before deasserting reset of cores */
-   tmp = readl(SG_IECTRL);
-   tmp |= 0x1;
-   writel(tmp, SG_IECTRL);
-}
diff --git a/arch/arm/mach-uniphier/ph1-pro4/Makefile 
b/arch/arm/mach-uniphier/ph1-pro4/Makefile
index 7fdb36a..afd9235 100644
--- a/arch/arm/mach-uniphier/ph1-pro4/Makefile
+++ b/arch/arm/mach-uniphier/ph1-pro4/Makefile
@@ -4,7 +4,7 @@
 
 ifdef CONFIG_SPL_BUILD
 obj-$(CONFIG_DEBUG_LL) += lowlevel_debug.o
-obj-y += sg_init.o pll_init.o early_clkrst_init.o \
+obj-y += pll_init.o early_clkrst_init.o \
pll_spectrum.o umc_init.o ddrphy_init.o
 obj-$(CONFIG_PFC_MICRO_SUPPORT_CARD) += sbc_init.o
 obj-$(CONFIG_DCC_MICRO_SUPPORT_CARD) += sbc_init_3cs.o
diff --git a/arch/arm/mach-uniphier/ph1-pro4/sg_init.c 
b/arch/arm/mach-uniphier/ph1-pro4/sg_init.c
deleted file mode 100644
index d6ccffb..000
--- a/arch/arm/mach-uniphier/ph1-pro4/sg_init.c
+++ /dev/null
@@ -1,18 +0,0 @@
-/*
- * Copyright (C) 2011-2015 Masahiro Yamada 
- *
- * SPDX-License-Identifier:GPL-2.0+
- */
-
-#include 
-#include 
-
-void sg_init(void)
-{
-   u32 tmp;
-
-   /* Input ports must be enabled before deasserting reset of cores */
-   tmp = readl(SG_IECTRL);
-   tmp |= 1 << 6;
-   writel(tmp, SG_IECTRL);
-}
diff --git a/arch/arm/mach-uniphier/ph1-sld8/pinctrl.c 
b/arch/arm/mach-uniphier/ph1-sld8/pinctrl.c
index 130c831..98da1f9 100644
--- a/arch/arm/mach-uniphier/ph1-sld8/pinctrl.c
+++ b/arch/arm/mach-uniphier/ph1-sld8/pinctrl.c
@@ -11,15 +11,6 @@ void pin_init(void)
 {
/* Comment format:PAD Name -> Function Name */
 
-#ifdef CONFIG_SYS_I2C_UNIPHIER
-   {
-   u32 tmp;
-   tmp = readl(SG_IECTRL);
-   tmp |= 0xc00; /* enable SCL0, SDA0, SCL1, SDA1 */
-   writel(tmp, SG_IECTRL);
-   }
-#endif
-
 #ifdef CONFIG_NAND_DENALI
sg_set_pinsel(15, 0);   /* XNFRE_GB -> XNFRE_GB */
sg_set_pinsel(16, 0);   /* XNFWE_GB -> XNFWE_GB */
diff --git a/arch/arm/mach-uniphier/ph1-sld8/sg_init.c 
b/arch/arm/mach-uniphier/ph1-sld8/sg_init.c
deleted file mode 100644
index a808289..000
--- a/arch/arm/mach-uniphier/ph1-sld8/sg_init.c
+++ /dev/null
@@ -1 +0,0 @@
-#include "../ph1-ld4/sg_init.c"
diff --git a/arch/arm/mach-uniphier/spl.c b/arch/arm/mach-uniphier/spl.c
index 86764bc..78534fc 100644
--- a/arch/arm/mach-uniphier/spl.c
+++ b/arch/arm/mach-uniphier/spl.c
@@ -1,7 +1,5 @@
 /*
- * Copyright (C) 2013-2015 Panasonic Corporation
- * Copyright (C) 2015  Socionext Inc.
- *   Author: Masahiro Yamada 
+ * Copyright (C) 2013-2015 Masahiro Yamada 
  *
  * SPDX-License-Identifier:GPL-2.0+
  */
@@ -16,6 +14,10 @@ void __weak bcu_init(void)
 {
 };
 
+void __weak sg_init(void)
+{
+};
+
 void __weak early_pin_init(void)
 {
 };
-- 
1.9.1

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[U-Boot] [PATCH v2 03/18] pinctrl: uniphier: add UniPhier PH1-Pro4 pinctrl driver

[Masahiro Yamada]

Add pin configuration and pinmux support for UniPhier PH1-Pro4 SoC.

Signed-off-by: Masahiro Yamada 
---

Changes in v2:
  - Add input-enable settings
  - Sync pin-mux table with Linux pinctrl driver

 drivers/pinctrl/uniphier/Kconfig|   6 ++
 drivers/pinctrl/uniphier/Makefile   |   1 +
 drivers/pinctrl/uniphier/pinctrl-ph1-pro4.c | 129 
 3 files changed, 136 insertions(+)
 create mode 100644 drivers/pinctrl/uniphier/pinctrl-ph1-pro4.c

diff --git a/drivers/pinctrl/uniphier/Kconfig b/drivers/pinctrl/uniphier/Kconfig
index 03593cd..c417a9f 100644
--- a/drivers/pinctrl/uniphier/Kconfig
+++ b/drivers/pinctrl/uniphier/Kconfig
@@ -9,4 +9,10 @@ config PINCTRL_UNIPHIER_PH1_LD4
default y
select PINCTRL_UNIPHIER_CORE
 
+config PINCTRL_UNIPHIER_PH1_PRO4
+   bool "UniPhier PH1-Pro4 SoC pinctrl driver"
+   depends on MACH_PH1_PRO4
+   default y
+   select PINCTRL_UNIPHIER_CORE
+
 endif
diff --git a/drivers/pinctrl/uniphier/Makefile 
b/drivers/pinctrl/uniphier/Makefile
index b4bd042..b1b597e 100644
--- a/drivers/pinctrl/uniphier/Makefile
+++ b/drivers/pinctrl/uniphier/Makefile
@@ -1,3 +1,4 @@
 obj-$(CONFIG_PINCTRL_UNIPHIER_CORE)+= pinctrl-uniphier-core.o
 
 obj-$(CONFIG_PINCTRL_UNIPHIER_PH1_LD4) += pinctrl-ph1-ld4.o
+obj-$(CONFIG_PINCTRL_UNIPHIER_PH1_PRO4)+= pinctrl-ph1-pro4.o
diff --git a/drivers/pinctrl/uniphier/pinctrl-ph1-pro4.c 
b/drivers/pinctrl/uniphier/pinctrl-ph1-pro4.c
new file mode 100644
index 000..1cb5cbd
--- /dev/null
+++ b/drivers/pinctrl/uniphier/pinctrl-ph1-pro4.c
@@ -0,0 +1,129 @@
+/*
+ * Copyright (C) 2015 Masahiro Yamada 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+
+#include "pinctrl-uniphier.h"
+
+static const struct uniphier_pinctrl_pin ph1_pro4_pins[] = {
+};
+
+static const unsigned emmc_pins[] = {40, 41, 42, 43, 51, 52, 53};
+static const unsigned emmc_muxvals[] = {1, 1, 1, 1, 1, 1, 1};
+static const unsigned emmc_dat8_pins[] = {44, 45, 46, 47};
+static const unsigned emmc_dat8_muxvals[] = {1, 1, 1, 1};
+static const unsigned i2c0_pins[] = {142, 143};
+static const unsigned i2c0_muxvals[] = {0, 0};
+static const unsigned i2c1_pins[] = {144, 145};
+static const unsigned i2c1_muxvals[] = {0, 0};
+static const unsigned i2c2_pins[] = {146, 147};
+static const unsigned i2c2_muxvals[] = {0, 0};
+static const unsigned i2c3_pins[] = {148, 149};
+static const unsigned i2c3_muxvals[] = {0, 0};
+static const unsigned i2c6_pins[] = {308, 309};
+static const unsigned i2c6_muxvals[] = {6, 6};
+static const unsigned nand_pins[] = {40, 41, 42, 43, 44, 45, 46, 47, 48, 49,
+50, 51, 52, 53, 54};
+static const unsigned nand_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+   0, 0};
+static const unsigned nand_cs1_pins[] = {131, 132};
+static const unsigned nand_cs1_muxvals[] = {1, 1};
+static const unsigned uart0_pins[] = {127, 128};
+static const unsigned uart0_muxvals[] = {0, 0};
+static const unsigned uart1_pins[] = {129, 130};
+static const unsigned uart1_muxvals[] = {0, 0};
+static const unsigned uart2_pins[] = {131, 132};
+static const unsigned uart2_muxvals[] = {0, 0};
+static const unsigned uart3_pins[] = {88, 89};
+static const unsigned uart3_muxvals[] = {2, 2};
+static const unsigned usb0_pins[] = {180, 181};
+static const unsigned usb0_muxvals[] = {0, 0};
+static const unsigned usb1_pins[] = {182, 183};
+static const unsigned usb1_muxvals[] = {0, 0};
+static const unsigned usb2_pins[] = {184, 185};
+static const unsigned usb2_muxvals[] = {0, 0};
+static const unsigned usb3_pins[] = {186, 187};
+static const unsigned usb3_muxvals[] = {0, 0};
+static const unsigned sd_pins[] = {150, 151, 152, 153, 154, 155, 156, 157, 
158};
+static const unsigned sd_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0};
+static const unsigned sd1_pins[] = {319, 320, 321, 322, 323, 324, 325, 326,
+   327};
+static const unsigned sd1_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0};
+static const struct uniphier_pinctrl_group ph1_pro4_groups[] = {
+   UNIPHIER_PINCTRL_GROUP(emmc),
+   UNIPHIER_PINCTRL_GROUP(emmc_dat8),
+   UNIPHIER_PINCTRL_GROUP(i2c0),
+   UNIPHIER_PINCTRL_GROUP(i2c1),
+   UNIPHIER_PINCTRL_GROUP(i2c2),
+   UNIPHIER_PINCTRL_GROUP(i2c3),
+   UNIPHIER_PINCTRL_GROUP(i2c6),
+   UNIPHIER_PINCTRL_GROUP(nand),
+   UNIPHIER_PINCTRL_GROUP(nand_cs1),
+   UNIPHIER_PINCTRL_GROUP(uart0),
+   UNIPHIER_PINCTRL_GROUP(uart1),
+   UNIPHIER_PINCTRL_GROUP(uart2),
+   UNIPHIER_PINCTRL_GROUP(uart3),
+   UNIPHIER_PINCTRL_GROUP(usb0),
+   UNIPHIER_PINCTRL_GROUP(usb1),
+   UNIPHIER_PINCTRL_GROUP(usb2),
+   UNIPHIER_PINCTRL_GROUP(usb3),
+   UNIPHIER_PINCTRL_GROUP(sd),
+   UNIPHIER_PINCTRL_GROUP(sd1),
+};
+
+static const char * const ph1_pro4_functions[] = {
+   

[U-Boot] [PATCH v2 00/18] ARM: uniphier: use pinctrl drivers and some cleanups

[Masahiro Yamada]

Masahiro Yamada (18):
  pinctrl: uniphier: add UniPhier pinctrl core support
  pinctrl: uniphier: add UniPhier PH1-LD4 pinctrl driver
  pinctrl: uniphier: add UniPhier PH1-Pro4 pinctrl driver
  pinctrl: uniphier: add UniPhier PH1-sLD8 pinctrl driver
  pinctrl: uniphier: add UniPhier PH1-Pro5 pinctrl driver
  pinctrl: uniphier: add UniPhier ProXstream2 pinctrl driver
  pinctrl: uniphier: add UniPhier PH1-LD6b pinctrl driver
  ARM: uniphier: enable simple-bus driver for SPL
  ARM: uniphier: increase CONFIG_SYS_MALLOC_F_LEN to bind all nodes
  ARM: dts: uniphier: prepare device trees to use pinctrl in SPL
  ARM: uniphier: enable PINCTRL and SPL_PINCTRL
  ARM: uniphier: drop ad-hoc early pin-muxing settings
  ARM: uniphier: drop ad-hoc input enable settings
  ARM: uniphier: drop DCC micro support card support
  ARM: uniphier: enable setexpr command
  ARM: uniphier: change the external bus address mapping
  ARM: uniphier: remove ifdef CONFIG_{SOC} conditionals from sg-regs.h
  ARM: uniphier: parse device tree to determine DRAM base and size

 arch/arm/dts/uniphier-ph1-ld4-ref.dts|  16 ++-
 arch/arm/dts/uniphier-ph1-ld6b-ref.dts   |  16 ++-
 arch/arm/dts/uniphier-ph1-pro4-ref.dts   |  16 ++-
 arch/arm/dts/uniphier-ph1-sld8-ref.dts   |  16 ++-
 arch/arm/mach-uniphier/Kconfig   |  23 +---
 arch/arm/mach-uniphier/Makefile  |   3 +-
 arch/arm/mach-uniphier/board_common.c|  12 --
 arch/arm/mach-uniphier/dram_init.c   |  51 +++-
 arch/arm/mach-uniphier/include/mach/board.h  |   6 +-
 arch/arm/mach-uniphier/include/mach/sg-regs.h|  40 +++---
 arch/arm/mach-uniphier/ph1-ld4/Makefile  |   7 +-
 arch/arm/mach-uniphier/ph1-ld4/early_pinctrl.c   |  27 
 arch/arm/mach-uniphier/ph1-ld4/lowlevel_debug.S  |   4 +-
 arch/arm/mach-uniphier/ph1-ld4/pinctrl.c |  46 +++
 arch/arm/mach-uniphier/ph1-ld4/sbc_init.c|  12 +-
 arch/arm/mach-uniphier/ph1-ld4/sbc_init_3cs.c|  49 
 arch/arm/mach-uniphier/ph1-ld4/sg_init.c |  18 ---
 arch/arm/mach-uniphier/ph1-pro4/Makefile |   7 +-
 arch/arm/mach-uniphier/ph1-pro4/early_pinctrl.c  |  26 
 arch/arm/mach-uniphier/ph1-pro4/lowlevel_debug.S |   4 +-
 arch/arm/mach-uniphier/ph1-pro4/pinctrl.c|  50 
 arch/arm/mach-uniphier/ph1-pro4/sbc_init.c   |  12 +-
 arch/arm/mach-uniphier/ph1-pro4/sbc_init_3cs.c   |  42 ---
 arch/arm/mach-uniphier/ph1-pro4/sg_init.c|  18 ---
 arch/arm/mach-uniphier/ph1-sld3/Makefile |   3 +-
 arch/arm/mach-uniphier/ph1-sld3/early_pinctrl.c  |  12 +-
 arch/arm/mach-uniphier/ph1-sld3/lowlevel_debug.S |   4 +-
 arch/arm/mach-uniphier/ph1-sld3/pinctrl.c|  16 +--
 arch/arm/mach-uniphier/ph1-sld3/sbc_init.c   |  14 +--
 arch/arm/mach-uniphier/ph1-sld3/sbc_init_3cs.c   |  37 --
 arch/arm/mach-uniphier/ph1-sld8/early_pinctrl.c  |  27 
 arch/arm/mach-uniphier/ph1-sld8/lowlevel_debug.S |   4 +-
 arch/arm/mach-uniphier/ph1-sld8/pinctrl.c|  55 
 arch/arm/mach-uniphier/ph1-sld8/sbc_init_3cs.c   |  57 -
 arch/arm/mach-uniphier/ph1-sld8/sg_init.c|   1 -
 arch/arm/mach-uniphier/spl.c |  13 +-
 arch/arm/mach-uniphier/support_card.c|  89 ++---
 configs/ph1_ld4_defconfig|   7 +-
 configs/ph1_pro4_defconfig   |   7 +-
 configs/ph1_sld3_defconfig   |   3 +-
 configs/ph1_sld8_defconfig   |   7 +-
 drivers/pinctrl/Kconfig  |   2 +
 drivers/pinctrl/Makefile |   2 +
 drivers/pinctrl/uniphier/Kconfig |  42 +++
 drivers/pinctrl/uniphier/Makefile|   8 ++
 drivers/pinctrl/uniphier/pinctrl-ph1-ld4.c   | 133 
 drivers/pinctrl/uniphier/pinctrl-ph1-ld6b.c  | 133 
 drivers/pinctrl/uniphier/pinctrl-ph1-pro4.c  | 129 +++
 drivers/pinctrl/uniphier/pinctrl-ph1-pro5.c  | 144 +
 drivers/pinctrl/uniphier/pinctrl-ph1-sld8.c  | 141 +
 drivers/pinctrl/uniphier/pinctrl-proxstream2.c   | 140 +
 drivers/pinctrl/uniphier/pinctrl-uniphier-core.c | 154 +++
 drivers/pinctrl/uniphier/pinctrl-uniphier.h  | 113 +
 include/configs/uniphier.h   |  35 ++
 54 files changed, 1437 insertions(+), 616 deletions(-)
 delete mode 100644 arch/arm/mach-uniphier/ph1-ld4/early_pinctrl.c
 delete mode 100644 arch/arm/mach-uniphier/ph1-ld4/sbc_init_3cs.c
 delete mode 100644 arch/arm/mach-uniphier/ph1-ld4/sg_init.c
 delete mode 100644 arch/arm/mach-uniphier/ph1-pro4/early_pinctrl.c
 delete mode 100644 arch/arm/mach-uniphier/ph1-pro4/sbc_init_3cs.c
 delete mode 100644 arch/arm/mach-uniphier/ph1-pro4/sg_init.c
 delete mode 100644 arch/arm/mach-uniphier/ph1-sld3/sbc_init_3cs.c
 delete mode 

[U-Boot] [PATCH v2 06/18] pinctrl: uniphier: add UniPhier ProXstream2 pinctrl driver

[Masahiro Yamada]

Add pin configuration and pinmux support for UniPhier ProXstream2
SoC.

Signed-off-by: Masahiro Yamada 
---

Changes in v2:
  - Add input-enable settings
  - Sync pin-mux table with Linux pinctrl driver

 drivers/pinctrl/uniphier/Kconfig   |   6 ++
 drivers/pinctrl/uniphier/Makefile  |   1 +
 drivers/pinctrl/uniphier/pinctrl-proxstream2.c | 140 +
 3 files changed, 147 insertions(+)
 create mode 100644 drivers/pinctrl/uniphier/pinctrl-proxstream2.c

diff --git a/drivers/pinctrl/uniphier/Kconfig b/drivers/pinctrl/uniphier/Kconfig
index 9d3065d..7f729b6 100644
--- a/drivers/pinctrl/uniphier/Kconfig
+++ b/drivers/pinctrl/uniphier/Kconfig
@@ -27,4 +27,10 @@ config PINCTRL_UNIPHIER_PH1_PRO5
default y
select PINCTRL_UNIPHIER_CORE
 
+config PINCTRL_UNIPHIER_PROXSTREAM2
+   bool "UniPhier ProXstream2 SoC pinctrl driver"
+   depends on MACH_PROXSTREAM2
+   default y
+   select PINCTRL_UNIPHIER_CORE
+
 endif
diff --git a/drivers/pinctrl/uniphier/Makefile 
b/drivers/pinctrl/uniphier/Makefile
index b0cd3e8..aed038c 100644
--- a/drivers/pinctrl/uniphier/Makefile
+++ b/drivers/pinctrl/uniphier/Makefile
@@ -4,3 +4,4 @@ obj-$(CONFIG_PINCTRL_UNIPHIER_PH1_LD4)  += 
pinctrl-ph1-ld4.o
 obj-$(CONFIG_PINCTRL_UNIPHIER_PH1_PRO4)+= pinctrl-ph1-pro4.o
 obj-$(CONFIG_PINCTRL_UNIPHIER_PH1_SLD8)+= pinctrl-ph1-sld8.o
 obj-$(CONFIG_PINCTRL_UNIPHIER_PH1_PRO5)+= pinctrl-ph1-pro5.o
+obj-$(CONFIG_PINCTRL_UNIPHIER_PROXSTREAM2) += pinctrl-proxstream2.o
diff --git a/drivers/pinctrl/uniphier/pinctrl-proxstream2.c 
b/drivers/pinctrl/uniphier/pinctrl-proxstream2.c
new file mode 100644
index 000..aefd61f
--- /dev/null
+++ b/drivers/pinctrl/uniphier/pinctrl-proxstream2.c
@@ -0,0 +1,140 @@
+/*
+ * Copyright (C) 2015 Masahiro Yamada 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+
+#include "pinctrl-uniphier.h"
+
+static const struct uniphier_pinctrl_pin proxstream2_pins[] = {
+   UNIPHIER_PINCTRL_PIN(113, 0),
+   UNIPHIER_PINCTRL_PIN(114, 0),
+   UNIPHIER_PINCTRL_PIN(115, 0),
+   UNIPHIER_PINCTRL_PIN(116, 0),
+};
+
+static const unsigned emmc_pins[] = {36, 37, 38, 39, 40, 41, 42};
+static const unsigned emmc_muxvals[] = {9, 9, 9, 9, 9, 9, 9};
+static const unsigned emmc_dat8_pins[] = {43, 44, 45, 46};
+static const unsigned emmc_dat8_muxvals[] = {9, 9, 9, 9};
+static const unsigned i2c0_pins[] = {109, 110};
+static const unsigned i2c0_muxvals[] = {8, 8};
+static const unsigned i2c1_pins[] = {111, 112};
+static const unsigned i2c1_muxvals[] = {8, 8};
+static const unsigned i2c2_pins[] = {171, 172};
+static const unsigned i2c2_muxvals[] = {8, 8};
+static const unsigned i2c3_pins[] = {159, 160};
+static const unsigned i2c3_muxvals[] = {8, 8};
+static const unsigned i2c5_pins[] = {183, 184};
+static const unsigned i2c5_muxvals[] = {11, 11};
+static const unsigned i2c6_pins[] = {185, 186};
+static const unsigned i2c6_muxvals[] = {11, 11};
+static const unsigned nand_pins[] = {30, 31, 32, 33, 34, 35, 36, 39, 40, 41,
+42, 43, 44, 45, 46};
+static const unsigned nand_muxvals[] = {8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8,
+   8, 8};
+static const unsigned nand_cs1_pins[] = {37, 38};
+static const unsigned nand_cs1_muxvals[] = {8, 8};
+static const unsigned uart0_pins[] = {217, 218};
+static const unsigned uart0_muxvals[] = {8, 8};
+static const unsigned uart0b_pins[] = {179, 180};
+static const unsigned uart0b_muxvals[] = {10, 10};
+static const unsigned uart1_pins[] = {115, 116};
+static const unsigned uart1_muxvals[] = {8, 8};
+static const unsigned uart2_pins[] = {113, 114};
+static const unsigned uart2_muxvals[] = {8, 8};
+static const unsigned uart3_pins[] = {219, 220};
+static const unsigned uart3_muxvals[] = {8, 8};
+static const unsigned uart3b_pins[] = {181, 182};
+static const unsigned uart3b_muxvals[] = {10, 10};
+static const unsigned usb0_pins[] = {56, 57};
+static const unsigned usb0_muxvals[] = {8, 8};
+static const unsigned usb1_pins[] = {58, 59};
+static const unsigned usb1_muxvals[] = {8, 8};
+static const unsigned usb2_pins[] = {60, 61};
+static const unsigned usb2_muxvals[] = {8, 8};
+static const unsigned usb3_pins[] = {62, 63};
+static const unsigned usb3_muxvals[] = {8, 8};
+static const unsigned sd_pins[] = {47, 48, 49, 50, 51, 52, 53, 54, 55};
+static const unsigned sd_muxvals[] = {8, 8, 8, 8, 8, 8, 8, 8, 8};
+
+static const struct uniphier_pinctrl_group proxstream2_groups[] = {
+   UNIPHIER_PINCTRL_GROUP(emmc),
+   UNIPHIER_PINCTRL_GROUP(emmc_dat8),
+   UNIPHIER_PINCTRL_GROUP(i2c0),
+   UNIPHIER_PINCTRL_GROUP(i2c1),
+   UNIPHIER_PINCTRL_GROUP(i2c2),
+   UNIPHIER_PINCTRL_GROUP(i2c3),
+   UNIPHIER_PINCTRL_GROUP(i2c5),
+   UNIPHIER_PINCTRL_GROUP(i2c6),
+   UNIPHIER_PINCTRL_GROUP(nand),
+  

[U-Boot] [PATCH v2 05/18] pinctrl: uniphier: add UniPhier PH1-Pro5 pinctrl driver

[Masahiro Yamada]

Add pin configuration and pinmux support for UniPhier PH1-Pro5 SoC.

Signed-off-by: Masahiro Yamada 
---

Changes in v2:
  - Add input-enable settings
  - Sync pin-mux table with Linux pinctrl driver

 drivers/pinctrl/uniphier/Kconfig|   6 ++
 drivers/pinctrl/uniphier/Makefile   |   1 +
 drivers/pinctrl/uniphier/pinctrl-ph1-pro5.c | 144 
 3 files changed, 151 insertions(+)
 create mode 100644 drivers/pinctrl/uniphier/pinctrl-ph1-pro5.c

diff --git a/drivers/pinctrl/uniphier/Kconfig b/drivers/pinctrl/uniphier/Kconfig
index a156a28..9d3065d 100644
--- a/drivers/pinctrl/uniphier/Kconfig
+++ b/drivers/pinctrl/uniphier/Kconfig
@@ -21,4 +21,10 @@ config PINCTRL_UNIPHIER_PH1_SLD8
default y
select PINCTRL_UNIPHIER_CORE
 
+config PINCTRL_UNIPHIER_PH1_PRO5
+   bool "UniPhier PH1-Pro5 SoC pinctrl driver"
+   depends on MACH_PH1_PRO5
+   default y
+   select PINCTRL_UNIPHIER_CORE
+
 endif
diff --git a/drivers/pinctrl/uniphier/Makefile 
b/drivers/pinctrl/uniphier/Makefile
index 3349fff..b0cd3e8 100644
--- a/drivers/pinctrl/uniphier/Makefile
+++ b/drivers/pinctrl/uniphier/Makefile
@@ -3,3 +3,4 @@ obj-$(CONFIG_PINCTRL_UNIPHIER_CORE) += 
pinctrl-uniphier-core.o
 obj-$(CONFIG_PINCTRL_UNIPHIER_PH1_LD4) += pinctrl-ph1-ld4.o
 obj-$(CONFIG_PINCTRL_UNIPHIER_PH1_PRO4)+= pinctrl-ph1-pro4.o
 obj-$(CONFIG_PINCTRL_UNIPHIER_PH1_SLD8)+= pinctrl-ph1-sld8.o
+obj-$(CONFIG_PINCTRL_UNIPHIER_PH1_PRO5)+= pinctrl-ph1-pro5.o
diff --git a/drivers/pinctrl/uniphier/pinctrl-ph1-pro5.c 
b/drivers/pinctrl/uniphier/pinctrl-ph1-pro5.c
new file mode 100644
index 000..03baf45
--- /dev/null
+++ b/drivers/pinctrl/uniphier/pinctrl-ph1-pro5.c
@@ -0,0 +1,144 @@
+/*
+ * Copyright (C) 2015 Masahiro Yamada 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+
+#include "pinctrl-uniphier.h"
+
+static const struct uniphier_pinctrl_pin ph1_pro5_pins[] = {
+   UNIPHIER_PINCTRL_PIN(47, 0),
+   UNIPHIER_PINCTRL_PIN(48, 0),
+   UNIPHIER_PINCTRL_PIN(49, 0),
+   UNIPHIER_PINCTRL_PIN(50, 0),
+   UNIPHIER_PINCTRL_PIN(53, 0),
+   UNIPHIER_PINCTRL_PIN(54, 0),
+   UNIPHIER_PINCTRL_PIN(87, 0),
+   UNIPHIER_PINCTRL_PIN(88, 0),
+   UNIPHIER_PINCTRL_PIN(101, 0),
+   UNIPHIER_PINCTRL_PIN(102, 0),
+};
+
+static const unsigned emmc_pins[] = {36, 37, 38, 39, 40, 41, 42};
+static const unsigned emmc_muxvals[] = {0, 0, 0, 0, 0, 0, 0};
+static const unsigned emmc_dat8_pins[] = {43, 44, 45, 46};
+static const unsigned emmc_dat8_muxvals[] = {0, 0, 0, 0};
+static const unsigned i2c0_pins[] = {112, 113};
+static const unsigned i2c0_muxvals[] = {0, 0};
+static const unsigned i2c1_pins[] = {114, 115};
+static const unsigned i2c1_muxvals[] = {0, 0};
+static const unsigned i2c2_pins[] = {116, 117};
+static const unsigned i2c2_muxvals[] = {0, 0};
+static const unsigned i2c3_pins[] = {118, 119};
+static const unsigned i2c3_muxvals[] = {0, 0};
+static const unsigned i2c5_pins[] = {87, 88};
+static const unsigned i2c5_muxvals[] = {2, 2};
+static const unsigned i2c5b_pins[] = {196, 197};
+static const unsigned i2c5b_muxvals[] = {2, 2};
+static const unsigned i2c5c_pins[] = {215, 216};
+static const unsigned i2c5c_muxvals[] = {2, 2};
+static const unsigned i2c6_pins[] = {101, 102};
+static const unsigned i2c6_muxvals[] = {2, 2};
+static const unsigned nand_pins[] = {19, 20, 21, 22, 23, 24, 25, 28, 29, 30,
+31, 32, 33, 34, 35};
+static const unsigned nand_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+   0, 0};
+static const unsigned nand_cs1_pins[] = {26, 27};
+static const unsigned nand_cs1_muxvals[] = {0, 0};
+static const unsigned uart0_pins[] = {47, 48};
+static const unsigned uart0_muxvals[] = {0, 0};
+static const unsigned uart0b_pins[] = {227, 228};
+static const unsigned uart0b_muxvals[] = {3, 3};
+static const unsigned uart1_pins[] = {49, 50};
+static const unsigned uart1_muxvals[] = {0, 0};
+static const unsigned uart2_pins[] = {51, 52};
+static const unsigned uart2_muxvals[] = {0, 0};
+static const unsigned uart3_pins[] = {53, 54};
+static const unsigned uart3_muxvals[] = {0, 0};
+static const unsigned usb0_pins[] = {124, 125};
+static const unsigned usb0_muxvals[] = {0, 0};
+static const unsigned usb1_pins[] = {126, 127};
+static const unsigned usb1_muxvals[] = {0, 0};
+static const unsigned usb2_pins[] = {128, 129};
+static const unsigned usb2_muxvals[] = {0, 0};
+static const unsigned sd_pins[] = {250, 251, 252, 253, 254, 255, 256, 257, 
258};
+static const unsigned sd_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0};
+
+static const struct uniphier_pinctrl_group ph1_pro5_groups[] = {
+   UNIPHIER_PINCTRL_GROUP(emmc),
+   UNIPHIER_PINCTRL_GROUP(emmc_dat8),
+   UNIPHIER_PINCTRL_GROUP(i2c0),
+   UNIPHIER_PINCTRL_GROUP(i2c1),
+  

[U-Boot] [PATCH v2 15/18] ARM: uniphier: enable setexpr command

[Masahiro Yamada]

This command will be used in the next commit to calculate
base-offseted addresses.

Signed-off-by: Masahiro Yamada 
---

Changes in v2: None

 configs/ph1_ld4_defconfig  | 1 -
 configs/ph1_pro4_defconfig | 1 -
 configs/ph1_sld3_defconfig | 1 -
 configs/ph1_sld8_defconfig | 1 -
 4 files changed, 4 deletions(-)

diff --git a/configs/ph1_ld4_defconfig b/configs/ph1_ld4_defconfig
index e9744a3..899a723 100644
--- a/configs/ph1_ld4_defconfig
+++ b/configs/ph1_ld4_defconfig
@@ -12,7 +12,6 @@ CONFIG_CMD_NAND=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
-# CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_TFTPPUT=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_TIME=y
diff --git a/configs/ph1_pro4_defconfig b/configs/ph1_pro4_defconfig
index 1b3092d..139767a 100644
--- a/configs/ph1_pro4_defconfig
+++ b/configs/ph1_pro4_defconfig
@@ -11,7 +11,6 @@ CONFIG_CMD_NAND=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
-# CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_TFTPPUT=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_TIME=y
diff --git a/configs/ph1_sld3_defconfig b/configs/ph1_sld3_defconfig
index df908e2..79ce0e2 100644
--- a/configs/ph1_sld3_defconfig
+++ b/configs/ph1_sld3_defconfig
@@ -11,7 +11,6 @@ CONFIG_CMD_NAND=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
-# CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_TFTPPUT=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_TIME=y
diff --git a/configs/ph1_sld8_defconfig b/configs/ph1_sld8_defconfig
index 8151562..216d49b 100644
--- a/configs/ph1_sld8_defconfig
+++ b/configs/ph1_sld8_defconfig
@@ -12,7 +12,6 @@ CONFIG_CMD_NAND=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
-# CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_TFTPPUT=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_TIME=y
-- 
1.9.1

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[U-Boot] [PATCH v2 11/18] ARM: uniphier: enable PINCTRL and SPL_PINCTRL

[Masahiro Yamada]

Now, UniPhier SoCs are ready to enable pinctrl drivers.

Signed-off-by: Masahiro Yamada 
---

Changes in v2: None

 configs/ph1_ld4_defconfig  | 2 ++
 configs/ph1_pro4_defconfig | 2 ++
 configs/ph1_sld8_defconfig | 2 ++
 3 files changed, 6 insertions(+)

diff --git a/configs/ph1_ld4_defconfig b/configs/ph1_ld4_defconfig
index 61eb037..13b124b 100644
--- a/configs/ph1_ld4_defconfig
+++ b/configs/ph1_ld4_defconfig
@@ -24,6 +24,8 @@ CONFIG_SYS_NAND_DENALI_64BIT=y
 CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8
 CONFIG_SPL_NAND_DENALI=y
 CONFIG_UNIPHIER_SERIAL=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
 CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_STORAGE=y
diff --git a/configs/ph1_pro4_defconfig b/configs/ph1_pro4_defconfig
index 7582fdf..0982d91 100644
--- a/configs/ph1_pro4_defconfig
+++ b/configs/ph1_pro4_defconfig
@@ -23,6 +23,8 @@ CONFIG_SYS_NAND_DENALI_64BIT=y
 CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8
 CONFIG_SPL_NAND_DENALI=y
 CONFIG_UNIPHIER_SERIAL=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_STORAGE=y
diff --git a/configs/ph1_sld8_defconfig b/configs/ph1_sld8_defconfig
index 236e673..584c41a 100644
--- a/configs/ph1_sld8_defconfig
+++ b/configs/ph1_sld8_defconfig
@@ -24,6 +24,8 @@ CONFIG_SYS_NAND_DENALI_64BIT=y
 CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8
 CONFIG_SPL_NAND_DENALI=y
 CONFIG_UNIPHIER_SERIAL=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
 CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_STORAGE=y
-- 
1.9.1

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[U-Boot] [PATCH v2 18/18] ARM: uniphier: parse device tree to determine DRAM base and size

[Masahiro Yamada]

Device tree specifies the available memory ranges in its "/memory"
node.  Use it to simplify the CONFIG defines.

Signed-off-by: Masahiro Yamada 
---

Changes in v2: None

 arch/arm/mach-uniphier/board_common.c | 12 -
 arch/arm/mach-uniphier/dram_init.c| 51 ---
 include/configs/uniphier.h| 11 +---
 3 files changed, 48 insertions(+), 26 deletions(-)

diff --git a/arch/arm/mach-uniphier/board_common.c 
b/arch/arm/mach-uniphier/board_common.c
index 5f2d5f6..967fa6c 100644
--- a/arch/arm/mach-uniphier/board_common.c
+++ b/arch/arm/mach-uniphier/board_common.c
@@ -18,15 +18,3 @@ int board_init(void)
 
return 0;
 }
-
-#if CONFIG_NR_DRAM_BANKS >= 2
-void dram_init_banksize(void)
-{
-   DECLARE_GLOBAL_DATA_PTR;
-
-   gd->bd->bi_dram[0].start = CONFIG_SDRAM0_BASE;
-   gd->bd->bi_dram[0].size  = CONFIG_SDRAM0_SIZE;
-   gd->bd->bi_dram[1].start = CONFIG_SDRAM1_BASE;
-   gd->bd->bi_dram[1].size  = CONFIG_SDRAM1_SIZE;
-}
-#endif
diff --git a/arch/arm/mach-uniphier/dram_init.c 
b/arch/arm/mach-uniphier/dram_init.c
index 4b8c938..32cc448 100644
--- a/arch/arm/mach-uniphier/dram_init.c
+++ b/arch/arm/mach-uniphier/dram_init.c
@@ -1,16 +1,59 @@
 /*
- * Copyright (C) 2012-2015 Panasonic Corporation
- *   Author: Masahiro Yamada 
+ * Copyright (C) 2012-2015 Masahiro Yamada 
  *
  * SPDX-License-Identifier:GPL-2.0+
  */
 
 #include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const void *get_memory_reg_prop(const void *fdt, int *lenp)
+{
+   int offset;
+
+   offset = fdt_path_offset(fdt, "/memory");
+   if (offset < 0)
+   return NULL;
+
+   return fdt_getprop(fdt, offset, "reg", lenp);
+}
 
 int dram_init(void)
 {
-   DECLARE_GLOBAL_DATA_PTR;
-   gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+   const fdt32_t *val;
+   int len;
+
+   val = get_memory_reg_prop(gd->fdt_blob, );
+   if (len < sizeof(*val))
+   return -EINVAL;
+
+   gd->ram_size = fdt32_to_cpu(*(val + 1));
+
+   debug("DRAM size = %08lx\n", gd->ram_size);
 
return 0;
 }
+
+void dram_init_banksize(void)
+{
+   const fdt32_t *val;
+   int len, i;
+
+   val = get_memory_reg_prop(gd->fdt_blob, );
+   if (len < 0)
+   return;
+
+   len /= sizeof(*val);
+   len /= 2;
+
+   for (i = 0; i < len; i++) {
+   gd->bd->bi_dram[i].start = fdt32_to_cpu(*val++);
+   gd->bd->bi_dram[i].size = fdt32_to_cpu(*val++);
+
+   debug("DRAM bank %d: start = %08lx, size = %08lx\n",
+ i, gd->bd->bi_dram[i].start, gd->bd->bi_dram[i].size);
+   }
+}
diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h
index 45b39c0..a15838b 100644
--- a/include/configs/uniphier.h
+++ b/include/configs/uniphier.h
@@ -295,17 +295,8 @@
 /* Open Firmware flat tree */
 #define CONFIG_OF_LIBFDT
 
-/* Memory Size & Mapping */
-#define CONFIG_SYS_SDRAM_BASE  CONFIG_SDRAM0_BASE
-
-#if CONFIG_SDRAM0_BASE + CONFIG_SDRAM0_SIZE >= CONFIG_SDRAM1_BASE
-/* Thre is no memory hole */
-#define CONFIG_NR_DRAM_BANKS   1
-#define CONFIG_SYS_SDRAM_SIZE  (CONFIG_SDRAM0_SIZE + CONFIG_SDRAM1_SIZE)
-#else
+#define CONFIG_SYS_SDRAM_BASE  0x8000
 #define CONFIG_NR_DRAM_BANKS   2
-#define CONFIG_SYS_SDRAM_SIZE  (CONFIG_SDRAM0_SIZE)
-#endif
 
 #if defined(CONFIG_MACH_PH1_SLD3) || defined(CONFIG_MACH_PH1_LD4) || \
defined(CONFIG_MACH_PH1_SLD8)
-- 
1.9.1

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[U-Boot] [PATCH 07/14] ARMv8/FSL_LSCH2: Add FSL_LSCH2 SoC

[Gong Qianyu]

From: Mingkai Hu 

Freescale LayerScape with Chassis Generation 2 is a set of SoCs with
ARMv8 cores and 2rd generation of Chassis.

Signed-off-by: Li Yang 
Signed-off-by: Hou Zhiqiang 
Signed-off-by: Mingkai Hu 
Signed-off-by: Gong Qianyu 
---
 arch/arm/cpu/armv8/Makefile   |   1 +
 arch/arm/cpu/armv8/fsl-lsch2/Makefile |  12 +
 arch/arm/cpu/armv8/fsl-lsch2/README   |  10 +
 arch/arm/cpu/armv8/fsl-lsch2/cpu.c| 414 ++
 arch/arm/cpu/armv8/fsl-lsch2/fdt.c|  13 +
 arch/arm/cpu/armv8/fsl-lsch2/fsl_lsch2_serdes.c   | 116 +
 arch/arm/cpu/armv8/fsl-lsch2/lowlevel.S   | 122 ++
 arch/arm/cpu/armv8/fsl-lsch2/ls1043a_serdes.c |  86 
 arch/arm/cpu/armv8/fsl-lsch2/soc.c|  36 ++
 arch/arm/cpu/armv8/fsl-lsch2/speed.c  | 137 ++
 arch/arm/cpu/armv8/fsl-lsch2/speed.h  |   7 +
 arch/arm/include/asm/arch-fsl-lsch2/clock.h   |  24 ++
 arch/arm/include/asm/arch-fsl-lsch2/config.h  | 148 +++
 arch/arm/include/asm/arch-fsl-lsch2/fsl_serdes.h  | 105 +
 arch/arm/include/asm/arch-fsl-lsch2/gpio.h|   9 +
 arch/arm/include/asm/arch-fsl-lsch2/immap_lsch2.h | 499 ++
 arch/arm/include/asm/arch-fsl-lsch2/imx-regs.h|  52 +++
 arch/arm/include/asm/arch-fsl-lsch2/mmu.h |  10 +
 arch/arm/include/asm/arch-fsl-lsch2/ns_access.h   | 179 
 arch/arm/include/asm/arch-fsl-lsch2/soc.h |   7 +
 arch/arm/include/asm/arch-fsl-lsch2/spl.h |  20 +
 arch/arm/include/asm/armv8/mmu.h  |   1 +
 arch/arm/include/asm/config.h |   3 +
 include/common.h  |   3 +
 24 files changed, 2014 insertions(+)

diff --git a/arch/arm/cpu/armv8/Makefile b/arch/arm/cpu/armv8/Makefile
index adb11b3..eee8344 100644
--- a/arch/arm/cpu/armv8/Makefile
+++ b/arch/arm/cpu/armv8/Makefile
@@ -15,6 +15,7 @@ obj-y += cache.o
 obj-y  += tlb.o
 obj-y  += transition.o
 
+obj-$(CONFIG_FSL_LSCH2) += fsl-lsch2/
 obj-$(CONFIG_FSL_LSCH3) += fsl-lsch3/
 obj-$(CONFIG_ARCH_ZYNQMP) += zynqmp/
 obj-$(CONFIG_TARGET_HIKEY) += hisilicon/
diff --git a/arch/arm/cpu/armv8/fsl-lsch2/Makefile 
b/arch/arm/cpu/armv8/fsl-lsch2/Makefile
new file mode 100644
index 000..23c5bf9
--- /dev/null
+++ b/arch/arm/cpu/armv8/fsl-lsch2/Makefile
@@ -0,0 +1,12 @@
+#
+# Copyright 2014, Freescale Semiconductor
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += cpu.o
+obj-y += soc.o
+obj-y += lowlevel.o
+obj-y += speed.o
+obj-$(CONFIG_SYS_HAS_SERDES) += fsl_lsch2_serdes.o ls1043a_serdes.o
+obj-$(CONFIG_OF_LIBFDT) += fdt.o
diff --git a/arch/arm/cpu/armv8/fsl-lsch2/README 
b/arch/arm/cpu/armv8/fsl-lsch2/README
new file mode 100644
index 000..1e71ad7
--- /dev/null
+++ b/arch/arm/cpu/armv8/fsl-lsch2/README
@@ -0,0 +1,10 @@
+#
+# Copyright 2014 Freescale Semiconductor
+#
+# SPDX-License-Identifier:  GPL-2.0+
+#
+
+Freescale LayerScape with Chassis Generation 2
+
+This architecture supports Freescale ARMv8 SoCs with Chassis generation 2,
+for example LS1043A.
diff --git a/arch/arm/cpu/armv8/fsl-lsch2/cpu.c 
b/arch/arm/cpu/armv8/fsl-lsch2/cpu.c
new file mode 100644
index 000..f81ad83
--- /dev/null
+++ b/arch/arm/cpu/armv8/fsl-lsch2/cpu.c
@@ -0,0 +1,414 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include "speed.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+/*
+ * To start MMU before DDR is available, we create MMU table in SRAM.
+ * The base address of SRAM is CONFIG_SYS_FSL_OCRAM_BASE. We use three
+ * levels of translation tables here to cover 40-bit address space.
+ * We use 4KB granule size, with 40 bits physical address, T0SZ=24
+ * Level 0 IA[39], table address @0
+ * Level 1 IA[31:30], table address @01000, 0x2000
+ * Level 2 IA[29:21], table address @0x3000
+ */
+
+#define SECTION_SHIFT_L0   39UL
+#define SECTION_SHIFT_L1   30UL
+#define SECTION_SHIFT_L2   21UL
+#define BLOCK_SIZE_L0  0x80UL
+#define BLOCK_SIZE_L1  (1 << SECTION_SHIFT_L1)
+#define BLOCK_SIZE_L2  (1 << SECTION_SHIFT_L2)
+#define CONFIG_SYS_IFC_BASE0x6000UL
+#define CONFIG_SYS_IFC_SIZE0x2000UL
+#define CONFIG_SYS_IFC_BASE2   0x62000UL
+#define CONFIG_SYS_IFC_SIZE2   0x0e000UL
+#define TCR_EL2_PS_40BIT   (2 << 16)
+#define LSCH2_VA_BITS  (40)
+#define LSCH2_TCR  (TCR_TG0_4K | \
+   TCR_EL2_PS_40BIT| \
+   TCR_SHARED_NON  | \
+   TCR_ORGN_NC | \
+   TCR_IRGN_NC | \
+   TCR_T0SZ(LSCH2_VA_BITS))
+#define LSCH2_TCR_FINAL(TCR_TG0_4K | \
+ 

[U-Boot] [PATCH 10/14] armv8/ls1043ardb: Add cpld command to boot from nand

[Gong Qianyu]

Signed-off-by: Gong Qianyu 
---
 board/freescale/ls1043ardb/cpld.c | 18 ++
 board/freescale/ls1043ardb/cpld.h |  1 +
 2 files changed, 19 insertions(+)

diff --git a/board/freescale/ls1043ardb/cpld.c 
b/board/freescale/ls1043ardb/cpld.c
index 3f1101e..5acb97d 100644
--- a/board/freescale/ls1043ardb/cpld.c
+++ b/board/freescale/ls1043ardb/cpld.c
@@ -45,6 +45,21 @@ void cpld_set_defbank(void)
CPLD_WRITE(global_rst, 1);
 }
 
+void cpld_set_nand(void)
+{
+   u16 reg = CPLD_CFG_RCW_SRC_NAND;
+   u8 reg5 = (u8)(reg >> 1);
+   u8 reg6 = (u8)(reg & 1);
+   cpld_rev_bit();
+
+   CPLD_WRITE(soft_mux_on, 1);
+
+   CPLD_WRITE(cfg_rcw_src1, reg5);
+   CPLD_WRITE(cfg_rcw_src2, reg6);
+
+   CPLD_WRITE(system_rst, 1);
+}
+
 #ifdef DEBUG
 static void cpld_dump_regs(void)
 {
@@ -91,6 +106,8 @@ int do_cpld(cmd_tbl_t *cmdtp, int flag, int argc, char * 
const argv[])
if (strcmp(argv[1], "reset") == 0) {
if (strcmp(argv[2], "altbank") == 0)
cpld_set_altbank();
+   else if (strcmp(argv[2], "nand") == 0)
+   cpld_set_nand();
else
cpld_set_defbank();
 #ifdef DEBUG
@@ -109,6 +126,7 @@ U_BOOT_CMD(
"Reset the board or alternate bank",
"reset: reset to default bank\n"
"cpld reset altbank: reset to alternate bank\n"
+   "cpld reset nand: reset to boot from NAND flash\n"
 #ifdef DEBUG
"cpld dump - display the CPLD registers\n"
 #endif
diff --git a/board/freescale/ls1043ardb/cpld.h 
b/board/freescale/ls1043ardb/cpld.h
index ea4efd8..5f43a8a 100644
--- a/board/freescale/ls1043ardb/cpld.h
+++ b/board/freescale/ls1043ardb/cpld.h
@@ -40,4 +40,5 @@ void cpld_rev_bit(unsigned char *value);
 #define CPLD_SW_MUX_BANK_SEL   0x40
 #define CPLD_BANK_SEL_MASK 0x07
 #define CPLD_BANK_SEL_ALTBANK  0x04
+#define CPLD_CFG_RCW_SRC_NAND  0x106
 #endif
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH 11/14] armv8/ls1043a: Add Fman support

[Gong Qianyu]

From: Shaohui Xie 

Signed-off-by: Hou Zhiqiang 
Signed-off-by: Shaohui Xie 
Signed-off-by: Mingkai Hu 
Signed-off-by: Gong Qianyu 
---
 arch/arm/cpu/armv8/fsl-lsch2/cpu.c  |  19 +
 arch/arm/cpu/armv8/fsl-lsch2/fdt.c  |   7 ++
 arch/arm/cpu/armv8/fsl-lsch2/speed.c|  23 ++
 board/freescale/common/fman.c   |   6 +-
 board/freescale/ls1043ardb/Makefile |   1 +
 board/freescale/ls1043ardb/eth.c|  77 +
 board/freescale/ls1043ardb/ls1043ardb.c |   4 ++
 drivers/net/fm/Makefile |   1 +
 drivers/net/fm/init.c   |  10 ++-
 drivers/net/fm/ls1043.c | 119 
 include/configs/ls1043a_common.h|  12 
 include/configs/ls1043ardb.h|  25 +++
 12 files changed, 301 insertions(+), 3 deletions(-)

diff --git a/arch/arm/cpu/armv8/fsl-lsch2/cpu.c 
b/arch/arm/cpu/armv8/fsl-lsch2/cpu.c
index f81ad83..c358534 100644
--- a/arch/arm/cpu/armv8/fsl-lsch2/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-lsch2/cpu.c
@@ -11,6 +11,7 @@
 #include 
 #include 
 #include 
+#include 
 #include "speed.h"
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -358,6 +359,9 @@ int print_cpuinfo(void)
printf("\n   Bus:  %-4s MHz  ",
   strmhz(buf, sysinfo.freq_systembus));
printf("DDR:  %-4s MT/s", strmhz(buf, sysinfo.freq_ddrbus));
+#ifdef CONFIG_SYS_DPAA_FMAN
+   printf("  FMAN: %-4s MHz", strmhz(buf, sysinfo.freq_fman[0]));
+#endif
puts("\n");
 
/*
@@ -378,11 +382,26 @@ int print_cpuinfo(void)
 }
 #endif
 
+/*
+ * Initializes on-chip ethernet controllers.
+ * to override, implement board_eth_init()
+ */
+int cpu_eth_init(bd_t *bis)
+{
+#ifdef CONFIG_FMAN_ENET
+   fm_standard_init(bis);
+#endif
+   return 0;
+}
+
 int arch_early_init_r(void)
 {
 #ifdef CONFIG_SYS_HAS_SERDES
fsl_serdes_init();
 #endif
+#ifdef CONFIG_FMAN_ENET
+   fman_enet_init();
+#endif
return 0;
 }
 
diff --git a/arch/arm/cpu/armv8/fsl-lsch2/fdt.c 
b/arch/arm/cpu/armv8/fsl-lsch2/fdt.c
index b4af812..fd9063d 100644
--- a/arch/arm/cpu/armv8/fsl-lsch2/fdt.c
+++ b/arch/arm/cpu/armv8/fsl-lsch2/fdt.c
@@ -7,6 +7,13 @@
 #include 
 #include 
 #include 
+#include 
+
+int fdt_fixup_phy_connection(void *blob, int offset, phy_interface_t phyc)
+{
+   return fdt_setprop_string(blob, offset, "phy-connection-type",
+phy_string_for_interface(phyc));
+}
 
 void ft_cpu_setup(void *blob, bd_t *bd)
 {
diff --git a/arch/arm/cpu/armv8/fsl-lsch2/speed.c 
b/arch/arm/cpu/armv8/fsl-lsch2/speed.c
index 2912d67..f5a7f73 100644
--- a/arch/arm/cpu/armv8/fsl-lsch2/speed.c
+++ b/arch/arm/cpu/armv8/fsl-lsch2/speed.c
@@ -25,6 +25,9 @@ void get_sys_info(struct sys_info *sys_info)
struct fsl_ifc ifc_regs = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
u32 ccr;
 #endif
+#ifdef CONFIG_SYS_DPAA_FMAN
+   u32 rcw_tmp;
+#endif
struct ccsr_clk *clk = (void *)(CONFIG_SYS_FSL_CLK_ADDR);
unsigned int cpu;
const u8 core_cplx_pll[8] = {
@@ -79,6 +82,26 @@ void get_sys_info(struct sys_info *sys_info)
 
 #define HWA_CGA_M1_CLK_SEL 0xe000
 #define HWA_CGA_M1_CLK_SHIFT   29
+#ifdef CONFIG_SYS_DPAA_FMAN
+   rcw_tmp = in_be32(>rcwsr[7]);
+   switch ((rcw_tmp & HWA_CGA_M1_CLK_SEL) >> HWA_CGA_M1_CLK_SHIFT) {
+   case 2:
+   sys_info->freq_fman[0] = freq_c_pll[0] / 2;
+   break;
+   case 3:
+   sys_info->freq_fman[0] = freq_c_pll[0] / 3;
+   break;
+   case 6:
+   sys_info->freq_fman[0] = freq_c_pll[1] / 2;
+   break;
+   case 7:
+   sys_info->freq_fman[0] = freq_c_pll[1] / 3;
+   break;
+   default:
+   printf("Error: Unknown FMan1 clock select!\n");
+   break;
+   }
+#endif
 
 #define HWA_CGA_M2_CLK_SEL 0x0007
 #define HWA_CGA_M2_CLK_SHIFT   0
diff --git a/board/freescale/common/fman.c b/board/freescale/common/fman.c
index 9dc5402..e491064 100644
--- a/board/freescale/common/fman.c
+++ b/board/freescale/common/fman.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2011 Freescale Semiconductor, Inc.
+ * Copyright 2011-2015 Freescale Semiconductor, Inc.
  *
  * SPDX-License-Identifier:GPL-2.0+
  */
@@ -10,7 +10,11 @@
 #include 
 
 #include 
+#ifdef CONFIG_FSL_LSCH2
+#include 
+#else
 #include 
+#endif
 
 /*
  * Given the following ...
diff --git a/board/freescale/ls1043ardb/Makefile 
b/board/freescale/ls1043ardb/Makefile
index dd17e2e..5fe1cc9 100644
--- a/board/freescale/ls1043ardb/Makefile
+++ b/board/freescale/ls1043ardb/Makefile
@@ -7,3 +7,4 @@
 obj-y += cpld.o
 obj-y += ddr.o
 obj-y += ls1043ardb.o
+obj-$(CONFIG_SYS_DPAA_FMAN) += eth.o
diff --git a/board/freescale/ls1043ardb/eth.c b/board/freescale/ls1043ardb/eth.c
new file mode 100644
index 

[U-Boot] [PATCH 08/14] ARMv8/ls1043ardb: Add LS1043ARDB board support

[Gong Qianyu]

From: Mingkai Hu 

LS1043ARDB Specification:
-
Memory subsystem:
 * 2GByte DDR4 SDRAM (32bit but)
 * 128 Mbyte NOR flash single-chip memory
 * 512 Mbyte NAND flash
 * 16 Mbyte high-speed SPI memory
 * SD connector to interface with the SD memory card

Ethernet:
 * XFI 10G port
 * QSGMII with 4x 1G ports
 * Two RGMII ports

PCIe:
 * PCIe2 (Lanes C) to mini-PCIe slot
 * PCIe3 (Lanes D) to PCIe slot

USB 3.0: two super speed USB 3.0 type A ports

UART: supports two UARTs up to 115200 bps for console

Signed-off-by: Hou Zhiqiang 
Signed-off-by: Li Yang 
Signed-off-by: Mingkai Hu 
Signed-off-by: Gong Qianyu 
---
 arch/arm/Kconfig|   8 ++
 board/freescale/ls1043ardb/Kconfig  |  16 +++
 board/freescale/ls1043ardb/MAINTAINERS  |   7 ++
 board/freescale/ls1043ardb/Makefile |   9 ++
 board/freescale/ls1043ardb/README   |  87 +++
 board/freescale/ls1043ardb/cpld.c   | 115 +++
 board/freescale/ls1043ardb/cpld.h   |  43 +++
 board/freescale/ls1043ardb/ddr.c| 190 +++
 board/freescale/ls1043ardb/ddr.h|  45 
 board/freescale/ls1043ardb/ls1043ardb.c | 134 ++
 configs/ls1043ardb_defconfig|   3 +
 drivers/i2c/mxc_i2c.c   |   2 +-
 include/configs/ls1043a_common.h| 131 ++
 include/configs/ls1043ardb.h| 191 
 14 files changed, 980 insertions(+), 1 deletion(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 8085a24..f935f19 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -662,6 +662,13 @@ config TARGET_LS1021ATWR
select CPU_V7
select SUPPORT_SPL
 
+config TARGET_LS1043ARDB
+   bool "Support ls1043ardb"
+   select ARM64
+   select SUPPORT_SPL
+   help
+ Support for Freescale LS1043ARDB platform.
+
 config TARGET_BALLOON3
bool "Support balloon3"
select CPU_PXA
@@ -827,6 +834,7 @@ source "board/freescale/ls2085aqds/Kconfig"
 source "board/freescale/ls2085ardb/Kconfig"
 source "board/freescale/ls1021aqds/Kconfig"
 source "board/freescale/ls1021atwr/Kconfig"
+source "board/freescale/ls1043ardb/Kconfig"
 source "board/freescale/mx23evk/Kconfig"
 source "board/freescale/mx25pdk/Kconfig"
 source "board/freescale/mx28evk/Kconfig"
diff --git a/board/freescale/ls1043ardb/Kconfig 
b/board/freescale/ls1043ardb/Kconfig
new file mode 100644
index 000..eb6a12a
--- /dev/null
+++ b/board/freescale/ls1043ardb/Kconfig
@@ -0,0 +1,16 @@
+
+if TARGET_LS1043ARDB
+
+config SYS_BOARD
+   default "ls1043ardb"
+
+config SYS_VENDOR
+   default "freescale"
+
+config SYS_SOC
+   default "fsl-lsch2"
+
+config SYS_CONFIG_NAME
+   default "ls1043ardb"
+
+endif
diff --git a/board/freescale/ls1043ardb/MAINTAINERS 
b/board/freescale/ls1043ardb/MAINTAINERS
new file mode 100644
index 000..b8f6be2
--- /dev/null
+++ b/board/freescale/ls1043ardb/MAINTAINERS
@@ -0,0 +1,7 @@
+LS1043A BOARD
+M: Mingkai Hu 
+S: Maintained
+F: board/freescale/ls1043ardb/
+F: board/freescale/ls1043ardb/ls1043ardb.c
+F: include/configs/ls1043ardb.h
+F: configs/ls1043ardb_defconfig
diff --git a/board/freescale/ls1043ardb/Makefile 
b/board/freescale/ls1043ardb/Makefile
new file mode 100644
index 000..dd17e2e
--- /dev/null
+++ b/board/freescale/ls1043ardb/Makefile
@@ -0,0 +1,9 @@
+#
+# Copyright 2015 Freescale Semiconductor
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += cpld.o
+obj-y += ddr.o
+obj-y += ls1043ardb.o
diff --git a/board/freescale/ls1043ardb/README 
b/board/freescale/ls1043ardb/README
new file mode 100644
index 000..0556e73
--- /dev/null
+++ b/board/freescale/ls1043ardb/README
@@ -0,0 +1,87 @@
+Overview
+
+The LS1043A Reference Design Board (RDB) is a high-performance computing,
+evaluation, and development platform that supports the QorIQ LS1043A
+LayerScape Architecture processor. The LS1043ARDB provides SW development
+platform for the Freescale LS1043A processor series, with a complete
+debugging environment. The LS1043A RDB is lead-free and RoHS-compliant.
+
+LS1043A SoC Overview
+
+The LS1043A integrated multicore processor combines four ARM Cortex-A53
+processor cores with datapath acceleration optimized for L2/3 packet
+processing, single pass security offload and robust traffic management
+and quality of service.
+
+The LS1043A SoC includes the following function and features:
+ - Four 64-bit ARM Cortex-A53 CPUs
+ - 1 MB unified L2 Cache
+ - One 32-bit DDR3L/DDR4 SDRAM memory controllers with ECC and interleaving
+   support
+ - Data Path Acceleration Architecture (DPAA) incorporating acceleration the
+   the following functions:
+   - Packet parsing, classification, and distribution (FMan)
+   - 

[U-Boot] [PATCH 09/14] armv8/ls1043ardb: Add nand boot support

[Gong Qianyu]

Signed-off-by: Gong Qianyu 
Signed-off-by: Hou Zhiqiang 
Signed-off-by: Shaohui Xie 
Signed-off-by: Mingkai Hu 
---
 arch/arm/Kconfig   |  1 +
 arch/arm/cpu/armv8/fsl-lsch2/Makefile  |  1 +
 arch/arm/cpu/armv8/fsl-lsch2/spl.c | 91 ++
 arch/arm/include/asm/arch-fsl-lsch2/config.h   |  2 +
 board/freescale/ls1043ardb/ls1043ardb_pbi.cfg  | 14 
 board/freescale/ls1043ardb/ls1043ardb_rcw_nand.cfg |  7 ++
 configs/ls1043ardb_nand_defconfig  |  4 +
 include/configs/ls1043a_common.h   | 31 
 include/configs/ls1043ardb.h   | 40 ++
 9 files changed, 191 insertions(+)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index f935f19..197c72d 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -612,6 +612,7 @@ config TARGET_VEXPRESS64_BASE_FVP
 config TARGET_VEXPRESS64_JUNO
bool "Support Versatile Express Juno Development Platform"
select ARM64
+   select SUPPORT_SPL
 
 config TARGET_LS2085A_EMU
bool "Support ls2085a_emu"
diff --git a/arch/arm/cpu/armv8/fsl-lsch2/Makefile 
b/arch/arm/cpu/armv8/fsl-lsch2/Makefile
index 23c5bf9..0573659 100644
--- a/arch/arm/cpu/armv8/fsl-lsch2/Makefile
+++ b/arch/arm/cpu/armv8/fsl-lsch2/Makefile
@@ -10,3 +10,4 @@ obj-y += lowlevel.o
 obj-y += speed.o
 obj-$(CONFIG_SYS_HAS_SERDES) += fsl_lsch2_serdes.o ls1043a_serdes.o
 obj-$(CONFIG_OF_LIBFDT) += fdt.o
+obj-$(CONFIG_SPL) += spl.o
diff --git a/arch/arm/cpu/armv8/fsl-lsch2/spl.c 
b/arch/arm/cpu/armv8/fsl-lsch2/spl.c
new file mode 100644
index 000..980901a
--- /dev/null
+++ b/arch/arm/cpu/armv8/fsl-lsch2/spl.c
@@ -0,0 +1,91 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include "../../../../../board/freescale/common/ns_access.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+u32 spl_boot_device(void)
+{
+#ifdef CONFIG_SPL_SPI_SUPPORT
+   return BOOT_DEVICE_SPI;
+#endif
+#ifdef CONFIG_SPL_MMC_SUPPORT
+   return BOOT_DEVICE_MMC1;
+#endif
+#ifdef CONFIG_SPL_NAND_SUPPORT
+   return BOOT_DEVICE_NAND;
+#endif
+   return 0;
+}
+
+u32 spl_boot_mode(void)
+{
+   switch (spl_boot_device()) {
+   case BOOT_DEVICE_MMC1:
+#ifdef CONFIG_SPL_FAT_SUPPORT
+   return MMCSD_MODE_FAT;
+#else
+   return MMCSD_MODE_RAW;
+#endif
+   break;
+   case BOOT_DEVICE_NAND:
+   case BOOT_DEVICE_SPI:
+   return 0;
+   break;
+   default:
+   puts("spl: error: unsupported device\n");
+   hang();
+   }
+}
+
+#ifdef CONFIG_SPL_BUILD
+void board_init_f(ulong dummy)
+{
+#ifdef CONFIG_SPL_NAND_SUPPORT
+   init_early_memctl_regs();
+
+   /*
+* There is LS1 SoC issue where NOR, FPGA are inaccessible during
+* NAND boot because IFC signals > IFC_AD7 are not enabled.
+* This workaround changes RCW source to make all signals enabled.
+*/
+   u32 porsr1, pinctl;
+   struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+   porsr1 = in_be32(>porsr1);
+   pinctl = ((porsr1 & ~(FSL_CHASSIS2_CCSR_PORSR1_RCW_MASK)) | 0x2480);
+   out_be32((unsigned int *)CONFIG_SYS_DCSR_DCFG_ADDR, pinctl);
+#endif
+
+   /* Set global data pointer */
+   gd = 
+
+   timer_init();   /* initialize timer */
+
+   get_clocks();
+
+   preloader_console_init();
+
+#ifdef CONFIG_SPL_I2C_SUPPORT
+   i2c_init_all();
+#endif
+   dram_init();
+
+   /* Clear the BSS */
+   memset(__bss_start, 0, __bss_end - __bss_start);
+
+#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
+   enable_layerscape_ns_access();
+#endif
+   board_init_r(NULL, 0);
+}
+#endif
diff --git a/arch/arm/include/asm/arch-fsl-lsch2/config.h 
b/arch/arm/include/asm/arch-fsl-lsch2/config.h
index 2125161..d0e4ba8 100644
--- a/arch/arm/include/asm/arch-fsl-lsch2/config.h
+++ b/arch/arm/include/asm/arch-fsl-lsch2/config.h
@@ -15,6 +15,8 @@
 #define CONFIG_SYS_INIT_SP_ADDR(CONFIG_SYS_FSL_OCRAM_BASE + 
0xfff0)
 
 #define CONFIG_SYS_IMMR0x0100
+#define CONFIG_SYS_DCSRBAR 0x2000
+#define CONFIG_SYS_DCSR_DCFG_ADDR  (CONFIG_SYS_DCSRBAR + 0x0022)
 
 #define CONFIG_SYS_FSL_DDR_ADDR(CONFIG_SYS_IMMR + 
0x0008)
 #define CONFIG_SYS_CCI400_ADDR (CONFIG_SYS_IMMR + 0x0018)
diff --git a/board/freescale/ls1043ardb/ls1043ardb_pbi.cfg 
b/board/freescale/ls1043ardb/ls1043ardb_pbi.cfg
new file mode 100644
index 000..f072274
--- /dev/null
+++ b/board/freescale/ls1043ardb/ls1043ardb_pbi.cfg
@@ -0,0 +1,14 @@
+#Configure Scratch register
+09570600 
+09570604 1000
+#Alt base register
+09570158 

[U-Boot] [PATCH 02/14] net/fm: bug fix when CONFIG_PHYLIB not defined

[Gong Qianyu]

From: Shaohui Xie 

phy_shutdown should be wrapped by CONFIG_PHYLIB.

Signed-off-by: Shaohui Xie 
Signed-off-by: Mingkai Hu 
Signed-off-by: Gong Qianyu 
---
 drivers/net/fm/eth.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/net/fm/eth.c b/drivers/net/fm/eth.c
index cd05dbc..67c96a2 100644
--- a/drivers/net/fm/eth.c
+++ b/drivers/net/fm/eth.c
@@ -453,8 +453,10 @@ static void fm_eth_halt(struct eth_device *dev)
/* disable bmi Rx port */
bmi_rx_port_disable(fm_eth->rx_port);
 
+#ifdef CONFIG_PHYLIB
if (fm_eth->phydev)
phy_shutdown(fm_eth->phydev);
+#endif
 }
 
 static int fm_eth_send(struct eth_device *dev, void *buf, int len)
-- 
2.1.0.27.g96db324

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Re: [U-Boot] [PATCH v4 08/11] dm: pci: Add an inline API to test if a device is on a PCI bus

[Bin Meng]

Hi Simon,

On Fri, Sep 11, 2015 at 4:41 AM, Simon Glass  wrote:
> Hi Bin,
>
> On 9 September 2015 at 21:58, Simon Glass  wrote:
>> On 3 September 2015 at 06:37, Bin Meng  wrote:
>>> Introduce device_is_on_pci_bus() which can be utilized by driver
>>> to test if a device is on a PCI bus.
>>>
>>> Signed-off-by: Bin Meng 
>>> Acked-by: Simon Glass 
>>>
>>> ---
>>>
>>> Changes in v4: None
>>> Changes in v3: None
>>> Changes in v2:
>>> - New patch to add an inline API to test if a device is on a PCI bus
>>>
>>>  drivers/pci/pci-uclass.c |  4 ++--
>>>  include/pci.h| 15 +++
>>>  2 files changed, 17 insertions(+), 2 deletions(-)
>>
>> Applied to u-boot-x86, thanks!
>
> Sorry, I did not end up bringing this in from testing.
>
> This causes build errors on quite a few boards - can you please take a look:
>
> w+../include/pci.h: In function 'device_is_on_pci_bus':
> w+../include/pci.h:1287:2: warning: implicit declaration of function
> 'device_get_uclass_id' [-Wimplicit-function-declaration]
>
> boards:
>
> alt,sniper,omap3_zoom1,p2571,omap3_beagle,mx6sxsabresd_spl,mx6ul_14x14_evk,devkit3250,apalis_t30,pcm051_rev3,pcm051_rev1,gose,venice2,ls2085ardb,mx6dlsabreauto,cm_t43,whistler,igep0030_nand,silk,am335x_boneblack,cairo,wandboard,birdland_bav335a,birdland_bav335b,mx6slevk_spl,am335x_evm_usbspl,igep0032,igep0030,devkit8000,chromebook_jerry,mx6qsabrelite,s5p_goni,snapper9g20,mx6sxsabresd,mx6dlsabresd,rpi_2,am335x_evm_nor,pengwyn,work_92105,tec-ng,trimslice,rpi,colibri_t30,igep0020,mx6cuboxi,cm_t335,ls2085aqds,beaver,am335x_baltos,mx6slevk_spinor,snapper9260,firefly-rk3288,jetson-tk1,mx6qsabresd,udoo,mx6sabresd_spl,igep0020_nand,am335x_evm_norboot,plutux,dalmore,marsboard,cgtqmx6qeval,am335x_evm_spiboot,lager,am335x_evm,cm_fx6,riotboard,omap3_logic,porter,pepper,omap3_overo,mx6slevk,am335x_boneblack_vboot,mx6qsabreauto,mx6qpsabreauto,am335x_gp_evm,p2371-,koelsch,am335x_igep0033,cardhu,e2220-1170
>

Sorry, please check the v5 series @ http://patchwork.ozlabs.org/patch/516672/

Regards,
Bin
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Re: [U-Boot] [PATCH] fdt: add new fdt address parsing functions

[Mugunthan V N]

On Wednesday 09 September 2015 11:38 PM, Simon Glass wrote:
> Hi,
> 
> On Monday, 7 September 2015, Mugunthan V N  wrote:
>>
>> On Friday 07 August 2015 03:01 AM, Stephen Warren wrote:
>>> From: Stephen Warren 
>>>
>>> fdtdec_get_addr_size() hard-codes the number of cells used to represent
>>> an address or size in DT. This is incorrect in many cases depending on
>>> the DT binding for a particular node or property (e.g. it is incorrect
>>> for the "reg" property). In most cases, DT parsing code must use the
>>> properties #address-cells and #size-cells to parse addres properties.
>>>
>>> This change splits up the implementation of fdtdec_get_addr_size() so
>>> that the core logic can be used for both hard-coded and non-hard-coded
>>> cases. Various wrapper functions are implemented that support cases
>>> where hard-coded cell counts should or should not be used, and where
>>> the client does and doesn't know the parent node ID that contains the
>>> properties #address-cells and #size-cells.
>>>
>>> dev_get_addr() is updated to use the new functions.
>>>
>>> Core functionality in fdtdec_get_addr_size_fixed() is widely tested via
>>> fdtdec_get_addr_size(). I tested fdtdec_get_addr_size_auto_noparent() and
>>> dev_get_addr() by manually modifying the Tegra I2C driver to invoke them.
>>>
>>> Much of the core implementation of fdtdec_get_addr_size_fixed(),
>>> fdtdec_get_addr_size_auto_parent(), and
>>> fdtdec_get_addr_size_auto_noparent() comes from Thierry Reding's
>>> previous commit "fdt: Fix fdtdec_get_addr_size() for 64-bit".
>>
>> Tested this patch for cpsw ethernet dt migration to getting cpsw address
>> space. Also dropped *#define DEBUG* in lib/fdtdev.c file.
>>
>> Tested-by: Mugunthan V N 
>>
> Thanks for testing this. I would like to apply this - are there any
> other comments?
> 

There is no other comments apart from removing #define DEBUG

Regards
Mugunthan V N

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[U-Boot] [PATCH 03/14] net: Move some header files to include/

[Gong Qianyu]

From: Shaohui Xie 

The fsl_dtsec.h & fsl_tgec.h & fsl_fman.h can be shared on both ARM
and PPC, move it out of ppc to include/, and change the path in
drivers accordingly.

Signed-off-by: Shaohui Xie 
Signed-off-by: Gong Qianyu 
---
 arch/powerpc/include/asm/fsl_dtsec.h| 231 --
 arch/powerpc/include/asm/fsl_fman.h | 463 
 arch/powerpc/include/asm/fsl_tgec.h | 202 
 arch/powerpc/include/asm/immap_85xx.h   |   2 +-
 board/freescale/b4860qds/eth_b4860qds.c |   2 +-
 board/freescale/corenet_ds/eth_hydra.c  |   2 +-
 board/freescale/corenet_ds/eth_p4080.c  |   2 +-
 board/freescale/corenet_ds/eth_superhydra.c |   2 +-
 board/freescale/p1023rdb/p1023rdb.c |   2 +-
 board/freescale/p2041rdb/eth.c  |   2 +-
 board/freescale/t102xqds/eth_t102xqds.c |   2 +-
 board/freescale/t102xrdb/eth_t102xrdb.c |   2 +-
 board/freescale/t1040qds/eth.c  |   2 +-
 board/freescale/t104xrdb/eth.c  |   2 +-
 board/freescale/t208xqds/eth_t208xqds.c |   2 +-
 board/freescale/t208xrdb/eth_t208xrdb.c |   2 +-
 board/freescale/t4qds/eth.c |   2 +-
 board/freescale/t4rdb/eth.c |   2 +-
 drivers/net/fm/dtsec.c  |   2 +-
 drivers/net/fm/eth.c|  18 +-
 drivers/net/fm/fm.h |   2 +-
 drivers/net/fm/tgec.c   |   2 +-
 drivers/net/fm/tgec_phy.c   |   2 +-
 include/fsl_dtsec.h | 231 ++
 include/fsl_fman.h  | 463 
 include/fsl_tgec.h  | 202 
 26 files changed, 924 insertions(+), 924 deletions(-)

diff --git a/arch/powerpc/include/asm/fsl_dtsec.h 
b/arch/powerpc/include/asm/fsl_dtsec.h
deleted file mode 100644
index 41b8398..000
--- a/arch/powerpc/include/asm/fsl_dtsec.h
+++ /dev/null
@@ -1,231 +0,0 @@
-/*
- * Copyright 2009-2011 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier:GPL-2.0+
- */
-
-#ifndef __DTSEC_H__
-#define __DTSEC_H__
-
-#include 
-
-struct dtsec {
-   u32 tsec_id;/* controller ID and version */
-   u32 tsec_id2;   /* controller ID and configuration */
-   u32 ievent; /* interrupt event */
-   u32 imask;  /* interrupt mask */
-   u32 res0;
-   u32 ecntrl; /* ethernet control and configuration */
-   u32 ptv;/* pause time value */
-   u32 tbipa;  /* TBI PHY address */
-   u32 res1[8];
-   u32 tctrl;  /* Transmit control register */
-   u32 res2[3];
-   u32 rctrl;  /* Receive control register */
-   u32 res3[11];
-   u32 igaddr[8];  /* Individual group address */
-   u32 gaddr[8];   /* group address */
-   u32 res4[16];
-   u32 maccfg1;/* MAC configuration register 1 */
-   u32 maccfg2;/* MAC configuration register 2 */
-   u32 ipgifg; /* inter-packet/inter-frame gap */
-   u32 hafdup; /* half-duplex control */
-   u32 maxfrm; /* Maximum frame size */
-   u32 res5[3];
-   u32 miimcfg;/* MII management configuration */
-   u32 miimcom;/* MII management command */
-   u32 miimadd;/* MII management address */
-   u32 miimcon;/* MII management control */
-   u32 miimstat;   /* MII management status */
-   u32 miimind;/* MII management indicator */
-   u32 res6;
-   u32 ifstat; /* Interface status */
-   u32 macstnaddr1;/* MAC station address 1 */
-   u32 macstnaddr2;/* MAC station address 2 */
-   u32 res7[46];
-   /* transmit and receive counter */
-   u32 tr64;   /* Tx and Rx 64 bytes frame */
-   u32 tr127;  /* Tx and Rx 65 to 127 bytes frame */
-   u32 tr255;  /* Tx and Rx 128 to 255 bytes frame */
-   u32 tr511;  /* Tx and Rx 256 to 511 bytes frame */
-   u32 tr1k;   /* Tx and Rx 512 to 1023 bytes frame */
-   u32 trmax;  /* Tx and Rx 1024 to 1518 bytes frame */
-   u32 trmgv;  /* Tx and Rx 1519 to 1522 good VLAN frame */
-   /* receive counters */
-   u32 rbyt;   /* Receive byte counter */
-   u32 rpkt;   /* Receive packet counter */
-   u32 rfcs;   /* Receive FCS error */
-   u32 rmca;   /* Receive multicast packet */
-   u32 rbca;   /* Receive broadcast packet */
-   u32 rxcf;   /* Receive control frame */
-   u32 rxpf;   /* Receive pause frame */
-   u32

Re: [U-Boot] [PATCH 2/4] mmc: dw_mmc: Zap endless timeout

[Marek Vasut]

On Friday, September 11, 2015 at 09:59:32 AM, Alexey Brodkin wrote:
> Hi Marek,

Hi!

> On Mon, 2015-07-27 at 22:39 +-0200, Marek Vasut wrote:
> +AD4- Endless timeouts are bad, since if we get stuck in one, we have no
> +AD4- way out. Zap this one by implementing proper timeout.
> +AD4-
> +AD4- Signed-off-by: Marek Vasut +ADw-marex+AEA-denx.de+AD4-
> +AD4- Cc: Dinh Nguyen +ADw-dinguyen+AEA-opensource.altera.com+AD4-
> +AD4- Cc: Pantelis Antoniou +ADw-panto+AEA-antoniou-consulting.com+AD4-
> +AD4- Cc: Tom Rini +ADw-trini+AEA-konsulko.com+AD4-
> +AD4- ---
> +AD4-  drivers/mmc/dw+AF8-mmc.c +AHw- 19
> +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+--- +AD4-  1 file changed, 17
> insertions(+-), 2 deletions(-)
> +AD4-
> +AD4- diff --git a/drivers/mmc/dw+AF8-mmc.c b/drivers/mmc/dw+AF8-mmc.c
> +AD4- index 3fffa71..0f61f16 100644
> +AD4- --- a/drivers/mmc/dw+AF8-mmc.c
> +AD4- +-+-+- b/drivers/mmc/dw+AF8-mmc.c
> +AD4- +AEAAQA- -211,14 +-211,29 +AEAAQA- static int
> dwmci+AF8-send+AF8-cmd(struct mmc +ACo-mmc, struct mmc+AF8-cmd +ACo-cmd,
> +AD4- +AH0-
> +AD4-
> +AD4- if (data) +AHs-
> +AD4- -   do +AHs-
> +AD4- +-  start +AD0- get+AF8-timer(0)+ADs-
> +AD4- +-  timeout +AD0- 1000+ADs-
> +AD4- +-  for (+ADsAOw-) +AHs-
> +AD4- mask +AD0- dwmci+AF8-readl(host, DWMCI+AF8-
RINTSTS)+ADs-
> +AD4- +-  /+ACo- Error during data transfer. +ACo-/
> +AD4- if (mask +ACY- (DWMCI+AF8-DATA+AF8-ERR +AHw-
> DWMCI+AF8-DATA+AF8-TOUT)) +AHs- +AD4- 
printf(+ACIAJQ-s: DATA
> ERROR+ACEAXA-n+ACI-, +AF8AXw-func+AF8AXw-)+ADs- +AD4- 
>   bounce+AF8-buffer+AF8-stop(+ACY-bbstate)+ADs-
> +AD4- return -1+ADs-
> +AD4- +AH0-
> +AD4- -   +AH0- while (+ACE-(mask +ACY- DWMCI+AF8-INTMSK+AF8-
DTO))+ADs-
> +AD4- +-
> +AD4- +-  /+ACo- Data arrived correctly. +ACo-/
> +AD4- +-  if (mask +ACY- DWMCI+AF8-INTMSK+AF8-DTO)
> +AD4- +-  break+ADs-
> +AD4- +-
> +AD4- +-  /+ACo- Check for timeout. +ACo-/
> +AD4- +-  if (get+AF8-timer(start) +AD4- timeout) +AHs-
> +AD4- +-  printf(+ACIAJQ-s: Timeout waiting for 
data+ACEAXA-n+ACI-,
> +AD4- +- +AF8AXw-func+AF8AXw-)+ADs-
> +AD4- +-  bounce+AF8-buffer+AF8-stop(+ACY-
bbstate)+ADs-
> +AD4- +-  return TIMEOUT+ADs-
> +AD4- +-  +AH0-
> +AD4- +-  +AH0-
> +AD4-
> +AD4- dwmci+AF8-writel(host, DWMCI+AF8-RINTSTS, mask)+ADs-
> +AD4-

btw Is your mailer totally broken by any chance ?

> It turned out that patch breaks functionality in some cases.
> For me on every attempt to download something significant (at least I see
> it on 5/7 Mb files) from SD I'm seeing timeout firing too early.
> 
> I added a bit of extra instrumentation to see where time is spent and why.

Check this patch:

[PATCH 1/2] mmc: dw_mmc: Increase timeout to 20 seconds

https://patchwork.ozlabs.org/patch/511899/

Does it fix things for you ?

[...]
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Re: [U-Boot] U-boot roadmap?

[Blibbet]

On 09/11/2015 04:12 PM, Lukasz Majewski wrote:
[..]
> Please look into ELCE2014 slides from u-boot mini summit at Dusseldorf
> (slides are available at denx.de webpage).
>
> There was a presentation from Simon Glass regarding device model road
> map.

http://www.denx.de/wiki/U-Boot/MiniSummitELCE2014
http://www.denx.de/wiki/U-Boot/DriverModel

[..]
> There will be u-boot Mini Summit held at ELCE 2015 in Dublin. I think
> that the road map issue is a good topic for our overall discussion
> panel.

http://www.denx.de/wiki/U-Boot/SummitELCE2015
http://events.linuxfoundation.org/events/linuxcon-europe/extend-the-experience/co-located-events

Thanks for the info!

Thanks,
Lee
RSS:
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limited to current scope:
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But only 3 posts on u-boot so far, bear with me, more once I can get
u-boot verified boot to work for me... :-)

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Re: [U-Boot] [PULL] u-boot-atmel/master -> u-boot/master

[Tom Rini]

On Fri, Sep 11, 2015 at 09:45:22AM +0200, Andreas Bießmann wrote:

> Hi Tom,
> 
> hopefully the last pull request for 2015.10 from atmel side. It finally
> contains a fix for two siemens boards (axm, taurus) for SPL size check, a DFU
> series for armv5 at91 devices acked by Łukasz Majewski and some trivial fixes.
> 
> The following changes since commit f0dc73c090317c7d0660443bc933d612a4c0c699:
> 
>   net: designware: Fix build warnings (2015-09-09 07:48:03 -0600)
> 
> are available in the git repository at:
> 
>   git://git.denx.de/u-boot-atmel.git master
> 
> for you to fetch changes up to e8b81eef4499c32b11d5f120171f39f67db0db59:
> 
>   at91, taurus, smartweb: add dfu support (2015-09-11 09:35:40 +0200)
> 

Applied to u-boot/master, thanks!

-- 
Tom


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Re: [U-Boot] arm: mvebu: u-boot does not start on db-88f6820-gp

[Stefan Roese]

Hi Stefan,

On 11.09.2015 15:50, Stefan Eichenberger wrote:

On 09/04/2015 06:44 PM, Stefan Roese wrote:


Unfortunately u-boot now hangs if I try to load an image from the
SD-Card:
e.g. if I run the following command u-boot hangs:
ext4load mmc 0:2 0x200 /boot/kernel.bin

I don't see why exactly it crashes, it seems for me that it's always at
a different position.

Here are two backtraces, always at a different positions:

Here u-boot stopped automatically:
Program received signal SIGTRAP, Trace/breakpoint trap.
0x7ff65d84 in ?? ()
(gdb) backtrace
#0  0x7ff65d84 in ?? ()
#1  0x803663d0 in ?? ()
#2  0x803663d0 in ?? ()
Backtrace stopped: previous frame identical to this frame (corrupt
stack?)

And here I've got perhaps some more information?
Program received signal SIGSTOP, Stopped (signal).
v7_inval_dcache_level_setway (log2_line_len=,
way_shift=, num_ways=,
 num_sets=, level=) at
arch/arm/cpu/armv7/cache_v7.c:62
62  for (set = num_sets - 1; set >= 0; set--) {
(gdb) backtrace
#0  v7_inval_dcache_level_setway (log2_line_len=,
way_shift=,
 num_ways=, num_sets=,
level=) at arch/arm/cpu/armv7/cache_v7.c:62
#1  v7_maint_dcache_level_setway (operation=, level=9) at
arch/arm/cpu/armv7/cache_v7.c:129
#2  v7_maint_dcache_all (operation=2146852864) at
arch/arm/cpu/armv7/cache_v7.c:147
#3  0xfbe2 in ?? ()
#4  0xfbe2 in ?? ()

Could it be that there is something wrong with cache/dram setup?


Maybe. Hard to tell. Why don't you use "dcache off" before you start
the command. If this works, then we still have a problem with cache
(L1 / L2)...


I now did some tests, it seems that the kernel only crashes if I access
the SD-Card, I'm able to load the kernel from an USB-Device. I tried to
disable the dcache but the problem still remains.

Another problem I have is that if I try to start a mainline kernel, it
will crash with the following trace, I think it doesn't find the
devicetree for some reasons:


Didn't you mention above, that booting Linux does work when booted via 
USB? Is this crash below a caused by accessing the SD-card?



## Booting kernel from Legacy Image at 0200 ...
Image Name:
Image Type:   ARM Linux Kernel Image (uncompressed)
Data Size:7258976 Bytes = 6.9 MiB
Load Address: 8000
Entry Point:  8000
Verifying Checksum ... OK
## Flattened Device Tree blob at 0300
Booting using the fdt blob at 0x300
Loading Kernel Image ... OK
Loading Device Tree to 7fb49000, end 7fb4ee70 ... OK

Starting kernel ...

[0.00] Booting Linux on physical CPU 0x0
[0.00] Linux version 4.2.0 (eichenberger@gruene) (gcc version
4.6.4 (Marvell GCC release 20150204-c4af733b 645
[0.00] CPU: ARMv7 Processor [414fc091] revision 1 (ARMv7),
cr=10c5387d
[0.00] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing
instruction cache
[0.00] Machine model: Marvell Armada 385 Development Board
[0.00] bootconsole [earlycon0] enabled
[0.00] Memory policy: Data cache writealloc
[0.00] Unable to handle kernel paging request at virtual address
3fb49000
[0.00] pgd = c0004000
[0.00] [3fb49000] *pgd=
[0.00] Internal error: Oops: 5 [#1] SMP ARM
[0.00] Modules linked in:
[0.00] CPU: 0 PID: 0 Comm: swapper Not tainted 4.2.0 #67
[0.00] Hardware name: Marvell Armada 380/385 (Device Tree)
[0.00] task: c06bd528 ti: c06b8000 task.ti: c06b8000
[0.00] PC is at fdt_check_header+0x0/0x78
[0.00] LR is at __unflatten_device_tree+0x1c/0x12c
[0.00] pc : []lr : [] psr: 21d3
[0.00] sp : c06b9f38  ip :   fp : ef7fce40
[0.00] r10: c071d2f0  r9 : c05c4d7c  r8 : 3fb49000
[0.00] r7 : c069454c  r6 : c06be514  r5 : c0712f68  r4 : c069454c
[0.00] r3 : c071d308  r2 : c069454c  r1 : c071d2f0  r0 : 3fb49000
[0.00] Flags: nzCv  IRQs off  FIQs off  Mode SVC_32  ISA ARM
Segment kernel
[0.00] Control: 10c5387d  Table: 404a  DAC: 0015
[0.00] Process swapper (pid: 0, stack limit = 0xc06b8220)
[0.00] Stack: (0xc06b9f38 to 0xc06ba000)
[0.00]
9f20:   
c070
[0.00] 9f40: 1000 0002f7ff 1000 0007 c069e348
c069454c c0712f68 c06be514
[0.00] 9f60: c06c2dc0 c06be514 000c c069514c c069e348
c0679448  10c5387d
[0.00] 9f80: 414fc091   c005aa68 c05c38cc
c06b9fb4  
[0.00] 9fa0: 0001  c06f4380  414fc091
  c067693c
[0.00] 9fc0:     
c06a9288  c06f4614
[0.00] 9fe0: c06ba4c0 c06a9284 c06be624 406a 
807c  
[0.00] [] (fdt_check_header) from []
(__unflatten_device_tree+0x1c/0x12c)
[0.00] [] (__unflatten_device_tree) from []
(unflatten_device_tree+0x1c/0x34)
[0.00] [] 

[U-Boot] Please pull u-boot-sunxi master

[Hans de Goede]

Hi Tom,

Here is another sunxi pull-req for v2015.10, highlights:

-Add support for 5 new boards
-Misc fixes

The following changes since commit efde6a579fe3c172d214fb3047b02c827779738a:

  Prepare v2015.10-rc3 (2015-09-07 08:56:35 -0400)

are available in the git repository at:

  http://git.denx.de/u-boot-sunxi.git master

for you to fetch changes up to cc19722f040fe326b1622dd1e2699179def7e45d:

  sunxi_nand_spl: Add config parameter for 4KiB page sized NAND devices 
(2015-09-10 20:20:45 +0200)


Hans de Goede (4):
  sun4i: Add defconfig and dts for the pov protab2-ips9 tablet
  sun4i: Add defconfig and dts for inet9f-rev03 based tablets
  sun4i: Add dts and defconfig for iNet-1 based tablets
  sun5i: Add q8_a13_tablet defconfig and dts

Jelle van der Waa (1):
  sun5i: Add A10s-Wobo-i5 defconfig and dts

Siarhei Siamashka (2):
  sunxi: Fix wrong serial console setup in Forfun Q88DB tablet
  sunxi: Ensure that 'mksunxiboot' tool produces deterministic output

Stefan Roese (1):
  sunxi_nand_spl: Add config parameter for 4KiB page sized NAND devices

 arch/arm/dts/Makefile   |   7 +-
 arch/arm/dts/sun4i-a10-inet1.dts| 226 
 arch/arm/dts/sun4i-a10-inet9f-rev03.dts | 219 +++
 arch/arm/dts/sun4i-a10-pov-protab2-ips9.dts | 209 +
 arch/arm/dts/sun5i-a10s-wobo-i5.dts | 224 +++
 arch/arm/dts/sun5i-a10s.dtsi|  11 ++
 arch/arm/dts/sun5i-a13-q8-tablet.dts|  60 
 arch/arm/dts/sun5i-q8-common.dtsi   | 170 +
 arch/arm/dts/sunxi-q8-common.dtsi   |  77 ++
 board/sunxi/MAINTAINERS |   6 +
 configs/A10s-Wobo-i5_defconfig  |  14 ++
 configs/forfun_q88db_defconfig  |   2 +-
 configs/inet1_defconfig |  22 +++
 configs/inet9f_rev03_defconfig  |  20 +++
 configs/pov_protab2_ips9_defconfig  |  21 +++
 configs/q8_a13_tablet_defconfig |  22 +++
 drivers/mtd/nand/sunxi_nand_spl.c   |   1 +
 tools/mksunxiboot.c |   2 +-
 18 files changed, 1310 insertions(+), 3 deletions(-)
 create mode 100644 arch/arm/dts/sun4i-a10-inet1.dts
 create mode 100644 arch/arm/dts/sun4i-a10-inet9f-rev03.dts
 create mode 100644 arch/arm/dts/sun4i-a10-pov-protab2-ips9.dts
 create mode 100644 arch/arm/dts/sun5i-a10s-wobo-i5.dts
 create mode 100644 arch/arm/dts/sun5i-a13-q8-tablet.dts
 create mode 100644 arch/arm/dts/sun5i-q8-common.dtsi
 create mode 100644 arch/arm/dts/sunxi-q8-common.dtsi
 create mode 100644 configs/A10s-Wobo-i5_defconfig
 create mode 100644 configs/inet1_defconfig
 create mode 100644 configs/inet9f_rev03_defconfig
 create mode 100644 configs/pov_protab2_ips9_defconfig
 create mode 100644 configs/q8_a13_tablet_defconfig

Regards,

Hans
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