[U-Boot] [PATCH v2 2/2] arm: stm32f4: fix a bug when a random sector gets erased

[Vadzim Dambrouski]

Old sector number is not being cleared from FLASH_CR register. For example
when first erased sector was 001 and then you want to erase sector 010,
sector 011 gets erased instead.
This patch clears old sector number from FLASH_CR register before a new
one is written.

Signed-off-by: Vadzim Dambrouski 
---

 arch/arm/cpu/armv7m/stm32f4/flash.c   | 3 +++
 arch/arm/include/asm/arch-stm32f4/stm32.h | 1 +
 2 files changed, 4 insertions(+)

diff --git a/arch/arm/cpu/armv7m/stm32f4/flash.c 
b/arch/arm/cpu/armv7m/stm32f4/flash.c
index ae63790..dd058bd 100644
--- a/arch/arm/cpu/armv7m/stm32f4/flash.c
+++ b/arch/arm/cpu/armv7m/stm32f4/flash.c
@@ -97,6 +97,9 @@ int flash_erase(flash_info_t *info, int first, int last)
while (readl(_FLASH->sr) & STM32_FLASH_SR_BSY)
;
 
+   /* clear old sector number before writing a new one */
+   clrbits_le32(_FLASH->cr, STM32_FLASH_CR_SNB_MASK);
+
if (bank == 0) {
setbits_le32(_FLASH->cr,
 (i << STM32_FLASH_CR_SNB_OFFSET));
diff --git a/arch/arm/include/asm/arch-stm32f4/stm32.h 
b/arch/arm/include/asm/arch-stm32f4/stm32.h
index 3ed3801..7ca6dc3 100644
--- a/arch/arm/include/asm/arch-stm32f4/stm32.h
+++ b/arch/arm/include/asm/arch-stm32f4/stm32.h
@@ -104,6 +104,7 @@ struct stm32_flash_regs {
 #define STM32_FLASH_CR_STRT(1 << 16)
 #define STM32_FLASH_CR_LOCK(1 << 31)
 #define STM32_FLASH_CR_SNB_OFFSET  3
+#define STM32_FLASH_CR_SNB_MASK(15 << 
STM32_FLASH_CR_SNB_OFFSET)
 
 enum clock {
CLOCK_CORE,
-- 
2.6.2

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[U-Boot] [PATCH v2 1/2] arm: stm32f4: fix a bug when only first sector gets erased

[Vadzim Dambrouski]

flash_lock call is inside a for loop, so after the first iteration flash
is locked and no more sectors can be erased.
Move flash_lock out of the loop.

Signed-off-by: Vadzim Dambrouski 
---

 arch/arm/cpu/armv7m/stm32f4/flash.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/cpu/armv7m/stm32f4/flash.c 
b/arch/arm/cpu/armv7m/stm32f4/flash.c
index e5c6111..ae63790 100644
--- a/arch/arm/cpu/armv7m/stm32f4/flash.c
+++ b/arch/arm/cpu/armv7m/stm32f4/flash.c
@@ -114,9 +114,9 @@ int flash_erase(flash_info_t *info, int first, int last)
;
 
clrbits_le32(_FLASH->cr, STM32_FLASH_CR_SER);
-   stm32f4_flash_lock(1);
}
 
+   stm32f4_flash_lock(1);
return 0;
 }
 
-- 
2.6.2

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Re: [U-Boot] [PATCH] mtd: pxa3xx_nand: Correct allocation and init bug

[Scott Wood]

On Fri, 2015-10-23 at 17:49 +, Kevin Smith wrote:
> Correct a null pointer dereference in board_nand_init().  Zeroed
> memory was allocated, then immediately dereferenced, which is a
> null dereference.  The dereference is completely removed, since
> this pointer is later initialized in alloc_nand_resources.
> 
> The allocation size is reduced from what was introduced from the
> Linux kernel, as U-boot uses the statically allocated nand_info
> instead of needing to dynamically allocate an mtd_info instance.
> 
> Also, some pointer math was corrected in the initialization of
> the nand_chip pointer.
> 
> Signed-off-by: Kevin Smith 
> Cc: Stefan Roese 
> Cc: Luka Perkov 
> Cc: Scott Wood 
> ---
>  drivers/mtd/nand/pxa3xx_nand.c | 17 +
>  1 file changed, 5 insertions(+), 12 deletions(-)
> 
> diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c
> index 1565a9a..e5ea5c2 100644
> --- a/drivers/mtd/nand/pxa3xx_nand.c
> +++ b/drivers/mtd/nand/pxa3xx_nand.c
> @@ -1486,8 +1486,8 @@ static int alloc_nand_resource(struct 
> pxa3xx_nand_info *info)
>   info->variant = pxa3xx_nand_get_variant();
>   for (cs = 0; cs < pdata->num_cs; cs++) {
>   mtd = _info[cs];
> - chip = (struct nand_chip *)info +
> - sizeof(struct pxa3xx_nand_host);
> + chip = (struct nand_chip *)
> + ((u8 *)[1] + sizeof(*host) * cs);

Yuck.  Could you please rework this driver to not play games with pointers 
and one giant allocation?  Why can't this function allocate each region it 
needs separately?

-Scott

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Re: [U-Boot] [PATCH] spi: Tegra: add device tree binding doc for SPI and QSPI

[Stephen Warren]

On 10/23/2015 11:52 AM, Tom Warren wrote:

Stephen,

Stephen Warren wrote at Friday, October 23, 2015 10:26 AM:

On 10/23/2015 11:11 AM, Tom Warren wrote:

This patch adds the device tree binding doc for the Tegra114 SPI
controller and the Tegra210 QSPI controller.


Initially, this should be sent as a Linux kernel patch, since the kernel 
currently
holds the definitive repository for DT bindings.

The binding should be based on the Tegra SPI binding present there, not on the
non-standard binding for Tegra114 SPI that's evidently in the U-Boot tree.

>

This is a copy of the 'nvidia,tegra114-spi.txt' binding in the kernel

> (Documentation/devicetree/bindings/spi/). I removed the dma and reset

fields, since they aren't required (or used) in U-Boot. I then added

> QSPI for T210, and named the file spi-tegra.txt. There wasn't a U-Boot
> SPI binding doc in U-Boot to start with.

Which kernel release did you use? The content in kernel git tag 
next-20151002, has been cleaned up quite a bit I suspect.


(Note that in that tag, the existing nvidia,tegra114-spi binding has one 
layout issue; I'd expect the clocks property to be documented 
immediately after the clock-names property. I'm not sure why it's not 
right now. This is just an FYI if you copy that file.)


Re "since they aren't required (or used) in U-Boot". A binding should be 
a description of the HW, and not influence by any particular OS or SW 
stack's design or implementation. If some feature exists in HW, it 
should be described in the binding, even if some particular SW stack 
isn't going to immediately make use of it. There's some leeway for 
optional features; if any arbitrary SW stack could make useful use of 
the HW without a particular feature, a simple binding could be submitted 
first without describing that feature, then enhanced later to add it. 
This avoids bike-shedding re: the design of some esoteric feature from 
blocking a simple binding being accepted. However, basic features that 
are simple, common, well-understood, and widely used (e.g. resets, DMA), 
should invariably be described right from the start.



That would imply sending the patch to the people/lists listed in the following
Linux kernel MAINTAINERS entry for DT bindings, plus at least the Tegra
mailing list and maintainers too:

OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS
M:  Rob Herring 
M:  Pawel Moll 
M:  Mark Rutland 
M:  Ian Campbell 
M:  Kumar Gala 
L:  devicet...@vger.kernel.org

>

Since this is basically a copy of a kernel binding doc, I didn't know that

> was necessary. Is that policy for U-Boot binding docs?

All bindings need to be reviewed by the DT binding review process. That 
currently involves submitting a Linux kernel patch to add the 
documentation of the binding to the kernel source tree. There have been 
discussions about moving the DT binding docs into a separate standalone 
repo with a seprate review process, but that hasn't happened yet. This 
is all policy for DT, so nothing to do with U-Boot or Linux or other SW.



Jagan - you have a few of these in the SPI bindings - did you have

> them reviewed by kernel/DT folk first?

I don't know about those specifically, but historical usage of DT in 
U-Boot has been extremely lax about standards, and has tended to diverge 
from the official set of bindings, currently stored in the kernel git tree.



Regardless, I'll resend with those people/lists in CC. Which Tegra 
ML/maintainers

> did you also want in there?

Generally, Linux kernel patches should be sent to whatever 
./scripts/get_maintainers.pl says, although in some cases you'd want to 
strip out some irrelevant people/lists so as not to make your CC too 
large. Here's the entry for Tegra:


TEGRA ARCHITECTURE SUPPORT
M:  Stephen Warren 
M:  Thierry Reding 
M:  Alexandre Courbot 
L:  linux-te...@vger.kernel.org

You should probably add in the ARM linux kernel mailing list but not 
bother with the main Linux kernel mailing list or general documentation 
people (the DT-binding-specific reviewers should be enough for this).



diff --git a/doc/device-tree-bindings/spi/spi-tegra.txt
b/doc/device-tree-bindings/spi/spi-tegra.txt
new file mode 100644
index 000..e215efe
--- /dev/null
+++ b/doc/device-tree-bindings/spi/spi-tegra.txt
@@ -0,0 +1,47 @@
+NVIDIA Tegra114 SPI controller.


Isn't this intended to be a binding for the QSPI controller?

>

Since there was no SPI binding, I included the Tegra114 SPI binding here.

> Note that other QSPI bindings exist here, for instance

spi-cadence.txt.If you'd like two separate binding docs, I can do that,

> but this seemed more efficient.

Any DT binding docs that get imported into the U-Boot source tree should 
be exactly identical to the official docs that are currently 

Re: [U-Boot] [PATCH v4 18/24] spi: cadence_qspi_apb: Use GENMASK

[Fabio Estevam]

Jagan,

On Fri, Oct 23, 2015 at 3:17 PM, Jagan Teki  wrote:
> On 23 October 2015 at 02:55, Tom Rini  wrote:
>> On Thu, Oct 22, 2015 at 07:10:17PM -0200, Fabio Estevam wrote:
>>> On Thu, Oct 22, 2015 at 6:50 PM, Jagan Teki  wrote:
>>>
>>> > reg &= ~(CQSPI_REG_CONFIG_CHIPSELECT_MASK
>>> > @@ -719,7 +719,7 @@ int cadence_qspi_apb_indirect_read_setup(struct 
>>> > cadence_spi_platdata *plat,
>>> >  #if defined(CONFIG_SPL_SPI_XIP) && defined(CONFIG_SPL_BUILD)
>>> > writel(0x0, plat->regbase + CQSPI_REG_MODE_BIT);
>>> >  #else
>>> > -   writel(0xFF, plat->regbase + CQSPI_REG_MODE_BIT);
>>> > +   writel(GENMASK(7, 0), plat->regbase + CQSPI_REG_MODE_BIT);
>>>
>>> Is the 0xFF really a mask here? It seems it is just writing 0xFF to
>>> the register directly without any masking operation.

Your quoting style is a bit odd.

You are replying to my message in Tom's reply. This is confusing.

> As register got initialized to all 1's like masking all to set may be
> we can add a macro like MODE_BIT_MASK and then will assign GENMASK to
> that.

Sorry, bu this sentence is hard to parse.

Anyway, this change is only making the code harder to read.
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Re: [U-Boot] Doubt in USB driver for Vybrid vf610

[Marek Vasut]

On Friday, October 23, 2015 at 07:18:44 AM, maitysancha...@gmail.com wrote:
> Hello Marek,

Hi,

> Any inputs on the below?

I don't have a Vybrid device, CCing Fabio.

> Thanks & Regards,
> Sanchayan Maity.
> 
> On 15-10-19 10:58:47, maitysancha...@gmail.com wrote:
> > Hello Marek,
> > 
> > On 15-10-17 21:59:07, maitysancha...@gmail.com wrote:
> > > Hello,
> > > 
> > > On 15-10-16 16:20:07, Santhosh Kumar Janardhanam -ERS, HCL Tech wrote:
> > > > Hi All,
> > > > I am working on USB part for vybrid vf-610 processor, We have two
> > > > ports in the board
> > > > 
> > > > when I type usb start in uboot command prompt, It returns as ENODEV
> > > > for USB0 and when analyzed, It is returning from the below code in
> > > > ehci-hcd_init function(in ehci-vf.c)
> > > > 
> > > > if (init == USB_INIT_HOST && index == 0)
> > > > 
> > > > return -ENODEV;
> > 
> > Along with the above
> > if (init == USB_INIT_DEVICE && index == 1)
> > 
> > return -ENODEV;
> > 
> > In the ehci-vf USB driver for Vybrid, currently we have two "if" cases as
> > above which basically serve the purpose of preventing one of the USB
> > ports from being configured as host, which we did like to keep as
> > client. So for us, USB0 is client and USB1 is host and the above was put
> > in with that intention to prevent USB0 from being configured as host,
> > when usb start is called. However this is bad for other users out there,
> > sorry about that.
> > 
> > I checked and it seems even without the above, if both ports are
> > configured as host with usb start and later dfu is called to used the
> > intended as client for upgrade purposes, things still seem to work. Not
> > sure if there are cases where this can break which I am missing.
> > 
> > Not being that well versed with USB I wanted to ask is this ok or this is
> > completely wrong? If it is ok, I guess we can go ahead and nuke the
> > above checks? OR will be it be a better approach to introduce something
> > like board_ehci_hch_init_with_type(int index, enum usb_init_type type)
> > which will be a weak function and then have the board specific code hook
> > call it?
> > 
> > - Sanchayan.
> > 
> > > >  If these two  lines are commented, the usb start is working and
> > > >  device is found on USB0.
> > > > 
> > > > Why is this check kept in the code?
> > > 
> > > I am the author of the ehci-vf USB driver which is based on iMX6
> > > implementation. The implementation was done as per our requirements
> > > where we have one port as host and another as client. In hindsight my
> > > implementation is severely restricting and at that time I missed
> > > thinking of it and did not had other boards to test.
> > > 
> > > I will fix this up and send a patch. However I need to look a bit. The
> > > ideal way would be to fix it up in board_ehci_hcd_init call however
> > > that does not provide the init parameter to distinguish between
> > > USB_INIT_DEVICE and USB_INIT_HOST.
> > > 
> > > May I ask are you using some module or you have your custom setup
> > > around the Vybrid? Sorry for the trouble. Thanks for reporting.
> > > 
> > > - Sanchayan.
> > > 
> > > > Regards,
> > > > Santhosh
> > > > 
> > > > ::DISCLAIMER::
> > > > -
> > > > -
> > > > --
> > > > 
> > > > The contents of this e-mail and any attachment(s) are confidential
> > > > and intended for the named recipient(s) only. E-mail transmission is
> > > > not guaranteed to be secure or error-free as information could be
> > > > intercepted, corrupted, lost, destroyed, arrive late or incomplete,
> > > > or may contain viruses in transmission. The e mail and its contents
> > > > (with or without referred errors) shall therefore not attach any
> > > > liability on the originator or HCL or its affiliates. Views or
> > > > opinions, if any, presented in this email are solely those of the
> > > > author and may not necessarily reflect the views or opinions of HCL
> > > > or its affiliates. Any form of reproduction, dissemination, copying,
> > > > disclosure, modification, distribution and / or publication of this
> > > > message without the prior written consent of authorized
> > > > representative of HCL is strictly prohibited. If you have received
> > > > this email in error please delete it and notify the sender
> > > > immediately. Before opening any email and/or attachments, please
> > > > check them for viruses and other defects.
> > > > 
> > > > -
> > > > -
> > > > --
> > > > 
> > > > ___
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Re: [U-Boot] [PATCH] arm: socfpga: Add CONFIG_BUILD_TARGET to socfpga_common.h

[Marek Vasut]

On Friday, October 23, 2015 at 09:26:52 AM, Stefan Roese wrote:
> By defining this macro, the combined image of SPL and main U-Boot will
> get built automatically.
> 
> Signed-off-by: Stefan Roese 
> Cc: Marek Vasut 
> Cc: Pavel Machek 
> Cc: Dinh Nguyen 

This is a good one, thanks!

Acked-by: Marek Vasut 

Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH] arm: socfpga: Add SoCFPGA SR1500 board

[Marek Vasut]

On Friday, October 23, 2015 at 09:26:53 AM, Stefan Roese wrote:
> The SR1500

Does SR mean Stefan Roese ? :-)

Anyway, shouldn't you place this device under board/vendorname/boardname
instead of plain board/boardname/ ?

And one more thing, would it be possible for you to do a short README on
adding a new board? That'd be real cool. Obviously, it's not something I
demand or that'd block this patch series, it'd be nice though.

> board is a CycloneV based board, similar to the EBV
> SoCrates, equipped with the following devices:
> 
> - SPI NOR
> - eMMC
> - Ethernet
> 
> Signed-off-by: Stefan Roese 
> Cc: Marek Vasut 
> Cc: Pavel Machek 
> Cc: Dinh Nguyen 

[...]

> +int board_early_init_f(void)
> +{
> + int ret;
> +
> + /* Reset the Marvell PHY 88E1510 */
> + ret = gpio_request(63, "PHY reset");
> + if (ret)
> + return ret;
> +
> + gpio_direction_output(63, 0);
> + mdelay(20);
> + gpio_set_value(63, 1);

Does the PHY come out of reset immediatelly after you deassert the nRESET
GPIO or not ? You might want to add a small delay here to bullet-proof the
code a bit more.

> + return 0;
> +}
> +
> +#define CONFIG_SYS_IDT_CLK_ADDR  0x6a
> +
> +static int do_clksave(cmd_tbl_t *cmdtp, int flag, int argc, char *const
> argv[]) +{
> + u8 buf[1];
> +
> + buf[0] = 0x01;
> + i2c_write(CONFIG_SYS_IDT_CLK_ADDR, 0, 0, buf, 1);
> +
> + return 0;
> +}
> +
> +U_BOOT_CMD(clksave, 1, 0, do_clksave,
> +"IDT 5V49EE702 Progsave command", "");

I am not convinced I should let this slide. Wouldn't it be better to just
have an environment script which sends 0x1 to this IDT Versaclock using the
i2c command ?

> +#define NET_DEV_NAME "ethernet@ff702000"
> +#define MII_MARVELL_PHY_PAGE 22
> +#define PHY_DIAG_START   (1 << 15)
> +#define PHY_DIAG_BUSY(1 << 11)
> +
> +static char str[16];

Please move this static var into do_phytest() and pass it into pair_state()
as an argument.

> +static char *pair_state(int val)
> +{
> + switch (val) {
> + case 0x00:
> + strcpy(str, "Invalid");
> + break;
> + case 0x01:
> + strcpy(str, "Pair Ok");
> + break;
> + case 0x02:
> + strcpy(str, "Pair Open");
> + break;
> + case 0x03:
> + strcpy(str, "Same Pair Short");
> + break;
> + case 0x04:
> + strcpy(str, "Cross Pair Short");

Do I count correctly that you do strcpy() here on a string which is 16 byte
long + one trailing '\0' (total 17 bytes) and you strcpy() it into 16 byte
long buffer ? Well that's not good, this will overwrite one byte past the
$str buffer with '\0' :-)

> + break;
> + case 0x09:
> + strcpy(str, "Pair Busy");
> + break;
> + default:
> + strcpy(str, "Reserved");
> + break;
> + };
> +
> + return str;
> +}
> +
> +static int do_phytest(cmd_tbl_t *cmdtp, int flag, int argc, char *const
> argv[]) +{
> + char devname[] = NET_DEV_NAME;

const char * here ?

> + int addr = 0;

Looks like unsigned value to me, please make it so.

> + u16 data;
> + u16 status;
> + u16 oldpage;
> + int i;
> +
> + /* Save current page register */
> + miiphy_read(devname, addr, MII_MARVELL_PHY_PAGE, );
> +
> + /*
> +  * Run cable disgnostics
> +  */
> + printf("Running cable diagnostic test...");
> + miiphy_write(devname, addr, MII_MARVELL_PHY_PAGE, 7);
> + miiphy_write(devname, addr, 21, PHY_DIAG_START);
> + miiphy_read(devname, addr, 21, );
> + while ((data & PHY_DIAG_BUSY) == PHY_DIAG_BUSY) {
> + miiphy_read(devname, addr, 21, );
> + mdelay(1);

Unbounded loop, do I need to say more ? ;-)

> + }
> + printf("done!\n");

[...]

> +/* Booting Linux */
> +#define CONFIG_BOOTDELAY 3
> +#define CONFIG_BOOTFILE  "uImage"
> +#define CONFIG_BOOTARGS  "console=ttyS0" 
__stringify(CONFIG_BAUDRATE)
> +#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET

Do you really need socfpga_vt on your quite certainly physical hardware ?

> +#define CONFIG_BOOTCOMMAND   "run ramboot"
> +#else
> +#define CONFIG_BOOTCOMMAND   "run mmcload; run mmcboot"
> +#endif
> +#define CONFIG_LOADADDR  0x8000
> +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
> +#define CONFIG_SYS_CONSOLE_INFO_QUIET/* don't print console @ 
> startup 
*/
> +
> +/* Ethernet on SoC (EMAC) */
> +#if defined(CONFIG_CMD_NET)
> +#define CONFIG_EMAC_BASE SOCFPGA_EMAC1_ADDRESS

This EMAC address is certainly not needed now, it should come from OF.

> +#define CONFIG_PHY_INTERFACE_MODEPHY_INTERFACE_MODE_RGMII
> +/* The PHY is autodetected, so no MII PHY address is needed here */
> +#define CONFIG_PHY_MARVELL
> +#define PHY_ANEG_TIMEOUT 8000
> +#endif
> +
> 

Re: [U-Boot] [PATCH v4 18/24] spi: cadence_qspi_apb: Use GENMASK

[Marek Vasut]

On Friday, October 23, 2015 at 07:17:28 PM, Jagan Teki wrote:
> On 23 October 2015 at 02:55, Tom Rini  wrote:
> > On Thu, Oct 22, 2015 at 07:10:17PM -0200, Fabio Estevam wrote:
> >> On Thu, Oct 22, 2015 at 6:50 PM, Jagan Teki  wrote:
> >> > reg &= ~(CQSPI_REG_CONFIG_CHIPSELECT_MASK
> >> > 
> >> > @@ -719,7 +719,7 @@ int cadence_qspi_apb_indirect_read_setup(struct
> >> > cadence_spi_platdata *plat,
> >> > 
> >> >  #if defined(CONFIG_SPL_SPI_XIP) && defined(CONFIG_SPL_BUILD)
> >> >  
> >> > writel(0x0, plat->regbase + CQSPI_REG_MODE_BIT);
> >> >  
> >> >  #else
> >> > 
> >> > -   writel(0xFF, plat->regbase + CQSPI_REG_MODE_BIT);
> >> > +   writel(GENMASK(7, 0), plat->regbase +
> >> > CQSPI_REG_MODE_BIT);
> >> 
> >> Is the 0xFF really a mask here? It seems it is just writing 0xFF to
> >> the register directly without any masking operation.
> 
> As register got initialized to all 1's like masking all to set may be
> we can add a macro like MODE_BIT_MASK and then will assign GENMASK to
> that.

Please keep the 0xff value, I agree with Fabio.

Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH v4 18/24] spi: cadence_qspi_apb: Use GENMASK

[Marek Vasut]

On Thursday, October 22, 2015 at 10:50:18 PM, Jagan Teki wrote:
> Replace numeric mask hexcodes with GENMASK macro in cadence_qspi_apb
> 
> Cc: Stefan Roese 
> Cc: Vikas Manocha 
> Cc: Marek Vasut 
> Signed-off-by: Jagan Teki 
> ---
>  drivers/spi/cadence_qspi_apb.c | 48
> +- 1 file changed, 24
> insertions(+), 24 deletions(-)
> 
> diff --git a/drivers/spi/cadence_qspi_apb.c
> b/drivers/spi/cadence_qspi_apb.c index 7786dd6..31e14ee 100644
> --- a/drivers/spi/cadence_qspi_apb.c
> +++ b/drivers/spi/cadence_qspi_apb.c
> @@ -44,7 +44,7 @@
>  #define CQSPI_INST_TYPE_QUAD (2)
> 
>  #define CQSPI_STIG_DATA_LEN_MAX  (8)
> -#define CQSPI_INDIRECTTRIGGER_ADDR_MASK  (0xF)
> +#define CQSPI_INDIRECTTRIGGER_ADDR_MASK  GENMASK(19, 0)
> 
>  #define CQSPI_DUMMY_CLKS_PER_BYTE(8)
>  #define CQSPI_DUMMY_BYTES_MAX(4)
> @@ -65,8 +65,8 @@
>  #define  CQSPI_REG_CONFIG_CHIPSELECT_LSB 10
>  #define  CQSPI_REG_CONFIG_BAUD_LSB   19
>  #define  CQSPI_REG_CONFIG_IDLE_LSB   31
> -#define  CQSPI_REG_CONFIG_CHIPSELECT_MASK0xF
> -#define  CQSPI_REG_CONFIG_BAUD_MASK  0xF
> +#define  CQSPI_REG_CONFIG_CHIPSELECT_MASKGENMASK(3, 0)
> +#define  CQSPI_REG_CONFIG_BAUD_MASK  GENMASK(3, 0)
> 
>  #define  CQSPI_REG_RD_INSTR  0x04
>  #define  CQSPI_REG_RD_INSTR_OPCODE_LSB   0
> @@ -75,10 +75,10 @@
>  #define  CQSPI_REG_RD_INSTR_TYPE_DATA_LSB16
>  #define  CQSPI_REG_RD_INSTR_MODE_EN_LSB  20
>  #define  CQSPI_REG_RD_INSTR_DUMMY_LSB24
> -#define  CQSPI_REG_RD_INSTR_TYPE_INSTR_MASK  0x3
> -#define  CQSPI_REG_RD_INSTR_TYPE_ADDR_MASK   0x3
> -#define  CQSPI_REG_RD_INSTR_TYPE_DATA_MASK   0x3
> -#define  CQSPI_REG_RD_INSTR_DUMMY_MASK   0x1F
> +#define  CQSPI_REG_RD_INSTR_TYPE_INSTR_MASK  GENMASK(1, 0)
> +#define  CQSPI_REG_RD_INSTR_TYPE_ADDR_MASK   GENMASK(1, 0)
> +#define  CQSPI_REG_RD_INSTR_TYPE_DATA_MASK   GENMASK(1, 0)
> +#define  CQSPI_REG_RD_INSTR_DUMMY_MASK   GENMASK(4, 0)
> 
>  #define  CQSPI_REG_WR_INSTR  0x08
>  #define  CQSPI_REG_WR_INSTR_OPCODE_LSB   0
> @@ -88,23 +88,23 @@
>  #define  CQSPI_REG_DELAY_TCHSH_LSB   8
>  #define  CQSPI_REG_DELAY_TSD2D_LSB   16
>  #define  CQSPI_REG_DELAY_TSHSL_LSB   24
> -#define  CQSPI_REG_DELAY_TSLCH_MASK  0xFF
> -#define  CQSPI_REG_DELAY_TCHSH_MASK  0xFF
> -#define  CQSPI_REG_DELAY_TSD2D_MASK  0xFF
> -#define  CQSPI_REG_DELAY_TSHSL_MASK  0xFF
> +#define  CQSPI_REG_DELAY_TSLCH_MASK  GENMASK(7, 0)
> +#define  CQSPI_REG_DELAY_TCHSH_MASK  GENMASK(7, 0)
> +#define  CQSPI_REG_DELAY_TSD2D_MASK  GENMASK(7, 0)
> +#define  CQSPI_REG_DELAY_TSHSL_MASK  GENMASK(7, 0)
> 
>  #define  CQSPI_READLCAPTURE  0x10
>  #define  CQSPI_READLCAPTURE_BYPASS_LSB   0
>  #define  CQSPI_READLCAPTURE_DELAY_LSB1
> -#define  CQSPI_READLCAPTURE_DELAY_MASK   0xF
> +#define  CQSPI_READLCAPTURE_DELAY_MASK   GENMASK(3, 0)
> 
>  #define  CQSPI_REG_SIZE  0x14
>  #define  CQSPI_REG_SIZE_ADDRESS_LSB  0
>  #define  CQSPI_REG_SIZE_PAGE_LSB 4
>  #define  CQSPI_REG_SIZE_BLOCK_LSB16
> -#define  CQSPI_REG_SIZE_ADDRESS_MASK 0xF
> -#define  CQSPI_REG_SIZE_PAGE_MASK0xFFF
> -#define  CQSPI_REG_SIZE_BLOCK_MASK   0x3F
> +#define  CQSPI_REG_SIZE_ADDRESS_MASK GENMASK(3, 0)
> +#define  CQSPI_REG_SIZE_PAGE_MASKGENMASK(11, 0)
> +#define  CQSPI_REG_SIZE_BLOCK_MASK   GENMASK(5, 0)
> 
>  #define  CQSPI_REG_SRAMPARTITION 0x18
>  #define  CQSPI_REG_INDIRECTTRIGGER   0x1C
> @@ -115,8 +115,8 @@
>  #define  CQSPI_REG_SDRAMLEVEL0x2C
>  #define  CQSPI_REG_SDRAMLEVEL_RD_LSB 0
>  #define  CQSPI_REG_SDRAMLEVEL_WR_LSB 16
> -#define  CQSPI_REG_SDRAMLEVEL_RD_MASK0x
> -#define  CQSPI_REG_SDRAMLEVEL_WR_MASK0x
> +#define  CQSPI_REG_SDRAMLEVEL_RD_MASKGENMASK(15, 0)
> +#define  CQSPI_REG_SDRAMLEVEL_WR_MASKGENMASK(15, 0)
> 
>  #define  CQSPI_REG_IRQSTATUS 0x40
>  #define  CQSPI_REG_IRQMASK   0x44
> @@ -142,11 +142,11 @@
>  #define  CQSPI_REG_CMDCTRL_RD_BYTES_LSB  20
>  #define  CQSPI_REG_CMDCTRL_RD_EN_LSB 23
>  #define  

Re: [U-Boot] [Patch V7 04/18] net/fm/eth: Use mb() to be compatible for both ARM and PowerPC

[Hou Zhiqiang]

> -Original Message-
> From: Wood Scott-B07421
> Sent: 2015年10月23日 7:11
> To: Gong Qianyu-B52263
> Cc: u-boot@lists.denx.de; Hu Mingkai-B21284; Sun York-R58495; Hou
> Zhiqiang-B48286; Xie Shaohui-B21989; Song Wenbin-B53747; Wood Scott-
> B07421; Kushwaha Prabhakar-B32579; Wang Huan-B18965
> Subject: Re: [Patch V7 04/18] net/fm/eth: Use mb() to be compatible for
> both ARM and PowerPC
> 
> On Thu, 2015-10-22 at 18:46 +0800, Gong Qianyu wrote:
> > From: Shaohui Xie 
> >
> > Use mb() instead of sync() to be compatible for both ARM and PowerPC.
> >
> > Signed-off-by: Shaohui Xie 
> > Signed-off-by: Mingkai Hu 
> > Signed-off-by: Gong Qianyu 
> > ---
> > V7:
> >  - No change.
> > V6:
> >  - No change.
> > V5:
> >  - No change.
> > V4:
> >  - No change.
> > V3:
> >  - New patch. Separated from patch 'net: Move some header files to
> include/'
> >
> >  drivers/net/fm/eth.c | 14 +++---
> >  1 file changed, 7 insertions(+), 7 deletions(-)
> >
> > diff --git a/drivers/net/fm/eth.c b/drivers/net/fm/eth.c index
> > 368d554..ad02c66 100644
> > --- a/drivers/net/fm/eth.c
> > +++ b/drivers/net/fm/eth.c
> > @@ -371,7 +371,7 @@ static void
> > fmc_tx_port_graceful_stop_enable(struct
> > fm_eth *fm_eth)
> >   pram = fm_eth->tx_pram;
> >   /* graceful stop transmission of frames */
> >   setbits_be32(>mode, PRAM_MODE_GRACEFUL_STOP);
> > - sync();
> > + mb();
> >  }
> >
> >  static void fmc_tx_port_graceful_stop_disable(struct fm_eth *fm_eth)
> > @@ -381,7 +381,7 @@ static void
> > fmc_tx_port_graceful_stop_disable(struct
> > fm_eth *fm_eth)
> >   pram = fm_eth->tx_pram;
> >   /* re-enable transmission of frames */
> >   clrbits_be32(>mode, PRAM_MODE_GRACEFUL_STOP);
> > - sync();
> > + mb();
> >  }
> 
> Why is it needed at all?  The I/O accessors should include the necessary
> barriers.

The I/O accessors of powerpc does include the barrier, but it absents from 
ARMs'.

Thanks,
Zhiqiang

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[U-Boot] [PATCH 1/4] mmc: atmel: Silence debug output

[Marek Vasut]

This driver generates clearly debugging prints when changing clock
speed, so silence those. Furthermore, the driver generates further
prints in case a command fails to complete. The later case woud be
useful, but for eMMC, command 8 can fail and it's not an error but
a part of the specification. Thus, make this debug() as well.

Signed-off-by: Marek Vasut 
---
 drivers/mmc/gen_atmel_mci.c | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/mmc/gen_atmel_mci.c b/drivers/mmc/gen_atmel_mci.c
index 45bcffb..2815e57 100644
--- a/drivers/mmc/gen_atmel_mci.c
+++ b/drivers/mmc/gen_atmel_mci.c
@@ -48,8 +48,8 @@ static unsigned int atmel_mci_get_version(struct atmel_mci 
*mci)
  */
 static void dump_cmd(u32 cmdr, u32 arg, u32 status, const char* msg)
 {
-   printf("gen_atmel_mci: CMDR %08x (%2u) ARGR %08x (SR: %08x) %s\n",
-   cmdr, cmdr&0x3F, arg, status, msg);
+   debug("gen_atmel_mci: CMDR %08x (%2u) ARGR %08x (SR: %08x) %s\n",
+ cmdr, cmdr & 0x3F, arg, status, msg);
 }
 
 /* Setup for MCI Clock and Block Size */
@@ -73,7 +73,7 @@ static void mci_set_mode(struct mmc *mmc, u32 hz, u32 blklen)
clkodd = clkdiv & 1;
clkdiv >>= 1;
 
-   printf("mci: setting clock %u Hz, block size %u\n",
+   debug("mci: setting clock %u Hz, block size %u\n",
   bus_hz / (clkdiv * 2 + clkodd + 2), blklen);
} else {
/* find clkdiv yielding a rate <= than requested */
@@ -81,7 +81,7 @@ static void mci_set_mode(struct mmc *mmc, u32 hz, u32 blklen)
if ((bus_hz / (clkdiv + 1) / 2) <= hz)
break;
}
-   printf("mci: setting clock %u Hz, block size %u\n",
+   debug("mci: setting clock %u Hz, block size %u\n",
   (bus_hz / (clkdiv + 1)) / 2, blklen);
 
}
-- 
2.1.4

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[U-Boot] [PATCH 3/4] mmc: atmel: Implement proper private data

[Marek Vasut]

Instead of passing just the register area as a private data, introduce
a proper struct atmel_mci_priv structure instead. This will become useful
in the subsequent patch, where we eliminate the global variable from this
driver.

Signed-off-by: Marek Vasut 
---
 drivers/mmc/gen_atmel_mci.c | 34 ++
 1 file changed, 22 insertions(+), 12 deletions(-)

diff --git a/drivers/mmc/gen_atmel_mci.c b/drivers/mmc/gen_atmel_mci.c
index 8b05fcd..abc77cc 100644
--- a/drivers/mmc/gen_atmel_mci.c
+++ b/drivers/mmc/gen_atmel_mci.c
@@ -32,6 +32,11 @@
 # define MCI_BUS 0
 #endif
 
+struct atmel_mci_priv {
+   struct mmc_config   cfg;
+   struct atmel_mci*mci;
+};
+
 static int initialized = 0;
 
 /* Read Atmel MCI IP version */
@@ -55,7 +60,8 @@ static void dump_cmd(u32 cmdr, u32 arg, u32 status, const 
char* msg)
 /* Setup for MCI Clock and Block Size */
 static void mci_set_mode(struct mmc *mmc, u32 hz, u32 blklen)
 {
-   atmel_mci_t *mci = mmc->priv;
+   struct atmel_mci_priv *priv = mmc->priv;
+   atmel_mci_t *mci = priv->mci;
u32 bus_hz = get_mci_clk_rate();
u32 clkdiv = 255;
unsigned int version = atmel_mci_get_version(mci);
@@ -198,7 +204,8 @@ io_fail:
 static int
 mci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
 {
-   atmel_mci_t *mci = mmc->priv;
+   struct atmel_mci_priv *priv = mmc->priv;
+   atmel_mci_t *mci = priv->mci;
u32 cmdr;
u32 error_flags = 0;
u32 status;
@@ -323,7 +330,8 @@ mci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct 
mmc_data *data)
 /* Entered into mmc structure during driver init */
 static void mci_set_ios(struct mmc *mmc)
 {
-   atmel_mci_t *mci = mmc->priv;
+   struct atmel_mci_priv *priv = mmc->priv;
+   atmel_mci_t *mci = priv->mci;
int bus_width = mmc->bus_width;
unsigned int version = atmel_mci_get_version(mci);
int busw;
@@ -359,7 +367,8 @@ static void mci_set_ios(struct mmc *mmc)
 /* Entered into mmc structure during driver init */
 static int mci_init(struct mmc *mmc)
 {
-   atmel_mci_t *mci = mmc->priv;
+   struct atmel_mci_priv *priv = mmc->priv;
+   atmel_mci_t *mci = priv->mci;
 
/* Initialize controller */
writel(MMCI_BIT(SWRST), >cr);  /* soft reset */
@@ -393,22 +402,23 @@ int atmel_mci_init(void *regs)
 {
struct mmc *mmc;
struct mmc_config *cfg;
-   struct atmel_mci *mci;
+   struct atmel_mci_priv *priv;
unsigned int version;
 
-   cfg = malloc(sizeof(*cfg));
-   if (cfg == NULL)
-   return -1;
-   memset(cfg, 0, sizeof(*cfg));
+   priv = calloc(1, sizeof(*priv));
+   if (!priv)
+   return -ENOMEM;
 
-   mci = (struct atmel_mci *)regs;
+   cfg = >cfg;
 
cfg->name = "mci";
cfg->ops = _mci_ops;
 
+   priv->mci = (struct atmel_mci *)regs;
+
/* need to be able to pass these in on a board by board basis */
cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
-   version = atmel_mci_get_version(mci);
+   version = atmel_mci_get_version(priv->mci);
if ((version & 0xf00) >= 0x300) {
cfg->host_caps = MMC_MODE_8BIT;
cfg->host_caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz;
@@ -425,7 +435,7 @@ int atmel_mci_init(void *regs)
 
cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
 
-   mmc = mmc_create(cfg, regs);
+   mmc = mmc_create(cfg, priv);
 
if (mmc == NULL) {
free(cfg);
-- 
2.1.4

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[U-Boot] [PATCH] ARM: at91: sama5: change the environment address to 0x6000

[Josh Wu]

As sama5 board has 32k sram size, so the at91bootstrap and spl for sama5
boards is bigger than 16k (0x4000). That will overlap the U-Boot
environment. So I move environment to 0x6000. And reduce its size as
well.

Signed-off-by: Josh Wu 
---

 include/configs/at91-sama5_common.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/include/configs/at91-sama5_common.h 
b/include/configs/at91-sama5_common.h
index a5990ce..0b60f0b 100644
--- a/include/configs/at91-sama5_common.h
+++ b/include/configs/at91-sama5_common.h
@@ -98,8 +98,8 @@
 #elif CONFIG_SYS_USE_SERIALFLASH
 /* u-boot env in serial flash, by default is bus 0 and cs 0 */
 #define CONFIG_ENV_IS_IN_SPI_FLASH
-#define CONFIG_ENV_OFFSET  0x4000
-#define CONFIG_ENV_SIZE0x4000
+#define CONFIG_ENV_OFFSET  0x6000
+#define CONFIG_ENV_SIZE0x2000
 #define CONFIG_ENV_SECT_SIZE   0x1000
 #define CONFIG_BOOTCOMMAND "sf probe 0; "  
\
"sf read 0x2100 0x6 0xc000; "   
\
-- 
1.9.1

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[U-Boot] [PATCH] at91: simplify spl board_init_f function

[Josh Wu]

crt0.S do both memset the bss section and call board_init_r for us, so
remove them from board_init_f().

Signed-off-by: Josh Wu 
---

 arch/arm/mach-at91/spl_atmel.c | 5 -
 1 file changed, 5 deletions(-)

diff --git a/arch/arm/mach-at91/spl_atmel.c b/arch/arm/mach-at91/spl_atmel.c
index 8ac5335..b2fb51d 100644
--- a/arch/arm/mach-at91/spl_atmel.c
+++ b/arch/arm/mach-at91/spl_atmel.c
@@ -98,9 +98,4 @@ void board_init_f(ulong dummy)
preloader_console_init();
 
mem_init();
-
-   /* Clear the BSS. */
-   memset(__bss_start, 0, __bss_end - __bss_start);
-
-   board_init_r(NULL, 0);
 }
-- 
1.9.1

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Re: [U-Boot] [PATCH 00/12] SPL mmc refactor and alternate boot device feature

[Nikita Kiryanov]

Hi Otavio,

On Thu, Oct 22, 2015 at 10:24:57AM -0200, Otavio Salvador wrote:
> On Thu, Oct 22, 2015 at 10:01 AM, Nikita Kiryanov  
> wrote:
> > This series has two parts: patches 1-7 perform refactors aimed at reducing 
> > the
> > ifdef complexity of SPL mmc code (and some nand as well). This refactor also
> > addresses a few design issues I noticed while working on the refactor.
> >
> > The rest of the series introduces a new SPL feature that allows board code 
> > to
> > define a list of boot devices that SPL will try before failing (instead of 
> > the
> > only one device it attempts now). This feature is useful for implementing
> > fallbacks, as well as reacting to bootROM sequences. For example:
> >
> > On CM-FX6, if boot from the alternate boot device (MMC) fails, the bootROM
> > proceeds to try boot from SPI flash. If the SPI flash boot is succesful, SPL
> > will still try to load U-Boot from MMC, instead of from the actual boot 
> > device
> > (SPI flash), and probably fail and hang. The alternate boot feature makes it
> > possible for SPL to follow the MMC boot attempt with boot from the SPI 
> > flash.
> > The CM-FX6 based miniature PC Utilite depends on this capability for its SPI
> > flash boot to work, since SPI flash boot is only attempted if MMC boot 
> > fails.
> >
> > This series was tested on CM-FX6 and compile tested for arm and powerpc.
> 
> Thanks a lot for working on this; it does improves the SPL framework
> and extends its feature set. One thing I missed is the patches to
> rework the current boards removing the defines the serie drops and a
> proper documentation in the README files.

I'll make the additions once it's clear what part of the spl_mmc
refactor is accepted. There shouldn't be much changes for the board
files though, since the #defines themselves are not eliminated, just
that their checks are moved to a place where they will not make it
difficult to read the source code.

> 
> -- 
> Otavio Salvador O.S. Systems
> http://www.ossystems.com.brhttp://code.ossystems.com.br
> Mobile: +55 (53) 9981-7854Mobile: +1 (347) 903-9750
> 
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Re: [U-Boot] [PATCH 2/5] splash_source: add support for filesystem formatted mmc

[Nikita Kiryanov]

On Wed, Oct 21, 2015 at 03:25:58PM +0300, Igor Grinberg wrote:
> Hi Nikita,
> 
> On 08/30/15 11:42, Nikita Kiryanov wrote:
> > Add support for loading splash image from an SD card formatted with
> > a filesystem. Update boards to maintain original behavior where needed.
> > 
> > Cc: Igor Grinberg 
> > Cc: Tom Rini 
> > Signed-off-by: Nikita Kiryanov 
> > ---
> 
> [...]
> 
> > diff --git a/common/splash_source.c b/common/splash_source.c
> > index 4820c12..cb45c63 100644
> > --- a/common/splash_source.c
> > +++ b/common/splash_source.c
> 
> [...]
> 
> > +static int splash_load_fs(struct splash_location *location, u32 
> > bmp_load_addr)
> > +{
> > +   int res;
> > +   loff_t bmp_size;
> > +
> > +   res = splash_select_fs_dev(location);
> > +   if (res)
> > +   return res;
> > +
> > +   res = fs_size("splash.bmp", _size);
> 
> The splash.bmp can be a default file name (which is selected through
> menuconfig), but I think, will it be better to make it a env variable?

Well, the menuconfig part I think is best left to another series because it
won't be a simple addition: default file name define would have to
depend on CONFIG_SPLASH_SOURCE, which shouldn't exist as an option
without CONFIG_SPLASH_SCREEN and its related defines, none of which have
a fitting place in the current menuconfig hierarchy. Then there's the
board config file changes these additions would cause.

As for the env variable suggestion though, that can be done.

> 
> > +   if (res) {
> > +   printf("Error (%d): cannot determine file size\n", res);
> > +   return res;
> > +   }
> > +
> > +   if (bmp_load_addr + bmp_size >= gd->start_addr_sp) {
> > +   printf("Error: splashimage address too high. Data overwrites 
> > U-Boot and/or placed beyond DRAM boundaries.\n");
> > +   return -EFAULT;
> > +   }
> > +
> > +   splash_select_fs_dev(location);
> > +   return fs_read("splash.bmp", bmp_load_addr, 0, 0, NULL);
> > +}
> > +
> 
> [...]
> 
> -- 
> Regards,
> Igor.
> 
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Re: [U-Boot] Pull request: u-boot-nios/master

[Tom Rini]

On Fri, Oct 23, 2015 at 03:04:14PM +0800, Thomas Chou wrote:

> Hi Tom,
> 
> Please pull,
> 
> The following changes since commit 9f13b6d147dc74f2400ce18d9d4005ba53f21fd3:
> 
>   ARM: AM335x: mux: change mmc0 cd pinmux from mmc0_sdcd to gpio (2015-10-22 
> 14:44:03 -0400)
> 
> are available in the git repository at:
> 
>   git://git.denx.de/u-boot-nios.git master
> 
> for you to fetch changes up to 96fa1e4385bb1b63c58c48d10b552605f47a6f7f:
> 
>   net: convert altera_tse to driver model and phylib (2015-10-23 14:55:48 
> +0800)
> 

Applied to u-boot/master, thanks!

-- 
Tom


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Re: [U-Boot] [PATCH] at91: simplify spl board_init_f function

[Simon Glass]

On 23 October 2015 at 03:23, Josh Wu  wrote:
> crt0.S do both memset the bss section and call board_init_r for us, so
> remove them from board_init_f().
>
> Signed-off-by: Josh Wu 
> ---
>
>  arch/arm/mach-at91/spl_atmel.c | 5 -
>  1 file changed, 5 deletions(-)

Reviewed-by: Simon Glass 
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[U-Boot] [PATCH v7 3/5] tricorder: switch to CONFIG_SYS_THUMB_BUILD

[Albert ARIBAUD]

The tricorder and tricorder_flash boards have grown too big.
Reduce their size by building them with CONFIG_SYS_THUMB_BUILD.

Signed-off-by: Albert ARIBAUD 
---

Changes in v7: None
Changes in v6: None
Changes in v5:
- switched tricorder[_flash] to Thumb-1 build

Changes in v4: None
Changes in v3: None
Changes in v2: None

 include/configs/tricorder.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/include/configs/tricorder.h b/include/configs/tricorder.h
index f04b572..2ac141c 100644
--- a/include/configs/tricorder.h
+++ b/include/configs/tricorder.h
@@ -17,6 +17,7 @@
 #define __CONFIG_H
 
 /* High Level Configuration Options */
+#define CONFIG_SYS_THUMB_BUILD
 #define CONFIG_OMAP/* in a TI OMAP core */
 #define CONFIG_OMAP_COMMON
 /* Common ARM Erratas */
-- 
2.1.4

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[U-Boot] [PATCH v7 5/5] Revive OpenRD targets

[Albert ARIBAUD]

Revert commit 7a2c1b13 which dropped OpenRD boards.
Assume maintainership of OpenRD.
Remove OpenRD from scrapyard.
Switch OpenRD to generic board.
Switch to Thumb build.

Signed-off-by: Albert ARIBAUD 
---

Changes in v7:
- remove openrd lines from doc/README.scrapyard

Changes in v6:
- revive OpenRD targets and assume maintainership
- switch OpenRD to generic board and Thumb
- fix checkpatch warning and checks

Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None

 arch/arm/mach-kirkwood/Kconfig|   4 +
 board/Marvell/openrd/Kconfig  |  12 +++
 board/Marvell/openrd/MAINTAINERS  |  12 +++
 board/Marvell/openrd/Makefile |  14 
 board/Marvell/openrd/kwbimage.cfg | 152 
 board/Marvell/openrd/openrd.c | 160 ++
 board/Marvell/openrd/openrd.h |  30 +++
 configs/openrd_base_defconfig |   7 ++
 configs/openrd_client_defconfig   |   7 ++
 configs/openrd_ultimate_defconfig |   7 ++
 doc/README.scrapyard  |   3 -
 include/configs/openrd.h  | 140 +
 12 files changed, 545 insertions(+), 3 deletions(-)
 create mode 100644 board/Marvell/openrd/Kconfig
 create mode 100644 board/Marvell/openrd/MAINTAINERS
 create mode 100644 board/Marvell/openrd/Makefile
 create mode 100644 board/Marvell/openrd/kwbimage.cfg
 create mode 100644 board/Marvell/openrd/openrd.c
 create mode 100644 board/Marvell/openrd/openrd.h
 create mode 100644 configs/openrd_base_defconfig
 create mode 100644 configs/openrd_client_defconfig
 create mode 100644 configs/openrd_ultimate_defconfig
 create mode 100644 include/configs/openrd.h

diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig
index aab5d19..f7737bf 100644
--- a/arch/arm/mach-kirkwood/Kconfig
+++ b/arch/arm/mach-kirkwood/Kconfig
@@ -4,6 +4,9 @@ choice
prompt "Marvell Kirkwood board select"
optional
 
+config TARGET_OPENRD
+   bool "Marvell OpenRD Board"
+
 config TARGET_DREAMPLUG
bool "DreamPlug Board"
 
@@ -51,6 +54,7 @@ endchoice
 config SYS_SOC
default "kirkwood"
 
+source "board/Marvell/openrd/Kconfig"
 source "board/Marvell/dreamplug/Kconfig"
 source "board/Marvell/guruplug/Kconfig"
 source "board/Marvell/sheevaplug/Kconfig"
diff --git a/board/Marvell/openrd/Kconfig b/board/Marvell/openrd/Kconfig
new file mode 100644
index 000..124b66d
--- /dev/null
+++ b/board/Marvell/openrd/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_OPENRD
+
+config SYS_BOARD
+   default "openrd"
+
+config SYS_VENDOR
+   default "Marvell"
+
+config SYS_CONFIG_NAME
+   default "openrd"
+
+endif
diff --git a/board/Marvell/openrd/MAINTAINERS b/board/Marvell/openrd/MAINTAINERS
new file mode 100644
index 000..3789a04
--- /dev/null
+++ b/board/Marvell/openrd/MAINTAINERS
@@ -0,0 +1,12 @@
+OPENRD BOARD
+M: Albert ARIBAUD 
+S: Maintained
+F: board/Marvell/openrd/
+F: include/configs/openrd.h
+F: configs/openrd_base_defconfig
+
+OPENRD_CLIENT BOARD
+M: Albert ARIBAUD 
+S: Maintained
+F: configs/openrd_client_defconfig
+F: configs/openrd_ultimate_defconfig
diff --git a/board/Marvell/openrd/Makefile b/board/Marvell/openrd/Makefile
new file mode 100644
index 000..8f95b79
--- /dev/null
+++ b/board/Marvell/openrd/Makefile
@@ -0,0 +1,14 @@
+#
+# (C) Copyright 2009
+# Net Insight 
+# Written-by: Simon Kagstrom 
+#
+# Based on sheevaplug:
+# (C) Copyright 2009
+# Marvell Semiconductor 
+# Written-by: Prafulla Wadaskar 
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y  := openrd.o
diff --git a/board/Marvell/openrd/kwbimage.cfg 
b/board/Marvell/openrd/kwbimage.cfg
new file mode 100644
index 000..8e59937
--- /dev/null
+++ b/board/Marvell/openrd/kwbimage.cfg
@@ -0,0 +1,152 @@
+#
+# (C) Copyright 2009
+# Marvell Semiconductor 
+# Written-by: Prafulla Wadaskar 
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Refer doc/README.kwbimage for more details about how-to configure
+# and create kirkwood boot image
+#
+
+# Boot Media configurations
+BOOT_FROM  nand
+NAND_ECC_MODE  default
+NAND_PAGE_SIZE 0x0800
+
+# SOC registers configuration using bootrom header extension
+# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
+
+# Configure RGMII-0 interface pad voltage to 1.8V
+DATA 0xFFD100e0 0x1b1b1b9b
+
+#Dram initalization for SINGLE x16 CL=5 @ 400MHz
+DATA 0xFFD01400 0x43000c30 # DDR Configuration register
+# bit13-0:  0xc30 (3120 DDR2 clks refresh rate)
+# bit23-14: zero
+# bit24: 1= enable exit self refresh mode on DDR access
+# bit25: 1 required
+# bit29-26: zero
+# bit31-30: 01
+
+DATA 0xFFD01404 0x37543000 # DDR Controller Control Low
+# bit 4:0=addr/cmd in smame cycle
+# bit 5:0=clk is driven during self refresh, we don't care for APX
+# bit 6:0=use recommended 

[U-Boot] [PATCH v7 4/5] kirkwood: support CONFIG_SYS_THUMB_BUILD

[Albert ARIBAUD]

Kirkwood files cpu.c and cache.c cannot build in Thumb state;
force them in ARM state even under CONFIG_SYS_THUMB_BUILD.

Signed-off-by: Albert ARIBAUD 
---

Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None

 arch/arm/mach-kirkwood/Makefile | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm/mach-kirkwood/Makefile b/arch/arm/mach-kirkwood/Makefile
index df4756e..5abcf70 100644
--- a/arch/arm/mach-kirkwood/Makefile
+++ b/arch/arm/mach-kirkwood/Makefile
@@ -9,3 +9,9 @@
 obj-y  = cpu.o
 obj-y  += cache.o
 obj-y  += mpp.o
+
+# cpu.o and cache.o contain CP15 instructions which cannot be run in
+# Thumb state, so build them for ARM state even with CONFIG_SYS_THUMB_BUILD
+
+CFLAGS_cpu.o := -marm
+CFLAGS_cache.o := -marm
-- 
2.1.4

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[U-Boot] [PATCH] vexpress64: use 2nd DRAM bank only on juno

[Ryan Harkin]

This patch makes the 2nd DRAM bank available on Juno only and not on
other vexpress64 targets, eg. the FVP models.

The commit below added a 2nd bank of NOR flash for Juno, but also for
all vexpress64 targets:

commit 2d0cee1ca2b9d977fa3214896bb2e30cfec77059
Author: Liviu Dudau 
Date:   Mon Oct 19 11:08:31 2015 +0100

vexpress64: Juno: Declare all 8GB of RAM and make them visible to the 
kernel.

Juno comes with 8GB RAM, but U-Boot only passes 2GB to the kernel.
Declare a secondary memory bank and set the sizes correctly.

Signed-off-by: Liviu Dudau 
Reviewed-by: Linus Walleij 
Reviewed-by: Ryan Harkin 
Tested-by: Ryan Harkin 

Unfortunately, I only fully tested on Juno R0, R1 and the FVP Foundation
model.  Whilst FVP Base AEMV8 models run U-Boot OK, they fail to boot
the kernel.

Signed-off-by: Ryan Harkin 
---
 board/armltd/vexpress64/vexpress64.c |  2 ++
 include/configs/vexpress_aemv8a.h| 13 ++---
 2 files changed, 12 insertions(+), 3 deletions(-)

diff --git a/board/armltd/vexpress64/vexpress64.c 
b/board/armltd/vexpress64/vexpress64.c
index f4e8084..22d7e6c 100644
--- a/board/armltd/vexpress64/vexpress64.c
+++ b/board/armltd/vexpress64/vexpress64.c
@@ -44,8 +44,10 @@ void dram_init_banksize(void)
 {
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+#ifdef PHYS_SDRAM_2
gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
+#endif
 }
 
 /*
diff --git a/include/configs/vexpress_aemv8a.h 
b/include/configs/vexpress_aemv8a.h
index 0f2f1a3..18ab915 100644
--- a/include/configs/vexpress_aemv8a.h
+++ b/include/configs/vexpress_aemv8a.h
@@ -168,15 +168,22 @@
 #define CONFIG_SYS_LOAD_ADDR   (V2M_BASE + 0x1000)
 
 /* Physical Memory Map */
-#define CONFIG_NR_DRAM_BANKS   2
 #define PHYS_SDRAM_1   (V2M_BASE)  /* SDRAM Bank #1 */
-#define PHYS_SDRAM_2   (0x88000)
 /* Top 16MB reserved for secure world use */
 #define DRAM_SEC_SIZE  0x0100
 #define PHYS_SDRAM_1_SIZE  0x8000 - DRAM_SEC_SIZE
-#define PHYS_SDRAM_2_SIZE  0x18000
 #define CONFIG_SYS_SDRAM_BASE  PHYS_SDRAM_1
 
+#ifdef CONFIG_TARGET_VEXPRESS64_JUNO
+#define CONFIG_NR_DRAM_BANKS   2
+#define PHYS_SDRAM_2   (0x88000)
+#define PHYS_SDRAM_2_SIZE  0x18000
+#define CONFIG_NR_DRAM_BANKS_LIST  { PHYS_SDRAM_1 , PHYS_SDRAM_2}
+#else
+#define CONFIG_NR_DRAM_BANKS   1
+#define CONFIG_NR_DRAM_BANKS_LIST  { PHYS_SDRAM_1 }
+#endif
+
 /* Enable memtest */
 #define CONFIG_CMD_MEMTEST
 #define CONFIG_SYS_MEMTEST_START   PHYS_SDRAM_1
-- 
2.1.4

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[U-Boot] [PATCH] cfi_flash: use specific width types for cword

[Ryan Harkin]

This patch changes the cword union to use specific length types that are
architecture indepented.

This patch also renames the members of the cword union to represent
their usage, i.e.:

c  -> w8
s  -> w16
l  -> w32
ll -> w64

Where "w" stands for "width" in bits.

I discovered this problem when enabling CFI flash on vexpress64.
cword.l was an unsigned long int, but it was intended to be 32 bits wide.
Unfortunately, it's 64-bits wide on a 64-bit system, meaning that a
64-bit system fails when attempting to use 32-bit wide CFI flash parts.

Similar problems also existed with the other cword sizes.

Signed-off-by: Ryan Harkin 
---
 drivers/mtd/cfi_flash.c | 82 -
 include/mtd/cfi_flash.h |  8 ++---
 2 files changed, 45 insertions(+), 45 deletions(-)

diff --git a/drivers/mtd/cfi_flash.c b/drivers/mtd/cfi_flash.c
index 50983b8..fc7a878 100644
--- a/drivers/mtd/cfi_flash.c
+++ b/drivers/mtd/cfi_flash.c
@@ -335,34 +335,34 @@ void flash_write_cmd (flash_info_t * info, flash_sect_t 
sect,
switch (info->portwidth) {
case FLASH_CFI_8BIT:
debug ("fwc addr %p cmd %x %x 8bit x %d bit\n", addr, cmd,
-  cword.c, info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
-   flash_write8(cword.c, addr);
+  cword.w8, info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
+   flash_write8(cword.w8, addr);
break;
case FLASH_CFI_16BIT:
debug ("fwc addr %p cmd %x %4.4x 16bit x %d bit\n", addr,
-  cmd, cword.w,
+  cmd, cword.w16,
   info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
-   flash_write16(cword.w, addr);
+   flash_write16(cword.w16, addr);
break;
case FLASH_CFI_32BIT:
-   debug ("fwc addr %p cmd %x %8.8lx 32bit x %d bit\n", addr,
-  cmd, cword.l,
+   debug ("fwc addr %p cmd %x %8.8x 32bit x %d bit\n", addr,
+  cmd, cword.w32,
   info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
-   flash_write32(cword.l, addr);
+   flash_write32(cword.w32, addr);
break;
case FLASH_CFI_64BIT:
 #ifdef DEBUG
{
char str[20];
 
-   print_longlong (str, cword.ll);
+   print_longlong (str, cword.w64);
 
debug ("fwrite addr %p cmd %x %s 64 bit x %d bit\n",
   addr, cmd, str,
   info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
}
 #endif
-   flash_write64(cword.ll, addr);
+   flash_write64(cword.w64, addr);
break;
}
 
@@ -393,16 +393,16 @@ static int flash_isequal (flash_info_t * info, 
flash_sect_t sect,
debug ("is= cmd %x(%c) addr %p ", cmd, cmd, addr);
switch (info->portwidth) {
case FLASH_CFI_8BIT:
-   debug ("is= %x %x\n", flash_read8(addr), cword.c);
-   retval = (flash_read8(addr) == cword.c);
+   debug ("is= %x %x\n", flash_read8(addr), cword.w8);
+   retval = (flash_read8(addr) == cword.w8);
break;
case FLASH_CFI_16BIT:
-   debug ("is= %4.4x %4.4x\n", flash_read16(addr), cword.w);
-   retval = (flash_read16(addr) == cword.w);
+   debug ("is= %4.4x %4.4x\n", flash_read16(addr), cword.w16);
+   retval = (flash_read16(addr) == cword.w16);
break;
case FLASH_CFI_32BIT:
-   debug ("is= %8.8x %8.8lx\n", flash_read32(addr), cword.l);
-   retval = (flash_read32(addr) == cword.l);
+   debug ("is= %8.8x %8.8x\n", flash_read32(addr), cword.w32);
+   retval = (flash_read32(addr) == cword.w32);
break;
case FLASH_CFI_64BIT:
 #ifdef DEBUG
@@ -411,11 +411,11 @@ static int flash_isequal (flash_info_t * info, 
flash_sect_t sect,
char str2[20];
 
print_longlong (str1, flash_read64(addr));
-   print_longlong (str2, cword.ll);
+   print_longlong (str2, cword.w64);
debug ("is= %s %s\n", str1, str2);
}
 #endif
-   retval = (flash_read64(addr) == cword.ll);
+   retval = (flash_read64(addr) == cword.w64);
break;
default:
retval = 0;
@@ -439,16 +439,16 @@ static int flash_isset (flash_info_t * info, flash_sect_t 
sect,
flash_make_cmd (info, cmd, );
switch (info->portwidth) {
case FLASH_CFI_8BIT:
-   retval = ((flash_read8(addr) & cword.c) == cword.c);
+   retval = ((flash_read8(addr) & cword.w8) == cword.w8);
break;
case FLASH_CFI_16BIT:

Re: [U-Boot] [PATCH 4/8] dm: pci: Support decoding ranges with duplicate entries

[Simon Glass]

Hi Stephen,

On 21 October 2015 at 14:25, Stephen Warren  wrote:
> On 10/17/2015 11:50 AM, Simon Glass wrote:
>>
>> At present we add a new resource entry for every range entry. But some
>> range
>> entries refer to configuration regions. To make this work, avoid adding
>> two
>> regions of the same time. The later ranges will overwrite the earlier
>> (configuration) ones.
>
>
> s/time/type/ in the last-but-one line.
>
> What's wrong with having two regions of the same type? Equally, if we can
> "get away" with not storing some of the regions that happen to have a
> duplicate type, why not recast the function so that it only stores regions
> of specific (useful/desired) types, and simply dropping all of the other
> regions. That'd be a lot more consistent than only storing a somewhat
> arbitrary subset of the regions.

I'm not 100% sure that we want to disallow multiple regions. Although
on non-x86 boards I've haven't seen hardware that supports multiple
regions.

>
>> There does not seem to be a way to distinguish the configuration ranges
>> other than by ordering.
>
>
> Well, they do have different addresses too. But yes, the DT binding is
> written so that the entries in ranges must appear in a specific order, so
> order is the correct way to index the entries.
>
>> diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c
>
>
>> @@ -720,9 +721,15 @@ static int decode_regions(struct pci_controller
>> *hose, const void *blob,
>> } else {
>> continue;
>> }
>> -   debug(" - type=%d\n", type);
>> -   pci_set_region(hose->regions + hose->region_count++,
>> pci_addr,
>> -  addr, size, type);
>> +   pos = -1;
>> +   for (i = 0; i < hose->region_count; i++) {
>> +   if (hose->regions[i].flags == type)
>> +   pos = i;
>
>
> and break too?

Could do, might be clearer.

>
>
>> +   }
>> +   if (pos == -1)
>> +   pos = hose->region_count++;
>> +   debug(" - type=%d, pos=%d\n", type, pos);
>> +   pci_set_region(hose->regions + pos, pci_addr, addr, size,
>> type);
>> }
>
>

Regards,
Simon
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[U-Boot] [PATCH v4] Tegra: T210: Add QSPI driver

[Tom Warren]

This is the normal Tegra SPI driver modified to work with the
QSPI controller in Tegra210. It does not do 2x/4x transfers
or any other QSPI protocol.

Signed-off-by: Yen Lin 
Signed-off-by: Tom Warren 
---
Changes in v2:
- Drop defconfig and pinmux files, this is a driver-only patch.
- If/when pinmux tables have been updated for P2371/P2571, another
- patch will be sent to enable the QSPI driver on those boards.
Changes in v3:
- removed status reg write/clear in claim_bus(), done in xfer()
Changes in v4:
- added timeout in wait for FIFO flush status in xfer()
- used BIT and GENMASK macros throughout
- minor changes in copyright message in driver and Kconfig help

 drivers/spi/Kconfig |   7 +
 drivers/spi/Makefile|   1 +
 drivers/spi/tegra210_qspi.c | 408 
 3 files changed, 416 insertions(+)
 create mode 100644 drivers/spi/tegra210_qspi.c

diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 2f8cf19..95286da 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -123,6 +123,13 @@ config TEGRA20_SLINK
  be used to access the SPI NOR flash on platforms embedding this
  nVidia Tegra20/Tegra30 IP cores.
 
+config TEGRA210_QSPI
+   bool "nVidia Tegra210 QSPI driver"
+   help
+ Enable the Tegra Quad-SPI (QSPI) driver for T210. This driver
+ be used to access SPI chips on platforms embedding this
+ NVIDIA Tegra210 IP core.
+
 config XILINX_SPI
bool "Xilinx SPI driver"
help
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index de241be..209a41e 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -46,6 +46,7 @@ obj-$(CONFIG_SH_QSPI) += sh_qspi.o
 obj-$(CONFIG_TEGRA114_SPI) += tegra114_spi.o
 obj-$(CONFIG_TEGRA20_SFLASH) += tegra20_sflash.o
 obj-$(CONFIG_TEGRA20_SLINK) += tegra20_slink.o
+obj-$(CONFIG_TEGRA210_QSPI) += tegra210_qspi.o
 obj-$(CONFIG_TI_QSPI) += ti_qspi.o
 obj-$(CONFIG_XILINX_SPI) += xilinx_spi.o
 obj-$(CONFIG_ZYNQ_SPI) += zynq_spi.o
diff --git a/drivers/spi/tegra210_qspi.c b/drivers/spi/tegra210_qspi.c
new file mode 100644
index 000..521f745
--- /dev/null
+++ b/drivers/spi/tegra210_qspi.c
@@ -0,0 +1,408 @@
+/*
+ * NVIDIA Tegra210 QSPI controller driver
+ *
+ * (C) Copyright 2015 NVIDIA Corporation 
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include "tegra_spi.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* COMMAND1 */
+#define QSPI_CMD1_GO   BIT(31)
+#define QSPI_CMD1_M_S  BIT(30)
+#define QSPI_CMD1_MODE_MASKGENMASK(1,0)
+#define QSPI_CMD1_MODE_SHIFT   28
+#define QSPI_CMD1_CS_SEL_MASK  GENMASK(1,0)
+#define QSPI_CMD1_CS_SEL_SHIFT 26
+#define QSPI_CMD1_CS_POL_INACTIVE0 BIT(22)
+#define QSPI_CMD1_CS_SW_HW BIT(21)
+#define QSPI_CMD1_CS_SW_VALBIT(20)
+#define QSPI_CMD1_IDLE_SDA_MASKGENMASK(1,0)
+#define QSPI_CMD1_IDLE_SDA_SHIFT   18
+#define QSPI_CMD1_BIDIRBIT(17)
+#define QSPI_CMD1_LSBI_FE  BIT(16)
+#define QSPI_CMD1_LSBY_FE  BIT(15)
+#define QSPI_CMD1_BOTH_EN_BIT  BIT(14)
+#define QSPI_CMD1_BOTH_EN_BYTE BIT(13)
+#define QSPI_CMD1_RX_ENBIT(12)
+#define QSPI_CMD1_TX_ENBIT(11)
+#define QSPI_CMD1_PACKED   BIT(5)
+#define QSPI_CMD1_BITLEN_MASK  GENMASK(4,0)
+#define QSPI_CMD1_BITLEN_SHIFT 0
+
+/* COMMAND2 */
+#define QSPI_CMD2_TX_CLK_TAP_DELAY BIT(6)
+#define QSPI_CMD2_TX_CLK_TAP_DELAY_MASKGENMASK(11,6)
+#define QSPI_CMD2_RX_CLK_TAP_DELAY BIT(0)
+#define QSPI_CMD2_RX_CLK_TAP_DELAY_MASKGENMASK(5,0)
+
+/* TRANSFER STATUS */
+#define QSPI_XFER_STS_RDY  BIT(30)
+
+/* FIFO STATUS */
+#define QSPI_FIFO_STS_CS_INACTIVE  BIT(31)
+#define QSPI_FIFO_STS_FRAME_ENDBIT(30)
+#define QSPI_FIFO_STS_RX_FIFO_FLUSHBIT(15)
+#define QSPI_FIFO_STS_TX_FIFO_FLUSHBIT(14)
+#define QSPI_FIFO_STS_ERR  BIT(8)
+#define QSPI_FIFO_STS_TX_FIFO_OVF  BIT(7)
+#define QSPI_FIFO_STS_TX_FIFO_UNR  BIT(6)
+#define QSPI_FIFO_STS_RX_FIFO_OVF  BIT(5)
+#define QSPI_FIFO_STS_RX_FIFO_UNR  BIT(4)
+#define QSPI_FIFO_STS_TX_FIFO_FULL BIT(3)
+#define QSPI_FIFO_STS_TX_FIFO_EMPTYBIT(2)
+#define QSPI_FIFO_STS_RX_FIFO_FULL BIT(1)
+#define QSPI_FIFO_STS_RX_FIFO_EMPTYBIT(0)
+
+#define QSPI_TIMEOUT   1000
+
+struct qspi_regs {
+   u32 command1;   /* 000:QSPI_COMMAND1 register */
+   u32 command2;   /* 004:QSPI_COMMAND2 register */
+   u32 timing1;/* 008:QSPI_CS_TIM1 register */
+   u32 timing2;/* 00c:QSPI_CS_TIM2 register */
+   u32 xfer_status;/* 010:QSPI_TRANS_STATUS register */
+   u32 fifo_status;/* 014:QSPI_FIFO_STATUS register */
+   u32 tx_data;/* 018:QSPI_TX_DATA register */
+  

[U-Boot] [PATCH v7 2/5] arm: support Thumb-1 with CONFIG_SYS_THUMB_BUILD

[Albert ARIBAUD]

When building a Thumb-1-only target with CONFIG_SYS_THUMB_BUILD,
some files fail to build, most of the time because they include
mcr instructions, which only exist for Thumb-2.

This patch introduces a Kconfig option CONFIG_THUMB2 and uses
it to select between Thumb-2 and ARM mode for the aforementioned
files.

Signed-off-by: Albert ARIBAUD 
---
This patch has been build-tested and run-tested on ED Mini V2,
above the "edmini: switch to SPL" patch, and found to reduce
U-Boot size by 25% and SPL size by 14%... and to run fine. :)

This patch has also been tested against side effects on the
non-Thumb wireless_space target. The binaries produced with
and without this patch were found to differ only by their
version string.

Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3:
- added arch/arm/lib/mem{set,cpy}.S to the list of modules
  which should always be built in ARM state.
- Selected HAS_THUMB2 for CPU_V7M.
- Fixed invalidate_l2_cache() when building for Thumb-1.

Changes in v2:
- fixed a typo in the commit message
- added file arch/arm/thumb1/include/asm/proc-armv/system.h,
  which overrides arch/arm/include/asm/proc-armv/system.h
  when building for Thumb-1 and provides non-functional but
  Thumb-compilable IRQ and FIQ related macros and functions.

 Makefile   |  2 +
 arch/arm/Kconfig   |  5 ++
 arch/arm/cpu/arm926ejs/Makefile| 11 
 arch/arm/cpu/arm926ejs/cache.c |  5 ++
 arch/arm/include/asm/cache.h   |  4 ++
 arch/arm/lib/Makefile  | 24 +
 arch/arm/lib/cache.c   | 11 
 arch/arm/lib/memcpy.S  |  4 +-
 arch/arm/lib/memset.S  |  2 +-
 arch/arm/mach-orion5x/Makefile | 10 
 arch/arm/thumb1/include/asm/proc-armv/system.h | 69 ++
 examples/standalone/Makefile   | 10 
 12 files changed, 154 insertions(+), 3 deletions(-)
 create mode 100644 arch/arm/thumb1/include/asm/proc-armv/system.h

diff --git a/Makefile b/Makefile
index d4c35ba..d7fbf95 100644
--- a/Makefile
+++ b/Makefile
@@ -605,6 +605,8 @@ KBUILD_CFLAGS += $(KCFLAGS)
 UBOOTINCLUDE:= \
-Iinclude \
$(if $(KBUILD_SRC), -I$(srctree)/include) \
+   $(if $(CONFIG_SYS_THUMB_BUILD), $(if $(CONFIG_HAS_THUMB2),, \
+   -I$(srctree)/arch/$(ARCH)/thumb1/include),) \
-I$(srctree)/arch/$(ARCH)/include \
-include $(srctree)/include/linux/kconfig.h
 
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 2632099..18aca86 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -10,6 +10,9 @@ config ARM64
 config HAS_VBAR
 bool
 
+config HAS_THUMB2
+bool
+
 config CPU_ARM720T
 bool
 
@@ -32,9 +35,11 @@ config CPU_ARM1176
 config CPU_V7
 bool
 select HAS_VBAR
+select HAS_THUMB2
 
 config CPU_V7M
bool
+select HAS_THUMB2
 
 config CPU_PXA
 bool
diff --git a/arch/arm/cpu/arm926ejs/Makefile b/arch/arm/cpu/arm926ejs/Makefile
index 63fa159..fe78922 100644
--- a/arch/arm/cpu/arm926ejs/Makefile
+++ b/arch/arm/cpu/arm926ejs/Makefile
@@ -20,3 +20,14 @@ obj-$(CONFIG_MX25) += mx25/
 obj-$(CONFIG_MX27) += mx27/
 obj-$(if $(filter mxs,$(SOC)),y) += mxs/
 obj-$(if $(filter spear,$(SOC)),y) += spear/
+
+# some files can only build in ARM or THUMB2, not THUMB1
+
+ifdef CONFIG_SYS_THUMB_BUILD
+ifndef CONFIG_HAS_THUMB2
+
+CFLAGS_cpu.o := -marm
+CFLAGS_cache.o := -marm
+
+endif
+endif
diff --git a/arch/arm/cpu/arm926ejs/cache.c b/arch/arm/cpu/arm926ejs/cache.c
index e5c1a6a..2839c86 100644
--- a/arch/arm/cpu/arm926ejs/cache.c
+++ b/arch/arm/cpu/arm926ejs/cache.c
@@ -82,4 +82,9 @@ void flush_dcache_all(void)
 /*
  * Stub implementations for l2 cache operations
  */
+
 __weak void l2_cache_disable(void) {}
+
+#if defined CONFIG_SYS_THUMB_BUILD
+__weak void invalidate_l2_cache(void) {}
+#endif
diff --git a/arch/arm/include/asm/cache.h b/arch/arm/include/asm/cache.h
index a836e9f..1f63127 100644
--- a/arch/arm/include/asm/cache.h
+++ b/arch/arm/include/asm/cache.h
@@ -16,6 +16,9 @@
 /*
  * Invalidate L2 Cache using co-proc instruction
  */
+#ifdef CONFIG_SYS_THUMB_BUILD
+void invalidate_l2_cache(void);
+#else
 static inline void invalidate_l2_cache(void)
 {
unsigned int val=0;
@@ -24,6 +27,7 @@ static inline void invalidate_l2_cache(void)
: : "r" (val) : "cc");
isb();
 }
+#endif
 
 void l2_cache_enable(void);
 void l2_cache_disable(void);
diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile
index 2bdfaba..f3db7b5 100644
--- a/arch/arm/lib/Makefile
+++ b/arch/arm/lib/Makefile
@@ -60,3 +60,27 @@ obj-$(CONFIG_DEBUG_LL)   += debug.o
 ifneq (,$(findstring -mabi=aapcs-linux,$(PLATFORM_CPPFLAGS)))
 extra-y+= eabi_compat.o
 endif
+

[U-Boot] [PATCH v7 0/5] Add support for Thumb-1 builds

[Albert ARIBAUD]

This series implements essential changes for thumb-1 support and
activates thumb-1 build for openrd and tricorder as a proof of
concept as well as a fix to bring the image sizes of openrd and
tricorder targets back under an acceptable limit.

For other targets, some additional files might need to be forced to
ARM building, notably architecture-specific instances of lowlevel_init.S
or of cpu.c. This should be handled on a case-by-case basis.

This series has two unfixed checkpatch diagnostics:

warning: arch/arm/mach-kirkwood/Kconfig,7:
please write a paragraph that describes the config symbol fully

(no option in this Kconfig has help info)

check: board/Marvell/openrd/openrd.c,42: Avoid CamelCase: 

(this is actually not an OpenRD problem and will be fixed
in another patch)

IMPORTANT NOTE:

The whole set has been build-tested across all ARM targets
and no build regression was detected -- actually, the series
does fix the x600 board which otherwise fails assembling an
mcr instruction.

Patch 1 has been confirmed to be binary-invariant.

Patch 2 has been build- and run-tested on ED Mini V2 (switched
temporarily to Thumb build) and confirmed to be binary-invariant
for non-thumb target Wireless Space.

Patches 3 through 6 have been build-tested BUT HAVE NOT BEEN
RUN-TESTED so far.

I will test on OpenRD (client) before the end of the merge
window, but:

*
Open-RD and Tricorder owners, PLEASE run-test this series
and report on the mailing list whether the target works.
*

Changes in v7:
- remove openrd lines from doc/README.scrapyard

Changes in v6:
- revive OpenRD targets and assume maintainership
- switch OpenRD to generic board and Thumb
- fix checkpatch warning and checks

Changes in v5:
- switched tricorder[_flash] to Thumb-1 build

Changes in v4:
- Made stm32f429-discovery explicitly state that it builds
  for Thumb

Changes in v3:
- added arch/arm/lib/mem{set,cpy}.S to the list of modules
  which should always be built in ARM state.
- Selected HAS_THUMB2 for CPU_V7M.
- Fixed invalidate_l2_cache() when building for Thumb-1.

Changes in v2:
- fixed a typo in the commit message
- added file arch/arm/thumb1/include/asm/proc-armv/system.h,
  which overrides arch/arm/include/asm/proc-armv/system.h
  when building for Thumb-1 and provides non-functional but
  Thumb-compilable IRQ and FIQ related macros and functions.

Albert ARIBAUD (5):
  stm32f429-discovery: add CONFIG_SYS_THUMB_BUILD
  arm: support Thumb-1 with CONFIG_SYS_THUMB_BUILD
  tricorder: switch to CONFIG_SYS_THUMB_BUILD
  kirkwood: support CONFIG_SYS_THUMB_BUILD
  Revive OpenRD targets

 Makefile   |   2 +
 arch/arm/Kconfig   |   5 +
 arch/arm/cpu/arm926ejs/Makefile|  11 ++
 arch/arm/cpu/arm926ejs/cache.c |   5 +
 arch/arm/include/asm/cache.h   |   4 +
 arch/arm/lib/Makefile  |  24 
 arch/arm/lib/cache.c   |  11 ++
 arch/arm/lib/memcpy.S  |   4 +-
 arch/arm/lib/memset.S  |   2 +-
 arch/arm/mach-kirkwood/Kconfig |   4 +
 arch/arm/mach-kirkwood/Makefile|   6 +
 arch/arm/mach-orion5x/Makefile |  10 ++
 arch/arm/thumb1/include/asm/proc-armv/system.h |  69 +++
 board/Marvell/openrd/Kconfig   |  12 ++
 board/Marvell/openrd/MAINTAINERS   |  12 ++
 board/Marvell/openrd/Makefile  |  14 +++
 board/Marvell/openrd/kwbimage.cfg  | 152 +++
 board/Marvell/openrd/openrd.c  | 160 +
 board/Marvell/openrd/openrd.h  |  30 +
 configs/openrd_base_defconfig  |   7 ++
 configs/openrd_client_defconfig|   7 ++
 configs/openrd_ultimate_defconfig  |   7 ++
 doc/README.scrapyard   |   3 -
 examples/standalone/Makefile   |  10 ++
 include/configs/openrd.h   | 140 ++
 include/configs/stm32f429-discovery.h  |   1 +
 include/configs/tricorder.h|   1 +
 27 files changed, 707 insertions(+), 6 deletions(-)
 create mode 100644 arch/arm/thumb1/include/asm/proc-armv/system.h
 create mode 100644 board/Marvell/openrd/Kconfig
 create mode 100644 board/Marvell/openrd/MAINTAINERS
 create mode 100644 board/Marvell/openrd/Makefile
 create mode 100644 board/Marvell/openrd/kwbimage.cfg
 create mode 100644 board/Marvell/openrd/openrd.c
 create mode 100644 board/Marvell/openrd/openrd.h
 create mode 100644 configs/openrd_base_defconfig
 create mode 100644 configs/openrd_client_defconfig
 create mode 100644 configs/openrd_ultimate_defconfig
 create mode 100644 include/configs/openrd.h

-- 
2.1.4

[U-Boot] [PATCH v7 1/5] stm32f429-discovery: add CONFIG_SYS_THUMB_BUILD

[Albert ARIBAUD]

This target is ARMv7-M therefore can only build for Thumb,
but it did not #define CONFIG_SYS_THUMB_BUILD, so the U-Boot
code did not know it had to build for Thumb(2), not ARM.

This patch is binary-invariant: builds of stm32f429-discovery
with and without this patch were compared and found to differ
only by their U-Boot version strings.

Signed-off-by: Albert ARIBAUD 
---

Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4:
- Made stm32f429-discovery explicitly state that it builds
  for Thumb

Changes in v3: None
Changes in v2: None

 include/configs/stm32f429-discovery.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/include/configs/stm32f429-discovery.h 
b/include/configs/stm32f429-discovery.h
index 19d9cf9..e773de4 100644
--- a/include/configs/stm32f429-discovery.h
+++ b/include/configs/stm32f429-discovery.h
@@ -9,6 +9,7 @@
 #define __CONFIG_H
 
 #define CONFIG_STM32F4
+#define CONFIG_SYS_THUMB_BUILD
 #define CONFIG_STM32F4DISCOVERY
 #define CONFIG_SYS_GENERIC_BOARD
 
-- 
2.1.4

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Re: [U-Boot] [PATCH 1/8] dm: tegra: pci: Move CONFIG_PCI_TEGRA to Kconfig

[Simon Glass]

Hi Stephen,

On 21 October 2015 at 14:13, Stephen Warren  wrote:
> On 10/17/2015 11:49 AM, Simon Glass wrote:
>>
>> Move this option to Kconig and fix up all users.
>
>
> What are your thoughts on how/when to merge this? The series (mainly the
> final patch) conflicts with my series to add Tegra210 support, plus one of
> them needs rebasing onto the other so that either the board support my
> series adds gets adjusted by this series, or my series is adjusted for all
> the changes in this series.
>
> Obviously I'd hope my series gets merged first since I sent it much
> earlier:-)
>
> FWIW, I rebased this series on top of my series to validate it, and pushed
> it to:
>
> git://github.com/swarren/u-boot.git pci-dm-conversion-rebase
>
> That seems to work OK, but the final patch I added there needs integration
> into earlier patches and/or cleanup work.

I don't mind which order it goes in. I cannot test on T210 anyway so I
may look to you to sort that out. Let me know what suits. I'll likely
respin this early next week and if your stuff in applied to tegra by
then then I'll base on top of it.

Regards,
Simon
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Re: [U-Boot] [PATCH 2/8] dm: pci: Avoid a driver model build error with CONFIG_CMD_PCI_ENUM

[Simon Glass]

Hi Stephen,

On 21 October 2015 at 14:16, Stephen Warren  wrote:
> On 10/17/2015 11:49 AM, Simon Glass wrote:
>>
>> This is not supported with driver model, so print a message instead of
>> generating a build error. Rescanning PCI is not yet implemented.
>
>
>> diff --git a/common/cmd_pci.c b/common/cmd_pci.c
>
>
>> @@ -457,7 +457,11 @@ static int do_pci(cmd_tbl_t *cmdtp, int flag, int
>> argc, char * const argv[])
>> return pci_cfg_display(bdf, addr, size, value);
>>   #ifdef CONFIG_CMD_PCI_ENUM
>> case 'e':
>> +# ifdef CONFIG_DM_PCI
>> +   printf("This command is not yet supported with driver
>> model\n");
>> +# else
>> pci_init();
>> +# endif
>
>
> That feature is enabled on most/all Tegra boards with PCI support. Hopefully
> nobody will miss it; I guess I haven't used it so I don't object to this
> change.
>
> However, wouldn't it be better to remove CONFIG_CMD_PCI_ENUM from the config
> header rather than leaving the command enabled yet non-functional? Or are
> you planning on implementing this path in the near future?

I was looking for feedback on why anyone would use this option. It's
not clear to me what it is for.

We can implement it for driver model if it is needed.

Regards,
Simon
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Re: [U-Boot] [PATCH v2 26/28] i8042: Handle a duplicate power-on-reset response

[Bin Meng]

Hi Simon,

On Mon, Oct 19, 2015 at 11:17 AM, Simon Glass  wrote:
> Sometimes we seem to get 0xaa twice which causes the config read to fail.
> This causes chromebook_link to fail to set up the keyboard.
>
> Add a check for this and read the config again when detected.
>
> Signed-off-by: Simon Glass 

Other than one typo below:

Reviewed-by: Bin Meng 

> ---
>
> Changes in v2:
> - Use device tree to handle this quirk
>
>  drivers/input/i8042.c | 21 +++--
>  1 file changed, 19 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/input/i8042.c b/drivers/input/i8042.c
> index e5e2926..6d358b7 100644
> --- a/drivers/input/i8042.c
> +++ b/drivers/input/i8042.c
> @@ -15,13 +15,20 @@
>  #include 
>  #include 
>
> +DECLARE_GLOBAL_DATA_PTR;
> +
>  /* defines */
>  #define in8(p) inb(p)
>  #define out8(p, v) outb(v, p)
>
> +enum {
> +   QUICK_DUP_POR   = 1 << 0,

typo: QUIRK

> +};
> +
>  /* locals */
>  struct i8042_kbd_priv {
> bool extended;  /* true if an extended keycode is expected next */
> +   int quirks; /* quirks that we support */
>  };
>
>  static unsigned char ext_key_map[] = {
> @@ -113,7 +120,7 @@ static int kbd_cmd_write(int cmd, int data)
> return kbd_write(I8042_DATA_REG, data);
>  }
>
> -static int kbd_reset(void)
> +static int kbd_reset(int quirk)
>  {
> int config;
>
> @@ -132,6 +139,10 @@ static int kbd_reset(void)
> if (config == -1)
> goto err;
>
> +   /* Sometimes get a second byte */
> +   else if ((quirk & QUICK_DUP_POR) && config == KBD_POR)
> +   config = kbd_cmd_read(CMD_RD_CONFIG);
> +
> config |= CONFIG_AT_TRANS;
> config &= ~(CONFIG_KIRQ_EN | CONFIG_MIRQ_EN);
> if (kbd_cmd_write(CMD_WR_CONFIG, config))
> @@ -246,6 +257,7 @@ static int i8042_kbd_check(struct input_config *input)
>  static int i8042_start(struct udevice *dev)
>  {
> struct keyboard_priv *uc_priv = dev_get_uclass_priv(dev);
> +   struct i8042_kbd_priv *priv = dev_get_priv(dev);
> struct input_config *input = _priv->input;
> int keymap, try;
> char *penv;
> @@ -264,7 +276,7 @@ static int i8042_start(struct udevice *dev)
> keymap = KBD_GER;
> }
>
> -   for (try = 0; kbd_reset() != 0; try++) {
> +   for (try = 0; kbd_reset(priv->quirks) != 0; try++) {
> if (try >= KBD_RESET_TRIES)
> return -1;
> }
> @@ -294,10 +306,15 @@ static int i8042_start(struct udevice *dev)
>  static int i8042_kbd_probe(struct udevice *dev)
>  {
> struct keyboard_priv *uc_priv = dev_get_uclass_priv(dev);
> +   struct i8042_kbd_priv *priv = dev_get_priv(dev);
> struct stdio_dev *sdev = _priv->sdev;
> struct input_config *input = _priv->input;
> int ret;
>
> +   if (fdtdec_get_bool(gd->fdt_blob, dev->of_offset,
> +   "intel,duplicate-por"))
> +   priv->quirks |= QUICK_DUP_POR;
> +
> /* Register the device. i8042_start() will be called soon */
> input->dev = dev;
> input->read_keys = i8042_kbd_check;
> --

Regards,
Bin
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Re: [U-Boot] [PATCH 3/5] splash_source: add support for filesystem formatted usb

[Igor Grinberg]

On 10/23/15 13:23, Nikita Kiryanov wrote:
> On Wed, Oct 21, 2015 at 04:01:46PM +0300, Igor Grinberg wrote:
>> On 08/30/15 11:42, Nikita Kiryanov wrote:
>>> Add support for loading splash image from USB drive formatted with a
>>> filesystem.
>>>
>>> Cc: Igor Grinberg 
>>> Cc: Tom Rini 
>>> Signed-off-by: Nikita Kiryanov 
>>
>> [...]
>>
>>> +#ifdef CONFIG_USB_STORAGE
>>> +   if (location->storage == SPLASH_STORAGE_USB) {
>>> +   usb_init();
>>> +   usb_stor_scan(1);
>>> +   }
>>> +#endif
>>
>> Can we use IS_ENABLED() stuff here instead?
> 
> IS_ENABLED() does not prevent compile errors, only closes off certain
> code paths.

Ok. Any other ways to not have that ifdefferry inside functions?


-- 
Regards,
Igor.
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Re: [U-Boot] [PATCH v8 1/4] include: Add log2 and fls64 header fi

[Tom Rini]

On Fri, Oct 23, 2015 at 06:36:27AM +0200, Wolfgang Denk wrote:
> Dear Tom,
> 
> In message <2015102627.GO23893@bill-the-cat> you wrote:
> > 
> > We don't have a hard rule here as we know the kernel will not adopt SPDX
> > tags currently.  For rare sync ups like this probably is, switching to a
> > tag might make sense, for stuff we'll resync every few kernel releases,
> > it's just resync noise possibly so I'll leave that to the people doing
> > the sync.
> 
> In any case the SPDX tag must be added.

Well, it comes down to how much of a PITA that makes re-syncing.  The
tags make life easier but the end goal is the reports.  This reminds me
that I need to go ping some people about the SPDX tooling, there's some
funny things to re-sync and some files to tag.

-- 
Tom


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Re: [U-Boot] [PATCH] fdt_support: Check for bank size before updating memory node

[Tom Rini]

On Fri, Oct 23, 2015 at 10:08:29AM +0530, Lokesh Vutla wrote:
> 
> 
> On Thursday 22 October 2015 08:21 PM, Tom Rini wrote:
> > On Thu, Oct 22, 2015 at 08:04:04PM +0530, Lokesh Vutla wrote:
> > 
> >> In case if one of the bank that is passed is of size zero, then u-boot
> >> will be updating memory node with a bank of size zero. There is not need
> >> to update memory node if size is zero, so check for bank size before
> > 
> > is not.
> Oops. will correct it in v2.
> 
> > 
> >> updating.
> >>
> >> Signed-off-by: Lokesh Vutla 
> >> ---
> >>  common/fdt_support.c | 3 +++
> >>  1 file changed, 3 insertions(+)
> >>
> >> diff --git a/common/fdt_support.c b/common/fdt_support.c
> >> index f86365e..0019eef 100644
> >> --- a/common/fdt_support.c
> >> +++ b/common/fdt_support.c
> >> @@ -401,6 +401,9 @@ static int fdt_pack_reg(const void *fdt, void *buf, 
> >> u64 *address, u64 *size,
> >>char *p = buf;
> >>  
> >>for (i = 0; i < n; i++) {
> >> +  if (size[i] == 0)
> >> +  continue;
> >> +
> >>if (address_cells == 2)
> >>*(fdt64_t *)p = cpu_to_fdt64(address[i]);
> >>else
> > 
> > So I suggested something along these lines a long while ago as part of
> > how to fix the problem of DT has correct (and larger than U-Boot can
> > see) memory size, so I like the change.  But it's a "big" behavior
> > change that we (I) need to note in the release notes at least.  When I
> > looked last things were either setting a 0 size or a correct looking
> > size, but I bet we'll still see a few things drop out wrt incorrect (too
> > small) memory size being passed.  I wonder what the best list(s) would
> > be to let everyone know about this would be...
> 
> Shall I take this as your Reviewed-by ? Not sure about how to let
> everyone know about this. Please let me know to whom all I have to cc
> for posting v2 of this patch.

Yeah, that counts as a reviewed by.  Once I merge this I'll go poke
lkml/lakml/linuxppc-dev at least.

-- 
Tom


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Re: [U-Boot] [PATCH 05/12] spl: mmc: get rid of #ifdef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION check

[Hans de Goede]

Hi,

On 10/23/2015 11:40 AM, Nikita Kiryanov wrote:

These are the results for arm boards.
Note that I had to manually edit a few files that caused buildman report
to stumble with the following type of error


Thanks, I see that the compiler manages to reduce the damage done to
growing the SPL (on sunxi) by only 16 bytes, which I must admit is better then
I expected and quite acceptable.

Regards,

Hans
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Re: [U-Boot] [PATCH 05/12] spl: mmc: get rid of #ifdef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION check

[Tom Rini]

On Fri, Oct 23, 2015 at 04:03:25PM +0200, Hans de Goede wrote:
> Hi,
> 
> On 10/23/2015 11:40 AM, Nikita Kiryanov wrote:
> >These are the results for arm boards.
> >Note that I had to manually edit a few files that caused buildman report
> >to stumble with the following type of error
> 
> Thanks, I see that the compiler manages to reduce the damage done to
> growing the SPL (on sunxi) by only 16 bytes, which I must admit is better then
> I expected and quite acceptable.

Indeed, thanks for doing the legwork Nikita!

-- 
Tom


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Re: [U-Boot] [Patch V7 04/18] net/fm/eth: Use mb() to be compatible for both ARM and PowerPC

[Scott Wood]

On Fri, 2015-10-23 at 06:01 -0500, Hou Zhiqiang-B48286 wrote:
> 
> > -Original Message-
> > From: Wood Scott-B07421
> > Sent: 2015年10月23日 7:11
> > To: Gong Qianyu-B52263
> > Cc: u-boot@lists.denx.de; Hu Mingkai-B21284; Sun York-R58495; Hou
> > Zhiqiang-B48286; Xie Shaohui-B21989; Song Wenbin-B53747; Wood Scott-
> > B07421; Kushwaha Prabhakar-B32579; Wang Huan-B18965
> > Subject: Re: [Patch V7 04/18] net/fm/eth: Use mb() to be compatible for
> > both ARM and PowerPC
> > 
> > On Thu, 2015-10-22 at 18:46 +0800, Gong Qianyu wrote:
> > > From: Shaohui Xie 
> > > 
> > > Use mb() instead of sync() to be compatible for both ARM and PowerPC.
> > > 
> > > Signed-off-by: Shaohui Xie 
> > > Signed-off-by: Mingkai Hu 
> > > Signed-off-by: Gong Qianyu 
> > > ---
> > > V7:
> > >  - No change.
> > > V6:
> > >  - No change.
> > > V5:
> > >  - No change.
> > > V4:
> > >  - No change.
> > > V3:
> > >  - New patch. Separated from patch 'net: Move some header files to
> > include/'
> > > 
> > >  drivers/net/fm/eth.c | 14 +++---
> > >  1 file changed, 7 insertions(+), 7 deletions(-)
> > > 
> > > diff --git a/drivers/net/fm/eth.c b/drivers/net/fm/eth.c index
> > > 368d554..ad02c66 100644
> > > --- a/drivers/net/fm/eth.c
> > > +++ b/drivers/net/fm/eth.c
> > > @@ -371,7 +371,7 @@ static void
> > > fmc_tx_port_graceful_stop_enable(struct
> > > fm_eth *fm_eth)
> > >   pram = fm_eth->tx_pram;
> > >   /* graceful stop transmission of frames */
> > >   setbits_be32(>mode, PRAM_MODE_GRACEFUL_STOP);
> > > - sync();
> > > + mb();
> > >  }
> > > 
> > >  static void fmc_tx_port_graceful_stop_disable(struct fm_eth *fm_eth)
> > > @@ -381,7 +381,7 @@ static void
> > > fmc_tx_port_graceful_stop_disable(struct
> > > fm_eth *fm_eth)
> > >   pram = fm_eth->tx_pram;
> > >   /* re-enable transmission of frames */
> > >   clrbits_be32(>mode, PRAM_MODE_GRACEFUL_STOP);
> > > - sync();
> > > + mb();
> > >  }
> > 
> > Why is it needed at all?  The I/O accessors should include the necessary
> > barriers.
> 
> The I/O accessors of powerpc does include the barrier, but it absents from 
> ARMs'.

Then fix ARM's accessors if they're missing barriers that are required.  But 
first, consider whether the barrier is required on ARM.  What is special 
about FM that it needs it where all other drivers don't?

-Scott

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[U-Boot] [PATCH] include/linux/mtd: Update copyright notices

[Tom Rini]

Condense these updates down to SPDX tags too while doing this.  This is
a port of a1452a3771c4eb85bd779790b040efdc36f4274e from the Linux
Kernel.

Signed-off-by: Tom Rini 
---
 include/linux/mtd/concat.h   |5 +++--
 include/linux/mtd/doc2000.h  |   11 ++-
 include/linux/mtd/mtd.h  |2 +-
 include/linux/mtd/nand_ecc.h |8 
 4 files changed, 14 insertions(+), 12 deletions(-)

diff --git a/include/linux/mtd/concat.h b/include/linux/mtd/concat.h
index 195a4a5..a374ca9 100644
--- a/include/linux/mtd/concat.h
+++ b/include/linux/mtd/concat.h
@@ -1,9 +1,10 @@
 /*
  * MTD device concatenation layer definitions
  *
- * (C) 2002 Robert Kaiser 
+ * Copyright © 2002  Robert Kaiser 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
  *
- * This code is GPL
  */
 
 #ifndef MTD_CONCAT_H
diff --git a/include/linux/mtd/doc2000.h b/include/linux/mtd/doc2000.h
index ba29d53..a3cfe6b 100644
--- a/include/linux/mtd/doc2000.h
+++ b/include/linux/mtd/doc2000.h
@@ -1,12 +1,13 @@
 /*
  * Linux driver for Disk-On-Chip devices
  *
- * Copyright (C) 1999 Machine Vision Holdings, Inc.
- * Copyright (C) 2001-2003 David Woodhouse 
- * Copyright (C) 2002-2003 Greg Ungerer 
- * Copyright (C) 2002-2003 SnapGear Inc
+ * Copyright © 1999 Machine Vision Holdings, Inc.
+ * Copyright © 1999-2010 David Woodhouse 
+ * Copyright © 2002-2003 Greg Ungerer 
+ * Copyright © 2002-2003 SnapGear Inc
+ *
+ * SPDX-License-Identifier:GPL-2.0+
  *
- * Released under GPL
  */
 
 #ifndef __MTD_DOC2000_H__
diff --git a/include/linux/mtd/mtd.h b/include/linux/mtd/mtd.h
index bc4d9bf8f..c8bca4d 100644
--- a/include/linux/mtd/mtd.h
+++ b/include/linux/mtd/mtd.h
@@ -1,7 +1,7 @@
 /*
  * Copyright © 1999-2010 David Woodhouse  et al.
  *
- * Released under GPL
+ * SPDX-License-Identifier:GPL-2.0+
  *
  */
 
diff --git a/include/linux/mtd/nand_ecc.h b/include/linux/mtd/nand_ecc.h
index 090da50..02ba9f7 100644
--- a/include/linux/mtd/nand_ecc.h
+++ b/include/linux/mtd/nand_ecc.h
@@ -1,11 +1,11 @@
 /*
  *  drivers/mtd/nand_ecc.h
  *
- *  Copyright (C) 2000 Steven J. Hill (sjh...@realitydiluted.com)
+ *  Copyright (C) 2000-2010 Steven J. Hill 
+ * David Woodhouse 
+ * Thomas Gleixner 
  *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
+ * SPDX-License-Identifier:GPL-2.0
  *
  * This file is the header for the ECC algorithm.
  */
-- 
1.7.9.5

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Re: [U-Boot] u-boot device model SPI + SPI Flash

[Jagan Teki]

On 23 October 2015 at 15:42, Hoefle Marco  wrote:
> Maybe somebody has a valid u-boot dts file for a microblaze system with an 
> SPI core? That would helpful.
> We want to move from a parallel nor flash to a SPI flash for FPGA config, 
> u-boot, Linux Kernel and rootfs.
> The last missing part is u-boot. The kernel dts file is ok and the mtd 
> partitions are set up correctly.

I even grepped on linux/arch/microblaze couldn't get much info, So
added Michal he well aware of this
may be he can help.

>> > -Original Message-
>> > From: Jagan Teki [mailto:jt...@openedev.com]
>> > Sent: Mittwoch, 21. Oktober 2015 18:45
>> > To: Hoefle Marco 
>> > Cc: u-boot@lists.denx.de
>> > Subject: Re: [U-Boot] u-boot device model SPI + SPI Flash
>> >
>> > On 21 October 2015 at 22:10, Hoefle Marco 
>> > wrote:
>> > > Hello Jagan,
>> > > Thank you for your reply.
>> > > Please find my comments bellow. I missed to mention that I am using
>> > > mainline 2015.07
>> > >
>> > >
>> > >> -Original Message-
>> > >> From: Jagan Teki [mailto:jt...@openedev.com]
>> > >> Sent: Mittwoch, 21. Oktober 2015 18:28
>> > >> To: Hoefle Marco 
>> > >> Cc: u-boot@lists.denx.de
>> > >> Subject: Re: [U-Boot] u-boot device model SPI + SPI Flash
>> > >>
>> > >> On 21 October 2015 at 16:25, Hoefle Marco
>> > >> 
>> > >> wrote:
>> > >> >
>> > >> >  Hello,
>> > >> > I saw that here is also a mailing list dedicated to device model
>> > >> > issues but it
>> > >> looks obsolete (last post February 2014) so I am using this forum.
>> > >>
>> > >> Please note its driver model - not a device model.
>> > > Ok
>> > >>
>> > >> >
>> > >> > I have a problem nearly identically to
>> > >> > http://lists.denx.de/pipermail/u-boot/2015-April/210754.html
>> > >> >
>> > >> >
>> > >> > The SPI initialization does not work:
>> > >> >
>> > >> > Invalid bus 0 (err=-19)
>> > >> > *** Warning - spi_flash_probe() failed, using default environment
>> > >>
>> > >> Which board it is? dts file name?
>> > > It is a custom dts file. It is for a Microblaze CPU in an Artix FPGA.
>> > > The dts reflects that one below
>> > >>
>> > >> >
>> > >> >
>> > >> > This is the device tree compiled into u-boot:
>> > >> >
>> > >> > U-Boot> fdt addr 0x8FEB8A7C
>> > >> > U-Boot> fdt print
>> > >> > / {
>> > >> > #address-cells = <0x0001>;
>> > >> > #size-cells = <0x0001>;
>> > >> > aliases {
>> > >> > serial0 = "serial@4060";
>> > >> > spi0 = "/axi_quad_spi@44a0";
>> > >> > };
>> > >> > memory {
>> > >> > device_type = "memory";
>> > >> > reg = <0x8000 0x1000>;
>> > >> > };
>> > >> > axi_quad_spi@44a0 {
>> > >> > compatible = "xlnx,xps-spi-2.00.a";
>> > >>
>> > >> Do you need zynq spi or qspi driver there is no compatible string
>> > >> with "xlnx,xps-spi-2.00.a" do know which source you're using?
>> > > This driver is used:
>> > > u-boot/drivers/spi/xilinx_spi.c
>> >
>> > In that case, use the compatible in your dts as below
>> >
>> > static const struct udevice_id xilinx_spi_ids[] = {
>> > { .compatible = "xlnx,xilinx-spi" },
>> > { }
>> > };
>> That was a copy paste failure, sorry for that. The reason was that in  the
>> meanwhile I tried the original Xilinx driver from their github tree. They 
>> have
>> the tag: compatible = "xlnx,xps-spi-2.00.a"
>>
>> However, I changed back to have mainline code only an put a few printfs to
>> it:
>> U-Boot 2015.07--33711bdd4a4dce942fb5ae85a68899a8357bdd94---dirty (Oct
>> 22 2015 - 07:57:35 +0200)
>>
>> DRAM:  256 MiB
>> uclass_find_device_by_seq: 0 -1
>> uclass_find_device_by_seq: 0 0
>>- -1 -1
>>- not found
>> env_relocate: 267
>> spi_flash_probe: 410
>> busnum: 0, cs: 0, max_hz: 5000
>> spi_setup_slave: 336
>> spi_get_bus_and_cs: 248
>> uclass_find_device_by_seq: 0 0
>>- -1 -1
>>- not found
>> uclass_find_device_by_seq: 1 0
>>- -1 -1
>>- not found
>> Invalid bus 0 (err=-19)
>> *** Warning - spi_flash_probe() failed, using default environment
>>
>>
>> U-Boot> fdt addr 0x8FEB89FC
>> U-Boot> fdt print
>> / {
>> #address-cells = <0x0001>;
>> #size-cells = <0x0001>;
>> aliases {
>> serial0 = "/serial@4060";
>> spi0 = "/axi_quad_spi@44a0";
>> };
>> memory {
>> device_type = "memory";
>> reg = <0x8000 0x1000>;
>> };
>> serial@4060 {
>> clock-frequency = <0x05f5e100>;
>> compatible = "xlnx,xps-uartlite-1.00.a";
>> current-speed = <0x0001c200>;
>> };
>> axi_quad_spi@44a0 {
>> compatible = "xlnx,xilinx-spi";
>> reg = <0x44a0 0x0001>;
>> 

Re: [U-Boot] [RFC] odroid: Add support for the ODROID-X board variant

[Minkyu Kang]

Dear Siarhei Siamashka,

On 20/10/15 08:39, Siarhei Siamashka wrote:
> ODROID-X uses a slightly older revision of the same base board
> as the ODROID-X2. But the CPU module in ODROID-X uses an older
> 1.4GHz revision of Exynos4412 SoC and less RAM (1GiB instead
> of 2GiB).
> 
> The current U-Boot code deadlocks on ODROID-X when probing the RAM
> size via get_ram_size() function. Reducing CONFIG_NR_DRAM_BANKS
> from 8 to 4 can fix this problem. But this constant is used in
> a lot of places in U-Boot, while SDRAM_BANK_SIZE can be easily
> replaced with the code which relies on runtime detection of the
> board type. So we change 4 or 8 banks of 256MiB with just one
> fake bank of 2GiB or 1GiB. The runtime detection check tries to
> read the PRO_ID register in the hope that it might be different
> between Exynos4412 and Exynos4412 Prime and enough to detect
> the difference between X and X2 board variants.
> 
> Signed-off-by: Siarhei Siamashka 
> ---
> 
> I'm assuming that the X and X2 hardware is nearly identical
> and can be supported with a common code in U-Boot, based on
> the changelog of PCB revisions:
> http://com.odroid.com/sigong/blog/blog_list.php?bid=132
> 
> This is an RFC patch because I don't have an X2 board and can't
> test if checking the PRO_ID register is good enough. If it does
> not work, then maybe some other method could be tried (probe
> the DRAM controller registers?).
> 
> Also does the number of DRAM banks have any special meaning on
> this platform in U-Boot and Linux (after the proprietary blob
> has already initialized the DRAM controller)?
> 
> If this approach is wrong, then what would be the best way to
> add support for the ODROID-X board?
> 
> Thanks.
> 
>  board/samsung/common/board.c  | 21 +
>  board/samsung/odroid/odroid.c | 14 ++
>  include/configs/odroid.h  | 10 ++
>  3 files changed, 33 insertions(+), 12 deletions(-)
> 
> diff --git a/board/samsung/common/board.c b/board/samsung/common/board.c
> index d32c75d..ac3ed4c 100644
> --- a/board/samsung/common/board.c
> +++ b/board/samsung/common/board.c
> @@ -94,14 +94,26 @@ int board_init(void)
>   return exynos_init();
>  }
>  
> +static u32 get_sdram_bank_size(void)
> +{
> + u32 sdram_bank_size = SDRAM_BANK_SIZE;
> +#ifdef CONFIG_BOARD_TYPES
> + if (strcmp(CONFIG_SYS_BOARD, "odroid") == 0 &&
> + strcmp(get_board_type(), "x") == 0)
> + sdram_bank_size = SDRAM_BANK_SIZE_ODROIDX;
> +#endif
> + return sdram_bank_size;
> +}
> +
>  int dram_init(void)
>  {
>   unsigned int i;
>   u32 addr;
> + u32 sdram_bank_size = get_sdram_bank_size();
>  
>   for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
> - addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE);
> - gd->ram_size += get_ram_size((long *)addr, SDRAM_BANK_SIZE);
> + addr = CONFIG_SYS_SDRAM_BASE + (i * sdram_bank_size);
> + gd->ram_size += get_ram_size((long *)addr, sdram_bank_size);
>   }
>   return 0;
>  }
> @@ -110,10 +122,11 @@ void dram_init_banksize(void)
>  {
>   unsigned int i;
>   u32 addr, size;
> + u32 sdram_bank_size = get_sdram_bank_size();
>  
>   for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
> - addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE);
> - size = get_ram_size((long *)addr, SDRAM_BANK_SIZE);
> + addr = CONFIG_SYS_SDRAM_BASE + (i * sdram_bank_size);
> + size = get_ram_size((long *)addr, sdram_bank_size);
>  
>   gd->bd->bi_dram[i].start = addr;
>   gd->bd->bi_dram[i].size = size;
> diff --git a/board/samsung/odroid/odroid.c b/board/samsung/odroid/odroid.c
> index 32155f1..e98e3be 100644
> --- a/board/samsung/odroid/odroid.c
> +++ b/board/samsung/odroid/odroid.c
> @@ -30,6 +30,7 @@ DECLARE_GLOBAL_DATA_PTR;
>  enum {
>   ODROID_TYPE_U3,
>   ODROID_TYPE_X2,
> + ODROID_TYPE_X,
>   ODROID_TYPES,
>  };
>  
> @@ -56,15 +57,20 @@ void set_board_type(void)
>   sdelay(20);
>  
>   /* Check GPC1 pin2 - LED supplied by XCL205 - X2 only */
> - if (readl(XCL205_STATE_GPIO_DAT) & (1 << XCL205_STATE_GPIO_PIN))
> - gd->board_type = ODROID_TYPE_X2;
> - else
> + if (readl(XCL205_STATE_GPIO_DAT) & (1 << XCL205_STATE_GPIO_PIN)) {
> + /* Check the SoC product information ID */
> + if (readl(EXYNOS4_PRO_ID) == 0xE4412211)

you can use s5p_cpu_id and s5p_cpu_rev.

> + gd->board_type = ODROID_TYPE_X;
> + else
> + gd->board_type = ODROID_TYPE_X2;
> + } else {
>   gd->board_type = ODROID_TYPE_U3;
> + }
>  }
>  
>  const char *get_board_type(void)
>  {
> - const char *board_type[] = {"u3", "x2"};
> + const char *board_type[] = {"u3", "x2", "x"};
>  
>   return board_type[gd->board_type];
>  }
> diff --git a/include/configs/odroid.h b/include/configs/odroid.h

Re: [U-Boot] u-boot device model SPI + SPI Flash

[Hoefle Marco]

Maybe somebody has a valid u-boot dts file for a microblaze system with an SPI 
core? That would helpful.
We want to move from a parallel nor flash to a SPI flash for FPGA config, 
u-boot, Linux Kernel and rootfs.
The last missing part is u-boot. The kernel dts file is ok and the mtd 
partitions are set up correctly.


 
> > -Original Message-
> > From: Jagan Teki [mailto:jt...@openedev.com]
> > Sent: Mittwoch, 21. Oktober 2015 18:45
> > To: Hoefle Marco 
> > Cc: u-boot@lists.denx.de
> > Subject: Re: [U-Boot] u-boot device model SPI + SPI Flash
> >
> > On 21 October 2015 at 22:10, Hoefle Marco 
> > wrote:
> > > Hello Jagan,
> > > Thank you for your reply.
> > > Please find my comments bellow. I missed to mention that I am using
> > > mainline 2015.07
> > >
> > >
> > >> -Original Message-
> > >> From: Jagan Teki [mailto:jt...@openedev.com]
> > >> Sent: Mittwoch, 21. Oktober 2015 18:28
> > >> To: Hoefle Marco 
> > >> Cc: u-boot@lists.denx.de
> > >> Subject: Re: [U-Boot] u-boot device model SPI + SPI Flash
> > >>
> > >> On 21 October 2015 at 16:25, Hoefle Marco
> > >> 
> > >> wrote:
> > >> >
> > >> >  Hello,
> > >> > I saw that here is also a mailing list dedicated to device model
> > >> > issues but it
> > >> looks obsolete (last post February 2014) so I am using this forum.
> > >>
> > >> Please note its driver model - not a device model.
> > > Ok
> > >>
> > >> >
> > >> > I have a problem nearly identically to
> > >> > http://lists.denx.de/pipermail/u-boot/2015-April/210754.html
> > >> >
> > >> >
> > >> > The SPI initialization does not work:
> > >> >
> > >> > Invalid bus 0 (err=-19)
> > >> > *** Warning - spi_flash_probe() failed, using default environment
> > >>
> > >> Which board it is? dts file name?
> > > It is a custom dts file. It is for a Microblaze CPU in an Artix FPGA.
> > > The dts reflects that one below
> > >>
> > >> >
> > >> >
> > >> > This is the device tree compiled into u-boot:
> > >> >
> > >> > U-Boot> fdt addr 0x8FEB8A7C
> > >> > U-Boot> fdt print
> > >> > / {
> > >> > #address-cells = <0x0001>;
> > >> > #size-cells = <0x0001>;
> > >> > aliases {
> > >> > serial0 = "serial@4060";
> > >> > spi0 = "/axi_quad_spi@44a0";
> > >> > };
> > >> > memory {
> > >> > device_type = "memory";
> > >> > reg = <0x8000 0x1000>;
> > >> > };
> > >> > axi_quad_spi@44a0 {
> > >> > compatible = "xlnx,xps-spi-2.00.a";
> > >>
> > >> Do you need zynq spi or qspi driver there is no compatible string
> > >> with "xlnx,xps-spi-2.00.a" do know which source you're using?
> > > This driver is used:
> > > u-boot/drivers/spi/xilinx_spi.c
> >
> > In that case, use the compatible in your dts as below
> >
> > static const struct udevice_id xilinx_spi_ids[] = {
> > { .compatible = "xlnx,xilinx-spi" },
> > { }
> > };
> That was a copy paste failure, sorry for that. The reason was that in  the
> meanwhile I tried the original Xilinx driver from their github tree. They have
> the tag: compatible = "xlnx,xps-spi-2.00.a"
> 
> However, I changed back to have mainline code only an put a few printfs to
> it:
> U-Boot 2015.07--33711bdd4a4dce942fb5ae85a68899a8357bdd94---dirty (Oct
> 22 2015 - 07:57:35 +0200)
> 
> DRAM:  256 MiB
> uclass_find_device_by_seq: 0 -1
> uclass_find_device_by_seq: 0 0
>- -1 -1
>- not found
> env_relocate: 267
> spi_flash_probe: 410
> busnum: 0, cs: 0, max_hz: 5000
> spi_setup_slave: 336
> spi_get_bus_and_cs: 248
> uclass_find_device_by_seq: 0 0
>- -1 -1
>- not found
> uclass_find_device_by_seq: 1 0
>- -1 -1
>- not found
> Invalid bus 0 (err=-19)
> *** Warning - spi_flash_probe() failed, using default environment
> 
> 
> U-Boot> fdt addr 0x8FEB89FC
> U-Boot> fdt print
> / {
> #address-cells = <0x0001>;
> #size-cells = <0x0001>;
> aliases {
> serial0 = "/serial@4060";
> spi0 = "/axi_quad_spi@44a0";
> };
> memory {
> device_type = "memory";
> reg = <0x8000 0x1000>;
> };
> serial@4060 {
> clock-frequency = <0x05f5e100>;
> compatible = "xlnx,xps-uartlite-1.00.a";
> current-speed = <0x0001c200>;
> };
> axi_quad_spi@44a0 {
> compatible = "xlnx,xilinx-spi";
> reg = <0x44a0 0x0001>;
> spi-max-frequency = <0x423a35c7>;
> #address-cells = <0x0001>;
> #size-cells = <0x>;
> status = "okay";
> is-dual = <0x>;
> num-cs = <0x0001>;
> flash@0 {
> compatible = "n25q128a11";
>

Re: [U-Boot] [PATCH 3/5] splash_source: add support for filesystem formatted usb

[Nikita Kiryanov]

On Wed, Oct 21, 2015 at 04:01:46PM +0300, Igor Grinberg wrote:
> On 08/30/15 11:42, Nikita Kiryanov wrote:
> > Add support for loading splash image from USB drive formatted with a
> > filesystem.
> > 
> > Cc: Igor Grinberg 
> > Cc: Tom Rini 
> > Signed-off-by: Nikita Kiryanov 
> 
> [...]
> 
> > +#ifdef CONFIG_USB_STORAGE
> > +   if (location->storage == SPLASH_STORAGE_USB) {
> > +   usb_init();
> > +   usb_stor_scan(1);
> > +   }
> > +#endif
> 
> Can we use IS_ENABLED() stuff here instead?

IS_ENABLED() does not prevent compile errors, only closes off certain
code paths.

> 
> 
> -- 
> Regards,
> Igor.
> 
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Re: [U-Boot] [PATCH v2 2/3] gpt: add optional parameter type in gpt command

[Tom Rini]

On Wed, Oct 21, 2015 at 02:14:48PM +0200, Patrick Delaunay wrote:

> code under flag CONFIG_PARTITION_TYPE_GUID
> add parameter "type" to select partition type guid
> 
> example of use with gpt command :
> 
>   partitions = uuid_disk=${uuid_gpt_disk}; \
>   name=boot,size=0x6bc00,uuid=${uuid_gpt_boot}; \
>   name=root,size=0x7538ba00,uuid=${uuid_gpt_root}, \
>  type=0fc63daf-8483-4772-8e79-3d69d8477de4;
> 
>   gpt write mmc 0 $partitions
> 
> Signed-off-by: Patrick Delaunay 

Reviewed-by: Tom Rini 

But I want to echo Simon's comment that we should update the docs a bit,
perhaps a few more words and an example in doc/README.gpt.

-- 
Tom


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Re: [U-Boot] [PATCH v4 18/24] spi: cadence_qspi_apb: Use GENMASK

[Jagan Teki]

On 23 October 2015 at 02:55, Tom Rini  wrote:
> On Thu, Oct 22, 2015 at 07:10:17PM -0200, Fabio Estevam wrote:
>> On Thu, Oct 22, 2015 at 6:50 PM, Jagan Teki  wrote:
>>
>> > reg &= ~(CQSPI_REG_CONFIG_CHIPSELECT_MASK
>> > @@ -719,7 +719,7 @@ int cadence_qspi_apb_indirect_read_setup(struct 
>> > cadence_spi_platdata *plat,
>> >  #if defined(CONFIG_SPL_SPI_XIP) && defined(CONFIG_SPL_BUILD)
>> > writel(0x0, plat->regbase + CQSPI_REG_MODE_BIT);
>> >  #else
>> > -   writel(0xFF, plat->regbase + CQSPI_REG_MODE_BIT);
>> > +   writel(GENMASK(7, 0), plat->regbase + CQSPI_REG_MODE_BIT);
>>
>> Is the 0xFF really a mask here? It seems it is just writing 0xFF to
>> the register directly without any masking operation.

As register got initialized to all 1's like masking all to set may be
we can add a macro like MODE_BIT_MASK and then will assign GENMASK to
that.

>
> Indeed, with context on the #else side it looks like an old fashioned
> "clear everything with magic value" which I suppose might technically be
> the bitmask but it's not helping with clarity in this case.

-- 
Jagan | openedev.
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Re: [U-Boot] [PATCH 2/8] dm: pci: Avoid a driver model build error with CONFIG_CMD_PCI_ENUM

[Stephen Warren]

On 10/23/2015 09:47 AM, Simon Glass wrote:

Hi Stephen,

On 21 October 2015 at 14:16, Stephen Warren  wrote:

On 10/17/2015 11:49 AM, Simon Glass wrote:


This is not supported with driver model, so print a message instead of
generating a build error. Rescanning PCI is not yet implemented.




diff --git a/common/cmd_pci.c b/common/cmd_pci.c




@@ -457,7 +457,11 @@ static int do_pci(cmd_tbl_t *cmdtp, int flag, int
argc, char * const argv[])
 return pci_cfg_display(bdf, addr, size, value);
   #ifdef CONFIG_CMD_PCI_ENUM
 case 'e':
+# ifdef CONFIG_DM_PCI
+   printf("This command is not yet supported with driver
model\n");
+# else
 pci_init();
+# endif



That feature is enabled on most/all Tegra boards with PCI support. Hopefully
nobody will miss it; I guess I haven't used it so I don't object to this
change.

However, wouldn't it be better to remove CONFIG_CMD_PCI_ENUM from the config
header rather than leaving the command enabled yet non-functional? Or are
you planning on implementing this path in the near future?


I was looking for feedback on why anyone would use this option. It's
not clear to me what it is for.


I assume it's to support hot-pluggable PCI connectors? Or perhaps it's 
just useful during debug of PCI drivers?



We can implement it for driver model if it is needed.


I'd be happy disabling it in the configs myself. Thierry, you enabled 
the option when you first implemented the Tegra PCIe controller driver. 
Do you have a preference?

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[U-Boot] [PATCH V2 1/7] ARM: tegra: rename dummy XUSB padctl implementation

[Stephen Warren]

From: Stephen Warren 

A future patch will soon move some of the XUSB padctl code into a common
file in arch/arm/mach-tegra. Rename the existing dummy XUSB padctl file
to avoid conflicting with that, or being confusing.

Signed-off-by: Stephen Warren 
---
 arch/arm/mach-tegra/Makefile   | 2 +-
 arch/arm/mach-tegra/{xusb-padctl.c => xusb-padctl-dummy.c} | 0
 2 files changed, 1 insertion(+), 1 deletion(-)
 rename arch/arm/mach-tegra/{xusb-padctl.c => xusb-padctl-dummy.c} (100%)

diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index 98431a91f875..2be6ef41fff6 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -23,7 +23,7 @@ obj-y += clock.o
 obj-y += lowlevel_init.o
 obj-y += pinmux-common.o
 obj-y += powergate.o
-obj-y += xusb-padctl.o
+obj-y += xusb-padctl-dummy.o
 obj-$(CONFIG_DISPLAY_CPUINFO) += sys_info.o
 obj-$(CONFIG_TEGRA_GPU) += gpu.o
 obj-$(CONFIG_TEGRA_CLOCK_SCALING) += emc.o
diff --git a/arch/arm/mach-tegra/xusb-padctl.c 
b/arch/arm/mach-tegra/xusb-padctl-dummy.c
similarity index 100%
rename from arch/arm/mach-tegra/xusb-padctl.c
rename to arch/arm/mach-tegra/xusb-padctl-dummy.c
-- 
1.9.1

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Re: [U-Boot] [PATCH v4] Tegra: T210: Add QSPI driver

[Stephen Warren]

On 10/23/2015 10:08 AM, Tom Warren wrote:

This is the normal Tegra SPI driver modified to work with the
QSPI controller in Tegra210. It does not do 2x/4x transfers
or any other QSPI protocol.


Once the DT binding is reviewed as a Linux patch, then this patch,
Acked-by: Stephen Warren 

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Re: [U-Boot] [PATCH] net/eth: fix a bug in on_ethaddr()

[Joe Hershberger]

On Wed, Oct 21, 2015 at 5:07 AM, Hu Vincent  wrote:
> Hi Joe,
>
> Would you please kindly help to pick up this patch which fixed the issue when 
> using multiple Ethernet ports?

Yes, now that the merge window is open, I will be pulling in all
patches assigned to me in patchwork and testing.

-Joe
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[U-Boot] [PATCH] mtd: pxa3xx_nand: Correct allocation and init bug

[Kevin Smith]

Correct a null pointer dereference in board_nand_init().  Zeroed
memory was allocated, then immediately dereferenced, which is a
null dereference.  The dereference is completely removed, since
this pointer is later initialized in alloc_nand_resources.

The allocation size is reduced from what was introduced from the
Linux kernel, as U-boot uses the statically allocated nand_info
instead of needing to dynamically allocate an mtd_info instance.

Also, some pointer math was corrected in the initialization of
the nand_chip pointer.

Signed-off-by: Kevin Smith 
Cc: Stefan Roese 
Cc: Luka Perkov 
Cc: Scott Wood 
---
 drivers/mtd/nand/pxa3xx_nand.c | 17 +
 1 file changed, 5 insertions(+), 12 deletions(-)

diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c
index 1565a9a..e5ea5c2 100644
--- a/drivers/mtd/nand/pxa3xx_nand.c
+++ b/drivers/mtd/nand/pxa3xx_nand.c
@@ -1486,8 +1486,8 @@ static int alloc_nand_resource(struct pxa3xx_nand_info 
*info)
info->variant = pxa3xx_nand_get_variant();
for (cs = 0; cs < pdata->num_cs; cs++) {
mtd = _info[cs];
-   chip = (struct nand_chip *)info +
-   sizeof(struct pxa3xx_nand_host);
+   chip = (struct nand_chip *)
+   ((u8 *)[1] + sizeof(*host) * cs);
host = (struct pxa3xx_nand_host *)chip;
info->host[cs] = host;
host->mtd = mtd;
@@ -1600,19 +1600,12 @@ void board_nand_init(void)
struct pxa3xx_nand_host *host;
int ret;
 
-   info = kzalloc(sizeof(*info) + (sizeof(struct mtd_info) +
-   sizeof(*host)) *
-  CONFIG_SYS_MAX_NAND_DEVICE, GFP_KERNEL);
+   info = kzalloc(sizeof(*info) +
+   sizeof(*host) * CONFIG_SYS_MAX_NAND_DEVICE,
+   GFP_KERNEL);
if (!info)
return;
 
-   /*
-* If CONFIG_SYS_NAND_SELF_INIT is defined, each driver is responsible
-* for instantiating struct nand_chip, while drivers/mtd/nand/nand.c
-* still provides a "struct mtd_info nand_info" instance.
-*/
-   info->host[0]->mtd = _info[0];
-
ret = pxa3xx_nand_probe(info);
if (ret)
return;
-- 
2.4.6
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[U-Boot] [PATCH V2 7/7] ARM: tegra: error check Tegra210 XUSB padctl waits

[Stephen Warren]

From: Stephen Warren 

Add code to detect timeouts when waiting for HW events such as PLL
lock done. Any errors are logged and trigger an error return code.

Signed-off-by: Stephen Warren 
---
 arch/arm/mach-tegra/tegra210/xusb-padctl.c | 25 -
 1 file changed, 20 insertions(+), 5 deletions(-)

diff --git a/arch/arm/mach-tegra/tegra210/xusb-padctl.c 
b/arch/arm/mach-tegra/tegra210/xusb-padctl.c
index 6022f1614bda..9ec93e7c4c4c 100644
--- a/arch/arm/mach-tegra/tegra210/xusb-padctl.c
+++ b/arch/arm/mach-tegra/tegra210/xusb-padctl.c
@@ -279,7 +279,10 @@ static int pcie_phy_enable(struct tegra_xusb_phy *phy)
if (value & XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_DONE)
break;
}
-
+   if (!(value & XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_DONE)) {
+   debug("  timeout\n");
+   return -ETIMEDOUT;
+   }
debug("  done\n");
 
value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
@@ -295,7 +298,10 @@ static int pcie_phy_enable(struct tegra_xusb_phy *phy)
if ((value & XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_DONE) == 0)
break;
}
-
+   if (value & XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_DONE) {
+   debug("  timeout\n");
+   return -ETIMEDOUT;
+   }
debug("  done\n");
 
value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
@@ -310,7 +316,10 @@ static int pcie_phy_enable(struct tegra_xusb_phy *phy)
if (value & XUSB_PADCTL_UPHY_PLL_P0_CTL1_LOCKDET_STATUS)
break;
}
-
+   if (!(value & XUSB_PADCTL_UPHY_PLL_P0_CTL1_LOCKDET_STATUS)) {
+   debug("  timeout\n");
+   return -ETIMEDOUT;
+   }
debug("  done\n");
 
value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
@@ -326,7 +335,10 @@ static int pcie_phy_enable(struct tegra_xusb_phy *phy)
if (value & XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_DONE)
break;
}
-
+   if (!(value & XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_DONE)) {
+   debug("  timeout\n");
+   return -ETIMEDOUT;
+   }
debug("  done\n");
 
value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
@@ -341,7 +353,10 @@ static int pcie_phy_enable(struct tegra_xusb_phy *phy)
if ((value & XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_DONE) == 0)
break;
}
-
+   if (value & XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_DONE) {
+   debug("  timeout\n");
+   return -ETIMEDOUT;
+   }
debug("  done\n");
 
value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
-- 
1.9.1

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[U-Boot] [PATCH V2 6/7] ARM: tegra: add lane tables to Tegra210 XUSB padctl

[Stephen Warren]

From: Stephen Warren 

Add the tables defining which pads and mux options exist in the Tegra210
XUSB padctl hardware.

Signed-off-by: Stephen Warren 
---
 arch/arm/mach-tegra/tegra210/xusb-padctl.c | 78 --
 arch/arm/mach-tegra/xusb-padctl-common.h   |  4 +-
 2 files changed, 76 insertions(+), 6 deletions(-)

diff --git a/arch/arm/mach-tegra/tegra210/xusb-padctl.c 
b/arch/arm/mach-tegra/tegra210/xusb-padctl.c
index 503354344067..6022f1614bda 100644
--- a/arch/arm/mach-tegra/tegra210/xusb-padctl.c
+++ b/arch/arm/mach-tegra/tegra210/xusb-padctl.c
@@ -15,6 +15,76 @@
 
 #include 
 
+enum tegra210_function {
+   TEGRA210_FUNC_SNPS,
+   TEGRA210_FUNC_XUSB,
+   TEGRA210_FUNC_UART,
+   TEGRA210_FUNC_PCIE_X1,
+   TEGRA210_FUNC_PCIE_X4,
+   TEGRA210_FUNC_USB3,
+   TEGRA210_FUNC_SATA,
+   TEGRA210_FUNC_RSVD,
+};
+
+static const char *const tegra210_functions[] = {
+   "snps",
+   "xusb",
+   "uart",
+   "pcie-x1",
+   "pcie-x4",
+   "usb3",
+   "sata",
+   "rsvd",
+};
+
+static const unsigned int tegra210_otg_functions[] = {
+   TEGRA210_FUNC_SNPS,
+   TEGRA210_FUNC_XUSB,
+   TEGRA210_FUNC_UART,
+   TEGRA210_FUNC_RSVD,
+};
+
+static const unsigned int tegra210_usb_functions[] = {
+   TEGRA210_FUNC_SNPS,
+   TEGRA210_FUNC_XUSB,
+};
+
+static const unsigned int tegra210_pci_functions[] = {
+   TEGRA210_FUNC_PCIE_X1,
+   TEGRA210_FUNC_USB3,
+   TEGRA210_FUNC_SATA,
+   TEGRA210_FUNC_PCIE_X4,
+};
+
+#define TEGRA210_LANE(_name, _offset, _shift, _mask, _iddq, _funcs)\
+   {   \
+   .name = _name,  \
+   .offset = _offset,  \
+   .shift = _shift,\
+   .mask = _mask,  \
+   .iddq = _iddq,  \
+   .num_funcs = ARRAY_SIZE(tegra210_##_funcs##_functions), \
+   .funcs = tegra210_##_funcs##_functions, \
+   }
+
+static const struct tegra_xusb_padctl_lane tegra210_lanes[] = {
+   TEGRA210_LANE("otg-0", 0x004,  0, 0x3, 0, otg),
+   TEGRA210_LANE("otg-1", 0x004,  2, 0x3, 0, otg),
+   TEGRA210_LANE("otg-2", 0x004,  4, 0x3, 0, otg),
+   TEGRA210_LANE("otg-3", 0x004,  6, 0x3, 0, otg),
+   TEGRA210_LANE("usb2-bias", 0x004, 18, 0x3, 0, otg),
+   TEGRA210_LANE("hsic-0",0x004, 14, 0x1, 0, usb),
+   TEGRA210_LANE("hsic-1",0x004, 15, 0x1, 0, usb),
+   TEGRA210_LANE("pcie-0",0x028, 12, 0x3, 1, pci),
+   TEGRA210_LANE("pcie-1",0x028, 14, 0x3, 2, pci),
+   TEGRA210_LANE("pcie-2",0x028, 16, 0x3, 3, pci),
+   TEGRA210_LANE("pcie-3",0x028, 18, 0x3, 4, pci),
+   TEGRA210_LANE("pcie-4",0x028, 20, 0x3, 5, pci),
+   TEGRA210_LANE("pcie-5",0x028, 22, 0x3, 6, pci),
+   TEGRA210_LANE("pcie-6",0x028, 24, 0x3, 7, pci),
+   TEGRA210_LANE("sata-0",0x028, 30, 0x3, 8, pci),
+};
+
 #define XUSB_PADCTL_ELPG_PROGRAM 0x024
 #define  XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN (1 << 31)
 #define  XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY (1 << 30)
@@ -328,10 +398,10 @@ static struct tegra_xusb_phy tegra210_phys[] = {
 };
 
 static const struct tegra_xusb_padctl_soc tegra210_socdata = {
-   .lanes = NULL,
-   .num_lanes = 0,
-   .functions = NULL,
-   .num_functions = 0,
+   .lanes = tegra210_lanes,
+   .num_lanes = ARRAY_SIZE(tegra210_lanes),
+   .functions = tegra210_functions,
+   .num_functions = ARRAY_SIZE(tegra210_functions),
.phys = tegra210_phys,
.num_phys = ARRAY_SIZE(tegra210_phys),
 };
diff --git a/arch/arm/mach-tegra/xusb-padctl-common.h 
b/arch/arm/mach-tegra/xusb-padctl-common.h
index 11ecb99b749d..f44790a65004 100644
--- a/arch/arm/mach-tegra/xusb-padctl-common.h
+++ b/arch/arm/mach-tegra/xusb-padctl-common.h
@@ -45,8 +45,8 @@ struct tegra_xusb_padctl_pin {
int iddq;
 };
 
-#define MAX_GROUPS 3
-#define MAX_PINS 6
+#define MAX_GROUPS 5
+#define MAX_PINS 7
 
 struct tegra_xusb_padctl_group {
const char *name;
-- 
1.9.1

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Re: [U-Boot] [PATCH v2 1/3] part:efi: add GUID for linux file system data

[Tom Rini]

On Wed, Oct 21, 2015 at 02:14:47PM +0200, Patrick Delaunay wrote:

> Previously, Linux used the same GUID for the data partitions as Windows
> (Basic data partition: EBD0A0A2-B9E5-4433-87C0-68B6B72699C7).
> This created problems when dual-booting Linux and Windows in UEFI-GPT
> Setup, so a new GUID (Linux filesystem data:
> 0FC63DAF-8483-4772-8E79-3D69D8477DE4) was defined jointly by GPT fdisk
> and GNU Parted developers.
> 
> Signed-off-by: Patrick Delaunay 

Reviewed-by: Tom Rini 

-- 
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[U-Boot] [PATCH V2 4/7] ARM: tegra: parameterize common XUSB code

[Stephen Warren]

From: Stephen Warren 

There are some differences between the Tegra124 and Tegra210 XUSB padctl
code. So far, the common XUSB padctl code only supports Tegra124. Add
some parameters etc. so that it can work for both chips.

This also allows moving Tegra124's process_nodes() into the common file;
something that would have requires edits during the move if done in the
previous commit.

Signed-off-by: Stephen Warren 
---
 arch/arm/mach-tegra/tegra124/xusb-padctl.c | 84 +++---
 arch/arm/mach-tegra/xusb-padctl-common.h   | 32 ++--
 2 files changed, 34 insertions(+), 82 deletions(-)

diff --git a/arch/arm/mach-tegra/tegra124/xusb-padctl.c 
b/arch/arm/mach-tegra/tegra124/xusb-padctl.c
index b3715d8f47bc..76af924b948d 100644
--- a/arch/arm/mach-tegra/tegra124/xusb-padctl.c
+++ b/arch/arm/mach-tegra/tegra124/xusb-padctl.c
@@ -8,16 +8,9 @@
 
 #include 
 #include 
-#include 
-#include 
 
 #include "../xusb-padctl-common.h"
 
-#include 
-
-#include 
-#include 
-
 #include 
 
 #define XUSB_PADCTL_ELPG_PROGRAM 0x01c
@@ -302,66 +295,27 @@ static const struct tegra_xusb_phy_ops sata_phy_ops = {
.unprepare = phy_unprepare,
 };
 
-struct tegra_xusb_padctl *padctl = &(struct tegra_xusb_padctl) {
-   .phys = {
-   [0] = {
-   .ops = _phy_ops,
-   },
-   [1] = {
-   .ops = _phy_ops,
-   },
+static struct tegra_xusb_phy tegra124_phys[] = {
+   {
+   .type = TEGRA_XUSB_PADCTL_PCIE,
+   .ops = _phy_ops,
+   .padctl = ,
+   },
+   {
+   .type = TEGRA_XUSB_PADCTL_SATA,
+   .ops = _phy_ops,
+   .padctl = ,
},
 };
 
-int process_nodes(const void *fdt, int nodes[], unsigned int count)
-{
-   unsigned int i;
-
-   for (i = 0; i < count; i++) {
-   enum fdt_compat_id id;
-   int err;
-
-   if (!fdtdec_get_is_enabled(fdt, nodes[i]))
-   continue;
-
-   id = fdtdec_lookup(fdt, nodes[i]);
-   switch (id) {
-   case COMPAT_NVIDIA_TEGRA124_XUSB_PADCTL:
-   break;
-
-   default:
-   error("unsupported compatible: %s",
- fdtdec_get_compatible(id));
-   continue;
-   }
-
-   padctl->num_lanes = ARRAY_SIZE(tegra124_lanes);
-   padctl->lanes = tegra124_lanes;
-
-   padctl->num_functions = ARRAY_SIZE(tegra124_functions);
-   padctl->functions = tegra124_functions;
-
-   err = tegra_xusb_padctl_parse_dt(padctl, fdt, nodes[i]);
-   if (err < 0) {
-   error("failed to parse DT: %d", err);
-   continue;
-   }
-
-   /* deassert XUSB padctl reset */
-   reset_set_enable(PERIPH_ID_XUSB_PADCTL, 0);
-
-   err = tegra_xusb_padctl_config_apply(padctl, >config);
-   if (err < 0) {
-   error("failed to apply pinmux: %d", err);
-   continue;
-   }
-
-   /* only a single instance is supported */
-   break;
-   }
-
-   return 0;
-}
+static const struct tegra_xusb_padctl_soc tegra124_socdata = {
+   .lanes = tegra124_lanes,
+   .num_lanes = ARRAY_SIZE(tegra124_lanes),
+   .functions = tegra124_functions,
+   .num_functions = ARRAY_SIZE(tegra124_functions),
+   .phys = tegra124_phys,
+   .num_phys = ARRAY_SIZE(tegra124_phys),
+};
 
 void tegra_xusb_padctl_init(const void *fdt)
 {
@@ -370,6 +324,6 @@ void tegra_xusb_padctl_init(const void *fdt)
count = fdtdec_find_aliases_for_id(fdt, "padctl",
   COMPAT_NVIDIA_TEGRA124_XUSB_PADCTL,
   nodes, ARRAY_SIZE(nodes));
-   if (process_nodes(fdt, nodes, count))
+   if (tegra_xusb_process_nodes(fdt, nodes, count, _socdata))
return;
 }
diff --git a/arch/arm/mach-tegra/xusb-padctl-common.h 
b/arch/arm/mach-tegra/xusb-padctl-common.h
index a65b754f6b7d..11ecb99b749d 100644
--- a/arch/arm/mach-tegra/xusb-padctl-common.h
+++ b/arch/arm/mach-tegra/xusb-padctl-common.h
@@ -33,8 +33,8 @@ struct tegra_xusb_phy_ops {
 };
 
 struct tegra_xusb_phy {
+   unsigned int type;
const struct tegra_xusb_phy_ops *ops;
-
struct tegra_xusb_padctl *padctl;
 };
 
@@ -58,6 +58,15 @@ struct tegra_xusb_padctl_group {
int iddq;
 };
 
+struct tegra_xusb_padctl_soc {
+   const struct tegra_xusb_padctl_lane *lanes;
+   unsigned int num_lanes;
+   const char *const *functions;
+   unsigned int num_functions;
+   struct tegra_xusb_phy *phys;
+   unsigned int num_phys;
+};
+
 struct tegra_xusb_padctl_config {
const char *name;
 
@@ -66,20 +75,13 @@ 

[U-Boot] [PATCH V2 2/7] ARM: tegra: clean up XUSB padctl error() calls

[Stephen Warren]

From: Stephen Warren 

This file defines pr_fmt(), so the individual error() calls don't need to
include the prefix in their format strings. Doing so results in duplicate
text in any error messages. Remove the duplication.

Signed-off-by: Stephen Warren 
---
v2: New patch.
---
 arch/arm/mach-tegra/tegra124/xusb-padctl.c | 33 +-
 1 file changed, 14 insertions(+), 19 deletions(-)

diff --git a/arch/arm/mach-tegra/tegra124/xusb-padctl.c 
b/arch/arm/mach-tegra/tegra124/xusb-padctl.c
index 43af883f2c12..ce857b8b05e9 100644
--- a/arch/arm/mach-tegra/tegra124/xusb-padctl.c
+++ b/arch/arm/mach-tegra/tegra124/xusb-padctl.c
@@ -220,7 +220,7 @@ static int tegra_xusb_padctl_disable(struct 
tegra_xusb_padctl *padctl)
u32 value;
 
if (padctl->enable == 0) {
-   error("tegra-xusb-padctl: unbalanced enable/disable");
+   error("unbalanced enable/disable");
return 0;
}
 
@@ -415,7 +415,7 @@ tegra_xusb_padctl_group_parse_dt(struct tegra_xusb_padctl 
*padctl,
 
len = fdt_count_strings(fdt, node, "nvidia,lanes");
if (len < 0) {
-   error("tegra-xusb-padctl: failed to parse \"nvidia,lanes\" 
property");
+   error("failed to parse \"nvidia,lanes\" property");
return -EINVAL;
}
 
@@ -425,7 +425,7 @@ tegra_xusb_padctl_group_parse_dt(struct tegra_xusb_padctl 
*padctl,
err = fdt_get_string_index(fdt, node, "nvidia,lanes", i,
   >pins[i]);
if (err < 0) {
-   error("tegra-xusb-padctl: failed to read string from 
\"nvidia,lanes\" property");
+   error("failed to read string from \"nvidia,lanes\" 
property");
return -EINVAL;
}
}
@@ -434,7 +434,7 @@ tegra_xusb_padctl_group_parse_dt(struct tegra_xusb_padctl 
*padctl,
 
err = fdt_get_string(fdt, node, "nvidia,function", >func);
if (err < 0) {
-   error("tegra-xusb-padctl: failed to parse \"nvidia,func\" 
property");
+   error("failed to parse \"nvidia,func\" property");
return -EINVAL;
}
 
@@ -487,15 +487,14 @@ tegra_xusb_padctl_group_apply(struct tegra_xusb_padctl 
*padctl,
 
lane = tegra_xusb_padctl_find_lane(padctl, group->pins[i]);
if (!lane) {
-   error("tegra-xusb-padctl: no lane for pin %s",
- group->pins[i]);
+   error("no lane for pin %s", group->pins[i]);
continue;
}
 
func = tegra_xusb_padctl_lane_find_function(padctl, lane,
group->func);
if (func < 0) {
-   error("tegra-xusb-padctl: function %s invalid for lane 
%s: %d",
+   error("function %s invalid for lane %s: %d",
  group->func, lane->name, func);
continue;
}
@@ -537,8 +536,7 @@ tegra_xusb_padctl_config_apply(struct tegra_xusb_padctl 
*padctl,
 
err = tegra_xusb_padctl_group_apply(padctl, group);
if (err < 0) {
-   error("tegra-xusb-padctl: failed to apply group %s: %d",
- group->name, err);
+   error("failed to apply group %s: %d", group->name, err);
continue;
}
}
@@ -564,8 +562,7 @@ tegra_xusb_padctl_config_parse_dt(struct tegra_xusb_padctl 
*padctl,
err = tegra_xusb_padctl_group_parse_dt(padctl, group, fdt,
   subnode);
if (err < 0) {
-   error("tegra-xusb-padctl: failed to parse group %s",
- group->name);
+   error("failed to parse group %s", group->name);
return err;
}
 
@@ -582,7 +579,7 @@ static int tegra_xusb_padctl_parse_dt(struct 
tegra_xusb_padctl *padctl,
 
err = fdt_get_resource(fdt, node, "reg", 0, >regs);
if (err < 0) {
-   error("tegra-xusb-padctl: registers not found");
+   error("registers not found");
return err;
}
 
@@ -592,8 +589,8 @@ static int tegra_xusb_padctl_parse_dt(struct 
tegra_xusb_padctl *padctl,
err = tegra_xusb_padctl_config_parse_dt(padctl, config, fdt,
subnode);
if (err < 0) {
-   error("tegra-xusb-padctl: failed to parse entry %s: %d",
- config->name, err);
+   error("failed to parse entry %s: %d", config->name,
+ err);
continue;
   

[U-Boot] [PATCH] env_ubi.c: Correct pointer error in env load

[Kevin Smith]

The variable "buf" in this function is a char array, and the
function ubi_volume_read is expecting a char *.  In the call, the
address of the pointer is being taken, incorrectly passing a
char **.  The compiler warning was being silenced by the cast.
Remove the address operator and the cast.

Signed-off-by: Kevin Smith 
Cc: Joe Hershberger 
Cc: Tom Rini 
---
 common/env_ubi.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/common/env_ubi.c b/common/env_ubi.c
index e0dc5af..e611199 100644
--- a/common/env_ubi.c
+++ b/common/env_ubi.c
@@ -181,8 +181,7 @@ void env_relocate_spec(void)
return;
}
 
-   if (ubi_volume_read(CONFIG_ENV_UBI_VOLUME, (void *),
-   CONFIG_ENV_SIZE)) {
+   if (ubi_volume_read(CONFIG_ENV_UBI_VOLUME, buf, CONFIG_ENV_SIZE)) {
printf("\n** Unable to read env from %s:%s **\n",
   CONFIG_ENV_UBI_PART, CONFIG_ENV_UBI_VOLUME);
set_default_env(NULL);
-- 
2.4.6
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Re: [U-Boot] [PATCH] spi: Tegra: add device tree binding doc for SPI and QSPI

[Tom Warren]

Stephen,

> -Original Message-
> From: Stephen Warren [mailto:swar...@wwwdotorg.org]
> Sent: Friday, October 23, 2015 10:26 AM
> To: Tom Warren 
> Cc: u-boot@lists.denx.de; jt...@openedev.com; Stephen Warren
> ; tomcwarren3...@gmail.com
> Subject: Re: [U-Boot] [PATCH] spi: Tegra: add device tree binding doc for SPI
> and QSPI
> 
> On 10/23/2015 11:11 AM, Tom Warren wrote:
> > This patch adds the device tree binding doc for the Tegra114 SPI
> > controller and the Tegra210 QSPI controller.
> 
> Initially, this should be sent as a Linux kernel patch, since the kernel 
> currently
> holds the definitive repository for DT bindings.
> 
> The binding should be based on the Tegra SPI binding present there, not on the
> non-standard binding for Tegra114 SPI that's evidently in the U-Boot tree.
This is a copy of the 'nvidia,tegra114-spi.txt' binding in the kernel 
(Documentation/devicetree/bindings/spi/). I removed the dma and reset fields, 
since they aren't required (or used) in U-Boot. I then added QSPI for T210, and 
named the file spi-tegra.txt. There wasn't a U-Boot SPI binding doc in U-Boot 
to start with.

> 
> That would imply sending the patch to the people/lists listed in the following
> Linux kernel MAINTAINERS entry for DT bindings, plus at least the Tegra
> mailing list and maintainers too:
> 
> OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS
> M:  Rob Herring 
> M:  Pawel Moll 
> M:  Mark Rutland 
> M:  Ian Campbell 
> M:  Kumar Gala 
> L:  devicet...@vger.kernel.org
Since this is basically a copy of a kernel binding doc, I didn't know that was 
necessary. Is that policy for U-Boot binding docs? Jagan - you have a few of 
these in the SPI bindings - did you have them reviewed by kernel/DT folk first?

Regardless, I'll resend with those people/lists in CC. Which Tegra 
ML/maintainers did you also want in there? 

> 
> > diff --git a/doc/device-tree-bindings/spi/spi-tegra.txt
> > b/doc/device-tree-bindings/spi/spi-tegra.txt
> > new file mode 100644
> > index 000..e215efe
> > --- /dev/null
> > +++ b/doc/device-tree-bindings/spi/spi-tegra.txt
> > @@ -0,0 +1,47 @@
> > +NVIDIA Tegra114 SPI controller.
> 
> Isn't this intended to be a binding for the QSPI controller?
Since there was no SPI binding, I included the Tegra114 SPI binding here. Note 
that other QSPI bindings exist here, for instance spi-cadence.txt. If you'd 
like two separate binding docs, I can do that, but this seemed more efficient.

> 
> > +Required properties:
> > +- compatible : should be "nvidia,tegra114-spi".
> 
> This should be "qspi" not "spi", assuming the HW really is different.
> This is a separate HW module, right?
Again, this is for the SPI controller, not QSPI. QSPI binding follows @ line 25 
below.

> 
> > +- reg: Should contain SPI registers location and length.
> > +- interrupts: Should contain SPI interrupts.
> > +- clocks : Should contain an entry for SPI clock.
> 
> Reset- and DMA-related properties are missing here.
> 
> You could mark the DMA properties optional, and leave it up to drivers to
> support PIO mode if the DMA properties are missing.
Will do.

> 
> > +Recommended properties:
> > +- spi-max-frequency: Definition as per
> > + doc/device-tree-bindings/spi/spi-bus.txt
> 
> That should use a relative path ("spi-bus.txt"), so that the same text applies
> irrespective of whether the file is contained within the Linux kernel or 
> U-Boot
> source trees.
Linux binding uses an absolute path 
(Documentation/devicetree/bindings/spi/spi-bus.txt), so I copied their usage to 
point to our spi-bus.txt. I can change to a relative path.

> 
> > +NVIDIA Tegra210 QSPI controller.
> 
> The binding for Tegra114 and Tegra210 should be (and appears to be)
> identical. There's no need to duplicate the text. Instead, simply say 
> something
> like the following for the compatible value in the one copy of the text:
> 
> - compatible : should be one of the following:
>   "nvidia,tegra114-qspi" (for Tegra114)
>   "nvidia,tegra210-qspi" (for Tegra210)
> 
Will do.

> However, if a driver that supports Tegra114 could operate correctly on
> Tegra210 without knowledge that it was running on different HW, the following
> compatible values area appropriate:
> 
> - compatible : should be one of the following:
>"nvidia,tegra114-qspi" (for Tegra114)
>"nvidia,tegra210-qspi", "nvidia,tegra114-qspi" (for Tegra210)

Thanks,

Tom
--
nvpublic
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[U-Boot] [PATCH V2 3/7] ARM: tegra: create common XUSB padctl driver file

[Stephen Warren]

From: Stephen Warren 

A fair amount of the XUSB padctl driver will be common between Tegra124
and Tegra210. To avoid cut/paste between the two chips, create a new
file that will contain the common code, and convert the Tegra124 code to
use it. This change doesn't move every last piece of code that can/will be
shared, but rather concentrates on moving code that can be moved with zero
changes, so there are no other diffs mixed in.

Signed-off-by: Stephen Warren 
---
v2: Fixed duplicate error() message prefixes.
---
 arch/arm/mach-tegra/tegra124/Makefile  |   1 +
 arch/arm/mach-tegra/tegra124/xusb-padctl.c | 346 +
 arch/arm/mach-tegra/xusb-padctl-common.c   | 305 +
 arch/arm/mach-tegra/xusb-padctl-common.h   | 103 +
 4 files changed, 414 insertions(+), 341 deletions(-)
 create mode 100644 arch/arm/mach-tegra/xusb-padctl-common.c
 create mode 100644 arch/arm/mach-tegra/xusb-padctl-common.h

diff --git a/arch/arm/mach-tegra/tegra124/Makefile 
b/arch/arm/mach-tegra/tegra124/Makefile
index f577f459be0f..c00de6151e2d 100644
--- a/arch/arm/mach-tegra/tegra124/Makefile
+++ b/arch/arm/mach-tegra/tegra124/Makefile
@@ -11,6 +11,7 @@ obj-y += clock.o
 obj-y  += funcmux.o
 obj-y  += pinmux.o
 obj-y  += xusb-padctl.o
+obj-y  += ../xusb-padctl-common.o
 
 ifndef CONFIG_SPL_BUILD
 obj-$(CONFIG_ARMV7_NONSEC) += psci.o
diff --git a/arch/arm/mach-tegra/tegra124/xusb-padctl.c 
b/arch/arm/mach-tegra/tegra124/xusb-padctl.c
index ce857b8b05e9..b3715d8f47bc 100644
--- a/arch/arm/mach-tegra/tegra124/xusb-padctl.c
+++ b/arch/arm/mach-tegra/tegra124/xusb-padctl.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2014-2015, NVIDIA CORPORATION.  All rights reserved.
  *
  * SPDX-License-Identifier: GPL-2.0
  */
@@ -11,6 +11,8 @@
 #include 
 #include 
 
+#include "../xusb-padctl-common.h"
+
 #include 
 
 #include 
@@ -83,18 +85,6 @@ static const unsigned int tegra124_pci_functions[] = {
TEGRA124_FUNC_RSVD,
 };
 
-struct tegra_xusb_padctl_lane {
-   const char *name;
-
-   unsigned int offset;
-   unsigned int shift;
-   unsigned int mask;
-   unsigned int iddq;
-
-   const unsigned int *funcs;
-   unsigned int num_funcs;
-};
-
 #define TEGRA124_LANE(_name, _offset, _shift, _mask, _iddq, _funcs)\
{   \
.name = _name,  \
@@ -121,74 +111,6 @@ static const struct tegra_xusb_padctl_lane 
tegra124_lanes[] = {
TEGRA124_LANE("sata-0", 0x134, 26, 0x3, 6, pci),
 };
 
-struct tegra_xusb_phy_ops {
-   int (*prepare)(struct tegra_xusb_phy *phy);
-   int (*enable)(struct tegra_xusb_phy *phy);
-   int (*disable)(struct tegra_xusb_phy *phy);
-   int (*unprepare)(struct tegra_xusb_phy *phy);
-};
-
-struct tegra_xusb_phy {
-   const struct tegra_xusb_phy_ops *ops;
-
-   struct tegra_xusb_padctl *padctl;
-};
-
-struct tegra_xusb_padctl_pin {
-   const struct tegra_xusb_padctl_lane *lane;
-
-   unsigned int func;
-   int iddq;
-};
-
-#define MAX_GROUPS 3
-#define MAX_PINS 6
-
-struct tegra_xusb_padctl_group {
-   const char *name;
-
-   const char *pins[MAX_PINS];
-   unsigned int num_pins;
-
-   const char *func;
-   int iddq;
-};
-
-struct tegra_xusb_padctl_config {
-   const char *name;
-
-   struct tegra_xusb_padctl_group groups[MAX_GROUPS];
-   unsigned int num_groups;
-};
-
-struct tegra_xusb_padctl {
-   struct fdt_resource regs;
-
-   unsigned int enable;
-
-   struct tegra_xusb_phy phys[2];
-
-   const struct tegra_xusb_padctl_lane *lanes;
-   unsigned int num_lanes;
-
-   const char *const *functions;
-   unsigned int num_functions;
-
-   struct tegra_xusb_padctl_config config;
-};
-
-static inline u32 padctl_readl(struct tegra_xusb_padctl *padctl,
-  unsigned long offset)
-{
-   return readl(padctl->regs.start + offset);
-}
-
-static inline void padctl_writel(struct tegra_xusb_padctl *padctl,
-u32 value, unsigned long offset)
-{
-   writel(value, padctl->regs.start + offset);
-}
-
 static int tegra_xusb_padctl_enable(struct tegra_xusb_padctl *padctl)
 {
u32 value;
@@ -380,7 +302,7 @@ static const struct tegra_xusb_phy_ops sata_phy_ops = {
.unprepare = phy_unprepare,
 };
 
-static struct tegra_xusb_padctl *padctl = &(struct tegra_xusb_padctl) {
+struct tegra_xusb_padctl *padctl = &(struct tegra_xusb_padctl) {
.phys = {
[0] = {
.ops = _phy_ops,
@@ -391,214 +313,7 @@ static struct tegra_xusb_padctl *padctl = &(struct 
tegra_xusb_padctl) {
},
 };
 
-static const struct tegra_xusb_padctl_lane *
-tegra_xusb_padctl_find_lane(struct tegra_xusb_padctl *padctl, const char *name)
-{
-   

[U-Boot] [PATCH V2 5/7] ARM: tegra: switch Tegra210 to common XUSB padctl

[Stephen Warren]

From: Stephen Warren 

This change simply deletes code from the Tegra210 XUSB padctl driver that
is already present in the common XUSB padctl code. Since all the arrays
in tegra210_socdata are empty, this update may leave the Tegra210 XUSB
padctl driver non-functional at run-time. However, (a) this driver is not
used yet so no regression can be observed and (b) the next commit will
immediately fix this up.

Signed-off-by: Stephen Warren 
---
 arch/arm/mach-tegra/tegra210/Makefile  |   1 +
 arch/arm/mach-tegra/tegra210/xusb-padctl.c | 173 +++--
 2 files changed, 16 insertions(+), 158 deletions(-)

diff --git a/arch/arm/mach-tegra/tegra210/Makefile 
b/arch/arm/mach-tegra/tegra210/Makefile
index 1fb8d1ac7483..b6012fc7baac 100644
--- a/arch/arm/mach-tegra/tegra210/Makefile
+++ b/arch/arm/mach-tegra/tegra210/Makefile
@@ -9,3 +9,4 @@ obj-y   += clock.o
 obj-y  += funcmux.o
 obj-y  += pinmux.o
 obj-y  += xusb-padctl.o
+obj-y  += ../xusb-padctl-common.o
diff --git a/arch/arm/mach-tegra/tegra210/xusb-padctl.c 
b/arch/arm/mach-tegra/tegra210/xusb-padctl.c
index 3c10a96aa396..503354344067 100644
--- a/arch/arm/mach-tegra/tegra210/xusb-padctl.c
+++ b/arch/arm/mach-tegra/tegra210/xusb-padctl.c
@@ -8,52 +8,13 @@
 
 #include 
 #include 
-#include 
-#include 
 
-#include 
+#include "../xusb-padctl-common.h"
 
 #include 
-#include 
 
 #include 
 
-struct tegra_xusb_phy_ops {
-   int (*prepare)(struct tegra_xusb_phy *phy);
-   int (*enable)(struct tegra_xusb_phy *phy);
-   int (*disable)(struct tegra_xusb_phy *phy);
-   int (*unprepare)(struct tegra_xusb_phy *phy);
-};
-
-struct tegra_xusb_phy {
-   const struct tegra_xusb_phy_ops *ops;
-
-   struct tegra_xusb_padctl *padctl;
-};
-
-struct tegra_xusb_padctl {
-   struct fdt_resource regs;
-
-   unsigned int enable;
-
-   struct tegra_xusb_phy phys[2];
-};
-
-static inline u32 padctl_readl(struct tegra_xusb_padctl *padctl,
-  unsigned long offset)
-{
-   u32 value = readl(padctl->regs.start + offset);
-   debug("padctl: %08lx > %08x\n", offset, value);
-   return value;
-}
-
-static inline void padctl_writel(struct tegra_xusb_padctl *padctl,
-u32 value, unsigned long offset)
-{
-   debug("padctl: %08lx < %08x\n", offset, value);
-   writel(value, padctl->regs.start + offset);
-}
-
 #define XUSB_PADCTL_ELPG_PROGRAM 0x024
 #define  XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN (1 << 31)
 #define  XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY (1 << 30)
@@ -358,120 +319,22 @@ static const struct tegra_xusb_phy_ops pcie_phy_ops = {
.unprepare = phy_unprepare,
 };
 
-static struct tegra_xusb_padctl *padctl = &(struct tegra_xusb_padctl) {
-   .phys = {
-   [0] = {
-   .ops = _phy_ops,
-   },
+static struct tegra_xusb_phy tegra210_phys[] = {
+   {
+   .type = TEGRA_XUSB_PADCTL_PCIE,
+   .ops = _phy_ops,
+   .padctl = ,
},
 };
 
-static int tegra_xusb_padctl_parse_dt(struct tegra_xusb_padctl *padctl,
- const void *fdt, int node)
-{
-   int err;
-
-   err = fdt_get_resource(fdt, node, "reg", 0, >regs);
-   if (err < 0) {
-   error("registers not found");
-   return err;
-   }
-
-   debug("regs: %pa-%pa\n", >regs.start,
- >regs.end);
-
-   return 0;
-}
-
-static int process_nodes(const void *fdt, int nodes[], unsigned int count)
-{
-   unsigned int i;
-   int err;
-
-   debug("> %s(fdt=%p, nodes=%p, count=%u)\n", __func__, fdt, nodes,
- count);
-
-   for (i = 0; i < count; i++) {
-   enum fdt_compat_id id;
-
-   if (!fdtdec_get_is_enabled(fdt, nodes[i]))
-   continue;
-
-   id = fdtdec_lookup(fdt, nodes[i]);
-   switch (id) {
-   case COMPAT_NVIDIA_TEGRA124_XUSB_PADCTL:
-   case COMPAT_NVIDIA_TEGRA210_XUSB_PADCTL:
-   break;
-
-   default:
-   error("unsupported compatible: %s",
- fdtdec_get_compatible(id));
-   continue;
-   }
-
-   err = tegra_xusb_padctl_parse_dt(padctl, fdt, nodes[i]);
-   if (err < 0) {
-   error("failed to parse DT: %d",
- err);
-   continue;
-   }
-
-   /* deassert XUSB padctl reset */
-   reset_set_enable(PERIPH_ID_XUSB_PADCTL, 0);
-
-   /* only a single instance is supported */
-   break;
-   }
-
-   debug("< %s()\n", __func__);
-   return 0;
-}
-
-struct tegra_xusb_phy *tegra_xusb_phy_get(unsigned int type)
-{
-   struct tegra_xusb_phy *phy = NULL;
-
-   switch (type) {
-   

Re: [U-Boot] [PATCH v4 18/24] spi: cadence_qspi_apb: Use GENMASK

[Vikas MANOCHA]

Acked-by: vikas.mano...@st.com

Rgds,
Vikas

> -Original Message-
> From: Jagan Teki [mailto:jt...@openedev.com]
> Sent: Thursday, October 22, 2015 1:50 PM
> To: u-boot@lists.denx.de
> Cc: Jagan Teki; Stefan Roese; Vikas MANOCHA; Marek Vasut
> Subject: [PATCH v4 18/24] spi: cadence_qspi_apb: Use GENMASK
> 
> Replace numeric mask hexcodes with GENMASK macro in cadence_qspi_apb
> 
> Cc: Stefan Roese 
> Cc: Vikas Manocha 
> Cc: Marek Vasut 
> Signed-off-by: Jagan Teki 
> ---
>  drivers/spi/cadence_qspi_apb.c | 48 +--
> ---
>  1 file changed, 24 insertions(+), 24 deletions(-)
> 
> diff --git a/drivers/spi/cadence_qspi_apb.c
> b/drivers/spi/cadence_qspi_apb.c index 7786dd6..31e14ee 100644
> --- a/drivers/spi/cadence_qspi_apb.c
> +++ b/drivers/spi/cadence_qspi_apb.c
> @@ -44,7 +44,7 @@
>  #define CQSPI_INST_TYPE_QUAD (2)
> 
>  #define CQSPI_STIG_DATA_LEN_MAX  (8)
> -#define CQSPI_INDIRECTTRIGGER_ADDR_MASK  (0xF)
> +#define CQSPI_INDIRECTTRIGGER_ADDR_MASK
>   GENMASK(19, 0)
> 
>  #define CQSPI_DUMMY_CLKS_PER_BYTE(8)
>  #define CQSPI_DUMMY_BYTES_MAX(4)
> @@ -65,8 +65,8 @@
>  #define  CQSPI_REG_CONFIG_CHIPSELECT_LSB 10
>  #define  CQSPI_REG_CONFIG_BAUD_LSB   19
>  #define  CQSPI_REG_CONFIG_IDLE_LSB   31
> -#define  CQSPI_REG_CONFIG_CHIPSELECT_MASK0xF
> -#define  CQSPI_REG_CONFIG_BAUD_MASK  0xF
> +#define  CQSPI_REG_CONFIG_CHIPSELECT_MASKGENMASK(3,
> 0)
> +#define  CQSPI_REG_CONFIG_BAUD_MASK  GENMASK(3,
> 0)
> 
>  #define  CQSPI_REG_RD_INSTR  0x04
>  #define  CQSPI_REG_RD_INSTR_OPCODE_LSB   0
> @@ -75,10 +75,10 @@
>  #define  CQSPI_REG_RD_INSTR_TYPE_DATA_LSB16
>  #define  CQSPI_REG_RD_INSTR_MODE_EN_LSB  20
>  #define  CQSPI_REG_RD_INSTR_DUMMY_LSB24
> -#define  CQSPI_REG_RD_INSTR_TYPE_INSTR_MASK  0x3
> -#define  CQSPI_REG_RD_INSTR_TYPE_ADDR_MASK   0x3
> -#define  CQSPI_REG_RD_INSTR_TYPE_DATA_MASK   0x3
> -#define  CQSPI_REG_RD_INSTR_DUMMY_MASK   0x1F
> +#define  CQSPI_REG_RD_INSTR_TYPE_INSTR_MASK  GENMASK(1,
> 0)
> +#define  CQSPI_REG_RD_INSTR_TYPE_ADDR_MASK   GENMASK(1,
> 0)
> +#define  CQSPI_REG_RD_INSTR_TYPE_DATA_MASK   GENMASK(1,
> 0)
> +#define  CQSPI_REG_RD_INSTR_DUMMY_MASK
>   GENMASK(4, 0)
> 
>  #define  CQSPI_REG_WR_INSTR  0x08
>  #define  CQSPI_REG_WR_INSTR_OPCODE_LSB   0
> @@ -88,23 +88,23 @@
>  #define  CQSPI_REG_DELAY_TCHSH_LSB   8
>  #define  CQSPI_REG_DELAY_TSD2D_LSB   16
>  #define  CQSPI_REG_DELAY_TSHSL_LSB   24
> -#define  CQSPI_REG_DELAY_TSLCH_MASK  0xFF
> -#define  CQSPI_REG_DELAY_TCHSH_MASK  0xFF
> -#define  CQSPI_REG_DELAY_TSD2D_MASK  0xFF
> -#define  CQSPI_REG_DELAY_TSHSL_MASK  0xFF
> +#define  CQSPI_REG_DELAY_TSLCH_MASK  GENMASK(7,
> 0)
> +#define  CQSPI_REG_DELAY_TCHSH_MASK  GENMASK(7,
> 0)
> +#define  CQSPI_REG_DELAY_TSD2D_MASK  GENMASK(7,
> 0)
> +#define  CQSPI_REG_DELAY_TSHSL_MASK  GENMASK(7,
> 0)
> 
>  #define  CQSPI_READLCAPTURE  0x10
>  #define  CQSPI_READLCAPTURE_BYPASS_LSB   0
>  #define  CQSPI_READLCAPTURE_DELAY_LSB1
> -#define  CQSPI_READLCAPTURE_DELAY_MASK   0xF
> +#define  CQSPI_READLCAPTURE_DELAY_MASK   GENMASK(3,
> 0)
> 
>  #define  CQSPI_REG_SIZE  0x14
>  #define  CQSPI_REG_SIZE_ADDRESS_LSB  0
>  #define  CQSPI_REG_SIZE_PAGE_LSB 4
>  #define  CQSPI_REG_SIZE_BLOCK_LSB16
> -#define  CQSPI_REG_SIZE_ADDRESS_MASK 0xF
> -#define  CQSPI_REG_SIZE_PAGE_MASK0xFFF
> -#define  CQSPI_REG_SIZE_BLOCK_MASK   0x3F
> +#define  CQSPI_REG_SIZE_ADDRESS_MASK GENMASK(3,
> 0)
> +#define  CQSPI_REG_SIZE_PAGE_MASKGENMASK(11, 0)
> +#define  CQSPI_REG_SIZE_BLOCK_MASK   GENMASK(5,
> 0)
> 
>  #define  CQSPI_REG_SRAMPARTITION 0x18
>  #define  CQSPI_REG_INDIRECTTRIGGER   0x1C
> @@ -115,8 +115,8 @@
>  #define  CQSPI_REG_SDRAMLEVEL0x2C
>  #define  CQSPI_REG_SDRAMLEVEL_RD_LSB 0
>  #define  CQSPI_REG_SDRAMLEVEL_WR_LSB 16
> -#define  CQSPI_REG_SDRAMLEVEL_RD_MASK0x
> -#define  CQSPI_REG_SDRAMLEVEL_WR_MASK0x
> +#define  CQSPI_REG_SDRAMLEVEL_RD_MASK
>   GENMASK(15, 0)
> +#define  CQSPI_REG_SDRAMLEVEL_WR_MASK
>   GENMASK(15, 0)
> 
>  #define  

Re: [U-Boot] [PATCH] spi: Tegra: add device tree binding doc for SPI and QSPI

[Stephen Warren]

On 10/23/2015 11:11 AM, Tom Warren wrote:

This patch adds the device tree binding doc for the Tegra114
SPI controller and the Tegra210 QSPI controller.


Initially, this should be sent as a Linux kernel patch, since the kernel 
currently holds the definitive repository for DT bindings.


The binding should be based on the Tegra SPI binding present there, not 
on the non-standard binding for Tegra114 SPI that's evidently in the 
U-Boot tree.


That would imply sending the patch to the people/lists listed in the 
following Linux kernel MAINTAINERS entry for DT bindings, plus at least 
the Tegra mailing list and maintainers too:


OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS
M:  Rob Herring 
M:  Pawel Moll 
M:  Mark Rutland 
M:  Ian Campbell 
M:  Kumar Gala 
L:  devicet...@vger.kernel.org


diff --git a/doc/device-tree-bindings/spi/spi-tegra.txt 
b/doc/device-tree-bindings/spi/spi-tegra.txt
new file mode 100644
index 000..e215efe
--- /dev/null
+++ b/doc/device-tree-bindings/spi/spi-tegra.txt
@@ -0,0 +1,47 @@
+NVIDIA Tegra114 SPI controller.


Isn't this intended to be a binding for the QSPI controller?


+Required properties:
+- compatible : should be "nvidia,tegra114-spi".


This should be "qspi" not "spi", assuming the HW really is different. 
This is a separate HW module, right?



+- reg: Should contain SPI registers location and length.
+- interrupts: Should contain SPI interrupts.
+- clocks : Should contain an entry for SPI clock.


Reset- and DMA-related properties are missing here.

You could mark the DMA properties optional, and leave it up to drivers 
to support PIO mode if the DMA properties are missing.



+Recommended properties:
+- spi-max-frequency: Definition as per
+ doc/device-tree-bindings/spi/spi-bus.txt


That should use a relative path ("spi-bus.txt"), so that the same text 
applies irrespective of whether the file is contained within the Linux 
kernel or U-Boot source trees.



+NVIDIA Tegra210 QSPI controller.


The binding for Tegra114 and Tegra210 should be (and appears to be) 
identical. There's no need to duplicate the text. Instead, simply say 
something like the following for the compatible value in the one copy of 
the text:


- compatible : should be one of the following:
 "nvidia,tegra114-qspi" (for Tegra114)
 "nvidia,tegra210-qspi" (for Tegra210)

However, if a driver that supports Tegra114 could operate correctly on 
Tegra210 without knowledge that it was running on different HW, the 
following compatible values area appropriate:


- compatible : should be one of the following:
  "nvidia,tegra114-qspi" (for Tegra114)
  "nvidia,tegra210-qspi", "nvidia,tegra114-qspi" (for Tegra210)
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[U-Boot] [PATCH 0/3] arm: mvebu: a38x: Cleanup serdes/DDR training

[Kevin Smith]

The a38x serdes init and DDR training code was imported more or less as-is from
Marvell's code with formatting cleanup changes.  This is a first pass at
cleaning up the code itself.

The topology data for several boards that are not supported by mainline U-Boot
are removed.  Also removed is a mechanism in the drivers themselves for
changing the board-specified configuration based on values loaded from an
on-board EEPROM.  This belongs in the board file instead of the driver, and is
not needed for the db-88f6820-gp development board, so is completely removed.

Kevin Smith (3):
  arm: mvebu: a38x: Remove unsupported topologies
  arm: mvebu: a38x: Add const to some function calls
  arm: mvebu: a38x: serdes specification cleanup

 arch/arm/mach-mvebu/serdes/a38x/Makefile   |1 -
 arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.c |   13 +-
 arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.h |2 +-
 .../serdes/a38x/high_speed_env_spec-38x.c  |1 -
 .../mach-mvebu/serdes/a38x/high_speed_env_spec.c   |  103 +-
 .../mach-mvebu/serdes/a38x/high_speed_env_spec.h   |8 +-
 .../serdes/a38x/high_speed_topology_spec-38x.c | 1009 
 .../serdes/a38x/high_speed_topology_spec.h |  124 ---
 arch/arm/mach-mvebu/serdes/a38x/seq_exec.c |1 -
 arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.c  |  151 ---
 arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.h  |2 -
 board/Marvell/db-88f6820-gp/db-88f6820-gp.c|   17 +
 drivers/ddr/marvell/a38x/ddr3_a38x.h   |5 -
 drivers/ddr/marvell/a38x/ddr3_init.c   |   72 --
 14 files changed, 65 insertions(+), 1444 deletions(-)
 delete mode 100644 
arch/arm/mach-mvebu/serdes/a38x/high_speed_topology_spec-38x.c
 delete mode 100644 arch/arm/mach-mvebu/serdes/a38x/high_speed_topology_spec.h

-- 
2.4.6
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[U-Boot] [PATCH 1/3] arm: mvebu: a38x: Remove unsupported topologies

[Kevin Smith]

A lot of extra configuration information was left over in the
Marvell serdes and DDR3 initialization code for boards that
U-boot does not support.  Remove this extra config information,
and the concept of fixing up board topologies with information
loaded from an EEPROM.  If this needs to be done, it should be
handled in the board file, not in core code.

Signed-off-by: Kevin Smith 
Cc: Stefan Roese 
Cc: Dirk Eibach 
Cc: Luka Perkov 
---
 arch/arm/mach-mvebu/serdes/a38x/Makefile   |1 -
 .../serdes/a38x/high_speed_env_spec-38x.c  |1 -
 .../mach-mvebu/serdes/a38x/high_speed_env_spec.c   |   26 -
 .../serdes/a38x/high_speed_topology_spec-38x.c | 1009 
 .../serdes/a38x/high_speed_topology_spec.h |  124 ---
 arch/arm/mach-mvebu/serdes/a38x/seq_exec.c |1 -
 arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.c  |  151 ---
 arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.h  |2 -
 board/Marvell/db-88f6820-gp/db-88f6820-gp.c|   16 +
 drivers/ddr/marvell/a38x/ddr3_a38x.h   |5 -
 drivers/ddr/marvell/a38x/ddr3_init.c   |   72 --
 11 files changed, 16 insertions(+), 1392 deletions(-)
 delete mode 100644 
arch/arm/mach-mvebu/serdes/a38x/high_speed_topology_spec-38x.c
 delete mode 100644 arch/arm/mach-mvebu/serdes/a38x/high_speed_topology_spec.h

diff --git a/arch/arm/mach-mvebu/serdes/a38x/Makefile 
b/arch/arm/mach-mvebu/serdes/a38x/Makefile
index 1503da8..83b3c0f 100644
--- a/arch/arm/mach-mvebu/serdes/a38x/Makefile
+++ b/arch/arm/mach-mvebu/serdes/a38x/Makefile
@@ -5,6 +5,5 @@
 obj-$(CONFIG_SPL_BUILD)= ctrl_pex.o
 obj-$(CONFIG_SPL_BUILD)+= high_speed_env_spec.o
 obj-$(CONFIG_SPL_BUILD)+= high_speed_env_spec-38x.o
-obj-$(CONFIG_SPL_BUILD)+= high_speed_topology_spec-38x.o
 obj-$(CONFIG_SPL_BUILD)+= seq_exec.o
 obj-$(CONFIG_SPL_BUILD)+= sys_env_lib.o
diff --git a/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec-38x.c 
b/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec-38x.c
index 5ff8567..104e7e8 100644
--- a/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec-38x.c
+++ b/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec-38x.c
@@ -5,7 +5,6 @@
  */
 
 #include 
-#include 
 #include 
 #include 
 #include 
diff --git a/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c 
b/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c
index 23af769..c95231b 100644
--- a/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c
+++ b/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c
@@ -5,14 +5,12 @@
  */
 
 #include 
-#include 
 #include 
 #include 
 #include 
 #include 
 
 #include "high_speed_env_spec.h"
-#include "high_speed_topology_spec.h"
 #include "sys_env_lib.h"
 #include "ctrl_pex.h"
 
@@ -1364,27 +1362,6 @@ enum serdes_seq serdes_type_and_speed_to_speed_seq(enum 
serdes_type serdes_type,
return seq_id;
 }
 
-/*
- * This is the weak default function for the Marvell evaluation or
- * development boarrds. Like the DB-88F6820-GP and others.
- * Custom boards should define this function in their board
- * code (board directory). And overwrite this default function
- * with this custom specific code.
- */
-__weak int hws_board_topology_load(struct serdes_map *serdes_map_array)
-{
-   u32 board_id = mv_board_id_get();
-   u32 board_id_index = mv_board_id_index_get(board_id);
-
-   DEBUG_INIT_FULL_S("\n### hws_board_topology_load ###\n");
-   /* getting board topology according to the board id */
-   DEBUG_INIT_FULL_S("Getting board topology according to the board id\n");
-
-   CHECK_STATUS(load_topology_func_arr[board_id_index] (serdes_map_array));
-
-   return MV_OK;
-}
-
 void print_topology_details(struct serdes_map *serdes_map_array)
 {
u32 lane_num;
@@ -1448,9 +1425,6 @@ int serdes_phy_config(void)
return MV_FAIL;
}
 
-   /* I2C init */
-   i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
-
/* Board topology load */
DEBUG_INIT_FULL_S
("ctrl_high_speed_serdes_phy_config: Loading board topology..\n");
diff --git a/arch/arm/mach-mvebu/serdes/a38x/high_speed_topology_spec-38x.c 
b/arch/arm/mach-mvebu/serdes/a38x/high_speed_topology_spec-38x.c
deleted file mode 100644
index 5f2c3eb..000
--- a/arch/arm/mach-mvebu/serdes/a38x/high_speed_topology_spec-38x.c
+++ /dev/null
@@ -1,1009 +0,0 @@
-/*
- * Copyright (C) Marvell International Ltd. and its affiliates
- *
- * SPDX-License-Identifier:GPL-2.0
- */
-
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-
-#include "high_speed_topology_spec.h"
-#include "sys_env_lib.h"
-
-#ifdef CONFIG_CUSTOMER_BOARD_SUPPORT
-/*
- * This is an example implementation for this custom board
- * specific function
- */
-static struct serdes_map custom_board_topology_config[] = {
-   /* Customer Board Topology - reference from 

[U-Boot] [PATCH 2/3] arm: mvebu: a38x: Add const to some function calls

[Kevin Smith]

Functions that do not modify the pointer passed should declare it
as const.

Signed-off-by: Kevin Smith 
Cc: Stefan Roese 
Cc: Dirk Eibach 
Cc: Luka Perkov 
---
 arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.c| 2 +-
 arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.h| 2 +-
 arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c | 6 +++---
 arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.h | 4 ++--
 4 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.c 
b/arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.c
index 5f223f9..9947412 100644
--- a/arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.c
+++ b/arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.c
@@ -13,7 +13,7 @@
 #include "ctrl_pex.h"
 #include "sys_env_lib.h"
 
-int hws_pex_config(struct serdes_map *serdes_map)
+int hws_pex_config(const struct serdes_map *serdes_map)
 {
u32 pex_idx, tmp, next_busno, first_busno, temp_pex_reg,
temp_reg, addr, dev_id, ctrl_mode;
diff --git a/arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.h 
b/arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.h
index df395bf..16ee4cb 100644
--- a/arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.h
+++ b/arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.h
@@ -78,7 +78,7 @@
 #define PEX_STATUS_AND_COMMAND 0x004
 #define PXSAC_MABORT   BIT(29) /* Recieved Master Abort */
 
-int hws_pex_config(struct serdes_map *serdes_map);
+int hws_pex_config(const struct serdes_map *serdes_map);
 int pex_local_bus_num_set(u32 pex_if, u32 bus_num);
 int pex_local_dev_num_set(u32 pex_if, u32 dev_num);
 u32 pex_config_read(u32 pex_if, u32 bus, u32 dev, u32 func, u32 reg_off);
diff --git a/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c 
b/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c
index c95231b..24e9af6 100644
--- a/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c
+++ b/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c
@@ -1362,7 +1362,7 @@ enum serdes_seq serdes_type_and_speed_to_speed_seq(enum 
serdes_type serdes_type,
return seq_id;
 }
 
-void print_topology_details(struct serdes_map *serdes_map_array)
+void print_topology_details(const struct serdes_map *serdes_map_array)
 {
u32 lane_num;
 
@@ -1462,7 +1462,7 @@ int serdes_polarity_config(u32 serdes_num, int is_rx)
return MV_OK;
 }
 
-int hws_power_up_serdes_lanes(struct serdes_map *serdes_config_map)
+int hws_power_up_serdes_lanes(const struct serdes_map *serdes_config_map)
 {
u32 serdes_id, serdes_lane_num;
enum ref_clock ref_clock;
@@ -2145,7 +2145,7 @@ int hws_ref_clock_set(u32 serdes_num, enum serdes_type 
serdes_type,
  * RETURNS:  MV_OK   - for success
  *   MV_BAD_PARAM- for fail
  */
-int hws_pex_tx_config_seq(struct serdes_map *serdes_map)
+int hws_pex_tx_config_seq(const struct serdes_map *serdes_map)
 {
enum serdes_mode serdes_mode;
u32 serdes_lane_id, serdes_lane_hw_num;
diff --git a/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.h 
b/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.h
index 2508721..5f3b9d8 100644
--- a/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.h
+++ b/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.h
@@ -220,7 +220,7 @@ enum serdes_seq serdes_type_and_speed_to_speed_seq(enum 
serdes_type serdes_type,
   enum serdes_speed baud_rate);
 int hws_serdes_seq_init(void);
 int hws_serdes_seq_db_init(void);
-int hws_power_up_serdes_lanes(struct serdes_map *serdes_config_map);
+int hws_power_up_serdes_lanes(const struct serdes_map *serdes_config_map);
 int hws_ctrl_high_speed_serdes_phy_config(void);
 int serdes_power_up_ctrl(u32 serdes_num, int serdes_power_up,
 enum serdes_type serdes_type,
@@ -244,7 +244,7 @@ u32 hws_serdes_get_ref_clock_val(enum serdes_type 
serdes_type);
 u32 hws_serdes_get_max_lane(void);
 int hws_get_ext_base_addr(u32 serdes_num, u32 base_addr, u32 unit_base_offset,
  u32 *unit_base_reg, u32 *unit_offset);
-int hws_pex_tx_config_seq(struct serdes_map *serdes_map);
+int hws_pex_tx_config_seq(const struct serdes_map *serdes_map);
 u32 hws_get_physical_serdes_num(u32 serdes_num);
 int hws_is_serdes_active(u8 lane_num);
 
-- 
2.4.6
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Re: [U-Boot] [PATCH v7 5/9] arm: serial: Add ability to use pre-initialized UARTs

[Tom Rini]

On Wed, Oct 21, 2015 at 02:49:20PM -0600, Simon Glass wrote:
> Hi,
> 
> On 20 October 2015 at 07:05, Rob Herring  wrote:
> > On Tue, Oct 20, 2015 at 3:15 AM, Linus Walleij  
> > wrote:
> >> On Tue, Oct 20, 2015 at 10:10 AM, Linus Walleij
> >>  wrote:
> >>> On Mon, Oct 19, 2015 at 9:21 PM, Rob Herring  wrote:
>  On Mon, Oct 19, 2015 at 7:57 AM, Linus Walleij 
>   wrote:
> >>>
>  Err, what?
> 
>  $ git log --merges --grep='Pull.*\(Herring\|Likely\)' --oneline
>  Documentation/devicetree/
> >>>
> >>> OK nice, bad research from me. My sloppy statement was
> >>> based on this:
> >>>
> >>> OPEN FIRMWARE AND FLATTENED DEVICE TREE
> >>> M:  Rob Herring 
> >>> M:  Frank Rowand 
> >>> M:  Grant Likely 
> >>> L:  devicet...@vger.kernel.org
> >>> W:  http://www.devicetree.org/
> >>> T:  git 
> >>> git://git.kernel.org/pub/scm/linux/kernel/git/glikely/linux.git
> >>> S:  Maintained
> >>> F:  drivers/of/
> >>> F:  include/linux/of*.h
> >>> F:  scripts/dtc/
> >>>
>  The DT core code and bindings (which don't go thru subsystem trees) go
>  together.
> >>>
> >>> I guess I should just send a patch adding
> >>>
> >>> F:Documentation/devicetree/*
> >>>
> >>> ...and hope things get better from that.
> >>
> >> Ah yeah now I also woke up properly... so there is a special group of 
> >> people
> >> listed under another heading for this, and I should know that, mea culpa.
> >>
> >> OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS
> >> M:  Rob Herring 
> >> M:  Pawel Moll 
> >> M:  Mark Rutland 
> >> M:  Ian Campbell 
> >> M:  Kumar Gala 
> >> L:  devicet...@vger.kernel.org
> >> S:  Maintained
> >> F:  Documentation/devicetree/
> >> F:  arch/*/boot/dts/
> >> F:  include/dt-bindings/
> >>
> >> So can we add your git tree as T: here and replace Grant's tree in
> >> the overall DT entry above it?
> >
> > I would hold off. We've not sorted out our workflow yet and may move
> > to a shared repo.
> 
> With respect to this patch, I wonder if someone in the 'circle of
> trust' might draw up a patch to handle skipping init and specifying
> the input the clock speed? A little bit of progress might go a long
> way.

Or at least "yes, if you do it $this way, we'll take it".. ?

-- 
Tom


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Re: [U-Boot] [PATCH v2 3/3] uuid: add selection by string for known partition type GUID

[Tom Rini]

On Wed, Oct 21, 2015 at 02:14:49PM +0200, Patrick Delaunay wrote:

> short strings can be used in type parameter of gpt command
> to replace the guid string for the types known by u-boot
> 
>   partitions = name=boot,size=0x6bc00,type=data; \
>name=root,size=0x7538ba00,type=linux;
>   gpt write mmc 0 $partitions
> 
> and they are also used to display the type of partition
> in "part list" command
> 
>   Partition Map for MMC device 0  --   Partition Type: EFI
> 
>   PartStart LBA   End LBA Name
>   Attributes
>   Type GUID
>   Partition GUID
> 1 0x0022  0x037f  "boot"
>   attrs:  0x
>   type:   ebd0a0a2-b9e5-4433-87c0-68b6b72699c7
>   type:   data
>   guid:   d117f98e-6f2c-d04b-a5b2-331a19f91cb2
> 2 0x0380  0x003a9fdc  "root"
>   attrs:  0x
>   type:   0fc63daf-8483-4772-8e79-3d69d8477de4
>   type:   linux
>   guid:   25718777-d0ad-7443-9e60-02cb591c9737
> 
> Signed-off-by: Patrick Delaunay 

Reviewed-by: Tom Rini 

-- 
Tom


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Re: [U-Boot] [PATCH v4 00/24] spi: Use BIT and GENMASK

[Jagan Teki]

On 23 October 2015 at 02:55, Tom Rini  wrote:
> On Fri, Oct 23, 2015 at 02:20:00AM +0530, Jagan Teki wrote:
>
>> This series replaces numerical bit shitfts and mask values
>> with BIT and GENMASK macro's
>>
>> Changes for v4:
>> - Patch split for individual drivers.
>> Changes for v3, v2:
>> - none
>
> For the GENMASK changes, how did you do the conversion?  I only
> reviewed-by the OMAP ones since I pulled out printf and manually
> confirmed each change.

Did it manually based on the bit masks' but these were verified on armv7 system.

--  Jagan | openedev.
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[U-Boot] [PATCH] spi: Tegra: add device tree binding doc for SPI and QSPI

[Tom Warren]

This patch adds the device tree binding doc for the Tegra114
SPI controller and the Tegra210 QSPI controller.

Signed-off-by: Tom Warren 
---
 doc/device-tree-bindings/spi/spi-tegra.txt | 47 ++
 1 file changed, 47 insertions(+)
 create mode 100644 doc/device-tree-bindings/spi/spi-tegra.txt

diff --git a/doc/device-tree-bindings/spi/spi-tegra.txt 
b/doc/device-tree-bindings/spi/spi-tegra.txt
new file mode 100644
index 000..e215efe
--- /dev/null
+++ b/doc/device-tree-bindings/spi/spi-tegra.txt
@@ -0,0 +1,47 @@
+NVIDIA Tegra114 SPI controller.
+
+Required properties:
+- compatible : should be "nvidia,tegra114-spi".
+- reg: Should contain SPI registers location and length.
+- interrupts: Should contain SPI interrupts.
+- clocks : Should contain an entry for SPI clock.
+
+Recommended properties:
+- spi-max-frequency: Definition as per
+ doc/device-tree-bindings/spi/spi-bus.txt
+Example:
+
+spi@7000d600 {
+   compatible = "nvidia,tegra114-spi";
+   reg = <0x7000d600 0x200>;
+   interrupts = <0 82 0x04>;
+   #address-cells = <1>;
+   #size-cells = <0>;
+   clocks = <_car 44>;
+   status = "disabled";
+   spi-max-frequency = <2500>;
+};
+
+NVIDIA Tegra210 QSPI controller.
+
+Required properties:
+- compatible : should be "nvidia,tegra210-qspi".
+- reg: Should contain QSPI registers location and length.
+- interrupts: Should contain QSPI interrupts.
+- clocks : Should contain an entry for QSPI clock.
+
+Recommended properties:
+- spi-max-frequency: Definition as per
+ doc/device-tree-bindings/spi/spi-bus.txt
+Example:
+
+spi@7041 {
+   compatible = "nvidia,tegra210-qspi";
+   reg = <0x0 0x7041 0x0 0x1000>;
+   interrupts = <0 10 0x04>;
+   #address-cells = <1>;
+   #size-cells = <0>;
+   clocks = <_car 211>;
+   status = "disabled";
+   spi-max-frequency = <2400>;
+};
-- 
1.8.2.1.610.g562af5b

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Re: [U-Boot] [PATCH v4 06/24] spi: cadence_qspi_apb: Use BIT macro

[Vikas MANOCHA]

Thanks Jagan for this patch.

Acked-by: vikas.mano...@st.com

Rgds,
Vikas

> -Original Message-
> From: Jagan Teki [mailto:jt...@openedev.com]
> Sent: Thursday, October 22, 2015 1:50 PM
> To: u-boot@lists.denx.de
> Cc: Jagan Teki; Stefan Roese; Vikas MANOCHA; Marek Vasut
> Subject: [PATCH v4 06/24] spi: cadence_qspi_apb: Use BIT macro
> 
> Replace numerical bit shift with BIT macro in cadence_qspi_apb
> 
> :%s/(1 << nr)/BIT(nr)/g
> where nr = 0, 1, 2  31
> 
> Cc: Stefan Roese 
> Cc: Vikas Manocha 
> Cc: Marek Vasut 
> Signed-off-by: Jagan Teki 
> ---
>  drivers/spi/cadence_qspi_apb.c | 28 ++--
>  1 file changed, 14 insertions(+), 14 deletions(-)
> 
> diff --git a/drivers/spi/cadence_qspi_apb.c
> b/drivers/spi/cadence_qspi_apb.c index d053407..7786dd6 100644
> --- a/drivers/spi/cadence_qspi_apb.c
> +++ b/drivers/spi/cadence_qspi_apb.c
> @@ -58,10 +58,10 @@
>  #define  CQSPI_REG_CONFIG0x00
>  #define  CQSPI_REG_CONFIG_CLK_POL_LSB1
>  #define  CQSPI_REG_CONFIG_CLK_PHA_LSB2
> -#define  CQSPI_REG_CONFIG_ENABLE_MASK(1 << 0)
> -#define  CQSPI_REG_CONFIG_DIRECT_MASK(1 << 7)
> -#define  CQSPI_REG_CONFIG_DECODE_MASK(1 << 9)
> -#define  CQSPI_REG_CONFIG_XIP_IMM_MASK   (1 << 18)
> +#define  CQSPI_REG_CONFIG_ENABLE_MASKBIT(0)
> +#define  CQSPI_REG_CONFIG_DIRECT_MASKBIT(7)
> +#define  CQSPI_REG_CONFIG_DECODE_MASKBIT(9)
> +#define  CQSPI_REG_CONFIG_XIP_IMM_MASK   BIT(18)
>  #define  CQSPI_REG_CONFIG_CHIPSELECT_LSB 10
>  #define  CQSPI_REG_CONFIG_BAUD_LSB   19
>  #define  CQSPI_REG_CONFIG_IDLE_LSB   31
> @@ -122,18 +122,18 @@
>  #define  CQSPI_REG_IRQMASK   0x44
> 
>  #define  CQSPI_REG_INDIRECTRD0x60
> -#define  CQSPI_REG_INDIRECTRD_START_MASK (1 <<
> 0)
> -#define  CQSPI_REG_INDIRECTRD_CANCEL_MASK(1 << 1)
> -#define  CQSPI_REG_INDIRECTRD_INPROGRESS_MASK(1 << 2)
> -#define  CQSPI_REG_INDIRECTRD_DONE_MASK  (1 <<
> 5)
> +#define  CQSPI_REG_INDIRECTRD_START_MASK BIT(0)
> +#define  CQSPI_REG_INDIRECTRD_CANCEL_MASKBIT(1)
> +#define  CQSPI_REG_INDIRECTRD_INPROGRESS_MASKBIT(2)
> +#define  CQSPI_REG_INDIRECTRD_DONE_MASK  BIT(5)
> 
>  #define  CQSPI_REG_INDIRECTRDWATERMARK   0x64
>  #define  CQSPI_REG_INDIRECTRDSTARTADDR   0x68
>  #define  CQSPI_REG_INDIRECTRDBYTES   0x6C
> 
>  #define  CQSPI_REG_CMDCTRL   0x90
> -#define  CQSPI_REG_CMDCTRL_EXECUTE_MASK  (1 <<
> 0)
> -#define  CQSPI_REG_CMDCTRL_INPROGRESS_MASK   (1 << 1)
> +#define  CQSPI_REG_CMDCTRL_EXECUTE_MASK  BIT(0)
> +#define  CQSPI_REG_CMDCTRL_INPROGRESS_MASK   BIT(1)
>  #define  CQSPI_REG_CMDCTRL_DUMMY_LSB 7
>  #define  CQSPI_REG_CMDCTRL_WR_BYTES_LSB  12
>  #define  CQSPI_REG_CMDCTRL_WR_EN_LSB 15
> @@ -149,10 +149,10 @@
>  #define  CQSPI_REG_CMDCTRL_OPCODE_MASK   0xFF
> 
>  #define  CQSPI_REG_INDIRECTWR0x70
> -#define  CQSPI_REG_INDIRECTWR_START_MASK (1 <<
> 0)
> -#define  CQSPI_REG_INDIRECTWR_CANCEL_MASK(1 << 1)
> -#define  CQSPI_REG_INDIRECTWR_INPROGRESS_MASK(1 <<
> 2)
> -#define  CQSPI_REG_INDIRECTWR_DONE_MASK  (1 <<
> 5)
> +#define  CQSPI_REG_INDIRECTWR_START_MASK BIT(0)
> +#define  CQSPI_REG_INDIRECTWR_CANCEL_MASKBIT(1)
> +#define  CQSPI_REG_INDIRECTWR_INPROGRESS_MASKBIT(2)
> +#define  CQSPI_REG_INDIRECTWR_DONE_MASK  BIT(5)
> 
>  #define  CQSPI_REG_INDIRECTWRWATERMARK   0x74
>  #define  CQSPI_REG_INDIRECTWRSTARTADDR   0x78
> --
> 1.9.1

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[U-Boot] [PATCH 3/3] arm: mvebu: a38x: serdes specification cleanup

[Kevin Smith]

Instead of allocating space in the driver for the serdes
specification table, just allow the board file to set a pointer
to it.  Also, allow the board to only specify the lanes that are
used instead of including unused lanes.

Signed-off-by: Kevin Smith 
Cc: Stefan Roese 
Cc: Dirk Eibach 
Cc: Luka Perkov 
---
 arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.c | 13 ++--
 arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.h |  2 +-
 .../mach-mvebu/serdes/a38x/high_speed_env_spec.c   | 77 +++---
 .../mach-mvebu/serdes/a38x/high_speed_env_spec.h   |  8 +--
 board/Marvell/db-88f6820-gp/db-88f6820-gp.c|  5 +-
 5 files changed, 51 insertions(+), 54 deletions(-)

diff --git a/arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.c 
b/arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.c
index 9947412..06a7715 100644
--- a/arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.c
+++ b/arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.c
@@ -13,17 +13,16 @@
 #include "ctrl_pex.h"
 #include "sys_env_lib.h"
 
-int hws_pex_config(const struct serdes_map *serdes_map)
+int hws_pex_config(const struct serdes_map *serdes_map, u8 count)
 {
u32 pex_idx, tmp, next_busno, first_busno, temp_pex_reg,
temp_reg, addr, dev_id, ctrl_mode;
enum serdes_type serdes_type;
-   u32 idx, max_lane_num;
+   u32 idx;
 
DEBUG_INIT_FULL_S("\n### hws_pex_config ###\n");
 
-   max_lane_num = hws_serdes_get_max_lane();
-   for (idx = 0; idx < max_lane_num; idx++) {
+   for (idx = 0; idx < count; idx++) {
serdes_type = serdes_map[idx].serdes_type;
/* configuration for PEX only */
if ((serdes_type != PEX0) && (serdes_type != PEX1) &&
@@ -47,7 +46,7 @@ int hws_pex_config(const struct serdes_map *serdes_map)
tmp = reg_read(SOC_CTRL_REG);
tmp &= ~0x03;
 
-   for (idx = 0; idx < max_lane_num; idx++) {
+   for (idx = 0; idx < count; idx++) {
serdes_type = serdes_map[idx].serdes_type;
if ((serdes_type != PEX0) &&
((serdes_map[idx].serdes_mode == PEX_ROOT_COMPLEX_X4) ||
@@ -81,7 +80,7 @@ int hws_pex_config(const struct serdes_map *serdes_map)
next_busno = 0;
mdelay(150);
 
-   for (idx = 0; idx < max_lane_num; idx++) {
+   for (idx = 0; idx < count; idx++) {
serdes_type = serdes_map[idx].serdes_type;
DEBUG_INIT_FULL_S(" serdes_type=0x");
DEBUG_INIT_FULL_D(serdes_type, 8);
@@ -191,7 +190,7 @@ int hws_pex_config(const struct serdes_map *serdes_map)
/* Update pex DEVICE ID */
ctrl_mode = sys_env_model_get();
 
-   for (idx = 0; idx < max_lane_num; idx++) {
+   for (idx = 0; idx < count; idx++) {
serdes_type = serdes_map[idx].serdes_type;
/* configuration for PEX only */
if ((serdes_type != PEX0) && (serdes_type != PEX1) &&
diff --git a/arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.h 
b/arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.h
index 16ee4cb..5f7e2c7 100644
--- a/arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.h
+++ b/arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.h
@@ -78,7 +78,7 @@
 #define PEX_STATUS_AND_COMMAND 0x004
 #define PXSAC_MABORT   BIT(29) /* Recieved Master Abort */
 
-int hws_pex_config(const struct serdes_map *serdes_map);
+int hws_pex_config(const struct serdes_map *serdes_map, u8 count);
 int pex_local_bus_num_set(u32 pex_if, u32 bus_num);
 int pex_local_dev_num_set(u32 pex_if, u32 dev_num);
 u32 pex_config_read(u32 pex_if, u32 bus, u32 dev, u32 func, u32 reg_off);
diff --git a/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c 
b/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c
index 24e9af6..7d67199 100644
--- a/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c
+++ b/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c
@@ -20,11 +20,6 @@
 #error "No device is defined"
 #endif
 
-/*
- * The board topology map, initialized in the beginning of
- * ctrl_high_speed_serdes_phy_config
- */
-struct serdes_map serdes_configuration_map[MAX_SERDES_LANES];
 
 /*
  * serdes_seq_db - holds all serdes sequences, their size and the
@@ -1362,7 +1357,8 @@ enum serdes_seq serdes_type_and_speed_to_speed_seq(enum 
serdes_type serdes_type,
return seq_id;
 }
 
-void print_topology_details(const struct serdes_map *serdes_map_array)
+static void print_topology_details(const struct serdes_map *serdes_map,
+   u8 count)
 {
u32 lane_num;
 
@@ -1370,16 +1366,16 @@ void print_topology_details(const struct serdes_map 
*serdes_map_array)
 
DEBUG_INIT_S(" | Lane #  | Speed |  Type   |\n");
DEBUG_INIT_S(" \n");
-   for (lane_num = 0; lane_num < hws_serdes_get_max_lane(); lane_num++) {
-   if (serdes_map_array[lane_num].serdes_type == 

[U-Boot] [PATCH v5 17/23] spi: cadence_qspi_apb: Use GENMASK

[Jagan Teki]

Replace numeric mask hexcodes with GENMASK macro
in cadence_qspi_apb

Cc: Fabio Estevam 
Cc: Stefan Roese 
Cc: Marek Vasut 
Cc: Tom Rini 
Acked-by: Vikas Manocha 
Signed-off-by: Jagan Teki 
---
 drivers/spi/cadence_qspi_apb.c | 46 +-
 1 file changed, 23 insertions(+), 23 deletions(-)

diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c
index 7786dd6..662d3bb 100644
--- a/drivers/spi/cadence_qspi_apb.c
+++ b/drivers/spi/cadence_qspi_apb.c
@@ -44,7 +44,7 @@
 #define CQSPI_INST_TYPE_QUAD   (2)
 
 #define CQSPI_STIG_DATA_LEN_MAX(8)
-#define CQSPI_INDIRECTTRIGGER_ADDR_MASK(0xF)
+#define CQSPI_INDIRECTTRIGGER_ADDR_MASKGENMASK(19, 0)
 
 #define CQSPI_DUMMY_CLKS_PER_BYTE  (8)
 #define CQSPI_DUMMY_BYTES_MAX  (4)
@@ -65,8 +65,8 @@
 #defineCQSPI_REG_CONFIG_CHIPSELECT_LSB 10
 #defineCQSPI_REG_CONFIG_BAUD_LSB   19
 #defineCQSPI_REG_CONFIG_IDLE_LSB   31
-#defineCQSPI_REG_CONFIG_CHIPSELECT_MASK0xF
-#defineCQSPI_REG_CONFIG_BAUD_MASK  0xF
+#defineCQSPI_REG_CONFIG_CHIPSELECT_MASKGENMASK(3, 0)
+#defineCQSPI_REG_CONFIG_BAUD_MASK  GENMASK(3, 0)
 
 #defineCQSPI_REG_RD_INSTR  0x04
 #defineCQSPI_REG_RD_INSTR_OPCODE_LSB   0
@@ -75,10 +75,10 @@
 #defineCQSPI_REG_RD_INSTR_TYPE_DATA_LSB16
 #defineCQSPI_REG_RD_INSTR_MODE_EN_LSB  20
 #defineCQSPI_REG_RD_INSTR_DUMMY_LSB24
-#defineCQSPI_REG_RD_INSTR_TYPE_INSTR_MASK  0x3
-#defineCQSPI_REG_RD_INSTR_TYPE_ADDR_MASK   0x3
-#defineCQSPI_REG_RD_INSTR_TYPE_DATA_MASK   0x3
-#defineCQSPI_REG_RD_INSTR_DUMMY_MASK   0x1F
+#defineCQSPI_REG_RD_INSTR_TYPE_INSTR_MASK  GENMASK(1, 0)
+#defineCQSPI_REG_RD_INSTR_TYPE_ADDR_MASK   GENMASK(1, 0)
+#defineCQSPI_REG_RD_INSTR_TYPE_DATA_MASK   GENMASK(1, 0)
+#defineCQSPI_REG_RD_INSTR_DUMMY_MASK   GENMASK(4, 0)
 
 #defineCQSPI_REG_WR_INSTR  0x08
 #defineCQSPI_REG_WR_INSTR_OPCODE_LSB   0
@@ -88,23 +88,23 @@
 #defineCQSPI_REG_DELAY_TCHSH_LSB   8
 #defineCQSPI_REG_DELAY_TSD2D_LSB   16
 #defineCQSPI_REG_DELAY_TSHSL_LSB   24
-#defineCQSPI_REG_DELAY_TSLCH_MASK  0xFF
-#defineCQSPI_REG_DELAY_TCHSH_MASK  0xFF
-#defineCQSPI_REG_DELAY_TSD2D_MASK  0xFF
-#defineCQSPI_REG_DELAY_TSHSL_MASK  0xFF
+#defineCQSPI_REG_DELAY_TSLCH_MASK  GENMASK(7, 0)
+#defineCQSPI_REG_DELAY_TCHSH_MASK  GENMASK(7, 0)
+#defineCQSPI_REG_DELAY_TSD2D_MASK  GENMASK(7, 0)
+#defineCQSPI_REG_DELAY_TSHSL_MASK  GENMASK(7, 0)
 
 #defineCQSPI_READLCAPTURE  0x10
 #defineCQSPI_READLCAPTURE_BYPASS_LSB   0
 #defineCQSPI_READLCAPTURE_DELAY_LSB1
-#defineCQSPI_READLCAPTURE_DELAY_MASK   0xF
+#defineCQSPI_READLCAPTURE_DELAY_MASK   GENMASK(3, 0)
 
 #defineCQSPI_REG_SIZE  0x14
 #defineCQSPI_REG_SIZE_ADDRESS_LSB  0
 #defineCQSPI_REG_SIZE_PAGE_LSB 4
 #defineCQSPI_REG_SIZE_BLOCK_LSB16
-#defineCQSPI_REG_SIZE_ADDRESS_MASK 0xF
-#defineCQSPI_REG_SIZE_PAGE_MASK0xFFF
-#defineCQSPI_REG_SIZE_BLOCK_MASK   0x3F
+#defineCQSPI_REG_SIZE_ADDRESS_MASK GENMASK(3, 0)
+#defineCQSPI_REG_SIZE_PAGE_MASKGENMASK(11, 0)
+#defineCQSPI_REG_SIZE_BLOCK_MASK   GENMASK(5, 0)
 
 #defineCQSPI_REG_SRAMPARTITION 0x18
 #defineCQSPI_REG_INDIRECTTRIGGER   0x1C
@@ -115,8 +115,8 @@
 #defineCQSPI_REG_SDRAMLEVEL0x2C
 #defineCQSPI_REG_SDRAMLEVEL_RD_LSB 0
 #defineCQSPI_REG_SDRAMLEVEL_WR_LSB 16
-#defineCQSPI_REG_SDRAMLEVEL_RD_MASK0x
-#defineCQSPI_REG_SDRAMLEVEL_WR_MASK0x
+#defineCQSPI_REG_SDRAMLEVEL_RD_MASKGENMASK(15, 0)
+#defineCQSPI_REG_SDRAMLEVEL_WR_MASKGENMASK(15, 0)
 
 #defineCQSPI_REG_IRQSTATUS 0x40
 #defineCQSPI_REG_IRQMASK   0x44
@@ -142,11 +142,11 @@
 #defineCQSPI_REG_CMDCTRL_RD_BYTES_LSB  20
 #defineCQSPI_REG_CMDCTRL_RD_EN_LSB 23
 #defineCQSPI_REG_CMDCTRL_OPCODE_LSB24
-#define

[U-Boot] [PATCH v5 21/23] spi: omap3_spi: Use GENMASK

[Jagan Teki]

Replace numeric mask hexcodes with GENMASK macro
in omap3_spi

Cc: Nikita Kiryanov 
Reviewed-by: Tom Rini 
Signed-off-by: Jagan Teki 
---
 drivers/spi/omap3_spi.h | 10 +-
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/spi/omap3_spi.h b/drivers/spi/omap3_spi.h
index fb02ea1..6a07c6d 100644
--- a/drivers/spi/omap3_spi.h
+++ b/drivers/spi/omap3_spi.h
@@ -64,12 +64,12 @@ struct mcspi {
 
 #define OMAP3_MCSPI_CHCONF_PHA BIT(0)
 #define OMAP3_MCSPI_CHCONF_POL BIT(1)
-#define OMAP3_MCSPI_CHCONF_CLKD_MASK   (0x0f << 2)
+#define OMAP3_MCSPI_CHCONF_CLKD_MASK   GENMASK(5, 2)
 #define OMAP3_MCSPI_CHCONF_EPOLBIT(6)
-#define OMAP3_MCSPI_CHCONF_WL_MASK (0x1f << 7)
-#define OMAP3_MCSPI_CHCONF_TRM_RX_ONLY (0x01 << 12)
-#define OMAP3_MCSPI_CHCONF_TRM_TX_ONLY (0x02 << 12)
-#define OMAP3_MCSPI_CHCONF_TRM_MASK(0x03 << 12)
+#define OMAP3_MCSPI_CHCONF_WL_MASK GENMASK(11, 7)
+#define OMAP3_MCSPI_CHCONF_TRM_RX_ONLY BIT(12)
+#define OMAP3_MCSPI_CHCONF_TRM_TX_ONLY BIT(13)
+#define OMAP3_MCSPI_CHCONF_TRM_MASKGENMASK(13, 12)
 #define OMAP3_MCSPI_CHCONF_DMAWBIT(14)
 #define OMAP3_MCSPI_CHCONF_DMARBIT(15)
 #define OMAP3_MCSPI_CHCONF_DPE0BIT(16)
-- 
1.9.1

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[U-Boot] [PATCH v5 20/23] spi: mxs_spi: Use GENMASK

[Jagan Teki]

Replace numeric mask hexcodes with GENMASK macro
in mxs_spi

Cc: Marek Vasut 
Signed-off-by: Jagan Teki 
---
 drivers/spi/mxs_spi.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/spi/mxs_spi.c b/drivers/spi/mxs_spi.c
index 627644b..459c603 100644
--- a/drivers/spi/mxs_spi.c
+++ b/drivers/spi/mxs_spi.c
@@ -23,7 +23,7 @@
 
 #defineMXS_SPI_MAX_TIMEOUT 100
 #defineMXS_SPI_PORT_OFFSET 0x2000
-#define MXS_SSP_CHIPSELECT_MASK0x0030
+#define MXS_SSP_CHIPSELECT_MASKGENMASK(21, 20)
 #define MXS_SSP_CHIPSELECT_SHIFT   20
 
 #define MXSSSP_SMALL_TRANSFER  512
-- 
1.9.1

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[U-Boot] [PATCH v5 22/23] spi: tegra: Use GENMASK

[Jagan Teki]

Replace numeric mask hexcodes with GENMASK macro
in tegra*.c

Cc: Stephen Warren 
Cc: Tom Warren 
Signed-off-by: Jagan Teki 
---
 drivers/spi/tegra114_spi.c   | 12 ++--
 drivers/spi/tegra20_sflash.c |  2 +-
 drivers/spi/tegra20_slink.c  |  4 ++--
 3 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/drivers/spi/tegra114_spi.c b/drivers/spi/tegra114_spi.c
index d9edd11..98a062c 100644
--- a/drivers/spi/tegra114_spi.c
+++ b/drivers/spi/tegra114_spi.c
@@ -35,9 +35,9 @@ DECLARE_GLOBAL_DATA_PTR;
 /* COMMAND1 */
 #define SPI_CMD1_GOBIT(31)
 #define SPI_CMD1_M_S   BIT(30)
-#define SPI_CMD1_MODE_MASK 0x3
+#define SPI_CMD1_MODE_MASK GENMASK(1, 0)
 #define SPI_CMD1_MODE_SHIFT28
-#define SPI_CMD1_CS_SEL_MASK   0x3
+#define SPI_CMD1_CS_SEL_MASK   GENMASK(1, 0)
 #define SPI_CMD1_CS_SEL_SHIFT  26
 #define SPI_CMD1_CS_POL_INACTIVE3  BIT(25)
 #define SPI_CMD1_CS_POL_INACTIVE2  BIT(24)
@@ -45,7 +45,7 @@ DECLARE_GLOBAL_DATA_PTR;
 #define SPI_CMD1_CS_POL_INACTIVE0  BIT(22)
 #define SPI_CMD1_CS_SW_HW  BIT(21)
 #define SPI_CMD1_CS_SW_VAL BIT(20)
-#define SPI_CMD1_IDLE_SDA_MASK 0x3
+#define SPI_CMD1_IDLE_SDA_MASK GENMASK(1, 0)
 #define SPI_CMD1_IDLE_SDA_SHIFT18
 #define SPI_CMD1_BIDIR BIT(17)
 #define SPI_CMD1_LSBI_FE   BIT(16)
@@ -55,14 +55,14 @@ DECLARE_GLOBAL_DATA_PTR;
 #define SPI_CMD1_RX_EN BIT(12)
 #define SPI_CMD1_TX_EN BIT(11)
 #define SPI_CMD1_PACKEDBIT(5)
-#define SPI_CMD1_BIT_LEN_MASK  0x1F
+#define SPI_CMD1_BIT_LEN_MASK  GENMASK(4, 0)
 #define SPI_CMD1_BIT_LEN_SHIFT 0
 
 /* COMMAND2 */
 #define SPI_CMD2_TX_CLK_TAP_DELAY  BIT(6)
-#define SPI_CMD2_TX_CLK_TAP_DELAY_MASK (0x3F << 6)
+#define SPI_CMD2_TX_CLK_TAP_DELAY_MASK GENMASK(11, 6)
 #define SPI_CMD2_RX_CLK_TAP_DELAY  BIT(0)
-#define SPI_CMD2_RX_CLK_TAP_DELAY_MASK (0x3F << 0)
+#define SPI_CMD2_RX_CLK_TAP_DELAY_MASK GENMASK(5, 0)
 
 /* TRANSFER STATUS */
 #define SPI_XFER_STS_RDY   BIT(30)
diff --git a/drivers/spi/tegra20_sflash.c b/drivers/spi/tegra20_sflash.c
index 5dc196b..6888a96 100644
--- a/drivers/spi/tegra20_sflash.c
+++ b/drivers/spi/tegra20_sflash.c
@@ -37,7 +37,7 @@ DECLARE_GLOBAL_DATA_PTR;
 #define SPI_CMD_CS1_EN BIT(6)
 #define SPI_CMD_CS0_EN BIT(5)
 #define SPI_CMD_BIT_LENGTH BIT(4)
-#define SPI_CMD_BIT_LENGTH_MASK0x001F
+#define SPI_CMD_BIT_LENGTH_MASKGENMASK(4, 0)
 
 #define SPI_STAT_BSY   BIT(31)
 #define SPI_STAT_RDY   BIT(30)
diff --git a/drivers/spi/tegra20_slink.c b/drivers/spi/tegra20_slink.c
index d1abac2..43054f1 100644
--- a/drivers/spi/tegra20_slink.c
+++ b/drivers/spi/tegra20_slink.c
@@ -46,13 +46,13 @@ DECLARE_GLOBAL_DATA_PTR;
 #define SLINK_CMD_CS_VAL   BIT(12)
 #define SLINK_CMD_CS_SOFT  BIT(11)
 #define SLINK_CMD_BIT_LENGTH   BIT(4)
-#define SLINK_CMD_BIT_LENGTH_MASK  0x001F
+#define SLINK_CMD_BIT_LENGTH_MASK  GENMASK(4, 0)
 /* COMMAND2 */
 #define SLINK_CMD2_TXENBIT(30)
 #define SLINK_CMD2_RXENBIT(31)
 #define SLINK_CMD2_SS_EN   BIT(18)
 #define SLINK_CMD2_SS_EN_SHIFT 18
-#define SLINK_CMD2_SS_EN_MASK  0x000C
+#define SLINK_CMD2_SS_EN_MASK  GENMASK(19, 18)
 #define SLINK_CMD2_CS_ACTIVE_BETWEEN   BIT(17)
 /* STATUS */
 #define SLINK_STAT_BSY BIT(31)
-- 
1.9.1

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[U-Boot] [PATCH v5 23/23] spi: xilinx_spi: Use GENMASK

[Jagan Teki]

Replace numeric mask hexcodes with GENMASK macro
in xilinx_spi

Cc: Michal Simek 
Signed-off-by: Jagan Teki 
---
 drivers/spi/xilinx_spi.c | 14 +++---
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/drivers/spi/xilinx_spi.c b/drivers/spi/xilinx_spi.c
index 7620163..0713714 100644
--- a/drivers/spi/xilinx_spi.c
+++ b/drivers/spi/xilinx_spi.c
@@ -52,14 +52,14 @@
 #define SPISR_RX_EMPTY BIT(0)
 
 /* SPI Data Transmit Register (spidtr), [1] p12, [2] p12 */
-#define SPIDTR_8BIT_MASK   (0xff << 0)
-#define SPIDTR_16BIT_MASK  (0x << 0)
-#define SPIDTR_32BIT_MASK  (0x << 0)
+#define SPIDTR_8BIT_MASK   GENMASK(7, 0)
+#define SPIDTR_16BIT_MASK  GENMASK(15, 0)
+#define SPIDTR_32BIT_MASK  GENMASK(31, 0)
 
 /* SPI Data Receive Register (spidrr), [1] p12, [2] p12 */
-#define SPIDRR_8BIT_MASK   (0xff << 0)
-#define SPIDRR_16BIT_MASK  (0x << 0)
-#define SPIDRR_32BIT_MASK  (0x << 0)
+#define SPIDRR_8BIT_MASK   GENMASK(7, 0)
+#define SPIDRR_16BIT_MASK  GENMASK(15, 0)
+#define SPIDRR_32BIT_MASK  GENMASK(31, 0)
 
 /* SPI Slave Select Register (spissr), [1] p13, [2] p13 */
 #define SPISSR_MASK(cs)(1 << (cs))
@@ -75,7 +75,7 @@
 #define XILSPI_SPICR_DFLT_OFF  (SPICR_MASTER_INHIBIT | SPICR_MANUAL_SS)
 
 #ifndef CONFIG_XILINX_SPI_IDLE_VAL
-#define CONFIG_XILINX_SPI_IDLE_VAL 0xff
+#define CONFIG_XILINX_SPI_IDLE_VAL GENMASK(7, 0)
 #endif
 
 #ifndef CONFIG_SYS_XILINX_SPI_LIST
-- 
1.9.1

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[U-Boot] [PATCH v2 2/3] sf: spi_flash_probe for both dm/non-dm

[Jagan Teki]

Let's use spi_flash_probe for dm and no-dm spi-flash
and make respective function definations separately.

Cc: Simon Glass 
Signed-off-by: Jagan Teki 
---
Changes for v2:
- none

 common/cmd_sf.c | 19 ++-
 drivers/mtd/spi/sf-uclass.c | 17 +
 include/spi_flash.h | 18 --
 3 files changed, 7 insertions(+), 47 deletions(-)

diff --git a/common/cmd_sf.c b/common/cmd_sf.c
index f1926e3..cdc6c26 100644
--- a/common/cmd_sf.c
+++ b/common/cmd_sf.c
@@ -83,9 +83,6 @@ static int do_spi_flash_probe(int argc, char * const argv[])
unsigned int speed = CONFIG_SF_DEFAULT_SPEED;
unsigned int mode = CONFIG_SF_DEFAULT_MODE;
char *endp;
-#ifndef CONFIG_DM_SPI_FLASH
-   struct spi_flash *new;
-#endif
 
if (argc >= 2) {
cs = simple_strtoul(argv[1], , 0);
@@ -113,27 +110,15 @@ static int do_spi_flash_probe(int argc, char * const 
argv[])
return -1;
}
 
-#ifdef CONFIG_DM_SPI_FLASH
-   flash = dm_spi_flash_probe(bus, cs, speed, mode);
-   if (!flash) {
-   printf("Failed to initialize SPI flash at %u:%u\n", bus, cs);
-   return 1;
-   }
-#else
if (flash)
spi_flash_free(flash);
 
-   new = spi_flash_probe(bus, cs, speed, mode);
-   flash = new;
-
-   if (!new) {
+   flash = spi_flash_probe(bus, cs, speed, mode);
+   if (!flash) {
printf("Failed to initialize SPI flash at %u:%u\n", bus, cs);
return 1;
}
 
-   flash = new;
-#endif
-
return 0;
 }
 
diff --git a/drivers/mtd/spi/sf-uclass.c b/drivers/mtd/spi/sf-uclass.c
index 9c109fa..a1c5810 100644
--- a/drivers/mtd/spi/sf-uclass.c
+++ b/drivers/mtd/spi/sf-uclass.c
@@ -27,21 +27,6 @@ int spi_flash_erase_dm(struct udevice *dev, u32 offset, 
size_t len)
return sf_get_ops(dev)->erase(dev, offset, len);
 }
 
-/*
- * TODO(s...@chromium.org): This is an old-style function. We should remove
- * it when all SPI flash drivers use dm
- */
-struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs,
- unsigned int max_hz, unsigned int spi_mode)
-{
-   struct udevice *dev;
-
-   if (spi_flash_probe_bus_cs(bus, cs, max_hz, spi_mode, ))
-   return NULL;
-
-   return dev_get_uclass_priv(dev);
-}
-
 void spi_flash_free(struct spi_flash *flash)
 {
spi_flash_remove(flash->spi->dev);
@@ -67,7 +52,7 @@ static int spi_flash_probe_bus_cs(unsigned int busnum, 
unsigned int cs,
return 0;
 }
 
-struct spi_flash *dm_spi_flash_probe(unsigned int busnum, unsigned int cs,
+struct spi_flash *spi_flash_probe(unsigned int busnum, unsigned int cs,
unsigned int max_hz, unsigned int spi_mode)
 {
struct udevice *bus, *new;
diff --git a/include/spi_flash.h b/include/spi_flash.h
index 5abbf99..0afc9fb 100644
--- a/include/spi_flash.h
+++ b/include/spi_flash.h
@@ -154,16 +154,6 @@ int spi_flash_write_dm(struct udevice *dev, u32 offset, 
size_t len,
  */
 int spi_flash_erase_dm(struct udevice *dev, u32 offset, size_t len);
 
-struct spi_flash *dm_spi_flash_probe(unsigned int busnum, unsigned int cs,
-   unsigned int max_hz, unsigned int spi_mode);
-
-/* Compatibility function - this is the old U-Boot API */
-struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs,
- unsigned int max_hz, unsigned int spi_mode);
-
-/* Compatibility function - this is the old U-Boot API */
-void spi_flash_free(struct spi_flash *flash);
-
 int spi_flash_remove(struct udevice *flash);
 
 static inline int spi_flash_read(struct spi_flash *flash, u32 offset,
@@ -192,8 +182,6 @@ int sandbox_sf_bind_emul(struct sandbox_state *state, int 
busnum, int cs,
 void sandbox_sf_unbind_emul(struct sandbox_state *state, int busnum, int cs);
 
 #else
-struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs,
-   unsigned int max_hz, unsigned int spi_mode);
 
 /**
  * Set up a new SPI flash from an fdt node
@@ -207,8 +195,6 @@ struct spi_flash *spi_flash_probe(unsigned int bus, 
unsigned int cs,
 struct spi_flash *spi_flash_probe_fdt(const void *blob, int slave_node,
  int spi_node);
 
-void spi_flash_free(struct spi_flash *flash);
-
 static inline int spi_flash_read(struct spi_flash *flash, u32 offset,
size_t len, void *buf)
 {
@@ -228,6 +214,10 @@ static inline int spi_flash_erase(struct spi_flash *flash, 
u32 offset,
 }
 #endif
 
+struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs,
+   unsigned int max_hz, unsigned int spi_mode);
+void spi_flash_free(struct spi_flash *flash);
+
 void spi_boot(void) __noreturn;
 void spi_spl_load_image(uint32_t offs, unsigned int size, void *vdst);
 
-- 
1.9.1

[U-Boot] [PATCH v2 1/3] sf: Add dm_spi_flash_probe

[Jagan Teki]

Updated dm-spi-flash probe using dm_spi_flash_probe.

Cc: Simon Glass 
Signed-off-by: Jagan Teki 
---
Changes for v2:
- none

 common/cmd_sf.c | 23 ---
 drivers/mtd/spi/sf-uclass.c | 27 ++-
 include/spi_flash.h |  5 ++---
 3 files changed, 32 insertions(+), 23 deletions(-)

diff --git a/common/cmd_sf.c b/common/cmd_sf.c
index ac7f5df..f1926e3 100644
--- a/common/cmd_sf.c
+++ b/common/cmd_sf.c
@@ -8,7 +8,6 @@
 
 #include 
 #include 
-#include 
 #include 
 #include 
 #include 
@@ -17,7 +16,6 @@
 #include 
 
 #include 
-#include 
 
 static struct spi_flash *flash;
 
@@ -85,10 +83,7 @@ static int do_spi_flash_probe(int argc, char * const argv[])
unsigned int speed = CONFIG_SF_DEFAULT_SPEED;
unsigned int mode = CONFIG_SF_DEFAULT_MODE;
char *endp;
-#ifdef CONFIG_DM_SPI_FLASH
-   struct udevice *new, *bus_dev;
-   int ret;
-#else
+#ifndef CONFIG_DM_SPI_FLASH
struct spi_flash *new;
 #endif
 
@@ -119,21 +114,11 @@ static int do_spi_flash_probe(int argc, char * const 
argv[])
}
 
 #ifdef CONFIG_DM_SPI_FLASH
-   /* Remove the old device, otherwise probe will just be a nop */
-   ret = spi_find_bus_and_cs(bus, cs, _dev, );
-   if (!ret) {
-   device_remove(new);
-   device_unbind(new);
-   }
-   flash = NULL;
-   ret = spi_flash_probe_bus_cs(bus, cs, speed, mode, );
-   if (ret) {
-   printf("Failed to initialize SPI flash at %u:%u (error %d)\n",
-  bus, cs, ret);
+   flash = dm_spi_flash_probe(bus, cs, speed, mode);
+   if (!flash) {
+   printf("Failed to initialize SPI flash at %u:%u\n", bus, cs);
return 1;
}
-
-   flash = dev_get_uclass_priv(new);
 #else
if (flash)
spi_flash_free(flash);
diff --git a/drivers/mtd/spi/sf-uclass.c b/drivers/mtd/spi/sf-uclass.c
index 350e21a..9c109fa 100644
--- a/drivers/mtd/spi/sf-uclass.c
+++ b/drivers/mtd/spi/sf-uclass.c
@@ -47,7 +47,7 @@ void spi_flash_free(struct spi_flash *flash)
spi_flash_remove(flash->spi->dev);
 }
 
-int spi_flash_probe_bus_cs(unsigned int busnum, unsigned int cs,
+static int spi_flash_probe_bus_cs(unsigned int busnum, unsigned int cs,
   unsigned int max_hz, unsigned int spi_mode,
   struct udevice **devp)
 {
@@ -67,6 +67,31 @@ int spi_flash_probe_bus_cs(unsigned int busnum, unsigned int 
cs,
return 0;
 }
 
+struct spi_flash *dm_spi_flash_probe(unsigned int busnum, unsigned int cs,
+   unsigned int max_hz, unsigned int spi_mode)
+{
+   struct udevice *bus, *new;
+   struct spi_flash *flash;
+   int ret;
+
+   /* Remove the old device, otherwise probe will just be a nop */
+   ret = spi_find_bus_and_cs(busnum, cs, , );
+   if (!ret) {
+   device_remove(new);
+   device_unbind(new);
+   }
+   flash = NULL;
+
+   ret = spi_flash_probe_bus_cs(busnum, cs, max_hz, spi_mode, );
+   if (ret) {
+   printf("Failed to initialize SPI flash at %u:%u (error %d)\n",
+  busnum, cs, ret);
+   return flash;
+   }
+
+   return dev_get_uclass_priv(new);
+}
+
 int spi_flash_remove(struct udevice *dev)
 {
return device_remove(dev);
diff --git a/include/spi_flash.h b/include/spi_flash.h
index 3b2d555..5abbf99 100644
--- a/include/spi_flash.h
+++ b/include/spi_flash.h
@@ -154,9 +154,8 @@ int spi_flash_write_dm(struct udevice *dev, u32 offset, 
size_t len,
  */
 int spi_flash_erase_dm(struct udevice *dev, u32 offset, size_t len);
 
-int spi_flash_probe_bus_cs(unsigned int busnum, unsigned int cs,
-  unsigned int max_hz, unsigned int spi_mode,
-  struct udevice **devp);
+struct spi_flash *dm_spi_flash_probe(unsigned int busnum, unsigned int cs,
+   unsigned int max_hz, unsigned int spi_mode);
 
 /* Compatibility function - this is the old U-Boot API */
 struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs,
-- 
1.9.1

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[U-Boot] [PATCH v2 3/3] sf: Remove spi_flash_remove

[Jagan Teki]

Use direct call to device_remove instead of exctra
spi_flash_remove defination.

Cc: Simon Glass 
Signed-off-by: Jagan Teki 
---
Changes for v2:
- none

 drivers/mtd/spi/sf-uclass.c | 7 +--
 include/spi_flash.h | 2 --
 2 files changed, 1 insertion(+), 8 deletions(-)

diff --git a/drivers/mtd/spi/sf-uclass.c b/drivers/mtd/spi/sf-uclass.c
index a1c5810..60d6cd9 100644
--- a/drivers/mtd/spi/sf-uclass.c
+++ b/drivers/mtd/spi/sf-uclass.c
@@ -29,7 +29,7 @@ int spi_flash_erase_dm(struct udevice *dev, u32 offset, 
size_t len)
 
 void spi_flash_free(struct spi_flash *flash)
 {
-   spi_flash_remove(flash->spi->dev);
+   device_remove(flash->spi->dev);
 }
 
 static int spi_flash_probe_bus_cs(unsigned int busnum, unsigned int cs,
@@ -77,11 +77,6 @@ struct spi_flash *spi_flash_probe(unsigned int busnum, 
unsigned int cs,
return dev_get_uclass_priv(new);
 }
 
-int spi_flash_remove(struct udevice *dev)
-{
-   return device_remove(dev);
-}
-
 UCLASS_DRIVER(spi_flash) = {
.id = UCLASS_SPI_FLASH,
.name   = "spi_flash",
diff --git a/include/spi_flash.h b/include/spi_flash.h
index 0afc9fb..0037f0b 100644
--- a/include/spi_flash.h
+++ b/include/spi_flash.h
@@ -154,8 +154,6 @@ int spi_flash_write_dm(struct udevice *dev, u32 offset, 
size_t len,
  */
 int spi_flash_erase_dm(struct udevice *dev, u32 offset, size_t len);
 
-int spi_flash_remove(struct udevice *flash);
-
 static inline int spi_flash_read(struct spi_flash *flash, u32 offset,
 size_t len, void *buf)
 {
-- 
1.9.1

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Re: [U-Boot] [PATCH v4 08/24] spi: exynos_spi: Use BIT macro

[Jagan Teki]

On 23 October 2015 at 02:54, Tom Rini  wrote:
> On Fri, Oct 23, 2015 at 02:20:08AM +0530, Jagan Teki wrote:
>
>> Replace numerical bit shift with BIT macro in exynos_spi
>>
>> :%s/(1 << nr)/BIT(nr)/g
>> where nr = 0, 1, 2  31
>>
>> Cc: Simon Glass 
>> Signed-off-by: Jagan Teki 
>> ---
>>  drivers/spi/exynos_spi.c | 4 ++--
>>  1 file changed, 2 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/spi/exynos_spi.c b/drivers/spi/exynos_spi.c
>> index 44948c3..ea3c51d 100644
>> --- a/drivers/spi/exynos_spi.c
>> +++ b/drivers/spi/exynos_spi.c
>> @@ -86,7 +86,7 @@ static void spi_request_bytes(struct exynos_spi *regs, int 
>> count, int step)
>>   writel(0, >swap_cfg);
>>   }
>>
>> - assert(count && count < (1 << 16));
>> + assert(count && count < BIT(16));
>>   setbits_le32(>ch_cfg, SPI_CH_RST);
>>   clrbits_le32(>ch_cfg, SPI_CH_RST);
>>
>> @@ -345,7 +345,7 @@ static int exynos_spi_xfer(struct udevice *dev, unsigned 
>> int bitlen,
>>*/
>>   bytelen = bitlen / 8;
>>   for (upto = 0; !ret && upto < bytelen; upto += todo) {
>> - todo = min(bytelen - upto, (1 << 16) - 4);
>> + todo = min(bytelen - upto, BIT(16) - 4);
>>   ret = spi_rx_tx(priv, todo, , , flags);
>>   if (ret)
>>   break;
>
> These look like (1 << 16) is a size, not a bit.  Can you read the
> functions in context and confirm that it really is bit 16 here, rather
> than 4KiB (0x1) ?

Ignoring this change this seems to be 65535 exynos SPI transfer limit,
not a bit.

-- 
Jagan | openedev
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Re: [U-Boot] [PATCH v9 1/4] include: Add log2 and generic bitops header files

[Jagan Teki]

On 22 October 2015 at 17:18, Fabio Estevam  wrote:
> On Thu, Oct 22, 2015 at 9:28 AM, Fabio Estevam  wrote:
>> On Thu, Oct 22, 2015 at 8:25 AM, Jagan Teki  wrote:
>>> On 20 October 2015 at 18:33, Fabio Estevam  
>>> wrote:
 Use the log2 and generic bitops header files directly from the kernel.
>>>
>>> Pls- add separate patches for log2 and biptops, do remember that use
>>> same Linux approach but don't add unneeded definitions now will add
>>> based on the need.
>>
>> I cannot only add log2 definition without the bitops, as ilog2 needs them.
>>
>> Also, I am not adding unneeded definitions. All the header files I
>> added are referenced.
>
> Or are you suggesting to do like this?
>
> - Patch 1: only add log2 header from the kernel
> - Patch 2: only add bitops headers from the kernel
> - Patch 3: Add the users for log2 and bitops headers

May be you can go-ahead with these but pls- don't add unnecessary code
which we may add it later based on the need.

thanks!
-- 
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[U-Boot] [PATCH v5 02/23] spi: zynq_[q]spi: Use GENMASK macro

[Jagan Teki]

GENMASK macro used on zynq_spi.c and zynq_qspi.c

GENMASK is used to create a contiguous bitmask([hi:lo]).
Ex: (0x7 << 3) => GENMASK(5, 3)

Cc: Siva Durga Prasad Paladugu 
Cc: Michal Simek 
Signed-off-by: Jagan Teki 
---
 drivers/spi/zynq_qspi.c | 8 
 drivers/spi/zynq_spi.c  | 6 +++---
 2 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/drivers/spi/zynq_qspi.c b/drivers/spi/zynq_qspi.c
index dd530a1..64b4eea 100644
--- a/drivers/spi/zynq_qspi.c
+++ b/drivers/spi/zynq_qspi.c
@@ -20,15 +20,15 @@ DECLARE_GLOBAL_DATA_PTR;
 #define ZYNQ_QSPI_CR_MSA_MASK  BIT(15) /* Manual start enb */
 #define ZYNQ_QSPI_CR_MCS_MASK  BIT(14) /* Manual chip select */
 #define ZYNQ_QSPI_CR_PCS_MASK  BIT(10) /* Peri chip select */
-#define ZYNQ_QSPI_CR_FW_MASK   (0x3 << 6)  /* FIFO width */
-#define ZYNQ_QSPI_CR_SS_MASK   (0xF << 10) /* Slave Select */
-#define ZYNQ_QSPI_CR_BAUD_MASK (0x7 << 3)  /* Baud rate div */
+#define ZYNQ_QSPI_CR_FW_MASK   GENMASK(7, 6)   /* FIFO width */
+#define ZYNQ_QSPI_CR_SS_MASK   GENMASK(13, 10) /* Slave Select */
+#define ZYNQ_QSPI_CR_BAUD_MASK GENMASK(5, 3)   /* Baud rate div */
 #define ZYNQ_QSPI_CR_CPHA_MASK BIT(2)  /* Clock phase */
 #define ZYNQ_QSPI_CR_CPOL_MASK BIT(1)  /* Clock polarity */
 #define ZYNQ_QSPI_CR_MSTREN_MASK   BIT(0)  /* Mode select */
 #define ZYNQ_QSPI_IXR_RXNEMPTY_MASKBIT(4)  /* RX_FIFO_not_empty */
 #define ZYNQ_QSPI_IXR_TXOW_MASKBIT(2)  /* TX_FIFO_not_full */
-#define ZYNQ_QSPI_IXR_ALL_MASK 0x7F/* All IXR bits */
+#define ZYNQ_QSPI_IXR_ALL_MASK GENMASK(6, 0)   /* All IXR bits */
 #define ZYNQ_QSPI_ENR_SPI_EN_MASK  BIT(0)  /* SPI Enable */
 
 /* zynq qspi Transmit Data Register */
diff --git a/drivers/spi/zynq_spi.c b/drivers/spi/zynq_spi.c
index 92e5712..9ede099 100644
--- a/drivers/spi/zynq_spi.c
+++ b/drivers/spi/zynq_spi.c
@@ -22,14 +22,14 @@ DECLARE_GLOBAL_DATA_PTR;
 /* zynq spi register bit masks ZYNQ_SPI___MASK */
 #define ZYNQ_SPI_CR_MSA_MASK   BIT(15) /* Manual start enb */
 #define ZYNQ_SPI_CR_MCS_MASK   BIT(14) /* Manual chip select */
-#define ZYNQ_SPI_CR_CS_MASK(0xF << 10) /* Chip select */
-#define ZYNQ_SPI_CR_BAUD_MASK  (0x7 << 3)  /* Baud rate div */
+#define ZYNQ_SPI_CR_CS_MASKGENMASK(13, 10) /* Chip select */
+#define ZYNQ_SPI_CR_BAUD_MASK  GENMASK(5, 3)   /* Baud rate div */
 #define ZYNQ_SPI_CR_CPHA_MASK  BIT(2)  /* Clock phase */
 #define ZYNQ_SPI_CR_CPOL_MASK  BIT(1)  /* Clock polarity */
 #define ZYNQ_SPI_CR_MSTREN_MASKBIT(0)  /* Mode select */
 #define ZYNQ_SPI_IXR_RXNEMPTY_MASK BIT(4)  /* RX_FIFO_not_empty */
 #define ZYNQ_SPI_IXR_TXOW_MASK BIT(2)  /* TX_FIFO_not_full */
-#define ZYNQ_SPI_IXR_ALL_MASK  0x7F/* All IXR bits */
+#define ZYNQ_SPI_IXR_ALL_MASK  GENMASK(6, 0)   /* All IXR bits */
 #define ZYNQ_SPI_ENR_SPI_EN_MASK   BIT(0)  /* SPI Enable */
 
 #define ZYNQ_SPI_CR_BAUD_MAX   8   /* Baud rate divisor max val */
-- 
1.9.1

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[U-Boot] [PATCH v5 00/23] spi: Use BIT and GENMASK

[Jagan Teki]

This series replaces numerical bit shitfts and mask values
with BIT and GENMASK macro's

Changes for v5:
- Dropped exynos_spi BIT changes
- Removed GENMASK for 0XFF on cadence_qspi_qpb
- Split the commit message body
Changes for v4:
- Patch split for individual drivers.
Changes for v3, v2:
- none

Jagan Teki (23):
  spi: zynq_[q]spi: Use BIT macro
  spi: zynq_[q]spi: Use GENMASK macro
  spi: altera_spi: Use BIT macro
  spi: atmel_spi: Use BIT macro
  spi: bfin_spi6xx: Use BIT macro
  spi: cadence_qspi_apb: Use BIT macro
  spi: designware_spi: Use BIT macro
  spi: fsl: Use BIT macro
  spi: ich: Use BIT macro
  spi: mpc8xxx_spi: Use BIT macro
  spi: omap3_spi: Use BIT macro
  spi: sh_qspi: Use BIT macro
  spi: tegra: Use BIT macro
  spi: ti_qspi: Use BIT macro
  spi: xilinx_spi: Use BIT macro
  spi: atmel_spi: Use GENMASK
  spi: cadence_qspi_apb: Use GENMASK
  spi: designware_spi: Use GENMASK
  spi: fsl_qspi: Use GENMASK
  spi: mxs_spi: Use GENMASK
  spi: omap3_spi: Use GENMASK
  spi: tegra: Use GENMASK
  spi: xilinx_spi: Use GENMASK

 drivers/spi/altera_spi.c   | 26 +++
 drivers/spi/atmel_spi.h| 54 +++---
 drivers/spi/bfin_spi6xx.c  |  8 ++---
 drivers/spi/cadence_qspi_apb.c | 74 
 drivers/spi/designware_spi.c   | 16 -
 drivers/spi/fsl_dspi.c |  2 +-
 drivers/spi/fsl_espi.c | 20 +--
 drivers/spi/fsl_qspi.c |  6 ++--
 drivers/spi/ich.c  |  4 +--
 drivers/spi/mpc8xxx_spi.c  |  2 +-
 drivers/spi/mxs_spi.c  |  2 +-
 drivers/spi/omap3_spi.h| 64 +--
 drivers/spi/sh_qspi.c  | 16 -
 drivers/spi/tegra114_spi.c | 76 +-
 drivers/spi/tegra20_sflash.c   | 54 +++---
 drivers/spi/tegra20_slink.c| 62 +-
 drivers/spi/ti_qspi.c  | 10 +++---
 drivers/spi/xilinx_spi.c   | 46 -
 drivers/spi/zynq_qspi.c| 28 
 drivers/spi/zynq_spi.c | 22 ++--
 20 files changed, 296 insertions(+), 296 deletions(-)

-- 
1.9.1

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[U-Boot] [PATCH v5 04/23] spi: atmel_spi: Use BIT macro

[Jagan Teki]

Replace numerical bit shift with BIT macro
in atmel_spi

:%s/(1 << nr)/BIT(nr)/g
where nr = 0, 1, 2  31

Cc: Bo Shen 
Reviewed-by: Tom Rini 
Signed-off-by: Jagan Teki 
---
 drivers/spi/atmel_spi.h | 52 -
 1 file changed, 26 insertions(+), 26 deletions(-)

diff --git a/drivers/spi/atmel_spi.h b/drivers/spi/atmel_spi.h
index 1538a23..5b892d2 100644
--- a/drivers/spi/atmel_spi.h
+++ b/drivers/spi/atmel_spi.h
@@ -15,19 +15,19 @@
 #define ATMEL_SPI_VERSION  0x00fc
 
 /* Bits in CR */
-#define ATMEL_SPI_CR_SPIEN (1 << 0)
-#define ATMEL_SPI_CR_SPIDIS(1 << 1)
-#define ATMEL_SPI_CR_SWRST (1 << 7)
-#define ATMEL_SPI_CR_LASTXFER  (1 << 24)
+#define ATMEL_SPI_CR_SPIEN BIT(0)
+#define ATMEL_SPI_CR_SPIDISBIT(1)
+#define ATMEL_SPI_CR_SWRST BIT(7)
+#define ATMEL_SPI_CR_LASTXFER  BIT(24)
 
 /* Bits in MR */
-#define ATMEL_SPI_MR_MSTR  (1 << 0)
-#define ATMEL_SPI_MR_PS(1 << 1)
-#define ATMEL_SPI_MR_PCSDEC(1 << 2)
-#define ATMEL_SPI_MR_FDIV  (1 << 3)
-#define ATMEL_SPI_MR_MODFDIS   (1 << 4)
-#define ATMEL_SPI_MR_WDRBT (1 << 5)
-#define ATMEL_SPI_MR_LLB   (1 << 7)
+#define ATMEL_SPI_MR_MSTR  BIT(0)
+#define ATMEL_SPI_MR_PSBIT(1)
+#define ATMEL_SPI_MR_PCSDECBIT(2)
+#define ATMEL_SPI_MR_FDIV  BIT(3)
+#define ATMEL_SPI_MR_MODFDIS   BIT(4)
+#define ATMEL_SPI_MR_WDRBT BIT(5)
+#define ATMEL_SPI_MR_LLB   BIT(7)
 #define ATMEL_SPI_MR_PCS(x)(((x) & 15) << 16)
 #define ATMEL_SPI_MR_DLYBCS(x) ((x) << 24)
 
@@ -38,25 +38,25 @@
 /* Bits in TDR */
 #define ATMEL_SPI_TDR_TD(x)(x)
 #define ATMEL_SPI_TDR_PCS(x)   ((x) << 16)
-#define ATMEL_SPI_TDR_LASTXFER (1 << 24)
+#define ATMEL_SPI_TDR_LASTXFER BIT(24)
 
 /* Bits in SR/IER/IDR/IMR */
-#define ATMEL_SPI_SR_RDRF  (1 << 0)
-#define ATMEL_SPI_SR_TDRE  (1 << 1)
-#define ATMEL_SPI_SR_MODF  (1 << 2)
-#define ATMEL_SPI_SR_OVRES (1 << 3)
-#define ATMEL_SPI_SR_ENDRX (1 << 4)
-#define ATMEL_SPI_SR_ENDTX (1 << 5)
-#define ATMEL_SPI_SR_RXBUFF(1 << 6)
-#define ATMEL_SPI_SR_TXBUFE(1 << 7)
-#define ATMEL_SPI_SR_NSSR  (1 << 8)
-#define ATMEL_SPI_SR_TXEMPTY   (1 << 9)
-#define ATMEL_SPI_SR_SPIENS(1 << 16)
+#define ATMEL_SPI_SR_RDRF  BIT(0)
+#define ATMEL_SPI_SR_TDRE  BIT(1)
+#define ATMEL_SPI_SR_MODF  BIT(2)
+#define ATMEL_SPI_SR_OVRES BIT(3)
+#define ATMEL_SPI_SR_ENDRX BIT(4)
+#define ATMEL_SPI_SR_ENDTX BIT(5)
+#define ATMEL_SPI_SR_RXBUFFBIT(6)
+#define ATMEL_SPI_SR_TXBUFEBIT(7)
+#define ATMEL_SPI_SR_NSSR  BIT(8)
+#define ATMEL_SPI_SR_TXEMPTY   BIT(9)
+#define ATMEL_SPI_SR_SPIENSBIT(16)
 
 /* Bits in CSRx */
-#define ATMEL_SPI_CSRx_CPOL(1 << 0)
-#define ATMEL_SPI_CSRx_NCPHA   (1 << 1)
-#define ATMEL_SPI_CSRx_CSAAT   (1 << 3)
+#define ATMEL_SPI_CSRx_CPOLBIT(0)
+#define ATMEL_SPI_CSRx_NCPHA   BIT(1)
+#define ATMEL_SPI_CSRx_CSAAT   BIT(3)
 #define ATMEL_SPI_CSRx_BITS(x) ((x) << 4)
 #define ATMEL_SPI_CSRx_SCBR(x) ((x) << 8)
 #define ATMEL_SPI_CSRx_SCBR_MAX0xff
-- 
1.9.1

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[U-Boot] [PATCH v5 03/23] spi: altera_spi: Use BIT macro

[Jagan Teki]

Replace numerical bit shift with BIT macro
in altera_spi

:%s/(1 << nr)/BIT(nr)/g
where nr = 0, 1, 2  31

Cc: Marek Vasut 
Reviewed-by: Tom Rini 
Signed-off-by: Jagan Teki 
---
 drivers/spi/altera_spi.c | 26 +-
 1 file changed, 13 insertions(+), 13 deletions(-)

diff --git a/drivers/spi/altera_spi.c b/drivers/spi/altera_spi.c
index a4d03d9..2302117 100644
--- a/drivers/spi/altera_spi.c
+++ b/drivers/spi/altera_spi.c
@@ -29,19 +29,19 @@ struct altera_spi_regs {
u32 slave_sel;
 };
 
-#define ALTERA_SPI_STATUS_ROE_MSK  (1 << 3)
-#define ALTERA_SPI_STATUS_TOE_MSK  (1 << 4)
-#define ALTERA_SPI_STATUS_TMT_MSK  (1 << 5)
-#define ALTERA_SPI_STATUS_TRDY_MSK (1 << 6)
-#define ALTERA_SPI_STATUS_RRDY_MSK (1 << 7)
-#define ALTERA_SPI_STATUS_E_MSK(1 << 8)
-
-#define ALTERA_SPI_CONTROL_IROE_MSK(1 << 3)
-#define ALTERA_SPI_CONTROL_ITOE_MSK(1 << 4)
-#define ALTERA_SPI_CONTROL_ITRDY_MSK   (1 << 6)
-#define ALTERA_SPI_CONTROL_IRRDY_MSK   (1 << 7)
-#define ALTERA_SPI_CONTROL_IE_MSK  (1 << 8)
-#define ALTERA_SPI_CONTROL_SSO_MSK (1 << 10)
+#define ALTERA_SPI_STATUS_ROE_MSK  BIT(3)
+#define ALTERA_SPI_STATUS_TOE_MSK  BIT(4)
+#define ALTERA_SPI_STATUS_TMT_MSK  BIT(5)
+#define ALTERA_SPI_STATUS_TRDY_MSK BIT(6)
+#define ALTERA_SPI_STATUS_RRDY_MSK BIT(7)
+#define ALTERA_SPI_STATUS_E_MSKBIT(8)
+
+#define ALTERA_SPI_CONTROL_IROE_MSKBIT(3)
+#define ALTERA_SPI_CONTROL_ITOE_MSKBIT(4)
+#define ALTERA_SPI_CONTROL_ITRDY_MSK   BIT(6)
+#define ALTERA_SPI_CONTROL_IRRDY_MSK   BIT(7)
+#define ALTERA_SPI_CONTROL_IE_MSK  BIT(8)
+#define ALTERA_SPI_CONTROL_SSO_MSK BIT(10)
 
 static ulong altera_spi_base_list[] = CONFIG_SYS_ALTERA_SPI_LIST;
 
-- 
1.9.1

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[U-Boot] [PATCH v5 01/23] spi: zynq_[q]spi: Use BIT macro

[Jagan Teki]

Used BIT macro on zynq_spi.c and zynq_qspi.c

:%s/(1 << nr)/BIT(nr)/g
where nr = 0, 1, 2  31

Cc: Siva Durga Prasad Paladugu 
Cc: Michal Simek 
Reviewed-by: Tom Rini 
Signed-off-by: Jagan Teki 
---
 drivers/spi/zynq_qspi.c | 20 ++--
 drivers/spi/zynq_spi.c  | 16 
 2 files changed, 18 insertions(+), 18 deletions(-)

diff --git a/drivers/spi/zynq_qspi.c b/drivers/spi/zynq_qspi.c
index 8aa61d7..dd530a1 100644
--- a/drivers/spi/zynq_qspi.c
+++ b/drivers/spi/zynq_qspi.c
@@ -16,20 +16,20 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 /* zynq qspi register bit masks ZYNQ_QSPI___MASK */
-#define ZYNQ_QSPI_CR_IFMODE_MASK   (1 << 31)   /* Flash intrface mode*/
-#define ZYNQ_QSPI_CR_MSA_MASK  (1 << 15)   /* Manual start enb */
-#define ZYNQ_QSPI_CR_MCS_MASK  (1 << 14)   /* Manual chip select */
-#define ZYNQ_QSPI_CR_PCS_MASK  (1 << 10)   /* Peri chip select */
+#define ZYNQ_QSPI_CR_IFMODE_MASK   BIT(31) /* Flash intrface mode*/
+#define ZYNQ_QSPI_CR_MSA_MASK  BIT(15) /* Manual start enb */
+#define ZYNQ_QSPI_CR_MCS_MASK  BIT(14) /* Manual chip select */
+#define ZYNQ_QSPI_CR_PCS_MASK  BIT(10) /* Peri chip select */
 #define ZYNQ_QSPI_CR_FW_MASK   (0x3 << 6)  /* FIFO width */
 #define ZYNQ_QSPI_CR_SS_MASK   (0xF << 10) /* Slave Select */
 #define ZYNQ_QSPI_CR_BAUD_MASK (0x7 << 3)  /* Baud rate div */
-#define ZYNQ_QSPI_CR_CPHA_MASK (1 << 2)/* Clock phase */
-#define ZYNQ_QSPI_CR_CPOL_MASK (1 << 1)/* Clock polarity */
-#define ZYNQ_QSPI_CR_MSTREN_MASK   (1 << 0)/* Mode select */
-#define ZYNQ_QSPI_IXR_RXNEMPTY_MASK(1 << 4)/* RX_FIFO_not_empty */
-#define ZYNQ_QSPI_IXR_TXOW_MASK(1 << 2)/* 
TX_FIFO_not_full */
+#define ZYNQ_QSPI_CR_CPHA_MASK BIT(2)  /* Clock phase */
+#define ZYNQ_QSPI_CR_CPOL_MASK BIT(1)  /* Clock polarity */
+#define ZYNQ_QSPI_CR_MSTREN_MASK   BIT(0)  /* Mode select */
+#define ZYNQ_QSPI_IXR_RXNEMPTY_MASKBIT(4)  /* RX_FIFO_not_empty */
+#define ZYNQ_QSPI_IXR_TXOW_MASKBIT(2)  /* TX_FIFO_not_full */
 #define ZYNQ_QSPI_IXR_ALL_MASK 0x7F/* All IXR bits */
-#define ZYNQ_QSPI_ENR_SPI_EN_MASK  (1 << 0)/* SPI Enable */
+#define ZYNQ_QSPI_ENR_SPI_EN_MASK  BIT(0)  /* SPI Enable */
 
 /* zynq qspi Transmit Data Register */
 #define ZYNQ_QSPI_TXD_00_00_OFFSET 0x1C/* Transmit 4-byte inst */
diff --git a/drivers/spi/zynq_spi.c b/drivers/spi/zynq_spi.c
index 65a9633..92e5712 100644
--- a/drivers/spi/zynq_spi.c
+++ b/drivers/spi/zynq_spi.c
@@ -20,17 +20,17 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 /* zynq spi register bit masks ZYNQ_SPI___MASK */
-#define ZYNQ_SPI_CR_MSA_MASK   (1 << 15)   /* Manual start enb */
-#define ZYNQ_SPI_CR_MCS_MASK   (1 << 14)   /* Manual chip select */
+#define ZYNQ_SPI_CR_MSA_MASK   BIT(15) /* Manual start enb */
+#define ZYNQ_SPI_CR_MCS_MASK   BIT(14) /* Manual chip select */
 #define ZYNQ_SPI_CR_CS_MASK(0xF << 10) /* Chip select */
 #define ZYNQ_SPI_CR_BAUD_MASK  (0x7 << 3)  /* Baud rate div */
-#define ZYNQ_SPI_CR_CPHA_MASK  (1 << 2)/* Clock phase */
-#define ZYNQ_SPI_CR_CPOL_MASK  (1 << 1)/* Clock polarity */
-#define ZYNQ_SPI_CR_MSTREN_MASK(1 << 0)/* Mode select 
*/
-#define ZYNQ_SPI_IXR_RXNEMPTY_MASK (1 << 4)/* RX_FIFO_not_empty */
-#define ZYNQ_SPI_IXR_TXOW_MASK (1 << 2)/* TX_FIFO_not_full */
+#define ZYNQ_SPI_CR_CPHA_MASK  BIT(2)  /* Clock phase */
+#define ZYNQ_SPI_CR_CPOL_MASK  BIT(1)  /* Clock polarity */
+#define ZYNQ_SPI_CR_MSTREN_MASKBIT(0)  /* Mode select */
+#define ZYNQ_SPI_IXR_RXNEMPTY_MASK BIT(4)  /* RX_FIFO_not_empty */
+#define ZYNQ_SPI_IXR_TXOW_MASK BIT(2)  /* TX_FIFO_not_full */
 #define ZYNQ_SPI_IXR_ALL_MASK  0x7F/* All IXR bits */
-#define ZYNQ_SPI_ENR_SPI_EN_MASK   (1 << 0)/* SPI Enable */
+#define ZYNQ_SPI_ENR_SPI_EN_MASK   BIT(0)  /* SPI Enable */
 
 #define ZYNQ_SPI_CR_BAUD_MAX   8   /* Baud rate divisor max val */
 #define ZYNQ_SPI_CR_BAUD_SHIFT 3   /* Baud rate divisor shift */
-- 
1.9.1

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[U-Boot] [PATCH v5 06/23] spi: cadence_qspi_apb: Use BIT macro

[Jagan Teki]

Replace numerical bit shift with BIT macro
in cadence_qspi_apb

:%s/(1 << nr)/BIT(nr)/g
where nr = 0, 1, 2  31

Cc: Stefan Roese 
Cc: Marek Vasut 
Acked-by: Vikas Manocha 
Reviewed-by: Tom Rini 
Signed-off-by: Jagan Teki 
---
 drivers/spi/cadence_qspi_apb.c | 28 ++--
 1 file changed, 14 insertions(+), 14 deletions(-)

diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c
index d053407..7786dd6 100644
--- a/drivers/spi/cadence_qspi_apb.c
+++ b/drivers/spi/cadence_qspi_apb.c
@@ -58,10 +58,10 @@
 #defineCQSPI_REG_CONFIG0x00
 #defineCQSPI_REG_CONFIG_CLK_POL_LSB1
 #defineCQSPI_REG_CONFIG_CLK_PHA_LSB2
-#defineCQSPI_REG_CONFIG_ENABLE_MASK(1 << 0)
-#defineCQSPI_REG_CONFIG_DIRECT_MASK(1 << 7)
-#defineCQSPI_REG_CONFIG_DECODE_MASK(1 << 9)
-#defineCQSPI_REG_CONFIG_XIP_IMM_MASK   (1 << 18)
+#defineCQSPI_REG_CONFIG_ENABLE_MASKBIT(0)
+#defineCQSPI_REG_CONFIG_DIRECT_MASKBIT(7)
+#defineCQSPI_REG_CONFIG_DECODE_MASKBIT(9)
+#defineCQSPI_REG_CONFIG_XIP_IMM_MASK   BIT(18)
 #defineCQSPI_REG_CONFIG_CHIPSELECT_LSB 10
 #defineCQSPI_REG_CONFIG_BAUD_LSB   19
 #defineCQSPI_REG_CONFIG_IDLE_LSB   31
@@ -122,18 +122,18 @@
 #defineCQSPI_REG_IRQMASK   0x44
 
 #defineCQSPI_REG_INDIRECTRD0x60
-#defineCQSPI_REG_INDIRECTRD_START_MASK (1 << 0)
-#defineCQSPI_REG_INDIRECTRD_CANCEL_MASK(1 << 1)
-#defineCQSPI_REG_INDIRECTRD_INPROGRESS_MASK(1 << 2)
-#defineCQSPI_REG_INDIRECTRD_DONE_MASK  (1 << 5)
+#defineCQSPI_REG_INDIRECTRD_START_MASK BIT(0)
+#defineCQSPI_REG_INDIRECTRD_CANCEL_MASKBIT(1)
+#defineCQSPI_REG_INDIRECTRD_INPROGRESS_MASKBIT(2)
+#defineCQSPI_REG_INDIRECTRD_DONE_MASK  BIT(5)
 
 #defineCQSPI_REG_INDIRECTRDWATERMARK   0x64
 #defineCQSPI_REG_INDIRECTRDSTARTADDR   0x68
 #defineCQSPI_REG_INDIRECTRDBYTES   0x6C
 
 #defineCQSPI_REG_CMDCTRL   0x90
-#defineCQSPI_REG_CMDCTRL_EXECUTE_MASK  (1 << 0)
-#defineCQSPI_REG_CMDCTRL_INPROGRESS_MASK   (1 << 1)
+#defineCQSPI_REG_CMDCTRL_EXECUTE_MASK  BIT(0)
+#defineCQSPI_REG_CMDCTRL_INPROGRESS_MASK   BIT(1)
 #defineCQSPI_REG_CMDCTRL_DUMMY_LSB 7
 #defineCQSPI_REG_CMDCTRL_WR_BYTES_LSB  12
 #defineCQSPI_REG_CMDCTRL_WR_EN_LSB 15
@@ -149,10 +149,10 @@
 #defineCQSPI_REG_CMDCTRL_OPCODE_MASK   0xFF
 
 #defineCQSPI_REG_INDIRECTWR0x70
-#defineCQSPI_REG_INDIRECTWR_START_MASK (1 << 0)
-#defineCQSPI_REG_INDIRECTWR_CANCEL_MASK(1 << 1)
-#defineCQSPI_REG_INDIRECTWR_INPROGRESS_MASK(1 << 2)
-#defineCQSPI_REG_INDIRECTWR_DONE_MASK  (1 << 5)
+#defineCQSPI_REG_INDIRECTWR_START_MASK BIT(0)
+#defineCQSPI_REG_INDIRECTWR_CANCEL_MASKBIT(1)
+#defineCQSPI_REG_INDIRECTWR_INPROGRESS_MASKBIT(2)
+#defineCQSPI_REG_INDIRECTWR_DONE_MASK  BIT(5)
 
 #defineCQSPI_REG_INDIRECTWRWATERMARK   0x74
 #defineCQSPI_REG_INDIRECTWRSTARTADDR   0x78
-- 
1.9.1

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[U-Boot] [PATCH v5 05/23] spi: bfin_spi6xx: Use BIT macro

[Jagan Teki]

Replace numerical bit shift with BIT macro
in bfin_spi6xx

:%s/(1 << nr)/BIT(nr)/g
where nr = 0, 1, 2  31

Reviewed-by: Tom Rini 
Signed-off-by: Jagan Teki 
---
 drivers/spi/bfin_spi6xx.c | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/spi/bfin_spi6xx.c b/drivers/spi/bfin_spi6xx.c
index eba01d1..8359d76 100644
--- a/drivers/spi/bfin_spi6xx.c
+++ b/drivers/spi/bfin_spi6xx.c
@@ -63,9 +63,9 @@ void spi_cs_activate(struct spi_slave *slave)
ssel = bfin_read32(>regs->ssel);
ssel |= 1 << slave->cs;
if (bss->cs_pol)
-   ssel |= (1 << 8) << slave->cs;
+   ssel |= BIT(8) << slave->cs;
else
-   ssel &= ~((1 << 8) << slave->cs);
+   ssel &= ~(BIT(8) << slave->cs);
bfin_write32(>regs->ssel, ssel);
}
 
@@ -83,9 +83,9 @@ void spi_cs_deactivate(struct spi_slave *slave)
u32 ssel;
ssel = bfin_read32(>regs->ssel);
if (bss->cs_pol)
-   ssel &= ~((1 << 8) << slave->cs);
+   ssel &= ~(BIT(8) << slave->cs);
else
-   ssel |= (1 << 8) << slave->cs;
+   ssel |= BIT(8) << slave->cs;
/* deassert cs */
bfin_write32(>regs->ssel, ssel);
SSYNC();
-- 
1.9.1

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[U-Boot] [PATCH v5 13/23] spi: tegra: Use BIT macro

[Jagan Teki]

Replace numerical bit shift with BIT macro
in tegra*.c

:%s/(1 << nr)/BIT(nr)/g
where nr = 0, 1, 2  31

Cc: Stephen Warren 
Cc: Tom Warren 
Reviewed-by: Tom Rini 
Signed-off-by: Jagan Teki 
---
 drivers/spi/tegra114_spi.c   | 64 ++--
 drivers/spi/tegra20_sflash.c | 50 +-
 drivers/spi/tegra20_slink.c  | 58 +++
 3 files changed, 86 insertions(+), 86 deletions(-)

diff --git a/drivers/spi/tegra114_spi.c b/drivers/spi/tegra114_spi.c
index a965f80..d9edd11 100644
--- a/drivers/spi/tegra114_spi.c
+++ b/drivers/spi/tegra114_spi.c
@@ -33,54 +33,54 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 /* COMMAND1 */
-#define SPI_CMD1_GO(1 << 31)
-#define SPI_CMD1_M_S   (1 << 30)
+#define SPI_CMD1_GOBIT(31)
+#define SPI_CMD1_M_S   BIT(30)
 #define SPI_CMD1_MODE_MASK 0x3
 #define SPI_CMD1_MODE_SHIFT28
 #define SPI_CMD1_CS_SEL_MASK   0x3
 #define SPI_CMD1_CS_SEL_SHIFT  26
-#define SPI_CMD1_CS_POL_INACTIVE3  (1 << 25)
-#define SPI_CMD1_CS_POL_INACTIVE2  (1 << 24)
-#define SPI_CMD1_CS_POL_INACTIVE1  (1 << 23)
-#define SPI_CMD1_CS_POL_INACTIVE0  (1 << 22)
-#define SPI_CMD1_CS_SW_HW  (1 << 21)
-#define SPI_CMD1_CS_SW_VAL (1 << 20)
+#define SPI_CMD1_CS_POL_INACTIVE3  BIT(25)
+#define SPI_CMD1_CS_POL_INACTIVE2  BIT(24)
+#define SPI_CMD1_CS_POL_INACTIVE1  BIT(23)
+#define SPI_CMD1_CS_POL_INACTIVE0  BIT(22)
+#define SPI_CMD1_CS_SW_HW  BIT(21)
+#define SPI_CMD1_CS_SW_VAL BIT(20)
 #define SPI_CMD1_IDLE_SDA_MASK 0x3
 #define SPI_CMD1_IDLE_SDA_SHIFT18
-#define SPI_CMD1_BIDIR (1 << 17)
-#define SPI_CMD1_LSBI_FE   (1 << 16)
-#define SPI_CMD1_LSBY_FE   (1 << 15)
-#define SPI_CMD1_BOTH_EN_BIT   (1 << 14)
-#define SPI_CMD1_BOTH_EN_BYTE  (1 << 13)
-#define SPI_CMD1_RX_EN (1 << 12)
-#define SPI_CMD1_TX_EN (1 << 11)
-#define SPI_CMD1_PACKED(1 << 5)
+#define SPI_CMD1_BIDIR BIT(17)
+#define SPI_CMD1_LSBI_FE   BIT(16)
+#define SPI_CMD1_LSBY_FE   BIT(15)
+#define SPI_CMD1_BOTH_EN_BIT   BIT(14)
+#define SPI_CMD1_BOTH_EN_BYTE  BIT(13)
+#define SPI_CMD1_RX_EN BIT(12)
+#define SPI_CMD1_TX_EN BIT(11)
+#define SPI_CMD1_PACKEDBIT(5)
 #define SPI_CMD1_BIT_LEN_MASK  0x1F
 #define SPI_CMD1_BIT_LEN_SHIFT 0
 
 /* COMMAND2 */
-#define SPI_CMD2_TX_CLK_TAP_DELAY  (1 << 6)
+#define SPI_CMD2_TX_CLK_TAP_DELAY  BIT(6)
 #define SPI_CMD2_TX_CLK_TAP_DELAY_MASK (0x3F << 6)
-#define SPI_CMD2_RX_CLK_TAP_DELAY  (1 << 0)
+#define SPI_CMD2_RX_CLK_TAP_DELAY  BIT(0)
 #define SPI_CMD2_RX_CLK_TAP_DELAY_MASK (0x3F << 0)
 
 /* TRANSFER STATUS */
-#define SPI_XFER_STS_RDY   (1 << 30)
+#define SPI_XFER_STS_RDY   BIT(30)
 
 /* FIFO STATUS */
-#define SPI_FIFO_STS_CS_INACTIVE   (1 << 31)
-#define SPI_FIFO_STS_FRAME_END (1 << 30)
-#define SPI_FIFO_STS_RX_FIFO_FLUSH (1 << 15)
-#define SPI_FIFO_STS_TX_FIFO_FLUSH (1 << 14)
-#define SPI_FIFO_STS_ERR   (1 << 8)
-#define SPI_FIFO_STS_TX_FIFO_OVF   (1 << 7)
-#define SPI_FIFO_STS_TX_FIFO_UNR   (1 << 6)
-#define SPI_FIFO_STS_RX_FIFO_OVF   (1 << 5)
-#define SPI_FIFO_STS_RX_FIFO_UNR   (1 << 4)
-#define SPI_FIFO_STS_TX_FIFO_FULL  (1 << 3)
-#define SPI_FIFO_STS_TX_FIFO_EMPTY (1 << 2)
-#define SPI_FIFO_STS_RX_FIFO_FULL  (1 << 1)
-#define SPI_FIFO_STS_RX_FIFO_EMPTY (1 << 0)
+#define SPI_FIFO_STS_CS_INACTIVE   BIT(31)
+#define SPI_FIFO_STS_FRAME_END BIT(30)
+#define SPI_FIFO_STS_RX_FIFO_FLUSH BIT(15)
+#define SPI_FIFO_STS_TX_FIFO_FLUSH BIT(14)
+#define SPI_FIFO_STS_ERR   BIT(8)
+#define SPI_FIFO_STS_TX_FIFO_OVF   BIT(7)
+#define SPI_FIFO_STS_TX_FIFO_UNR   BIT(6)
+#define SPI_FIFO_STS_RX_FIFO_OVF   BIT(5)
+#define SPI_FIFO_STS_RX_FIFO_UNR   BIT(4)
+#define SPI_FIFO_STS_TX_FIFO_FULL  BIT(3)
+#define SPI_FIFO_STS_TX_FIFO_EMPTY BIT(2)
+#define SPI_FIFO_STS_RX_FIFO_FULL  BIT(1)
+#define SPI_FIFO_STS_RX_FIFO_EMPTY BIT(0)
 
 #define SPI_TIMEOUT1000
 #define TEGRA_SPI_MAX_FREQ 5200
diff --git a/drivers/spi/tegra20_sflash.c b/drivers/spi/tegra20_sflash.c
index afa0848..5dc196b 100644
--- a/drivers/spi/tegra20_sflash.c
+++ b/drivers/spi/tegra20_sflash.c
@@ -20,37 +20,37 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#define SPI_CMD_GO (1 << 30)
+#define SPI_CMD_GO BIT(30)
 #define SPI_CMD_ACTIVE_SCLK_SHIFT  26
 #define SPI_CMD_ACTIVE_SCLK_MASK   (3 << SPI_CMD_ACTIVE_SCLK_SHIFT)
-#define SPI_CMD_CK_SDA 

[U-Boot] [PATCH v5 14/23] spi: ti_qspi: Use BIT macro

[Jagan Teki]

Replace numerical bit shift with BIT macro
in ti_qspi

:%s/(1 << nr)/BIT(nr)/g
where nr = 0, 1, 2  31

Cc: Vignesh R 
Reviewed-by: Tom Rini 
Signed-off-by: Jagan Teki 
---
 drivers/spi/ti_qspi.c | 10 +-
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c
index bd63db8..ecd9d78 100644
--- a/drivers/spi/ti_qspi.c
+++ b/drivers/spi/ti_qspi.c
@@ -20,13 +20,13 @@
 #define QSPI_TIMEOUT200
 #define QSPI_FCLK   19200
 /* clock control */
-#define QSPI_CLK_EN (1 << 31)
+#define QSPI_CLK_EN BIT(31)
 #define QSPI_CLK_DIV_MAX0x
 /* command */
 #define QSPI_EN_CS(n)   (n << 28)
 #define QSPI_WLEN(n)((n-1) << 19)
-#define QSPI_3_PIN  (1 << 18)
-#define QSPI_RD_SNGL(1 << 16)
+#define QSPI_3_PIN  BIT(18)
+#define QSPI_RD_SNGLBIT(16)
 #define QSPI_WR_SNGL(2 << 16)
 #define QSPI_INVAL  (4 << 16)
 #define QSPI_RD_QUAD(7 << 16)
@@ -36,8 +36,8 @@
 #define QSPI_CSPOL(n)   (1 << (1 + n*8))
 #define QSPI_CKPOL(n)   (1 << (n*8))
 /* status */
-#define QSPI_WC (1 << 1)
-#define QSPI_BUSY   (1 << 0)
+#define QSPI_WC BIT(1)
+#define QSPI_BUSY   BIT(0)
 #define QSPI_WC_BUSY(QSPI_WC | QSPI_BUSY)
 #define QSPI_XFER_DONE  QSPI_WC
 #define MM_SWITCH   0x01
-- 
1.9.1

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[U-Boot] [PATCH v5 08/23] spi: fsl: Use BIT macro

[Jagan Teki]

Replace numerical bit shift with BIT macro
in fsl_*spi.c

:%s/(1 << nr)/BIT(nr)/g
where nr = 0, 1, 2  31

Cc: York Sun 
Cc: Haikun Wang 
Reviewed-by: Tom Rini 
Signed-off-by: Jagan Teki 
---
 drivers/spi/fsl_dspi.c |  2 +-
 drivers/spi/fsl_espi.c | 20 ++--
 drivers/spi/fsl_qspi.c |  4 ++--
 3 files changed, 13 insertions(+), 13 deletions(-)

diff --git a/drivers/spi/fsl_dspi.c b/drivers/spi/fsl_dspi.c
index 887edd8..c8dcb27 100644
--- a/drivers/spi/fsl_dspi.c
+++ b/drivers/spi/fsl_dspi.c
@@ -24,7 +24,7 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 /* fsl_dspi_platdata flags */
-#define DSPI_FLAG_REGMAP_ENDIAN_BIG(1 << 0)
+#define DSPI_FLAG_REGMAP_ENDIAN_BIGBIT(0)
 
 /* idle data value */
 #define DSPI_IDLE_VAL  0x0
diff --git a/drivers/spi/fsl_espi.c b/drivers/spi/fsl_espi.c
index 375dc07..b1586d1 100644
--- a/drivers/spi/fsl_espi.c
+++ b/drivers/spi/fsl_espi.c
@@ -32,26 +32,26 @@ struct fsl_spi_slave {
 #define ESPI_MAX_CS_NUM4
 #define ESPI_FIFO_WIDTH_BIT32
 
-#define ESPI_EV_RNE(1 << 9)
-#define ESPI_EV_TNF(1 << 8)
-#define ESPI_EV_DON(1 << 14)
-#define ESPI_EV_TXE(1 << 15)
+#define ESPI_EV_RNEBIT(9)
+#define ESPI_EV_TNFBIT(8)
+#define ESPI_EV_DONBIT(14)
+#define ESPI_EV_TXEBIT(15)
 #define ESPI_EV_RFCNT_SHIFT24
 #define ESPI_EV_RFCNT_MASK (0x3f << ESPI_EV_RFCNT_SHIFT)
 
-#define ESPI_MODE_EN   (1 << 31)   /* Enable interface */
+#define ESPI_MODE_EN   BIT(31) /* Enable interface */
 #define ESPI_MODE_TXTHR(x) ((x) << 8)  /* Tx FIFO threshold */
 #define ESPI_MODE_RXTHR(x) ((x) << 0)  /* Rx FIFO threshold */
 
 #define ESPI_COM_CS(x) ((x) << 30)
 #define ESPI_COM_TRANLEN(x)((x) << 0)
 
-#define ESPI_CSMODE_CI_INACTIVEHIGH(1 << 31)
-#define ESPI_CSMODE_CP_BEGIN_EDGCLK(1 << 30)
-#define ESPI_CSMODE_REV_MSB_FIRST  (1 << 29)
-#define ESPI_CSMODE_DIV16  (1 << 28)
+#define ESPI_CSMODE_CI_INACTIVEHIGHBIT(31)
+#define ESPI_CSMODE_CP_BEGIN_EDGCLKBIT(30)
+#define ESPI_CSMODE_REV_MSB_FIRST  BIT(29)
+#define ESPI_CSMODE_DIV16  BIT(28)
 #define ESPI_CSMODE_PM(x)  ((x) << 24)
-#define ESPI_CSMODE_POL_ASSERTED_LOW   (1 << 20)
+#define ESPI_CSMODE_POL_ASSERTED_LOW   BIT(20)
 #define ESPI_CSMODE_LEN(x) ((x) << 16)
 #define ESPI_CSMODE_CSBEF(x)   ((x) << 12)
 #define ESPI_CSMODE_CSAFT(x)   ((x) << 8)
diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c
index 868df5f..e1a0ec9 100644
--- a/drivers/spi/fsl_qspi.c
+++ b/drivers/spi/fsl_qspi.c
@@ -68,7 +68,7 @@ DECLARE_GLOBAL_DATA_PTR;
 #define QSPI_CMD_SE_4B 0xdc/* Sector erase (usually 64KiB) */
 
 /* fsl_qspi_platdata flags */
-#define QSPI_FLAG_REGMAP_ENDIAN_BIG(1 << 0)
+#define QSPI_FLAG_REGMAP_ENDIAN_BIGBIT(0)
 
 /* default SCK frequency, unit: HZ */
 #define FSL_QSPI_DEFAULT_SCK_FREQ  5000
@@ -383,7 +383,7 @@ static void qspi_enable_ddr_mode(struct fsl_qspi_priv *priv)
/* Enable the module again (enable the DDR too) */
reg |= QSPI_MCR_DDR_EN_MASK;
/* Enable bit 29 for imx6sx */
-   reg |= (1 << 29);
+   reg |= BIT(29);
 
qspi_write32(priv->flags, >mcr, reg);
 }
-- 
1.9.1

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[U-Boot] [PATCH v5 11/23] spi: omap3_spi: Use BIT macro

[Jagan Teki]

Replace numerical bit shift with BIT macro
in omap3_spi

:%s/(1 << nr)/BIT(nr)/g
where nr = 0, 1, 2  31

Cc: Nikita Kiryanov 
Reviewed-by: Tom Rini 
Signed-off-by: Jagan Teki 
---
 drivers/spi/omap3_spi.h | 48 
 1 file changed, 24 insertions(+), 24 deletions(-)

diff --git a/drivers/spi/omap3_spi.h b/drivers/spi/omap3_spi.h
index 4af22c1..fb02ea1 100644
--- a/drivers/spi/omap3_spi.h
+++ b/drivers/spi/omap3_spi.h
@@ -52,40 +52,40 @@ struct mcspi {
 
 /* per-register bitmasks */
 #define OMAP3_MCSPI_SYSCONFIG_SMARTIDLE (2 << 3)
-#define OMAP3_MCSPI_SYSCONFIG_ENAWAKEUP (1 << 2)
-#define OMAP3_MCSPI_SYSCONFIG_AUTOIDLE (1 << 0)
-#define OMAP3_MCSPI_SYSCONFIG_SOFTRESET (1 << 1)
+#define OMAP3_MCSPI_SYSCONFIG_ENAWAKEUP BIT(2)
+#define OMAP3_MCSPI_SYSCONFIG_AUTOIDLE BIT(0)
+#define OMAP3_MCSPI_SYSCONFIG_SOFTRESET BIT(1)
 
-#define OMAP3_MCSPI_SYSSTATUS_RESETDONE (1 << 0)
+#define OMAP3_MCSPI_SYSSTATUS_RESETDONE BIT(0)
 
-#define OMAP3_MCSPI_MODULCTRL_SINGLE   (1 << 0)
-#define OMAP3_MCSPI_MODULCTRL_MS   (1 << 2)
-#define OMAP3_MCSPI_MODULCTRL_STEST(1 << 3)
+#define OMAP3_MCSPI_MODULCTRL_SINGLE   BIT(0)
+#define OMAP3_MCSPI_MODULCTRL_MS   BIT(2)
+#define OMAP3_MCSPI_MODULCTRL_STESTBIT(3)
 
-#define OMAP3_MCSPI_CHCONF_PHA (1 << 0)
-#define OMAP3_MCSPI_CHCONF_POL (1 << 1)
+#define OMAP3_MCSPI_CHCONF_PHA BIT(0)
+#define OMAP3_MCSPI_CHCONF_POL BIT(1)
 #define OMAP3_MCSPI_CHCONF_CLKD_MASK   (0x0f << 2)
-#define OMAP3_MCSPI_CHCONF_EPOL(1 << 6)
+#define OMAP3_MCSPI_CHCONF_EPOLBIT(6)
 #define OMAP3_MCSPI_CHCONF_WL_MASK (0x1f << 7)
 #define OMAP3_MCSPI_CHCONF_TRM_RX_ONLY (0x01 << 12)
 #define OMAP3_MCSPI_CHCONF_TRM_TX_ONLY (0x02 << 12)
 #define OMAP3_MCSPI_CHCONF_TRM_MASK(0x03 << 12)
-#define OMAP3_MCSPI_CHCONF_DMAW(1 << 14)
-#define OMAP3_MCSPI_CHCONF_DMAR(1 << 15)
-#define OMAP3_MCSPI_CHCONF_DPE0(1 << 16)
-#define OMAP3_MCSPI_CHCONF_DPE1(1 << 17)
-#define OMAP3_MCSPI_CHCONF_IS  (1 << 18)
-#define OMAP3_MCSPI_CHCONF_TURBO   (1 << 19)
-#define OMAP3_MCSPI_CHCONF_FORCE   (1 << 20)
-
-#define OMAP3_MCSPI_CHSTAT_RXS (1 << 0)
-#define OMAP3_MCSPI_CHSTAT_TXS (1 << 1)
-#define OMAP3_MCSPI_CHSTAT_EOT (1 << 2)
-
-#define OMAP3_MCSPI_CHCTRL_EN  (1 << 0)
+#define OMAP3_MCSPI_CHCONF_DMAWBIT(14)
+#define OMAP3_MCSPI_CHCONF_DMARBIT(15)
+#define OMAP3_MCSPI_CHCONF_DPE0BIT(16)
+#define OMAP3_MCSPI_CHCONF_DPE1BIT(17)
+#define OMAP3_MCSPI_CHCONF_IS  BIT(18)
+#define OMAP3_MCSPI_CHCONF_TURBO   BIT(19)
+#define OMAP3_MCSPI_CHCONF_FORCE   BIT(20)
+
+#define OMAP3_MCSPI_CHSTAT_RXS BIT(0)
+#define OMAP3_MCSPI_CHSTAT_TXS BIT(1)
+#define OMAP3_MCSPI_CHSTAT_EOT BIT(2)
+
+#define OMAP3_MCSPI_CHCTRL_EN  BIT(0)
 #define OMAP3_MCSPI_CHCTRL_DIS (0 << 0)
 
-#define OMAP3_MCSPI_WAKEUPENABLE_WKEN  (1 << 0)
+#define OMAP3_MCSPI_WAKEUPENABLE_WKEN  BIT(0)
 
 struct omap3_spi_slave {
struct spi_slave slave;
-- 
1.9.1

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[U-Boot] [PATCH v5 09/23] spi: ich: Use BIT macro

[Jagan Teki]

Replace numerical bit shift with BIT macro
in ich

:%s/(1 << nr)/BIT(nr)/g
where nr = 0, 1, 2  31

Cc: Simon Glass 
Reviewed-by: Tom Rini 
Signed-off-by: Jagan Teki 
---
 drivers/spi/ich.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c
index be4c0a3..af327c4 100644
--- a/drivers/spi/ich.c
+++ b/drivers/spi/ich.c
@@ -692,13 +692,13 @@ static int ich_spi_probe(struct udevice *bus)
 */
if (plat->use_sbase) {
bios_cntl = ich_readb(priv, priv->bcr);
-   bios_cntl &= ~(1 << 5); /* clear Enable InSMM_STS (EISS) */
+   bios_cntl &= ~BIT(5);   /* clear Enable InSMM_STS (EISS) */
bios_cntl |= 1; /* Write Protect Disable (WPD) */
ich_writeb(priv, bios_cntl, priv->bcr);
} else {
pci_read_config_byte(plat->dev, 0xdc, _cntl);
if (plat->ich_version == 9)
-   bios_cntl &= ~(1 << 5);
+   bios_cntl &= ~BIT(5);
pci_write_config_byte(plat->dev, 0xdc, bios_cntl | 0x1);
}
 
-- 
1.9.1

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[U-Boot] [PATCH v5 10/23] spi: mpc8xxx_spi: Use BIT macro

[Jagan Teki]

Replace numerical bit shift with BIT macro
in mpc8xxx_spi

:%s/(1 << nr)/BIT(nr)/g
where nr = 0, 1, 2  31

Reviewed-by: Tom Rini 
Signed-off-by: Jagan Teki 
---
 drivers/spi/mpc8xxx_spi.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/spi/mpc8xxx_spi.c b/drivers/spi/mpc8xxx_spi.c
index 0d59c36..00cbcbf 100644
--- a/drivers/spi/mpc8xxx_spi.c
+++ b/drivers/spi/mpc8xxx_spi.c
@@ -55,7 +55,7 @@ void spi_init(void)
 * some registers
 */
spi->mode = SPI_MODE_REV | SPI_MODE_MS | SPI_MODE_EN;
-   spi->mode = (spi->mode & 0xfff0) | (1 << 16); /* Use SYSCLK / 8
+   spi->mode = (spi->mode & 0xfff0) | BIT(16); /* Use SYSCLK / 8
 (16.67MHz typ.) */
spi->event = 0x;/* Clear all SPI events */
spi->mask = 0x; /* Mask  all SPI interrupts */
-- 
1.9.1

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[U-Boot] [PATCH v5 18/23] spi: designware_spi: Use GENMASK

[Jagan Teki]

Replace numeric mask hexcodes with GENMASK macro
in designware_spi

Cc: Stefan Roese 
Cc: Marek Vasut 
Reviewed-by: Tom Rini 
Signed-off-by: Jagan Teki 
---
 drivers/spi/designware_spi.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/spi/designware_spi.c b/drivers/spi/designware_spi.c
index 7885e46..24a6e98 100644
--- a/drivers/spi/designware_spi.c
+++ b/drivers/spi/designware_spi.c
@@ -74,7 +74,7 @@ DECLARE_GLOBAL_DATA_PTR;
 #define SPI_CFS_OFFSET 12
 
 /* Bit fields in SR, 7 bits */
-#define SR_MASK0x7f/* cover 7 bits 
*/
+#define SR_MASKGENMASK(6, 0)   /* cover 7 bits 
*/
 #define SR_BUSYBIT(0)
 #define SR_TF_NOT_FULL BIT(1)
 #define SR_TF_EMPT BIT(2)
-- 
1.9.1

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[U-Boot] [PATCH v5 19/23] spi: fsl_qspi: Use GENMASK

[Jagan Teki]

Replace numeric mask hexcodes with GENMASK macro
in fsl_qspi

Cc: York Sun 
Cc: Haikun Wang 
Signed-off-by: Jagan Teki 
---
 drivers/spi/fsl_qspi.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c
index e1a0ec9..10733df 100644
--- a/drivers/spi/fsl_qspi.c
+++ b/drivers/spi/fsl_qspi.c
@@ -24,7 +24,7 @@ DECLARE_GLOBAL_DATA_PTR;
 #define TX_BUFFER_SIZE 0x40
 #endif
 
-#define OFFSET_BITS_MASK   0x00ff
+#define OFFSET_BITS_MASK   GENMASK(24, 0)
 
 #define FLASH_STATUS_WEL   0x02
 
-- 
1.9.1

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[U-Boot] [PATCH v5 16/23] spi: atmel_spi: Use GENMASK

[Jagan Teki]

Replace numeric mask hexcodes with GENMASK macro
in atmel_spi

Cc: Bo Shen 
Reviewed-by: Tom Rini 
Signed-off-by: Jagan Teki 
---
 drivers/spi/atmel_spi.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/spi/atmel_spi.h b/drivers/spi/atmel_spi.h
index 5b892d2..76b8556 100644
--- a/drivers/spi/atmel_spi.h
+++ b/drivers/spi/atmel_spi.h
@@ -59,7 +59,7 @@
 #define ATMEL_SPI_CSRx_CSAAT   BIT(3)
 #define ATMEL_SPI_CSRx_BITS(x) ((x) << 4)
 #define ATMEL_SPI_CSRx_SCBR(x) ((x) << 8)
-#define ATMEL_SPI_CSRx_SCBR_MAX0xff
+#define ATMEL_SPI_CSRx_SCBR_MAXGENMASK(7, 0)
 #define ATMEL_SPI_CSRx_DLYBS(x)((x) << 16)
 #define ATMEL_SPI_CSRx_DLYBCT(x)   ((x) << 24)
 
-- 
1.9.1

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[U-Boot] [PATCH v5 15/23] spi: xilinx_spi: Use BIT macro

[Jagan Teki]

Replace numerical bit shift with BIT macro
in xilinx_spi

:%s/(1 << nr)/BIT(nr)/g
where nr = 0, 1, 2  31

Cc: Michal Simek 
Reviewed-by: Tom Rini 
Signed-off-by: Jagan Teki 
---
 drivers/spi/xilinx_spi.c | 32 
 1 file changed, 16 insertions(+), 16 deletions(-)

diff --git a/drivers/spi/xilinx_spi.c b/drivers/spi/xilinx_spi.c
index 8ccc578..7620163 100644
--- a/drivers/spi/xilinx_spi.c
+++ b/drivers/spi/xilinx_spi.c
@@ -32,24 +32,24 @@
  */
 
 /* SPI Control Register (spicr), [1] p9, [2] p8 */
-#define SPICR_LSB_FIRST(1 << 9)
-#define SPICR_MASTER_INHIBIT   (1 << 8)
-#define SPICR_MANUAL_SS(1 << 7)
-#define SPICR_RXFIFO_RESEST(1 << 6)
-#define SPICR_TXFIFO_RESEST(1 << 5)
-#define SPICR_CPHA (1 << 4)
-#define SPICR_CPOL (1 << 3)
-#define SPICR_MASTER_MODE  (1 << 2)
-#define SPICR_SPE  (1 << 1)
-#define SPICR_LOOP (1 << 0)
+#define SPICR_LSB_FIRSTBIT(9)
+#define SPICR_MASTER_INHIBIT   BIT(8)
+#define SPICR_MANUAL_SSBIT(7)
+#define SPICR_RXFIFO_RESESTBIT(6)
+#define SPICR_TXFIFO_RESESTBIT(5)
+#define SPICR_CPHA BIT(4)
+#define SPICR_CPOL BIT(3)
+#define SPICR_MASTER_MODE  BIT(2)
+#define SPICR_SPE  BIT(1)
+#define SPICR_LOOP BIT(0)
 
 /* SPI Status Register (spisr), [1] p11, [2] p10 */
-#define SPISR_SLAVE_MODE_SELECT(1 << 5)
-#define SPISR_MODF (1 << 4)
-#define SPISR_TX_FULL  (1 << 3)
-#define SPISR_TX_EMPTY (1 << 2)
-#define SPISR_RX_FULL  (1 << 1)
-#define SPISR_RX_EMPTY (1 << 0)
+#define SPISR_SLAVE_MODE_SELECTBIT(5)
+#define SPISR_MODF BIT(4)
+#define SPISR_TX_FULL  BIT(3)
+#define SPISR_TX_EMPTY BIT(2)
+#define SPISR_RX_FULL  BIT(1)
+#define SPISR_RX_EMPTY BIT(0)
 
 /* SPI Data Transmit Register (spidtr), [1] p12, [2] p12 */
 #define SPIDTR_8BIT_MASK   (0xff << 0)
-- 
1.9.1

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[U-Boot] [PATCH v5 07/23] spi: designware_spi: Use BIT macro

[Jagan Teki]

Replace numerical bit shift with BIT macro
in designware_spi

:%s/(1 << nr)/BIT(nr)/g
where nr = 0, 1, 2  31

Cc: Stefan Roese 
Cc: Marek Vasut 
Signed-off-by: Jagan Teki 
---
 drivers/spi/designware_spi.c | 14 +++---
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/drivers/spi/designware_spi.c b/drivers/spi/designware_spi.c
index 86ee90f..7885e46 100644
--- a/drivers/spi/designware_spi.c
+++ b/drivers/spi/designware_spi.c
@@ -75,13 +75,13 @@ DECLARE_GLOBAL_DATA_PTR;
 
 /* Bit fields in SR, 7 bits */
 #define SR_MASK0x7f/* cover 7 bits 
*/
-#define SR_BUSY(1 << 0)
-#define SR_TF_NOT_FULL (1 << 1)
-#define SR_TF_EMPT (1 << 2)
-#define SR_RF_NOT_EMPT (1 << 3)
-#define SR_RF_FULL (1 << 4)
-#define SR_TX_ERR  (1 << 5)
-#define SR_DCOL(1 << 6)
+#define SR_BUSYBIT(0)
+#define SR_TF_NOT_FULL BIT(1)
+#define SR_TF_EMPT BIT(2)
+#define SR_RF_NOT_EMPT BIT(3)
+#define SR_RF_FULL BIT(4)
+#define SR_TX_ERR  BIT(5)
+#define SR_DCOLBIT(6)
 
 #define RX_TIMEOUT 1000/* timeout in ms */
 
-- 
1.9.1

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[U-Boot] [PATCH v5 12/23] spi: sh_qspi: Use BIT macro

[Jagan Teki]

Replace numerical bit shift with BIT macro
in sh_qspi

:%s/(1 << nr)/BIT(nr)/g
where nr = 0, 1, 2  31

Cc: Nobuhiro Iwamatsu 
Reviewed-by: Tom Rini 
Signed-off-by: Jagan Teki 
---
 drivers/spi/sh_qspi.c | 16 
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/drivers/spi/sh_qspi.c b/drivers/spi/sh_qspi.c
index 77ede6b..7209e1d 100644
--- a/drivers/spi/sh_qspi.c
+++ b/drivers/spi/sh_qspi.c
@@ -21,19 +21,19 @@
 #define SPPCR_IO3FV0x04
 #define SPPCR_IO2FV0x02
 #define SPPCR_IO1FV0x01
-#define SPBDCR_RXBC0   (1 << 0)
-#define SPCMD_SCKDEN   (1 << 15)
-#define SPCMD_SLNDEN   (1 << 14)
-#define SPCMD_SPNDEN   (1 << 13)
-#define SPCMD_SSLKP(1 << 7)
-#define SPCMD_BRDV0(1 << 2)
+#define SPBDCR_RXBC0   BIT(0)
+#define SPCMD_SCKDEN   BIT(15)
+#define SPCMD_SLNDEN   BIT(14)
+#define SPCMD_SPNDEN   BIT(13)
+#define SPCMD_SSLKPBIT(7)
+#define SPCMD_BRDV0BIT(2)
 #define SPCMD_INIT1SPCMD_SCKDEN | SPCMD_SLNDEN | \
SPCMD_SPNDEN | SPCMD_SSLKP | \
SPCMD_BRDV0
 #define SPCMD_INIT2SPCMD_SPNDEN | SPCMD_SSLKP | \
SPCMD_BRDV0
-#define SPBFCR_TXRST   (1 << 7)
-#define SPBFCR_RXRST   (1 << 6)
+#define SPBFCR_TXRST   BIT(7)
+#define SPBFCR_RXRST   BIT(6)
 
 /* SH QSPI register set */
 struct sh_qspi_regs {
-- 
1.9.1

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Re: [U-Boot] [PATCH] mtd: pxa3xx_nand: Correct allocation and init bug

[Scott Wood]

On Fri, 2015-10-23 at 19:56 +, Kevin Smith wrote:
> Hi Scott,
> 
> On 10/23/2015 01:20 PM, Scott Wood wrote:
> > 
> > Yuck.  Could you please rework this driver to not play games with pointers
> > and one giant allocation?  Why can't this function allocate each region it
> > needs separately?
> > 
> > -Scott
> > 
> This driver is taken from Linux.  There are a few API modifications to 
> make it work in U-Boot, but the main form and function of the driver is 
> the same.  The single allocation method is used by Linux and is kept 
> here in U-boot.

Sigh... At least do this in alloc_nand_resources() the way Linux does, rather 
than taking it a step further and allocating an array of these blobs.

> As for why Linux does this, it may be for cache coherency, avoiding
> memory fragmentation, speed (fewer calls to malloc), or something else.  
> I agree it is kind of opaque, but is probably done for a good reason.

I'm sure there was a reason but that doesn't mean it was a good reason.  I 
don't understand how cache coherency would be relevant, nor do I agree that 
trying to optimize a boot path to have fewer malloc calls at the expense of 
making the code more complicated is a "good reason".

>   I didn't port the driver, and I don't know if the reason is applicable to
> U-Boot or if a rework is appropriate.  Maybe Stefan can comment?
> 
> Either way, I am not able to rework it right now.  I think my patch 
> fixes a legitimate issue.  (It at least fixes the crashes I was 
> experiencing).  I hope it can be accepted as-is.

Does Linux have this problem?  Assuming no, please fix this by making the 
driver look more like Linux.  At least then it would be the same ugliness.

Can you explain how the change in the calculation of "chip" and the 
allocation size is relevant to the NULL dereference?  Couldn't that be fixed 
by just removing the "info->host[0]->mtd" line?

-Scott

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