Hi Josh,
Thank you for your review.
> -Original Message-
> From: Wu, Josh
> Sent: 2015年11月5日 10:54
> To: Yang, Wenyou; U-Boot Mailing List
> Subject: Re: [U-Boot] [PATCH 2/3] arm: at91/spl: matrix: improve
> implementation
> of matrix
>
> Hi, Wenyou
>
> On 11/4/2015 2:28 PM, Wenyou Yan
On 5 November 2015 at 13:03, Hannes Schmelzer wrote:
> Hi Jagan,
>
> did you take notice about that?
> Maybe i've not seen your answer.
I will get my hardware next week, sure we can discuss this.
>
>
> On 15.10.2015 10:39, Hannes Schmelzer wrote:
>>
>>
>> Hi Jagan,
>>
>> during bringing up QSPI
Hi Josh,
Thank you for your review.
> -Original Message-
> From: Wu, Josh
> Sent: 2015年11月5日 10:59
> To: Yang, Wenyou; U-Boot Mailing List
> Subject: Re: [U-Boot] [PATCH 3/3] arm: at91: spl/atmel_sfr: move saic
> redirect to
> separate file
>
> Hi, Wenyou
>
> On 11/4/2015 2:28 PM, Weny
Hi Josh,
Thank you for your review.
> -Original Message-
> From: Wu, Josh
> Sent: 2015年11月5日 10:53
> To: Yang, Wenyou; U-Boot Mailing List
> Subject: Re: [U-Boot] [PATCH 1/3] arm: at91/spl: matrix: move matrix init to
> separate file
>
> Hi, Wenyou
>
> On 11/4/2015 2:28 PM, Wenyou Yang
On Tue, 3 Nov 2015 23:23:38 -0800
Bin Meng wrote:
> DEV_EXT_VIDEO does not have any actual meaning, hence drop it.
>
> Signed-off-by: Bin Meng
>
> ---
>
> arch/powerpc/cpu/mpc8xx/video.c | 1 -
> board/bf527-ezkit/video.c | 1 -
> board/bf533-stamp/video.c | 1 -
> board/bf548-e
On Tue, 3 Nov 2015 23:23:37 -0800
Bin Meng wrote:
> DEV_FLAGS_SYSTEM does not have any actual meaning, hence drop it.
>
> Signed-off-by: Bin Meng
> ---
>
> arch/blackfin/cpu/jtag-console.c | 2 +-
> board/bf527-ezkit/video.c| 1 -
> board/bf533-stamp/video.c| 1 -
> board/bf5
On Thu, 29 Oct 2015 15:54:39 +0800
Peng Fan wrote:
> Change mxs_set_lcdclk prototype to add a new parameter
> base_addr. There are two LCD interfaces for i.MX6SX,
> we may support LCDIF1 or LCDIF2.
>
> Signed-off-by: Peng Fan
> Cc: Stefano Babic
> Cc: Anatolij Gustschin
> ---
>
> V3:
> Add
Hi Jagan,
did you take notice about that?
Maybe i've not seen your answer.
regards,
Hannes
On 15.10.2015 10:39, Hannes Schmelzer wrote:
Hi Jagan,
during bringing up QSPI within SPL on my ZYNQ ZC702 board i made some
review of your code.
Have a look.
On 01.09.2015 08:11, Jagan Teki wrote:
On Thu, 29 Oct 2015 15:54:49 +0800
Peng Fan wrote:
> Introudce a new function lcdif_power_down.
>
> 1. Waits for a VSYNC interrupt to guarantee the reset is done at the
>VSYNC edge, which somehow makes the LCDIF consume the display FIFO(?)
>and helps the LCDIF work normally at the kernel
On 11/05/2015 01:28 AM, Nishanth Menon wrote:
> When the vendor common libraries exists, then board should be able to
> reference headers located there, rather than having to do weird logic
> such as '#include "../common/xyz.h"'.
>
> Signed-off-by: Nishanth Menon
> ---
>
> Makefile
When the vendor common libraries exists, then board should be able to
reference headers located there, rather than having to do weird logic
such as '#include "../common/xyz.h"'.
Signed-off-by: Nishanth Menon
---
Makefile| 1 +
board/ti/am57xx/board.c | 2 +-
2 files changed, 2 i
Yes, it's an erratum. But I don't have the erratum number from the document. I
will connect the hardware team to check whether there is an erratum number.
Thanks.
Best Regards,
Yuan Yao
> -Original Message-
> From: York Sun [mailto:york...@freescale.com]
> Sent: Thursday, November 05,
On 11/05/2015 12:00 AM, Lokesh Vutla wrote:
[...]
>> diff --git a/board/ti/common/board.h b/board/ti/common/board.h
>> new file mode 100644
>> index ..19d63cad82f9
>> --- /dev/null
>> +++ b/board/ti/common/board.h
>
> May be keep this header file under arch/arm/include/asm/ so that it
Dear Tom,
The following changes since commit 0e067a65f57189703668826d9841fea477026bf6:
x86: Select the ns16550 debug UART for minnowmax, chromebook_link (2015-10-30
18:04:14 -0400)
are available in the git repository at:
http://git.denx.de/u-boot-samsung
for you to fetch changes up to 58
2015년 11월 5일 목요일, Przemyslaw Marczak님이 작성한 메시지:
> Commit: sandbox: add ADC driver
>
> adds the driver without its main header file.
> It causes build brake for sandbox_defonfig.
>
> This commit adds a missing header:
> - include/sandbox-adc.h
>
> Signed-off-by: Przemyslaw Marczak >
> Cc: Minkyu Ka
If the core runs at higher than x3 speed of the platform, there is
possiblity about sev instruction to getting missed by other cores.
This is because of SoC Run Control block may not able to sample
the EVENTI(Sev) signals.
Configure Run Control and EPU to periodically send out EVENTI signals to
wa
On Thursday 05 November 2015 03:30 AM, Steve Kipisz wrote:
> From: Lokesh Vutla
>
> Several TI EVMs have EEPROM that can contain board description information
> such as revision, DDR definition, serial number, etc. In just about all
> cases, these EEPROM are on the I2C bus and provides us the o
On Thursday 05 November 2015 03:30 AM, Steve Kipisz wrote:
> Many TI EVMs have capability to store relevant board information
> such as DDR description in EEPROM. Further many pad configuration
> variations can occur as part of revision changes in the platform.
> In-order to support these at runt
On Thursday 05 November 2015 03:30 AM, Steve Kipisz wrote:
> Centralize gpi2c_init into omap_common from the sys_proto header so
> that the information can be reused across SoCs.
Reviewed-by: Lokesh Vutla
Thanks and regards,
Lokesh
>
> Signed-off-by: Steve Kipisz
> Reviewed-by: Tom Rini
> -
On Thursday 05 November 2015 03:30 AM, Steve Kipisz wrote:
> Early clock initialization is currently done in two stages for OMAP4/5
> SoCs. The first stage is the initialization of console clocks and
> then we initialize basic clocks for functionality necessary for SoC
> initialization and basic
Hi Chin Liang,
On 2015年11月04日 22:27, Chin Liang See wrote:
+#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MONITOR_BASE - \
+CONFIG_ENV_SIZE - \
+CONFIG_SYS_MALLOC_LEN -\
Since CONFIG_ENV_IS_IN_FLASH, I
On Thursday, November 05, 2015 at 04:17:38 AM, Ye.Li wrote:
> All the i.MX6, i.MX23 and i.MX28 OTG controllers only support UTMI
> interface. Set to ULPI is not correct, even the controller will reject
> this
> setting in PORTSC register.
>
> Signed-off-by: Ye.Li
> ---
> drivers/usb/gadget/ci_ud
+Simon,
Hi,
On Thu, Nov 5, 2015 at 7:45 AM, Scott Wood wrote:
> On Mon, 2015-11-02 at 19:15 +0800, Gong Qianyu wrote:
>> diff --git a/drivers/pci/pcie_layerscape.c b/drivers/pci/pcie_layerscape.c
>> index 4cee038..8471678 100644
>> --- a/drivers/pci/pcie_layerscape.c
>> +++ b/drivers/pci/pcie_la
On 11/04/2015 05:43 PM, Nishanth Menon wrote:
[...]
>> index 5cd6873f5e97..9d85d31b2cf1 100644
>> --- a/board/ti/am57xx/Makefile
>> +++ b/board/ti/am57xx/Makefile
>> @@ -6,3 +6,5 @@
>> #
>>
>> obj-y := board.o
>> +obj-y += ../common/board.o
>
One final comment on the ../common/boa
On Thursday, November 05, 2015 at 05:26:25 AM, Thomas Chou wrote:
> HI Chin Liang,
>
> On 2015年11月05日 11:05, Chin Liang See wrote:
> > I notice you are writing in word style which might have concern in
> > performance. As the burst count can go up to 64, we can write larger
> > data th
HI Chin Liang,
On 2015年11月05日 11:05, Chin Liang See wrote:
I notice you are writing in word style which might have concern in
performance. As the burst count can go up to 64, we can write larger
data through memcpy. This will avoid redundancy of data header (opcode
+ address + dummy).
You cann
> -Original Message-
> From: York Sun [mailto:york...@freescale.com]
> Sent: Thursday, November 05, 2015 9:38 AM
> To: Kushwaha Prabhakar-B32579 ; u-
> b...@lists.denx.de
> Subject: Re: [PATCH][v2] armv8: ls2085a: Add workaround of errata A009635
>
>
>
> On 11/04/2015 07:58 PM, Kushwaha
DPMACx to PHY mapping for SGMII is mentioned as QSGMII.
So fix typo in README for QSGMII rise card.
Signed-off-by: Prabhakar Kushwaha
---
board/freescale/ls2085aqds/README | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/board/freescale/ls2085aqds/README
b/board/freescale/ls
On 11/04/2015 07:58 PM, Kushwaha Prabhakar-B32579 wrote:
>
>> -Original Message-
>> From: York Sun [mailto:york...@freescale.com]
>> Sent: Thursday, November 05, 2015 12:27 AM
>> To: Kushwaha Prabhakar-B32579 ; u-
>> b...@lists.denx.de
>> Subject: Re: [PATCH][v2] armv8: ls2085a: Add work
> -Original Message-
> From: York Sun [mailto:york...@freescale.com]
> Sent: Thursday, November 05, 2015 12:27 AM
> To: Kushwaha Prabhakar-B32579 ; u-
> b...@lists.denx.de
> Subject: Re: [PATCH][v2] armv8: ls2085a: Add workaround of errata A009635
>
>
>
> On 11/03/2015 11:24 PM, Prabhak
All the i.MX6, i.MX23 and i.MX28 OTG controllers only support UTMI interface.
Set to ULPI is not correct, even the controller will reject this
setting in PORTSC register.
Signed-off-by: Ye.Li
---
drivers/usb/gadget/ci_udc.c | 12
1 files changed, 0 insertions(+), 12 deletions(-)
On Thu, Nov 5, 2015 at 2:54 AM, Stephen Warren wrote:
> On 10/30/2015 05:07 AM, Ivan Mercier wrote:
>>
>> Hi,
>>
>> I'm using a ethernet controller intel i210
>> (http://www.commell.com.tw/product/Surveillance/MPX-210.htm) on my
>> nvidia tegra k1 jetson.
>
>
> (You didn't actually CC anyone invol
As 3G/1G user/kernel memory split is used on LS1021A, the Linux kernel
fails to access the device tree blob on boot. The reason is that u-boot
relocates the device tree blob into high memory when booting the kernel
and the kernel is unable to access the blob.
To avoid this issue, fdt_high is set t
For most device addresses excution shouldn't be allowed. Revise
the MMU table to enforce execute-never bits. OCRAM, DDR and IFC
are allowed for excution.
Signed-off-by: York Sun
Signed-off-by: Alison Wang
Reported-by: Zhichun Hua
---
arch/arm/cpu/armv8/cache_v8.c | 4 +-
arch
On Thu, 2015-11-05 at 03:53 +0100, ma...@denx.de wrote:
> On Thursday, November 05, 2015 at 03:49:18 AM, Chin Liang See wrote:
> > Hi Marek,
> >
> > On Wed, 2015-11-04 at 10:18 +, ma...@denx.de wrote:
> > > On Wednesday, November 04, 2015 at 04:56:10 PM, Chin Liang See wrote:
> > > > On Tue, 2
Hi, Wenyou
On 11/4/2015 2:28 PM, Wenyou Yang wrote:
To make saic redirect code sharing with other SoCs, move the
saic redirect code from SAMA5D4 particular file,
mach-at91/armv7/sama5d4_devices.c to a separate file,
mach-at91/atmel_sfr.c
maybe move it as mach-at91/armv7/atmel_sfr.c?
Best Rega
Hi, Wenyou
On 11/4/2015 2:28 PM, Wenyou Yang wrote:
To make matrix initialization code sharing with others,
use the matrix slave id macros, instead of hard-coding.
it is better if you split the following 'removing code' as another patch.
Best Regards,
Josh Wu
Remove the write protection mode
Hi, Wenyou
On 11/4/2015 2:28 PM, Wenyou Yang wrote:
To make the matrix initialization code sharing with other SoCs,
move it from SAMA5D4 particular file,
mach-at91/armv7/sama5d4_devices.c to a separate file,
mach-at91/matrix.c
is it possible just move it to mach-at91/armv7/matrix.c, as it is onl
On Thursday, November 05, 2015 at 03:49:18 AM, Chin Liang See wrote:
> Hi Marek,
>
> On Wed, 2015-11-04 at 10:18 +, ma...@denx.de wrote:
> > On Wednesday, November 04, 2015 at 04:56:10 PM, Chin Liang See wrote:
> > > On Tue, 2015-11-03 at 21:22 +0800, tho...@wytron.com.tw wrote:
> > > > Add Al
The following changes since commit 96d59e9d6aa74e35c63dc74da10e41f8ba0f6de4:
mpc85xx/t2081: enable parsing DDR ratio for T2081 rev1.1 (2015-11-02 08:51:50
-0800)
are available in the git repository at:
git://git.denx.de/u-boot-usb.git
for you to fetch changes up to f6fcebf5c181365a3c9ebc6
The following changes since commit 96d59e9d6aa74e35c63dc74da10e41f8ba0f6de4:
mpc85xx/t2081: enable parsing DDR ratio for T2081 rev1.1 (2015-11-02 08:51:50
-0800)
are available in the git repository at:
git://git.denx.de/u-boot-socfpga.git
for you to fetch changes up to a55f28624e97e1e43ac
Hi Marek,
On Wed, 2015-11-04 at 10:18 +, ma...@denx.de wrote:
> On Wednesday, November 04, 2015 at 04:56:10 PM, Chin Liang See wrote:
> > On Tue, 2015-11-03 at 21:22 +0800, tho...@wytron.com.tw wrote:
> > > Add Altera Generic Quad SPI Controller support. The controller
> > > converts SPI NOR f
On Thu, 2015-11-05 at 02:34 +0100, ma...@denx.de wrote:
> On Wednesday, November 04, 2015 at 03:51:56 PM, Chin Liang See wrote:
> > On Sat, 2015-10-17 at 16:14 +0200, ma...@denx.de wrote:
> > > On Saturday, October 17, 2015 at 03:32:38 PM, Chin Liang See wrote:
> > > > Ensure the intended SCLK freq
Hi Colin,
On Tue, Oct 27, 2015 at 02:00:24PM -0700, Colin Cross wrote:
> On Monday, October 12, 2015 at 6:43:37 AM UTC-7, Maxime Ripard wrote:
> >
> > Hi,
> >
> > I'm currently writing the support in U-Boot for NAND-backed devices
> > using fastboot [1], and that work derived a bit to supporting
On Wednesday, November 04, 2015 at 03:51:56 PM, Chin Liang See wrote:
> On Sat, 2015-10-17 at 16:14 +0200, ma...@denx.de wrote:
> > On Saturday, October 17, 2015 at 03:32:38 PM, Chin Liang See wrote:
> > > Ensure the intended SCLK frequency not exceeding the maximum
> > > frequency. If that happen,
>From 3af52a1a6d71ac3d78e0dec56da2fd8eb07a91d1 Mon Sep 17 00:00:00 2001
From: Adam Ford
Date: Wed, 4 Nov 2015 17:13:15 -0600
Subject: [PATCH] omap3_logic: Cleanup and remove redundant defines make bootz
easier
Some unnecesary includes still exist from the initial conversion
to ti_omap3_common.h
On Mon, 2015-11-02 at 19:15 +0800, Gong Qianyu wrote:
> diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fdt.h
> b/arch/arm/include/asm/arch-fsl-layerscape/fdt.h
> index 4da73ab..e3989a8 100644
> --- a/arch/arm/include/asm/arch-fsl-layerscape/fdt.h
> +++ b/arch/arm/include/asm/arch-fsl-layer
On 11/04/2015 04:00 PM, Steve Kipisz wrote:
> Several TI EVMs have onboard EEPROM that contain board description
> information. The onboard EEPROM on Beaglebone, Beaglebone Black, AM335x
> EVM, AM43x EVM, AM57xx EVM, Beagleboard-x15 all share the same format.
>
> This series of patches introduces
On Mon, 2015-11-02 at 19:15 +0800, Gong Qianyu wrote:
> Reuse dts files from ls1043a linux kernel. Some parts in dts files
> may not be needed by U-Boot.
>
> Signed-off-by: Gong Qianyu
> ---
> V2:
> - New Patch.
>
> arch/arm/dts/Makefile| 1 +
> arch/arm/dts/fsl-ls1043a-rdb.dts |
On Mon, 2015-11-02 at 19:15 +0800, Gong Qianyu wrote:
> diff --git a/drivers/pci/pcie_layerscape.c b/drivers/pci/pcie_layerscape.c
> index 4cee038..8471678 100644
> --- a/drivers/pci/pcie_layerscape.c
> +++ b/drivers/pci/pcie_layerscape.c
> @@ -13,6 +13,7 @@
> #include
> #ifdef CONFIG_FSL_LAYERS
On Wed, Nov 04, 2015 at 03:24:09PM -0800, York Sun wrote:
> Tom,
>
> The following changes since commit 83bf005710a1e01341de5e2f44a3ce082717e313:
>
> arm: at91: reworked meesc board support (2015-11-03 14:21:32 +0100)
>
> are available in the git repository at:
>
> git://git.denx.de/u-boot
On 11/04/2015 04:00 PM, Steve Kipisz wrote:
> From: Lokesh Vutla
>
> Several TI EVMs have EEPROM that can contain board description information
> such as revision, DDR definition, serial number, etc. In just about all
> cases, these EEPROM are on the I2C bus and provides us the opportunity
> to c
Oops. Clicked send button too fast. Adding mailing list.
Forwarded Message
Subject: Please pull u-boot-mpc85xx master
Date: Wed, 4 Nov 2015 15:24:09 -0800
From: York Sun
To: Tom Rini
Tom,
The following changes since commit 83bf005710a1e01341de5e2f44a3ce082717e313:
arm: at
On 11/04/2015 01:48 PM, Andy Fleming wrote:
> This board runs a P5020 or P5040 chip, and utilizes
> an EEPROM with similar formatting to the Freescale P5020DS.
>
> Large amounts of this code were developed by
> Adrian Cox
>
> Signed-off-by: Andy Fleming
> ---
> v3:
> * Clarified sys_eep
On 10/21/2015 04:59 PM, Andy Fleming wrote:
> The code is from Adrian Cox, and is patterned after similar
> support in Linux (drivers/rtc/rtc-ds1307.c:1121-1135). This
> chip is used on the Cyrus board from Varisys.
>
> Signed-off-by: Andy Fleming
> ---
> drivers/rtc/Makefile | 2 +-
> driver
On Wed, Nov 04, 2015 at 02:34:42PM -0800, York Sun wrote:
>
>
> On 10/21/2015 04:59 PM, Andy Fleming wrote:
> > The code is from Adrian Cox, and is patterned after similar
> > support in Linux (drivers/rtc/rtc-ds1307.c:1121-1135). This
> > chip is used on the Cyrus board from Varisys.
> >
> > Si
On 10/21/2015 04:59 PM, Andy Fleming wrote:
> The code is from Adrian Cox, and is patterned after similar
> support in Linux (drivers/rtc/rtc-ds1307.c:1121-1135). This
> chip is used on the Cyrus board from Varisys.
>
> Signed-off-by: Andy Fleming
> ---
> drivers/rtc/Makefile | 2 +-
> driver
On Wed, Nov 04, 2015 at 03:48:33PM +0100, Michal Simek wrote:
> Hi Tom,
>
> please pull these patches to your tree. They are enabling DM for Zynq
> and ZynqMP targets and also they are fixing compilation error which is
> currently in the tree.
> Also as I have promised I am removing zc70x target
From: Lokesh Vutla
Several TI EVMs have EEPROM that can contain board description information
such as revision, DDR definition, serial number, etc. In just about all
cases, these EEPROM are on the I2C bus and provides us the opportunity
to centralize the generic operations involved.
The on-board
Current AM57xx evm supports both BeagleBoard-X15
(http://beagleboard.org/x15) and AM57xx EVM
(http://www.ti.com/tool/tmdxevm5728).
The AM572x EValuation Module(EVM) provides an affordable platform to
quickly start evaluation of Sitara. ARM Cortex-A15 AM57x Processors
(AM5728, AM5726, AM5718, AM571
Centralize gpi2c_init into omap_common from the sys_proto header so
that the information can be reused across SoCs.
Signed-off-by: Steve Kipisz
Reviewed-by: Tom Rini
---
v3 Based on:
master 83bf0057 arm: at91: reworked meesc board support
Changes in v3 (since v2):
- No changes
v2: http:
Many TI EVMs have capability to store relevant board information
such as DDR description in EEPROM. Further many pad configuration
variations can occur as part of revision changes in the platform.
In-order to support these at runtime, we for a board detection hook
which is available for override fr
Several TI EVMs have onboard EEPROM that contain board description
information. The onboard EEPROM on Beaglebone, Beaglebone Black, AM335x
EVM, AM43x EVM, AM57xx EVM, Beagleboard-x15 all share the same format.
This series of patches introduces code which is generic among these
platforms. The board
Early clock initialization is currently done in two stages for OMAP4/5
SoCs. The first stage is the initialization of console clocks and
then we initialize basic clocks for functionality necessary for SoC
initialization and basic board functionality.
By splitting up prcm_init and centralizing this
Looks like one spot got missed. Probably due to the backslash.
Signed-off-by: Andy Fleming
---
Noticed this while reading up on the MAINTAINERS files
scripts/get_maintainer.pl | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/scripts/get_maintainer.pl b/scripts/get_maintainer.
This board runs a P5020 or P5040 chip, and utilizes
an EEPROM with similar formatting to the Freescale P5020DS.
Large amounts of this code were developed by
Adrian Cox
Signed-off-by: Andy Fleming
---
v3:
* Clarified sys_eeprom.c comments
* Removed errant whitespace
* Add
On Wed, Nov 4, 2015 at 12:39 PM, York Sun wrote:
>
>
> On 11/03/2015 03:30 PM, Andy Fleming wrote:
>> This board runs a P5020 or P5040 chip, and utilizes
>> an EEPROM with similar formatting to the Freescale P5020DS.
>>
>> Large amounts of this code were developed by
>> Adrian Cox
>>
>> Signed-of
On 11/03/2015 11:24 PM, Prabhakar Kushwaha wrote:
> If the core runs at higher than x3 speed of the platform, there is
> possiblity about sev instruction to getting missed by other cores.
> This is because of SoC Run Control block may not able to sample
> the EVENTI(Sev) signals.
>
> Configure
On 10/30/2015 05:07 AM, Ivan Mercier wrote:
Hi,
I'm using a ethernet controller intel i210
(http://www.commell.com.tw/product/Surveillance/MPX-210.htm) on my
nvidia tegra k1 jetson.
(You didn't actually CC anyone involved with Tegra, so I only
accidentally noticed this while I was looking at
On 10/21/2015 03:14 AM, Yuan Yao wrote:
> EDDRTQCFG Registers are Integration Strap values which controls
> performance parameters for DDR Controller.
>
> The bit 25 is used to disable priorities within DDR since DDR
> are connected backwards on Rev2.0.
>
> Signed-off-by: Yuan Yao
> ---
> arc
On 10/21/2015 03:14 AM, Yuan Yao wrote:
> Affects: DDR
> Description: Memory controller performance is not optimal with default
> internal target queue register values.
> Impact: Memory controller performance is not optimal.
> Workaround: Write a value of 63b2_0002h to address: 157_020Ch.
>
>
Pl
On 11/03/2015 03:30 PM, Andy Fleming wrote:
> This board runs a P5020 or P5040 chip, and utilizes
> an EEPROM with similar formatting to the Freescale P5020DS.
>
> Large amounts of this code were developed by
> Adrian Cox
>
> Signed-off-by: Andy Fleming
> ---
> v2:
> * Cleaned up sys_ee
Hi Thomas,
On Wed, Nov 4, 2015 at 6:28 AM, Thomas Chou wrote:
> Get numbers of fdt address and size cells in altera_tse_probe(),
> thereby remove the assumption of one address cell and one size
> cell.
>
> Signed-off-by: Thomas Chou
> ---
Acked-by: Joe Hershberger
_
On Wed, Nov 4, 2015 at 7:40 AM, Michal Simek wrote:
> On 11/02/2015 10:39 PM, Joe Hershberger wrote:
>> On Tue, Oct 27, 2015 at 10:17 AM, Michal Simek
>> wrote:
>>> Based on spec:
>>> "MDC must not exceed 2.5 MHz (MDC is only active during MDIO read and
>>> write operations)"
>>> Zynq is running
When 4 chip-selects are used, vref should use range 1 and CDT uses 80 ohm,
and 2T timing is enabled.
Signed-off-by: York Sun
---
board/freescale/ls2085ardb/ddr.c | 16
1 file changed, 12 insertions(+), 4 deletions(-)
diff --git a/board/freescale/ls2085ardb/ddr.c b/board/fre
For four chip-selects enabled case, RTT is parked on all of them.
Signed-off-by: York Sun
---
drivers/ddr/fsl/ctrl_regs.c | 19 +++
1 file changed, 15 insertions(+), 4 deletions(-)
diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c
index 36bf647..99714bf 1
In case four chip-selects are all active, the turnaround times need to
increase to avoid overlapping under heavy load.
Signed-off-by: York Sun
---
drivers/ddr/fsl/ctrl_regs.c | 26 --
1 file changed, 24 insertions(+), 2 deletions(-)
diff --git a/drivers/ddr/fsl/ctrl_r
MR6 bit 6 is set accrodingly for range 1 or 2, per JEDEC spec.
Signed-off-by: York Sun
---
drivers/ddr/fsl/ctrl_regs.c |3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c
index 8543679..36bf647 100644
--- a/drivers/ddr/fsl/ctrl_reg
When 4 chip-selects are used, vref should use range 1 and CDT uses 80 ohm,
and 2T timing is enabled.
Signed-off-by: York Sun
---
board/freescale/ls2085aqds/ddr.c | 16
1 file changed, 12 insertions(+), 4 deletions(-)
diff --git a/board/freescale/ls2085aqds/ddr.c b/board/free
The workaround requires different setting for range 1 vs 2.
Also adjust timeout value for waiting for controller to be idle.
Signed-off-by: York Sun
---
drivers/ddr/fsl/fsl_ddr_gen4.c | 22 +++---
1 file changed, 15 insertions(+), 7 deletions(-)
diff --git a/drivers/ddr/fsl/f
This patch set revises the DDR driver to support higher speed for DDR4
under heavy load (two dual-rank DIMMs) for four-chipselect interleaving.
Single quad-rank DIMM is not supported yet.
York Sun (7):
driver/ddr/fsl: Update DDR4 RTT values
driver/ddr/fsl: Update DDR4 MR6 for Vref range
dri
DDR4 has different RTT value and code according to JEDEC spec. Update
the macros and options .
Signed-off-by: York Sun
---
drivers/ddr/fsl/options.c | 237 -
include/fsl_ddr_sdram.h |9 ++
2 files changed, 244 insertions(+), 2 deletions(-)
dif
Am 04.11.2015 um 18:13 schrieb Fabio Estevam:
> From: Fabio Estevam
>
> The generic bitops headers are required when calling logarithimic
> functions, such as ilog2().
>
> Signed-off-by: Fabio Estevam
> ---
> Applies against u-boot-spi next
>
> arch/mips/include/asm/bitops.h | 5 +
> 1
Freescale LSCH3 platforms use two DDR controlers interleaving mode out of
reset. It can be configured to disable one controller. To support this
operation, the driver needs to detect and skip the disabled controller.
Signed-off-by: York Sun
---
Change log
v1: Initial patch. Tested on LS2085AQD
On 11/04/2015 11:13 AM, Fabio Estevam wrote:
> From: Fabio Estevam
>
> The generic bitops headers are required when calling logarithimic
> functions, such as ilog2().
>
s/logarithimic/logarithmic
Same comment for 2/4 and 3/4
Dinh
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On Thursday, October 15, 2015 04:55:55 PM Tom Rini wrote:
> On Thu, Oct 15, 2015 at 03:52:08AM +0200, Andreas Färber wrote:
> > Am 15.10.2015 um 02:40 schrieb Tom Rini:
> > > On Thu, Oct 15, 2015 at 02:28:34AM +0200, Andreas Färber wrote:
> > >> Am 12.10.2015 um 17:18 schrieb Tom Rini:
> > >>> If y
Commit: sandbox: add ADC driver
adds the driver without its main header file.
It causes build brake for sandbox_defonfig.
This commit adds a missing header:
- include/sandbox-adc.h
Signed-off-by: Przemyslaw Marczak
Cc: Minkyu Kang
Cc: Simon Glass
---
include/sandbox-adc.h | 31 ++
Hello Minkyu,
On 11/04/2015 04:43 PM, Minkyu Kang wrote:
Dear Przemyslaw Marczak,
On 4 November 2015 at 18:37, Przemyslaw Marczak mailto:p.marc...@samsung.com>> wrote:
Hello Minkyu,
On 11/04/2015 03:05 AM, Minkyu Kang wrote:
Dear Przemyslaw Marczak,
2015년 11월 4일 수요일,
From: Fabio Estevam
Let the function and its prototype use the same variable type for 'len'.
Signed-off-by: Fabio Estevam
---
Applies against u-boot-spi next
drivers/mtd/spi/sf_ops.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/mtd/spi/sf_ops.c b/drivers/mtd
From: Fabio Estevam
The generic bitops headers are required when calling logarithimic
functions, such as ilog2().
Signed-off-by: Fabio Estevam
---
Applies against u-boot-spi next
arch/avr32/include/asm/bitops.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/avr32/include/asm/bi
From: Fabio Estevam
The generic bitops headers are required when calling logarithimic
functions, such as ilog2().
Signed-off-by: Fabio Estevam
---
Applies against u-boot-spi next
arch/mips/include/asm/bitops.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/mips/include/asm/bito
From: Fabio Estevam
The generic bitops headers are required when calling logarithimic
functions, such as ilog2().
Signed-off-by: Fabio Estevam
---
Applies against u-boot-spi next
arch/arc/include/asm/bitops.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arc/include/asm/bitops
On 4 November 2015 at 21:52, Chin Liang See wrote:
> On Wed, 2015-11-04 at 17:12 +0800, tho...@wytron.com.tw wrote:
>> Replace numerical bit shift with BIT macro
>> in altera_tse
>>
>> :%s/(1 << nr)/BIT(nr)/g
>> where nr = 0, 1, 2 31
>>
>> Signed-off-by: Thomas Chou
>> ---
>
>
> Reviewed-by:
On Wed, 2015-11-04 at 17:12 +0800, tho...@wytron.com.tw wrote:
> Replace numerical bit shift with BIT macro
> in altera_tse
>
> :%s/(1 << nr)/BIT(nr)/g
> where nr = 0, 1, 2 31
>
> Signed-off-by: Thomas Chou
> ---
Reviewed-by: Chin Liang See
Thanks
Chin Liang
___
On Wed, 2015-11-04 at 17:12 +0800, tho...@wytron.com.tw wrote:
> Remove unused macro.
>
> Signed-off-by: Thomas Chou
> ---
Reviewed-by: Chin Liang See
Thanks
Chin Liang
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On Wed, 2015-11-04 at 03:29 +, tho...@wytron.com.tw wrote:
> Remove the useless parenthesis.
>
> Signed-off-by: Thomas Chou
> ---
Reviewed-by: Chin Liang See
Thanks
Chin Liang
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On Wednesday, November 04, 2015 at 04:56:10 PM, Chin Liang See wrote:
> On Tue, 2015-11-03 at 21:22 +0800, tho...@wytron.com.tw wrote:
> > Add Altera Generic Quad SPI Controller support. The controller
> > converts SPI NOR flash to parallel flash interface. So it is
> > not like other SPI flash, bu
Hi Thomas,
On Wed, 2015-11-04 at 17:12 +0800, tho...@wytron.com.tw wrote:
> fix CamelCase.
>
> CHECK: Avoid CamelCase:
> #170: FILE: drivers/net/altera_tse.h:170:
> + u32 aMACID_1; /*The MAC addresses */
>
> Signed-off-by: Thomas Chou
> ---
> drivers/net/altera_tse.h | 81
> ++
On Wed, 2015-11-04 at 17:12 +0800, tho...@wytron.com.tw wrote:
> Fix packed and aligned attribute warnings.
>
> WARNING: __packed is preferred over __attribute__((packed))
> #14: FILE: drivers/net/altera_tse.h:14:
> +#define __packed_1___attribute__ ((packed, aligned(1)))
>
> WARNING: __align
On Wed, 2015-11-04 at 17:12 +0800, tho...@wytron.com.tw wrote:
> Use data type u32/u16/u8 for regs and desc, as it is more
> portable.
>
> Signed-off-by: Thomas Chou
Reviewed-by: Chin Liang See
Thanks
Chin Liang
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