Re: [U-Boot] [PATCH 3/5] fsl: usb: make errata function common for PPC and ARM

[Sriram Dash]

>-Original Message-
>From: Marek Vasut [mailto:ma...@denx.de]
>Sent: Thursday, May 26, 2016 5:51 PM
>To: Sriram Dash ; u-boot@lists.denx.de
>Cc: york sun ; albert.u.b...@aribaud.net; Rajesh Bhagat
>
>Subject: Re: [PATCH 3/5] fsl: usb: make errata function common for PPC and ARM
>
>On 05/26/2016 07:59 AM, Sriram Dash wrote:
>
>Since there is no commit message, I have no clue what the rationale for this 
>patch
>is, sorry. Please explain.
>

This patch adds support for ARM for the errata applicability checking code.
Will take care in v2.

>Besides, I would much rather see a patch which moves all these static inline
>functions into a dedicated C file and converts this header into just a list of
>prototypes. I wouldn't be surprised if the U-Boot size dropped a bit too.
>

Will move the function definitions to a new file in v2.
Shall I place the file in drivers/usb/common/fsl_usb.c or 
drivers/usb/host/fsl_usb.c
and keep fsl_usb.h at same place.

Please suggest.

>> Signed-off-by: Sriram Dash 
>> Signed-off-by: Rajesh Bhagat 
>> ---
>>  drivers/usb/common/fsl-dt-fixup.c |  1 +
>>  include/fsl_usb.h | 51 
>> ---
>>  2 files changed, 17 insertions(+), 35 deletions(-)
>>
>> diff --git a/drivers/usb/common/fsl-dt-fixup.c
>> b/drivers/usb/common/fsl-dt-fixup.c
>> index 520130e..47e1049 100644
>> --- a/drivers/usb/common/fsl-dt-fixup.c
>> +++ b/drivers/usb/common/fsl-dt-fixup.c
>> @@ -12,6 +12,7 @@
>>  #include 
>>  #include 
>>  #include 
>> +#include 
>>  #include 
>>  #include 
>>
>> diff --git a/include/fsl_usb.h b/include/fsl_usb.h index
>> 187e384..d9db0ea 100644
>> --- a/include/fsl_usb.h
>> +++ b/include/fsl_usb.h
>> @@ -86,13 +86,14 @@ struct ccsr_usb_phy {  #endif
>>
>>  /* USB Erratum Checking code */
>> -#ifdef CONFIG_PPC
>> +#if defined(CONFIG_PPC) || defined(CONFIG_ARM)
>>  static inline bool has_dual_phy(void)  {
>>  u32 svr = get_svr();
>>  u32 soc = SVR_SOC_VER(svr);
>>
>>  switch (soc) {
>> +#ifdef CONFIG_PPC
>>  case SVR_T1023:
>>  case SVR_T1024:
>>  case SVR_T1013:
>> @@ -109,6 +110,7 @@ static inline bool has_dual_phy(void)
>>  case SVR_T4160:
>>  case SVR_T4080:
>>  return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0);
>> +#endif
>>  }
>>
>>  return false;
>> @@ -120,6 +122,7 @@ static inline bool has_erratum_a006261(void)
>>  u32 soc = SVR_SOC_VER(svr);
>>
>>  switch (soc) {
>> +#ifdef CONFIG_PPC
>>  case SVR_P1010:
>>  return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0);
>>  case SVR_P2041:
>> @@ -145,6 +148,7 @@ static inline bool has_erratum_a006261(void)
>>  return IS_SVR_REV(svr, 1, 0);
>>  case SVR_P5040:
>>  return IS_SVR_REV(svr, 1, 0);
>> +#endif
>>  }
>>
>>  return false;
>> @@ -156,6 +160,7 @@ static inline bool has_erratum_a007075(void)
>>  u32 soc = SVR_SOC_VER(svr);
>>
>>  switch (soc) {
>> +#ifdef CONFIG_PPC
>>  case SVR_B4860:
>>  case SVR_B4420:
>>  return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0); @@ 
>> -163,14
>> +168,18 @@ static inline bool has_erratum_a007075(void)
>>  return IS_SVR_REV(svr, 1, 0);
>>  case SVR_P4080:
>>  return IS_SVR_REV(svr, 2, 0) || IS_SVR_REV(svr, 3, 0);
>> +#endif
>>  }
>>  return false;
>>  }
>>
>>  static inline bool has_erratum_a007798(void)  {
>> +#ifdef CONFIG_PPC
>>  return SVR_SOC_VER(get_svr()) == SVR_T4240 &&
>>  IS_SVR_REV(get_svr(), 2, 0);
>> +#endif
>> +return false;
>>  }
>>
>>  static inline bool has_erratum_a007792(void) @@ -179,6 +188,7 @@
>> static inline bool has_erratum_a007792(void)
>>  u32 soc = SVR_SOC_VER(svr);
>>
>>  switch (soc) {
>> +#ifdef CONFIG_PPC
>>  case SVR_T4240:
>>  case SVR_T4160:
>>  case SVR_T4080:
>> @@ -193,6 +203,7 @@ static inline bool has_erratum_a007792(void)
>>  case SVR_T2080:
>>  case SVR_T2081:
>>  return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 1, 1);
>> +#endif
>>  }
>>  return false;
>>  }
>> @@ -203,9 +214,11 @@ static inline bool has_erratum_a005697(void)
>>  u32 soc = SVR_SOC_VER(svr);
>>
>>  switch (soc) {
>> +#ifdef CONFIG_PPC
>>  case SVR_9131:
>>  case SVR_9132:
>>  return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 1, 1);
>> +#endif
>>  }
>>  return false;
>>  }
>> @@ -216,6 +229,7 @@ static inline bool has_erratum_a004477(void)
>>  u32 soc = SVR_SOC_VER(svr);
>>
>>  switch (soc) {
>> +#ifdef CONFIG_PPC
>>  case SVR_P1010:
>>  return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0);
>>  case SVR_P1022:
>> @@ -230,44 +244,11 @@ static inline bool has_erratum_a004477(void)
>>  return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0);
>>  case SVR_P4080:
>>  return IS_SVR_REV(svr, 2, 0) || 

Re: [U-Boot] [PATCH v2 03/11] ARM: PSCI: export common PSCI function declarations for C code

[Chen-Yu Tsai]

On Fri, May 27, 2016 at 12:49 AM, Marc Zyngier  wrote:
> On 26/05/16 15:01, Chen-Yu Tsai wrote:
>> Some common PSCI functions are written in assembly, but it should be
>> possible to use them from C code.
>>
>> Add function declarations for C code to consume.
>>
>> Signed-off-by: Chen-Yu Tsai 
>> ---
>>  arch/arm/include/asm/psci.h | 8 
>>  1 file changed, 8 insertions(+)
>>
>> diff --git a/arch/arm/include/asm/psci.h b/arch/arm/include/asm/psci.h
>> index 128a606444fe..8b245139cbdb 100644
>> --- a/arch/arm/include/asm/psci.h
>> +++ b/arch/arm/include/asm/psci.h
>> @@ -33,6 +33,14 @@
>>  #define ARM_PSCI_RET_DENIED  (-3)
>>
>>  #ifndef __ASSEMBLY__
>> +#include 
>> +#include 
>
> nit: you don't need any of these #include.

I think  is still needed for u32?
Unless there's some compiler magic I don't know about.

I'll drop the other one.

ChenYu

>
>> +
>> +void psci_cpu_entry(void);
>> +u32 psci_get_cpu_id(void);
>> +u32 psci_get_cpu_stack_top(int cpu);
>> +void psci_cpu_off_common(void);
>> +
>>  int psci_update_dt(void *fdt);
>>  void psci_board_init(void);
>>  #endif /* ! __ASSEMBLY__ */
>>
>
> Thanks,
>
> M.
> --
> Jazz is not dead. It just smells funny...
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Re: [U-Boot] [PATCH v2 11/11] sunxi: Add PSCI implementation in C

[Chen-Yu Tsai]

On Fri, May 27, 2016 at 1:19 AM, Marc Zyngier  wrote:
> On 26/05/16 15:01, Chen-Yu Tsai wrote:
>> To make the PSCI backend more maintainable and easier to port to newer
>> SoCs, rewrite the current PSCI implementation in C.
>>
>> Some inline assembly bits are required to access coprocessor registers.
>> PSCI stack setup is the only part left completely in assembly. In theory
>> this part could be split out of psci_arch_init into a separate common
>> function, and psci_arch_init could be completely in C.
>>
>> Signed-off-by: Chen-Yu Tsai 
>> ---
>>  arch/arm/cpu/armv7/sunxi/Makefile |   7 +-
>>  arch/arm/cpu/armv7/sunxi/psci.c   | 269 
>> ++
>>  arch/arm/cpu/armv7/sunxi/psci_head.S  |  66 +
>>  arch/arm/cpu/armv7/sunxi/psci_sun6i.S | 262 
>> -
>>  arch/arm/cpu/armv7/sunxi/psci_sun7i.S | 237 --
>>  5 files changed, 337 insertions(+), 504 deletions(-)
>>  create mode 100644 arch/arm/cpu/armv7/sunxi/psci.c
>>  create mode 100644 arch/arm/cpu/armv7/sunxi/psci_head.S
>>  delete mode 100644 arch/arm/cpu/armv7/sunxi/psci_sun6i.S
>>  delete mode 100644 arch/arm/cpu/armv7/sunxi/psci_sun7i.S
>>
>> diff --git a/arch/arm/cpu/armv7/sunxi/Makefile 
>> b/arch/arm/cpu/armv7/sunxi/Makefile
>> index 4d2274a38ed1..c2085101685b 100644
>> --- a/arch/arm/cpu/armv7/sunxi/Makefile
>> +++ b/arch/arm/cpu/armv7/sunxi/Makefile
>> @@ -13,11 +13,8 @@ obj-$(CONFIG_MACH_SUN6I)   += tzpc.o
>>  obj-$(CONFIG_MACH_SUN8I_H3)  += tzpc.o
>>
>>  ifndef CONFIG_SPL_BUILD
>> -ifdef CONFIG_ARMV7_PSCI
>> -obj-$(CONFIG_MACH_SUN6I) += psci_sun6i.o
>> -obj-$(CONFIG_MACH_SUN7I) += psci_sun7i.o
>> -obj-$(CONFIG_MACH_SUN8I) += psci_sun6i.o
>> -endif
>> +obj-$(CONFIG_ARMV7_PSCI) += psci.o
>> +obj-$(CONFIG_ARMV7_PSCI) += psci_head.o
>>  endif
>>
>>  ifdef CONFIG_SPL_BUILD
>> diff --git a/arch/arm/cpu/armv7/sunxi/psci.c 
>> b/arch/arm/cpu/armv7/sunxi/psci.c
>> new file mode 100644
>> index ..f0c151a349c8
>> --- /dev/null
>> +++ b/arch/arm/cpu/armv7/sunxi/psci.c
>> @@ -0,0 +1,269 @@
>> +/*
>> + * Copyright (C) 2016
>> + * Author: Chen-Yu Tsai 
>> + *
>> + * Based on assembly code by Marc Zyngier ,
>> + * which was based on code by Carl van Schaik .
>> + *
>> + * SPDX-License-Identifier:  GPL-2.0
>> + */
>> +#include 
>> +#include 
>> +
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +
>> +#include 
>> +
>> +#define __secure __attribute__ ((section ("._secure.text")))
>> +#define __irq__attribute__ ((interrupt ("IRQ")))
>> +
>> +#define  GICD_BASE   (SUNXI_GIC400_BASE + GIC_DIST_OFFSET)
>> +#define  GICC_BASE   (SUNXI_GIC400_BASE + GIC_CPU_OFFSET_A15)
>> +
>> +static void cp15_write_cntp_tval(u32 tval)
>> +{
>> + asm volatile ("mcr p15, 0, %0, c14, c2, 0" : : "r" (tval));
>> +}
>> +
>> +static void cp15_write_cntp_ctl(u32 val)
>> +{
>> + asm volatile ("mcr p15, 0, %0, c14, c2, 1" : : "r" (val));
>> +}
>> +
>> +static u32 cp15_read_cntp_ctl(void)
>> +{
>> + u32 val;
>> +
>> + asm volatile ("mrc p15, 0, %0, c14, c2, 1" : "=r" (val));
>> +
>> + return val;
>> +}
>> +
>> +static void __secure __mdelay(u32 ms)
>> +{
>> + u32 reg = DIV_ROUND_UP(CONFIG_TIMER_CLK_FREQ, ms);
>> +
>> + cp15_write_cntp_tval(reg);
>> + ISB;
>> + cp15_write_cntp_ctl(3);
>> +
>> + do {
>> + ISB;
>> + reg = cp15_read_cntp_ctl();
>> + } while (!(reg & BIT(2)));
>> +
>> + cp15_write_cntp_ctl(0);
>> +}
>> +
>> +#ifdef CONFIG_MACH_SUN7I
>> +/* sun7i (A20) is different from other single cluster SoCs */
>> +static void sunxi_cpu_set_power(int __always_unused cpu, bool on)
>
> Missing __secure annotation?

Right. This worked because the compiler inlined the whole thing.
I'll add it.

>
>> +{
>> + struct sunxi_cpucfg_reg *cpucfg =
>> + (struct sunxi_cpucfg_reg *)SUNXI_CPUCFG_BASE;
>> +
>> + if (on) {
>> + /* Release power clamp */
>> + u32 tmp = 0x1ff;
>> + do {
>> + tmp >>= 1;
>> + writel(tmp, >cpu1_pwr_clamp);
>> + } while (tmp);
>> +
>> + __mdelay(10);
>> +
>> + /* Clear power gating */
>> + clrbits_le32(>cpu1_pwroff, BIT(0));
>> + } else {
>> + /* Set power gating */
>> + setbits_le32(>cpu1_pwroff, BIT(0));
>> +
>> + /* Activate power clamp */
>> + writel(0xff, >cpu1_pwr_clamp);
>> + }
>> +}
>> +#else /* ! CONFIG_MACH_SUN7I */
>> +static void sunxi_cpu_set_power(int cpu, bool on)
>
> Same here?
>
>> +{
>> + struct sunxi_prcm_reg *prcm =
>> + (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
>> +
>> + if (on) {
>> +#if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN8I_H3)
>> + 

Re: [U-Boot] [PATCH v2 6/8] x86: quark: Generate ACPI FADT/MADT tables

[Bin Meng]

On Thu, May 26, 2016 at 10:19 AM, Bin Meng  wrote:
> Generate quark platform-specific FADT/MADT tables.
>
> Signed-off-by: Bin Meng 
> Reviewed-by: Simon Glass 
> ---
>
> Changes in v2: None
>
>  arch/x86/cpu/quark/Makefile |   1 +
>  arch/x86/cpu/quark/acpi.c   | 163 
> 
>  2 files changed, 164 insertions(+)
>  create mode 100644 arch/x86/cpu/quark/acpi.c
>

applied to u-boot-x86, thanks!
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Re: [U-Boot] [PATCH v2 7/8] x86: galileo: Enable ACPI table generation

[Bin Meng]

On Thu, May 26, 2016 at 10:19 AM, Bin Meng  wrote:
> Enable ACPI table generation by creating a DSDT table.
>
> Signed-off-by: Bin Meng 
> Reviewed-by: Simon Glass 
> ---
>
> Changes in v2: None
>
>  board/intel/galileo/.gitignore |  3 +++
>  board/intel/galileo/Makefile   |  1 +
>  board/intel/galileo/acpi/mainboard.asl | 11 +++
>  board/intel/galileo/dsdt.asl   | 14 ++
>  configs/galileo_defconfig  |  1 +
>  doc/README.x86 |  5 -
>  6 files changed, 34 insertions(+), 1 deletion(-)
>  create mode 100644 board/intel/galileo/.gitignore
>  create mode 100644 board/intel/galileo/acpi/mainboard.asl
>  create mode 100644 board/intel/galileo/dsdt.asl
>

applied to u-boot-x86, thanks!
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Re: [U-Boot] [PATCH v2 8/8] x86: baytrail: acpi: Fix I/O APIC ID in the MADT table

[Bin Meng]

On Thu, May 26, 2016 at 10:19 AM, Bin Meng  wrote:
> So far this is hardcoded to 2, but it should really be read
> from the I/O APIC register.
>
> Signed-off-by: Bin Meng 
> Reviewed-by: Simon Glass 
>
> ---
>
> Changes in v2: None
>
>  arch/x86/cpu/baytrail/acpi.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>

applied to u-boot-x86, thanks!
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Re: [U-Boot] [PATCH v2 5/8] x86: quark: Add platform ASL files

[Bin Meng]

On Thu, May 26, 2016 at 10:19 AM, Bin Meng  wrote:
> This adds basic quark platform ASL files. They are intended to be
> included in dsdt.asl of any board that is based on this platform.
>
> Signed-off-by: Bin Meng 
> Reviewed-by: Simon Glass 
> ---
>
> Changes in v2: None
>
>  arch/x86/include/asm/arch-quark/acpi/irqroute.h|  15 ++
>  arch/x86/include/asm/arch-quark/acpi/lpc.asl   | 125 ++
>  arch/x86/include/asm/arch-quark/acpi/platform.asl  |  33 
>  .../include/asm/arch-quark/acpi/sleepstates.asl|  10 ++
>  .../include/asm/arch-quark/acpi/southcluster.asl   | 184 
> +
>  arch/x86/include/asm/arch-quark/iomap.h|  47 ++
>  arch/x86/include/asm/arch-quark/irq.h  |  19 +++
>  7 files changed, 433 insertions(+)
>  create mode 100644 arch/x86/include/asm/arch-quark/acpi/irqroute.h
>  create mode 100644 arch/x86/include/asm/arch-quark/acpi/lpc.asl
>  create mode 100644 arch/x86/include/asm/arch-quark/acpi/platform.asl
>  create mode 100644 arch/x86/include/asm/arch-quark/acpi/sleepstates.asl
>  create mode 100644 arch/x86/include/asm/arch-quark/acpi/southcluster.asl
>  create mode 100644 arch/x86/include/asm/arch-quark/iomap.h
>  create mode 100644 arch/x86/include/asm/arch-quark/irq.h
>

applied to u-boot-x86, thanks!
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Re: [U-Boot] [PATCH v2 4/8] x86: quark: Prepare device.h for inclusion by ASL

[Bin Meng]

On Thu, May 26, 2016 at 10:19 AM, Bin Meng  wrote:
> There is a device.h for quark on-chip devices, mainly for definitions
> of internal PCI device numbers, but it's not ready to be included by
> ASL files. Update to use hex numbers for PCI dev and __ASSEMBLY__.
>
> Signed-off-by: Bin Meng 
> Reviewed-by: Simon Glass 
>
> ---
>
> Changes in v2:
> - Use __ASSEMBLY__ in device.h
>
>  arch/x86/include/asm/arch-quark/device.h | 21 +++--
>  1 file changed, 15 insertions(+), 6 deletions(-)
>

applied to u-boot-x86, thanks!
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Re: [U-Boot] [PATCH v2 2/8] x86: acpi: Make irqroute.asl common

[Bin Meng]

On Thu, May 26, 2016 at 10:19 AM, Bin Meng  wrote:
> The irqroute.asl file is already common enough to all x86 platforms.
> Platform ASL files need only provide a irqroute.h to describe how
> internal PCI devices and PCIe downstream port devices' INTx pins are
> routed to which PIRQ pin.
>
> Signed-off-by: Bin Meng 
> Reviewed-by: Simon Glass 
> ---
>
> Changes in v2: None
>
>  arch/x86/include/asm/{arch-baytrail => }/acpi/irq_helper.h | 2 +-
>  arch/x86/include/asm/{arch-baytrail => }/acpi/irqroute.asl | 0
>  arch/x86/include/asm/arch-baytrail/acpi/southcluster.asl   | 2 +-
>  3 files changed, 2 insertions(+), 2 deletions(-)
>  rename arch/x86/include/asm/{arch-baytrail => }/acpi/irq_helper.h (98%)
>  rename arch/x86/include/asm/{arch-baytrail => }/acpi/irqroute.asl (100%)
>

applied to u-boot-x86, thanks!
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Re: [U-Boot] [PATCH v2 1/8] x86: acpi: Create a common irqlinks ASL file

[Bin Meng]

On Thu, May 26, 2016 at 10:19 AM, Bin Meng  wrote:
> Move the irqlinks.asl file currently in the BayTrail directory to
> a common place to be shared among all x86 platforms. As the PIRQ
> routing control programming interface is common to Intel chipsets,
> leave the common part in the common file, and move the platform
> specific part to the platform files.
>
> Signed-off-by: Bin Meng 
> Reviewed-by: Simon Glass 
> ---
>
> Changes in v2: None
>
>  .../asm/{arch-baytrail => }/acpi/irqlinks.asl  | 33 
> +-
>  arch/x86/include/asm/arch-baytrail/acpi/lpc.asl| 23 ++-
>  2 files changed, 35 insertions(+), 21 deletions(-)
>  rename arch/x86/include/asm/{arch-baytrail => }/acpi/irqlinks.asl (92%)
>

applied to u-boot-x86, thanks!
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Re: [U-Boot] [PATCH v2 3/8] acpi: Pass -D__ASSEMBLY__ when compiling ASL files

[Bin Meng]

On Thu, May 26, 2016 at 10:19 AM, Bin Meng  wrote:
> ASL files may include various U-Boot header files, but IASL compiler
> does not understand any C language embedded in these header files.
> To reuse those header files for ASL compiling, use __ASSEMBLY__ in
> the header files to exclude everything that is not liked by IASL.
>
> Signed-off-by: Bin Meng 
> Reviewed-by: Simon Glass 
>
> ---
>
> Changes in v2:
> - Use __ASSEMBLY__ define
>
>  scripts/Makefile.lib | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>

applied to u-boot-x86, thanks!
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Re: [U-Boot] [PATCH v2 1/2] powerpc/mpc85xx: SECURE BOOT- Enable chain of trust in SPL

[Teddy Reed]

The build/config changes to common/drivers/lib are more general than
the powerpc/mpc85xx board support and IMO should be represented in a
separate patch.

Check out: https://www.mail-archive.com/u-boot@lists.denx.de/msg211374.html
for an example set of needed changes.

I mentioned before that I'm happy to resubmit that patch to
generically support an SPL-based verified boot. :) I haven't seen any
requested changes, and it is almost 100% mimicking Simon's, so that
gives me a bit of assurance. ;)

On Wed, May 25, 2016 at 9:40 AM, Sumit Garg  wrote:
> As part of Chain of Trust for Secure boot, the SPL U-Boot will validate
> the next level U-boot image. Add a new function spl_validate_uboot to
> perform the validation.
>
> Enable hardware crypto operations in SPL using SEC block.
> In case of Secure Boot, PAMU is not bypassed. For allowing SEC block
> access to CPC configured as SRAM, configure PAMU.
>
> Reviewed-by: Ruchika Gupta 
> Signed-off-by: Aneesh Bansal 
> Signed-off-by: Sumit Garg 
> ---
> Changes in v2:
> Patches rebased
>
>  arch/powerpc/cpu/mpc8xxx/fsl_pamu.c |  8 +
>  arch/powerpc/cpu/mpc8xxx/pamu_table.c   |  8 +
>  arch/powerpc/include/asm/fsl_secure_boot.h  | 26 +++
>  board/freescale/common/fsl_chain_of_trust.c | 50 
> +
>  common/Makefile |  2 ++
>  drivers/Makefile|  1 +
>  drivers/crypto/fsl/jr.c | 16 +
>  drivers/mtd/nand/fsl_ifc_spl.c  | 24 ++
>  include/fsl_validate.h  |  1 +
>  lib/Makefile|  3 ++
>  10 files changed, 139 insertions(+)
>
> diff --git a/arch/powerpc/cpu/mpc8xxx/fsl_pamu.c 
> b/arch/powerpc/cpu/mpc8xxx/fsl_pamu.c
> index 9421f1e..ede8e66 100644
> --- a/arch/powerpc/cpu/mpc8xxx/fsl_pamu.c
> +++ b/arch/powerpc/cpu/mpc8xxx/fsl_pamu.c
> @@ -239,15 +239,23 @@ int pamu_init(void)
> spaact_size = sizeof(struct paace) * NUM_SPAACT_ENTRIES;
>
> /* Allocate space for Primary PAACT Table */
> +#if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_PPAACT_ADDR))
> +   ppaact = (void *)CONFIG_SPL_PPAACT_ADDR;
> +#else
> ppaact = memalign(PAMU_TABLE_ALIGNMENT, ppaact_size);
> if (!ppaact)
> return -1;
> +#endif
> memset(ppaact, 0, ppaact_size);
>
> /* Allocate space for Secondary PAACT Table */
> +#if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SPAACT_ADDR))
> +   sec = (void *)CONFIG_SPL_SPAACT_ADDR;
> +#else
> sec = memalign(PAMU_TABLE_ALIGNMENT, spaact_size);
> if (!sec)
> return -1;
> +#endif
> memset(sec, 0, spaact_size);
>
> ppaact_phys = virt_to_phys((void *)ppaact);
> diff --git a/arch/powerpc/cpu/mpc8xxx/pamu_table.c 
> b/arch/powerpc/cpu/mpc8xxx/pamu_table.c
> index 26c5ea4..a8e6f51 100644
> --- a/arch/powerpc/cpu/mpc8xxx/pamu_table.c
> +++ b/arch/powerpc/cpu/mpc8xxx/pamu_table.c
> @@ -28,6 +28,14 @@ void construct_pamu_addr_table(struct pamu_addr_tbl *tbl, 
> int *num_entries)
>
> i++;
>  #endif
> +#if (defined(CONFIG_SPL_BUILD) && (CONFIG_SYS_INIT_L3_VADDR))
> +   tbl->start_addr[i] =
> +   (uint64_t)virt_to_phys((void *)CONFIG_SYS_INIT_L3_VADDR);
> +   tbl->size[i] = 256 * 1024; /* 256K CPC flash */
> +   tbl->end_addr[i] = tbl->start_addr[i] +  tbl->size[i] - 1;
> +
> +   i++;
> +#endif
> debug("PAMU address\t\t\tsize\n");
> for (j = 0; j < i ; j++)
> debug("%llx \t\t\t%llx\n",  tbl->start_addr[j],  
> tbl->size[j]);
> diff --git a/arch/powerpc/include/asm/fsl_secure_boot.h 
> b/arch/powerpc/include/asm/fsl_secure_boot.h
> index 826f9c9..2a29277 100644
> --- a/arch/powerpc/include/asm/fsl_secure_boot.h
> +++ b/arch/powerpc/include/asm/fsl_secure_boot.h
> @@ -72,6 +72,30 @@
>
>  #ifdef CONFIG_CHAIN_OF_TRUST
>
> +#ifdef CONFIG_SPL_BUILD
> +#define CONFIG_SPL_DM  1
> +#define CONFIG_SPL_CRYPTO_SUPPORT
> +#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
> +/*
> + * PPAACT and SPAACT table for PAMU must be placed on DDR after DDR init
> + * due to space crunch on CPC and thus malloc will not work.
> + */
> +#define CONFIG_SPL_PPAACT_ADDR 0x2e00
> +#define CONFIG_SPL_SPAACT_ADDR 0x2f00
> +#define CONFIG_SPL_JR0_LIODN_S 454
> +#define CONFIG_SPL_JR0_LIODN_NS458
> +/*
> + * Define the key hash for U-Boot here if public/private key pair used to
> + * sign U-boot are different from the SRK hash put in the fuse
> + * Example of defining KEY_HASH is
> + * #define CONFIG_SPL_UBOOT_KEY_HASH \
> + *  "41066b564c6ffcef40ccbc1e0a5d0d519604000c785d97bbefd25e4d288d1c8b"
> + * else leave it defined as NULL
> + */
> +
> +#define CONFIG_SPL_UBOOT_KEY_HASH  NULL
> +#endif /* ifdef CONFIG_SPL_BUILD */
> +
>  #define CONFIG_CMD_ESBC_VALIDATE
>  

Re: [U-Boot] [PATCH] Lower USB_MAX_XFER_BLK to 32767 by default for trimslice

[Marek Vasut]

On 05/26/2016 10:55 PM, Nicolas Chauvet wrote:
> I'm experiencing an issue when loading a generic distro initramfs
> on trimslice-pro (with ssd using ehci) with the default value of
> 65535 for USB_MAX_XFER_BLK
>  EHCI timed out on TD - token=0x80008d80
> 
> As adviced by Marek on IRC, using a lower value for
> USB_MAX_XFER_BLK allows to load the file
> 
> Tested values on tegra20-trimslice:
> 4095 ok
> 32767 ok
> 32768 timeout
> 36864 timeout
> 40960 timeout
> 49150 timeout
> 
> Tested on current u-boot master

I don't really like adding such patch which affects many devices just to
fix one particular device which is crappy. If you could add some
quirk table into u-boot instead and lower this number only for those
buggy devices, that'd be much better.

> Signed-off-by: Nicolas Chauvet 
> ---
>  common/usb_storage.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/common/usb_storage.c b/common/usb_storage.c
> index 7e6e52d..c69a7f7 100644
> --- a/common/usb_storage.c
> +++ b/common/usb_storage.c
> @@ -106,7 +106,7 @@ struct us_data {
>   * enough free heap space left, but the SCSI READ(10) and WRITE(10) commands 
> are
>   * limited to 65535 blocks.
>   */
> -#define USB_MAX_XFER_BLK 65535
> +#define USB_MAX_XFER_BLK 32767
>  #else
>  #define USB_MAX_XFER_BLK 20
>  #endif
> 


-- 
Best regards,
Marek Vasut
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH] board: ls2080ardb: qds: Fix compiling issue when FSL_MC_ENET not defined

[York Sun]

U-Boot should continue to work without management complex (MC).
Fix compiling errors and warnings.

Signed-off-by: York Sun 

---

 board/freescale/ls2080aqds/ls2080aqds.c |2 ++
 board/freescale/ls2080ardb/ls2080ardb.c |6 ++
 2 files changed, 8 insertions(+)

diff --git a/board/freescale/ls2080aqds/ls2080aqds.c 
b/board/freescale/ls2080aqds/ls2080aqds.c
index b3bd40a..897793d 100644
--- a/board/freescale/ls2080aqds/ls2080aqds.c
+++ b/board/freescale/ls2080aqds/ls2080aqds.c
@@ -282,7 +282,9 @@ void fdt_fixup_board_enet(void *fdt)
 #ifdef CONFIG_OF_BOARD_SETUP
 int ft_board_setup(void *blob, bd_t *bd)
 {
+#ifdef CONFIG_FSL_MC_ENET
int err;
+#endif
u64 base[CONFIG_NR_DRAM_BANKS];
u64 size[CONFIG_NR_DRAM_BANKS];
 
diff --git a/board/freescale/ls2080ardb/ls2080ardb.c 
b/board/freescale/ls2080ardb/ls2080ardb.c
index fb39af6..52e5e3f 100644
--- a/board/freescale/ls2080ardb/ls2080ardb.c
+++ b/board/freescale/ls2080ardb/ls2080ardb.c
@@ -156,7 +156,9 @@ int board_init(void)
 {
char *env_hwconfig;
u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
+#ifdef CONFIG_FSL_MC_ENET
u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE;
+#endif
u32 val;
 
init_final_memctl_regs();
@@ -178,8 +180,10 @@ int board_init(void)
 
QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET_EN);
 
+#ifdef CONFIG_FSL_MC_ENET
/* invert AQR405 IRQ pins polarity */
out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR405_IRQ_MASK);
+#endif
 
return 0;
 }
@@ -261,7 +265,9 @@ void fdt_fixup_board_enet(void *fdt)
 #ifdef CONFIG_OF_BOARD_SETUP
 int ft_board_setup(void *blob, bd_t *bd)
 {
+#ifdef CONFIG_FSL_MC_ENET
int err;
+#endif
u64 base[CONFIG_NR_DRAM_BANKS];
u64 size[CONFIG_NR_DRAM_BANKS];
 
-- 
1.7.9.5

___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH] Lower USB_MAX_XFER_BLK to 32767 by default for trimslice

[Nicolas Chauvet]

I'm experiencing an issue when loading a generic distro initramfs
on trimslice-pro (with ssd using ehci) with the default value of
65535 for USB_MAX_XFER_BLK
 EHCI timed out on TD - token=0x80008d80

As adviced by Marek on IRC, using a lower value for
USB_MAX_XFER_BLK allows to load the file

Tested values on tegra20-trimslice:
4095 ok
32767 ok
32768 timeout
36864 timeout
40960 timeout
49150 timeout

Tested on current u-boot master

Signed-off-by: Nicolas Chauvet 
---
 common/usb_storage.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/common/usb_storage.c b/common/usb_storage.c
index 7e6e52d..c69a7f7 100644
--- a/common/usb_storage.c
+++ b/common/usb_storage.c
@@ -106,7 +106,7 @@ struct us_data {
  * enough free heap space left, but the SCSI READ(10) and WRITE(10) commands 
are
  * limited to 65535 blocks.
  */
-#define USB_MAX_XFER_BLK   65535
+#define USB_MAX_XFER_BLK   32767
 #else
 #define USB_MAX_XFER_BLK   20
 #endif
-- 
2.4.11

___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH] drivers/ddr/fsl: Disabling data init if ECC is not enabled

[York Sun]

If ECC is not enabled, data init can be disabled to speed up booting.

Signed-off-by: York Sun 

---

 drivers/ddr/fsl/options.c |3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/ddr/fsl/options.c b/drivers/ddr/fsl/options.c
index d0075ff..793d12a 100644
--- a/drivers/ddr/fsl/options.c
+++ b/drivers/ddr/fsl/options.c
@@ -886,7 +886,8 @@ unsigned int populate_memctl_options(const 
common_timing_params_t *common_dimm,
} else
popts->ecc_mode = 1;
 #endif
-   popts->ecc_init_using_memctl = 1; /* 0 = use DMA, 1 = use memctl */
+   /* 1 = use memory controler to init data */
+   popts->ecc_init_using_memctl = popts->ecc_mode ? 1 : 0;
 
/*
 * Choose DQS config
-- 
1.7.9.5

___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH] mips: jz47xx: Add Creator CI20 platform

[Marek Vasut]

From: Paul Burton 

Add support for the Creator CI20 platform based on the JZ4780 SoC.
The DTS file comes from Linux 4.6 as of revision
78800558d104e003f9ae92e0107f1de39cf9de9f

So far, there are still a few details which will have to be fixed
once they are fleshed out in Linux:
- pinmux: Thus far, this board just pokes the pinmux registers to
  set the pinmux. For MMC in SPL, this will have to stay.
  But for full u-boot a proper pinmux driver will have to
  be added once the pinmux semantics in DT are in mainline
  Linux.
- ethernet,efuse: DT bindings are missing from mainline Linux.

Signed-off-by: Marek Vasut 
Cc: Daniel Schwierzeck 
Cc: Paul Burton 
---
 arch/mips/dts/Makefile|   1 +
 arch/mips/dts/ci20.dts| 114 ++
 arch/mips/mach-jz47xx/Kconfig |  11 ++
 board/imgtec/ci20/Kconfig |  15 ++
 board/imgtec/ci20/Makefile|   5 +
 board/imgtec/ci20/README  |  10 ++
 board/imgtec/ci20/ci20.c  | 354 ++
 configs/ci20_defconfig|  19 +++
 include/configs/ci20.h| 122 +++
 9 files changed, 651 insertions(+)
 create mode 100644 arch/mips/dts/ci20.dts
 create mode 100644 board/imgtec/ci20/Kconfig
 create mode 100644 board/imgtec/ci20/Makefile
 create mode 100644 board/imgtec/ci20/README
 create mode 100644 board/imgtec/ci20/ci20.c
 create mode 100644 configs/ci20_defconfig
 create mode 100644 include/configs/ci20.h

diff --git a/arch/mips/dts/Makefile b/arch/mips/dts/Makefile
index 2f04d73..121ab83 100644
--- a/arch/mips/dts/Makefile
+++ b/arch/mips/dts/Makefile
@@ -7,6 +7,7 @@ dtb-$(CONFIG_TARGET_AP143) += ap143.dtb
 dtb-$(CONFIG_TARGET_MALTA) += mti,malta.dtb
 dtb-$(CONFIG_TARGET_PIC32MZDASK) += pic32mzda_sk.dtb
 dtb-$(CONFIG_BOARD_TPLINK_WDR4300) += tplink_wdr4300.dtb
+dtb-$(CONFIG_TARGET_JZ4780_CI20) += ci20.dtb
 
 targets += $(dtb-y)
 
diff --git a/arch/mips/dts/ci20.dts b/arch/mips/dts/ci20.dts
new file mode 100644
index 000..9dab5e6
--- /dev/null
+++ b/arch/mips/dts/ci20.dts
@@ -0,0 +1,114 @@
+/dts-v1/;
+
+#include "jz4780.dtsi"
+
+/ {
+   compatible = "img,ci20", "ingenic,jz4780";
+
+   aliases {
+   serial0 = 
+   serial1 = 
+   serial3 = 
+   serial4 = 
+   };
+
+   chosen {
+   stdout-path = 
+   };
+
+   memory {
+   device_type = "memory";
+   reg = <0x0 0x1000
+  0x3000 0x3000>;
+   };
+};
+
+ {
+   clock-frequency = <4800>;
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+
+   nandc: nand-controller@1 {
+   compatible = "ingenic,jz4780-nand";
+   reg = <1 0 0x100>;
+
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   ingenic,bch-controller = <>;
+
+   ingenic,nemc-tAS = <10>;
+   ingenic,nemc-tAH = <5>;
+   ingenic,nemc-tBP = <10>;
+   ingenic,nemc-tAW = <15>;
+   ingenic,nemc-tSTRV = <100>;
+
+   nand@1 {
+   reg = <1>;
+
+   nand-ecc-step-size = <1024>;
+   nand-ecc-strength = <24>;
+   nand-ecc-mode = "hw";
+   nand-on-flash-bbt;
+
+   partitions {
+   compatible = "fixed-partitions";
+   #address-cells = <2>;
+   #size-cells = <2>;
+
+   partition@0 {
+   label = "u-boot-spl";
+   reg = <0x0 0x0 0x0 0x80>;
+   };
+
+   partition@0x80 {
+   label = "u-boot";
+   reg = <0x0 0x80 0x0 0x20>;
+   };
+
+   partition@0xa0 {
+   label = "u-boot-env";
+   reg = <0x0 0xa0 0x0 0x20>;
+   };
+
+   partition@0xc0 {
+   label = "boot";
+   reg = <0x0 0xc0 0x0 0x400>;
+   };
+
+   partition@0x8c0 {
+   label = "system";
+   reg = <0x0 0x4c0 0x1 0xfb40>;
+   };
+   };
+   };
+   };
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   bus-width = 

[U-Boot] [PATCH 1/2] mips: jz47xx: Add JZ4780 SoC support

[Marek Vasut]

From: Paul Burton 

Add initial support for the Ingenic JZ47xx MIPS SoC.
The DTSI file comes from Linux 4.6 as of revision
78800558d104e003f9ae92e0107f1de39cf9de9f

Signed-off-by: Marek Vasut 
Cc: Daniel Schwierzeck 
Cc: Paul Burton 
---
 arch/mips/Kconfig|   7 +
 arch/mips/Makefile   |   1 +
 arch/mips/dts/jz4780.dtsi| 137 ++
 arch/mips/mach-jz47xx/Kconfig|  15 +
 arch/mips/mach-jz47xx/Makefile   |   7 +
 arch/mips/mach-jz47xx/include/mach/jz4780.h  |  99 +
 arch/mips/mach-jz47xx/include/mach/jz4780_dram.h | 457 
 arch/mips/mach-jz47xx/jz4780/Makefile|   5 +
 arch/mips/mach-jz47xx/jz4780/jz4780.c| 126 ++
 arch/mips/mach-jz47xx/jz4780/pll.c   | 527 +++
 arch/mips/mach-jz47xx/jz4780/sdram.c | 271 
 arch/mips/mach-jz47xx/jz4780/timer.c | 238 ++
 arch/mips/mach-jz47xx/jz4780/u-boot-spl.lds  |  52 +++
 arch/mips/mach-jz47xx/start.S|  99 +
 include/dt-bindings/clock/jz4780-cgu.h   |  88 
 15 files changed, 2129 insertions(+)
 create mode 100644 arch/mips/dts/jz4780.dtsi
 create mode 100644 arch/mips/mach-jz47xx/Kconfig
 create mode 100644 arch/mips/mach-jz47xx/Makefile
 create mode 100644 arch/mips/mach-jz47xx/include/mach/jz4780.h
 create mode 100644 arch/mips/mach-jz47xx/include/mach/jz4780_dram.h
 create mode 100644 arch/mips/mach-jz47xx/jz4780/Makefile
 create mode 100644 arch/mips/mach-jz47xx/jz4780/jz4780.c
 create mode 100644 arch/mips/mach-jz47xx/jz4780/pll.c
 create mode 100644 arch/mips/mach-jz47xx/jz4780/sdram.c
 create mode 100644 arch/mips/mach-jz47xx/jz4780/timer.c
 create mode 100644 arch/mips/mach-jz47xx/jz4780/u-boot-spl.lds
 create mode 100644 arch/mips/mach-jz47xx/start.S
 create mode 100644 include/dt-bindings/clock/jz4780-cgu.h

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 53363e3..ab9719c 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -65,6 +65,12 @@ config ARCH_ATH79
select OF_CONTROL
select DM
 
+config ARCH_JZ47XX
+   bool "Support Ingenic JZ47xx"
+   select SUPPORT_SPL
+   select OF_CONTROL
+   select DM
+
 config MACH_PIC32
bool "Support Microchip PIC32"
select OF_CONTROL
@@ -78,6 +84,7 @@ source "board/micronas/vct/Kconfig"
 source "board/pb1x00/Kconfig"
 source "board/qemu-mips/Kconfig"
 source "arch/mips/mach-ath79/Kconfig"
+source "arch/mips/mach-jz47xx/Kconfig"
 source "arch/mips/mach-pic32/Kconfig"
 
 if MIPS
diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index 0b5dbb6..d28241e 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -15,6 +15,7 @@ libs-y += arch/mips/lib/
 
 machine-$(CONFIG_SOC_AU1X00) += au1x00
 machine-$(CONFIG_ARCH_ATH79) += ath79
+machine-$(CONFIG_ARCH_JZ47XX) += jz47xx
 machine-$(CONFIG_MACH_PIC32) += pic32
 
 machdirs := $(patsubst %,arch/mips/mach-%/,$(machine-y))
diff --git a/arch/mips/dts/jz4780.dtsi b/arch/mips/dts/jz4780.dtsi
new file mode 100644
index 000..b868b42
--- /dev/null
+++ b/arch/mips/dts/jz4780.dtsi
@@ -0,0 +1,137 @@
+#include 
+
+/ {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   compatible = "ingenic,jz4780";
+
+   cpuintc: interrupt-controller {
+   #address-cells = <0>;
+   #interrupt-cells = <1>;
+   interrupt-controller;
+   compatible = "mti,cpu-interrupt-controller";
+   };
+
+   intc: interrupt-controller@10001000 {
+   compatible = "ingenic,jz4780-intc";
+   reg = <0x10001000 0x50>;
+
+   interrupt-controller;
+   #interrupt-cells = <1>;
+
+   interrupt-parent = <>;
+   interrupts = <2>;
+   };
+
+   ext: ext {
+   compatible = "fixed-clock";
+   #clock-cells = <0>;
+   };
+
+   rtc: rtc {
+   compatible = "fixed-clock";
+   #clock-cells = <0>;
+   clock-frequency = <32768>;
+   };
+
+   cgu: jz4780-cgu@1000 {
+   compatible = "ingenic,jz4780-cgu";
+   reg = <0x1000 0x100>;
+
+   clocks = <>, <>;
+   clock-names = "ext", "rtc";
+
+   #clock-cells = <1>;
+   };
+
+   uart0: serial@1003 {
+   compatible = "ingenic,jz4780-uart";
+   reg = <0x1003 0x100>;
+
+   interrupt-parent = <>;
+   interrupts = <51>;
+
+   clocks = <>, < JZ4780_CLK_UART0>;
+   clock-names = "baud", "module";
+
+   status = "disabled";
+   };
+
+   uart1: serial@10031000 {
+   compatible = "ingenic,jz4780-uart";
+   reg = <0x10031000 0x100>;
+
+   

[U-Boot] [PATCH 2/2] mips: jz47xx: Add minimal JZ MMC node

[Marek Vasut]

Add minimal JZ MMC node into the JZ4780 device tree.
This piece is picked from the CI20 Linux repository.

Signed-off-by: Marek Vasut 
Cc: Daniel Schwierzeck 
Cc: Paul Burton 
---
 arch/mips/dts/jz4780.dtsi | 20 
 1 file changed, 20 insertions(+)

diff --git a/arch/mips/dts/jz4780.dtsi b/arch/mips/dts/jz4780.dtsi
index b868b42..2b022c3 100644
--- a/arch/mips/dts/jz4780.dtsi
+++ b/arch/mips/dts/jz4780.dtsi
@@ -44,6 +44,26 @@
#clock-cells = <1>;
};
 
+   msc0: msc@1345 {
+   compatible = "ingenic,jz4780-mmc";
+   reg = <0x1345 0x1000>;
+
+   status = "disabled";
+
+   clocks = < JZ4780_CLK_MSC0>;
+   clock-names = "mmc";
+   };
+
+   msc1: msc@1346 {
+   compatible = "ingenic,jz4780-mmc";
+   reg = <0x1346 0x1000>;
+
+   clocks = < JZ4780_CLK_MSC1>;
+   clock-names = "mmc";
+
+   status = "disabled";
+   };
+
uart0: serial@1003 {
compatible = "ingenic,jz4780-uart";
reg = <0x1003 0x100>;
-- 
2.7.0

___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH] mips: Add SPL header

[Marek Vasut]

From: Paul Burton 

Add header with SPL boot mode and type definitions.

Signed-off-by: Marek Vasut 
Cc: Daniel Schwierzeck 
Cc: Paul Burton 
---
 arch/mips/include/asm/spl.h | 35 +++
 1 file changed, 35 insertions(+)
 create mode 100644 arch/mips/include/asm/spl.h

diff --git a/arch/mips/include/asm/spl.h b/arch/mips/include/asm/spl.h
new file mode 100644
index 000..01baab6
--- /dev/null
+++ b/arch/mips/include/asm/spl.h
@@ -0,0 +1,35 @@
+/*
+ * (C) Copyright 2012
+ * Texas Instruments, 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+#ifndef_ASM_SPL_H_
+#define_ASM_SPL_H_
+
+enum {
+   BOOT_DEVICE_RAM,
+   BOOT_DEVICE_MMC1,
+   BOOT_DEVICE_MMC2,
+   BOOT_DEVICE_MMC2_2,
+   BOOT_DEVICE_NAND,
+   BOOT_DEVICE_ONENAND,
+   BOOT_DEVICE_NOR,
+   BOOT_DEVICE_UART,
+   BOOT_DEVICE_SPI,
+   BOOT_DEVICE_USB,
+   BOOT_DEVICE_SATA,
+   BOOT_DEVICE_I2C,
+   BOOT_DEVICE_BOARD,
+   BOOT_DEVICE_NONE
+};
+
+/* Linker symbols. */
+extern char __bss_start[];
+extern ulong __bss_end;
+
+#ifndef CONFIG_DM
+extern gd_t gdata;
+#endif
+
+#endif
-- 
2.7.0

___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH] misc: Add JZ47xx efuse driver

[Marek Vasut]

From: Paul Burton 

Add driver for the efuse block in the JZ47xx SOC.

Signed-off-by: Marek Vasut 
Cc: Daniel Schwierzeck 
Cc: Paul Burton 
---
 drivers/misc/Kconfig|   6 +++
 drivers/misc/Makefile   |   1 +
 drivers/misc/jz4780_efuse.c | 100 
 3 files changed, 107 insertions(+)
 create mode 100644 drivers/misc/jz4780_efuse.c

diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index c40f6b5..9dbf47d 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -83,6 +83,12 @@ config FSL_SEC_MON
  Security Monitor can be transitioned on any security failures,
  like software violations or hardware security violations.
 
+config JZ4780_EFUSE
+   bool "Ingenic JZ4780 eFUSE support"
+   depends on ARCH_JZ47XX
+   help
+ This selects support for the eFUSE on Ingenic JZ4780 SoCs.
+
 config MXC_OCOTP
bool "Enable MXC OCOTP Driver"
help
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index 98704f2..458cb77 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -44,3 +44,4 @@ obj-$(CONFIG_RESET) += reset-uclass.o
 obj-$(CONFIG_FSL_DEVICE_DISABLE) += fsl_devdis.o
 obj-$(CONFIG_WINBOND_W83627) += winbond_w83627.o
 obj-$(CONFIG_QFW) += qfw.o
+obj-$(CONFIG_JZ4780_EFUSE) += jz4780_efuse.o
diff --git a/drivers/misc/jz4780_efuse.c b/drivers/misc/jz4780_efuse.c
new file mode 100644
index 000..77ef96b
--- /dev/null
+++ b/drivers/misc/jz4780_efuse.c
@@ -0,0 +1,100 @@
+/*
+ * JZ4780 EFUSE driver
+ *
+ * Copyright (c) 2014 Imagination Technologies
+ * Author: Alex Smith 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define EFUSE_EFUCTRL  0xd0
+#define EFUSE_EFUCFG   0xd4
+#define EFUSE_EFUSTATE 0xd8
+#define EFUSE_EFUDATA(n)   (0xdc + ((n) * 4))
+
+#define EFUSE_EFUCTRL_RD_ENBIT(0)
+#define EFUSE_EFUCTRL_LEN_BIT  16
+#define EFUSE_EFUCTRL_LEN_MASK 0x1f
+#define EFUSE_EFUCTRL_ADDR_BIT 21
+#define EFUSE_EFUCTRL_ADDR_MASK0x1ff
+#define EFUSE_EFUCTRL_CS   BIT(30)
+
+#define EFUSE_EFUCFG_RD_STROBE_BIT 16
+#define EFUSE_EFUCFG_RD_STROBE_MASK0xf
+#define EFUSE_EFUCFG_RD_ADJ_BIT20
+#define EFUSE_EFUCFG_RD_ADJ_MASK   0xf
+
+#define EFUSE_EFUSTATE_RD_DONE BIT(0)
+
+static void jz4780_efuse_read_chunk(size_t addr, size_t count, u8 *buf)
+{
+   void __iomem *regs = (void __iomem *)NEMC_BASE;
+   size_t i;
+   u32 val;
+
+   val = EFUSE_EFUCTRL_RD_EN |
+ ((count - 1) << EFUSE_EFUCTRL_LEN_BIT) |
+ (addr << EFUSE_EFUCTRL_ADDR_BIT) |
+ ((addr > 0x200) ? EFUSE_EFUCTRL_CS : 0);
+   writel(val, regs + EFUSE_EFUCTRL);
+   /* FIXME -- wait_bit() */
+   while (!(readl(regs + EFUSE_EFUSTATE) & EFUSE_EFUSTATE_RD_DONE))
+   ;
+
+   if ((count % 4) == 0) {
+   for (i = 0; i < count / 4; i++) {
+   val = readl(regs + EFUSE_EFUDATA(i));
+   put_unaligned(val, (u32 *)(buf + (i * 4)));
+   }
+   } else {
+   val = readl(regs + EFUSE_EFUDATA(0));
+   if (count > 2)
+   buf[2] = (val >> 16) & 0xff;
+   if (count > 1)
+   buf[1] = (val >> 8) & 0xff;
+   buf[0] = val & 0xff;
+   }
+}
+
+static inline int jz4780_efuse_chunk_size(size_t count)
+{
+   if (count >= 32)
+   return 32;
+   else if ((count / 4) > 0)
+   return (count / 4) * 4;
+   else
+   return count % 4;
+}
+
+void jz4780_efuse_read(size_t addr, size_t count, u8 *buf)
+{
+   size_t chunk;
+
+   while (count > 0) {
+   chunk = jz4780_efuse_chunk_size(count);
+   jz4780_efuse_read_chunk(addr, chunk, buf);
+   addr += chunk;
+   buf += chunk;
+   count -= chunk;
+   }
+}
+
+void jz4780_efuse_init(u32 ahb2_rate)
+{
+   void __iomem *regs = (void __iomem *)NEMC_BASE;
+   u32 rd_adj, rd_strobe, tmp;
+
+   rd_adj = (((6500 * (ahb2_rate / 100)) / 100) + 0xf) / 2;
+   tmp = (((35000 * (ahb2_rate / 100)) / 100) - 4) - rd_adj;
+   rd_strobe = ((tmp + 0xf) / 2 < 7) ? 7 : (tmp + 0xf) / 2;
+
+   tmp = (rd_adj << EFUSE_EFUCFG_RD_ADJ_BIT) |
+ (rd_strobe << EFUSE_EFUCFG_RD_STROBE_BIT);
+   writel(tmp, regs + EFUSE_EFUCFG);
+}
-- 
2.7.0

___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH] gpio: Add JZ47xx GPIO driver

[Marek Vasut]

From: Paul Burton 

Add primitive GPIO controller driver for the JZ47xx SoC.

Signed-off-by: Marek Vasut 
Cc: Daniel Schwierzeck 
Cc: Paul Burton 
---
 drivers/gpio/Kconfig   |  8 +
 drivers/gpio/Makefile  |  1 +
 drivers/gpio/gpio-jz47xx.c | 79 ++
 3 files changed, 88 insertions(+)
 create mode 100644 drivers/gpio/gpio-jz47xx.c

diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index 93a7e8c..7140dbe 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -173,4 +173,12 @@ config DM_PCA953X
 
  Now, max 24 bits chips and PCA953X compatible chips are
  supported
+
+config JZ47XX_GPIO
+   bool "Ingenic JZ47xx GPIO driver"
+   depends on ARCH_JZ47XX
+   default y
+   help
+ Supports GPIO access on Ingenic JZ47xx SoCs.
+
 endmenu
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index ddec1ef..3338517 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -55,3 +55,4 @@ obj-$(CONFIG_PIC32_GPIO)  += pic32_gpio.o
 obj-$(CONFIG_MVEBU_GPIO)   += mvebu_gpio.o
 obj-$(CONFIG_MSM_GPIO) += msm_gpio.o
 obj-$(CONFIG_PM8916_GPIO)  += pm8916_gpio.o
+obj-$(CONFIG_JZ47XX_GPIO)  += gpio-jz47xx.o
diff --git a/drivers/gpio/gpio-jz47xx.c b/drivers/gpio/gpio-jz47xx.c
new file mode 100644
index 000..7520925
--- /dev/null
+++ b/drivers/gpio/gpio-jz47xx.c
@@ -0,0 +1,79 @@
+/*
+ * Ingenic JZ47xx GPIO
+ *
+ * Copyright (C) 2011 Marek Vasut 
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+int gpio_get_value(unsigned gpio)
+{
+   void __iomem *gpio_regs = (void __iomem *)GPIO_BASE;
+   int port = gpio / 32;
+   int pin = gpio % 32;
+
+   return readl(gpio_regs + GPIO_PXPIN(port)) & BIT(pin);
+}
+
+int gpio_set_value(unsigned gpio, int value)
+{
+   void __iomem *gpio_regs = (void __iomem *)GPIO_BASE;
+   int port = gpio / 32;
+   int pin = gpio % 32;
+
+   if (value)
+   writel(BIT(pin), gpio_regs + GPIO_PXPAT0S(port));
+   else
+   writel(BIT(pin), gpio_regs + GPIO_PXPAT0C(port));
+
+   return 0;
+}
+
+int gpio_direction_input(unsigned gpio)
+{
+   void __iomem *gpio_regs = (void __iomem *)GPIO_BASE;
+   int port = gpio / 32;
+   int pin = gpio % 32;
+
+   writel(BIT(pin), gpio_regs + GPIO_PXINTC(port));
+   writel(BIT(pin), gpio_regs + GPIO_PXMASKS(port));
+   writel(BIT(pin), gpio_regs + GPIO_PXPAT1S(port));
+
+   return 0;
+}
+
+int gpio_direction_output(unsigned gpio, int value)
+{
+   void __iomem *gpio_regs = (void __iomem *)GPIO_BASE;
+   int port = gpio / 32;
+   int pin = gpio % 32;
+
+   writel(BIT(pin), gpio_regs + GPIO_PXINTC(port));
+   writel(BIT(pin), gpio_regs + GPIO_PXMASKS(port));
+   writel(BIT(pin), gpio_regs + GPIO_PXPAT1C(port));
+
+   gpio_set_value(gpio, value);
+
+   return 0;
+}
+
+int gpio_request(unsigned gpio, const char *label)
+{
+   int port = gpio / 32;
+
+   if (port >= 6)
+   return -EINVAL;
+
+   return 0;
+}
+
+int gpio_free(unsigned gpio)
+{
+   return 0;
+}
-- 
2.7.0

___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH] mmc: Add JZ47xx SD/MMC controller driver

[Marek Vasut]

From: Paul Burton 

Add driver for the JZ47xx MSC controller.

Signed-off-by: Marek Vasut 
Cc: Daniel Schwierzeck 
Cc: Paul Burton 
---
 drivers/mmc/Kconfig  |   6 +
 drivers/mmc/Makefile |   1 +
 drivers/mmc/jz_mmc.c | 443 +++
 3 files changed, 450 insertions(+)
 create mode 100644 drivers/mmc/jz_mmc.c

diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
index c80efc3..da9c86b 100644
--- a/drivers/mmc/Kconfig
+++ b/drivers/mmc/Kconfig
@@ -58,6 +58,12 @@ config MMC_UNIPHIER
help
  This selects support for the SD/MMC Host Controller on UniPhier SoCs.
 
+config JZ47XX_MMC
+   bool "Ingenic JZ47xx SD/MMC Host Controller support"
+   depends on ARCH_JZ47XX
+   help
+ This selects support for the SD Card Controller on Ingenic JZ47xx 
SoCs.
+
 config SANDBOX_MMC
bool "Sandbox MMC support"
depends on MMC && SANDBOX
diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile
index 4d986cb..4c381c5 100644
--- a/drivers/mmc/Makefile
+++ b/drivers/mmc/Makefile
@@ -55,6 +55,7 @@ obj-$(CONFIG_SPEAR_SDHCI) += spear_sdhci.o
 obj-$(CONFIG_TEGRA_MMC) += tegra_mmc.o
 obj-$(CONFIG_MMC_UNIPHIER) += uniphier-sd.o
 obj-$(CONFIG_ZYNQ_SDHCI) += zynq_sdhci.o
+obj-$(CONFIG_JZ47XX_MMC) += jz_mmc.o
 
 ifdef CONFIG_SPL_BUILD
 obj-$(CONFIG_SPL_MMC_BOOT) += fsl_esdhc_spl.o
diff --git a/drivers/mmc/jz_mmc.c b/drivers/mmc/jz_mmc.c
new file mode 100644
index 000..68f5a21
--- /dev/null
+++ b/drivers/mmc/jz_mmc.c
@@ -0,0 +1,443 @@
+/*
+ * Ingenic JZ MMC driver
+ *
+ * Copyright (c) 2013 Imagination Technologies
+ * Author: Paul Burton 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/* Registers */
+#define MSC_STRPCL 0x000
+#define MSC_STAT   0x004
+#define MSC_CLKRT  0x008
+#define MSC_CMDAT  0x00c
+#define MSC_RESTO  0x010
+#define MSC_RDTO   0x014
+#define MSC_BLKLEN 0x018
+#define MSC_NOB0x01c
+#define MSC_SNOB   0x020
+#define MSC_IMASK  0x024
+#define MSC_IREG   0x028
+#define MSC_CMD0x02c
+#define MSC_ARG0x030
+#define MSC_RES0x034
+#define MSC_RXFIFO 0x038
+#define MSC_TXFIFO 0x03c
+#define MSC_LPM0x040
+#define MSC_DMAC   0x044
+#define MSC_DMANDA 0x048
+#define MSC_DMADA  0x04c
+#define MSC_DMALEN 0x050
+#define MSC_DMACMD 0x054
+#define MSC_CTRL2  0x058
+#define MSC_RTCNT  0x05c
+#define MSC_DBG0x0fc
+
+/* MSC Clock and Control Register (MSC_STRPCL) */
+
+#define MSC_STRPCL_EXIT_MULTIPLE   BIT(7)
+#define MSC_STRPCL_EXIT_TRANSFER   BIT(6)
+#define MSC_STRPCL_START_READWAIT  BIT(5)
+#define MSC_STRPCL_STOP_READWAIT   BIT(4)
+#define MSC_STRPCL_RESET   BIT(3)
+#define MSC_STRPCL_START_OPBIT(2)
+#define MSC_STRPCL_CLOCK_CONTROL_STOP  BIT(0)
+#define MSC_STRPCL_CLOCK_CONTROL_START BIT(1)
+
+/* MSC Status Register (MSC_STAT) */
+
+#define MSC_STAT_AUTO_CMD_DONE BIT(31)
+#define MSC_STAT_IS_RESETTING  BIT(15)
+#define MSC_STAT_SDIO_INT_ACTIVE   BIT(14)
+#define MSC_STAT_PRG_DONE  BIT(13)
+#define MSC_STAT_DATA_TRAN_DONEBIT(12)
+#define MSC_STAT_END_CMD_RES   BIT(11)
+#define MSC_STAT_DATA_FIFO_AFULL   BIT(10)
+#define MSC_STAT_IS_READWAIT   BIT(9)
+#define MSC_STAT_CLK_ENBIT(8)
+#define MSC_STAT_DATA_FIFO_FULLBIT(7)
+#define MSC_STAT_DATA_FIFO_EMPTY   BIT(6)
+#define MSC_STAT_CRC_RES_ERR   BIT(5)
+#define MSC_STAT_CRC_READ_ERRORBIT(4)
+#define MSC_STAT_CRC_WRITE_ERROR   BIT(2)
+#define MSC_STAT_CRC_WRITE_ERROR_NOSTS BIT(4)
+#define MSC_STAT_TIME_OUT_RES  BIT(1)
+#define MSC_STAT_TIME_OUT_READ BIT(0)
+
+/* MSC Bus Clock Control Register (MSC_CLKRT) */
+#define MSC_CLKRT_CLK_RATE_MASK0x7
+
+/* MSC Command Sequence Control Register (MSC_CMDAT) */
+
+#define MSC_CMDAT_IO_ABORT BIT(11)
+#define MSC_CMDAT_BUS_WIDTH_1BIT   (0x0 << 9)
+#define MSC_CMDAT_BUS_WIDTH_4BIT   (0x2 << 9)
+#define MSC_CMDAT_DMA_EN   BIT(8)
+#define MSC_CMDAT_INIT BIT(7)
+#define MSC_CMDAT_BUSY BIT(6)
+#define MSC_CMDAT_STREAM_BLOCK BIT(5)
+#define MSC_CMDAT_WRITEBIT(4)
+#define MSC_CMDAT_DATA_EN  

[U-Boot] [PATCH] mmc: Tinification of the mmc code

[Marek Vasut]

Add new configuration option CONFIG_MMC_TINY which strips away all
memory allocation within the MMC code and code for handling multiple
cards. This allows extremely space-constrained SPL code use the MMC
framework.

Signed-off-by: Marek Vasut 
Cc: Tom Rini 
Cc: Simon Glass 
---
 common/spl/spl_mmc.c |  4 
 drivers/mmc/Makefile |  2 ++
 drivers/mmc/mmc.c| 59 +++-
 include/mmc.h|  1 +
 4 files changed, 65 insertions(+), 1 deletion(-)

diff --git a/common/spl/spl_mmc.c b/common/spl/spl_mmc.c
index ae42221..51f0f24 100644
--- a/common/spl/spl_mmc.c
+++ b/common/spl/spl_mmc.c
@@ -300,7 +300,11 @@ int spl_mmc_load_image(u32 boot_device)
if (part == 7)
part = 0;
 
+#ifdef CONFIG_MMC_TINY
+   err = mmc_switch_part(mmc, part);
+#else
err = blk_dselect_hwpart(mmc_get_blk_desc(mmc), part);
+#endif
if (err) {
 #ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
puts("spl: mmc partition switch failed\n");
diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile
index 3da4817..4d986cb 100644
--- a/drivers/mmc/Makefile
+++ b/drivers/mmc/Makefile
@@ -10,8 +10,10 @@ obj-$(CONFIG_GENERIC_MMC) += mmc-uclass.o
 endif
 
 ifndef CONFIG_BLK
+ifndef CONFIG_MMC_TINY
 obj-$(CONFIG_GENERIC_MMC) += mmc_legacy.o
 endif
+endif
 
 obj-$(CONFIG_ARM_PL180_MMCI) += arm_pl180_mmci.o
 obj-$(CONFIG_ATMEL_SDHCI) += atmel_sdhci.o
diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index d687345..1f240ed 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -21,6 +21,29 @@
 #include 
 #include "mmc_private.h"
 
+#if defined(CONFIG_MMC_TINY)
+static struct mmc mmc_static;
+struct mmc *find_mmc_device(int dev_num)
+{
+   return _static;
+}
+
+void mmc_do_preinit(void)
+{
+   struct mmc *m = _static;
+#ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
+   mmc_set_preinit(m, 1);
+#endif
+   if (m->preinit)
+   mmc_start_init(m);
+}
+
+struct blk_desc *mmc_get_blk_desc(struct mmc *mmc)
+{
+   return >block_dev;
+}
+#endif
+
 __weak int board_mmc_getwp(struct mmc *mmc)
 {
return -1;
@@ -238,7 +261,11 @@ static ulong mmc_bread(struct blk_desc *block_dev, 
lbaint_t start,
if (!mmc)
return 0;
 
+#ifdef CONFIG_MMC_TINY
+   err = mmc_switch_part(mmc, block_dev->hwpart);
+#else
err = blk_dselect_hwpart(block_dev, block_dev->hwpart);
+#endif
if (err < 0)
return 0;
 
@@ -568,7 +595,7 @@ static int mmc_set_capacity(struct mmc *mmc, int part_num)
return 0;
 }
 
-static int mmc_switch_part(struct mmc *mmc, unsigned int part_num)
+int mmc_switch_part(struct mmc *mmc, unsigned int part_num)
 {
int ret;
 
@@ -1585,6 +1612,34 @@ int mmc_unbind(struct udevice *dev)
return 0;
 }
 
+#elif defined(CONFIG_MMC_TINY)
+static struct mmc mmc_static = {
+   .dsr_imp= 0,
+   .dsr= 0x,
+   .block_dev = {
+   .if_type= IF_TYPE_MMC,
+   .removable  = 1,
+   .devnum = 0,
+   .block_read = mmc_bread,
+   .block_write= mmc_bwrite,
+   .block_erase= mmc_berase,
+   .part_type  = 0,
+   },
+};
+
+struct mmc *mmc_create(const struct mmc_config *cfg, void *priv)
+{
+   struct mmc *mmc = _static;
+
+   mmc->cfg = cfg;
+   mmc->priv = priv;
+
+   return mmc;
+}
+
+void mmc_destroy(struct mmc *mmc)
+{
+}
 #else
 struct mmc *mmc_create(const struct mmc_config *cfg, void *priv)
 {
@@ -1834,8 +1889,10 @@ int mmc_initialize(bd_t *bis)
initialized = 1;
 
 #ifndef CONFIG_BLK
+#ifndef CONFIG_MMC_TINY
mmc_list_init();
 #endif
+#endif
ret = mmc_probe(bis);
if (ret)
return ret;
diff --git a/include/mmc.h b/include/mmc.h
index a5c6573..08a59c2 100644
--- a/include/mmc.h
+++ b/include/mmc.h
@@ -444,6 +444,7 @@ struct mmc *find_mmc_device(int dev_num);
 int mmc_set_dev(int dev_num);
 void print_mmc_devices(char separator);
 int get_mmc_num(void);
+int mmc_switch_part(struct mmc *mmc, unsigned int part_num);
 int mmc_hwpart_config(struct mmc *mmc, const struct mmc_hwpart_conf *conf,
  enum mmc_hwpart_conf_mode mode);
 int mmc_getcd(struct mmc *mmc);
-- 
2.7.0

___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH 3/3] serial: 16550: Add Ingenic JZ4780 support

[Marek Vasut]

Add compatibility string for the Ingenic JZ4780 SoC, the necessary
UART enable bit into FCR and register shift. Neither are encoded
in the DTS coming from Linux, so we need to support it this way.

Signed-off-by: Marek Vasut 
Cc: Tom Rini 
Cc: Simon Glass 
Cc: Daniel Schwierzeck 
Cc: Paul Burton 
---
 drivers/serial/ns16550.c | 7 +++
 include/ns16550.h| 3 +++
 2 files changed, 10 insertions(+)

diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c
index f371f74..8dc0e65 100644
--- a/drivers/serial/ns16550.c
+++ b/drivers/serial/ns16550.c
@@ -362,11 +362,13 @@ int ns16550_serial_probe(struct udevice *dev)
 #if CONFIG_IS_ENABLED(OF_CONTROL)
 enum {
PORT_NS16550 = 0,
+   PORT_JZ4780,
 };
 
 int ns16550_serial_ofdata_to_platdata(struct udevice *dev)
 {
struct ns16550_platdata *plat = dev->platdata;
+   const u32 port_type = dev_get_driver_data(dev);
fdt_addr_t addr;
 
/* try Processor Local Bus device first */
@@ -422,6 +424,10 @@ int ns16550_serial_ofdata_to_platdata(struct udevice *dev)
}
 
plat->fcr = UART_FCRVAL;
+   if (port_type == PORT_JZ4780) {
+   plat->fcr |= UART_FCR_UME;
+   plat->reg_shift = 2;
+   }
 
return 0;
 }
@@ -443,6 +449,7 @@ const struct dm_serial_ops ns16550_serial_ops = {
 static const struct udevice_id ns16550_serial_ids[] = {
{ .compatible = "ns16550",  .data = PORT_NS16550 },
{ .compatible = "ns16550a", .data = PORT_NS16550 },
+   { .compatible = "ingenic,jz4780-uart",  .data = PORT_JZ4780  },
{ .compatible = "nvidia,tegra20-uart",  .data = PORT_NS16550 },
{ .compatible = "snps,dw-apb-uart", .data = PORT_NS16550 },
{ .compatible = "ti,omap2-uart",.data = PORT_NS16550 },
diff --git a/include/ns16550.h b/include/ns16550.h
index 45fd68b..7c97036 100644
--- a/include/ns16550.h
+++ b/include/ns16550.h
@@ -118,6 +118,9 @@ typedef struct NS16550 *NS16550_t;
 #define UART_FCR_RXSR  0x02 /* Receiver soft reset */
 #define UART_FCR_TXSR  0x04 /* Transmitter soft reset */
 
+/* Ingenic JZ47xx specific UART-enable bit. */
+#define UART_FCR_UME   0x10
+
 /*
  * These are the definitions for the Modem Control Register
  */
-- 
2.7.0

___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH 2/3] serial: 16550: Add port type as driver data

[Marek Vasut]

Add driver data to each compatible string to identify the type of
the port. Since all the ports in the driver are entirely compatible
with 16550 for now, all are marked with PORT_NS16550. But, there
are ports which have specific quirks, like the JZ4780 UART, which
do not have any DT property to denote the quirks. Instead, Linux
uses the compatible string to discern such ports and enable the
necessary quirks.

Signed-off-by: Marek Vasut 
Cc: Tom Rini 
Cc: Simon Glass 
---
 drivers/serial/ns16550.c | 24 ++--
 1 file changed, 14 insertions(+), 10 deletions(-)

diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c
index b39ce02..f371f74 100644
--- a/drivers/serial/ns16550.c
+++ b/drivers/serial/ns16550.c
@@ -360,6 +360,10 @@ int ns16550_serial_probe(struct udevice *dev)
 }
 
 #if CONFIG_IS_ENABLED(OF_CONTROL)
+enum {
+   PORT_NS16550 = 0,
+};
+
 int ns16550_serial_ofdata_to_platdata(struct udevice *dev)
 {
struct ns16550_platdata *plat = dev->platdata;
@@ -437,16 +441,16 @@ const struct dm_serial_ops ns16550_serial_ops = {
  * compatible string to your dts.
  */
 static const struct udevice_id ns16550_serial_ids[] = {
-   { .compatible = "ns16550" },
-   { .compatible = "ns16550a" },
-   { .compatible = "nvidia,tegra20-uart" },
-   { .compatible = "snps,dw-apb-uart" },
-   { .compatible = "ti,omap2-uart" },
-   { .compatible = "ti,omap3-uart" },
-   { .compatible = "ti,omap4-uart" },
-   { .compatible = "ti,am3352-uart" },
-   { .compatible = "ti,am4372-uart" },
-   { .compatible = "ti,dra742-uart" },
+   { .compatible = "ns16550",  .data = PORT_NS16550 },
+   { .compatible = "ns16550a", .data = PORT_NS16550 },
+   { .compatible = "nvidia,tegra20-uart",  .data = PORT_NS16550 },
+   { .compatible = "snps,dw-apb-uart", .data = PORT_NS16550 },
+   { .compatible = "ti,omap2-uart",.data = PORT_NS16550 },
+   { .compatible = "ti,omap3-uart",.data = PORT_NS16550 },
+   { .compatible = "ti,omap4-uart",.data = PORT_NS16550 },
+   { .compatible = "ti,am3352-uart",   .data = PORT_NS16550 },
+   { .compatible = "ti,am4372-uart",   .data = PORT_NS16550 },
+   { .compatible = "ti,dra742-uart",   .data = PORT_NS16550 },
{}
 };
 #endif
-- 
2.7.0

___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH 1/3] serial: 16550: Add getfcr accessor

[Marek Vasut]

Add function which allows fetching the default FCR register setting
from platform data for DM , while retaining old behavior for non-DM
by returning UART_FCRVAL.

Signed-off-by: Marek Vasut 
Cc: Tom Rini 
Cc: Simon Glass 
---
 drivers/serial/ns16550.c | 20 +---
 include/ns16550.h|  1 +
 2 files changed, 18 insertions(+), 3 deletions(-)

diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c
index c6cb3eb..b39ce02 100644
--- a/drivers/serial/ns16550.c
+++ b/drivers/serial/ns16550.c
@@ -120,6 +120,13 @@ static int ns16550_readb(NS16550_t port, int offset)
return serial_in_shift(addr + plat->reg_offset, plat->reg_shift);
 }
 
+static u32 ns16550_getfcr(NS16550_t port)
+{
+   struct ns16550_platdata *plat = port->plat;
+
+   return plat->fcr;
+}
+
 /* We can clean these up once everything is moved to driver model */
 #define serial_out(value, addr)\
ns16550_writeb(com_port, \
@@ -127,6 +134,11 @@ static int ns16550_readb(NS16550_t port, int offset)
 #define serial_in(addr) \
ns16550_readb(com_port, \
(unsigned char *)addr - (unsigned char *)com_port)
+#else
+static u32 ns16550_getfcr(NS16550_t port)
+{
+   return UART_FCRVAL;
+}
 #endif
 
 int ns16550_calc_divisor(NS16550_t port, int clock, int baudrate)
@@ -170,7 +182,7 @@ void NS16550_init(NS16550_t com_port, int baud_divisor)
serial_out(0x7, _port->mdr1);   /* mode select reset TL16C750*/
 #endif
serial_out(UART_MCRVAL, _port->mcr);
-   serial_out(UART_FCRVAL, _port->fcr);
+   serial_out(ns16550_getfcr(com_port), _port->fcr);
if (baud_divisor != -1)
NS16550_setbrg(com_port, baud_divisor);
 #if defined(CONFIG_OMAP) || \
@@ -191,7 +203,7 @@ void NS16550_reinit(NS16550_t com_port, int baud_divisor)
serial_out(CONFIG_SYS_NS16550_IER, _port->ier);
NS16550_setbrg(com_port, 0);
serial_out(UART_MCRVAL, _port->mcr);
-   serial_out(UART_FCRVAL, _port->fcr);
+   serial_out(ns16550_getfcr(com_port), _port->fcr);
NS16550_setbrg(com_port, baud_divisor);
 }
 #endif /* CONFIG_NS16550_MIN_FUNCTIONS */
@@ -262,7 +274,7 @@ static inline void _debug_uart_init(void)
CONFIG_BAUDRATE);
serial_dout(_port->ier, CONFIG_SYS_NS16550_IER);
serial_dout(_port->mcr, UART_MCRVAL);
-   serial_dout(_port->fcr, UART_FCRVAL);
+   serial_dout(_port->fcr, ns16550_getfcr(com_port));
 
serial_dout(_port->lcr, UART_LCR_BKSE | UART_LCRVAL);
serial_dout(_port->dll, baud_divisor & 0xff);
@@ -405,6 +417,8 @@ int ns16550_serial_ofdata_to_platdata(struct udevice *dev)
return -EINVAL;
}
 
+   plat->fcr = UART_FCRVAL;
+
return 0;
 }
 #endif
diff --git a/include/ns16550.h b/include/ns16550.h
index 1311f4c..45fd68b 100644
--- a/include/ns16550.h
+++ b/include/ns16550.h
@@ -57,6 +57,7 @@ struct ns16550_platdata {
int reg_shift;
int clock;
int reg_offset;
+   u32 fcr;
 };
 
 struct udevice;
-- 
2.7.0

___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Re: [U-Boot] [PATCH] serial: 16550: Add JZ47xx support

[Marek Vasut]

On 05/26/2016 03:55 PM, Paul Burton wrote:
> On Thu, May 26, 2016 at 02:05:07PM +0200, Marek Vasut wrote:
>>> Interesting :) May I ask which platform/SoC you're working with? Have
>>> you seen the (unfortunately currently out of tree) port we did for the
>>> JZ4780-based Ci20? I recall the pain of squeezing SPL down to a small
>>> enough size well...
>>
>> I bought the CI20, yeah. I started with that tree and am now getting it
>> into mainline shape. I actually managed to optimize the SPL, so it does
>> not overflow. One of the things which helped a lot was removing slop[1]
>> from the structures and using appropriate data types in them (like don't
>> use u32 to store an 8bit number). I also tinified the MMC stack, so that
>> it won't pull in too much useless code.
>>
>> At this point, I have a u-boot running from SD card and the SD driver in
>> full U-Boot is already probing from DT and using DM. I sent Daniel the
>> updated patches, but they are still work in progress. Nonetheless, if
>> you want me forward that to you as well, let me know.
>>
>> I plan to get this CI20 submitted at some point this or next week, so it
>> can land in 2016.07 (I hope!) and then debian and fedora-mips (and other
>> distros) can pick it up and package proper. That's how I see it.
> 
> That sounds great :) I'd be interested in seeing them but probably won't
> have any time to look at them for a few weeks anyway (busy with other
> work things & then getting married & going off on honeymoon!). So
> hopefully by the time I'd get round to having a look they'll be in
> mainline :)

Congratulations ! I sent you a separate mail and I'm going to submit
some of the stuff now too.

>> btw. what is the linux support status of the ci20 ? Is anyone working
>> on that? I saw the DTS in Linux, but it's pretty bare-bones.
> 
> Yeah the support in mainline Linux is a bit basic at the moment. The
> biggest holdup is pinctrl support which I need to do some work on - the
> DT bindings are more complicated than they need to be, and the driver
> should probably be made more generic to cover other Ingenic SoCs before
> it goes into mainline.

I wonder if I should drill into that now ;-)

>> btw2. can I get the ci40 anywhere or is that just unobtainium board ?
> 
> I'll email you separately about that.
> 
> Thanks,
> Paul
> 


-- 
Best regards,
Marek Vasut
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Re: [U-Boot] [PATCH v3 1/2] armv8: Support loading 32-bit OS in AArch32 execution state

[Alexander Graf]

On 26.05.16 10:41, Alison Wang wrote:
> To support loading a 32-bit OS, the execution state will change from
> AArch64 to AArch32 when jumping to kernel.
> 
> The architecture information will be got through checking FIT
> image, then U-Boot will load 32-bit OS or 64-bit OS automatically.
> 
> Signed-off-by: Ebony Zhu 
> Signed-off-by: Alison Wang 
> Signed-off-by: Chenhui Zhao 
> ---
> Changes in v3:
> - Comments the functions and the arguments.
> - Rename the real parameters.
> - Use the macros instead of the magic values.
> - Remove the redundant codes.
> - Clean up all of the mess in boot_jump_linux().
> - Add CONFIG_ARM64_SUPPORT_AARCH32 to detect for some ARM64 system doesn't 
> support AArch32 state.
> 
> Changes in v2:
> - armv8_switch_to_el2_aarch32() is removed. armv8_switch_to_el2_m is used
>   to switch to AArch64 EL2 or AArch32 Hyp.
> - armv8_switch_to_el1_aarch32() is removed. armv8_switch_to_el1_m is used
>   to switch to AArch64 EL1 or AArch32 SVC.
> 
>  arch/arm/Kconfig|   6 ++
>  arch/arm/cpu/armv8/transition.S |   8 +-
>  arch/arm/include/asm/macro.h| 174 
> ++--
>  arch/arm/include/asm/system.h   | 118 ++-
>  arch/arm/lib/bootm.c|  19 -
>  common/image-fit.c  |  14 +++-
>  6 files changed, 287 insertions(+), 52 deletions(-)
> 
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index 729b181..794cb4f 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -77,6 +77,12 @@ config SYS_L2CACHE_OFF
> If SoC does not support L2CACHE or one do not want to enable
> L2CACHE, choose this option.
>  
> +config ARM64_SUPPORT_AARCH32
> + bool "ARM64 system support AArch32 execution state"
> + default y if ARM64 && !CONFIG_THUNDERX

I don't think that works. In Kconfig you need to omit the CONFIG_ parts.
It's "ARM64" also, not "CONFIG_ARM64".

Please just try to run a local make defconfig on the thunderx reference
system and see whether it includes the option or not.

> + help
> +   This ARM64 system supports AArch32 execution state.
> +
>  choice
>   prompt "Target select"
>   default TARGET_HIKEY
> diff --git a/arch/arm/cpu/armv8/transition.S b/arch/arm/cpu/armv8/transition.S
> index 253a39b..417e8b4 100644
> --- a/arch/arm/cpu/armv8/transition.S
> +++ b/arch/arm/cpu/armv8/transition.S
> @@ -11,13 +11,13 @@
>  #include 
>  
>  ENTRY(armv8_switch_to_el2)
> - switch_el x0, 1f, 0f, 0f
> + switch_el x4, 1f, 0f, 0f
>  0:   ret
> -1:   armv8_switch_to_el2_m x0
> +1:   armv8_switch_to_el2_m x0, x1, x2, x3, x4
>  ENDPROC(armv8_switch_to_el2)
>  
>  ENTRY(armv8_switch_to_el1)
> - switch_el x0, 0f, 1f, 0f
> + switch_el x4, 0f, 1f, 0f
>  0:   ret
> -1:   armv8_switch_to_el1_m x0, x1
> +1:   armv8_switch_to_el1_m x0, x1, x2, x3, x4
>  ENDPROC(armv8_switch_to_el1)
> diff --git a/arch/arm/include/asm/macro.h b/arch/arm/include/asm/macro.h
> index 9bb0efa..dd2c510 100644
> --- a/arch/arm/include/asm/macro.h
> +++ b/arch/arm/include/asm/macro.h
> @@ -8,6 +8,9 @@
>  
>  #ifndef __ASM_ARM_MACRO_H__
>  #define __ASM_ARM_MACRO_H__
> +
> +#include 
> +
>  #ifdef __ASSEMBLY__
>  
>  /*
> @@ -135,13 +138,18 @@ lr  .reqx30
>  #endif
>  .endm
>  
> -.macro armv8_switch_to_el2_m, xreg1
> - /* 64bit EL2 | HCE | SMD | RES1 (Bits[5:4]) | Non-secure EL0/EL1 */
> - mov \xreg1, #0x5b1
> - msr scr_el3, \xreg1
> +/*
> + * Switch from EL3 to EL2 for ARMv8
> + * @ep: kernel entry point
> + * @arch:   machine nr
> + * @ftaddr: fdt address
> + * @flag:   The execution state flag for lower exception
> + *  level, ES_TO_AARCH64 or ES_TO_AARCH32
> + */
> +.macro armv8_switch_to_el2_m, ep, arch, ftaddr, flag, xreg5

You're never really using the arch and ftaddr arguments. Just describe
in the macro header that they need to be in x1 and x2 respectively and
leave them out of the argument list for the macro.

Also please rename "xreg5" to something like "scratchreg" or "tmp" or
"tmpreg". Then it's more obvious what this argument is about.

>   msr cptr_el3, xzr   /* Disable coprocessor traps to EL3 */
> - mov \xreg1, #0x33ff
> - msr cptr_el2, \xreg1/* Disable coprocessor traps to EL2 */
> + mov \xreg5, #(CPTR_EL2_BIT13_12_RES1 | CPTR_EL2_BIT9_0_RES1)
> + msr cptr_el2, \xreg5/* Disable coprocessor traps to EL2 */
>  
>   /* Initialize Generic Timers */
>   msr cntvoff_el2, xzr
> @@ -152,45 +160,92 @@ lr  .reqx30
>* and RES0 bits (31,30,27,26,24,21,20,17,15-13,10-6) +
>* EE,WXN,I,SA,C,A,M to 0
>*/
> - mov \xreg1, #0x0830
> - movk\xreg1, #0x30C5, lsl #16
> - msr sctlr_el2, \xreg1
> + ldr \xreg5, =(SCTLR_EL2_BIT29_28_RES1 | SCTLR_EL2_EE_LE |\
> +   SCTLR_EL2_BIT23_22_RES1 | SCTLR_EL2_WXN_DIS |\
> +  

Re: [U-Boot] [PATCH] serial: 16550: Add JZ47xx support

[Simon Glass]

Hi Marek,

On 26 May 2016 at 11:35, Marek Vasut  wrote:
> On 05/26/2016 07:07 PM, Simon Glass wrote:
>> Hi Marek,
>>
>> On 26 May 2016 at 10:53, Marek Vasut  wrote:
>>> On 05/26/2016 06:48 PM, Simon Glass wrote:
 Hi Marek,

 On 26 May 2016 at 10:47, Marek Vasut  wrote:
> On 05/26/2016 06:44 PM, Simon Glass wrote:
>> Hi Marek,
>>
>> On 26 May 2016 at 10:34, Marek Vasut  wrote:
>>> On 05/26/2016 03:29 PM, Simon Glass wrote:
 Hi Marek,

 On 25 May 2016 at 16:35, Marek Vasut  wrote:
> On 05/26/2016 12:31 AM, Daniel Schwierzeck wrote:
>>
>>
>> Am 26.05.2016 um 00:21 schrieb Marek Vasut:
>>> On 05/26/2016 12:17 AM, Daniel Schwierzeck wrote:


 Am 25.05.2016 um 02:19 schrieb Marek Vasut:
> The Ingenic JZ47xx requires special bit (UART_EN) set in FCR 
> register
> in order to work at all. Add this special case handling into the 
> driver.
>
> Signed-off-by: Marek Vasut 
> Cc: Tom Rini 
> Cc: Simon Glass 
> Cc: Daniel Schwierzeck 
> Cc: Paul Burton 
> ---
>  drivers/serial/ns16550.c | 8 
>  1 file changed, 8 insertions(+)
>
> diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c
> index 30ba0aa..1323881 100644
> --- a/drivers/serial/ns16550.c
> +++ b/drivers/serial/ns16550.c
> @@ -50,6 +50,14 @@ DECLARE_GLOBAL_DATA_PTR;
>  #endif
>  #endif
>
> +#ifdef CONFIG_ARCH_JZ47XX
> +#undef UART_FCRVAL
> +/* Ingenic JZ47xx SoCs require that a 'UART Module Enable' bit 
> be set */
> +#define UART_FCR_UME  0x10
> +#define UART_FCRVAL (UART_FCR_FIFO_EN | UART_FCR_RXSR |   \
> +   UART_FCR_TXSR | UART_FCR_UME)
> +#endif

 I think this could be added as DT property
>>>
>>> Not for SPL, which has 14 kiB size limit and it is itching to 
>>> overflow.
>>> I am literally counting bytes in the SPL and removing slop from
>>> structures to make it fit, just barely. With the USB loader, I can
>>> brutalize the SPL into having extremely rudimentary UART support now
>>> (like printch() being the most advanced output mechanism, but you 
>>> can
>>> only use it three times, otherwise the code won't fit and the board 
>>> is
>>> eaten by demons) and this is where this patch comes into play.
>>>
>>> So yes, for full u-boot, this _should_ be part of DT. For SPL, 
>>> please apply.
>>>
>>
>> ok, but wouldn't it be better to introduce an option like
>> CONFIG_SYS_NS16550_UME instead of using the SoC-specific
>> CONFIG_ARCH_JZ47XX. This driver is messed up enough ;)
>
> I was undecided between this (like the IER) and adding new ifdef (like
> SOC_KEYSTONE). Whichever way is fine with me. Yeah, the driver is
> repugnant for sure.
>
> +
>  #ifndef CONFIG_SYS_NS16550_IER
>  #define CONFIG_SYS_NS16550_IER  0x00
>  #endif /* CONFIG_SYS_NS16550_IER */
>

 That way seems better to me. You should be able to add your UME flag
 as a Kconfig for this driver, in drivers/serial/Kconfig, which
 defaults to 0. It would be good to keep out board-specific stuff from
 this file, as you did with OMAP1510.
>>>
>>> I'm not really sure I want to expose the CONFIG_SYS_NS16550_FCR override
>>> via Kconfig. The extra bits should be set via DT props
>>> unless there is some really good reason why that cannot be done
>>> (like size limitation in SPL or DT not available).
>>>
>>> I tried these approaches:
>>> 1) Add Kconfig option for CONFIG_SYS_NS16550_FCR , where you
>>>set specific byte value. This makes it hard to figure out
>>>which bits are set in the FCR just by looking at the value.
>>> 2) Add Kconfig option selected if ARCH_JZ47XX is selected and
>>>use that in the driver to add the extra UME bit.
>>> 3) Define CONFIG_SYS_NS16550_FCR in include/configs/board.h
>>>using the macros from ns16550.h . This makes it obvious
>>>which bits are set.
>>>
>>> I am undecided between 2 and 3, but inclined to go with 3.
>>> What do you think ?
>>
>> How about making your feature an option, like CONFIG_SYS_NS16550_UEN,
>> which defaults to 0, but in your case is 

Re: [U-Boot] [PATCH] serial: 16550: Add JZ47xx support

[Marek Vasut]

On 05/26/2016 07:07 PM, Simon Glass wrote:
> Hi Marek,
> 
> On 26 May 2016 at 10:53, Marek Vasut  wrote:
>> On 05/26/2016 06:48 PM, Simon Glass wrote:
>>> Hi Marek,
>>>
>>> On 26 May 2016 at 10:47, Marek Vasut  wrote:
 On 05/26/2016 06:44 PM, Simon Glass wrote:
> Hi Marek,
>
> On 26 May 2016 at 10:34, Marek Vasut  wrote:
>> On 05/26/2016 03:29 PM, Simon Glass wrote:
>>> Hi Marek,
>>>
>>> On 25 May 2016 at 16:35, Marek Vasut  wrote:
 On 05/26/2016 12:31 AM, Daniel Schwierzeck wrote:
>
>
> Am 26.05.2016 um 00:21 schrieb Marek Vasut:
>> On 05/26/2016 12:17 AM, Daniel Schwierzeck wrote:
>>>
>>>
>>> Am 25.05.2016 um 02:19 schrieb Marek Vasut:
 The Ingenic JZ47xx requires special bit (UART_EN) set in FCR 
 register
 in order to work at all. Add this special case handling into the 
 driver.

 Signed-off-by: Marek Vasut 
 Cc: Tom Rini 
 Cc: Simon Glass 
 Cc: Daniel Schwierzeck 
 Cc: Paul Burton 
 ---
  drivers/serial/ns16550.c | 8 
  1 file changed, 8 insertions(+)

 diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c
 index 30ba0aa..1323881 100644
 --- a/drivers/serial/ns16550.c
 +++ b/drivers/serial/ns16550.c
 @@ -50,6 +50,14 @@ DECLARE_GLOBAL_DATA_PTR;
  #endif
  #endif

 +#ifdef CONFIG_ARCH_JZ47XX
 +#undef UART_FCRVAL
 +/* Ingenic JZ47xx SoCs require that a 'UART Module Enable' bit be 
 set */
 +#define UART_FCR_UME  0x10
 +#define UART_FCRVAL (UART_FCR_FIFO_EN | UART_FCR_RXSR |   \
 +   UART_FCR_TXSR | UART_FCR_UME)
 +#endif
>>>
>>> I think this could be added as DT property
>>
>> Not for SPL, which has 14 kiB size limit and it is itching to 
>> overflow.
>> I am literally counting bytes in the SPL and removing slop from
>> structures to make it fit, just barely. With the USB loader, I can
>> brutalize the SPL into having extremely rudimentary UART support now
>> (like printch() being the most advanced output mechanism, but you can
>> only use it three times, otherwise the code won't fit and the board 
>> is
>> eaten by demons) and this is where this patch comes into play.
>>
>> So yes, for full u-boot, this _should_ be part of DT. For SPL, 
>> please apply.
>>
>
> ok, but wouldn't it be better to introduce an option like
> CONFIG_SYS_NS16550_UME instead of using the SoC-specific
> CONFIG_ARCH_JZ47XX. This driver is messed up enough ;)

 I was undecided between this (like the IER) and adding new ifdef (like
 SOC_KEYSTONE). Whichever way is fine with me. Yeah, the driver is
 repugnant for sure.

 +
  #ifndef CONFIG_SYS_NS16550_IER
  #define CONFIG_SYS_NS16550_IER  0x00
  #endif /* CONFIG_SYS_NS16550_IER */

>>>
>>> That way seems better to me. You should be able to add your UME flag
>>> as a Kconfig for this driver, in drivers/serial/Kconfig, which
>>> defaults to 0. It would be good to keep out board-specific stuff from
>>> this file, as you did with OMAP1510.
>>
>> I'm not really sure I want to expose the CONFIG_SYS_NS16550_FCR override
>> via Kconfig. The extra bits should be set via DT props
>> unless there is some really good reason why that cannot be done
>> (like size limitation in SPL or DT not available).
>>
>> I tried these approaches:
>> 1) Add Kconfig option for CONFIG_SYS_NS16550_FCR , where you
>>set specific byte value. This makes it hard to figure out
>>which bits are set in the FCR just by looking at the value.
>> 2) Add Kconfig option selected if ARCH_JZ47XX is selected and
>>use that in the driver to add the extra UME bit.
>> 3) Define CONFIG_SYS_NS16550_FCR in include/configs/board.h
>>using the macros from ns16550.h . This makes it obvious
>>which bits are set.
>>
>> I am undecided between 2 and 3, but inclined to go with 3.
>> What do you think ?
>
> How about making your feature an option, like CONFIG_SYS_NS16550_UEN,
> which defaults to 0, but in your case is 0x10. You can OR it into the
> value.

 That's quite close to 1) , but then what if someone comes and wants to
 remove some bits from the FCR instead of adding some?
>>>
>>> Seems 

Re: [U-Boot] [PATCH v2 11/11] sunxi: Add PSCI implementation in C

[Marc Zyngier]

On 26/05/16 15:01, Chen-Yu Tsai wrote:
> To make the PSCI backend more maintainable and easier to port to newer
> SoCs, rewrite the current PSCI implementation in C.
> 
> Some inline assembly bits are required to access coprocessor registers.
> PSCI stack setup is the only part left completely in assembly. In theory
> this part could be split out of psci_arch_init into a separate common
> function, and psci_arch_init could be completely in C.
> 
> Signed-off-by: Chen-Yu Tsai 
> ---
>  arch/arm/cpu/armv7/sunxi/Makefile |   7 +-
>  arch/arm/cpu/armv7/sunxi/psci.c   | 269 
> ++
>  arch/arm/cpu/armv7/sunxi/psci_head.S  |  66 +
>  arch/arm/cpu/armv7/sunxi/psci_sun6i.S | 262 -
>  arch/arm/cpu/armv7/sunxi/psci_sun7i.S | 237 --
>  5 files changed, 337 insertions(+), 504 deletions(-)
>  create mode 100644 arch/arm/cpu/armv7/sunxi/psci.c
>  create mode 100644 arch/arm/cpu/armv7/sunxi/psci_head.S
>  delete mode 100644 arch/arm/cpu/armv7/sunxi/psci_sun6i.S
>  delete mode 100644 arch/arm/cpu/armv7/sunxi/psci_sun7i.S
> 
> diff --git a/arch/arm/cpu/armv7/sunxi/Makefile 
> b/arch/arm/cpu/armv7/sunxi/Makefile
> index 4d2274a38ed1..c2085101685b 100644
> --- a/arch/arm/cpu/armv7/sunxi/Makefile
> +++ b/arch/arm/cpu/armv7/sunxi/Makefile
> @@ -13,11 +13,8 @@ obj-$(CONFIG_MACH_SUN6I)   += tzpc.o
>  obj-$(CONFIG_MACH_SUN8I_H3)  += tzpc.o
>  
>  ifndef CONFIG_SPL_BUILD
> -ifdef CONFIG_ARMV7_PSCI
> -obj-$(CONFIG_MACH_SUN6I) += psci_sun6i.o
> -obj-$(CONFIG_MACH_SUN7I) += psci_sun7i.o
> -obj-$(CONFIG_MACH_SUN8I) += psci_sun6i.o
> -endif
> +obj-$(CONFIG_ARMV7_PSCI) += psci.o
> +obj-$(CONFIG_ARMV7_PSCI) += psci_head.o
>  endif
>  
>  ifdef CONFIG_SPL_BUILD
> diff --git a/arch/arm/cpu/armv7/sunxi/psci.c b/arch/arm/cpu/armv7/sunxi/psci.c
> new file mode 100644
> index ..f0c151a349c8
> --- /dev/null
> +++ b/arch/arm/cpu/armv7/sunxi/psci.c
> @@ -0,0 +1,269 @@
> +/*
> + * Copyright (C) 2016
> + * Author: Chen-Yu Tsai 
> + *
> + * Based on assembly code by Marc Zyngier ,
> + * which was based on code by Carl van Schaik .
> + *
> + * SPDX-License-Identifier:  GPL-2.0
> + */
> +#include 
> +#include 
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +#include 
> +
> +#define __secure __attribute__ ((section ("._secure.text")))
> +#define __irq__attribute__ ((interrupt ("IRQ")))
> +
> +#define  GICD_BASE   (SUNXI_GIC400_BASE + GIC_DIST_OFFSET)
> +#define  GICC_BASE   (SUNXI_GIC400_BASE + GIC_CPU_OFFSET_A15)
> +
> +static void cp15_write_cntp_tval(u32 tval)
> +{
> + asm volatile ("mcr p15, 0, %0, c14, c2, 0" : : "r" (tval));
> +}
> +
> +static void cp15_write_cntp_ctl(u32 val)
> +{
> + asm volatile ("mcr p15, 0, %0, c14, c2, 1" : : "r" (val));
> +}
> +
> +static u32 cp15_read_cntp_ctl(void)
> +{
> + u32 val;
> +
> + asm volatile ("mrc p15, 0, %0, c14, c2, 1" : "=r" (val));
> +
> + return val;
> +}
> +
> +static void __secure __mdelay(u32 ms)
> +{
> + u32 reg = DIV_ROUND_UP(CONFIG_TIMER_CLK_FREQ, ms);
> +
> + cp15_write_cntp_tval(reg);
> + ISB;
> + cp15_write_cntp_ctl(3);
> +
> + do {
> + ISB;
> + reg = cp15_read_cntp_ctl();
> + } while (!(reg & BIT(2)));
> +
> + cp15_write_cntp_ctl(0);
> +}
> +
> +#ifdef CONFIG_MACH_SUN7I
> +/* sun7i (A20) is different from other single cluster SoCs */
> +static void sunxi_cpu_set_power(int __always_unused cpu, bool on)

Missing __secure annotation?

> +{
> + struct sunxi_cpucfg_reg *cpucfg =
> + (struct sunxi_cpucfg_reg *)SUNXI_CPUCFG_BASE;
> +
> + if (on) {
> + /* Release power clamp */
> + u32 tmp = 0x1ff;
> + do {
> + tmp >>= 1;
> + writel(tmp, >cpu1_pwr_clamp);
> + } while (tmp);
> +
> + __mdelay(10);
> +
> + /* Clear power gating */
> + clrbits_le32(>cpu1_pwroff, BIT(0));
> + } else {
> + /* Set power gating */
> + setbits_le32(>cpu1_pwroff, BIT(0));
> +
> + /* Activate power clamp */
> + writel(0xff, >cpu1_pwr_clamp);
> + }
> +}
> +#else /* ! CONFIG_MACH_SUN7I */
> +static void sunxi_cpu_set_power(int cpu, bool on)

Same here?

> +{
> + struct sunxi_prcm_reg *prcm =
> + (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
> +
> + if (on) {
> +#if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN8I_H3)
> + /* Release power clamp (A31 & H3 only) */
> + u32 tmp = 0x1ff;
> + do {
> + tmp >>= 1;
> + writel(tmp, >cpu_pwr_clamp[cpu]);
> + } while (tmp);
> +#endif

Do you still need these #ifdefs now that you've split the code from the
sun7i 

Re: [U-Boot] [PATCH v3 1/2] armv8: Support loading 32-bit OS in AArch32 execution state

[York Sun]

On 05/26/2016 01:51 AM, Alison Wang wrote:
> To support loading a 32-bit OS, the execution state will change from
> AArch64 to AArch32 when jumping to kernel.
> 
> The architecture information will be got through checking FIT
> image, then U-Boot will load 32-bit OS or 64-bit OS automatically.
> 
> Signed-off-by: Ebony Zhu 
> Signed-off-by: Alison Wang 
> Signed-off-by: Chenhui Zhao 
> ---
> Changes in v3:
> - Comments the functions and the arguments.
> - Rename the real parameters.
> - Use the macros instead of the magic values.
> - Remove the redundant codes.
> - Clean up all of the mess in boot_jump_linux().
> - Add CONFIG_ARM64_SUPPORT_AARCH32 to detect for some ARM64 system doesn't 
> support AArch32 state.
> 
> Changes in v2:
> - armv8_switch_to_el2_aarch32() is removed. armv8_switch_to_el2_m is used
>   to switch to AArch64 EL2 or AArch32 Hyp.
> - armv8_switch_to_el1_aarch32() is removed. armv8_switch_to_el1_m is used
>   to switch to AArch64 EL1 or AArch32 SVC.
> 
>  arch/arm/Kconfig|   6 ++
>  arch/arm/cpu/armv8/transition.S |   8 +-
>  arch/arm/include/asm/macro.h| 174 
> ++--
>  arch/arm/include/asm/system.h   | 118 ++-
>  arch/arm/lib/bootm.c|  19 -
>  common/image-fit.c  |  14 +++-
>  6 files changed, 287 insertions(+), 52 deletions(-)
> 
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index 729b181..794cb4f 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -77,6 +77,12 @@ config SYS_L2CACHE_OFF
> If SoC does not support L2CACHE or one do not want to enable
> L2CACHE, choose this option.
>  
> +config ARM64_SUPPORT_AARCH32
> + bool "ARM64 system support AArch32 execution state"
> + default y if ARM64 && !CONFIG_THUNDERX
> + help
> +   This ARM64 system supports AArch32 execution state.
> +
>  choice
>   prompt "Target select"
>   default TARGET_HIKEY
> diff --git a/arch/arm/cpu/armv8/transition.S b/arch/arm/cpu/armv8/transition.S
> index 253a39b..417e8b4 100644
> --- a/arch/arm/cpu/armv8/transition.S
> +++ b/arch/arm/cpu/armv8/transition.S
> @@ -11,13 +11,13 @@
>  #include 
>  
>  ENTRY(armv8_switch_to_el2)
> - switch_el x0, 1f, 0f, 0f
> + switch_el x4, 1f, 0f, 0f
>  0:   ret
> -1:   armv8_switch_to_el2_m x0
> +1:   armv8_switch_to_el2_m x0, x1, x2, x3, x4
>  ENDPROC(armv8_switch_to_el2)

Alison,

I see you are chaning macro armv8_switch_to_el2. You may have missed one in
start.S. This is the code you can't test with our ARMv8 chip.

York

___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Re: [U-Boot] [PATCH] serial: 16550: Add JZ47xx support

[Simon Glass]

Hi Marek,

On 26 May 2016 at 10:53, Marek Vasut  wrote:
> On 05/26/2016 06:48 PM, Simon Glass wrote:
>> Hi Marek,
>>
>> On 26 May 2016 at 10:47, Marek Vasut  wrote:
>>> On 05/26/2016 06:44 PM, Simon Glass wrote:
 Hi Marek,

 On 26 May 2016 at 10:34, Marek Vasut  wrote:
> On 05/26/2016 03:29 PM, Simon Glass wrote:
>> Hi Marek,
>>
>> On 25 May 2016 at 16:35, Marek Vasut  wrote:
>>> On 05/26/2016 12:31 AM, Daniel Schwierzeck wrote:


 Am 26.05.2016 um 00:21 schrieb Marek Vasut:
> On 05/26/2016 12:17 AM, Daniel Schwierzeck wrote:
>>
>>
>> Am 25.05.2016 um 02:19 schrieb Marek Vasut:
>>> The Ingenic JZ47xx requires special bit (UART_EN) set in FCR 
>>> register
>>> in order to work at all. Add this special case handling into the 
>>> driver.
>>>
>>> Signed-off-by: Marek Vasut 
>>> Cc: Tom Rini 
>>> Cc: Simon Glass 
>>> Cc: Daniel Schwierzeck 
>>> Cc: Paul Burton 
>>> ---
>>>  drivers/serial/ns16550.c | 8 
>>>  1 file changed, 8 insertions(+)
>>>
>>> diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c
>>> index 30ba0aa..1323881 100644
>>> --- a/drivers/serial/ns16550.c
>>> +++ b/drivers/serial/ns16550.c
>>> @@ -50,6 +50,14 @@ DECLARE_GLOBAL_DATA_PTR;
>>>  #endif
>>>  #endif
>>>
>>> +#ifdef CONFIG_ARCH_JZ47XX
>>> +#undef UART_FCRVAL
>>> +/* Ingenic JZ47xx SoCs require that a 'UART Module Enable' bit be 
>>> set */
>>> +#define UART_FCR_UME  0x10
>>> +#define UART_FCRVAL (UART_FCR_FIFO_EN | UART_FCR_RXSR |   \
>>> +   UART_FCR_TXSR | UART_FCR_UME)
>>> +#endif
>>
>> I think this could be added as DT property
>
> Not for SPL, which has 14 kiB size limit and it is itching to 
> overflow.
> I am literally counting bytes in the SPL and removing slop from
> structures to make it fit, just barely. With the USB loader, I can
> brutalize the SPL into having extremely rudimentary UART support now
> (like printch() being the most advanced output mechanism, but you can
> only use it three times, otherwise the code won't fit and the board is
> eaten by demons) and this is where this patch comes into play.
>
> So yes, for full u-boot, this _should_ be part of DT. For SPL, please 
> apply.
>

 ok, but wouldn't it be better to introduce an option like
 CONFIG_SYS_NS16550_UME instead of using the SoC-specific
 CONFIG_ARCH_JZ47XX. This driver is messed up enough ;)
>>>
>>> I was undecided between this (like the IER) and adding new ifdef (like
>>> SOC_KEYSTONE). Whichever way is fine with me. Yeah, the driver is
>>> repugnant for sure.
>>>
>>> +
>>>  #ifndef CONFIG_SYS_NS16550_IER
>>>  #define CONFIG_SYS_NS16550_IER  0x00
>>>  #endif /* CONFIG_SYS_NS16550_IER */
>>>
>>
>> That way seems better to me. You should be able to add your UME flag
>> as a Kconfig for this driver, in drivers/serial/Kconfig, which
>> defaults to 0. It would be good to keep out board-specific stuff from
>> this file, as you did with OMAP1510.
>
> I'm not really sure I want to expose the CONFIG_SYS_NS16550_FCR override
> via Kconfig. The extra bits should be set via DT props
> unless there is some really good reason why that cannot be done
> (like size limitation in SPL or DT not available).
>
> I tried these approaches:
> 1) Add Kconfig option for CONFIG_SYS_NS16550_FCR , where you
>set specific byte value. This makes it hard to figure out
>which bits are set in the FCR just by looking at the value.
> 2) Add Kconfig option selected if ARCH_JZ47XX is selected and
>use that in the driver to add the extra UME bit.
> 3) Define CONFIG_SYS_NS16550_FCR in include/configs/board.h
>using the macros from ns16550.h . This makes it obvious
>which bits are set.
>
> I am undecided between 2 and 3, but inclined to go with 3.
> What do you think ?

 How about making your feature an option, like CONFIG_SYS_NS16550_UEN,
 which defaults to 0, but in your case is 0x10. You can OR it into the
 value.
>>>
>>> That's quite close to 1) , but then what if someone comes and wants to
>>> remove some bits from the FCR instead of adding some?
>>
>> Seems like speculative complexity to me - let's worry about it when it 
>> happens!
>
> Heh, ok. But if we add Kconfig stuff, we can as well go with option 2) ,
> which would only 

Re: [U-Boot] [PATCH] serial: 16550: Add JZ47xx support

[Marek Vasut]

On 05/26/2016 06:48 PM, Simon Glass wrote:
> Hi Marek,
> 
> On 26 May 2016 at 10:47, Marek Vasut  wrote:
>> On 05/26/2016 06:44 PM, Simon Glass wrote:
>>> Hi Marek,
>>>
>>> On 26 May 2016 at 10:34, Marek Vasut  wrote:
 On 05/26/2016 03:29 PM, Simon Glass wrote:
> Hi Marek,
>
> On 25 May 2016 at 16:35, Marek Vasut  wrote:
>> On 05/26/2016 12:31 AM, Daniel Schwierzeck wrote:
>>>
>>>
>>> Am 26.05.2016 um 00:21 schrieb Marek Vasut:
 On 05/26/2016 12:17 AM, Daniel Schwierzeck wrote:
>
>
> Am 25.05.2016 um 02:19 schrieb Marek Vasut:
>> The Ingenic JZ47xx requires special bit (UART_EN) set in FCR register
>> in order to work at all. Add this special case handling into the 
>> driver.
>>
>> Signed-off-by: Marek Vasut 
>> Cc: Tom Rini 
>> Cc: Simon Glass 
>> Cc: Daniel Schwierzeck 
>> Cc: Paul Burton 
>> ---
>>  drivers/serial/ns16550.c | 8 
>>  1 file changed, 8 insertions(+)
>>
>> diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c
>> index 30ba0aa..1323881 100644
>> --- a/drivers/serial/ns16550.c
>> +++ b/drivers/serial/ns16550.c
>> @@ -50,6 +50,14 @@ DECLARE_GLOBAL_DATA_PTR;
>>  #endif
>>  #endif
>>
>> +#ifdef CONFIG_ARCH_JZ47XX
>> +#undef UART_FCRVAL
>> +/* Ingenic JZ47xx SoCs require that a 'UART Module Enable' bit be 
>> set */
>> +#define UART_FCR_UME  0x10
>> +#define UART_FCRVAL (UART_FCR_FIFO_EN | UART_FCR_RXSR |   \
>> +   UART_FCR_TXSR | UART_FCR_UME)
>> +#endif
>
> I think this could be added as DT property

 Not for SPL, which has 14 kiB size limit and it is itching to overflow.
 I am literally counting bytes in the SPL and removing slop from
 structures to make it fit, just barely. With the USB loader, I can
 brutalize the SPL into having extremely rudimentary UART support now
 (like printch() being the most advanced output mechanism, but you can
 only use it three times, otherwise the code won't fit and the board is
 eaten by demons) and this is where this patch comes into play.

 So yes, for full u-boot, this _should_ be part of DT. For SPL, please 
 apply.

>>>
>>> ok, but wouldn't it be better to introduce an option like
>>> CONFIG_SYS_NS16550_UME instead of using the SoC-specific
>>> CONFIG_ARCH_JZ47XX. This driver is messed up enough ;)
>>
>> I was undecided between this (like the IER) and adding new ifdef (like
>> SOC_KEYSTONE). Whichever way is fine with me. Yeah, the driver is
>> repugnant for sure.
>>
>> +
>>  #ifndef CONFIG_SYS_NS16550_IER
>>  #define CONFIG_SYS_NS16550_IER  0x00
>>  #endif /* CONFIG_SYS_NS16550_IER */
>>
>
> That way seems better to me. You should be able to add your UME flag
> as a Kconfig for this driver, in drivers/serial/Kconfig, which
> defaults to 0. It would be good to keep out board-specific stuff from
> this file, as you did with OMAP1510.

 I'm not really sure I want to expose the CONFIG_SYS_NS16550_FCR override
 via Kconfig. The extra bits should be set via DT props
 unless there is some really good reason why that cannot be done
 (like size limitation in SPL or DT not available).

 I tried these approaches:
 1) Add Kconfig option for CONFIG_SYS_NS16550_FCR , where you
set specific byte value. This makes it hard to figure out
which bits are set in the FCR just by looking at the value.
 2) Add Kconfig option selected if ARCH_JZ47XX is selected and
use that in the driver to add the extra UME bit.
 3) Define CONFIG_SYS_NS16550_FCR in include/configs/board.h
using the macros from ns16550.h . This makes it obvious
which bits are set.

 I am undecided between 2 and 3, but inclined to go with 3.
 What do you think ?
>>>
>>> How about making your feature an option, like CONFIG_SYS_NS16550_UEN,
>>> which defaults to 0, but in your case is 0x10. You can OR it into the
>>> value.
>>
>> That's quite close to 1) , but then what if someone comes and wants to
>> remove some bits from the FCR instead of adding some?
> 
> Seems like speculative complexity to me - let's worry about it when it 
> happens!

Maybe this is not even worth the effort and I should just ignore serial
support in SPL and only go with serial support in full u-boot, where I
can configure the FCR from DT. Then we avoid all this complex stuff.


-- 
Best regards,
Marek Vasut
___
U-Boot 

Re: [U-Boot] [PATCH] serial: 16550: Add JZ47xx support

[Marek Vasut]

On 05/26/2016 06:48 PM, Simon Glass wrote:
> Hi Marek,
> 
> On 26 May 2016 at 10:47, Marek Vasut  wrote:
>> On 05/26/2016 06:44 PM, Simon Glass wrote:
>>> Hi Marek,
>>>
>>> On 26 May 2016 at 10:34, Marek Vasut  wrote:
 On 05/26/2016 03:29 PM, Simon Glass wrote:
> Hi Marek,
>
> On 25 May 2016 at 16:35, Marek Vasut  wrote:
>> On 05/26/2016 12:31 AM, Daniel Schwierzeck wrote:
>>>
>>>
>>> Am 26.05.2016 um 00:21 schrieb Marek Vasut:
 On 05/26/2016 12:17 AM, Daniel Schwierzeck wrote:
>
>
> Am 25.05.2016 um 02:19 schrieb Marek Vasut:
>> The Ingenic JZ47xx requires special bit (UART_EN) set in FCR register
>> in order to work at all. Add this special case handling into the 
>> driver.
>>
>> Signed-off-by: Marek Vasut 
>> Cc: Tom Rini 
>> Cc: Simon Glass 
>> Cc: Daniel Schwierzeck 
>> Cc: Paul Burton 
>> ---
>>  drivers/serial/ns16550.c | 8 
>>  1 file changed, 8 insertions(+)
>>
>> diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c
>> index 30ba0aa..1323881 100644
>> --- a/drivers/serial/ns16550.c
>> +++ b/drivers/serial/ns16550.c
>> @@ -50,6 +50,14 @@ DECLARE_GLOBAL_DATA_PTR;
>>  #endif
>>  #endif
>>
>> +#ifdef CONFIG_ARCH_JZ47XX
>> +#undef UART_FCRVAL
>> +/* Ingenic JZ47xx SoCs require that a 'UART Module Enable' bit be 
>> set */
>> +#define UART_FCR_UME  0x10
>> +#define UART_FCRVAL (UART_FCR_FIFO_EN | UART_FCR_RXSR |   \
>> +   UART_FCR_TXSR | UART_FCR_UME)
>> +#endif
>
> I think this could be added as DT property

 Not for SPL, which has 14 kiB size limit and it is itching to overflow.
 I am literally counting bytes in the SPL and removing slop from
 structures to make it fit, just barely. With the USB loader, I can
 brutalize the SPL into having extremely rudimentary UART support now
 (like printch() being the most advanced output mechanism, but you can
 only use it three times, otherwise the code won't fit and the board is
 eaten by demons) and this is where this patch comes into play.

 So yes, for full u-boot, this _should_ be part of DT. For SPL, please 
 apply.

>>>
>>> ok, but wouldn't it be better to introduce an option like
>>> CONFIG_SYS_NS16550_UME instead of using the SoC-specific
>>> CONFIG_ARCH_JZ47XX. This driver is messed up enough ;)
>>
>> I was undecided between this (like the IER) and adding new ifdef (like
>> SOC_KEYSTONE). Whichever way is fine with me. Yeah, the driver is
>> repugnant for sure.
>>
>> +
>>  #ifndef CONFIG_SYS_NS16550_IER
>>  #define CONFIG_SYS_NS16550_IER  0x00
>>  #endif /* CONFIG_SYS_NS16550_IER */
>>
>
> That way seems better to me. You should be able to add your UME flag
> as a Kconfig for this driver, in drivers/serial/Kconfig, which
> defaults to 0. It would be good to keep out board-specific stuff from
> this file, as you did with OMAP1510.

 I'm not really sure I want to expose the CONFIG_SYS_NS16550_FCR override
 via Kconfig. The extra bits should be set via DT props
 unless there is some really good reason why that cannot be done
 (like size limitation in SPL or DT not available).

 I tried these approaches:
 1) Add Kconfig option for CONFIG_SYS_NS16550_FCR , where you
set specific byte value. This makes it hard to figure out
which bits are set in the FCR just by looking at the value.
 2) Add Kconfig option selected if ARCH_JZ47XX is selected and
use that in the driver to add the extra UME bit.
 3) Define CONFIG_SYS_NS16550_FCR in include/configs/board.h
using the macros from ns16550.h . This makes it obvious
which bits are set.

 I am undecided between 2 and 3, but inclined to go with 3.
 What do you think ?
>>>
>>> How about making your feature an option, like CONFIG_SYS_NS16550_UEN,
>>> which defaults to 0, but in your case is 0x10. You can OR it into the
>>> value.
>>
>> That's quite close to 1) , but then what if someone comes and wants to
>> remove some bits from the FCR instead of adding some?
> 
> Seems like speculative complexity to me - let's worry about it when it 
> happens!

Heh, ok. But if we add Kconfig stuff, we can as well go with option 2) ,
which would only show up if JZ47XX is selected. Since this bits is
specific to this lineup of SoCs , that makes sense in my head. What do
you think ?


-- 
Best regards,
Marek Vasut

Re: [U-Boot] [PATCH v2 04/11] ARM: allocate extra space for PSCI stack in secure section during link phase

[Marc Zyngier]

On 26/05/16 15:01, Chen-Yu Tsai wrote:
> The PSCI implementation expects at most 2 pages worth of space reserved
> at the end of the secure section for its stacks. If PSCI is relocated to
> secure SRAM, then everything is fine. If no secure SRAM is available,
> and PSCI remains in main memory, the reserved memory space doesn't cover
> the space used by the stack.
> 
> If one accesses PSCI after Linux has fully booted, the memory that should
> have been reserved for the PSCI stacks may have been used by the kernel
> or userspace, and would be corrupted. Observed after effects include the
> system hanging or telinit core dumping when trying to reboot. It seems
> the init process gets hit the most on my test bed.
> 
> This fix allocates the space used by the PSCI stacks in the secure
> section by skipping pages in the linker script, but only when there is
> no secure SRAM, to avoid bloating the binary.
> 
> This fix is only a stop gap. It would be better to rework the stack
> allocation mechanism, maybe with proper usage of CONFIG_ macros and an
> explicit symbol.
> 
> Signed-off-by: Chen-Yu Tsai 
> 
> squash! ARM: allocate extra space for PSCI stack in secure section during 
> link phase
> ---
>  arch/arm/cpu/u-boot.lds | 7 +++
>  1 file changed, 7 insertions(+)
> 
> diff --git a/arch/arm/cpu/u-boot.lds b/arch/arm/cpu/u-boot.lds
> index cfab8b041234..0770f8c878d1 100644
> --- a/arch/arm/cpu/u-boot.lds
> +++ b/arch/arm/cpu/u-boot.lds
> @@ -50,6 +50,7 @@ SECTIONS
>  
>  #ifndef CONFIG_ARMV7_SECURE_BASE
>  #define CONFIG_ARMV7_SECURE_BASE
> +#define __ARMV7_ALLOCATE_SECURE_STACK

ALLOCATE_SECURE_STACK is a bit of a misnomer, because nothing is secure
at all there (it is in RAM).

Something like PSCI_RAM_STACK would be more accurate.

>  #endif
>  
>   .__secure_start : {
> @@ -67,6 +68,12 @@ SECTIONS
>   SIZEOF(.__secure_start) +
>   SIZEOF(.secure_text);
>  
> +#ifdef __ARMV7_ALLOCATE_SECURE_STACK
> + /* Align to page boundary and skip 2 pages */
> + . = (. & ~ 0xfff) + 0x2000;
> +#undef __ARMV7_ALLOCATE_SECURE_STACK
> +#endif
> +
>   __secure_end_lma = .;
>   .__secure_end : AT(__secure_end_lma) {
>   *(.__secure_end)
> 

Thanks,

M.
-- 
Jazz is not dead. It just smells funny...
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Re: [U-Boot] [PATCH v2 03/11] ARM: PSCI: export common PSCI function declarations for C code

[Marc Zyngier]

On 26/05/16 15:01, Chen-Yu Tsai wrote:
> Some common PSCI functions are written in assembly, but it should be
> possible to use them from C code.
> 
> Add function declarations for C code to consume.
> 
> Signed-off-by: Chen-Yu Tsai 
> ---
>  arch/arm/include/asm/psci.h | 8 
>  1 file changed, 8 insertions(+)
> 
> diff --git a/arch/arm/include/asm/psci.h b/arch/arm/include/asm/psci.h
> index 128a606444fe..8b245139cbdb 100644
> --- a/arch/arm/include/asm/psci.h
> +++ b/arch/arm/include/asm/psci.h
> @@ -33,6 +33,14 @@
>  #define ARM_PSCI_RET_DENIED  (-3)
>  
>  #ifndef __ASSEMBLY__
> +#include 
> +#include 

nit: you don't need any of these #include.

> +
> +void psci_cpu_entry(void);
> +u32 psci_get_cpu_id(void);
> +u32 psci_get_cpu_stack_top(int cpu);
> +void psci_cpu_off_common(void);
> +
>  int psci_update_dt(void *fdt);
>  void psci_board_init(void);
>  #endif /* ! __ASSEMBLY__ */
> 

Thanks,

M.
-- 
Jazz is not dead. It just smells funny...
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Re: [U-Boot] [PATCH] serial: 16550: Add JZ47xx support

[Simon Glass]

Hi Marek,

On 26 May 2016 at 10:47, Marek Vasut  wrote:
> On 05/26/2016 06:44 PM, Simon Glass wrote:
>> Hi Marek,
>>
>> On 26 May 2016 at 10:34, Marek Vasut  wrote:
>>> On 05/26/2016 03:29 PM, Simon Glass wrote:
 Hi Marek,

 On 25 May 2016 at 16:35, Marek Vasut  wrote:
> On 05/26/2016 12:31 AM, Daniel Schwierzeck wrote:
>>
>>
>> Am 26.05.2016 um 00:21 schrieb Marek Vasut:
>>> On 05/26/2016 12:17 AM, Daniel Schwierzeck wrote:


 Am 25.05.2016 um 02:19 schrieb Marek Vasut:
> The Ingenic JZ47xx requires special bit (UART_EN) set in FCR register
> in order to work at all. Add this special case handling into the 
> driver.
>
> Signed-off-by: Marek Vasut 
> Cc: Tom Rini 
> Cc: Simon Glass 
> Cc: Daniel Schwierzeck 
> Cc: Paul Burton 
> ---
>  drivers/serial/ns16550.c | 8 
>  1 file changed, 8 insertions(+)
>
> diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c
> index 30ba0aa..1323881 100644
> --- a/drivers/serial/ns16550.c
> +++ b/drivers/serial/ns16550.c
> @@ -50,6 +50,14 @@ DECLARE_GLOBAL_DATA_PTR;
>  #endif
>  #endif
>
> +#ifdef CONFIG_ARCH_JZ47XX
> +#undef UART_FCRVAL
> +/* Ingenic JZ47xx SoCs require that a 'UART Module Enable' bit be 
> set */
> +#define UART_FCR_UME  0x10
> +#define UART_FCRVAL (UART_FCR_FIFO_EN | UART_FCR_RXSR |   \
> +   UART_FCR_TXSR | UART_FCR_UME)
> +#endif

 I think this could be added as DT property
>>>
>>> Not for SPL, which has 14 kiB size limit and it is itching to overflow.
>>> I am literally counting bytes in the SPL and removing slop from
>>> structures to make it fit, just barely. With the USB loader, I can
>>> brutalize the SPL into having extremely rudimentary UART support now
>>> (like printch() being the most advanced output mechanism, but you can
>>> only use it three times, otherwise the code won't fit and the board is
>>> eaten by demons) and this is where this patch comes into play.
>>>
>>> So yes, for full u-boot, this _should_ be part of DT. For SPL, please 
>>> apply.
>>>
>>
>> ok, but wouldn't it be better to introduce an option like
>> CONFIG_SYS_NS16550_UME instead of using the SoC-specific
>> CONFIG_ARCH_JZ47XX. This driver is messed up enough ;)
>
> I was undecided between this (like the IER) and adding new ifdef (like
> SOC_KEYSTONE). Whichever way is fine with me. Yeah, the driver is
> repugnant for sure.
>
> +
>  #ifndef CONFIG_SYS_NS16550_IER
>  #define CONFIG_SYS_NS16550_IER  0x00
>  #endif /* CONFIG_SYS_NS16550_IER */
>

 That way seems better to me. You should be able to add your UME flag
 as a Kconfig for this driver, in drivers/serial/Kconfig, which
 defaults to 0. It would be good to keep out board-specific stuff from
 this file, as you did with OMAP1510.
>>>
>>> I'm not really sure I want to expose the CONFIG_SYS_NS16550_FCR override
>>> via Kconfig. The extra bits should be set via DT props
>>> unless there is some really good reason why that cannot be done
>>> (like size limitation in SPL or DT not available).
>>>
>>> I tried these approaches:
>>> 1) Add Kconfig option for CONFIG_SYS_NS16550_FCR , where you
>>>set specific byte value. This makes it hard to figure out
>>>which bits are set in the FCR just by looking at the value.
>>> 2) Add Kconfig option selected if ARCH_JZ47XX is selected and
>>>use that in the driver to add the extra UME bit.
>>> 3) Define CONFIG_SYS_NS16550_FCR in include/configs/board.h
>>>using the macros from ns16550.h . This makes it obvious
>>>which bits are set.
>>>
>>> I am undecided between 2 and 3, but inclined to go with 3.
>>> What do you think ?
>>
>> How about making your feature an option, like CONFIG_SYS_NS16550_UEN,
>> which defaults to 0, but in your case is 0x10. You can OR it into the
>> value.
>
> That's quite close to 1) , but then what if someone comes and wants to
> remove some bits from the FCR instead of adding some?

Seems like speculative complexity to me - let's worry about it when it happens!

- Simon
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Re: [U-Boot] [PATCH 3/3] MIPS: Abstract cache op loops with a macro

[Marek Vasut]

On 05/26/2016 05:58 PM, Paul Burton wrote:
> The various cache maintenance routines perform a number of loops over
> cache lines. Rather than duplicate the code for performing such loops,
> abstract it out into a new cache_loop macro which performs an arbitrary
> number of cache ops on a range of addresses. This reduces duplication in
> the existing L1 cache maintenance code & will allow for not adding
> further duplication when introducing L2 cache support.
> 
> Signed-off-by: Paul Burton 
> 
> ---
> 
>  arch/mips/lib/cache.c | 59 
> ---
>  1 file changed, 18 insertions(+), 41 deletions(-)
> 
> diff --git a/arch/mips/lib/cache.c b/arch/mips/lib/cache.c
> index 2bb91c6..320335c 100644
> --- a/arch/mips/lib/cache.c
> +++ b/arch/mips/lib/cache.c
> @@ -37,82 +37,59 @@ static inline unsigned long dcache_line_size(void)
>   return 2 << dl;
>  }
>  
> +#define cache_loop(start, end, lsize, ops...) do {   \
> + const void *addr = (const void *)(start & ~(lsize - 1));\
> + const void *aend = (const void *)((end - 1) & ~(lsize - 1));\
> + const unsigned int cache_ops[] = { ops };   \

Can't you turn this into a function instead and pass some flags to
select the ops instead ?

> + unsigned int i; \
> + \
> + for (; addr <= aend; addr += lsize) {   \
> + for (i = 0; i < ARRAY_SIZE(cache_ops); i++) \
> + mips_cache(cache_ops[i], addr); \
> + }   \
> +} while (0)
> +
>  void flush_cache(ulong start_addr, ulong size)
>  {
>   unsigned long ilsize = icache_line_size();
>   unsigned long dlsize = dcache_line_size();
> - const void *addr, *aend;
>  
>   /* aend will be miscalculated when size is zero, so we return here */
>   if (size == 0)
>   return;
>  
> - addr = (const void *)(start_addr & ~(dlsize - 1));
> - aend = (const void *)((start_addr + size - 1) & ~(dlsize - 1));
> -
>   if (ilsize == dlsize) {
>   /* flush I-cache & D-cache simultaneously */
> - while (1) {
> - mips_cache(HIT_WRITEBACK_INV_D, addr);
> - mips_cache(HIT_INVALIDATE_I, addr);
> - if (addr == aend)
> - break;
> - addr += dlsize;
> - }
> + cache_loop(start_addr, start_addr + size, ilsize,
> +HIT_WRITEBACK_INV_D, HIT_INVALIDATE_I);
>   return;
>   }
>  
>   /* flush D-cache */
> - while (1) {
> - mips_cache(HIT_WRITEBACK_INV_D, addr);
> - if (addr == aend)
> - break;
> - addr += dlsize;
> - }
> + cache_loop(start_addr, start_addr + size, dlsize, HIT_WRITEBACK_INV_D);
>  
>   /* flush I-cache */
> - addr = (const void *)(start_addr & ~(ilsize - 1));
> - aend = (const void *)((start_addr + size - 1) & ~(ilsize - 1));
> - while (1) {
> - mips_cache(HIT_INVALIDATE_I, addr);
> - if (addr == aend)
> - break;
> - addr += ilsize;
> - }
> + cache_loop(start_addr, start_addr + size, ilsize, HIT_INVALIDATE_I);
>  }
>  
>  void flush_dcache_range(ulong start_addr, ulong stop)
>  {
>   unsigned long lsize = dcache_line_size();
> - const void *addr = (const void *)(start_addr & ~(lsize - 1));
> - const void *aend = (const void *)((stop - 1) & ~(lsize - 1));
>  
>   /* aend will be miscalculated when size is zero, so we return here */
>   if (start_addr == stop)
>   return;
>  
> - while (1) {
> - mips_cache(HIT_WRITEBACK_INV_D, addr);
> - if (addr == aend)
> - break;
> - addr += lsize;
> - }
> + cache_loop(start_addr, stop, lsize, HIT_WRITEBACK_INV_D);
>  }
>  
>  void invalidate_dcache_range(ulong start_addr, ulong stop)
>  {
>   unsigned long lsize = dcache_line_size();
> - const void *addr = (const void *)(start_addr & ~(lsize - 1));
> - const void *aend = (const void *)((stop - 1) & ~(lsize - 1));
>  
>   /* aend will be miscalculated when size is zero, so we return here */
>   if (start_addr == stop)
>   return;
>  
> - while (1) {
> - mips_cache(HIT_INVALIDATE_D, addr);
> - if (addr == aend)
> - break;
> - addr += lsize;
> - }
> + cache_loop(start_addr, stop, lsize, HIT_INVALIDATE_I);
>  }
> 


-- 
Best regards,
Marek Vasut
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Re: [U-Boot] [PATCH 2/3] MIPS: Split I & D cache line size config

[Marek Vasut]

On 05/26/2016 05:58 PM, Paul Burton wrote:
> Allow L1 Icache & L1 Dcache line size to be specified separately, since
> there's no architectural mandate that they be the same. The
> [id]cache_line_size functions are tidied up to take advantage of the
> fact that the Kconfig entries are always present to simply check them
> for zero rather than needing to #ifdef on their presence.
> 
> Signed-off-by: Paul Burton 
> ---
> 
>  arch/mips/Kconfig|  6 +-
>  arch/mips/lib/cache.c| 22 +++---
>  arch/mips/lib/cache_init.S   |  4 ++--
>  board/dbau1x00/Kconfig   |  5 -
>  board/micronas/vct/Kconfig   |  5 -
>  board/pb1x00/Kconfig |  5 -
>  board/qca/ap121/Kconfig  |  5 -
>  board/qca/ap143/Kconfig  |  5 -
>  board/qemu-mips/Kconfig  |  5 -
>  board/tplink/wdr4300/Kconfig |  5 -
>  10 files changed, 42 insertions(+), 25 deletions(-)
> 
> diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
> index 13f1164..8af8799 100644
> --- a/arch/mips/Kconfig
> +++ b/arch/mips/Kconfig
> @@ -247,11 +247,15 @@ config SYS_DCACHE_SIZE
>   hex
>   default 0
>  
> +config SYS_DCACHE_LINE_SIZE
> + hex
> + default 0
> +
>  config SYS_ICACHE_SIZE
>   hex
>   default 0
>  
> -config SYS_CACHELINE_SIZE
> +config SYS_ICACHE_LINE_SIZE

Be careful here, CONFIG_SYS_CACHELINE_SIZE is established all over the
u-boot, so this might cause build breakage. You should keep some
compatibility CONFIG_SYS_CACHELINE_SIZE entry and set it to default to
SYS_DCACHE_LINE_SIZE , since it's mostly used for DMA anyway.

>   hex
>   default 0
>  
> diff --git a/arch/mips/lib/cache.c b/arch/mips/lib/cache.c
> index 7695325..2bb91c6 100644
> --- a/arch/mips/lib/cache.c
> +++ b/arch/mips/lib/cache.c
> @@ -9,23 +9,13 @@
>  #include 
>  #include 
>  
> -#if CONFIG_SYS_CACHELINE_SIZE != 0
> -
>  static inline unsigned long icache_line_size(void)
>  {
> - return CONFIG_SYS_CACHELINE_SIZE;
> -}
> -
> -static inline unsigned long dcache_line_size(void)
> -{
> - return CONFIG_SYS_CACHELINE_SIZE;
> -}
> + unsigned long conf1, il;
>  
> -#else /* !CONFIG_SYS_CACHELINE_SIZE */
> + if (CONFIG_SYS_ICACHE_LINE_SIZE != 0)
> + return CONFIG_SYS_ICACHE_LINE_SIZE;
>  
> -static inline unsigned long icache_line_size(void)
> -{
> - unsigned long conf1, il;
>   conf1 = read_c0_config1();
>   il = (conf1 & MIPS_CONF1_IL) >> MIPS_CONF1_IL_SHF;
>   if (!il)
> @@ -36,6 +26,10 @@ static inline unsigned long icache_line_size(void)
>  static inline unsigned long dcache_line_size(void)
>  {
>   unsigned long conf1, dl;
> +
> + if (CONFIG_SYS_DCACHE_LINE_SIZE != 0)
> + return CONFIG_SYS_DCACHE_LINE_SIZE;
> +
>   conf1 = read_c0_config1();
>   dl = (conf1 & MIPS_CONF1_DL) >> MIPS_CONF1_DL_SHF;
>   if (!dl)
> @@ -43,8 +37,6 @@ static inline unsigned long dcache_line_size(void)
>   return 2 << dl;
>  }
>  
> -#endif /* !CONFIG_SYS_CACHELINE_SIZE */
> -
>  void flush_cache(ulong start_addr, ulong size)
>  {
>   unsigned long ilsize = icache_line_size();
> diff --git a/arch/mips/lib/cache_init.S b/arch/mips/lib/cache_init.S
> index e4a44ff..41cb3a6 100644
> --- a/arch/mips/lib/cache_init.S
> +++ b/arch/mips/lib/cache_init.S
> @@ -101,14 +101,14 @@
>  LEAF(mips_cache_reset)
>  #if CONFIG_SYS_ICACHE_SIZE != 0
>   li  t2, CONFIG_SYS_ICACHE_SIZE
> - li  t8, CONFIG_SYS_CACHELINE_SIZE
> + li  t8, CONFIG_SYS_ICACHE_LINE_SIZE
>  #else
>   l1_info t2, t8, MIPS_CONF1_IA_SHF
>  #endif
>  
>  #if CONFIG_SYS_DCACHE_SIZE != 0
>   li  t3, CONFIG_SYS_DCACHE_SIZE
> - li  t9, CONFIG_SYS_CACHELINE_SIZE
> + li  t9, CONFIG_SYS_DCACHE_LINE_SIZE
>  #else
>   l1_info t3, t9, MIPS_CONF1_DA_SHF
>  #endif
> diff --git a/board/dbau1x00/Kconfig b/board/dbau1x00/Kconfig
> index 1715a28..448176d 100644
> --- a/board/dbau1x00/Kconfig
> +++ b/board/dbau1x00/Kconfig
> @@ -15,10 +15,13 @@ config SYS_TEXT_BASE
>  config SYS_DCACHE_SIZE
>   default 16384
>  
> +config SYS_DCACHE_LINE_SIZE
> + default 32
> +
>  config SYS_ICACHE_SIZE
>   default 16384
>  
> -config SYS_CACHELINE_SIZE
> +config SYS_ICACHE_LINE_SIZE
>   default 32
>  
>  menu "dbau1x00 board options"
> diff --git a/board/micronas/vct/Kconfig b/board/micronas/vct/Kconfig
> index 5bb6f03..df7c029 100644
> --- a/board/micronas/vct/Kconfig
> +++ b/board/micronas/vct/Kconfig
> @@ -15,10 +15,13 @@ config SYS_TEXT_BASE
>  config SYS_DCACHE_SIZE
>   default 16384
>  
> +config SYS_DCACHE_LINE_SIZE
> + default 32
> +
>  config SYS_ICACHE_SIZE
>   default 16384
>  
> -config SYS_CACHELINE_SIZE
> +config SYS_ICACHE_LINE_SIZE
>   default 32
>  
>  menu "vct board options"
> diff --git a/board/pb1x00/Kconfig b/board/pb1x00/Kconfig
> index 27b2ef0..ef8905d 100644
> --- a/board/pb1x00/Kconfig
> +++ b/board/pb1x00/Kconfig
> @@ -15,10 +15,13 @@ config SYS_TEXT_BASE
>  config 

Re: [U-Boot] [PATCH] serial: 16550: Add JZ47xx support

[Marek Vasut]

On 05/26/2016 06:44 PM, Simon Glass wrote:
> Hi Marek,
> 
> On 26 May 2016 at 10:34, Marek Vasut  wrote:
>> On 05/26/2016 03:29 PM, Simon Glass wrote:
>>> Hi Marek,
>>>
>>> On 25 May 2016 at 16:35, Marek Vasut  wrote:
 On 05/26/2016 12:31 AM, Daniel Schwierzeck wrote:
>
>
> Am 26.05.2016 um 00:21 schrieb Marek Vasut:
>> On 05/26/2016 12:17 AM, Daniel Schwierzeck wrote:
>>>
>>>
>>> Am 25.05.2016 um 02:19 schrieb Marek Vasut:
 The Ingenic JZ47xx requires special bit (UART_EN) set in FCR register
 in order to work at all. Add this special case handling into the 
 driver.

 Signed-off-by: Marek Vasut 
 Cc: Tom Rini 
 Cc: Simon Glass 
 Cc: Daniel Schwierzeck 
 Cc: Paul Burton 
 ---
  drivers/serial/ns16550.c | 8 
  1 file changed, 8 insertions(+)

 diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c
 index 30ba0aa..1323881 100644
 --- a/drivers/serial/ns16550.c
 +++ b/drivers/serial/ns16550.c
 @@ -50,6 +50,14 @@ DECLARE_GLOBAL_DATA_PTR;
  #endif
  #endif

 +#ifdef CONFIG_ARCH_JZ47XX
 +#undef UART_FCRVAL
 +/* Ingenic JZ47xx SoCs require that a 'UART Module Enable' bit be set 
 */
 +#define UART_FCR_UME  0x10
 +#define UART_FCRVAL (UART_FCR_FIFO_EN | UART_FCR_RXSR |   \
 +   UART_FCR_TXSR | UART_FCR_UME)
 +#endif
>>>
>>> I think this could be added as DT property
>>
>> Not for SPL, which has 14 kiB size limit and it is itching to overflow.
>> I am literally counting bytes in the SPL and removing slop from
>> structures to make it fit, just barely. With the USB loader, I can
>> brutalize the SPL into having extremely rudimentary UART support now
>> (like printch() being the most advanced output mechanism, but you can
>> only use it three times, otherwise the code won't fit and the board is
>> eaten by demons) and this is where this patch comes into play.
>>
>> So yes, for full u-boot, this _should_ be part of DT. For SPL, please 
>> apply.
>>
>
> ok, but wouldn't it be better to introduce an option like
> CONFIG_SYS_NS16550_UME instead of using the SoC-specific
> CONFIG_ARCH_JZ47XX. This driver is messed up enough ;)

 I was undecided between this (like the IER) and adding new ifdef (like
 SOC_KEYSTONE). Whichever way is fine with me. Yeah, the driver is
 repugnant for sure.

 +
  #ifndef CONFIG_SYS_NS16550_IER
  #define CONFIG_SYS_NS16550_IER  0x00
  #endif /* CONFIG_SYS_NS16550_IER */

>>>
>>> That way seems better to me. You should be able to add your UME flag
>>> as a Kconfig for this driver, in drivers/serial/Kconfig, which
>>> defaults to 0. It would be good to keep out board-specific stuff from
>>> this file, as you did with OMAP1510.
>>
>> I'm not really sure I want to expose the CONFIG_SYS_NS16550_FCR override
>> via Kconfig. The extra bits should be set via DT props
>> unless there is some really good reason why that cannot be done
>> (like size limitation in SPL or DT not available).
>>
>> I tried these approaches:
>> 1) Add Kconfig option for CONFIG_SYS_NS16550_FCR , where you
>>set specific byte value. This makes it hard to figure out
>>which bits are set in the FCR just by looking at the value.
>> 2) Add Kconfig option selected if ARCH_JZ47XX is selected and
>>use that in the driver to add the extra UME bit.
>> 3) Define CONFIG_SYS_NS16550_FCR in include/configs/board.h
>>using the macros from ns16550.h . This makes it obvious
>>which bits are set.
>>
>> I am undecided between 2 and 3, but inclined to go with 3.
>> What do you think ?
> 
> How about making your feature an option, like CONFIG_SYS_NS16550_UEN,
> which defaults to 0, but in your case is 0x10. You can OR it into the
> value.

That's quite close to 1) , but then what if someone comes and wants to
remove some bits from the FCR instead of adding some?

-- 
Best regards,
Marek Vasut
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Re: [U-Boot] [PATCH 1/3] MIPS: Move cache sizes to Kconfig

[Marek Vasut]

On 05/26/2016 05:58 PM, Paul Burton wrote:
> Move details of the L1 cache line sizes & total sizes into Kconfig,
> defaulting to 0 & using 0 to indicate that the value should be
> autodetected.
> 
> Signed-off-by: Paul Burton 
> ---
> 
>  arch/mips/Kconfig| 12 
>  arch/mips/lib/cache.c|  2 +-
>  arch/mips/lib/cache_init.S   |  6 +++---
>  board/dbau1x00/Kconfig   |  9 +
>  board/micronas/vct/Kconfig   |  9 +
>  board/pb1x00/Kconfig |  9 +
>  board/qca/ap121/Kconfig  |  9 +
>  board/qca/ap143/Kconfig  |  9 +
>  board/qemu-mips/Kconfig  |  9 +
>  board/tplink/wdr4300/Kconfig |  9 +
>  include/configs/ap121.h  |  5 -
>  include/configs/ap143.h  |  5 -
>  include/configs/dbau1x00.h   |  7 ---
>  include/configs/pb1x00.h |  6 --
>  include/configs/qemu-mips.h  |  7 ---
>  include/configs/qemu-mips64.h|  7 ---
>  include/configs/tplink_wdr4300.h |  5 -
>  include/configs/vct.h|  7 ---
>  18 files changed, 79 insertions(+), 53 deletions(-)
> 
> diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
> index abaeaf0..13f1164 100644
> --- a/arch/mips/Kconfig
> +++ b/arch/mips/Kconfig
> @@ -243,6 +243,18 @@ config SWAP_IO_SPACE
>  config SYS_MIPS_CACHE_INIT_RAM_LOAD
>   bool
>  
> +config SYS_DCACHE_SIZE
> + hex
> + default 0
> +
> +config SYS_ICACHE_SIZE
> + hex
> + default 0
> +
> +config SYS_CACHELINE_SIZE
> + hex
> + default 0
> +

Please add some short help text to those options.

>  config MIPS_L1_CACHE_SHIFT_4
>   bool
>  
> diff --git a/arch/mips/lib/cache.c b/arch/mips/lib/cache.c
> index 7482005..7695325 100644
> --- a/arch/mips/lib/cache.c
> +++ b/arch/mips/lib/cache.c
> @@ -9,7 +9,7 @@
>  #include 
>  #include 
>  
> -#ifdef CONFIG_SYS_CACHELINE_SIZE
> +#if CONFIG_SYS_CACHELINE_SIZE != 0

Wouldn't it make more sense to introduce something like
CONFIG_HAVE_CACHE_SUPPORT instead , so you don't need this
#if CONFIG_FOO != 0 construct all over the place ?

Cool stuff otherwise, thanks!

>  
>  static inline unsigned long icache_line_size(void)
>  {
> diff --git a/arch/mips/lib/cache_init.S b/arch/mips/lib/cache_init.S
> index 08b7c3a..e4a44ff 100644
> --- a/arch/mips/lib/cache_init.S
> +++ b/arch/mips/lib/cache_init.S
> @@ -99,14 +99,14 @@
>   *
>   */
>  LEAF(mips_cache_reset)
> -#ifdef CONFIG_SYS_ICACHE_SIZE
> +#if CONFIG_SYS_ICACHE_SIZE != 0
>   li  t2, CONFIG_SYS_ICACHE_SIZE
>   li  t8, CONFIG_SYS_CACHELINE_SIZE
>  #else
>   l1_info t2, t8, MIPS_CONF1_IA_SHF
>  #endif
>  
> -#ifdef CONFIG_SYS_DCACHE_SIZE
> +#if CONFIG_SYS_DCACHE_SIZE != 0
>   li  t3, CONFIG_SYS_DCACHE_SIZE
>   li  t9, CONFIG_SYS_CACHELINE_SIZE
>  #else
> @@ -116,7 +116,7 @@ LEAF(mips_cache_reset)
>  #ifdef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD
>  
>   /* Determine the largest L1 cache size */
> -#if defined(CONFIG_SYS_ICACHE_SIZE) && defined(CONFIG_SYS_DCACHE_SIZE)
> +#if (CONFIG_SYS_ICACHE_SIZE != 0) && (CONFIG_SYS_DCACHE_SIZE != 0)
>  #if CONFIG_SYS_ICACHE_SIZE > CONFIG_SYS_DCACHE_SIZE
>   li  v0, CONFIG_SYS_ICACHE_SIZE
>  #else
> diff --git a/board/dbau1x00/Kconfig b/board/dbau1x00/Kconfig
> index 342ec59..1715a28 100644
> --- a/board/dbau1x00/Kconfig
> +++ b/board/dbau1x00/Kconfig
> @@ -12,6 +12,15 @@ config SYS_CONFIG_NAME
>  config SYS_TEXT_BASE
>   default 0xbfc0
>  
> +config SYS_DCACHE_SIZE
> + default 16384
> +
> +config SYS_ICACHE_SIZE
> + default 16384
> +
> +config SYS_CACHELINE_SIZE
> + default 32
> +
>  menu "dbau1x00 board options"
>  
>  choice
> diff --git a/board/micronas/vct/Kconfig b/board/micronas/vct/Kconfig
> index 535a77b..5bb6f03 100644
> --- a/board/micronas/vct/Kconfig
> +++ b/board/micronas/vct/Kconfig
> @@ -12,6 +12,15 @@ config SYS_CONFIG_NAME
>  config SYS_TEXT_BASE
>   default 0x8700
>  
> +config SYS_DCACHE_SIZE
> + default 16384
> +
> +config SYS_ICACHE_SIZE
> + default 16384
> +
> +config SYS_CACHELINE_SIZE
> + default 32
> +
>  menu "vct board options"
>  
>  choice
> diff --git a/board/pb1x00/Kconfig b/board/pb1x00/Kconfig
> index 236a410..27b2ef0 100644
> --- a/board/pb1x00/Kconfig
> +++ b/board/pb1x00/Kconfig
> @@ -12,4 +12,13 @@ config SYS_CONFIG_NAME
>  config SYS_TEXT_BASE
>   default 0x8380
>  
> +config SYS_DCACHE_SIZE
> + default 16384
> +
> +config SYS_ICACHE_SIZE
> + default 16384
> +
> +config SYS_CACHELINE_SIZE
> + default 32
> +
>  endif
> diff --git a/board/qca/ap121/Kconfig b/board/qca/ap121/Kconfig
> index c3ecc8f..1ace0e5 100644
> --- a/board/qca/ap121/Kconfig
> +++ b/board/qca/ap121/Kconfig
> @@ -12,4 +12,13 @@ config SYS_CONFIG_NAME
>  config SYS_TEXT_BASE
>   default 0x9f00
>  
> +config SYS_DCACHE_SIZE
> + default 0x8000
> +
> +config SYS_ICACHE_SIZE
> + default 0x1
> +
> 

Re: [U-Boot] [PATCH] serial: 16550: Add JZ47xx support

[Simon Glass]

Hi Marek,

On 26 May 2016 at 10:34, Marek Vasut  wrote:
> On 05/26/2016 03:29 PM, Simon Glass wrote:
>> Hi Marek,
>>
>> On 25 May 2016 at 16:35, Marek Vasut  wrote:
>>> On 05/26/2016 12:31 AM, Daniel Schwierzeck wrote:


 Am 26.05.2016 um 00:21 schrieb Marek Vasut:
> On 05/26/2016 12:17 AM, Daniel Schwierzeck wrote:
>>
>>
>> Am 25.05.2016 um 02:19 schrieb Marek Vasut:
>>> The Ingenic JZ47xx requires special bit (UART_EN) set in FCR register
>>> in order to work at all. Add this special case handling into the driver.
>>>
>>> Signed-off-by: Marek Vasut 
>>> Cc: Tom Rini 
>>> Cc: Simon Glass 
>>> Cc: Daniel Schwierzeck 
>>> Cc: Paul Burton 
>>> ---
>>>  drivers/serial/ns16550.c | 8 
>>>  1 file changed, 8 insertions(+)
>>>
>>> diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c
>>> index 30ba0aa..1323881 100644
>>> --- a/drivers/serial/ns16550.c
>>> +++ b/drivers/serial/ns16550.c
>>> @@ -50,6 +50,14 @@ DECLARE_GLOBAL_DATA_PTR;
>>>  #endif
>>>  #endif
>>>
>>> +#ifdef CONFIG_ARCH_JZ47XX
>>> +#undef UART_FCRVAL
>>> +/* Ingenic JZ47xx SoCs require that a 'UART Module Enable' bit be set 
>>> */
>>> +#define UART_FCR_UME  0x10
>>> +#define UART_FCRVAL (UART_FCR_FIFO_EN | UART_FCR_RXSR |   \
>>> +   UART_FCR_TXSR | UART_FCR_UME)
>>> +#endif
>>
>> I think this could be added as DT property
>
> Not for SPL, which has 14 kiB size limit and it is itching to overflow.
> I am literally counting bytes in the SPL and removing slop from
> structures to make it fit, just barely. With the USB loader, I can
> brutalize the SPL into having extremely rudimentary UART support now
> (like printch() being the most advanced output mechanism, but you can
> only use it three times, otherwise the code won't fit and the board is
> eaten by demons) and this is where this patch comes into play.
>
> So yes, for full u-boot, this _should_ be part of DT. For SPL, please 
> apply.
>

 ok, but wouldn't it be better to introduce an option like
 CONFIG_SYS_NS16550_UME instead of using the SoC-specific
 CONFIG_ARCH_JZ47XX. This driver is messed up enough ;)
>>>
>>> I was undecided between this (like the IER) and adding new ifdef (like
>>> SOC_KEYSTONE). Whichever way is fine with me. Yeah, the driver is
>>> repugnant for sure.
>>>
>>> +
>>>  #ifndef CONFIG_SYS_NS16550_IER
>>>  #define CONFIG_SYS_NS16550_IER  0x00
>>>  #endif /* CONFIG_SYS_NS16550_IER */
>>>
>>
>> That way seems better to me. You should be able to add your UME flag
>> as a Kconfig for this driver, in drivers/serial/Kconfig, which
>> defaults to 0. It would be good to keep out board-specific stuff from
>> this file, as you did with OMAP1510.
>
> I'm not really sure I want to expose the CONFIG_SYS_NS16550_FCR override
> via Kconfig. The extra bits should be set via DT props
> unless there is some really good reason why that cannot be done
> (like size limitation in SPL or DT not available).
>
> I tried these approaches:
> 1) Add Kconfig option for CONFIG_SYS_NS16550_FCR , where you
>set specific byte value. This makes it hard to figure out
>which bits are set in the FCR just by looking at the value.
> 2) Add Kconfig option selected if ARCH_JZ47XX is selected and
>use that in the driver to add the extra UME bit.
> 3) Define CONFIG_SYS_NS16550_FCR in include/configs/board.h
>using the macros from ns16550.h . This makes it obvious
>which bits are set.
>
> I am undecided between 2 and 3, but inclined to go with 3.
> What do you think ?

How about making your feature an option, like CONFIG_SYS_NS16550_UEN,
which defaults to 0, but in your case is 0x10. You can OR it into the
value.

Regards,
Simon
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Re: [U-Boot] [PATCH] serial: 16550: Add JZ47xx support

[Marek Vasut]

On 05/26/2016 03:29 PM, Simon Glass wrote:
> Hi Marek,
> 
> On 25 May 2016 at 16:35, Marek Vasut  wrote:
>> On 05/26/2016 12:31 AM, Daniel Schwierzeck wrote:
>>>
>>>
>>> Am 26.05.2016 um 00:21 schrieb Marek Vasut:
 On 05/26/2016 12:17 AM, Daniel Schwierzeck wrote:
>
>
> Am 25.05.2016 um 02:19 schrieb Marek Vasut:
>> The Ingenic JZ47xx requires special bit (UART_EN) set in FCR register
>> in order to work at all. Add this special case handling into the driver.
>>
>> Signed-off-by: Marek Vasut 
>> Cc: Tom Rini 
>> Cc: Simon Glass 
>> Cc: Daniel Schwierzeck 
>> Cc: Paul Burton 
>> ---
>>  drivers/serial/ns16550.c | 8 
>>  1 file changed, 8 insertions(+)
>>
>> diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c
>> index 30ba0aa..1323881 100644
>> --- a/drivers/serial/ns16550.c
>> +++ b/drivers/serial/ns16550.c
>> @@ -50,6 +50,14 @@ DECLARE_GLOBAL_DATA_PTR;
>>  #endif
>>  #endif
>>
>> +#ifdef CONFIG_ARCH_JZ47XX
>> +#undef UART_FCRVAL
>> +/* Ingenic JZ47xx SoCs require that a 'UART Module Enable' bit be set */
>> +#define UART_FCR_UME  0x10
>> +#define UART_FCRVAL (UART_FCR_FIFO_EN | UART_FCR_RXSR |   \
>> +   UART_FCR_TXSR | UART_FCR_UME)
>> +#endif
>
> I think this could be added as DT property

 Not for SPL, which has 14 kiB size limit and it is itching to overflow.
 I am literally counting bytes in the SPL and removing slop from
 structures to make it fit, just barely. With the USB loader, I can
 brutalize the SPL into having extremely rudimentary UART support now
 (like printch() being the most advanced output mechanism, but you can
 only use it three times, otherwise the code won't fit and the board is
 eaten by demons) and this is where this patch comes into play.

 So yes, for full u-boot, this _should_ be part of DT. For SPL, please 
 apply.

>>>
>>> ok, but wouldn't it be better to introduce an option like
>>> CONFIG_SYS_NS16550_UME instead of using the SoC-specific
>>> CONFIG_ARCH_JZ47XX. This driver is messed up enough ;)
>>
>> I was undecided between this (like the IER) and adding new ifdef (like
>> SOC_KEYSTONE). Whichever way is fine with me. Yeah, the driver is
>> repugnant for sure.
>>
>> +
>>  #ifndef CONFIG_SYS_NS16550_IER
>>  #define CONFIG_SYS_NS16550_IER  0x00
>>  #endif /* CONFIG_SYS_NS16550_IER */
>>
> 
> That way seems better to me. You should be able to add your UME flag
> as a Kconfig for this driver, in drivers/serial/Kconfig, which
> defaults to 0. It would be good to keep out board-specific stuff from
> this file, as you did with OMAP1510.

I'm not really sure I want to expose the CONFIG_SYS_NS16550_FCR override
via Kconfig. The extra bits should be set via DT props
unless there is some really good reason why that cannot be done
(like size limitation in SPL or DT not available).

I tried these approaches:
1) Add Kconfig option for CONFIG_SYS_NS16550_FCR , where you
   set specific byte value. This makes it hard to figure out
   which bits are set in the FCR just by looking at the value.
2) Add Kconfig option selected if ARCH_JZ47XX is selected and
   use that in the driver to add the extra UME bit.
3) Define CONFIG_SYS_NS16550_FCR in include/configs/board.h
   using the macros from ns16550.h . This makes it obvious
   which bits are set.

I am undecided between 2 and 3, but inclined to go with 3.
What do you think ?

-- 
Best regards,
Marek Vasut
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH v2] net: pcnet: Fix init on big endian 64 bit

[Paul Burton]

If dev->iobase is 64 bits wide then writing the value of the BAR into a
pointer to iobase will not work on big endian systems, where the BAR
value will incorrectly get written to the upper 32 bits of the 64 bit
variable. Fix this by reading the BAR into a u32, matching the type
expected by pci_read_config_dword.

Signed-off-by: Paul Burton 

---

Changes in v2:
- Drop useless cast of 

 drivers/net/pcnet.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/net/pcnet.c b/drivers/net/pcnet.c
index d1fd4e4..1da9996 100644
--- a/drivers/net/pcnet.c
+++ b/drivers/net/pcnet.c
@@ -155,6 +155,7 @@ int pcnet_initialize(bd_t *bis)
struct eth_device *dev;
u16 command, status;
int dev_nr = 0;
+   u32 bar;
 
PCNET_DEBUG1("\npcnet_initialize...\n");
 
@@ -182,9 +183,8 @@ int pcnet_initialize(bd_t *bis)
/*
 * Setup the PCI device.
 */
-   pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0,
- (unsigned int *)>iobase);
-   dev->iobase = pci_io_to_phys(devbusfn, dev->iobase);
+   pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, );
+   dev->iobase = pci_io_to_phys(devbusfn, bar);
dev->iobase &= ~0xf;
 
PCNET_DEBUG1("%s: devbusfn=0x%x iobase=0x%lx: ",
-- 
2.8.3

___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH RESEND] phy: atheros: add support for RGMII_ID, RGMII_TXID and RGMII_RXID

[Andrea Merello]

This adds support for internal delay on RX and TX on RGMII interface for the
AR8035 phy.

This is basically the same Linux driver do. Tested on a Zynq Zturn board (for
which u-boot support in is my tree; first patch waiting ML approval)

Signed-off-by: Andrea Merello 

diff --git a/drivers/net/phy/atheros.c b/drivers/net/phy/atheros.c
index e57c412..694a338 100644
--- a/drivers/net/phy/atheros.c
+++ b/drivers/net/phy/atheros.c
@@ -31,6 +31,22 @@ static int ar8035_config(struct phy_device *phydev)
regval = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, (regval|0x0100));

+   if ((phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) ||
+   (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)) {
+   /* select debug reg 5 */
+   phy_write(phydev, MDIO_DEVAD_NONE, 0x1D, 0x5);
+   /* enable tx delay */
+   phy_write(phydev, MDIO_DEVAD_NONE, 0x1E, 0x0100);
+   }
+
+   if ((phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) ||
+   (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)) {
+   /* select debug reg 0 */
+   phy_write(phydev, MDIO_DEVAD_NONE, 0x1D, 0x0);
+   /* enable rx delay */
+   phy_write(phydev, MDIO_DEVAD_NONE, 0x1E, 0x8000);
+   }
+
phydev->supported = phydev->drv->features;

genphy_config_aneg(phydev);
--
2.1.4
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH] net: pcnet: Fix init on big endian 64 bit

[Paul Burton]

If dev->iobase is 64 bits wide then writing the value of the BAR into a
pointer to iobase will not work on big endian systems, where the BAR
value will incorrectly get written to the upper 32 bits of the 64 bit
variable. Fix this by reading the BAR into a u32, matching the type
expected by pci_read_config_dword.

Signed-off-by: Paul Burton 

---

 drivers/net/pcnet.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/net/pcnet.c b/drivers/net/pcnet.c
index d1fd4e4..f0a553e 100644
--- a/drivers/net/pcnet.c
+++ b/drivers/net/pcnet.c
@@ -155,6 +155,7 @@ int pcnet_initialize(bd_t *bis)
struct eth_device *dev;
u16 command, status;
int dev_nr = 0;
+   u32 bar;
 
PCNET_DEBUG1("\npcnet_initialize...\n");
 
@@ -183,8 +184,8 @@ int pcnet_initialize(bd_t *bis)
 * Setup the PCI device.
 */
pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0,
- (unsigned int *)>iobase);
-   dev->iobase = pci_io_to_phys(devbusfn, dev->iobase);
+ (unsigned int *));
+   dev->iobase = pci_io_to_phys(devbusfn, bar);
dev->iobase &= ~0xf;
 
PCNET_DEBUG1("%s: devbusfn=0x%x iobase=0x%lx: ",
-- 
2.8.3

___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH 06/12] arm: lib: Fix uldivmod.S build on Thumb2

[Marek Vasut]

This assembler source won't build in Thumb2 mode, so fix it adding
the necessary Thumb2 conditional macros from unified.h .

This patch also defines CONFIG_THUMB2_KERNEL and CONFIG_ARM_ASM_UNIFIED
which is necessary for correct build of these files both in ARM and
Thumb mode, just like Linux does.

Signed-off-by: Marek Vasut 
Cc: Albert Aribaud 
Cc: Masahiro Yamada 
Cc: Simon Glass 
Cc: Tom Rini 
---
 arch/arm/lib/uldivmod.S | 8 +++-
 1 file changed, 3 insertions(+), 5 deletions(-)

diff --git a/arch/arm/lib/uldivmod.S b/arch/arm/lib/uldivmod.S
index 426c2f2..2efcd73 100644
--- a/arch/arm/lib/uldivmod.S
+++ b/arch/arm/lib/uldivmod.S
@@ -9,10 +9,6 @@
 #include 
 #include 
 
-/* We don't use Thumb instructions for now */
-#define ARM(x...)  x
-#define THUMB(x...)
-
 /*
  * A, Q = r0 + (r1 << 32)
  * B, R = r2 + (r3 << 32)
@@ -226,7 +222,9 @@ THUMB(  orrpl   A_0, A_0, TMP   )
@ Shift A to the right by the appropriate amount.
rsb D_1, D_0, #32
mov Q_0, A_0, lsr D_0
-   orr Q_0, A_1, lsl D_1
+ ARM(   orr Q_0, Q_0, A_1, lsl D_1 )
+ THUMB(lsl A_1, D_1)
+ THUMB(orr Q_0, A_1)
mov Q_1, A_1, lsr D_0
@ Move C to R
mov R_0, C_0
-- 
2.7.0

___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH 05/12] arm: lib: Sync libgcc 32b division/modulo operations

[Marek Vasut]

Sync the libgcc 32bit division and modulo operations with Linux 4.4.6 ,
commit 0d1912303e54ed1b2a371be0bba51c384dd57326 . The functions in these
four files are present in lib1funcs.S in Linux, so replace these files
with lib1funcs.S from Linux.

Since we do not support stack unwinding, instead of importing the whole
asm/unwind.h and all the baggage, this patch defines empty UNWIND() macro
in lib1funcs.S . Moreover, to make all of the functions available, define
CONFIG_AEABI , which is safe, because U-Boot is always compiled with ARM
EABI.

This patch also defines CONFIG_THUMB2_KERNEL and CONFIG_ARM_ASM_UNIFIED
which is necessary for correct build of these files both in ARM and
Thumb mode, just like Linux does.

Signed-off-by: Marek Vasut 
Cc: Albert Aribaud 
Cc: Masahiro Yamada 
Cc: Simon Glass 
Cc: Tom Rini 
---
 arch/arm/lib/Makefile|   5 +-
 arch/arm/lib/divsi3.S| 143 ---
 arch/arm/lib/lib1funcs.S | 351 +++
 arch/arm/lib/modsi3.S|  99 -
 arch/arm/lib/udivsi3.S   |  95 -
 arch/arm/lib/umodsi3.S   |  90 
 6 files changed, 353 insertions(+), 430 deletions(-)
 delete mode 100644 arch/arm/lib/divsi3.S
 create mode 100644 arch/arm/lib/lib1funcs.S
 delete mode 100644 arch/arm/lib/modsi3.S
 delete mode 100644 arch/arm/lib/udivsi3.S
 delete mode 100644 arch/arm/lib/umodsi3.S

diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile
index cafd94d..0b0dbcb 100644
--- a/arch/arm/lib/Makefile
+++ b/arch/arm/lib/Makefile
@@ -5,9 +5,8 @@
 # SPDX-License-Identifier: GPL-2.0+
 #
 
-lib-$(CONFIG_USE_PRIVATE_LIBGCC) += ashldi3.o ashrdi3.o divsi3.o \
-   lshrdi3.o modsi3.o udivsi3.o umodsi3.o div0.o \
-   uldivmod.o
+lib-$(CONFIG_USE_PRIVATE_LIBGCC) += ashldi3.o ashrdi3.o lshrdi3.o \
+   lib1funcs.o uldivmod.o div0.o
 
 ifdef CONFIG_CPU_V7M
 obj-y  += vectors_m.o crt0.o
diff --git a/arch/arm/lib/divsi3.S b/arch/arm/lib/divsi3.S
deleted file mode 100644
index c463c68..000
--- a/arch/arm/lib/divsi3.S
+++ /dev/null
@@ -1,143 +0,0 @@
-#include 
-
-.macro ARM_DIV_BODY dividend, divisor, result, curbit
-
-#if __LINUX_ARM_ARCH__ >= 5
-
-   clz \curbit, \divisor
-   clz \result, \dividend
-   sub \result, \curbit, \result
-   mov \curbit, #1
-   mov \divisor, \divisor, lsl \result
-   mov \curbit, \curbit, lsl \result
-   mov \result, #0
-
-#else
-
-   @ Initially shift the divisor left 3 bits if possible,
-   @ set curbit accordingly.  This allows for curbit to be located
-   @ at the left end of each 4 bit nibbles in the division loop
-   @ to save one loop in most cases.
-   tst \divisor, #0xe000
-   moveq   \divisor, \divisor, lsl #3
-   moveq   \curbit, #8
-   movne   \curbit, #1
-
-   @ Unless the divisor is very big, shift it up in multiples of
-   @ four bits, since this is the amount of unwinding in the main
-   @ division loop.  Continue shifting until the divisor is
-   @ larger than the dividend.
-1: cmp \divisor, #0x1000
-   cmplo   \divisor, \dividend
-   movlo   \divisor, \divisor, lsl #4
-   movlo   \curbit, \curbit, lsl #4
-   blo 1b
-
-   @ For very big divisors, we must shift it a bit at a time, or
-   @ we will be in danger of overflowing.
-1: cmp \divisor, #0x8000
-   cmplo   \divisor, \dividend
-   movlo   \divisor, \divisor, lsl #1
-   movlo   \curbit, \curbit, lsl #1
-   blo 1b
-
-   mov \result, #0
-
-#endif
-
-   @ Division loop
-1: cmp \dividend, \divisor
-   subhs   \dividend, \dividend, \divisor
-   orrhs   \result,   \result,   \curbit
-   cmp \dividend, \divisor,  lsr #1
-   subhs   \dividend, \dividend, \divisor, lsr #1
-   orrhs   \result,   \result,   \curbit,  lsr #1
-   cmp \dividend, \divisor,  lsr #2
-   subhs   \dividend, \dividend, \divisor, lsr #2
-   orrhs   \result,   \result,   \curbit,  lsr #2
-   cmp \dividend, \divisor,  lsr #3
-   subhs   \dividend, \dividend, \divisor, lsr #3
-   orrhs   \result,   \result,   \curbit,  lsr #3
-   cmp \dividend, #0   @ Early termination?
-   movnes  \curbit,   \curbit,  lsr #4 @ No, any more bits to do?
-   movne   \divisor,  \divisor, lsr #4
-   bne 1b
-
-.endm
-
-.macro ARM_DIV2_ORDER divisor, order
-
-#if __LINUX_ARM_ARCH__ >= 5
-
-   clz \order, \divisor
-   rsb \order, \order, #31
-
-#else
-
-   cmp \divisor, #(1 << 16)
-   movhs   \divisor, \divisor, lsr #16
-   movhs   \order, #16
-   movlo   \order, #0
-
-   cmp \divisor, #(1 << 8)
-   movhs   \divisor, \divisor, lsr #8
-   addhs   \order, 

[U-Boot] [PATCH 12/12] lib: Enable private libgcc by default

[Marek Vasut]

This patch decouples U-Boot binary from the toolchain on systems where
private libgcc is available. Instead of pulling in functions provided
by the libgcc from the toolchain, U-Boot will use it's own set of libgcc
functions. These functions are usually imported from Linux kernel, which
also uses it's own libgcc functions instead of the ones provided by the
toolchain.

This patch solves a rather common problem. The toolchain can usually
generate code for many variants of target architecture and often even
different endianness. The libgcc on the other hand is usually compiled
for one particular configuration and the functions provided by it may
or may not be suited for use in U-Boot. This can manifest in two ways,
either the U-Boot fails to compile altogether and linker will complain
or, in the much worse case, the resulting U-Boot will build, but will
misbehave in very subtle and hard to debug ways.

Signed-off-by: Marek Vasut 
Cc: Albert Aribaud 
Cc: Masahiro Yamada 
Cc: Simon Glass 
Cc: Tom Rini 
---
V2: Enable the private libgcc only for ARM<=7 and MIPS
---
 lib/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/lib/Kconfig b/lib/Kconfig
index 2b97c2b..02ca405 100644
--- a/lib/Kconfig
+++ b/lib/Kconfig
@@ -14,6 +14,7 @@ config HAVE_PRIVATE_LIBGCC
 config USE_PRIVATE_LIBGCC
bool "Use private libgcc"
depends on HAVE_PRIVATE_LIBGCC
+   default y if HAVE_PRIVATE_LIBGCC && ((ARM && !ARM64) || MIPS)
help
  This option allows you to use the built-in libgcc implementation
  of U-Boot instead of the one provided by the compiler.
-- 
2.7.0

___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH 10/12] arm: lib: Import Thumb1 functions

[Marek Vasut]

Import functions into lib1funcs.S which are required for Thumb1
build. These functions come from gcc 5.3.1 release.

Signed-off-by: Marek Vasut 
Cc: Albert Aribaud 
Cc: Masahiro Yamada 
Cc: Simon Glass 
Cc: Tom Rini 
---
 arch/arm/lib/lib1funcs.S | 53 
 1 file changed, 53 insertions(+)

diff --git a/arch/arm/lib/lib1funcs.S b/arch/arm/lib/lib1funcs.S
index c343ea9..408839b 100644
--- a/arch/arm/lib/lib1funcs.S
+++ b/arch/arm/lib/lib1funcs.S
@@ -349,3 +349,56 @@ UNWIND(.save {lr})
ldr pc, [sp], #8
 UNWIND(.fnend)
 ENDPROC(Ldiv0)
+
+/* Thumb-1 specialities */
+#if defined(CONFIG_SYS_THUMB_BUILD) && !defined(CONFIG_HAS_THUMB2)
+ENTRY(__gnu_thumb1_case_sqi)
+   push{r1}
+   mov r1, lr
+   lsrsr1, r1, #1
+   lslsr1, r1, #1
+   ldrsb   r1, [r1, r0]
+   lslsr1, r1, #1
+   add lr, lr, r1
+   pop {r1}
+   bx  lr
+ENDPROC(__gnu_thumb1_case_sqi)
+
+ENTRY(__gnu_thumb1_case_uqi)
+   push{r1}
+   mov r1, lr
+   lsrsr1, r1, #1
+   lslsr1, r1, #1
+   ldrbr1, [r1, r0]
+   lslsr1, r1, #1
+   add lr, lr, r1
+   pop {r1}
+   bx  lr
+ENDPROC(__gnu_thumb1_case_uqi)
+
+ENTRY(__gnu_thumb1_case_shi)
+   push{r0, r1}
+   mov r1, lr
+   lsrsr1, r1, #1
+   lslsr0, r0, #1
+   lslsr1, r1, #1
+   ldrsh   r1, [r1, r0]
+   lslsr1, r1, #1
+   add lr, lr, r1
+   pop {r0, r1}
+   bx  lr
+ENDPROC(__gnu_thumb1_case_shi)
+
+ENTRY(__gnu_thumb1_case_uhi)
+   push{r0, r1}
+   mov r1, lr
+   lsrsr1, r1, #1
+   lslsr0, r0, #1
+   lslsr1, r1, #1
+   ldrhr1, [r1, r0]
+   lslsr1, r1, #1
+   add lr, lr, r1
+   pop {r0, r1}
+   bx  lr
+ENDPROC(__gnu_thumb1_case_uhi)
+#endif
-- 
2.7.0

___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH 11/12] arm: lib: Split asm symbols into different .text subsections

[Marek Vasut]

Split each symbol in lib1funcs into different .text.foo section instead
of placing all of them into plain .text . This allows the linker to collect
and discard unused assembler symbols.

Signed-off-by: Marek Vasut 
Cc: Albert Aribaud 
Cc: Masahiro Yamada 
Cc: Simon Glass 
Cc: Tom Rini 
---
 arch/arm/lib/ashldi3.S   |  2 ++
 arch/arm/lib/ashrdi3.S   |  2 ++
 arch/arm/lib/div64.S |  2 ++
 arch/arm/lib/lib1funcs.S | 25 +
 arch/arm/lib/lshrdi3.S   |  2 ++
 arch/arm/lib/muldi3.S|  2 ++
 arch/arm/lib/uldivmod.S  |  3 +++
 7 files changed, 38 insertions(+)

diff --git a/arch/arm/lib/ashldi3.S b/arch/arm/lib/ashldi3.S
index a4f5ebb..6c9ae91 100644
--- a/arch/arm/lib/ashldi3.S
+++ b/arch/arm/lib/ashldi3.S
@@ -17,6 +17,7 @@
 
 ENTRY(__ashldi3)
 ENTRY(__aeabi_llsl)
+.pushsection .text.__ashldi3, "ax"
 
subsr3, r2, #32
rsb ip, r2, #32
@@ -28,5 +29,6 @@ ENTRY(__aeabi_llsl)
mov al, al, lsl r2
ret lr
 
+.popsection
 ENDPROC(__ashldi3)
 ENDPROC(__aeabi_llsl)
diff --git a/arch/arm/lib/ashrdi3.S b/arch/arm/lib/ashrdi3.S
index c6e1ed3..3eb59ec 100644
--- a/arch/arm/lib/ashrdi3.S
+++ b/arch/arm/lib/ashrdi3.S
@@ -17,6 +17,7 @@
 
 ENTRY(__ashrdi3)
 ENTRY(__aeabi_lasr)
+.pushsection .text.__ashrdi3, "ax"
 
subsr3, r2, #32
rsb ip, r2, #32
@@ -28,5 +29,6 @@ ENTRY(__aeabi_lasr)
mov ah, ah, asr r2
ret lr
 
+.popsection
 ENDPROC(__ashrdi3)
 ENDPROC(__aeabi_lasr)
diff --git a/arch/arm/lib/div64.S b/arch/arm/lib/div64.S
index a42a0f0..5bfb41d 100644
--- a/arch/arm/lib/div64.S
+++ b/arch/arm/lib/div64.S
@@ -47,6 +47,7 @@
 
 ENTRY(__do_div64)
 UNWIND(.fnstart)
+.pushsection .text.__do_div64, "ax"
 
@ Test for easy paths first.
subsip, r4, #1
@@ -192,6 +193,7 @@ UNWIND(.fnstart)
moveq   yh, xh
moveq   xh, #0
reteq   lr
+.popsection
 UNWIND(.fnend)
 
 UNWIND(.fnstart)
diff --git a/arch/arm/lib/lib1funcs.S b/arch/arm/lib/lib1funcs.S
index 408839b..f1becda 100644
--- a/arch/arm/lib/lib1funcs.S
+++ b/arch/arm/lib/lib1funcs.S
@@ -196,6 +196,7 @@
 ENTRY(__udivsi3)
 ENTRY(__aeabi_uidiv)
 UNWIND(.fnstart)
+.pushsection .text.__udivsi3, "ax"
 
subsr2, r1, #1
reteq   lr
@@ -219,12 +220,14 @@ UNWIND(.fnstart)
mov r0, r0, lsr r2
ret lr
 
+.popsection
 UNWIND(.fnend)
 ENDPROC(__udivsi3)
 ENDPROC(__aeabi_uidiv)
 
 ENTRY(__umodsi3)
 UNWIND(.fnstart)
+.pushsection .text.__umodsi3, "ax"
 
subsr2, r1, #1  @ compare divisor with 1
bcc Ldiv0
@@ -238,12 +241,14 @@ UNWIND(.fnstart)
 
ret lr
 
+.popsection
 UNWIND(.fnend)
 ENDPROC(__umodsi3)
 
 ENTRY(__divsi3)
 ENTRY(__aeabi_idiv)
 UNWIND(.fnstart)
+.pushsection .text.__divsi3, "ax"
 
cmp r1, #0
eor ip, r0, r1  @ save the sign of the result.
@@ -280,12 +285,14 @@ UNWIND(.fnstart)
rsbmi   r0, r0, #0
ret lr
 
+.popsection
 UNWIND(.fnend)
 ENDPROC(__divsi3)
 ENDPROC(__aeabi_idiv)
 
 ENTRY(__modsi3)
 UNWIND(.fnstart)
+.pushsection .text.__modsi3, "ax"
 
cmp r1, #0
beq Ldiv0
@@ -305,6 +312,7 @@ UNWIND(.fnstart)
rsbmi   r0, r0, #0
ret lr
 
+.popsection
 UNWIND(.fnend)
 ENDPROC(__modsi3)
 
@@ -313,6 +321,7 @@ ENDPROC(__modsi3)
 ENTRY(__aeabi_uidivmod)
 UNWIND(.fnstart)
 UNWIND(.save {r0, r1, ip, lr}  )
+.pushsection .text.__aeabi_uidivmod, "ax"
 
stmfd   sp!, {r0, r1, ip, lr}
bl  __aeabi_uidiv
@@ -321,12 +330,15 @@ UNWIND(.save {r0, r1, ip, lr} )
sub r1, r1, r3
ret lr
 
+.popsection
 UNWIND(.fnend)
 ENDPROC(__aeabi_uidivmod)
 
 ENTRY(__aeabi_idivmod)
 UNWIND(.fnstart)
 UNWIND(.save {r0, r1, ip, lr}  )
+.pushsection .text.__aeabi_uidivmod, "ax"
+
stmfd   sp!, {r0, r1, ip, lr}
bl  __aeabi_idiv
ldmfd   sp!, {r1, r2, ip, lr}
@@ -334,6 +346,7 @@ UNWIND(.save {r0, r1, ip, lr}   )
sub r1, r1, r3
ret lr
 
+.popsection
 UNWIND(.fnend)
 ENDPROC(__aeabi_idivmod)
 
@@ -343,16 +356,21 @@ Ldiv0:
 UNWIND(.fnstart)
 UNWIND(.pad #4)
 UNWIND(.save {lr})
+.pushsection .text.Ldiv0, "ax"
+
str lr, [sp, #-8]!
bl  __div0
mov r0, #0  @ About as wrong as it could be.
ldr pc, [sp], #8
+
+.popsection
 UNWIND(.fnend)
 ENDPROC(Ldiv0)
 
 /* Thumb-1 specialities */
 #if defined(CONFIG_SYS_THUMB_BUILD) && !defined(CONFIG_HAS_THUMB2)
 ENTRY(__gnu_thumb1_case_sqi)
+.pushsection .text.__gnu_thumb1_case_sqi, "ax"
push{r1}
mov r1, lr
lsrsr1, r1, #1
@@ -362,9 +380,11 @@ ENTRY(__gnu_thumb1_case_sqi)
add lr, lr, r1
pop {r1}
bx  lr
+.popsection
 ENDPROC(__gnu_thumb1_case_sqi)
 
 ENTRY(__gnu_thumb1_case_uqi)
+.pushsection 

[U-Boot] [PATCH 09/12] arm: lib: import muldi3.S from Linux

[Marek Vasut]

Import muldi3.S from Linux 4.4.6 , commit 
0d1912303e54ed1b2a371be0bba51c384dd57326
on arm32. This file implements __aeabi_lmul and it's alias __muldi3, which
is needed when doing Thumb1 builds.

This patch also defines CONFIG_THUMB2_KERNEL and CONFIG_ARM_ASM_UNIFIED
which is necessary for correct build of these files both in ARM and
Thumb mode, just like Linux does.

Signed-off-by: Marek Vasut 
Cc: Albert Aribaud 
Cc: Masahiro Yamada 
Cc: Simon Glass 
Cc: Tom Rini 
---
 arch/arm/lib/Makefile |  3 ++-
 arch/arm/lib/muldi3.S | 46 ++
 2 files changed, 48 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/lib/muldi3.S

diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile
index 8945915..86489fd 100644
--- a/arch/arm/lib/Makefile
+++ b/arch/arm/lib/Makefile
@@ -6,7 +6,8 @@
 #
 
 lib-$(CONFIG_USE_PRIVATE_LIBGCC) += ashldi3.o ashrdi3.o lshrdi3.o \
-   lib1funcs.o uldivmod.o div0.o div64.o
+   lib1funcs.o uldivmod.o div0.o \
+   div64.o muldi3.o
 
 ifdef CONFIG_CPU_V7M
 obj-y  += vectors_m.o crt0.o
diff --git a/arch/arm/lib/muldi3.S b/arch/arm/lib/muldi3.S
new file mode 100644
index 000..daa5704
--- /dev/null
+++ b/arch/arm/lib/muldi3.S
@@ -0,0 +1,46 @@
+/*
+ *  linux/arch/arm/lib/muldi3.S
+ *
+ *  Author: Nicolas Pitre
+ *  Created:Oct 19, 2005
+ *  Copyright:  Monta Vista Software, Inc.
+ *
+ *  SPDX-License-Identifier:   GPL-2.0
+ */
+
+#include 
+#include 
+
+#ifdef __ARMEB__
+#define xh r0
+#define xl r1
+#define yh r2
+#define yl r3
+#else
+#define xl r0
+#define xh r1
+#define yl r2
+#define yh r3
+#endif
+
+ENTRY(__muldi3)
+ENTRY(__aeabi_lmul)
+
+   mul xh, yl, xh
+   mla xh, xl, yh, xh
+   mov ip, xl, lsr #16
+   mov yh, yl, lsr #16
+   bic xl, xl, ip, lsl #16
+   bic yl, yl, yh, lsl #16
+   mla xh, yh, ip, xh
+   mul yh, xl, yh
+   mul xl, yl, xl
+   mul ip, yl, ip
+   addsxl, xl, yh, lsl #16
+   adc xh, xh, yh, lsr #16
+   addsxl, xl, ip, lsl #16
+   adc xh, xh, ip, lsr #16
+   ret lr
+
+ENDPROC(__muldi3)
+ENDPROC(__aeabi_lmul)
-- 
2.7.0

___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH 08/12] arm: lib: Repair Warning: conditional infixes are deprecated in unified syntax

[Marek Vasut]

Fix the following warning when building for thumb2 target by tweaking the
instruction syntax:

Warning: conditional infixes are deprecated in unified syntax

Signed-off-by: Marek Vasut 
Cc: Albert Aribaud 
Cc: Masahiro Yamada 
Cc: Simon Glass 
Cc: Tom Rini 
---
 arch/arm/lib/div64.S | 4 ++--
 arch/arm/lib/lib1funcs.S | 4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/arm/lib/div64.S b/arch/arm/lib/div64.S
index 03986c2..a42a0f0 100644
--- a/arch/arm/lib/div64.S
+++ b/arch/arm/lib/div64.S
@@ -88,8 +88,8 @@ UNWIND(.fnstart)
@ Break out early if dividend reaches 0.
 2: cmp xh, yl
orrcs   yh, yh, ip
-   subcss  xh, xh, yl
-   movnes  ip, ip, lsr #1
+   subscs  xh, xh, yl
+   movsne  ip, ip, lsr #1
mov yl, yl, lsr #1
bne 2b
 
diff --git a/arch/arm/lib/lib1funcs.S b/arch/arm/lib/lib1funcs.S
index 5871dbe..c343ea9 100644
--- a/arch/arm/lib/lib1funcs.S
+++ b/arch/arm/lib/lib1funcs.S
@@ -84,7 +84,7 @@
subhs   \dividend, \dividend, \divisor, lsr #3
orrhs   \result,   \result,   \curbit,  lsr #3
cmp \dividend, #0   @ Early termination?
-   movnes  \curbit,   \curbit,  lsr #4 @ No, any more bits to do?
+   movsne  \curbit,   \curbit,  lsr #4 @ No, any more bits to do?
movne   \divisor,  \divisor, lsr #4
bne 1b
 
@@ -170,7 +170,7 @@
subhs   \dividend, \dividend, \divisor, lsr #3
cmp \dividend, #1
mov \divisor, \divisor, lsr #4
-   subges  \order, \order, #4
+   subsge  \order, \order, #4
bge 1b
 
tst \order, #3
-- 
2.7.0

___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH 03/12] arm: lib: Drop underscore from private libgcc filenames

[Marek Vasut]

Drop the underscore from the filenames of files implementing libgcc
routines. There is no functional change. This change is done to make
sync with Linux kernel easier.

Signed-off-by: Marek Vasut 
Cc: Albert Aribaud 
Cc: Masahiro Yamada 
Cc: Simon Glass 
Cc: Tom Rini 
---
 arch/arm/lib/Makefile| 6 +++---
 arch/arm/lib/{_ashldi3.S => ashldi3.S}   | 0
 arch/arm/lib/{_ashrdi3.S => ashrdi3.S}   | 0
 arch/arm/lib/{_divsi3.S => divsi3.S} | 0
 arch/arm/lib/{_lshrdi3.S => lshrdi3.S}   | 0
 arch/arm/lib/{_modsi3.S => modsi3.S} | 0
 arch/arm/lib/{_udivsi3.S => udivsi3.S}   | 0
 arch/arm/lib/{_uldivmod.S => uldivmod.S} | 0
 arch/arm/lib/{_umodsi3.S => umodsi3.S}   | 0
 9 files changed, 3 insertions(+), 3 deletions(-)
 rename arch/arm/lib/{_ashldi3.S => ashldi3.S} (100%)
 rename arch/arm/lib/{_ashrdi3.S => ashrdi3.S} (100%)
 rename arch/arm/lib/{_divsi3.S => divsi3.S} (100%)
 rename arch/arm/lib/{_lshrdi3.S => lshrdi3.S} (100%)
 rename arch/arm/lib/{_modsi3.S => modsi3.S} (100%)
 rename arch/arm/lib/{_udivsi3.S => udivsi3.S} (100%)
 rename arch/arm/lib/{_uldivmod.S => uldivmod.S} (100%)
 rename arch/arm/lib/{_umodsi3.S => umodsi3.S} (100%)

diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile
index 1112b9e..cafd94d 100644
--- a/arch/arm/lib/Makefile
+++ b/arch/arm/lib/Makefile
@@ -5,9 +5,9 @@
 # SPDX-License-Identifier: GPL-2.0+
 #
 
-lib-$(CONFIG_USE_PRIVATE_LIBGCC) += _ashldi3.o _ashrdi3.o _divsi3.o \
-   _lshrdi3.o _modsi3.o _udivsi3.o _umodsi3.o div0.o \
-   _uldivmod.o
+lib-$(CONFIG_USE_PRIVATE_LIBGCC) += ashldi3.o ashrdi3.o divsi3.o \
+   lshrdi3.o modsi3.o udivsi3.o umodsi3.o div0.o \
+   uldivmod.o
 
 ifdef CONFIG_CPU_V7M
 obj-y  += vectors_m.o crt0.o
diff --git a/arch/arm/lib/_ashldi3.S b/arch/arm/lib/ashldi3.S
similarity index 100%
rename from arch/arm/lib/_ashldi3.S
rename to arch/arm/lib/ashldi3.S
diff --git a/arch/arm/lib/_ashrdi3.S b/arch/arm/lib/ashrdi3.S
similarity index 100%
rename from arch/arm/lib/_ashrdi3.S
rename to arch/arm/lib/ashrdi3.S
diff --git a/arch/arm/lib/_divsi3.S b/arch/arm/lib/divsi3.S
similarity index 100%
rename from arch/arm/lib/_divsi3.S
rename to arch/arm/lib/divsi3.S
diff --git a/arch/arm/lib/_lshrdi3.S b/arch/arm/lib/lshrdi3.S
similarity index 100%
rename from arch/arm/lib/_lshrdi3.S
rename to arch/arm/lib/lshrdi3.S
diff --git a/arch/arm/lib/_modsi3.S b/arch/arm/lib/modsi3.S
similarity index 100%
rename from arch/arm/lib/_modsi3.S
rename to arch/arm/lib/modsi3.S
diff --git a/arch/arm/lib/_udivsi3.S b/arch/arm/lib/udivsi3.S
similarity index 100%
rename from arch/arm/lib/_udivsi3.S
rename to arch/arm/lib/udivsi3.S
diff --git a/arch/arm/lib/_uldivmod.S b/arch/arm/lib/uldivmod.S
similarity index 100%
rename from arch/arm/lib/_uldivmod.S
rename to arch/arm/lib/uldivmod.S
diff --git a/arch/arm/lib/_umodsi3.S b/arch/arm/lib/umodsi3.S
similarity index 100%
rename from arch/arm/lib/_umodsi3.S
rename to arch/arm/lib/umodsi3.S
-- 
2.7.0

___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH 04/12] arm: lib: Sync libgcc shift operations

[Marek Vasut]

Sync the libgcc shift operations with Linux kernel 4.4.6 , commit
0d1912303e54ed1b2a371be0bba51c384dd57326 . Syncing these three
files is easy, as there is almost no change in them, except the
addition of Thumb support.

This patch also defines CONFIG_THUMB2_KERNEL and CONFIG_ARM_ASM_UNIFIED
which is necessary for correct build of these files both in ARM and
Thumb mode, just like Linux does.

Signed-off-by: Marek Vasut 
Cc: Albert Aribaud 
Cc: Masahiro Yamada 
Cc: Simon Glass 
Cc: Tom Rini 
---
 arch/arm/lib/ashldi3.S | 12 
 arch/arm/lib/ashrdi3.S | 12 
 arch/arm/lib/lshrdi3.S | 12 
 3 files changed, 24 insertions(+), 12 deletions(-)

diff --git a/arch/arm/lib/ashldi3.S b/arch/arm/lib/ashldi3.S
index 9c34c21..a4f5ebb 100644
--- a/arch/arm/lib/ashldi3.S
+++ b/arch/arm/lib/ashldi3.S
@@ -5,6 +5,7 @@
  */
 
 #include 
+#include 
 
 #ifdef __ARMEB__
 #define al r1
@@ -14,15 +15,18 @@
 #define ah r1
 #endif
 
-.globl __ashldi3
-__ashldi3:
+ENTRY(__ashldi3)
 ENTRY(__aeabi_llsl)
 
subsr3, r2, #32
rsb ip, r2, #32
movmi   ah, ah, lsl r2
movpl   ah, al, lsl r3
-   orrmi   ah, ah, al, lsr ip
+ ARM(  orrmi   ah, ah, al, lsr ip  )
+ THUMB(lsrmi   r3, al, ip  )
+ THUMB(orrmi   ah, ah, r3  )
mov al, al, lsl r2
-   mov pc, lr
+   ret lr
+
+ENDPROC(__ashldi3)
 ENDPROC(__aeabi_llsl)
diff --git a/arch/arm/lib/ashrdi3.S b/arch/arm/lib/ashrdi3.S
index c74fd64..c6e1ed3 100644
--- a/arch/arm/lib/ashrdi3.S
+++ b/arch/arm/lib/ashrdi3.S
@@ -5,6 +5,7 @@
  */
 
 #include 
+#include 
 
 #ifdef __ARMEB__
 #define al r1
@@ -14,15 +15,18 @@
 #define ah r1
 #endif
 
-.globl __ashrdi3
-__ashrdi3:
+ENTRY(__ashrdi3)
 ENTRY(__aeabi_lasr)
 
subsr3, r2, #32
rsb ip, r2, #32
movmi   al, al, lsr r2
movpl   al, ah, asr r3
-   orrmi   al, al, ah, lsl ip
+ ARM(  orrmi   al, al, ah, lsl ip  )
+ THUMB(lslmi   r3, ah, ip  )
+ THUMB(orrmi   al, al, r3  )
mov ah, ah, asr r2
-   mov pc, lr
+   ret lr
+
+ENDPROC(__ashrdi3)
 ENDPROC(__aeabi_lasr)
diff --git a/arch/arm/lib/lshrdi3.S b/arch/arm/lib/lshrdi3.S
index 1f9b916..9c51141 100644
--- a/arch/arm/lib/lshrdi3.S
+++ b/arch/arm/lib/lshrdi3.S
@@ -5,6 +5,7 @@
  */
 
 #include 
+#include 
 
 #ifdef __ARMEB__
 #define al r1
@@ -14,15 +15,18 @@
 #define ah r1
 #endif
 
-.globl __lshrdi3
-__lshrdi3:
+ENTRY(__lshrdi3)
 ENTRY(__aeabi_llsr)
 
subsr3, r2, #32
rsb ip, r2, #32
movmi   al, al, lsr r2
movpl   al, ah, lsr r3
-   orrmi   al, al, ah, lsl ip
+ ARM(  orrmi   al, al, ah, lsl ip  )
+ THUMB(lslmi   r3, ah, ip  )
+ THUMB(orrmi   al, al, r3  )
mov ah, ah, lsr r2
-   mov pc, lr
+   ret lr
+
+ENDPROC(__lshrdi3)
 ENDPROC(__aeabi_llsr)
-- 
2.7.0

___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH 02/12] arm: include: Import unified.h from Linux kernel

[Marek Vasut]

Import unified.h from Linux kernel 4.4.6 , commit
0d1912303e54ed1b2a371be0bba51c384dd57326 . This header file contains
macros used in libgcc functions in Linux kernel on ARM and will be
needed for the libgcc sync.

Since unified.h defines the W(instr) macro, we must drop this from
the macro from memcpy.S , otherwise this triggers a warning about
symbol redefinition. In order to keep the changes to unified.h to
the minimum, tweak arch/arm/lib/Makefile such that it defines the
CONFIG_ARM_ASM_UNIFIED macro, which places .syntax unified into all
of the assembler files. This is mandatory.

Moreover, for Thumb2 build, define CONFIG_THUMB2_KERNEL macro if and
only if Thumb2 build is enabled. This macro is checked by unified.h
and toggles between ARM and Thumb2 variant of the instructions in the
assembler source files.

Finally, this patch defines __LINUX_ARM_ARCH__=N macro based on the
new CONFIG_SYS_ARM_ARCH Kconfig option. This macro selects between
more optimal and more dense codepaths which work on armv5 and newer
and less optimal codepaths which work on armv4 and possible armv3m.
Tegra2 needs the same special handling as it does in arch/arm/Makefile
to cater for the arm720t boot core.

Signed-off-by: Marek Vasut 
Cc: Albert Aribaud 
Cc: Masahiro Yamada 
Cc: Simon Glass 
Cc: Tom Rini 
---
 arch/arm/include/asm/assembler.h |   1 +
 arch/arm/include/asm/unified.h   | 129 +++
 arch/arm/lib/Makefile|   9 ++-
 arch/arm/lib/memcpy.S|   6 --
 4 files changed, 138 insertions(+), 7 deletions(-)
 create mode 100644 arch/arm/include/asm/unified.h

diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h
index 11b80fb..ae1e42f 100644
--- a/arch/arm/include/asm/assembler.h
+++ b/arch/arm/include/asm/assembler.h
@@ -15,6 +15,7 @@
  */
 
 #include 
+#include 
 
 /*
  * Endian independent macros for shifting bytes within registers.
diff --git a/arch/arm/include/asm/unified.h b/arch/arm/include/asm/unified.h
new file mode 100644
index 000..1b26002
--- /dev/null
+++ b/arch/arm/include/asm/unified.h
@@ -0,0 +1,129 @@
+/*
+ * include/asm-arm/unified.h - Unified Assembler Syntax helper macros
+ *
+ * Copyright (C) 2008 ARM Limited
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#ifndef __ASM_UNIFIED_H
+#define __ASM_UNIFIED_H
+
+#if defined(__ASSEMBLY__) && defined(CONFIG_ARM_ASM_UNIFIED)
+   .syntax unified
+#endif
+
+#ifdef CONFIG_CPU_V7M
+#define AR_CLASS(x...)
+#define M_CLASS(x...)  x
+#else
+#define AR_CLASS(x...) x
+#define M_CLASS(x...)
+#endif
+
+#ifdef CONFIG_THUMB2_KERNEL
+
+#if __GNUC__ < 4
+#error Thumb-2 kernel requires gcc >= 4
+#endif
+
+/* The CPSR bit describing the instruction set (Thumb) */
+#define PSR_ISETSTATE  PSR_T_BIT
+
+#define ARM(x...)
+#define THUMB(x...)x
+#ifdef __ASSEMBLY__
+#define W(instr)   instr.w
+#else
+#define WASM(instr)#instr ".w"
+#endif
+
+#else  /* !CONFIG_THUMB2_KERNEL */
+
+/* The CPSR bit describing the instruction set (ARM) */
+#define PSR_ISETSTATE  0
+
+#define ARM(x...)  x
+#define THUMB(x...)
+#ifdef __ASSEMBLY__
+#define W(instr)   instr
+#else
+#define WASM(instr)#instr
+#endif
+
+#endif /* CONFIG_THUMB2_KERNEL */
+
+#ifndef CONFIG_ARM_ASM_UNIFIED
+
+/*
+ * If the unified assembly syntax isn't used (in ARM mode), these
+ * macros expand to an empty string
+ */
+#ifdef __ASSEMBLY__
+   .macro  it, cond
+   .endm
+   .macro  itt, cond
+   .endm
+   .macro  ite, cond
+   .endm
+   .macro  ittt, cond
+   .endm
+   .macro  itte, cond
+   .endm
+   .macro  itet, cond
+   .endm
+   .macro  itee, cond
+   .endm
+   .macro  i, cond
+   .endm
+   .macro  ittte, cond
+   .endm
+   .macro  ittet, cond
+   .endm
+   .macro  ittee, cond
+   .endm
+   .macro  itett, cond
+   .endm
+   .macro  itete, cond
+   .endm
+   .macro  iteet, cond
+   .endm
+   .macro  iteee, cond
+   .endm
+#else  /* !__ASSEMBLY__ */
+__asm__(
+"  .macro  it, cond\n"
+"  .endm\n"
+"  .macro  itt, cond\n"
+"  .endm\n"
+"  .macro  ite, cond\n"
+"  .endm\n"
+"  .macro  ittt, cond\n"
+"  .endm\n"
+"  .macro  itte, cond\n"
+"  .endm\n"
+"  .macro  itet, cond\n"
+"  .endm\n"
+"  .macro  itee, cond\n"
+"  .endm\n"
+"  .macro  i, cond\n"
+"  .endm\n"
+"  .macro  ittte, cond\n"
+"  .endm\n"
+"  .macro  ittet, cond\n"
+"  .endm\n"
+"  .macro  ittee, cond\n"
+"  .endm\n"
+"  .macro  itett, cond\n"
+"  .endm\n"
+"  .macro  itete, cond\n"
+"  .endm\n"
+"  .macro  iteet, cond\n"
+"  .endm\n"
+"  .macro  iteee, cond\n"
+"  .endm\n");
+#endif /* __ASSEMBLY__ */
+
+#endif /* CONFIG_ARM_ASM_UNIFIED */
+
+#endif /* !__ASM_UNIFIED_H */
diff --git 

[U-Boot] [PATCH 01/12] arm: config: Introduce CONFIG_SYS_ARM_ARCH

[Marek Vasut]

Introduce new helper Kconfig option, which is automatically set to
the version of ARM architecture for which the U-Boot is built. This
is useful when selecting tuning options in the libgcc imported from
Linux kernel.

Signed-off-by: Marek Vasut 
Cc: Albert Aribaud 
Cc: Masahiro Yamada 
Cc: Simon Glass 
Cc: Tom Rini 
---
 arch/arm/Kconfig | 14 ++
 1 file changed, 14 insertions(+)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 729b181..b71c2bb 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -64,6 +64,20 @@ config SYS_CPU
 default "sa1100" if CPU_SA1100
default "armv8" if ARM64
 
+config SYS_ARM_ARCH
+   int
+   default 4 if CPU_ARM720T
+   default 4 if CPU_ARM920T
+   default 5 if CPU_ARM926EJS
+   default 5 if CPU_ARM946ES
+   default 6 if CPU_ARM1136
+   default 6 if CPU_ARM1176
+   default 7 if CPU_V7
+   default 7 if CPU_V7M
+   default 5 if CPU_PXA
+   default 4 if CPU_SA1100
+   default 8 if ARM64
+
 config SEMIHOSTING
bool "support boot from semihosting"
help
-- 
2.7.0

___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH 07/12] arm: lib: Import __do_div64 from Linux

[Marek Vasut]

Import __do_div64 from Linux 4.4.6 , commit 
0d1912303e54ed1b2a371be0bba51c384dd57326
on arm32. This function is for some toolchains, which generate _udivmoddi4()
for 64 bit division.

Since we do not support stack unwinding, instead of importing the whole
asm/unwind.h and all the baggage, this patch defines empty UNWIND() macro.

This patch also defines CONFIG_THUMB2_KERNEL and CONFIG_ARM_ASM_UNIFIED
which is necessary for correct build of these files both in ARM and
Thumb mode, just like Linux does.

Signed-off-by: Marek Vasut 
Cc: Albert Aribaud 
Cc: Masahiro Yamada 
Cc: Simon Glass 
Cc: Tom Rini 
---
 arch/arm/lib/Makefile |   2 +-
 arch/arm/lib/div64.S  | 212 ++
 2 files changed, 213 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/lib/div64.S

diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile
index 0b0dbcb..8945915 100644
--- a/arch/arm/lib/Makefile
+++ b/arch/arm/lib/Makefile
@@ -6,7 +6,7 @@
 #
 
 lib-$(CONFIG_USE_PRIVATE_LIBGCC) += ashldi3.o ashrdi3.o lshrdi3.o \
-   lib1funcs.o uldivmod.o div0.o
+   lib1funcs.o uldivmod.o div0.o div64.o
 
 ifdef CONFIG_CPU_V7M
 obj-y  += vectors_m.o crt0.o
diff --git a/arch/arm/lib/div64.S b/arch/arm/lib/div64.S
new file mode 100644
index 000..03986c2
--- /dev/null
+++ b/arch/arm/lib/div64.S
@@ -0,0 +1,212 @@
+/*
+ *  linux/arch/arm/lib/div64.S
+ *
+ *  Optimized computation of 64-bit dividend / 32-bit divisor
+ *
+ *  Author:Nicolas Pitre
+ *  Created:   Oct 5, 2003
+ *  Copyright: Monta Vista Software, Inc.
+ *
+ *  SPDX-License-Identifier:   GPL-2.0
+ */
+
+#include 
+#include 
+#ifdef __UBOOT__
+#define UNWIND(x...)
+#endif
+
+#ifdef __ARMEB__
+#define xh r0
+#define xl r1
+#define yh r2
+#define yl r3
+#else
+#define xl r0
+#define xh r1
+#define yl r2
+#define yh r3
+#endif
+
+/*
+ * __do_div64: perform a division with 64-bit dividend and 32-bit divisor.
+ *
+ * Note: Calling convention is totally non standard for optimal code.
+ *   This is meant to be used by do_div() from include/asm/div64.h only.
+ *
+ * Input parameters:
+ * xh-xl   = dividend (clobbered)
+ * r4  = divisor (preserved)
+ *
+ * Output values:
+ * yh-yl   = result
+ * xh  = remainder
+ *
+ * Clobbered regs: xl, ip
+ */
+
+ENTRY(__do_div64)
+UNWIND(.fnstart)
+
+   @ Test for easy paths first.
+   subsip, r4, #1
+   bls 9f  @ divisor is 0 or 1
+   tst ip, r4
+   beq 8f  @ divisor is power of 2
+
+   @ See if we need to handle upper 32-bit result.
+   cmp xh, r4
+   mov yh, #0
+   blo 3f
+
+   @ Align divisor with upper part of dividend.
+   @ The aligned divisor is stored in yl preserving the original.
+   @ The bit position is stored in ip.
+
+#if __LINUX_ARM_ARCH__ >= 5
+
+   clz yl, r4
+   clz ip, xh
+   sub yl, yl, ip
+   mov ip, #1
+   mov ip, ip, lsl yl
+   mov yl, r4, lsl yl
+
+#else
+
+   mov yl, r4
+   mov ip, #1
+1: cmp yl, #0x8000
+   cmpcc   yl, xh
+   movcc   yl, yl, lsl #1
+   movcc   ip, ip, lsl #1
+   bcc 1b
+
+#endif
+
+   @ The division loop for needed upper bit positions.
+   @ Break out early if dividend reaches 0.
+2: cmp xh, yl
+   orrcs   yh, yh, ip
+   subcss  xh, xh, yl
+   movnes  ip, ip, lsr #1
+   mov yl, yl, lsr #1
+   bne 2b
+
+   @ See if we need to handle lower 32-bit result.
+3: cmp xh, #0
+   mov yl, #0
+   cmpeq   xl, r4
+   movlo   xh, xl
+   retlo   lr
+
+   @ The division loop for lower bit positions.
+   @ Here we shift remainer bits leftwards rather than moving the
+   @ divisor for comparisons, considering the carry-out bit as well.
+   mov ip, #0x8000
+4: movsxl, xl, lsl #1
+   adcsxh, xh, xh
+   beq 6f
+   cmpcc   xh, r4
+5: orrcs   yl, yl, ip
+   subcs   xh, xh, r4
+   movsip, ip, lsr #1
+   bne 4b
+   ret lr
+
+   @ The top part of remainder became zero.  If carry is set
+   @ (the 33th bit) this is a false positive so resume the loop.
+   @ Otherwise, if lower part is also null then we are done.
+6: bcs 5b
+   cmp xl, #0
+   reteq   lr
+
+   @ We still have remainer bits in the low part.  Bring them up.
+
+#if __LINUX_ARM_ARCH__ >= 5
+
+   clz xh, xl  @ we know xh is zero here so...
+   add xh, xh, #1
+   mov xl, xl, lsl xh
+   mov ip, ip, lsr xh
+
+#else
+
+7: movsxl, xl, lsl #1
+   mov ip, ip, lsr #1
+   bcc 7b
+
+#endif
+
+   @ Current remainder is now 1.  It is worthless to compare with
+   

[U-Boot] [PATCH 2/2] [RFC] ARM: omap: Enable tiny printf/sprintf on omap3_logic

[Marek Vasut]

Enable support for tiny printf and tiny sprintf on the omap3_logic
board to trim down the SPL size. This makes the SPL actually build
again and fit into the SRAM.

Signed-off-by: Marek Vasut 
Cc: Simon Glass 
Cc: Tom Rini 
---
 include/configs/omap3_logic.h | 5 +
 1 file changed, 5 insertions(+)

diff --git a/include/configs/omap3_logic.h b/include/configs/omap3_logic.h
index 3c11e2a..8ff5f66 100644
--- a/include/configs/omap3_logic.h
+++ b/include/configs/omap3_logic.h
@@ -290,6 +290,11 @@
 
 #define CONFIG_SPL_OMAP3_ID_NAND
 
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_USE_TINY_PRINTF
+#define CONFIG_USE_TINY_SPRINTF
+#endif
+
 /* NAND: SPL falcon mode configs */
 #ifdef CONFIG_SPL_OS_BOOT
 #define CONFIG_CMD_SPL_NAND_OFS0x24
-- 
2.7.0

___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH 1/2] [RFC] lib: Implement support for tiny sprintf()

[Marek Vasut]

Tweak the tiny printf code to also provide similarly tiny sprintf()
implementation. This is not comformant with POSIX for sure, but it
keeps the size down while still behaving rather reasonably.

Signed-off-by: Marek Vasut 
Cc: Simon Glass 
Cc: Tom Rini 
---
 lib/tiny-printf.c | 38 +-
 1 file changed, 33 insertions(+), 5 deletions(-)

diff --git a/lib/tiny-printf.c b/lib/tiny-printf.c
index a06abed..b9fba97 100644
--- a/lib/tiny-printf.c
+++ b/lib/tiny-printf.c
@@ -40,7 +40,17 @@ static void div_out(unsigned int *num, unsigned int div)
out_dgt(dgt);
 }
 
-int vprintf(const char *fmt, va_list va)
+#ifdef CONFIG_USE_TINY_SPRINTF
+#define local_putc(pbuf, ch)   \
+   if (pbuf)   \
+   *(pbuf)++ = (ch);   \
+   else\
+   putc(ch);
+#else
+   #define local_putc(pbuf, ch)putc(ch)
+#endif
+
+static int local_xprintf(char *pbuf, const char *fmt, va_list va)
 {
char ch;
char *p;
@@ -50,7 +60,7 @@ int vprintf(const char *fmt, va_list va)
 
while ((ch = *(fmt++))) {
if (ch != '%') {
-   putc(ch);
+   local_putc(pbuf, ch);
} else {
char lz = 0;
char w = 0;
@@ -115,10 +125,10 @@ int vprintf(const char *fmt, va_list va)
while (*bf++ && w > 0)
w--;
while (w-- > 0)
-   putc(lz ? '0' : ' ');
+   local_putc(pbuf, lz ? '0' : ' ');
if (p) {
while ((ch = *p++))
-   putc(ch);
+   local_putc(pbuf, ch);
}
}
}
@@ -127,13 +137,31 @@ abort:
return 0;
 }
 
+
+int vprintf(const char *fmt, va_list va)
+{
+   return local_xprintf(NULL, fmt, va);
+}
+
 int printf(const char *fmt, ...)
 {
va_list va;
int ret;
 
va_start(va, fmt);
-   ret = vprintf(fmt, va);
+   ret = local_xprintf(NULL, fmt, va);
+   va_end(va);
+
+   return ret;
+}
+
+int sprintf(char *buf, const char *fmt, ...)
+{
+   va_list va;
+   int ret;
+
+   va_start(va, fmt);
+   ret = local_xprintf(buf, fmt, va);
va_end(va);
 
return ret;
-- 
2.7.0

___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH 3/3] MIPS: Abstract cache op loops with a macro

[Paul Burton]

The various cache maintenance routines perform a number of loops over
cache lines. Rather than duplicate the code for performing such loops,
abstract it out into a new cache_loop macro which performs an arbitrary
number of cache ops on a range of addresses. This reduces duplication in
the existing L1 cache maintenance code & will allow for not adding
further duplication when introducing L2 cache support.

Signed-off-by: Paul Burton 

---

 arch/mips/lib/cache.c | 59 ---
 1 file changed, 18 insertions(+), 41 deletions(-)

diff --git a/arch/mips/lib/cache.c b/arch/mips/lib/cache.c
index 2bb91c6..320335c 100644
--- a/arch/mips/lib/cache.c
+++ b/arch/mips/lib/cache.c
@@ -37,82 +37,59 @@ static inline unsigned long dcache_line_size(void)
return 2 << dl;
 }
 
+#define cache_loop(start, end, lsize, ops...) do { \
+   const void *addr = (const void *)(start & ~(lsize - 1));\
+   const void *aend = (const void *)((end - 1) & ~(lsize - 1));\
+   const unsigned int cache_ops[] = { ops };   \
+   unsigned int i; \
+   \
+   for (; addr <= aend; addr += lsize) {   \
+   for (i = 0; i < ARRAY_SIZE(cache_ops); i++) \
+   mips_cache(cache_ops[i], addr); \
+   }   \
+} while (0)
+
 void flush_cache(ulong start_addr, ulong size)
 {
unsigned long ilsize = icache_line_size();
unsigned long dlsize = dcache_line_size();
-   const void *addr, *aend;
 
/* aend will be miscalculated when size is zero, so we return here */
if (size == 0)
return;
 
-   addr = (const void *)(start_addr & ~(dlsize - 1));
-   aend = (const void *)((start_addr + size - 1) & ~(dlsize - 1));
-
if (ilsize == dlsize) {
/* flush I-cache & D-cache simultaneously */
-   while (1) {
-   mips_cache(HIT_WRITEBACK_INV_D, addr);
-   mips_cache(HIT_INVALIDATE_I, addr);
-   if (addr == aend)
-   break;
-   addr += dlsize;
-   }
+   cache_loop(start_addr, start_addr + size, ilsize,
+  HIT_WRITEBACK_INV_D, HIT_INVALIDATE_I);
return;
}
 
/* flush D-cache */
-   while (1) {
-   mips_cache(HIT_WRITEBACK_INV_D, addr);
-   if (addr == aend)
-   break;
-   addr += dlsize;
-   }
+   cache_loop(start_addr, start_addr + size, dlsize, HIT_WRITEBACK_INV_D);
 
/* flush I-cache */
-   addr = (const void *)(start_addr & ~(ilsize - 1));
-   aend = (const void *)((start_addr + size - 1) & ~(ilsize - 1));
-   while (1) {
-   mips_cache(HIT_INVALIDATE_I, addr);
-   if (addr == aend)
-   break;
-   addr += ilsize;
-   }
+   cache_loop(start_addr, start_addr + size, ilsize, HIT_INVALIDATE_I);
 }
 
 void flush_dcache_range(ulong start_addr, ulong stop)
 {
unsigned long lsize = dcache_line_size();
-   const void *addr = (const void *)(start_addr & ~(lsize - 1));
-   const void *aend = (const void *)((stop - 1) & ~(lsize - 1));
 
/* aend will be miscalculated when size is zero, so we return here */
if (start_addr == stop)
return;
 
-   while (1) {
-   mips_cache(HIT_WRITEBACK_INV_D, addr);
-   if (addr == aend)
-   break;
-   addr += lsize;
-   }
+   cache_loop(start_addr, stop, lsize, HIT_WRITEBACK_INV_D);
 }
 
 void invalidate_dcache_range(ulong start_addr, ulong stop)
 {
unsigned long lsize = dcache_line_size();
-   const void *addr = (const void *)(start_addr & ~(lsize - 1));
-   const void *aend = (const void *)((stop - 1) & ~(lsize - 1));
 
/* aend will be miscalculated when size is zero, so we return here */
if (start_addr == stop)
return;
 
-   while (1) {
-   mips_cache(HIT_INVALIDATE_D, addr);
-   if (addr == aend)
-   break;
-   addr += lsize;
-   }
+   cache_loop(start_addr, stop, lsize, HIT_INVALIDATE_I);
 }
-- 
2.8.3

___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH 2/3] MIPS: Split I & D cache line size config

[Paul Burton]

Allow L1 Icache & L1 Dcache line size to be specified separately, since
there's no architectural mandate that they be the same. The
[id]cache_line_size functions are tidied up to take advantage of the
fact that the Kconfig entries are always present to simply check them
for zero rather than needing to #ifdef on their presence.

Signed-off-by: Paul Burton 
---

 arch/mips/Kconfig|  6 +-
 arch/mips/lib/cache.c| 22 +++---
 arch/mips/lib/cache_init.S   |  4 ++--
 board/dbau1x00/Kconfig   |  5 -
 board/micronas/vct/Kconfig   |  5 -
 board/pb1x00/Kconfig |  5 -
 board/qca/ap121/Kconfig  |  5 -
 board/qca/ap143/Kconfig  |  5 -
 board/qemu-mips/Kconfig  |  5 -
 board/tplink/wdr4300/Kconfig |  5 -
 10 files changed, 42 insertions(+), 25 deletions(-)

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 13f1164..8af8799 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -247,11 +247,15 @@ config SYS_DCACHE_SIZE
hex
default 0
 
+config SYS_DCACHE_LINE_SIZE
+   hex
+   default 0
+
 config SYS_ICACHE_SIZE
hex
default 0
 
-config SYS_CACHELINE_SIZE
+config SYS_ICACHE_LINE_SIZE
hex
default 0
 
diff --git a/arch/mips/lib/cache.c b/arch/mips/lib/cache.c
index 7695325..2bb91c6 100644
--- a/arch/mips/lib/cache.c
+++ b/arch/mips/lib/cache.c
@@ -9,23 +9,13 @@
 #include 
 #include 
 
-#if CONFIG_SYS_CACHELINE_SIZE != 0
-
 static inline unsigned long icache_line_size(void)
 {
-   return CONFIG_SYS_CACHELINE_SIZE;
-}
-
-static inline unsigned long dcache_line_size(void)
-{
-   return CONFIG_SYS_CACHELINE_SIZE;
-}
+   unsigned long conf1, il;
 
-#else /* !CONFIG_SYS_CACHELINE_SIZE */
+   if (CONFIG_SYS_ICACHE_LINE_SIZE != 0)
+   return CONFIG_SYS_ICACHE_LINE_SIZE;
 
-static inline unsigned long icache_line_size(void)
-{
-   unsigned long conf1, il;
conf1 = read_c0_config1();
il = (conf1 & MIPS_CONF1_IL) >> MIPS_CONF1_IL_SHF;
if (!il)
@@ -36,6 +26,10 @@ static inline unsigned long icache_line_size(void)
 static inline unsigned long dcache_line_size(void)
 {
unsigned long conf1, dl;
+
+   if (CONFIG_SYS_DCACHE_LINE_SIZE != 0)
+   return CONFIG_SYS_DCACHE_LINE_SIZE;
+
conf1 = read_c0_config1();
dl = (conf1 & MIPS_CONF1_DL) >> MIPS_CONF1_DL_SHF;
if (!dl)
@@ -43,8 +37,6 @@ static inline unsigned long dcache_line_size(void)
return 2 << dl;
 }
 
-#endif /* !CONFIG_SYS_CACHELINE_SIZE */
-
 void flush_cache(ulong start_addr, ulong size)
 {
unsigned long ilsize = icache_line_size();
diff --git a/arch/mips/lib/cache_init.S b/arch/mips/lib/cache_init.S
index e4a44ff..41cb3a6 100644
--- a/arch/mips/lib/cache_init.S
+++ b/arch/mips/lib/cache_init.S
@@ -101,14 +101,14 @@
 LEAF(mips_cache_reset)
 #if CONFIG_SYS_ICACHE_SIZE != 0
li  t2, CONFIG_SYS_ICACHE_SIZE
-   li  t8, CONFIG_SYS_CACHELINE_SIZE
+   li  t8, CONFIG_SYS_ICACHE_LINE_SIZE
 #else
l1_info t2, t8, MIPS_CONF1_IA_SHF
 #endif
 
 #if CONFIG_SYS_DCACHE_SIZE != 0
li  t3, CONFIG_SYS_DCACHE_SIZE
-   li  t9, CONFIG_SYS_CACHELINE_SIZE
+   li  t9, CONFIG_SYS_DCACHE_LINE_SIZE
 #else
l1_info t3, t9, MIPS_CONF1_DA_SHF
 #endif
diff --git a/board/dbau1x00/Kconfig b/board/dbau1x00/Kconfig
index 1715a28..448176d 100644
--- a/board/dbau1x00/Kconfig
+++ b/board/dbau1x00/Kconfig
@@ -15,10 +15,13 @@ config SYS_TEXT_BASE
 config SYS_DCACHE_SIZE
default 16384
 
+config SYS_DCACHE_LINE_SIZE
+   default 32
+
 config SYS_ICACHE_SIZE
default 16384
 
-config SYS_CACHELINE_SIZE
+config SYS_ICACHE_LINE_SIZE
default 32
 
 menu "dbau1x00 board options"
diff --git a/board/micronas/vct/Kconfig b/board/micronas/vct/Kconfig
index 5bb6f03..df7c029 100644
--- a/board/micronas/vct/Kconfig
+++ b/board/micronas/vct/Kconfig
@@ -15,10 +15,13 @@ config SYS_TEXT_BASE
 config SYS_DCACHE_SIZE
default 16384
 
+config SYS_DCACHE_LINE_SIZE
+   default 32
+
 config SYS_ICACHE_SIZE
default 16384
 
-config SYS_CACHELINE_SIZE
+config SYS_ICACHE_LINE_SIZE
default 32
 
 menu "vct board options"
diff --git a/board/pb1x00/Kconfig b/board/pb1x00/Kconfig
index 27b2ef0..ef8905d 100644
--- a/board/pb1x00/Kconfig
+++ b/board/pb1x00/Kconfig
@@ -15,10 +15,13 @@ config SYS_TEXT_BASE
 config SYS_DCACHE_SIZE
default 16384
 
+config SYS_DCACHE_LINE_SIZE
+   default 32
+
 config SYS_ICACHE_SIZE
default 16384
 
-config SYS_CACHELINE_SIZE
+config SYS_ICACHE_LINE_SIZE
default 32
 
 endif
diff --git a/board/qca/ap121/Kconfig b/board/qca/ap121/Kconfig
index 1ace0e5..09a06d8 100644
--- a/board/qca/ap121/Kconfig
+++ b/board/qca/ap121/Kconfig
@@ -15,10 +15,13 @@ config SYS_TEXT_BASE
 config SYS_DCACHE_SIZE
default 0x8000
 
+config SYS_DCACHE_LINE_SIZE
+   default 32
+
 config SYS_ICACHE_SIZE

[U-Boot] [PATCH 0/3] MIPS cache cleanups

[Paul Burton]

This short series cleans up the MIPS cache code in preparation for
introducing support for L2 cache support. It's hopefully a useful
standalone cleanup as-is, so I'll submit it now.

Paul Burton (3):
  MIPS: Move cache sizes to Kconfig
  MIPS: Split I & D cache line size config
  MIPS: Abstract cache op loops with a macro

 arch/mips/Kconfig| 16 
 arch/mips/lib/cache.c| 79 
 arch/mips/lib/cache_init.S   | 10 ++---
 board/dbau1x00/Kconfig   | 12 ++
 board/micronas/vct/Kconfig   | 12 ++
 board/pb1x00/Kconfig | 12 ++
 board/qca/ap121/Kconfig  | 12 ++
 board/qca/ap143/Kconfig  | 12 ++
 board/qemu-mips/Kconfig  | 12 ++
 board/tplink/wdr4300/Kconfig | 12 ++
 include/configs/ap121.h  |  5 ---
 include/configs/ap143.h  |  5 ---
 include/configs/dbau1x00.h   |  7 
 include/configs/pb1x00.h |  6 ---
 include/configs/qemu-mips.h  |  7 
 include/configs/qemu-mips64.h|  7 
 include/configs/tplink_wdr4300.h |  5 ---
 include/configs/vct.h|  7 
 18 files changed, 129 insertions(+), 109 deletions(-)

-- 
2.8.3

___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH 1/3] MIPS: Move cache sizes to Kconfig

[Paul Burton]

Move details of the L1 cache line sizes & total sizes into Kconfig,
defaulting to 0 & using 0 to indicate that the value should be
autodetected.

Signed-off-by: Paul Burton 
---

 arch/mips/Kconfig| 12 
 arch/mips/lib/cache.c|  2 +-
 arch/mips/lib/cache_init.S   |  6 +++---
 board/dbau1x00/Kconfig   |  9 +
 board/micronas/vct/Kconfig   |  9 +
 board/pb1x00/Kconfig |  9 +
 board/qca/ap121/Kconfig  |  9 +
 board/qca/ap143/Kconfig  |  9 +
 board/qemu-mips/Kconfig  |  9 +
 board/tplink/wdr4300/Kconfig |  9 +
 include/configs/ap121.h  |  5 -
 include/configs/ap143.h  |  5 -
 include/configs/dbau1x00.h   |  7 ---
 include/configs/pb1x00.h |  6 --
 include/configs/qemu-mips.h  |  7 ---
 include/configs/qemu-mips64.h|  7 ---
 include/configs/tplink_wdr4300.h |  5 -
 include/configs/vct.h|  7 ---
 18 files changed, 79 insertions(+), 53 deletions(-)

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index abaeaf0..13f1164 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -243,6 +243,18 @@ config SWAP_IO_SPACE
 config SYS_MIPS_CACHE_INIT_RAM_LOAD
bool
 
+config SYS_DCACHE_SIZE
+   hex
+   default 0
+
+config SYS_ICACHE_SIZE
+   hex
+   default 0
+
+config SYS_CACHELINE_SIZE
+   hex
+   default 0
+
 config MIPS_L1_CACHE_SHIFT_4
bool
 
diff --git a/arch/mips/lib/cache.c b/arch/mips/lib/cache.c
index 7482005..7695325 100644
--- a/arch/mips/lib/cache.c
+++ b/arch/mips/lib/cache.c
@@ -9,7 +9,7 @@
 #include 
 #include 
 
-#ifdef CONFIG_SYS_CACHELINE_SIZE
+#if CONFIG_SYS_CACHELINE_SIZE != 0
 
 static inline unsigned long icache_line_size(void)
 {
diff --git a/arch/mips/lib/cache_init.S b/arch/mips/lib/cache_init.S
index 08b7c3a..e4a44ff 100644
--- a/arch/mips/lib/cache_init.S
+++ b/arch/mips/lib/cache_init.S
@@ -99,14 +99,14 @@
  *
  */
 LEAF(mips_cache_reset)
-#ifdef CONFIG_SYS_ICACHE_SIZE
+#if CONFIG_SYS_ICACHE_SIZE != 0
li  t2, CONFIG_SYS_ICACHE_SIZE
li  t8, CONFIG_SYS_CACHELINE_SIZE
 #else
l1_info t2, t8, MIPS_CONF1_IA_SHF
 #endif
 
-#ifdef CONFIG_SYS_DCACHE_SIZE
+#if CONFIG_SYS_DCACHE_SIZE != 0
li  t3, CONFIG_SYS_DCACHE_SIZE
li  t9, CONFIG_SYS_CACHELINE_SIZE
 #else
@@ -116,7 +116,7 @@ LEAF(mips_cache_reset)
 #ifdef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD
 
/* Determine the largest L1 cache size */
-#if defined(CONFIG_SYS_ICACHE_SIZE) && defined(CONFIG_SYS_DCACHE_SIZE)
+#if (CONFIG_SYS_ICACHE_SIZE != 0) && (CONFIG_SYS_DCACHE_SIZE != 0)
 #if CONFIG_SYS_ICACHE_SIZE > CONFIG_SYS_DCACHE_SIZE
li  v0, CONFIG_SYS_ICACHE_SIZE
 #else
diff --git a/board/dbau1x00/Kconfig b/board/dbau1x00/Kconfig
index 342ec59..1715a28 100644
--- a/board/dbau1x00/Kconfig
+++ b/board/dbau1x00/Kconfig
@@ -12,6 +12,15 @@ config SYS_CONFIG_NAME
 config SYS_TEXT_BASE
default 0xbfc0
 
+config SYS_DCACHE_SIZE
+   default 16384
+
+config SYS_ICACHE_SIZE
+   default 16384
+
+config SYS_CACHELINE_SIZE
+   default 32
+
 menu "dbau1x00 board options"
 
 choice
diff --git a/board/micronas/vct/Kconfig b/board/micronas/vct/Kconfig
index 535a77b..5bb6f03 100644
--- a/board/micronas/vct/Kconfig
+++ b/board/micronas/vct/Kconfig
@@ -12,6 +12,15 @@ config SYS_CONFIG_NAME
 config SYS_TEXT_BASE
default 0x8700
 
+config SYS_DCACHE_SIZE
+   default 16384
+
+config SYS_ICACHE_SIZE
+   default 16384
+
+config SYS_CACHELINE_SIZE
+   default 32
+
 menu "vct board options"
 
 choice
diff --git a/board/pb1x00/Kconfig b/board/pb1x00/Kconfig
index 236a410..27b2ef0 100644
--- a/board/pb1x00/Kconfig
+++ b/board/pb1x00/Kconfig
@@ -12,4 +12,13 @@ config SYS_CONFIG_NAME
 config SYS_TEXT_BASE
default 0x8380
 
+config SYS_DCACHE_SIZE
+   default 16384
+
+config SYS_ICACHE_SIZE
+   default 16384
+
+config SYS_CACHELINE_SIZE
+   default 32
+
 endif
diff --git a/board/qca/ap121/Kconfig b/board/qca/ap121/Kconfig
index c3ecc8f..1ace0e5 100644
--- a/board/qca/ap121/Kconfig
+++ b/board/qca/ap121/Kconfig
@@ -12,4 +12,13 @@ config SYS_CONFIG_NAME
 config SYS_TEXT_BASE
default 0x9f00
 
+config SYS_DCACHE_SIZE
+   default 0x8000
+
+config SYS_ICACHE_SIZE
+   default 0x1
+
+config SYS_CACHELINE_SIZE
+   default 32
+
 endif
diff --git a/board/qca/ap143/Kconfig b/board/qca/ap143/Kconfig
index 5ea5d6f..ac73782 100644
--- a/board/qca/ap143/Kconfig
+++ b/board/qca/ap143/Kconfig
@@ -12,4 +12,13 @@ config SYS_CONFIG_NAME
 config SYS_TEXT_BASE
default 0x9f00
 
+config SYS_DCACHE_SIZE
+   default 0x8000
+
+config SYS_ICACHE_SIZE
+   default 0x1
+
+config SYS_CACHELINE_SIZE
+   default 32
+
 endif
diff --git a/board/qemu-mips/Kconfig b/board/qemu-mips/Kconfig
index 3de1f44..66957e7 100644
--- 

Re: [U-Boot] [PATCH v2] MIPS: provide a default u-boot-spl.lds

[Marek Vasut]

On 05/26/2016 03:28 PM, Daniel Schwierzeck wrote:
> Provide a default linker script for SPL binaries. Start address
> and size of text section and BSS section are configurable. All
> sections are arranged in a way that only relevant sections are
> kept in the code section for maximum size reduction. All other
> sections are kept but moved outside the code section to help
> with debugging.
> 
> Signed-off-by: Daniel Schwierzeck 
> 
> ---
> 
> Changes in v2:
> - add missing section .u_boot_list
> 
>  arch/mips/config.mk  |  5 ++-
>  arch/mips/cpu/u-boot-spl.lds | 90 
> 
>  2 files changed, 93 insertions(+), 2 deletions(-)
>  create mode 100644 arch/mips/cpu/u-boot-spl.lds
> 
> diff --git a/arch/mips/config.mk b/arch/mips/config.mk
> index 609a998..dcd3460 100644
> --- a/arch/mips/config.mk
> +++ b/arch/mips/config.mk
> @@ -65,7 +65,7 @@ else
>  PF_ABICALLS  := -mabicalls
>  PF_PIC   := -fpic
>  PF_PIE   := -pie
> -PF_OBJCOPY   := -j .got -j .u_boot_list -j .rel.dyn -j 
> .padding
> +PF_OBJCOPY   := -j .got -j .rel.dyn -j .padding
>  PF_OBJCOPY   += -j .dtb.init.rodata
>  endif
>  
> @@ -74,4 +74,5 @@ PLATFORM_CPPFLAGS   += -msoft-float
>  PLATFORM_LDFLAGS += -G 0 -static -n -nostdlib
>  PLATFORM_RELFLAGS+= -ffunction-sections -fdata-sections
>  LDFLAGS_FINAL+= --gc-sections $(PF_PIE)
> -OBJCOPYFLAGS += -j .text -j .rodata -j .data $(PF_OBJCOPY)
> +OBJCOPYFLAGS += -j .text -j .rodata -j .data -j .u_boot_list
> +OBJCOPYFLAGS += $(PF_OBJCOPY)
> diff --git a/arch/mips/cpu/u-boot-spl.lds b/arch/mips/cpu/u-boot-spl.lds
> new file mode 100644
> index 000..07004ea
> --- /dev/null
> +++ b/arch/mips/cpu/u-boot-spl.lds
> @@ -0,0 +1,90 @@
> +/*
> + * SPDX-License-Identifier:  GPL-2.0+
> + */
> +
> +MEMORY { .spl_mem : ORIGIN = CONFIG_SPL_TEXT_BASE, \
> + LENGTH = CONFIG_SPL_MAX_SIZE }
> +MEMORY { .bss_mem : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \
> + LENGTH = CONFIG_SPL_BSS_MAX_SIZE }
> +
> +OUTPUT_ARCH(mips)
> +ENTRY(_start)
> +SECTIONS
> +{
> + . = 0x;
> +
> + . = ALIGN(4);
> + .text : {
> + *(.text*)
> + } > .spl_mem
> +
> + . = ALIGN(4);
> + .rodata : {
> + *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
> + } > .spl_mem
> +
> + . = ALIGN(4);
> + .data : {
> + *(SORT_BY_ALIGNMENT(.data*))
> + *(SORT_BY_ALIGNMENT(.sdata*))
> + } > .spl_mem
> +
> +#ifdef CONFIG_SPL_DM

Is the ifdef really necessary ? I think if the list is empty, the
u_boot_list will just be an zero-length symbol and since both this and
the image_copy_end are 4-byte aligned, there will be no wasted space.

> + . = ALIGN(4);
> + .u_boot_list : {
> + KEEP(*(SORT(.u_boot_list*)));
> + } > .spl_mem
> +#endif
> +
> + . = ALIGN(4);
> + __image_copy_end = .;
> +
> + .bss (NOLOAD) : {
> + __bss_start = .;
> + *(.bss*)
> + *(.sbss*)
> + *(COMMON)
> + . = ALIGN(4);
> + __bss_end = .;
> + } > .bss_mem
> +
> + .rel.dyn (NOLOAD) : {
> + *(.rel.dyn)
> + }
> +
> + .dynsym : {
> + *(.dynsym)
> + }
> +
> + .dynbss : {
> + *(.dynbss)
> + }
> +
> + .dynstr : {
> + *(.dynstr)
> + }
> +
> + .dynamic : {
> + *(.dynamic)
> + }
> +
> + .plt : {
> + *(.plt)
> + }
> +
> + .interp : {
> + *(.interp)
> + }
> +
> + .gnu : {
> + *(.gnu*)
> + }
> +
> + .MIPS.stubs : {
> + *(.MIPS.stubs)
> + }
> +
> + .hash : {
> + *(.hash)
> + }
> +}
> 


-- 
Best regards,
Marek Vasut
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Re: [U-Boot] [GIT PULL] u-boot-mips/master

[Tom Rini]

On Thu, May 26, 2016 at 02:13:38AM +0200, Daniel Schwierzeck wrote:

> Hi Tom,
> 
> here is another batch of MIPS updates.
> 
> The following changes since commit fc15b9beed05dec6cc092c265042381a0eadb0e9:
> 
>   Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq (2016-05-24 
> 13:42:03 -0400)
> 
> are available in the git repository at:
> 
>   git://git.denx.de/u-boot-mips.git master
> 
> for you to fetch changes up to 4349b55b9953d0bb591f13ca9985edf591348ced:
> 
>   mips: ath79: ar933x: Avoid warning with gcc5 (2016-05-26 01:34:14 +0200)
> 

Applied to u-boot/master, thanks!

-- 
Tom


signature.asc
Description: Digital signature
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Re: [U-Boot] arm64: fix arm64 Linux boot image header field sizes

[Tom Rini]

On Wed, May 25, 2016 at 09:48:14AM +0100, Andre Przywara wrote:

> The arm64 Linux boot protocol [1] describes the fields in the Image
> header as being 64-bit little endian values.
> So fix the endianess conversion to use 64-bit sized operations, for
> both image_size and text_offset.
> Also we use a local variable for the image_size to avoid both writing
> to the header and also accessing it after we actually unmapped it.
> 
> Signed-off-by: Andre Przywara 
> 
> [1] 
> https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/Documentation/arm64/booting.txt

Applied to u-boot/master, thanks!

-- 
Tom


signature.asc
Description: Digital signature
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Re: [U-Boot] Please pull u-boot-mpc85xx master

[Tom Rini]

On Tue, May 24, 2016 at 08:37:01PM -0700, York Sun wrote:

> Tom,
> 
> The following changes since commit aeaec0e682f45b9e0c62c522fafea353931f73ed:
> 
>   Prepare v2016.05 (2016-05-16 10:40:32 -0400)
> 
> are available in the git repository at:
> 
>   git://git.denx.de/u-boot-mpc85xx.git master
> 
> for you to fetch changes up to 8ef548d5f13e68e1b3975d9b68920bfa8bf09891:
> 
>   powerpc:t4240: MAC9 and MAC10 should not be identified as 1G interface in 
> some
> case (2016-05-24 17:11:03 -0700)
> 

Applied to u-boot/master, thanks!

-- 
Tom


signature.asc
Description: Digital signature
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Re: [U-Boot] Please pull u-boot-sunxi master

[Tom Rini]

On Wed, May 25, 2016 at 06:15:39PM +0200, Hans de Goede wrote:

> Hi Tom,
> 
> Here is the first sunxi pull-req for v2016.07, it
> contains a few improvements and fixes, nothing special.
> 
> Note the big diffstat is due to cleaning up defconfig's
> be enabling various CMD options by default on sunxi.
> 
> The following changes since commit fc15b9beed05dec6cc092c265042381a0eadb0e9:
> 
>   Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq (2016-05-24 
> 13:42:03 -0400)
> 
> are available in the git repository at:
> 
>   http://git.denx.de/u-boot-sunxi.git master
> 
> for you to fetch changes up to 0e6e34ac8dbb597a34e1eca4fb640c3eb5e52467:
> 
>   sunxi: Olimex A20 boards: Enable LDO3 and LDO4 regulators (2016-05-25 
> 17:52:56 +0200)
> 

Applied to u-boot/master, thanks!

-- 
Tom


signature.asc
Description: Digital signature
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Re: [U-Boot] [PATCH] ARM: dts: dra7x: Support QSPI MODE-0 operation at 64MHz

[Tom Rini]

On Wed, May 25, 2016 at 01:18:43PM +0530, Vignesh R wrote:
> 
> 
> On 05/20/2016 06:32 PM, Tom Rini wrote:
> > On Fri, May 20, 2016 at 04:11:22PM +0530, Vignesh R wrote:
> > 
> >> According to Data Manual(SPRS915P) of AM57x, TI QSPI controller on
> >> DRA74(rev 1.1+)/DRA72 EVM can support up to 64MHz in MODE-0, whereas
> >> MODE-3 is limited to 48MHz. Hence, switch to MODE-0 for better
> >> throughput.
> >>
> >> Signed-off-by: Vignesh R 
> > 
> > Are older revs seen in the wild or just within TI?  Thanks!
> 
> QSPI was never supported on rev 1.0 due to erratas, moreover rev 1.0s
> are not production version.

OK, thanks!

Reviewed-by: Tom Rini 

-- 
Tom


signature.asc
Description: Digital signature
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Re: [U-Boot] pull request: u-boot-uniphier/master

[Tom Rini]

On Thu, May 26, 2016 at 12:52:04AM +0900, Masahiro Yamada wrote:

> Hi Tom,
> 
> Here are some UniPhier SoC updates for v2016.07-rc1:
> - Support the second ARMv8 SoC from Socionext Inc.
> - Misc cleanups and fixes
> 
> 
> The following changes since commit fc15b9beed05dec6cc092c265042381a0eadb0e9:
> 
>   Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq
> (2016-05-24 13:42:03 -0400)
> 
> are available in the git repository at:
> 
> 
>   git://git.denx.de/u-boot-uniphier.git master
> 
> for you to fetch changes up to d7e103c08f5bb29d8126eaef3b7b6d6bafacea80:
> 
>   ARM: uniphier: add EHCI nodes for PH1-LD11 (2016-05-26 00:37:13 +0900)
> 

Applied to u-boot/master, thanks!

-- 
Tom


signature.asc
Description: Digital signature
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Re: [U-Boot] [PATCH] ARM: k2g: Configure reset mux to device reset

[Nishanth Menon]

On 05/26/2016 08:35 AM, Lokesh Vutla wrote:
> BOOTCFG_RSTMUX8 register controls the reset mux associated with the ARM.
> Timer5(dedicated to ARM) when used as WatchDog timer, the events it
> generates are routed to the above mux.
> 
> Following are the 3 events that can controlled bt the reset mux:
> - Device Reset
> - An interrupt to the ARM_GIC
> - An interrupt to the ARM_GIC followed by a device reset.
> 
> Right now to give a default watchdog behaviour "Device reset" is
> being selected.
> 
> Signed-off-by: Lokesh Vutla 
> ---


Thanks.
Acked-by: Nishanth Menon 

>  arch/arm/mach-keystone/include/mach/hardware-k2g.h | 12 
>  board/ti/ks2_evm/board_k2g.c   | 16 
>  2 files changed, 28 insertions(+)
> 
> diff --git a/arch/arm/mach-keystone/include/mach/hardware-k2g.h 
> b/arch/arm/mach-keystone/include/mach/hardware-k2g.h
> index ca2a119..0f6bf61 100644
> --- a/arch/arm/mach-keystone/include/mach/hardware-k2g.h
> +++ b/arch/arm/mach-keystone/include/mach/hardware-k2g.h
> @@ -74,4 +74,16 @@
>  #define K2G_GPIO_DIR_OFFSET  0x0
>  #define K2G_GPIO_SETDATA_OFFSET  0x8
>  
> +/* BOOTCFG RESETMUX8 */
> +#define KS2_RSTMUX8  (KS2_DEVICE_STATE_CTRL_BASE + 0x328)
> +
> +/* RESETMUX register definitions */
> +#define RSTMUX_LOCK8_SHIFT   0x0
> +#define RSTMUX_LOCK8_MASK(0x1 << 0)
> +#define RSTMUX_OMODE8_SHIFT  0x1
> +#define RSTMUX_OMODE8_MASK   (0x7 << 1)
> +#define RSTMUX_OMODE8_DEV_RESET  0x2
> +#define RSTMUX_OMODE8_INT0x3
> +#define RSTMUX_OMODE8_INT_AND_DEV_RESET  0x4
> +
>  #endif /* __ASM_ARCH_HARDWARE_K2G_H */
> diff --git a/board/ti/ks2_evm/board_k2g.c b/board/ti/ks2_evm/board_k2g.c
> index b62c412..8f16845 100644
> --- a/board/ti/ks2_evm/board_k2g.c
> +++ b/board/ti/ks2_evm/board_k2g.c
> @@ -117,12 +117,28 @@ int board_mmc_init(bd_t *bis)
>  #endif
>  
>  #ifdef CONFIG_BOARD_EARLY_INIT_F
> +
> +static void k2g_reset_mux_config(void)
> +{
> + /* Unlock the reset mux register */
> + clrbits_le32(KS2_RSTMUX8, RSTMUX_LOCK8_MASK);
> +
> + /* Configure BOOTCFG_RSTMUX8 for WDT event to cause a device reset */
> + clrsetbits_le32(KS2_RSTMUX8, RSTMUX_OMODE8_MASK,
> + RSTMUX_OMODE8_DEV_RESET << RSTMUX_OMODE8_SHIFT);
> +
> + /* lock the reset mux register to prevent any spurious writes. */
> + setbits_le32(KS2_RSTMUX8, RSTMUX_LOCK8_MASK);
> +}
> +
>  int board_early_init_f(void)
>  {
>   init_plls();
>  
>   k2g_mux_config();
>  
> + k2g_reset_mux_config();
> +
>   /* deassert FLASH_HOLD */
>   clrbits_le32(K2G_GPIO1_BANK2_BASE + K2G_GPIO_DIR_OFFSET,
>BIT(9));
> 


-- 
Regards,
Nishanth Menon
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Re: [U-Boot] [PATCH] serial: 16550: Drop OMAP1510 support

[Nishanth Menon]

On 05/24/2016 07:13 PM, Marek Vasut wrote:
> The CONFIG_OMAP1510 is no longer defined, so remove this dead code.
> 
> Signed-off-by: Marek Vasut 
> Cc: Tom Rini 
> Cc: Simon Glass 

Acked-by: Nishanth Menon 

-- 
Regards,
Nishanth Menon
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Re: [U-Boot] please pull u-boot-samsung master

[Tom Rini]

On Thu, May 26, 2016 at 02:03:08PM +0900, Minkyu Kang wrote:

> Dear Tom,
> 
> The following changes since commit fc15b9beed05dec6cc092c265042381a0eadb0e9:
> 
>   Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq (2016-05-24 
> 13:42:03 -0400)
> 
> are available in the git repository at:
> 
> 
>   http://git.denx.de/u-boot-samsung 
> 
> for you to fetch changes up to 086e13c5f6f79a68246d6b803cf4736cb6815e44:
> 
>   ARM: exynos: Disable serial support in SPL (2016-05-26 12:55:49 +0900)
> 

With this applied snow, peach-pi, spring and peach-pit no longer compile
due to an EFI issue, please investigate, thanks!

-- 
Tom


signature.asc
Description: Digital signature
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Re: [U-Boot] [PATCH 2/4] MIPS: Fix _ACAST32_ for pointers on MIPS64

[Daniel Schwierzeck]

Am 26.05.2016 um 15:51 schrieb Paul Burton:
> 
> Hi Daniel,
> 
> I've submitted an alternate fix in v2 of the series just now. It still
> requires a change to MIPS code but it mirrors one I have submitted to
> Linux, and hopefully one you'll find acceptable. It makes MIPS32 &
> MIPS64 more consistent & prevents drivers needing to care about which
> segment of the virtual address space an address is in when calling
> virt_to_phys.
> 

yes that one looks good, thanks.

-- 
- Daniel



signature.asc
Description: OpenPGP digital signature
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH] net: phy: micrel: add support for KSZ886x switches in MIIM mode

[Alexey Firago]

This patch adds a phy driver for the Micrel KSZ886x switches.

Similarly to the KSZ8895, SoC MAC is directly connected to the switch
MAC on the switch CPU port, so the link to the switch is always up.

KSZ886x switches can be used in the following configuration modes:
- Unmanaged mode with config stored in external EEPROM
- Managed mode over SPI
- Managed mode over I2C
- Managed mode over mdio/mdc (aka MIIM or SMI)

This patch supports only unmanaged and MIIM modes.

Based on Micrel KSZ886x driver from Linux kernel and
Micrel KSZ8895 driver from U-Boot.

Verified with the KSZ8863MLL.

Signed-off-by: Alexey Firago 
---
 drivers/net/phy/micrel.c | 26 ++
 1 file changed, 26 insertions(+)

diff --git a/drivers/net/phy/micrel.c b/drivers/net/phy/micrel.c
index 8fcf737..58891f8 100644
--- a/drivers/net/phy/micrel.c
+++ b/drivers/net/phy/micrel.c
@@ -482,6 +482,31 @@ static struct phy_driver ksz9031_driver = {
.readext = _phy_extread,
 };
 
+int ksz886x_config(struct phy_device *phydev)
+{
+   /* we are connected directly to the switch without
+* dedicated PHY. */
+   phydev->link = 1;
+   phydev->duplex = DUPLEX_FULL;
+   phydev->speed = SPEED_100;
+   return 0;
+}
+
+static int ksz886x_startup(struct phy_device *phydev)
+{
+   return 0;
+}
+
+static struct phy_driver ksz886x_driver = {
+   .name = "Micrel KSZ886x Switch",
+   .uid  = 0x00221430,
+   .mask = 0xf0,
+   .features = PHY_BASIC_FEATURES,
+   .config = _config,
+   .startup = _startup,
+   .shutdown = _shutdown,
+};
+
 int phy_micrel_init(void)
 {
phy_register(_driver);
@@ -495,5 +520,6 @@ int phy_micrel_init(void)
 #endif
phy_register(_driver);
phy_register(_driver);
+   phy_register(_driver);
return 0;
 }
-- 
1.9.1

___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Re: [U-Boot] Unaligned flush_dcache_range in axs101.c

[Vineet Gupta]

On Thursday 26 May 2016 05:09 PM, Alexey Brodkin wrote:

> In the code you were referring what I wanted to modify reset vector of the 
> slave core.
> And while we were living without IOC it was all OK. My code above wrote-back
> (or as we used to call it within ARC "flushed") L1 data cache with modified
> reset vector contents to L2 (which is combined data and instruction cache in 
> case of ARC)
> and once slave core was unhalted it read reset vector contents via instruction
> fetch hardware and executed right what I wanted.

I don't have the full context here, but I think for this specific case (writing
reset vector of other core), you don't need to invent a new interface. You can
just do an uncached store (ST.di) which will ensure that the data goes straight 
to
memory. You need to make sure that this line is not in other cores' caches L1
and/or L2 - which can probably be assumed if it's just coming out of reset.

-Vineet
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH v2 04/11] ARM: allocate extra space for PSCI stack in secure section during link phase

[Chen-Yu Tsai]

The PSCI implementation expects at most 2 pages worth of space reserved
at the end of the secure section for its stacks. If PSCI is relocated to
secure SRAM, then everything is fine. If no secure SRAM is available,
and PSCI remains in main memory, the reserved memory space doesn't cover
the space used by the stack.

If one accesses PSCI after Linux has fully booted, the memory that should
have been reserved for the PSCI stacks may have been used by the kernel
or userspace, and would be corrupted. Observed after effects include the
system hanging or telinit core dumping when trying to reboot. It seems
the init process gets hit the most on my test bed.

This fix allocates the space used by the PSCI stacks in the secure
section by skipping pages in the linker script, but only when there is
no secure SRAM, to avoid bloating the binary.

This fix is only a stop gap. It would be better to rework the stack
allocation mechanism, maybe with proper usage of CONFIG_ macros and an
explicit symbol.

Signed-off-by: Chen-Yu Tsai 

squash! ARM: allocate extra space for PSCI stack in secure section during link 
phase
---
 arch/arm/cpu/u-boot.lds | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm/cpu/u-boot.lds b/arch/arm/cpu/u-boot.lds
index cfab8b041234..0770f8c878d1 100644
--- a/arch/arm/cpu/u-boot.lds
+++ b/arch/arm/cpu/u-boot.lds
@@ -50,6 +50,7 @@ SECTIONS
 
 #ifndef CONFIG_ARMV7_SECURE_BASE
 #define CONFIG_ARMV7_SECURE_BASE
+#define __ARMV7_ALLOCATE_SECURE_STACK
 #endif
 
.__secure_start : {
@@ -67,6 +68,12 @@ SECTIONS
SIZEOF(.__secure_start) +
SIZEOF(.secure_text);
 
+#ifdef __ARMV7_ALLOCATE_SECURE_STACK
+   /* Align to page boundary and skip 2 pages */
+   . = (. & ~ 0xfff) + 0x2000;
+#undef __ARMV7_ALLOCATE_SECURE_STACK
+#endif
+
__secure_end_lma = .;
.__secure_end : AT(__secure_end_lma) {
*(.__secure_end)
-- 
2.8.1

___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH v2 03/11] ARM: PSCI: export common PSCI function declarations for C code

[Chen-Yu Tsai]

Some common PSCI functions are written in assembly, but it should be
possible to use them from C code.

Add function declarations for C code to consume.

Signed-off-by: Chen-Yu Tsai 
---
 arch/arm/include/asm/psci.h | 8 
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/include/asm/psci.h b/arch/arm/include/asm/psci.h
index 128a606444fe..8b245139cbdb 100644
--- a/arch/arm/include/asm/psci.h
+++ b/arch/arm/include/asm/psci.h
@@ -33,6 +33,14 @@
 #define ARM_PSCI_RET_DENIED(-3)
 
 #ifndef __ASSEMBLY__
+#include 
+#include 
+
+void psci_cpu_entry(void);
+u32 psci_get_cpu_id(void);
+u32 psci_get_cpu_stack_top(int cpu);
+void psci_cpu_off_common(void);
+
 int psci_update_dt(void *fdt);
 void psci_board_init(void);
 #endif /* ! __ASSEMBLY__ */
-- 
2.8.1

___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH v2 05/11] sunxi: Make CPUCFG_BASE macro names the same across families

[Chen-Yu Tsai]

Use SUNXI_CPUCFG_BASE across all families. This makes writing common
PSCI code easier.

Signed-off-by: Chen-Yu Tsai 
---
 arch/arm/cpu/armv7/sunxi/psci_sun6i.S   | 16 
 arch/arm/cpu/armv7/sunxi/psci_sun7i.S   |  8 
 arch/arm/include/asm/arch-sunxi/cpu_sun4i.h | 15 +--
 3 files changed, 25 insertions(+), 14 deletions(-)

diff --git a/arch/arm/cpu/armv7/sunxi/psci_sun6i.S 
b/arch/arm/cpu/armv7/sunxi/psci_sun6i.S
index 90b5bfd35947..9752550dea35 100644
--- a/arch/arm/cpu/armv7/sunxi/psci_sun6i.S
+++ b/arch/arm/cpu/armv7/sunxi/psci_sun6i.S
@@ -73,8 +73,8 @@ psci_fiq_enter:
lsr r9, r9, #10
and r9, r9, #0xf
 
-   movwr8, #(SUN6I_CPUCFG_BASE & 0x)
-   movtr8, #(SUN6I_CPUCFG_BASE >> 16)
+   movwr8, #(SUNXI_CPUCFG_BASE & 0x)
+   movtr8, #(SUNXI_CPUCFG_BASE >> 16)
 
@ Wait for the core to enter WFI
lsl r11, r9, #6 @ x64
@@ -114,8 +114,8 @@ psci_fiq_enter:
str r10, [r12, #0x140]
 #endif
 
-   movwr8, #(SUN6I_CPUCFG_BASE & 0x)
-   movtr8, #(SUN6I_CPUCFG_BASE >> 16)
+   movwr8, #(SUNXI_CPUCFG_BASE & 0x)
+   movtr8, #(SUNXI_CPUCFG_BASE >> 16)
 
@ Unlock CPU
ldr r10, [r8, #0x1e4]
@@ -139,8 +139,8 @@ psci_cpu_on:
str r2, [r0]@ store target PC at stack top
dsb
 
-   movwr0, #(SUN6I_CPUCFG_BASE & 0x)
-   movtr0, #(SUN6I_CPUCFG_BASE >> 16)
+   movwr0, #(SUNXI_CPUCFG_BASE & 0x)
+   movtr0, #(SUNXI_CPUCFG_BASE >> 16)
 
@ CPU mask
and r1, r1, #3  @ only care about first cluster
@@ -189,8 +189,8 @@ psci_cpu_on:
str r6, [r0, #0x100]
 
@ re-calculate CPU control register address
-   movwr0, #(SUN6I_CPUCFG_BASE & 0x)
-   movtr0, #(SUN6I_CPUCFG_BASE >> 16)
+   movwr0, #(SUNXI_CPUCFG_BASE & 0x)
+   movtr0, #(SUNXI_CPUCFG_BASE >> 16)
 
@ Deassert reset on target CPU
mov r6, #3
diff --git a/arch/arm/cpu/armv7/sunxi/psci_sun7i.S 
b/arch/arm/cpu/armv7/sunxi/psci_sun7i.S
index e15d587f2901..ac8ebf888a4a 100644
--- a/arch/arm/cpu/armv7/sunxi/psci_sun7i.S
+++ b/arch/arm/cpu/armv7/sunxi/psci_sun7i.S
@@ -73,8 +73,8 @@ psci_fiq_enter:
lsr r9, r9, #10
and r9, r9, #0xf
 
-   movwr8, #(SUN7I_CPUCFG_BASE & 0x)
-   movtr8, #(SUN7I_CPUCFG_BASE >> 16)
+   movwr8, #(SUNXI_CPUCFG_BASE & 0x)
+   movtr8, #(SUNXI_CPUCFG_BASE >> 16)
 
@ Wait for the core to enter WFI
lsl r11, r9, #6 @ x64
@@ -128,8 +128,8 @@ psci_cpu_on:
str r2, [r0]@ store target PC at stack top
dsb
 
-   movwr0, #(SUN7I_CPUCFG_BASE & 0x)
-   movtr0, #(SUN7I_CPUCFG_BASE >> 16)
+   movwr0, #(SUNXI_CPUCFG_BASE & 0x)
+   movtr0, #(SUNXI_CPUCFG_BASE >> 16)
 
@ CPU mask
and r1, r1, #3  @ only care about first cluster
diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h 
b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
index 65c0441fe8a2..47e327e71f84 100644
--- a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
+++ b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
@@ -18,6 +18,10 @@
 #define SUNXI_SRAM_D_BASE  0x0001  /* 4 kiB */
 #define SUNXI_SRAM_B_BASE  0x0002  /* 64 kiB (secure) */
 
+#ifdef CONFIG_MACH_SUN8I_A83T
+#define SUNXI_CPUCFG_BASE  0x0170
+#endif
+
 #define SUNXI_SRAMC_BASE   0x01c0
 #define SUNXI_DRAMC_BASE   0x01c01000
 #define SUNXI_DMA_BASE 0x01c02000
@@ -94,7 +98,10 @@
 
 #define SUNXI_TP_BASE  0x01c25000
 #define SUNXI_PMU_BASE 0x01c25400
-#define SUN7I_CPUCFG_BASE  0x01c25c00
+
+#ifdef CONFIG_MACH_SUN7I
+#define SUNXI_CPUCFG_BASE  0x01c25c00
+#endif
 
 #define SUNXI_UART0_BASE   0x01c28000
 #define SUNXI_UART1_BASE   0x01c28400
@@ -148,7 +155,11 @@
 
 #define SUNXI_RTC_BASE 0x01f0
 #define SUNXI_PRCM_BASE0x01f01400
-#define SUN6I_CPUCFG_BASE  0x01f01c00
+
+#if defined CONFIG_SUNXI_GEN_SUN6I && !defined CONFIG_MACH_SUN8I_A83T
+#define SUNXI_CPUCFG_BASE  0x01f01c00
+#endif
+
 #define SUNXI_R_TWI_BASE   0x01f02400
 #define SUNXI_R_UART_BASE  0x01f02800
 #define SUNXI_R_PIO_BASE   0x01f02c00
-- 
2.8.1

___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH v2 10/11] sunxi: Add base address for GIC

[Chen-Yu Tsai]

Instead of hardcoding the GIC addresses in the PSCI implementation,
provide a base address in the cpu header.

Signed-off-by: Chen-Yu Tsai 
---
 arch/arm/cpu/armv7/sunxi/psci_sun6i.S   | 4 ++--
 arch/arm/cpu/armv7/sunxi/psci_sun7i.S   | 4 ++--
 arch/arm/include/asm/arch-sunxi/cpu_sun4i.h | 2 ++
 3 files changed, 6 insertions(+), 4 deletions(-)

diff --git a/arch/arm/cpu/armv7/sunxi/psci_sun6i.S 
b/arch/arm/cpu/armv7/sunxi/psci_sun6i.S
index 9752550dea35..95fdb0e58874 100644
--- a/arch/arm/cpu/armv7/sunxi/psci_sun6i.S
+++ b/arch/arm/cpu/armv7/sunxi/psci_sun6i.S
@@ -42,8 +42,8 @@
 
 #defineONE_MS  (CONFIG_TIMER_CLK_FREQ / 1000)
 #defineTEN_MS  (10 * ONE_MS)
-#defineGICD_BASE   0x1c81000
-#defineGICC_BASE   0x1c82000
+#defineGICD_BASE   (SUNXI_GIC400_BASE +  0x1000)
+#defineGICC_BASE   (SUNXI_GIC400_BASE +  0x2000)
 
 .globl psci_fiq_enter
 psci_fiq_enter:
diff --git a/arch/arm/cpu/armv7/sunxi/psci_sun7i.S 
b/arch/arm/cpu/armv7/sunxi/psci_sun7i.S
index ac8ebf888a4a..87bbd725f0b3 100644
--- a/arch/arm/cpu/armv7/sunxi/psci_sun7i.S
+++ b/arch/arm/cpu/armv7/sunxi/psci_sun7i.S
@@ -42,8 +42,8 @@
 
 #defineONE_MS  (CONFIG_TIMER_CLK_FREQ / 1000)
 #defineTEN_MS  (10 * ONE_MS)
-#defineGICD_BASE   0x1c81000
-#defineGICC_BASE   0x1c82000
+#defineGICD_BASE   (SUNXI_GIC400_BASE +  0x1000)
+#defineGICC_BASE   (SUNXI_GIC400_BASE +  0x2000)
 
 .globl psci_fiq_enter
 psci_fiq_enter:
diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h 
b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
index 47e327e71f84..c5e9d88bab5c 100644
--- a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
+++ b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
@@ -143,6 +143,8 @@
 #define SUNXI_DRAM_PHY0_BASE   0x01c65000
 #define SUNXI_DRAM_PHY1_BASE   0x01c66000
 
+#define SUNXI_GIC400_BASE  0x01c8
+
 /* module sram */
 #define SUNXI_SRAM_C_BASE  0x01d0
 
-- 
2.8.1

___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH v2 07/11] sunxi: Add missing linux/types.h header for cpucfg_sun6i.h

[Chen-Yu Tsai]

cpucfg_sun6i.h includes a register definition for the CPUCFG register
block. The types used are u32 and u8, which are defined in linux/types.h.

Signed-off-by: Chen-Yu Tsai 
---
 arch/arm/include/asm/arch-sunxi/cpucfg_sun6i.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/include/asm/arch-sunxi/cpucfg_sun6i.h 
b/arch/arm/include/asm/arch-sunxi/cpucfg_sun6i.h
index e2a29cb1818e..6885a972ce0b 100644
--- a/arch/arm/include/asm/arch-sunxi/cpucfg_sun6i.h
+++ b/arch/arm/include/asm/arch-sunxi/cpucfg_sun6i.h
@@ -9,6 +9,8 @@
 #ifndef _SUNXI_CPUCFG_H
 #define _SUNXI_CPUCFG_H
 
+#include 
+
 #ifndef __ASSEMBLY__
 
 struct sunxi_cpucfg_reg {
-- 
2.8.1

___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH v2 11/11] sunxi: Add PSCI implementation in C

[Chen-Yu Tsai]

To make the PSCI backend more maintainable and easier to port to newer
SoCs, rewrite the current PSCI implementation in C.

Some inline assembly bits are required to access coprocessor registers.
PSCI stack setup is the only part left completely in assembly. In theory
this part could be split out of psci_arch_init into a separate common
function, and psci_arch_init could be completely in C.

Signed-off-by: Chen-Yu Tsai 
---
 arch/arm/cpu/armv7/sunxi/Makefile |   7 +-
 arch/arm/cpu/armv7/sunxi/psci.c   | 269 ++
 arch/arm/cpu/armv7/sunxi/psci_head.S  |  66 +
 arch/arm/cpu/armv7/sunxi/psci_sun6i.S | 262 -
 arch/arm/cpu/armv7/sunxi/psci_sun7i.S | 237 --
 5 files changed, 337 insertions(+), 504 deletions(-)
 create mode 100644 arch/arm/cpu/armv7/sunxi/psci.c
 create mode 100644 arch/arm/cpu/armv7/sunxi/psci_head.S
 delete mode 100644 arch/arm/cpu/armv7/sunxi/psci_sun6i.S
 delete mode 100644 arch/arm/cpu/armv7/sunxi/psci_sun7i.S

diff --git a/arch/arm/cpu/armv7/sunxi/Makefile 
b/arch/arm/cpu/armv7/sunxi/Makefile
index 4d2274a38ed1..c2085101685b 100644
--- a/arch/arm/cpu/armv7/sunxi/Makefile
+++ b/arch/arm/cpu/armv7/sunxi/Makefile
@@ -13,11 +13,8 @@ obj-$(CONFIG_MACH_SUN6I) += tzpc.o
 obj-$(CONFIG_MACH_SUN8I_H3)+= tzpc.o
 
 ifndef CONFIG_SPL_BUILD
-ifdef CONFIG_ARMV7_PSCI
-obj-$(CONFIG_MACH_SUN6I)   += psci_sun6i.o
-obj-$(CONFIG_MACH_SUN7I)   += psci_sun7i.o
-obj-$(CONFIG_MACH_SUN8I)   += psci_sun6i.o
-endif
+obj-$(CONFIG_ARMV7_PSCI)   += psci.o
+obj-$(CONFIG_ARMV7_PSCI)   += psci_head.o
 endif
 
 ifdef CONFIG_SPL_BUILD
diff --git a/arch/arm/cpu/armv7/sunxi/psci.c b/arch/arm/cpu/armv7/sunxi/psci.c
new file mode 100644
index ..f0c151a349c8
--- /dev/null
+++ b/arch/arm/cpu/armv7/sunxi/psci.c
@@ -0,0 +1,269 @@
+/*
+ * Copyright (C) 2016
+ * Author: Chen-Yu Tsai 
+ *
+ * Based on assembly code by Marc Zyngier ,
+ * which was based on code by Carl van Schaik .
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+#include 
+#include 
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+
+#define __secure   __attribute__ ((section ("._secure.text")))
+#define __irq  __attribute__ ((interrupt ("IRQ")))
+
+#defineGICD_BASE   (SUNXI_GIC400_BASE + GIC_DIST_OFFSET)
+#defineGICC_BASE   (SUNXI_GIC400_BASE + GIC_CPU_OFFSET_A15)
+
+static void cp15_write_cntp_tval(u32 tval)
+{
+   asm volatile ("mcr p15, 0, %0, c14, c2, 0" : : "r" (tval));
+}
+
+static void cp15_write_cntp_ctl(u32 val)
+{
+   asm volatile ("mcr p15, 0, %0, c14, c2, 1" : : "r" (val));
+}
+
+static u32 cp15_read_cntp_ctl(void)
+{
+   u32 val;
+
+   asm volatile ("mrc p15, 0, %0, c14, c2, 1" : "=r" (val));
+
+   return val;
+}
+
+static void __secure __mdelay(u32 ms)
+{
+   u32 reg = DIV_ROUND_UP(CONFIG_TIMER_CLK_FREQ, ms);
+
+   cp15_write_cntp_tval(reg);
+   ISB;
+   cp15_write_cntp_ctl(3);
+
+   do {
+   ISB;
+   reg = cp15_read_cntp_ctl();
+   } while (!(reg & BIT(2)));
+
+   cp15_write_cntp_ctl(0);
+}
+
+#ifdef CONFIG_MACH_SUN7I
+/* sun7i (A20) is different from other single cluster SoCs */
+static void sunxi_cpu_set_power(int __always_unused cpu, bool on)
+{
+   struct sunxi_cpucfg_reg *cpucfg =
+   (struct sunxi_cpucfg_reg *)SUNXI_CPUCFG_BASE;
+
+   if (on) {
+   /* Release power clamp */
+   u32 tmp = 0x1ff;
+   do {
+   tmp >>= 1;
+   writel(tmp, >cpu1_pwr_clamp);
+   } while (tmp);
+
+   __mdelay(10);
+
+   /* Clear power gating */
+   clrbits_le32(>cpu1_pwroff, BIT(0));
+   } else {
+   /* Set power gating */
+   setbits_le32(>cpu1_pwroff, BIT(0));
+
+   /* Activate power clamp */
+   writel(0xff, >cpu1_pwr_clamp);
+   }
+}
+#else /* ! CONFIG_MACH_SUN7I */
+static void sunxi_cpu_set_power(int cpu, bool on)
+{
+   struct sunxi_prcm_reg *prcm =
+   (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
+
+   if (on) {
+#if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN8I_H3)
+   /* Release power clamp (A31 & H3 only) */
+   u32 tmp = 0x1ff;
+   do {
+   tmp >>= 1;
+   writel(tmp, >cpu_pwr_clamp[cpu]);
+   } while (tmp);
+#endif
+
+   __mdelay(10);
+
+   /* Clear power gating */
+   clrbits_le32(>cpu_pwroff, BIT(cpu));
+   } else {
+   /* Set power gating */
+   setbits_le32(>cpu_pwroff, BIT(cpu));
+
+#if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN8I_H3)
+   /* Activate power clamp (A31 & H3 only) */
+

[U-Boot] [PATCH v2 08/11] sunxi: Group cpu core related controls together

[Chen-Yu Tsai]

Instead of listing individual registers for controls to each processor
core, list them as an array of registers. This makes accessing controls
by core index easier.

Also rename "cpucfg_sun6i.h" (which was unused anyway) to the more generic
"cpucfg.h", and add packed attribute to struct sunxi_cpucfg.

Signed-off-by: Chen-Yu Tsai 
---
 .../asm/arch-sunxi/{cpucfg_sun6i.h => cpucfg.h}| 34 +-
 arch/arm/include/asm/arch-sunxi/prcm.h |  6 ++--
 2 files changed, 16 insertions(+), 24 deletions(-)
 rename arch/arm/include/asm/arch-sunxi/{cpucfg_sun6i.h => cpucfg.h} (68%)

diff --git a/arch/arm/include/asm/arch-sunxi/cpucfg_sun6i.h 
b/arch/arm/include/asm/arch-sunxi/cpucfg.h
similarity index 68%
rename from arch/arm/include/asm/arch-sunxi/cpucfg_sun6i.h
rename to arch/arm/include/asm/arch-sunxi/cpucfg.h
index 6885a972ce0b..f6d2f21d9d24 100644
--- a/arch/arm/include/asm/arch-sunxi/cpucfg_sun6i.h
+++ b/arch/arm/include/asm/arch-sunxi/cpucfg.h
@@ -9,37 +9,31 @@
 #ifndef _SUNXI_CPUCFG_H
 #define _SUNXI_CPUCFG_H
 
+#include 
 #include 
 
 #ifndef __ASSEMBLY__
 
-struct sunxi_cpucfg_reg {
+struct __packed sunxi_cpucfg_cpu {
+   u32 rst;/* base + 0x0 */
+   u32 ctrl;   /* base + 0x4 */
+   u32 status; /* base + 0x8 */
+   u8 res[0x34];   /* base + 0xc */
+};
+
+struct __packed sunxi_cpucfg_reg {
u8 res0[0x40];  /* 0x000 */
-   u32 cpu0_rst;   /* 0x040 */
-   u32 cpu0_ctrl;  /* 0x044 */
-   u32 cpu0_status;/* 0x048 */
-   u8 res1[0x34];  /* 0x04c */
-   u32 cpu1_rst;   /* 0x080 */
-   u32 cpu1_ctrl;  /* 0x084 */
-   u32 cpu1_status;/* 0x088 */
-   u8 res2[0x34];  /* 0x08c */
-   u32 cpu2_rst;   /* 0x0c0 */
-   u32 cpu2_ctrl;  /* 0x0c4 */
-   u32 cpu2_status;/* 0x0c8 */
-   u8 res3[0x34];  /* 0x0cc */
-   u32 cpu3_rst;   /* 0x100 */
-   u32 cpu3_ctrl;  /* 0x104 */
-   u32 cpu3_status;/* 0x108 */
-   u8 res4[0x78];  /* 0x10c */
+   struct sunxi_cpucfg_cpu cpu[4]; /* 0x040 */
+   u8 res1[0x44];  /* 0x140 */
u32 gen_ctrl;   /* 0x184 */
u32 l2_status;  /* 0x188 */
-   u8 res5[0x4];   /* 0x18c */
+   u8 res2[0x4];   /* 0x18c */
u32 event_in;   /* 0x190 */
-   u8 res6[0xc];   /* 0x194 */
+   u8 res3[0xc];   /* 0x194 */
u32 super_standy_flag;  /* 0x1a0 */
u32 priv0;  /* 0x1a4 */
u32 priv1;  /* 0x1a8 */
-   u8 res7[0x54];  /* 0x1ac */
+   u8 res4[0x54];  /* 0x1ac */
u32 idle_cnt0_low;  /* 0x200 */
u32 idle_cnt0_high; /* 0x204 */
u32 idle_cnt0_ctrl; /* 0x208 */
diff --git a/arch/arm/include/asm/arch-sunxi/prcm.h 
b/arch/arm/include/asm/arch-sunxi/prcm.h
index 34e01e825df2..ae3880b13bdf 100644
--- a/arch/arm/include/asm/arch-sunxi/prcm.h
+++ b/arch/arm/include/asm/arch-sunxi/prcm.h
@@ -227,10 +227,8 @@ struct __packed sunxi_prcm_reg {
u32 gpu_pwroff; /* 0x118 */
u8 res9[0x4];   /* 0x11c */
u32 vdd_pwr_reset;  /* 0x120 */
-   u8 res10[0x20]; /* 0x124 */
-   u32 cpu1_pwr_clamp; /* 0x144 */
-   u32 cpu2_pwr_clamp; /* 0x148 */
-   u32 cpu3_pwr_clamp; /* 0x14c */
+   u8 res10[0x1c]; /* 0x124 */
+   u32 cpu_pwr_clamp[4];   /* 0x140 but first one is actually unused */
u8 res11[0x30]; /* 0x150 */
u32 dram_pwr;   /* 0x180 */
u8 res12[0xc];  /* 0x184 */
-- 
2.8.1

___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH v2 09/11] sunxi: Add CPUCFG debug lock and sun7i cpu power controls

[Chen-Yu Tsai]

CPUCFG has an unlisted debug control register, which is used to disable
external debug access.

Also, sun7i secondary core power controls are in CPUCFG, as there's no
separate PRCM block.

Signed-off-by: Chen-Yu Tsai 
---
 arch/arm/include/asm/arch-sunxi/cpucfg.h | 7 ++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/arch/arm/include/asm/arch-sunxi/cpucfg.h 
b/arch/arm/include/asm/arch-sunxi/cpucfg.h
index f6d2f21d9d24..297cdd28c060 100644
--- a/arch/arm/include/asm/arch-sunxi/cpucfg.h
+++ b/arch/arm/include/asm/arch-sunxi/cpucfg.h
@@ -33,7 +33,12 @@ struct __packed sunxi_cpucfg_reg {
u32 super_standy_flag;  /* 0x1a0 */
u32 priv0;  /* 0x1a4 */
u32 priv1;  /* 0x1a8 */
-   u8 res4[0x54];  /* 0x1ac */
+   u8 res4[0x4];   /* 0x1ac */
+   u32 cpu1_pwr_clamp; /* 0x1b0 sun7i only */
+   u32 cpu1_pwroff;/* 0x1b4 sun7i only */
+   u8 res5[0x2c];  /* 0x1b8 */
+   u32 dbg_ctrl1;  /* 0x1e4 */
+   u8 res6[0x18];  /* 0x1e8 */
u32 idle_cnt0_low;  /* 0x200 */
u32 idle_cnt0_high; /* 0x204 */
u32 idle_cnt0_ctrl; /* 0x208 */
-- 
2.8.1

___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH v2 06/11] sunxi: Add packed attribute to struct sunxi_prcm_reg

[Chen-Yu Tsai]

struct sunxi_prcm_reg is a representation of the PRCM registers. Add
the packed attribute to prevent the compiler from doing funny things.

Signed-off-by: Chen-Yu Tsai 
---
 arch/arm/include/asm/arch-sunxi/prcm.h | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/arch/arm/include/asm/arch-sunxi/prcm.h 
b/arch/arm/include/asm/arch-sunxi/prcm.h
index 556c1af60058..34e01e825df2 100644
--- a/arch/arm/include/asm/arch-sunxi/prcm.h
+++ b/arch/arm/include/asm/arch-sunxi/prcm.h
@@ -197,7 +197,9 @@
 #define PRCM_CPU3_PWR_CLAMP_MASK PRCM_CPU3_PWR_CLAMP(0xff)
 
 #ifndef __ASSEMBLY__
-struct sunxi_prcm_reg {
+#include 
+
+struct __packed sunxi_prcm_reg {
u32 cpus_cfg;   /* 0x000 */
u8 res0[0x8];   /* 0x004 */
u32 apb0_ratio; /* 0x00c */
-- 
2.8.1

___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH v2 00/11] sunxi: PSCI implementation rewrite in C

[Chen-Yu Tsai]

Hi everyone,

This series rewrites the Allwinner/sunxi PSCI implementation in C, to make
it easier to maintain and extend for the currently unsupported multi-cluster
SoCs. The SMP code in the BSP kernels are in C. Having the PSCI code in C
as well will make it easier to work on.

To be able to convert the platform bits to C, some common PSCI functions
have to be fixed up according to the ARM calling conventions. Function
declarations are also needed.

This series is based on sunxi/next. Parts of it will likely conflict with
the effort to support PSCI 1.0 on the Freescale LS102xA.

Changes since v1:

  - Add and use helpers for accessing co-processors.

  - Split out power gating/clamping into helpers based on sun7i and the rest.

  - Drop secure section attribute on PSCI common function declarations.

  - Add packed attribute to PRCM and CPUCFG register struct definitions.

  - Only allocate PSCI stack space when PSCI is put in main memory.

  - Make it clear that PSCI stack overwriting normal memory only happens
when PSCI is put in main memory.

  - Drop "cc" from clobber list.

  - Add comments explaining the need to preserve registers across
psci_arch_init, and preserve r0 instead of setting it to 0.

Patch 1 fixes up psci_get_cpu_stack_top.

Patch 2 fixes up the PSCI version of v7_flush_dcache_all.

Patch 3 adds function declarations for some of the common PSCI functions.

Patch 4 fixes issues with reserving memory for the secure section.

Patch 5 unifies the CPUCFG_BASE macro names for various sunxi platforms.

Patch 6 adds packed attribute to struct sunxi_prcm_reg.

Patch 7 adds a missing header to cpucfg.h

Patch 8 groups cpu core related controls together into one struct per core.
This makes it straightforward to access the controls by the cpu index.

Patch 9 adds some missing fields to cpucfg, which were used in the assembly
code.

Patch 10 adds the base address for the GIC.

Patch 11 is the new PSCI implementation in C. Almost all of the code is
converted, with the exception of initial setup of the stack.


Regards
ChenYu


Chen-Yu Tsai (11):
  ARM: PSCI: use only r0 and r3 in psci_get_cpu_stack_top()
  ARM: PSCI: save and restore clobbered registers in v7_flush_dcache_all
  ARM: PSCI: export common PSCI function declarations for C code
  ARM: allocate extra space for PSCI stack in secure section during link
phase
  sunxi: Make CPUCFG_BASE macro names the same across families
  sunxi: Add packed attribute to struct sunxi_prcm_reg
  sunxi: Add missing linux/types.h header for cpucfg_sun6i.h
  sunxi: Group cpu core related controls together
  sunxi: Add CPUCFG debug lock and sun7i cpu power controls
  sunxi: Add base address for GIC
  sunxi: Add PSCI implementation in C

 arch/arm/cpu/armv7/psci.S  |  20 +-
 arch/arm/cpu/armv7/sunxi/Makefile  |   7 +-
 arch/arm/cpu/armv7/sunxi/psci.c| 269 +
 arch/arm/cpu/armv7/sunxi/psci_head.S   |  66 +
 arch/arm/cpu/armv7/sunxi/psci_sun6i.S  | 262 
 arch/arm/cpu/armv7/sunxi/psci_sun7i.S  | 237 --
 arch/arm/cpu/u-boot.lds|   7 +
 arch/arm/include/asm/arch-sunxi/cpu_sun4i.h|  17 +-
 .../asm/arch-sunxi/{cpucfg_sun6i.h => cpucfg.h}|  41 ++--
 arch/arm/include/asm/arch-sunxi/prcm.h |  10 +-
 arch/arm/include/asm/psci.h|   8 +
 11 files changed, 404 insertions(+), 540 deletions(-)
 create mode 100644 arch/arm/cpu/armv7/sunxi/psci.c
 create mode 100644 arch/arm/cpu/armv7/sunxi/psci_head.S
 delete mode 100644 arch/arm/cpu/armv7/sunxi/psci_sun6i.S
 delete mode 100644 arch/arm/cpu/armv7/sunxi/psci_sun7i.S
 rename arch/arm/include/asm/arch-sunxi/{cpucfg_sun6i.h => cpucfg.h} (67%)

-- 
2.8.1

___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH v2 01/11] ARM: PSCI: use only r0 and r3 in psci_get_cpu_stack_top()

[Chen-Yu Tsai]

For psci_get_cpu_stack_top() to be usable in C code, it must adhere to
the ARM calling conventions. Since it could be called when the stack
is still unavailable, and the entry code to linux also expects r1 and
r2 to remain unchanged, stick to r0 and r3.

Signed-off-by: Chen-Yu Tsai 
---
 arch/arm/cpu/armv7/psci.S | 18 +-
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/arch/arm/cpu/armv7/psci.S b/arch/arm/cpu/armv7/psci.S
index 87c0c0b6f5eb..cdd001fe3fb0 100644
--- a/arch/arm/cpu/armv7/psci.S
+++ b/arch/arm/cpu/armv7/psci.S
@@ -196,15 +196,15 @@ ENDPROC(psci_cpu_off_common)
 
 @ expects CPU ID in r0 and returns stack top in r0
 ENTRY(psci_get_cpu_stack_top)
-   mov r5, #0x400  @ 1kB of stack per CPU
-   mul r0, r0, r5
-
-   ldr r5, =psci_text_end  @ end of monitor text
-   add r5, r5, #0x2000 @ Skip two pages
-   lsr r5, r5, #12 @ Align to start of page
-   lsl r5, r5, #12
-   sub r5, r5, #4  @ reserve 1 word for target PC
-   sub r0, r5, r0  @ here's our stack!
+   mov r3, #0x400  @ 1kB of stack per CPU
+   mul r0, r0, r3
+
+   ldr r3, =psci_text_end  @ end of monitor text
+   add r3, r3, #0x2000 @ Skip two pages
+   lsr r3, r3, #12 @ Align to start of page
+   lsl r3, r3, #12
+   sub r3, r3, #4  @ reserve 1 word for target PC
+   sub r0, r3, r0  @ here's our stack!
 
bx  lr
 ENDPROC(psci_get_cpu_stack_top)
-- 
2.8.1

___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH v2 02/11] ARM: PSCI: save and restore clobbered registers in v7_flush_dcache_all

[Chen-Yu Tsai]

Signed-off-by: Chen-Yu Tsai 
---
 arch/arm/cpu/armv7/psci.S | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/cpu/armv7/psci.S b/arch/arm/cpu/armv7/psci.S
index cdd001fe3fb0..ab408378fcae 100644
--- a/arch/arm/cpu/armv7/psci.S
+++ b/arch/arm/cpu/armv7/psci.S
@@ -110,6 +110,7 @@ ENDPROC(psci_get_cpu_id)
 
 /* Imported from Linux kernel */
 LENTRY(v7_flush_dcache_all)
+   stmfd   sp!, {r4-r5, r7, r9-r11, lr}
dmb @ ensure ordering with previous 
memory accesses
mrc p15, 1, r0, c0, c0, 1   @ read clidr
andsr3, r0, #0x700  @ extract loc from clidr
@@ -153,6 +154,7 @@ finished:
mcr p15, 2, r10, c0, c0, 0  @ select current cache level in 
cssr
dsb st
isb
+   ldmfd   sp!, {r4-r5, r7, r9-r11, lr}
bx  lr
 ENDPROC(v7_flush_dcache_all)
 
-- 
2.8.1

___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Re: [U-Boot] [PATCH] serial: 16550: Add JZ47xx support

[Paul Burton]

On Thu, May 26, 2016 at 02:05:07PM +0200, Marek Vasut wrote:
> > Interesting :) May I ask which platform/SoC you're working with? Have
> > you seen the (unfortunately currently out of tree) port we did for the
> > JZ4780-based Ci20? I recall the pain of squeezing SPL down to a small
> > enough size well...
> 
> I bought the CI20, yeah. I started with that tree and am now getting it
> into mainline shape. I actually managed to optimize the SPL, so it does
> not overflow. One of the things which helped a lot was removing slop[1]
> from the structures and using appropriate data types in them (like don't
> use u32 to store an 8bit number). I also tinified the MMC stack, so that
> it won't pull in too much useless code.
> 
> At this point, I have a u-boot running from SD card and the SD driver in
> full U-Boot is already probing from DT and using DM. I sent Daniel the
> updated patches, but they are still work in progress. Nonetheless, if
> you want me forward that to you as well, let me know.
> 
> I plan to get this CI20 submitted at some point this or next week, so it
> can land in 2016.07 (I hope!) and then debian and fedora-mips (and other
> distros) can pick it up and package proper. That's how I see it.

That sounds great :) I'd be interested in seeing them but probably won't
have any time to look at them for a few weeks anyway (busy with other
work things & then getting married & going off on honeymoon!). So
hopefully by the time I'd get round to having a look they'll be in
mainline :)

> btw. what is the linux support status of the ci20 ? Is anyone working
> on that? I saw the DTS in Linux, but it's pretty bare-bones.

Yeah the support in mainline Linux is a bit basic at the moment. The
biggest holdup is pinctrl support which I need to do some work on - the
DT bindings are more complicated than they need to be, and the driver
should probably be made more generic to cover other Ingenic SoCs before
it goes into mainline.

> btw2. can I get the ci40 anywhere or is that just unobtainium board ?

I'll email you separately about that.

Thanks,
Paul
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Re: [U-Boot] [PATCH 2/4] MIPS: Fix _ACAST32_ for pointers on MIPS64

[Paul Burton]

On Thu, May 26, 2016 at 01:18:21AM +0200, Daniel Schwierzeck wrote:
> 
> 
> Am 17.05.2016 um 12:56 schrieb Paul Burton:
> > When building for MIPS64 and providing a pointer to _ACAST32_,
> > optionally via CPHYSADDR or one of the CKSEGxADDR macros, the cast
> > directly to a 32 bit int leads to compilation warnings such as the
> > following:
> > 
> >   In file included from ./arch/mips/include/asm/io.h:17:0,
> >from drivers/net/pcnet.c:14:
> >   drivers/net/pcnet.c: In function ‘pcnet_virt_to_mem’:
> >   ./arch/mips/include/asm/addrspace.h:39:29: warning: cast from pointer to 
> > integer of different size [-Wpointer-to-int-cast]
> >#define _ACAST32_  (_ATYPE_)(_ATYPE32_) /* widen if necessary */
> >^
> >   ./arch/mips/include/asm/addrspace.h:51:25: note: in expansion of macro 
> > ‘_ACAST32_’
> >#define CPHYSADDR(a)  ((_ACAST32_(a)) & 0x1fff)
> >^
> >   ./arch/mips/include/asm/addrspace.h:71:25: note: in expansion of macro 
> > ‘CPHYSADDR’
> >#define CKSEG0ADDR(a)  (CPHYSADDR(a) | CKSEG0)
> >^
> >   drivers/net/pcnet.c:144:23: note: in expansion of macro ‘CKSEG0ADDR’
> >  virt_addr = (void *)CKSEG0ADDR(addr);
> >  ^
> > 
> > Fix this by first casting provided values to a pointer-width integer,
> > then truncating to a 32 bit int & widening back to pointer-width.
> > 
> > Signed-off-by: Paul Burton 
> > ---
> > 
> >  arch/mips/include/asm/addrspace.h | 4 ++--
> >  1 file changed, 2 insertions(+), 2 deletions(-)
> > 
> > diff --git a/arch/mips/include/asm/addrspace.h 
> > b/arch/mips/include/asm/addrspace.h
> > index 0994e96..fe497b5 100644
> > --- a/arch/mips/include/asm/addrspace.h
> > +++ b/arch/mips/include/asm/addrspace.h
> > @@ -36,8 +36,8 @@
> >  #define _ACAST32_
> >  #define _ACAST64_
> >  #else
> > -#define _ACAST32_  (_ATYPE_)(_ATYPE32_)/* widen if necessary */
> > -#define _ACAST64_  (_ATYPE64_) /* do _not_ narrow */
> > +#define _ACAST32_  (_ATYPE_)(_ATYPE32_)(_ATYPE_)   /* widen if necessary */
> > +#define _ACAST64_  (_ATYPE64_) /* do _not_ narrow */
> >  #endif
> >  
> >  /*
> > 
> 
> could you fix this in the pcnet driver? If possible I want to avoid
> U-Boot specific changes on files imported from Linux.
> 
> -- 
> - Daniel
> 

Hi Daniel,

I've submitted an alternate fix in v2 of the series just now. It still
requires a change to MIPS code but it mirrors one I have submitted to
Linux, and hopefully one you'll find acceptable. It makes MIPS32 &
MIPS64 more consistent & prevents drivers needing to care about which
segment of the virtual address space an address is in when calling
virt_to_phys.

Thanks,
Paul
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH v2 4/4] malta: Allow MIPS64 builds

[Paul Burton]

Both real Malta boards & emulators that mimic Malta (eg. QEMU) can
support MIPS64 CPUs. Allow MIPS64 builds of U-Boot for such boards,
which enables the user to make use of the whole 64 bit address space.

Signed-off-by: Paul Burton 
---

Changes in v2: None

 arch/mips/Kconfig  |  3 +++
 board/imgtec/malta/Kconfig |  3 ++-
 board/imgtec/malta/lowlevel_init.S | 13 +++--
 include/configs/malta.h| 18 +-
 4 files changed, 25 insertions(+), 12 deletions(-)

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 53363e3..abaeaf0 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -33,6 +33,9 @@ config TARGET_MALTA
select SUPPORTS_CPU_MIPS32_R1
select SUPPORTS_CPU_MIPS32_R2
select SUPPORTS_CPU_MIPS32_R6
+   select SUPPORTS_CPU_MIPS64_R1
+   select SUPPORTS_CPU_MIPS64_R2
+   select SUPPORTS_CPU_MIPS64_R6
select SWAP_IO_SPACE
select MIPS_L1_CACHE_SHIFT_6
 
diff --git a/board/imgtec/malta/Kconfig b/board/imgtec/malta/Kconfig
index 2bb8e8b..98eb4d1 100644
--- a/board/imgtec/malta/Kconfig
+++ b/board/imgtec/malta/Kconfig
@@ -10,6 +10,7 @@ config SYS_CONFIG_NAME
default "malta"
 
 config SYS_TEXT_BASE
-   default 0xbe00
+   default 0xbe00 if 32BIT
+   default 0xbe00 if 64BIT
 
 endif
diff --git a/board/imgtec/malta/lowlevel_init.S 
b/board/imgtec/malta/lowlevel_init.S
index 534db1d..3d48cdc 100644
--- a/board/imgtec/malta/lowlevel_init.S
+++ b/board/imgtec/malta/lowlevel_init.S
@@ -10,6 +10,7 @@
 #include 
 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -34,7 +35,7 @@ lowlevel_init:
mtc0t0, CP0_CONFIG, 2
 
/* detect the core card */
-   li  t0, KSEG1ADDR(MALTA_REVISION)
+   PTR_LI  t0, CKSEG1ADDR(MALTA_REVISION)
lw  t0, 0(t0)
srl t0, t0, MALTA_REVISION_CORID_SHF
andit0, t0, (MALTA_REVISION_CORID_MSK >> \
@@ -68,12 +69,12 @@ lowlevel_init:
 */
 _gt64120:
/* move GT64120 registers from 0x1400 to 0x1be0 */
-   li  t1, KSEG1ADDR(GT_DEF_BASE)
+   PTR_LI  t1, CKSEG1ADDR(GT_DEF_BASE)
li  t0, CPU_TO_GT32(0xdf00)
sw  t0, GT_ISD_OFS(t1)
 
/* setup MEM-to-PCI0 mapping */
-   li  t1, KSEG1ADDR(MALTA_GT_BASE)
+   PTR_LI  t1, CKSEG1ADDR(MALTA_GT_BASE)
 
/* setup PCI0 io window to 0x1800-0x181f */
li  t0, CPU_TO_GT32(0xc000)
@@ -100,7 +101,7 @@ _gt64120:
 */
 _msc01:
/* setup peripheral bus controller clock divide */
-   li  t0, KSEG1ADDR(MALTA_MSC01_PBC_BASE)
+   PTR_LI  t0, CKSEG1ADDR(MALTA_MSC01_PBC_BASE)
li  t1, 0x1 << MSC01_PBC_CLKCFG_SHF
sw  t1, MSC01_PBC_CLKCFG_OFS(t0)
 
@@ -122,7 +123,7 @@ _msc01:
sw  t1, MSC01_PBC_CS0CFG_OFS(t0)
 
/* setup basic address decode */
-   li  t0, KSEG1ADDR(MALTA_MSC01_BIU_BASE)
+   PTR_LI  t0, CKSEG1ADDR(MALTA_MSC01_BIU_BASE)
li  t1, 0x0
li  t2, -CONFIG_SYS_MEM_SIZE
sw  t1, MSC01_BIU_MCBAS1L_OFS(t0)
@@ -157,7 +158,7 @@ _msc01:
sw  t2, MSC01_BIU_IP3MSK2L_OFS(t0)
 
/* setup PCI memory */
-   li  t0, KSEG1ADDR(MALTA_MSC01_PCI_BASE)
+   PTR_LI  t0, CKSEG1ADDR(MALTA_MSC01_PCI_BASE)
li  t1, MALTA_MSC01_PCIMEM_BASE
li  t2, (-MALTA_MSC01_PCIMEM_SIZE) & MSC01_PCI_SC2PMMSKL_MSK_MSK
li  t3, MALTA_MSC01_PCIMEM_MAP
diff --git a/include/configs/malta.h b/include/configs/malta.h
index a369678..fc4baba 100644
--- a/include/configs/malta.h
+++ b/include/configs/malta.h
@@ -39,14 +39,18 @@
  */
 #define CONFIG_SYS_MONITOR_BASECONFIG_SYS_TEXT_BASE
 
-#define CONFIG_SYS_SDRAM_BASE  0x8000 /* Cached addr */
+#ifdef CONFIG_64BIT
+# define CONFIG_SYS_SDRAM_BASE 0x8000
+#else
+# define CONFIG_SYS_SDRAM_BASE 0x8000
+#endif
 #define CONFIG_SYS_MEM_SIZE(256 * 1024 * 1024)
 
 #define CONFIG_SYS_INIT_SP_OFFSET  0x40
 
-#define CONFIG_SYS_LOAD_ADDR   0x8100
-#define CONFIG_SYS_MEMTEST_START   0x8010
-#define CONFIG_SYS_MEMTEST_END 0x8080
+#define CONFIG_SYS_LOAD_ADDR   (CONFIG_SYS_SDRAM_BASE + 0x0100)
+#define CONFIG_SYS_MEMTEST_START   (CONFIG_SYS_SDRAM_BASE + 0x0010)
+#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x0080)
 
 #define CONFIG_SYS_MALLOC_LEN  (128 * 1024)
 #define CONFIG_SYS_BOOTPARAMS_LEN  (128 * 1024)
@@ -69,7 +73,11 @@
 /*
  * Flash configuration
  */
-#define CONFIG_SYS_FLASH_BASE  0xbe00
+#ifdef CONFIG_64BIT
+# define CONFIG_SYS_FLASH_BASE 0xbe00
+#else
+# define CONFIG_SYS_FLASH_BASE 0xbe00
+#endif
 #define CONFIG_SYS_MAX_FLASH_BANKS 1
 #define CONFIG_SYS_MAX_FLASH_SECT  128
 #define CONFIG_SYS_FLASH_CFI
-- 
2.8.3

[U-Boot] [PATCH v2 3/4] net: pcnet: Make 64 bit safe

[Paul Burton]

Fix the pcnet driver to build safely on 64 bit platforms, in preparation
for allowing MIPS64 builds for Malta boards.

Signed-off-by: Paul Burton 
---

Changes in v2: None

 drivers/net/pcnet.c | 18 ++
 1 file changed, 10 insertions(+), 8 deletions(-)

diff --git a/drivers/net/pcnet.c b/drivers/net/pcnet.c
index efa4afb..d1fd4e4 100644
--- a/drivers/net/pcnet.c
+++ b/drivers/net/pcnet.c
@@ -137,7 +137,7 @@ static int pcnet_probe (struct eth_device *dev, bd_t * bis, 
int dev_num);
 static inline pci_addr_t pcnet_virt_to_mem(const struct eth_device *dev,
void *addr)
 {
-   pci_dev_t devbusfn = (pci_dev_t)dev->priv;
+   pci_dev_t devbusfn = (pci_dev_t)(unsigned long)dev->priv;
void *virt_addr = addr;
 
return pci_virt_to_mem(devbusfn, virt_addr);
@@ -176,7 +176,7 @@ int pcnet_initialize(bd_t *bis)
break;
}
memset(dev, 0, sizeof(*dev));
-   dev->priv = (void *)devbusfn;
+   dev->priv = (void *)(unsigned long)devbusfn;
sprintf(dev->name, "pcnet#%d", dev_nr);
 
/*
@@ -187,8 +187,8 @@ int pcnet_initialize(bd_t *bis)
dev->iobase = pci_io_to_phys(devbusfn, dev->iobase);
dev->iobase &= ~0xf;
 
-   PCNET_DEBUG1("%s: devbusfn=0x%x iobase=0x%x: ",
-dev->name, devbusfn, dev->iobase);
+   PCNET_DEBUG1("%s: devbusfn=0x%x iobase=0x%lx: ",
+dev->name, devbusfn, (unsigned long)dev->iobase);
 
command = PCI_COMMAND_IO | PCI_COMMAND_MASTER;
pci_write_config_word(devbusfn, PCI_COMMAND, command);
@@ -295,7 +295,7 @@ static int pcnet_init(struct eth_device *dev, bd_t *bis)
 {
struct pcnet_uncached_priv *uc;
int i, val;
-   u32 addr;
+   unsigned long addr;
 
PCNET_DEBUG1("%s: pcnet_init...\n", dev->name);
 
@@ -333,16 +333,18 @@ static int pcnet_init(struct eth_device *dev, bd_t *bis)
 * must be aligned on 16-byte boundaries.
 */
if (lp == NULL) {
-   addr = (u32)malloc(sizeof(pcnet_priv_t) + 0x10);
+   addr = (unsigned long)malloc(sizeof(pcnet_priv_t) + 0x10);
addr = (addr + 0xf) & ~0xf;
lp = (pcnet_priv_t *)addr;
 
-   addr = (u32)memalign(ARCH_DMA_MINALIGN, sizeof(*lp->uc));
+   addr = (unsigned long)memalign(ARCH_DMA_MINALIGN,
+  sizeof(*lp->uc));
flush_dcache_range(addr, addr + sizeof(*lp->uc));
addr = UNCACHED_SDRAM(addr);
lp->uc = (struct pcnet_uncached_priv *)addr;
 
-   addr = (u32)memalign(ARCH_DMA_MINALIGN, sizeof(*lp->rx_buf));
+   addr = (unsigned long)memalign(ARCH_DMA_MINALIGN,
+  sizeof(*lp->rx_buf));
flush_dcache_range(addr, addr + sizeof(*lp->rx_buf));
lp->rx_buf = (void *)addr;
}
-- 
2.8.3

___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH v2 2/4] net: pcnet: Stop converting kseg1->kseg0 addresses

[Paul Burton]

Now that MIPS virt_to_phys can handle kseg1 addresses on MIPS32, stop
manually converting addresses to their kseg0 equivalents in the pcnet
driver.

Signed-off-by: Paul Burton 

---

Changes in v2:
- New patch.

 drivers/net/pcnet.c | 15 ++-
 1 file changed, 6 insertions(+), 9 deletions(-)

diff --git a/drivers/net/pcnet.c b/drivers/net/pcnet.c
index 16a7512..efa4afb 100644
--- a/drivers/net/pcnet.c
+++ b/drivers/net/pcnet.c
@@ -135,14 +135,11 @@ static void pcnet_halt (struct eth_device *dev);
 static int pcnet_probe (struct eth_device *dev, bd_t * bis, int dev_num);
 
 static inline pci_addr_t pcnet_virt_to_mem(const struct eth_device *dev,
-   void *addr, bool uncached)
+   void *addr)
 {
pci_dev_t devbusfn = (pci_dev_t)dev->priv;
void *virt_addr = addr;
 
-   if (uncached)
-   virt_addr = (void *)CKSEG0ADDR(addr);
-
return pci_virt_to_mem(devbusfn, virt_addr);
 }
 
@@ -361,7 +358,7 @@ static int pcnet_init(struct eth_device *dev, bd_t *bis)
 */
lp->cur_rx = 0;
for (i = 0; i < RX_RING_SIZE; i++) {
-   addr = pcnet_virt_to_mem(dev, (*lp->rx_buf)[i], false);
+   addr = pcnet_virt_to_mem(dev, (*lp->rx_buf)[i]);
uc->rx_ring[i].base = cpu_to_le32(addr);
uc->rx_ring[i].buf_length = cpu_to_le16(-PKT_BUF_SZ);
uc->rx_ring[i].status = cpu_to_le16(0x8000);
@@ -393,9 +390,9 @@ static int pcnet_init(struct eth_device *dev, bd_t *bis)
 
uc->init_block.tlen_rlen = cpu_to_le16(TX_RING_LEN_BITS |
   RX_RING_LEN_BITS);
-   addr = pcnet_virt_to_mem(dev, uc->rx_ring, true);
+   addr = pcnet_virt_to_mem(dev, uc->rx_ring);
uc->init_block.rx_ring = cpu_to_le32(addr);
-   addr = pcnet_virt_to_mem(dev, uc->tx_ring, true);
+   addr = pcnet_virt_to_mem(dev, uc->tx_ring);
uc->init_block.tx_ring = cpu_to_le32(addr);
 
PCNET_DEBUG1("\ntlen_rlen=0x%x rx_ring=0x%x tx_ring=0x%x\n",
@@ -406,7 +403,7 @@ static int pcnet_init(struct eth_device *dev, bd_t *bis)
 * Tell the controller where the Init Block is located.
 */
barrier();
-   addr = pcnet_virt_to_mem(dev, >uc->init_block, true);
+   addr = pcnet_virt_to_mem(dev, >uc->init_block);
pcnet_write_csr(dev, 1, addr & 0x);
pcnet_write_csr(dev, 2, (addr >> 16) & 0x);
 
@@ -464,7 +461,7 @@ static int pcnet_send(struct eth_device *dev, void *packet, 
int pkt_len)
 * Setup Tx ring. Caution: the write order is important here,
 * set the status with the "ownership" bits last.
 */
-   addr = pcnet_virt_to_mem(dev, packet, false);
+   addr = pcnet_virt_to_mem(dev, packet);
writew(-pkt_len, >length);
writel(0, >misc);
writel(addr, >base);
-- 
2.8.3

___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH v2 1/4] MIPS: Use CPHYSADDR to implement mips32 virt_to_phys

[Paul Burton]

Use CPHYSADDR to implement the virt_to_phys function for converting from
a virtual to a physical address for MIPS32, much as is already done for
MIPS64. This allows for virt_to_phys to work regardless of whether the
address being translated is in kseg0 or kseg1, unlike the previous
subtraction based approach which only worked for addresses in kseg0.
This allows for drivers to provide an address to virt_to_phys without
needing to manually ensure that kseg1 addresses are converted to
equivalent kseg0 addresses first.

This patch is equivalent to this Linux patch currently waiting to be
reviewed & merged:

https://patchwork.linux-mips.org/patch/12564/

Signed-off-by: Paul Burton 

---

Changes in v2:
- New patch.

 arch/mips/include/asm/io.h | 5 +
 1 file changed, 1 insertion(+), 4 deletions(-)

diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h
index 723a60a..5b86386 100644
--- a/arch/mips/include/asm/io.h
+++ b/arch/mips/include/asm/io.h
@@ -92,11 +92,8 @@ static inline unsigned long virt_to_phys(volatile const void 
*address)
 #ifdef CONFIG_64BIT
if (addr < CKSEG0)
return XPHYSADDR(addr);
-
-   return CPHYSADDR(addr);
-#else
-   return addr - PAGE_OFFSET + PHYS_OFFSET;
 #endif
+   return CPHYSADDR(addr);
 }
 
 /*
-- 
2.8.3

___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH v2 0/4] Malta MIPS64 support

[Paul Burton]

This series allows MIPS64 builds for Malta boards, which can be used
either on real Malta boards with a MIPS64 CPU or in QEMU. It prepares by
fixing some 64 bit safety issues that affect the ethernet driver, then
allows the builds for the Malta board.

This series applies atop u-boot-mips/next as of 4349b55b9953.

Paul Burton (4):
  MIPS: Use CPHYSADDR to implement mips32 virt_to_phys
  net: pcnet: Stop converting kseg1->kseg0 addresses
  net: pcnet: Make 64 bit safe
  malta: Allow MIPS64 builds

 arch/mips/Kconfig  |  3 +++
 arch/mips/include/asm/io.h |  5 +
 board/imgtec/malta/Kconfig |  3 ++-
 board/imgtec/malta/lowlevel_init.S | 13 +++--
 drivers/net/pcnet.c| 33 -
 include/configs/malta.h| 18 +-
 6 files changed, 42 insertions(+), 33 deletions(-)

-- 
2.8.3

___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH] ARM: k2g: Configure reset mux to device reset

[Lokesh Vutla]

BOOTCFG_RSTMUX8 register controls the reset mux associated with the ARM.
Timer5(dedicated to ARM) when used as WatchDog timer, the events it
generates are routed to the above mux.

Following are the 3 events that can controlled bt the reset mux:
- Device Reset
- An interrupt to the ARM_GIC
- An interrupt to the ARM_GIC followed by a device reset.

Right now to give a default watchdog behaviour "Device reset" is
being selected.

Signed-off-by: Lokesh Vutla 
---
 arch/arm/mach-keystone/include/mach/hardware-k2g.h | 12 
 board/ti/ks2_evm/board_k2g.c   | 16 
 2 files changed, 28 insertions(+)

diff --git a/arch/arm/mach-keystone/include/mach/hardware-k2g.h 
b/arch/arm/mach-keystone/include/mach/hardware-k2g.h
index ca2a119..0f6bf61 100644
--- a/arch/arm/mach-keystone/include/mach/hardware-k2g.h
+++ b/arch/arm/mach-keystone/include/mach/hardware-k2g.h
@@ -74,4 +74,16 @@
 #define K2G_GPIO_DIR_OFFSET0x0
 #define K2G_GPIO_SETDATA_OFFSET0x8
 
+/* BOOTCFG RESETMUX8 */
+#define KS2_RSTMUX8(KS2_DEVICE_STATE_CTRL_BASE + 0x328)
+
+/* RESETMUX register definitions */
+#define RSTMUX_LOCK8_SHIFT 0x0
+#define RSTMUX_LOCK8_MASK  (0x1 << 0)
+#define RSTMUX_OMODE8_SHIFT0x1
+#define RSTMUX_OMODE8_MASK (0x7 << 1)
+#define RSTMUX_OMODE8_DEV_RESET0x2
+#define RSTMUX_OMODE8_INT  0x3
+#define RSTMUX_OMODE8_INT_AND_DEV_RESET0x4
+
 #endif /* __ASM_ARCH_HARDWARE_K2G_H */
diff --git a/board/ti/ks2_evm/board_k2g.c b/board/ti/ks2_evm/board_k2g.c
index b62c412..8f16845 100644
--- a/board/ti/ks2_evm/board_k2g.c
+++ b/board/ti/ks2_evm/board_k2g.c
@@ -117,12 +117,28 @@ int board_mmc_init(bd_t *bis)
 #endif
 
 #ifdef CONFIG_BOARD_EARLY_INIT_F
+
+static void k2g_reset_mux_config(void)
+{
+   /* Unlock the reset mux register */
+   clrbits_le32(KS2_RSTMUX8, RSTMUX_LOCK8_MASK);
+
+   /* Configure BOOTCFG_RSTMUX8 for WDT event to cause a device reset */
+   clrsetbits_le32(KS2_RSTMUX8, RSTMUX_OMODE8_MASK,
+   RSTMUX_OMODE8_DEV_RESET << RSTMUX_OMODE8_SHIFT);
+
+   /* lock the reset mux register to prevent any spurious writes. */
+   setbits_le32(KS2_RSTMUX8, RSTMUX_LOCK8_MASK);
+}
+
 int board_early_init_f(void)
 {
init_plls();
 
k2g_mux_config();
 
+   k2g_reset_mux_config();
+
/* deassert FLASH_HOLD */
clrbits_le32(K2G_GPIO1_BANK2_BASE + K2G_GPIO_DIR_OFFSET,
 BIT(9));
-- 
2.8.2

___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Re: [U-Boot] [PATCH] serial: 16550: Add JZ47xx support

[Simon Glass]

Hi Marek,

On 25 May 2016 at 16:35, Marek Vasut  wrote:
> On 05/26/2016 12:31 AM, Daniel Schwierzeck wrote:
>>
>>
>> Am 26.05.2016 um 00:21 schrieb Marek Vasut:
>>> On 05/26/2016 12:17 AM, Daniel Schwierzeck wrote:


 Am 25.05.2016 um 02:19 schrieb Marek Vasut:
> The Ingenic JZ47xx requires special bit (UART_EN) set in FCR register
> in order to work at all. Add this special case handling into the driver.
>
> Signed-off-by: Marek Vasut 
> Cc: Tom Rini 
> Cc: Simon Glass 
> Cc: Daniel Schwierzeck 
> Cc: Paul Burton 
> ---
>  drivers/serial/ns16550.c | 8 
>  1 file changed, 8 insertions(+)
>
> diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c
> index 30ba0aa..1323881 100644
> --- a/drivers/serial/ns16550.c
> +++ b/drivers/serial/ns16550.c
> @@ -50,6 +50,14 @@ DECLARE_GLOBAL_DATA_PTR;
>  #endif
>  #endif
>
> +#ifdef CONFIG_ARCH_JZ47XX
> +#undef UART_FCRVAL
> +/* Ingenic JZ47xx SoCs require that a 'UART Module Enable' bit be set */
> +#define UART_FCR_UME  0x10
> +#define UART_FCRVAL (UART_FCR_FIFO_EN | UART_FCR_RXSR |   \
> +   UART_FCR_TXSR | UART_FCR_UME)
> +#endif

 I think this could be added as DT property
>>>
>>> Not for SPL, which has 14 kiB size limit and it is itching to overflow.
>>> I am literally counting bytes in the SPL and removing slop from
>>> structures to make it fit, just barely. With the USB loader, I can
>>> brutalize the SPL into having extremely rudimentary UART support now
>>> (like printch() being the most advanced output mechanism, but you can
>>> only use it three times, otherwise the code won't fit and the board is
>>> eaten by demons) and this is where this patch comes into play.
>>>
>>> So yes, for full u-boot, this _should_ be part of DT. For SPL, please apply.
>>>
>>
>> ok, but wouldn't it be better to introduce an option like
>> CONFIG_SYS_NS16550_UME instead of using the SoC-specific
>> CONFIG_ARCH_JZ47XX. This driver is messed up enough ;)
>
> I was undecided between this (like the IER) and adding new ifdef (like
> SOC_KEYSTONE). Whichever way is fine with me. Yeah, the driver is
> repugnant for sure.
>
> +
>  #ifndef CONFIG_SYS_NS16550_IER
>  #define CONFIG_SYS_NS16550_IER  0x00
>  #endif /* CONFIG_SYS_NS16550_IER */
>

That way seems better to me. You should be able to add your UME flag
as a Kconfig for this driver, in drivers/serial/Kconfig, which
defaults to 0. It would be good to keep out board-specific stuff from
this file, as you did with OMAP1510.

Regards,
Simon
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot