Hello Simon,
Am 13.09.2016 um 15:08 schrieb Simon Glass:
Hi Heiko,
On 13 September 2016 at 00:02, Heiko Schocher wrote:
Hello Simon,
Am 13.09.2016 um 07:18 schrieb Simon Glass:
This series moves all the CONFIG_SPL_..._SUPPORT options to Kconfig and
fixes up existing boards
>From: Sriram Dash [mailto:sriram.d...@nxp.com]
>
Hello Marek,
Any comments?
>For FSL USB node fixup, the dt is walked multiple times for fixing erratum and
>phy
>type. This patch walks the tree and fixes the node till no more USB nodes are
>left.
>
>Signed-off-by: Sriram Dash
Currently the controller by default enables the Receive Detect feature in P3
mode in USB 3.0 PHY. However, USB 3.0 PHY does not reliably support receive
detection in P3 mode.
Enabling the USB3 controller to configure USB in P2 mode whenever the Receive
Detect feature is required.
Signed-off-by:
Override the switch_to_hypervisor function to switch cpu to hypervisor
mode using the available ROM code hook early in the boot phase before
the boot loader checks for HYP mode.
Based on the work done by Jonathan Bergsagel jbergsa...@ti.com.
Cc: beagleboard-...@googlegroups.com
Signed-off-by:
On some of the SoCs one cannot enable hypervisor mode directly from the
u-boot because the ROM code puts the chip to supervisor mode after it
jumps to boot loader. Hence introduce a weak function which can be
overridden based on the SoC type and switch to hypervisor mode in a
custom way.
Cc:
Enable Linear Physical Address Extension mode which is a
prerequisite for hypervisor mode.
Signed-off-by: Keerthy
---
configs/dra7xx_evm_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/configs/dra7xx_evm_defconfig b/configs/dra7xx_evm_defconfig
index
Enable Linear Physical Address Extension mode which is a
prerequisite for hypervisor mode.
Signed-off-by: Keerthy
---
configs/am57xx_evm_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/configs/am57xx_evm_defconfig b/configs/am57xx_evm_defconfig
index
Cache configuration methods is different for LPAE and non-LPAE cases.
Hence the bits and the interpretaion is different for two cases.
In case of non-LPAE mode short descriptor format is used and we need
to set Cache and Buffer bits.
In the case of LPAE the cache configuration happens via MAIR0
As of now the mmu section shift is hardcoded to 20 but with LPAE
coming into picture this can be different. Hence replacing 20 with
MMU_SECTION_SHIFT macro.
Signed-off-by: Keerthy
---
arch/arm/cpu/armv7/omap-common/omap-cache.c | 4 ++--
1 file changed, 2 insertions(+), 2
On SoCs like DRA7, OMAP5 one cannot enable hypervisor mode directly from the
u-boot because the ROM code puts the chip to supervisor mode after it
jumps to boot loader.
Patch 1-4 enable LPAE.
Patch 5: Introduces a weak function which can be overridden specific to
SoCs to switch to hypervisor
> "Heiko" == Heiko Schocher writes:
Heiko> Hello Peter, Am 14.09.2016 um 05:49 schrieb
Heiko> peter.ch...@data61.csiro.au:
>> After any operation that downloads a file (e.g., pxe get, or dhcp),
>> the buffer containing the downloaded data is flushed. This is
>> unnecessary and
Delete CONFIG_SKIP_LOWLEVEL_INIT define in ls1021atwr.h and
ls1021aqds.h can let it run cpu_init_cp15 to enable i-cache. First
stage of u-boot can run faster after that. There is a description
about skip lowlevel init in board/freescale/ls1021atwr/README.
Signed-off-by: Xiaoliang Yang
I have found very little online about getting a standalone application up and
running.
I don't have much experience in general let alone firmware level code.
What are the steps to creating my own standalone application?
I got the hello_world.bin running, but the makefiles are so complex that I
A type mismatch in the efi_allocate_pool boot service flow causes
hazardous memory scribbling on 32-bit systems.
This is efi_allocate_pool's prototype:
static efi_status_t EFIAPI efi_allocate_pool(int pool_type,
unsigned long size,
Suspicious implicit sign extension exist. ext_csd[] is defined
as "u8", capacity is defined as u64, so u8 is promoted to signed
int first int the "|" expersion, then the sign extended to u64.
if the tmp sign value is largeer than 0x7fff, after the sign
extension, the upper bits of the result
Enable palmas PMIC config options.
Signed-off-by: Keerthy
---
configs/dra7xx_evm_defconfig | 3 +++
1 file changed, 3 insertions(+)
diff --git a/configs/dra7xx_evm_defconfig b/configs/dra7xx_evm_defconfig
index 64184de..882e615 100644
--- a/configs/dra7xx_evm_defconfig
+++
The driver provides regulator set/get voltage
enable/disable functions for palmas family of PMICs.
Signed-off-by: Keerthy
---
drivers/power/regulator/Kconfig| 8 +
drivers/power/regulator/Makefile | 1 +
drivers/power/regulator/palmas_regulator.c |
Add support to bind the regulators/child nodes with the pmic.
Signed-off-by: Keerthy
---
drivers/power/pmic/Kconfig | 7 +
drivers/power/pmic/Makefile | 1 +
drivers/power/pmic/palmas.c | 77 +
include/power/palmas.h | 25
Enable palmas PMIC config options.
Signed-off-by: Keerthy
---
configs/am57xx_evm_defconfig | 3 +++
1 file changed, 3 insertions(+)
diff --git a/configs/am57xx_evm_defconfig b/configs/am57xx_evm_defconfig
index d49129d..b277783 100644
--- a/configs/am57xx_evm_defconfig
+++
The ctrl reg contains bit fields to enable and disable regulators,
and volt_reg has the bit fields to configure the voltage values.
The registers are frequently accessed hence make them part
of dm_regulator_uclass_platdata structure.
Signed-off-by: Keerthy
---
The series adds support for Palmas family of PMICs.
Implements functions to configure regulators. Enable/Disable
Get/Set voltages of regulators.
Supports TPS659038, TPS65917, Palmas.
Tested on TPS659038, TPS65917 using DRA7XX-EVM and AM57XX-EVM.
Keerthy (5):
power: regulator: Add ctrl_reg
Hello Peter,
Am 14.09.2016 um 05:49 schrieb peter.ch...@data61.csiro.au:
After any operation that downloads a file (e.g., pxe get, or dhcp), the
buffer containing the downloaded data is flushed. This is unnecessary
and annoying. Unnecessary, because
the network driver should already have
After any operation that downloads a file (e.g., pxe get, or dhcp), the
buffer containing the downloaded data is flushed. This is unnecessary
and annoying. Unnecessary, because
the network driver should already have fliushed the cache for the DMAed area,
and annoying because it generates a cache
Hi Tom,
On 13 September 2016 at 21:44, Simon Glass wrote:
> Despite the availability of Kconfig, the number of ad-hoc CONFIG options in
> U-Boot is still at over 8000.
>
> In February 2015 (commit 741e58e0) there were around 8387 ad-hoc CONFIGs.
> As of this patch there are
Despite the availability of Kconfig, the number of ad-hoc CONFIG options in
U-Boot is still at over 8000.
In February 2015 (commit 741e58e0) there were around 8387 ad-hoc CONFIGs.
As of this patch there are about 8336, only a little fewer.
One problem is that new ones are still being added,
> "Fabio" == Fabio Estevam writes:
Fabio> On Tue, Sep 13, 2016 at 10:30 PM,
Fabio> wrote:
>> After any operation that downloads a file (e.g., pxe get, or dhcp),
>> the buffer containing the downloaded data is flushed. This patch
>> rounds up
New CONFIG options should be added via Kconfig. To help prevent new ad-hoc
CONFIGs from being added, give a build error when these are detected.
Signed-off-by: Simon Glass
Acked-by: Stephen Warren
Tested-by: Stephen Warren
---
Changes
On Tue, Sep 13, 2016 at 10:30 PM, wrote:
> After any operation that downloads a file (e.g., pxe get, or dhcp), the
> buffer containing the downloaded data is flushed. This patch rounds
> up the flushed size to a cacheline boundary, preventing a cache
> misalignment
2016-09-13 3:28 GMT+09:00 Stephen Warren :
> On 09/12/2016 08:23 AM, Tom Rini wrote:
>>
>> On Mon, Sep 12, 2016 at 11:24:35AM +0900, Masahiro Yamada wrote:
>>>
>>> 2016-09-10 7:25 GMT+09:00 Stephen Warren :
On 09/09/2016 03:14 PM, Tom Rini
Sinlinx SinA33 uses PB4 for mmc0 card detect.
Signed-off-by: Chen-Yu Tsai
---
configs/Sinlinx_SinA33_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/configs/Sinlinx_SinA33_defconfig b/configs/Sinlinx_SinA33_defconfig
index 013c35e1a835..77eb05bf251a 100644
---
Sinlinx SinA33 has 1 USB host port. Enable EHCI_HCD support for it.
Also enable USB mass storage support so we can access USB sticks.
Signed-off-by: Chen-Yu Tsai
---
configs/Sinlinx_SinA33_defconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git
Sinlinx SinA33 has a USB OTG port, but VBUS is controlled manually from
a jumper pad.
Enable OTG in gadget mode, as well as the download gadget and related
functions.
Signed-off-by: Chen-Yu Tsai
---
configs/Sinlinx_SinA33_defconfig | 8
1 file changed, 8 insertions(+)
On 09/08/2016 11:12 PM, Q.Y. Gong wrote:
>
> I can boot it up with this patch set on star server: LS2085ARDB-1.
> I also tested the single patch and no issue.
>
> This is my U-Boot command:
> =>tftp 8200 b52263/ls2080ardb/u-boot-with-spl.bin;nand erase 8
> 18;nand write 8200 8
Enable the NAND interface on this board.
Signed-off-by: Chris Packham
---
arch/arm/dts/armada-385-amc.dts | 8
configs/db-88f6820-amc_defconfig | 2 ++
include/configs/db-88f6820-amc.h | 4
3 files changed, 14 insertions(+)
diff --git
This board is a plug in card for Marvell's switch system development
kits. Form-factor aside it is similar to the DB-88F6820-GP with the
following differences.
- TCLK is 200MHz
- SPI1 is used
- No SATA
- No MMC
- NAND flash
Signed-off-by: Chris Packham
---
I've used my
88F6820 is a specific Armada-38x chip that is used on the DB-88F6820-GP
board. Rather than having DB_88F6820_GP and TARGET_DB_88F6820_GP which
selects the former. Rename DB_88F6820_GP to 88F6820 so that other boards
using the 88F6820 can be added.
Signed-off-by: Chris Packham
The call to flush cache on the transmit buffer was misplaced (for very
short packets) and asked to flush less than a cacheline.
Move the flush cache call to after a short packet has been padded
to minimum length (so the padding is flushed too), and round the size
up to a cacheline.
After any operation that downloads a file (e.g., pxe get, or dhcp), the
buffer containing the downloaded data is flushed. This patch rounds
up the flushed size to a cacheline boundary, preventing a cache
misalignment message from u-boot.
Signed-off-by: Peter Chubb
Hi Jagan,
On Wed, Sep 14, 2016 at 12:41:17AM +0530, Jagan Teki wrote:
>Hi Peng,
>
>On Thu, Sep 8, 2016 at 7:05 AM, Peng Fan wrote:
>> Hi Jagan,
>> On Wed, Sep 07, 2016 at 08:21:07PM +0530, Jagan Teki wrote:
>>>On Thu, Aug 11, 2016 at 11:32 AM, Peng Fan
The core position is not continuous for some SoCs. For example,
valid cores may present at position 0, 1, 4, 5, 8, 9, etc. Some
registers (including boot release register) only count existing
cores. Current implementation of cpu_mask() complies with the
continuous numbering. However, command "cpu
Instead of providing the full path, specify directory and filename
separately. This allows to specify intermediate directories, required
for some additional tests.
Signed-off-by: Stefan Brüns
---
test/fs/fs-test.sh | 58
ext4 and fat code emit some diagnostic messages during command execution.
These additional lines force a match window size which strictly is not
necessary.
Signed-off-by: Stefan Brüns
---
test/fs/fs-test.sh | 26 +++---
1 file changed, 15
/ and /./ should reference the same file.
Signed-off-by: Stefan Brüns
---
test/fs/fs-test.sh | 29 -
1 file changed, 28 insertions(+), 1 deletion(-)
diff --git a/test/fs/fs-test.sh b/test/fs/fs-test.sh
index 69abdab..520344b 100755
---
This is a regression test for a crash happening if the first dirent
in the block matches. Code tried to access a predecessor entry which
does not exist.
The crash happened for any block, but "." is always the first entry in
the first directory block and thus easy to check for.
Signed-off-by:
The first 3 patches do some cleanups for the current test, especially TC11
had some issues (strange match for expected output, use of unitialized
variable).
The last two patches add test cases for handling ".". Ext4 used to crash,
as a match on the first entry of a directory block was not handled
The write file is created from $SMALL_FILE by appending ".w" on all
other occurences in the code.
Signed-off-by: Stefan Brüns
---
test/fs/fs-test.sh | 10 --
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git a/test/fs/fs-test.sh
On Tue, Sep 13, 2016 at 11:24 AM, Jagan Teki wrote:
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |\
> + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
> + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST
Add support for reading back flash parameters as reported by
the ec.
Signed-off-by: Moritz Fischer
Cc: Simon Glass
Cc: u-boot@lists.denx.de
---
drivers/misc/cros_ec.c | 21 +
1 file changed, 21 insertions(+)
diff --git
Add command to print out the flash info as reported by the
ec. The data read back includes size, write block size,
erase block size.
Signed-off-by: Moritz Fischer
Cc: Simon Glass
Cc: u-boot@lists.denx.de
---
drivers/misc/cros_ec.c | 10 ++
1
Hi Jagan,
On Tue, Sep 13, 2016 at 4:11 PM, Jagan Teki wrote:
+int dram_init(void)
+{
+ gd->ram_size = imx_ddr_size();
>
> Is this common call for all imx soc's to get the ddr size? because I
> observed incorrect size when I call this function.
On 09/12/2016 07:54 PM, Wenyou Yang wrote:
For the peripheral clock, provide the clock ops for the clock
provider, such as spi0_clk. The .of_xlate is to get the clk->id,
the .enable is to enable the spi0 peripheral clock, the .get_rate
is to get the clock frequency.
The driver for periph32ck
Hi Peng,
On Thu, Sep 8, 2016 at 7:05 AM, Peng Fan wrote:
> Hi Jagan,
> On Wed, Sep 07, 2016 at 08:21:07PM +0530, Jagan Teki wrote:
>>On Thu, Aug 11, 2016 at 11:32 AM, Peng Fan wrote:
>>> Add i.MX6ULL EVK board support:
>>> Add device tree file,
On Dienstag, 13. September 2016 12:33:15 CEST Stephen Warren wrote:
> On 09/12/2016 03:48 PM, Stefan Bruens wrote:
> > On Montag, 12. September 2016 12:39:35 CEST you wrote:
> >> On 09/11/2016 02:46 PM, Stefan Brüns wrote:
> >>> This is a regression test for a crash happening if the first dirent
>
On 09/12/2016 08:23 PM, Wenyou Yang wrote:
Add driver model support while retaining the existing legacy code.
This allows the driver to support boards that have converted to
driver model as well as those that have not.
I only reviewed the clock-related calls in this file, and they look
fine,
On 09/12/2016 07:54 PM, Wenyou Yang wrote:
Due to the peripheral clock driver improvement, remove the
unneccessary clock calling.
Patches 3-7,
Acked-by: Stephen Warren
___
U-Boot mailing list
U-Boot@lists.denx.de
On Dienstag, 13. September 2016 12:36:26 CEST you wrote:
> On 09/12/2016 04:04 PM, Stefan Bruens wrote:
> > On Montag, 12. September 2016 12:44:08 CEST you wrote:
> >> On 09/11/2016 02:46 PM, Stefan Brüns wrote:
> >>> / and /./ should reference the same file.
> >>>
> >>> diff --git
On 09/12/2016 07:54 PM, Wenyou Yang wrote:
In order to make clk->dev available in ops->of_xlate() to get the
clock ID from the 'reg' property of the clock node, assign the
clk->dev before calling ops->of_xlate().
It does seem reasonable to me to allow using the same of_xlate
implementation
Hi Tom,
On 13 September 2016 at 07:49, Tom Rini wrote:
> On Tue, Sep 13, 2016 at 07:35:42AM -0600, Simon Glass wrote:
>> Hi Tom,
>>
>> On 13 September 2016 at 07:16, Tom Rini wrote:
>> > On Mon, Sep 12, 2016 at 11:20:00PM -0600, Simon Glass wrote:
>> >
>>
On 09/12/2016 04:04 PM, Stefan Bruens wrote:
On Montag, 12. September 2016 12:44:08 CEST you wrote:
On 09/11/2016 02:46 PM, Stefan Brüns wrote:
/ and /./ should reference the same file.
diff --git a/test/fs/fs-test.sh b/test/fs/fs-test.sh
+# Read 1MB from small file
+${PREFIX}load
On 09/12/2016 03:48 PM, Stefan Bruens wrote:
On Montag, 12. September 2016 12:39:35 CEST you wrote:
On 09/11/2016 02:46 PM, Stefan Brüns wrote:
This is a regression test for a crash happening if the first dirent
in the block matches. Code tried to access a predecessor entry which
does not
Hi Marcin,
On Wed, Aug 31, 2016 at 7:54 AM, Marcin Niestroj
wrote:
> liteSOM is a System On Module (http://grinn-global.com/litesom/). It
> can't exists on its own, but will be used as part of other boards.
>
> Hardware specification:
> * NXP i.MX6UL processor
> *
From: Stephen Warren
Implement a clock uclass driver for the Tegra CAR. This allows clients to
use standard clock APIs on Tegra. This device is intended to be
instantiated by the core Tegra CAR driver, rather than being instantiated
directly from DT. The implementation uses
From: Stephen Warren
Implementations of the standard clock and reset APIs are available on all
Tegra SoCs now, so enable compilation of those uclasses.
Enable the Tegra CAR drivers for all SoCs prior to the BPMP being
available. This provides an implementation of those APIs
From: Stephen Warren
Now that the standard clock/reset APIs are available for all Tegra SoCs,
convert the MMC driver to use them exclusively, and remove any references
to the custom Tegra-specific APIs.
Cc: Jaehoon Chung
Signed-off-by: Stephen Warren
From: Stephen Warren
Now that the standard clock/reset APIs are available for all Tegra SoCs,
convert the I2C driver to use them exclusively, and remove any references
to the custom Tegra-specific APIs.
Cc: Heiko Schocher
Signed-off-by: Stephen Warren
From: Stephen Warren
Implement a reset uclass driver for the Tegra CAR. This allows clients to
use standard reset APIs on Tegra. This device is intended to be
instantiated by the core Tegra CAR driver, rather than being instantiated
directly from DT. The implementation uses
From: Stephen Warren
The Tegra CAR (Clock And Reset) module provides control of most clocks
and reset signals within the Tegra SoC. This change implements a driver
for this module. However, since the module implements multiple kinds of
services (clocks, resets, perhaps more),
From: Stephen Warren
Currently, Tegra peripheral drivers control two aspects of their HW module
clock(s):
1) The clock enable/rate for the peripheral clock itself.
2) The system-level clock tree setup, i.e. the clock parent.
Aspect 1 is reasonable, but aspect 2 is a
From: Stephen Warren
A future patch will implement a clock uclass driver for Tegra. That driver
will call into Tegra's existing clock code to simplify the transition;
this avoids tieing the clock uclass patches into significant refactoring
of the existing custom clock API
From: Stephen Warren
The primary benefit of this change is that it adds all missing clocks and
resets properties to peripherals. This will allow peripheral drivers to
migrate to the standard clock and reset APIs in the future.
Main changes:
* Brought in the correct Tegra210
From: Stephen Warren
The primary benefit of this change is that it adds all missing clocks and
resets properties to peripherals. This will allow peripheral drivers to
migrate to the standard clock and reset APIs in the future.
Main changes:
* Conversion of SPI nodes to
From: Stephen Warren
The primary benefit of this change is that it adds all missing clocks and
resets properties to peripherals. This will allow peripheral drivers to
migrate to the standard clock and reset APIs in the future.
Main changes:
* USB phy_type property is aligned
From: Stephen Warren
The primary benefit of this change is that it adds all missing clocks and
resets properties to peripherals. This will allow peripheral drivers to
migrate to the standard clock and reset APIs in the future.
Main changes:
* Modification of PCIe memory
From: Tom Warren
Convert the Tegra MMC driver to DM_MMC. Support for non-DM is removed
to avoid ifdefs in the code. DM_MMC is now enabled for all Tegra builds.
Cc: Jaehoon Chung
Signed-off-by: Tom Warren
(swarren, fixed some NULL
From: Stephen Warren
This brings in a few minor fixes since the last sync. The largest change
is the removal of the definition for TEGRA20_CLK_PCIE_XCLK. This clock
doesn't actually exist.
Remaining deltas:
* Addition of u-boot,dm-pre-reloc property to a couple of nodes.
*
From: Stephen Warren
Apparently the unit address in a DT node name is now supposed to be a
single integer value, rather than a comma-separated list of individual
cell values. Fix the U-Boot DTs to comply with this naming convention.
Signed-off-by: Stephen Warren
From: Stephen Warren
Most other pin mux is configured in this function. This removes the
need to do it in an MMC-specific initialization function, which is good
since that function is going away later in this series.
Signed-off-by: Stephen Warren
---
From: Stephen Warren
The Tegra MMC driver currently honors "sdhci" entries in /aliases. The
MMC core however uses "mmc" entries in /aliases. This difference will be
relevant once the Tegra MMC driver is converted to DM, and the MMC core
handles alias lookups. To avoid issues
From: Stephen Warren
pad_init_mmc() is performing an SoC-specific operation, using registers
within the MMC controller. There's no reason to implement this code
outside the MMC driver, so move it inside the driver.
Cc: Jaehoon Chung
Signed-off-by:
From: Stephen Warren
struct mmc_host is a Tegra-specific structure, but the name implies it's
something defined by core MMC code, which is confusing. Rename it to
struct tegra_mmc_priv to make its purpose more obvious. The new name is
also more appropriate for a DM driver
From: Stephen Warren
The MMC driver will soon be converted to use standard clock/reset APIs,
and so the periph_id field in the MMC device priv struct will disappear.
Rework the implementation of pad_init_mmc() to rely on this; using the
device register address is a much more
From: Tom Warren
During debug of the DM_MMC changes to the Tegra MMC driver, I
noticed that the 'removable' property wasn't being set correctly
for the eMMC parts on most Tegra boards. Since the kernel DTS has
this property set correctly, it should be in U-Boot's Tegra DT
This should be handled by the pinctrl driver.
Signed-off-by: Masahiro Yamada
---
arch/arm/mach-uniphier/pinctrl/pinctrl-ld4.c | 6 --
1 file changed, 6 deletions(-)
diff --git a/arch/arm/mach-uniphier/pinctrl/pinctrl-ld4.c
This is needed to get access to UniPhier System Bus (external bus).
Signed-off-by: Masahiro Yamada
---
drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c | 9 +++
drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c | 9 +++
Each DRAM channel size of LD21 is half of that of LD20.
Signed-off-by: Masahiro Yamada
---
arch/arm/mach-uniphier/boards.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-uniphier/boards.c b/arch/arm/mach-uniphier/boards.c
Unfortunately, this SoC needs per-board adjustment between clock
and address/command lines. This flag will be passed to the DRAM
init function and used for compensating the difference of DRAM
timing parameters.
Signed-off-by: Masahiro Yamada
---
This is the state-of-the-art MMC driver implementation.
Signed-off-by: Masahiro Yamada
Reviewed-by: Simon Glass
---
arch/arm/Kconfig | 1 +
drivers/mmc/Kconfig | 1 +
drivers/mmc/uniphier-sd.c | 50
We can use checkboard() stub to show additional board information,
so misc_init_f() should not be used for this purpose.
Signed-off-by: Masahiro Yamada
---
arch/arm/mach-uniphier/Makefile | 1 -
arch/arm/mach-uniphier/micro-support-card.c | 2 +-
These macros are only referenced in pinctrl-uniphier-core.c, so
they need not reside in a header file.
Signed-off-by: Masahiro Yamada
---
drivers/pinctrl/uniphier/pinctrl-uniphier-core.c | 4
drivers/pinctrl/uniphier/pinctrl-uniphier.h | 4
2 files
This driver has not been converted to Driver Model, and it is an
obstacle to migrate other block device drivers. Remove it for now.
The UniPhier SoCs already use a DM-based EHCI driver, so now
ARCH_UNIPHIER can select DM_USB.
These two changes must be done atomically because removing the
legacy
This SoC is equipped with two EHCI cores and two xHCI cores.
Enable the generic EHCI driver for the former.
Signed-off-by: Masahiro Yamada
---
configs/uniphier_pro4_defconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/configs/uniphier_pro4_defconfig
Currently, the UniPhier platform calls several init functions in the
following order:
[1] spl_board_init()
[2] board_early_init_f()
[3] board_init()
[4] board_early_init_r()
[5] board_late_init()
The serial console is not ready at the point of [2], so we want to
avoid using [2] from
ARCH_UNIPHIER is having more and more select:s. Sort them in case
a select is accidentally duplicated.
Signed-off-by: Masahiro Yamada
---
arch/arm/Kconfig | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/arch/arm/Kconfig
These ad-hoc pinmux settings were used for the legacy xHCI driver,
which has gone now.
Signed-off-by: Masahiro Yamada
---
arch/arm/mach-uniphier/pinctrl/pinctrl-ld20.c | 12
arch/arm/mach-uniphier/pinctrl/pinctrl-ld6b.c | 11 ---
I want to get this series in during this merge window.
- DM migration
* remove legacy xHCI driver
* convert MMC driver to CONFIG_BLOCK
- Pinctrl driver improvements
* New pin-group
* Macro cleanup
- Misc fixes, cleanups
* Fix DRAM size of LD21 SoC
*
Fixed typo for doc/README.imximage on respective imximage.cfg files.
Cc: Tom Rini
Cc: Peng Fan
Cc: Stefano Babic
Cc: Fabio Estevam
Signed-off-by: Jagan Teki
---
This series supports Engicam i.CoreM6 QDL modules on top of
u-boot-imx.git/next and test on the respective starter kits as well.
Jagan Teki (5):
imx: iomux-v3: Fix build error with snvs base
serial: Kconfig: Add MXC_UART entry
thermal: Kconfig: Add IMX_THERMAL entry
Kconfig: Add
Added kconfig for IMX_THERMAL driver.
Cc: Simon Glass
Cc: Fabio Estevam
Cc: Stefano Babic
Cc: Peng Fan
Cc: Matteo Lisi
Cc: Michael Trimarchi
Signed-off-by:
Boot Log for i.CoreM6 Quad/Dual Starter Kit:
U-Boot SPL 2016.09-rc2-30745-gd99a2be (Sep 13 2016 - 18:28:43)
Trying to boot from MMC1
U-Boot 2016.09-rc2-30745-gd99a2be (Sep 13 2016 - 18:28:43 +0530)
CPU: Freescale i.MX6Q rev1.2 at 792MHz
CPU: Industrial temperature grade (-40C to 105C) at
snvs base is added only for i.MX6ULL but the code is
added for common, so firing build error while compiling
other i.MX6 SOC's
Issue observed with the below patch
"imx: mx6ull: Update memory map address"
(sha1: e8eac1b5b3a98a06426bc4867c03c38329841e5c)
Build log:
CC
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