Re: [U-Boot] [PATCH 00/82] x86: Add initial support for 64-bit U-Boot

[Bin Meng]

Hi Simon,

On Mon, Sep 26, 2016 at 11:33 AM, Simon Glass  wrote:
> At present U-Boot runs entirely in 32-bit mode on x86, except for the
> initial switch from 16-bit mode. On 64-bit machines it is possible to run
> in 64-bit mode. This series starts the process of adding this support.
>
> The main benefit of 64-bit mode for a boot loader is direct access to all
> available memory. There are also more registers, but this makes very little
> difference.
>
> This feature is implemented by putting all of the 32-bit code in an SPL
> build. SPL then runs through all the init that has to be done in 32-bit
> mode, changes to 64-bit mode and then jumps to U-Boot proper.
>
> Typically the total code size increases slightly. For example, on link in
> 32-bit mode, U-Boot has around 480KB of code (admittedly with a large
> number of features enabled). In 64-bit mode, U-Boot falls to around 460KB,
> but SPL adds another 60KB, for a net increase of 40KB. Partly this is due
> to code duplication and partly it is due to the worse code density of
> 64-bit code on x86.
>
> Many major features are not implemented yet, for example:
> - SDRAM sizing
> - Booting linux
> - FSP support
> - EFI support
> - SCSI device init
> - Running video ROMs
>
> Still, this is a big step forward towards full 64-bit support. To enable it,
> select CONFIG_X86_RUN_64BIT.
>
> This series is available at u-boot-x86/64-working
>

Looks it requires a 64-bit toolchain to compile 64-bit U-Boot. For
example, I used kernel.org i386 toolchain to compile 64-bit U-Boot, I
got:

include/asm-generic/bitops/__fls.h: In function '__fls':
include/asm-generic/bitops/__fls.h:17:2: warning: left shift count >=
width of type
  if (!(word & (~0ul << 32))) {
  ^
include/asm-generic/bitops/__fls.h:19:3: warning: left shift count >=
width of type
   word <<= 32;
   ^
include/asm-generic/bitops/__fls.h:22:2: warning: left shift count >=
width of type
  if (!(word & (~0ul << (BITS_PER_LONG-16 {
  ^
include/asm-generic/bitops/__fls.h:26:2: warning: left shift count >=
width of type
  if (!(word & (~0ul << (BITS_PER_LONG-8 {
  ^
include/asm-generic/bitops/__fls.h:30:2: warning: left shift count >=
width of type
  if (!(word & (~0ul << (BITS_PER_LONG-4 {
  ^
include/asm-generic/bitops/__fls.h:34:2: warning: left shift count >=
width of type
  if (!(word & (~0ul << (BITS_PER_LONG-2 {
  ^
include/asm-generic/bitops/__fls.h:38:2: warning: left shift count >=
width of type
  if (!(word & (~0ul << (BITS_PER_LONG-1
  ^
arch/x86/cpu/intel_common/microcode.c: In function 'microcode_read_rev':
arch/x86/cpu/intel_common/microcode.c:79:2: error: PIC register
clobbered by 'ebx' in 'asm'
  asm volatile (
  ^
make[2]: *** [arch/x86/cpu/intel_common/microcode.o] Error 1

After I switched to 64-bit toolchain from kernel.org (x86_64-linux),
there was no such warnings/errors, but I still got build failure at
last.

  ./tools/binman/binman -d u-boot.dtb -O . -I . -I
./board/google/chromebook_link u-boot-x86-16bit.bin
Traceback (most recent call last):
  File "./tools/binman/binman", line 31, in 
import control
  File "./tools/binman/control.py", line 17, in 
from image import Image
  File "./tools/binman/image.py", line 12, in 
import entry
  File "./tools/binman/etype/entry.py", line 8, in 
import importlib
ImportError: No module named importlib
make: *** [u-boot.rom] Error 1

Regards,
Bin
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[U-Boot] [PATCH] configs: ls2080ardb: Enable DSPI flash support

[Yuan Yao]

From: Yuan Yao 

There is the stmicro DSPI flash on LS12080ARDB.
Enable DSPI flash related configure options.

Signed-off-by: Yuan Yao 
---
 include/configs/ls2080ardb.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h
index b93e919..90e31d4 100644
--- a/include/configs/ls2080ardb.h
+++ b/include/configs/ls2080ardb.h
@@ -271,6 +271,7 @@ unsigned long get_board_sys_clk(void);
 #ifdef CONFIG_FSL_DSPI
 #define CONFIG_SPI_FLASH
 #define CONFIG_SPI_FLASH_BAR
+#define CONFIG_SPI_FLASH_STMICRO
 #endif
 
 /*
-- 
2.1.0.27.g96db324

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Re: [U-Boot] [PATCH 37/82] x86: mrccache: Fix error handling in mrccache_get_region()

[Bin Meng]

On Tue, Oct 11, 2016 at 11:17 AM, Bin Meng  wrote:
> On Mon, Sep 26, 2016 at 11:33 AM, Simon Glass  wrote:
>> This should return normal errors, not device-tree errors. Fix it.
>>
>> Signed-off-by: Simon Glass 
>> ---
>>
>>  arch/x86/lib/mrccache.c | 8 +---
>>  1 file changed, 5 insertions(+), 3 deletions(-)
>>
>> diff --git a/arch/x86/lib/mrccache.c b/arch/x86/lib/mrccache.c
>> index 67bace4..eca88ac 100644
>> --- a/arch/x86/lib/mrccache.c
>> +++ b/arch/x86/lib/mrccache.c
>> @@ -198,11 +198,13 @@ int mrccache_get_region(struct udevice **devp, struct 
>> mrc_region *entry)
>>
>> /* Find the flash chip within the SPI controller node */
>> node = fdtdec_next_compatible(blob, 0, COMPAT_GENERIC_SPI_FLASH);
>> -   if (node < 0)
>> +   if (node < 0) {
>> +   debug("%s: Cannot find SPI flash\n", __func__);
>> return -ENOENT;
>> +   }
>>
>> if (fdtdec_get_int_array(blob, node, "memory-map", reg, 2))
>> -   return -FDT_ERR_NOTFOUND;
>> +   return -EINVAL;
>> entry->base = reg[0];
>>
>> /* Find the place where we put the MRC cache */
>> @@ -211,7 +213,7 @@ int mrccache_get_region(struct udevice **devp, struct 
>> mrc_region *entry)
>> return -EPERM;
>>
>> if (fdtdec_get_int_array(blob, mrc_node, "reg", reg, 2))
>> -   return -FDT_ERR_NOTFOUND;
>> +   return -EINVAL;
>> entry->offset = reg[0];
>> entry->length = reg[1];
>>
>> --
>
> Reviewed-by: Bin Meng 

applied to u-boot-x86, thanks!
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Re: [U-Boot] [PATCH 35/82] x86: Drop unused init_helper functions

[Bin Meng]

On Tue, Oct 11, 2016 at 11:17 AM, Bin Meng  wrote:
> On Mon, Sep 26, 2016 at 11:33 AM, Simon Glass  wrote:
>> Drop init_bd_struct_r() which is no-longer used. Also drop the declaration
>> for init_func_spi() since this is now handled by generic board init.
>>
>> Signed-off-by: Simon Glass 
>> ---
>>
>>  arch/x86/include/asm/init_helpers.h |  2 --
>>  arch/x86/lib/init_helpers.c | 10 --
>>  2 files changed, 12 deletions(-)
>>
>
> Reviewed-by: Bin Meng 

applied to u-boot-x86, thanks!
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Re: [U-Boot] [PATCH 32/82] x86: ivybridge: Tidy up enable_clock_gating() for 64-bit

[Bin Meng]

On Tue, Oct 11, 2016 at 11:16 AM, Bin Meng  wrote:
> Hi Simon,
>
> On Mon, Sep 26, 2016 at 11:33 AM, Simon Glass  wrote:
>> Fix the hex case and remove unused brackets. Use -0U instead of ~0UL to
>
> Should be: ~0U

Fixed this, and

>
>> allow compilation on 64-bit machines.
>>
>> Signed-off-by: Simon Glass 
>> ---
>>
>>  arch/x86/cpu/ivybridge/lpc.c | 8 
>>  1 file changed, 4 insertions(+), 4 deletions(-)
>>
>> diff --git a/arch/x86/cpu/ivybridge/lpc.c b/arch/x86/cpu/ivybridge/lpc.c
>> index c564713..aef1206 100644
>> --- a/arch/x86/cpu/ivybridge/lpc.c
>> +++ b/arch/x86/cpu/ivybridge/lpc.c
>> @@ -357,10 +357,10 @@ static void enable_clock_gating(struct udevice *pch)
>> reg16 |= (1 << 2) | (1 << 11);
>> dm_pci_write_config16(pch, GEN_PMCON_1, reg16);
>>
>> -   pch_iobp_update(pch, 0xEB007F07, ~0UL, (1 << 31));
>> -   pch_iobp_update(pch, 0xEB004000, ~0UL, (1 << 7));
>> -   pch_iobp_update(pch, 0xEC007F07, ~0UL, (1 << 31));
>> -   pch_iobp_update(pch, 0xEC004000, ~0UL, (1 << 7));
>> +   pch_iobp_update(pch, 0xeb007f07, ~0U, 1 << 31);
>> +   pch_iobp_update(pch, 0xeb004000, ~0U, 1 << 7);
>> +   pch_iobp_update(pch, 0xec007f07, ~0U, 1 << 31);
>> +   pch_iobp_update(pch, 0xec004000, ~0U, 1 << 7);
>>
>> reg32 = readl(RCB_REG(CG));
>> reg32 |= (1 << 31);
>> --
>
> Reviewed-by: Bin Meng 

applied to u-boot-x86, thanks!
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Re: [U-Boot] [PATCH 31/82] x86: ivybridge: Fix PCH power setup

[Bin Meng]

On Tue, Oct 11, 2016 at 11:16 AM, Bin Meng  wrote:
> On Mon, Sep 26, 2016 at 11:33 AM, Simon Glass  wrote:
>> At present pch_power_options() has the arguments to writel() around the
>> wrong way. Fix this and update it to compile on 64-bit machines.
>>
>> Signed-off-by: Simon Glass 
>> ---
>>
>>  arch/x86/cpu/ivybridge/lpc.c | 8 
>>  1 file changed, 4 insertions(+), 4 deletions(-)
>>
>
> Reviewed-by: Bin Meng 

applied to u-boot-x86, thanks!
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Re: [U-Boot] [PATCH 28/82] x86: Don't export interrupt handlers with x86_64

[Bin Meng]

On Tue, Oct 11, 2016 at 11:16 AM, Bin Meng  wrote:
> On Mon, Sep 26, 2016 at 11:33 AM, Simon Glass  wrote:
>> We don't have a way of adjusting these at present so it is best to refuse to
>> export these functions. This can be implemented later if the API is required.
>>
>> Signed-off-by: Simon Glass 
>> ---
>>
>>  include/_exports.h | 2 +-
>>  1 file changed, 1 insertion(+), 1 deletion(-)
>>
>
> Reviewed-by: Bin Meng 

applied to u-boot-x86, thanks!
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Re: [U-Boot] [PATCH 22/82] x86: Correct address casts in interrupt code

[Bin Meng]

On Tue, Oct 11, 2016 at 11:16 AM, Bin Meng  wrote:
> On Mon, Sep 26, 2016 at 11:33 AM, Simon Glass  wrote:
>> We should cast an address to unsigned long, not u32.
>>
>> Signed-off-by: Simon Glass 
>> ---
>>
>>  arch/x86/cpu/interrupts.c | 4 ++--
>>  1 file changed, 2 insertions(+), 2 deletions(-)
>>
>
> Reviewed-by: Bin Meng 

applied to u-boot-x86, thanks!
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Re: [U-Boot] [PATCH 21/82] x86: Correct address casts in cpu code

[Bin Meng]

On Tue, Oct 11, 2016 at 11:16 AM, Bin Meng  wrote:
> On Mon, Sep 26, 2016 at 11:33 AM, Simon Glass  wrote:
>> We should cast an address to unsigned long, not u32.
>>
>> Signed-off-by: Simon Glass 
>> ---
>>
>>  arch/x86/cpu/cpu.c | 10 --
>>  1 file changed, 4 insertions(+), 6 deletions(-)
>>
>
> Reviewed-by: Bin Meng 

applied to u-boot-x86, thanks!
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Re: [U-Boot] [PATCH 20/82] x86: Allow interrupts to be disabled in 64-bit mode

[Bin Meng]

On Tue, Oct 11, 2016 at 11:16 AM, Bin Meng  wrote:
> On Mon, Sep 26, 2016 at 11:33 AM, Simon Glass  wrote:
>> Update the code to support both 32-bit and 64-bit modes.
>>
>> Signed-off-by: Simon Glass 
>> ---
>>
>>  arch/x86/cpu/interrupts.c | 5 -
>>  1 file changed, 4 insertions(+), 1 deletion(-)
>>
>
> Reviewed-by: Bin Meng 

applied to u-boot-x86, thanks!
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Re: [U-Boot] [PATCH 18/82] usb: pci: Fix cast for 64-bit compilation

[Bin Meng]

On Tue, Oct 11, 2016 at 11:16 AM, Bin Meng  wrote:
> On Mon, Sep 26, 2016 at 11:33 AM, Simon Glass  wrote:
>> Fix a cast that causes warnings on 64-bit machines.
>>
>> Signed-off-by: Simon Glass 
>> ---
>>
>>  drivers/usb/host/ehci-pci.c | 4 ++--
>>  1 file changed, 2 insertions(+), 2 deletions(-)
>>
>
> Reviewed-by: Bin Meng 

applied to u-boot-x86, thanks!
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Re: [U-Boot] [PATCH 27/82] x86: i2c: Fix cast of address to 32-bit value

[Bin Meng]

On Tue, Oct 11, 2016 at 11:16 AM, Bin Meng  wrote:
> On Mon, Sep 26, 2016 at 11:33 AM, Simon Glass  wrote:
>> This gives a build warning on 64-bit x86. Fix it.
>>
>> Signed-off-by: Simon Glass 
>> ---
>>
>>  drivers/i2c/intel_i2c.c | 6 +++---
>>  1 file changed, 3 insertions(+), 3 deletions(-)
>>
>
> Reviewed-by: Bin Meng 

applied to u-boot-x86, thanks!
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Re: [U-Boot] [PATCH 17/82] tpm: Tidy up use of size_t

[Bin Meng]

On Tue, Oct 11, 2016 at 11:16 AM, Bin Meng  wrote:
> On Mon, Sep 26, 2016 at 11:33 AM, Simon Glass  wrote:
>> We should consistently use %z with size_t, and avoid passing a uint32_t as
>> a size_t value. Fix these issues to avoid warnings on 64-bit machines.
>>
>> Signed-off-by: Simon Glass 
>> ---
>>
>>  drivers/tpm/tpm_tis_lpc.c | 4 ++--
>>  1 file changed, 2 insertions(+), 2 deletions(-)
>>
>
> Reviewed-by: Bin Meng 

applied to u-boot-x86, thanks!
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Re: [U-Boot] [PATCH 08/82] rtc: Use CONFIG_X86 instead of __I386__

[Bin Meng]

On Tue, Oct 11, 2016 at 11:15 AM, Bin Meng  wrote:
> On Mon, Sep 26, 2016 at 11:33 AM, Simon Glass  wrote:
>> For 64-bit x86, __I386__ should perhaps not be defined. It is not clear from
>> the definition, but let's use CONFIG_X86 to be sure.
>>
>> Signed-off-by: Simon Glass 
>> ---
>>
>>  drivers/rtc/mc146818.c | 2 +-
>>  1 file changed, 1 insertion(+), 1 deletion(-)
>>
>
> Reviewed-by: Bin Meng 

applied to u-boot-x86, thanks!
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Re: [U-Boot] [PATCH 04/82] board_f: Drop the extra fdtdec_prepare_fdt()

[Bin Meng]

On Tue, Oct 11, 2016 at 11:15 AM, Bin Meng  wrote:
> On Mon, Sep 26, 2016 at 11:33 AM, Simon Glass  wrote:
>> This is already called earlier, from fdtdec_setup(), so drop this unnecessary
>> call from the init sequence.
>>
>> Signed-off-by: Simon Glass 
>> ---
>>
>>  common/board_f.c | 3 ---
>>  1 file changed, 3 deletions(-)
>>
>
> Reviewed-by: Bin Meng 

applied to u-boot-x86, thanks!
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Re: [U-Boot] [PATCH 03/82] bios_emulator: Fix cast for 64-bit compilation

[Bin Meng]

On Tue, Oct 11, 2016 at 11:15 AM, Bin Meng  wrote:
> On Mon, Sep 26, 2016 at 11:33 AM, Simon Glass  wrote:
>> Fix a cast that causes warnings on 64-bit machines.
>>
>> Signed-off-by: Simon Glass 
>> ---
>>
>>  drivers/bios_emulator/atibios.c | 2 +-
>>  1 file changed, 1 insertion(+), 1 deletion(-)
>>
>
> Reviewed-by: Bin Meng 

applied to u-boot-x86, thanks!
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Re: [U-Boot] [PATCH 06/82] elf: Add the Elf64_Rela type

[Bin Meng]

On Tue, Oct 11, 2016 at 11:15 AM, Bin Meng  wrote:
> On Mon, Sep 26, 2016 at 11:33 AM, Simon Glass  wrote:
>> Add this so that we can support 64-bit relocation on x86.
>>
>> Signed-off-by: Simon Glass 
>> ---
>>
>>  include/elf.h | 6 ++
>>  1 file changed, 6 insertions(+)
>>
>
> Reviewed-by: Bin Meng 

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Re: [U-Boot] [PATCH 02/82] Add _image_binary_end section declaration

[Bin Meng]

On Tue, Oct 11, 2016 at 11:15 AM, Bin Meng  wrote:
> On Mon, Sep 26, 2016 at 11:33 AM, Simon Glass  wrote:
>> This is used in some link scripts, so add a declaration for it.
>>
>> Signed-off-by: Simon Glass 
>> ---
>>
>>  include/asm-generic/sections.h | 1 +
>>  1 file changed, 1 insertion(+)
>>
>
> Reviewed-by: Bin Meng 

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Re: [U-Boot] [PATCH v5 0/5] net: fec_mxc: Convert to DM

[Jagan Teki]

Hi Stefano,

On Thu, Oct 6, 2016 at 4:25 PM, Jagan Teki  wrote:
> From: Jagan Teki 
>
> This series convert fec_mxc to DM and tested both dm and
> non-dm code and it is on top of u-boot-imx/master
>
> Changes for v5:
> - Add stub fec calls to minimize the #ifdef's
> - Use same func names on eth_ops
> - Remove reset_gpio in fec_mxc.h
> - Add new patches, for cleanup driver
>
> Changes for v4:
> - rebase to u-boot-imx/master
>
> Changes for v3:
> - Add ARM: dts: imx6qdl-icore: Add FEC support
> - icorem6: Use CONFIG_DM_ETH support
>
> Changes for v2:
> - Add TODO for implementing the enet reset code
>
> Jagan Teki (5):
>   net: fec_mxc: Remove unneeded eth_device arg from fec_get_hwaddr
>   net: fec_mxc: Convert into driver model
>   net: fec_mxc: Driver cleanups
>   ARM: dts: imx6qdl-icore: Add FEC support
>   icorem6: Use CONFIG_DM_ETH support

Any comments, otherwise please apply.

thanks!
-- 
Jagan Teki
Free Software Engineer | www.openedev.com
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Re: [U-Boot] [PATCH v7 00/21] imx6: Add Engicam i.CoreM6 QDL support

[Jagan Teki]

Hi Stefano,

On Sun, Oct 9, 2016 at 8:15 PM, Jagan Teki  wrote:
> Hi Stefano,
>
> On Sat, Oct 8, 2016 at 6:00 PM, Jagan Teki  wrote:
>> From: Jagan Teki 
>>
>> This series supports Engicam i.CoreM6 QDL modules on top of u-boot-imx/master
>> and test on the respective starter kits as well.
>>
>> Tested both MMC and NAND boot.
>>
>> Changes for v7:
>> - Add patch to CONFIG_DEFAULT_FDT_FILE to defconfigs
>> - Rebase on u-boot-imx/master
>>
>> Changes for v6:
>> - Rebase to u-boot-imx/master
>> - Move few SPL configs to defconfigs
>>
>> Changes for v5:
>> - Add NAND support
>>
>> Changes for v4:
>> - Add 'net: Kconfig: Add FEC_MXC entry' patch
>> - Updated ENV configs along with comments
>> - Restructured configs for more readability
>> - Add CONFIG_ENV_OVERWRITE
>> - Rename icorem6qdl_defconfig with icorem6qdl_mmc_defconfig
>>
>> Changes for v3:
>> - Remove "v2 01/17 imx: iomux-v3: Fix build error with snvs base" 
>> patch
>> - Remove 'default n' on Kconfig DEFAULT_FDT_FILE patch
>> - Add minimal devicetree support for Engicam i.CoreM6 QDL
>> - Add is_mx6dl()
>> - Add is_mx6solo()
>> - Use is_mx6dq()
>> - Add last commit sha1 and header in pull devicetree files from Linux
>>
>> Changes for v2:
>> - Make static to local iomux structure in board file
>> - Corrected rowaddr in mx6_ddr3_cfg
>> - Used imx_ddr_size
>> - Add FEC support and tested the same
>> - Add DM_GPIO, DM_MMC support
>> - Add pinctrl support
>> - Add devicetree support
>>
>> Jagan Teki (21):
>>   serial: Kconfig: Add MXC_UART entry
>>   thermal: Kconfig: Add IMX_THERMAL entry
>>   config: Move CONFIG_DEFAULT_FDT_FILE to defconfigs
>>   arm: imx: Add Engicam i.CoreM6 QDL Starter Kit initial support
>>   net: Kconfig: Add FEC_MXC entry
>>   imx6: icorem6: Add ENET support
>>   imx: s/docs\/README.imximage/doc\/README.imximage/g
>>   arm: dts: Add devicetree for i.MX6DL
>>   arm: dts: Add devicetree for i.MX6DQL
>>   arm: dts: imx6dl: Add pinctrl defines
>>   dt-bindings: clock: imx6qdl: Add clock defines
>>   arm: imx6q: Add devicetree support for Engicam i.CoreM6 DualLite/Solo
>>   imx6q: icorem6: Enable pinctrl driver
>>   engicam: icorem6: Add DM_GPIO, DM_MMC support
>>   arm: dts: Add devicetree for i.MX6Q
>>   arm: dts: imx6q: Add pinctrl defines
>>   arm: imx6q: Add devicetree support for Engicam i.CoreM6 Quad/Dual
>>   mtd: nand: Kconfig: Add NAND_MXS entry
>>   imx6: icorem6: Add NAND support
>>   imx6: icorem6: Enable MTD device support
>>   imx6: icorem6: Add default mtd nand partition table
>
> All set now, please do apply.

Let me know if you still find any issues, otherwise apply this.

thanks!
-- 
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Re: [U-Boot] [PATCH 36/82] x86: lib: Fix types and casts for 64-bit compilation

[Bin Meng]

Hi Simon,

On Mon, Sep 26, 2016 at 11:33 AM, Simon Glass  wrote:
> Fix various compiler warnings in the x86 library code.
>
> Signed-off-by: Simon Glass 
> ---
>
>  arch/x86/lib/bios.c | 4 ++--
>  arch/x86/lib/pinctrl_ich6.c | 2 +-
>  arch/x86/lib/pirq_routing.c | 4 ++--
>  arch/x86/lib/sfi.c  | 4 ++--
>  arch/x86/lib/zimage.c   | 2 +-
>  5 files changed, 8 insertions(+), 8 deletions(-)
>
> diff --git a/arch/x86/lib/bios.c b/arch/x86/lib/bios.c
> index 9324bdb..66d7629 100644
> --- a/arch/x86/lib/bios.c
> +++ b/arch/x86/lib/bios.c
> @@ -157,7 +157,7 @@ static void setup_realmode_idt(void)
>  for (i = 0; i < 256; i++) {
> idts[i].cs = 0;
> idts[i].offset = 0x1000 + (i * __idt_handler_size);
> -   write_idt_stub((void *)((u32)idts[i].offset), i);
> +   write_idt_stub((void *)((ulong)idts[i].offset), i);
> }
>
> /*
> @@ -227,7 +227,7 @@ static void vbe_set_graphics(int vesa_mode, struct 
> vbe_mode_info *mode_info)
> mode_info->video_mode = (1 << 14) | vesa_mode;
> vbe_get_mode_info(mode_info);
>
> -   framebuffer = (unsigned char *)mode_info->vesa.phys_base_ptr;
> +   framebuffer = (unsigned char *)(ulong)mode_info->vesa.phys_base_ptr;
> debug("VBE: resolution:  %dx%d@%d\n",
>   le16_to_cpu(mode_info->vesa.x_resolution),
>   le16_to_cpu(mode_info->vesa.y_resolution),
> diff --git a/arch/x86/lib/pinctrl_ich6.c b/arch/x86/lib/pinctrl_ich6.c
> index 3f94cdf..fb2d294 100644
> --- a/arch/x86/lib/pinctrl_ich6.c
> +++ b/arch/x86/lib/pinctrl_ich6.c
> @@ -104,7 +104,7 @@ static int ich6_pinctrl_cfg_pin(s32 gpiobase, s32 iobase, 
> int pin_node)
>
> /* if iobase is present, let's configure the pad */
> if (iobase != -1) {
> -   int iobase_addr;
> +   ulong iobase_addr;
>
> /*
>  * The offset for the same pin for the IOBASE and GPIOBASE are

Reviewed-by: Bin Meng 

> diff --git a/arch/x86/lib/pirq_routing.c b/arch/x86/lib/pirq_routing.c
> index a93d355..c98526d 100644
> --- a/arch/x86/lib/pirq_routing.c
> +++ b/arch/x86/lib/pirq_routing.c
> @@ -114,14 +114,14 @@ u32 copy_pirq_routing_table(u32 addr, struct 
> irq_routing_table *rt)
> addr = ALIGN(addr, 16);
>
> debug("Copying Interrupt Routing Table to 0x%x\n", addr);
> -   memcpy((void *)addr, rt, rt->size);
> +   memcpy((void *)(uintptr_t)addr, rt, rt->size);
>
> /*
>  * We do the sanity check here against the copied table after memcpy,
>  * as something might go wrong after the memcpy, which is normally
>  * due to the F segment decode is not turned on to systeam RAM.
>  */
> -   rom_rt = (struct irq_routing_table *)addr;
> +   rom_rt = (struct irq_routing_table *)(uintptr_t)addr;
> if (rom_rt->signature != PIRQ_SIGNATURE ||
> rom_rt->version != PIRQ_VERSION || rom_rt->size % 16) {
> printf("Interrupt Routing Table not valid\n");
> diff --git a/arch/x86/lib/sfi.c b/arch/x86/lib/sfi.c
> index 9564853..507e037 100644
> --- a/arch/x86/lib/sfi.c
> +++ b/arch/x86/lib/sfi.c
> @@ -38,14 +38,14 @@ static void *get_entry_start(struct table_info *tab)
> tab->table[tab->count] = tab->entry_start;
> tab->entry_start += sizeof(struct sfi_table_header);
>
> -   return (void *)tab->entry_start;
> +   return (void *)(uintptr_t)tab->entry_start;
>  }
>
>  static void finish_table(struct table_info *tab, const char *sig, void 
> *entry)
>  {
> struct sfi_table_header *hdr;
>
> -   hdr = (struct sfi_table_header *)(tab->base + tab->ptr);
> +   hdr = (struct sfi_table_header *)(uintptr_t)(tab->base + tab->ptr);
> strcpy(hdr->sig, sig);
> hdr->len = sizeof(*hdr) + ((ulong)entry - tab->entry_start);
> hdr->rev = 1;
> diff --git a/arch/x86/lib/zimage.c b/arch/x86/lib/zimage.c
> index 1b33c77..b6b0f2b 100644
> --- a/arch/x86/lib/zimage.c
> +++ b/arch/x86/lib/zimage.c
> @@ -165,7 +165,7 @@ struct boot_params *load_zimage(char *image, unsigned 
> long kernel_size,
>  * A very old kernel MUST have its real-mode code
>  * loaded at 0x9
>  */
> -   if ((u32)setup_base != 0x9) {
> +   if ((ulong)setup_base != 0x9) {
> /* Copy the real-mode kernel */
> memmove((void *)0x9, setup_base, setup_size);
>
> --

Can the above 3 changes merged into patch#23: x86: Use unsigned long
for address in table generation, since they are all table related
changes?

Regards,
Bin
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Re: [U-Boot] [PATCH 37/82] x86: mrccache: Fix error handling in mrccache_get_region()

[Bin Meng]

On Mon, Sep 26, 2016 at 11:33 AM, Simon Glass  wrote:
> This should return normal errors, not device-tree errors. Fix it.
>
> Signed-off-by: Simon Glass 
> ---
>
>  arch/x86/lib/mrccache.c | 8 +---
>  1 file changed, 5 insertions(+), 3 deletions(-)
>
> diff --git a/arch/x86/lib/mrccache.c b/arch/x86/lib/mrccache.c
> index 67bace4..eca88ac 100644
> --- a/arch/x86/lib/mrccache.c
> +++ b/arch/x86/lib/mrccache.c
> @@ -198,11 +198,13 @@ int mrccache_get_region(struct udevice **devp, struct 
> mrc_region *entry)
>
> /* Find the flash chip within the SPI controller node */
> node = fdtdec_next_compatible(blob, 0, COMPAT_GENERIC_SPI_FLASH);
> -   if (node < 0)
> +   if (node < 0) {
> +   debug("%s: Cannot find SPI flash\n", __func__);
> return -ENOENT;
> +   }
>
> if (fdtdec_get_int_array(blob, node, "memory-map", reg, 2))
> -   return -FDT_ERR_NOTFOUND;
> +   return -EINVAL;
> entry->base = reg[0];
>
> /* Find the place where we put the MRC cache */
> @@ -211,7 +213,7 @@ int mrccache_get_region(struct udevice **devp, struct 
> mrc_region *entry)
> return -EPERM;
>
> if (fdtdec_get_int_array(blob, mrc_node, "reg", reg, 2))
> -   return -FDT_ERR_NOTFOUND;
> +   return -EINVAL;
> entry->offset = reg[0];
> entry->length = reg[1];
>
> --

Reviewed-by: Bin Meng 
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Re: [U-Boot] [PATCH 34/82] x86: fsp: Fix cast for 64-bit compilation

[Bin Meng]

Hi Simon,

On Mon, Sep 26, 2016 at 11:33 AM, Simon Glass  wrote:
> Fix a cast in get_next_hob() that causes warnings on 64-bit machines.
>
> Signed-off-by: Simon Glass 
> ---
>
>  arch/x86/include/asm/fsp/fsp_hob.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>

Reviewed-by: Bin Meng 

What about get_guid_hob_data() in the same file? I think it will cause
building warning too.

Regards,
Bin
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Re: [U-Boot] [PATCH 35/82] x86: Drop unused init_helper functions

[Bin Meng]

On Mon, Sep 26, 2016 at 11:33 AM, Simon Glass  wrote:
> Drop init_bd_struct_r() which is no-longer used. Also drop the declaration
> for init_func_spi() since this is now handled by generic board init.
>
> Signed-off-by: Simon Glass 
> ---
>
>  arch/x86/include/asm/init_helpers.h |  2 --
>  arch/x86/lib/init_helpers.c | 10 --
>  2 files changed, 12 deletions(-)
>

Reviewed-by: Bin Meng 
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Re: [U-Boot] [PATCH 33/82] x86: dts: Mark serial as needed before relocation

[Bin Meng]

Hi Simon,

On Mon, Sep 26, 2016 at 11:33 AM, Simon Glass  wrote:
> We almost always need the serial port before relocation, so mark it as such.
> This will ensure that it appears in the device tree for SPL, if used.
>
> Signed-off-by: Simon Glass 
> ---
>
>  arch/x86/dts/serial.dtsi | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/arch/x86/dts/serial.dtsi b/arch/x86/dts/serial.dtsi
> index 54c3faf..22f7b54 100644
> --- a/arch/x86/dts/serial.dtsi
> +++ b/arch/x86/dts/serial.dtsi
> @@ -1,5 +1,6 @@
>  / {
> serial: serial {
> +   u-boot,dm-pre-reloc;

The ns16550 driver already has the pre-relocation flag, why is this
still needed?

> compatible = "ns16550";
> reg = <0x3f8 8>;
> reg-shift = <0>;
> --

Regards,
Bin
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Re: [U-Boot] [PATCH 31/82] x86: ivybridge: Fix PCH power setup

[Bin Meng]

On Mon, Sep 26, 2016 at 11:33 AM, Simon Glass  wrote:
> At present pch_power_options() has the arguments to writel() around the
> wrong way. Fix this and update it to compile on 64-bit machines.
>
> Signed-off-by: Simon Glass 
> ---
>
>  arch/x86/cpu/ivybridge/lpc.c | 8 
>  1 file changed, 4 insertions(+), 4 deletions(-)
>

Reviewed-by: Bin Meng 
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Re: [U-Boot] [PATCH 32/82] x86: ivybridge: Tidy up enable_clock_gating() for 64-bit

[Bin Meng]

Hi Simon,

On Mon, Sep 26, 2016 at 11:33 AM, Simon Glass  wrote:
> Fix the hex case and remove unused brackets. Use -0U instead of ~0UL to

Should be: ~0U

> allow compilation on 64-bit machines.
>
> Signed-off-by: Simon Glass 
> ---
>
>  arch/x86/cpu/ivybridge/lpc.c | 8 
>  1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/arch/x86/cpu/ivybridge/lpc.c b/arch/x86/cpu/ivybridge/lpc.c
> index c564713..aef1206 100644
> --- a/arch/x86/cpu/ivybridge/lpc.c
> +++ b/arch/x86/cpu/ivybridge/lpc.c
> @@ -357,10 +357,10 @@ static void enable_clock_gating(struct udevice *pch)
> reg16 |= (1 << 2) | (1 << 11);
> dm_pci_write_config16(pch, GEN_PMCON_1, reg16);
>
> -   pch_iobp_update(pch, 0xEB007F07, ~0UL, (1 << 31));
> -   pch_iobp_update(pch, 0xEB004000, ~0UL, (1 << 7));
> -   pch_iobp_update(pch, 0xEC007F07, ~0UL, (1 << 31));
> -   pch_iobp_update(pch, 0xEC004000, ~0UL, (1 << 7));
> +   pch_iobp_update(pch, 0xeb007f07, ~0U, 1 << 31);
> +   pch_iobp_update(pch, 0xeb004000, ~0U, 1 << 7);
> +   pch_iobp_update(pch, 0xec007f07, ~0U, 1 << 31);
> +   pch_iobp_update(pch, 0xec004000, ~0U, 1 << 7);
>
> reg32 = readl(RCB_REG(CG));
> reg32 |= (1 << 31);
> --

Reviewed-by: Bin Meng 
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Re: [U-Boot] [PATCH 29/82] x86: ivybridge: Add more debugging for failures

[Bin Meng]

Hi Simon,

On Mon, Sep 26, 2016 at 11:33 AM, Simon Glass  wrote:
> Add various debug() messages in places where errors occur. This aids with
> debugging.
>
> Signed-off-by: Simon Glass 
> ---
>
>  arch/x86/cpu/ivybridge/cpu.c   |  4 +++-
>  arch/x86/cpu/ivybridge/sdram.c | 36 +++-
>  2 files changed, 30 insertions(+), 10 deletions(-)
>
> diff --git a/arch/x86/cpu/ivybridge/cpu.c b/arch/x86/cpu/ivybridge/cpu.c
> index 85e361a..9d7c21d 100644
> --- a/arch/x86/cpu/ivybridge/cpu.c
> +++ b/arch/x86/cpu/ivybridge/cpu.c
> @@ -169,8 +169,10 @@ int print_cpuinfo(void)
>
> /* Enable SPD ROMs and DDR-III DRAM */
> ret = uclass_first_device_err(UCLASS_I2C, );
> -   if (ret)
> +   if (ret) {
> +   debug("%s: Failed to get I2C\n", __func__);
> return ret;
> +   }
>
> /* Prepare USB controller early in S3 resume */
> if (boot_mode == PEI_BOOT_RESUME) {
> diff --git a/arch/x86/cpu/ivybridge/sdram.c b/arch/x86/cpu/ivybridge/sdram.c
> index e0b06b5..eef6d78 100644
> --- a/arch/x86/cpu/ivybridge/sdram.c
> +++ b/arch/x86/cpu/ivybridge/sdram.c
> @@ -207,8 +207,10 @@ static int copy_spd(struct udevice *dev, struct pei_data 
> *peid)
> int ret;
>
> ret = mrc_locate_spd(dev, sizeof(peid->spd_data[0]), );
> -   if (ret)
> +   if (ret) {
> +   debug("%s: Could not locate SPD\n", __func__);
> return ret;
> +   }
>
> memcpy(peid->spd_data[0], data, sizeof(peid->spd_data[0]));
>
> @@ -460,18 +462,26 @@ int dram_init(void)
>
> /* We need the pinctrl set up early */
> ret = syscon_get_by_driver_data(X86_SYSCON_PINCONF, );
> -   if (ret)
> +   if (ret) {
> +   debug("%s: Could not get pinconf\n", __func__);
> return ret;
> +   }
>
> ret = uclass_first_device_err(UCLASS_NORTHBRIDGE, );
> -   if (ret)
> +   if (ret) {
> +   debug("%s: Could not get northbridge\n", __func__);
> return ret;
> +   }
> ret = syscon_get_by_driver_data(X86_SYSCON_ME, _dev);
> -   if (ret)
> +   if (ret) {
> +   debug("%s: Could not get ME\n", __func__);
> return ret;
> +   }
> ret = copy_spd(dev, pei_data);
> -   if (ret)
> +   if (ret) {
> +   debug("%s: Could not get SPD\n", __func__);
> return ret;
> +   }
> pei_data->boot_mode = gd->arch.pei_boot_mode;
> debug("Boot mode %d\n", gd->arch.pei_boot_mode);
> debug("mrc_input %p\n", pei_data->mrc_input);
> @@ -498,19 +508,27 @@ int dram_init(void)
>
> /* Wait for ME to be ready */
> ret = intel_early_me_init(me_dev);
> -   if (ret)
> +   if (ret) {
> +   debug("%s: Could not init ME\n", __func__);
> return ret;
> +   }
> ret = intel_early_me_uma_size(me_dev);
> -   if (ret < 0)
> +   if (ret < 0) {
> +   debug("%s: Could not get UMA size\n", __func__);
> return ret;
> +   }
>
> ret = mrc_common_init(dev, pei_data, false);
> -   if (ret)
> +   if (ret) {
> +   debug("%s: mrc_common_init() failed\n", __func__);
> return ret;
> +   }
>
> ret = sdram_find(dev);
> -   if (ret)
> +   if (ret) {
> +   debug("%s: sdram_find() failed\n", __func__);
> return ret;
> +   }
> gd->ram_size = gd->arch.meminfo.total_32bit_memory;
>
> debug("MRC output data length %#x at %p\n", pei_data->mrc_output_len,
> --

How about output the return value as well?

Regards,
Bin
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Re: [U-Boot] [PATCH 30/82] x86: ivybridge: Fix types for 64-bit compilation

[Bin Meng]

Hi Simon,

On Mon, Sep 26, 2016 at 11:33 AM, Simon Glass  wrote:
> Fix a few types that causes warnings on 64-bit machines.
>
> Signed-off-by: Simon Glass 
> ---
>
>  arch/x86/cpu/ivybridge/gma.c  | 2 +-
>  arch/x86/cpu/ivybridge/sata.c | 4 ++--
>  2 files changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/arch/x86/cpu/ivybridge/gma.c b/arch/x86/cpu/ivybridge/gma.c
> index 59866bd..cf0c91d 100644
> --- a/arch/x86/cpu/ivybridge/gma.c
> +++ b/arch/x86/cpu/ivybridge/gma.c
> @@ -831,7 +831,7 @@ int gma_func0_init(struct udevice *dev)
> mtrr_add_request(MTRR_TYPE_WRCOMB, base, 256 << 20);
> mtrr_commit(true);
>
> -   gtt_bar = (void *)dm_pci_read_bar32(dev, 0);
> +   gtt_bar = (void *)(ulong)dm_pci_read_bar32(dev, 0);
> debug("GT bar %p\n", gtt_bar);
> ret = gma_pm_init_pre_vbios(gtt_bar, rev);
> if (ret)
> diff --git a/arch/x86/cpu/ivybridge/sata.c b/arch/x86/cpu/ivybridge/sata.c
> index 1ce8195..bf11d48 100644
> --- a/arch/x86/cpu/ivybridge/sata.c
> +++ b/arch/x86/cpu/ivybridge/sata.c
> @@ -54,7 +54,7 @@ static void bd82x6x_sata_init(struct udevice *dev, struct 
> udevice *pch)
>
> mode = fdt_getprop(blob, node, "intel,sata-mode", NULL);
> if (!mode || !strcmp(mode, "ahci")) {
> -   u32 abar;
> +   ulong abar;
>
> debug("SATA: Controller in AHCI mode\n");
>
> @@ -73,7 +73,7 @@ static void bd82x6x_sata_init(struct udevice *dev, struct 
> udevice *pch)
>
> /* Initialize AHCI memory-mapped space */
> abar = dm_pci_read_bar32(dev, 5);
> -   debug("ABAR: %08X\n", abar);
> +   debug("ABAR: %08lx\n", abar);
> /* CAP (HBA Capabilities) : enable power management */
> reg32 = readl(abar + 0x00);
> reg32 |= 0x0c006000;  /* set PSC+SSC+SALP+SSS */
> --

This patch does not apply due to DM video conversion on Ivybridge.

Regards,
Bin
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Re: [U-Boot] [PATCH 28/82] x86: Don't export interrupt handlers with x86_64

[Bin Meng]

On Mon, Sep 26, 2016 at 11:33 AM, Simon Glass  wrote:
> We don't have a way of adjusting these at present so it is best to refuse to
> export these functions. This can be implemented later if the API is required.
>
> Signed-off-by: Simon Glass 
> ---
>
>  include/_exports.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>

Reviewed-by: Bin Meng 
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Re: [U-Boot] [PATCH 26/82] x86: ivybridge: Declare global data where it is used

[Bin Meng]

On Mon, Sep 26, 2016 at 11:33 AM, Simon Glass  wrote:
> Some files are missing this declaration. Add it to avoid build errors when
> we actually need the declaration.
>
> Signed-off-by: Simon Glass 
> ---
>
>  arch/x86/cpu/ivybridge/bd82x6x.c | 2 ++
>  arch/x86/cpu/ivybridge/gma.c | 2 ++
>  arch/x86/cpu/ivybridge/lpc.c | 2 ++
>  arch/x86/cpu/ivybridge/model_206ax.c | 2 ++
>  arch/x86/cpu/ivybridge/northbridge.c | 2 ++
>  5 files changed, 10 insertions(+)
>

Reviewed-by: Bin Meng 

> diff --git a/arch/x86/cpu/ivybridge/bd82x6x.c 
> b/arch/x86/cpu/ivybridge/bd82x6x.c
> index 5b58d6c..3c5e159 100644
> --- a/arch/x86/cpu/ivybridge/bd82x6x.c
> +++ b/arch/x86/cpu/ivybridge/bd82x6x.c
> @@ -21,6 +21,8 @@
>  #include 
>  #include 
>
> +DECLARE_GLOBAL_DATA_PTR;
> +
>  #define GPIO_BASE  0x48
>  #define BIOS_CTRL  0xdc
>
> diff --git a/arch/x86/cpu/ivybridge/gma.c b/arch/x86/cpu/ivybridge/gma.c
> index 37e2e6e..59866bd 100644
> --- a/arch/x86/cpu/ivybridge/gma.c
> +++ b/arch/x86/cpu/ivybridge/gma.c
> @@ -19,6 +19,8 @@
>  #include 
>  #include 
>
> +DECLARE_GLOBAL_DATA_PTR;
> +

But I think this is not needed since gma.c has been dropped due to DM
video conversion.

>  struct gt_powermeter {
> u16 reg;
> u32 value;
> diff --git a/arch/x86/cpu/ivybridge/lpc.c b/arch/x86/cpu/ivybridge/lpc.c
> index 4e0be2a..0b4343a 100644
> --- a/arch/x86/cpu/ivybridge/lpc.c
> +++ b/arch/x86/cpu/ivybridge/lpc.c
> @@ -20,6 +20,8 @@
>  #include 
>  #include 
>
> +DECLARE_GLOBAL_DATA_PTR;
> +
>  #define NMI_OFF0
>
>  #define ENABLE_ACPI_MODE_IN_COREBOOT   0
> diff --git a/arch/x86/cpu/ivybridge/model_206ax.c 
> b/arch/x86/cpu/ivybridge/model_206ax.c
> index 38e244b..ae7c540 100644
> --- a/arch/x86/cpu/ivybridge/model_206ax.c
> +++ b/arch/x86/cpu/ivybridge/model_206ax.c
> @@ -23,6 +23,8 @@
>  #include 
>  #include 
>
> +DECLARE_GLOBAL_DATA_PTR;
> +
>  static void enable_vmx(void)
>  {
> struct cpuid_result regs;
> diff --git a/arch/x86/cpu/ivybridge/northbridge.c 
> b/arch/x86/cpu/ivybridge/northbridge.c
> index 491f289..94f31c4 100644
> --- a/arch/x86/cpu/ivybridge/northbridge.c
> +++ b/arch/x86/cpu/ivybridge/northbridge.c
> @@ -19,6 +19,8 @@
>  #include 
>  #include 
>
> +DECLARE_GLOBAL_DATA_PTR;
> +
>  int bridge_silicon_revision(struct udevice *dev)
>  {
> struct cpuid_result result;
> --

Regards,
Bin
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Re: [U-Boot] [PATCH 27/82] x86: i2c: Fix cast of address to 32-bit value

[Bin Meng]

On Mon, Sep 26, 2016 at 11:33 AM, Simon Glass  wrote:
> This gives a build warning on 64-bit x86. Fix it.
>
> Signed-off-by: Simon Glass 
> ---
>
>  drivers/i2c/intel_i2c.c | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
>

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Re: [U-Boot] [PATCH 22/82] x86: Correct address casts in interrupt code

[Bin Meng]

On Mon, Sep 26, 2016 at 11:33 AM, Simon Glass  wrote:
> We should cast an address to unsigned long, not u32.
>
> Signed-off-by: Simon Glass 
> ---
>
>  arch/x86/cpu/interrupts.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>

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Re: [U-Boot] [PATCH 21/82] x86: Correct address casts in cpu code

[Bin Meng]

On Mon, Sep 26, 2016 at 11:33 AM, Simon Glass  wrote:
> We should cast an address to unsigned long, not u32.
>
> Signed-off-by: Simon Glass 
> ---
>
>  arch/x86/cpu/cpu.c | 10 --
>  1 file changed, 4 insertions(+), 6 deletions(-)
>

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Re: [U-Boot] [PATCH 18/82] usb: pci: Fix cast for 64-bit compilation

[Bin Meng]

On Mon, Sep 26, 2016 at 11:33 AM, Simon Glass  wrote:
> Fix a cast that causes warnings on 64-bit machines.
>
> Signed-off-by: Simon Glass 
> ---
>
>  drivers/usb/host/ehci-pci.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>

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Re: [U-Boot] [PATCH 20/82] x86: Allow interrupts to be disabled in 64-bit mode

[Bin Meng]

On Mon, Sep 26, 2016 at 11:33 AM, Simon Glass  wrote:
> Update the code to support both 32-bit and 64-bit modes.
>
> Signed-off-by: Simon Glass 
> ---
>
>  arch/x86/cpu/interrupts.c | 5 -
>  1 file changed, 4 insertions(+), 1 deletion(-)
>

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Re: [U-Boot] [PATCH 19/82] video: Use ulong for video frame buffer address

[Bin Meng]

On Mon, Sep 26, 2016 at 11:33 AM, Simon Glass  wrote:
> Change this type from int to ulong to avoid warnings on 64-bit machines.
>
> Signed-off-by: Simon Glass 
> ---
>
>  include/video_fb.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/include/video_fb.h b/include/video_fb.h
> index b008853..4a4fd5f 100644
> --- a/include/video_fb.h
> +++ b/include/video_fb.h
> @@ -38,7 +38,7 @@ typedef struct graphic_device {
>  unsigned int dprBase;
>  unsigned int vprBase;
>  unsigned int cprBase;
> -unsigned int frameAdrs;
> +unsigned long frameAdrs;
>  unsigned int memSize;
>  unsigned int mode;
>  unsigned int gdfIndex;
> --

I suspect this patch is not needed after this series:
http://lists.denx.de/pipermail/u-boot/2016-October/269561.html

Regards,
Bin
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Re: [U-Boot] [PATCH 06/82] elf: Add the Elf64_Rela type

[Bin Meng]

On Mon, Sep 26, 2016 at 11:33 AM, Simon Glass  wrote:
> Add this so that we can support 64-bit relocation on x86.
>
> Signed-off-by: Simon Glass 
> ---
>
>  include/elf.h | 6 ++
>  1 file changed, 6 insertions(+)
>

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Re: [U-Boot] [PATCH 17/82] tpm: Tidy up use of size_t

[Bin Meng]

On Mon, Sep 26, 2016 at 11:33 AM, Simon Glass  wrote:
> We should consistently use %z with size_t, and avoid passing a uint32_t as
> a size_t value. Fix these issues to avoid warnings on 64-bit machines.
>
> Signed-off-by: Simon Glass 
> ---
>
>  drivers/tpm/tpm_tis_lpc.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>

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Re: [U-Boot] [PATCH 08/82] rtc: Use CONFIG_X86 instead of __I386__

[Bin Meng]

On Mon, Sep 26, 2016 at 11:33 AM, Simon Glass  wrote:
> For 64-bit x86, __I386__ should perhaps not be defined. It is not clear from
> the definition, but let's use CONFIG_X86 to be sure.
>
> Signed-off-by: Simon Glass 
> ---
>
>  drivers/rtc/mc146818.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>

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Re: [U-Boot] [PATCH 09/82] spl: spi: Add a debug message if loading fails

[Bin Meng]

Hi Simon,

On Mon, Sep 26, 2016 at 11:33 AM, Simon Glass  wrote:
> This currently fails silently. Add a debug message to aid debugging.
>
> Signed-off-by: Simon Glass 
> ---
>
>  common/spl/spl_spi.c | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/common/spl/spl_spi.c b/common/spl/spl_spi.c
> index a3caafb..3f400eb 100644
> --- a/common/spl/spl_spi.c
> +++ b/common/spl/spl_spi.c
> @@ -96,8 +96,10 @@ static int spl_spi_load_image(struct spl_image_info 
> *spl_image,
> /* Load u-boot, mkimage header is 64 bytes. */
> err = spi_flash_read(flash, CONFIG_SYS_SPI_U_BOOT_OFFS, 0x40,
>  (void *)header);
> -   if (err)
> +   if (err) {
> +   debug("%s: Failed to read from SPI flash\n", 
> __func__);

How about output the err num as well?

> return err;
> +   }
>
> if (IS_ENABLED(CONFIG_SPL_LOAD_FIT)) {
> struct spl_load_info load;
> --

Regards,
Bin
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Re: [U-Boot] [PATCH 05/82] console: Don't enable CONFIG-CONSOLE_MUX, etc. in SPL

[Bin Meng]

Hi Simon,

Typo of CONFIG-CONSOLE_MUX in the commit title.

On Mon, Sep 26, 2016 at 11:33 AM, Simon Glass  wrote:
> CONFIG_CONSOLE_MUX and CONFIG_SYS_CONSOLE_IS_IN_ENV are not applicable
> for SPL. Update the console code to use CONFIG_IS_ENABLED(), so that these
> options will be inactive in SPL.

I don't understand, what's the difference between CONFIG_IS_ENABLE() and #ifdef?

>
> Signed-off-by: Simon Glass 
> ---
>
>  common/console.c | 30 +++---
>  1 file changed, 15 insertions(+), 15 deletions(-)
>

[snip]

Regards,
Bin
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Re: [U-Boot] [PATCH 04/82] board_f: Drop the extra fdtdec_prepare_fdt()

[Bin Meng]

On Mon, Sep 26, 2016 at 11:33 AM, Simon Glass  wrote:
> This is already called earlier, from fdtdec_setup(), so drop this unnecessary
> call from the init sequence.
>
> Signed-off-by: Simon Glass 
> ---
>
>  common/board_f.c | 3 ---
>  1 file changed, 3 deletions(-)
>

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Re: [U-Boot] [PATCH 02/82] Add _image_binary_end section declaration

[Bin Meng]

On Mon, Sep 26, 2016 at 11:33 AM, Simon Glass  wrote:
> This is used in some link scripts, so add a declaration for it.
>
> Signed-off-by: Simon Glass 
> ---
>
>  include/asm-generic/sections.h | 1 +
>  1 file changed, 1 insertion(+)
>

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Re: [U-Boot] [PATCH 03/82] bios_emulator: Fix cast for 64-bit compilation

[Bin Meng]

On Mon, Sep 26, 2016 at 11:33 AM, Simon Glass  wrote:
> Fix a cast that causes warnings on 64-bit machines.
>
> Signed-off-by: Simon Glass 
> ---
>
>  drivers/bios_emulator/atibios.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>

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Re: [U-Boot] [PATCH v2] fs:When 'go' run the program by 'fatload', added the cache flush to prevent cache mismatch.

[yoko]

Dear Jim,

Thank you very much.

I read the Wiki page.
I was running to load the standalone application program.
CPU is so ARM, there is instruction and data caches.

As in the Wiki of example, a program that was loaded with 'loads' command
was able to run.
However, when I loaded in the same program the 'fatload' command, it could
not be executed.

When I look at the source program, in the 'loads' command has been executed
cache flush.
But, in the 'fatload' command, cache flash was not executed.

So, I created this patch.

Thanks.

---
yoko


2016-10-10 22:26 GMT+09:00 James Chargin :

> Dear yoko,
>
> On 10/07/2016 08:20 PM, yoko wrote:
>
>> Signed-off-by: yoko 
>> ---
>>
>> Changes for v2:
>>- The commit message is changed.
>>
>>  fs/fs.c | 3 ++-
>>  1 file changed, 2 insertions(+), 1 deletion(-)
>>
>> diff --git a/fs/fs.c b/fs/fs.c
>> index 595ff1f..7607230 100644
>> --- a/fs/fs.c
>> +++ b/fs/fs.c
>> @@ -417,6 +417,8 @@ int do_load(cmd_tbl_t *cmdtp, int flag, int argc,
>> char * const argv[],
>> }
>> puts("\n");
>>
>> +   flush_cache(addr, len_read);
>> +
>> setenv_hex("fileaddr", addr);
>> setenv_hex("filesize", len_read);
>>
>> @@ -535,4 +537,3 @@ int do_fs_type(cmd_tbl_t *cmdtp, int flag, int argc,
>> char * const argv[])
>>
>> return CMD_RET_SUCCESS;
>>  }
>> -
>>
>>
> The wiki includes information about cache considerations for the "go"
> command [1]. If possible, please check that information to be sure it
> remains consistent with this patch.
>
> Thanks,
> Jim
>
> [1] http://www.denx.de/wiki/view/DULG/UBootStandalone#Section_5.12.3.
> --
> Jim Chargin
> AJA Video Systems   j...@aja.com
> (530) 271-3334  http://www.aja.com
>
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Re: [U-Boot] [PATCH 4/5] sf: Add status register protect for Winbond

[Bin Meng]

On Tue, Oct 11, 2016 at 2:58 AM, George McCollister
 wrote:
> Winbond parts such as W25Q64FV and Spansion parts such as S25FL128S
> support two status register protection bits. Implement sr_protect for
> Winbond and Spansion devices.
>
>  ---
>  | SRP1 | SRP0 | Method   | Description|
>  -|-
>  | 0| 0| Software | Blocked until write enable |
>  | 0| 1| Hardware | Blocked if WP pin is low   |
>  | 1| 0| Power| Blocked until power down   |
>  | 1| 1| OTP  | Blocked permanently|
>  ---
>
> Not all devices support OTP.
>
> Signed-off-by: George McCollister 
> ---
>  drivers/mtd/spi/sf_internal.h |  1 +
>  drivers/mtd/spi/spi_flash.c   | 57 
> +++
>  2 files changed, 58 insertions(+)
>

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Re: [U-Boot] [PATCH 5/5] sf: Add sr-protect sub-command

[Bin Meng]

On Tue, Oct 11, 2016 at 2:58 AM, George McCollister
 wrote:
> Add an sf sub-command named sr-protect which allows the status register
> protection method to be changed.
>
> Valid settings are software, hardware, power and otp.
>
> Signed-off-by: George McCollister 
> ---
>  cmd/sf.c | 28 
>  1 file changed, 28 insertions(+)
>

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Re: [U-Boot] [PATCH 2/5] sf: Add status register protect for STMICRO, SST

[Bin Meng]

On Tue, Oct 11, 2016 at 2:57 AM, George McCollister
 wrote:
> STMICRO parts such as M25PX64 and SST parts such as SST26VF032B support
> a single status register protect bit. When set this bit cause writes to
> the status register to be blocked when the write protect signal is low.
>
> Implement sr_protect for these devices.
>
> Signed-off-by: George McCollister 
> ---
>  drivers/mtd/spi/sf_internal.h |  1 +
>  drivers/mtd/spi/spi_flash.c   | 35 +++
>  2 files changed, 36 insertions(+)
>

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Re: [U-Boot] [PATCH 3/5] sf: Use stm_lock/unlock for Spansion and Winbond

[Bin Meng]

On Tue, Oct 11, 2016 at 2:57 AM, George McCollister
 wrote:
> Spansion parts such as S25FL128S and Winbond parts such as W25Q64FV
> support the block protection mechanism implemented as
> stm_lock() and stm_unlock(). Use stm_lock() and stm_unlock() for
> Spansion and Winbond devices.
>
> Signed-off-by: George McCollister 
> ---
>  drivers/mtd/spi/spi_flash.c | 11 ++-
>  1 file changed, 10 insertions(+), 1 deletion(-)
>

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Re: [U-Boot] [PATCH 1/5] sf: Add status register protection mechanism

[Bin Meng]

On Tue, Oct 11, 2016 at 2:57 AM, George McCollister
 wrote:
> Many SPI NOR flash devices support status register protection through
> one or two status register protection bits. Status register protection
> enables protection of block protect and other bits from manipulation.
>
> So far, four different status register protection methods have been
> observed:
>
>  Software - Writes to the status register are blocked until
> a write enable bit is set by software.
>  Hardware - Writes to the status register are blocked while
> a pin is in a certain state.
>  Power- Writes to the status register are blocked until
> the next power-down.
>  One Time Program - Writes to the status register are permanently
> blocked.
>
> Signed-off-by: George McCollister 
> ---
>  include/spi_flash.h | 17 +
>  1 file changed, 17 insertions(+)
>

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Re: [U-Boot] build error with CONFIG_DM_PCI disabled in menuconfig

[Bin Meng]

On Mon, Oct 10, 2016 at 11:47 PM, Ding, ChiX  wrote:
> Hi there
> I disabled CONFIG_DM_PCI in menuconfig because I have problem detecting AHCI 
> SCSI controller on X86 board
> with CONFIG_DM_PCI enabled and the older code in drivers/pci/pci.c works for 
> me in the previous U-boot version.
> Then I got the build error :
> u-boot/arch/x86/cpu/irq.c:29: undefined reference to `dm_pci_read_config8'
> u-boot/arch/x86/cpu/irq.c:104: undefined reference to `dm_pci_get_bdf'
> u-boot/arch/x86/cpu/irq.c:147: undefined reference to `dm_pci_read_config32'
> u-boot/arch/x86/cpu/pci.c:69: undefined reference to `pci_read_config16'
> u-boot/arch/x86/cpu/pci.c:73: undefined reference to `pci_read_config8'
> u-boot/arch/x86/cpu/pci.c:86: undefined reference to `pci_write_config8'
> u-boot/arch/x86/lib/bios_interrupts.c:137: undefined reference to 
> `dm_pci_find_device'
> u-boot/arch/x86/lib/bios_interrupts.c:141: undefined reference to 
> `dm_pci_get_bdf'
>
> It seems that the code refers to the DM_PCI code regardless if  CONFIG_DM_PCI 
> is enabled or not.
> Is it ok to build U-boot with CONFIG_DM_PCI disabled or  did I miss anything?
>

x86 has been fully converted to DM PCI, so legacy PCI driver is not
supported now.

Which board are you using? Can you debug why AHCI does not work with DM PCI?

Regards,
Bin
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Re: [U-Boot] [PATCH v2] cmd: cros_ec: Move crosec commands to cmd subdirectory

[Simon Glass]

On 4 October 2016 at 18:08, Moritz Fischer  wrote:
> Move crosec commands from drivers/misc/cros_ec.c to
> cmd/cros_ec.c
>
> Acked-by: Simon Glass 
> Signed-off-by: Moritz Fischer 
> Cc: Simon Glass 
> Cc: Heiko Schocher 
> Cc: Bin Meng 
> Cc: Miao Yan 
> Cc: Masahiro Yamada 
> Cc: Stefan Roese 
> Cc: Przemyslaw Marczak 
> Cc: Maxime Ripard 
> Cc: Nishanth Menon 
> Cc: u-boot@lists.denx.de
>
> ---
> Changes from v1:
>
> - Default to build CMD_CROS_EC in when CROS_EC is activated
> - Get rid of leftover const ec_current_image_name[] artifact from
>   moving stuff to separate file
> - Added Simon's Acked-By:
>
> ---
>  cmd/Kconfig|  13 ++
>  cmd/Makefile   |   1 +
>  cmd/cros_ec.c  | 366 
> +
>  drivers/misc/cros_ec.c | 351 ---
>  include/cros_ec.h  |  11 ++
>  5 files changed, 391 insertions(+), 351 deletions(-)
>  create mode 100644 cmd/cros_ec.c

Applied to u-boot-dm, thanks!
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Re: [U-Boot] [PATCH] sandbox: Use the address in readl/writel() functions

[Simon Glass]

On 1 October 2016 at 14:42, Simon Glass  wrote:
> At present these functions do not touch addr, which can raising warnings
> about unused variables.
>
> This fixes the following warnings:
>
> sandbox_spl defconfig
> drivers/core/regmap.c: In function ‘regmap_read’:
> drivers/core/regmap.c:125:12: warning: unused variable ‘ptr’ 
> [-Wunused-variable]
>   uint32_t *ptr = map_physmem(map->base + offset, 4, MAP_NOCACHE);
> ^
> drivers/core/regmap.c: In function ‘regmap_write’:
> drivers/core/regmap.c:134:12: warning: unused variable ‘ptr’ 
> [-Wunused-variable]
>   uint32_t *ptr = map_physmem(map->base + offset, 4, MAP_NOCACHE);
>
> Signed-off-by: Simon Glass 
> Fixes: 3bfb8cb4 (dm: regmap: Implement simple regmap_read & regmap_write)
> ---
>
>  arch/sandbox/include/asm/io.h | 12 ++--
>  1 file changed, 6 insertions(+), 6 deletions(-)

Applied to u-boot-dm
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Re: [U-Boot] [PATCH 3/5] sandbox/fs: Use correct size path name buffer

[Simon Glass]

On 3 October 2016 at 15:50, Simon Glass  wrote:
> On 1 October 2016 at 12:41, Stefan Brüns  wrote:
>> The readdir linux manpage explicitly states (quoting POSIX.1) that
>> sizeof(d_name) is not correct for determining the required size, but to
>> always use strlen. Grow the buffer if needed.
>>
>> Signed-off-by: Stefan Brüns 
>> ---
>>  arch/sandbox/cpu/os.c | 13 ++---
>>  1 file changed, 10 insertions(+), 3 deletions(-)
>
> Acked-by: Simon Glass 

Applied to u-boot-dm, thanks!
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Re: [U-Boot] [PATCH 2/5] sandbox/fs: Make linking of nodes in os_dirent_ls more obvious

[Simon Glass]

On 3 October 2016 at 15:49, Simon Glass  wrote:
> On 1 October 2016 at 12:41, Stefan Brüns  wrote:
>> Previously, after reading/creating the second dirent, the second entry
>> would be chained to the first entry and the first entry would be linked
>> to head. Instead, immediately link the first entry to head.
>>
>> Signed-off-by: Stefan Brüns 
>> ---
>>  arch/sandbox/cpu/os.c | 4 ++--
>>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> Acked-by: Simon Glass 

Applied to u-boot-dm, thanks!
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Re: [U-Boot] [PATCH 5/5] sandbox/fs: Use readdir instead of deprecated readdir_r

[Simon Glass]

On 3 October 2016 at 15:50, Simon Glass  wrote:
> On 1 October 2016 at 12:41, Stefan Brüns  wrote:
>> Using readdir_r limits the maximum file name length and may even be
>> unsafe, and is thus deprecated in since glibc 2.24.
>>
>> Signed-off-by: Stefan Brüns 
>> ---
>>  arch/sandbox/cpu/os.c | 19 +++
>>  1 file changed, 11 insertions(+), 8 deletions(-)
>
> Acked-by: Simon Glass 

Applied to u-boot-dm, thanks!
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Re: [U-Boot] [PATCH v2 4/5] sandbox/fs: Set correct filetype for unknown filetype

[Simon Glass]

On 4 October 2016 at 13:46, Stefan Brüns  wrote:
> The "hostfs ls" command prefixes each directory entry with either DIR,
> LNK or "   " if it is a directory, symlink resp. regular file, or
> "???" for any other or unknown type.
> The latter only works if the type is set correctly, as the entry defaults
> to OS_FILET_REG and e.g. socket files show up as regular files.
>
> Signed-off-by: Stefan Brüns 
> Acked-by: Simon Glass 
> ---
>  arch/sandbox/cpu/os.c | 2 ++
>  1 file changed, 2 insertions(+)

Applied to u-boot-dm, thanks!
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Re: [U-Boot] [PATCH v6 6/6] configs: am57xx_evm_defconfig: Enable CMD_REG option

[Simon Glass]

On 30 September 2016 at 20:17, Tom Rini  wrote:
> On Fri, Sep 30, 2016 at 09:20:47AM +0530, Keerthy wrote:
>
>> Enable CMD_REG option.
>>
>> Signed-off-by: Keerthy 
>
> Reviewed-by: Tom Rini 

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Re: [U-Boot] [PATCH 1/5] sandbox/fs: Free memory allocated by os_dirent_ls

[Simon Glass]

\On 3 October 2016 at 15:49, Simon Glass  wrote:
> On 1 October 2016 at 12:41, Stefan Brüns  wrote:
>> Signed-off-by: Stefan Brüns 
>> ---
>>  fs/sandbox/sandboxfs.c |  1 +
>>  include/os.h   | 11 ++-
>>  2 files changed, 11 insertions(+), 1 deletion(-)
>
> Acked-by: Simon Glass 

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Re: [U-Boot] [PATCH v3 2/2] power: regulator: lp873x: Add regulator support

[Simon Glass]

On 29 September 2016 at 22:04, Keerthy  wrote:
> The driver provides regulator set/get voltage
> enable/disable functions for lp873x family of PMICs.
>
> Signed-off-by: Keerthy 
> Reviewed-by: Simon Glass 
> ---
> Changes in v2:
>
>   * Used pmic_reg_read/pmic_reg_write instead of direct i2c
> read/write calls.
>
>  drivers/power/regulator/Kconfig|   8 +
>  drivers/power/regulator/Makefile   |   1 +
>  drivers/power/regulator/lp873x_regulator.c | 357 
> +
>  3 files changed, 366 insertions(+)
>  create mode 100644 drivers/power/regulator/lp873x_regulator.c

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Re: [U-Boot] [PATCH v6 4/6] configs: dra7xx_evm_defconfig: Enable PALMAS options

[Simon Glass]

On 29 September 2016 at 21:50, Keerthy  wrote:
> Enable palmas PMIC config options.
>
> Signed-off-by: Keerthy 
> Reviewed-by: Tom Rini 
> ---
>  configs/dra7xx_evm_defconfig | 3 +++
>  1 file changed, 3 insertions(+)

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Re: [U-Boot] [PATCH v6 5/6] configs: am57xx_evm_defconfig: Enable PALMAS options

[Simon Glass]

On 29 September 2016 at 21:50, Keerthy  wrote:
> Enable palmas PMIC config options.
>
> Signed-off-by: Keerthy 
> Reviewed-by: Tom Rini 
> ---
>  configs/am57xx_evm_defconfig | 3 +++
>  1 file changed, 3 insertions(+)

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Re: [U-Boot] [PATCH v3 1/2] power: pmic: lp873x: Add the base pmic support

[Simon Glass]

On 29 September 2016 at 22:04, Keerthy  wrote:
> Add support to bind the regulators/child nodes with the pmic.
>
> Signed-off-by: Keerthy 
> Reviewed-by: Simon Glass 
> ---
>
> Changes in v3:
>
>   * Used dm_i2c_write and dm_i2c_read in place of dm_i2c_reg_write
> dm_i2c_reg_read respectively.
>
> Changes in v2:
>
>   * Added pmic read/write functions.
>
>  drivers/power/pmic/Kconfig  |  7 
>  drivers/power/pmic/Makefile |  1 +
>  drivers/power/pmic/lp873x.c | 86 
> +
>  include/power/lp873x.h  | 19 ++
>  4 files changed, 113 insertions(+)
>  create mode 100644 drivers/power/pmic/lp873x.c
>  create mode 100644 include/power/lp873x.h

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Re: [U-Boot] [PATCH v6 3/6] power: regulator: palmas: Add regulator support

[Simon Glass]

On 29 September 2016 at 21:50, Keerthy  wrote:
> The driver provides regulator set/get voltage
> enable/disable functions for palmas family of PMICs.
>
> Signed-off-by: Keerthy 
> Reviewed-by: Simon Glass 
> Reviewed-by: Tom Rini 
> ---
>
> Changes in v5:
>
>   * Used pmic_reg_read pmic_reg_write functions instead of
> direct i2c calls.
>
>  drivers/power/regulator/Kconfig|   8 +
>  drivers/power/regulator/Makefile   |   1 +
>  drivers/power/regulator/palmas_regulator.c | 453 
> +
>  3 files changed, 462 insertions(+)
>  create mode 100644 drivers/power/regulator/palmas_regulator.c

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Re: [U-Boot] [PATCH v6 2/6] power: pmic: Palmas: Add the base pmic support

[Simon Glass]

On 29 September 2016 at 21:50, Keerthy  wrote:
> Add support to bind the regulators/child nodes with the pmic.
> Also adds the pmic i2c based read/write funtions to access pmic
> registers.
>
> Signed-off-by: Keerthy 
> Reviewed-by: Simon Glass 
> Reviewed-by: Tom Rini 
> ---
> Changes in v6:
>
>   * Used dm_i2c_write and dm_i2c_read in place of dm_i2c_reg_write
> dm_i2c_reg_read respectively.
>
> Changes in v5:
>
>   * Added pmic read/write functions.
>
>  drivers/power/pmic/Kconfig  |   7 +++
>  drivers/power/pmic/Makefile |   1 +
>  drivers/power/pmic/palmas.c | 104 
> 
>  include/power/palmas.h  |  25 +++
>  4 files changed, 137 insertions(+)
>  create mode 100644 drivers/power/pmic/palmas.c
>  create mode 100644 include/power/palmas.h

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Re: [U-Boot] [PATCH v2] power: regulator: Add support for gpio regulators

[Simon Glass]

On 6 October 2016 at 08:28, Przemyslaw Marczak  wrote:
> Hello,
>
>
> On 10/05/2016 06:50 PM, Simon Glass wrote:
>>
>> Hi Keerthy,
>>
>> On 5 October 2016 at 05:58, Keerthy  wrote:
>>>
>>>
>>> On Monday 19 September 2016 06:29 AM, Simon Glass wrote:

 On 15 September 2016 at 05:34, Keerthy  wrote:
>
> Add support for gpio regulators. As of now this driver caters
> to gpio regulators with one gpio. Supports setting voltage values to
> gpio
> regulators and retrieving the values.
>
> Signed-off-by: Keerthy 
> ---
>
> Changes in v2:
>
>* Added states and voltages as part of plat data to have
>  a generic state to voltage mapping removing any assumptions.
>
>   drivers/power/regulator/Kconfig  |   8 ++
>   drivers/power/regulator/Makefile |   1 +
>   drivers/power/regulator/gpio-regulator.c | 137
> +++
>   include/power/regulator.h|   1 +
>   4 files changed, 147 insertions(+)
>   create mode 100644 drivers/power/regulator/gpio-regulator.c


 Reviewed-by: Simon Glass 
>>>
>>>
>>> Simon,
>>>
>>> Wanted to know who is pulling this patch.
>>
>> Looking in patchwork it is assigned to Przemyslaw.
>>
>> Regards,
>> Simon
>>
>>
>>
>
> I'm sorry for the silence, I have very limited time for open source at
> present, and now it's hard for me to watch the list.
> Simon, I will assign it to you in patchwork, since you have already done the
> review.

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Re: [U-Boot] [PATCH v6 1/6] power: regulator: Add ctrl_reg and volt_reg fields for pmic

[Simon Glass]

On 29 September 2016 at 21:50, Keerthy  wrote:
> The ctrl reg contains bit fields to enable and disable regulators,
> and volt_reg has the bit fields to configure the voltage values.
> The registers are frequently accessed hence make them part
> of dm_regulator_uclass_platdata structure.
>
> Signed-off-by: Keerthy 
> Reviewed-by: Tom Rini 
> Reviewed-by: Simon Glass 
> ---
>  include/power/regulator.h | 4 
>  1 file changed, 4 insertions(+)

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Re: [U-Boot] [PATCH] power: regulator: Add limits checking while setting voltage and current

[Simon Glass]

Hi Keerthy,

On 15 September 2016 at 05:16, Keerthy  wrote:
>
>
> On Thursday 15 September 2016 04:38 PM, Keerthy wrote:
>>
>>
>>
>> On Thursday 15 September 2016 04:26 PM, Przemyslaw Marczak wrote:
>>>
>>> Hello Keerthy,
>>>
>>> On 09/15/2016 10:54 AM, Keerthy wrote:

 Currently the specific set ops functions are directly
 called without any check for voltage/current limits for a regulator.
 Check for them and proceed.

 Signed-off-by: Keerthy 
 ---
   drivers/power/regulator/regulator-uclass.c | 10 ++
   1 file changed, 10 insertions(+)

 diff --git a/drivers/power/regulator/regulator-uclass.c
 b/drivers/power/regulator/regulator-uclass.c
 index 4434e36..089455e 100644
 --- a/drivers/power/regulator/regulator-uclass.c
 +++ b/drivers/power/regulator/regulator-uclass.c
 @@ -41,6 +41,11 @@ int regulator_get_value(struct udevice *dev)
   int regulator_set_value(struct udevice *dev, int uV)
   {
   const struct dm_regulator_ops *ops = dev_get_driver_ops(dev);
 +struct dm_regulator_uclass_platdata *uc_pdata;
 +
 +uc_pdata = dev_get_uclass_platdata(dev);
 +if (uV < uc_pdata->min_uV || uV > uc_pdata->max_uV)
 +return -EINVAL;
 if (!ops || !ops->set_value)
   return -ENOSYS;
 @@ -61,6 +66,11 @@ int regulator_get_current(struct udevice *dev)
   int regulator_set_current(struct udevice *dev, int uA)
   {
   const struct dm_regulator_ops *ops = dev_get_driver_ops(dev);
 +struct dm_regulator_uclass_platdata *uc_pdata;
 +
 +uc_pdata = dev_get_uclass_platdata(dev);
 +if (uA < uc_pdata->min_uA || uA > uc_pdata->max_uA)
 +return -EINVAL;
 if (!ops || !ops->set_current)
   return -ENOSYS;
>>>
>>>
>>> Adding those two checks will conflict with "force" option for
>>> cmd/regulator.c:283.
>>> There was value range checking in the command's code, but it was left
>>> unchecked
>>> for regulator direct calls.
>>>
>>> This change is good, but then maybe the "force" option should be removed
>>> from command,
>>> or API's prototypes should be updated by force flag argument?
>>>
>>> I assumed that this option could be useful for quick over-voltage
>>> setting (until reboot),
>>> since usually (min_uV == max_uV) - the voltage can't be changed in any
>>> range.
>>>
>>> The driver should take care about ignore it or not, however probably
>>> nobody used this.
>>>
>>> Of course this could potentially damage the device by wrong use,
>>> which can be also made by passing the force flag as an argument - by
>>> mistake.
>>>
>>> What do you thing about, update the dm_regulator_ops by:
>>>
>>>  - int (*set_value)(struct udevice *dev, int uV, int flag);
>>>  - int (*set_current)(struct udevice *dev, int uA, int flag);
>
>
> I personally do not like setting an extra flag everywhere just because we
> want to support force option.
>
> I would rather have 2 functions like:
>
> int (*force_set_value)(struct udevice *dev, int uV);
> int (*force_set_current)(struct udevice *dev, int uA);
>
> Where we can set the value ignoring the limits. But again that must be used
> with at most caution as setting higher voltages might end up damaging the
> device.

That seems OK to me.

>
>
>>>
>>> and also new flag to the present defined:
>>>
>>>  - REGULATOR_FLAG_FORCE = 1 << 2
>>>
>>> This requires more work, but will provide the functionality in a proper
>>> way.
>>
>>
>> I do not know cmd_regulator is the right place to check for min_uV and
>> max_uV. dm_regulator_uclass_platdata has both the limits and this i feel
>> is a perfectly valid check in generic place else we would be again
>> checking for the same condition in every possible regulator specific
>> drivers.
>>
>> As far as the force option is concerned that i believe is more for
>> testing and like you said can be implemented by setting a flag.
>>
>> Just take a simple case of say a driver like mmc which unknowingly
>> requests a wrong voltage and the base driver has no check against min
>> and max voltages and assuming the regulator driver goes ahead and sets a
>> very high voltage. That can be catastrophic right?

What is the status of this patch please?

Also it breaks tests (make tests) - can you please take a  look?

Regards,
Simon
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[U-Boot] Please pull u-boot-mmc

[Jaehoon Chung]

Dear Tom,

Could you these patches on u-boot/master?

The following changes since commit f5fd45ff64e28a73499548358e3d1ceda0de7daf:

  Merge branch 'master' of git://www.denx.de/git/u-boot-imx (2016-10-08 
09:33:37 -0400)

are available in the git repository at:

  http://git.denx.de/u-boot-mmc.git master

for you to fetch changes up to 57718f017b10871cd9dc03dca56c3bd690fc2614:

  mmc: Fix cast for 64-bit compilation (2016-10-11 07:46:11 +0900)


Jaehoon Chung (4):
  mmc: s5p_sdhci: support the Driver model for Exynos
  mmc: dw_mmc: remove the unnecessary arguments for dwmci_setup_cfg
  mmc: sdhci: use the host version value in sdhci_setup_cfg
  mmc: sdhci: use the generic error number

Simon Glass (1):
  mmc: Fix cast for 64-bit compilation

 drivers/mmc/atmel_sdhci.c |  1 -
 drivers/mmc/bcm2835_sdhci.c   |  3 +-
 drivers/mmc/dw_mmc.c  | 13 ---
 drivers/mmc/exynos_dw_mmc.c   |  3 +-
 drivers/mmc/ftsdc021_sdhci.c  |  2 +-
 drivers/mmc/kona_sdhci.c  | 11 ++
 drivers/mmc/msm_sdhci.c   |  3 --
 drivers/mmc/mv_sdhci.c|  6 +---
 drivers/mmc/pci_mmc.c |  2 +-
 drivers/mmc/rockchip_dw_mmc.c |  3 +-
 drivers/mmc/s5p_sdhci.c   | 80 ---
 drivers/mmc/sdhci.c   | 18 ++
 drivers/mmc/socfpga_dw_mmc.c  |  3 +-
 drivers/mmc/spear_sdhci.c |  5 ---
 drivers/mmc/zynq_sdhci.c  |  2 --
 include/dwmmc.h   |  8 ++---
 16 files changed, 105 insertions(+), 58 deletions(-)

Best Regards,
Jaehoon Chung
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Re: [U-Boot] [PATCH 07/82] mmc: Fix cast for 64-bit compilation

[Jaehoon Chung]

On 10/10/2016 03:56 PM, Bin Meng wrote:
> On Mon, Sep 26, 2016 at 11:33 AM, Simon Glass  wrote:
>> Fix a cast that causes warnings on 64-bit machines.
>>
>> Signed-off-by: Simon Glass 
>> ---
>>
>>  drivers/mmc/pci_mmc.c | 2 +-
>>  1 file changed, 1 insertion(+), 1 deletion(-)
>>
> 
> Reviewed-by: Bin Meng 

Applied on u-boot-mmc. Thanks!

Best Regards,
Jaehoon Chung

> 
> 
> 

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[U-Boot] Pull request, u-boot-tegra/master

[Tom Warren]

Tom,

Please pull u-boot-tegra/master into U-Boot/master. Thanks!

All Tegra builds are OK, and Stephen's automated test system reports that
all tests pass.

The following changes since commit f5fd45ff64e28a73499548358e3d1ceda0de7daf:

  Merge branch 'master' of git://www.denx.de/git/u-boot-imx (2016-10-08
09:33:37 -0400)

are available in the git repository at:

  git://git.denx.de/u-boot-tegra.git master

for you to fetch changes up to d40d69ee350b62af90c2b522e05cbb3eb5f27112:

  ARM: tegra: reduce DRAM size mapped into MMU on ARM64 (2016-10-10
11:00:03 -0700)


Marcel Ziswiler (5):
  tegra: usb gadget: fix ci udc operation if not hostpc capable
  simple panel: fix spelling of debug message
  regulator: fixed: honour optionality of enable gpio
  colibri_t20: fix display configuration
  colibri_t20: fix usb operation and controller order

Stephen Warren (1):
  ARM: tegra: reduce DRAM size mapped into MMU on ARM64

 arch/arm/dts/tegra20-colibri.dts  | 117
+++---
 arch/arm/mach-tegra/arm64-mmu.c   |   2 +-
 drivers/power/regulator/fixed.c   |  21 --
 drivers/video/simple_panel.c  |   2 +-
 include/configs/tegra-common-usb-gadget.h |   2 +
 5 files changed, 94 insertions(+), 50 deletions(-)
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Re: [U-Boot] [PATCH v2 2/6] apalis/colibri_t20/t30: deactivate displaying board info

[Stephen Warren]

On 10/05/2016 10:12 AM, Stefan Agner wrote:

On 2016-10-05 08:53, Stephen Warren wrote:

On 10/03/2016 02:27 PM, Stefan Agner wrote:

On 03.10.2016 10:28, Stephen Warren wrote:

On 09/30/2016 04:00 AM, Marcel Ziswiler wrote:

On Wed, 2016-09-28 at 12:00 -0600, Stephen Warren wrote:

On 09/28/2016 03:35 AM, Marcel Ziswiler wrote:


Avoid a checkboard() name clash with our upcoming custom
implementation
thereof.

If you want to avoid naming conflicts, please simply name your new
function something that doesn't conflict. That way it will avoid
confusion is someone actually wants to enable the
CONFIG_DISPLAY_BOARDINFO option themselves, plus it avoids taking
the
current feature set away.


No, it is not just any function. We do want our custom checkboard() to
be called upon boot and not the Tegra generic one just printing a hard
coded string.

I guess alternatively we could gate the checkboard() call
in arch/arm/mach-tegra/board2.c with a

#if !defined(CONFIG_CUSTOM_BOARDINFO)

just as introduced a while ago in common/board_info.c

http://git.denx.de/?p=u-boot.git;a=blob;f=common/board_info.c;h=bd5dcfa
066358c2cc44ce5d19fcc3e77d555cd09;hb=HEAD#l20

in order to not print the hard coded name from the device tree.


I'd prefer to keep the behaviour standard across all Tegra boards. If
you want to do additional actions in the checkboard() function, I
suggest making it call an optional additional function:

__weak int tegra_checkboard(void)
{
return 0;
}

int checkboard(void)
{
...
return tegra_checkboard();
}


Well that would print a message "Board: " ... twice, which is rather
strange.


Surely you simply make tegra_checkboard() not contain duplicate code?


What do you think of my idea?


I'd rather not introduce any more ifdefs, but instead have a single
path through the code-base.


Sorry, I was a bit unclear, with my other idea I meant the answer I sent
to patch 3/6 of this patchset:
http://lists.denx.de/pipermail/u-boot/2016-October/268669.html

It does remove a ifdef...


That's probably better than adding more ifdefs. It does have the 
disadvantage of not using the common show_board_info() or Tegra-wide 
checkboard() implementations though, which means that anything added 
there won't execute on all Tegras, which could potentially be confusing.

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[U-Boot] [PATCH 5/5] sf: Add sr-protect sub-command

[George McCollister]

Add an sf sub-command named sr-protect which allows the status register
protection method to be changed.

Valid settings are software, hardware, power and otp.

Signed-off-by: George McCollister 
---
 cmd/sf.c | 28 
 1 file changed, 28 insertions(+)

diff --git a/cmd/sf.c b/cmd/sf.c
index 65b117f..1a42bf6 100644
--- a/cmd/sf.c
+++ b/cmd/sf.c
@@ -380,6 +380,30 @@ static int do_spi_protect(int argc, char * const argv[])
return ret == 0 ? 0 : 1;
 }
 
+static int do_spi_sr_protect(int argc, char * const argv[])
+{
+   int ret;
+   enum srp_method method;
+
+   if (argc != 2)
+   return -1;
+
+   if (strcmp(argv[1], "software") == 0)
+   method = SRP_SOFTWARE;
+   else if (strcmp(argv[1], "hardware") == 0)
+   method = SRP_HARDWARE;
+   else if (strcmp(argv[1], "power") == 0)
+   method = SRP_POWER;
+   else if (strcmp(argv[1], "otp") == 0)
+   method = SRP_OTP;
+   else
+   return -1;  /* Unknown parameter */
+
+   ret = spi_flash_sr_protect(flash, method);
+
+   return ret == 0 ? 0 : 1;
+}
+
 #ifdef CONFIG_CMD_SF_TEST
 enum {
STAGE_ERASE,
@@ -574,6 +598,8 @@ static int do_spi_flash(cmd_tbl_t *cmdtp, int flag, int 
argc,
ret = do_spi_flash_erase(argc, argv);
else if (strcmp(cmd, "protect") == 0)
ret = do_spi_protect(argc, argv);
+   else if (strcmp(cmd, "sr-protect") == 0)
+   ret = do_spi_sr_protect(argc, argv);
 #ifdef CONFIG_CMD_SF_TEST
else if (!strcmp(cmd, "test"))
ret = do_spi_flash_test(argc, argv);
@@ -615,5 +641,7 @@ U_BOOT_CMD(
" or to start of mtd 
`partition'\n"
"sf protect lock/unlock sector len  - protect/unprotect 'len' bytes 
starting\n"
" at address 'sector'\n"
+   "sf sr-protect method   - set status register protect 
method to\n"
+   " software, hardware, power or 
otp\n"
SF_TEST_HELP
 );
-- 
2.9.3

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[U-Boot] [PATCH 4/5] sf: Add status register protect for Winbond

[George McCollister]

Winbond parts such as W25Q64FV and Spansion parts such as S25FL128S
support two status register protection bits. Implement sr_protect for
Winbond and Spansion devices.

 ---
 | SRP1 | SRP0 | Method   | Description|
 -|-
 | 0| 0| Software | Blocked until write enable |
 | 0| 1| Hardware | Blocked if WP pin is low   |
 | 1| 0| Power| Blocked until power down   |
 | 1| 1| OTP  | Blocked permanently|
 ---

Not all devices support OTP.

Signed-off-by: George McCollister 
---
 drivers/mtd/spi/sf_internal.h |  1 +
 drivers/mtd/spi/spi_flash.c   | 57 +++
 2 files changed, 58 insertions(+)

diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h
index 1b576e8..7a97fc4 100644
--- a/drivers/mtd/spi/sf_internal.h
+++ b/drivers/mtd/spi/sf_internal.h
@@ -82,6 +82,7 @@ enum spi_nor_option_flags {
 #define SR_BP1 BIT(3)  /* Block protect 1 */
 #define SR_BP2 BIT(4)  /* Block protect 2 */
 #define SR_SRP0BIT(7)  /* Status register 
protect 0 */
+#define SR_SRP1BIT(0)  /* Status register 
protect 1 */
 
 /* Flash timeout values */
 #define SPI_FLASH_PROG_TIMEOUT (2 * CONFIG_SYS_HZ)
diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
index 392146b..80e67e6 100644
--- a/drivers/mtd/spi/spi_flash.c
+++ b/drivers/mtd/spi/spi_flash.c
@@ -874,6 +874,62 @@ int stm_sr_protect(struct spi_flash *flash, enum 
srp_method method)
 }
 #endif
 
+#if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
+/*
+ * Set status register protection method for parts with two protection bits
+ *
+ * Returns negative on errors, 0 on success.
+ */
+int winbond_sr_protect(struct spi_flash *flash, enum srp_method method)
+{
+   u8 status_old[2], status_new[2];
+   u8 mask[2] = {SR_SRP0, SR_SRP1};
+   u8 val[2];
+   u8 cmd;
+   int ret;
+
+   ret = read_sr(flash, _old[0]);
+   if (ret < 0)
+   return ret;
+
+   ret = read_cr(flash, _old[1]);
+   if (ret < 0)
+   return ret;
+
+   switch (method) {
+   case SRP_SOFTWARE:
+   val[0] = 0;
+   val[1] = 0;
+   break;
+   case SRP_HARDWARE:
+   val[0] = SR_SRP0;
+   val[1] = 0;
+   break;
+   case SRP_POWER:
+   val[0] = 0;
+   val[1] = SR_SRP1;
+   break;
+   case SRP_OTP:
+   val[0] = SR_SRP0;
+   val[1] = SR_SRP1;
+   break;
+   default:
+   return -EOPNOTSUPP;
+   }
+
+   status_new[0] = (status_old[0] & ~mask[0]) | val[0];
+   status_new[1] = (status_old[1] & ~mask[1]) | val[1];
+
+   cmd = CMD_WRITE_STATUS;
+   ret = spi_flash_write_common(flash, , 1, _new, 2);
+   if (ret) {
+   debug("SF: fail to write status register\n");
+   return ret;
+   }
+
+   return 0;
+}
+#endif
 
 #ifdef CONFIG_SPI_FLASH_MACRONIX
 static int macronix_quad_enable(struct spi_flash *flash)
@@ -1169,6 +1225,7 @@ int spi_flash_scan(struct spi_flash *flash)
flash->flash_lock = stm_lock;
flash->flash_unlock = stm_unlock;
flash->flash_is_locked = stm_is_locked;
+   flash->sr_protect = winbond_sr_protect;
break;
 #endif
default:
-- 
2.9.3

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[U-Boot] [PATCH 1/5] sf: Add status register protection mechanism

[George McCollister]

Many SPI NOR flash devices support status register protection through
one or two status register protection bits. Status register protection
enables protection of block protect and other bits from manipulation.

So far, four different status register protection methods have been
observed:

 Software - Writes to the status register are blocked until
a write enable bit is set by software.
 Hardware - Writes to the status register are blocked while
a pin is in a certain state.
 Power- Writes to the status register are blocked until
the next power-down.
 One Time Program - Writes to the status register are permanently
blocked.

Signed-off-by: George McCollister 
---
 include/spi_flash.h | 17 +
 1 file changed, 17 insertions(+)

diff --git a/include/spi_flash.h b/include/spi_flash.h
index be2fe3f..d1f63c7 100644
--- a/include/spi_flash.h
+++ b/include/spi_flash.h
@@ -26,6 +26,13 @@
 # define CONFIG_SF_DEFAULT_BUS 0
 #endif
 
+enum srp_method {
+   SRP_SOFTWARE,
+   SRP_HARDWARE,
+   SRP_POWER,
+   SRP_OTP,
+};
+
 struct spi_slave;
 
 /**
@@ -89,6 +96,7 @@ struct spi_flash {
int (*flash_lock)(struct spi_flash *flash, u32 ofs, size_t len);
int (*flash_unlock)(struct spi_flash *flash, u32 ofs, size_t len);
int (*flash_is_locked)(struct spi_flash *flash, u32 ofs, size_t len);
+   int (*sr_protect)(struct spi_flash *flash, enum srp_method method);
 #ifndef CONFIG_DM_SPI_FLASH
/*
 * These are not strictly needed for driver model, but keep them here
@@ -239,4 +247,13 @@ static inline int spi_flash_protect(struct spi_flash 
*flash, u32 ofs, u32 len,
return flash->flash_unlock(flash, ofs, len);
 }
 
+static inline int spi_flash_sr_protect(struct spi_flash *flash,
+   enum srp_method method)
+{
+   if (!flash->sr_protect)
+   return -EOPNOTSUPP;
+
+   return flash->sr_protect(flash, method);
+}
+
 #endif /* _SPI_FLASH_H_ */
-- 
2.9.3

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[U-Boot] [PATCH 2/5] sf: Add status register protect for STMICRO, SST

[George McCollister]

STMICRO parts such as M25PX64 and SST parts such as SST26VF032B support
a single status register protect bit. When set this bit cause writes to
the status register to be blocked when the write protect signal is low.

Implement sr_protect for these devices.

Signed-off-by: George McCollister 
---
 drivers/mtd/spi/sf_internal.h |  1 +
 drivers/mtd/spi/spi_flash.c   | 35 +++
 2 files changed, 36 insertions(+)

diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h
index cde4cfb..1b576e8 100644
--- a/drivers/mtd/spi/sf_internal.h
+++ b/drivers/mtd/spi/sf_internal.h
@@ -81,6 +81,7 @@ enum spi_nor_option_flags {
 #define SR_BP0 BIT(2)  /* Block protect 0 */
 #define SR_BP1 BIT(3)  /* Block protect 1 */
 #define SR_BP2 BIT(4)  /* Block protect 2 */
+#define SR_SRP0BIT(7)  /* Status register 
protect 0 */
 
 /* Flash timeout values */
 #define SPI_FLASH_PROG_TIMEOUT (2 * CONFIG_SYS_HZ)
diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
index 7f6e9ae..0e33901 100644
--- a/drivers/mtd/spi/spi_flash.c
+++ b/drivers/mtd/spi/spi_flash.c
@@ -837,6 +837,40 @@ int stm_unlock(struct spi_flash *flash, u32 ofs, size_t 
len)
 
return 0;
 }
+
+/*
+ * Set status register protection method for parts with one protection bit
+ *
+ * Returns negative on errors, 0 on success.
+ */
+int stm_sr_protect(struct spi_flash *flash, enum srp_method method)
+{
+   uint8_t status_old, status_new;
+   u8 mask = SR_SRP0;
+   u8 val;
+   int ret;
+
+   ret = read_sr(flash, _old);
+   if (ret < 0)
+   return ret;
+
+   switch (method) {
+   case SRP_SOFTWARE:
+   val = 0;
+   break;
+   case SRP_HARDWARE:
+   val = SR_SRP0;
+   break;
+   default:
+   return -EOPNOTSUPP;
+   }
+
+   status_new = (status_old & ~mask) | val;
+
+   write_sr(flash, status_new);
+
+   return 0;
+}
 #endif
 
 
@@ -1125,6 +1159,7 @@ int spi_flash_scan(struct spi_flash *flash)
flash->flash_lock = stm_lock;
flash->flash_unlock = stm_unlock;
flash->flash_is_locked = stm_is_locked;
+   flash->sr_protect = stm_sr_protect;
 #endif
break;
default:
-- 
2.9.3

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[U-Boot] [PATCH 3/5] sf: Use stm_lock/unlock for Spansion and Winbond

[George McCollister]

Spansion parts such as S25FL128S and Winbond parts such as W25Q64FV
support the block protection mechanism implemented as
stm_lock() and stm_unlock(). Use stm_lock() and stm_unlock() for
Spansion and Winbond devices.

Signed-off-by: George McCollister 
---
 drivers/mtd/spi/spi_flash.c | 11 ++-
 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
index 0e33901..392146b 100644
--- a/drivers/mtd/spi/spi_flash.c
+++ b/drivers/mtd/spi/spi_flash.c
@@ -664,7 +664,8 @@ int sst_write_bp(struct spi_flash *flash, u32 offset, 
size_t len,
 }
 #endif
 
-#if defined(CONFIG_SPI_FLASH_STMICRO) || defined(CONFIG_SPI_FLASH_SST)
+#if defined(CONFIG_SPI_FLASH_STMICRO) || defined(CONFIG_SPI_FLASH_SST) || \
+   defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
 static void stm_get_locked_range(struct spi_flash *flash, u8 sr, loff_t *ofs,
 u64 *len)
 {
@@ -1160,8 +1161,16 @@ int spi_flash_scan(struct spi_flash *flash)
flash->flash_unlock = stm_unlock;
flash->flash_is_locked = stm_is_locked;
flash->sr_protect = stm_sr_protect;
+   break;
 #endif
+#if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
+   case SPI_FLASH_CFI_MFR_SPANSION:
+   case SPI_FLASH_CFI_MFR_WINBOND:
+   flash->flash_lock = stm_lock;
+   flash->flash_unlock = stm_unlock;
+   flash->flash_is_locked = stm_is_locked;
break;
+#endif
default:
debug("SF: Lock ops not supported for %02x flash\n", idcode[0]);
}
-- 
2.9.3

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[U-Boot] [PATCH 0/5] sf: Add support for status register protect

[George McCollister]

Many SPI NOR flash devices support status register protection through
one or two status register protection bits. Protection of the status
register is essential in defending the device from rogue software which
may attempt to modify block protection bits in order to make malicious
modifications to the data stored in flash. This patch series adds
status register protect support for STMICRO, SST, Winbond and Spansion
devices and also implements an sf sub-command to set the used
protection method.

George McCollister (5):
  sf: Add status register protection mechanism
  sf: Add status register protect for STMICRO, SST
  sf: Use stm_lock/unlock for Spansion and Winbond
  sf: Add status register protect for Winbond
  sf: Add sr-protect sub-command

 cmd/sf.c  |  28 
 drivers/mtd/spi/sf_internal.h |   2 +
 drivers/mtd/spi/spi_flash.c   | 103 +-
 include/spi_flash.h   |  17 +++
 4 files changed, 149 insertions(+), 1 deletion(-)

-- 
2.9.3

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Re: [U-Boot] [PATCH v3 2/3] rk3288: sdram: auto-detect the capacity

[Vagrant Cascadian]

On 2016-10-07, Kever Yang wrote:
> Add support for rk3288 dram capacity auto detect, support DDR3 and
> LPDDR3, DDR2 is not supported.
> The program will automatically detect:
> - channel number
> - rank number
> - column address number
> - row address number
>
> The dts file do not need to describe those info after apply this patch.
>
> Signed-off-by: Kever Yang 
> Tested-by: Simon Glass 
> Tested-by: Vagrant Cascadian 
> ---
>
> Changes in v3:
> - add error report and return value when error happen
> - add comments for stride and address bits.
>
> Changes in v2:
> - update code for OF_PLATDATA enabled
> - bug fix for ddrconfig

Tested the updated v3 patch with u-boot 2016.11-rc1, using both firefly
2GB and 4GB variants. Both detect appropriate amount of ram and
otherwise work fine.

Tested-by: Vagrant Cascadian 

live well,
  vagrant

>  arch/arm/include/asm/arch-rockchip/sdram.h   |  15 ++
>  arch/arm/mach-rockchip/rk3288/sdram_rk3288.c | 272 
> ++-
>  2 files changed, 245 insertions(+), 42 deletions(-)
>
> diff --git a/arch/arm/include/asm/arch-rockchip/sdram.h 
> b/arch/arm/include/asm/arch-rockchip/sdram.h
> index 82c3d07..d7d67ba 100644
> --- a/arch/arm/include/asm/arch-rockchip/sdram.h
> +++ b/arch/arm/include/asm/arch-rockchip/sdram.h
> @@ -16,6 +16,11 @@ enum {
>  };
>  
>  struct rk3288_sdram_channel {
> + /*
> +  * bit width in address, eg:
> +  * 8 banks using 3 bit to address,
> +  * 2 cs using 1 bit to address.
> +  */
>   u8 rank;
>   u8 col;
>   u8 bk;
> @@ -87,6 +92,16 @@ struct rk3288_base_params {
>   u32 ddrconfig;
>   u32 ddr_freq;
>   u32 dramtype;
> + /*
> +  * DDR Stride is address mapping for DRAM space
> +  * Stride   Ch 0 range  Ch1 range   Total
> +  * 0x00 0-256MB 256MB-512MB 512MB
> +  * 0x05 0-1GB   0-1GB   1GB
> +  * 0x09 0-2GB   0-2GB   2GB
> +  * 0x0d 0-4GB   0-4GB   4GB
> +  * 0x17 N/A 0-4GB   4GB
> +  * 0x1a 0-4GB   4GB-8GB 8GB
> +  */
>   u32 stride;
>   u32 odt;
>  };
> diff --git a/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c 
> b/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c
> index cf9ef2e..a7eadc5 100644
> --- a/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c
> +++ b/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c
> @@ -57,6 +57,10 @@ struct rk3288_sdram_params {
>   struct regmap *map;
>  };
>  
> +#define TEST_PATTEN  0x5aa5f00f
> +#define DQS_GATE_TRAINING_ERROR_RANK0(1 << 4)
> +#define DQS_GATE_TRAINING_ERROR_RANK1(2 << 4)
> +
>  #ifdef CONFIG_SPL_BUILD
>  static void copy_to_reg(u32 *dest, const u32 *src, u32 n)
>  {
> @@ -214,7 +218,7 @@ static void ddr_set_en_bst_odt(struct rk3288_grf *grf, 
> uint channel,
>  }
>  
>  static void pctl_cfg(u32 channel, struct rk3288_ddr_pctl *pctl,
> -  const struct rk3288_sdram_params *sdram_params,
> +  struct rk3288_sdram_params *sdram_params,
>struct rk3288_grf *grf)
>  {
>   unsigned int burstlen;
> @@ -264,7 +268,7 @@ static void pctl_cfg(u32 channel, struct rk3288_ddr_pctl 
> *pctl,
>  }
>  
>  static void phy_cfg(const struct chan_info *chan, u32 channel,
> - const struct rk3288_sdram_params *sdram_params)
> + struct rk3288_sdram_params *sdram_params)
>  {
>   struct rk3288_ddr_publ *publ = chan->publ;
>   struct rk3288_msch *msch = chan->msch;
> @@ -446,7 +450,7 @@ static void set_bandwidth_ratio(const struct chan_info 
> *chan, u32 channel,
>  }
>  
>  static int data_training(const struct chan_info *chan, u32 channel,
> -  const struct rk3288_sdram_params *sdram_params)
> +  struct rk3288_sdram_params *sdram_params)
>  {
>   unsigned int j;
>   int ret = 0;
> @@ -549,7 +553,7 @@ static void move_to_access_state(const struct chan_info 
> *chan)
>  }
>  
>  static void dram_cfg_rbc(const struct chan_info *chan, u32 chnum,
> -  const struct rk3288_sdram_params *sdram_params)
> +  struct rk3288_sdram_params *sdram_params)
>  {
>   struct rk3288_ddr_publ *publ = chan->publ;
>  
> @@ -563,7 +567,7 @@ static void dram_cfg_rbc(const struct chan_info *chan, 
> u32 chnum,
>  }
>  
>  static void dram_all_config(const struct dram_info *dram,
> - const struct rk3288_sdram_params *sdram_params)
> + struct rk3288_sdram_params *sdram_params)
>  {
>   unsigned int chan;
>   u32 sys_reg = 0;
> @@ -589,9 +593,191 @@ static void dram_all_config(const struct dram_info 
> *dram,
>   writel(sys_reg, >pmu->sys_reg[2]);
>   rk_clrsetreg(>sgrf->soc_con2, 0x1f, sdram_params->base.stride);
>  }
> +const int ddrconf_table[] = {

Re: [U-Boot] [PATCH] net: smsc95xx: fix DM MAC address reading

[Stephen Warren]

On 09/23/2016 11:43 AM, Joe Hershberger wrote:

On Fri, Sep 23, 2016 at 11:31 AM, Stephen Warren  wrote:

On 09/15/2016 01:20 PM, Joe Hershberger wrote:


On Thu, Sep 15, 2016 at 1:53 PM, Stephen Warren 
wrote:


From: Stephen Warren 

eth-uclass.c expects DM-capable Ethernet adapters to implement ops->
read_rom_hwaddr(), or for some other mechanism to set pdata->enetaddr, or
for the user to set environment variable $usbethaddr. Without any of
these, it will refuse to initialize the device since no valid MAC address
is known. Implement this function for the smsc95xx driver.

With this feature implemented, there is no point smsc95xx_init_common()
re-reading the MAC address from ROM, so ifdef out this code when DM_ETH
is enabled.

This allows (at least) the built-in Ethernet on the NVIDIA Harmony board
to operate again.

Fixes: 0990fcb77219 ("net: smsc95xx: Add driver-model support")
Signed-off-by: Stephen Warren 



Acked-by: Joe Hershberger 



Joe, was that ack just so you remember you've reviewed this when you come to
applying patches later, or was it a signal to someone else that they should
apply it?


No, I'll pull it in.


Joe, I can't find this applied anywhere yet.
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[U-Boot] build error with CONFIG_DM_PCI disabled in menuconfig

[Ding, ChiX]

Hi there
I disabled CONFIG_DM_PCI in menuconfig because I have problem detecting AHCI 
SCSI controller on X86 board
with CONFIG_DM_PCI enabled and the older code in drivers/pci/pci.c works for me 
in the previous U-boot version.
Then I got the build error :
u-boot/arch/x86/cpu/irq.c:29: undefined reference to `dm_pci_read_config8'
u-boot/arch/x86/cpu/irq.c:104: undefined reference to `dm_pci_get_bdf'
u-boot/arch/x86/cpu/irq.c:147: undefined reference to `dm_pci_read_config32'
u-boot/arch/x86/cpu/pci.c:69: undefined reference to `pci_read_config16'
u-boot/arch/x86/cpu/pci.c:73: undefined reference to `pci_read_config8'
u-boot/arch/x86/cpu/pci.c:86: undefined reference to `pci_write_config8'
u-boot/arch/x86/lib/bios_interrupts.c:137: undefined reference to 
`dm_pci_find_device'
u-boot/arch/x86/lib/bios_interrupts.c:141: undefined reference to 
`dm_pci_get_bdf'

It seems that the code refers to the DM_PCI code regardless if  CONFIG_DM_PCI 
is enabled or not.
Is it ok to build U-boot with CONFIG_DM_PCI disabled or  did I miss anything?

Thanks a lot,
Chi
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Registered in Ireland
Registered Office: Collinstown Industrial Park, Leixlip, County Kildare
Registered Number: 308263


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[U-Boot] [PATCH] ARM: tegra: reduce DRAM size mapped into MMU on ARM64

[Stephen Warren]

From: Stephen Warren 

ARM CPUs can architecturally (speculatively) prefetch completely arbitrary
normal memory locations, as defined by the current translation tables. The
current MMU configuration for 64-bit Tegras maps an extremely large range
of addresses as DRAM, well beyond the actual physical maximum DRAM window,
even though U-Boot only needs access to the first 2GB of DRAM; the Tegra
port of U-Boot deliberately limits itself to 2GB of RAM since some HW
modules on at least some 64-bit Tegra SoCs can only access a 32-bit
physical address space. This change reduces the amount of RAM mapped via
the MMU to disallow the CPU from ever speculatively accessing RAM that
U-Boot will definitely not access. This avoids the possibility of the HW
raising SError due to accesses to always-invalid physical addresses.

Signed-off-by: Stephen Warren 
---
 arch/arm/mach-tegra/arm64-mmu.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/mach-tegra/arm64-mmu.c b/arch/arm/mach-tegra/arm64-mmu.c
index 7b1d258ed84f..a79a5192e076 100644
--- a/arch/arm/mach-tegra/arm64-mmu.c
+++ b/arch/arm/mach-tegra/arm64-mmu.c
@@ -23,7 +23,7 @@ static struct mm_region tegra_mem_map[] = {
}, {
.virt = 0x8000UL,
.phys = 0x8000UL,
-   .size = 0xff8000UL,
+   .size = 0x8000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 PTE_BLOCK_INNER_SHARE
}, {
-- 
2.10.1

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[U-Boot] [RFC 4/4] arm: socfpga: scrub the SDRAM to properly enable ECC support

[Dinh Nguyen]

From: Dinh Nguyen 

In order for SDRAM ECC to work correctly, the SDRAM needs to get zero'd which
enables the ECC bit. By using the PL330 DMA to fill the SDRAM with zeroes,
the operation is completed in ~1.2 seconds, versus ~14 seconds with a memset.

Signed-off-by: Dinh Nguyen 
---
 arch/arm/mach-socfpga/include/mach/reset_manager.h | 21 
 arch/arm/mach-socfpga/include/mach/sdram.h |  2 ++
 arch/arm/mach-socfpga/spl.c|  8 +++
 arch/arm/mach-socfpga/wrap_sdram_config.c  | 28 ++
 configs/socfpga_cyclone5_defconfig |  2 ++
 5 files changed, 61 insertions(+)

diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h 
b/arch/arm/mach-socfpga/include/mach/reset_manager.h
index 2f070f2..9750026 100644
--- a/arch/arm/mach-socfpga/include/mach/reset_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h
@@ -79,4 +79,25 @@ struct socfpga_reset_manager {
 /* Create a human-readable reference to SoCFPGA reset. */
 #define SOCFPGA_RESET(_name)   RSTMGR_##_name
 
+#define RSTMGR_STAT_L4WD1RST_MASK 0x8000
+#define RSTMGR_STAT_L4WD0RST_MASK 0x4000
+#define RSTMGR_STAT_MPUWD1RST_MASK 0x2000
+#define RSTMGR_STAT_MPUWD0RST_MASK 0x1000
+#define RSTMGR_STAT_SWWARMRST_MASK 0x0400
+#define RSTMGR_STAT_FPGAWARMRST_MASK 0x0200
+#define RSTMGR_STAT_NRSTPINRST_MASK 0x0100
+#define RSTMGR_STAT_SWCOLDRST_MASK 0x0010
+#define RSTMGR_STAT_CONFIGIOCOLDRST_MASK 0x0008
+#define RSTMGR_STAT_FPGACOLDRST_MASK 0x0004
+#define RSTMGR_STAT_NPORPINRST_MASK 0x0002
+#define RSTMGR_STAT_PORVOLTRST_MASK 0x0001
+
+#define RSTMGR_WARMRST_MASK(RSTMGR_STAT_SWWARMRST_MASK | \
+RSTMGR_STAT_L4WD0RST_MASK | \
+RSTMGR_STAT_L4WD1RST_MASK | \
+RSTMGR_STAT_MPUWD1RST_MASK | \
+RSTMGR_STAT_MPUWD0RST_MASK | \
+RSTMGR_STAT_FPGAWARMRST_MASK | \
+RSTMGR_STAT_NRSTPINRST_MASK)
+
 #endif /* _RESET_MANAGER_H_ */
diff --git a/arch/arm/mach-socfpga/include/mach/sdram.h 
b/arch/arm/mach-socfpga/include/mach/sdram.h
index f12bb84..5154ad2 100644
--- a/arch/arm/mach-socfpga/include/mach/sdram.h
+++ b/arch/arm/mach-socfpga/include/mach/sdram.h
@@ -20,6 +20,8 @@ const struct socfpga_sdram_rw_mgr_config 
*socfpga_get_sdram_rwmgr_config(void);
 const struct socfpga_sdram_io_config *socfpga_get_sdram_io_config(void);
 const struct socfpga_sdram_misc_config *socfpga_get_sdram_misc_config(void);
 
+void sdram_ecc_init(void);
+
 #define SDR_CTRLGRP_ADDRESS(SOCFPGA_SDR_ADDRESS | 0x5000)
 
 struct socfpga_sdr_ctrl {
diff --git a/arch/arm/mach-socfpga/spl.c b/arch/arm/mach-socfpga/spl.c
index fec4c7a..26688ad 100644
--- a/arch/arm/mach-socfpga/spl.c
+++ b/arch/arm/mach-socfpga/spl.c
@@ -30,6 +30,8 @@ static struct nic301_registers *nic301_regs =
(struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
 static struct socfpga_system_manager *sysmgr_regs =
(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
+static const struct socfpga_reset_manager *reset_manager_base =
+   (void *)SOCFPGA_RSTMGR_ADDRESS;
 
 u32 spl_boot_device(void)
 {
@@ -85,6 +87,9 @@ void board_init_f(ulong dummy)
 #endif
unsigned long sdram_size;
unsigned long reg;
+   u32 rst_mgr_status;
+
+   rst_mgr_status = readl(_manager_base->status);
 
/*
 * First C code to run. Clear fake OCRAM ECC first as SBE
@@ -179,6 +184,9 @@ void board_init_f(ulong dummy)
 
socfpga_bridges_reset(1);
 
+   if ((rst_mgr_status & RSTMGR_WARMRST_MASK) == 0)
+   sdram_ecc_init();
+
/* Configure simple malloc base pointer into RAM. */
gd->malloc_base = CONFIG_SYS_TEXT_BASE + (1024 * 1024);
 }
diff --git a/arch/arm/mach-socfpga/wrap_sdram_config.c 
b/arch/arm/mach-socfpga/wrap_sdram_config.c
index 31cc7de..dfa6423 100644
--- a/arch/arm/mach-socfpga/wrap_sdram_config.c
+++ b/arch/arm/mach-socfpga/wrap_sdram_config.c
@@ -5,8 +5,10 @@
  */
 
 #include 
+#include 
 #include 
 #include 
+#include 
 
 /* Board-specific header. */
 #include 
@@ -310,3 +312,29 @@ const struct socfpga_sdram_misc_config 
*socfpga_get_sdram_misc_config(void)
 {
return _config;
 }
+
+#if (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN == 1)
+/* init the whole SDRAM ECC bit */
+void sdram_ecc_init(void)
+{
+   struct pl330_transfer_struct pl330;
+   u8 pl330_buf[2000];
+
+   pl330.dst_addr = CONFIG_SYS_SDRAM_BASE;
+   pl330.len = sdram_calculate_size();
+   pl330.channel_num = 0;
+   pl330.buf_size = sizeof(pl330_buf);
+   pl330.buf = pl330_buf;
+
+   pl330.transfer_type = DMA_SUPPORTS_DEV_TO_MEM;
+   pl330.reg_base = (void __iomem *)SOCFPGA_DMASECURE_ADDRESS;
+
+   puts("SDRAM: Initializing SDRAM ECC\n");
+
+   

[U-Boot] [RFC 3/4] dm: add DMA_SUPPORTS_DEV_TO_MEM type to DMA_UCLASS

[Dinh Nguyen]

From: Dinh Nguyen 

Add DMA_SUPPORTS_DEV_TO_MEM type to the DMA uclass.

Signed-off-by: Dinh Nguyen 
---
 drivers/dma/dma-uclass.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/dma/dma-uclass.c b/drivers/dma/dma-uclass.c
index ea21fd9..a021395 100644
--- a/drivers/dma/dma-uclass.c
+++ b/drivers/dma/dma-uclass.c
@@ -49,7 +49,8 @@ int dma_memcpy(void *dst, void *src, size_t len)
const struct dma_ops *ops;
int ret;
 
-   ret = dma_get_device(DMA_SUPPORTS_MEM_TO_MEM, );
+   ret = dma_get_device(DMA_SUPPORTS_MEM_TO_MEM |
+DMA_SUPPORTS_DEV_TO_MEM, );
if (ret < 0)
return ret;
 
-- 
2.8.3

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[U-Boot] [RFC 1/4] drivers: dma: Add the ARM PL330 DMA driver

[Dinh Nguyen]

From: Dinh Nguyen 

Adopted from the Linux kernel PL330 DMA driver.

Signed-off-by: Dinh Nguyen 
---
 arch/arm/include/asm/pl330.h | 105 +
 drivers/dma/pl330.c  | 942 +++
 2 files changed, 1047 insertions(+)
 create mode 100644 arch/arm/include/asm/pl330.h
 create mode 100644 drivers/dma/pl330.c

diff --git a/arch/arm/include/asm/pl330.h b/arch/arm/include/asm/pl330.h
new file mode 100644
index 000..dd19b4c
--- /dev/null
+++ b/arch/arm/include/asm/pl330.h
@@ -0,0 +1,105 @@
+/*
+ * Copyright (C) 2010 Samsung Electronics Co. Ltd.
+ * Jaswinder Singh 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ *
+ * adapted from linux kernel pl330.h
+ */
+
+#ifndef__PL330_H_
+#define__PL330_H_
+
+#define PL330_STATE_STOPPED(1 << 0)
+#define PL330_STATE_EXECUTING  (1 << 1)
+#define PL330_STATE_WFE(1 << 2)
+#define PL330_STATE_FAULTING   (1 << 3)
+#define PL330_STATE_COMPLETING (1 << 4)
+#define PL330_STATE_WFP(1 << 5)
+#define PL330_STATE_KILLING(1 << 6)
+#define PL330_STATE_FAULT_COMPLETING   (1 << 7)
+#define PL330_STATE_CACHEMISS  (1 << 8)
+#define PL330_STATE_UPDTPC (1 << 9)
+#define PL330_STATE_ATBARRIER  (1 << 10)
+#define PL330_STATE_QUEUEBUSY  (1 << 11)
+#define PL330_STATE_INVALID(1 << 15)
+
+#define PL330_DMA_MAX_BURST_SIZE   3
+
+/* structure to be passed in for pl330_transfer_x */
+struct pl330_transfer_struct {
+   void __iomem *reg_base;
+   u32 channel_num;
+   u32 src_addr;
+   u32 dst_addr;
+   u32 len;
+   u32 brst_size;
+   u32 single_brst_size;
+   u32 brst_len;
+   u32 peripheral_id;
+   u32 transfer_type;
+   u32 enable_cache1;
+   u32 buf_size;
+   u8 *buf;
+};
+
+enum pl330_srccachectrl {
+   SCCTRL0 = 0,/* Noncacheable and nonbufferable */
+   SCCTRL1,/* Bufferable only */
+   SCCTRL2,/* Cacheable, but do not allocate */
+   SCCTRL3,/* Cacheable and bufferable, but do not allocate */
+   SINVALID1,
+   SINVALID2,
+   SCCTRL6,/* Cacheable write-through, allocate on reads only */
+   SCCTRL7,/* Cacheable write-back, allocate on reads only */
+};
+
+enum pl330_dstcachectrl {
+   DCCTRL0 = 0,/* Noncacheable and nonbufferable */
+   DCCTRL1,/* Bufferable only */
+   DCCTRL2,/* Cacheable, but do not allocate */
+   DCCTRL3,/* Cacheable and bufferable, but do not allocate */
+   DINVALID1 = 8,
+   DINVALID2,
+   DCCTRL6,/* Cacheable write-through, allocate on writes only */
+   DCCTRL7,/* Cacheable write-back, allocate on writes only */
+};
+
+enum pl330_byteswap {
+   SWAP_NO = 0,
+   SWAP_2,
+   SWAP_4,
+   SWAP_8,
+   SWAP_16,
+};
+
+/*
+ * Request Configuration.
+ * The PL330 core does not modify this and uses the last
+ * working configuration if the request doesn't provide any.
+ *
+ * The Client may want to provide this info only for the
+ * first request and a request with new settings.
+ */
+struct pl330_reqcfg {
+   /* Address Incrementing */
+   unsigned dst_inc:1;
+   unsigned src_inc:1;
+
+   /*
+* For now, the SRC & DST protection levels
+* and burst size/length are assumed same.
+*/
+   int nonsecure;
+   int privileged;
+   int insnaccess;
+   unsigned brst_len:5;
+   unsigned brst_size:3; /* in power of 2 */
+
+   enum pl330_dstcachectrl dcctl;
+   enum pl330_srccachectrl scctl;
+   enum pl330_byteswap swap;
+};
+
+void arm_pl330_transfer(struct pl330_transfer_struct *pl330);
+#endif /* __PL330_H_ */
diff --git a/drivers/dma/pl330.c b/drivers/dma/pl330.c
new file mode 100644
index 000..a97cd9f
--- /dev/null
+++ b/drivers/dma/pl330.c
@@ -0,0 +1,942 @@
+/*
+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * Copyright (C) 2010 Samsung Electronics Co. Ltd.
+ * Jaswinder Singh 
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+struct dma_pl330_platdata {
+   u32 base;
+};
+
+/* Register and Bit field Definitions */
+#define DS 0x0
+#define DS_ST_STOP 0x0
+#define DS_ST_EXEC 0x1
+#define DS_ST_CMISS0x2
+#define DS_ST_UPDTPC   0x3
+#define DS_ST_WFE  0x4
+#define DS_ST_ATBRR0x5
+#define DS_ST_QBUSY0x6
+#define DS_ST_WFP  0x7
+#define DS_ST_KILL 0x8
+#define DS_ST_CMPLT0x9
+#define DS_ST_FLTCMP   0xe
+#define DS_ST_FAULT0xf
+
+#define DPC0x4
+#define INTEN  

[U-Boot] [RFC 2/4] dma: Kconfig: Add CONFIG_PL330_DMA entry

[Dinh Nguyen]

From: Dinh Nguyen 

Add PL330_DMA entry.

Signed-off-by: Dinh Nguyen 
---
 drivers/dma/Kconfig  | 4 
 drivers/dma/Makefile | 1 +
 2 files changed, 5 insertions(+)

diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
index 1b92c77..d95f959 100644
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -19,4 +19,8 @@ config TI_EDMA3
  This driver support data transfer between memory
  regions.
 
+config PL330_DMA
+   bool "PL330 DMA driver"
+   help
+ Enable the ARM PL330 DMA driver.
 endmenu # menu "DMA Support"
diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile
index 39b78b2..d287512 100644
--- a/drivers/dma/Makefile
+++ b/drivers/dma/Makefile
@@ -13,3 +13,4 @@ obj-$(CONFIG_FSL_DMA) += fsl_dma.o
 obj-$(CONFIG_TI_KSNAV) += keystone_nav.o keystone_nav_cfg.o
 obj-$(CONFIG_TI_EDMA3) += ti-edma3.o
 obj-$(CONFIG_DMA_LPC32XX) += lpc32xx_dma.o
+obj-$(CONFIG_PL330_DMA) += pl330.o
-- 
2.8.3

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[U-Boot] [RFC] 0/4] Add Pl330 DMA support

[Dinh Nguyen]

Hi,

This patchset adds the PL330 DMA driver to U-Boot. The SoCFPGA platform makes
use of the PL330 to transfer zereos to the SDRAM which enables the ECC bit.

This is only an RFC because after rebasing to v2016.11-rc1, I had to revert
the following patch "a78cd8613204 ARM: Rework and correct barrier definitions"
in order for this patch set to work correctly. With the above patch applied,
after the SDRAM scrubbing is complete, the SPL is failing to find the MMC
device.

I'm continue to debug this, but would like to solicit comments with this
patchset.

Thanks,
Dinh


Dinh Nguyen (4):
  drivers: dma: Add the ARM PL330 DMA driver
  dma: Kconfig: Add CONFIG_PL330_DMA entry
  dm: add DMA_SUPPORTS_DEV_TO_MEM type to DMA_UCLASS
  arm: socfpga: scrub the SDRAM to properly enable ECC support

 arch/arm/include/asm/pl330.h   | 105 +++
 arch/arm/mach-socfpga/include/mach/reset_manager.h |  21 +
 arch/arm/mach-socfpga/include/mach/sdram.h |   2 +
 arch/arm/mach-socfpga/spl.c|   8 +
 arch/arm/mach-socfpga/wrap_sdram_config.c  |  28 +
 configs/socfpga_cyclone5_defconfig |   2 +
 drivers/dma/Kconfig|   4 +
 drivers/dma/Makefile   |   1 +
 drivers/dma/dma-uclass.c   |   3 +-
 drivers/dma/pl330.c| 942 +
 10 files changed, 1115 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/include/asm/pl330.h
 create mode 100644 drivers/dma/pl330.c

-- 
2.8.3

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Re: [U-Boot] [PATCH] armv8:ls1012a: Update bootargs for fast-boot

[york sun]

On 10/10/2016 12:36 AM, Pratiyush Srivastava wrote:
> Add optimization parameters like "quiet" in bootargs to reduce the system
> boot time
>
> Signed-off-by: Pratiyush Mohan Srivastava 
> Signed-off-by: Harninder Rai 
> ---
>  include/configs/ls1012a_common.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/include/configs/ls1012a_common.h 
> b/include/configs/ls1012a_common.h
> index 5fb6c47..a0ef2cd 100644
> --- a/include/configs/ls1012a_common.h
> +++ b/include/configs/ls1012a_common.h
> @@ -120,7 +120,7 @@
>   "console=ttyAMA0,38400n8\0"
>
>  #define CONFIG_BOOTARGS  "console=ttyS0,115200 root=/dev/ram0 " \
> - "earlycon=uart8250,mmio,0x21c0500"
> + "earlycon=uart8250,mmio,0x21c0500 quiet 
> lpj=25"
>  #define CONFIG_BOOTCOMMAND   "sf probe 0:0; sf read $kernel_load "\
>   "$kernel_start $kernel_size && "\
>   "bootm $kernel_load"
>

How much improvement do you get by using "quiet"? You didn't mention lpj 
in the commit message. Did you get the number from kernel log? LS1012A 
is a single core SoC. How much time do you save by setting lpj?

York
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Re: [U-Boot] [PATCH 1/9] dm: pci: return the real controller in pci_bus_to_hose()

[M.H. Lian]

Hi Bin，

Thanks for your comments.

The series of patches is to change legacy PCIe driver to DM PCIe driver.
The first two patches are to change DM to support multiple PCIe controllers.
The 8th patch is to change Layerscape PCIe driver based on DM
Other patches are to add PCIe dts node for five SoCs.

Thanks,
Minghuan

> -Original Message-
> From: Bin Meng [mailto:bmeng...@gmail.com]
> Sent: Monday, October 10, 2016 5:03 PM
> To: M.H. Lian ; Simon Glass 
> Cc: U-Boot Mailing List ; Mingkai Hu
> ; Leo Li 
> Subject: Re: [U-Boot] [PATCH 1/9] dm: pci: return the real controller in
> pci_bus_to_hose()
> 
> +Simon
> 
> Hi Minghuan,
> 
> On Mon, Oct 10, 2016 at 4:47 PM, Minghuan Lian 
> wrote:
> > for the legacy PCI driver, the function pci_bus_to_hose() returns the
> > real PCIe controller. To keep consistency, this function is changed to
> > return the PCIe controller pointer of the root bus instead of the
> > current PCIe bus.
> >
> > Signed-off-by: Minghuan Lian 
> > ---
> >  drivers/pci/pci_compat.c | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/pci/pci_compat.c b/drivers/pci/pci_compat.c index
> > ddaf358..25bc095 100644
> > --- a/drivers/pci/pci_compat.c
> > +++ b/drivers/pci/pci_compat.c
> > @@ -49,5 +49,5 @@ struct pci_controller *pci_bus_to_hose(int busnum)
> > return NULL;
> > }
> >
> > -   return dev_get_uclass_priv(bus);
> > +   return dev_get_uclass_priv(pci_get_controller(bus));
> >  }
> > --
> 
> Any reason why don't we add DM PCI to the new board?
> 
> Regards,
> Bin
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Re: [U-Boot] [PATCH v2] fs:When 'go' run the program by 'fatload', added the cache flush to prevent cache mismatch.

[James Chargin]

Dear yoko,

On 10/07/2016 08:20 PM, yoko wrote:

Signed-off-by: yoko 
---

Changes for v2:
   - The commit message is changed.

 fs/fs.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/fs/fs.c b/fs/fs.c
index 595ff1f..7607230 100644
--- a/fs/fs.c
+++ b/fs/fs.c
@@ -417,6 +417,8 @@ int do_load(cmd_tbl_t *cmdtp, int flag, int argc, char * 
const argv[],
}
puts("\n");

+   flush_cache(addr, len_read);
+
setenv_hex("fileaddr", addr);
setenv_hex("filesize", len_read);

@@ -535,4 +537,3 @@ int do_fs_type(cmd_tbl_t *cmdtp, int flag, int argc, char * 
const argv[])

return CMD_RET_SUCCESS;
 }
-



The wiki includes information about cache considerations for the "go" 
command [1]. If possible, please check that information to be sure it 
remains consistent with this patch.


Thanks,
Jim

[1] http://www.denx.de/wiki/view/DULG/UBootStandalone#Section_5.12.3.
--
Jim Chargin
AJA Video Systems   j...@aja.com
(530) 271-3334  http://www.aja.com
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[U-Boot] [PATCH 2/3] include: configs: am335x: add Atheros phy support

[Mugunthan V N]

In AM335x GP EVM, Atheros 8031 phy is used, enable the driver as
AM335x SoC RGMII delay mode has to be enabled in phy as mentioned
in the silicon errata Advisory 1.0.10

Signed-off-by: Mugunthan V N 
---
 include/configs/am335x_evm.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h
index 272c71b..daa7dd8 100644
--- a/include/configs/am335x_evm.h
+++ b/include/configs/am335x_evm.h
@@ -432,6 +432,8 @@
 #define CONFIG_PHY_GIGE
 #define CONFIG_PHYLIB
 #define CONFIG_PHY_SMSC
+/* Enable Atheros phy driver */
+#define CONFIG_PHY_ATHEROS
 
 /*
  * NOR Size = 16 MiB
-- 
2.10.0.372.g6fe1b14

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[U-Boot] [PATCH 1/3] drivers: net: phy: atheros: add separate config for AR8031

[Mugunthan V N]

In the current driver implementation, config() callback is common
for AR8035 and AR8031 phy. In config() callback, driver tries to
configure MMD Access Control Register and MMD Access Address Data
Register unconditionally for both phy versions which leads to
auto negotiation failure in AM335x EVMsk second port which uses
AR8031 Giga bit RGMII phy. Fixing this by adding separate config
for AR8031 phy.

Reviewed-by: Sekhar Nori 
Signed-off-by: Mugunthan V N 
---
 drivers/net/phy/atheros.c | 37 -
 1 file changed, 36 insertions(+), 1 deletion(-)

diff --git a/drivers/net/phy/atheros.c b/drivers/net/phy/atheros.c
index e57c412..faf5175 100644
--- a/drivers/net/phy/atheros.c
+++ b/drivers/net/phy/atheros.c
@@ -8,6 +8,15 @@
  */
 #include 
 
+#define AR803x_PHY_DEBUG_ADDR_REG  0x1d
+#define AR803x_PHY_DEBUG_DATA_REG  0x1e
+
+#define AR803x_DEBUG_REG_5 0x5
+#define AR803x_RGMII_TX_CLK_DLY0x100
+
+#define AR803x_DEBUG_REG_0 0x0
+#define AR803x_RGMII_RX_CLK_DLY0x8000
+
 static int ar8021_config(struct phy_device *phydev)
 {
phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
@@ -17,6 +26,32 @@ static int ar8021_config(struct phy_device *phydev)
return 0;
 }
 
+static int ar8031_config(struct phy_device *phydev)
+{
+   if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID ||
+   phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
+   phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_ADDR_REG,
+ AR803x_DEBUG_REG_5);
+   phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_DATA_REG,
+ AR803x_RGMII_TX_CLK_DLY);
+   }
+
+   if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID ||
+   phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
+   phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_ADDR_REG,
+ AR803x_DEBUG_REG_0);
+   phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_DATA_REG,
+ AR803x_RGMII_RX_CLK_DLY);
+   }
+
+   phydev->supported = phydev->drv->features;
+
+   genphy_config_aneg(phydev);
+   genphy_restart_aneg(phydev);
+
+   return 0;
+}
+
 static int ar8035_config(struct phy_device *phydev)
 {
int regval;
@@ -54,7 +89,7 @@ static struct phy_driver AR8031_driver =  {
.uid = 0x4dd074,
.mask = 0xffef,
.features = PHY_GBIT_FEATURES,
-   .config = ar8035_config,
+   .config = ar8031_config,
.startup = genphy_startup,
.shutdown = genphy_shutdown,
 };
-- 
2.10.0.372.g6fe1b14

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[U-Boot] [PATCH 3/3] driver: net: cpsw: add support for RGMII id mode support and RMII clock source selection

[Mugunthan V N]

cpsw driver supports only selection of phy mode in control module
but control module has more setting like RGMII ID mode selection,
RMII clock source selection. So ported to cpsw-phy-sel driver
from kernel to u-boot.

Signed-off-by: Mugunthan V N 
---
 drivers/net/cpsw.c | 153 -
 include/cpsw.h |   1 +
 2 files changed, 140 insertions(+), 14 deletions(-)

diff --git a/drivers/net/cpsw.c b/drivers/net/cpsw.c
index d17505e..1441f44 100644
--- a/drivers/net/cpsw.c
+++ b/drivers/net/cpsw.c
@@ -225,6 +225,18 @@ struct cpdma_chan {
void*hdp, *cp, *rxfree;
 };
 
+/* AM33xx SoC specific definitions for the CONTROL port */
+#define AM33XX_GMII_SEL_MODE_MII   0
+#define AM33XX_GMII_SEL_MODE_RMII  1
+#define AM33XX_GMII_SEL_MODE_RGMII 2
+
+#define AM33XX_GMII_SEL_RGMII1_IDMODE  BIT(4)
+#define AM33XX_GMII_SEL_RGMII2_IDMODE  BIT(5)
+#define AM33XX_GMII_SEL_RMII1_IO_CLK_ENBIT(6)
+#define AM33XX_GMII_SEL_RMII2_IO_CLK_ENBIT(7)
+
+#define GMII_SEL_MODE_MASK 0x3
+
 #define desc_write(desc, fld, val) __raw_writel((u32)(val), &(desc)->fld)
 #define desc_read(desc, fld)   __raw_readl(&(desc)->fld)
 #define desc_read_ptr(desc, fld)   ((void *)__raw_readl(&(desc)->fld))
@@ -1150,12 +1162,129 @@ static inline fdt_addr_t cpsw_get_addr_by_node(const 
void *fdt, int node)
  false);
 }
 
+static void cpsw_gmii_sel_am3352(struct cpsw_priv *priv,
+phy_interface_t phy_mode)
+{
+   u32 reg;
+   u32 mask;
+   u32 mode = 0;
+   bool rgmii_id = false;
+   int slave = priv->data.active_slave;
+
+   reg = readl(priv->data.gmii_sel);
+
+   switch (phy_mode) {
+   case PHY_INTERFACE_MODE_RMII:
+   mode = AM33XX_GMII_SEL_MODE_RMII;
+   break;
+
+   case PHY_INTERFACE_MODE_RGMII:
+   mode = AM33XX_GMII_SEL_MODE_RGMII;
+   break;
+   case PHY_INTERFACE_MODE_RGMII_ID:
+   case PHY_INTERFACE_MODE_RGMII_RXID:
+   case PHY_INTERFACE_MODE_RGMII_TXID:
+   mode = AM33XX_GMII_SEL_MODE_RGMII;
+   rgmii_id = true;
+   break;
+
+   case PHY_INTERFACE_MODE_MII:
+   default:
+   mode = AM33XX_GMII_SEL_MODE_MII;
+   break;
+   };
+
+   mask = GMII_SEL_MODE_MASK << (slave * 2) | BIT(slave + 6);
+   mode <<= slave * 2;
+
+   if (priv->data.rmii_clock_external) {
+   if (slave == 0)
+   mode |= AM33XX_GMII_SEL_RMII1_IO_CLK_EN;
+   else
+   mode |= AM33XX_GMII_SEL_RMII2_IO_CLK_EN;
+   }
+
+   if (rgmii_id) {
+   if (slave == 0)
+   mode |= AM33XX_GMII_SEL_RGMII1_IDMODE;
+   else
+   mode |= AM33XX_GMII_SEL_RGMII2_IDMODE;
+   }
+
+   reg &= ~mask;
+   reg |= mode;
+
+   writel(reg, priv->data.gmii_sel);
+}
+
+static void cpsw_gmii_sel_dra7xx(struct cpsw_priv *priv,
+phy_interface_t phy_mode)
+{
+   u32 reg;
+   u32 mask;
+   u32 mode = 0;
+   int slave = priv->data.active_slave;
+
+   reg = readl(priv->data.gmii_sel);
+
+   switch (phy_mode) {
+   case PHY_INTERFACE_MODE_RMII:
+   mode = AM33XX_GMII_SEL_MODE_RMII;
+   break;
+
+   case PHY_INTERFACE_MODE_RGMII:
+   case PHY_INTERFACE_MODE_RGMII_ID:
+   case PHY_INTERFACE_MODE_RGMII_RXID:
+   case PHY_INTERFACE_MODE_RGMII_TXID:
+   mode = AM33XX_GMII_SEL_MODE_RGMII;
+   break;
+
+   case PHY_INTERFACE_MODE_MII:
+   default:
+   mode = AM33XX_GMII_SEL_MODE_MII;
+   break;
+   };
+
+   switch (slave) {
+   case 0:
+   mask = GMII_SEL_MODE_MASK;
+   break;
+   case 1:
+   mask = GMII_SEL_MODE_MASK << 4;
+   mode <<= 4;
+   break;
+   default:
+   dev_err(priv->dev, "invalid slave number...\n");
+   return;
+   }
+
+   if (priv->data.rmii_clock_external)
+   dev_err(priv->dev, "RMII External clock is not supported\n");
+
+   reg &= ~mask;
+   reg |= mode;
+
+   writel(reg, priv->data.gmii_sel);
+}
+
+static void cpsw_phy_sel(struct cpsw_priv *priv, const char *compat,
+phy_interface_t phy_mode)
+{
+   if (!strcmp(compat, "ti,am3352-cpsw-phy-sel"))
+   cpsw_gmii_sel_am3352(priv, phy_mode);
+   if (!strcmp(compat, "ti,am43xx-cpsw-phy-sel"))
+   cpsw_gmii_sel_am3352(priv, phy_mode);
+   else if (!strcmp(compat, "ti,dra7xx-cpsw-phy-sel"))
+   cpsw_gmii_sel_dra7xx(priv, phy_mode);
+}
+
 static int cpsw_eth_ofdata_to_platdata(struct udevice *dev)
 {
struct eth_pdata *pdata = dev_get_platdata(dev);
 

[U-Boot] [PATCH 0/3] Add Atheros phy delay support and CPSW RGMII id support

[Mugunthan V N]

This patch series adds support for RGMII phy internal delay
support for Atheros 8031 phy driver and also add support for
the phy mode configuration in control module in cpsw driver.

Tested the series on the following EVMs with a zImage download
from server, logs [1] and pushed a branch for testing [2].

* DRA 72 Rev B EVM
* DRA 72 Rev C EVM
* DRA 74 EVM
* AM437x GP EVM
* AM335x BBB
* AM335x GP EVM

[1] - http://pastebin.ubuntu.com/23302895/
[2] - git://git.ti.com/~mugunthanvnm/ti-u-boot/mugunth-ti-u-boot.git cpsw-rgmii

Mugunthan V N (3):
  drivers: net: phy: atheros: add separate config for AR8031
  include: configs: am335x: add Atheros phy support
  driver: net: cpsw: add support for RGMII id mode support and RMII
clock source selection

 drivers/net/cpsw.c   | 153 +++
 drivers/net/phy/atheros.c|  37 ++-
 include/configs/am335x_evm.h |   2 +
 include/cpsw.h   |   1 +
 4 files changed, 178 insertions(+), 15 deletions(-)

-- 
2.10.0.372.g6fe1b14

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[U-Boot] AHCI controller not found

[Ding, ChiX]

Hi there
I'm testing U-boot as Coreboot payload on Intel board. It boots into U-boot 
shell but fails to detect AHCI controller.
SCSI:  Error: SCSI Controller(s) 8086:19B2 8086:19C2 not found

AHCI SCSI devices are defined in coreboot.h,
#define CONFIG_SCSI_AHCI
#define CONFIG_SCSI_DEV_LIST{PCI_VENDOR_ID_INTEL, \
0x19b2},  \
{PCI_VENDOR_ID_INTEL,   \
0x19c2}

I debug into scsi_init(void). It goes through a loop to try to find PCI device 
for  the AHCI controllers defined above in coreboot.h .
I tried the new code "enable driver mode for PCI" and the old code using 
pci_find_device() function, but both fail to find the devices.

#ifdef CONFIG_DM_PCI
struct udevice *dev;
int ret;

ret = dm_pci_find_device(scsi_device_list[i].vendor,
 scsi_device_list[i].device, 0, );
if (!ret) {
busdevfunc = dm_pci_get_bdf(dev);
break;
}
#else
busdevfunc = pci_find_device(scsi_device_list[i].vendor,
 scsi_device_list[i].device,
 0);
#endif


My device tree file below is a barebone which only defines serial port, 
keyboard, timer. They work fine.
I wonder that in order to find AHCI controller, shall I add some definition for 
PCI device into the device tree file?
What's the minimum definition shall I add?

/include/ "skeleton.dtsi"
/include/ "keyboard.dtsi"
/include/ "serial.dtsi"
/include/ "rtc.dtsi"
/include/ "tsc_timer.dtsi"

/ {
#address-cells = <1>;
#size-cells = <1>;
model = "Google Alex";
compatible = "google,alex", "intel,atom-pineview";

config {
   silent_console = <0>;
};

gpio: gpio {};

serial {
reg = <0x1000 8>;
clock-frequency = <115200>;
};

tsc-timer {
clock-frequency = <10>;
};

chosen {
stdout-path = "/serial";
};

memory { device_type = "memory"; reg = <0 0>; };

};


Thanks a lot,
Chi
--
Intel Research and Development Ireland Limited
Registered in Ireland
Registered Office: Collinstown Industrial Park, Leixlip, County Kildare
Registered Number: 308263


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Re: [U-Boot] [PATCH 0/6] Add support for the BK4R1 variant of PCM052

[Albert ARIBAUD]

Hi Stefano,

Sorry for the delay.

Le Fri, 7 Oct 2016 12:01:02 +0200, Stefano Babic  a
écrit :

> Hi Albert,
> 
> On 06/10/2016 15:43, Albert ARIBAUD wrote:
> 
> > 
> > Hmm... What U-Boot commit do you apply above?  
> 
> It was on top of v2016.11-rc1, and then I have already applied several
> patches for i.MX.
> 
> I am very sorry for that: generally, I check the patches in a separate
> local branch, but it seemed I made a mistake and I have applied it on my
> -master, and after my last push they are already on the server. It was
> not my intention. Of course, I will revert them back if you do not like
> / disagree.

No problem.

I could not reproduce the problem on my side (i.e., origin/master
buildman builds bk4r1 without any warning or error), but anyway, your
change appears harmless enough, so I'm fine with you adding it.

Thanks!

Cordialement,
Albert ARIBAUD
3ADEV
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Re: [U-Boot] [PATCH 2/9] dm: pci: remove pci_bus_to_hose(0) calling

[Bin Meng]

+Simon

Hi Minghuan,

On Mon, Oct 10, 2016 at 4:47 PM, Minghuan Lian  wrote:
> There may be multiple PCIe controllers in a SoC.
> It is not correct that always calling pci_bus_to_hose(0) to get
> the first PCIe controller for the PCIe device connected other
> controllers. We just remove this calling because hose always point
> the correct PCIe controller.
>
> Signed-off-by: Minghuan Lian 
> ---
>  drivers/pci/pci_common.c | 10 --
>  1 file changed, 10 deletions(-)
>
> diff --git a/drivers/pci/pci_common.c b/drivers/pci/pci_common.c
> index 1755914..448e814 100644
> --- a/drivers/pci/pci_common.c
> +++ b/drivers/pci/pci_common.c
> @@ -181,11 +181,6 @@ phys_addr_t pci_hose_bus_to_phys(struct pci_controller 
> *hose,
> return phys_addr;
> }
>
> -#ifdef CONFIG_DM_PCI
> -   /* The root controller has the region information */
> -   hose = pci_bus_to_hose(0);
> -#endif

Again if you fully convert the driver to use DM PCI, this API won't be
called. And what's broken here? The comment says "The root controller
has the region information", which is correct.

> -
> /*
>  * if PCI_REGION_MEM is set we do a two pass search with preference
>  * on matches that don't have PCI_REGION_SYS_MEMORY set
> @@ -248,11 +243,6 @@ pci_addr_t pci_hose_phys_to_bus(struct pci_controller 
> *hose,
> return bus_addr;
> }
>
> -#ifdef CONFIG_DM_PCI
> -   /* The root controller has the region information */
> -   hose = pci_bus_to_hose(0);
> -#endif
> -
> /*
>  * if PCI_REGION_MEM is set we do a two pass search with preference
>  * on matches that don't have PCI_REGION_SYS_MEMORY set
> --

Regards,
Bin
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Re: [U-Boot] [PATCH 8/9] pci: layerscape: rewrite pci driver based on DM

[Bin Meng]

Hi Minghuan,

On Mon, Oct 10, 2016 at 4:47 PM, Minghuan Lian  wrote:
> There are more than five kinds of Layerscape SoCs. unfortunately,
> PCIe controller of each SoC is a little bit different. In order
> to avoid too many macro definitions, the patch re-implement PCIe
> driver based on DM. PCIe dts node is to describe the difference.
>
> Signed-off-by: Minghuan Lian 
> ---
>  .../include/asm/arch-fsl-layerscape/immap_lsch3.h  |   8 -
>  drivers/pci/Kconfig|   8 +
>  drivers/pci/pcie_layerscape.c  | 958 
> +++--
>  include/configs/ls1012a_common.h   |  12 +
>  include/configs/ls1012aqds.h   |  24 -
>  include/configs/ls1012ardb.h   |  24 -
>  include/configs/ls1021aqds.h   |  18 +-
>  include/configs/ls1021atwr.h   |  18 +-
>  include/configs/ls1043a_common.h   |  23 +-
>  include/configs/ls2080a_common.h   |  27 +-
>  include/configs/ls2080aqds.h   |   8 -
>  include/configs/ls2080ardb.h   |   8 -

These header file changes should not be put in the same commit of the
layerscape PCIe driver conversion. They should be in a separate
commit. So you are likely to have 3 commits: firstly add DM codes with
#ifdef CONFIG_DM_PCI #endif in the layerscape PCIe driver, without
breaking the existing board support. 2nd commit to update the boards
configuration files (defconfig and the header), and 3rd commit to
remove the #ifdef CONFIG_DM_PCI #endif, only leaving the DM version
codes.

>  12 files changed, 526 insertions(+), 610 deletions(-)
>
> diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h 
> b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
> index 7acba27..bd07808 100644
> --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
> +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
> @@ -104,14 +104,6 @@
>  #define CONFIG_SYS_PCIE2_PHYS_ADDR 0x12ULL
>  #define CONFIG_SYS_PCIE3_PHYS_ADDR 0x14ULL
>  #define CONFIG_SYS_PCIE4_PHYS_ADDR 0x16ULL
> -/* LUT registers */
> -#define PCIE_LUT_BASE  0x8
> -#define PCIE_LUT_LCTRL00x7F8
> -#define PCIE_LUT_DBG   0x7FC
> -#define PCIE_LUT_UDR(n) (0x800 + (n) * 8)
> -#define PCIE_LUT_LDR(n) (0x804 + (n) * 8)
> -#define PCIE_LUT_ENABLE (1 << 31)
> -#define PCIE_LUT_ENTRY_COUNT32
>

[snip]

Regards,
Bin
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Re: [U-Boot] [PATCH 9/9] armv8: ls1046a: Enable PCIe support

[Bin Meng]

Hi Minghuan,

On Mon, Oct 10, 2016 at 4:47 PM, Minghuan Lian  wrote:
> Signed-off-by: Minghuan Lian 
> ---
>  include/configs/ls1046a_common.h | 15 +++
>  1 file changed, 15 insertions(+)
>
> diff --git a/include/configs/ls1046a_common.h 
> b/include/configs/ls1046a_common.h
> index 7c5e635..f8f5ee2 100644
> --- a/include/configs/ls1046a_common.h
> +++ b/include/configs/ls1046a_common.h
> @@ -117,6 +117,21 @@
>  #define CONFIG_SYS_I2C_MXC_I2C3
>  #define CONFIG_SYS_I2C_MXC_I2C4
>
> +/* PCIe */
> +#define CONFIG_PCI /* Enable PCI/PCIE */
> +#define CONFIG_DM_PCI  /* Enable driver mode for PCI */
> +#define CONFIG_DM_PCI_COMPAT
> +#define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */
> +#define CONFIG_SYS_PCI_64BIT

Please do not add any Kconfig option in the header file any more.
These already converted Kconfig options should be moved to boards'
defconfig files.

> +
> +#ifdef CONFIG_PCI
> +#define CONFIG_PCI_PNP
> +#define CONFIG_PCI_SCAN_SHOW
> +#define CONFIG_CMD_PCI
> +#define CONFIG_NET_MULTI
> +#define CONFIG_E1000
> +#endif
> +
>  /* Command line configuration */
>  #define CONFIG_CMD_ENV
>
> --

Regards,
Bin
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