[U-Boot] [PATCH] spl: unbreak CONFIG_SPL_MULTI_DTB_FIT after fixing CONFIG_OF_EMBED

[Goldschmidt Simon]

Commit 9bd76b80 "spl: make CONFIG_OF_EMBED pass dts through fdtgrep"
moved the fdtgrep code from scripts/Makefile.spl to dts/Makefile so
that the dtb is stripped in embedded mode, too.

This broke CONFIG_SPL_MULTI_DTB_FIT where fdtgrep is still called
from scripts/Makefile.spl to strip all dtbs in CONFIG_SPL_OF_LIST.
To fix that, cmd_fdtgrep is brought back into scripts/Makefile.spl
at the downside of having it duplicated in two makefiles.
---
 scripts/Makefile.spl | 16 
 1 file changed, 16 insertions(+)

diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl
index 64390e5785..72e74f14c3 100644
--- a/scripts/Makefile.spl
+++ b/scripts/Makefile.spl
@@ -239,6 +239,22 @@ $(obj)/$(SPL_BIN)-pad.bin: $(obj)/$(SPL_BIN)
@bss_size_str=$(shell $(NM) $< | awk 'BEGIN {size = 0} /__bss_size/ 
{size = $$1} END {print "ibase=16; " toupper(size)}' | bc); \
dd if=/dev/zero of=$@ bs=1 count=$${bss_size_str} 2>/dev/null;
 
+# Pass the original device tree file through fdtgrep twice. The first pass
+# removes any unwanted nodes (i.e. those which don't have the
+# 'u-boot,dm-pre-reloc' property and thus are not needed by SPL. The second
+# pass removes various unused properties from the remaining nodes.
+# The output is typically a much smaller device tree file.
+ifeq ($(CONFIG_TPL_BUILD),y)
+fdtgrep_props := -b u-boot,dm-pre-reloc -b u-boot,dm-tpl
+else
+fdtgrep_props := -b u-boot,dm-pre-reloc -b u-boot,dm-spl
+endif
+quiet_cmd_fdtgrep = FDTGREP $@
+  cmd_fdtgrep = $(objtree)/tools/fdtgrep $(fdtgrep_props) -RT $< \
+   -n /chosen -n /config -O dtb | \
+   $(objtree)/tools/fdtgrep -r -O dtb - -o $@ \
+   $(addprefix -P ,$(subst $\",,$(CONFIG_OF_SPL_REMOVE_PROPS)))
+
 $(obj)/$(SPL_BIN).dtb: dts/dt-spl.dtb FORCE
$(call if_changed,copy)
 
-- 
2.12.2.windows.2

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [PATCH] spl: make CONFIG_OF_EMBED pass dts through fdtgrep

[Goldschmidt Simon]

On Tue, 09/01/18 15:43, Lokesh Vutla wrote:
> On Sunday 26 November 2017 05:08 PM, Simon Glass wrote:
> > On 21 November 2017 at 05:29, Goldschmidt Simon
> >  wrote:
> >> Building spl with CONFIG_OF_EMBED enabled results in an error message
> >> on my board: "SPL image too big". This is because the fdtgrep build
> >> step is only executed for CONFIG_OF_SEPARATE.
> >>
> >> Fix this by moving the fdtgrep build step ('cmd_fdtgreo') from
> >> scripts/Makefile.spl to dts/Makefile so that the reduced dtb is
> >> available for all kinds of spl builds.
> >>
> >> The resulting variable name for the embedded device tree blob
> >> changes, too, which is why common.h and fdtdec.c have tiny changes.
> >>
> >> Signed-off-by: Simon Goldschmidt 
> 
> This is breaking SPL build with CONFIG_SPL_MULTI_DTB_FIT enabled as it tries
> to call fdtgrep for shrinking all the dtbs in SPL_OF_LIST.

You're right. Sorry for that. I'll send a patch that fixes this.

Simon
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [PATCH] doc: bindings: soft-spi: update documentation to match the code

[Jagan Teki]

On Fri, Dec 29, 2017 at 8:25 PM, Miquel Raynal
 wrote:
> Linux bindings have been introduced in the code (removing the U-Boot
> specific ones) without documentation update. Compatible string has
> changed, as well as the four GPIO properties. Reflect this by updating
> the soft-spi.txt documentation.
>
> Fixes: 102412c415 ("dm: spi: soft_spi: switch to use linux compatible string")
> Signed-off-by: Miquel Raynal 
> ---

Applied to u-boot-spi/master

thanks!
-- 
Jagan Teki
Senior Linux Kernel Engineer | Amarula Solutions
U-Boot, Linux | Upstream Maintainer
Hyderabad, India.
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] RFE : CONFIG_OF_LIBFDT_OVERLAY=y in configs/orangepi_one_defconfig

[Jagan Teki]

On Tue, Jan 9, 2018 at 8:04 AM, Peter Robinson  wrote:
> On Mon, Jan 8, 2018 at 7:01 AM, Ken Harris  wrote:
>> Can you enable the "fdt apply" command on the "Orange Pi One" u-boot :
>
> I think most AllWinner boards would likely want/need this
> functionality in one form or another (maybe tablets/laptops based on
> AllWinner are the exception here) so you might want to see how the
> maintainers want to handle it more as a default than enabling it on
> each individual device.
>
>> diff --git a/configs/orangepi_one_defconfig b/configs/orangepi_one_defconfig
>> index 36feab204c..edc6f549dc 100644
>> --- a/configs/orangepi_one_defconfig
>> +++ b/configs/orangepi_one_defconfig
>> @@ -15,3 +15,6 @@ CONFIG_SPL=y
>>  CONFIG_SUN8I_EMAC=y
>>  CONFIG_USB_EHCI_HCD=y
>>  CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
>> +CONFIG_OF_LIBFDT=y
>> +CONFIG_OF_LIBFDT_OVERLAY=y
>> +

Supported [1] already.

[1] 
http://git.denx.de/?p=u-boot-sunxi.git;a=commitdiff;h=e7deb5772cb13bca3cdca3e29e4cb5bb85cd77b4
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [PATCH 09/11] sunxi: imply CONFIG_OF_LIBFDT_OVERLAY

[Jagan Teki]

On Thu, Dec 21, 2017 at 6:10 PM, Maxime Ripard
 wrote:
> From: Andre Heider 
>
> fdt overlay support is useful for all sunxi boards, enable per default
> and remove it from sunxi defconfigs.
>
> Signed-off-by: Andre Heider 
> Signed-off-by: Maxime Ripard 
> ---

Applied to u-boot-sunxi/master
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH] serial: lpuart: Proper device identification

[Sriram Dash]

Identify and distinguish between platform device type of MX7ULP
and LS1021A.

This is a fix to: 7edf5c45 serial: lpuart: add i.MX7ULP support

Signed-off-by: Sriram Dash 
Acked-by: Peng Fan 
---
 drivers/serial/serial_lpuart.c | 18 +++---
 1 file changed, 7 insertions(+), 11 deletions(-)

diff --git a/drivers/serial/serial_lpuart.c b/drivers/serial/serial_lpuart.c
index 382f8ba..536d30f 100644
--- a/drivers/serial/serial_lpuart.c
+++ b/drivers/serial/serial_lpuart.c
@@ -265,11 +265,9 @@ static int _lpuart32_serial_getc(struct 
lpuart_serial_platdata *plat)
 
lpuart_read32(plat->flags, >data, );
 
-   if (plat->devtype & DEV_MX7ULP) {
-   lpuart_read32(plat->flags, >stat, );
-   if (stat & STAT_OR)
-   lpuart_write32(plat->flags, >stat, STAT_OR);
-   }
+   lpuart_read32(plat->flags, >stat, );
+   if (stat & STAT_OR)
+   lpuart_write32(plat->flags, >stat, STAT_OR);
 
return val & 0x3ff;
 }
@@ -280,10 +278,8 @@ static void _lpuart32_serial_putc(struct 
lpuart_serial_platdata *plat,
struct lpuart_fsl_reg32 *base = plat->reg;
u32 stat;
 
-   if (plat->devtype & DEV_MX7ULP) {
-   if (c == '\n')
-   serial_putc('\r');
-   }
+   if (c == '\n')
+   serial_putc('\r');
 
while (true) {
lpuart_read32(plat->flags, >stat, );
@@ -330,7 +326,7 @@ static int _lpuart32_serial_init(struct 
lpuart_serial_platdata *plat)
 
lpuart_write32(plat->flags, >match, 0);
 
-   if (plat->devtype & DEV_MX7ULP) {
+   if (plat->devtype == DEV_MX7ULP) {
_lpuart32_serial_setbrg_7ulp(plat, gd->baudrate);
} else {
/* provide data bits, parity, stop bit, etc */
@@ -347,7 +343,7 @@ static int lpuart_serial_setbrg(struct udevice *dev, int 
baudrate)
struct lpuart_serial_platdata *plat = dev->platdata;
 
if (is_lpuart32(dev)) {
-   if (plat->devtype & DEV_MX7ULP)
+   if (plat->devtype == DEV_MX7ULP)
_lpuart32_serial_setbrg_7ulp(plat, baudrate);
else
_lpuart32_serial_setbrg(plat, baudrate);
-- 
1.9.1

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [PATCH 08/11] net: regex: Disable by default on sunXi

[Jagan Teki]

On Thu, Dec 21, 2017 at 9:35 PM, Andre Przywara  wrote:
> Hi,
>
> On 21/12/17 12:40, Maxime Ripard wrote:
>> The sunXi arm64 build has overflown, leading to the main U-boot binary
>> overwriting the environment when flashing the new image, or even worse,
>> overwriting itself when we're calling saveenv.
>>
>> Disable this command that is not critical until we can adress the issue
>> properly.
>
> Nit: this not a command.
>
>> Signed-off-by: Maxime Ripard 
>
> Reviewed-by: Andre Przywara 

Fixed nit

Applied to u-boot-sunxi/master
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [PATCH 07/11] video: bpp16: Disable by default on sunXi

[Jagan Teki]

On Thu, Dec 21, 2017 at 9:42 PM, Anatolij Gustschin  wrote:
> On Thu, 21 Dec 2017 13:40:26 +0100
> Maxime Ripard maxime.rip...@free-electrons.com wrote:
>
>> The sunXi arm64 build has overflown, leading to the main U-boot binary
>> overwriting the environment when flashing the new image, or even worse,
>> overwriting itself when we're calling saveenv.
>>
>> Disable this command that is not critical until we can adress the issue
>> properly.
>>
>> Signed-off-by: Maxime Ripard 
>
> Reviewed-by: Anatolij Gustschin 

Applied to u-boot-sunxi/master
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [PATCH 06/11] video: bpp8: Disable by default on sunXi

[Jagan Teki]

On Thu, Dec 21, 2017 at 9:31 PM, Anatolij Gustschin  wrote:
> On Thu, 21 Dec 2017 13:40:25 +0100
> Maxime Ripard maxime.rip...@free-electrons.com wrote:
>
>> The sunXi arm64 build has overflown, leading to the main U-boot binary
>> overwriting the environment when flashing the new image, or even worse,
>> overwriting itself when we're calling saveenv.
>>
>> Disable this command that is not critical until we can adress the issue
>> properly.
>>
>> Signed-off-by: Maxime Ripard 
>
> Reviewed-by: Anatolij Gustschin 

Applied to u-boot-sunxi/master
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [PATCH 05/11] cmd: misc: Disable by default on sunXi

[Jagan Teki]

On Thu, Dec 21, 2017 at 6:10 PM, Maxime Ripard
 wrote:
> The sunXi arm64 build has overflown, leading to the main U-boot binary
> overwriting the environment when flashing the new image, or even worse,
> overwriting itself when we're calling saveenv.
>
> Disable this command that is not critical until we can adress the issue
> properly.
>
> Signed-off-by: Maxime Ripard 
> ---

Applied to u-boot-sunxi/master
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [PATCH 04/11] cmd: loads: Disable by default on sunXi

[Jagan Teki]

On Thu, Dec 21, 2017 at 6:10 PM, Maxime Ripard
 wrote:
> The sunXi arm64 build has overflown, leading to the main U-boot binary
> overwriting the environment when flashing the new image, or even worse,
> overwriting itself when we're calling saveenv.
>
> Disable this command that is not critical until we can adress the issue
> properly.
>
> Signed-off-by: Maxime Ripard 
> ---

Applied to u-boot-sunxi/master
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [PATCH 03/11] cmd: loadb: Disable by default on sunXi

[Jagan Teki]

On Thu, Dec 21, 2017 at 6:10 PM, Maxime Ripard
 wrote:
> The sunXi arm64 build has overflown, leading to the main U-boot binary
> overwriting the environment when flashing the new image, or even worse,
> overwriting itself when we're calling saveenv.
>
> Disable this command that is not critical until we can adress the issue
> properly.
>
> Signed-off-by: Maxime Ripard 
> ---

Applied to u-boot-sunxi/master
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [PATCH 02/11] cmd: unzip: Disable by default on sunXi

[Jagan Teki]

On Thu, Dec 21, 2017 at 6:10 PM, Maxime Ripard
 wrote:
> The sunXi arm64 build has overflown, leading to the main U-boot binary
> overwriting the environment when flashing the new image, or even worse,
> overwriting itself when we're calling saveenv.
>
> Disable this command that is not critical until we can adress the issue
> properly.
>
> Signed-off-by: Maxime Ripard 
> ---

Applied to u-boot-sunxi/master
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [PATCH 01/11] cmd: crc32: Disable by default on sunXi

[Jagan Teki]

On Thu, Dec 21, 2017 at 6:10 PM, Maxime Ripard
 wrote:
> The sunXi arm64 build has overflown, leading to the main U-boot binary
> overwriting the environment when flashing the new image, or even worse,
> overwriting itself when we're calling saveenv.
>
> Disable this command that is not critical until we can adress the issue
> properly.
>
> Signed-off-by: Maxime Ripard 
> ---

Applied to u-boot-sunxi/master
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [PATCH v2] musb: sunxi: Use base address from device tree

[Jagan Teki]

On Thu, Jan 4, 2018 at 6:55 PM, Maxime Ripard
 wrote:
> On Sat, Dec 30, 2017 at 08:44:07PM +0800, Chen-Yu Tsai wrote:
>> Now that the musb sunxi glue driver is completely device model / device
>> tree driven, we should use the base address from the device tree,
>> instead of hard-coding it in the source code.
>>
>> Fixes: 3a61b080acee ("musb: sunxi: switch to the device model")
>> Signed-off-by: Chen-Yu Tsai 
>
> Acked-by: Maxime Ripard 

Applied to u-boot-sunxi/master
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [PATCH] ARM: sunxi: Remove left-over cd-inverted property from pcDuino3

[Jagan Teki]

On Thu, Jan 4, 2018 at 8:34 PM, Maxime Ripard
 wrote:
> On Sat, Dec 23, 2017 at 12:30:56AM +0200, Tuomas Tynkkynen wrote:
>> Commit 8620f384098b ("dm: sunxi: Linksprite_pcDuino3: Correct polarity
>> of MMC card detect") claims that the Pcduino3 device tree had an
>> incorrect polarity for the card detect pin and thus changed the polarity
>> flag of the cd-gpios from GPIO_ACTIVE_HIGH to GPIO_ACTIVE_LOW.
>>
>> Actually the DT was correct since according to the mmc binding, a
>> combination of GPIO_ACTIVE_HIGH + cd-inverted results in an active-low
>> polarity. But because the U-Boot driver lacks the code to look at the
>> cd-inverted property (unlike the Linux driver) it interpreted the
>> polarity of active-high. Thus, after that commit the DT is actually
>> wrong from the binding/Linux point of view.
>>
>> To make both Linux and U-Boot interpret the DT in the same way, just
>> drop the left-over cd-inverted property. I've sent a Linux patch to
>> switch all sunxi DTs over to not using the cd-inverted property, so
>> eventually all sunxi boards in U-Boot will be consistent in not using
>> cd-inverted.
>>
>> Signed-off-by: Tuomas Tynkkynen 
>
> Acked-by: Maxime Ripard 

Applied to u-boot-sunxi/master
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [PATCH] sunxi: maintainers: Add myself for the TBS A711

[Jagan Teki]

On Thu, Dec 21, 2017 at 6:26 PM, Tom Rini  wrote:
> On Thu, Dec 21, 2017 at 01:55:52PM +0100, Maxime Ripard wrote:
>
>> Support for that board got introduced recently without the maintainers
>> part. Let's fix that.
>>
>> Signed-off-by: Maxime Ripard 
>
> Reviewed-by: Tom Rini 

Applied to u-boot-sunxi/master
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH V5 18/31] imx: cpu: support get_boot_device for i.MX8M

[Peng Fan]

Enable get_boot_device for i.MX8M, it supports boot type USB.

Signed-off-by: Peng Fan 
Cc: Stefano Babic 
Cc: Fabio Estevam 
---
 arch/arm/mach-imx/cpu.c | 7 ++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-imx/cpu.c b/arch/arm/mach-imx/cpu.c
index a7d89f2033..4d4d434906 100644
--- a/arch/arm/mach-imx/cpu.c
+++ b/arch/arm/mach-imx/cpu.c
@@ -410,7 +410,7 @@ u32 get_cpu_temp_grade(int *minc, int *maxc)
 }
 #endif
 
-#if defined(CONFIG_MX7)
+#if defined(CONFIG_MX7) || defined(CONFIG_MX8M)
 enum boot_device get_boot_device(void)
 {
struct bootrom_sw_info **p =
@@ -439,6 +439,11 @@ enum boot_device get_boot_device(void)
case BOOT_TYPE_SPINOR:
boot_dev = SPI_NOR_BOOT;
break;
+#ifdef CONFIG_MX8M
+   case BOOT_TYPE_USB:
+   boot_dev = USB_BOOT;
+   break;
+#endif
default:
break;
}
-- 
2.14.1

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH V5 26/31] net: fec: do not access reserved register for i.MX8M

[Peng Fan]

The MIB RAM and FIFO receive start register does not exist on
i.MX8M. Accessing these register will cause system hang.

Signed-off-by: Peng Fan 
Acked-by: Joe Hershberger 
Reviewed-by: Stefano Babic 
Reviewed-by: Fabio Estevam 
---
 drivers/net/fec_mxc.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
index 433e19f0f8..4cbc8cbbfd 100644
--- a/drivers/net/fec_mxc.c
+++ b/drivers/net/fec_mxc.c
@@ -562,8 +562,8 @@ static int fec_init(struct eth_device *dev, bd_t *bd)
writel(0x, >eth->gaddr1);
writel(0x, >eth->gaddr2);
 
-   /* Do not access reserved register for i.MX6UL */
-   if (!is_mx6ul() && !is_mx6ull()) {
+   /* Do not access reserved register */
+   if (!is_mx6ul() && !is_mx6ull() && !is_mx8m()) {
/* clear MIB RAM */
for (i = mib_ptr; i <= mib_ptr + 0xfc; i += 4)
writel(0, i);
-- 
2.14.1

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH V5 29/31] power: pmic/regulator allow dm be omitted by SPL

[Peng Fan]

Allow the dm driver be omitted by SPL.

Signed-off-by: Peng Fan 
Reviewed-by: Simon Glass 
Cc: Jaehoon Chung 
Cc: Stefano Babic 
---
 drivers/power/pmic/Makefile  | 2 +-
 drivers/power/regulator/Makefile | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/power/pmic/Makefile b/drivers/power/pmic/Makefile
index 7d6c583d34..fc19fdc701 100644
--- a/drivers/power/pmic/Makefile
+++ b/drivers/power/pmic/Makefile
@@ -8,7 +8,7 @@
 obj-$(CONFIG_DM_PMIC) += pmic-uclass.o
 obj-$(CONFIG_DM_PMIC_MAX77686) += max77686.o
 obj-$(CONFIG_DM_PMIC_MAX8998) += max8998.o
-obj-$(CONFIG_DM_PMIC_PFUZE100) += pfuze100.o
+obj-$(CONFIG_$(SPL_)DM_PMIC_PFUZE100) += pfuze100.o
 obj-$(CONFIG_PMIC_S2MPS11) += s2mps11.o
 obj-$(CONFIG_DM_PMIC_SANDBOX) += sandbox.o i2c_pmic_emul.o
 obj-$(CONFIG_PMIC_ACT8846) += act8846.o
diff --git a/drivers/power/regulator/Makefile b/drivers/power/regulator/Makefile
index 7a2e76dc82..353177d5f4 100644
--- a/drivers/power/regulator/Makefile
+++ b/drivers/power/regulator/Makefile
@@ -9,7 +9,7 @@ obj-$(CONFIG_$(SPL_)DM_REGULATOR) += regulator-uclass.o
 obj-$(CONFIG_REGULATOR_ACT8846) += act8846.o
 obj-$(CONFIG_REGULATOR_AS3722) += as3722_regulator.o
 obj-$(CONFIG_DM_REGULATOR_MAX77686) += max77686.o
-obj-$(CONFIG_DM_REGULATOR_PFUZE100) += pfuze100.o
+obj-$(CONFIG_$(SPL_)DM_PMIC_PFUZE100) += pfuze100.o
 obj-$(CONFIG_REGULATOR_PWM) += pwm_regulator.o
 obj-$(CONFIG_$(SPL_)DM_REGULATOR_FIXED) += fixed.o
 obj-$(CONFIG_$(SPL_)DM_REGULATOR_GPIO) += gpio-regulator.o
-- 
2.14.1

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH V5 17/31] imx: mx7: move get_boot_device to cpu.c

[Peng Fan]

Move get_boot_device to cpu.c to prepare adding i.MX8M support,
because i.MX8M share same code with i.MX7.

Signed-off-by: Peng Fan 
Cc: Stefano Babic 
Cc: Fabio Estevam 
---
 arch/arm/include/asm/arch-mx7/imx-regs.h  |  8 ---
 arch/arm/include/asm/mach-imx/boot_mode.h |  9 
 arch/arm/mach-imx/cpu.c   | 38 +++
 arch/arm/mach-imx/mx7/soc.c   | 35 
 4 files changed, 47 insertions(+), 43 deletions(-)

diff --git a/arch/arm/include/asm/arch-mx7/imx-regs.h 
b/arch/arm/include/asm/arch-mx7/imx-regs.h
index a421b9bc04..3726f02af5 100644
--- a/arch/arm/include/asm/arch-mx7/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx7/imx-regs.h
@@ -1210,14 +1210,6 @@ extern void pcie_power_off(void);
readl(USBOTG2_IPS_BASE_ADDR + 0x158))
 #definedisconnect_from_pc(void) writel(0x0, USBOTG1_IPS_BASE_ADDR + 
0x140)
 
-/* Boot device type */
-#define BOOT_TYPE_SD   0x1
-#define BOOT_TYPE_MMC  0x2
-#define BOOT_TYPE_NAND 0x3
-#define BOOT_TYPE_QSPI 0x4
-#define BOOT_TYPE_WEIM 0x5
-#define BOOT_TYPE_SPINOR   0x6
-
 struct bootrom_sw_info {
u8 reserved_1;
u8 boot_dev_instance;
diff --git a/arch/arm/include/asm/mach-imx/boot_mode.h 
b/arch/arm/include/asm/mach-imx/boot_mode.h
index e3ed046b25..300868a45e 100644
--- a/arch/arm/include/asm/mach-imx/boot_mode.h
+++ b/arch/arm/include/asm/mach-imx/boot_mode.h
@@ -31,6 +31,15 @@ enum boot_device {
BOOT_DEV_NUM = UNKNOWN_BOOT,
 };
 
+/* Boot device type */
+#define BOOT_TYPE_SD   0x1
+#define BOOT_TYPE_MMC  0x2
+#define BOOT_TYPE_NAND 0x3
+#define BOOT_TYPE_QSPI 0x4
+#define BOOT_TYPE_WEIM 0x5
+#define BOOT_TYPE_SPINOR   0x6
+#define BOOT_TYPE_USB  0xF
+
 struct boot_mode {
const char *name;
unsigned cfg_val;
diff --git a/arch/arm/mach-imx/cpu.c b/arch/arm/mach-imx/cpu.c
index fd6d08c533..a7d89f2033 100644
--- a/arch/arm/mach-imx/cpu.c
+++ b/arch/arm/mach-imx/cpu.c
@@ -16,6 +16,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -409,6 +410,43 @@ u32 get_cpu_temp_grade(int *minc, int *maxc)
 }
 #endif
 
+#if defined(CONFIG_MX7)
+enum boot_device get_boot_device(void)
+{
+   struct bootrom_sw_info **p =
+   (struct bootrom_sw_info **)(ulong)ROM_SW_INFO_ADDR;
+
+   enum boot_device boot_dev = SD1_BOOT;
+   u8 boot_type = (*p)->boot_dev_type;
+   u8 boot_instance = (*p)->boot_dev_instance;
+
+   switch (boot_type) {
+   case BOOT_TYPE_SD:
+   boot_dev = boot_instance + SD1_BOOT;
+   break;
+   case BOOT_TYPE_MMC:
+   boot_dev = boot_instance + MMC1_BOOT;
+   break;
+   case BOOT_TYPE_NAND:
+   boot_dev = NAND_BOOT;
+   break;
+   case BOOT_TYPE_QSPI:
+   boot_dev = QSPI_BOOT;
+   break;
+   case BOOT_TYPE_WEIM:
+   boot_dev = WEIM_NOR_BOOT;
+   break;
+   case BOOT_TYPE_SPINOR:
+   boot_dev = SPI_NOR_BOOT;
+   break;
+   default:
+   break;
+   }
+
+   return boot_dev;
+}
+#endif
+
 #ifdef CONFIG_NXP_BOARD_REVISION
 int nxp_board_rev(void)
 {
diff --git a/arch/arm/mach-imx/mx7/soc.c b/arch/arm/mach-imx/mx7/soc.c
index 72dbd625c9..62bd3a0e5f 100644
--- a/arch/arm/mach-imx/mx7/soc.c
+++ b/arch/arm/mach-imx/mx7/soc.c
@@ -250,41 +250,6 @@ const struct boot_mode soc_boot_modes[] = {
{NULL,  0},
 };
 
-enum boot_device get_boot_device(void)
-{
-   struct bootrom_sw_info **p =
-   (struct bootrom_sw_info **)ROM_SW_INFO_ADDR;
-
-   enum boot_device boot_dev = SD1_BOOT;
-   u8 boot_type = (*p)->boot_dev_type;
-   u8 boot_instance = (*p)->boot_dev_instance;
-
-   switch (boot_type) {
-   case BOOT_TYPE_SD:
-   boot_dev = boot_instance + SD1_BOOT;
-   break;
-   case BOOT_TYPE_MMC:
-   boot_dev = boot_instance + MMC1_BOOT;
-   break;
-   case BOOT_TYPE_NAND:
-   boot_dev = NAND_BOOT;
-   break;
-   case BOOT_TYPE_QSPI:
-   boot_dev = QSPI_BOOT;
-   break;
-   case BOOT_TYPE_WEIM:
-   boot_dev = WEIM_NOR_BOOT;
-   break;
-   case BOOT_TYPE_SPINOR:
-   boot_dev = SPI_NOR_BOOT;
-   break;
-   default:
-   break;
-   }
-
-   return boot_dev;
-}
-
 #ifdef CONFIG_ENV_IS_IN_MMC
 __weak int board_mmc_get_env_dev(int devno)
 {
-- 
2.14.1

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH V5 22/31] misc: ocotp: add i.MX8M support

[Peng Fan]

i.MX8M OCOTP follow same flow as i.MX6Q, but it has 64 banks
and each bank 4 words.

Signed-off-by: Peng Fan 
Reviewed-by: Stefano Babic 
Reviewed-by: Fabio Estevam 
---
 drivers/misc/mxc_ocotp.c | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/drivers/misc/mxc_ocotp.c b/drivers/misc/mxc_ocotp.c
index 8986bb4ad0..0cf24a4c88 100644
--- a/drivers/misc/mxc_ocotp.c
+++ b/drivers/misc/mxc_ocotp.c
@@ -35,6 +35,8 @@
 #define BM_OUT_STATUS_DED  0x0400
 #define BM_OUT_STATUS_LOCKED   0x0800
 #define BM_OUT_STATUS_PROGFAIL 0x1000
+#elif defined(CONFIG_MX8M)
+#define BM_CTRL_ADDR   0x00ff
 #else
 #define BM_CTRL_ADDR   0x007f
 #endif
@@ -79,6 +81,9 @@
 #elif defined(CONFIG_MX7ULP)
 #define FUSE_BANK_SIZE 0x80
 #define FUSE_BANKS 31
+#elif defined(CONFIG_MX8M)
+#define FUSE_BANK_SIZE 0x40
+#define FUSE_BANKS 64
 #else
 #error "Unsupported architecture\n"
 #endif
@@ -294,6 +299,8 @@ static void setup_direct_access(struct ocotp_regs *regs, 
u32 bank, u32 word,
u32 wr_unlock = write ? BV_CTRL_WR_UNLOCK_KEY : 0;
 #ifdef CONFIG_MX7
u32 addr = bank;
+#elif defined CONFIG_MX8M
+   u32 addr = bank << 2 | word;
 #else
u32 addr;
/* Bank 7 and Bank 8 only supports 4 words each for i.MX6ULL */
-- 
2.14.1

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH V5 25/31] gpio: mxc: add i.MX8M support

[Peng Fan]

Add i.MX8M GPIO support.
There are 4 GPIO banks on i.MX8M.

Signed-off-by: Peng Fan 
Reviewed-by: Fabio Estevam 
Cc: Stefano Babic 
---
 drivers/gpio/mxc_gpio.c | 22 +++---
 1 file changed, 15 insertions(+), 7 deletions(-)

diff --git a/drivers/gpio/mxc_gpio.c b/drivers/gpio/mxc_gpio.c
index cfa620bceb..d0e365a54b 100644
--- a/drivers/gpio/mxc_gpio.c
+++ b/drivers/gpio/mxc_gpio.c
@@ -41,13 +41,13 @@ static unsigned long gpio_ports[] = {
[2] = GPIO3_BASE_ADDR,
 #if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX51) || \
defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
-   defined(CONFIG_MX7)
+   defined(CONFIG_MX7) || defined(CONFIG_MX8M)
[3] = GPIO4_BASE_ADDR,
 #endif
 #if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
-   defined(CONFIG_MX7)
+   defined(CONFIG_MX7) || defined(CONFIG_MX8M)
[4] = GPIO5_BASE_ADDR,
-#if !(defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL))
+#if !(defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || defined(CONFIG_MX8M))
[5] = GPIO6_BASE_ADDR,
 #endif
 #endif
@@ -349,13 +349,17 @@ static const struct mxc_gpio_plat mxc_plat[] = {
{ 1, (struct gpio_regs *)GPIO2_BASE_ADDR },
{ 2, (struct gpio_regs *)GPIO3_BASE_ADDR },
 #if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX51) || \
-   defined(CONFIG_MX53) || defined(CONFIG_MX6)
+   defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
+   defined(CONFIG_MX8M)
{ 3, (struct gpio_regs *)GPIO4_BASE_ADDR },
 #endif
-#if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6)
+#if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
+   defined(CONFIG_MX8M)
{ 4, (struct gpio_regs *)GPIO5_BASE_ADDR },
+#ifndef CONFIG_MX8M
{ 5, (struct gpio_regs *)GPIO6_BASE_ADDR },
 #endif
+#endif
 #if defined(CONFIG_MX53) || defined(CONFIG_MX6)
{ 6, (struct gpio_regs *)GPIO7_BASE_ADDR },
 #endif
@@ -366,13 +370,17 @@ U_BOOT_DEVICES(mxc_gpios) = {
{ "gpio_mxc", _plat[1] },
{ "gpio_mxc", _plat[2] },
 #if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX51) || \
-   defined(CONFIG_MX53) || defined(CONFIG_MX6)
+   defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
+   defined(CONFIG_MX8M)
{ "gpio_mxc", _plat[3] },
 #endif
-#if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6)
+#if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
+   defined(CONFIG_MX8M)
{ "gpio_mxc", _plat[4] },
+#ifndef CONFIG_MX8M
{ "gpio_mxc", _plat[5] },
 #endif
+#endif
 #if defined(CONFIG_MX53) || defined(CONFIG_MX6)
{ "gpio_mxc", _plat[6] },
 #endif
-- 
2.14.1

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH V5 31/31] imx: add i.MX8MQ EVK support

[Peng Fan]

Add i.MX8MQ EVK support. SPL will initialize ddr and load ddr phy
firmware. Then loading FIT image, ATF to OCRAM, U-Boot and DTB to
DRAM.

The boot log with Arm trusted firmware console enabled:
"
U-Boot SPL 2018.01-00038-gbd426c08ea (Jan 10 2018 - 13:14:56)
PMIC:  PFUZE100 ID=0x10
Normal Boot
Trying to boot from MMC2
NOTICE:  Configureing TZASC380
NOTICE:  BL31: v1.4(release):o8.0.0_1.3.0_8m-prc-20171211-6-g54fb0797-dirty
NOTICE:  BL31: Built : 07:17:16, Jan  8 2018
NOTICE:  sip svc init

U-Boot 2018.01-00038-gbd426c08ea (Jan 10 2018 - 13:14:56 +0800)

CPU:   Freescale i.MX8MQ rev2.0 at 1000 MHz
Reset cause: POR
Model: Freescale i.MX8MQ EVK
DRAM:  3 GiB
MMC:   FSL_SDHC: 0, FSL_SDHC: 1
Using default environment

In:serial
Out:   serial
Err:   serial
Net:   No ethernet found.
Hit any key to stop autoboot:  0
u-boot=>
"

Signed-off-by: Peng Fan 
Cc: Fabio Estevam 
Cc: Stefano Babic 
---
 arch/arm/dts/Makefile|2 +
 arch/arm/dts/fsl-imx8mq-evk.dts  |  424 +
 arch/arm/include/asm/arch-mx8m/ddr.h |9 +
 arch/arm/mach-imx/mx8m/Kconfig   |   12 +
 board/freescale/mx8mq_evk/Kconfig|   12 +
 board/freescale/mx8mq_evk/Makefile   |   12 +
 board/freescale/mx8mq_evk/README |   47 +
 board/freescale/mx8mq_evk/ddr/ddr_init.c |  246 +
 board/freescale/mx8mq_evk/ddr/ddrphy_train.c | 1272 ++
 board/freescale/mx8mq_evk/ddr/helper.c   |  101 ++
 board/freescale/mx8mq_evk/mx8mq_evk.c|  156 
 board/freescale/mx8mq_evk/spl.c  |  230 +
 configs/mx8mq_evk_defconfig  |   27 +
 include/configs/mx8mq_evk.h  |  269 ++
 14 files changed, 2819 insertions(+)
 create mode 100644 arch/arm/dts/fsl-imx8mq-evk.dts
 create mode 100644 board/freescale/mx8mq_evk/Kconfig
 create mode 100644 board/freescale/mx8mq_evk/Makefile
 create mode 100644 board/freescale/mx8mq_evk/README
 create mode 100644 board/freescale/mx8mq_evk/ddr/ddr_init.c
 create mode 100644 board/freescale/mx8mq_evk/ddr/ddrphy_train.c
 create mode 100644 board/freescale/mx8mq_evk/ddr/helper.c
 create mode 100644 board/freescale/mx8mq_evk/mx8mq_evk.c
 create mode 100644 board/freescale/mx8mq_evk/spl.c
 create mode 100644 configs/mx8mq_evk_defconfig
 create mode 100644 include/configs/mx8mq_evk.h

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index a895c70284..299107977f 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -391,6 +391,8 @@ dtb-$(CONFIG_MX7) += imx7-colibri.dtb \
 
 dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-evk.dtb
 
+dtb-$(CONFIG_ARCH_MX8M) += fsl-imx8mq-evk.dtb
+
 dtb-$(CONFIG_RCAR_GEN3) += \
r8a7795-h3ulcb.dtb \
r8a7795-salvator-x.dtb \
diff --git a/arch/arm/dts/fsl-imx8mq-evk.dts b/arch/arm/dts/fsl-imx8mq-evk.dts
new file mode 100644
index 00..f0aa3485e6
--- /dev/null
+++ b/arch/arm/dts/fsl-imx8mq-evk.dts
@@ -0,0 +1,424 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+
+/* First 128KB is for PSCI ATF. */
+/memreserve/ 0x4000 0x0002;
+
+#include "fsl-imx8mq.dtsi"
+
+/ {
+   model = "Freescale i.MX8MQ EVK";
+   compatible = "fsl,imx8mq-evk", "fsl,imx8mq";
+
+   chosen {
+   bootargs = "console=ttymxc0,115200 
earlycon=ec_imx6q,0x3086,115200";
+   };
+
+   regulators {
+   compatible = "simple-bus";
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   reg_usdhc2_vmmc: usdhc2_vmmc {
+   compatible = "regulator-fixed";
+   regulator-name = "VSD_3V3";
+   regulator-min-microvolt = <330>;
+   regulator-max-microvolt = <330>;
+   gpio = < 19 GPIO_ACTIVE_HIGH>;
+   enable-active-high;
+   };
+   };
+
+   pwmleds {
+   compatible = "pwm-leds";
+
+   ledpwm2 {
+   label = "PWM2";
+   pwms = < 0 5>;
+   max-brightness = <255>;
+   };
+   };
+};
+
+ {
+   pinctrl-names = "default";
+
+   imx8mq-evk {
+   pinctrl_fec1: fec1grp {
+   fsl,pins = <
+   MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3
+  

[U-Boot] [PATCH V5 24/31] imx: lcdif: include i.MX8M

[Peng Fan]

Include i.MX8M in lcdif register layout map.
Also included i.MX7ULP in this patch, since share same with i.MX8M.

Signed-off-by: Peng Fan 
Reviewed-by: Stefano Babic 
Reviewed-by: Fabio Estevam 
---
 arch/arm/include/asm/mach-imx/regs-lcdif.h | 10 ++
 1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/arch/arm/include/asm/mach-imx/regs-lcdif.h 
b/arch/arm/include/asm/mach-imx/regs-lcdif.h
index c6cf03bf5a..38a2c6d4ee 100644
--- a/arch/arm/include/asm/mach-imx/regs-lcdif.h
+++ b/arch/arm/include/asm/mach-imx/regs-lcdif.h
@@ -19,11 +19,11 @@
 struct mxs_lcdif_regs {
mxs_reg_32(hw_lcdif_ctrl)   /* 0x00 */
mxs_reg_32(hw_lcdif_ctrl1)  /* 0x10 */
-
 #if defined(CONFIG_MX28) || defined(CONFIG_MX6SX) || \
defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL) || \
defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || \
-   defined(CONFIG_MX7)
+   defined(CONFIG_MX7) || defined(CONFIG_MX7ULP) || \
+   defined(CONFIG_MX8M)
mxs_reg_32(hw_lcdif_ctrl2)  /* 0x20 */
 #endif
mxs_reg_32(hw_lcdif_transfer_count) /* 0x20/0x30 */
@@ -61,7 +61,8 @@ struct mxs_lcdif_regs {
 #if defined(CONFIG_MX28) || defined(CONFIG_MX6SX) || \
defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL) || \
defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || \
-   defined(CONFIG_MX7)
+   defined(CONFIG_MX7) || defined(CONFIG_MX7ULP) || \
+   defined(CONFIG_MX8M)
mxs_reg_32(hw_lcdif_crc_stat)   /* 0x1a0 */
 #endif
mxs_reg_32(hw_lcdif_lcdif_stat) /* 0x1d0/0x1b0 */
@@ -72,7 +73,8 @@ struct mxs_lcdif_regs {
 #if defined(CONFIG_MX6SX) || \
defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL) || \
defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || \
-   defined(CONFIG_MX7)
+   defined(CONFIG_MX7) || defined(CONFIG_MX7ULP) || \
+   defined(CONFIG_MX8M)
mxs_reg_32(hw_lcdif_thres)
mxs_reg_32(hw_lcdif_as_ctrl)
mxs_reg_32(hw_lcdif_as_buf)
-- 
2.14.1

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH V5 23/31] mmc: fsl_esdhc: support i.MX8M

[Peng Fan]

Support i.MX8M in fsl esdhc driver.

Signed-off-by: Peng Fan 
Reviewed-by: Stefano Babic 
Reviewed-by: Fabio Estevam 
---
 drivers/mmc/fsl_esdhc.c | 12 
 1 file changed, 8 insertions(+), 4 deletions(-)

diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index 499d622c6d..3a56f7c2bc 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -228,7 +228,8 @@ static int esdhc_setup_data(struct fsl_esdhc_priv *priv, 
struct mmc *mmc,
 {
int timeout;
struct fsl_esdhc *regs = priv->esdhc_regs;
-#if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234)
+#if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \
+   defined(CONFIG_MX8M)
dma_addr_t addr;
 #endif
uint wml_value;
@@ -241,7 +242,8 @@ static int esdhc_setup_data(struct fsl_esdhc_priv *priv, 
struct mmc *mmc,
 
esdhc_clrsetbits32(>wml, WML_RD_WML_MASK, wml_value);
 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
-#if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234)
+#if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \
+   defined(CONFIG_MX8M)
addr = virt_to_phys((void *)(data->dest));
if (upper_32_bits(addr))
printf("Error found for upper 32 bits\n");
@@ -270,7 +272,8 @@ static int esdhc_setup_data(struct fsl_esdhc_priv *priv, 
struct mmc *mmc,
esdhc_clrsetbits32(>wml, WML_WR_WML_MASK,
wml_value << 16);
 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
-#if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234)
+#if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \
+   defined(CONFIG_MX8M)
addr = virt_to_phys((void *)(data->src));
if (upper_32_bits(addr))
printf("Error found for upper 32 bits\n");
@@ -335,7 +338,8 @@ static void check_and_invalidate_dcache_range
unsigned end = 0;
unsigned size = roundup(ARCH_DMA_MINALIGN,
data->blocks*data->blocksize);
-#if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234)
+#if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \
+   defined(CONFIG_MX8M)
dma_addr_t addr;
 
addr = virt_to_phys((void *)(data->dest));
-- 
2.14.1

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH V5 16/31] imx: bootaux: support i.MX8M

[Peng Fan]

Add i.MX8M support. Because i.MX8M use SiP call trap
to Arm Trusted Firmware to handle M4, so use #ifdef
to avoid build error on i.MX6/7.

Signed-off-by: Peng Fan 
---
 arch/arm/mach-imx/imx_bootaux.c | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/arch/arm/mach-imx/imx_bootaux.c b/arch/arm/mach-imx/imx_bootaux.c
index 02728514b7..6256b3a778 100644
--- a/arch/arm/mach-imx/imx_bootaux.c
+++ b/arch/arm/mach-imx/imx_bootaux.c
@@ -6,7 +6,9 @@
 
 #include 
 #include 
+#include 
 #include 
+#include 
 #include 
 
 int arch_auxiliary_core_up(u32 core_id, ulong boot_private_data)
@@ -24,14 +26,21 @@ int arch_auxiliary_core_up(u32 core_id, ulong 
boot_private_data)
writel(pc, M4_BOOTROM_BASE_ADDR + 4);
 
/* Enable M4 */
+#ifdef CONFIG_MX8M
+   call_imx_sip(IMX_SIP_SRC, IMX_SIP_SRC_M4_START, 0, 0);
+#else
clrsetbits_le32(SRC_BASE_ADDR + SRC_M4_REG_OFFSET,
SRC_M4C_NON_SCLR_RST_MASK, SRC_M4_ENABLE_MASK);
+#endif
 
return 0;
 }
 
 int arch_auxiliary_core_check_up(u32 core_id)
 {
+#ifdef CONFIG_MX8M
+   return call_imx_sip(IMX_SIP_SRC, IMX_SIP_SRC_M4_STARTED, 0, 0);
+#else
unsigned int val;
 
val = readl(SRC_BASE_ADDR + SRC_M4_REG_OFFSET);
@@ -40,6 +49,7 @@ int arch_auxiliary_core_check_up(u32 core_id)
return 0;  /* assert in reset */
 
return 1;
+#endif
 }
 
 /*
-- 
2.14.1

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH V5 30/31] imx: mx8m: add ddr controller memory map

[Peng Fan]

Add ddrc memory map and enum types used in ddr initialization.

Signed-off-by: Peng Fan 
Cc: Fabio Estevam 
Cc: Stefano Babic 
---
 arch/arm/include/asm/arch-mx8m/ddr.h | 356 +++
 1 file changed, 356 insertions(+)
 create mode 100644 arch/arm/include/asm/arch-mx8m/ddr.h

diff --git a/arch/arm/include/asm/arch-mx8m/ddr.h 
b/arch/arm/include/asm/arch-mx8m/ddr.h
new file mode 100644
index 00..b37382eab0
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx8m/ddr.h
@@ -0,0 +1,356 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_MX8M_DDR_H
+#define __ASM_ARCH_MX8M_DDR_H
+
+#define DDRC_DDR_SS_GPR0   0x3d00
+#define DDRC_IPS_BASE_ADDR_0   0x3f40
+#define IP2APB_DDRPHY_IPS_BASE_ADDR(X) (0x3c00 + (X * 0x200))
+#define DDRPHY_MEM(X)  (0x3c00 + (X * 0x200) + 0x5)
+
+struct ddrc_freq {
+   u32 res0[8];
+   u32 derateen;
+   u32 derateint;
+   u32 res1[10];
+   u32 rfshctl0;
+   u32 res2[4];
+   u32 rfshtmg;
+   u32 rfshtmg1;
+   u32 res3[28];
+   u32 init3;
+   u32 init4;
+   u32 res;
+   u32 init6;
+   u32 init7;
+   u32 res4[4];
+   u32 dramtmg0;
+   u32 dramtmg1;
+   u32 dramtmg2;
+   u32 dramtmg3;
+   u32 dramtmg4;
+   u32 dramtmg5;
+   u32 dramtmg6;
+   u32 dramtmg7;
+   u32 dramtmg8;
+   u32 dramtmg9;
+   u32 dramtmg10;
+   u32 dramtmg11;
+   u32 dramtmg12;
+   u32 dramtmg13;
+   u32 dramtmg14;
+   u32 dramtmg15;
+   u32 dramtmg16;
+   u32 dramtmg17;
+   u32 res5[10];
+   u32 mramtmg0;
+   u32 mramtmg1;
+   u32 mramtmg4;
+   u32 mramtmg9;
+   u32 zqctl0;
+   u32 res6[3];
+   u32 dfitmg0;
+   u32 dfitmg1;
+   u32 res7[7];
+   u32 dfitmg2;
+   u32 dfitmg3;
+   u32 res8[33];
+   u32 odtcfg;
+};
+
+struct imx8m_ddrc_regs {
+   u32 mstr;
+   u32 stat;
+   u32 mstr1;
+   u32 res1;
+   u32 mrctrl0;
+   u32 mrctrl1;
+   u32 mrstat;
+   u32 mrctrl2;
+   u32 derateen;
+   u32 derateint;
+   u32 mstr2;
+   u32 res2;
+   u32 pwrctl;
+   u32 pwrtmg;
+   u32 hwlpctl;
+   u32 hwffcctl;
+   u32 hwffcstat;
+   u32 res3[3];
+   u32 rfshctl0;
+   u32 rfshctl1;
+   u32 rfshctl2;
+   u32 rfshctl4;
+   u32 rfshctl3;
+   u32 rfshtmg;
+   u32 rfshtmg1;
+   u32 res4;
+   u32 ecccfg0;
+   u32 ecccfg1;
+   u32 eccstat;
+   u32 eccclr;
+   u32 eccerrcnt;
+   u32 ecccaddr0;
+   u32 ecccaddr1;
+   u32 ecccsyn0;
+   u32 ecccsyn1;
+   u32 ecccsyn2;
+   u32 eccbitmask0;
+   u32 eccbitmask1;
+   u32 eccbitmask2;
+   u32 eccuaddr0;
+   u32 eccuaddr1;
+   u32 eccusyn0;
+   u32 eccusyn1;
+   u32 eccusyn2;
+   u32 eccpoisonaddr0;
+   u32 eccpoisonaddr1;
+   u32 crcparctl0;
+   u32 crcparctl1;
+   u32 crcparctl2;
+   u32 crcparstat;
+   u32 init0;
+   u32 init1;
+   u32 init2;
+   u32 init3;
+   u32 init4;
+   u32 init5;
+   u32 init6;
+   u32 init7;
+   u32 dimmctl;
+   u32 rankctl;
+   u32 res5;
+   u32 chctl;
+   u32 dramtmg0;
+   u32 dramtmg1;
+   u32 dramtmg2;
+   u32 dramtmg3;
+   u32 dramtmg4;
+   u32 dramtmg5;
+   u32 dramtmg6;
+   u32 dramtmg7;
+   u32 dramtmg8;
+   u32 dramtmg9;
+   u32 dramtmg10;
+   u32 dramtmg11;
+   u32 dramtmg12;
+   u32 dramtmg13;
+   u32 dramtmg14;
+   u32 dramtmg15;
+   u32 dramtmg16;
+   u32 dramtmg17;
+   u32 res6[10];
+   u32 mramtmg0;
+   u32 mramtmg1;
+   u32 mramtmg4;
+   u32 mramtmg9;
+   u32 zqctl0;
+   u32 zqctl1;
+   u32 zqctl2;
+   u32 zqstat;
+   u32 dfitmg0;
+   u32 dfitmg1;
+   u32 dfilpcfg0;
+   u32 dfilpcfg1;
+   u32 dfiupd0;
+   u32 dfiupd1;
+   u32 dfiupd2;
+   u32 res7;
+   u32 dfimisc;
+   u32 dfitmg2;
+   u32 dfitmg3;
+   u32 dfistat;
+   u32 dbictl;
+   u32 dfiphymstr;
+   u32 res8[14];
+   u32 addrmap0;
+   u32 addrmap1;
+   u32 addrmap2;
+   u32 addrmap3;
+   u32 addrmap4;
+   u32 addrmap5;
+   u32 addrmap6;
+   u32 addrmap7;
+   u32 addrmap8;
+   u32 addrmap9;
+   u32 addrmap10;
+   u32 addrmap11;
+   u32 res9[4];
+   u32 odtcfg;
+   u32 odtmap;
+   u32 res10[2];
+   u32 sched;
+   u32 sched1;
+   u32 sched2;
+   u32 perfhpr1;
+   u32 res11;
+   u32 perflpr1;
+   u32 res12;
+   u32 perfwr1;
+   u32 res13[4];
+   u32 dqmap0;
+   u32 dqmap1;
+   u32 dqmap2;
+   u32 dqmap3;
+   u32 dqmap4;
+   u32 dqmap5;
+   u32 res14[26];
+   u32 dbg0;
+   u32 dbg1;
+   

[U-Boot] [PATCH V5 28/31] imx: imx8mq: add dtsi file

[Peng Fan]

Add dtsi file for i.MX8MQ.

Signed-off-by: Peng Fan 
Reviewed-by: Fabio Estevam 
Cc: Stefano Babic 
---
 arch/arm/dts/fsl-imx8-ca53.dtsi   |  92 +
 arch/arm/dts/fsl-imx8mq.dtsi  | 429 
 include/dt-bindings/clock/imx8mq-clock.h  | 612 +
 include/dt-bindings/pinctrl/pins-imx8mq.h | 632 ++
 4 files changed, 1765 insertions(+)
 create mode 100644 arch/arm/dts/fsl-imx8-ca53.dtsi
 create mode 100644 arch/arm/dts/fsl-imx8mq.dtsi
 create mode 100644 include/dt-bindings/clock/imx8mq-clock.h
 create mode 100644 include/dt-bindings/pinctrl/pins-imx8mq.h

diff --git a/arch/arm/dts/fsl-imx8-ca53.dtsi b/arch/arm/dts/fsl-imx8-ca53.dtsi
new file mode 100644
index 00..6a2292a51e
--- /dev/null
+++ b/arch/arm/dts/fsl-imx8-ca53.dtsi
@@ -0,0 +1,92 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/{
+   cpus {
+   #address-cells = <2>;
+   #size-cells = <0>;
+
+   idle-states {
+   entry-method = "psci";
+
+   CPU_SLEEP: cpu-sleep {
+   compatible = "arm,idle-state";
+   local-timer-stop;
+   arm,psci-suspend-param = <0x000>;
+   entry-latency-us = <700>;
+   exit-latency-us = <250>;
+   min-residency-us = <1000>;
+   };
+
+   CLUSTER_SLEEP: cluster-sleep {
+   compatible = "arm,idle-state";
+   local-timer-stop;
+   arm,psci-suspend-param = <0x100>;
+   entry-latency-us = <1000>;
+   exit-latency-us = <700>;
+   min-residency-us = <2700>;
+   wakeup-latency-us = <1500>;
+   };
+   };
+
+   /* We have 1 clusters having 4 Cortex-A53 cores */
+   A53_0: cpu@0 {
+   device_type = "cpu";
+   compatible = "arm,cortex-a53";
+   reg = <0x0 0x0>;
+   enable-method = "psci";
+   next-level-cache = <_L2>;
+   cpu-idle-states = <_SLEEP>;
+   };
+
+   A53_1: cpu@1 {
+   device_type = "cpu";
+   compatible = "arm,cortex-a53";
+   reg = <0x0 0x1>;
+   enable-method = "psci";
+   next-level-cache = <_L2>;
+   cpu-idle-states = <_SLEEP>;
+   };
+
+   A53_2: cpu@2 {
+   device_type = "cpu";
+   compatible = "arm,cortex-a53";
+   reg = <0x0 0x2>;
+   enable-method = "psci";
+   next-level-cache = <_L2>;
+   cpu-idle-states = <_SLEEP>;
+   };
+
+   A53_3: cpu@3 {
+   device_type = "cpu";
+   compatible = "arm,cortex-a53";
+   reg = <0x0 0x3>;
+   enable-method = "psci";
+   next-level-cache = <_L2>;
+   cpu-idle-states = <_SLEEP>;
+   };
+
+   A53_L2: l2-cache0 {
+   compatible = "cache";
+   };
+   };
+
+   psci {
+   compatible = "arm,psci-1.0";
+   method = "smc";
+   cpu_suspend   = <0xc401>;
+   cpu_off   = <0xc402>;
+   cpu_on= <0xc403>;
+   };
+};
diff --git a/arch/arm/dts/fsl-imx8mq.dtsi b/arch/arm/dts/fsl-imx8mq.dtsi
new file mode 100644
index 00..814a1b7df4
--- /dev/null
+++ b/arch/arm/dts/fsl-imx8mq.dtsi
@@ -0,0 +1,429 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT 

[U-Boot] [PATCH V5 27/31] net: fec: fix build warnings for 64bits support

[Peng Fan]

From: Ye Li 

When building for 64bits system, we get some warnings about type
cast between pointer and integer. This patch eliminates the warnings
by using ulong/long type which is 32bits on 32bits system or 64bits on
64bits system.

Signed-off-by: Ye Li 
Signed-off-by: Peng Fan 
Acked-by: Joe Hershberger 
Reviewed-by: Stefano Babic 
Reviewed-by: Fabio Estevam 
---
 drivers/net/fec_mxc.c | 74 ++-
 1 file changed, 43 insertions(+), 31 deletions(-)

diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
index 4cbc8cbbfd..ff7ad91116 100644
--- a/drivers/net/fec_mxc.c
+++ b/drivers/net/fec_mxc.c
@@ -284,7 +284,7 @@ static int fec_tx_task_disable(struct fec_priv *fec)
 static void fec_rbd_init(struct fec_priv *fec, int count, int dsize)
 {
uint32_t size;
-   uint8_t *data;
+   ulong data;
int i;
 
/*
@@ -293,9 +293,9 @@ static void fec_rbd_init(struct fec_priv *fec, int count, 
int dsize)
 */
size = roundup(dsize, ARCH_DMA_MINALIGN);
for (i = 0; i < count; i++) {
-   data = (uint8_t *)fec->rbd_base[i].data_pointer;
-   memset(data, 0, dsize);
-   flush_dcache_range((uint32_t)data, (uint32_t)data + size);
+   data = fec->rbd_base[i].data_pointer;
+   memset((void *)data, 0, dsize);
+   flush_dcache_range(data, data + size);
 
fec->rbd_base[i].status = FEC_RBD_EMPTY;
fec->rbd_base[i].data_length = 0;
@@ -305,8 +305,8 @@ static void fec_rbd_init(struct fec_priv *fec, int count, 
int dsize)
fec->rbd_base[i - 1].status = FEC_RBD_WRAP | FEC_RBD_EMPTY;
fec->rbd_index = 0;
 
-   flush_dcache_range((unsigned)fec->rbd_base,
-  (unsigned)fec->rbd_base + size);
+   flush_dcache_range((ulong)fec->rbd_base,
+  (ulong)fec->rbd_base + size);
 }
 
 /**
@@ -323,7 +323,7 @@ static void fec_rbd_init(struct fec_priv *fec, int count, 
int dsize)
  */
 static void fec_tbd_init(struct fec_priv *fec)
 {
-   unsigned addr = (unsigned)fec->tbd_base;
+   ulong addr = (ulong)fec->tbd_base;
unsigned size = roundup(2 * sizeof(struct fec_bd),
ARCH_DMA_MINALIGN);
 
@@ -423,7 +423,7 @@ static int fec_open(struct eth_device *edev)
struct fec_priv *fec = (struct fec_priv *)edev->priv;
 #endif
int speed;
-   uint32_t addr, size;
+   ulong addr, size;
int i;
 
debug("fec_open: fec_open(dev)\n");
@@ -439,7 +439,7 @@ static int fec_open(struct eth_device *edev)
/* Flush the descriptors into RAM */
size = roundup(FEC_RBD_NUM * sizeof(struct fec_bd),
ARCH_DMA_MINALIGN);
-   addr = (uint32_t)fec->rbd_base;
+   addr = (ulong)fec->rbd_base;
flush_dcache_range(addr, addr + size);
 
 #ifdef FEC_QUIRK_ENET_MAC
@@ -533,8 +533,9 @@ static int fec_init(struct eth_device *dev, bd_t *bd)
 #else
struct fec_priv *fec = (struct fec_priv *)dev->priv;
 #endif
-   uint32_t mib_ptr = (uint32_t)>eth->rmon_t_drop;
-   int i;
+   u8 *mib_ptr = (uint8_t *)>eth->rmon_t_drop;
+   u8 *i;
+   ulong addr;
 
/* Initialize MAC address */
 #ifdef CONFIG_DM_ETH
@@ -574,8 +575,12 @@ static int fec_init(struct eth_device *dev, bd_t *bd)
 
/* size and address of each buffer */
writel(FEC_MAX_PKT_SIZE, >eth->emrbr);
-   writel((uint32_t)fec->tbd_base, >eth->etdsr);
-   writel((uint32_t)fec->rbd_base, >eth->erdsr);
+
+   addr = (ulong)fec->tbd_base;
+   writel((uint32_t)addr, >eth->etdsr);
+
+   addr = (ulong)fec->rbd_base;
+   writel((uint32_t)addr, >eth->erdsr);
 
 #ifndef CONFIG_PHYLIB
if (fec->xcv_type != SEVENWIRE)
@@ -640,8 +645,8 @@ static int fec_send(struct eth_device *dev, void *packet, 
int length)
 #endif
 {
unsigned int status;
-   uint32_t size, end;
-   uint32_t addr;
+   u32 size;
+   ulong addr, end;
int timeout = FEC_XFER_TIMEOUT;
int ret = 0;
 
@@ -672,13 +677,13 @@ static int fec_send(struct eth_device *dev, void *packet, 
int length)
swap_packet((uint32_t *)packet, length);
 #endif
 
-   addr = (uint32_t)packet;
+   addr = (ulong)packet;
end = roundup(addr + length, ARCH_DMA_MINALIGN);
addr &= ~(ARCH_DMA_MINALIGN - 1);
flush_dcache_range(addr, end);
 
writew(length, >tbd_base[fec->tbd_index].data_length);
-   writel(addr, >tbd_base[fec->tbd_index].data_pointer);
+   writel((uint32_t)addr, >tbd_base[fec->tbd_index].data_pointer);
 
/*
 * update BD's status now
@@ -698,7 +703,7 @@ static int fec_send(struct eth_device *dev, void *packet, 
int length)
 * can start DMA.
 */
size = roundup(2 * sizeof(struct fec_bd), 

[U-Boot] [PATCH V5 15/31] imx: cleanup bootaux

[Peng Fan]

Move i.MX6/7 bootaux code to imx_bootaux.c.
The i.MX6/7 has different src layout, so define M4 reg offset
to ease the cleanup. Redefine the M4 related BIT for share
common code.

Signed-off-by: Peng Fan 
Cc: Stefano Babic 
Cc: Fabio Estevam 
---
 arch/arm/include/asm/arch-mx6/imx-regs.h |  9 
 arch/arm/include/asm/arch-mx7/imx-regs.h | 10 +
 arch/arm/mach-imx/imx_bootaux.c  | 36 +++---
 arch/arm/mach-imx/mx6/soc.c  | 38 
 arch/arm/mach-imx/mx7/soc.c  | 36 --
 5 files changed, 39 insertions(+), 90 deletions(-)

diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h 
b/arch/arm/include/asm/arch-mx6/imx-regs.h
index 48ce0edd06..8513406a8e 100644
--- a/arch/arm/include/asm/arch-mx6/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
@@ -482,10 +482,11 @@ struct src {
 
 #define src_base ((struct src *)SRC_BASE_ADDR)
 
-#define SRC_SCR_M4_ENABLE_OFFSET22
-#define SRC_SCR_M4_ENABLE_MASK  (1 << 22)
-#define SRC_SCR_M4C_NON_SCLR_RST_OFFSET 4
-#define SRC_SCR_M4C_NON_SCLR_RST_MASK   (1 << 4)
+#define SRC_M4_REG_OFFSET  0
+#define SRC_M4_ENABLE_OFFSET   22
+#define SRC_M4_ENABLE_MASK BIT(22)
+#define SRC_M4C_NON_SCLR_RST_OFFSET4
+#define SRC_M4C_NON_SCLR_RST_MASK  BIT(4)
 
 /* GPR1 bitfields */
 #define IOMUXC_GPR1_APP_CLK_REQ_N  BIT(30)
diff --git a/arch/arm/include/asm/arch-mx7/imx-regs.h 
b/arch/arm/include/asm/arch-mx7/imx-regs.h
index f0693f9028..a421b9bc04 100644
--- a/arch/arm/include/asm/arch-mx7/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx7/imx-regs.h
@@ -264,10 +264,12 @@ struct src {
u32 ddrc_rcr;
 };
 
-#define SRC_M4RCR_M4C_NON_SCLR_RST_OFFSET  0
-#define SRC_M4RCR_M4C_NON_SCLR_RST_MASK(1 << 0)
-#define SRC_M4RCR_ENABLE_M4_OFFSET 3
-#define SRC_M4RCR_ENABLE_M4_MASK   (1 << 3)
+#define SRC_M4_REG_OFFSET  0xC
+#define SRC_M4C_NON_SCLR_RST_OFFSET0
+#define SRC_M4C_NON_SCLR_RST_MASK  BIT(0)
+#define SRC_M4_ENABLE_OFFSET   3
+#define SRC_M4_ENABLE_MASK BIT(3)
+
 #define SRC_DDRC_RCR_DDRC_CORE_RST_OFFSET  1
 #define SRC_DDRC_RCR_DDRC_CORE_RST_MASK(1 << 1)
 
diff --git a/arch/arm/mach-imx/imx_bootaux.c b/arch/arm/mach-imx/imx_bootaux.c
index b62dfbf6bf..02728514b7 100644
--- a/arch/arm/mach-imx/imx_bootaux.c
+++ b/arch/arm/mach-imx/imx_bootaux.c
@@ -5,21 +5,41 @@
  */
 
 #include 
+#include 
 #include 
 #include 
 
-/* Allow for arch specific config before we boot */
-int __weak arch_auxiliary_core_up(u32 core_id, u32 boot_private_data)
+int arch_auxiliary_core_up(u32 core_id, ulong boot_private_data)
 {
-   /* please define platform specific arch_auxiliary_core_up() */
-   return CMD_RET_FAILURE;
+   ulong stack, pc;
+
+   if (!boot_private_data)
+   return -EINVAL;
+
+   stack = *(ulong *)boot_private_data;
+   pc = *(ulong *)(boot_private_data + 4);
+
+   /* Set the stack and pc to M4 bootROM */
+   writel(stack, M4_BOOTROM_BASE_ADDR);
+   writel(pc, M4_BOOTROM_BASE_ADDR + 4);
+
+   /* Enable M4 */
+   clrsetbits_le32(SRC_BASE_ADDR + SRC_M4_REG_OFFSET,
+   SRC_M4C_NON_SCLR_RST_MASK, SRC_M4_ENABLE_MASK);
+
+   return 0;
 }
 
-/* Allow for arch specific config before we boot */
-int __weak arch_auxiliary_core_check_up(u32 core_id)
+int arch_auxiliary_core_check_up(u32 core_id)
 {
-   /* please define platform specific arch_auxiliary_core_check_up() */
-   return 0;
+   unsigned int val;
+
+   val = readl(SRC_BASE_ADDR + SRC_M4_REG_OFFSET);
+
+   if (val & SRC_M4C_NON_SCLR_RST_MASK)
+   return 0;  /* assert in reset */
+
+   return 1;
 }
 
 /*
diff --git a/arch/arm/mach-imx/mx6/soc.c b/arch/arm/mach-imx/mx6/soc.c
index b3bee58f10..9b3d8f69b2 100644
--- a/arch/arm/mach-imx/mx6/soc.c
+++ b/arch/arm/mach-imx/mx6/soc.c
@@ -666,41 +666,3 @@ void gpr_init(void)
writel(0x007F007F, >gpr[7]);
}
 }
-
-#ifdef CONFIG_IMX_BOOTAUX
-int arch_auxiliary_core_up(u32 core_id, u32 boot_private_data)
-{
-   struct src *src_reg;
-   u32 stack, pc;
-
-   if (!boot_private_data)
-   return -EINVAL;
-
-   stack = *(u32 *)boot_private_data;
-   pc = *(u32 *)(boot_private_data + 4);
-
-   /* Set the stack and pc to M4 bootROM */
-   writel(stack, M4_BOOTROM_BASE_ADDR);
-   writel(pc, M4_BOOTROM_BASE_ADDR + 4);
-
-   /* Enable M4 */
-   src_reg = (struct src *)SRC_BASE_ADDR;
-   clrsetbits_le32(_reg->scr, SRC_SCR_M4C_NON_SCLR_RST_MASK,
-   SRC_SCR_M4_ENABLE_MASK);
-
-   return 0;
-}
-
-int arch_auxiliary_core_check_up(u32 core_id)
-{
-   struct src *src_reg = (struct src *)SRC_BASE_ADDR;
-   unsigned val;
-
-  

[U-Boot] [PATCH V5 19/31] imx: mx7: move mmc env code to mmc_env.c

[Peng Fan]

The mx7 mmc env code is shared by i.MX8M, so move it to mmc_env.c.

Signed-off-by: Peng Fan 
---
 arch/arm/mach-imx/Makefile  |  1 +
 arch/arm/mach-imx/mmc_env.c | 30 ++
 arch/arm/mach-imx/mx7/soc.c | 21 -
 3 files changed, 31 insertions(+), 21 deletions(-)
 create mode 100644 arch/arm/mach-imx/mmc_env.c

diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index 714b858e73..e38b560d51 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -22,6 +22,7 @@ endif
 ifeq ($(SOC),$(filter $(SOC),mx7))
 obj-y  += cpu.o
 obj-$(CONFIG_SYS_I2C_MXC) += i2c-mxv7.o
+obj-$(CONFIG_ENV_IS_IN_MMC) += mmc_env.o
 endif
 ifeq ($(SOC),$(filter $(SOC),mx6 mx7))
 obj-y  += cache.o init.o
diff --git a/arch/arm/mach-imx/mmc_env.c b/arch/arm/mach-imx/mmc_env.c
new file mode 100644
index 00..ccadd2c1e0
--- /dev/null
+++ b/arch/arm/mach-imx/mmc_env.c
@@ -0,0 +1,30 @@
+/*
+ * Copyright (C) 2017 NXP
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+__weak int board_mmc_get_env_dev(int devno)
+{
+   return CONFIG_SYS_MMC_ENV_DEV;
+}
+
+int mmc_get_env_dev(void)
+{
+   struct bootrom_sw_info **p =
+   (struct bootrom_sw_info **)(ulong)ROM_SW_INFO_ADDR;
+   int devno = (*p)->boot_dev_instance;
+   u8 boot_type = (*p)->boot_dev_type;
+
+   /* If not boot from sd/mmc, use default value */
+   if ((boot_type != BOOT_TYPE_SD) && (boot_type != BOOT_TYPE_MMC))
+   return CONFIG_SYS_MMC_ENV_DEV;
+
+   return board_mmc_get_env_dev(devno);
+}
diff --git a/arch/arm/mach-imx/mx7/soc.c b/arch/arm/mach-imx/mx7/soc.c
index 62bd3a0e5f..172be2ccc0 100644
--- a/arch/arm/mach-imx/mx7/soc.c
+++ b/arch/arm/mach-imx/mx7/soc.c
@@ -250,27 +250,6 @@ const struct boot_mode soc_boot_modes[] = {
{NULL,  0},
 };
 
-#ifdef CONFIG_ENV_IS_IN_MMC
-__weak int board_mmc_get_env_dev(int devno)
-{
-   return CONFIG_SYS_MMC_ENV_DEV;
-}
-
-int mmc_get_env_dev(void)
-{
-   struct bootrom_sw_info **p =
-   (struct bootrom_sw_info **)ROM_SW_INFO_ADDR;
-   int devno = (*p)->boot_dev_instance;
-   u8 boot_type = (*p)->boot_dev_type;
-
-   /* If not boot from sd/mmc, use default value */
-   if ((boot_type != BOOT_TYPE_SD) && (boot_type != BOOT_TYPE_MMC))
-   return CONFIG_SYS_MMC_ENV_DEV;
-
-   return board_mmc_get_env_dev(devno);
-}
-#endif
-
 void s_init(void)
 {
 #if !defined CONFIG_SPL_BUILD
-- 
2.14.1

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH V5 13/31] imx: cpu: add cpu speed/grade for i.MX8M

[Peng Fan]

Use more general enum types for speed grade.
Refine get_cpu_speed_grade_hz to support i.MX8M.

Signed-off-by: Peng Fan 
Cc: Stefano Babic 
Cc: Fabio Estevam 
---
 arch/arm/mach-imx/cpu.c | 27 +++
 1 file changed, 15 insertions(+), 12 deletions(-)

diff --git a/arch/arm/mach-imx/cpu.c b/arch/arm/mach-imx/cpu.c
index 52dbafb50c..fd6d08c533 100644
--- a/arch/arm/mach-imx/cpu.c
+++ b/arch/arm/mach-imx/cpu.c
@@ -333,16 +333,18 @@ void set_chipselect_size(int const cs_size)
 }
 #endif
 
-#if defined(CONFIG_MX7)
+#if defined(CONFIG_MX7) || defined(CONFIG_MX8M)
 /*
  * OCOTP_TESTER3[9:8] (see Fusemap Description Table offset 0x440)
  * defines a 2-bit SPEED_GRADING
  */
 #define OCOTP_TESTER3_SPEED_SHIFT  8
-#define OCOTP_TESTER3_SPEED_800MHZ 0
-#define OCOTP_TESTER3_SPEED_500MHZ 1
-#define OCOTP_TESTER3_SPEED_1GHZ   2
-#define OCOTP_TESTER3_SPEED_1P2GHZ 3
+enum cpu_speed {
+   OCOTP_TESTER3_SPEED_GRADE0,
+   OCOTP_TESTER3_SPEED_GRADE1,
+   OCOTP_TESTER3_SPEED_GRADE2,
+   OCOTP_TESTER3_SPEED_GRADE3,
+};
 
 u32 get_cpu_speed_grade_hz(void)
 {
@@ -357,15 +359,16 @@ u32 get_cpu_speed_grade_hz(void)
val &= 0x3;
 
switch(val) {
-   case OCOTP_TESTER3_SPEED_800MHZ:
+   case OCOTP_TESTER3_SPEED_GRADE0:
return 8;
-   case OCOTP_TESTER3_SPEED_500MHZ:
-   return 5;
-   case OCOTP_TESTER3_SPEED_1GHZ:
-   return 10;
-   case OCOTP_TESTER3_SPEED_1P2GHZ:
-   return 12;
+   case OCOTP_TESTER3_SPEED_GRADE1:
+   return is_mx7() ? 5 : 10;
+   case OCOTP_TESTER3_SPEED_GRADE2:
+   return is_mx7() ? 10 : 13;
+   case OCOTP_TESTER3_SPEED_GRADE3:
+   return is_mx7() ? 12 : 15;
}
+
return 0;
 }
 
-- 
2.14.1

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH V5 11/31] imx: add pad settings bit definition for i.MX8M

[Peng Fan]

Add pad settings bit definition for i.MX8M.

Signed-off-by: Peng Fan 
Reviewed-by: Fabio Estevam 
Cc: Stefano Babic 
---
 arch/arm/include/asm/mach-imx/iomux-v3.h | 22 +-
 1 file changed, 21 insertions(+), 1 deletion(-)

diff --git a/arch/arm/include/asm/mach-imx/iomux-v3.h 
b/arch/arm/include/asm/mach-imx/iomux-v3.h
index ed75e9cd9a..800d4cfb50 100644
--- a/arch/arm/include/asm/mach-imx/iomux-v3.h
+++ b/arch/arm/include/asm/mach-imx/iomux-v3.h
@@ -87,7 +87,27 @@ typedef u64 iomux_v3_cfg_t;
 #define IOMUX_CONFIG_LPSR   0x20
 #define MUX_MODE_LPSR   ((iomux_v3_cfg_t)IOMUX_CONFIG_LPSR << \
MUX_MODE_SHIFT)
-#ifdef CONFIG_MX7
+#ifdef CONFIG_MX8M
+#define PAD_CTL_DSE0   (0x0 << 0)
+#define PAD_CTL_DSE1   (0x1 << 0)
+#define PAD_CTL_DSE2   (0x2 << 0)
+#define PAD_CTL_DSE3   (0x3 << 0)
+#define PAD_CTL_DSE4   (0x4 << 0)
+#define PAD_CTL_DSE5   (0x5 << 0)
+#define PAD_CTL_DSE6   (0x6 << 0)
+#define PAD_CTL_DSE7   (0x7 << 0)
+
+#define PAD_CTL_FSEL0  (0x0 << 3)
+#define PAD_CTL_FSEL1  (0x1 << 3)
+#define PAD_CTL_FSEL2  (0x2 << 3)
+#define PAD_CTL_FSEL3  (0x3 << 3)
+
+#define PAD_CTL_ODE(0x1 << 5)
+#define PAD_CTL_PUE(0x1 << 6)
+#define PAD_CTL_HYS(0x1 << 7)
+#define PAD_CTL_LVTTL  (0x1 << 8)
+
+#elif defined CONFIG_MX7
 
 #define IOMUX_LPSR_SEL_INPUT_OFS 0x7
 
-- 
2.14.1

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH V5 20/31] imx: mx8m: add soc related settings and files

[Peng Fan]

Add SoC level initialization code
 - arch_cpu_init
 - mmu table
 - detect cpu revision
 - reset cpu and wdog settings
 - timer init
 - wdog settings
 - lowlevel init to save/restore registers
 - a few dummy header file to avoid build failure
 - ft_system_setup

Signed-off-by: Peng Fan 
Cc: Stefano Babic 
Cc: Fabio Estevam 
---
 arch/arm/include/asm/arch-mx8m/crm_regs.h  |  10 ++
 arch/arm/include/asm/arch-mx8m/gpio.h  |  12 ++
 arch/arm/include/asm/arch-mx8m/sys_proto.h |  18 +++
 arch/arm/mach-imx/Makefile |   2 +-
 arch/arm/mach-imx/mx8m/Makefile|   3 +-
 arch/arm/mach-imx/mx8m/lowlevel_init.S |  63 
 arch/arm/mach-imx/mx8m/soc.c   | 227 +
 7 files changed, 333 insertions(+), 2 deletions(-)
 create mode 100644 arch/arm/include/asm/arch-mx8m/crm_regs.h
 create mode 100644 arch/arm/include/asm/arch-mx8m/gpio.h
 create mode 100644 arch/arm/include/asm/arch-mx8m/sys_proto.h
 create mode 100644 arch/arm/mach-imx/mx8m/lowlevel_init.S
 create mode 100644 arch/arm/mach-imx/mx8m/soc.c

diff --git a/arch/arm/include/asm/arch-mx8m/crm_regs.h 
b/arch/arm/include/asm/arch-mx8m/crm_regs.h
new file mode 100644
index 00..6582318983
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx8m/crm_regs.h
@@ -0,0 +1,10 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef _ASM_ARCH_MX8M_CRM_REGS_H
+#define _ASM_ARCH_MX8M_CRM_REGS_H
+/* Dummy header, some imx-common code needs this file */
+#endif
diff --git a/arch/arm/include/asm/arch-mx8m/gpio.h 
b/arch/arm/include/asm/arch-mx8m/gpio.h
new file mode 100644
index 00..b666d37700
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx8m/gpio.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_MX8M_GPIO_H
+#define __ASM_ARCH_MX8M_GPIO_H
+
+#include 
+
+#endif
diff --git a/arch/arm/include/asm/arch-mx8m/sys_proto.h 
b/arch/arm/include/asm/arch-mx8m/sys_proto.h
new file mode 100644
index 00..8bf9ac6697
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx8m/sys_proto.h
@@ -0,0 +1,18 @@
+/*
+ * Copyright (C) 2017 NXP
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef __ARCH_MX8M_SYS_PROTO_H
+#define __ARCH_MX8M_SYS_PROTO_H
+
+#include 
+
+void set_wdog_reset(struct wdog_regs *wdog);
+void enable_tzc380(void);
+void restore_boot_params(void);
+extern unsigned long rom_pointer[];
+enum boot_device get_boot_device(void);
+bool is_usb_boot(void);
+#endif
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index e38b560d51..4c4e15c6e7 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -132,4 +132,4 @@ obj-$(CONFIG_MX5) += mx5/
 obj-$(CONFIG_MX6) += mx6/
 obj-$(CONFIG_MX7) += mx7/
 obj-$(CONFIG_ARCH_MX7ULP) += mx7ulp/
-
+obj-$(CONFIG_MX8M) += mx8m/
diff --git a/arch/arm/mach-imx/mx8m/Makefile b/arch/arm/mach-imx/mx8m/Makefile
index 05f38842f0..b1c5d74aab 100644
--- a/arch/arm/mach-imx/mx8m/Makefile
+++ b/arch/arm/mach-imx/mx8m/Makefile
@@ -4,4 +4,5 @@
 # SPDX-License-Identifier: GPL-2.0+
 #
 
-obj-y += clock.o clock_slice.o
+obj-y += lowlevel_init.o
+obj-y += clock.o clock_slice.o soc.o
diff --git a/arch/arm/mach-imx/mx8m/lowlevel_init.S 
b/arch/arm/mach-imx/mx8m/lowlevel_init.S
new file mode 100644
index 00..d388f3ba95
--- /dev/null
+++ b/arch/arm/mach-imx/mx8m/lowlevel_init.S
@@ -0,0 +1,63 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+
+.align 8
+.global rom_pointer
+rom_pointer:
+   .space 256
+
+/*
+ * Routine: save_boot_params (called after reset from start.S)
+ */
+
+.global save_boot_params
+save_boot_params:
+   /* The firmware provided ATAG/FDT address can be found in r2/x0 */
+   adr x0, rom_pointer
+   stp x1, x2, [x0], #16
+   stp x3, x4, [x0], #16
+   stp x5, x6, [x0], #16
+   stp x7, x8, [x0], #16
+   stp x9, x10, [x0], #16
+   stp x11, x12, [x0], #16
+   stp x13, x14, [x0], #16
+   stp x15, x16, [x0], #16
+   stp x17, x18, [x0], #16
+   stp x19, x20, [x0], #16
+   stp x21, x22, [x0], #16
+   stp x23, x24, [x0], #16
+   stp x25, x26, [x0], #16
+   stp x27, x28, [x0], #16
+   stp x29, x30, [x0], #16
+   mov x30, sp
+   str x30, [x0], #8
+
+   /* Returns */
+   b   save_boot_params_ret
+
+.global restore_boot_params
+restore_boot_params:
+   adr x0, rom_pointer
+   ldp x1, x2, [x0], #16
+   ldp x3, x4, [x0], #16
+   ldp x5, x6, [x0], #16
+   ldp x7, x8, [x0], #16
+   ldp x9, x10, [x0], #16
+   ldp x11, x12, [x0], #16
+   ldp x13, x14, [x0], #16
+   ldp x15, x16, [x0], #16
+   ldp x17, x18, [x0], #16
+   ldp x19, x20, [x0], #16
+   ldp x21, x22, [x0], #16
+   ldp 

[U-Boot] [PATCH V5 21/31] imx: makefile: compile files for i.MX8M

[Peng Fan]

Compile files for i.MX8M

Signed-off-by: Peng Fan 
Reviewed-by: Fabio Estevam 
Cc: Stefano Babic 
---
 arch/arm/mach-imx/Makefile | 13 +++--
 1 file changed, 11 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index 4c4e15c6e7..95a542fa01 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -7,15 +7,24 @@
 # SPDX-License-Identifier: GPL-2.0+
 #
 
-ifeq ($(SOC),$(filter $(SOC),mx25 mx35 mx5 mx6 mx7 vf610))
+ifeq ($(SOC),$(filter $(SOC),mx25 mx35 mx5 mx6 mx7 mx8m vf610))
 obj-y  = iomux-v3.o
 endif
+
+ifeq ($(SOC),$(filter $(SOC),mx8m))
+obj-$(CONFIG_IMX_BOOTAUX) += imx_bootaux.o
+obj-$(CONFIG_ENV_IS_IN_MMC) += mmc_env.o
+obj-$(CONFIG_FEC_MXC) += mac.o
+obj-$(CONFIG_SYS_I2C_MXC) += i2c-mxv7.o
+obj-y += cpu.o
+endif
+
 ifeq ($(SOC),$(filter $(SOC),mx5 mx6))
 obj-y  += cpu.o speed.o
 obj-$(CONFIG_GPT_TIMER) += timer.o
 obj-$(CONFIG_SYS_I2C_MXC) += i2c-mxv7.o
 endif
-ifeq ($(SOC),$(filter $(SOC),mx7 mx6 mxs))
+ifeq ($(SOC),$(filter $(SOC),mx7 mx6 mxs mx8m))
 obj-y  += misc.o
 obj-$(CONFIG_SPL_BUILD)+= spl.o
 endif
-- 
2.14.1

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH V5 07/31] imx: boot_mode: add USB_BOOT entry

[Peng Fan]

Add USB_BOOT entry.

Signed-off-by: Peng Fan 
Reviewed-by: Stefano Babic 
Reviewed-by: Fabio Estevam 
---
 arch/arm/include/asm/mach-imx/boot_mode.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/include/asm/mach-imx/boot_mode.h 
b/arch/arm/include/asm/mach-imx/boot_mode.h
index a8239f2f7a..e3ed046b25 100644
--- a/arch/arm/include/asm/mach-imx/boot_mode.h
+++ b/arch/arm/include/asm/mach-imx/boot_mode.h
@@ -26,6 +26,7 @@ enum boot_device {
MMC4_BOOT,
NAND_BOOT,
QSPI_BOOT,
+   USB_BOOT,
UNKNOWN_BOOT,
BOOT_DEV_NUM = UNKNOWN_BOOT,
 };
-- 
2.14.1

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH V5 10/31] imx: add i.MX8MQ SoC Revision and is_mx8m helper

[Peng Fan]

Add i.MX8MQ SoC Revision
Add is_mx8m helper
The 7ULP is a dummy number, so use 0xEx.

Signed-off-by: Peng Fan 
Reviewed-by: Fabio Estevam 
Cc: Stefano Babic 
---
 arch/arm/include/asm/arch-imx/cpu.h   | 6 --
 arch/arm/include/asm/mach-imx/sys_proto.h | 1 +
 2 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/arch/arm/include/asm/arch-imx/cpu.h 
b/arch/arm/include/asm/arch-imx/cpu.h
index ec5b419e47..470961c6f7 100644
--- a/arch/arm/include/asm/arch-imx/cpu.h
+++ b/arch/arm/include/asm/arch-imx/cpu.h
@@ -25,12 +25,14 @@
 #define MXC_CPU_MX6QP  0x69
 #define MXC_CPU_MX7S   0x71 /* dummy ID */
 #define MXC_CPU_MX7D   0x72
-#define MXC_CPU_MX7ULP 0x81 /* Temporally hard code */
+#define MXC_CPU_MX8MQ  0x82
+#define MXC_CPU_MX7ULP 0xE1 /* Temporally hard code */
 #define MXC_CPU_VF610  0xF6 /* dummy ID */
 
 #define MXC_SOC_MX60x60
 #define MXC_SOC_MX70x70
-#define MXC_SOC_MX7ULP 0x80 /* dummy */
+#define MXC_SOC_MX8M   0x80
+#define MXC_SOC_MX7ULP 0xE0 /* dummy */
 
 #define CHIP_REV_1_00x10
 #define CHIP_REV_1_10x11
diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h 
b/arch/arm/include/asm/mach-imx/sys_proto.h
index c53e5400a1..96795e1814 100644
--- a/arch/arm/include/asm/mach-imx/sys_proto.h
+++ b/arch/arm/include/asm/mach-imx/sys_proto.h
@@ -27,6 +27,7 @@
 
 #define is_mx6() (is_soc_type(MXC_SOC_MX6))
 #define is_mx7() (is_soc_type(MXC_SOC_MX7))
+#define is_mx8m() (is_soc_type(MXC_SOC_MX8M))
 
 #define is_mx6dqp() (is_cpu_type(MXC_CPU_MX6QP) || is_cpu_type(MXC_CPU_MX6DP))
 #define is_mx6dq() (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D))
-- 
2.14.1

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH V5 14/31] imx: refactor imx_get_mac_from_fuse

[Peng Fan]

Move imx_get_mac_from_fuse to a new mac.c for i.MX6/7.
Since fuse regs structure are different for i.MX6/7, use mac
address offset in code and define a new local struture
imx_mac_fuse.

Also sort the config order.

Signed-off-by: Peng Fan 
Cc: Stefano Babic 
Cc: Fabio Estevam 
---
 arch/arm/mach-imx/Makefile  |  3 ++-
 arch/arm/mach-imx/mac.c | 61 +
 arch/arm/mach-imx/mx6/soc.c | 34 -
 arch/arm/mach-imx/mx7/soc.c | 32 
 4 files changed, 63 insertions(+), 67 deletions(-)
 create mode 100644 arch/arm/mach-imx/mac.c

diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index 63db0e15c4..714b858e73 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -25,12 +25,13 @@ obj-$(CONFIG_SYS_I2C_MXC) += i2c-mxv7.o
 endif
 ifeq ($(SOC),$(filter $(SOC),mx6 mx7))
 obj-y  += cache.o init.o
-obj-$(CONFIG_SATA) += sata.o
+obj-$(CONFIG_FEC_MXC) += mac.o
 obj-$(CONFIG_IMX_VIDEO_SKIP) += video.o
 obj-$(CONFIG_IMX_RDC) += rdc-sema.o
 ifneq ($(CONFIG_SPL_BUILD),y)
 obj-$(CONFIG_IMX_BOOTAUX) += imx_bootaux.o
 endif
+obj-$(CONFIG_SATA) += sata.o
 obj-$(CONFIG_SECURE_BOOT)+= hab.o
 obj-$(CONFIG_SYSCOUNTER_TIMER) += syscounter.o
 endif
diff --git a/arch/arm/mach-imx/mac.c b/arch/arm/mach-imx/mac.c
new file mode 100644
index 00..dd7fd92d31
--- /dev/null
+++ b/arch/arm/mach-imx/mac.c
@@ -0,0 +1,61 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * Peng Fan 
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+struct imx_mac_fuse {
+   u32 mac_addr0;
+   u32 rsvd0[3];
+   u32 mac_addr1;
+   u32 rsvd1[3];
+   u32 mac_addr2;
+   u32 rsvd2[7];
+};
+
+#define MAC_FUSE_MX6_OFFSET0x620
+#define MAC_FUSE_MX7_OFFSET0x640
+
+void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
+{
+   struct imx_mac_fuse *fuse;
+   u32 offset;
+   bool has_second_mac;
+
+   offset = is_mx6() ? MAC_FUSE_MX6_OFFSET : MAC_FUSE_MX7_OFFSET;
+   fuse = (struct imx_mac_fuse *)(ulong)(OCOTP_BASE_ADDR + offset);
+   has_second_mac = is_mx7() || is_mx6sx() || is_mx6ul() || is_mx6ull();
+
+   if (has_second_mac && dev_id == 1) {
+   u32 value = readl(>mac_addr2);
+
+   mac[0] = value >> 24;
+   mac[1] = value >> 16;
+   mac[2] = value >> 8;
+   mac[3] = value;
+
+   value = readl(>mac_addr1);
+   mac[4] = value >> 24;
+   mac[5] = value >> 16;
+
+   } else {
+   u32 value = readl(>mac_addr1);
+
+   mac[0] = value >> 8;
+   mac[1] = value;
+
+   value = readl(>mac_addr0);
+   mac[2] = value >> 24;
+   mac[3] = value >> 16;
+   mac[4] = value >> 8;
+   mac[5] = value;
+   }
+}
diff --git a/arch/arm/mach-imx/mx6/soc.c b/arch/arm/mach-imx/mx6/soc.c
index 43cb58106b..b3bee58f10 100644
--- a/arch/arm/mach-imx/mx6/soc.c
+++ b/arch/arm/mach-imx/mx6/soc.c
@@ -518,40 +518,6 @@ int board_postclk_init(void)
return 0;
 }
 
-#if defined(CONFIG_FEC_MXC)
-void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
-{
-   struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
-   struct fuse_bank *bank = >bank[4];
-   struct fuse_bank4_regs *fuse =
-   (struct fuse_bank4_regs *)bank->fuse_regs;
-
-   if ((is_mx6sx() || is_mx6ul() || is_mx6ull()) && dev_id == 1) {
-   u32 value = readl(>mac_addr2);
-   mac[0] = value >> 24 ;
-   mac[1] = value >> 16 ;
-   mac[2] = value >> 8 ;
-   mac[3] = value ;
-
-   value = readl(>mac_addr1);
-   mac[4] = value >> 24 ;
-   mac[5] = value >> 16 ;
-   
-   } else {
-   u32 value = readl(>mac_addr1);
-   mac[0] = (value >> 8);
-   mac[1] = value ;
-
-   value = readl(>mac_addr0);
-   mac[2] = value >> 24 ;
-   mac[3] = value >> 16 ;
-   mac[4] = value >> 8 ;
-   mac[5] = value ;
-   }
-
-}
-#endif
-
 #ifndef CONFIG_SPL_BUILD
 /*
  * cfg_val will be used for
diff --git a/arch/arm/mach-imx/mx7/soc.c b/arch/arm/mach-imx/mx7/soc.c
index 032dfcf2ce..10dec8bdf4 100644
--- a/arch/arm/mach-imx/mx7/soc.c
+++ b/arch/arm/mach-imx/mx7/soc.c
@@ -208,38 +208,6 @@ void get_board_serial(struct tag_serialnr *serialnr)
 }
 #endif
 
-#if defined(CONFIG_FEC_MXC)
-void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
-{
-   struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
-   struct fuse_bank *bank = >bank[9];
-   struct fuse_bank9_regs *fuse =
-   (struct fuse_bank9_regs *)bank->fuse_regs;
-
-   if (0 == dev_id) {
-   u32 value = 

[U-Boot] [PATCH V5 09/31] imx: spl: implement spl_boot_device for i.MX8M

[Peng Fan]

Implement spl_boot_device for i.MX8M.

Signed-off-by: Peng Fan 
Reviewed-by: Fabio Estevam 
Cc: Stefano Babic 
---
 arch/arm/mach-imx/spl.c | 10 +++---
 1 file changed, 7 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-imx/spl.c b/arch/arm/mach-imx/spl.c
index 723f51fad3..7c4ee82cd1 100644
--- a/arch/arm/mach-imx/spl.c
+++ b/arch/arm/mach-imx/spl.c
@@ -97,8 +97,8 @@ u32 spl_boot_device(void)
return BOOT_DEVICE_NONE;
 }
 
-#elif defined(CONFIG_MX7)
-/* Translate iMX7 boot device to the SPL boot device enumeration */
+#elif defined(CONFIG_MX7) || defined(CONFIG_MX8M)
+/* Translate iMX7/MX8M boot device to the SPL boot device enumeration */
 u32 spl_boot_device(void)
 {
enum boot_device boot_device_spl = get_boot_device();
@@ -112,11 +112,15 @@ u32 spl_boot_device(void)
return BOOT_DEVICE_MMC2;
case SPI_NOR_BOOT:
return BOOT_DEVICE_SPI;
+   case NAND_BOOT:
+   return BOOT_DEVICE_NAND;
+   case USB_BOOT:
+   return BOOT_DEVICE_USB;
default:
return BOOT_DEVICE_NONE;
}
 }
-#endif /* CONFIG_MX6 || CONFIG_MX7 */
+#endif /* CONFIG_MX6 || CONFIG_MX7 || CONFIG_MX8M */
 
 #ifdef CONFIG_SPL_USB_GADGET_SUPPORT
 int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name)
-- 
2.14.1

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH V5 12/31] imx: cpu: move speed/temp to common cpu

[Peng Fan]

The i.MX7 cpu speed/temp code could be reused on i.MX8M,
so move them to common cpu code.

Signed-off-by: Peng Fan 
Cc: Stefano Babic 
Cc: Fabio Estevam 
---
 arch/arm/mach-imx/cpu.c | 73 +
 arch/arm/mach-imx/mx7/soc.c | 71 ---
 2 files changed, 73 insertions(+), 71 deletions(-)

diff --git a/arch/arm/mach-imx/cpu.c b/arch/arm/mach-imx/cpu.c
index fae8b0a419..52dbafb50c 100644
--- a/arch/arm/mach-imx/cpu.c
+++ b/arch/arm/mach-imx/cpu.c
@@ -333,6 +333,79 @@ void set_chipselect_size(int const cs_size)
 }
 #endif
 
+#if defined(CONFIG_MX7)
+/*
+ * OCOTP_TESTER3[9:8] (see Fusemap Description Table offset 0x440)
+ * defines a 2-bit SPEED_GRADING
+ */
+#define OCOTP_TESTER3_SPEED_SHIFT  8
+#define OCOTP_TESTER3_SPEED_800MHZ 0
+#define OCOTP_TESTER3_SPEED_500MHZ 1
+#define OCOTP_TESTER3_SPEED_1GHZ   2
+#define OCOTP_TESTER3_SPEED_1P2GHZ 3
+
+u32 get_cpu_speed_grade_hz(void)
+{
+   struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
+   struct fuse_bank *bank = >bank[1];
+   struct fuse_bank1_regs *fuse =
+   (struct fuse_bank1_regs *)bank->fuse_regs;
+   uint32_t val;
+
+   val = readl(>tester3);
+   val >>= OCOTP_TESTER3_SPEED_SHIFT;
+   val &= 0x3;
+
+   switch(val) {
+   case OCOTP_TESTER3_SPEED_800MHZ:
+   return 8;
+   case OCOTP_TESTER3_SPEED_500MHZ:
+   return 5;
+   case OCOTP_TESTER3_SPEED_1GHZ:
+   return 10;
+   case OCOTP_TESTER3_SPEED_1P2GHZ:
+   return 12;
+   }
+   return 0;
+}
+
+/*
+ * OCOTP_TESTER3[7:6] (see Fusemap Description Table offset 0x440)
+ * defines a 2-bit SPEED_GRADING
+ */
+#define OCOTP_TESTER3_TEMP_SHIFT   6
+
+u32 get_cpu_temp_grade(int *minc, int *maxc)
+{
+   struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
+   struct fuse_bank *bank = >bank[1];
+   struct fuse_bank1_regs *fuse =
+   (struct fuse_bank1_regs *)bank->fuse_regs;
+   uint32_t val;
+
+   val = readl(>tester3);
+   val >>= OCOTP_TESTER3_TEMP_SHIFT;
+   val &= 0x3;
+
+   if (minc && maxc) {
+   if (val == TEMP_AUTOMOTIVE) {
+   *minc = -40;
+   *maxc = 125;
+   } else if (val == TEMP_INDUSTRIAL) {
+   *minc = -40;
+   *maxc = 105;
+   } else if (val == TEMP_EXTCOMMERCIAL) {
+   *minc = -20;
+   *maxc = 105;
+   } else {
+   *minc = 0;
+   *maxc = 95;
+   }
+   }
+   return val;
+}
+#endif
+
 #ifdef CONFIG_NXP_BOARD_REVISION
 int nxp_board_rev(void)
 {
diff --git a/arch/arm/mach-imx/mx7/soc.c b/arch/arm/mach-imx/mx7/soc.c
index d160e80146..032dfcf2ce 100644
--- a/arch/arm/mach-imx/mx7/soc.c
+++ b/arch/arm/mach-imx/mx7/soc.c
@@ -97,77 +97,6 @@ struct imx_sec_config_fuse_t const imx_sec_config_fuse = {
 };
 #endif
 
-/*
- * OCOTP_TESTER3[9:8] (see Fusemap Description Table offset 0x440)
- * defines a 2-bit SPEED_GRADING
- */
-#define OCOTP_TESTER3_SPEED_SHIFT  8
-#define OCOTP_TESTER3_SPEED_800MHZ 0
-#define OCOTP_TESTER3_SPEED_500MHZ 1
-#define OCOTP_TESTER3_SPEED_1GHZ   2
-#define OCOTP_TESTER3_SPEED_1P2GHZ 3
-
-u32 get_cpu_speed_grade_hz(void)
-{
-   struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
-   struct fuse_bank *bank = >bank[1];
-   struct fuse_bank1_regs *fuse =
-   (struct fuse_bank1_regs *)bank->fuse_regs;
-   uint32_t val;
-
-   val = readl(>tester3);
-   val >>= OCOTP_TESTER3_SPEED_SHIFT;
-   val &= 0x3;
-
-   switch(val) {
-   case OCOTP_TESTER3_SPEED_800MHZ:
-   return 8;
-   case OCOTP_TESTER3_SPEED_500MHZ:
-   return 5;
-   case OCOTP_TESTER3_SPEED_1GHZ:
-   return 10;
-   case OCOTP_TESTER3_SPEED_1P2GHZ:
-   return 12;
-   }
-   return 0;
-}
-
-/*
- * OCOTP_TESTER3[7:6] (see Fusemap Description Table offset 0x440)
- * defines a 2-bit SPEED_GRADING
- */
-#define OCOTP_TESTER3_TEMP_SHIFT   6
-
-u32 get_cpu_temp_grade(int *minc, int *maxc)
-{
-   struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
-   struct fuse_bank *bank = >bank[1];
-   struct fuse_bank1_regs *fuse =
-   (struct fuse_bank1_regs *)bank->fuse_regs;
-   uint32_t val;
-
-   val = readl(>tester3);
-   val >>= OCOTP_TESTER3_TEMP_SHIFT;
-   val &= 0x3;
-
-   if (minc && maxc) {
-   if (val == TEMP_AUTOMOTIVE) {
-   *minc = -40;
-   *maxc = 125;
-   } else if (val == TEMP_INDUSTRIAL) {
-   *minc = -40;
- 

[U-Boot] [PATCH V5 08/31] imx: cpu: update cpu file to support i.MX8M

[Peng Fan]

Update get_reset_cause to reflect i.MX8M
Compile out get_ahb_clk and set_chipselect_size for i.MX8M

Signed-off-by: Peng Fan 
Reviewed-by: Stefano Babic 
Reviewed-by: Fabio Estevam 
---
 arch/arm/mach-imx/cpu.c | 11 ++-
 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-imx/cpu.c b/arch/arm/mach-imx/cpu.c
index a32ab87e9b..fae8b0a419 100644
--- a/arch/arm/mach-imx/cpu.c
+++ b/arch/arm/mach-imx/cpu.c
@@ -62,6 +62,11 @@ static char *get_reset_cause(void)
return "WDOG4";
case 0x00200:
return "TEMPSENSE";
+#elif defined(CONFIG_MX8M)
+   case 0x00100:
+   return "WDOG2";
+   case 0x00200:
+   return "TEMPSENSE";
 #else
case 0x00100:
return "TEMPSENSE";
@@ -137,6 +142,8 @@ unsigned imx_ddr_size(void)
 const char *get_imx_type(u32 imxtype)
 {
switch (imxtype) {
+   case MXC_CPU_MX8MQ:
+   return "8MQ";   /* Quad-core version of the mx8m */
case MXC_CPU_MX7S:
return "7S";/* Single-core version of the mx7 */
case MXC_CPU_MX7D:
@@ -259,7 +266,7 @@ int cpu_mmc_init(bd_t *bis)
 }
 #endif
 
-#ifndef CONFIG_MX7
+#if !(defined(CONFIG_MX7) || defined(CONFIG_MX8M))
 u32 get_ahb_clk(void)
 {
struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
@@ -293,6 +300,7 @@ void arch_preboot_os(void)
 #endif
 }
 
+#ifndef CONFIG_MX8M
 void set_chipselect_size(int const cs_size)
 {
unsigned int reg;
@@ -323,6 +331,7 @@ void set_chipselect_size(int const cs_size)
 
writel(reg, _regs->gpr[1]);
 }
+#endif
 
 #ifdef CONFIG_NXP_BOARD_REVISION
 int nxp_board_rev(void)
-- 
2.14.1

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH V5 04/31] imx: mx8m: add pin header file

[Peng Fan]

Add pin header file for i.MX8M

Signed-off-by: Peng Fan 
Reviewed-by: Fabio Estevam 
Cc: Stefano Babic 
---
 arch/arm/include/asm/arch-mx8m/mx8mq_pins.h | 623 
 1 file changed, 623 insertions(+)
 create mode 100644 arch/arm/include/asm/arch-mx8m/mx8mq_pins.h

diff --git a/arch/arm/include/asm/arch-mx8m/mx8mq_pins.h 
b/arch/arm/include/asm/arch-mx8m/mx8mq_pins.h
new file mode 100644
index 00..062bea7299
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx8m/mx8mq_pins.h
@@ -0,0 +1,623 @@
+/*
+ * Copyright (C) 2017 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_MX8MQ_PINS_H__
+#define __ASM_ARCH_MX8MQ_PINS_H__
+
+#include 
+
+enum {
+   IMX8MQ_PAD_GPIO1_IO00__GPIO1_IO0= 
IOMUX_PAD(0x0290, 0x0028, 0, 0x, 0, 0),
+   IMX8MQ_PAD_GPIO1_IO00__CCM_ENET_PHY_REF_CLK_ROOT= 
IOMUX_PAD(0x0290, 0x0028, 1, 0x, 0, 0),
+   IMX8MQ_PAD_GPIO1_IO00__XTALOSC_REF_CLK_32K  = 
IOMUX_PAD(0x0290, 0x0028, 5, 0x, 0, 0),
+   IMX8MQ_PAD_GPIO1_IO00__CCM_EXT_CLK1 = 
IOMUX_PAD(0x0290, 0x0028, 6, 0x, 0, 0),
+   IMX8MQ_PAD_GPIO1_IO00__JTAG_FAIL= 
IOMUX_PAD(0x0290, 0x0028, 7, 0x, 0, 0),
+
+   IMX8MQ_PAD_GPIO1_IO01__GPIO1_IO1= 
IOMUX_PAD(0x0294, 0x002C, 0, 0x, 0, 0),
+   IMX8MQ_PAD_GPIO1_IO01__PWM1_OUT = 
IOMUX_PAD(0x0294, 0x002C, 1, 0x, 0, 0),
+   IMX8MQ_PAD_GPIO1_IO01__XTALOSC_REF_CLK_24M  = 
IOMUX_PAD(0x0294, 0x002C, 5, 0x, 0, 0),
+   IMX8MQ_PAD_GPIO1_IO01__CCM_EXT_CLK2 = 
IOMUX_PAD(0x0294, 0x002C, 6, 0x, 0, 0),
+   IMX8MQ_PAD_GPIO1_IO01__JTAG_ACTIVE  = 
IOMUX_PAD(0x0294, 0x002C, 7, 0x, 0, 0),
+
+   IMX8MQ_PAD_GPIO1_IO02__GPIO1_IO2= 
IOMUX_PAD(0x0298, 0x0030, 0, 0x, 0, 0),
+   IMX8MQ_PAD_GPIO1_IO02__WDOG1_WDOG_B = 
IOMUX_PAD(0x0298, 0x0030, 1, 0x, 0, 0),
+   IMX8MQ_PAD_GPIO1_IO02__WDOG1_WDOG_ANY   = 
IOMUX_PAD(0x0298, 0x0030, 5, 0x, 0, 0),
+   IMX8MQ_PAD_GPIO1_IO02__JTAG_DE_B= 
IOMUX_PAD(0x0298, 0x0030, 7, 0x, 0, 0),
+
+   IMX8MQ_PAD_GPIO1_IO03__GPIO1_IO3= 
IOMUX_PAD(0x029C, 0x0034, 0, 0x, 0, 0),
+   IMX8MQ_PAD_GPIO1_IO03__USDHC1_VSELECT   = 
IOMUX_PAD(0x029C, 0x0034, 1, 0x, 0, 0),
+   IMX8MQ_PAD_GPIO1_IO03__SDMA1_EXT_EVENT0 = 
IOMUX_PAD(0x029C, 0x0034, 5, 0x, 0, 0),
+   IMX8MQ_PAD_GPIO1_IO03__XTALOSC_XTAL_OK  = 
IOMUX_PAD(0x029C, 0x0034, 6, 0x, 0, 0),
+   IMX8MQ_PAD_GPIO1_IO03__JTAG_DONE= 
IOMUX_PAD(0x029C, 0x0034, 7, 0x, 0, 0),
+
+   IMX8MQ_PAD_GPIO1_IO04__GPIO1_IO4= 
IOMUX_PAD(0x02A0, 0x0038, 0, 0x, 0, 0),
+   IMX8MQ_PAD_GPIO1_IO04__USDHC2_VSELECT   = 
IOMUX_PAD(0x02A0, 0x0038, 1, 0x, 0, 0),
+   IMX8MQ_PAD_GPIO1_IO04__SDMA1_EXT_EVENT1 = 
IOMUX_PAD(0x02A0, 0x0038, 5, 0x, 0, 0),
+   IMX8MQ_PAD_GPIO1_IO04__XTALOSC_XTAL_OK_1V   = 
IOMUX_PAD(0x02A0, 0x0038, 6, 0x, 0, 0),
+
+   IMX8MQ_PAD_GPIO1_IO05__GPIO1_IO5= 
IOMUX_PAD(0x02A4, 0x003C, 0, 0x, 0, 0),
+   IMX8MQ_PAD_GPIO1_IO05__ARM_PLATFORM_CM4_NMI = 
IOMUX_PAD(0x02A4, 0x003C, 1, 0x, 0, 0),
+   IMX8MQ_PAD_GPIO1_IO05__CCM_PMIC_READY   = 
IOMUX_PAD(0x02A4, 0x003C, 5, 0x04BC, 0, 0),
+   IMX8MQ_PAD_GPIO1_IO05__SRC_INT_BOOT = 
IOMUX_PAD(0x02A4, 0x003C, 6, 0x, 0, 0),
+
+   IMX8MQ_PAD_GPIO1_IO06__GPIO1_IO6= 
IOMUX_PAD(0x02A8, 0x0040, 0, 0x, 0, 0),
+   IMX8MQ_PAD_GPIO1_IO06__ENET_MDC = 
IOMUX_PAD(0x02A8, 0x0040, 1, 0x, 0, 0),
+   IMX8MQ_PAD_GPIO1_IO06__USDHC1_CD_B  = 
IOMUX_PAD(0x02A8, 0x0040, 5, 0x, 0, 0),
+   IMX8MQ_PAD_GPIO1_IO06__CCM_EXT_CLK3 = 
IOMUX_PAD(0x02A8, 0x0040, 6, 0x, 0, 0),
+
+   IMX8MQ_PAD_GPIO1_IO07__GPIO1_IO7= 
IOMUX_PAD(0x02AC, 0x0044, 0, 0x, 0, 0),
+   IMX8MQ_PAD_GPIO1_IO07__ENET_MDIO= 
IOMUX_PAD(0x02AC, 0x0044, 1, 0x04C0, 0, 0),
+   IMX8MQ_PAD_GPIO1_IO07__USDHC1_WP= 
IOMUX_PAD(0x02AC, 0x0044, 5, 0x, 0, 0),
+   IMX8MQ_PAD_GPIO1_IO07__CCM_EXT_CLK4 = 
IOMUX_PAD(0x02AC, 0x0044, 6, 0x, 0, 0),
+
+   IMX8MQ_PAD_GPIO1_IO08__GPIO1_IO8= 
IOMUX_PAD(0x02B0, 0x0048, 0, 0x, 0, 0),
+   IMX8MQ_PAD_GPIO1_IO08__ENET_1588_EVENT0_IN  = 

[U-Boot] [PATCH V5 05/31] imx: mx8m: add clock driver

[Peng Fan]

Add clock driver to support i.MX8M.

There are two kind PLLs, FRAC pll and SSCG pll. ROM already
configured SYS PLL1/2, we only need to configure the output.
ocotp/i2c/pll decoding and configuration/usdhc/lcdif/dram pll/
enet clock are configured in the code.

Signed-off-by: Peng Fan 
Cc: Fabio Estevam 
Cc: Stefano Babic 
---
 arch/arm/include/asm/arch-mx8m/clock.h | 657 +++
 arch/arm/mach-imx/mx8m/Makefile|   7 +
 arch/arm/mach-imx/mx8m/clock.c | 795 +
 arch/arm/mach-imx/mx8m/clock_slice.c   | 742 ++
 4 files changed, 2201 insertions(+)
 create mode 100644 arch/arm/include/asm/arch-mx8m/clock.h
 create mode 100644 arch/arm/mach-imx/mx8m/Makefile
 create mode 100644 arch/arm/mach-imx/mx8m/clock.c
 create mode 100644 arch/arm/mach-imx/mx8m/clock_slice.c

diff --git a/arch/arm/include/asm/arch-mx8m/clock.h 
b/arch/arm/include/asm/arch-mx8m/clock.h
new file mode 100644
index 00..12b453
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx8m/clock.h
@@ -0,0 +1,657 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * Peng Fan 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef _ASM_ARCH_IMX8M_CLOCK_H
+#define _ASM_ARCH_IMX8M_CLOCK_H
+
+#include 
+
+enum pll_clocks {
+   ANATOP_ARM_PLL,
+   ANATOP_GPU_PLL,
+   ANATOP_SYSTEM_PLL1,
+   ANATOP_SYSTEM_PLL2,
+   ANATOP_SYSTEM_PLL3,
+   ANATOP_AUDIO_PLL1,
+   ANATOP_AUDIO_PLL2,
+   ANATOP_VIDEO_PLL1,
+   ANATOP_VIDEO_PLL2,
+   ANATOP_DRAM_PLL,
+};
+
+enum clk_slice_type {
+   CORE_CLOCK_SLICE,
+   BUS_CLOCK_SLICE,
+   IP_CLOCK_SLICE,
+   AHB_CLOCK_SLICE,
+   IPG_CLOCK_SLICE,
+   CORE_SEL_CLOCK_SLICE,
+   DRAM_SEL_CLOCK_SLICE,
+};
+
+enum clk_root_index {
+   MXC_ARM_CLK = 0,
+   ARM_A53_CLK_ROOT= 0,
+   ARM_M4_CLK_ROOT = 1,
+   VPU_A53_CLK_ROOT= 2,
+   GPU_CORE_CLK_ROOT   = 3,
+   GPU_SHADER_CLK_ROOT = 4,
+   MAIN_AXI_CLK_ROOT   = 16,
+   ENET_AXI_CLK_ROOT   = 17,
+   NAND_USDHC_BUS_CLK_ROOT = 18,
+   VPU_BUS_CLK_ROOT= 19,
+   DISPLAY_AXI_CLK_ROOT= 20,
+   DISPLAY_APB_CLK_ROOT= 21,
+   DISPLAY_RTRM_CLK_ROOT   = 22,
+   USB_BUS_CLK_ROOT= 23,
+   GPU_AXI_CLK_ROOT= 24,
+   GPU_AHB_CLK_ROOT= 25,
+   NOC_CLK_ROOT= 26,
+   NOC_APB_CLK_ROOT= 27,
+   AHB_CLK_ROOT= 32,
+   IPG_CLK_ROOT= 33,
+   MXC_IPG_CLK = 33,
+   AUDIO_AHB_CLK_ROOT  = 34,
+   MIPI_DSI_ESC_RX_CLK_ROOT= 36,
+   DRAM_SEL_CFG= 48,
+   CORE_SEL_CFG= 49,
+   DRAM_ALT_CLK_ROOT   = 64,
+   DRAM_APB_CLK_ROOT   = 65,
+   VPU_G1_CLK_ROOT = 66,
+   VPU_G2_CLK_ROOT = 67,
+   DISPLAY_DTRC_CLK_ROOT   = 68,
+   DISPLAY_DC8000_CLK_ROOT = 69,
+   PCIE1_CTRL_CLK_ROOT = 70,
+   PCIE1_PHY_CLK_ROOT  = 71,
+   PCIE1_AUX_CLK_ROOT  = 72,
+   DC_PIXEL_CLK_ROOT   = 73,
+   LCDIF_PIXEL_CLK_ROOT= 74,
+   SAI1_CLK_ROOT   = 75,
+   SAI2_CLK_ROOT   = 76,
+   SAI3_CLK_ROOT   = 77,
+   SAI4_CLK_ROOT   = 78,
+   SAI5_CLK_ROOT   = 79,
+   SAI6_CLK_ROOT   = 80,
+   SPDIF1_CLK_ROOT = 81,
+   SPDIF2_CLK_ROOT = 82,
+   ENET_REF_CLK_ROOT   = 83,
+   ENET_TIMER_CLK_ROOT = 84,
+   ENET_PHY_REF_CLK_ROOT   = 85,
+   NAND_CLK_ROOT   = 86,
+   QSPI_CLK_ROOT   = 87,
+   MXC_ESDHC_CLK   = 88,
+   USDHC1_CLK_ROOT = 88,
+   MXC_ESDHC2_CLK  = 89,
+   USDHC2_CLK_ROOT = 89,
+   I2C1_CLK_ROOT   = 90,
+   MXC_I2C_CLK = 90,
+   I2C2_CLK_ROOT   = 91,
+   I2C3_CLK_ROOT   = 92,
+   I2C4_CLK_ROOT   = 93,
+   UART1_CLK_ROOT  = 94,
+   UART2_CLK_ROOT  = 95,
+   UART3_CLK_ROOT  = 96,
+   UART4_CLK_ROOT  = 97,
+   USB_CORE_REF_CLK_ROOT   = 98,
+   USB_PHY_REF_CLK_ROOT= 99,
+   GIC_CLK_ROOT= 100,
+   ECSPI1_CLK_ROOT = 101,
+   ECSPI2_CLK_ROOT = 102,
+   PWM1_CLK_ROOT   = 103,
+   

[U-Boot] [PATCH V5 06/31] imx: add sip function

[Peng Fan]

Add SiP (Silicon Provider) services function to issue
SMC call to Arm Trusted Firmware.

More SiP information could be found in
  https://github.com/ARM-software/arm-trusted-firmware/blob/master/
  docs/arm-sip-service.rst

Signed-off-by: Peng Fan 
Reviewed-by: Fabio Estevam 
Cc: Stefano Babic 
---
 arch/arm/include/asm/mach-imx/sys_proto.h |  3 +++
 arch/arm/mach-imx/Makefile|  2 ++
 arch/arm/mach-imx/sip.c   | 23 +++
 include/imx_sip.h | 14 ++
 4 files changed, 42 insertions(+)
 create mode 100644 arch/arm/mach-imx/sip.c
 create mode 100644 include/imx_sip.h

diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h 
b/arch/arm/include/asm/mach-imx/sys_proto.h
index d518e03809..c53e5400a1 100644
--- a/arch/arm/include/asm/mach-imx/sys_proto.h
+++ b/arch/arm/include/asm/mach-imx/sys_proto.h
@@ -126,4 +126,7 @@ void lcdif_power_down(void);
 int mxs_reset_block(struct mxs_register_32 *reg);
 int mxs_wait_mask_set(struct mxs_register_32 *reg, u32 mask, u32 timeout);
 int mxs_wait_mask_clr(struct mxs_register_32 *reg, u32 mask, u32 timeout);
+
+unsigned long call_imx_sip(unsigned long id, unsigned long reg0,
+  unsigned long reg1, unsigned long reg2);
 #endif
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index cf39d08bdd..63db0e15c4 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -124,6 +124,8 @@ spl/u-boot-nand-spl.imx: SPL FORCE
 
 targets += $(addprefix ../../../,$(IMX_CONFIG) SPL u-boot.uim 
spl/u-boot-nand-spl.imx)
 
+obj-$(CONFIG_ARM64) += sip.o
+
 obj-$(CONFIG_MX5) += mx5/
 obj-$(CONFIG_MX6) += mx6/
 obj-$(CONFIG_MX7) += mx7/
diff --git a/arch/arm/mach-imx/sip.c b/arch/arm/mach-imx/sip.c
new file mode 100644
index 00..b724330d35
--- /dev/null
+++ b/arch/arm/mach-imx/sip.c
@@ -0,0 +1,23 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+
+unsigned long call_imx_sip(unsigned long id, unsigned long reg0,
+  unsigned long reg1, unsigned long reg2)
+{
+   struct pt_regs regs;
+
+   regs.regs[0] = id;
+   regs.regs[1] = reg0;
+   regs.regs[2] = reg1;
+   regs.regs[3] = reg2;
+
+   smc_call();
+
+   return regs.regs[0];
+}
diff --git a/include/imx_sip.h b/include/imx_sip.h
new file mode 100644
index 00..48ab878749
--- /dev/null
+++ b/include/imx_sip.h
@@ -0,0 +1,14 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef _IMX_SIP_H__
+#define _IMX_SIP_H_
+
+#define IMX_SIP_SRC0xC205
+#define IMX_SIP_SRC_M4_START   0x00
+#define IMX_SIP_SRC_M4_STARTED 0x01
+
+#endif
-- 
2.14.1

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH V5 03/31] imx: mx8m: add register definition header file

[Peng Fan]

Add register definition header file for i.MX8M

Signed-off-by: Peng Fan 
Reviewed-by: Fabio Estevam 
Cc: Stefano Babic 
---
 arch/arm/include/asm/arch-mx8m/imx-regs.h | 468 ++
 1 file changed, 468 insertions(+)
 create mode 100644 arch/arm/include/asm/arch-mx8m/imx-regs.h

diff --git a/arch/arm/include/asm/arch-mx8m/imx-regs.h 
b/arch/arm/include/asm/arch-mx8m/imx-regs.h
new file mode 100644
index 00..a10034cc35
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx8m/imx-regs.h
@@ -0,0 +1,468 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_MX8M_REGS_H__
+#define __ASM_ARCH_MX8M_REGS_H__
+
+#include 
+
+#define ROM_VERSION_A0 0x800
+#define ROM_VERSION_B0 0x83C
+
+#define M4_BOOTROM_BASE_ADDR   0x007E
+
+#define SAI1_BASE_ADDR 0x3001
+#define SAI6_BASE_ADDR 0x3003
+#define SAI5_BASE_ADDR 0x3004
+#define SAI4_BASE_ADDR 0x3005
+#define SPBA2_BASE_ADDR0x300F
+#define AIPS1_BASE_ADDR0x301F
+#define GPIO1_BASE_ADDR0X3020
+#define GPIO2_BASE_ADDR0x3021
+#define GPIO3_BASE_ADDR0x3022
+#define GPIO4_BASE_ADDR0x3023
+#define GPIO5_BASE_ADDR0x3024
+#define ANA_TSENSOR_BASE_ADDR  0x3026
+#define ANA_OSC_BASE_ADDR  0x3027
+#define WDOG1_BASE_ADDR0x3028
+#define WDOG2_BASE_ADDR0x3029
+#define WDOG3_BASE_ADDR0x302A
+#define SDMA2_BASE_ADDR0x302C
+#define GPT1_BASE_ADDR 0x302D
+#define GPT2_BASE_ADDR 0x302E
+#define GPT3_BASE_ADDR 0x302F
+#define ROMCP_BASE_ADDR0x3031
+#define LCDIF_BASE_ADDR0x3032
+#define IOMUXC_BASE_ADDR   0x3033
+#define IOMUXC_GPR_BASE_ADDR   0x3034
+#define OCOTP_BASE_ADDR0x3035
+#define ANATOP_BASE_ADDR   0x3036
+#define SNVS_HP_BASE_ADDR  0x3037
+#define CCM_BASE_ADDR  0x3038
+#define SRC_BASE_ADDR  0x3039
+#define GPC_BASE_ADDR  0x303A
+#define SEMAPHORE1_BASE_ADDR   0x303B
+#define SEMAPHORE2_BASE_ADDR   0x303C
+#define RDC_BASE_ADDR  0x303D
+#define CSU_BASE_ADDR  0x303E
+
+#define AIPS2_BASE_ADDR0x305F
+#define PWM1_BASE_ADDR 0x3066
+#define PWM2_BASE_ADDR 0x3067
+#define PWM3_BASE_ADDR 0x3068
+#define PWM4_BASE_ADDR 0x3069
+#define SYSCNT_RD_BASE_ADDR0x306A
+#define SYSCNT_CMP_BASE_ADDR   0x306B
+#define SYSCNT_CTRL_BASE_ADDR  0x306C
+#define GPT6_BASE_ADDR 0x306E
+#define GPT5_BASE_ADDR 0x306F
+#define GPT4_BASE_ADDR 0x3070
+#define PERFMON1_BASE_ADDR 0x307C
+#define PERFMON2_BASE_ADDR 0x307D
+#define QOSC_BASE_ADDR 0x307F
+
+#define SPDIF1_BASE_ADDR   0x3081
+#define ECSPI1_BASE_ADDR   0x3082
+#define ECSPI2_BASE_ADDR   0x3083
+#define ECSPI3_BASE_ADDR   0x3084
+#define UART1_BASE_ADDR0x3086
+#define UART3_BASE_ADDR0x3088
+#define UART2_BASE_ADDR0x3089
+#define SPDIF2_BASE_ADDR   0x308A
+#define SAI2_BASE_ADDR 0x308B
+#define SAI3_BASE_ADDR 0x308C
+#define SPBA1_BASE_ADDR0x308F
+#define CAAM_BASE_ADDR 0x3090
+#define AIPS3_BASE_ADDR0x309F
+#define MIPI_PHY_BASE_ADDR 0x30A0
+#define MIPI_DSI_BASE_ADDR 0x30A1
+#define I2C1_BASE_ADDR 0x30A2
+#define I2C2_BASE_ADDR 0x30A3
+#define I2C3_BASE_ADDR 0x30A4
+#define I2C4_BASE_ADDR 0x30A5
+#define UART4_BASE_ADDR0x30A6
+#define MIPI_CSI_BASE_ADDR 0x30A7
+#define MIPI_CSI_PHY1_BASE_ADDR0x30A8
+#define CSI1_BASE_ADDR 0x30A9
+#define MU_A_BASE_ADDR 0x30AA
+#define MU_B_BASE_ADDR 0x30AB
+#define SEMAPHOR_HS_BASE_ADDR  0x30AC
+#define USDHC1_BASE_ADDR   0x30B4
+#define USDHC2_BASE_ADDR   0x30B5
+#define MIPI_CS2_BASE_ADDR 0x30B6
+#define MIPI_CSI_PHY2_BASE_ADDR0x30B7
+#define CSI2_BASE_ADDR 0x30B8
+#define QSPI0_BASE_ADDR0x30BB
+#define QSPI0_AMBA_BASE0x0800
+#define SDMA1_BASE_ADDR0x30BD
+#define ENET1_BASE_ADDR0x30BE
+
+#define HDMI_CTRL_BASE_ADDR0x32C0
+#define AIPS4_BASE_ADDR0x32DF
+#define DC1_BASE_ADDR  0x32E0
+#define DC2_BASE_ADDR  0x32E1
+#define DC3_BASE_ADDR  0x32E2
+#define HDMI_SEC_BASE_ADDR 0x32E4
+#define TZASC_BASE_ADDR0x32F8
+#define 

[U-Boot] [PATCH V5 01/31] arm: imx: Rework i.MX specific commands to be excluded from SPL

[Peng Fan]

From: Tom Rini 

The "clocks" and "bootaux" commands are only usable in full U-Boot, not
SPL, so do not link them inside of SPL.  Rework a little of the bootaux
related code to make use of __weak and declare parts of it static as
it's local to the file.

Cc: Stefano Babic 
Cc: Fabio Estevam 
Signed-off-by: Tom Rini 
---
 arch/arm/mach-imx/Makefile   |  2 ++
 arch/arm/mach-imx/imx_bootaux.c  | 13 -
 arch/arm/mach-imx/mx5/clock.c|  4 +++-
 arch/arm/mach-imx/mx7/clock.c|  2 ++
 arch/arm/mach-imx/mx7ulp/clock.c |  2 ++
 5 files changed, 13 insertions(+), 10 deletions(-)

diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index d7966cfd4a..cf39d08bdd 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -28,7 +28,9 @@ obj-y += cache.o init.o
 obj-$(CONFIG_SATA) += sata.o
 obj-$(CONFIG_IMX_VIDEO_SKIP) += video.o
 obj-$(CONFIG_IMX_RDC) += rdc-sema.o
+ifneq ($(CONFIG_SPL_BUILD),y)
 obj-$(CONFIG_IMX_BOOTAUX) += imx_bootaux.o
+endif
 obj-$(CONFIG_SECURE_BOOT)+= hab.o
 obj-$(CONFIG_SYSCOUNTER_TIMER) += syscounter.o
 endif
diff --git a/arch/arm/mach-imx/imx_bootaux.c b/arch/arm/mach-imx/imx_bootaux.c
index 69026df763..b62dfbf6bf 100644
--- a/arch/arm/mach-imx/imx_bootaux.c
+++ b/arch/arm/mach-imx/imx_bootaux.c
@@ -6,27 +6,22 @@
 
 #include 
 #include 
+#include 
 
 /* Allow for arch specific config before we boot */
-static int __arch_auxiliary_core_up(u32 core_id, u32 boot_private_data)
+int __weak arch_auxiliary_core_up(u32 core_id, u32 boot_private_data)
 {
/* please define platform specific arch_auxiliary_core_up() */
return CMD_RET_FAILURE;
 }
 
-int arch_auxiliary_core_up(u32 core_id, u32 boot_private_data)
-   __attribute__((weak, alias("__arch_auxiliary_core_up")));
-
 /* Allow for arch specific config before we boot */
-static int __arch_auxiliary_core_check_up(u32 core_id)
+int __weak arch_auxiliary_core_check_up(u32 core_id)
 {
/* please define platform specific arch_auxiliary_core_check_up() */
return 0;
 }
 
-int arch_auxiliary_core_check_up(u32 core_id)
-   __attribute__((weak, alias("__arch_auxiliary_core_check_up")));
-
 /*
  * To i.MX6SX and i.MX7D, the image supported by bootaux needs
  * the reset vector at the head for the image, with SP and PC
@@ -40,7 +35,7 @@ int arch_auxiliary_core_check_up(u32 core_id)
  * The TCMUL is mapped to (M4_BOOTROM_BASE_ADDR) at A core side for
  * accessing the M4 TCMUL.
  */
-int do_bootaux(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+static int do_bootaux(cmd_tbl_t *cmdtp, int flag, int argc, char * const 
argv[])
 {
ulong addr;
int ret, up;
diff --git a/arch/arm/mach-imx/mx5/clock.c b/arch/arm/mach-imx/mx5/clock.c
index 610098c175..284f6d4cde 100644
--- a/arch/arm/mach-imx/mx5/clock.c
+++ b/arch/arm/mach-imx/mx5/clock.c
@@ -911,10 +911,11 @@ void mxc_set_sata_internal_clock(void)
 }
 #endif
 
+#ifndef CONFIG_SPL_BUILD
 /*
  * Dump some core clockes.
  */
-int do_mx5_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const 
argv[])
+static int do_mx5_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * 
const argv[])
 {
u32 freq;
 
@@ -947,3 +948,4 @@ U_BOOT_CMD(
"display clocks",
""
 );
+#endif
diff --git a/arch/arm/mach-imx/mx7/clock.c b/arch/arm/mach-imx/mx7/clock.c
index 8150faa1a3..c11042d6f5 100644
--- a/arch/arm/mach-imx/mx7/clock.c
+++ b/arch/arm/mach-imx/mx7/clock.c
@@ -1096,6 +1096,7 @@ void epdc_clock_disable(void)
 }
 #endif
 
+#ifndef CONFIG_SPL_BUILD
 /*
  * Dump some core clockes.
  */
@@ -1131,3 +1132,4 @@ U_BOOT_CMD(
"display clocks",
""
 );
+#endif
diff --git a/arch/arm/mach-imx/mx7ulp/clock.c b/arch/arm/mach-imx/mx7ulp/clock.c
index 77b282addd..553d62149d 100644
--- a/arch/arm/mach-imx/mx7ulp/clock.c
+++ b/arch/arm/mach-imx/mx7ulp/clock.c
@@ -323,6 +323,7 @@ void hab_caam_clock_enable(unsigned char enable)
 }
 #endif
 
+#ifndef CONFIG_SPL_BUILD
 /*
  * Dump some core clockes.
  */
@@ -363,3 +364,4 @@ U_BOOT_CMD(
"display clocks",
""
 );
+#endif
-- 
2.14.1

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH V5 02/31] imx: add i.MX8M into Kconfig

[Peng Fan]

Add i.MX8M into Kconfig, create a new folder mx8m
dedicated for i.MX8M.

Signed-off-by: Peng Fan 
Reviewed-by: Fabio Estevam 
Cc: Stefano Babic 
---
 arch/arm/Kconfig   | 14 +++---
 arch/arm/Makefile  |  4 ++--
 arch/arm/mach-imx/mx8m/Kconfig | 10 ++
 3 files changed, 23 insertions(+), 5 deletions(-)
 create mode 100644 arch/arm/mach-imx/mx8m/Kconfig

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index f2c35e32c6..b095bfe2e5 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -604,6 +604,12 @@ config ARCH_MESON
  targeted at media players and tablet computers. We currently
  support the S905 (GXBaby) 64-bit SoC.
 
+config ARCH_MX8M
+   bool "NXP i.MX8M platform"
+   select ARM64
+   select DM
+   select SUPPORT_SPL
+
 config ARCH_MX25
bool "NXP MX25"
select CPU_ARM926EJS
@@ -1180,13 +1186,15 @@ source "arch/arm/cpu/armv7/ls102xa/Kconfig"
 
 source "arch/arm/mach-imx/mx2/Kconfig"
 
-source "arch/arm/mach-imx/mx7ulp/Kconfig"
+source "arch/arm/mach-imx/mx5/Kconfig"
+
+source "arch/arm/mach-imx/mx6/Kconfig"
 
 source "arch/arm/mach-imx/mx7/Kconfig"
 
-source "arch/arm/mach-imx/mx6/Kconfig"
+source "arch/arm/mach-imx/mx7ulp/Kconfig"
 
-source "arch/arm/mach-imx/mx5/Kconfig"
+source "arch/arm/mach-imx/mx8m/Kconfig"
 
 source "arch/arm/mach-omap2/Kconfig"
 
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 0e0ae77822..5881fdc8e2 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -95,11 +95,11 @@ libs-y += arch/arm/cpu/
 libs-y += arch/arm/lib/
 
 ifeq ($(CONFIG_SPL_BUILD),y)
-ifneq (,$(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_MX35)$(filter $(SOC), mx25 mx5 
mx6 mx7 mx35))
+ifneq (,$(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_MX35)$(filter $(SOC), mx25 mx5 
mx6 mx7 mx35 mx8m))
 libs-y += arch/arm/mach-imx/
 endif
 else
-ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx7 mx7ulp mx31 mx35 mxs vf610))
+ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx7 mx7ulp mx31 mx35 mxs mx8m 
vf610))
 libs-y += arch/arm/mach-imx/
 endif
 endif
diff --git a/arch/arm/mach-imx/mx8m/Kconfig b/arch/arm/mach-imx/mx8m/Kconfig
new file mode 100644
index 00..3a84c2f2b0
--- /dev/null
+++ b/arch/arm/mach-imx/mx8m/Kconfig
@@ -0,0 +1,10 @@
+if ARCH_MX8M
+
+config MX8M
+   bool
+   select ROM_UNIFIED_SECTIONS
+
+config SYS_SOC
+   default "mx8m"
+
+endif
-- 
2.14.1

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH V5 00/31] imx: add i.MX8M support and i.MX8MQ EVK

[Peng Fan]

This patchset is to add i.MX8M and i.MX8MQ-EVK support

V5:
 Drop wait_mask_set/clr_timeout and switch to use readl_poll_timeout in
 the patchset.

V4:
 Regenerate patchset based on Tom's master tree. 
 In this patchset, https://patchwork.ozlabs.org/patch/855027/
 "arm: imx: Rework i.MX specific commands to be excluded from SPL" from
 Tom is included to avoid merge conflicts because the i.mx8m change
 also has some modification to bootaux and arch/arm/mach-imx/Makefile.
 Because CONFIG_GPT_TIMER change, I did a small modification to apply
 Tom's patch, no function change.

 Include ATF link in README.

V3:
 This patchset based on https://patchwork.ozlabs.org/patch/855027/
 "arm: imx: Rework i.MX specific commands to be excluded from SPL" from
 Tom to avoid this patchset fail apply after Tom's patch merged.

 Previously "power: pmic/regulator allow dm be omited by SPL" broke other
 boards, in V3 patchset, only touch pfuze100 related options.

 Sharing code about get mac from fuse between mx7/mx8m
 Sharing code about bootaux between mx6/7/mx8m
 Sharing code about cpu speed grade between mx7/mx8m
 Sharing code about get boot device between mx7/mx8m
 Sharding code about mmc env between mx7/mx8m

 Introduce wait_mask_set/clr_timeout to avoid deadloop in clock pll 
configuration

 Correct authorship of fix building warning on fec arm64, patch 27/31.

 Switch to use structure for DDR Controller. For DDR PHY registers,
 there are about more than 10 thousands registers, I could not convert
 them with detailed register name, and the script is generated from IC team,
 So I use regs[0x] arrays here fo easily converting between IC team
 released script and uboot ddr phy cod.

 Improve REAMME file to include where to download firmware and imx-mkimage
 and how to build

 Add review tags on the V2 patchset.

 Hope this patchset could catch up next release :)

V2:

 patch 02/23: convert to structure, drop is_boot_from_usb and
  disconnect_from_usb
 patch 04/23: conver to use structure for the clock driver, removed the
  CCM_xxx macros. Add static for local functons.
  Add init_usdhc_clk, init_uart_clk and etc to not enable
  them all at default.
 patch 05/23: Add more commit msg for the sip part.
 patch 08/23: Merge the spl boot device with i.MX7
 patch 12/23: Typo fix and return error fix from Heiko for the SoC related part
 patch 22/23: Use a weak function ddr_init. If patch 23/23 could not be
  accepted at current stage, to make others still be could be
  compiled.

The patchset depends on
https://patchwork.ozlabs.org/patch/841934/
https://patchwork.ozlabs.org/patch/841958/
to be tested on real hardware.

V1:

patch: "power: pmic.h: include dm/ofnode.h" and
"power: pmic/regulator allow dm be omited by SPL" is previously reviewed
in mailist to not merged. If no issue, you may pick it up.

The board support is a large patch because of the ddr related code.
If it is not good, please first review/pick-up other patches if they
are ok.



Peng Fan (29):
  imx: add i.MX8M into Kconfig
  imx: mx8m: add register definition header file
  imx: mx8m: add pin header file
  imx: mx8m: add clock driver
  imx: add sip function
  imx: boot_mode: add USB_BOOT entry
  imx: cpu: update cpu file to support i.MX8M
  imx: spl: implement spl_boot_device for i.MX8M
  imx: add i.MX8MQ SoC Revision and is_mx8m helper
  imx: add pad settings bit definition for i.MX8M
  imx: cpu: move speed/temp to common cpu
  imx: cpu: add cpu speed/grade for i.MX8M
  imx: refactor imx_get_mac_from_fuse
  imx: cleanup bootaux
  imx: bootaux: support i.MX8M
  imx: mx7: move get_boot_device to cpu.c
  imx: cpu: support get_boot_device for i.MX8M
  imx: mx7: move mmc env code to mmc_env.c
  imx: mx8m: add soc related settings and files
  imx: makefile: compile files for i.MX8M
  misc: ocotp: add i.MX8M support
  mmc: fsl_esdhc: support i.MX8M
  imx: lcdif: include i.MX8M
  gpio: mxc: add i.MX8M support
  net: fec: do not access reserved register for i.MX8M
  imx: imx8mq: add dtsi file
  power: pmic/regulator allow dm be omitted by SPL
  imx: mx8m: add ddr controller memory map
  imx: add i.MX8MQ EVK support

Tom Rini (1):
  arm: imx: Rework i.MX specific commands to be excluded from SPL

Ye Li (1):
  net: fec: fix build warnings for 64bits support

 arch/arm/Kconfig |   14 +-
 arch/arm/Makefile|4 +-
 arch/arm/dts/Makefile|2 +
 arch/arm/dts/fsl-imx8-ca53.dtsi  |   92 ++
 arch/arm/dts/fsl-imx8mq-evk.dts  |  424 +
 arch/arm/dts/fsl-imx8mq.dtsi |  429 +
 arch/arm/include/asm/arch-imx/cpu.h  |6 +-
 arch/arm/include/asm/arch-mx6/imx-regs.h |9 +-
 arch/arm/include/asm/arch-mx7/imx-regs.h |   18 +-
 arch/arm/include/asm/arch-mx8m/clock.h   |  657 +
 arch/arm/include/asm/arch-mx8m/crm_regs.h|   10 +
 

Re: [U-Boot] [PATCH V4 05/32] time: add wait_mask_set/clr_timeout helper functions

[Peng Fan]

On Wed, Jan 10, 2018 at 12:19:28PM +0900, Masahiro Yamada wrote:
>2018-01-10 12:05 GMT+09:00 Peng Fan :
>> Add heler functions for wait mask set/clr.
>>
>> Signed-off-by: Peng Fan 
>> Cc: Stefano Babic 
>> Cc: Fabio Estevam 
>> Cc: Masahiro Yamada 
>> Cc: Simon Glass 
>> ---
>>  include/linux/delay.h |  4 
>>  lib/time.c| 30 ++
>>  2 files changed, 34 insertions(+)
>>
>> diff --git a/include/linux/delay.h b/include/linux/delay.h
>> index 3dcd435d0d..b08fcb8c09 100644
>> --- a/include/linux/delay.h
>> +++ b/include/linux/delay.h
>> @@ -21,4 +21,8 @@ static inline void ndelay(unsigned long nsec)
>> udelay(DIV_ROUND_UP(nsec, 1000));
>>  }
>>
>> +int wait_mask_set_timeout(void *addr, u32 mask, u32 timeout);
>> +
>> +int wait_mask_clr_timeout(void *addr, u32 mask, u32 timeout);
>> +
>>  #endif /* defined(_LINUX_DELAY_H) */
>> diff --git a/lib/time.c b/lib/time.c
>> index aed1a091f2..9701287629 100644
>> --- a/lib/time.c
>> +++ b/lib/time.c
>> @@ -171,3 +171,33 @@ void udelay(unsigned long usec)
>> usec -= kv;
>> } while(usec);
>>  }
>> +
>> +int wait_mask_set_timeout(void *addr, u32 mask, u32 timeout)
>> +{
>> +   unsigned long long end_tick;
>> +   u32 val;
>> +
>> +   end_tick = usec_to_tick(timeout) + get_ticks();
>> +   do {
>> +   val = readl(addr);
>> +   if ((val & mask) == mask)
>> +   return 0;
>> +   } while (end_tick > get_ticks());
>> +
>> +   return -ETIMEDOUT;
>> +}
>> +
>> +int wait_mask_clr_timeout(void *addr, u32 mask, u32 timeout)
>> +{
>> +   unsigned long long end_tick;
>> +   u32 val;
>> +
>> +   end_tick = usec_to_tick(timeout) + get_ticks();
>> +   do {
>> +   val = readl(addr);
>> +   if (!(val & mask))
>> +   return 0;
>> +   } while (end_tick > get_ticks());
>> +
>> +   return -ETIMEDOUT;
>> +}
>> --
>
>NACK.
>
>You are re-inventing wheel.
>
>Please use include/linux/iopoll.h

Thanks for the info. I'll discard this patch and fix the usage in the patchset.

Thanks,
Peng.

>
>
>
>
>
>-- 
>Best Regards
>Masahiro Yamada
>___
>U-Boot mailing list
>U-Boot@lists.denx.de
>https://lists.denx.de/listinfo/u-boot

-- 
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH] ddr: marvell: only assert M_ODT[0] on write for a single CS

[Chris Packham]

When using only a single DDR chip select only assert M_ODT[0] on write.
Do not assert it on read and do not assert M_ODT[1] at all.

Signed-off-by: Chris Packham 

---
I have a custom board that sees correctable ECC errors (when running
memtester[1] from Linux). When I used Marvell's bootloader I didn't see
the errors.

There are a number of differences in Marvell's bootloader but this
seems to be the minimal change that fixes my issue and may help other
boards using a single CS. I've regression tested the db-88f6820-amc
board.

 drivers/ddr/marvell/a38x/ddr3_init.h|  3 ++-
 drivers/ddr/marvell/a38x/ddr3_training.c| 14 +-
 drivers/ddr/marvell/a38x/ddr3_training_static.c |  3 ++-
 3 files changed, 13 insertions(+), 7 deletions(-)

diff --git a/drivers/ddr/marvell/a38x/ddr3_init.h 
b/drivers/ddr/marvell/a38x/ddr3_init.h
index 8cb08864c292..a4c75a9fa68f 100644
--- a/drivers/ddr/marvell/a38x/ddr3_init.h
+++ b/drivers/ddr/marvell/a38x/ddr3_init.h
@@ -183,7 +183,8 @@ extern u32 g_znodt_data;
 extern u32 g_zpodt_ctrl;
 extern u32 g_znodt_ctrl;
 extern u32 g_dic;
-extern u32 g_odt_config;
+extern u32 g_odt_config_2cs;
+extern u32 g_odt_config_1cs;
 extern u32 g_rtt_nom;
 
 extern u8 debug_training_access;
diff --git a/drivers/ddr/marvell/a38x/ddr3_training.c 
b/drivers/ddr/marvell/a38x/ddr3_training.c
index e70ca4b42551..e82c317fab7b 100644
--- a/drivers/ddr/marvell/a38x/ddr3_training.c
+++ b/drivers/ddr/marvell/a38x/ddr3_training.c
@@ -315,6 +315,7 @@ int hws_ddr3_tip_init_controller(u32 dev_num, struct 
init_cntr_param *init_cntr_
enum hws_access_type access_type = ACCESS_TYPE_UNICAST;
u32 data_read[MAX_INTERFACE_NUM];
struct hws_topology_map *tm = ddr3_get_topology_map();
+   u32 odt_config = g_odt_config_2cs;
 
DEBUG_TRAINING_IP(DEBUG_LEVEL_TRACE,
  ("Init_controller, do_mrs_phy=%d, is_ctrl64_bit=%d\n",
@@ -570,6 +571,10 @@ int hws_ddr3_tip_init_controller(u32 dev_num, struct 
init_cntr_param *init_cntr_
  DUNIT_CONTROL_HIGH_REG,
  (init_cntr_prm->msys_init << 7), (1 << 
7)));
 
+   /* calculate number of CS (per interface) */
+   CHECK_STATUS(calc_cs_num
+(dev_num, if_id, _num));
+
timing = tm->interface_params[if_id].timing;
 
if (mode2_t != 0xff) {
@@ -578,9 +583,6 @@ int hws_ddr3_tip_init_controller(u32 dev_num, struct 
init_cntr_param *init_cntr_
/* Board topology map is forcing timing */
t2t = (timing == HWS_TIM_2T) ? 1 : 0;
} else {
-   /* calculate number of CS (per interface) */
-   CHECK_STATUS(calc_cs_num
-(dev_num, if_id, _num));
t2t = (cs_num == 1) ? 0 : 1;
}
 
@@ -623,9 +625,11 @@ int hws_ddr3_tip_init_controller(u32 dev_num, struct 
init_cntr_param *init_cntr_
  (1 << 11)));
 
/* Set Active control for ODT write transactions */
+   if (cs_num == 1)
+   odt_config = g_odt_config_1cs;
CHECK_STATUS(ddr3_tip_if_write
 (dev_num, ACCESS_TYPE_MULTICAST,
- PARAM_NOT_CARE, 0x1494, g_odt_config,
+ PARAM_NOT_CARE, 0x1494, odt_config,
  MASK_ALL_BITS));
}
} else {
@@ -1591,7 +1595,7 @@ static int ddr3_tip_write_odt(u32 dev_num, enum 
hws_access_type access_type,
 
CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id,
   ODT_TIMING_LOW, val, 0x0));
-   val = 0x71 | ((cwl_value - 1) << 8) | ((cwl_value + 5) << 12);
+   val = 0x91 | ((cwl_value - 1) << 8) | ((cwl_value + 5) << 12);
CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id,
   ODT_TIMING_HI_REG, val, 0x));
if (odt_additional == 1) {
diff --git a/drivers/ddr/marvell/a38x/ddr3_training_static.c 
b/drivers/ddr/marvell/a38x/ddr3_training_static.c
index 5101f3f38349..b73bbf4f1b0d 100644
--- a/drivers/ddr/marvell/a38x/ddr3_training_static.c
+++ b/drivers/ddr/marvell/a38x/ddr3_training_static.c
@@ -21,7 +21,8 @@ u32 g_zpodt_data = 45;/* controller data - P 
ODT */
 u32 g_znodt_data = 45; /* controller data - N ODT */
 u32 g_zpodt_ctrl = 45; /* controller data - P ODT */
 u32 g_znodt_ctrl = 45; /* controller data - N ODT */
-u32 g_odt_config = 0x120012;
+u32 g_odt_config_2cs = 0x120012;
+u32 g_odt_config_1cs = 0x1;
 u32 g_rtt_nom = 0x44;
 u32 g_dic = 

Re: [U-Boot] [PATCH V4 05/32] time: add wait_mask_set/clr_timeout helper functions

[Masahiro Yamada]

2018-01-10 12:05 GMT+09:00 Peng Fan :
> Add heler functions for wait mask set/clr.
>
> Signed-off-by: Peng Fan 
> Cc: Stefano Babic 
> Cc: Fabio Estevam 
> Cc: Masahiro Yamada 
> Cc: Simon Glass 
> ---
>  include/linux/delay.h |  4 
>  lib/time.c| 30 ++
>  2 files changed, 34 insertions(+)
>
> diff --git a/include/linux/delay.h b/include/linux/delay.h
> index 3dcd435d0d..b08fcb8c09 100644
> --- a/include/linux/delay.h
> +++ b/include/linux/delay.h
> @@ -21,4 +21,8 @@ static inline void ndelay(unsigned long nsec)
> udelay(DIV_ROUND_UP(nsec, 1000));
>  }
>
> +int wait_mask_set_timeout(void *addr, u32 mask, u32 timeout);
> +
> +int wait_mask_clr_timeout(void *addr, u32 mask, u32 timeout);
> +
>  #endif /* defined(_LINUX_DELAY_H) */
> diff --git a/lib/time.c b/lib/time.c
> index aed1a091f2..9701287629 100644
> --- a/lib/time.c
> +++ b/lib/time.c
> @@ -171,3 +171,33 @@ void udelay(unsigned long usec)
> usec -= kv;
> } while(usec);
>  }
> +
> +int wait_mask_set_timeout(void *addr, u32 mask, u32 timeout)
> +{
> +   unsigned long long end_tick;
> +   u32 val;
> +
> +   end_tick = usec_to_tick(timeout) + get_ticks();
> +   do {
> +   val = readl(addr);
> +   if ((val & mask) == mask)
> +   return 0;
> +   } while (end_tick > get_ticks());
> +
> +   return -ETIMEDOUT;
> +}
> +
> +int wait_mask_clr_timeout(void *addr, u32 mask, u32 timeout)
> +{
> +   unsigned long long end_tick;
> +   u32 val;
> +
> +   end_tick = usec_to_tick(timeout) + get_ticks();
> +   do {
> +   val = readl(addr);
> +   if (!(val & mask))
> +   return 0;
> +   } while (end_tick > get_ticks());
> +
> +   return -ETIMEDOUT;
> +}
> --

NACK.

You are re-inventing wheel.

Please use include/linux/iopoll.h





-- 
Best Regards
Masahiro Yamada
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [GIT PULL] ZFS: lundman/master

[Jorgen Lundman]

Hello,
I didn't hear back about the changes, so I'll proceed to this stage. :)
Please find additional ZFS boot features, and fixes. Please advise if
outside git repositories are not allowed.

The following changes since commit ab61e175713a0400c6ece6348e8f655998cf574d:

  ARM: rmobile: Rework the ULCB CPLD driver (Sun Nov 26 20:32:44 2017 +0100)

are available in the git repository at:

  https://github.com/lundman/u-boot.git master

for you to fetch changes up to c2727e5004fe011d19156d728babdf968515b28d:

  Update ZFS support to latest (Thu Dec 7 16:09:26 2017 +0900)

Jorgen Lundman (1):
  Update ZFS support to latest

 cmd/zfs.c|   22 +-
 fs/zfs/Makefile  |4 +-
 fs/zfs/dev.c |   20 +-
 fs/zfs/zfs.c | 3223 +++---
 fs/zfs/zfs_fletcher.c|6 +-
 fs/zfs/zfs_lz4.c |  286 
 fs/zfs/zfs_sha256.c  |   14 +-
 include/zfs/dmu.h|   48 +-
 include/zfs/sa_impl.h|5 +-
 include/zfs/spa.h|   18 +
 include/zfs/uberblock_impl.h |   15 +-
 include/zfs/zap_leaf.h   |4 +-
 include/zfs/zfs.h|   22 +-
 include/zfs/zio.h|9 +-
 include/zfs_common.h |   27 +-
 15 files changed, 2819 insertions(+), 904 deletions(-)


-- 
Jorgen Lundman   | 
Unix Administrator   | +81 (0)90-5578-8500
Shibuya-ku, Tokyo| Japan

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH V4 32/32] imx: add i.MX8MQ EVK support

[Peng Fan]

Add i.MX8MQ EVK support. SPL will initialize ddr and load ddr phy
firmware. Then loading FIT image, ATF to OCRAM, U-Boot and DTB to
DRAM.

The boot log with Arm trusted firmware console enabled:
"
U-Boot SPL 2018.01-rc3-00044-g0b075f6be7 (Jan 09 2018 - 17:57:28)
PMIC:  PFUZE100 ID=0x10
Normal Boot
Trying to boot from MMC2
NOTICE:  Configureing TZASC380
NOTICE:  BL31: v1.4(release):o8.0.0_1.3.0_8m-prc-20171211-6-g54fb0797-dirty
NOTICE:  BL31: Built : 07:17:16, Jan  8 2018
NOTICE:  sip svc init

U-Boot 2018.01-rc3-00044-g0b075f6be7 (Jan 09 2018 - 17:57:28 +0800)

CPU:   Freescale i.MX8MQ rev2.0 at 1000 MHz
Reset cause: POR
Model: Freescale i.MX8MQ EVK
DRAM:  3 GiB
MMC:   FSL_SDHC: 0, FSL_SDHC: 1
Using default environment

In:serial
Out:   serial
Err:   serial
Net:   No ethernet found.
Hit any key to stop autoboot:  0
u-boot=>
"

Signed-off-by: Peng Fan 
Cc: Fabio Estevam 
Cc: Stefano Babic 
---
 arch/arm/dts/Makefile|2 +
 arch/arm/dts/fsl-imx8mq-evk.dts  |  424 +
 arch/arm/include/asm/arch-mx8m/ddr.h |9 +
 arch/arm/mach-imx/mx8m/Kconfig   |   12 +
 board/freescale/mx8mq_evk/Kconfig|   12 +
 board/freescale/mx8mq_evk/Makefile   |   12 +
 board/freescale/mx8mq_evk/README |   47 +
 board/freescale/mx8mq_evk/ddr/ddr_init.c |  238 +
 board/freescale/mx8mq_evk/ddr/ddrphy_train.c | 1253 ++
 board/freescale/mx8mq_evk/ddr/helper.c   |  101 +++
 board/freescale/mx8mq_evk/mx8mq_evk.c|  156 
 board/freescale/mx8mq_evk/spl.c  |  230 +
 configs/mx8mq_evk_defconfig  |   27 +
 include/configs/mx8mq_evk.h  |  269 ++
 14 files changed, 2792 insertions(+)
 create mode 100644 arch/arm/dts/fsl-imx8mq-evk.dts
 create mode 100644 board/freescale/mx8mq_evk/Kconfig
 create mode 100644 board/freescale/mx8mq_evk/Makefile
 create mode 100644 board/freescale/mx8mq_evk/README
 create mode 100644 board/freescale/mx8mq_evk/ddr/ddr_init.c
 create mode 100644 board/freescale/mx8mq_evk/ddr/ddrphy_train.c
 create mode 100644 board/freescale/mx8mq_evk/ddr/helper.c
 create mode 100644 board/freescale/mx8mq_evk/mx8mq_evk.c
 create mode 100644 board/freescale/mx8mq_evk/spl.c
 create mode 100644 configs/mx8mq_evk_defconfig
 create mode 100644 include/configs/mx8mq_evk.h

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index a895c70284..299107977f 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -391,6 +391,8 @@ dtb-$(CONFIG_MX7) += imx7-colibri.dtb \
 
 dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-evk.dtb
 
+dtb-$(CONFIG_ARCH_MX8M) += fsl-imx8mq-evk.dtb
+
 dtb-$(CONFIG_RCAR_GEN3) += \
r8a7795-h3ulcb.dtb \
r8a7795-salvator-x.dtb \
diff --git a/arch/arm/dts/fsl-imx8mq-evk.dts b/arch/arm/dts/fsl-imx8mq-evk.dts
new file mode 100644
index 00..f0aa3485e6
--- /dev/null
+++ b/arch/arm/dts/fsl-imx8mq-evk.dts
@@ -0,0 +1,424 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+
+/* First 128KB is for PSCI ATF. */
+/memreserve/ 0x4000 0x0002;
+
+#include "fsl-imx8mq.dtsi"
+
+/ {
+   model = "Freescale i.MX8MQ EVK";
+   compatible = "fsl,imx8mq-evk", "fsl,imx8mq";
+
+   chosen {
+   bootargs = "console=ttymxc0,115200 
earlycon=ec_imx6q,0x3086,115200";
+   };
+
+   regulators {
+   compatible = "simple-bus";
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   reg_usdhc2_vmmc: usdhc2_vmmc {
+   compatible = "regulator-fixed";
+   regulator-name = "VSD_3V3";
+   regulator-min-microvolt = <330>;
+   regulator-max-microvolt = <330>;
+   gpio = < 19 GPIO_ACTIVE_HIGH>;
+   enable-active-high;
+   };
+   };
+
+   pwmleds {
+   compatible = "pwm-leds";
+
+   ledpwm2 {
+   label = "PWM2";
+   pwms = < 0 5>;
+   max-brightness = <255>;
+   };
+   };
+};
+
+ {
+   pinctrl-names = "default";
+
+   imx8mq-evk {
+   pinctrl_fec1: fec1grp {
+   fsl,pins = <
+   MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3
+ 

[U-Boot] [PATCH V4 23/32] misc: ocotp: add i.MX8M support

[Peng Fan]

i.MX8M OCOTP follow same flow as i.MX6Q, but it has 64 banks
and each bank 4 words.

Signed-off-by: Peng Fan 
Reviewed-by: Stefano Babic 
Reviewed-by: Fabio Estevam 
---
 drivers/misc/mxc_ocotp.c | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/drivers/misc/mxc_ocotp.c b/drivers/misc/mxc_ocotp.c
index 8986bb4ad0..0cf24a4c88 100644
--- a/drivers/misc/mxc_ocotp.c
+++ b/drivers/misc/mxc_ocotp.c
@@ -35,6 +35,8 @@
 #define BM_OUT_STATUS_DED  0x0400
 #define BM_OUT_STATUS_LOCKED   0x0800
 #define BM_OUT_STATUS_PROGFAIL 0x1000
+#elif defined(CONFIG_MX8M)
+#define BM_CTRL_ADDR   0x00ff
 #else
 #define BM_CTRL_ADDR   0x007f
 #endif
@@ -79,6 +81,9 @@
 #elif defined(CONFIG_MX7ULP)
 #define FUSE_BANK_SIZE 0x80
 #define FUSE_BANKS 31
+#elif defined(CONFIG_MX8M)
+#define FUSE_BANK_SIZE 0x40
+#define FUSE_BANKS 64
 #else
 #error "Unsupported architecture\n"
 #endif
@@ -294,6 +299,8 @@ static void setup_direct_access(struct ocotp_regs *regs, 
u32 bank, u32 word,
u32 wr_unlock = write ? BV_CTRL_WR_UNLOCK_KEY : 0;
 #ifdef CONFIG_MX7
u32 addr = bank;
+#elif defined CONFIG_MX8M
+   u32 addr = bank << 2 | word;
 #else
u32 addr;
/* Bank 7 and Bank 8 only supports 4 words each for i.MX6ULL */
-- 
2.14.1

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH V4 28/32] net: fec: fix build warnings for 64bits support

[Peng Fan]

From: Ye Li 

When building for 64bits system, we get some warnings about type
cast between pointer and integer. This patch eliminates the warnings
by using ulong/long type which is 32bits on 32bits system or 64bits on
64bits system.

Signed-off-by: Ye Li 
Signed-off-by: Peng Fan 
Acked-by: Joe Hershberger 
Reviewed-by: Stefano Babic 
Reviewed-by: Fabio Estevam 
---
 drivers/net/fec_mxc.c | 74 ++-
 1 file changed, 43 insertions(+), 31 deletions(-)

diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
index 4cbc8cbbfd..ff7ad91116 100644
--- a/drivers/net/fec_mxc.c
+++ b/drivers/net/fec_mxc.c
@@ -284,7 +284,7 @@ static int fec_tx_task_disable(struct fec_priv *fec)
 static void fec_rbd_init(struct fec_priv *fec, int count, int dsize)
 {
uint32_t size;
-   uint8_t *data;
+   ulong data;
int i;
 
/*
@@ -293,9 +293,9 @@ static void fec_rbd_init(struct fec_priv *fec, int count, 
int dsize)
 */
size = roundup(dsize, ARCH_DMA_MINALIGN);
for (i = 0; i < count; i++) {
-   data = (uint8_t *)fec->rbd_base[i].data_pointer;
-   memset(data, 0, dsize);
-   flush_dcache_range((uint32_t)data, (uint32_t)data + size);
+   data = fec->rbd_base[i].data_pointer;
+   memset((void *)data, 0, dsize);
+   flush_dcache_range(data, data + size);
 
fec->rbd_base[i].status = FEC_RBD_EMPTY;
fec->rbd_base[i].data_length = 0;
@@ -305,8 +305,8 @@ static void fec_rbd_init(struct fec_priv *fec, int count, 
int dsize)
fec->rbd_base[i - 1].status = FEC_RBD_WRAP | FEC_RBD_EMPTY;
fec->rbd_index = 0;
 
-   flush_dcache_range((unsigned)fec->rbd_base,
-  (unsigned)fec->rbd_base + size);
+   flush_dcache_range((ulong)fec->rbd_base,
+  (ulong)fec->rbd_base + size);
 }
 
 /**
@@ -323,7 +323,7 @@ static void fec_rbd_init(struct fec_priv *fec, int count, 
int dsize)
  */
 static void fec_tbd_init(struct fec_priv *fec)
 {
-   unsigned addr = (unsigned)fec->tbd_base;
+   ulong addr = (ulong)fec->tbd_base;
unsigned size = roundup(2 * sizeof(struct fec_bd),
ARCH_DMA_MINALIGN);
 
@@ -423,7 +423,7 @@ static int fec_open(struct eth_device *edev)
struct fec_priv *fec = (struct fec_priv *)edev->priv;
 #endif
int speed;
-   uint32_t addr, size;
+   ulong addr, size;
int i;
 
debug("fec_open: fec_open(dev)\n");
@@ -439,7 +439,7 @@ static int fec_open(struct eth_device *edev)
/* Flush the descriptors into RAM */
size = roundup(FEC_RBD_NUM * sizeof(struct fec_bd),
ARCH_DMA_MINALIGN);
-   addr = (uint32_t)fec->rbd_base;
+   addr = (ulong)fec->rbd_base;
flush_dcache_range(addr, addr + size);
 
 #ifdef FEC_QUIRK_ENET_MAC
@@ -533,8 +533,9 @@ static int fec_init(struct eth_device *dev, bd_t *bd)
 #else
struct fec_priv *fec = (struct fec_priv *)dev->priv;
 #endif
-   uint32_t mib_ptr = (uint32_t)>eth->rmon_t_drop;
-   int i;
+   u8 *mib_ptr = (uint8_t *)>eth->rmon_t_drop;
+   u8 *i;
+   ulong addr;
 
/* Initialize MAC address */
 #ifdef CONFIG_DM_ETH
@@ -574,8 +575,12 @@ static int fec_init(struct eth_device *dev, bd_t *bd)
 
/* size and address of each buffer */
writel(FEC_MAX_PKT_SIZE, >eth->emrbr);
-   writel((uint32_t)fec->tbd_base, >eth->etdsr);
-   writel((uint32_t)fec->rbd_base, >eth->erdsr);
+
+   addr = (ulong)fec->tbd_base;
+   writel((uint32_t)addr, >eth->etdsr);
+
+   addr = (ulong)fec->rbd_base;
+   writel((uint32_t)addr, >eth->erdsr);
 
 #ifndef CONFIG_PHYLIB
if (fec->xcv_type != SEVENWIRE)
@@ -640,8 +645,8 @@ static int fec_send(struct eth_device *dev, void *packet, 
int length)
 #endif
 {
unsigned int status;
-   uint32_t size, end;
-   uint32_t addr;
+   u32 size;
+   ulong addr, end;
int timeout = FEC_XFER_TIMEOUT;
int ret = 0;
 
@@ -672,13 +677,13 @@ static int fec_send(struct eth_device *dev, void *packet, 
int length)
swap_packet((uint32_t *)packet, length);
 #endif
 
-   addr = (uint32_t)packet;
+   addr = (ulong)packet;
end = roundup(addr + length, ARCH_DMA_MINALIGN);
addr &= ~(ARCH_DMA_MINALIGN - 1);
flush_dcache_range(addr, end);
 
writew(length, >tbd_base[fec->tbd_index].data_length);
-   writel(addr, >tbd_base[fec->tbd_index].data_pointer);
+   writel((uint32_t)addr, >tbd_base[fec->tbd_index].data_pointer);
 
/*
 * update BD's status now
@@ -698,7 +703,7 @@ static int fec_send(struct eth_device *dev, void *packet, 
int length)
 * can start DMA.
 */
size = roundup(2 * sizeof(struct fec_bd), 

[U-Boot] [PATCH V4 25/32] imx: lcdif: include i.MX8M

[Peng Fan]

Include i.MX8M in lcdif register layout map.
Also included i.MX7ULP in this patch, since share same with i.MX8M.

Signed-off-by: Peng Fan 
Reviewed-by: Stefano Babic 
Reviewed-by: Fabio Estevam 
---
 arch/arm/include/asm/mach-imx/regs-lcdif.h | 10 ++
 1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/arch/arm/include/asm/mach-imx/regs-lcdif.h 
b/arch/arm/include/asm/mach-imx/regs-lcdif.h
index c6cf03bf5a..38a2c6d4ee 100644
--- a/arch/arm/include/asm/mach-imx/regs-lcdif.h
+++ b/arch/arm/include/asm/mach-imx/regs-lcdif.h
@@ -19,11 +19,11 @@
 struct mxs_lcdif_regs {
mxs_reg_32(hw_lcdif_ctrl)   /* 0x00 */
mxs_reg_32(hw_lcdif_ctrl1)  /* 0x10 */
-
 #if defined(CONFIG_MX28) || defined(CONFIG_MX6SX) || \
defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL) || \
defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || \
-   defined(CONFIG_MX7)
+   defined(CONFIG_MX7) || defined(CONFIG_MX7ULP) || \
+   defined(CONFIG_MX8M)
mxs_reg_32(hw_lcdif_ctrl2)  /* 0x20 */
 #endif
mxs_reg_32(hw_lcdif_transfer_count) /* 0x20/0x30 */
@@ -61,7 +61,8 @@ struct mxs_lcdif_regs {
 #if defined(CONFIG_MX28) || defined(CONFIG_MX6SX) || \
defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL) || \
defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || \
-   defined(CONFIG_MX7)
+   defined(CONFIG_MX7) || defined(CONFIG_MX7ULP) || \
+   defined(CONFIG_MX8M)
mxs_reg_32(hw_lcdif_crc_stat)   /* 0x1a0 */
 #endif
mxs_reg_32(hw_lcdif_lcdif_stat) /* 0x1d0/0x1b0 */
@@ -72,7 +73,8 @@ struct mxs_lcdif_regs {
 #if defined(CONFIG_MX6SX) || \
defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL) || \
defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || \
-   defined(CONFIG_MX7)
+   defined(CONFIG_MX7) || defined(CONFIG_MX7ULP) || \
+   defined(CONFIG_MX8M)
mxs_reg_32(hw_lcdif_thres)
mxs_reg_32(hw_lcdif_as_ctrl)
mxs_reg_32(hw_lcdif_as_buf)
-- 
2.14.1

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH V4 26/32] gpio: mxc: add i.MX8M support

[Peng Fan]

Add i.MX8M GPIO support.
There are 4 GPIO banks on i.MX8M.

Signed-off-by: Peng Fan 
Reviewed-by: Fabio Estevam 
Cc: Stefano Babic 
---
 drivers/gpio/mxc_gpio.c | 22 +++---
 1 file changed, 15 insertions(+), 7 deletions(-)

diff --git a/drivers/gpio/mxc_gpio.c b/drivers/gpio/mxc_gpio.c
index cfa620bceb..d0e365a54b 100644
--- a/drivers/gpio/mxc_gpio.c
+++ b/drivers/gpio/mxc_gpio.c
@@ -41,13 +41,13 @@ static unsigned long gpio_ports[] = {
[2] = GPIO3_BASE_ADDR,
 #if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX51) || \
defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
-   defined(CONFIG_MX7)
+   defined(CONFIG_MX7) || defined(CONFIG_MX8M)
[3] = GPIO4_BASE_ADDR,
 #endif
 #if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
-   defined(CONFIG_MX7)
+   defined(CONFIG_MX7) || defined(CONFIG_MX8M)
[4] = GPIO5_BASE_ADDR,
-#if !(defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL))
+#if !(defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || defined(CONFIG_MX8M))
[5] = GPIO6_BASE_ADDR,
 #endif
 #endif
@@ -349,13 +349,17 @@ static const struct mxc_gpio_plat mxc_plat[] = {
{ 1, (struct gpio_regs *)GPIO2_BASE_ADDR },
{ 2, (struct gpio_regs *)GPIO3_BASE_ADDR },
 #if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX51) || \
-   defined(CONFIG_MX53) || defined(CONFIG_MX6)
+   defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
+   defined(CONFIG_MX8M)
{ 3, (struct gpio_regs *)GPIO4_BASE_ADDR },
 #endif
-#if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6)
+#if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
+   defined(CONFIG_MX8M)
{ 4, (struct gpio_regs *)GPIO5_BASE_ADDR },
+#ifndef CONFIG_MX8M
{ 5, (struct gpio_regs *)GPIO6_BASE_ADDR },
 #endif
+#endif
 #if defined(CONFIG_MX53) || defined(CONFIG_MX6)
{ 6, (struct gpio_regs *)GPIO7_BASE_ADDR },
 #endif
@@ -366,13 +370,17 @@ U_BOOT_DEVICES(mxc_gpios) = {
{ "gpio_mxc", _plat[1] },
{ "gpio_mxc", _plat[2] },
 #if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX51) || \
-   defined(CONFIG_MX53) || defined(CONFIG_MX6)
+   defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
+   defined(CONFIG_MX8M)
{ "gpio_mxc", _plat[3] },
 #endif
-#if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6)
+#if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
+   defined(CONFIG_MX8M)
{ "gpio_mxc", _plat[4] },
+#ifndef CONFIG_MX8M
{ "gpio_mxc", _plat[5] },
 #endif
+#endif
 #if defined(CONFIG_MX53) || defined(CONFIG_MX6)
{ "gpio_mxc", _plat[6] },
 #endif
-- 
2.14.1

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH V4 17/32] imx: bootaux: support i.MX8M

[Peng Fan]

Add i.MX8M support. Because i.MX8M use SiP call trap
to Arm Trusted Firmware to handle M4, so use #ifdef
to avoid build error on i.MX6/7.

Signed-off-by: Peng Fan 
---
 arch/arm/mach-imx/imx_bootaux.c | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/arch/arm/mach-imx/imx_bootaux.c b/arch/arm/mach-imx/imx_bootaux.c
index 02728514b7..6256b3a778 100644
--- a/arch/arm/mach-imx/imx_bootaux.c
+++ b/arch/arm/mach-imx/imx_bootaux.c
@@ -6,7 +6,9 @@
 
 #include 
 #include 
+#include 
 #include 
+#include 
 #include 
 
 int arch_auxiliary_core_up(u32 core_id, ulong boot_private_data)
@@ -24,14 +26,21 @@ int arch_auxiliary_core_up(u32 core_id, ulong 
boot_private_data)
writel(pc, M4_BOOTROM_BASE_ADDR + 4);
 
/* Enable M4 */
+#ifdef CONFIG_MX8M
+   call_imx_sip(IMX_SIP_SRC, IMX_SIP_SRC_M4_START, 0, 0);
+#else
clrsetbits_le32(SRC_BASE_ADDR + SRC_M4_REG_OFFSET,
SRC_M4C_NON_SCLR_RST_MASK, SRC_M4_ENABLE_MASK);
+#endif
 
return 0;
 }
 
 int arch_auxiliary_core_check_up(u32 core_id)
 {
+#ifdef CONFIG_MX8M
+   return call_imx_sip(IMX_SIP_SRC, IMX_SIP_SRC_M4_STARTED, 0, 0);
+#else
unsigned int val;
 
val = readl(SRC_BASE_ADDR + SRC_M4_REG_OFFSET);
@@ -40,6 +49,7 @@ int arch_auxiliary_core_check_up(u32 core_id)
return 0;  /* assert in reset */
 
return 1;
+#endif
 }
 
 /*
-- 
2.14.1

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH V4 22/32] imx: makefile: compile files for i.MX8M

[Peng Fan]

Compile files for i.MX8M

Signed-off-by: Peng Fan 
Reviewed-by: Fabio Estevam 
Cc: Stefano Babic 
---
 arch/arm/mach-imx/Makefile | 13 +++--
 1 file changed, 11 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index 4c4e15c6e7..95a542fa01 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -7,15 +7,24 @@
 # SPDX-License-Identifier: GPL-2.0+
 #
 
-ifeq ($(SOC),$(filter $(SOC),mx25 mx35 mx5 mx6 mx7 vf610))
+ifeq ($(SOC),$(filter $(SOC),mx25 mx35 mx5 mx6 mx7 mx8m vf610))
 obj-y  = iomux-v3.o
 endif
+
+ifeq ($(SOC),$(filter $(SOC),mx8m))
+obj-$(CONFIG_IMX_BOOTAUX) += imx_bootaux.o
+obj-$(CONFIG_ENV_IS_IN_MMC) += mmc_env.o
+obj-$(CONFIG_FEC_MXC) += mac.o
+obj-$(CONFIG_SYS_I2C_MXC) += i2c-mxv7.o
+obj-y += cpu.o
+endif
+
 ifeq ($(SOC),$(filter $(SOC),mx5 mx6))
 obj-y  += cpu.o speed.o
 obj-$(CONFIG_GPT_TIMER) += timer.o
 obj-$(CONFIG_SYS_I2C_MXC) += i2c-mxv7.o
 endif
-ifeq ($(SOC),$(filter $(SOC),mx7 mx6 mxs))
+ifeq ($(SOC),$(filter $(SOC),mx7 mx6 mxs mx8m))
 obj-y  += misc.o
 obj-$(CONFIG_SPL_BUILD)+= spl.o
 endif
-- 
2.14.1

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH V4 30/32] power: pmic/regulator allow dm be omitted by SPL

[Peng Fan]

Allow the dm driver be omitted by SPL.

Signed-off-by: Peng Fan 
Reviewed-by: Simon Glass 
Cc: Jaehoon Chung 
Cc: Stefano Babic 
---
 drivers/power/pmic/Makefile  | 2 +-
 drivers/power/regulator/Makefile | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/power/pmic/Makefile b/drivers/power/pmic/Makefile
index 7d6c583d34..fc19fdc701 100644
--- a/drivers/power/pmic/Makefile
+++ b/drivers/power/pmic/Makefile
@@ -8,7 +8,7 @@
 obj-$(CONFIG_DM_PMIC) += pmic-uclass.o
 obj-$(CONFIG_DM_PMIC_MAX77686) += max77686.o
 obj-$(CONFIG_DM_PMIC_MAX8998) += max8998.o
-obj-$(CONFIG_DM_PMIC_PFUZE100) += pfuze100.o
+obj-$(CONFIG_$(SPL_)DM_PMIC_PFUZE100) += pfuze100.o
 obj-$(CONFIG_PMIC_S2MPS11) += s2mps11.o
 obj-$(CONFIG_DM_PMIC_SANDBOX) += sandbox.o i2c_pmic_emul.o
 obj-$(CONFIG_PMIC_ACT8846) += act8846.o
diff --git a/drivers/power/regulator/Makefile b/drivers/power/regulator/Makefile
index 7a2e76dc82..353177d5f4 100644
--- a/drivers/power/regulator/Makefile
+++ b/drivers/power/regulator/Makefile
@@ -9,7 +9,7 @@ obj-$(CONFIG_$(SPL_)DM_REGULATOR) += regulator-uclass.o
 obj-$(CONFIG_REGULATOR_ACT8846) += act8846.o
 obj-$(CONFIG_REGULATOR_AS3722) += as3722_regulator.o
 obj-$(CONFIG_DM_REGULATOR_MAX77686) += max77686.o
-obj-$(CONFIG_DM_REGULATOR_PFUZE100) += pfuze100.o
+obj-$(CONFIG_$(SPL_)DM_PMIC_PFUZE100) += pfuze100.o
 obj-$(CONFIG_REGULATOR_PWM) += pwm_regulator.o
 obj-$(CONFIG_$(SPL_)DM_REGULATOR_FIXED) += fixed.o
 obj-$(CONFIG_$(SPL_)DM_REGULATOR_GPIO) += gpio-regulator.o
-- 
2.14.1

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH V4 16/32] imx: cleanup bootaux

[Peng Fan]

Move i.MX6/7 bootaux code to imx_bootaux.c.
The i.MX6/7 has different src layout, so define M4 reg offset
to ease the cleanup. Redefine the M4 related BIT for share
common code.

Signed-off-by: Peng Fan 
Cc: Stefano Babic 
Cc: Fabio Estevam 
---
 arch/arm/include/asm/arch-mx6/imx-regs.h |  9 
 arch/arm/include/asm/arch-mx7/imx-regs.h | 10 +
 arch/arm/mach-imx/imx_bootaux.c  | 36 +++---
 arch/arm/mach-imx/mx6/soc.c  | 38 
 arch/arm/mach-imx/mx7/soc.c  | 36 --
 5 files changed, 39 insertions(+), 90 deletions(-)

diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h 
b/arch/arm/include/asm/arch-mx6/imx-regs.h
index 48ce0edd06..8513406a8e 100644
--- a/arch/arm/include/asm/arch-mx6/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
@@ -482,10 +482,11 @@ struct src {
 
 #define src_base ((struct src *)SRC_BASE_ADDR)
 
-#define SRC_SCR_M4_ENABLE_OFFSET22
-#define SRC_SCR_M4_ENABLE_MASK  (1 << 22)
-#define SRC_SCR_M4C_NON_SCLR_RST_OFFSET 4
-#define SRC_SCR_M4C_NON_SCLR_RST_MASK   (1 << 4)
+#define SRC_M4_REG_OFFSET  0
+#define SRC_M4_ENABLE_OFFSET   22
+#define SRC_M4_ENABLE_MASK BIT(22)
+#define SRC_M4C_NON_SCLR_RST_OFFSET4
+#define SRC_M4C_NON_SCLR_RST_MASK  BIT(4)
 
 /* GPR1 bitfields */
 #define IOMUXC_GPR1_APP_CLK_REQ_N  BIT(30)
diff --git a/arch/arm/include/asm/arch-mx7/imx-regs.h 
b/arch/arm/include/asm/arch-mx7/imx-regs.h
index f0693f9028..a421b9bc04 100644
--- a/arch/arm/include/asm/arch-mx7/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx7/imx-regs.h
@@ -264,10 +264,12 @@ struct src {
u32 ddrc_rcr;
 };
 
-#define SRC_M4RCR_M4C_NON_SCLR_RST_OFFSET  0
-#define SRC_M4RCR_M4C_NON_SCLR_RST_MASK(1 << 0)
-#define SRC_M4RCR_ENABLE_M4_OFFSET 3
-#define SRC_M4RCR_ENABLE_M4_MASK   (1 << 3)
+#define SRC_M4_REG_OFFSET  0xC
+#define SRC_M4C_NON_SCLR_RST_OFFSET0
+#define SRC_M4C_NON_SCLR_RST_MASK  BIT(0)
+#define SRC_M4_ENABLE_OFFSET   3
+#define SRC_M4_ENABLE_MASK BIT(3)
+
 #define SRC_DDRC_RCR_DDRC_CORE_RST_OFFSET  1
 #define SRC_DDRC_RCR_DDRC_CORE_RST_MASK(1 << 1)
 
diff --git a/arch/arm/mach-imx/imx_bootaux.c b/arch/arm/mach-imx/imx_bootaux.c
index b62dfbf6bf..02728514b7 100644
--- a/arch/arm/mach-imx/imx_bootaux.c
+++ b/arch/arm/mach-imx/imx_bootaux.c
@@ -5,21 +5,41 @@
  */
 
 #include 
+#include 
 #include 
 #include 
 
-/* Allow for arch specific config before we boot */
-int __weak arch_auxiliary_core_up(u32 core_id, u32 boot_private_data)
+int arch_auxiliary_core_up(u32 core_id, ulong boot_private_data)
 {
-   /* please define platform specific arch_auxiliary_core_up() */
-   return CMD_RET_FAILURE;
+   ulong stack, pc;
+
+   if (!boot_private_data)
+   return -EINVAL;
+
+   stack = *(ulong *)boot_private_data;
+   pc = *(ulong *)(boot_private_data + 4);
+
+   /* Set the stack and pc to M4 bootROM */
+   writel(stack, M4_BOOTROM_BASE_ADDR);
+   writel(pc, M4_BOOTROM_BASE_ADDR + 4);
+
+   /* Enable M4 */
+   clrsetbits_le32(SRC_BASE_ADDR + SRC_M4_REG_OFFSET,
+   SRC_M4C_NON_SCLR_RST_MASK, SRC_M4_ENABLE_MASK);
+
+   return 0;
 }
 
-/* Allow for arch specific config before we boot */
-int __weak arch_auxiliary_core_check_up(u32 core_id)
+int arch_auxiliary_core_check_up(u32 core_id)
 {
-   /* please define platform specific arch_auxiliary_core_check_up() */
-   return 0;
+   unsigned int val;
+
+   val = readl(SRC_BASE_ADDR + SRC_M4_REG_OFFSET);
+
+   if (val & SRC_M4C_NON_SCLR_RST_MASK)
+   return 0;  /* assert in reset */
+
+   return 1;
 }
 
 /*
diff --git a/arch/arm/mach-imx/mx6/soc.c b/arch/arm/mach-imx/mx6/soc.c
index b3bee58f10..9b3d8f69b2 100644
--- a/arch/arm/mach-imx/mx6/soc.c
+++ b/arch/arm/mach-imx/mx6/soc.c
@@ -666,41 +666,3 @@ void gpr_init(void)
writel(0x007F007F, >gpr[7]);
}
 }
-
-#ifdef CONFIG_IMX_BOOTAUX
-int arch_auxiliary_core_up(u32 core_id, u32 boot_private_data)
-{
-   struct src *src_reg;
-   u32 stack, pc;
-
-   if (!boot_private_data)
-   return -EINVAL;
-
-   stack = *(u32 *)boot_private_data;
-   pc = *(u32 *)(boot_private_data + 4);
-
-   /* Set the stack and pc to M4 bootROM */
-   writel(stack, M4_BOOTROM_BASE_ADDR);
-   writel(pc, M4_BOOTROM_BASE_ADDR + 4);
-
-   /* Enable M4 */
-   src_reg = (struct src *)SRC_BASE_ADDR;
-   clrsetbits_le32(_reg->scr, SRC_SCR_M4C_NON_SCLR_RST_MASK,
-   SRC_SCR_M4_ENABLE_MASK);
-
-   return 0;
-}
-
-int arch_auxiliary_core_check_up(u32 core_id)
-{
-   struct src *src_reg = (struct src *)SRC_BASE_ADDR;
-   unsigned val;
-
-  

[U-Boot] [PATCH V4 14/32] imx: cpu: add cpu speed/grade for i.MX8M

[Peng Fan]

Use more general enum types for speed grade.
Refine get_cpu_speed_grade_hz to support i.MX8M.

Signed-off-by: Peng Fan 
Cc: Stefano Babic 
Cc: Fabio Estevam 
---
 arch/arm/mach-imx/cpu.c | 27 +++
 1 file changed, 15 insertions(+), 12 deletions(-)

diff --git a/arch/arm/mach-imx/cpu.c b/arch/arm/mach-imx/cpu.c
index 52dbafb50c..fd6d08c533 100644
--- a/arch/arm/mach-imx/cpu.c
+++ b/arch/arm/mach-imx/cpu.c
@@ -333,16 +333,18 @@ void set_chipselect_size(int const cs_size)
 }
 #endif
 
-#if defined(CONFIG_MX7)
+#if defined(CONFIG_MX7) || defined(CONFIG_MX8M)
 /*
  * OCOTP_TESTER3[9:8] (see Fusemap Description Table offset 0x440)
  * defines a 2-bit SPEED_GRADING
  */
 #define OCOTP_TESTER3_SPEED_SHIFT  8
-#define OCOTP_TESTER3_SPEED_800MHZ 0
-#define OCOTP_TESTER3_SPEED_500MHZ 1
-#define OCOTP_TESTER3_SPEED_1GHZ   2
-#define OCOTP_TESTER3_SPEED_1P2GHZ 3
+enum cpu_speed {
+   OCOTP_TESTER3_SPEED_GRADE0,
+   OCOTP_TESTER3_SPEED_GRADE1,
+   OCOTP_TESTER3_SPEED_GRADE2,
+   OCOTP_TESTER3_SPEED_GRADE3,
+};
 
 u32 get_cpu_speed_grade_hz(void)
 {
@@ -357,15 +359,16 @@ u32 get_cpu_speed_grade_hz(void)
val &= 0x3;
 
switch(val) {
-   case OCOTP_TESTER3_SPEED_800MHZ:
+   case OCOTP_TESTER3_SPEED_GRADE0:
return 8;
-   case OCOTP_TESTER3_SPEED_500MHZ:
-   return 5;
-   case OCOTP_TESTER3_SPEED_1GHZ:
-   return 10;
-   case OCOTP_TESTER3_SPEED_1P2GHZ:
-   return 12;
+   case OCOTP_TESTER3_SPEED_GRADE1:
+   return is_mx7() ? 5 : 10;
+   case OCOTP_TESTER3_SPEED_GRADE2:
+   return is_mx7() ? 10 : 13;
+   case OCOTP_TESTER3_SPEED_GRADE3:
+   return is_mx7() ? 12 : 15;
}
+
return 0;
 }
 
-- 
2.14.1

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH V4 27/32] net: fec: do not access reserved register for i.MX8M

[Peng Fan]

The MIB RAM and FIFO receive start register does not exist on
i.MX8M. Accessing these register will cause system hang.

Signed-off-by: Peng Fan 
Acked-by: Joe Hershberger 
Reviewed-by: Stefano Babic 
Reviewed-by: Fabio Estevam 
---
 drivers/net/fec_mxc.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
index 433e19f0f8..4cbc8cbbfd 100644
--- a/drivers/net/fec_mxc.c
+++ b/drivers/net/fec_mxc.c
@@ -562,8 +562,8 @@ static int fec_init(struct eth_device *dev, bd_t *bd)
writel(0x, >eth->gaddr1);
writel(0x, >eth->gaddr2);
 
-   /* Do not access reserved register for i.MX6UL */
-   if (!is_mx6ul() && !is_mx6ull()) {
+   /* Do not access reserved register */
+   if (!is_mx6ul() && !is_mx6ull() && !is_mx8m()) {
/* clear MIB RAM */
for (i = mib_ptr; i <= mib_ptr + 0xfc; i += 4)
writel(0, i);
-- 
2.14.1

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH V4 29/32] imx: imx8mq: add dtsi file

[Peng Fan]

Add dtsi file for i.MX8MQ.

Signed-off-by: Peng Fan 
Reviewed-by: Fabio Estevam 
Cc: Stefano Babic 
---
 arch/arm/dts/fsl-imx8-ca53.dtsi   |  92 +
 arch/arm/dts/fsl-imx8mq.dtsi  | 429 
 include/dt-bindings/clock/imx8mq-clock.h  | 612 +
 include/dt-bindings/pinctrl/pins-imx8mq.h | 632 ++
 4 files changed, 1765 insertions(+)
 create mode 100644 arch/arm/dts/fsl-imx8-ca53.dtsi
 create mode 100644 arch/arm/dts/fsl-imx8mq.dtsi
 create mode 100644 include/dt-bindings/clock/imx8mq-clock.h
 create mode 100644 include/dt-bindings/pinctrl/pins-imx8mq.h

diff --git a/arch/arm/dts/fsl-imx8-ca53.dtsi b/arch/arm/dts/fsl-imx8-ca53.dtsi
new file mode 100644
index 00..6a2292a51e
--- /dev/null
+++ b/arch/arm/dts/fsl-imx8-ca53.dtsi
@@ -0,0 +1,92 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/{
+   cpus {
+   #address-cells = <2>;
+   #size-cells = <0>;
+
+   idle-states {
+   entry-method = "psci";
+
+   CPU_SLEEP: cpu-sleep {
+   compatible = "arm,idle-state";
+   local-timer-stop;
+   arm,psci-suspend-param = <0x000>;
+   entry-latency-us = <700>;
+   exit-latency-us = <250>;
+   min-residency-us = <1000>;
+   };
+
+   CLUSTER_SLEEP: cluster-sleep {
+   compatible = "arm,idle-state";
+   local-timer-stop;
+   arm,psci-suspend-param = <0x100>;
+   entry-latency-us = <1000>;
+   exit-latency-us = <700>;
+   min-residency-us = <2700>;
+   wakeup-latency-us = <1500>;
+   };
+   };
+
+   /* We have 1 clusters having 4 Cortex-A53 cores */
+   A53_0: cpu@0 {
+   device_type = "cpu";
+   compatible = "arm,cortex-a53";
+   reg = <0x0 0x0>;
+   enable-method = "psci";
+   next-level-cache = <_L2>;
+   cpu-idle-states = <_SLEEP>;
+   };
+
+   A53_1: cpu@1 {
+   device_type = "cpu";
+   compatible = "arm,cortex-a53";
+   reg = <0x0 0x1>;
+   enable-method = "psci";
+   next-level-cache = <_L2>;
+   cpu-idle-states = <_SLEEP>;
+   };
+
+   A53_2: cpu@2 {
+   device_type = "cpu";
+   compatible = "arm,cortex-a53";
+   reg = <0x0 0x2>;
+   enable-method = "psci";
+   next-level-cache = <_L2>;
+   cpu-idle-states = <_SLEEP>;
+   };
+
+   A53_3: cpu@3 {
+   device_type = "cpu";
+   compatible = "arm,cortex-a53";
+   reg = <0x0 0x3>;
+   enable-method = "psci";
+   next-level-cache = <_L2>;
+   cpu-idle-states = <_SLEEP>;
+   };
+
+   A53_L2: l2-cache0 {
+   compatible = "cache";
+   };
+   };
+
+   psci {
+   compatible = "arm,psci-1.0";
+   method = "smc";
+   cpu_suspend   = <0xc401>;
+   cpu_off   = <0xc402>;
+   cpu_on= <0xc403>;
+   };
+};
diff --git a/arch/arm/dts/fsl-imx8mq.dtsi b/arch/arm/dts/fsl-imx8mq.dtsi
new file mode 100644
index 00..814a1b7df4
--- /dev/null
+++ b/arch/arm/dts/fsl-imx8mq.dtsi
@@ -0,0 +1,429 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT 

[U-Boot] [PATCH V4 15/32] imx: refactor imx_get_mac_from_fuse

[Peng Fan]

Move imx_get_mac_from_fuse to a new mac.c for i.MX6/7.
Since fuse regs structure are different for i.MX6/7, use mac
address offset in code and define a new local struture
imx_mac_fuse.

Also sort the config order.

Signed-off-by: Peng Fan 
Cc: Stefano Babic 
Cc: Fabio Estevam 
---
 arch/arm/mach-imx/Makefile  |  3 ++-
 arch/arm/mach-imx/mac.c | 61 +
 arch/arm/mach-imx/mx6/soc.c | 34 -
 arch/arm/mach-imx/mx7/soc.c | 32 
 4 files changed, 63 insertions(+), 67 deletions(-)
 create mode 100644 arch/arm/mach-imx/mac.c

diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index 63db0e15c4..714b858e73 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -25,12 +25,13 @@ obj-$(CONFIG_SYS_I2C_MXC) += i2c-mxv7.o
 endif
 ifeq ($(SOC),$(filter $(SOC),mx6 mx7))
 obj-y  += cache.o init.o
-obj-$(CONFIG_SATA) += sata.o
+obj-$(CONFIG_FEC_MXC) += mac.o
 obj-$(CONFIG_IMX_VIDEO_SKIP) += video.o
 obj-$(CONFIG_IMX_RDC) += rdc-sema.o
 ifneq ($(CONFIG_SPL_BUILD),y)
 obj-$(CONFIG_IMX_BOOTAUX) += imx_bootaux.o
 endif
+obj-$(CONFIG_SATA) += sata.o
 obj-$(CONFIG_SECURE_BOOT)+= hab.o
 obj-$(CONFIG_SYSCOUNTER_TIMER) += syscounter.o
 endif
diff --git a/arch/arm/mach-imx/mac.c b/arch/arm/mach-imx/mac.c
new file mode 100644
index 00..dd7fd92d31
--- /dev/null
+++ b/arch/arm/mach-imx/mac.c
@@ -0,0 +1,61 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * Peng Fan 
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+struct imx_mac_fuse {
+   u32 mac_addr0;
+   u32 rsvd0[3];
+   u32 mac_addr1;
+   u32 rsvd1[3];
+   u32 mac_addr2;
+   u32 rsvd2[7];
+};
+
+#define MAC_FUSE_MX6_OFFSET0x620
+#define MAC_FUSE_MX7_OFFSET0x640
+
+void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
+{
+   struct imx_mac_fuse *fuse;
+   u32 offset;
+   bool has_second_mac;
+
+   offset = is_mx6() ? MAC_FUSE_MX6_OFFSET : MAC_FUSE_MX7_OFFSET;
+   fuse = (struct imx_mac_fuse *)(ulong)(OCOTP_BASE_ADDR + offset);
+   has_second_mac = is_mx7() || is_mx6sx() || is_mx6ul() || is_mx6ull();
+
+   if (has_second_mac && dev_id == 1) {
+   u32 value = readl(>mac_addr2);
+
+   mac[0] = value >> 24;
+   mac[1] = value >> 16;
+   mac[2] = value >> 8;
+   mac[3] = value;
+
+   value = readl(>mac_addr1);
+   mac[4] = value >> 24;
+   mac[5] = value >> 16;
+
+   } else {
+   u32 value = readl(>mac_addr1);
+
+   mac[0] = value >> 8;
+   mac[1] = value;
+
+   value = readl(>mac_addr0);
+   mac[2] = value >> 24;
+   mac[3] = value >> 16;
+   mac[4] = value >> 8;
+   mac[5] = value;
+   }
+}
diff --git a/arch/arm/mach-imx/mx6/soc.c b/arch/arm/mach-imx/mx6/soc.c
index 43cb58106b..b3bee58f10 100644
--- a/arch/arm/mach-imx/mx6/soc.c
+++ b/arch/arm/mach-imx/mx6/soc.c
@@ -518,40 +518,6 @@ int board_postclk_init(void)
return 0;
 }
 
-#if defined(CONFIG_FEC_MXC)
-void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
-{
-   struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
-   struct fuse_bank *bank = >bank[4];
-   struct fuse_bank4_regs *fuse =
-   (struct fuse_bank4_regs *)bank->fuse_regs;
-
-   if ((is_mx6sx() || is_mx6ul() || is_mx6ull()) && dev_id == 1) {
-   u32 value = readl(>mac_addr2);
-   mac[0] = value >> 24 ;
-   mac[1] = value >> 16 ;
-   mac[2] = value >> 8 ;
-   mac[3] = value ;
-
-   value = readl(>mac_addr1);
-   mac[4] = value >> 24 ;
-   mac[5] = value >> 16 ;
-   
-   } else {
-   u32 value = readl(>mac_addr1);
-   mac[0] = (value >> 8);
-   mac[1] = value ;
-
-   value = readl(>mac_addr0);
-   mac[2] = value >> 24 ;
-   mac[3] = value >> 16 ;
-   mac[4] = value >> 8 ;
-   mac[5] = value ;
-   }
-
-}
-#endif
-
 #ifndef CONFIG_SPL_BUILD
 /*
  * cfg_val will be used for
diff --git a/arch/arm/mach-imx/mx7/soc.c b/arch/arm/mach-imx/mx7/soc.c
index 032dfcf2ce..10dec8bdf4 100644
--- a/arch/arm/mach-imx/mx7/soc.c
+++ b/arch/arm/mach-imx/mx7/soc.c
@@ -208,38 +208,6 @@ void get_board_serial(struct tag_serialnr *serialnr)
 }
 #endif
 
-#if defined(CONFIG_FEC_MXC)
-void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
-{
-   struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
-   struct fuse_bank *bank = >bank[9];
-   struct fuse_bank9_regs *fuse =
-   (struct fuse_bank9_regs *)bank->fuse_regs;
-
-   if (0 == dev_id) {
-   u32 value = 

[U-Boot] [PATCH V4 21/32] imx: mx8m: add soc related settings and files

[Peng Fan]

Add SoC level initialization code
 - arch_cpu_init
 - mmu table
 - detect cpu revision
 - reset cpu and wdog settings
 - timer init
 - wdog settings
 - lowlevel init to save/restore registers
 - a few dummy header file to avoid build failure
 - ft_system_setup

Signed-off-by: Peng Fan 
Cc: Stefano Babic 
Cc: Fabio Estevam 
---
 arch/arm/include/asm/arch-mx8m/crm_regs.h  |  10 ++
 arch/arm/include/asm/arch-mx8m/gpio.h  |  12 ++
 arch/arm/include/asm/arch-mx8m/sys_proto.h |  18 +++
 arch/arm/mach-imx/Makefile |   2 +-
 arch/arm/mach-imx/mx8m/Makefile|   3 +-
 arch/arm/mach-imx/mx8m/lowlevel_init.S |  63 
 arch/arm/mach-imx/mx8m/soc.c   | 227 +
 7 files changed, 333 insertions(+), 2 deletions(-)
 create mode 100644 arch/arm/include/asm/arch-mx8m/crm_regs.h
 create mode 100644 arch/arm/include/asm/arch-mx8m/gpio.h
 create mode 100644 arch/arm/include/asm/arch-mx8m/sys_proto.h
 create mode 100644 arch/arm/mach-imx/mx8m/lowlevel_init.S
 create mode 100644 arch/arm/mach-imx/mx8m/soc.c

diff --git a/arch/arm/include/asm/arch-mx8m/crm_regs.h 
b/arch/arm/include/asm/arch-mx8m/crm_regs.h
new file mode 100644
index 00..6582318983
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx8m/crm_regs.h
@@ -0,0 +1,10 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef _ASM_ARCH_MX8M_CRM_REGS_H
+#define _ASM_ARCH_MX8M_CRM_REGS_H
+/* Dummy header, some imx-common code needs this file */
+#endif
diff --git a/arch/arm/include/asm/arch-mx8m/gpio.h 
b/arch/arm/include/asm/arch-mx8m/gpio.h
new file mode 100644
index 00..b666d37700
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx8m/gpio.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_MX8M_GPIO_H
+#define __ASM_ARCH_MX8M_GPIO_H
+
+#include 
+
+#endif
diff --git a/arch/arm/include/asm/arch-mx8m/sys_proto.h 
b/arch/arm/include/asm/arch-mx8m/sys_proto.h
new file mode 100644
index 00..8bf9ac6697
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx8m/sys_proto.h
@@ -0,0 +1,18 @@
+/*
+ * Copyright (C) 2017 NXP
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef __ARCH_MX8M_SYS_PROTO_H
+#define __ARCH_MX8M_SYS_PROTO_H
+
+#include 
+
+void set_wdog_reset(struct wdog_regs *wdog);
+void enable_tzc380(void);
+void restore_boot_params(void);
+extern unsigned long rom_pointer[];
+enum boot_device get_boot_device(void);
+bool is_usb_boot(void);
+#endif
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index e38b560d51..4c4e15c6e7 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -132,4 +132,4 @@ obj-$(CONFIG_MX5) += mx5/
 obj-$(CONFIG_MX6) += mx6/
 obj-$(CONFIG_MX7) += mx7/
 obj-$(CONFIG_ARCH_MX7ULP) += mx7ulp/
-
+obj-$(CONFIG_MX8M) += mx8m/
diff --git a/arch/arm/mach-imx/mx8m/Makefile b/arch/arm/mach-imx/mx8m/Makefile
index 05f38842f0..b1c5d74aab 100644
--- a/arch/arm/mach-imx/mx8m/Makefile
+++ b/arch/arm/mach-imx/mx8m/Makefile
@@ -4,4 +4,5 @@
 # SPDX-License-Identifier: GPL-2.0+
 #
 
-obj-y += clock.o clock_slice.o
+obj-y += lowlevel_init.o
+obj-y += clock.o clock_slice.o soc.o
diff --git a/arch/arm/mach-imx/mx8m/lowlevel_init.S 
b/arch/arm/mach-imx/mx8m/lowlevel_init.S
new file mode 100644
index 00..d388f3ba95
--- /dev/null
+++ b/arch/arm/mach-imx/mx8m/lowlevel_init.S
@@ -0,0 +1,63 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+
+.align 8
+.global rom_pointer
+rom_pointer:
+   .space 256
+
+/*
+ * Routine: save_boot_params (called after reset from start.S)
+ */
+
+.global save_boot_params
+save_boot_params:
+   /* The firmware provided ATAG/FDT address can be found in r2/x0 */
+   adr x0, rom_pointer
+   stp x1, x2, [x0], #16
+   stp x3, x4, [x0], #16
+   stp x5, x6, [x0], #16
+   stp x7, x8, [x0], #16
+   stp x9, x10, [x0], #16
+   stp x11, x12, [x0], #16
+   stp x13, x14, [x0], #16
+   stp x15, x16, [x0], #16
+   stp x17, x18, [x0], #16
+   stp x19, x20, [x0], #16
+   stp x21, x22, [x0], #16
+   stp x23, x24, [x0], #16
+   stp x25, x26, [x0], #16
+   stp x27, x28, [x0], #16
+   stp x29, x30, [x0], #16
+   mov x30, sp
+   str x30, [x0], #8
+
+   /* Returns */
+   b   save_boot_params_ret
+
+.global restore_boot_params
+restore_boot_params:
+   adr x0, rom_pointer
+   ldp x1, x2, [x0], #16
+   ldp x3, x4, [x0], #16
+   ldp x5, x6, [x0], #16
+   ldp x7, x8, [x0], #16
+   ldp x9, x10, [x0], #16
+   ldp x11, x12, [x0], #16
+   ldp x13, x14, [x0], #16
+   ldp x15, x16, [x0], #16
+   ldp x17, x18, [x0], #16
+   ldp x19, x20, [x0], #16
+   ldp x21, x22, [x0], #16
+   ldp 

[U-Boot] [PATCH V4 24/32] mmc: fsl_esdhc: support i.MX8M

[Peng Fan]

Support i.MX8M in fsl esdhc driver.

Signed-off-by: Peng Fan 
Reviewed-by: Stefano Babic 
Reviewed-by: Fabio Estevam 
---
 drivers/mmc/fsl_esdhc.c | 12 
 1 file changed, 8 insertions(+), 4 deletions(-)

diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index 499d622c6d..3a56f7c2bc 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -228,7 +228,8 @@ static int esdhc_setup_data(struct fsl_esdhc_priv *priv, 
struct mmc *mmc,
 {
int timeout;
struct fsl_esdhc *regs = priv->esdhc_regs;
-#if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234)
+#if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \
+   defined(CONFIG_MX8M)
dma_addr_t addr;
 #endif
uint wml_value;
@@ -241,7 +242,8 @@ static int esdhc_setup_data(struct fsl_esdhc_priv *priv, 
struct mmc *mmc,
 
esdhc_clrsetbits32(>wml, WML_RD_WML_MASK, wml_value);
 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
-#if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234)
+#if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \
+   defined(CONFIG_MX8M)
addr = virt_to_phys((void *)(data->dest));
if (upper_32_bits(addr))
printf("Error found for upper 32 bits\n");
@@ -270,7 +272,8 @@ static int esdhc_setup_data(struct fsl_esdhc_priv *priv, 
struct mmc *mmc,
esdhc_clrsetbits32(>wml, WML_WR_WML_MASK,
wml_value << 16);
 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
-#if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234)
+#if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \
+   defined(CONFIG_MX8M)
addr = virt_to_phys((void *)(data->src));
if (upper_32_bits(addr))
printf("Error found for upper 32 bits\n");
@@ -335,7 +338,8 @@ static void check_and_invalidate_dcache_range
unsigned end = 0;
unsigned size = roundup(ARCH_DMA_MINALIGN,
data->blocks*data->blocksize);
-#if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234)
+#if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \
+   defined(CONFIG_MX8M)
dma_addr_t addr;
 
addr = virt_to_phys((void *)(data->dest));
-- 
2.14.1

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH V4 12/32] imx: add pad settings bit definition for i.MX8M

[Peng Fan]

Add pad settings bit definition for i.MX8M.

Signed-off-by: Peng Fan 
Reviewed-by: Fabio Estevam 
Cc: Stefano Babic 
---
 arch/arm/include/asm/mach-imx/iomux-v3.h | 22 +-
 1 file changed, 21 insertions(+), 1 deletion(-)

diff --git a/arch/arm/include/asm/mach-imx/iomux-v3.h 
b/arch/arm/include/asm/mach-imx/iomux-v3.h
index ed75e9cd9a..800d4cfb50 100644
--- a/arch/arm/include/asm/mach-imx/iomux-v3.h
+++ b/arch/arm/include/asm/mach-imx/iomux-v3.h
@@ -87,7 +87,27 @@ typedef u64 iomux_v3_cfg_t;
 #define IOMUX_CONFIG_LPSR   0x20
 #define MUX_MODE_LPSR   ((iomux_v3_cfg_t)IOMUX_CONFIG_LPSR << \
MUX_MODE_SHIFT)
-#ifdef CONFIG_MX7
+#ifdef CONFIG_MX8M
+#define PAD_CTL_DSE0   (0x0 << 0)
+#define PAD_CTL_DSE1   (0x1 << 0)
+#define PAD_CTL_DSE2   (0x2 << 0)
+#define PAD_CTL_DSE3   (0x3 << 0)
+#define PAD_CTL_DSE4   (0x4 << 0)
+#define PAD_CTL_DSE5   (0x5 << 0)
+#define PAD_CTL_DSE6   (0x6 << 0)
+#define PAD_CTL_DSE7   (0x7 << 0)
+
+#define PAD_CTL_FSEL0  (0x0 << 3)
+#define PAD_CTL_FSEL1  (0x1 << 3)
+#define PAD_CTL_FSEL2  (0x2 << 3)
+#define PAD_CTL_FSEL3  (0x3 << 3)
+
+#define PAD_CTL_ODE(0x1 << 5)
+#define PAD_CTL_PUE(0x1 << 6)
+#define PAD_CTL_HYS(0x1 << 7)
+#define PAD_CTL_LVTTL  (0x1 << 8)
+
+#elif defined CONFIG_MX7
 
 #define IOMUX_LPSR_SEL_INPUT_OFS 0x7
 
-- 
2.14.1

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH V4 20/32] imx: mx7: move mmc env code to mmc_env.c

[Peng Fan]

The mx7 mmc env code is shared by i.MX8M, so move it to mmc_env.c.

Signed-off-by: Peng Fan 
---
 arch/arm/mach-imx/Makefile  |  1 +
 arch/arm/mach-imx/mmc_env.c | 30 ++
 arch/arm/mach-imx/mx7/soc.c | 21 -
 3 files changed, 31 insertions(+), 21 deletions(-)
 create mode 100644 arch/arm/mach-imx/mmc_env.c

diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index 714b858e73..e38b560d51 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -22,6 +22,7 @@ endif
 ifeq ($(SOC),$(filter $(SOC),mx7))
 obj-y  += cpu.o
 obj-$(CONFIG_SYS_I2C_MXC) += i2c-mxv7.o
+obj-$(CONFIG_ENV_IS_IN_MMC) += mmc_env.o
 endif
 ifeq ($(SOC),$(filter $(SOC),mx6 mx7))
 obj-y  += cache.o init.o
diff --git a/arch/arm/mach-imx/mmc_env.c b/arch/arm/mach-imx/mmc_env.c
new file mode 100644
index 00..ccadd2c1e0
--- /dev/null
+++ b/arch/arm/mach-imx/mmc_env.c
@@ -0,0 +1,30 @@
+/*
+ * Copyright (C) 2017 NXP
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+__weak int board_mmc_get_env_dev(int devno)
+{
+   return CONFIG_SYS_MMC_ENV_DEV;
+}
+
+int mmc_get_env_dev(void)
+{
+   struct bootrom_sw_info **p =
+   (struct bootrom_sw_info **)(ulong)ROM_SW_INFO_ADDR;
+   int devno = (*p)->boot_dev_instance;
+   u8 boot_type = (*p)->boot_dev_type;
+
+   /* If not boot from sd/mmc, use default value */
+   if ((boot_type != BOOT_TYPE_SD) && (boot_type != BOOT_TYPE_MMC))
+   return CONFIG_SYS_MMC_ENV_DEV;
+
+   return board_mmc_get_env_dev(devno);
+}
diff --git a/arch/arm/mach-imx/mx7/soc.c b/arch/arm/mach-imx/mx7/soc.c
index 62bd3a0e5f..172be2ccc0 100644
--- a/arch/arm/mach-imx/mx7/soc.c
+++ b/arch/arm/mach-imx/mx7/soc.c
@@ -250,27 +250,6 @@ const struct boot_mode soc_boot_modes[] = {
{NULL,  0},
 };
 
-#ifdef CONFIG_ENV_IS_IN_MMC
-__weak int board_mmc_get_env_dev(int devno)
-{
-   return CONFIG_SYS_MMC_ENV_DEV;
-}
-
-int mmc_get_env_dev(void)
-{
-   struct bootrom_sw_info **p =
-   (struct bootrom_sw_info **)ROM_SW_INFO_ADDR;
-   int devno = (*p)->boot_dev_instance;
-   u8 boot_type = (*p)->boot_dev_type;
-
-   /* If not boot from sd/mmc, use default value */
-   if ((boot_type != BOOT_TYPE_SD) && (boot_type != BOOT_TYPE_MMC))
-   return CONFIG_SYS_MMC_ENV_DEV;
-
-   return board_mmc_get_env_dev(devno);
-}
-#endif
-
 void s_init(void)
 {
 #if !defined CONFIG_SPL_BUILD
-- 
2.14.1

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH V4 31/32] imx: mx8m: add ddr controller memory map

[Peng Fan]

Add ddrc memory map and enum types used in ddr initialization.

Signed-off-by: Peng Fan 
Cc: Fabio Estevam 
Cc: Stefano Babic 
---
 arch/arm/include/asm/arch-mx8m/ddr.h | 356 +++
 1 file changed, 356 insertions(+)
 create mode 100644 arch/arm/include/asm/arch-mx8m/ddr.h

diff --git a/arch/arm/include/asm/arch-mx8m/ddr.h 
b/arch/arm/include/asm/arch-mx8m/ddr.h
new file mode 100644
index 00..b37382eab0
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx8m/ddr.h
@@ -0,0 +1,356 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_MX8M_DDR_H
+#define __ASM_ARCH_MX8M_DDR_H
+
+#define DDRC_DDR_SS_GPR0   0x3d00
+#define DDRC_IPS_BASE_ADDR_0   0x3f40
+#define IP2APB_DDRPHY_IPS_BASE_ADDR(X) (0x3c00 + (X * 0x200))
+#define DDRPHY_MEM(X)  (0x3c00 + (X * 0x200) + 0x5)
+
+struct ddrc_freq {
+   u32 res0[8];
+   u32 derateen;
+   u32 derateint;
+   u32 res1[10];
+   u32 rfshctl0;
+   u32 res2[4];
+   u32 rfshtmg;
+   u32 rfshtmg1;
+   u32 res3[28];
+   u32 init3;
+   u32 init4;
+   u32 res;
+   u32 init6;
+   u32 init7;
+   u32 res4[4];
+   u32 dramtmg0;
+   u32 dramtmg1;
+   u32 dramtmg2;
+   u32 dramtmg3;
+   u32 dramtmg4;
+   u32 dramtmg5;
+   u32 dramtmg6;
+   u32 dramtmg7;
+   u32 dramtmg8;
+   u32 dramtmg9;
+   u32 dramtmg10;
+   u32 dramtmg11;
+   u32 dramtmg12;
+   u32 dramtmg13;
+   u32 dramtmg14;
+   u32 dramtmg15;
+   u32 dramtmg16;
+   u32 dramtmg17;
+   u32 res5[10];
+   u32 mramtmg0;
+   u32 mramtmg1;
+   u32 mramtmg4;
+   u32 mramtmg9;
+   u32 zqctl0;
+   u32 res6[3];
+   u32 dfitmg0;
+   u32 dfitmg1;
+   u32 res7[7];
+   u32 dfitmg2;
+   u32 dfitmg3;
+   u32 res8[33];
+   u32 odtcfg;
+};
+
+struct imx8m_ddrc_regs {
+   u32 mstr;
+   u32 stat;
+   u32 mstr1;
+   u32 res1;
+   u32 mrctrl0;
+   u32 mrctrl1;
+   u32 mrstat;
+   u32 mrctrl2;
+   u32 derateen;
+   u32 derateint;
+   u32 mstr2;
+   u32 res2;
+   u32 pwrctl;
+   u32 pwrtmg;
+   u32 hwlpctl;
+   u32 hwffcctl;
+   u32 hwffcstat;
+   u32 res3[3];
+   u32 rfshctl0;
+   u32 rfshctl1;
+   u32 rfshctl2;
+   u32 rfshctl4;
+   u32 rfshctl3;
+   u32 rfshtmg;
+   u32 rfshtmg1;
+   u32 res4;
+   u32 ecccfg0;
+   u32 ecccfg1;
+   u32 eccstat;
+   u32 eccclr;
+   u32 eccerrcnt;
+   u32 ecccaddr0;
+   u32 ecccaddr1;
+   u32 ecccsyn0;
+   u32 ecccsyn1;
+   u32 ecccsyn2;
+   u32 eccbitmask0;
+   u32 eccbitmask1;
+   u32 eccbitmask2;
+   u32 eccuaddr0;
+   u32 eccuaddr1;
+   u32 eccusyn0;
+   u32 eccusyn1;
+   u32 eccusyn2;
+   u32 eccpoisonaddr0;
+   u32 eccpoisonaddr1;
+   u32 crcparctl0;
+   u32 crcparctl1;
+   u32 crcparctl2;
+   u32 crcparstat;
+   u32 init0;
+   u32 init1;
+   u32 init2;
+   u32 init3;
+   u32 init4;
+   u32 init5;
+   u32 init6;
+   u32 init7;
+   u32 dimmctl;
+   u32 rankctl;
+   u32 res5;
+   u32 chctl;
+   u32 dramtmg0;
+   u32 dramtmg1;
+   u32 dramtmg2;
+   u32 dramtmg3;
+   u32 dramtmg4;
+   u32 dramtmg5;
+   u32 dramtmg6;
+   u32 dramtmg7;
+   u32 dramtmg8;
+   u32 dramtmg9;
+   u32 dramtmg10;
+   u32 dramtmg11;
+   u32 dramtmg12;
+   u32 dramtmg13;
+   u32 dramtmg14;
+   u32 dramtmg15;
+   u32 dramtmg16;
+   u32 dramtmg17;
+   u32 res6[10];
+   u32 mramtmg0;
+   u32 mramtmg1;
+   u32 mramtmg4;
+   u32 mramtmg9;
+   u32 zqctl0;
+   u32 zqctl1;
+   u32 zqctl2;
+   u32 zqstat;
+   u32 dfitmg0;
+   u32 dfitmg1;
+   u32 dfilpcfg0;
+   u32 dfilpcfg1;
+   u32 dfiupd0;
+   u32 dfiupd1;
+   u32 dfiupd2;
+   u32 res7;
+   u32 dfimisc;
+   u32 dfitmg2;
+   u32 dfitmg3;
+   u32 dfistat;
+   u32 dbictl;
+   u32 dfiphymstr;
+   u32 res8[14];
+   u32 addrmap0;
+   u32 addrmap1;
+   u32 addrmap2;
+   u32 addrmap3;
+   u32 addrmap4;
+   u32 addrmap5;
+   u32 addrmap6;
+   u32 addrmap7;
+   u32 addrmap8;
+   u32 addrmap9;
+   u32 addrmap10;
+   u32 addrmap11;
+   u32 res9[4];
+   u32 odtcfg;
+   u32 odtmap;
+   u32 res10[2];
+   u32 sched;
+   u32 sched1;
+   u32 sched2;
+   u32 perfhpr1;
+   u32 res11;
+   u32 perflpr1;
+   u32 res12;
+   u32 perfwr1;
+   u32 res13[4];
+   u32 dqmap0;
+   u32 dqmap1;
+   u32 dqmap2;
+   u32 dqmap3;
+   u32 dqmap4;
+   u32 dqmap5;
+   u32 res14[26];
+   u32 dbg0;
+   u32 dbg1;
+   

[U-Boot] [PATCH V4 13/32] imx: cpu: move speed/temp to common cpu

[Peng Fan]

The i.MX7 cpu speed/temp code could be reused on i.MX8M,
so move them to common cpu code.

Signed-off-by: Peng Fan 
Cc: Stefano Babic 
Cc: Fabio Estevam 
---
 arch/arm/mach-imx/cpu.c | 73 +
 arch/arm/mach-imx/mx7/soc.c | 71 ---
 2 files changed, 73 insertions(+), 71 deletions(-)

diff --git a/arch/arm/mach-imx/cpu.c b/arch/arm/mach-imx/cpu.c
index fae8b0a419..52dbafb50c 100644
--- a/arch/arm/mach-imx/cpu.c
+++ b/arch/arm/mach-imx/cpu.c
@@ -333,6 +333,79 @@ void set_chipselect_size(int const cs_size)
 }
 #endif
 
+#if defined(CONFIG_MX7)
+/*
+ * OCOTP_TESTER3[9:8] (see Fusemap Description Table offset 0x440)
+ * defines a 2-bit SPEED_GRADING
+ */
+#define OCOTP_TESTER3_SPEED_SHIFT  8
+#define OCOTP_TESTER3_SPEED_800MHZ 0
+#define OCOTP_TESTER3_SPEED_500MHZ 1
+#define OCOTP_TESTER3_SPEED_1GHZ   2
+#define OCOTP_TESTER3_SPEED_1P2GHZ 3
+
+u32 get_cpu_speed_grade_hz(void)
+{
+   struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
+   struct fuse_bank *bank = >bank[1];
+   struct fuse_bank1_regs *fuse =
+   (struct fuse_bank1_regs *)bank->fuse_regs;
+   uint32_t val;
+
+   val = readl(>tester3);
+   val >>= OCOTP_TESTER3_SPEED_SHIFT;
+   val &= 0x3;
+
+   switch(val) {
+   case OCOTP_TESTER3_SPEED_800MHZ:
+   return 8;
+   case OCOTP_TESTER3_SPEED_500MHZ:
+   return 5;
+   case OCOTP_TESTER3_SPEED_1GHZ:
+   return 10;
+   case OCOTP_TESTER3_SPEED_1P2GHZ:
+   return 12;
+   }
+   return 0;
+}
+
+/*
+ * OCOTP_TESTER3[7:6] (see Fusemap Description Table offset 0x440)
+ * defines a 2-bit SPEED_GRADING
+ */
+#define OCOTP_TESTER3_TEMP_SHIFT   6
+
+u32 get_cpu_temp_grade(int *minc, int *maxc)
+{
+   struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
+   struct fuse_bank *bank = >bank[1];
+   struct fuse_bank1_regs *fuse =
+   (struct fuse_bank1_regs *)bank->fuse_regs;
+   uint32_t val;
+
+   val = readl(>tester3);
+   val >>= OCOTP_TESTER3_TEMP_SHIFT;
+   val &= 0x3;
+
+   if (minc && maxc) {
+   if (val == TEMP_AUTOMOTIVE) {
+   *minc = -40;
+   *maxc = 125;
+   } else if (val == TEMP_INDUSTRIAL) {
+   *minc = -40;
+   *maxc = 105;
+   } else if (val == TEMP_EXTCOMMERCIAL) {
+   *minc = -20;
+   *maxc = 105;
+   } else {
+   *minc = 0;
+   *maxc = 95;
+   }
+   }
+   return val;
+}
+#endif
+
 #ifdef CONFIG_NXP_BOARD_REVISION
 int nxp_board_rev(void)
 {
diff --git a/arch/arm/mach-imx/mx7/soc.c b/arch/arm/mach-imx/mx7/soc.c
index d160e80146..032dfcf2ce 100644
--- a/arch/arm/mach-imx/mx7/soc.c
+++ b/arch/arm/mach-imx/mx7/soc.c
@@ -97,77 +97,6 @@ struct imx_sec_config_fuse_t const imx_sec_config_fuse = {
 };
 #endif
 
-/*
- * OCOTP_TESTER3[9:8] (see Fusemap Description Table offset 0x440)
- * defines a 2-bit SPEED_GRADING
- */
-#define OCOTP_TESTER3_SPEED_SHIFT  8
-#define OCOTP_TESTER3_SPEED_800MHZ 0
-#define OCOTP_TESTER3_SPEED_500MHZ 1
-#define OCOTP_TESTER3_SPEED_1GHZ   2
-#define OCOTP_TESTER3_SPEED_1P2GHZ 3
-
-u32 get_cpu_speed_grade_hz(void)
-{
-   struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
-   struct fuse_bank *bank = >bank[1];
-   struct fuse_bank1_regs *fuse =
-   (struct fuse_bank1_regs *)bank->fuse_regs;
-   uint32_t val;
-
-   val = readl(>tester3);
-   val >>= OCOTP_TESTER3_SPEED_SHIFT;
-   val &= 0x3;
-
-   switch(val) {
-   case OCOTP_TESTER3_SPEED_800MHZ:
-   return 8;
-   case OCOTP_TESTER3_SPEED_500MHZ:
-   return 5;
-   case OCOTP_TESTER3_SPEED_1GHZ:
-   return 10;
-   case OCOTP_TESTER3_SPEED_1P2GHZ:
-   return 12;
-   }
-   return 0;
-}
-
-/*
- * OCOTP_TESTER3[7:6] (see Fusemap Description Table offset 0x440)
- * defines a 2-bit SPEED_GRADING
- */
-#define OCOTP_TESTER3_TEMP_SHIFT   6
-
-u32 get_cpu_temp_grade(int *minc, int *maxc)
-{
-   struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
-   struct fuse_bank *bank = >bank[1];
-   struct fuse_bank1_regs *fuse =
-   (struct fuse_bank1_regs *)bank->fuse_regs;
-   uint32_t val;
-
-   val = readl(>tester3);
-   val >>= OCOTP_TESTER3_TEMP_SHIFT;
-   val &= 0x3;
-
-   if (minc && maxc) {
-   if (val == TEMP_AUTOMOTIVE) {
-   *minc = -40;
-   *maxc = 125;
-   } else if (val == TEMP_INDUSTRIAL) {
-   *minc = -40;
- 

[U-Boot] [PATCH V4 18/32] imx: mx7: move get_boot_device to cpu.c

[Peng Fan]

Move get_boot_device to cpu.c to prepare adding i.MX8M support,
because i.MX8M share same code with i.MX7.

Signed-off-by: Peng Fan 
Cc: Stefano Babic 
Cc: Fabio Estevam 
---
 arch/arm/include/asm/arch-mx7/imx-regs.h  |  8 ---
 arch/arm/include/asm/mach-imx/boot_mode.h |  9 
 arch/arm/mach-imx/cpu.c   | 38 +++
 arch/arm/mach-imx/mx7/soc.c   | 35 
 4 files changed, 47 insertions(+), 43 deletions(-)

diff --git a/arch/arm/include/asm/arch-mx7/imx-regs.h 
b/arch/arm/include/asm/arch-mx7/imx-regs.h
index a421b9bc04..3726f02af5 100644
--- a/arch/arm/include/asm/arch-mx7/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx7/imx-regs.h
@@ -1210,14 +1210,6 @@ extern void pcie_power_off(void);
readl(USBOTG2_IPS_BASE_ADDR + 0x158))
 #definedisconnect_from_pc(void) writel(0x0, USBOTG1_IPS_BASE_ADDR + 
0x140)
 
-/* Boot device type */
-#define BOOT_TYPE_SD   0x1
-#define BOOT_TYPE_MMC  0x2
-#define BOOT_TYPE_NAND 0x3
-#define BOOT_TYPE_QSPI 0x4
-#define BOOT_TYPE_WEIM 0x5
-#define BOOT_TYPE_SPINOR   0x6
-
 struct bootrom_sw_info {
u8 reserved_1;
u8 boot_dev_instance;
diff --git a/arch/arm/include/asm/mach-imx/boot_mode.h 
b/arch/arm/include/asm/mach-imx/boot_mode.h
index e3ed046b25..300868a45e 100644
--- a/arch/arm/include/asm/mach-imx/boot_mode.h
+++ b/arch/arm/include/asm/mach-imx/boot_mode.h
@@ -31,6 +31,15 @@ enum boot_device {
BOOT_DEV_NUM = UNKNOWN_BOOT,
 };
 
+/* Boot device type */
+#define BOOT_TYPE_SD   0x1
+#define BOOT_TYPE_MMC  0x2
+#define BOOT_TYPE_NAND 0x3
+#define BOOT_TYPE_QSPI 0x4
+#define BOOT_TYPE_WEIM 0x5
+#define BOOT_TYPE_SPINOR   0x6
+#define BOOT_TYPE_USB  0xF
+
 struct boot_mode {
const char *name;
unsigned cfg_val;
diff --git a/arch/arm/mach-imx/cpu.c b/arch/arm/mach-imx/cpu.c
index fd6d08c533..a7d89f2033 100644
--- a/arch/arm/mach-imx/cpu.c
+++ b/arch/arm/mach-imx/cpu.c
@@ -16,6 +16,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -409,6 +410,43 @@ u32 get_cpu_temp_grade(int *minc, int *maxc)
 }
 #endif
 
+#if defined(CONFIG_MX7)
+enum boot_device get_boot_device(void)
+{
+   struct bootrom_sw_info **p =
+   (struct bootrom_sw_info **)(ulong)ROM_SW_INFO_ADDR;
+
+   enum boot_device boot_dev = SD1_BOOT;
+   u8 boot_type = (*p)->boot_dev_type;
+   u8 boot_instance = (*p)->boot_dev_instance;
+
+   switch (boot_type) {
+   case BOOT_TYPE_SD:
+   boot_dev = boot_instance + SD1_BOOT;
+   break;
+   case BOOT_TYPE_MMC:
+   boot_dev = boot_instance + MMC1_BOOT;
+   break;
+   case BOOT_TYPE_NAND:
+   boot_dev = NAND_BOOT;
+   break;
+   case BOOT_TYPE_QSPI:
+   boot_dev = QSPI_BOOT;
+   break;
+   case BOOT_TYPE_WEIM:
+   boot_dev = WEIM_NOR_BOOT;
+   break;
+   case BOOT_TYPE_SPINOR:
+   boot_dev = SPI_NOR_BOOT;
+   break;
+   default:
+   break;
+   }
+
+   return boot_dev;
+}
+#endif
+
 #ifdef CONFIG_NXP_BOARD_REVISION
 int nxp_board_rev(void)
 {
diff --git a/arch/arm/mach-imx/mx7/soc.c b/arch/arm/mach-imx/mx7/soc.c
index 72dbd625c9..62bd3a0e5f 100644
--- a/arch/arm/mach-imx/mx7/soc.c
+++ b/arch/arm/mach-imx/mx7/soc.c
@@ -250,41 +250,6 @@ const struct boot_mode soc_boot_modes[] = {
{NULL,  0},
 };
 
-enum boot_device get_boot_device(void)
-{
-   struct bootrom_sw_info **p =
-   (struct bootrom_sw_info **)ROM_SW_INFO_ADDR;
-
-   enum boot_device boot_dev = SD1_BOOT;
-   u8 boot_type = (*p)->boot_dev_type;
-   u8 boot_instance = (*p)->boot_dev_instance;
-
-   switch (boot_type) {
-   case BOOT_TYPE_SD:
-   boot_dev = boot_instance + SD1_BOOT;
-   break;
-   case BOOT_TYPE_MMC:
-   boot_dev = boot_instance + MMC1_BOOT;
-   break;
-   case BOOT_TYPE_NAND:
-   boot_dev = NAND_BOOT;
-   break;
-   case BOOT_TYPE_QSPI:
-   boot_dev = QSPI_BOOT;
-   break;
-   case BOOT_TYPE_WEIM:
-   boot_dev = WEIM_NOR_BOOT;
-   break;
-   case BOOT_TYPE_SPINOR:
-   boot_dev = SPI_NOR_BOOT;
-   break;
-   default:
-   break;
-   }
-
-   return boot_dev;
-}
-
 #ifdef CONFIG_ENV_IS_IN_MMC
 __weak int board_mmc_get_env_dev(int devno)
 {
-- 
2.14.1

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH V4 19/32] imx: cpu: support get_boot_device for i.MX8M

[Peng Fan]

Enable get_boot_device for i.MX8M, it supports boot type USB.

Signed-off-by: Peng Fan 
Cc: Stefano Babic 
Cc: Fabio Estevam 
---
 arch/arm/mach-imx/cpu.c | 7 ++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-imx/cpu.c b/arch/arm/mach-imx/cpu.c
index a7d89f2033..4d4d434906 100644
--- a/arch/arm/mach-imx/cpu.c
+++ b/arch/arm/mach-imx/cpu.c
@@ -410,7 +410,7 @@ u32 get_cpu_temp_grade(int *minc, int *maxc)
 }
 #endif
 
-#if defined(CONFIG_MX7)
+#if defined(CONFIG_MX7) || defined(CONFIG_MX8M)
 enum boot_device get_boot_device(void)
 {
struct bootrom_sw_info **p =
@@ -439,6 +439,11 @@ enum boot_device get_boot_device(void)
case BOOT_TYPE_SPINOR:
boot_dev = SPI_NOR_BOOT;
break;
+#ifdef CONFIG_MX8M
+   case BOOT_TYPE_USB:
+   boot_dev = USB_BOOT;
+   break;
+#endif
default:
break;
}
-- 
2.14.1

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH V4 06/32] imx: mx8m: add clock driver

[Peng Fan]

Add clock driver to support i.MX8M.

There are two kind PLLs, FRAC pll and SSCG pll. ROM already
configured SYS PLL1/2, we only need to configure the output.
ocotp/i2c/pll decoding and configuration/usdhc/lcdif/dram pll/
enet clock are configured in the code.

Signed-off-by: Peng Fan 
Cc: Fabio Estevam 
Cc: Stefano Babic 
---
 arch/arm/include/asm/arch-mx8m/clock.h | 657 +++
 arch/arm/mach-imx/mx8m/Makefile|   7 +
 arch/arm/mach-imx/mx8m/clock.c | 795 +
 arch/arm/mach-imx/mx8m/clock_slice.c   | 742 ++
 4 files changed, 2201 insertions(+)
 create mode 100644 arch/arm/include/asm/arch-mx8m/clock.h
 create mode 100644 arch/arm/mach-imx/mx8m/Makefile
 create mode 100644 arch/arm/mach-imx/mx8m/clock.c
 create mode 100644 arch/arm/mach-imx/mx8m/clock_slice.c

diff --git a/arch/arm/include/asm/arch-mx8m/clock.h 
b/arch/arm/include/asm/arch-mx8m/clock.h
new file mode 100644
index 00..12b453
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx8m/clock.h
@@ -0,0 +1,657 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * Peng Fan 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef _ASM_ARCH_IMX8M_CLOCK_H
+#define _ASM_ARCH_IMX8M_CLOCK_H
+
+#include 
+
+enum pll_clocks {
+   ANATOP_ARM_PLL,
+   ANATOP_GPU_PLL,
+   ANATOP_SYSTEM_PLL1,
+   ANATOP_SYSTEM_PLL2,
+   ANATOP_SYSTEM_PLL3,
+   ANATOP_AUDIO_PLL1,
+   ANATOP_AUDIO_PLL2,
+   ANATOP_VIDEO_PLL1,
+   ANATOP_VIDEO_PLL2,
+   ANATOP_DRAM_PLL,
+};
+
+enum clk_slice_type {
+   CORE_CLOCK_SLICE,
+   BUS_CLOCK_SLICE,
+   IP_CLOCK_SLICE,
+   AHB_CLOCK_SLICE,
+   IPG_CLOCK_SLICE,
+   CORE_SEL_CLOCK_SLICE,
+   DRAM_SEL_CLOCK_SLICE,
+};
+
+enum clk_root_index {
+   MXC_ARM_CLK = 0,
+   ARM_A53_CLK_ROOT= 0,
+   ARM_M4_CLK_ROOT = 1,
+   VPU_A53_CLK_ROOT= 2,
+   GPU_CORE_CLK_ROOT   = 3,
+   GPU_SHADER_CLK_ROOT = 4,
+   MAIN_AXI_CLK_ROOT   = 16,
+   ENET_AXI_CLK_ROOT   = 17,
+   NAND_USDHC_BUS_CLK_ROOT = 18,
+   VPU_BUS_CLK_ROOT= 19,
+   DISPLAY_AXI_CLK_ROOT= 20,
+   DISPLAY_APB_CLK_ROOT= 21,
+   DISPLAY_RTRM_CLK_ROOT   = 22,
+   USB_BUS_CLK_ROOT= 23,
+   GPU_AXI_CLK_ROOT= 24,
+   GPU_AHB_CLK_ROOT= 25,
+   NOC_CLK_ROOT= 26,
+   NOC_APB_CLK_ROOT= 27,
+   AHB_CLK_ROOT= 32,
+   IPG_CLK_ROOT= 33,
+   MXC_IPG_CLK = 33,
+   AUDIO_AHB_CLK_ROOT  = 34,
+   MIPI_DSI_ESC_RX_CLK_ROOT= 36,
+   DRAM_SEL_CFG= 48,
+   CORE_SEL_CFG= 49,
+   DRAM_ALT_CLK_ROOT   = 64,
+   DRAM_APB_CLK_ROOT   = 65,
+   VPU_G1_CLK_ROOT = 66,
+   VPU_G2_CLK_ROOT = 67,
+   DISPLAY_DTRC_CLK_ROOT   = 68,
+   DISPLAY_DC8000_CLK_ROOT = 69,
+   PCIE1_CTRL_CLK_ROOT = 70,
+   PCIE1_PHY_CLK_ROOT  = 71,
+   PCIE1_AUX_CLK_ROOT  = 72,
+   DC_PIXEL_CLK_ROOT   = 73,
+   LCDIF_PIXEL_CLK_ROOT= 74,
+   SAI1_CLK_ROOT   = 75,
+   SAI2_CLK_ROOT   = 76,
+   SAI3_CLK_ROOT   = 77,
+   SAI4_CLK_ROOT   = 78,
+   SAI5_CLK_ROOT   = 79,
+   SAI6_CLK_ROOT   = 80,
+   SPDIF1_CLK_ROOT = 81,
+   SPDIF2_CLK_ROOT = 82,
+   ENET_REF_CLK_ROOT   = 83,
+   ENET_TIMER_CLK_ROOT = 84,
+   ENET_PHY_REF_CLK_ROOT   = 85,
+   NAND_CLK_ROOT   = 86,
+   QSPI_CLK_ROOT   = 87,
+   MXC_ESDHC_CLK   = 88,
+   USDHC1_CLK_ROOT = 88,
+   MXC_ESDHC2_CLK  = 89,
+   USDHC2_CLK_ROOT = 89,
+   I2C1_CLK_ROOT   = 90,
+   MXC_I2C_CLK = 90,
+   I2C2_CLK_ROOT   = 91,
+   I2C3_CLK_ROOT   = 92,
+   I2C4_CLK_ROOT   = 93,
+   UART1_CLK_ROOT  = 94,
+   UART2_CLK_ROOT  = 95,
+   UART3_CLK_ROOT  = 96,
+   UART4_CLK_ROOT  = 97,
+   USB_CORE_REF_CLK_ROOT   = 98,
+   USB_PHY_REF_CLK_ROOT= 99,
+   GIC_CLK_ROOT= 100,
+   ECSPI1_CLK_ROOT = 101,
+   ECSPI2_CLK_ROOT = 102,
+   PWM1_CLK_ROOT   = 103,
+   

[U-Boot] [PATCH V4 04/32] imx: mx8m: add pin header file

[Peng Fan]

Add pin header file for i.MX8M

Signed-off-by: Peng Fan 
Reviewed-by: Fabio Estevam 
Cc: Stefano Babic 
---
 arch/arm/include/asm/arch-mx8m/mx8mq_pins.h | 623 
 1 file changed, 623 insertions(+)
 create mode 100644 arch/arm/include/asm/arch-mx8m/mx8mq_pins.h

diff --git a/arch/arm/include/asm/arch-mx8m/mx8mq_pins.h 
b/arch/arm/include/asm/arch-mx8m/mx8mq_pins.h
new file mode 100644
index 00..062bea7299
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx8m/mx8mq_pins.h
@@ -0,0 +1,623 @@
+/*
+ * Copyright (C) 2017 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_MX8MQ_PINS_H__
+#define __ASM_ARCH_MX8MQ_PINS_H__
+
+#include 
+
+enum {
+   IMX8MQ_PAD_GPIO1_IO00__GPIO1_IO0= 
IOMUX_PAD(0x0290, 0x0028, 0, 0x, 0, 0),
+   IMX8MQ_PAD_GPIO1_IO00__CCM_ENET_PHY_REF_CLK_ROOT= 
IOMUX_PAD(0x0290, 0x0028, 1, 0x, 0, 0),
+   IMX8MQ_PAD_GPIO1_IO00__XTALOSC_REF_CLK_32K  = 
IOMUX_PAD(0x0290, 0x0028, 5, 0x, 0, 0),
+   IMX8MQ_PAD_GPIO1_IO00__CCM_EXT_CLK1 = 
IOMUX_PAD(0x0290, 0x0028, 6, 0x, 0, 0),
+   IMX8MQ_PAD_GPIO1_IO00__JTAG_FAIL= 
IOMUX_PAD(0x0290, 0x0028, 7, 0x, 0, 0),
+
+   IMX8MQ_PAD_GPIO1_IO01__GPIO1_IO1= 
IOMUX_PAD(0x0294, 0x002C, 0, 0x, 0, 0),
+   IMX8MQ_PAD_GPIO1_IO01__PWM1_OUT = 
IOMUX_PAD(0x0294, 0x002C, 1, 0x, 0, 0),
+   IMX8MQ_PAD_GPIO1_IO01__XTALOSC_REF_CLK_24M  = 
IOMUX_PAD(0x0294, 0x002C, 5, 0x, 0, 0),
+   IMX8MQ_PAD_GPIO1_IO01__CCM_EXT_CLK2 = 
IOMUX_PAD(0x0294, 0x002C, 6, 0x, 0, 0),
+   IMX8MQ_PAD_GPIO1_IO01__JTAG_ACTIVE  = 
IOMUX_PAD(0x0294, 0x002C, 7, 0x, 0, 0),
+
+   IMX8MQ_PAD_GPIO1_IO02__GPIO1_IO2= 
IOMUX_PAD(0x0298, 0x0030, 0, 0x, 0, 0),
+   IMX8MQ_PAD_GPIO1_IO02__WDOG1_WDOG_B = 
IOMUX_PAD(0x0298, 0x0030, 1, 0x, 0, 0),
+   IMX8MQ_PAD_GPIO1_IO02__WDOG1_WDOG_ANY   = 
IOMUX_PAD(0x0298, 0x0030, 5, 0x, 0, 0),
+   IMX8MQ_PAD_GPIO1_IO02__JTAG_DE_B= 
IOMUX_PAD(0x0298, 0x0030, 7, 0x, 0, 0),
+
+   IMX8MQ_PAD_GPIO1_IO03__GPIO1_IO3= 
IOMUX_PAD(0x029C, 0x0034, 0, 0x, 0, 0),
+   IMX8MQ_PAD_GPIO1_IO03__USDHC1_VSELECT   = 
IOMUX_PAD(0x029C, 0x0034, 1, 0x, 0, 0),
+   IMX8MQ_PAD_GPIO1_IO03__SDMA1_EXT_EVENT0 = 
IOMUX_PAD(0x029C, 0x0034, 5, 0x, 0, 0),
+   IMX8MQ_PAD_GPIO1_IO03__XTALOSC_XTAL_OK  = 
IOMUX_PAD(0x029C, 0x0034, 6, 0x, 0, 0),
+   IMX8MQ_PAD_GPIO1_IO03__JTAG_DONE= 
IOMUX_PAD(0x029C, 0x0034, 7, 0x, 0, 0),
+
+   IMX8MQ_PAD_GPIO1_IO04__GPIO1_IO4= 
IOMUX_PAD(0x02A0, 0x0038, 0, 0x, 0, 0),
+   IMX8MQ_PAD_GPIO1_IO04__USDHC2_VSELECT   = 
IOMUX_PAD(0x02A0, 0x0038, 1, 0x, 0, 0),
+   IMX8MQ_PAD_GPIO1_IO04__SDMA1_EXT_EVENT1 = 
IOMUX_PAD(0x02A0, 0x0038, 5, 0x, 0, 0),
+   IMX8MQ_PAD_GPIO1_IO04__XTALOSC_XTAL_OK_1V   = 
IOMUX_PAD(0x02A0, 0x0038, 6, 0x, 0, 0),
+
+   IMX8MQ_PAD_GPIO1_IO05__GPIO1_IO5= 
IOMUX_PAD(0x02A4, 0x003C, 0, 0x, 0, 0),
+   IMX8MQ_PAD_GPIO1_IO05__ARM_PLATFORM_CM4_NMI = 
IOMUX_PAD(0x02A4, 0x003C, 1, 0x, 0, 0),
+   IMX8MQ_PAD_GPIO1_IO05__CCM_PMIC_READY   = 
IOMUX_PAD(0x02A4, 0x003C, 5, 0x04BC, 0, 0),
+   IMX8MQ_PAD_GPIO1_IO05__SRC_INT_BOOT = 
IOMUX_PAD(0x02A4, 0x003C, 6, 0x, 0, 0),
+
+   IMX8MQ_PAD_GPIO1_IO06__GPIO1_IO6= 
IOMUX_PAD(0x02A8, 0x0040, 0, 0x, 0, 0),
+   IMX8MQ_PAD_GPIO1_IO06__ENET_MDC = 
IOMUX_PAD(0x02A8, 0x0040, 1, 0x, 0, 0),
+   IMX8MQ_PAD_GPIO1_IO06__USDHC1_CD_B  = 
IOMUX_PAD(0x02A8, 0x0040, 5, 0x, 0, 0),
+   IMX8MQ_PAD_GPIO1_IO06__CCM_EXT_CLK3 = 
IOMUX_PAD(0x02A8, 0x0040, 6, 0x, 0, 0),
+
+   IMX8MQ_PAD_GPIO1_IO07__GPIO1_IO7= 
IOMUX_PAD(0x02AC, 0x0044, 0, 0x, 0, 0),
+   IMX8MQ_PAD_GPIO1_IO07__ENET_MDIO= 
IOMUX_PAD(0x02AC, 0x0044, 1, 0x04C0, 0, 0),
+   IMX8MQ_PAD_GPIO1_IO07__USDHC1_WP= 
IOMUX_PAD(0x02AC, 0x0044, 5, 0x, 0, 0),
+   IMX8MQ_PAD_GPIO1_IO07__CCM_EXT_CLK4 = 
IOMUX_PAD(0x02AC, 0x0044, 6, 0x, 0, 0),
+
+   IMX8MQ_PAD_GPIO1_IO08__GPIO1_IO8= 
IOMUX_PAD(0x02B0, 0x0048, 0, 0x, 0, 0),
+   IMX8MQ_PAD_GPIO1_IO08__ENET_1588_EVENT0_IN  = 

[U-Boot] [PATCH V4 07/32] imx: add sip function

[Peng Fan]

Add SiP (Silicon Provider) services function to issue
SMC call to Arm Trusted Firmware.

More SiP information could be found in
  https://github.com/ARM-software/arm-trusted-firmware/blob/master/
  docs/arm-sip-service.rst

Signed-off-by: Peng Fan 
Reviewed-by: Fabio Estevam 
Cc: Stefano Babic 
---
 arch/arm/include/asm/mach-imx/sys_proto.h |  3 +++
 arch/arm/mach-imx/Makefile|  2 ++
 arch/arm/mach-imx/sip.c   | 23 +++
 include/imx_sip.h | 14 ++
 4 files changed, 42 insertions(+)
 create mode 100644 arch/arm/mach-imx/sip.c
 create mode 100644 include/imx_sip.h

diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h 
b/arch/arm/include/asm/mach-imx/sys_proto.h
index d518e03809..c53e5400a1 100644
--- a/arch/arm/include/asm/mach-imx/sys_proto.h
+++ b/arch/arm/include/asm/mach-imx/sys_proto.h
@@ -126,4 +126,7 @@ void lcdif_power_down(void);
 int mxs_reset_block(struct mxs_register_32 *reg);
 int mxs_wait_mask_set(struct mxs_register_32 *reg, u32 mask, u32 timeout);
 int mxs_wait_mask_clr(struct mxs_register_32 *reg, u32 mask, u32 timeout);
+
+unsigned long call_imx_sip(unsigned long id, unsigned long reg0,
+  unsigned long reg1, unsigned long reg2);
 #endif
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index cf39d08bdd..63db0e15c4 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -124,6 +124,8 @@ spl/u-boot-nand-spl.imx: SPL FORCE
 
 targets += $(addprefix ../../../,$(IMX_CONFIG) SPL u-boot.uim 
spl/u-boot-nand-spl.imx)
 
+obj-$(CONFIG_ARM64) += sip.o
+
 obj-$(CONFIG_MX5) += mx5/
 obj-$(CONFIG_MX6) += mx6/
 obj-$(CONFIG_MX7) += mx7/
diff --git a/arch/arm/mach-imx/sip.c b/arch/arm/mach-imx/sip.c
new file mode 100644
index 00..b724330d35
--- /dev/null
+++ b/arch/arm/mach-imx/sip.c
@@ -0,0 +1,23 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+
+unsigned long call_imx_sip(unsigned long id, unsigned long reg0,
+  unsigned long reg1, unsigned long reg2)
+{
+   struct pt_regs regs;
+
+   regs.regs[0] = id;
+   regs.regs[1] = reg0;
+   regs.regs[2] = reg1;
+   regs.regs[3] = reg2;
+
+   smc_call();
+
+   return regs.regs[0];
+}
diff --git a/include/imx_sip.h b/include/imx_sip.h
new file mode 100644
index 00..48ab878749
--- /dev/null
+++ b/include/imx_sip.h
@@ -0,0 +1,14 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef _IMX_SIP_H__
+#define _IMX_SIP_H_
+
+#define IMX_SIP_SRC0xC205
+#define IMX_SIP_SRC_M4_START   0x00
+#define IMX_SIP_SRC_M4_STARTED 0x01
+
+#endif
-- 
2.14.1

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH V4 08/32] imx: boot_mode: add USB_BOOT entry

[Peng Fan]

Add USB_BOOT entry.

Signed-off-by: Peng Fan 
Reviewed-by: Stefano Babic 
Reviewed-by: Fabio Estevam 
---
 arch/arm/include/asm/mach-imx/boot_mode.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/include/asm/mach-imx/boot_mode.h 
b/arch/arm/include/asm/mach-imx/boot_mode.h
index a8239f2f7a..e3ed046b25 100644
--- a/arch/arm/include/asm/mach-imx/boot_mode.h
+++ b/arch/arm/include/asm/mach-imx/boot_mode.h
@@ -26,6 +26,7 @@ enum boot_device {
MMC4_BOOT,
NAND_BOOT,
QSPI_BOOT,
+   USB_BOOT,
UNKNOWN_BOOT,
BOOT_DEV_NUM = UNKNOWN_BOOT,
 };
-- 
2.14.1

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH V4 10/32] imx: spl: implement spl_boot_device for i.MX8M

[Peng Fan]

Implement spl_boot_device for i.MX8M.

Signed-off-by: Peng Fan 
Reviewed-by: Fabio Estevam 
Cc: Stefano Babic 
---
 arch/arm/mach-imx/spl.c | 10 +++---
 1 file changed, 7 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-imx/spl.c b/arch/arm/mach-imx/spl.c
index 723f51fad3..7c4ee82cd1 100644
--- a/arch/arm/mach-imx/spl.c
+++ b/arch/arm/mach-imx/spl.c
@@ -97,8 +97,8 @@ u32 spl_boot_device(void)
return BOOT_DEVICE_NONE;
 }
 
-#elif defined(CONFIG_MX7)
-/* Translate iMX7 boot device to the SPL boot device enumeration */
+#elif defined(CONFIG_MX7) || defined(CONFIG_MX8M)
+/* Translate iMX7/MX8M boot device to the SPL boot device enumeration */
 u32 spl_boot_device(void)
 {
enum boot_device boot_device_spl = get_boot_device();
@@ -112,11 +112,15 @@ u32 spl_boot_device(void)
return BOOT_DEVICE_MMC2;
case SPI_NOR_BOOT:
return BOOT_DEVICE_SPI;
+   case NAND_BOOT:
+   return BOOT_DEVICE_NAND;
+   case USB_BOOT:
+   return BOOT_DEVICE_USB;
default:
return BOOT_DEVICE_NONE;
}
 }
-#endif /* CONFIG_MX6 || CONFIG_MX7 */
+#endif /* CONFIG_MX6 || CONFIG_MX7 || CONFIG_MX8M */
 
 #ifdef CONFIG_SPL_USB_GADGET_SUPPORT
 int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name)
-- 
2.14.1

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH V4 09/32] imx: cpu: update cpu file to support i.MX8M

[Peng Fan]

Update get_reset_cause to reflect i.MX8M
Compile out get_ahb_clk and set_chipselect_size for i.MX8M

Signed-off-by: Peng Fan 
Reviewed-by: Stefano Babic 
Reviewed-by: Fabio Estevam 
---
 arch/arm/mach-imx/cpu.c | 11 ++-
 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-imx/cpu.c b/arch/arm/mach-imx/cpu.c
index a32ab87e9b..fae8b0a419 100644
--- a/arch/arm/mach-imx/cpu.c
+++ b/arch/arm/mach-imx/cpu.c
@@ -62,6 +62,11 @@ static char *get_reset_cause(void)
return "WDOG4";
case 0x00200:
return "TEMPSENSE";
+#elif defined(CONFIG_MX8M)
+   case 0x00100:
+   return "WDOG2";
+   case 0x00200:
+   return "TEMPSENSE";
 #else
case 0x00100:
return "TEMPSENSE";
@@ -137,6 +142,8 @@ unsigned imx_ddr_size(void)
 const char *get_imx_type(u32 imxtype)
 {
switch (imxtype) {
+   case MXC_CPU_MX8MQ:
+   return "8MQ";   /* Quad-core version of the mx8m */
case MXC_CPU_MX7S:
return "7S";/* Single-core version of the mx7 */
case MXC_CPU_MX7D:
@@ -259,7 +266,7 @@ int cpu_mmc_init(bd_t *bis)
 }
 #endif
 
-#ifndef CONFIG_MX7
+#if !(defined(CONFIG_MX7) || defined(CONFIG_MX8M))
 u32 get_ahb_clk(void)
 {
struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
@@ -293,6 +300,7 @@ void arch_preboot_os(void)
 #endif
 }
 
+#ifndef CONFIG_MX8M
 void set_chipselect_size(int const cs_size)
 {
unsigned int reg;
@@ -323,6 +331,7 @@ void set_chipselect_size(int const cs_size)
 
writel(reg, _regs->gpr[1]);
 }
+#endif
 
 #ifdef CONFIG_NXP_BOARD_REVISION
 int nxp_board_rev(void)
-- 
2.14.1

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH V4 11/32] imx: add i.MX8MQ SoC Revision and is_mx8m helper

[Peng Fan]

Add i.MX8MQ SoC Revision
Add is_mx8m helper
The 7ULP is a dummy number, so use 0xEx.

Signed-off-by: Peng Fan 
Reviewed-by: Fabio Estevam 
Cc: Stefano Babic 
---
 arch/arm/include/asm/arch-imx/cpu.h   | 6 --
 arch/arm/include/asm/mach-imx/sys_proto.h | 1 +
 2 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/arch/arm/include/asm/arch-imx/cpu.h 
b/arch/arm/include/asm/arch-imx/cpu.h
index ec5b419e47..470961c6f7 100644
--- a/arch/arm/include/asm/arch-imx/cpu.h
+++ b/arch/arm/include/asm/arch-imx/cpu.h
@@ -25,12 +25,14 @@
 #define MXC_CPU_MX6QP  0x69
 #define MXC_CPU_MX7S   0x71 /* dummy ID */
 #define MXC_CPU_MX7D   0x72
-#define MXC_CPU_MX7ULP 0x81 /* Temporally hard code */
+#define MXC_CPU_MX8MQ  0x82
+#define MXC_CPU_MX7ULP 0xE1 /* Temporally hard code */
 #define MXC_CPU_VF610  0xF6 /* dummy ID */
 
 #define MXC_SOC_MX60x60
 #define MXC_SOC_MX70x70
-#define MXC_SOC_MX7ULP 0x80 /* dummy */
+#define MXC_SOC_MX8M   0x80
+#define MXC_SOC_MX7ULP 0xE0 /* dummy */
 
 #define CHIP_REV_1_00x10
 #define CHIP_REV_1_10x11
diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h 
b/arch/arm/include/asm/mach-imx/sys_proto.h
index c53e5400a1..96795e1814 100644
--- a/arch/arm/include/asm/mach-imx/sys_proto.h
+++ b/arch/arm/include/asm/mach-imx/sys_proto.h
@@ -27,6 +27,7 @@
 
 #define is_mx6() (is_soc_type(MXC_SOC_MX6))
 #define is_mx7() (is_soc_type(MXC_SOC_MX7))
+#define is_mx8m() (is_soc_type(MXC_SOC_MX8M))
 
 #define is_mx6dqp() (is_cpu_type(MXC_CPU_MX6QP) || is_cpu_type(MXC_CPU_MX6DP))
 #define is_mx6dq() (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D))
-- 
2.14.1

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH V4 05/32] time: add wait_mask_set/clr_timeout helper functions

[Peng Fan]

Add heler functions for wait mask set/clr.

Signed-off-by: Peng Fan 
Cc: Stefano Babic 
Cc: Fabio Estevam 
Cc: Masahiro Yamada 
Cc: Simon Glass 
---
 include/linux/delay.h |  4 
 lib/time.c| 30 ++
 2 files changed, 34 insertions(+)

diff --git a/include/linux/delay.h b/include/linux/delay.h
index 3dcd435d0d..b08fcb8c09 100644
--- a/include/linux/delay.h
+++ b/include/linux/delay.h
@@ -21,4 +21,8 @@ static inline void ndelay(unsigned long nsec)
udelay(DIV_ROUND_UP(nsec, 1000));
 }
 
+int wait_mask_set_timeout(void *addr, u32 mask, u32 timeout);
+
+int wait_mask_clr_timeout(void *addr, u32 mask, u32 timeout);
+
 #endif /* defined(_LINUX_DELAY_H) */
diff --git a/lib/time.c b/lib/time.c
index aed1a091f2..9701287629 100644
--- a/lib/time.c
+++ b/lib/time.c
@@ -171,3 +171,33 @@ void udelay(unsigned long usec)
usec -= kv;
} while(usec);
 }
+
+int wait_mask_set_timeout(void *addr, u32 mask, u32 timeout)
+{
+   unsigned long long end_tick;
+   u32 val;
+
+   end_tick = usec_to_tick(timeout) + get_ticks();
+   do {
+   val = readl(addr);
+   if ((val & mask) == mask)
+   return 0;
+   } while (end_tick > get_ticks());
+
+   return -ETIMEDOUT;
+}
+
+int wait_mask_clr_timeout(void *addr, u32 mask, u32 timeout)
+{
+   unsigned long long end_tick;
+   u32 val;
+
+   end_tick = usec_to_tick(timeout) + get_ticks();
+   do {
+   val = readl(addr);
+   if (!(val & mask))
+   return 0;
+   } while (end_tick > get_ticks());
+
+   return -ETIMEDOUT;
+}
-- 
2.14.1

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH V4 03/32] imx: mx8m: add register definition header file

[Peng Fan]

Add register definition header file for i.MX8M

Signed-off-by: Peng Fan 
Reviewed-by: Fabio Estevam 
Cc: Stefano Babic 
---
 arch/arm/include/asm/arch-mx8m/imx-regs.h | 468 ++
 1 file changed, 468 insertions(+)
 create mode 100644 arch/arm/include/asm/arch-mx8m/imx-regs.h

diff --git a/arch/arm/include/asm/arch-mx8m/imx-regs.h 
b/arch/arm/include/asm/arch-mx8m/imx-regs.h
new file mode 100644
index 00..a10034cc35
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx8m/imx-regs.h
@@ -0,0 +1,468 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_MX8M_REGS_H__
+#define __ASM_ARCH_MX8M_REGS_H__
+
+#include 
+
+#define ROM_VERSION_A0 0x800
+#define ROM_VERSION_B0 0x83C
+
+#define M4_BOOTROM_BASE_ADDR   0x007E
+
+#define SAI1_BASE_ADDR 0x3001
+#define SAI6_BASE_ADDR 0x3003
+#define SAI5_BASE_ADDR 0x3004
+#define SAI4_BASE_ADDR 0x3005
+#define SPBA2_BASE_ADDR0x300F
+#define AIPS1_BASE_ADDR0x301F
+#define GPIO1_BASE_ADDR0X3020
+#define GPIO2_BASE_ADDR0x3021
+#define GPIO3_BASE_ADDR0x3022
+#define GPIO4_BASE_ADDR0x3023
+#define GPIO5_BASE_ADDR0x3024
+#define ANA_TSENSOR_BASE_ADDR  0x3026
+#define ANA_OSC_BASE_ADDR  0x3027
+#define WDOG1_BASE_ADDR0x3028
+#define WDOG2_BASE_ADDR0x3029
+#define WDOG3_BASE_ADDR0x302A
+#define SDMA2_BASE_ADDR0x302C
+#define GPT1_BASE_ADDR 0x302D
+#define GPT2_BASE_ADDR 0x302E
+#define GPT3_BASE_ADDR 0x302F
+#define ROMCP_BASE_ADDR0x3031
+#define LCDIF_BASE_ADDR0x3032
+#define IOMUXC_BASE_ADDR   0x3033
+#define IOMUXC_GPR_BASE_ADDR   0x3034
+#define OCOTP_BASE_ADDR0x3035
+#define ANATOP_BASE_ADDR   0x3036
+#define SNVS_HP_BASE_ADDR  0x3037
+#define CCM_BASE_ADDR  0x3038
+#define SRC_BASE_ADDR  0x3039
+#define GPC_BASE_ADDR  0x303A
+#define SEMAPHORE1_BASE_ADDR   0x303B
+#define SEMAPHORE2_BASE_ADDR   0x303C
+#define RDC_BASE_ADDR  0x303D
+#define CSU_BASE_ADDR  0x303E
+
+#define AIPS2_BASE_ADDR0x305F
+#define PWM1_BASE_ADDR 0x3066
+#define PWM2_BASE_ADDR 0x3067
+#define PWM3_BASE_ADDR 0x3068
+#define PWM4_BASE_ADDR 0x3069
+#define SYSCNT_RD_BASE_ADDR0x306A
+#define SYSCNT_CMP_BASE_ADDR   0x306B
+#define SYSCNT_CTRL_BASE_ADDR  0x306C
+#define GPT6_BASE_ADDR 0x306E
+#define GPT5_BASE_ADDR 0x306F
+#define GPT4_BASE_ADDR 0x3070
+#define PERFMON1_BASE_ADDR 0x307C
+#define PERFMON2_BASE_ADDR 0x307D
+#define QOSC_BASE_ADDR 0x307F
+
+#define SPDIF1_BASE_ADDR   0x3081
+#define ECSPI1_BASE_ADDR   0x3082
+#define ECSPI2_BASE_ADDR   0x3083
+#define ECSPI3_BASE_ADDR   0x3084
+#define UART1_BASE_ADDR0x3086
+#define UART3_BASE_ADDR0x3088
+#define UART2_BASE_ADDR0x3089
+#define SPDIF2_BASE_ADDR   0x308A
+#define SAI2_BASE_ADDR 0x308B
+#define SAI3_BASE_ADDR 0x308C
+#define SPBA1_BASE_ADDR0x308F
+#define CAAM_BASE_ADDR 0x3090
+#define AIPS3_BASE_ADDR0x309F
+#define MIPI_PHY_BASE_ADDR 0x30A0
+#define MIPI_DSI_BASE_ADDR 0x30A1
+#define I2C1_BASE_ADDR 0x30A2
+#define I2C2_BASE_ADDR 0x30A3
+#define I2C3_BASE_ADDR 0x30A4
+#define I2C4_BASE_ADDR 0x30A5
+#define UART4_BASE_ADDR0x30A6
+#define MIPI_CSI_BASE_ADDR 0x30A7
+#define MIPI_CSI_PHY1_BASE_ADDR0x30A8
+#define CSI1_BASE_ADDR 0x30A9
+#define MU_A_BASE_ADDR 0x30AA
+#define MU_B_BASE_ADDR 0x30AB
+#define SEMAPHOR_HS_BASE_ADDR  0x30AC
+#define USDHC1_BASE_ADDR   0x30B4
+#define USDHC2_BASE_ADDR   0x30B5
+#define MIPI_CS2_BASE_ADDR 0x30B6
+#define MIPI_CSI_PHY2_BASE_ADDR0x30B7
+#define CSI2_BASE_ADDR 0x30B8
+#define QSPI0_BASE_ADDR0x30BB
+#define QSPI0_AMBA_BASE0x0800
+#define SDMA1_BASE_ADDR0x30BD
+#define ENET1_BASE_ADDR0x30BE
+
+#define HDMI_CTRL_BASE_ADDR0x32C0
+#define AIPS4_BASE_ADDR0x32DF
+#define DC1_BASE_ADDR  0x32E0
+#define DC2_BASE_ADDR  0x32E1
+#define DC3_BASE_ADDR  0x32E2
+#define HDMI_SEC_BASE_ADDR 0x32E4
+#define TZASC_BASE_ADDR0x32F8
+#define 

[U-Boot] [PATCH V4 02/32] imx: add i.MX8M into Kconfig

[Peng Fan]

Add i.MX8M into Kconfig, create a new folder mx8m
dedicated for i.MX8M.

Signed-off-by: Peng Fan 
Reviewed-by: Fabio Estevam 
Cc: Stefano Babic 
---
 arch/arm/Kconfig   | 14 +++---
 arch/arm/Makefile  |  4 ++--
 arch/arm/mach-imx/mx8m/Kconfig | 10 ++
 3 files changed, 23 insertions(+), 5 deletions(-)
 create mode 100644 arch/arm/mach-imx/mx8m/Kconfig

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index f2c35e32c6..b095bfe2e5 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -604,6 +604,12 @@ config ARCH_MESON
  targeted at media players and tablet computers. We currently
  support the S905 (GXBaby) 64-bit SoC.
 
+config ARCH_MX8M
+   bool "NXP i.MX8M platform"
+   select ARM64
+   select DM
+   select SUPPORT_SPL
+
 config ARCH_MX25
bool "NXP MX25"
select CPU_ARM926EJS
@@ -1180,13 +1186,15 @@ source "arch/arm/cpu/armv7/ls102xa/Kconfig"
 
 source "arch/arm/mach-imx/mx2/Kconfig"
 
-source "arch/arm/mach-imx/mx7ulp/Kconfig"
+source "arch/arm/mach-imx/mx5/Kconfig"
+
+source "arch/arm/mach-imx/mx6/Kconfig"
 
 source "arch/arm/mach-imx/mx7/Kconfig"
 
-source "arch/arm/mach-imx/mx6/Kconfig"
+source "arch/arm/mach-imx/mx7ulp/Kconfig"
 
-source "arch/arm/mach-imx/mx5/Kconfig"
+source "arch/arm/mach-imx/mx8m/Kconfig"
 
 source "arch/arm/mach-omap2/Kconfig"
 
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 0e0ae77822..5881fdc8e2 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -95,11 +95,11 @@ libs-y += arch/arm/cpu/
 libs-y += arch/arm/lib/
 
 ifeq ($(CONFIG_SPL_BUILD),y)
-ifneq (,$(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_MX35)$(filter $(SOC), mx25 mx5 
mx6 mx7 mx35))
+ifneq (,$(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_MX35)$(filter $(SOC), mx25 mx5 
mx6 mx7 mx35 mx8m))
 libs-y += arch/arm/mach-imx/
 endif
 else
-ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx7 mx7ulp mx31 mx35 mxs vf610))
+ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx7 mx7ulp mx31 mx35 mxs mx8m 
vf610))
 libs-y += arch/arm/mach-imx/
 endif
 endif
diff --git a/arch/arm/mach-imx/mx8m/Kconfig b/arch/arm/mach-imx/mx8m/Kconfig
new file mode 100644
index 00..3a84c2f2b0
--- /dev/null
+++ b/arch/arm/mach-imx/mx8m/Kconfig
@@ -0,0 +1,10 @@
+if ARCH_MX8M
+
+config MX8M
+   bool
+   select ROM_UNIFIED_SECTIONS
+
+config SYS_SOC
+   default "mx8m"
+
+endif
-- 
2.14.1

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH V4 00/32] imx: add i.MX8M support and i.MX8MQ EVK

[Peng Fan]

This patchset is to add i.MX8M and i.MX8MQ-EVK support

V4:
 Regenerate patchset based on Tom's master tree. 
 In this patchset, https://patchwork.ozlabs.org/patch/855027/
 "arm: imx: Rework i.MX specific commands to be excluded from SPL" from
 Tom is included to avoid merge conflicts because the i.mx8m change
 also has some modification to bootaux and arch/arm/mach-imx/Makefile.
 Because CONFIG_GPT_TIMER change, I did a small modification to apply
 Tom's patch, no function change.

 Include ATF link in README.

V3:
 This patchset based on https://patchwork.ozlabs.org/patch/855027/
 "arm: imx: Rework i.MX specific commands to be excluded from SPL" from
 Tom to avoid this patchset fail apply after Tom's patch merged.

 Previously "power: pmic/regulator allow dm be omited by SPL" broke other
 boards, in V3 patchset, only touch pfuze100 related options.

 Sharing code about get mac from fuse between mx7/mx8m
 Sharing code about bootaux between mx6/7/mx8m
 Sharing code about cpu speed grade between mx7/mx8m
 Sharing code about get boot device between mx7/mx8m
 Sharding code about mmc env between mx7/mx8m

 Introduce wait_mask_set/clr_timeout to avoid deadloop in clock pll 
configuration

 Correct authorship of fix building warning on fec arm64, patch 27/31.

 Switch to use structure for DDR Controller. For DDR PHY registers,
 there are about more than 10 thousands registers, I could not convert
 them with detailed register name, and the script is generated from IC team,
 So I use regs[0x] arrays here fo easily converting between IC team
 released script and uboot ddr phy cod.

 Improve REAMME file to include where to download firmware and imx-mkimage
 and how to build

 Add review tags on the V2 patchset.

 Hope this patchset could catch up next release :)

V2:

 patch 02/23: convert to structure, drop is_boot_from_usb and
  disconnect_from_usb
 patch 04/23: conver to use structure for the clock driver, removed the
  CCM_xxx macros. Add static for local functons.
  Add init_usdhc_clk, init_uart_clk and etc to not enable
  them all at default.
 patch 05/23: Add more commit msg for the sip part.
 patch 08/23: Merge the spl boot device with i.MX7
 patch 12/23: Typo fix and return error fix from Heiko for the SoC related part
 patch 22/23: Use a weak function ddr_init. If patch 23/23 could not be
  accepted at current stage, to make others still be could be
  compiled.

The patchset depends on
https://patchwork.ozlabs.org/patch/841934/
https://patchwork.ozlabs.org/patch/841958/
to be tested on real hardware.

V1:

patch: "power: pmic.h: include dm/ofnode.h" and
"power: pmic/regulator allow dm be omited by SPL" is previously reviewed
in mailist to not merged. If no issue, you may pick it up.

The board support is a large patch because of the ddr related code.
If it is not good, please first review/pick-up other patches if they
are ok.



Peng Fan (30):
  imx: add i.MX8M into Kconfig
  imx: mx8m: add register definition header file
  imx: mx8m: add pin header file
  time: add wait_mask_set/clr_timeout helper functions
  imx: mx8m: add clock driver
  imx: add sip function
  imx: boot_mode: add USB_BOOT entry
  imx: cpu: update cpu file to support i.MX8M
  imx: spl: implement spl_boot_device for i.MX8M
  imx: add i.MX8MQ SoC Revision and is_mx8m helper
  imx: add pad settings bit definition for i.MX8M
  imx: cpu: move speed/temp to common cpu
  imx: cpu: add cpu speed/grade for i.MX8M
  imx: refactor imx_get_mac_from_fuse
  imx: cleanup bootaux
  imx: bootaux: support i.MX8M
  imx: mx7: move get_boot_device to cpu.c
  imx: cpu: support get_boot_device for i.MX8M
  imx: mx7: move mmc env code to mmc_env.c
  imx: mx8m: add soc related settings and files
  imx: makefile: compile files for i.MX8M
  misc: ocotp: add i.MX8M support
  mmc: fsl_esdhc: support i.MX8M
  imx: lcdif: include i.MX8M
  gpio: mxc: add i.MX8M support
  net: fec: do not access reserved register for i.MX8M
  imx: imx8mq: add dtsi file
  power: pmic/regulator allow dm be omitted by SPL
  imx: mx8m: add ddr controller memory map
  imx: add i.MX8MQ EVK support

Tom Rini (1):
  arm: imx: Rework i.MX specific commands to be excluded from SPL

Ye Li (1):
  net: fec: fix build warnings for 64bits support

 arch/arm/Kconfig |   14 +-
 arch/arm/Makefile|4 +-
 arch/arm/dts/Makefile|2 +
 arch/arm/dts/fsl-imx8-ca53.dtsi  |   92 ++
 arch/arm/dts/fsl-imx8mq-evk.dts  |  424 +
 arch/arm/dts/fsl-imx8mq.dtsi |  429 +
 arch/arm/include/asm/arch-imx/cpu.h  |6 +-
 arch/arm/include/asm/arch-mx6/imx-regs.h |9 +-
 arch/arm/include/asm/arch-mx7/imx-regs.h |   18 +-
 arch/arm/include/asm/arch-mx8m/clock.h   |  657 ++
 arch/arm/include/asm/arch-mx8m/crm_regs.h|   10 +
 arch/arm/include/asm/arch-mx8m/ddr.h |  

[U-Boot] [PATCH V4 01/32] arm: imx: Rework i.MX specific commands to be excluded from SPL

[Peng Fan]

From: Tom Rini 

The "clocks" and "bootaux" commands are only usable in full U-Boot, not
SPL, so do not link them inside of SPL.  Rework a little of the bootaux
related code to make use of __weak and declare parts of it static as
it's local to the file.

Cc: Stefano Babic 
Cc: Fabio Estevam 
Signed-off-by: Tom Rini 
---
 arch/arm/mach-imx/Makefile   |  2 ++
 arch/arm/mach-imx/imx_bootaux.c  | 13 -
 arch/arm/mach-imx/mx5/clock.c|  4 +++-
 arch/arm/mach-imx/mx7/clock.c|  2 ++
 arch/arm/mach-imx/mx7ulp/clock.c |  2 ++
 5 files changed, 13 insertions(+), 10 deletions(-)

diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index d7966cfd4a..cf39d08bdd 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -28,7 +28,9 @@ obj-y += cache.o init.o
 obj-$(CONFIG_SATA) += sata.o
 obj-$(CONFIG_IMX_VIDEO_SKIP) += video.o
 obj-$(CONFIG_IMX_RDC) += rdc-sema.o
+ifneq ($(CONFIG_SPL_BUILD),y)
 obj-$(CONFIG_IMX_BOOTAUX) += imx_bootaux.o
+endif
 obj-$(CONFIG_SECURE_BOOT)+= hab.o
 obj-$(CONFIG_SYSCOUNTER_TIMER) += syscounter.o
 endif
diff --git a/arch/arm/mach-imx/imx_bootaux.c b/arch/arm/mach-imx/imx_bootaux.c
index 69026df763..b62dfbf6bf 100644
--- a/arch/arm/mach-imx/imx_bootaux.c
+++ b/arch/arm/mach-imx/imx_bootaux.c
@@ -6,27 +6,22 @@
 
 #include 
 #include 
+#include 
 
 /* Allow for arch specific config before we boot */
-static int __arch_auxiliary_core_up(u32 core_id, u32 boot_private_data)
+int __weak arch_auxiliary_core_up(u32 core_id, u32 boot_private_data)
 {
/* please define platform specific arch_auxiliary_core_up() */
return CMD_RET_FAILURE;
 }
 
-int arch_auxiliary_core_up(u32 core_id, u32 boot_private_data)
-   __attribute__((weak, alias("__arch_auxiliary_core_up")));
-
 /* Allow for arch specific config before we boot */
-static int __arch_auxiliary_core_check_up(u32 core_id)
+int __weak arch_auxiliary_core_check_up(u32 core_id)
 {
/* please define platform specific arch_auxiliary_core_check_up() */
return 0;
 }
 
-int arch_auxiliary_core_check_up(u32 core_id)
-   __attribute__((weak, alias("__arch_auxiliary_core_check_up")));
-
 /*
  * To i.MX6SX and i.MX7D, the image supported by bootaux needs
  * the reset vector at the head for the image, with SP and PC
@@ -40,7 +35,7 @@ int arch_auxiliary_core_check_up(u32 core_id)
  * The TCMUL is mapped to (M4_BOOTROM_BASE_ADDR) at A core side for
  * accessing the M4 TCMUL.
  */
-int do_bootaux(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+static int do_bootaux(cmd_tbl_t *cmdtp, int flag, int argc, char * const 
argv[])
 {
ulong addr;
int ret, up;
diff --git a/arch/arm/mach-imx/mx5/clock.c b/arch/arm/mach-imx/mx5/clock.c
index 610098c175..284f6d4cde 100644
--- a/arch/arm/mach-imx/mx5/clock.c
+++ b/arch/arm/mach-imx/mx5/clock.c
@@ -911,10 +911,11 @@ void mxc_set_sata_internal_clock(void)
 }
 #endif
 
+#ifndef CONFIG_SPL_BUILD
 /*
  * Dump some core clockes.
  */
-int do_mx5_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const 
argv[])
+static int do_mx5_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * 
const argv[])
 {
u32 freq;
 
@@ -947,3 +948,4 @@ U_BOOT_CMD(
"display clocks",
""
 );
+#endif
diff --git a/arch/arm/mach-imx/mx7/clock.c b/arch/arm/mach-imx/mx7/clock.c
index 8150faa1a3..c11042d6f5 100644
--- a/arch/arm/mach-imx/mx7/clock.c
+++ b/arch/arm/mach-imx/mx7/clock.c
@@ -1096,6 +1096,7 @@ void epdc_clock_disable(void)
 }
 #endif
 
+#ifndef CONFIG_SPL_BUILD
 /*
  * Dump some core clockes.
  */
@@ -1131,3 +1132,4 @@ U_BOOT_CMD(
"display clocks",
""
 );
+#endif
diff --git a/arch/arm/mach-imx/mx7ulp/clock.c b/arch/arm/mach-imx/mx7ulp/clock.c
index 77b282addd..553d62149d 100644
--- a/arch/arm/mach-imx/mx7ulp/clock.c
+++ b/arch/arm/mach-imx/mx7ulp/clock.c
@@ -323,6 +323,7 @@ void hab_caam_clock_enable(unsigned char enable)
 }
 #endif
 
+#ifndef CONFIG_SPL_BUILD
 /*
  * Dump some core clockes.
  */
@@ -363,3 +364,4 @@ U_BOOT_CMD(
"display clocks",
""
 );
+#endif
-- 
2.14.1

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [PATCH V3 00/31] imx: add i.MX8M support and i.MX8MQ EVK

[Peng Fan]

On Wed, Jan 10, 2018 at 12:13:42AM -0200, Fabio Estevam wrote:
>On Wed, Jan 10, 2018 at 12:09 AM, Fabio Estevam  wrote:
>
>> It would be better to generate the series against U-Boot 2018.11 master.
>
>2018.01 I mean :-)

ok. I'll post out V4 based on Tom's master tree with.
this https://patchwork.ozlabs.org/patch/855027/
"arm: imx: Rework i.MX specific commands to be excluded from SPL" applied.

Thanks,
Peng

-- 
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [PATCH v4 1/7] driver/ddr: Add support for setting timing in hws_topology_map

[Chris Packham]

Hi Marek,

On Sat, Jun 10, 2017 at 5:28 AM, Marek Behún  wrote:
> The DDR3 training code for Marvell A38X currently computes 1t timing
> when given board topology map of the Turris Omnia, but Omnia needs 2t.
>
> This patch adds support for enforcing the 2t timing in struct
> hws_topology_map, through a new enum hws_timing, which can assume
> following values:
>   HWS_TIM_DEFAULT - default behaviour, compute whether to enable 2t
> from the number of CSs
>   HWS_TIM_1T  - enforce 1t
>   HWS_TIM_2T  - enforce 2t
>
> This patch also sets all the board topology maps (db-88f6820-amc,
> db-88f6820-gp, controlcenterdc and clearfog) to have timing set to
> HWS_TIM_DEFAULT.
>
> Signed-off-by: Marek Behun 
> Reviewed-by: Stefan Roese 

Sorry for only noticing this now but I'd like to add to this
discussion that Marvell _unconditionally_ enable 2T mode in their
bootloader (personally I hope they adopt your change). This may be an
indication that we should set HWS_TIM_2T for the clearfog and
db-88f6820 boards.
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [PATCH 03/07] db410c: replace reset driver with psci

[Tuomas Tynkkynen]

Hi Jorge,

On 01/09/2018 11:12 AM, Jorge Ramirez-Ortiz wrote:

From: Jorge Ramirez-Ortiz 

this should be the norm for armv8 platforms.

Signed-off-by: Jorge Ramirez-Ortiz 
---
  arch/arm/dts/dragonboard410c.dts |  5 ---
  board/qualcomm/dragonboard410c/dragonboard410c.c |  5 +++
  configs/dragonboard410c_defconfig|  2 +-
  drivers/sysreset/Makefile|  2 --
  drivers/sysreset/sysreset_snapdragon.c   | 40 
  5 files changed, 6 insertions(+), 48 deletions(-)
  delete mode 100644 drivers/sysreset/sysreset_snapdragon.c

diff --git a/arch/arm/dts/dragonboard410c.dts b/arch/arm/dts/dragonboard410c.dts
index 25aeac4..b67e588 100644
--- a/arch/arm/dts/dragonboard410c.dts
+++ b/arch/arm/dts/dragonboard410c.dts
@@ -48,11 +48,6 @@
clock = < 4>;
};
  
-		restart@4ab000 {

-   compatible = "qcom,pshold";
-   reg = <0x4ab000 0x4>;
-   };
-
soc_gpios: pinctrl@100 {
compatible = "qcom,apq8016-pinctrl";
reg = <0x100 0x30>;
diff --git a/board/qualcomm/dragonboard410c/dragonboard410c.c 
b/board/qualcomm/dragonboard410c/dragonboard410c.c
index 99fc91b..8ef4338 100644
--- a/board/qualcomm/dragonboard410c/dragonboard410c.c
+++ b/board/qualcomm/dragonboard410c/dragonboard410c.c
@@ -171,3 +171,8 @@ int ft_board_setup(void *blob, bd_t *bd)
  
  	return 0;

  }
+
+void reset_cpu(ulong addr)
+{
+   psci_system_reset();
+}


I think you don't need to implement this boilerplate reset_cpu() function
if you just enable CONFIG_SYSRESET_PSCI. At least that works for qemu_arm.
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [PATCH V3 00/31] imx: add i.MX8M support and i.MX8MQ EVK

[Fabio Estevam]

On Wed, Jan 10, 2018 at 12:09 AM, Fabio Estevam  wrote:

> It would be better to generate the series against U-Boot 2018.11 master.

2018.01 I mean :-)
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [PATCH V3 00/31] imx: add i.MX8M support and i.MX8MQ EVK

[Fabio Estevam]

Hi Peng,

On Tue, Jan 9, 2018 at 10:55 PM, Peng Fan  wrote:

> As noted in cover-letter,
> This patchset based on https://patchwork.ozlabs.org/patch/855027/
> "arm: imx: Rework i.MX specific commands to be excluded from SPL" from
> Tom to avoid this patchset fail apply after Tom's patch merged.
>
> I use imx/master branch of Stefano's tree. Because of recent GPT_TIMER
> entry in arch/arm/mach-imx/Makefile, applying Tom's patch needs a small
> modification. After that, you could apply the whole patchset.

It would be better to generate the series against U-Boot 2018.11 master.

If there is any dependency on your series, then you can add such patch
as part of your series, so that people can cleanly apply the whole
series against 2018.01.

Thanks
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH v3 5/6] treewide: convert assert() to BUG_ON()

[Masahiro Yamada]

We do not need multiple ways to do the same thing.  Instead of
assert(), use BUG_ON() from Linux.  The logic is opposite, but
Coccinelle is of great help for such a conversion.  We could
simply convert assert(x) to BUG_ON(!x) for all expressions "x",
but I did a bit better job by converting assert(a == b) to
BUG_ON(a != b), etc.

The semantic patch I used is as follows:

// 

-assert(0)
+BUG()
@@
expression a;
@@
-assert((a))
+assert(a)
@@
expression a;
@@
-assert(a == 0)
+BUG_ON(a)
@@
expression a;
@@
-assert(a == NULL)
+BUG_ON(a)
@@
expression a;
@@
-assert(a != 0)
+BUG_ON(!a)
@@
expression a;
@@
-assert(a != NULL)
+BUG_ON(!a)
@@
expression a, b;
@@
-assert(a == b)
+BUG_ON(a != b)
@@
expression a, b;
@@
-assert(a != b)
+BUG_ON(a == b)
@@
expression a, b;
@@
-assert(a < b)
+BUG_ON(a >= b)
@@
expression a, b;
@@
-assert(a <= b)
+BUG_ON(a > b)
@@
expression a;
@@
-assert(!a)
+BUG_ON(a)
@@
expression a;
@@
-assert(a)
+BUG_ON(!a)
// 

Signed-off-by: Masahiro Yamada 
Reviewed-by: Simon Glass 
---

Changes in v3:
  - Re-run coccinelle based on v2017.01

Changes in v2:
 - Improve semantic patch and re-run coccinelle based on commit 02907004294d98

 arch/arm/mach-exynos/clock.c|  4 +-
 arch/arm/mach-tegra/clock.c | 10 ++--
 arch/arm/mach-tegra/pinmux-common.c | 80 +--
 arch/arm/mach-tegra/tegra114/clock.c| 10 ++--
 arch/arm/mach-tegra/tegra124/clock.c| 10 ++--
 arch/arm/mach-tegra/tegra20/clock.c | 14 ++---
 arch/arm/mach-tegra/tegra210/clock.c| 10 ++--
 arch/arm/mach-tegra/tegra30/clock.c | 10 ++--
 arch/sandbox/cpu/state.c|  4 +-
 arch/x86/cpu/intel_common/mrc.c |  2 +-
 arch/x86/lib/efi/efi.c  |  2 +-
 arch/x86/lib/fsp/fsp_support.c  |  6 +-
 arch/x86/lib/physmem.c  |  5 +-
 board/freescale/qemu-ppce500/qemu-ppce500.c |  8 +--
 cmd/bootefi.c   |  2 +-
 cmd/mtdparts.c  |  2 +-
 cmd/tpm_test.c  | 28 +-
 common/dlmalloc.c   | 86 ++---
 common/fdt_support.c|  2 +-
 common/hwconfig.c   | 36 ++--
 drivers/clk/clk-uclass.c|  2 +-
 drivers/clk/rockchip/clk_rk3036.c   | 23 
 drivers/clk/rockchip/clk_rk3128.c   | 27 -
 drivers/clk/rockchip/clk_rk3188.c   | 28 --
 drivers/clk/rockchip/clk_rk322x.c   | 23 
 drivers/clk/rockchip/clk_rk3288.c   | 36 +---
 drivers/clk/rockchip/clk_rk3328.c   |  8 +--
 drivers/clk/rockchip/clk_rk3368.c   |  4 +-
 drivers/clk/rockchip/clk_rk3399.c   | 51 +++--
 drivers/clk/rockchip/clk_rv1108.c   |  2 +-
 drivers/core/device-remove.c|  8 +--
 drivers/core/device.c   |  2 +-
 drivers/core/ofnode.c   | 24 
 drivers/core/uclass.c   |  4 +-
 drivers/gpio/gpio-uclass.c  |  2 +-
 drivers/i2c/i2c-uclass.c|  2 +-
 drivers/input/input.c   |  4 +-
 drivers/input/key_matrix.c  |  2 +-
 drivers/misc/cros_ec.c  | 10 ++--
 drivers/misc/cros_ec_i2c.c  |  4 +-
 drivers/mtd/nand/tegra_nand.c   |  2 +-
 drivers/mtd/spi/sandbox.c   |  4 +-
 drivers/net/fsl-mc/mc.c |  2 +-
 drivers/phy/phy-uclass.c|  2 +-
 drivers/power/tps6586x.c|  4 +-
 drivers/rtc/rtc-uclass.c| 10 ++--
 drivers/sound/sound.c   |  2 +-
 drivers/spi/exynos_spi.c|  6 +-
 drivers/usb/emul/sandbox_flash.c|  2 +-
 drivers/usb/host/usb-uclass.c   |  4 +-
 drivers/video/stb_truetype.h|  2 +-
 fs/ext4/dev.c   |  2 +-
 fs/ext4/ext4_common.c   |  2 +-
 fs/ext4/ext4_journal.c  |  2 +-
 fs/fat/fat.c|  2 +-
 include/dm/ofnode.h |  4 +-
 include/efi_loader.h| 12 ++--
 lib/circbuf.c   | 16 +++---
 lib/efi_loader/efi_boottime.c   |  2 +-
 lib/efi_loader/efi_device_path.c|  2 +-
 lib/efi_loader/efi_file.c   |  2 +-
 lib/efi_loader/efi_memory.c |  2 +-
 lib/fdtdec.c|  8 +--
 lib/membuff.c   |  4 +-
 lib/physmem.c   |  4 +-
 lib/qsort.c |  2 +-
 lib/slre.c  |  8 +--
 net/eth-uclass.c|  2 +-
 net/eth_legacy.c

[U-Boot] [PATCH v3 0/6] assert() is almost used in the same way as BUG_ON(), except:

[Masahiro Yamada]

  - the logic is opposite
  - currently, assert() is compiled only when DEBUG is defined

Coccinelle can easily convert assert() to BUG_ON().

A problem is it would grow the image size.
In v2, I introduced a new CONFIG option to allow to disable it.

In v3, it is default 'y'.  I disabled it only for openrd boards.


Masahiro Yamada (6):
  Enable CONFIG_PANIC_HANG for boards without do_reset()
  usb: xhci: return ERR_PTR(-ETIMEDOUT) at the end of
xhci_wait_for_event()
  Introduce CONFIG_BUG_CHECKS to allow to disable BUG{_ON} and WARN_ON
  ARM: openrd: disable CONFIG_BUG_CHECKS
  treewide: convert assert() to BUG_ON()
  Remove assert()

 arch/arm/mach-exynos/clock.c|  4 +-
 arch/arm/mach-tegra/clock.c | 10 ++--
 arch/arm/mach-tegra/pinmux-common.c | 80 +--
 arch/arm/mach-tegra/tegra114/clock.c| 10 ++--
 arch/arm/mach-tegra/tegra124/clock.c| 10 ++--
 arch/arm/mach-tegra/tegra20/clock.c | 14 ++---
 arch/arm/mach-tegra/tegra210/clock.c| 10 ++--
 arch/arm/mach-tegra/tegra30/clock.c | 10 ++--
 arch/sandbox/cpu/state.c|  4 +-
 arch/x86/cpu/intel_common/mrc.c |  2 +-
 arch/x86/lib/efi/efi.c  |  2 +-
 arch/x86/lib/fsp/fsp_support.c  |  6 +-
 arch/x86/lib/physmem.c  |  5 +-
 board/freescale/qemu-ppce500/qemu-ppce500.c |  8 +--
 cmd/bootefi.c   |  2 +-
 cmd/mtdparts.c  |  2 +-
 cmd/tpm_test.c  | 28 +-
 common/dlmalloc.c   | 86 ++---
 common/fdt_support.c|  2 +-
 common/hwconfig.c   | 36 ++--
 configs/cl-som-imx7_defconfig   |  1 +
 configs/evb-rk3229_defconfig|  1 +
 configs/mccmon6_sd_defconfig|  1 +
 configs/openrd_base_defconfig   |  1 +
 configs/openrd_client_defconfig |  1 +
 configs/openrd_ultimate_defconfig   |  1 +
 configs/opos6uldev_defconfig|  1 +
 drivers/clk/clk-uclass.c|  2 +-
 drivers/clk/rockchip/clk_rk3036.c   | 23 
 drivers/clk/rockchip/clk_rk3128.c   | 27 -
 drivers/clk/rockchip/clk_rk3188.c   | 28 --
 drivers/clk/rockchip/clk_rk322x.c   | 23 
 drivers/clk/rockchip/clk_rk3288.c   | 36 +---
 drivers/clk/rockchip/clk_rk3328.c   |  8 +--
 drivers/clk/rockchip/clk_rk3368.c   |  4 +-
 drivers/clk/rockchip/clk_rk3399.c   | 51 +++--
 drivers/clk/rockchip/clk_rv1108.c   |  2 +-
 drivers/core/device-remove.c|  8 +--
 drivers/core/device.c   |  2 +-
 drivers/core/ofnode.c   | 24 
 drivers/core/uclass.c   |  4 +-
 drivers/gpio/gpio-uclass.c  |  2 +-
 drivers/i2c/i2c-uclass.c|  2 +-
 drivers/input/input.c   |  4 +-
 drivers/input/key_matrix.c  |  2 +-
 drivers/misc/cros_ec.c  | 10 ++--
 drivers/misc/cros_ec_i2c.c  |  4 +-
 drivers/mtd/nand/tegra_nand.c   |  2 +-
 drivers/mtd/spi/sandbox.c   |  4 +-
 drivers/net/fsl-mc/mc.c |  2 +-
 drivers/phy/phy-uclass.c|  2 +-
 drivers/power/tps6586x.c|  4 +-
 drivers/rtc/rtc-uclass.c| 10 ++--
 drivers/sound/sound.c   |  2 +-
 drivers/spi/exynos_spi.c|  6 +-
 drivers/usb/emul/sandbox_flash.c|  2 +-
 drivers/usb/host/usb-uclass.c   |  4 +-
 drivers/usb/host/xhci-ring.c|  7 +++
 drivers/video/stb_truetype.h|  2 +-
 fs/ext4/dev.c   |  2 +-
 fs/ext4/ext4_common.c   |  2 +-
 fs/ext4/ext4_journal.c  |  2 +-
 fs/fat/fat.c|  2 +-
 include/dm/ofnode.h |  4 +-
 include/efi_loader.h| 12 ++--
 include/linux/bug.h |  9 ++-
 include/log.h   | 15 -
 lib/Kconfig |  9 +++
 lib/circbuf.c   | 16 +++---
 lib/efi_loader/efi_boottime.c   |  2 +-
 lib/efi_loader/efi_device_path.c|  2 +-
 lib/efi_loader/efi_file.c   |  2 +-
 lib/efi_loader/efi_memory.c |  2 +-
 lib/fdtdec.c|  8 +--
 lib/membuff.c   |  4 +-
 lib/physmem.c   |  4 +-
 lib/qsort.c |  2 +-
 lib/slre.c  |  8 +--
 lib/tiny-printf.c   |  9 ---
 

[U-Boot] [PATCH v3 3/6] Introduce CONFIG_BUG_CHECKS to allow to disable BUG{_ON} and WARN_ON

[Masahiro Yamada]

BUG(), BUG_ON(), WARN_ON(), etc. are generally used to test a condition
that should never happen.  If it does, it is a bug, then they print
noisy messages.

They are useful to catch bugs, and Linux always enables them, but doing
so in U-Boot causes image size problems on some platforms.

Introduce CONFIG_BUG_CHECKS to switch this feature.  It is enabled by
default since it is the current behavior.  Disable it if your platform
needs to save memory footprint.

Suggested-by: Tom Rini 
Signed-off-by: Masahiro Yamada 
Reviewed-by: Simon Glass 
---

Changes in v3:
  - Flip the default to 'y'
  - Rename CONFIG_ENABLE_BUG_CHECKS to CONFIG_BUG_CHECKS
because I thought "ENABLE" was not a necessary word
  - define to "do {} while (0)"

Changes in v2:
  - Newly added

 include/linux/bug.h | 9 -
 lib/Kconfig | 9 +
 2 files changed, 17 insertions(+), 1 deletion(-)

diff --git a/include/linux/bug.h b/include/linux/bug.h
index f07bb71..045e639 100644
--- a/include/linux/bug.h
+++ b/include/linux/bug.h
@@ -6,17 +6,24 @@
 #include 
 #include 
 
+#ifdef CONFIG_BUG_CHECKS
 #define BUG() do { \
printk("BUG at %s:%d/%s()!\n", __FILE__, __LINE__, __func__); \
panic("BUG!"); \
 } while (0)
+#define __WARN()   \
+   printk("WARNING at %s:%d/%s()!\n", __FILE__, __LINE__, __func__)
+#else
+#define BUG()  do {} while (0)
+#define __WARN()   do {} while (0)
+#endif
 
 #define BUG_ON(condition) do { if (unlikely(condition)) BUG(); } while (0)
 
 #define WARN_ON(condition) ({  \
int __ret_warn_on = !!(condition);  \
if (unlikely(__ret_warn_on))\
-   printk("WARNING at %s:%d/%s()!\n", __FILE__, __LINE__, 
__func__); \
+   __WARN();   \
unlikely(__ret_warn_on);\
 })
 
diff --git a/lib/Kconfig b/lib/Kconfig
index 00ac650..dee5dc2 100644
--- a/lib/Kconfig
+++ b/lib/Kconfig
@@ -45,6 +45,15 @@ config USE_TINY_PRINTF
 
  The supported format specifiers are %c, %s, %u/%d and %x.
 
+config BUG_CHECKS
+   bool "Enable BUG/BUG_ON() checks and WARN_ON() logs"
+   default y
+   help
+ BUG(), BUG_ON(), and WARN_ON() print noisy messages.  BUG() and
+ BUG_ON() also reboot or halt the system.
+
+ Disable this if your platform needs to save memory footprint.
+
 config PANIC_HANG
bool "Do not reset the system on fatal error"
help
-- 
2.7.4

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH v3 2/6] usb: xhci: return ERR_PTR(-ETIMEDOUT) at the end of xhci_wait_for_event()

[Masahiro Yamada]

xhci_wait_for_event() is supposed to return a pointer to union xhci_trb,
but it does not return anything at the end of the function.

This relies on that the end of the function is unreachable due to BUG().

We are planning to make BUG() no-op for platforms with strong image size
constraint.  Doing so would cause compiler warning:

drivers/usb/host/xhci-ring.c:475:1: warning: control reaches end of non-void 
function [-Wreturn-type]
 }
 ^

So, this function must return something.  From the error message just
above, ERR_PTR(-ETIMEDOUT) seems a good choice.

The use of BUG() looks suspicious here in the first place; no response
from hardware is not a bug.  It should be treated as a normal error.
So, this function must return an error pointer instead of BUG(), then
the caller must handle it properly.

I am not fixing the code because this is not the only place that stops
the system.  Just one failure of xHCI halts the system, here and there.

I left a comment block, hoping somebody will take a look.

Signed-off-by: Masahiro Yamada 
---

Changes in v3:
  - newly added

Changes in v2: None

 drivers/usb/host/xhci-ring.c | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/drivers/usb/host/xhci-ring.c b/drivers/usb/host/xhci-ring.c
index 579e670..d780367 100644
--- a/drivers/usb/host/xhci-ring.c
+++ b/drivers/usb/host/xhci-ring.c
@@ -471,7 +471,14 @@ union xhci_trb *xhci_wait_for_event(struct xhci_ctrl 
*ctrl, trb_type expected)
return NULL;
 
printf("XHCI timeout on event type %d... cannot recover.\n", expected);
+
+   /*
+* CHECK:
+* Is this software bug?  Is this a good reason to halt the system?
+*/
BUG();
+
+   return ERR_PTR(-ETIMEDOUT);
 }
 
 /*
-- 
2.7.4

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH v3 6/6] Remove assert()

[Masahiro Yamada]

No more users of assert() except host tools.  Remove.

Signed-off-by: Masahiro Yamada 
Reviewed-by: Simon Glass 
---

Changes in v3:
 - Rebase on v2017.01

Changes in v2: None

 include/log.h | 15 ---
 lib/tiny-printf.c |  9 -
 lib/vsprintf.c|  9 -
 3 files changed, 33 deletions(-)

diff --git a/include/log.h b/include/log.h
index 8083b64..60a77c4 100644
--- a/include/log.h
+++ b/include/log.h
@@ -141,21 +141,6 @@ int _log(enum log_category_t cat, enum log_level_t level, 
const char *file,
 #define warn_non_spl(fmt, args...) \
debug_cond(!_SPL_BUILD, fmt, ##args)
 
-/*
- * An assertion is run-time check done in debug mode only. If DEBUG is not
- * defined then it is skipped. If DEBUG is defined and the assertion fails,
- * then it calls panic*( which may or may not reset/halt U-Boot (see
- * CONFIG_PANIC_HANG), It is hoped that all failing assertions are found
- * before release, and after release it is hoped that they don't matter. But
- * in any case these failing assertions cannot be fixed with a reset (which
- * may just do the same assertion again).
- */
-void __assert_fail(const char *assertion, const char *file, unsigned int line,
-  const char *function);
-#define assert(x) \
-   ({ if (!(x) && _DEBUG) \
-   __assert_fail(#x, __FILE__, __LINE__, __func__); })
-
 /**
  * struct log_rec - a single log record
  *
diff --git a/lib/tiny-printf.c b/lib/tiny-printf.c
index 0b04813..d5b6d69 100644
--- a/lib/tiny-printf.c
+++ b/lib/tiny-printf.c
@@ -381,12 +381,3 @@ int snprintf(char *buf, size_t size, const char *fmt, ...)
 
return ret;
 }
-
-void __assert_fail(const char *assertion, const char *file, unsigned line,
-  const char *function)
-{
-   /* This will not return */
-   printf("%s:%u: %s: Assertion `%s' failed.", file, line, function,
-  assertion);
-   hang();
-}
diff --git a/lib/vsprintf.c b/lib/vsprintf.c
index dd572d2..4208239 100644
--- a/lib/vsprintf.c
+++ b/lib/vsprintf.c
@@ -789,15 +789,6 @@ int vprintf(const char *fmt, va_list args)
return i;
 }
 
-
-void __assert_fail(const char *assertion, const char *file, unsigned line,
-  const char *function)
-{
-   /* This will not return */
-   panic("%s:%u: %s: Assertion `%s' failed.", file, line, function,
- assertion);
-}
-
 char *simple_itoa(ulong i)
 {
/* 21 digits plus null terminator, good for 64-bit or smaller ints */
-- 
2.7.4

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH v3 1/6] Enable CONFIG_PANIC_HANG for boards without do_reset()

[Masahiro Yamada]

Calling panic() for these boards causes build error:
  undefined reference to `do_reset'

They must compile do_reset(), or define CONFIG_PANIC_HANG.

Signed-off-by: Masahiro Yamada 
Reviewed-by: Simon Glass 
---

Changes in v3: None
Changes in v2: None

 configs/cl-som-imx7_defconfig | 1 +
 configs/evb-rk3229_defconfig  | 1 +
 configs/mccmon6_sd_defconfig  | 1 +
 configs/opos6uldev_defconfig  | 1 +
 4 files changed, 4 insertions(+)

diff --git a/configs/cl-som-imx7_defconfig b/configs/cl-som-imx7_defconfig
index d37c82c..150396f 100644
--- a/configs/cl-som-imx7_defconfig
+++ b/configs/cl-som-imx7_defconfig
@@ -51,3 +51,4 @@ CONFIG_USB_STORAGE=y
 CONFIG_USB_GADGET=y
 CONFIG_CI_UDC=y
 CONFIG_OF_LIBFDT=y
+CONFIG_PANIC_HANG=y
diff --git a/configs/evb-rk3229_defconfig b/configs/evb-rk3229_defconfig
index b226f66..21c1bfd 100644
--- a/configs/evb-rk3229_defconfig
+++ b/configs/evb-rk3229_defconfig
@@ -48,3 +48,4 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x2207
 CONFIG_USB_GADGET_PRODUCT_NUM=0x320a
 CONFIG_USB_GADGET_DWC2_OTG=y
 CONFIG_ERRNO_STR=y
+CONFIG_PANIC_HANG=y
diff --git a/configs/mccmon6_sd_defconfig b/configs/mccmon6_sd_defconfig
index 97f7f9a..3f00ead 100644
--- a/configs/mccmon6_sd_defconfig
+++ b/configs/mccmon6_sd_defconfig
@@ -44,3 +44,4 @@ CONFIG_DM_THERMAL=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
 CONFIG_OF_LIBFDT=y
+CONFIG_PANIC_HANG=y
diff --git a/configs/opos6uldev_defconfig b/configs/opos6uldev_defconfig
index 0149ae3..51ebc73 100644
--- a/configs/opos6uldev_defconfig
+++ b/configs/opos6uldev_defconfig
@@ -84,3 +84,4 @@ CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_VIDEO=y
 CONFIG_OF_LIBFDT_OVERLAY=y
 # CONFIG_EFI_LOADER is not set
+CONFIG_PANIC_HANG=y
-- 
2.7.4

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH v3 4/6] ARM: openrd: disable CONFIG_BUG_CHECKS

[Masahiro Yamada]

These boards are always on the boundary of "u-boot-nodtb.bin exceeds
file size limit" error.

Commit ab5502bf561b ("ARM: openrd: set CONFIG_LOGLEVEL to 2") reduced
the loglevel to save memory footprint.

They are hitting the size limit, again.  Disable CONFIG_BUG_CHECKS.

Signed-off-by: Masahiro Yamada 
---

Changes in v3:
  - newly added

Changes in v2: None

 configs/openrd_base_defconfig | 1 +
 configs/openrd_client_defconfig   | 1 +
 configs/openrd_ultimate_defconfig | 1 +
 3 files changed, 3 insertions(+)

diff --git a/configs/openrd_base_defconfig b/configs/openrd_base_defconfig
index 1a829b7..17c915e 100644
--- a/configs/openrd_base_defconfig
+++ b/configs/openrd_base_defconfig
@@ -29,4 +29,5 @@ CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_STORAGE=y
+# CONFIG_BUG_CHECKS is not set
 CONFIG_OF_LIBFDT=y
diff --git a/configs/openrd_client_defconfig b/configs/openrd_client_defconfig
index 7a95b5b..5e234dd 100644
--- a/configs/openrd_client_defconfig
+++ b/configs/openrd_client_defconfig
@@ -29,4 +29,5 @@ CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_STORAGE=y
+# CONFIG_BUG_CHECKS is not set
 CONFIG_OF_LIBFDT=y
diff --git a/configs/openrd_ultimate_defconfig 
b/configs/openrd_ultimate_defconfig
index 757be16..d51b614 100644
--- a/configs/openrd_ultimate_defconfig
+++ b/configs/openrd_ultimate_defconfig
@@ -29,4 +29,5 @@ CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_STORAGE=y
+# CONFIG_BUG_CHECKS is not set
 CONFIG_OF_LIBFDT=y
-- 
2.7.4

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [PATCH V3 00/31] imx: add i.MX8M support and i.MX8MQ EVK

[Peng Fan]

Hi Diego,

On Tue, Jan 09, 2018 at 03:42:29PM -0200, Diego Dorta wrote:
>Hi peng,
>
>2018-01-09 10:11 GMT-02:00 Peng Fan :
>> This patchset is to add i.MX8M and i.MX8MQ-EVK support
>>
>> V3:
>>  This patchset based on https://patchwork.ozlabs.org/patch/855027/
>>  "arm: imx: Rework i.MX specific commands to be excluded from SPL" from
>>  Tom to avoid this patchset fail apply after Tom's patch merged.
>>
>>  Previously "power: pmic/regulator allow dm be omited by SPL" broke other
>>  boards, in V3 patchset, only touch pfuze100 related options.
>>
>>  Sharing code about get mac from fuse between mx7/mx8m
>>  Sharing code about bootaux between mx6/7/mx8m
>>  Sharing code about cpu speed grade between mx7/mx8m
>>  Sharing code about get boot device between mx7/mx8m
>>  Sharding code about mmc env between mx7/mx8m
>>
>>  Introduce wait_mask_set/clr_timeout to avoid deadloop in clock pll 
>> configuration
>>
>>  Correct authorship of fix building warning on fec arm64, patch 27/31.
>>
>>  Switch to use structure for DDR Controller. For DDR PHY registers,
>>  there are about more than 10 thousands registers, I could not convert
>>  them with detailed register name, and the script is generated from IC team,
>>  So I use regs[0x] arrays here fo easily converting between IC team
>>  released script and uboot ddr phy cod.
>>
>>  Improve REAMME file to include where to download firmware and imx-mkimage
>>  and how to build
>>
>>  Add review tags on the V2 patchset.
>>
>>  Hope this patchset could catch up next release :)
>>
>> V2:
>>
>>  patch 02/23: convert to structure, drop is_boot_from_usb and
>>   disconnect_from_usb
>>  patch 04/23: conver to use structure for the clock driver, removed the
>>   CCM_xxx macros. Add static for local functons.
>>   Add init_usdhc_clk, init_uart_clk and etc to not enable
>>   them all at default.
>>  patch 05/23: Add more commit msg for the sip part.
>>  patch 08/23: Merge the spl boot device with i.MX7
>>  patch 12/23: Typo fix and return error fix from Heiko for the SoC related 
>> part
>>  patch 22/23: Use a weak function ddr_init. If patch 23/23 could not be
>>   accepted at current stage, to make others still be could be
>>   compiled.
>>
>> The patchset depends on
>> https://patchwork.ozlabs.org/patch/841934/
>> https://patchwork.ozlabs.org/patch/841958/
>> to be tested on real hardware.
>>
>> V1:
>>
>> patch: "power: pmic.h: include dm/ofnode.h" and
>> "power: pmic/regulator allow dm be omited by SPL" is previously reviewed
>> in mailist to not merged. If no issue, you may pick it up.
>>
>> The board support is a large patch because of the ddr related code.
>> If it is not good, please first review/pick-up other patches if they
>> are ok.
>>
>> Peng Fan (30):
>>   imx: add i.MX8M into Kconfig
>>   imx: mx8m: add register definition header file
>>   imx: mx8m: add pin header file
>>   time: add wait_mask_set/clr_timeout helper functions
>>   imx: mx8m: add clock driver
>>   imx: add sip function
>>   imx: boot_mode: add USB_BOOT entry
>>   imx: cpu: update cpu file to support i.MX8M
>>   imx: spl: implement spl_boot_device for i.MX8M
>>   imx: add i.MX8MQ SoC Revision and is_mx8m helper
>>   imx: add pad settings bit definition for i.MX8M
>>   imx: cpu: move speed/temp to common cpu
>>   imx: cpu: add cpu speed/grade for i.MX8M
>>   imx: refactor imx_get_mac_from_fuse
>>   imx: cleanup bootaux
>>   imx: bootaux: support i.MX8M
>>   imx: mx7: move get_boot_device to cpu.c
>>   imx: cpu: support get_boot_device for i.MX8M
>>   imx: mx7: move mmc env code to mmc_env.c
>>   imx: mx8m: add soc related settings and files
>>   imx: makefile: compile files for i.MX8M
>>   misc: ocotp: add i.MX8M support
>>   mmc: fsl_esdhc: support i.MX8M
>>   imx: lcdif: include i.MX8M
>>   gpio: mxc: add i.MX8M support
>>   net: fec: do not access reserved register for i.MX8M
>>   imx: imx8mq: add dtsi file
>>   power: pmic/regulator allow dm be omitted by SPL
>>   imx: mx8m: add ddr controller memory map
>>   imx: add i.MX8MQ EVK support
>
>I've tried to apply your patches on v2018.01 and I got this error:
>
>u-boot$ git am imx-add-i.MX8M-support-and-i.MX8MQ-EVK.patch
>Applying: imx: add i.MX8M into Kconfig
>Applying: imx: mx8m: add register definition header file
>Applying: imx: mx8m: add pin header file
>Applying: time: add wait_mask_set/clr_timeout helper functions
>Applying: imx: mx8m: add clock driver
>Applying: imx: add sip function
>Applying: imx: boot_mode: add USB_BOOT entry
>Applying: imx: cpu: update cpu file to support i.MX8M
>Applying: imx: spl: implement spl_boot_device for i.MX8M
>Applying: imx: add i.MX8MQ SoC Revision and is_mx8m helper
>Applying: imx: add pad settings bit definition for i.MX8M
>Applying: imx: cpu: move speed/temp to common cpu
>Applying: imx: cpu: add cpu speed/grade for i.MX8M
>Applying: imx: refactor imx_get_mac_from_fuse
>error: patch failed: 

Re: [U-Boot] [PATCH v2 06/16] efi: sandbox: Adjust memory usage for sandbox

[Heinrich Schuchardt]

On 12/04/2017 10:28 PM, Simon Glass wrote:
> With sandbox the U-Boot code is not mapped into the sandbox memory range
> so does not need to be excluded when allocating EFI memory. Update the EFI
> memory init code to take account of that.
> 
> Also use mapmem instead of a cast to convert a memory address to a
> pointer.
> 
> Signed-off-by: Simon Glass 
> ---
> 
> Changes in v2:
> - Update to use mapmem instead of a cast
> 
>  lib/efi_loader/efi_memory.c | 31 ++-
>  1 file changed, 18 insertions(+), 13 deletions(-)
> 
> diff --git a/lib/efi_loader/efi_memory.c b/lib/efi_loader/efi_memory.c
> index e95896ca0a..3ad58d8930 100644
> --- a/lib/efi_loader/efi_memory.c
> +++ b/lib/efi_loader/efi_memory.c
> @@ -10,6 +10,7 @@
>  #include 
>  #include 
>  #include 
> +#include 
>  #include 
>  #include 
>  #include 
> @@ -366,7 +367,7 @@ efi_status_t efi_allocate_pool(int pool_type, unsigned 
> long size,
>   r = efi_allocate_pages(0, pool_type, num_pages, );
>  
>   if (r == EFI_SUCCESS) {
> - struct efi_pool_allocation *alloc = (void *)(uintptr_t)t;
> + struct efi_pool_allocation *alloc = map_sysmem(t, size);
>   alloc->num_pages = num_pages;
>   *buffer = alloc->data;
>   }
> @@ -460,18 +461,22 @@ int efi_memory_init(void)
>  
>   efi_add_known_memory();
>  
> - /* Add U-Boot */
> - uboot_start = (gd->start_addr_sp - uboot_stack_size) & ~EFI_PAGE_MASK;
> - uboot_pages = (gd->ram_top - uboot_start) >> EFI_PAGE_SHIFT;
> - efi_add_memory_map(uboot_start, uboot_pages, EFI_LOADER_DATA, false);
> -
> - /* Add Runtime Services */
> - runtime_start = (ulong)&__efi_runtime_start & ~EFI_PAGE_MASK;
> - runtime_end = (ulong)&__efi_runtime_stop;
> - runtime_end = (runtime_end + EFI_PAGE_MASK) & ~EFI_PAGE_MASK;
> - runtime_pages = (runtime_end - runtime_start) >> EFI_PAGE_SHIFT;
> - efi_add_memory_map(runtime_start, runtime_pages,
> -EFI_RUNTIME_SERVICES_CODE, false);
> + if (!IS_ENABLED(CONFIG_SANDBOX)) {
> + /* Add U-Boot */
> + uboot_start = (gd->start_addr_sp - uboot_stack_size) &
> + ~EFI_PAGE_MASK;
> + uboot_pages = (gd->ram_top - uboot_start) >> EFI_PAGE_SHIFT;
> + efi_add_memory_map(uboot_start, uboot_pages, EFI_LOADER_DATA,
> +false);
> +
> + /* Add Runtime Services */
> + runtime_start = (ulong)&__efi_runtime_start & ~EFI_PAGE_MASK;
> + runtime_end = (ulong)&__efi_runtime_stop;
> + runtime_end = (runtime_end + EFI_PAGE_MASK) & ~EFI_PAGE_MASK;
> + runtime_pages = (runtime_end - runtime_start) >> EFI_PAGE_SHIFT;
> + efi_add_memory_map(runtime_start, runtime_pages,
> +EFI_RUNTIME_SERVICES_CODE, false);
> + }
>  
>  #ifdef CONFIG_EFI_LOADER_BOUNCE_BUFFER
>   /* Request a 32bit 64MB bounce buffer region */
> 

bootefi selftest shows an error. You should setup the EFI memory for
CONFIG_SANDBOX=y too.

Setting up 'ExitBootServices'
Setting up 'ExitBootServices' succeeded
lib/efi_selftest/efi_selftest.c(53):
ERROR: GetMemoryMap did not return EFI_SUCCESS

Best regards

Heinrich
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot