Re: [U-Boot] [PATCH] vxworks: fixed cpu enable using PSCI on armv8

[Bin Meng]

Hi Vasyl,

On Wed, Mar 28, 2018 at 3:29 AM, Vasyl Vavrychuk  wrote:
> Without armv8_setup_psci register VBAR_EL3 is not set up property which
> makes SMC calls jump to invalid location.
>
> smp_kick_all_cpus is required to make slave cpus leave gic_wait_for_interrupt.
> Without this they will never pursue booting process.
>
> This implementation is very similiar to what is done in boot_jump_linux
> in arch/arm/lib/bootm.c file.
>
> Tested on VxWorks 7 release SR0520 2017-12-08.
>

On what board?

As I mentioned before, why do you want to use 'bootvx' to boot a
VxWorks 7 kernel? I believe VxWorks 7 ARM kernel is loaded via
'bootm'. See doc/README.vxworks.

> Signed-off-by: Vasyl Vavrychuk 
> ---
>  cmd/elf.c | 5 +
>  1 file changed, 5 insertions(+)
>
> diff --git a/cmd/elf.c b/cmd/elf.c
> index 5745a389da..db690fc619 100644
> --- a/cmd/elf.c
> +++ b/cmd/elf.c
> @@ -372,6 +372,11 @@ int do_bootvx(cmd_tbl_t *cmdtp, int flag, int argc, char 
> * const argv[])
> printf("## Starting vxWorks at 0x%08lx ...\n", addr);
>
> dcache_disable();
> +#if defined(CONFIG_ARM64) && defined(CONFIG_ARMV8_PSCI)
> +   armv8_setup_psci();
> +   smp_kick_all_cpus();

What about ARMv8 32-bit? What about ARMv7? Should we call
smp_kick_all_cpus() for ARMv7 as well? Seems to me the logic of
#ifdefs here needs to be tuned.

> +#endif
> +
>  #ifdef CONFIG_X86
> /* VxWorks on x86 uses stack to pass parameters */
> ((asmlinkage void (*)(int))addr)(0);
> --

Regards,
Bin
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Re: [U-Boot] [PATCH 22/36] rockchip: dts: rk3288: update spl-boot-order

[Kever Yang]

Hi Peter,


On 03/27/2018 07:55 PM, Peter Robinson wrote:
> On Tue, Mar 27, 2018 at 10:29 AM, Kever Yang  
> wrote:
>> Use "uboot,spl-boot-orde" instead of "uboot,boot0".
> I think these should be in *-u-boot.dtsi files, 

Yes, you are right about this, and move all this u-boot configs into
*-u-boot.dtsi files is also one of my TODO clean up jobs.

I didn't do this now because of the frame work do not fit what we
already have now.

@Simon, @Philipp,
Here is what I want to do:
- I think in most case, all the boards with same SoC shares the U-Boot
configs,
  eg. it's better to have one rk3288-u-boot.dtsi instead of 12
rk3288-xxboard-u-boot.dtsi
- The build system supports to automatic add x-u-boot.dtsi(feature add
by Simon),
    the x could be:
   -u-boot.dtsi where  is the base name of the .dts
file 
  
-u-boot.dtsi

  
-u-boot.dtsi   

  
-u-boot.dtsi

So use CONFIG_SYS_SOC-u-boot.dtsi should be the best choice.
- But we can't use it because the value is always "rockchip"
- we can not change this into a real soc name because:
   There is a symbolic link "arch/${ARCH}/include/asm/arch" for header
file pointing to
   the SoC/CPU specific header directory; and all rockchip headers are
locate at
    arch/arm/include/asm/arch-rockchip/, including many common header
files and
    soc specific files.
- Are we going to add arch-rk3xxx folder for each soc like arch-mxx and
arch-tegraxxx,
  and copy the common header files into each soc directory? Is there
other solution?

Thanks,
- Kever
> that enables easy sync
> between the linux kernel dts files and u-boot like done on a number of
> other configs, a couple of the rk3368 devices seem to already use this
> as does devices like AllWinner
>
>> Signed-off-by: Kever Yang 
>> ---
>>
>>  arch/arm/dts/rk3288-phycore-rdk.dts | 6 +-
>>  arch/arm/dts/rk3288-veyron.dtsi | 6 +-
>>  2 files changed, 2 insertions(+), 10 deletions(-)
>>
>> diff --git a/arch/arm/dts/rk3288-phycore-rdk.dts 
>> b/arch/arm/dts/rk3288-phycore-rdk.dts
>> index f2bb7b5..3bf8efb 100644
>> --- a/arch/arm/dts/rk3288-phycore-rdk.dts
>> +++ b/arch/arm/dts/rk3288-phycore-rdk.dts
>> @@ -53,11 +53,7 @@
>>
>> chosen {
>> stdout-path = 
>> -   };
>> -
>> -   config {
>> -   u-boot,dm-pre-reloc;
>> -   u-boot,boot0 = 
>> +   u-boot,spl-boot-order = 
>> };
>>
>> user_buttons: user-buttons {
>> diff --git a/arch/arm/dts/rk3288-veyron.dtsi 
>> b/arch/arm/dts/rk3288-veyron.dtsi
>> index a314058..77b9bf8 100644
>> --- a/arch/arm/dts/rk3288-veyron.dtsi
>> +++ b/arch/arm/dts/rk3288-veyron.dtsi
>> @@ -17,11 +17,7 @@
>>
>> chosen {
>> stdout-path = 
>> -   };
>> -
>> -   config {
>> -   u-boot,dm-pre-reloc;
>> -   u-boot,boot0 = _flash;
>> +   u-boot,spl-boot-order = _flash;
>> };
>>
>> firmware {
>> --
>> 1.9.1
>>
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Re: [U-Boot] [PATCH 26/36] rockchip: rk1108: remove rockchip timer for sys timer

[Kever Yang]

Hi Alexander,


On 03/28/2018 12:21 AM, Alexander Kochetkov wrote:
> The question is: does rk3066 and rk3188 have arch timer? If no, than removing 
> rk_timer
> will break u-boot for these chips.

Thanks for your comment, I will double check about if this two chips
have arch
timer, I think it should be, but I don't have boards now.

Thanks,
- Kever
>
> And my comment was about global timer, not arch timer. And I failed to enable 
> arch
> timer for rk3188 in the kernel.
>
> Alexander.
>
>> 27 марта 2018 г., в 19:07, Alexander Kochetkov  
>> написал(а):
>>
>>> 27 марта 2018 г., в 12:29, Kever Yang  
>>> написал(а):
>>>
>>> We use ARM arch timer instead.
>> Hi, Kever!
>>
>> Just let you know, that arch timer rate on rk3066 and rk3188 depends on CPU 
>> frequency.
>> I’ve made patch[1] for fixing that in kernel.
>> If u-boot do arm clock changes after timer initialization, timer can provide 
>> inaccurate delays.
>>
>> [1] 
>> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/drivers/clocksource/rockchip_timer.c?id=5e0a39d0f727b35c8b7ef56ba0724c8ceb006297
>>
>> Alexander.
>


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Re: [U-Boot] [PATCH 33/36] rockchip: dts: rk3399-firefly: enable uart2 in spl

[Kever Yang]

Hi Peter,


On 03/27/2018 07:49 PM, Peter Robinson wrote:
> On Tue, Mar 27, 2018 at 10:29 AM, Kever Yang  
> wrote:
>> pre-loader console in SPL needs UART.
>>
>> Signed-off-by: Kever Yang 
>> ---
>>
>>  arch/arm/dts/rk3399-firefly.dts | 1 +
>>  1 file changed, 1 insertion(+)
>>
>> diff --git a/arch/arm/dts/rk3399-firefly.dts 
>> b/arch/arm/dts/rk3399-firefly.dts
>> index f134c00..a007fa1 100644
>> --- a/arch/arm/dts/rk3399-firefly.dts
>> +++ b/arch/arm/dts/rk3399-firefly.dts
>> @@ -648,6 +648,7 @@
>>  };
>>
>>   {
>> +   u-boot,dm-pre-reloc;
> if this is u-boot specific shouldn't it be in a rk3399-firefly-u-boot.dtsi ?

Yes, this should go to rk3399-firefly-u-boot.dtsi.

Thanks,
- Kever
>
>> status = "okay";
>>  };
>>
>> --
>> 1.9.1
>>
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Re: [U-Boot] [PATCH] warp7: configs: enable CONFIG_CMD_FS_GENERIC

[Fabio Estevam]

Hi Pierre-Jean,

On Tue, Mar 27, 2018 at 4:50 PM, Pierre-Jean TEXIER
 wrote:
> This enable generic file system commands (load, ls).
>
> Signed-off-by: Pierre-Jean TEXIER 
> ---
>  configs/warp7_defconfig| 1 +
>  configs/warp7_secure_defconfig | 1 +
>  2 files changed, 2 insertions(+)
>
> diff --git a/configs/warp7_defconfig b/configs/warp7_defconfig
> index 29c4512..3856918 100644
> --- a/configs/warp7_defconfig
> +++ b/configs/warp7_defconfig
> @@ -26,6 +26,7 @@ CONFIG_CMD_EXT2=y
>  CONFIG_CMD_EXT4=y
>  CONFIG_CMD_EXT4_WRITE=y
>  CONFIG_CMD_FAT=y
> +CONFIG_CMD_FS_GENERIC=y

It is OK to make this change, but please also change
include/configs/warp.h so that is uses 'load' instead of 'fatload'.

Also, please run ./scripts/get_maintainer.pl so that you do not miss
to Cc the board maintainer and also Stefano Babic.

Thanks
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Re: [U-Boot] [PATCH v3 2/2] imx: hab: Provide hab_auth_img_or_fail command

[Breno Matheus Lima]

Hi All,

-Original Message-
From: Bryan O'Donoghue [mailto:bryan.odonog...@linaro.org] 
Sent: segunda-feira, 26 de março de 2018 11:37
To: u-boot@lists.denx.de; Fabio Estevam 
Cc: rui.si...@linaro.org; sba...@denx.de; Bryan O'Donoghue 
; Utkarsh Gupta ; Breno 
Matheus Lima 
Subject: [PATCH v3 2/2] imx: hab: Provide hab_auth_img_or_fail command

This patch adds hab_auth_img_or_fail() a command line function that 
encapsulates a common usage of authenticate and failover, namely if 
authenticate image fails, then drop to BootROM USB recovery mode.

For secure-boot systems, this type of locked down behavior is important to 
ensure no unsigned images can be run.

It's possible to script this logic but, when done over and over again the 
environment starts get very complex and repetitive, reducing that script 
repetition down to a command line function makes sense.

Signed-off-by: Bryan O'Donoghue 
Cc: Utkarsh Gupta 
Cc: Breno Lima 
Cc: Fabio Estevam 

Tested-by: Breno Lima 

Thanks,
Breno
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Re: [U-Boot] [PATCH v3 1/2] imximage: Encase majority of header in __ASSEMBLY__ declaration

[Breno Matheus Lima]

Hi All,

-Original Message-
From: Bryan O'Donoghue [mailto:bryan.odonog...@linaro.org] 
Sent: segunda-feira, 26 de março de 2018 11:37
To: u-boot@lists.denx.de; Fabio Estevam 
Cc: rui.si...@linaro.org; sba...@denx.de; Bryan O'Donoghue 
; Utkarsh Gupta ; Breno 
Matheus Lima 
Subject: [PATCH v3 1/2] imximage: Encase majority of header in __ASSEMBLY__ 
declaration

Subsequent patches will want to include imageimage.h but in doing so include it 
on an assembly compile path causing a range of compile errors.
Fix the errors pre-emptively by encasing the majority of the declarations in 
imximage.h inside an ifdef __ASSEMBLY__ block.

Signed-off-by: Bryan O'Donoghue 
Cc: Utkarsh Gupta 
Cc: Breno Lima 
Cc: Fabio Estevam 

Tested-by: Breno Lima 

Thanks,
Breno

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[U-Boot] [PATCH] warp7: configs: enable CONFIG_CMD_FS_GENERIC

[Pierre-Jean TEXIER]

This enable generic file system commands (load, ls).

Signed-off-by: Pierre-Jean TEXIER 
---
 configs/warp7_defconfig| 1 +
 configs/warp7_secure_defconfig | 1 +
 2 files changed, 2 insertions(+)

diff --git a/configs/warp7_defconfig b/configs/warp7_defconfig
index 29c4512..3856918 100644
--- a/configs/warp7_defconfig
+++ b/configs/warp7_defconfig
@@ -26,6 +26,7 @@ CONFIG_CMD_EXT2=y
 CONFIG_CMD_EXT4=y
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_DFU_MMC=y
 CONFIG_USB=y
diff --git a/configs/warp7_secure_defconfig b/configs/warp7_secure_defconfig
index 7310855..e894578 100644
--- a/configs/warp7_secure_defconfig
+++ b/configs/warp7_secure_defconfig
@@ -26,6 +26,7 @@ CONFIG_CMD_EXT2=y
 CONFIG_CMD_EXT4=y
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_DFU_MMC=y
 CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y
-- 
2.7.4

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Re: [U-Boot] [PATCH v2] Kconfig: cmd: Make networking command dependent on NET

[Joe Hershberger]

Hi Heinrich,

On Wed, Feb 28, 2018 at 5:05 PM, Heinrich Schuchardt
 wrote:
> On 02/28/2018 02:09 AM, Tom Rini wrote:
>>
>> On Mon, Feb 26, 2018 at 04:01:02PM +0100, Michal Simek wrote:
>>
>>> Enable networking command only when NET is enabled.
>>> And remove selecting NET for CMD_NET
>>>
>>> Signed-off-by: Michal Simek 
>>> ---
>>>
>>> Changes in v2:
>>> - Check several boards by hand.
>>>
>>> There is a huge impact on defconfigs because of select NET.
>>> But this change makes sense to do but it just needs to be syncup
>>> properly. Do we have a tool for this kind of change?
>>
>>
>> So, I've applied this patch, with a good bit of modification.  What I
>> wasn't clear about before, sorry, was that we need to make NET default y
>> in here too.  However, we also have some decent areas of the code that
>> use "CONFIG_CMD_NET" when it really means "CONFIG_NET", at least
>> conceptually.  But in order to make everything work as-is today, and
>> leave these fixes to a later point in time (as they are fixes and should
>> happen) we change some areas today that reference CONFIG_NET to
>> reference CONFIG_CMD_NET.  Once net/ gets cleaned up, we can use
>> CONFIG_NET without CONFIG_CMD_NET in more area.  It's also not quite
>> 100% size-neutral as the topic_miami* boards were playing some games
>> that can't quite be done as they were before, but I believe the end
>> result is they can now more easily and thoroughly disable the networking
>> stuff that intended to be removed.
>>
>>
>
> Hello Tom,
>
> in spite of you comments above I do not understand why you changed
> cmd/bootefi.c to depend on CONFIG_CMD_NET instead of CONFIG_NET.
>
> This was not part of Michal's patch.
>
> I would prefer if changes would be sent to the list for review *before*
> being applied.
>
> As the patch that you applied is not Michal's patch your authorship should
> be documented in the git log.
>
> I cannot see any reason why network support should be disabled in bootefi if
> there are no network commands available.

I think there is a fair amount of conflation since some of the basic
functions like bootp and dhcp are only accessible through the
commands, but you're right that it should be possible to use
networking with a static IP and no network commands.

> Please, undo this change.
>
> Best regards
>
> Heinrich
>
>
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Re: [U-Boot] [PATCH v4 13/19] sunxi: DT: A64: update board .dts files from Linux

[André Przywara]

On 27/03/18 18:58, Jagan Teki wrote:
> On Sat, Mar 24, 2018 at 6:37 AM, André Przywara  
> wrote:
>> On 23/03/18 18:14, Jagan Teki wrote:
>>> On Wed, Mar 14, 2018 at 7:27 AM, Andre Przywara  
>>> wrote:
 Update the .dts files for the various boards with an Allwinner A64 SoC.
 This is as of v4.15-rc9, exactly Linux commit:
>>
>> 
>>

   {
 pinctrl-names = "default";
 pinctrl-0 = <_pins>;
 -   vmmc-supply = <_vcc3v3>;
 +   vmmc-supply = <_dcdc1>;
>>>
>>> These AXP regulator stuff need to wait until the relevant driver
>>> supported through dt
>>
>> Well, we could take the two patches I had in v3 that revert this change.
>> As mentioned before, DCDC1 is an always-on regulator anyways.
> 
> May it's good option to look at v3 changes, since DM_MMC Migration
> expires in coming release, dt changes which are related to MMC we can
> wait for proper supported feature get IN(like pinctrl, clock, reset),
> that means we should anyway need to move DM_MMC but with working dt
> changes.
> 
> The big question for me here is about SPL, I'm sure we can get the
> size issues. May be we try platdata but in any case we need to enable
> DM ie increase the size (atleast for A64, H5)

So my understanding is that those DM_ defines are just for
U-Boot proper, and the SPL needs extra symbols to be also "DMed".
See the definition of CONFIG_IS_ENABLED().
So by just #defining CONFIG_DM_MMC the SPL still looks the same (using
the non-DM code), and indeed I don't run into size issues with the SPL.

Given the uniformity of at least the MMC device in sunxi, I think in the
medium term  we get away with some simple platdata, without pulling the
DT into SPL. The clocks might be a bit more hairy here, though. But
that's nothing for *now* to solve.

Just getting cheeky and wonder if we actually need to touch the clocks
since the boot ROM has actually done all this work already (since we
always load from the same media as the boot ROOM).

Cheers,
Andre.

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Re: [U-Boot] [PATCH v2 3/3] imx: hab: Provide hab_auth_img_or_fail command

[Breno Matheus Lima]

Hi All,

2018-03-27 19:44 GMT-03:00 Breno Matheus Lima :
> Hi Bryan,
>
> 2018-03-26 11:11 GMT-03:00 Bryan O'Donoghue :
>> This patch adds hab_auth_img_or_fail() a command line function that
>> encapsulates a common usage of authenticate and failover, namely if
>> authenticate image fails, then drop to BootROM USB recovery mode.
>>
>> For secure-boot systems, this type of locked down behavior is important to
>> ensure no unsigned images can be run.
>>
>> It's possible to script this logic but, when done over and over again the
>> environment starts get very complex and repetitive, reducing that script
>> repetition down to a command line function makes sense.
>>
>> Signed-off-by: Bryan O'Donoghue 
>> Cc: Utkarsh Gupta 
>> Cc: Breno Lima 
>> Cc: Fabio Estevam 
>
> Tested-by: Breno Lima 
>
> Thanks,
> Breno

Sorry, I have comment on the wrong series, my intention was to comment
on V3 series. I will resend the tested-by

Thanks,
Breno Matheus Lima
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Re: [U-Boot] [PATCH v2 3/3] imx: hab: Provide hab_auth_img_or_fail command

[Breno Matheus Lima]

Hi Bryan,

2018-03-26 11:11 GMT-03:00 Bryan O'Donoghue :
> This patch adds hab_auth_img_or_fail() a command line function that
> encapsulates a common usage of authenticate and failover, namely if
> authenticate image fails, then drop to BootROM USB recovery mode.
>
> For secure-boot systems, this type of locked down behavior is important to
> ensure no unsigned images can be run.
>
> It's possible to script this logic but, when done over and over again the
> environment starts get very complex and repetitive, reducing that script
> repetition down to a command line function makes sense.
>
> Signed-off-by: Bryan O'Donoghue 
> Cc: Utkarsh Gupta 
> Cc: Breno Lima 
> Cc: Fabio Estevam 

Tested-by: Breno Lima 

Thanks,
Breno
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[U-Boot] [PATCH] vxworks: fixed cpu enable using PSCI on armv8

[Vasyl Vavrychuk]

Without armv8_setup_psci register VBAR_EL3 is not set up property which
makes SMC calls jump to invalid location.

smp_kick_all_cpus is required to make slave cpus leave gic_wait_for_interrupt.
Without this they will never pursue booting process.

This implementation is very similiar to what is done in boot_jump_linux
in arch/arm/lib/bootm.c file.

Tested on VxWorks 7 release SR0520 2017-12-08.

Signed-off-by: Vasyl Vavrychuk 
---
 cmd/elf.c | 5 +
 1 file changed, 5 insertions(+)

diff --git a/cmd/elf.c b/cmd/elf.c
index 5745a389da..db690fc619 100644
--- a/cmd/elf.c
+++ b/cmd/elf.c
@@ -372,6 +372,11 @@ int do_bootvx(cmd_tbl_t *cmdtp, int flag, int argc, char * 
const argv[])
printf("## Starting vxWorks at 0x%08lx ...\n", addr);
 
dcache_disable();
+#if defined(CONFIG_ARM64) && defined(CONFIG_ARMV8_PSCI)
+   armv8_setup_psci();
+   smp_kick_all_cpus();
+#endif
+
 #ifdef CONFIG_X86
/* VxWorks on x86 uses stack to pass parameters */
((asmlinkage void (*)(int))addr)(0);
-- 
2.11.0

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[U-Boot] [PATCH] mmc: mv_sdhci: zero out sdhci_host structure

[Matt Pelland]

The mv_sdhci driver was not zeroing the sdhci_host structure it
allocates causing random access violations in parts of the mmc core
where the "ops" member pointers are checked and called if not NULL.

Signed-off-by: Matt Pelland 
---
 drivers/mmc/mv_sdhci.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/mmc/mv_sdhci.c b/drivers/mmc/mv_sdhci.c
index 69aa87babe..afc03f75a0 100644
--- a/drivers/mmc/mv_sdhci.c
+++ b/drivers/mmc/mv_sdhci.c
@@ -74,6 +74,8 @@ int mv_sdh_init(unsigned long regbase, u32 max_clk, u32 
min_clk, u32 quirks)
return -ENOMEM;
}
 
+   memset(host, 0, sizeof(struct sdhci_host));
+
host->name = MVSDH_NAME;
host->ioaddr = (void *)regbase;
host->quirks = quirks;
-- 
2.14.3

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[U-Boot] [PATCH] net: mvneta: support setting hardware address

[Matt Pelland]

mvneta already supports setting the MAC address but this was only done
internally when some other part of U-Boot tries to actually use the
interface. This commit exposes this functionality to the ethernet core
code so that the MAC addresses of all interfaces are configured
correctly even if they are not used before loading Linux.

Signed-off-by: Matt Pelland 
---
 drivers/net/mvneta.c | 11 +++
 1 file changed, 11 insertions(+)

diff --git a/drivers/net/mvneta.c b/drivers/net/mvneta.c
index 83e3153768..fdff772178 100644
--- a/drivers/net/mvneta.c
+++ b/drivers/net/mvneta.c
@@ -890,6 +890,16 @@ static void mvneta_mac_addr_set(struct mvneta_port *pp, 
unsigned char *addr,
mvneta_set_ucast_addr(pp, addr[5], queue);
 }
 
+static int mvneta_write_hwaddr(struct udevice *dev)
+{
+   mvneta_mac_addr_set(
+   dev_get_priv(dev),
+   ((struct eth_pdata *)dev_get_platdata(dev))->enetaddr,
+   rxq_def);
+
+   return 0;
+}
+
 /* Handle rx descriptor fill by setting buf_cookie and buf_phys_addr */
 static void mvneta_rx_desc_fill(struct mvneta_rx_desc *rx_desc,
u32 phys_addr, u32 cookie)
@@ -1753,6 +1763,7 @@ static const struct eth_ops mvneta_ops = {
.send   = mvneta_send,
.recv   = mvneta_recv,
.stop   = mvneta_stop,
+   .write_hwaddr   = mvneta_write_hwaddr,
 };
 
 static int mvneta_ofdata_to_platdata(struct udevice *dev)
-- 
2.14.3

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Re: [U-Boot] [PATCH 1/3] dm: Add migration plan for CONFIG_BLK

[Jagan Teki]

On Mon, Sep 4, 2017 at 9:57 PM,   wrote:
> Hi Tom,
>
> On 7 August 2017 at 09:39, Tom Rini  wrote:
>> On Sat, Aug 05, 2017 at 03:45:53PM -0600, Simon Glass wrote:
>>
>>> The CONFIG_BLK conversion involves quite invasive changes in the U-Boot
>>> code, with #ifdefs and different code paths. We should try to move over to
>>> this soon so we can drop the old code.

I hope this will applicable to SPL too?

If so, we are having SPL size issues with few Allwinner families, if
enable SPL_DM any suggestions?
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Re: [U-Boot] [PATCH v4 13/19] sunxi: DT: A64: update board .dts files from Linux

[Jagan Teki]

On Sat, Mar 24, 2018 at 6:37 AM, André Przywara  wrote:
> On 23/03/18 18:14, Jagan Teki wrote:
>> On Wed, Mar 14, 2018 at 7:27 AM, Andre Przywara  
>> wrote:
>>> Update the .dts files for the various boards with an Allwinner A64 SoC.
>>> This is as of v4.15-rc9, exactly Linux commit:
>
> 
>
>>>
>>>   {
>>> pinctrl-names = "default";
>>> pinctrl-0 = <_pins>;
>>> -   vmmc-supply = <_vcc3v3>;
>>> +   vmmc-supply = <_dcdc1>;
>>
>> These AXP regulator stuff need to wait until the relevant driver
>> supported through dt
>
> Well, we could take the two patches I had in v3 that revert this change.
> As mentioned before, DCDC1 is an always-on regulator anyways.

May it's good option to look at v3 changes, since DM_MMC Migration
expires in coming release, dt changes which are related to MMC we can
wait for proper supported feature get IN(like pinctrl, clock, reset),
that means we should anyway need to move DM_MMC but with working dt
changes.

The big question for me here is about SPL, I'm sure we can get the
size issues. May be we try platdata but in any case we need to enable
DM ie increase the size (atleast for A64, H5)

Jagan.
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Re: [U-Boot] [PATCH v4 13/19] sunxi: DT: A64: update board .dts files from Linux

[Jagan Teki]

On Tue, Mar 27, 2018 at 8:13 PM, Andre Przywara  wrote:
> Hi Maxime,
>
> thanks for the answer.
>
> On 27/03/18 15:30, Maxime Ripard wrote:
>> Hi,
>>
>> On Sat, Mar 24, 2018 at 01:07:27AM +, André Przywara wrote:
>>> On 23/03/18 18:14, Jagan Teki wrote:
 On Wed, Mar 14, 2018 at 7:27 AM, Andre Przywara  
 wrote:
> Update the .dts files for the various boards with an Allwinner A64 SoC.
> This is as of v4.15-rc9, exactly Linux commit:
>>>
>>> 
>>>
>
>   {
> pinctrl-names = "default";
> pinctrl-0 = <_pins>;
> -   vmmc-supply = <_vcc3v3>;
> +   vmmc-supply = <_dcdc1>;

 These AXP regulator stuff need to wait until the relevant driver
 supported through dt
>>>
>>> Well, we could take the two patches I had in v3 that revert this change.
>>> As mentioned before, DCDC1 is an always-on regulator anyways.
>>>
>>> But actually that's not our problem, as we don't define DM_REGULATORS,
>>> so we will never parse those properties.
>>>
>>> Instead:
>>>
 otherwise moving to DM_MMC might fail to get the
 regulator? [1]
 [1] https://patchwork.ozlabs.org/patch/887405/
>>>
>>> Ah, thanks for the link, I totally missed that.
>>> So as Heinrich rightfully feared in his first patch, this change - for
>>> all sunxi boards - breaks most of them: The DM-MMC part of the sunxi MMC
>>> driver is not ready for any other SoC than the A20:
>>> a) The only compatible string it knows is "allwinner,sun5i-a13-mmc".
>>> b) It assumes the old style clocks, even without checking if the
>>> referenced nodes are compatible.
>>>
>>> So while a) is trivial to fix (U-Boot probably does not need to care
>>> about the differences in the MMC controllers of the different SoCs), b)
>>> is more of a beast.
>>> I started looking into an easy implementation of the new clocks,
>>> basically just enough to get MMC going, for the H3/H5 and A64. This
>>> could be extended for other clocks once we need them.
>>> But I am afraid this is not 2018.05 material anymore.
>>>
>>> So what do we do here?
>>>
>>> 1) Just switch over A20? The A20 DTs in U-Boot use the old-style clocks
>>> still, so that's fine. And we postpone the DM-MMC switch for the rest
>>> until we have some DM new-style clock driver?
>>
>> I'm not sure I'd like to do that to be honest, this sounds like
>> something that will never happen.
>>
>>> 2) Push forward on some simple sunxi-ng MMC clock driver?
>>
>> That one would work for me
>>
>>> 3) Don't use DM_MMC at all?
>>
>> Given the warning that was set for the next release, I'm not sure we
>> have much choice unfortunately.
>
> OK. So meanwhile I have something almost(TM) working:
> - drivers/clk/sunxi/clk-a64.c, which is a UCLASS_CLK implementation of
> the clock IDs from allwinner,sun50i-a64-ccu that we need: CLK_BUS_UARTx,
> CLK_BUS_MMCx, CLK_MMCx. Their implementation is fairly simple, actually
> (I did it the U-Boot way, not pulling in any super-fancy Linux code).
> Porting this over to H3/H5 and other SoCs should be trivial: copy/paste
> for now. We can look at how to unify this later.
> - drivers/mmc/sunxi_mmc.c extended to use UCLASS_CLK clocks. This is
> also not too bad, but I seem to miss a bit in here, as it times out.
> Will debug this tonight.
> - Cowardly dodging a proper UCLASS_RESET driver for now, instead hacking
> the single bit in :-(

I did this missing DM work like pinctrl, reset and clk and unable to
send because of size issues. which was with v2017.03.

I'm thinking DM_MMC should wait till the driver should have support of
these feature with all family SOC's

Jagan.

-- 
Jagan Teki
Free Software Engineer | www.openedev.com
U-Boot, Linux | Upstream Maintainer
Hyderabad, India.
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Re: [U-Boot] [PATCH 26/36] rockchip: rk1108: remove rockchip timer for sys timer

[Alexander Kochetkov]

The question is: does rk3066 and rk3188 have arch timer? If no, than removing 
rk_timer
will break u-boot for these chips.

And my comment was about global timer, not arch timer. And I failed to enable 
arch
timer for rk3188 in the kernel.

Alexander.

> 27 марта 2018 г., в 19:07, Alexander Kochetkov  
> написал(а):
> 
>> 
>> 27 марта 2018 г., в 12:29, Kever Yang  написал(а):
>> 
>> We use ARM arch timer instead.
> 
> Hi, Kever!
> 
> Just let you know, that arch timer rate on rk3066 and rk3188 depends on CPU 
> frequency.
> I’ve made patch[1] for fixing that in kernel.
> If u-boot do arm clock changes after timer initialization, timer can provide 
> inaccurate delays.
> 
> [1] 
> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/drivers/clocksource/rockchip_timer.c?id=5e0a39d0f727b35c8b7ef56ba0724c8ceb006297
> 
> Alexander.

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Re: [U-Boot] [PATCH 26/36] rockchip: rk1108: remove rockchip timer for sys timer

[Alexander Kochetkov]

> 27 марта 2018 г., в 12:29, Kever Yang  написал(а):
> 
> We use ARM arch timer instead.

Hi, Kever!

Just let you know, that arch timer rate on rk3066 and rk3188 depends on CPU 
frequency.
I’ve made patch[1] for fixing that in kernel.
If u-boot do arm clock changes after timer initialization, timer can provide 
inaccurate delays.

[1] 
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/drivers/clocksource/rockchip_timer.c?id=5e0a39d0f727b35c8b7ef56ba0724c8ceb006297

Alexander.

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Re: [U-Boot] [PATCH] cmd: nvedit: Add filtering during env import

[Alex Kiernan]

On Tue, Mar 27, 2018 at 2:30 PM, Quentin Schulz
 wrote:

> What I'm more concerned about is that after we've merged your patch,
> it isn't possible to pass multiple parameters at the end of the command.
> There might be (I have no example as of today) some things we want to do
> in the future that can't be done an other way than passing a list of
> arguments at the end of the command and your patch prevent doing so in
> the future.
>

Fair comment... I was really just following what was already there for
env export (so much so I could cut'n'paste the documentation changes).

> We can do it now with a single option (-w or whatever letter we want to
> use) so I guess it's better to leave the option for cases that really
> require to have a list of parameters passed to the command.
>

I really don't like magic variables that get used invisibly, though I
guess you could pass a variable in.

-- 
Alex Kiernan
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Re: [U-Boot] [PATCH 2/2] efi_loader: set the dhcp ack received flag

[Heinrich Schuchardt]

On 03/27/2018 02:24 PM, Patrick Wildt wrote:
> The PXE object contains a flag that specifies whether or not a DHCP
> ACK has been received.  This can be used by EFI Applications to find
> out whether or not it is worth to read the DHCP information from our
> object.
> 
> Signed-off-by: Patrick Wildt 
> ---
>  lib/efi_loader/efi_net.c | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/lib/efi_loader/efi_net.c b/lib/efi_loader/efi_net.c
> index 8c5d5b492c..0b9c7b9345 100644
> --- a/lib/efi_loader/efi_net.c
> +++ b/lib/efi_loader/efi_net.c
> @@ -332,8 +332,10 @@ int efi_net_register(void)
>   netobj->net_mode.max_packet_size = PKTSIZE;
>  
>   netobj->pxe.mode = >pxe_mode;
> - if (dhcp_ack)
> + if (dhcp_ack) {
>   netobj->pxe_mode.dhcp_ack = *dhcp_ack;
> + netobj->pxe_mode.dhcp_ack_received = 1;
> + }

We have received a DHCPOFFER and we now send a DHCPREQUEST to the
selected server. This is when efi_net_set_dhcp_ack() is called which
sets the variable dhcp_ack.

If the server sustains its offer it responds with a DHCPACK or with a
DHCPNACK. Shouldn't we ensure a DHCPACK was received (and not a DHCNACK)
before setting dhcp_ack_received?

Best regards

Heinrich
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Re: [U-Boot] [PATCH 26/36] rockchip: rk1108: remove rockchip timer for sys timer

[Dr. Philipp Tomsich]

> On 27 Mar 2018, at 11:29, Kever Yang  wrote:
> 
> We use ARM arch timer instead.

Could you please provide a more useful commit message.
Please consider that most people that look through the GIT log are
not familiar with our platform.

Thanks,
Philipp.

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Re: [U-Boot] [PATCH 1/2] efi_loader: complete efi_pxe_mode struct definition

[Heinrich Schuchardt]

On 03/27/2018 02:23 PM, Patrick Wildt wrote:
> The efi_pxe_mode struct which represents the PXE_BASE_CODE_PROTOCOL
> Replace the placeholder paddings in the efi_pxe_mode struct with the
> actual fields as defined in UEFI's PXE Base Code Protocol.  Since
> our efi_ip_address is a simple char array set a specific alignment
> to the efi_ip_address fields, as expected by the UEFI spec.
> 
> Signed-off-by: Patrick Wildt 
> ---
>  include/efi_api.h | 25 +++--
>  1 file changed, 23 insertions(+), 2 deletions(-)
> 
> diff --git a/include/efi_api.h b/include/efi_api.h
> index 3ba650e57e..06789acdd1 100644
> --- a/include/efi_api.h
> +++ b/include/efi_api.h
> @@ -662,7 +662,7 @@ struct efi_mac_address {
>  
>  struct efi_ip_address {
>   u8 ip_addr[16];
> -};
> +} __attribute__((aligned(4)));
>  
>  enum efi_simple_network_state {
>   EFI_NETWORK_STOPPED,
> @@ -756,7 +756,28 @@ struct efi_pxe_packet {
>  
>  struct efi_pxe_mode
>  {
> - u8 unused[52];
> + u8 started;
> + u8 ipv6_available;
> + u8 ipv6_supported;
> + u8 using_ipv6;
> + u8 bis_supported;
> + u8 bis_detected;
> + u8 auto_arp;
> + u8 send_guid;
> + u8 dhcp_discover_valid;
> + u8 dhcp_ack_received;
> + u8 proxy_offer_received;
> + u8 pxe_discovervalid;

%s/pxe_discovervalid/pxe_discover_valid/

Everywhere else you replaced CamelCase by underscores.

Rest looks fine. Thanks.

Regards

Heinrich

> + u8 pxe_reply_received;
> + u8 pxe_bis_reply_received;
> + u8 icmp_error_received;
> + u8 tftp_error_received;
> + u8 make_callbacks;
> + u8 ttl;
> + u8 tos;
> + u8 pad;
> + struct efi_ip_address station_ip;
> + struct efi_ip_address subnet_mask;
>   struct efi_pxe_packet dhcp_discover;
>   struct efi_pxe_packet dhcp_ack;
>   struct efi_pxe_packet proxy_offer;
> 

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Re: [U-Boot] [PATCH] vxworks: fixed cpu enable using PSCI on armv8

[Bin Meng]

Hi Vasyl,

On Mon, Mar 26, 2018 at 3:58 PM, Vasyl Vavrychuk  wrote:
> Without armv8_setup_psci register VBAR_EL3 is not set up properly which
> makes SMC calls jump to invalid location.
>
> smp_kick_all_cpus is required to make slave cpus leave gic_wait_for_interrupt.
> Without this they will never pursue booting process.
>
> This implementation is very similiar to what is done in boot_jump_linux
> in arch/arm/lib/bootm.c file.

Could you please include what VxWorks version was tested on what board?

>
> Signed-off-by: Vasyl Vavrychuk 
> ---
>  cmd/elf.c | 5 +
>  1 file changed, 5 insertions(+)
>
> diff --git a/cmd/elf.c b/cmd/elf.c
> index 5745a389da..db690fc619 100644
> --- a/cmd/elf.c
> +++ b/cmd/elf.c
> @@ -372,6 +372,11 @@ int do_bootvx(cmd_tbl_t *cmdtp, int flag, int argc, char 
> * const argv[])
> printf("## Starting vxWorks at 0x%08lx ...\n", addr);
>
> dcache_disable();
> +#if defined(CONFIG_ARM64) && defined(CONFIG_ARMV8_PSCI)
> +   armv8_setup_psci();
> +   smp_kick_all_cpus();
> +#endif
> +

AFAIK, the ARMv8 is only supported in VxWorks 7, but per
README.vxworks, VxWorks 7 uses 'bootm' for ARM/PPC to load its image,
then why do you want to use 'bootvx' command?

>  #ifdef CONFIG_X86
> /* VxWorks on x86 uses stack to pass parameters */
> ((asmlinkage void (*)(int))addr)(0);
> --

Regards,
Bin
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Re: [U-Boot] [PATCH 3/3] configs: am43xx_evm_qspiboot_defconfig: Move to DM

[Lokesh Vutla]

On Monday 26 March 2018 01:27 PM, Vignesh R wrote:
> Move am43xx_evm_qspiboot_defconfig to DM. This is required as SPI core
> and TI QSPI driver no longer supports non DM interfaces.
> 
> Signed-off-by: Vignesh R 


Reviewed-by: Lokesh Vutla 

Thanks and regards,
Lokesh

> ---
>  configs/am43xx_evm_qspiboot_defconfig | 10 +-
>  1 file changed, 9 insertions(+), 1 deletion(-)
> 
> diff --git a/configs/am43xx_evm_qspiboot_defconfig 
> b/configs/am43xx_evm_qspiboot_defconfig
> index 2bc302c7ed97..3fbf701e601e 100644
> --- a/configs/am43xx_evm_qspiboot_defconfig
> +++ b/configs/am43xx_evm_qspiboot_defconfig
> @@ -3,6 +3,7 @@ CONFIG_ARM=y
>  CONFIG_ARCH_OMAP2PLUS=y
>  CONFIG_SYS_TEXT_BASE=0x3000
>  CONFIG_AM43XX=y
> +CONFIG_DEFAULT_DEVICE_TREE="am437x-sk-evm"
>  CONFIG_DISTRO_DEFAULTS=y
>  CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,QSPI,QSPI_BOOT"
>  CONFIG_QSPI_BOOT=y
> @@ -23,10 +24,18 @@ CONFIG_CMD_SPI=y
>  CONFIG_CMD_USB=y
>  # CONFIG_CMD_SETEXPR is not set
>  CONFIG_CMD_EXT4_WRITE=y
> +CONFIG_OF_CONTROL=y
> +CONFIG_OF_LIST="am4372-generic am437x-sk-evm am437x-idk-evm"
> +CONFIG_DTB_RESELECT=y
> +CONFIG_MULTI_DTB_FIT=y
>  CONFIG_ENV_IS_IN_SPI_FLASH=y
> +CONFIG_DM=y
> +# CONFIG_BLK is not set
>  CONFIG_DFU_MMC=y
>  CONFIG_DFU_RAM=y
>  CONFIG_DFU_SF=y
> +CONFIG_DM_GPIO=y
> +CONFIG_DM_MMC=y
>  CONFIG_MMC_OMAP_HS=y
>  CONFIG_SPI_FLASH=y
>  CONFIG_SPI_FLASH_MACRONIX=y
> @@ -48,4 +57,3 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x0403
>  CONFIG_USB_GADGET_PRODUCT_NUM=0xbd00
>  CONFIG_USB_GADGET_DOWNLOAD=y
>  CONFIG_FAT_WRITE=y
> -CONFIG_OF_LIBFDT=y
> 
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Re: [U-Boot] [PATCH 2/3] ARM: dts: Add new "generic" am4372 device tree file.

[Lokesh Vutla]

On Monday 26 March 2018 01:27 PM, Vignesh R wrote:
> With U-boot runtime board detect for DTB selection a "default" dtb needs
> to be created. This will be used temporarily until the "proper" dtb is
> selected.
> 
> Also, add -u-boot.dtsi for AM437x SK and IDK to enable I2C for
> board detection via DM_I2C.
> 
> Signed-off-by: Vignesh R 



Reviewed-by: Lokesh Vutla 

Thanks and regards,
Lokesh

> ---
>  arch/arm/dts/Makefile   |  3 ++-
>  arch/arm/dts/am4372-generic-u-boot.dtsi | 15 +++
>  arch/arm/dts/am4372-generic.dts | 24 
>  arch/arm/dts/am437x-idk-evm-u-boot.dtsi | 23 +++
>  arch/arm/dts/am437x-sk-evm-u-boot.dtsi  | 23 +++
>  5 files changed, 87 insertions(+), 1 deletion(-)
>  create mode 100644 arch/arm/dts/am4372-generic-u-boot.dtsi
>  create mode 100644 arch/arm/dts/am4372-generic.dts
>  create mode 100644 arch/arm/dts/am437x-idk-evm-u-boot.dtsi
>  create mode 100644 arch/arm/dts/am437x-sk-evm-u-boot.dtsi
> 
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> index 7dd1dffae599..15212acf90fa 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -167,7 +167,8 @@ dtb-$(CONFIG_AM33XX) += am335x-boneblack.dtb 
> am335x-bone.dtb \
>   am335x-pdu001.dtb
>  dtb-$(CONFIG_AM43XX) += am437x-gp-evm.dtb am437x-sk-evm.dtb  \
>   am43x-epos-evm.dtb \
> - am437x-idk-evm.dtb
> + am437x-idk-evm.dtb \
> + am4372-generic.dtb
>  dtb-$(CONFIG_TI816X) += dm8168-evm.dtb
>  dtb-$(CONFIG_THUNDERX) += thunderx-88xx.dtb
>  
> diff --git a/arch/arm/dts/am4372-generic-u-boot.dtsi 
> b/arch/arm/dts/am4372-generic-u-boot.dtsi
> new file mode 100644
> index ..03a8a8d17b8c
> --- /dev/null
> +++ b/arch/arm/dts/am4372-generic-u-boot.dtsi
> @@ -0,0 +1,15 @@
> +/*
> + * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
> + *
> + * SPDX-License-Identifier:  GPL-2.0+
> + */
> +
> +/{
> + ocp {
> + u-boot,dm-pre-reloc;
> + };
> +};
> +
> + {
> + u-boot,dm-pre-reloc;
> +};
> diff --git a/arch/arm/dts/am4372-generic.dts b/arch/arm/dts/am4372-generic.dts
> new file mode 100644
> index ..0c4843901882
> --- /dev/null
> +++ b/arch/arm/dts/am4372-generic.dts
> @@ -0,0 +1,24 @@
> +/*
> + * Device Tree Source for Generic AM4372 EVM
> + *
> + * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +/dts-v1/;
> +
> +#include "am4372.dtsi"
> +
> +/ {
> + compatible = "ti,am4372", "ti,am43";
> + model = "Texas Instruments AM4372 Generic";
> +
> + chosen {
> + stdout-path = 
> + };
> +};
> +
> + {
> + status = "okay";
> +};
> diff --git a/arch/arm/dts/am437x-idk-evm-u-boot.dtsi 
> b/arch/arm/dts/am437x-idk-evm-u-boot.dtsi
> new file mode 100644
> index ..2f68d7ae9cdc
> --- /dev/null
> +++ b/arch/arm/dts/am437x-idk-evm-u-boot.dtsi
> @@ -0,0 +1,23 @@
> +/*
> + * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
> + *
> + * SPDX-License-Identifier:  GPL-2.0+
> + */
> +
> +/{
> + ocp {
> + u-boot,dm-spl;
> + };
> +};
> +
> + {
> + u-boot,dm-spl;
> +};
> +
> + {
> + u-boot,dm-spl;
> +};
> +
> + {
> + u-boot,dm-spl;
> +};
> diff --git a/arch/arm/dts/am437x-sk-evm-u-boot.dtsi 
> b/arch/arm/dts/am437x-sk-evm-u-boot.dtsi
> new file mode 100644
> index ..2f68d7ae9cdc
> --- /dev/null
> +++ b/arch/arm/dts/am437x-sk-evm-u-boot.dtsi
> @@ -0,0 +1,23 @@
> +/*
> + * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
> + *
> + * SPDX-License-Identifier:  GPL-2.0+
> + */
> +
> +/{
> + ocp {
> + u-boot,dm-spl;
> + };
> +};
> +
> + {
> + u-boot,dm-spl;
> +};
> +
> + {
> + u-boot,dm-spl;
> +};
> +
> + {
> + u-boot,dm-spl;
> +};
> 
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Re: [U-Boot] [PATCH 1/3] board: ti: am43xx: Define embedded_dtb_select for runtime DTB selection in U-boot

[Lokesh Vutla]

On Monday 26 March 2018 01:27 PM, Vignesh R wrote:
> AM437x QSPI boot is a single stage boot and hence needs runtime DTB
> selection to support AM437x-SK and AM437x-IDK with DM enabled. This is
> required to move am43xx_evm_qspiboot_defconfig to use DM/DT.
> 
> Signed-off-by: Vignesh R 

Reviewed-by: Lokesh Vutla 

Thanks and regards,
Lokesh

> ---
>  board/ti/am43xx/board.c | 18 --
>  1 file changed, 16 insertions(+), 2 deletions(-)
> 
> diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c
> index 715960a596e9..38af1673273b 100644
> --- a/board/ti/am43xx/board.c
> +++ b/board/ti/am43xx/board.c
> @@ -852,10 +852,14 @@ int ft_board_setup(void *blob, bd_t *bd)
>  }
>  #endif
>  
> -#ifdef CONFIG_SPL_LOAD_FIT
> +#if defined(CONFIG_SPL_LOAD_FIT) || defined(CONFIG_DTB_RESELECT)
>  int board_fit_config_name_match(const char *name)
>  {
> - if (board_is_evm() && !strcmp(name, "am437x-gp-evm"))
> + bool eeprom_read = board_ti_was_eeprom_read();
> +
> + if (!strcmp(name, "am4372-generic") && !eeprom_read)
> + return 0;
> + else if (board_is_evm() && !strcmp(name, "am437x-gp-evm"))
>   return 0;
>   else if (board_is_sk() && !strcmp(name, "am437x-sk-evm"))
>   return 0;
> @@ -868,6 +872,16 @@ int board_fit_config_name_match(const char *name)
>  }
>  #endif
>  
> +#ifdef CONFIG_DTB_RESELECT
> +int embedded_dtb_select(void)
> +{
> + do_board_detect();
> + fdtdec_setup();
> +
> + return 0;
> +}
> +#endif
> +
>  #ifdef CONFIG_TI_SECURE_DEVICE
>  void board_fit_image_post_process(void **p_image, size_t *p_size)
>  {
> 
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[U-Boot] [PATCH v2 1/2] dm: i2c: dts: Add gpios and pinctrl device tree properties

[Alexander Kochetkov]

The commit describe usage of gpios and pinctrl device tree
properties in order to enable gpio-based software deblocking.

Signed-off-by: Alexander Kochetkov 
---
 doc/device-tree-bindings/i2c/i2c.txt |   13 +
 1 file changed, 13 insertions(+)

diff --git a/doc/device-tree-bindings/i2c/i2c.txt 
b/doc/device-tree-bindings/i2c/i2c.txt
index ea918dd..de818d4 100644
--- a/doc/device-tree-bindings/i2c/i2c.txt
+++ b/doc/device-tree-bindings/i2c/i2c.txt
@@ -12,6 +12,11 @@ property which allows the chip offset length to be selected.
 Optional properties:
 - u-boot,i2c-offset-len - length of chip offset in bytes. If omitted the
 default value of 1 is used.
+- gpios = , ;
+  pinctrl-names = "default", "gpio";
+  pinctrl-0 = <_xfer>;
+  pinctrl-1 = <_gpio>;
+Pin description for I2C bus software deblocking.
 
 
 Example
@@ -26,3 +31,11 @@ i2c4: i2c@12ca {
ec-interrupt = < 6 GPIO_ACTIVE_LOW>;
};
 };
+
+ {
+   pinctrl-names = "default", "gpio";
+   pinctrl-0 = <_xfer>;
+   pinctrl-1 = <_gpio>;
+   gpios = < 26 GPIO_ACTIVE_LOW>, /* SDA */
+   < 27 GPIO_ACTIVE_LOW>; /* SCL */
+};
-- 
1.7.9.5

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[U-Boot] [PATCH v2 2/2] dm: i2c: implement gpio-based I2C deblock

[Alexander Kochetkov]

The commit implement a gpio-based software deblocking. The code
extract I2C pins description from device tree, switch pins to GPIO
mode, toggle SCL until slave release SDA, send I2C stop and switch
I2C pins back to I2C mode.

Signed-off-by: Alexander Kochetkov 
---
 drivers/i2c/i2c-uclass.c |  118 ++
 1 file changed, 109 insertions(+), 9 deletions(-)

diff --git a/drivers/i2c/i2c-uclass.c b/drivers/i2c/i2c-uclass.c
index 920811a..4ac6ef8 100644
--- a/drivers/i2c/i2c-uclass.c
+++ b/drivers/i2c/i2c-uclass.c
@@ -11,9 +11,19 @@
 #include 
 #include 
 #include 
+#include 
+#ifdef CONFIG_DM_GPIO
+#include 
+#endif
 
 #define I2C_MAX_OFFSET_LEN 4
 
+enum {
+   PIN_SDA = 0,
+   PIN_SCL,
+   PIN_COUNT,
+};
+
 /* Useful debugging function */
 void i2c_dump_msgs(struct i2c_msg *msg, int nmsgs)
 {
@@ -445,20 +455,110 @@ int i2c_get_chip_offset_len(struct udevice *dev)
return chip->offset_len;
 }
 
+#ifdef CONFIG_DM_GPIO
+static void i2c_gpio_set_pin(struct gpio_desc *pin, int bit)
+{
+   if (bit)
+   dm_gpio_set_dir_flags(pin, GPIOD_IS_IN);
+   else
+   dm_gpio_set_dir_flags(pin, GPIOD_IS_OUT |
+  GPIOD_ACTIVE_LOW |
+  GPIOD_IS_OUT_ACTIVE);
+}
+
+static int i2c_gpio_get_pin(struct gpio_desc *pin)
+{
+   return dm_gpio_get_value(pin);
+}
+
+static int i2c_deblock_gpio_loop(struct gpio_desc *sda_pin,
+struct gpio_desc *scl_pin)
+{
+   int counter = 9;
+   int ret = 0;
+
+   i2c_gpio_set_pin(sda_pin, 1);
+   i2c_gpio_set_pin(scl_pin, 1);
+   udelay(5);
+
+   /*  Toggle SCL until slave release SDA */
+   while (counter-- >= 0) {
+   i2c_gpio_set_pin(scl_pin, 1);
+   udelay(5);
+   i2c_gpio_set_pin(scl_pin, 0);
+   udelay(5);
+   if (i2c_gpio_get_pin(sda_pin))
+   break;
+   }
+
+   /* Then, send I2C stop */
+   i2c_gpio_set_pin(sda_pin, 0);
+   udelay(5);
+
+   i2c_gpio_set_pin(scl_pin, 1);
+   udelay(5);
+
+   i2c_gpio_set_pin(sda_pin, 1);
+   udelay(5);
+
+   if (!i2c_gpio_get_pin(sda_pin) || !i2c_gpio_get_pin(scl_pin))
+   ret = -EREMOTEIO;
+
+   return ret;
+}
+
+static int i2c_deblock_gpio(struct udevice *bus)
+{
+   struct gpio_desc gpios[PIN_COUNT];
+   int ret, ret0;
+
+   ret = gpio_request_list_by_name(bus, "gpios", gpios,
+   ARRAY_SIZE(gpios), GPIOD_IS_IN);
+   if (ret != ARRAY_SIZE(gpios)) {
+   debug("%s: I2C Node '%s' has no 'gpios' property %s\n",
+ __func__, dev_read_name(bus), bus->name);
+   if (ret >= 0) {
+   gpio_free_list(bus, gpios, ret);
+   ret = -ENOENT;
+   }
+   goto out;
+   }
+
+   ret = pinctrl_select_state(bus, "gpio");
+   if (ret) {
+   debug("%s: I2C Node '%s' has no 'gpio' pinctrl state. %s\n",
+ __func__, dev_read_name(bus), bus->name);
+   goto out_no_pinctrl;
+   }
+
+   ret0 = i2c_deblock_gpio_loop([PIN_SDA], [PIN_SCL]);
+
+   ret = pinctrl_select_state(bus, "default");
+   if (ret) {
+   debug("%s: I2C Node '%s' has no 'default' pinctrl state. %s\n",
+ __func__, dev_read_name(bus), bus->name);
+   }
+
+   ret = !ret ? ret0 : ret;
+
+out_no_pinctrl:
+   gpio_free_list(bus, gpios, ARRAY_SIZE(gpios));
+out:
+   return ret;
+}
+#else
+static int i2c_deblock_gpio(struct udevice *bus)
+{
+   return -ENOSYS;
+}
+#endif // CONFIG_DM_GPIO
+
 int i2c_deblock(struct udevice *bus)
 {
struct dm_i2c_ops *ops = i2c_get_ops(bus);
 
-   /*
-* We could implement a software deblocking here if we could get
-* access to the GPIOs used by I2C, and switch them to GPIO mode
-* and then back to I2C. This is somewhat beyond our powers in
-* driver model at present, so for now just fail.
-*
-* See https://patchwork.ozlabs.org/patch/399040/
-*/
if (!ops->deblock)
-   return -ENOSYS;
+   return i2c_deblock_gpio(bus);
 
return ops->deblock(bus);
 }
-- 
1.7.9.5

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[U-Boot] [PATCH v2 0/2] dm: i2c: implement gpio-based I2C deblock

[Alexander Kochetkov]

Hello, Heiko! 

Here is try2 of my previous patch[1].

Done in v2:
- fix checkpatch warnings
- ENOSYS warning still present, but it was in original code also 
  and for me it looks like -ENOSYS must be returned in case of
  missed i2c_deblock_gpio() implementation.
WARNING: ENOSYS means 'invalid syscall nr' and nothing else
#138: FILE: drivers/i2c/i2c-uclass.c:552:
+   return -ENOSYS;
- fix travis build, results can be viewed here:
  https://travis-ci.org/akochetkov/u-boot/builds/358822512
- add property description to i2c.txt

I have question. I declared PIN_SDA, PIN_SCL, PIN_COUNT constants for
i2c-uclass.c. The same constants exist in the i2c-gpio.c. Should I place
them into i2c.h or may leave as is?

[1] https://lists.denx.de/pipermail/u-boot/2018-March/thread.html#321755

Alexander Kochetkov (2):
  dm: i2c: dts: Add gpios and pinctrl device tree properties
  dm: i2c: implement gpio-based I2C deblock

 doc/device-tree-bindings/i2c/i2c.txt |   13 
 drivers/i2c/i2c-uclass.c |  118 +++---
 2 files changed, 122 insertions(+), 9 deletions(-)

-- 
1.7.9.5

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[U-Boot] [PATCH 14/16] arm64: zynqmp: Remove number from clock-generator node name

[Michal Simek]

There shouldn't be a number appended based on spec.

Signed-off-by: Michal Simek 
---

 arch/arm/dts/zynqmp-zcu102-revA.dts | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/arm/dts/zynqmp-zcu102-revA.dts 
b/arch/arm/dts/zynqmp-zcu102-revA.dts
index 9f2b46cf7677..93f1d85d05d1 100644
--- a/arch/arm/dts/zynqmp-zcu102-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu102-revA.dts
@@ -424,7 +424,7 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
-   si5341: clock-generator1@36 { /* SI5341 - u69 */
+   si5341: clock-generator@36 { /* SI5341 - u69 */
compatible = "si5341";
reg = <0x36>;
};
@@ -434,7 +434,7 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
-   si570_1: clock-generator2@5d { /* USER SI570 - u42 */
+   si570_1: clock-generator@5d { /* USER SI570 - u42 */
#clock-cells = <0>;
compatible = "silabs,si570";
reg = <0x5d>;
@@ -447,7 +447,7 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
-   si570_2: clock-generator3@5d { /* USER MGT SI570 - u56 
*/
+   si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */
#clock-cells = <0>;
compatible = "silabs,si570";
reg = <0x5d>;
@@ -460,7 +460,7 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <4>;
-   si5328: clock-generator4@69 {/* SI5328 - u20 */
+   si5328: clock-generator@69 {/* SI5328 - u20 */
compatible = "silabs,si5328";
reg = <0x69>;
/*
-- 
1.9.1

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[U-Boot] [PATCH 10/16] arm64: zynqmp: Add eeprom reference to eeprom nodes

[Michal Simek]

eeprom can contain information which can be used by nvmem drivers.

Signed-off-by: Michal Simek 
---

 arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts 
b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts
index 7968aa7bec5d..c794c91de186 100644
--- a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts
+++ b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts
@@ -91,7 +91,8 @@
  {
status = "okay";
clock-frequency = <40>;
-   eeprom@55 {
+
+   eeprom: eeprom@55 {
compatible = "atmel,24c64"; /* 24AA64 */
reg = <0x55>;
};
-- 
1.9.1

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[U-Boot] [PATCH 03/16] arm64: zynqmp: Use i2c-mux instead of i2cswitch instead

[Michal Simek]

Based on review from mainline i2c-mux is standard name for i2c switches.

Signed-off-by: Michal Simek 
---

 arch/arm/dts/zynqmp-zcu102-revA.dts | 6 +++---
 arch/arm/dts/zynqmp-zcu102-revB.dts | 2 +-
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/arm/dts/zynqmp-zcu102-revA.dts 
b/arch/arm/dts/zynqmp-zcu102-revA.dts
index 1c9e4b1bd328..5f4ac22e1d7a 100644
--- a/arch/arm/dts/zynqmp-zcu102-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu102-revA.dts
@@ -220,7 +220,7 @@
 */
};
 
-   i2cswitch@75 { /* u60 */
+   i2c-mux@75 { /* u60 */
compatible = "nxp,pca9544";
#address-cells = <1>;
#size-cells = <0>;
@@ -412,7 +412,7 @@ 
drivers/hwmon/pmbus/Makefile:11:obj-$(CONFIG_SENSORS_MAX20751)  += max20751.o
 
/* FIXME PL i2c via PCA9306 - u45 */
/* FIXME MSP430 - u41 - not detected */
-   i2cswitch@74 { /* u34 */
+   i2c-mux@74 { /* u34 */
compatible = "nxp,pca9548";
#address-cells = <1>;
#size-cells = <0>;
@@ -487,7 +487,7 @@ 
drivers/hwmon/pmbus/Makefile:11:obj-$(CONFIG_SENSORS_MAX20751)  += max20751.o
/* 5 - 7 unconnected */
};
 
-   i2cswitch@75 {
+   i2c-mux@75 {
compatible = "nxp,pca9548"; /* u135 */
#address-cells = <1>;
#size-cells = <0>;
diff --git a/arch/arm/dts/zynqmp-zcu102-revB.dts 
b/arch/arm/dts/zynqmp-zcu102-revB.dts
index d0acb29b64b3..46517ba0b4e2 100644
--- a/arch/arm/dts/zynqmp-zcu102-revB.dts
+++ b/arch/arm/dts/zynqmp-zcu102-revB.dts
@@ -31,7 +31,7 @@
 
 /* Fix collision with u61 */
  {
-   i2cswitch@75 {
+   i2c-mux@75 {
i2c@2 {
max15303@1b { /* u8 */
compatible = "maxim,max15303";
-- 
1.9.1

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[U-Boot] [PATCH 15/16] arm64: zynqmp: Add silabs prefix to u69 for zcu102

[Michal Simek]

Add vendor prefix to si5341.

Signed-off-by: Michal Simek 
---

 arch/arm/dts/zynqmp-zcu102-revA.dts | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/dts/zynqmp-zcu102-revA.dts 
b/arch/arm/dts/zynqmp-zcu102-revA.dts
index 93f1d85d05d1..059d1ffe8680 100644
--- a/arch/arm/dts/zynqmp-zcu102-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu102-revA.dts
@@ -425,7 +425,7 @@
#size-cells = <0>;
reg = <1>;
si5341: clock-generator@36 { /* SI5341 - u69 */
-   compatible = "si5341";
+   compatible = "silabs,si5341";
reg = <0x36>;
};
 
-- 
1.9.1

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[U-Boot] [PATCH 07/16] arm64: zynqmp: Use s/_/-/g in node name for zcu102 rev1.0

[Michal Simek]

Follow spec for node names.

Signed-off-by: Michal Simek 
---

 arch/arm/dts/zynqmp-zcu102-rev1.0.dts | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/arm/dts/zynqmp-zcu102-rev1.0.dts 
b/arch/arm/dts/zynqmp-zcu102-rev1.0.dts
index 3fc3e749913a..b1a95a91d18d 100644
--- a/arch/arm/dts/zynqmp-zcu102-rev1.0.dts
+++ b/arch/arm/dts/zynqmp-zcu102-rev1.0.dts
@@ -18,19 +18,19 @@
#address-cells = <1>;
#size-cells = <1>;
 
-   board_sn: board_sn@0 {
+   board_sn: board-sn@0 {
reg = <0x0 0x14>;
};
 
-   eth_mac: eth_mac@20 {
+   eth_mac: eth-mac@20 {
reg = <0x20 0x6>;
};
 
-   board_name: board_name@d0 {
+   board_name: board-name@d0 {
reg = <0xd0 0x6>;
};
 
-   board_revision: board_revision@e0 {
+   board_revision: board-revision@e0 {
reg = <0xe0 0x3>;
};
 };
-- 
1.9.1

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[U-Boot] [PATCH 13/16] arm64: zynqmp: Remove u-boot commands from dts files

[Michal Simek]

U-Boot commands shouldn't be the part of kernel DTS files.

Signed-off-by: Michal Simek 
---

 arch/arm/dts/zynqmp-zcu102-revA.dts | 26 ++
 1 file changed, 10 insertions(+), 16 deletions(-)

diff --git a/arch/arm/dts/zynqmp-zcu102-revA.dts 
b/arch/arm/dts/zynqmp-zcu102-revA.dts
index 60d3f7103170..9f2b46cf7677 100644
--- a/arch/arm/dts/zynqmp-zcu102-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu102-revA.dts
@@ -144,12 +144,6 @@
sda-gpios = < 15 GPIO_ACTIVE_HIGH>;
 
tca6416_u97: gpio@20 {
-   /*
-* Enable all GTs to out from U-Boot
-* i2c mw 20 6 0  - setup IO to output
-* i2c mw 20 2 ef - setup output values on pins 0-7
-* i2c mw 20 3 ff - setup output values on pins 10-17
-*/
compatible = "ti,tca6416";
reg = <0x20>;
gpio-controller;
@@ -193,7 +187,7 @@
};
};
 
-   tca6416_u61: gpio@21 { /* FIXME enable it by i2c mw 21 6 0 */
+   tca6416_u61: gpio@21 {
compatible = "ti,tca6416";
reg = <0x21>;
gpio-controller;
@@ -224,7 +218,7 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <0x75>;
-   i2c@0 { /* i2c mw 75 0 1 */
+   i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
@@ -280,7 +274,7 @@
shunt-resistor = <5000>;
};
};
-   i2c@1 { /* i2c mw 75 0 1 */
+   i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
@@ -326,7 +320,7 @@
shunt-resistor = <5000>;
};
};
-   i2c@2 { /* i2c mw 75 0 1 */
+   i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
@@ -409,7 +403,7 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <0x74>;
-   i2c@0 { /* i2c mw 74 0 1 */
+   i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
@@ -426,7 +420,7 @@
reg = <0x54>;
};
};
-   i2c@1 { /* i2c mw 74 0 2 */
+   i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
@@ -436,7 +430,7 @@
};
 
};
-   i2c@2 { /* i2c mw 74 0 4 */
+   i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
@@ -449,7 +443,7 @@
clock-frequency = <3>;
};
};
-   i2c@3 { /* i2c mw 74 0 8 */
+   i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
@@ -462,7 +456,7 @@
clock-frequency = <14850>;
};
};
-   i2c@4 { /* i2c mw 74 0 10 */
+   i2c@4 {
#address-cells = <1>;
#size-cells = <0>;
reg = <4>;
@@ -503,7 +497,7 @@
reg = <2>;
/* SYSMON */
};
-   i2c@3 { /* i2c mw 75 0 8 */
+   i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
-- 
1.9.1

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[U-Boot] [PATCH 16/16] arm64: zynqmp: Remove double spaces from dts file

[Michal Simek]

There is no reason to have double spaces for indentation.

Signed-off-by: Michal Simek 
---

 arch/arm/dts/zynqmp-zcu102-rev1.0.dts | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/dts/zynqmp-zcu102-rev1.0.dts 
b/arch/arm/dts/zynqmp-zcu102-rev1.0.dts
index b1a95a91d18d..6647e97edba3 100644
--- a/arch/arm/dts/zynqmp-zcu102-rev1.0.dts
+++ b/arch/arm/dts/zynqmp-zcu102-rev1.0.dts
@@ -14,7 +14,7 @@
compatible = "xlnx,zynqmp-zcu102-rev1.0", "xlnx,zynqmp-zcu102", 
"xlnx,zynqmp";
 };
 
-  {
+ {
#address-cells = <1>;
#size-cells = <1>;
 
-- 
1.9.1

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[U-Boot] [PATCH 08/16] arm64: zynqmp: Fix spi flash partition definition for zc1751 dc2

[Michal Simek]

Using different node name and label partitions as data.
Also use latest compatible strings based on mainline review.

Signed-off-by: Michal Simek 
---

 arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts | 16 
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts 
b/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts
index 22a3c1ebeccc..afa90a8a5b09 100644
--- a/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts
+++ b/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts
@@ -178,15 +178,15 @@
  {
status = "okay";
num-cs = <1>;
-   spi0_flash0: spi0_flash0@0 {
-   compatible = "m25p80";
+   spi0_flash0: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
+   compatible = "sst,sst25wf080", "jedec,spi-nor";
spi-max-frequency = <5000>;
reg = <0>;
 
-   spi0_flash0@0 {
-   label = "spi0_flash0";
+   partition@0 {
+   label = "data";
reg = <0x0 0x10>;
};
};
@@ -195,15 +195,15 @@
  {
status = "okay";
num-cs = <1>;
-   spi1_flash0: spi1_flash0@0 {
-   compatible = "mtd_dataflash";
+   spi1_flash0: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
+   compatible = "atmel,at45db041e", "atmel,at45", 
"atmel,dataflash";
spi-max-frequency = <2000>;
reg = <0>;
 
-   spi1_flash0@0 {
-   label = "spi1_flash0";
+   partition@0 {
+   label = "data";
reg = <0x0 0x84000>;
};
};
-- 
1.9.1

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[U-Boot] [PATCH 12/16] arm64: zynqmp: Update sd properties for dc5

[Michal Simek]

From: Srinivas Goud 

This patch adds no-1-8-v below properties to sd node for dc5 board dts.

Signed-off-by: Srinivas Goud 
Signed-off-by: Michal Simek 
---

 arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts 
b/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts
index 16a14eacd8e9..0632b18ccf00 100644
--- a/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts
+++ b/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts
@@ -92,6 +92,7 @@
 
  {
status = "okay";
+   no-1-8-v;
 };
 
  {
-- 
1.9.1

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Re: [U-Boot] [PATCH v4 13/19] sunxi: DT: A64: update board .dts files from Linux

[Andre Przywara]

Hi Maxime,

thanks for the answer.

On 27/03/18 15:30, Maxime Ripard wrote:
> Hi,
> 
> On Sat, Mar 24, 2018 at 01:07:27AM +, André Przywara wrote:
>> On 23/03/18 18:14, Jagan Teki wrote:
>>> On Wed, Mar 14, 2018 at 7:27 AM, Andre Przywara  
>>> wrote:
 Update the .dts files for the various boards with an Allwinner A64 SoC.
 This is as of v4.15-rc9, exactly Linux commit:
>>
>> 
>>

   {
 pinctrl-names = "default";
 pinctrl-0 = <_pins>;
 -   vmmc-supply = <_vcc3v3>;
 +   vmmc-supply = <_dcdc1>;
>>>
>>> These AXP regulator stuff need to wait until the relevant driver
>>> supported through dt
>>
>> Well, we could take the two patches I had in v3 that revert this change.
>> As mentioned before, DCDC1 is an always-on regulator anyways.
>>
>> But actually that's not our problem, as we don't define DM_REGULATORS,
>> so we will never parse those properties.
>>
>> Instead:
>>
>>> otherwise moving to DM_MMC might fail to get the
>>> regulator? [1]
>>> [1] https://patchwork.ozlabs.org/patch/887405/
>>
>> Ah, thanks for the link, I totally missed that.
>> So as Heinrich rightfully feared in his first patch, this change - for
>> all sunxi boards - breaks most of them: The DM-MMC part of the sunxi MMC
>> driver is not ready for any other SoC than the A20:
>> a) The only compatible string it knows is "allwinner,sun5i-a13-mmc".
>> b) It assumes the old style clocks, even without checking if the
>> referenced nodes are compatible.
>>
>> So while a) is trivial to fix (U-Boot probably does not need to care
>> about the differences in the MMC controllers of the different SoCs), b)
>> is more of a beast.
>> I started looking into an easy implementation of the new clocks,
>> basically just enough to get MMC going, for the H3/H5 and A64. This
>> could be extended for other clocks once we need them.
>> But I am afraid this is not 2018.05 material anymore.
>>
>> So what do we do here?
>>
>> 1) Just switch over A20? The A20 DTs in U-Boot use the old-style clocks
>> still, so that's fine. And we postpone the DM-MMC switch for the rest
>> until we have some DM new-style clock driver?
> 
> I'm not sure I'd like to do that to be honest, this sounds like
> something that will never happen.
> 
>> 2) Push forward on some simple sunxi-ng MMC clock driver?
> 
> That one would work for me
> 
>> 3) Don't use DM_MMC at all?
> 
> Given the warning that was set for the next release, I'm not sure we
> have much choice unfortunately.

OK. So meanwhile I have something almost(TM) working:
- drivers/clk/sunxi/clk-a64.c, which is a UCLASS_CLK implementation of
the clock IDs from allwinner,sun50i-a64-ccu that we need: CLK_BUS_UARTx,
CLK_BUS_MMCx, CLK_MMCx. Their implementation is fairly simple, actually
(I did it the U-Boot way, not pulling in any super-fancy Linux code).
Porting this over to H3/H5 and other SoCs should be trivial: copy/paste
for now. We can look at how to unify this later.
- drivers/mmc/sunxi_mmc.c extended to use UCLASS_CLK clocks. This is
also not too bad, but I seem to miss a bit in here, as it times out.
Will debug this tonight.
- Cowardly dodging a proper UCLASS_RESET driver for now, instead hacking
the single bit in :-(

That looks tight to still get into this merge window, though, at least
if we follow the usual process.

Keep you posted.

Cheers,
Andre.
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[U-Boot] [PATCH 02/16] arm64: zynqmp: Use maxim prefix for all maxim chips

[Michal Simek]

Use vendor prefix for Maxim chips.

Signed-off-by: Michal Simek 
---

 arch/arm/dts/zynqmp-zcu102-revA.dts | 28 ++--
 arch/arm/dts/zynqmp-zcu102-revB.dts |  2 +-
 2 files changed, 15 insertions(+), 15 deletions(-)

diff --git a/arch/arm/dts/zynqmp-zcu102-revA.dts 
b/arch/arm/dts/zynqmp-zcu102-revA.dts
index 2be6eb0eb5eb..1c9e4b1bd328 100644
--- a/arch/arm/dts/zynqmp-zcu102-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu102-revA.dts
@@ -333,51 +333,51 @@
reg = <2>;
/* MAXIM_PMBUS - 00 */
max15301@a { /* u46 */
-   compatible = "max15301";
+   compatible = "maxim,max15301";
reg = <0xa>;
};
max15303@b { /* u4 */
-   compatible = "max15303";
+   compatible = "maxim,max15303";
reg = <0xb>;
};
max15303@10 { /* u13 */
-   compatible = "max15303";
+   compatible = "maxim,max15303";
reg = <0x10>;
};
max15301@13 { /* u47 */
-   compatible = "max15301";
+   compatible = "maxim,max15301";
reg = <0x13>;
};
max15303@14 { /* u7 */
-   compatible = "max15303";
+   compatible = "maxim,max15303";
reg = <0x14>;
};
max15303@15 { /* u6 */
-   compatible = "max15303";
+   compatible = "maxim,max15303";
reg = <0x15>;
};
max15303@16 { /* u10 */
-   compatible = "max15303";
+   compatible = "maxim,max15303";
reg = <0x16>;
};
max15303@17 { /* u9 */
-   compatible = "max15303";
+   compatible = "maxim,max15303";
reg = <0x17>;
};
max15301@18 { /* u63 */
-   compatible = "max15301";
+   compatible = "maxim,max15301";
reg = <0x18>;
};
max15303@1a { /* u49 */
-   compatible = "max15303";
+   compatible = "maxim,max15303";
reg = <0x1a>;
};
max15303@1d { /* u18 */
-   compatible = "max15303";
+   compatible = "maxim,max15303";
reg = <0x1d>;
};
max15303@20 { /* u8 */
-   compatible = "max15303";
+   compatible = "maxim,max15303";
status = "disabled"; /* unreachable */
reg = <0x20>;
};
@@ -386,11 +386,11 @@
 drivers/hwmon/pmbus/Makefile:11:obj-$(CONFIG_SENSORS_MAX20751)  += max20751.o
 */
max20751@72 { /* u95 FIXME - not detected */
-   compatible = "max20751";
+   compatible = "maxim,max20751";
reg = <0x72>;
};
max20751@73 { /* u96 FIXME - not detected */
-   compatible = "max20751";
+   compatible = "maxim,max20751";
reg = <0x73>;
};
};
diff --git a/arch/arm/dts/zynqmp-zcu102-revB.dts 
b/arch/arm/dts/zynqmp-zcu102-revB.dts
index c771a946b21b..d0acb29b64b3 100644
--- a/arch/arm/dts/zynqmp-zcu102-revB.dts
+++ b/arch/arm/dts/zynqmp-zcu102-revB.dts
@@ -34,7 +34,7 @@
i2cswitch@75 {
i2c@2 {
max15303@1b { /* u8 */
-   compatible = "max15303";
+   compatible = "maxim,max15303";
reg = <0x1b>;
};
/delete-node/ max15303@20;
-- 
1.9.1

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[U-Boot] [PATCH 11/16] arm64: zynqmp: Enable ttcs for zc1751 dc5

[Michal Simek]

Enable TTCs for this target as is done in Linux kernel.

Signed-off-by: Michal Simek 
---

 arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts | 16 
 1 file changed, 16 insertions(+)

diff --git a/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts 
b/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts
index fe737be038f1..16a14eacd8e9 100644
--- a/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts
+++ b/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts
@@ -94,6 +94,22 @@
status = "okay";
 };
 
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
+
  {
status = "okay";
 };
-- 
1.9.1

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[U-Boot] [PATCH 06/16] arm64: zynqmp: Use keycode from input/input.h

[Michal Simek]

Instead of hardcoding numbers.

Signed-off-by: Michal Simek 
---

 arch/arm/dts/zynqmp-zcu102-revA.dts | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/arm/dts/zynqmp-zcu102-revA.dts 
b/arch/arm/dts/zynqmp-zcu102-revA.dts
index efa94a14194b..c04e37dc65f3 100644
--- a/arch/arm/dts/zynqmp-zcu102-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu102-revA.dts
@@ -11,6 +11,7 @@
 
 #include "zynqmp.dtsi"
 #include "zynqmp-clk-ccf.dtsi"
+#include 
 #include 
 #include 
 #include 
@@ -51,7 +52,7 @@
sw19 {
label = "sw19";
gpios = < 22 GPIO_ACTIVE_HIGH>;
-   linux,code = <108>; /* down */
+   linux,code = ;
gpio-key,wakeup;
autorepeat;
};
-- 
1.9.1

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[U-Boot] [PATCH 09/16] arm64: zynqmp: Use atmel prefix instead of at

[Michal Simek]

This changes was done in mainline and this patch is just following it.

Signed-off-by: Michal Simek 
---

 arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts | 2 +-
 arch/arm/dts/zynqmp-zcu102-revA.dts  | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts 
b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts
index 3c2054734c4b..7968aa7bec5d 100644
--- a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts
+++ b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts
@@ -92,7 +92,7 @@
status = "okay";
clock-frequency = <40>;
eeprom@55 {
-   compatible = "at,24c64"; /* 24AA64 */
+   compatible = "atmel,24c64"; /* 24AA64 */
reg = <0x55>;
};
 };
diff --git a/arch/arm/dts/zynqmp-zcu102-revA.dts 
b/arch/arm/dts/zynqmp-zcu102-revA.dts
index c04e37dc65f3..60d3f7103170 100644
--- a/arch/arm/dts/zynqmp-zcu102-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu102-revA.dts
@@ -422,7 +422,7 @@
 * 768B - 1024B address 0x57
 */
eeprom: eeprom@54 { /* u23 */
-   compatible = "at,24c08";
+   compatible = "atmel,24c08";
reg = <0x54>;
};
};
-- 
1.9.1

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[U-Boot] [PATCH 05/16] arm64: zynqmp: Remove additional comments from dts files

[Michal Simek]

Remove additional comments which were removed as the part of upstreaming.

Signed-off-by: Michal Simek 
---

 arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts |  1 -
 arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts |  1 -
 arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts |  1 -
 arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts |  3 ---
 arch/arm/dts/zynqmp-zcu102-revA.dts  | 29 -
 arch/arm/dts/zynqmp-zcu102-revB.dts  |  2 --
 6 files changed, 8 insertions(+), 29 deletions(-)

diff --git a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts 
b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts
index 0ddb43df6d4f..3c2054734c4b 100644
--- a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts
+++ b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts
@@ -39,7 +39,6 @@
};
 };
 
-/* fpd_dma clk 667MHz, lpd_dma 500MHz */
 _dma_chan1 {
status = "okay";
 };
diff --git a/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts 
b/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts
index 670cc447559c..22a3c1ebeccc 100644
--- a/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts
+++ b/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts
@@ -49,7 +49,6 @@
status = "okay";
 };
 
-/* fpd_dma clk 667MHz, lpd_dma 500MHz */
 _dma_chan1 {
status = "okay";
 };
diff --git a/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts 
b/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts
index 41012fa61de5..fb49b4fcb492 100644
--- a/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts
+++ b/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts
@@ -51,7 +51,6 @@
status = "okay";
 };
 
-/* fpd_dma clk 667MHz, lpd_dma 500MHz */
 _dma_chan1 {
status = "okay";
 };
diff --git a/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts 
b/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts
index 99aa74e54e67..fe737be038f1 100644
--- a/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts
+++ b/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts
@@ -37,7 +37,6 @@
};
 };
 
-/* fpd_dma clk 667MHz, lpd_dma 500MHz */
 _dma_chan1 {
status = "okay";
 };
@@ -83,12 +82,10 @@
status = "okay";
 };
 
-/* FIXME: Add device */
  {
status = "okay";
 };
 
-/* FIXME: Add device */
  {
status = "okay";
 };
diff --git a/arch/arm/dts/zynqmp-zcu102-revA.dts 
b/arch/arm/dts/zynqmp-zcu102-revA.dts
index c9cffc125bfb..efa94a14194b 100644
--- a/arch/arm/dts/zynqmp-zcu102-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu102-revA.dts
@@ -77,7 +77,6 @@
status = "okay";
 };
 
-/* fpd_dma clk 667MHz, lpd_dma 500MHz */
 _dma_chan1 {
status = "okay";
 };
@@ -381,23 +380,17 @@
reg = <0x20>;
};
 
-/* drivers/hwmon/pmbus/Kconfig:86:   be called max20751.
-drivers/hwmon/pmbus/Makefile:11:obj-$(CONFIG_SENSORS_MAX20751)  += max20751.o
-*/
-   max20751@72 { /* u95 FIXME - not detected */
+   max20751@72 { /* u95 */
compatible = "maxim,max20751";
reg = <0x72>;
};
-   max20751@73 { /* u96 FIXME - not detected */
+   max20751@73 { /* u96 */
compatible = "maxim,max20751";
reg = <0x73>;
};
};
/* Bus 3 is not connected */
};
-
-   /* FIXME PMOD - j160 */
-   /* FIXME MSP430F - u41 - not detected */
 };
 
  {
@@ -409,8 +402,7 @@ 
drivers/hwmon/pmbus/Makefile:11:obj-$(CONFIG_SENSORS_MAX20751)  += max20751.o
scl-gpios = < 16 GPIO_ACTIVE_HIGH>;
sda-gpios = < 17 GPIO_ACTIVE_HIGH>;
 
-   /* FIXME PL i2c via PCA9306 - u45 */
-   /* FIXME MSP430 - u41 - not detected */
+   /* PL i2c via PCA9306 - u45 */
i2c-mux@74 { /* u34 */
compatible = "nxp,pca9548";
#address-cells = <1>;
@@ -515,24 +507,19 @@ 
drivers/hwmon/pmbus/Makefile:11:obj-$(CONFIG_SENSORS_MAX20751)  += max20751.o
#size-cells = <0>;
reg = <3>;
/* DDR4 SODIMM */
-   dev@19 { /* u-boot detection */
-   compatible = "xxx";
+   dev@19 {
reg = <0x19>;
};
-   dev@30 { /* u-boot detection */
-   compatible = "xxx";
+   dev@30 {
reg = <0x30>;
};
-   dev@35 { /* u-boot detection */
-   compatible = "xxx";
+   dev@35 {
reg = <0x35>;
};
-   dev@36 { /* u-boot detection */
-   compatible = "xxx";
+   dev@36 {
reg = <0x36>;
};
-   dev@51 { /* u-boot detection - maybe SPD */
- 

[U-Boot] [PATCH 04/16] arm64: zynqmp: Sync up license with mainline kernel

[Michal Simek]

Mainline Linux kernel has adopted SPDX header license in a different
format then was used before. This patch is syncing it up.

Also update years in License text and remove Nathalie's email because it
is no longer valid.

Signed-off-by: Michal Simek 
---

 arch/arm/dts/zynqmp-clk-ccf.dtsi | 3 +--
 arch/arm/dts/zynqmp-clk.dtsi | 5 ++---
 arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts | 5 ++---
 arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts | 5 ++---
 arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts | 5 ++---
 arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts | 5 ++---
 arch/arm/dts/zynqmp-zcu102-rev1.0.dts| 5 ++---
 arch/arm/dts/zynqmp-zcu102-revA.dts  | 5 ++---
 arch/arm/dts/zynqmp-zcu102-revB.dts  | 5 ++---
 arch/arm/dts/zynqmp.dtsi | 6 +-
 10 files changed, 22 insertions(+), 27 deletions(-)

diff --git a/arch/arm/dts/zynqmp-clk-ccf.dtsi b/arch/arm/dts/zynqmp-clk-ccf.dtsi
index 4449d5b93d1f..b18d8d19c304 100644
--- a/arch/arm/dts/zynqmp-clk-ccf.dtsi
+++ b/arch/arm/dts/zynqmp-clk-ccf.dtsi
@@ -1,11 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * Clock specification for Xilinx ZynqMP
  *
  * (C) Copyright 2017, Xilinx, Inc.
  *
  * Michal Simek 
- *
- * SPDX-License-Identifier: GPL-2.0+
  */
 
 / {
diff --git a/arch/arm/dts/zynqmp-clk.dtsi b/arch/arm/dts/zynqmp-clk.dtsi
index f6e83e15132a..45d84a6b7df9 100644
--- a/arch/arm/dts/zynqmp-clk.dtsi
+++ b/arch/arm/dts/zynqmp-clk.dtsi
@@ -1,11 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * Clock specification for Xilinx ZynqMP
  *
- * (C) Copyright 2015, Xilinx, Inc.
+ * (C) Copyright 2015 - 2018, Xilinx, Inc.
  *
  * Michal Simek 
- *
- * SPDX-License-Identifier:GPL-2.0+
  */
 
 / {
diff --git a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts 
b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts
index 9062ffe919e1..0ddb43df6d4f 100644
--- a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts
+++ b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts
@@ -1,11 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * dts file for Xilinx ZynqMP zc1751-xm015-dc1
  *
- * (C) Copyright 2015, Xilinx, Inc.
+ * (C) Copyright 2015 - 2018, Xilinx, Inc.
  *
  * Michal Simek 
- *
- * SPDX-License-Identifier:GPL-2.0+
  */
 
 /dts-v1/;
diff --git a/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts 
b/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts
index bf43bf874885..670cc447559c 100644
--- a/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts
+++ b/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts
@@ -1,11 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * dts file for Xilinx ZynqMP zc1751-xm016-dc2
  *
- * (C) Copyright 2015, Xilinx, Inc.
+ * (C) Copyright 2015 - 2018, Xilinx, Inc.
  *
  * Michal Simek 
- *
- * SPDX-License-Identifier:GPL-2.0+
  */
 
 /dts-v1/;
diff --git a/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts 
b/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts
index 39c82c592f73..41012fa61de5 100644
--- a/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts
+++ b/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts
@@ -1,11 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * dts file for Xilinx ZynqMP zc1751-xm018-dc4
  *
- * (C) Copyright 2015 - 2016, Xilinx, Inc.
+ * (C) Copyright 2015 - 2018, Xilinx, Inc.
  *
  * Michal Simek 
- *
- * SPDX-License-Identifier:GPL-2.0+
  */
 
 /dts-v1/;
diff --git a/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts 
b/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts
index c774b866fb14..99aa74e54e67 100644
--- a/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts
+++ b/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts
@@ -1,12 +1,11 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * dts file for Xilinx ZynqMP zc1751-xm019-dc5
  *
- * (C) Copyright 2015, Xilinx, Inc.
+ * (C) Copyright 2015 - 2018, Xilinx, Inc.
  *
  * Siva Durga Prasad 
  * Michal Simek 
- *
- * SPDX-License-Identifier:GPL-2.0+
  */
 
 /dts-v1/;
diff --git a/arch/arm/dts/zynqmp-zcu102-rev1.0.dts 
b/arch/arm/dts/zynqmp-zcu102-rev1.0.dts
index 323a674e3a62..3fc3e749913a 100644
--- a/arch/arm/dts/zynqmp-zcu102-rev1.0.dts
+++ b/arch/arm/dts/zynqmp-zcu102-rev1.0.dts
@@ -1,11 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * dts file for Xilinx ZynqMP ZCU102 Rev1.0
  *
- * (C) Copyright 2016, Xilinx, Inc.
+ * (C) Copyright 2016 - 2018, Xilinx, Inc.
  *
  * Michal Simek 
- *
- * SPDX-License-Identifier:GPL-2.0+
  */
 
 #include "zynqmp-zcu102-revB.dts"
diff --git a/arch/arm/dts/zynqmp-zcu102-revA.dts 
b/arch/arm/dts/zynqmp-zcu102-revA.dts
index 5f4ac22e1d7a..c9cffc125bfb 100644
--- a/arch/arm/dts/zynqmp-zcu102-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu102-revA.dts
@@ -1,11 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * dts file for Xilinx ZynqMP ZCU102 RevA
  *
- * (C) Copyright 2015, Xilinx, Inc.
+ * (C) Copyright 2015 - 2018, Xilinx, Inc.
  *
  * Michal Simek 
- *
- * 

[U-Boot] [PATCH 01/16] arm64: zynqmp: Sync alignment with mainline

[Michal Simek]

Sync pcie and lpd_dma nodes with mainline version.
Incorrect locations are causing diff in statistics that's why
synchronizations are needed.

Signed-off-by: Michal Simek 
---

 arch/arm/dts/zynqmp.dtsi | 19 ++-
 1 file changed, 10 insertions(+), 9 deletions(-)

diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi
index 5bdab6116451..e71399f83d27 100644
--- a/arch/arm/dts/zynqmp.dtsi
+++ b/arch/arm/dts/zynqmp.dtsi
@@ -547,10 +547,10 @@
lpd_dma_chan1: dma@ffa8 {
status = "disabled";
compatible = "xlnx,zynqmp-dma-1.0";
-   clock-names = "clk_main", "clk_apb";
reg = <0x0 0xffa8 0x0 0x1000>;
interrupt-parent = <>;
interrupts = <0 77 4>;
+   clock-names = "clk_main", "clk_apb";
xlnx,bus-width = <64>;
#stream-id-cells = <1>;
iommus = < 0x868>;
@@ -560,10 +560,10 @@
lpd_dma_chan2: dma@ffa9 {
status = "disabled";
compatible = "xlnx,zynqmp-dma-1.0";
-   clock-names = "clk_main", "clk_apb";
reg = <0x0 0xffa9 0x0 0x1000>;
interrupt-parent = <>;
interrupts = <0 78 4>;
+   clock-names = "clk_main", "clk_apb";
xlnx,bus-width = <64>;
#stream-id-cells = <1>;
iommus = < 0x869>;
@@ -573,10 +573,10 @@
lpd_dma_chan3: dma@ffaa {
status = "disabled";
compatible = "xlnx,zynqmp-dma-1.0";
-   clock-names = "clk_main", "clk_apb";
reg = <0x0 0xffaa 0x0 0x1000>;
interrupt-parent = <>;
interrupts = <0 79 4>;
+   clock-names = "clk_main", "clk_apb";
xlnx,bus-width = <64>;
#stream-id-cells = <1>;
iommus = < 0x86a>;
@@ -586,10 +586,10 @@
lpd_dma_chan4: dma@ffab {
status = "disabled";
compatible = "xlnx,zynqmp-dma-1.0";
-   clock-names = "clk_main", "clk_apb";
reg = <0x0 0xffab 0x0 0x1000>;
interrupt-parent = <>;
interrupts = <0 80 4>;
+   clock-names = "clk_main", "clk_apb";
xlnx,bus-width = <64>;
#stream-id-cells = <1>;
iommus = < 0x86b>;
@@ -599,10 +599,10 @@
lpd_dma_chan5: dma@ffac {
status = "disabled";
compatible = "xlnx,zynqmp-dma-1.0";
-   clock-names = "clk_main", "clk_apb";
reg = <0x0 0xffac 0x0 0x1000>;
interrupt-parent = <>;
interrupts = <0 81 4>;
+   clock-names = "clk_main", "clk_apb";
xlnx,bus-width = <64>;
#stream-id-cells = <1>;
iommus = < 0x86c>;
@@ -612,10 +612,10 @@
lpd_dma_chan6: dma@ffad {
status = "disabled";
compatible = "xlnx,zynqmp-dma-1.0";
-   clock-names = "clk_main", "clk_apb";
reg = <0x0 0xffad 0x0 0x1000>;
interrupt-parent = <>;
interrupts = <0 82 4>;
+   clock-names = "clk_main", "clk_apb";
xlnx,bus-width = <64>;
#stream-id-cells = <1>;
iommus = < 0x86d>;
@@ -625,10 +625,10 @@
lpd_dma_chan7: dma@ffae {
status = "disabled";
compatible = "xlnx,zynqmp-dma-1.0";
-   clock-names = "clk_main", "clk_apb";
reg = <0x0 0xffae 0x0 0x1000>;
interrupt-parent = <>;
interrupts = <0 83 4>;
+   clock-names = "clk_main", "clk_apb";
xlnx,bus-width = <64>;
#stream-id-cells = <1>;
iommus = < 0x86e>;
@@ -638,10 +638,10 @@
lpd_dma_chan8: dma@ffaf {
status = "disabled";
compatible = "xlnx,zynqmp-dma-1.0";
-   clock-names = "clk_main", "clk_apb";
reg = <0x0 0xffaf 0x0 0x1000>;
interrupt-parent = <>;
interrupts = <0 84 4>;
+   clock-names = 

[U-Boot] [PATCH 00/16] Syncup DTS files with mainline Linux kernel

[Michal Simek]

Upstreaming and reviewing of more zynqmp boards pointed to some issues
which should be fixed also in u-boot.
This patchset is synchronizing things which were reviewed.

Thanks,
Michal


Michal Simek (15):
  arm64: zynqmp: Sync alignment with mainline
  arm64: zynqmp: Use maxim prefix for all maxim chips
  arm64: zynqmp: Use i2c-mux instead of i2cswitch instead
  arm64: zynqmp: Sync up license with mainline kernel
  arm64: zynqmp: Remove additional comments from dts files
  arm64: zynqmp: Use keycode from input/input.h
  arm64: zynqmp: Use s/_/-/g in node name for zcu102 rev1.0
  arm64: zynqmp: Fix spi flash partition definition for zc1751 dc2
  arm64: zynqmp: Use atmel prefix instead of at
  arm64: zynqmp: Add eeprom reference to eeprom nodes
  arm64: zynqmp: Enable ttcs for zc1751 dc5
  arm64: zynqmp: Remove u-boot commands from dts files
  arm64: zynqmp: Remove number from clock-generator node name
  arm64: zynqmp: Add silabs prefix to u69 for zcu102
  arm64: zynqmp: Remove double spaces from dts file

Srinivas Goud (1):
  arm64: zynqmp: Update sd properties for dc5

 arch/arm/dts/zynqmp-clk-ccf.dtsi |   3 +-
 arch/arm/dts/zynqmp-clk.dtsi |   5 +-
 arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts |  11 ++--
 arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts |  22 +++
 arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts |   6 +-
 arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts |  25 +--
 arch/arm/dts/zynqmp-zcu102-rev1.0.dts|  15 ++---
 arch/arm/dts/zynqmp-zcu102-revA.dts  | 109 +--
 arch/arm/dts/zynqmp-zcu102-revB.dts  |  11 ++--
 arch/arm/dts/zynqmp.dtsi |  25 ---
 10 files changed, 110 insertions(+), 122 deletions(-)

-- 
1.9.1

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Re: [U-Boot] [PATCH] watchdog: Add Cadence watchdog driver

[Michal Simek]

Hi,

On 26.3.2018 21:48, Heinrich Schuchardt wrote:
> Hello Shreenidhi,
> 
> with the patch you added the CONFIG_WATCHDOG to drivers/watchdog/Kconfig.
> 
> Could you, please, add a description of CONFIG_WATCHDOG to
> doc/README.watchdog.

If you look at the history then last reasonable change was done in 2015
by Simon. Content of this file could be most likely just added to
Kconfig and it can be removed.

> 
> In include/watchdog.h I found this:
> "CONFIG_HW_WATCHDOG and CONFIG_WATCHDOG can't be used together."
> 
> So shouldn't CONFIG_WATCHDOG depend on !HW_WATCHDOG in Kconfig?
> This avoids a possible error at compile time.

!HW_WATCHDOG should be probably the part of config WDT not just for
CDNS.

Thanks,
Michal

-- 
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Xilinx Microblaze
Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP ARM64 SoCs
U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP SoCs




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Re: [U-Boot] [PATCH v4 13/19] sunxi: DT: A64: update board .dts files from Linux

[Maxime Ripard]

Hi,

On Sat, Mar 24, 2018 at 01:07:27AM +, André Przywara wrote:
> On 23/03/18 18:14, Jagan Teki wrote:
> > On Wed, Mar 14, 2018 at 7:27 AM, Andre Przywara  
> > wrote:
> >> Update the .dts files for the various boards with an Allwinner A64 SoC.
> >> This is as of v4.15-rc9, exactly Linux commit:
> 
> 
> 
> >>
> >>   {
> >> pinctrl-names = "default";
> >> pinctrl-0 = <_pins>;
> >> -   vmmc-supply = <_vcc3v3>;
> >> +   vmmc-supply = <_dcdc1>;
> > 
> > These AXP regulator stuff need to wait until the relevant driver
> > supported through dt
> 
> Well, we could take the two patches I had in v3 that revert this change.
> As mentioned before, DCDC1 is an always-on regulator anyways.
> 
> But actually that's not our problem, as we don't define DM_REGULATORS,
> so we will never parse those properties.
> 
> Instead:
> 
> > otherwise moving to DM_MMC might fail to get the
> > regulator? [1]
> > [1] https://patchwork.ozlabs.org/patch/887405/
> 
> Ah, thanks for the link, I totally missed that.
> So as Heinrich rightfully feared in his first patch, this change - for
> all sunxi boards - breaks most of them: The DM-MMC part of the sunxi MMC
> driver is not ready for any other SoC than the A20:
> a) The only compatible string it knows is "allwinner,sun5i-a13-mmc".
> b) It assumes the old style clocks, even without checking if the
> referenced nodes are compatible.
> 
> So while a) is trivial to fix (U-Boot probably does not need to care
> about the differences in the MMC controllers of the different SoCs), b)
> is more of a beast.
> I started looking into an easy implementation of the new clocks,
> basically just enough to get MMC going, for the H3/H5 and A64. This
> could be extended for other clocks once we need them.
> But I am afraid this is not 2018.05 material anymore.
> 
> So what do we do here?
> 
> 1) Just switch over A20? The A20 DTs in U-Boot use the old-style clocks
> still, so that's fine. And we postpone the DM-MMC switch for the rest
> until we have some DM new-style clock driver?

I'm not sure I'd like to do that to be honest, this sounds like
something that will never happen.

> 2) Push forward on some simple sunxi-ng MMC clock driver?

That one would work for me

> 3) Don't use DM_MMC at all?

Given the warning that was set for the next release, I'm not sure we
have much choice unfortunately.

Maxime

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Embedded Linux and Kernel engineering
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[U-Boot] [PATCH 1/1] sunxi: mmc: Fix phase delays

[Stefan Mavrodiev]

U-boot driver for sunxi-mmc uses PLL6, unlike linux kernel where
PLL5 is used, with clock rates respectively 600MHz and 768MHz.
Thus there are different phase degree steps - 24 for the kernel and
30 for u-boot.

In the kernel driver the phase is set 90 deg for output and 120 for
sample. Dividing by 30 will result values 3 and 4. Those are the
values set in the u-boot driver.

However, the condition defining delays is wrong. MMC core driver
requests clock of 52MHz, sunxi-driver sets clock of 50MHz, but
phase is set 30 deg for output and 120 deg for sample.

Apparently this works for most cards.
On A20-SOM204-EVB-eMMC there is eMMC card (KLMAG2GEND) which complains
about it. Maybe there is other boards with similar problem?
So the fix is to match delays for both u-boot and kernel.

Signed-off-by: Stefan Mavrodiev 
---
 drivers/mmc/sunxi_mmc.c | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c
index 4edb4be..be55dc4 100644
--- a/drivers/mmc/sunxi_mmc.c
+++ b/drivers/mmc/sunxi_mmc.c
@@ -146,19 +146,19 @@ static int mmc_set_mod_clk(struct sunxi_mmc_priv *priv, 
unsigned int hz)
oclk_dly = 0;
sclk_dly = 5;
 #ifdef CONFIG_MACH_SUN9I
-   } else if (hz <= 5000) {
+   } else if (hz <= 5200) {
oclk_dly = 5;
sclk_dly = 4;
} else {
-   /* hz > 5000 */
+   /* hz > 5200 */
oclk_dly = 2;
sclk_dly = 4;
 #else
-   } else if (hz <= 5000) {
+   } else if (hz <= 5200) {
oclk_dly = 3;
sclk_dly = 4;
} else {
-   /* hz > 5000 */
+   /* hz > 5200 */
oclk_dly = 1;
sclk_dly = 4;
 #endif
-- 
2.7.4

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Re: [U-Boot] [PATCH] cmd: nvedit: Add filtering during env import

[Quentin Schulz]

On Tue, Mar 27, 2018 at 03:14:59PM +0200, Quentin Schulz wrote:
> On Tue, Mar 27, 2018 at 01:39:25PM +0100, Alex Kiernan wrote:
> > On Tue, Mar 27, 2018 at 10:28 AM, Quentin Schulz
> >  wrote:
> > > Hi Alex,
> > >
> > > On Tue, Mar 27, 2018 at 08:43:26AM +, Alex Kiernan wrote:
> > >> When importing variables allow size to be elided using '-' and then
> > >> support a list of variables which restricts what will be picked during
> > >> the import.
> > >>
> > >> Signed-off-by: Alex Kiernan 
> > >
> > > I'm pretty sure it's the same goal as this patch[1] I suggested.
> > 
> > It is, maybe it was your message I was thinking of when I asked the
> > question the other day:
> > 
> > https://lists.denx.de/pipermail/u-boot/2018-March/323687.html
> > 
> > > Could you answer in the thread telling you need it as well so that we
> > > could get it merged or at least reviewed?
> > >
> > 
> > Assuming I've understood your patch correctly, I think I can replicate
> > your use case with this:
> > 
> >   env import ... ${whitelisted_vars}
> > 
> > I've two uses for this right now for this - with different white lists:
> > 
> >   # override defaults from uboot.env
> >   if fatload mmc ${mmcdev} ${loadaddr} uboot.env; then
> >   env import -c ${loadaddr} ${filesize} serial# ethaddr
> >   fi
> > 
> >   # source OSTree deployments
> >   if load ${devtype} ${bootpart} ${loadaddr} /boot/loader/uEnv.txt; then
> >   env import -t ${loadaddr} ${filesize} kernel_image
> > kernel_image2 bootargs bootargs2
> >   fi
> > 
> 
> What I don't like with this approach is that it's going to be very hard
> to read the line if you want to import a lot of variables.
> 
> You could do the same with just a
> 
> setenv whitelisted_vars my_var0 my_var1
> env import -w -t ${loadaddr} ${filesize}
> 
> setenv whitelisted_vars my_var2
> env import -w -t ${loadaddr} ${filesize}
> 
> I find it more readable.
> 

OK, so that was a bad example as you could do the same with your patch
:D

What I'm more concerned about is that after we've merged your patch,
it isn't possible to pass multiple parameters at the end of the command.
There might be (I have no example as of today) some things we want to do
in the future that can't be done an other way than passing a list of
arguments at the end of the command and your patch prevent doing so in
the future.

We can do it now with a single option (-w or whatever letter we want to
use) so I guess it's better to leave the option for cases that really
require to have a list of parameters passed to the command.

Quentin


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Re: [U-Boot] [PATCH] cmd: nvedit: Add filtering during env import

[Quentin Schulz]

On Tue, Mar 27, 2018 at 01:39:25PM +0100, Alex Kiernan wrote:
> On Tue, Mar 27, 2018 at 10:28 AM, Quentin Schulz
>  wrote:
> > Hi Alex,
> >
> > On Tue, Mar 27, 2018 at 08:43:26AM +, Alex Kiernan wrote:
> >> When importing variables allow size to be elided using '-' and then
> >> support a list of variables which restricts what will be picked during
> >> the import.
> >>
> >> Signed-off-by: Alex Kiernan 
> >
> > I'm pretty sure it's the same goal as this patch[1] I suggested.
> 
> It is, maybe it was your message I was thinking of when I asked the
> question the other day:
> 
> https://lists.denx.de/pipermail/u-boot/2018-March/323687.html
> 
> > Could you answer in the thread telling you need it as well so that we
> > could get it merged or at least reviewed?
> >
> 
> Assuming I've understood your patch correctly, I think I can replicate
> your use case with this:
> 
>   env import ... ${whitelisted_vars}
> 
> I've two uses for this right now for this - with different white lists:
> 
>   # override defaults from uboot.env
>   if fatload mmc ${mmcdev} ${loadaddr} uboot.env; then
>   env import -c ${loadaddr} ${filesize} serial# ethaddr
>   fi
> 
>   # source OSTree deployments
>   if load ${devtype} ${bootpart} ${loadaddr} /boot/loader/uEnv.txt; then
>   env import -t ${loadaddr} ${filesize} kernel_image
> kernel_image2 bootargs bootargs2
>   fi
> 

What I don't like with this approach is that it's going to be very hard
to read the line if you want to import a lot of variables.

You could do the same with just a

setenv whitelisted_vars my_var0 my_var1
env import -w -t ${loadaddr} ${filesize}

setenv whitelisted_vars my_var2
env import -w -t ${loadaddr} ${filesize}

I find it more readable.

Quentin


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[U-Boot] [PATCH] ext4fs: Add ext4 extent tree cache

[evan . g . thompson]

From: Evan Thompson 

In ext4, the file inode can store up to 4 extents. If a file requires
more (due to size or fragmentation), an extent index tree is used.

Currently, u-boot reads a node from each level of the extent tree
for every block read, which is very inefficient when extent tree
depth is > 0.

This patch adds a cache for the extent tree. We cache the 1
most-recently-seen node at each extent tree level. The typical workload
is sequential block access, so once we leave a given tree node, it will
not be revisited. Therefore, it makes sense to just cache one node
per tree level.

Cached blocks are lazily allocated. The typical case is extent tree
depth = 0, in which case no caching is needed and no allocations will
occur.

For files with extent tree depth = 1, this patch produces a ~10x
improvement in read speed. For deeper extent trees, the improvement is
larger. On my test device, a 3MB file which previously took 9s to read
now takes 150ms.

Cache size is configurable with CONFIG_EXT4_EXTENT_CACHE_SIZE. However
the default of 5 (the maximum depth of well-formed extent trees) is
recommended.

Signed-off-by: Evan Thompson 
---
 doc/README.ext4   |  7 +
 fs/ext4/ext4_common.c | 74 +++
 2 files changed, 76 insertions(+), 5 deletions(-)

diff --git a/doc/README.ext4 b/doc/README.ext4
index 8ecd21eee3..a501b92396 100644
--- a/doc/README.ext4
+++ b/doc/README.ext4
@@ -33,6 +33,13 @@ In addition, to get the write access command "ext4write", 
enable:
 which automatically selects CONFIG_EXT4_WRITE if it wasn't defined
 already.
 
+For files with extents, an ext4 extent tree cache improves performance:
+
+  CONFIG_EXT4_EXTENT_CACHE_SIZE <#>
+
+The above cache size defaults to 5 if not defined. This default is
+strongly recommended. 0 will turn off extent caching.
+
 Also relevant are the generic filesystem commands, selected by:
 
   CONFIG_CMD_FS_GENERIC
diff --git a/fs/ext4/ext4_common.c b/fs/ext4/ext4_common.c
index e3cc30a1e0..61aade1ced 100644
--- a/fs/ext4/ext4_common.c
+++ b/fs/ext4/ext4_common.c
@@ -1523,6 +1523,47 @@ void ext4fs_allocate_blocks(struct ext2_inode 
*file_inode,
 
 #endif
 
+/* Extent tree cache caches one entry per tree level
+ * eg, ext_block->eh_depth is used as the index into the cache
+ *
+ * If the tree is deeper than CONFIG_EXT4_EXTENT_CACHE_SIZE (very unlikely),
+ * file read performance will be impacted by repeated re-reads
+ * of those index nodes.
+ */
+
+#ifndef CONFIG_EXT4_EXTENT_CACHE_SIZE
+#define CONFIG_EXT4_EXTENT_CACHE_SIZE 5
+#endif
+
+struct extent_cache_entry {
+   unsigned long long block;
+   struct ext4_extent_header *ext_block;
+};
+
+static struct extent_cache_entry
+   extent_cache[CONFIG_EXT4_EXTENT_CACHE_SIZE];
+
+static void ext4fs_init_extent_block_cache(void)
+{
+   int i;
+
+   for (i = 0; i < CONFIG_EXT4_EXTENT_CACHE_SIZE; i++) {
+   extent_cache[i].block = 0;
+   extent_cache[i].ext_block = NULL;
+   }
+}
+
+static void ext4fs_free_extent_block_cache(void)
+{
+   int i;
+
+   for (i = 0; i < CONFIG_EXT4_EXTENT_CACHE_SIZE; i++) {
+   extent_cache[i].block = 0;
+   free(extent_cache[i].ext_block);
+   extent_cache[i].ext_block = NULL;
+   }
+}
+
 static struct ext4_extent_header *ext4fs_get_extent_block
(struct ext2_data *data, char *buf,
struct ext4_extent_header *ext_block,
@@ -1532,6 +1573,7 @@ static struct ext4_extent_header *ext4fs_get_extent_block
unsigned long long block;
int blksz = EXT2_BLOCK_SIZE(data);
int i;
+   unsigned int cache_item;
 
while (1) {
index = (struct ext4_extent_idx *)(ext_block + 1);
@@ -1554,11 +1596,31 @@ static struct ext4_extent_header 
*ext4fs_get_extent_block
block = le16_to_cpu(index[i].ei_leaf_hi);
block = (block << 32) + le32_to_cpu(index[i].ei_leaf_lo);
 
-   if (ext4fs_devread((lbaint_t)block << log2_blksz, 0, blksz,
-  buf))
-   ext_block = (struct ext4_extent_header *)buf;
-   else
-   return NULL;
+   // check cache, read block from device if not found
+   cache_item = le16_to_cpu(ext_block->eh_depth) - 1;
+   if (cache_item < CONFIG_EXT4_EXTENT_CACHE_SIZE &&
+   extent_cache[cache_item].block == block) {
+   ext_block = extent_cache[cache_item].ext_block;
+   } else {
+   if (ext4fs_devread((lbaint_t)block << log2_blksz, 0,
+  blksz, buf))
+   ext_block = (struct ext4_extent_header *)buf;
+   else
+   return NULL;
+   // put in cache
+   

[U-Boot] [PATCH v3 00/10] Add support for DM_USB for TI's DRA7 EVMs and AM57 EVMs platforms

[Jean-Jacques Hiblot]

Supporting DM USB is required to support DM_ETH and USB network adapters
with the same binary.
This series adds support for DM_USB for the DRA7/AM57 families. It
leverages the work done for the STi family.

This series applies on top of "xhci-dwc3: Couple of fixes for USB3 support"

limitation:
- only Host mode is supported. The Device mode can be added later.

Tested on:
- dra7 evm
- dra71 evm
- dra72 evm
- dra72 evm rev C
- dra76 evm
- AM572 evm

Changes in v3:
- in syscon_regmap_lookup_by_phandle(), use dev_dbg() instead of printf()
- added unit test for syscon_regmap_lookup_by_phandle()
- use the live tree API in the omap5 glue logic

Changes in v2:
- Add USB3 support to ti-pipe3-phy driver
- omap-usb2-phy: Implement power_on and power_off callbacks
- am57xx boards: when DM_USB is used, turn on the required USB clocks
- split dts changes in 2 commits: one for binding the children of
  ocp2scp@4a08, and one to disable USB1  on all DRA7 EVMs
- Instead of disabling USB1 port in dts files, use *-u-boot.dtsi files
- Enable DM_USB in am57xx_evm_defconfig. USB3 (super speed) is supported.

Jean-Jacques Hiblot (8):
  syscon: dm: Add a new method to get a regmap from DTS
  usb: omap5: Add glue logic to support DM for USB host
  phy: Add a new driver for OMAP's USB2 PHYs
  board: ti: dra7xx-evm: turn on USB clocks in late init stage
  dts: dra7x: make ocp2scp@4a08 compatible with simple-bus
  dts: dra7x: Disable USB1 on all evms
  configs: enable DM_USB for all the platforms of the DRA7 family
  configs: am57xx_evm: Enable DM_USB and dependencies

Vignesh R (2):
  phy: ti-pip3-phy: Add support for USB3 PHY
  board; ti: am57xx: turn on USB clocks

 arch/arm/dts/dra7-evm-u-boot.dtsi   |   8 ++
 arch/arm/dts/dra71-evm-u-boot.dtsi  |   9 ++
 arch/arm/dts/dra72-evm-revc-u-boot.dtsi |   8 ++
 arch/arm/dts/dra72-evm-u-boot.dtsi  |  23 
 arch/arm/dts/dra76-evm-u-boot.dtsi  |   9 ++
 arch/arm/dts/omap5-u-boot.dtsi  |   4 +
 arch/sandbox/dts/test.dts   |   6 +-
 board/ti/am57xx/board.c |  19 +++
 board/ti/dra7xx/evm.c   |  19 +++
 configs/am57xx_evm_defconfig|   5 +
 configs/dra7xx_evm_defconfig|   2 +
 configs/dra7xx_hs_evm_defconfig |   2 +
 drivers/core/syscon-uclass.c|  23 
 drivers/phy/Kconfig |   8 ++
 drivers/phy/Makefile|   1 +
 drivers/phy/omap-usb2-phy.c | 198 
 drivers/phy/ti-pipe3-phy.c  |  30 +++--
 drivers/usb/host/Kconfig|  10 ++
 drivers/usb/host/Makefile   |   1 +
 drivers/usb/host/dwc3-omap-glue.c   |  60 ++
 include/syscon.h|  13 +++
 test/dm/syscon.c|  29 +
 22 files changed, 478 insertions(+), 9 deletions(-)
 create mode 100644 arch/arm/dts/dra72-evm-u-boot.dtsi
 create mode 100644 drivers/phy/omap-usb2-phy.c
 create mode 100644 drivers/usb/host/dwc3-omap-glue.c

-- 
2.7.4

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[U-Boot] [PATCH] vxworks: fixed cpu enable using PSCI on armv8

[Vasyl Vavrychuk]

Without armv8_setup_psci register VBAR_EL3 is not set up properly which
makes SMC calls jump to invalid location.

smp_kick_all_cpus is required to make slave cpus leave gic_wait_for_interrupt.
Without this they will never pursue booting process.

This implementation is very similiar to what is done in boot_jump_linux
in arch/arm/lib/bootm.c file.

Signed-off-by: Vasyl Vavrychuk 
---
 cmd/elf.c | 5 +
 1 file changed, 5 insertions(+)

diff --git a/cmd/elf.c b/cmd/elf.c
index 5745a389da..db690fc619 100644
--- a/cmd/elf.c
+++ b/cmd/elf.c
@@ -372,6 +372,11 @@ int do_bootvx(cmd_tbl_t *cmdtp, int flag, int argc, char * 
const argv[])
printf("## Starting vxWorks at 0x%08lx ...\n", addr);
 
dcache_disable();
+#if defined(CONFIG_ARM64) && defined(CONFIG_ARMV8_PSCI)
+   armv8_setup_psci();
+   smp_kick_all_cpus();
+#endif
+
 #ifdef CONFIG_X86
/* VxWorks on x86 uses stack to pass parameters */
((asmlinkage void (*)(int))addr)(0);
-- 
2.11.0

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Re: [U-Boot] [PATCH] cmd: nvedit: Add filtering during env import

[Quentin Schulz]

Hi Alex,

On Tue, Mar 27, 2018 at 08:43:26AM +, Alex Kiernan wrote:
> When importing variables allow size to be elided using '-' and then
> support a list of variables which restricts what will be picked during
> the import.
> 
> Signed-off-by: Alex Kiernan 

I'm pretty sure it's the same goal as this patch[1] I suggested.
Could you answer in the thread telling you need it as well so that we
could get it merged or at least reviewed?

Thanks,
Quentin

[1] http://patchwork.ozlabs.org/patch/855542/

> ---
> 
>  cmd/nvedit.c | 26 +++---
>  1 file changed, 19 insertions(+), 7 deletions(-)
> 
> diff --git a/cmd/nvedit.c b/cmd/nvedit.c
> index 4cb25b8..486bb24 100644
> --- a/cmd/nvedit.c
> +++ b/cmd/nvedit.c
> @@ -972,7 +972,7 @@ sep_err:
>  
>  #ifdef CONFIG_CMD_IMPORTENV
>  /*
> - * env import [-d] [-t [-r] | -b | -c] addr [size]
> + * env import [-d] [-t [-r] | -b | -c] addr [size] [var ...]
>   *   -d: delete existing environment before importing;
>   *   otherwise overwrite / append to existing definitions
>   *   -t: assume text format; either "size" must be given or the
> @@ -985,7 +985,10 @@ sep_err:
>   *   -c: assume checksum protected environment format
>   *   addr:   memory address to read from
>   *   size:   length of input data; if missing, proper '\0'
> - *   termination is mandatory
> + *   termination is mandatory. If not required and passing
> + *   variables to import use '-'
> + *   var...: List of variable names that get imported. Without arguments,
> + *   all variables are imported
>   */
>  static int do_env_import(cmd_tbl_t *cmdtp, int flag,
>int argc, char * const argv[])
> @@ -1043,11 +1046,20 @@ static int do_env_import(cmd_tbl_t *cmdtp, int flag,
>   crlf_is_lf = 0;
>  
>   addr = simple_strtoul(argv[0], NULL, 16);
> + --argc;
> + ++argv;
>   ptr = map_sysmem(addr, 0);
>  
> - if (argc == 2) {
> - size = simple_strtoul(argv[1], NULL, 16);
> - } else if (argc == 1 && chk) {
> + if (argc >= 1 && !strcmp(argv[0], "-")) {
> + --argc;
> + ++argv;
> + }
> +
> + if (argc >= 1) {
> + size = simple_strtoul(argv[0], NULL, 16);
> + --argc;
> + ++argv;
> + } else if (argc == 0 && chk) {
>   puts("## Error: external checksum format must pass size\n");
>   return CMD_RET_FAILURE;
>   } else {
> @@ -1084,7 +1096,7 @@ static int do_env_import(cmd_tbl_t *cmdtp, int flag,
>   }
>  
>   if (himport_r(_htab, ptr, size, sep, del ? 0 : H_NOCLEAR,
> - crlf_is_lf, 0, NULL) == 0) {
> + crlf_is_lf, argc, argc ? argv : NULL) == 0) {
>   pr_err("Environment import failed: errno = %d\n", errno);
>   return 1;
>   }
> @@ -1213,7 +1225,7 @@ static char env_help_text[] =
>  #endif
>  #endif
>  #if defined(CONFIG_CMD_IMPORTENV)
> - "env import [-d] [-t [-r] | -b | -c] addr [size] - import environment\n"
> + "env import [-d] [-t [-r] | -b | -c] addr [size] [var ...] - import 
> environment\n"
>  #endif
>   "env print [-a | name ...] - print environment\n"
>  #if defined(CONFIG_CMD_RUN)
> -- 
> 2.7.4
> 
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[U-Boot] [PATCH 00/36] rockchip: clean up board file for rockchip SoCs

[Kever Yang]

This patch set is to clean code for board related file, after this
patch set, all the Rockchip SoCs will share the same tpl/spl/board
file and very similar boot flow.

tpl.c: target for init DDR sdram, only internal sram available,
   prefer tpl to be as simple as possible and then back to backrom;
spl.c: target for load U-Boot and Trust(option) image and boot into
   next stage, init DDR sdram if no tpl exist;
board.c: use for U-Boot proper for all Rockchip SoCs.

We prefer to reduce boot flow option like RETURN_TO_BROM in SPL/TPL,
and will enable trust(ATF or OPTEE) support for all SoCs with TrustZone,
will share scripts for link and firmware package.

Only rk3399 is using spl+Trust/U-Boot and all other SoCs should go to
tpl+spl_Trust/U-Boot mode now.



Kever Yang (36):
  rockchip: rk3288: move configure_l2ctlr back to rk3288
  rockchip: add common MACRO to enable sys arch timer
  rockchip: enable SYS_NS16550 for all SoCs by default
  rockchip: defconfig: remove CONFIG_SYS_NS16550
  rockchip: add STIMER_BASE for all SoCs
  rockchip: add IRAM_START_ADDR for all SoCs
  rockchip: rk3328: add BOOT_MODE_REG for rk3328
  rockchip: rk322x: remove use rockchip timer as sys timer
  rockchip: rk322x: sdram: use common udelay instead of rockchip_udelay
  rockchip: rk322x: prepare to use common board file
  rockchip: defconfig enable sysreset for rk3229 spl
  rockchip: rk3036: sdram: use udelay instead of rockchip_udelay
  rockchip: rk3036: remove sys timer
  rockchip: rk3036: prepare to use commong board file
  rockchip: declare sdram_init() in common header
  rockchip: sdram-common: add api to pass dram info to trust os
  rockchip: sdram_common: add common dram_init_banksize
  rockchip: rk3188: remove rockchip timer as sys timer
  rockchip: rk3188: prepare to use common board file
  rockchip: rk3128: remove rockchip timer as systimer
  rockchip: rk3128: prepare use common board file
  rockchip: dts: rk3288: update spl-boot-order
  rockchip: rk3288: remove rockchip timer for sys timer
  armv8: add timer_get_boot_us() for generic timer
  rockchip: rk3288: prepare to use common board file
  rockchip: rk1108: remove rockchip timer for sys timer
  rockchip: rv1108: prepare to use common board file
  rockchip: rk3328: prepare to use common board file
  rockchip: rk3368: prepare to use common board file
  rockchip: lion-rk3368: remove rockchip timer
  rockchip: rk3399: prepare to use common board file
  rockchip: remove rk_timer
  rockchip: dts: rk3399-firefly: enable uart2 in spl
  rockchip: spl-boot-order: do not enable with OF_PLATDATA
  rockchip: declear boot_devices in bootrom.h
  rockchip: add common board file for rockchip platform

 arch/arm/Kconfig   |   1 +
 arch/arm/cpu/armv8/generic_timer.c |   6 +
 arch/arm/dts/rk3288-phycore-rdk.dts|   6 +-
 arch/arm/dts/rk3288-veyron.dtsi|   6 +-
 arch/arm/dts/rk3399-firefly.dts|   1 +
 arch/arm/include/asm/arch-rockchip/bootrom.h   |   2 +
 arch/arm/include/asm/arch-rockchip/sdram_common.h  |   4 +
 arch/arm/include/asm/arch-rockchip/sys_proto.h |  25 +-
 arch/arm/mach-rockchip/Kconfig |  38 ++-
 arch/arm/mach-rockchip/Makefile|  23 +-
 arch/arm/mach-rockchip/{rk3128-board.c => board.c} |  93 +++---
 arch/arm/mach-rockchip/rk3036-board.c  | 104 ---
 arch/arm/mach-rockchip/rk3036/Makefile |   2 +-
 .../{rk3036-board-spl.c => rk3036/rk3036.c}|  41 +--
 arch/arm/mach-rockchip/rk3036/sdram_rk3036.c   |  33 +-
 arch/arm/mach-rockchip/rk3188-board-spl.c  | 226 --
 arch/arm/mach-rockchip/rk3188-board.c  |  82 -
 arch/arm/mach-rockchip/rk3188/Makefile |   1 +
 arch/arm/mach-rockchip/rk3188/rk3188.c |  23 ++
 arch/arm/mach-rockchip/rk322x-board.c  | 155 --
 arch/arm/mach-rockchip/rk322x/Makefile |   2 +-
 .../{rk322x-board-spl.c => rk322x/rk322x.c}|  86 ++
 arch/arm/mach-rockchip/rk3288-board-spl.c  | 304 --
 arch/arm/mach-rockchip/rk3288-board-tpl.c  |  84 -
 arch/arm/mach-rockchip/rk3288-board.c  | 338 -
 arch/arm/mach-rockchip/rk3288/rk3288.c | 328 +++-
 arch/arm/mach-rockchip/rk3328/rk3328.c |  59 +++-
 arch/arm/mach-rockchip/rk3368-board-spl.c  |  73 -
 arch/arm/mach-rockchip/rk3368-board-tpl.c  | 157 --
 arch/arm/mach-rockchip/rk3368/rk3368.c | 116 ++-
 arch/arm/mach-rockchip/rk3399-board-spl.c  | 179 ---
 arch/arm/mach-rockchip/rk3399-board.c  |  14 -
 arch/arm/mach-rockchip/rk3399/rk3399.c |  86 +-
 arch/arm/mach-rockchip/rk_timer.c  |  48 ---
 arch/arm/mach-rockchip/rv1108/rv1108.c |   8 -
 arch/arm/mach-rockchip/sdram_common.c  |  84 

[U-Boot] How to access non Ethernet PHY from U-boot

[Greg]

Hi,
I have a CFP module which is interfaced on the MDIO bus of NXP MPC8308
controller. I want to access the CFP module registers from u-boot using
'mii' command, as of now the 'mii info' is not listing this device which
has address '6' in the MDIO bus.

In the case of Ethernet PHY I would go to drivers/net/tsec.c and add the
structure info in 'struct phy_info *phy_info[]' for the probe function to
detect it.

A CFP module follows MDIO  interface definition in IEEE 802.3 Clause 45,
http://www.cfp-msa.org/Documents/CFP_MSA_MIS_V2p2r06a.pdf

Any help is appreciated.
Greg
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[U-Boot] How to access non Ethernet PHY from U-boot

[Greg]

Hi,
I have a CFP module which is interfaced on the MDIO bus of NXP MPC8308
controller. I want to access the CFP module registers from u-boot using
'mii' command, as of now the 'mii info' is not listing this device which
has address '6' in the MDIO bus.

In the case of Ethernet PHY I would go to drivers/net/tsec.c and add the
structure info in 'struct phy_info *phy_info[]' for the probe function to
detect it.

A CFP module follows MDIO  interface definition in IEEE 802.3 Clause 45,
http://www.cfp-msa.org/Documents/CFP_MSA_MIS_V2p2r06a.pdf

Any help is appreciated.

Greg
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Re: [U-Boot] [PATCH] cmd: nvedit: Add filtering during env import

[Alex Kiernan]

On Tue, Mar 27, 2018 at 10:28 AM, Quentin Schulz
 wrote:
> Hi Alex,
>
> On Tue, Mar 27, 2018 at 08:43:26AM +, Alex Kiernan wrote:
>> When importing variables allow size to be elided using '-' and then
>> support a list of variables which restricts what will be picked during
>> the import.
>>
>> Signed-off-by: Alex Kiernan 
>
> I'm pretty sure it's the same goal as this patch[1] I suggested.

It is, maybe it was your message I was thinking of when I asked the
question the other day:

https://lists.denx.de/pipermail/u-boot/2018-March/323687.html

> Could you answer in the thread telling you need it as well so that we
> could get it merged or at least reviewed?
>

Assuming I've understood your patch correctly, I think I can replicate
your use case with this:

  env import ... ${whitelisted_vars}

I've two uses for this right now for this - with different white lists:

  # override defaults from uboot.env
  if fatload mmc ${mmcdev} ${loadaddr} uboot.env; then
  env import -c ${loadaddr} ${filesize} serial# ethaddr
  fi

  # source OSTree deployments
  if load ${devtype} ${bootpart} ${loadaddr} /boot/loader/uEnv.txt; then
  env import -t ${loadaddr} ${filesize} kernel_image
kernel_image2 bootargs bootargs2
  fi

-- 
Alex Kiernan
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[U-Boot] [PATCH 2/2] efi_loader: set the dhcp ack received flag

[Patrick Wildt]

The PXE object contains a flag that specifies whether or not a DHCP
ACK has been received.  This can be used by EFI Applications to find
out whether or not it is worth to read the DHCP information from our
object.

Signed-off-by: Patrick Wildt 
---
 lib/efi_loader/efi_net.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/lib/efi_loader/efi_net.c b/lib/efi_loader/efi_net.c
index 8c5d5b492c..0b9c7b9345 100644
--- a/lib/efi_loader/efi_net.c
+++ b/lib/efi_loader/efi_net.c
@@ -332,8 +332,10 @@ int efi_net_register(void)
netobj->net_mode.max_packet_size = PKTSIZE;
 
netobj->pxe.mode = >pxe_mode;
-   if (dhcp_ack)
+   if (dhcp_ack) {
netobj->pxe_mode.dhcp_ack = *dhcp_ack;
+   netobj->pxe_mode.dhcp_ack_received = 1;
+   }
 
/*
 * Create WaitForPacket event.
-- 
2.14.3 (Apple Git-98)

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[U-Boot] [PATCH 1/2] efi_loader: complete efi_pxe_mode struct definition

[Patrick Wildt]

The efi_pxe_mode struct which represents the PXE_BASE_CODE_PROTOCOL
Replace the placeholder paddings in the efi_pxe_mode struct with the
actual fields as defined in UEFI's PXE Base Code Protocol.  Since
our efi_ip_address is a simple char array set a specific alignment
to the efi_ip_address fields, as expected by the UEFI spec.

Signed-off-by: Patrick Wildt 
---
 include/efi_api.h | 25 +++--
 1 file changed, 23 insertions(+), 2 deletions(-)

diff --git a/include/efi_api.h b/include/efi_api.h
index 3ba650e57e..06789acdd1 100644
--- a/include/efi_api.h
+++ b/include/efi_api.h
@@ -662,7 +662,7 @@ struct efi_mac_address {
 
 struct efi_ip_address {
u8 ip_addr[16];
-};
+} __attribute__((aligned(4)));
 
 enum efi_simple_network_state {
EFI_NETWORK_STOPPED,
@@ -756,7 +756,28 @@ struct efi_pxe_packet {
 
 struct efi_pxe_mode
 {
-   u8 unused[52];
+   u8 started;
+   u8 ipv6_available;
+   u8 ipv6_supported;
+   u8 using_ipv6;
+   u8 bis_supported;
+   u8 bis_detected;
+   u8 auto_arp;
+   u8 send_guid;
+   u8 dhcp_discover_valid;
+   u8 dhcp_ack_received;
+   u8 proxy_offer_received;
+   u8 pxe_discovervalid;
+   u8 pxe_reply_received;
+   u8 pxe_bis_reply_received;
+   u8 icmp_error_received;
+   u8 tftp_error_received;
+   u8 make_callbacks;
+   u8 ttl;
+   u8 tos;
+   u8 pad;
+   struct efi_ip_address station_ip;
+   struct efi_ip_address subnet_mask;
struct efi_pxe_packet dhcp_discover;
struct efi_pxe_packet dhcp_ack;
struct efi_pxe_packet proxy_offer;
-- 
2.14.3 (Apple Git-98)

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[U-Boot] FEC and EFI Simple Network

[Patrick Wildt]

Hi,

I have been debugging network issues when running an EFI Application
that uses the EFI Simple Network protocol on an i.MX6 machine (FEC).

The symptom is that u-boot's (FEC) internal RX ring index is reset to 0,
while the controller is still at idx 3 (or something else).  This is
caused by the following circumstances:

The Simple Network protocol offers methods like Start(), Stop(),
Initialize(), Shutdown(), Reset().  Also the protocol has a state.  The
states are Stopped, Started, Initialized.  The transition is as follows:

Stopped ---Start()---> Started ---Initialize()--> Initialized

Start() does some initialization, Initialize() allocates the TX/RX
descriptors and actually kicks off the network engine.

So far, only Initialize() is implemented in our u-boot interface, and it
calls eth_init() which in the end calls fec_init().  Our network state
is _always_ Started.  This means that EFI Applications see that that the
state is Started and then call Initialize() to start the actual network
traffic.  There is no call to Stop()/Shutdown()/Reset() as it's supposed
to be in a sane state.

In my case the FEC is already initialized since I booted using network
and the RX desc index is already non-zero.  Now the EFI Application sees
that the state is Started, calls Initialize() which makes u-boot call
eth_init() which then calls fec_init().

fec_init() does not reset the controller so that the controller-internal
RX desc index is not reset to zero.  fec_init() calls fec_open() which
then resets the driver-internal RX desc index to zero.  Now they are out
of sync, boom.

This means that fec_init() without a previous fec_halt() breaks the
whole network if it was already running.  The Designware driver as used
by some sunxi platforms does a reset of the controller in the init
function.  Maybe calling fec_halt() at the start of fec_init() could be
a possible solution?

Patrick

diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
index ff7ad91116..ba8bd9920d 100644
--- a/drivers/net/fec_mxc.c
+++ b/drivers/net/fec_mxc.c
@@ -522,6 +522,12 @@ static int fec_open(struct eth_device *edev)
return 0;
 }
 
+#ifdef CONFIG_DM_ETH
+static void fecmxc_halt(struct udevice *dev);
+#else
+static void fec_halt(struct eth_device *dev);
+#endif
+
 #ifdef CONFIG_DM_ETH
 static int fecmxc_init(struct udevice *dev)
 #else
@@ -537,6 +543,15 @@ static int fec_init(struct eth_device *dev, bd_t *bd)
u8 *i;
ulong addr;
 
+#ifdef CONFIG_DM_ETH
+   fecmxc_halt(dev);
+#else
+   fec_halt(dev);
+#endif
+
+   writel(~FEC_TCNTRL_GTS & readl(>eth->x_cntrl),
+  >eth->x_cntrl);
+
/* Initialize MAC address */
 #ifdef CONFIG_DM_ETH
fecmxc_set_hwaddr(dev);
@@ -825,19 +840,12 @@ static int fec_recv(struct eth_device *dev)
}
if (ievent & FEC_IEVENT_HBERR) {
/* Heartbeat error */
-   writel(0x0001 | readl(>eth->x_cntrl),
+   writel(FEC_TCNTRL_GTS | readl(>eth->x_cntrl),
   >eth->x_cntrl);
}
if (ievent & FEC_IEVENT_GRA) {
/* Graceful stop complete */
-   if (readl(>eth->x_cntrl) & 0x0001) {
-#ifdef CONFIG_DM_ETH
-   fecmxc_halt(dev);
-#else
-   fec_halt(dev);
-#endif
-   writel(~0x0001 & readl(>eth->x_cntrl),
-  >eth->x_cntrl);
+   if (readl(>eth->x_cntrl) & FEC_TCNTRL_GTS) {
 #ifdef CONFIG_DM_ETH
fecmxc_init(dev);
 #else
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Re: [U-Boot] [PATCH 22/36] rockchip: dts: rk3288: update spl-boot-order

[Peter Robinson]

On Tue, Mar 27, 2018 at 10:29 AM, Kever Yang  wrote:
> Use "uboot,spl-boot-orde" instead of "uboot,boot0".

I think these should be in *-u-boot.dtsi files, that enables easy sync
between the linux kernel dts files and u-boot like done on a number of
other configs, a couple of the rk3368 devices seem to already use this
as does devices like AllWinner

> Signed-off-by: Kever Yang 
> ---
>
>  arch/arm/dts/rk3288-phycore-rdk.dts | 6 +-
>  arch/arm/dts/rk3288-veyron.dtsi | 6 +-
>  2 files changed, 2 insertions(+), 10 deletions(-)
>
> diff --git a/arch/arm/dts/rk3288-phycore-rdk.dts 
> b/arch/arm/dts/rk3288-phycore-rdk.dts
> index f2bb7b5..3bf8efb 100644
> --- a/arch/arm/dts/rk3288-phycore-rdk.dts
> +++ b/arch/arm/dts/rk3288-phycore-rdk.dts
> @@ -53,11 +53,7 @@
>
> chosen {
> stdout-path = 
> -   };
> -
> -   config {
> -   u-boot,dm-pre-reloc;
> -   u-boot,boot0 = 
> +   u-boot,spl-boot-order = 
> };
>
> user_buttons: user-buttons {
> diff --git a/arch/arm/dts/rk3288-veyron.dtsi b/arch/arm/dts/rk3288-veyron.dtsi
> index a314058..77b9bf8 100644
> --- a/arch/arm/dts/rk3288-veyron.dtsi
> +++ b/arch/arm/dts/rk3288-veyron.dtsi
> @@ -17,11 +17,7 @@
>
> chosen {
> stdout-path = 
> -   };
> -
> -   config {
> -   u-boot,dm-pre-reloc;
> -   u-boot,boot0 = _flash;
> +   u-boot,spl-boot-order = _flash;
> };
>
> firmware {
> --
> 1.9.1
>
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Re: [U-Boot] [PATCH 33/36] rockchip: dts: rk3399-firefly: enable uart2 in spl

[Peter Robinson]

On Tue, Mar 27, 2018 at 10:29 AM, Kever Yang  wrote:
> pre-loader console in SPL needs UART.
>
> Signed-off-by: Kever Yang 
> ---
>
>  arch/arm/dts/rk3399-firefly.dts | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/arch/arm/dts/rk3399-firefly.dts b/arch/arm/dts/rk3399-firefly.dts
> index f134c00..a007fa1 100644
> --- a/arch/arm/dts/rk3399-firefly.dts
> +++ b/arch/arm/dts/rk3399-firefly.dts
> @@ -648,6 +648,7 @@
>  };
>
>   {
> +   u-boot,dm-pre-reloc;

if this is u-boot specific shouldn't it be in a rk3399-firefly-u-boot.dtsi ?

> status = "okay";
>  };
>
> --
> 1.9.1
>
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[U-Boot] [PATCH v2] power: pwm regulator: support live tree

[Andy Yan]

Use live tree compatible api for pwm regulator.

Signed-off-by: Andy Yan 

---

Changes in v2:
- remove unused head files

 drivers/power/regulator/pwm_regulator.c | 15 ---
 1 file changed, 4 insertions(+), 11 deletions(-)

diff --git a/drivers/power/regulator/pwm_regulator.c 
b/drivers/power/regulator/pwm_regulator.c
index b63f941..29bceb5 100644
--- a/drivers/power/regulator/pwm_regulator.c
+++ b/drivers/power/regulator/pwm_regulator.c
@@ -13,9 +13,6 @@
 #include 
 #include 
 #include 
-#include 
-#include 
-#include 
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -94,13 +91,10 @@ static int pwm_regulator_set_voltage(struct udevice *dev, 
int uvolt)
 static int pwm_regulator_ofdata_to_platdata(struct udevice *dev)
 {
struct pwm_regulator_info *priv = dev_get_priv(dev);
-   struct fdtdec_phandle_args args;
-   const void *blob = gd->fdt_blob;
-   int node = dev_of_offset(dev);
+   struct ofnode_phandle_args args;
int ret;
 
-   ret = fdtdec_parse_phandle_with_args(blob, node, "pwms", "#pwm-cells",
-0, 0, );
+   ret = dev_read_phandle_with_args(dev, "pwms", "#pwm-cells", 0, 0, 
);
if (ret) {
debug("%s: Cannot get PWM phandle: ret=%d\n", __func__, ret);
return ret;
@@ -109,14 +103,13 @@ static int pwm_regulator_ofdata_to_platdata(struct 
udevice *dev)
priv->period_ns = args.args[1];
priv->polarity = args.args[2];
 
-   priv->init_voltage = fdtdec_get_int(blob, node,
-   "regulator-init-microvolt", -1);
+   priv->init_voltage = dev_read_u32_default(dev, 
"regulator-init-microvolt", -1);
if (priv->init_voltage < 0) {
printf("Cannot find regulator pwm init_voltage\n");
return -EINVAL;
}
 
-   ret = uclass_get_device_by_of_offset(UCLASS_PWM, args.node, >pwm);
+   ret = uclass_get_device_by_ofnode(UCLASS_PWM, args.node, >pwm);
if (ret) {
debug("%s: Cannot get PWM: ret=%d\n", __func__, ret);
return ret;
-- 
2.7.4


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Re: [U-Boot] [PATCH 26/36] rockchip: rk1108: remove rockchip timer for sys timer

[Andy Yan]

hi Kever:

    s/rk1108/rv1108


On 2018年03月27日 17:29, Kever Yang wrote:

We use ARM arch timer instead.

Signed-off-by: Kever Yang 
---

  include/configs/rv1108_common.h | 5 -
  1 file changed, 5 deletions(-)

diff --git a/include/configs/rv1108_common.h b/include/configs/rv1108_common.h
index cd204e9..7a9ec7b 100644
--- a/include/configs/rv1108_common.h
+++ b/include/configs/rv1108_common.h
@@ -13,11 +13,6 @@
  #define CONFIG_SYS_CBSIZE 1024
  #define CONFIG_SKIP_LOWLEVEL_INIT
  
-#define CONFIG_SYS_TIMER_RATE		(24 * 1000 * 1000)

-/* TIMER1,initialized by ddr initialize code */
-#define CONFIG_SYS_TIMER_BASE  0x10350020
-#define CONFIG_SYS_TIMER_COUNTER   (CONFIG_SYS_TIMER_BASE + 8)
-
  #define CONFIG_SYS_SDRAM_BASE 0x6000
  #define CONFIG_NR_DRAM_BANKS  1
  #define CONFIG_SYS_INIT_SP_ADDR   (CONFIG_SYS_TEXT_BASE + 
0x10)



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Re: [U-Boot] [PATCH] rockchip: clk: rk3188: update dpll settings to make EMAC work

[Kever Yang]

Hi Philipp,

    Sorry for reply so late.
On 02/26/2018 07:28 PM, Dr. Philipp Tomsich wrote:
> Kever,
>
> please review.
>
> Thanks,
> Philipp.
>
>> On 26 Feb 2018, at 12:27, Alexander Kochetkov  wrote:
>>
>> The patch set dpll settings for 300MHz to values used by binary
>> blob[1]. With new values dpll still generate 300MHz clock, but
>> EMAC work. Probably with new values dpll generate more stable clock.
>>
>> dpll on rk3188 provide clocks to DDR and EMAC. With current
>> dpll settings EMAC doesn't work on radxa rock. EMAC sends packets
>> to network, but it doesn't receive anything. ifconfig shows a lot
>> of framing errors.
>>
>> [1] https://github.com/linux-rockchip/u-boot-rockchip/blob/u-boot-rk3288/
>>tools/rk_tools/3188_LPDDR2_300MHz_DDR3_300MHz_20130830.bin
>>
>> Signed-off-by: Alexander Kochetkov 
>> ---
>> drivers/clk/rockchip/clk_rk3188.c |2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/drivers/clk/rockchip/clk_rk3188.c 
>> b/drivers/clk/rockchip/clk_rk3188.c
>> index 6451c95..f674e60 100644
>> --- a/drivers/clk/rockchip/clk_rk3188.c
>> +++ b/drivers/clk/rockchip/clk_rk3188.c
>> @@ -123,7 +123,7 @@ static int rkclk_configure_ddr(struct rk3188_cru *cru, 
>> struct rk3188_grf *grf,
>> unsigned int hz, bool has_bwadj)
>> {
>>  static const struct pll_div dpll_cfg[] = {
>> -{.nf = 25, .nr = 2, .no = 1},
>> +{.nf = 75, .nr = 1, .no = 6},

Rockchip always prefer to use nr=1 even if we can only get a frequency
close to target frequency,
because this setting can get smaller jitter. Some of IP like jitter may
very sensitive to this setting.

Reviewed-by: Kever Yang 

Thanks,
- Kever
>>  {.nf = 400, .nr = 9, .no = 2},
>>  {.nf = 500, .nr = 9, .no = 2},
>>  {.nf = 100, .nr = 3, .no = 1},
>> -- 
>> 1.7.9.5
>>
>


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[U-Boot] [PATCH 26/36] rockchip: rk1108: remove rockchip timer for sys timer

[Kever Yang]

We use ARM arch timer instead.

Signed-off-by: Kever Yang 
---

 include/configs/rv1108_common.h | 5 -
 1 file changed, 5 deletions(-)

diff --git a/include/configs/rv1108_common.h b/include/configs/rv1108_common.h
index cd204e9..7a9ec7b 100644
--- a/include/configs/rv1108_common.h
+++ b/include/configs/rv1108_common.h
@@ -13,11 +13,6 @@
 #define CONFIG_SYS_CBSIZE  1024
 #define CONFIG_SKIP_LOWLEVEL_INIT
 
-#define CONFIG_SYS_TIMER_RATE  (24 * 1000 * 1000)
-/* TIMER1,initialized by ddr initialize code */
-#define CONFIG_SYS_TIMER_BASE  0x10350020
-#define CONFIG_SYS_TIMER_COUNTER   (CONFIG_SYS_TIMER_BASE + 8)
-
 #define CONFIG_SYS_SDRAM_BASE  0x6000
 #define CONFIG_NR_DRAM_BANKS   1
 #define CONFIG_SYS_INIT_SP_ADDR(CONFIG_SYS_TEXT_BASE + 
0x10)
-- 
1.9.1

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[U-Boot] [PATCH 25/36] rockchip: rk3288: prepare to use common board file

[Kever Yang]

Use common board file and move SoC spec setting into rk3288.c

Signed-off-by: Kever Yang 
---

 arch/arm/mach-rockchip/rk3288-board-spl.c  | 304 --
 arch/arm/mach-rockchip/rk3288-board-tpl.c  |  84 -
 arch/arm/mach-rockchip/rk3288-board.c  | 338 -
 arch/arm/mach-rockchip/rk3288/rk3288.c | 304 +-
 board/chipspark/popmetal_rk3288/popmetal-rk3288.c  |   9 +-
 board/mqmaker/miqi_rk3288/miqi-rk3288.c|   7 -
 board/phytec/phycore_rk3288/phycore-rk3288.c   |  45 ++-
 board/rockchip/evb_rk3288/evb-rk3288.c |   7 -
 .../rockchip/evb_rk3288_rk1608/evb-rk3288-rk1608.c |   8 +
 board/rockchip/fennec_rk3288/fennec-rk3288.c   |   7 -
 board/rockchip/tinker_rk3288/tinker-rk3288.c   |   2 +-
 11 files changed, 357 insertions(+), 758 deletions(-)
 delete mode 100644 arch/arm/mach-rockchip/rk3288-board-spl.c
 delete mode 100644 arch/arm/mach-rockchip/rk3288-board-tpl.c
 delete mode 100644 arch/arm/mach-rockchip/rk3288-board.c
 create mode 100644 board/rockchip/evb_rk3288_rk1608/evb-rk3288-rk1608.c

diff --git a/arch/arm/mach-rockchip/rk3288-board-spl.c 
b/arch/arm/mach-rockchip/rk3288-board-spl.c
deleted file mode 100644
index f3ea624..000
--- a/arch/arm/mach-rockchip/rk3288-board-spl.c
+++ /dev/null
@@ -1,304 +0,0 @@
-/*
- * (C) Copyright 2015 Google, Inc
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-
-DECLARE_GLOBAL_DATA_PTR;
-
-u32 spl_boot_device(void)
-{
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
-   const void *blob = gd->fdt_blob;
-   struct udevice *dev;
-   const char *bootdev;
-   int node;
-   int ret;
-
-   bootdev = fdtdec_get_config_string(blob, "u-boot,boot0");
-   debug("Boot device %s\n", bootdev);
-   if (!bootdev)
-   goto fallback;
-
-   node = fdt_path_offset(blob, bootdev);
-   if (node < 0) {
-   debug("node=%d\n", node);
-   goto fallback;
-   }
-   ret = device_get_global_by_of_offset(node, );
-   if (ret) {
-   debug("device at node %s/%d not found: %d\n", bootdev, node,
- ret);
-   goto fallback;
-   }
-   debug("Found device %s\n", dev->name);
-   switch (device_get_uclass_id(dev)) {
-   case UCLASS_SPI_FLASH:
-   return BOOT_DEVICE_SPI;
-   case UCLASS_MMC:
-   return BOOT_DEVICE_MMC1;
-   default:
-   debug("Booting from device uclass '%s' not supported\n",
- dev_get_uclass_name(dev));
-   }
-
-fallback:
-#elif defined(CONFIG_TARGET_CHROMEBOOK_JERRY) || \
-   defined(CONFIG_TARGET_CHROMEBIT_MICKEY) || \
-   defined(CONFIG_TARGET_CHROMEBOOK_MINNIE)
-   return BOOT_DEVICE_SPI;
-#endif
-   return BOOT_DEVICE_MMC1;
-}
-
-#ifdef CONFIG_SPL_MMC_SUPPORT
-static int configure_emmc(struct udevice *pinctrl)
-{
-#if defined(CONFIG_TARGET_CHROMEBOOK_JERRY)
-
-   struct gpio_desc desc;
-   int ret;
-
-   pinctrl_request_noflags(pinctrl, PERIPH_ID_EMMC);
-
-   /*
-* TODO(s...@chromium.org): Pick this up from device tree or perhaps
-* use the EMMC_PWREN setting.
-*/
-   ret = dm_gpio_lookup_name("D9", );
-   if (ret) {
-   debug("gpio ret=%d\n", ret);
-   return ret;
-   }
-   ret = dm_gpio_request(, "emmc_pwren");
-   if (ret) {
-   debug("gpio_request ret=%d\n", ret);
-   return ret;
-   }
-   ret = dm_gpio_set_dir_flags(, GPIOD_IS_OUT);
-   if (ret) {
-   debug("gpio dir ret=%d\n", ret);
-   return ret;
-   }
-   ret = dm_gpio_set_value(, 1);
-   if (ret) {
-   debug("gpio value ret=%d\n", ret);
-   return ret;
-   }
-#endif
-   return 0;
-}
-#endif
-
-#if !defined(CONFIG_SPL_OF_PLATDATA)
-static int phycore_init(void)
-{
-   struct udevice *pmic;
-   int ret;
-
-   ret = uclass_first_device_err(UCLASS_PMIC, );
-   if (ret)
-   return ret;
-
-#if defined(CONFIG_SPL_POWER_SUPPORT)
-   /* Increase USB input current to 2A */
-   ret = rk818_spl_configure_usb_input_current(pmic, 2000);
-   if (ret)
-   return ret;
-
-   /* Close charger when USB lower then 3.26V */
-   ret = rk818_spl_configure_usb_chrg_shutdown(pmic, 326);
-   if (ret)
-   return ret;
-#endif
-
-   return 0;
-}
-#endif
-
-void board_init_f(ulong dummy)
-{
-   struct udevice *pinctrl;
-   struct udevice *dev;
-   int ret;
-
-   /* Example code showing how to enable the debug 

[U-Boot] [PATCH 35/36] rockchip: declear boot_devices in bootrom.h

[Kever Yang]

boot_devices may defined in soc file, and used in board file,
we need to delear it in header file.

Signed-off-by: Kever Yang 
---

 arch/arm/include/asm/arch-rockchip/bootrom.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/include/asm/arch-rockchip/bootrom.h 
b/arch/arm/include/asm/arch-rockchip/bootrom.h
index 103b799..ac2f370 100644
--- a/arch/arm/include/asm/arch-rockchip/bootrom.h
+++ b/arch/arm/include/asm/arch-rockchip/bootrom.h
@@ -53,6 +53,8 @@ enum {
BROM_LAST_BOOTSOURCE = BROM_BOOTSOURCE_USB
 };
 
+extern const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1];
+
 /**
  * Locations of the boot-device identifier in SRAM
  */
-- 
1.9.1

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[U-Boot] [PATCH 29/36] rockchip: rk3368: prepare to use common board file

[Kever Yang]

Use common board file and move SoC spec setting into rk3368.c

Signed-off-by: Kever Yang 
---

 arch/arm/mach-rockchip/rk3368-board-spl.c |  73 --
 arch/arm/mach-rockchip/rk3368-board-tpl.c | 157 --
 arch/arm/mach-rockchip/rk3368/rk3368.c| 116 ++--
 board/geekbuying/geekbox/geekbox.c|   5 -
 board/rockchip/evb_px5/evb-px5.c  |   5 -
 board/rockchip/sheep_rk3368/sheep_rk3368.c|   5 -
 board/theobroma-systems/lion_rk3368/lion_rk3368.c |   8 --
 7 files changed, 106 insertions(+), 263 deletions(-)
 delete mode 100644 arch/arm/mach-rockchip/rk3368-board-spl.c
 delete mode 100644 arch/arm/mach-rockchip/rk3368-board-tpl.c

diff --git a/arch/arm/mach-rockchip/rk3368-board-spl.c 
b/arch/arm/mach-rockchip/rk3368-board-spl.c
deleted file mode 100644
index 8055ae5..000
--- a/arch/arm/mach-rockchip/rk3368-board-spl.c
+++ /dev/null
@@ -1,73 +0,0 @@
-/*
- * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-
-DECLARE_GLOBAL_DATA_PTR;
-
-void board_debug_uart_init(void)
-{
-}
-
-void board_init_f(ulong dummy)
-{
-   struct udevice *pinctrl;
-   struct udevice *dev;
-   int ret;
-
-   ret = spl_early_init();
-   if (ret) {
-   debug("spl_early_init() failed: %d\n", ret);
-   hang();
-   }
-
-   /* Set up our preloader console */
-   ret = uclass_get_device(UCLASS_PINCTRL, 0, );
-   if (ret) {
-   pr_err("%s: pinctrl init failed: %d\n", __func__, ret);
-   hang();
-   }
-
-   ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_UART0);
-   if (ret) {
-   pr_err("%s: failed to set up console UART\n", __func__);
-   hang();
-   }
-
-   preloader_console_init();
-
-   ret = uclass_get_device(UCLASS_RAM, 0, );
-   if (ret) {
-   debug("DRAM init failed: %d\n", ret);
-   return;
-   }
-}
-
-u32 spl_boot_device(void)
-{
-   return BOOT_DEVICE_MMC1;
-}
-
-#ifdef CONFIG_SPL_LOAD_FIT
-int board_fit_config_name_match(const char *name)
-{
-   /* Just empty function now - can't decide what to choose */
-   debug("%s: %s\n", __func__, name);
-
-   return 0;
-}
-#endif
diff --git a/arch/arm/mach-rockchip/rk3368-board-tpl.c 
b/arch/arm/mach-rockchip/rk3368-board-tpl.c
deleted file mode 100644
index 60d5aea..000
--- a/arch/arm/mach-rockchip/rk3368-board-tpl.c
+++ /dev/null
@@ -1,157 +0,0 @@
-/*
- * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * The SPL (and also the full U-Boot stage on the RK3368) will run in
- * secure mode (i.e. EL3) and an ATF will eventually be booted before
- * starting up the operating system... so we can initialize the SGRF
- * here and rely on the ATF installing the final (secure) policy
- * later.
- */
-static inline uintptr_t sgrf_soc_con_addr(unsigned no)
-{
-   const uintptr_t SGRF_BASE =
-   (uintptr_t)syscon_get_first_range(ROCKCHIP_SYSCON_SGRF);
-
-   return SGRF_BASE + sizeof(u32) * no;
-}
-
-static inline uintptr_t sgrf_busdmac_addr(unsigned no)
-{
-   const uintptr_t SGRF_BASE =
-   (uintptr_t)syscon_get_first_range(ROCKCHIP_SYSCON_SGRF);
-   const uintptr_t SGRF_BUSDMAC_OFFSET = 0x100;
-   const uintptr_t SGRF_BUSDMAC_BASE = SGRF_BASE + SGRF_BUSDMAC_OFFSET;
-
-   return SGRF_BUSDMAC_BASE + sizeof(u32) * no;
-}
-
-static void sgrf_init(void)
-{
-   struct rk3368_cru * const cru =
-   (struct rk3368_cru * const)rockchip_get_cru();
-   const u16 SGRF_SOC_CON_SEC = GENMASK(15, 0);
-   const u16 SGRF_BUSDMAC_CON0_SEC = BIT(2);
-   const u16 SGRF_BUSDMAC_CON1_SEC = GENMASK(15, 12);
-
-   /* Set all configurable IP to 'non secure'-mode */
-   rk_setreg(sgrf_soc_con_addr(5), SGRF_SOC_CON_SEC);
-   rk_setreg(sgrf_soc_con_addr(6), SGRF_SOC_CON_SEC);
-   rk_setreg(sgrf_soc_con_addr(7), SGRF_SOC_CON_SEC);
-
-   /*
-* From rockchip-uboot/arch/arm/cpu/armv8/rk33xx/cpu.c
-* Original comment: "ddr space set no secure mode"
-*/
-   rk_clrreg(sgrf_soc_con_addr(8), SGRF_SOC_CON_SEC);
-   rk_clrreg(sgrf_soc_con_addr(9), SGRF_SOC_CON_SEC);
-   rk_clrreg(sgrf_soc_con_addr(10), SGRF_SOC_CON_SEC);
-
-   /* Set 'secure dma' to 'non secure'-mode */
-   rk_setreg(sgrf_busdmac_addr(0), SGRF_BUSDMAC_CON0_SEC);
-   rk_setreg(sgrf_busdmac_addr(1), SGRF_BUSDMAC_CON1_SEC);
-
-   dsb();  /* barrier */
-
-   

[U-Boot] [PATCH 10/36] rockchip: rk322x: prepare to use common board file

[Kever Yang]

Move soc spec setting into rk322x.c and remove rk322x-board/board-spl.c

Signed-off-by: Kever Yang 
---

 arch/arm/mach-rockchip/rk322x-board.c  | 155 -
 arch/arm/mach-rockchip/rk322x/Makefile |   2 +-
 .../{rk322x-board-spl.c => rk322x/rk322x.c}|  86 
 3 files changed, 29 insertions(+), 214 deletions(-)
 delete mode 100644 arch/arm/mach-rockchip/rk322x-board.c
 rename arch/arm/mach-rockchip/{rk322x-board-spl.c => rk322x/rk322x.c} (51%)

diff --git a/arch/arm/mach-rockchip/rk322x-board.c 
b/arch/arm/mach-rockchip/rk322x-board.c
deleted file mode 100644
index 8642a90..000
--- a/arch/arm/mach-rockchip/rk322x-board.c
+++ /dev/null
@@ -1,155 +0,0 @@
-/*
- * (C) Copyright 2017 Rockchip Electronics Co., Ltd.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-
-DECLARE_GLOBAL_DATA_PTR;
-
-__weak int rk_board_late_init(void)
-{
-   return 0;
-}
-
-int board_late_init(void)
-{
-   setup_boot_mode();
-
-   return rk_board_late_init();
-}
-
-int board_init(void)
-{
-#include 
-   /* Enable early UART2 channel 1 on the RK322x */
-#define GRF_BASE   0x1100
-   struct rk322x_grf * const grf = (void *)GRF_BASE;
-   enum {
-   GPIO1B2_SHIFT   = 4,
-   GPIO1B2_MASK= 3 << GPIO1B2_SHIFT,
-   GPIO1B2_GPIO= 0,
-   GPIO1B2_UART21_SIN,
-
-   GPIO1B1_SHIFT   = 2,
-   GPIO1B1_MASK= 3 << GPIO1B1_SHIFT,
-   GPIO1B1_GPIO= 0,
-   GPIO1B1_UART1_SOUT,
-   GPIO1B1_UART21_SOUT,
-   };
-   enum {
-   CON_IOMUX_UART2SEL_SHIFT= 8,
-   CON_IOMUX_UART2SEL_MASK = 1 << CON_IOMUX_UART2SEL_SHIFT,
-   CON_IOMUX_UART2SEL_2= 0,
-   CON_IOMUX_UART2SEL_21,
-   };
-
-   rk_clrsetreg(>gpio1b_iomux,
-GPIO1B1_MASK | GPIO1B2_MASK,
-GPIO1B2_UART21_SIN << GPIO1B2_SHIFT |
-GPIO1B1_UART21_SOUT << GPIO1B1_SHIFT);
-   /* Set channel C as UART2 input */
-   rk_clrsetreg(>con_iomux,
-CON_IOMUX_UART2SEL_MASK,
-CON_IOMUX_UART2SEL_21 << CON_IOMUX_UART2SEL_SHIFT);
-
-   /*
-   * The integrated macphy is enabled by default, disable it
-   * for saving power consuming.
-   */
-   rk_clrsetreg(>macphy_con[0],
-MACPHY_CFG_ENABLE_MASK,
-0 << MACPHY_CFG_ENABLE_SHIFT);
-
-   return 0;
-}
-
-int dram_init_banksize(void)
-{
-   gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
-   gd->bd->bi_dram[0].size = 0x840;
-   /* Reserve 0x20 for OPTEE */
-   gd->bd->bi_dram[1].start = CONFIG_SYS_SDRAM_BASE
-   + gd->bd->bi_dram[0].size + 0x20;
-   gd->bd->bi_dram[1].size = gd->bd->bi_dram[0].start
-   + gd->ram_size - gd->bd->bi_dram[1].start;
-
-   return 0;
-}
-
-#ifndef CONFIG_SYS_DCACHE_OFF
-void enable_caches(void)
-{
-   /* Enable D-cache. I-cache is already enabled in start.S */
-   dcache_enable();
-}
-#endif
-
-#if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG)
-#include 
-#include 
-
-static struct dwc2_plat_otg_data rk322x_otg_data = {
-   .rx_fifo_sz = 512,
-   .np_tx_fifo_sz  = 16,
-   .tx_fifo_sz = 128,
-};
-
-int board_usb_init(int index, enum usb_init_type init)
-{
-   int node;
-   const char *mode;
-   bool matched = false;
-   const void *blob = gd->fdt_blob;
-
-   /* find the usb_otg node */
-   node = fdt_node_offset_by_compatible(blob, -1,
-   "rockchip,rk3288-usb");
-
-   while (node > 0) {
-   mode = fdt_getprop(blob, node, "dr_mode", NULL);
-   if (mode && strcmp(mode, "otg") == 0) {
-   matched = true;
-   break;
-   }
-
-   node = fdt_node_offset_by_compatible(blob, node,
-   "rockchip,rk3288-usb");
-   }
-   if (!matched) {
-   debug("Not found usb_otg device\n");
-   return -ENODEV;
-   }
-   rk322x_otg_data.regs_otg = fdtdec_get_addr(blob, node, "reg");
-
-   return dwc2_udc_probe(_otg_data);
-}
-
-int board_usb_cleanup(int index, enum usb_init_type init)
-{
-   return 0;
-}
-#endif
-
-#if defined(CONFIG_USB_FUNCTION_FASTBOOT)
-int fb_set_reboot_flag(void)
-{
-   struct rk322x_grf *grf;
-
-   printf("Setting reboot to fastboot flag ...\n");
-   grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
-   /* Set boot mode to fastboot */
-   writel(BOOT_FASTBOOT, >os_reg[0]);
-
-   return 0;
-}
-#endif
diff --git 

[U-Boot] [PATCH 31/36] rockchip: rk3399: prepare to use common board file

[Kever Yang]

Use common board file and move SoC spec setting into rk3399.c

Signed-off-by: Kever Yang 
---

 arch/arm/mach-rockchip/rk3399-board-spl.c | 179 --
 arch/arm/mach-rockchip/rk3399-board.c |  14 --
 arch/arm/mach-rockchip/rk3399/rk3399.c|  86 +--
 board/rockchip/evb_rk3399/evb-rk3399.c|  56 ---
 board/theobroma-systems/puma_rk3399/puma-rk3399.c |  17 +-
 5 files changed, 103 insertions(+), 249 deletions(-)
 delete mode 100644 arch/arm/mach-rockchip/rk3399-board-spl.c
 delete mode 100644 arch/arm/mach-rockchip/rk3399-board.c

diff --git a/arch/arm/mach-rockchip/rk3399-board-spl.c 
b/arch/arm/mach-rockchip/rk3399-board-spl.c
deleted file mode 100644
index d35990e..000
--- a/arch/arm/mach-rockchip/rk3399-board-spl.c
+++ /dev/null
@@ -1,179 +0,0 @@
-/*
- * (C) Copyright 2016 Rockchip Electronics Co., Ltd
- * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-
-DECLARE_GLOBAL_DATA_PTR;
-
-void board_return_to_bootrom(void)
-{
-   back_to_bootrom(BROM_BOOT_NEXTSTAGE);
-}
-
-static const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
-   [BROM_BOOTSOURCE_EMMC] = "/sdhci@fe33",
-   [BROM_BOOTSOURCE_SPINOR] = "/spi@ff1d",
-   [BROM_BOOTSOURCE_SD] = "/dwmmc@fe32",
-};
-
-const char *board_spl_was_booted_from(void)
-{
-   u32  bootdevice_brom_id = readl(RK3399_BROM_BOOTSOURCE_ID_ADDR);
-   const char *bootdevice_ofpath = NULL;
-
-   if (bootdevice_brom_id < ARRAY_SIZE(boot_devices))
-   bootdevice_ofpath = boot_devices[bootdevice_brom_id];
-
-   if (bootdevice_ofpath)
-   debug("%s: brom_bootdevice_id %x maps to '%s'\n",
- __func__, bootdevice_brom_id, bootdevice_ofpath);
-   else
-   debug("%s: failed to resolve brom_bootdevice_id %x\n",
- __func__, bootdevice_brom_id);
-
-   return bootdevice_ofpath;
-}
-
-u32 spl_boot_device(void)
-{
-   u32 boot_device = BOOT_DEVICE_MMC1;
-
-   if (CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM))
-   return BOOT_DEVICE_BOOTROM;
-
-   return boot_device;
-}
-
-#define TIMER_CHN10_BASE   0xff8680a0
-#define TIMER_END_COUNT_L  0x00
-#define TIMER_END_COUNT_H  0x04
-#define TIMER_INIT_COUNT_L 0x10
-#define TIMER_INIT_COUNT_H 0x14
-#define TIMER_CONTROL_REG  0x1c
-
-#define TIMER_EN   0x1
-#defineTIMER_FMODE (0 << 1)
-#defineTIMER_RMODE (1 << 1)
-
-void secure_timer_init(void)
-{
-   writel(0x, TIMER_CHN10_BASE + TIMER_END_COUNT_L);
-   writel(0x, TIMER_CHN10_BASE + TIMER_END_COUNT_H);
-   writel(0, TIMER_CHN10_BASE + TIMER_INIT_COUNT_L);
-   writel(0, TIMER_CHN10_BASE + TIMER_INIT_COUNT_H);
-   writel(TIMER_EN | TIMER_FMODE, TIMER_CHN10_BASE + TIMER_CONTROL_REG);
-}
-
-void board_debug_uart_init(void)
-{
-#define GRF_BASE   0xff77
-   struct rk3399_grf_regs * const grf = (void *)GRF_BASE;
-
-#if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff18)
-   /* Enable early UART0 on the RK3399 */
-   rk_clrsetreg(>gpio2c_iomux,
-GRF_GPIO2C0_SEL_MASK,
-GRF_UART0BT_SIN << GRF_GPIO2C0_SEL_SHIFT);
-   rk_clrsetreg(>gpio2c_iomux,
-GRF_GPIO2C1_SEL_MASK,
-GRF_UART0BT_SOUT << GRF_GPIO2C1_SEL_SHIFT);
-#else
-   /* Enable early UART2 channel C on the RK3399 */
-   rk_clrsetreg(>gpio4c_iomux,
-GRF_GPIO4C3_SEL_MASK,
-GRF_UART2DGBC_SIN << GRF_GPIO4C3_SEL_SHIFT);
-   rk_clrsetreg(>gpio4c_iomux,
-GRF_GPIO4C4_SEL_MASK,
-GRF_UART2DBGC_SOUT << GRF_GPIO4C4_SEL_SHIFT);
-   /* Set channel C as UART2 input */
-   rk_clrsetreg(>soc_con7,
-GRF_UART_DBG_SEL_MASK,
-GRF_UART_DBG_SEL_C << GRF_UART_DBG_SEL_SHIFT);
-#endif
-}
-
-void board_init_f(ulong dummy)
-{
-   struct udevice *pinctrl;
-   struct udevice *dev;
-   struct rk3399_pmusgrf_regs *sgrf;
-   struct rk3399_grf_regs *grf;
-   int ret;
-
-#define EARLY_UART
-#ifdef EARLY_UART
-   /*
-* Debug UART can be used from here if required:
-*
-* debug_uart_init();
-* printch('a');
-* printhex8(0x1234);
-* printascii("string");
-*/
-   debug_uart_init();
-   printascii("U-Boot SPL board init");
-#endif
-
-   ret = spl_early_init();
-   if (ret) {
-   debug("spl_early_init() failed: %d\n", ret);
-   hang();
-   }
-
-   /*
-* Disable DDR and SRAM security regions.
-*
-* As we are entered from the BootROM, the 

[U-Boot] [PATCH 14/36] rockchip: rk3036: prepare to use commong board file

[Kever Yang]

Move some soc spec setting into rk3036.c

Signed-off-by: Kever Yang 
---

 arch/arm/mach-rockchip/rk3036-board.c  | 104 -
 arch/arm/mach-rockchip/rk3036/Makefile |   2 +-
 .../{rk3036-board-spl.c => rk3036/rk3036.c}|  41 ++--
 arch/arm/mach-rockchip/rk3036/sdram_rk3036.c   |  14 +++
 4 files changed, 24 insertions(+), 137 deletions(-)
 delete mode 100644 arch/arm/mach-rockchip/rk3036-board.c
 rename arch/arm/mach-rockchip/{rk3036-board-spl.c => rk3036/rk3036.c} (50%)

diff --git a/arch/arm/mach-rockchip/rk3036-board.c 
b/arch/arm/mach-rockchip/rk3036-board.c
deleted file mode 100644
index a5d2571..000
--- a/arch/arm/mach-rockchip/rk3036-board.c
+++ /dev/null
@@ -1,104 +0,0 @@
-/*
- * (C) Copyright 2015 Rockchip Electronics Co., Ltd
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-
-DECLARE_GLOBAL_DATA_PTR;
-
-__weak int rk_board_late_init(void)
-{
-   return 0;
-}
-
-int board_late_init(void)
-{
-   setup_boot_mode();
-
-   return rk_board_late_init();
-}
-
-int board_init(void)
-{
-   return 0;
-}
-
-#if !CONFIG_IS_ENABLED(RAM)
-/*
- * When CONFIG_RAM is enabled, the dram_init() function is implemented
- * in sdram_common.c.
- */
-int dram_init(void)
-{
-   gd->ram_size = sdram_size();
-
-   return 0;
-}
-#endif
-
-#ifndef CONFIG_SYS_DCACHE_OFF
-void enable_caches(void)
-{
-   /* Enable D-cache. I-cache is already enabled in start.S */
-   dcache_enable();
-}
-#endif
-
-#if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG)
-#include 
-#include 
-
-static struct dwc2_plat_otg_data rk3036_otg_data = {
-   .rx_fifo_sz = 512,
-   .np_tx_fifo_sz  = 16,
-   .tx_fifo_sz = 128,
-};
-
-int board_usb_init(int index, enum usb_init_type init)
-{
-   int node;
-   const char *mode;
-   bool matched = false;
-   const void *blob = gd->fdt_blob;
-
-   /* find the usb_otg node */
-   node = fdt_node_offset_by_compatible(blob, -1,
-   "rockchip,rk3288-usb");
-
-   while (node > 0) {
-   mode = fdt_getprop(blob, node, "dr_mode", NULL);
-   if (mode && strcmp(mode, "otg") == 0) {
-   matched = true;
-   break;
-   }
-
-   node = fdt_node_offset_by_compatible(blob, node,
-   "rockchip,rk3288-usb");
-   }
-   if (!matched) {
-   debug("Not found usb_otg device\n");
-   return -ENODEV;
-   }
-   rk3036_otg_data.regs_otg = fdtdec_get_addr(blob, node, "reg");
-
-   return dwc2_udc_probe(_otg_data);
-}
-
-int board_usb_cleanup(int index, enum usb_init_type init)
-{
-   return 0;
-}
-#endif
diff --git a/arch/arm/mach-rockchip/rk3036/Makefile 
b/arch/arm/mach-rockchip/rk3036/Makefile
index 20d28f7..8a144d1 100644
--- a/arch/arm/mach-rockchip/rk3036/Makefile
+++ b/arch/arm/mach-rockchip/rk3036/Makefile
@@ -4,7 +4,7 @@
 # SPDX-License-Identifier: GPL-2.0+
 #
 
-obj-y += clk_rk3036.o
+obj-y += rk3036.o clk_rk3036.o
 
 ifndef CONFIG_SPL_BUILD
 obj-y += syscon_rk3036.o
diff --git a/arch/arm/mach-rockchip/rk3036-board-spl.c 
b/arch/arm/mach-rockchip/rk3036/rk3036.c
similarity index 50%
rename from arch/arm/mach-rockchip/rk3036-board-spl.c
rename to arch/arm/mach-rockchip/rk3036/rk3036.c
index 550e3a1..39cc43b 100644
--- a/arch/arm/mach-rockchip/rk3036-board-spl.c
+++ b/arch/arm/mach-rockchip/rk3036/rk3036.c
@@ -1,28 +1,22 @@
 /*
- * (C) Copyright 2015 Rockchip Electronics Co., Ltd
+ * Copyright (c) 2017 Rockchip Electronics Co., Ltd
  *
  * SPDX-License-Identifier: GPL-2.0+
  */
-
-#include 
-#include 
 #include 
 #include 
-#include 
 #include 
-#include 
-#include 
-#include 
-
-DECLARE_GLOBAL_DATA_PTR;
-
+#include 
 #define GRF_BASE   0x20008000
 
-#define DEBUG_UART_BASE0x20068000
-
-void board_init_f(ulong dummy)
+#ifdef CONFIG_SPL_BUILD
+int arch_cpu_init(void)
+{
+   return 0;
+}
+#endif
+void board_debug_uart_init(void)
 {
-#ifdef EARLY_DEBUG
struct rk3036_grf * const grf = (void *)GRF_BASE;
/*
 * NOTE: sd card and debug uart use same iomux in rk3036,
@@ -34,22 +28,5 @@ void board_init_f(ulong dummy)
 GPIO1C2_MASK << GPIO1C2_SHIFT,
 GPIO1C3_UART2_SOUT << GPIO1C3_SHIFT |
 GPIO1C2_UART2_SIN << GPIO1C2_SHIFT);
-   debug_uart_init();
-#endif
-   rockchip_timer_init();
-   sdram_init();
-
-   /* return to maskrom */
-   back_to_bootrom(BROM_BOOT_NEXTSTAGE);
-}
 
-/* Place Holders */
-void board_init_r(gd_t *id, ulong dest_addr)
-{
-   /*
-* Function attribute is no-return
-* This Function never executes
-*/
-   while (1)
-   ;
 }
diff --git 

[U-Boot] [PATCH 27/36] rockchip: rv1108: prepare to use common board file

[Kever Yang]

Remove functions will present at common board file.

Signed-off-by: Kever Yang 
---

 arch/arm/mach-rockchip/rv1108/rv1108.c | 8 
 board/rockchip/evb_rv1108/evb_rv1108.c | 6 --
 2 files changed, 14 deletions(-)

diff --git a/arch/arm/mach-rockchip/rv1108/rv1108.c 
b/arch/arm/mach-rockchip/rv1108/rv1108.c
index 868cdd5..3b6b21d 100644
--- a/arch/arm/mach-rockchip/rv1108/rv1108.c
+++ b/arch/arm/mach-rockchip/rv1108/rv1108.c
@@ -5,11 +5,3 @@
  */
 
 #include 
-
-#ifndef CONFIG_SYS_DCACHE_OFF
-void enable_caches(void)
-{
-   /* Enable D-cache. I-cache is already enabled in start.S */
-   dcache_enable();
-}
-#endif
diff --git a/board/rockchip/evb_rv1108/evb_rv1108.c 
b/board/rockchip/evb_rv1108/evb_rv1108.c
index 54bd08b..0160f42 100644
--- a/board/rockchip/evb_rv1108/evb_rv1108.c
+++ b/board/rockchip/evb_rv1108/evb_rv1108.c
@@ -47,12 +47,6 @@ int mach_cpu_init(void)
return 0;
 }
 
-
-int board_init(void)
-{
-   return 0;
-}
-
 int dram_init(void)
 {
gd->ram_size = 0x800;
-- 
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[U-Boot] [PATCH 18/36] rockchip: rk3188: remove rockchip timer as sys timer

[Kever Yang]

We use ARM arch timer instead.

Signed-off-by: Kever Yang 
---

 include/configs/rk3188_common.h | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/include/configs/rk3188_common.h b/include/configs/rk3188_common.h
index 30c150e..7dddf11 100644
--- a/include/configs/rk3188_common.h
+++ b/include/configs/rk3188_common.h
@@ -17,9 +17,6 @@
 #define CONFIG_SYS_MALLOC_LEN  (32 << 20)
 #define CONFIG_SYS_CBSIZE  1024
 
-#define CONFIG_SYS_TIMER_RATE  (24 * 1000 * 1000)
-#define CONFIG_SYS_TIMER_BASE  0x2000e000 /* TIMER3 */
-#define CONFIG_SYS_TIMER_COUNTER   (CONFIG_SYS_TIMER_BASE + 8)
 #define CONFIG_SYS_TIMER_COUNTS_DOWN
 
 #ifdef CONFIG_SPL_ROCKCHIP_BACK_TO_BROM
-- 
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[U-Boot] [PATCH 16/36] rockchip: sdram-common: add api to pass dram info to trust os

[Kever Yang]

Trust OS decode this info like this:
https://github.com/ARM-software/arm-trusted-firmware/blob/master/plat/rockchip/common/drivers/parameter/ddr_parameter.c#L19
We have to set a available value, or else we get error info from
Trust OS like this:
"ERROR:   over or zero region, nr=3145987, max=10"

Signed-off-by: Kever Yang 
---

 arch/arm/include/asm/arch-rockchip/sdram_common.h |  4 
 arch/arm/mach-rockchip/sdram_common.c | 21 +
 2 files changed, 25 insertions(+)

diff --git a/arch/arm/include/asm/arch-rockchip/sdram_common.h 
b/arch/arm/include/asm/arch-rockchip/sdram_common.h
index fec8586..55c6b81 100644
--- a/arch/arm/include/asm/arch-rockchip/sdram_common.h
+++ b/arch/arm/include/asm/arch-rockchip/sdram_common.h
@@ -55,4 +55,8 @@ size_t rockchip_sdram_size(phys_addr_t reg);
 
 /* Called by U-Boot board_init_r for Rockchip SoCs */
 int dram_init(void);
+
+/* Write ddr param to a known place for trustos */
+int rockchip_setup_ddr_param(struct ram_info *info);
+
 #endif
diff --git a/arch/arm/mach-rockchip/sdram_common.c 
b/arch/arm/mach-rockchip/sdram_common.c
index 76dbdc8..3a71f09 100644
--- a/arch/arm/mach-rockchip/sdram_common.c
+++ b/arch/arm/mach-rockchip/sdram_common.c
@@ -12,6 +12,15 @@
 #include 
 
 DECLARE_GLOBAL_DATA_PTR;
+struct ddr_param {
+   u32 count;
+   u32 reserved;
+   u64 bank_addr;
+   u64 bank_size;
+};
+
+#define PARAM_DRAM_INFO_OFFSET 0x200
+
 size_t rockchip_sdram_size(phys_addr_t reg)
 {
u32 rank, col, bk, cs0_row, cs1_row, bw, row_3_4;
@@ -81,3 +90,15 @@ ulong board_get_usable_ram_top(ulong total_size)
 
return (gd->ram_top > top) ? top : gd->ram_top;
 }
+
+int rockchip_setup_ddr_param(struct ram_info *info)
+{
+   struct ddr_param *dinfo = (struct ddr_param *)CONFIG_SYS_SDRAM_BASE +
+   PARAM_DRAM_INFO_OFFSET;
+
+   dinfo->count = 1;
+   dinfo->bank_addr = info->base;
+   dinfo->bank_size = info->size;
+
+   return 0;
+}
-- 
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[U-Boot] [PATCH 22/36] rockchip: dts: rk3288: update spl-boot-order

[Kever Yang]

Use "uboot,spl-boot-orde" instead of "uboot,boot0".

Signed-off-by: Kever Yang 
---

 arch/arm/dts/rk3288-phycore-rdk.dts | 6 +-
 arch/arm/dts/rk3288-veyron.dtsi | 6 +-
 2 files changed, 2 insertions(+), 10 deletions(-)

diff --git a/arch/arm/dts/rk3288-phycore-rdk.dts 
b/arch/arm/dts/rk3288-phycore-rdk.dts
index f2bb7b5..3bf8efb 100644
--- a/arch/arm/dts/rk3288-phycore-rdk.dts
+++ b/arch/arm/dts/rk3288-phycore-rdk.dts
@@ -53,11 +53,7 @@
 
chosen {
stdout-path = 
-   };
-
-   config {
-   u-boot,dm-pre-reloc;
-   u-boot,boot0 = 
+   u-boot,spl-boot-order = 
};
 
user_buttons: user-buttons {
diff --git a/arch/arm/dts/rk3288-veyron.dtsi b/arch/arm/dts/rk3288-veyron.dtsi
index a314058..77b9bf8 100644
--- a/arch/arm/dts/rk3288-veyron.dtsi
+++ b/arch/arm/dts/rk3288-veyron.dtsi
@@ -17,11 +17,7 @@
 
chosen {
stdout-path = 
-   };
-
-   config {
-   u-boot,dm-pre-reloc;
-   u-boot,boot0 = _flash;
+   u-boot,spl-boot-order = _flash;
};
 
firmware {
-- 
1.9.1

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[U-Boot] [PATCH 24/36] armv8: add timer_get_boot_us() for generic timer

[Kever Yang]

We need timer_get_boot_us() for boot stage if we use generic timer only.

Signed-off-by: Kever Yang 
---

 arch/arm/cpu/armv8/generic_timer.c | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm/cpu/armv8/generic_timer.c 
b/arch/arm/cpu/armv8/generic_timer.c
index a2dda33..d96217e 100644
--- a/arch/arm/cpu/armv8/generic_timer.c
+++ b/arch/arm/cpu/armv8/generic_timer.c
@@ -7,6 +7,7 @@
 
 #include 
 #include 
+#include 
 #include 
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -52,6 +53,11 @@ uint64_t get_ticks(void)
return ticks;
 }
 
+ulong timer_get_boot_us(void)
+{
+   return lldiv(get_ticks(), CONFIG_SYS_HZ_CLOCK / (CONFIG_SYS_HZ * 1000));
+}
+
 unsigned long usec2ticks(unsigned long usec)
 {
ulong ticks;
-- 
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[U-Boot] [PATCH 32/36] rockchip: remove rk_timer

[Kever Yang]

We do not use rk_timer.c now, remove it.

Signed-off-by: Kever Yang 
---

 arch/arm/mach-rockchip/rk_timer.c | 48 ---
 1 file changed, 48 deletions(-)
 delete mode 100644 arch/arm/mach-rockchip/rk_timer.c

diff --git a/arch/arm/mach-rockchip/rk_timer.c 
b/arch/arm/mach-rockchip/rk_timer.c
deleted file mode 100644
index 853b986..000
--- a/arch/arm/mach-rockchip/rk_timer.c
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- * (C) Copyright 2015 Rockchip Electronics Co., Ltd
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include 
-#include 
-#include 
-#include 
-
-struct rk_timer * const timer_ptr = (void *)CONFIG_SYS_TIMER_BASE;
-
-static uint64_t rockchip_get_ticks(void)
-{
-   uint64_t timebase_h, timebase_l;
-
-   timebase_l = readl(_ptr->timer_curr_value0);
-   timebase_h = readl(_ptr->timer_curr_value1);
-
-   return timebase_h << 32 | timebase_l;
-}
-
-static uint64_t usec_to_tick(unsigned int usec)
-{
-   uint64_t tick = usec;
-   tick *= CONFIG_SYS_TIMER_RATE / (1000 * 1000);
-   return tick;
-}
-
-void rockchip_udelay(unsigned int usec)
-{
-   uint64_t tmp;
-
-   /* get timestamp */
-   tmp = rockchip_get_ticks() + usec_to_tick(usec);
-
-   /* loop till event */
-   while (rockchip_get_ticks() < tmp+1)
-   ;
-}
-
-void rockchip_timer_init(void)
-{
-   writel(0x, _ptr->timer_load_count0);
-   writel(0x, _ptr->timer_load_count1);
-   writel(1, _ptr->timer_ctrl_reg);
-}
-- 
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[U-Boot] [PATCH 34/36] rockchip: spl-boot-order: do not enable with OF_PLATDATA

[Kever Yang]

The "fdt_*" functions may not enable even if the OF_CONTROL is enabled.

Signed-off-by: Kever Yang 
---

 arch/arm/mach-rockchip/spl-boot-order.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/mach-rockchip/spl-boot-order.c 
b/arch/arm/mach-rockchip/spl-boot-order.c
index 843998d..cf4cc77 100644
--- a/arch/arm/mach-rockchip/spl-boot-order.c
+++ b/arch/arm/mach-rockchip/spl-boot-order.c
@@ -9,7 +9,7 @@
 #include 
 #include 
 
-#if CONFIG_IS_ENABLED(OF_CONTROL)
+#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
 /**
  * spl_node_to_boot_device() - maps from a DT-node to a SPL boot device
  * @node:  of_offset of the node
-- 
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[U-Boot] [PATCH 20/36] rockchip: rk3128: remove rockchip timer as systimer

[Kever Yang]

We use ARM arch timer instead.

Signed-off-by: Kever Yang 
---

 include/configs/rk3128_common.h | 4 
 1 file changed, 4 deletions(-)

diff --git a/include/configs/rk3128_common.h b/include/configs/rk3128_common.h
index c593f18..313a1e2 100644
--- a/include/configs/rk3128_common.h
+++ b/include/configs/rk3128_common.h
@@ -15,10 +15,6 @@
 #define CONFIG_SYS_CBSIZE  1024
 #define CONFIG_SKIP_LOWLEVEL_INIT
 
-#define CONFIG_SYS_TIMER_RATE  (24 * 1000 * 1000)
-#define CONFIG_SYS_TIMER_BASE  0x200440a0 /* TIMER5 */
-#define CONFIG_SYS_TIMER_COUNTER   (CONFIG_SYS_TIMER_BASE + 8)
-
 #define CONFIG_SYS_INIT_SP_ADDR0x6010
 #define CONFIG_SYS_LOAD_ADDR   0x60800800
 
-- 
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[U-Boot] [PATCH 36/36] rockchip: add common board file for rockchip platform

[Kever Yang]

We use common board/spl/tpl file for all rockchip SoCs,
- all the SoC spec setting should move into SoC file like rk3288.c;
- tpl is option and only purpose to init DRAM, clock, uart(option);
- spl do secure relate one time init, boot device select, boot into
  U-Boot or trust or OS in falcon mode;
- board do boot mode detect, enable regulator, usb init and so on.

Signed-off-by: Kever Yang 
---

 arch/arm/mach-rockchip/Makefile |  23 +
 arch/arm/mach-rockchip/board.c  | 136 
 arch/arm/mach-rockchip/spl.c| 195 
 arch/arm/mach-rockchip/tpl.c| 111 +++
 4 files changed, 445 insertions(+), 20 deletions(-)
 create mode 100644 arch/arm/mach-rockchip/board.c
 create mode 100644 arch/arm/mach-rockchip/spl.c
 create mode 100644 arch/arm/mach-rockchip/tpl.c

diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile
index e1b0519..3aba66c 100644
--- a/arch/arm/mach-rockchip/Makefile
+++ b/arch/arm/mach-rockchip/Makefile
@@ -11,15 +11,8 @@
 obj-spl-$(CONFIG_ROCKCHIP_BROM_HELPER) += bootrom.o
 obj-tpl-$(CONFIG_ROCKCHIP_BROM_HELPER) += bootrom.o
 
-obj-tpl-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board-tpl.o
-obj-tpl-$(CONFIG_ROCKCHIP_RK3368) += rk3368-board-tpl.o
-
-obj-spl-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board-spl.o
-obj-spl-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board-spl.o
-obj-spl-$(CONFIG_ROCKCHIP_RK322X) += rk322x-board-spl.o
-obj-spl-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board-spl.o
-obj-spl-$(CONFIG_ROCKCHIP_RK3368) += rk3368-board-spl.o spl-boot-order.o
-obj-spl-$(CONFIG_ROCKCHIP_RK3399) += rk3399-board-spl.o spl-boot-order.o
+obj-tpl-y += tpl.o
+obj-spl-y += spl.o spl-boot-order.o
 
 ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TPL_BUILD),)
 
@@ -28,21 +21,11 @@ ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TPL_BUILD),)
 # we can have the preprocessor correctly recognise both 0x0 and 0
 # meaning "turn it off".
 obj-y += boot_mode.o
-
-obj-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board.o
-obj-$(CONFIG_ROCKCHIP_RK3128) += rk3128-board.o
-obj-$(CONFIG_ROCKCHIP_RK322X) += rk322x-board.o
-obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board.o
-obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board.o
-obj-$(CONFIG_ROCKCHIP_RK3399) += rk3399-board.o
+obj-y += board.o
 endif
 
 obj-$(CONFIG_$(SPL_TPL_)RAM) += sdram_common.o
 
-ifndef CONFIG_ARM64
-obj-y += rk_timer.o
-endif
-
 obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036/
 obj-$(CONFIG_ROCKCHIP_RK3128) += rk3128/
 ifndef CONFIG_TPL_BUILD
diff --git a/arch/arm/mach-rockchip/board.c b/arch/arm/mach-rockchip/board.c
new file mode 100644
index 000..52c6f66
--- /dev/null
+++ b/arch/arm/mach-rockchip/board.c
@@ -0,0 +1,136 @@
+/*
+ * (C) Copyright 2017 Rockchip Electronics Co., Ltd.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#ifdef CONFIG_DM_REGULATOR
+#include 
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if defined(CONFIG_USB_FUNCTION_FASTBOOT)
+int fb_set_reboot_flag(void)
+{
+   printf("Setting reboot to fastboot flag ...\n");
+   /* Set boot mode to fastboot */
+   writel(BOOT_FASTBOOT, CONFIG_ROCKCHIP_BOOT_MODE_REG);
+
+   return 0;
+}
+
+#define FASTBOOT_KEY_GPIO 43 /* GPIO1_B3 */
+static int fastboot_key_pressed(void)
+{
+   gpio_request(FASTBOOT_KEY_GPIO, "fastboot_key");
+   gpio_direction_input(FASTBOOT_KEY_GPIO);
+   return !gpio_get_value(FASTBOOT_KEY_GPIO);
+}
+#endif
+
+__weak int rk_board_init(void)
+{
+   return 0;
+}
+
+__weak int rk_board_late_init(void)
+{
+   return 0;
+}
+
+int board_late_init(void)
+{
+#if defined(CONFIG_USB_FUNCTION_FASTBOOT)
+   if (fastboot_key_pressed()) {
+   printf("fastboot key pressed!\n");
+   fb_set_reboot_flag();
+   }
+#endif
+
+#if (CONFIG_ROCKCHIP_BOOT_MODE_REG > 0)
+   setup_boot_mode();
+#endif
+
+   return rk_board_late_init();
+}
+
+int board_init(void)
+{
+   int ret;
+
+#if !defined(CONFIG_SUPPORT_SPL)
+   board_debug_uart_init();
+#endif
+#ifdef CONFIG_DM_REGULATOR
+   ret = regulators_enable_boot_on(false);
+   if (ret)
+   debug("%s: Cannot enable boot on regulator\n", __func__);
+#endif
+
+   return rk_board_init();
+}
+
+#if !defined(CONFIG_SYS_DCACHE_OFF) && !defined(CONFIG_ARM64)
+void enable_caches(void)
+{
+   /* Enable D-cache. I-cache is already enabled in start.S */
+   dcache_enable();
+}
+#endif
+
+#if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG)
+#include 
+#include 
+
+static struct dwc2_plat_otg_data otg_data = {
+   .rx_fifo_sz = 512,
+   .np_tx_fifo_sz  = 16,
+   .tx_fifo_sz = 128,
+};
+
+int board_usb_init(int index, enum usb_init_type init)
+{
+   int node;
+   const char *mode;
+   bool matched = false;
+   const void *blob = gd->fdt_blob;
+
+   /* find the usb_otg node */
+   node = 

[U-Boot] [PATCH 33/36] rockchip: dts: rk3399-firefly: enable uart2 in spl

[Kever Yang]

pre-loader console in SPL needs UART.

Signed-off-by: Kever Yang 
---

 arch/arm/dts/rk3399-firefly.dts | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/dts/rk3399-firefly.dts b/arch/arm/dts/rk3399-firefly.dts
index f134c00..a007fa1 100644
--- a/arch/arm/dts/rk3399-firefly.dts
+++ b/arch/arm/dts/rk3399-firefly.dts
@@ -648,6 +648,7 @@
 };
 
  {
+   u-boot,dm-pre-reloc;
status = "okay";
 };
 
-- 
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[U-Boot] [PATCH 28/36] rockchip: rk3328: prepare to use common board file

[Kever Yang]

Use common board file and move SoC spec setting into rk3328.c

Signed-off-by: Kever Yang 
---

 arch/arm/mach-rockchip/rk3328/rk3328.c | 59 +-
 board/rockchip/evb_rk3328/evb-rk3328.c | 66 --
 2 files changed, 51 insertions(+), 74 deletions(-)

diff --git a/arch/arm/mach-rockchip/rk3328/rk3328.c 
b/arch/arm/mach-rockchip/rk3328/rk3328.c
index 6764494..ddf53d5 100644
--- a/arch/arm/mach-rockchip/rk3328/rk3328.c
+++ b/arch/arm/mach-rockchip/rk3328/rk3328.c
@@ -5,12 +5,22 @@
  */
 
 #include 
+#include 
 #include 
+#include 
+#include 
 #include 
 #include 
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#define CRU_BASE   0xFF44
+#define GRF_BASE   0xFF10
+#define UART2_BASE 0xFF13
+
+#define CRU_MISC_CON   0xff440084
+#define FW_DDR_CON_REG 0xff7c0040
+
 static struct mm_region rk3328_mem_map[] = {
{
.virt = 0x0UL,
@@ -33,20 +43,53 @@ static struct mm_region rk3328_mem_map[] = {
 
 struct mm_region *mem_map = rk3328_mem_map;
 
-int dram_init_banksize(void)
+const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
+   [BROM_BOOTSOURCE_EMMC] = "/rksdmmc@ff52",
+   [BROM_BOOTSOURCE_SD] = "/rksdmmc@ff50",
+};
+
+int arch_cpu_init(void)
 {
-   size_t max_size = min((unsigned long)gd->ram_size, gd->ram_top);
+#ifdef CONFIG_TPL_BUILD
+   struct rk3328_grf_regs * const grf = (void *)GRF_BASE;
+   /* We do some SoC one time setting here. */
+
+   /* Disable the ddr secure region setting to make it non-secure */
+   rk_setreg(FW_DDR_CON_REG, 0x200);
 
-   /* Reserve 0x20 for ATF bl31 */
-   gd->bd->bi_dram[0].start = 0x20;
-   gd->bd->bi_dram[0].size = max_size - gd->bd->bi_dram[0].start;
+   /* HDMI phy clock source select HDMIPHY clock out */
+   rk_clrreg(CRU_MISC_CON, 1 << 13);
 
+#endif
return 0;
 }
 
-int arch_cpu_init(void)
+void board_debug_uart_init(void)
 {
-   /* We do some SoC one time setting here. */
+#ifdef CONFIG_TPL_BUILD
+   struct rk3328_grf_regs * const grf = (void *)GRF_BASE;
+   struct rk_uart * const uart = (void *)UART2_BASE;
 
-   return 0;
+   /* uart_sel_clk default select 24MHz */
+   writel((3 << (8 + 16)) | (2 << 8), CRU_BASE + 0x148);
+
+   /* init uart baud rate 150 */
+   writel(0x83, >lcr);
+   writel(0x1, >rbr);
+   writel(0x3, >lcr);
+
+   /* Enable early UART2 */
+   rk_clrsetreg(>com_iomux,
+IOMUX_SEL_UART2_MASK,
+IOMUX_SEL_UART2_M1 << IOMUX_SEL_UART2_SHIFT);
+   rk_clrsetreg(>gpio2a_iomux,
+GPIO2A0_SEL_MASK,
+GPIO2A0_UART2_TX_M1 << GPIO2A0_SEL_SHIFT);
+   rk_clrsetreg(>gpio2a_iomux,
+GPIO2A1_SEL_MASK,
+GPIO2A1_UART2_RX_M1 << GPIO2A1_SEL_SHIFT);
+
+   /* enable FIFO */
+   writel(0x1, >sfe);
+#endif
 }
diff --git a/board/rockchip/evb_rk3328/evb-rk3328.c 
b/board/rockchip/evb_rk3328/evb-rk3328.c
index 99a73da..c8e7a3a 100644
--- a/board/rockchip/evb_rk3328/evb-rk3328.c
+++ b/board/rockchip/evb_rk3328/evb-rk3328.c
@@ -3,69 +3,3 @@
  *
  * SPDX-License-Identifier: GPL-2.0+
  */
-
-#include 
-#include 
-#include 
-#include 
-#include 
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int board_init(void)
-{
-   int ret;
-
-   ret = regulators_enable_boot_on(false);
-   if (ret)
-   debug("%s: Cannot enable boot on regulator\n", __func__);
-
-   return ret;
-}
-
-#if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG)
-#include 
-#include 
-
-static struct dwc2_plat_otg_data rk3328_otg_data = {
-   .rx_fifo_sz = 512,
-   .np_tx_fifo_sz  = 16,
-   .tx_fifo_sz = 128,
-};
-
-int board_usb_init(int index, enum usb_init_type init)
-{
-   int node;
-   const char *mode;
-   bool matched = false;
-   const void *blob = gd->fdt_blob;
-
-   /* find the usb_otg node */
-   node = fdt_node_offset_by_compatible(blob, -1,
-   "rockchip,rk3328-usb");
-
-   while (node > 0) {
-   mode = fdt_getprop(blob, node, "dr_mode", NULL);
-   if (mode && strcmp(mode, "otg") == 0) {
-   matched = true;
-   break;
-   }
-
-   node = fdt_node_offset_by_compatible(blob, node,
-   "rockchip,rk3328-usb");
-   }
-   if (!matched) {
-   debug("Not found usb_otg device\n");
-   return -ENODEV;
-   }
-
-   rk3328_otg_data.regs_otg = fdtdec_get_addr(blob, node, "reg");
-
-   return dwc2_udc_probe(_otg_data);
-}
-
-int board_usb_cleanup(int index, enum usb_init_type init)
-{
-   return 0;
-}
-#endif
-- 
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[U-Boot] [PATCH 30/36] rockchip: lion-rk3368: remove rockchip timer

[Kever Yang]

We use ARM generic timer.

Signed-off-by: Kever Yang 
---

 configs/lion-rk3368_defconfig | 4 
 1 file changed, 4 deletions(-)

diff --git a/configs/lion-rk3368_defconfig b/configs/lion-rk3368_defconfig
index 8a95ce3..89c4d76 100644
--- a/configs/lion-rk3368_defconfig
+++ b/configs/lion-rk3368_defconfig
@@ -88,10 +88,6 @@ CONFIG_DEBUG_UART_ANNOUNCE=y
 CONFIG_DEBUG_UART_SKIP_INIT=y
 CONFIG_ROCKCHIP_SPI=y
 CONFIG_SYSRESET=y
-CONFIG_TIMER=y
-CONFIG_SPL_TIMER=y
-CONFIG_TPL_TIMER=y
-CONFIG_ROCKCHIP_TIMER=y
 CONFIG_USE_TINY_PRINTF=y
 CONFIG_SPL_TINY_MEMSET=y
 CONFIG_LZO=y
-- 
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[U-Boot] [PATCH 17/36] rockchip: sdram_common: add common dram_init_banksize

[Kever Yang]

dram_init_banksize() can be common used by all SoCs, move it into
sdram_common.c

Signed-off-by: Kever Yang 
---

 arch/arm/mach-rockchip/sdram_common.c | 63 ++-
 1 file changed, 62 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-rockchip/sdram_common.c 
b/arch/arm/mach-rockchip/sdram_common.c
index 3a71f09..ff86096 100644
--- a/arch/arm/mach-rockchip/sdram_common.c
+++ b/arch/arm/mach-rockchip/sdram_common.c
@@ -21,13 +21,74 @@ struct ddr_param {
 
 #define PARAM_DRAM_INFO_OFFSET 0x200
 
+#define TRUST_PARAMETER_OFFSET(34 * 1024 * 1024)
+
+struct tos_parameter_t {
+   u32 version;
+   u32 checksum;
+   struct {
+   char name[8];
+   s64 phy_addr;
+   u32 size;
+   u32 flags;
+   } tee_mem;
+   struct {
+   char name[8];
+   s64 phy_addr;
+   u32 size;
+   u32 flags;
+   } drm_mem;
+   s64 reserve[8];
+};
+
+int dram_init_banksize(void)
+{
+   size_t top = min((unsigned long)(gd->ram_size + CONFIG_SYS_SDRAM_BASE),
+gd->ram_top);
+
+#ifdef CONFIG_ARM64
+   /* Reserve 0x20 for ATF bl31 */
+   gd->bd->bi_dram[0].start = 0x20;
+   gd->bd->bi_dram[0].size = top - gd->bd->bi_dram[0].start;
+#else
+#ifdef CONFIG_SPL_OPTEE
+   struct tos_parameter_t *tos_parameter;
+
+   tos_parameter = (struct tos_parameter_t *)(CONFIG_SYS_SDRAM_BASE +
+   TRUST_PARAMETER_OFFSET);
+
+   if (tos_parameter->tee_mem.flags == 1) {
+   gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+   gd->bd->bi_dram[0].size = tos_parameter->tee_mem.phy_addr
+   - CONFIG_SYS_SDRAM_BASE;
+   gd->bd->bi_dram[1].start = tos_parameter->tee_mem.phy_addr +
+   tos_parameter->tee_mem.size;
+   gd->bd->bi_dram[1].size = gd->bd->bi_dram[0].start
+   + top - gd->bd->bi_dram[1].start;
+   } else {
+   gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+   gd->bd->bi_dram[0].size = 0x840;
+   /* Reserve 32M for OPTEE with TA */
+   gd->bd->bi_dram[1].start = CONFIG_SYS_SDRAM_BASE
+   + gd->bd->bi_dram[0].size + 0x200;
+   gd->bd->bi_dram[1].size = gd->bd->bi_dram[0].start
+   + top - gd->bd->bi_dram[1].start;
+   }
+#else
+   gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+   gd->bd->bi_dram[0].size = top - gd->bd->bi_dram[0].start;
+#endif
+#endif
+
+   return 0;
+}
+
 size_t rockchip_sdram_size(phys_addr_t reg)
 {
u32 rank, col, bk, cs0_row, cs1_row, bw, row_3_4;
size_t chipsize_mb = 0;
size_t size_mb = 0;
u32 ch;
-
u32 sys_reg = readl(reg);
u32 ch_num = 1 + ((sys_reg >> SYS_REG_NUM_CH_SHIFT)
   & SYS_REG_NUM_CH_MASK);
-- 
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[U-Boot] [PATCH 15/36] rockchip: declare sdram_init() in common header

[Kever Yang]

We need a dedicate sdram_init() function for those SoCS not
using SPL_FRAMEWORK.

Signed-off-by: Kever Yang 
---

 arch/arm/include/asm/arch-rockchip/sys_proto.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm/include/asm/arch-rockchip/sys_proto.h 
b/arch/arm/include/asm/arch-rockchip/sys_proto.h
index 3617ac2..7b7e336 100644
--- a/arch/arm/include/asm/arch-rockchip/sys_proto.h
+++ b/arch/arm/include/asm/arch-rockchip/sys_proto.h
@@ -7,5 +7,8 @@
 #ifndef _ASM_ARCH_SYS_PROTO_H
 #define _ASM_ARCH_SYS_PROTO_H
 
+#ifndef CONFIG_SPL_FRAMEWORK
+void sdram_init(void);
+#endif
 
 #endif /* _ASM_ARCH_SYS_PROTO_H */
-- 
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[U-Boot] [PATCH 23/36] rockchip: rk3288: remove rockchip timer for sys timer

[Kever Yang]

Use ARM arch timer instead

Signed-off-by: Kever Yang 
---

 include/configs/rk3288_common.h | 4 
 1 file changed, 4 deletions(-)

diff --git a/include/configs/rk3288_common.h b/include/configs/rk3288_common.h
index 44d5c2a..8d0a0f9 100644
--- a/include/configs/rk3288_common.h
+++ b/include/configs/rk3288_common.h
@@ -15,10 +15,6 @@
 #define CONFIG_SYS_MALLOC_LEN  (32 << 20)
 #define CONFIG_SYS_CBSIZE  1024
 
-#define CONFIG_SYS_TIMER_RATE  (24 * 1000 * 1000)
-#defineCONFIG_SYS_TIMER_BASE   0xff810020 /* TIMER7 */
-#define CONFIG_SYS_TIMER_COUNTER   (CONFIG_SYS_TIMER_BASE + 8)
-
 #ifdef CONFIG_SPL_ROCKCHIP_BACK_TO_BROM
 /* Bootrom will load u-boot binary to 0x0 once return from SPL */
 #endif
-- 
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[U-Boot] [PATCH 12/36] rockchip: rk3036: sdram: use udelay instead of rockchip_udelay

[Kever Yang]

We are going to remove rockchip_udelay after enable arch timer.

Signed-off-by: Kever Yang 
---

 arch/arm/mach-rockchip/rk3036/sdram_rk3036.c | 19 +--
 1 file changed, 9 insertions(+), 10 deletions(-)

diff --git a/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c 
b/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c
index e5393ec..ce3f09a 100644
--- a/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c
+++ b/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c
@@ -10,7 +10,6 @@
 #include 
 #include 
 #include 
-#include 
 #include 
 
 /*
@@ -346,7 +345,7 @@ static void rkdclk_init(struct rk3036_sdram_priv *priv)
 
/* waiting for pll lock */
while (readl(>con1) & (1 << PLL_LOCK_STATUS_SHIFT))
-   rockchip_udelay(1);
+   udelay(1);
 
/* PLL enter normal-mode */
rk_clrsetreg(>cru->cru_mode_con, DPLL_MODE_MASK,
@@ -374,25 +373,25 @@ void phy_pctrl_reset(struct rk3036_sdram_priv *priv)
1 << DDRCTRL_PSRST_SHIFT | 1 << DDRCTRL_SRST_SHIFT |
1 << DDRPHY_PSRST_SHIFT | 1 << DDRPHY_SRST_SHIFT);
 
-   rockchip_udelay(10);
+   udelay(10);
 
rk_clrreg(>cru->cru_softrst_con[5], 1 << DDRPHY_PSRST_SHIFT |
  1 << DDRPHY_SRST_SHIFT);
-   rockchip_udelay(10);
+   udelay(10);
 
rk_clrreg(>cru->cru_softrst_con[5], 1 << DDRCTRL_PSRST_SHIFT |
  1 << DDRCTRL_SRST_SHIFT);
-   rockchip_udelay(10);
+   udelay(10);
 
clrsetbits_le32(_phy->ddrphy_reg1,
SOFT_RESET_MASK << SOFT_RESET_SHIFT,
0 << SOFT_RESET_SHIFT);
-   rockchip_udelay(10);
+   udelay(10);
clrsetbits_le32(_phy->ddrphy_reg1,
SOFT_RESET_MASK << SOFT_RESET_SHIFT,
3 << SOFT_RESET_SHIFT);
 
-   rockchip_udelay(1);
+   udelay(1);
 }
 
 void phy_dll_bypass_set(struct rk3036_sdram_priv *priv, unsigned int freq)
@@ -445,7 +444,7 @@ static void send_command(struct rk3036_ddr_pctl *pctl,
 u32 rank, u32 cmd, u32 arg)
 {
writel((START_CMD | (rank << 20) | arg | cmd), >mcmd);
-   rockchip_udelay(1);
+   udelay(1);
while (readl(>mcmd) & START_CMD)
;
 }
@@ -455,7 +454,7 @@ static void memory_init(struct rk3036_sdram_priv *priv)
struct rk3036_ddr_pctl *pctl = priv->pctl;
 
send_command(pctl, 3, DESELECT_CMD, 0);
-   rockchip_udelay(1);
+   udelay(1);
send_command(pctl, 3, PREA_CMD, 0);
send_command(pctl, 3, MRS_CMD,
 (0x02 & BANK_ADDR_MASK) << BANK_ADDR_SHIFT |
@@ -493,7 +492,7 @@ static void data_training(struct rk3036_sdram_priv *priv)
clrsetbits_le32(_phy->ddrphy_reg2, 0x03,
DQS_SQU_CAL_NORMAL_MODE | DQS_SQU_CAL_START);
 
-   rockchip_udelay(1);
+   udelay(1);
while ((readl(_phy->ddrphy_reg62) & CAL_DONE_MASK) !=
(HIGH_8BIT_CAL_DONE | LOW_8BIT_CAL_DONE)) {
;
-- 
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[U-Boot] [PATCH 13/36] rockchip: rk3036: remove sys timer

[Kever Yang]

Use ARM arch timer instead.

Signed-off-by: Kever Yang 
---

 include/configs/rk3036_common.h | 4 
 1 file changed, 4 deletions(-)

diff --git a/include/configs/rk3036_common.h b/include/configs/rk3036_common.h
index c5ec864..8230373 100644
--- a/include/configs/rk3036_common.h
+++ b/include/configs/rk3036_common.h
@@ -14,10 +14,6 @@
 #define CONFIG_SYS_CBSIZE  1024
 #define CONFIG_SKIP_LOWLEVEL_INIT
 
-#define CONFIG_SYS_TIMER_RATE  (24 * 1000 * 1000)
-#define CONFIG_SYS_TIMER_BASE  0x200440a0 /* TIMER5 */
-#define CONFIG_SYS_TIMER_COUNTER   (CONFIG_SYS_TIMER_BASE + 8)
-
 #define CONFIG_SYS_INIT_SP_ADDR0x6010
 #define CONFIG_SYS_LOAD_ADDR   0x60800800
 #define CONFIG_SPL_STACK   0x10081fff
-- 
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[U-Boot] [PATCH 21/36] rockchip: rk3128: prepare use common board file

[Kever Yang]

remoe rk3128 board file and move SoC spec setting into rk3128.c

Signed-off-by: Kever Yang 
---

 arch/arm/mach-rockchip/rk3128-board.c | 127 --
 1 file changed, 127 deletions(-)
 delete mode 100644 arch/arm/mach-rockchip/rk3128-board.c

diff --git a/arch/arm/mach-rockchip/rk3128-board.c 
b/arch/arm/mach-rockchip/rk3128-board.c
deleted file mode 100644
index 2e8393d..000
--- a/arch/arm/mach-rockchip/rk3128-board.c
+++ /dev/null
@@ -1,127 +0,0 @@
-/*
- * (C) Copyright 2017 Rockchip Electronics Co., Ltd.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-
-DECLARE_GLOBAL_DATA_PTR;
-
-__weak int rk_board_late_init(void)
-{
-   return 0;
-}
-
-int board_late_init(void)
-{
-   setup_boot_mode();
-
-   return rk_board_late_init();
-}
-
-int board_init(void)
-{
-   int ret = 0;
-
-   rockchip_timer_init();
-
-   ret = regulators_enable_boot_on(false);
-   if (ret) {
-   debug("%s: Cannot enable boot on regulator\n", __func__);
-   return ret;
-   }
-
-   return 0;
-}
-
-int dram_init_banksize(void)
-{
-   gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
-   gd->bd->bi_dram[0].size = 0x840;
-   /* Reserve 0xe0(14MB) for OPTEE with TA enabled, otherwise 2MB */
-   gd->bd->bi_dram[1].start = CONFIG_SYS_SDRAM_BASE
-   + gd->bd->bi_dram[0].size + 0xe0;
-   gd->bd->bi_dram[1].size = gd->bd->bi_dram[0].start
-   + gd->ram_size - gd->bd->bi_dram[1].start;
-
-   return 0;
-}
-
-#ifndef CONFIG_SYS_DCACHE_OFF
-void enable_caches(void)
-{
-   /* Enable D-cache. I-cache is already enabled in start.S */
-   dcache_enable();
-}
-#endif
-
-#if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG)
-#include 
-#include 
-
-static struct dwc2_plat_otg_data rk3128_otg_data = {
-   .rx_fifo_sz = 512,
-   .np_tx_fifo_sz  = 16,
-   .tx_fifo_sz = 128,
-};
-
-int board_usb_init(int index, enum usb_init_type init)
-{
-   int node;
-   const char *mode;
-   bool matched = false;
-   const void *blob = gd->fdt_blob;
-
-   /* find the usb_otg node */
-   node = fdt_node_offset_by_compatible(blob, -1,
-"rockchip,rk3128-usb");
-
-   while (node > 0) {
-   mode = fdt_getprop(blob, node, "dr_mode", NULL);
-   if (mode && strcmp(mode, "otg") == 0) {
-   matched = true;
-   break;
-   }
-
-   node = fdt_node_offset_by_compatible(blob, node,
-"rockchip,rk3128-usb");
-   }
-   if (!matched) {
-   debug("Not found usb_otg device\n");
-   return -ENODEV;
-   }
-   rk3128_otg_data.regs_otg = fdtdec_get_addr(blob, node, "reg");
-
-   return dwc2_udc_probe(_otg_data);
-}
-
-int board_usb_cleanup(int index, enum usb_init_type init)
-{
-   return 0;
-}
-#endif
-
-#if defined(CONFIG_USB_FUNCTION_FASTBOOT)
-int fb_set_reboot_flag(void)
-{
-   struct rk3128_grf *grf;
-
-   printf("Setting reboot to fastboot flag ...\n");
-   grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
-   /* Set boot mode to fastboot */
-   writel(BOOT_FASTBOOT, >os_reg[0]);
-
-   return 0;
-}
-#endif
-- 
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[U-Boot] [PATCH 11/36] rockchip: defconfig enable sysreset for rk3229 spl

[Kever Yang]

We need CONFIG_SPL_DRIVERS_MISC_SUPPORT to enable sysreset driver,
which will fix missing do_reset() error in SPL build.

Signed-off-by: Kever Yang 
---

 configs/evb-rk3229_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/configs/evb-rk3229_defconfig b/configs/evb-rk3229_defconfig
index 96afda8..4f1007a 100644
--- a/configs/evb-rk3229_defconfig
+++ b/configs/evb-rk3229_defconfig
@@ -7,6 +7,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x800
 CONFIG_ROCKCHIP_RK322X=y
 CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y
 CONFIG_TARGET_EVB_RK3229=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
 CONFIG_SPL_STACK_R_ADDR=0x8
 CONFIG_DEFAULT_DEVICE_TREE="rk3229-evb"
 CONFIG_DEBUG_UART=y
-- 
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[U-Boot] [PATCH 19/36] rockchip: rk3188: prepare to use common board file

[Kever Yang]

Move SoC spec setting into rk3188.c

Signed-off-by: Kever Yang 
---

 arch/arm/mach-rockchip/rk3188-board-spl.c | 226 --
 arch/arm/mach-rockchip/rk3188-board.c |  82 ---
 arch/arm/mach-rockchip/rk3188/Makefile|   1 +
 arch/arm/mach-rockchip/rk3188/rk3188.c|  23 +++
 4 files changed, 24 insertions(+), 308 deletions(-)
 delete mode 100644 arch/arm/mach-rockchip/rk3188-board-spl.c
 delete mode 100644 arch/arm/mach-rockchip/rk3188-board.c
 create mode 100644 arch/arm/mach-rockchip/rk3188/rk3188.c

diff --git a/arch/arm/mach-rockchip/rk3188-board-spl.c 
b/arch/arm/mach-rockchip/rk3188-board-spl.c
deleted file mode 100644
index 74771d3..000
--- a/arch/arm/mach-rockchip/rk3188-board-spl.c
+++ /dev/null
@@ -1,226 +0,0 @@
-/*
- * (C) Copyright 2015 Google, Inc
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-
-DECLARE_GLOBAL_DATA_PTR;
-
-u32 spl_boot_device(void)
-{
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
-   const void *blob = gd->fdt_blob;
-   struct udevice *dev;
-   const char *bootdev;
-   int node;
-   int ret;
-
-   bootdev = fdtdec_get_config_string(blob, "u-boot,boot0");
-   debug("Boot device %s\n", bootdev);
-   if (!bootdev)
-   goto fallback;
-
-   node = fdt_path_offset(blob, bootdev);
-   if (node < 0) {
-   debug("node=%d\n", node);
-   goto fallback;
-   }
-   ret = device_get_global_by_of_offset(node, );
-   if (ret) {
-   debug("device at node %s/%d not found: %d\n", bootdev, node,
- ret);
-   goto fallback;
-   }
-   debug("Found device %s\n", dev->name);
-   switch (device_get_uclass_id(dev)) {
-   case UCLASS_SPI_FLASH:
-   return BOOT_DEVICE_SPI;
-   case UCLASS_MMC:
-   return BOOT_DEVICE_MMC1;
-   default:
-   debug("Booting from device uclass '%s' not supported\n",
- dev_get_uclass_name(dev));
-   }
-
-fallback:
-#endif
-   return BOOT_DEVICE_MMC1;
-}
-
-static int setup_arm_clock(void)
-{
-   struct udevice *dev;
-   struct clk clk;
-   int ret;
-
-   ret = rockchip_get_clk();
-   if (ret)
-   return ret;
-
-   clk.id = CLK_ARM;
-   ret = clk_request(dev, );
-   if (ret < 0)
-   return ret;
-
-   ret = clk_set_rate(, 6);
-
-   clk_free();
-   return ret;
-}
-
-void board_init_f(ulong dummy)
-{
-   struct udevice *pinctrl, *dev;
-   int ret;
-
-   /* Example code showing how to enable the debug UART on RK3188 */
-#ifdef EARLY_UART
-#include 
-   /* Enable early UART on the RK3188 */
-#define GRF_BASE   0x20008000
-   struct rk3188_grf * const grf = (void *)GRF_BASE;
-
-   rk_clrsetreg(>gpio1b_iomux,
-GPIO1B1_MASK << GPIO1B1_SHIFT |
-GPIO1B0_MASK << GPIO1B0_SHIFT,
-GPIO1B1_UART2_SOUT << GPIO1B1_SHIFT |
-GPIO1B0_UART2_SIN << GPIO1B0_SHIFT);
-   /*
-* Debug UART can be used from here if required:
-*
-* debug_uart_init();
-* printch('a');
-* printhex8(0x1234);
-* printascii("string");
-*/
-   debug_uart_init();
-   printch('s');
-   printch('p');
-   printch('l');
-   printch('\n');
-#endif
-
-   ret = spl_early_init();
-   if (ret) {
-   debug("spl_early_init() failed: %d\n", ret);
-   hang();
-   }
-
-   rockchip_timer_init();
-
-   ret = rockchip_get_clk();
-   if (ret) {
-   debug("CLK init failed: %d\n", ret);
-   return;
-   }
-
-   ret = uclass_get_device(UCLASS_PINCTRL, 0, );
-   if (ret) {
-   debug("Pinctrl init failed: %d\n", ret);
-   return;
-   }
-
-   ret = uclass_get_device(UCLASS_RAM, 0, );
-   if (ret) {
-   debug("DRAM init failed: %d\n", ret);
-   return;
-   }
-
-   setup_arm_clock();
-#if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM) && !defined(CONFIG_SPL_BOARD_INIT)
-   back_to_bootrom(BROM_BOOT_NEXTSTAGE);
-#endif
-}
-
-static int setup_led(void)
-{
-#ifdef CONFIG_SPL_LED
-   struct udevice *dev;
-   char *led_name;
-   int ret;
-
-   led_name = fdtdec_get_config_string(gd->fdt_blob, "u-boot,boot-led");
-   if (!led_name)
-   return 0;
-   ret = led_get_by_label(led_name, );
-   if (ret) {
-   debug("%s: get=%d\n", __func__, ret);
-   return ret;
-   }
-   ret = led_set_on(dev, 1);
-   if (ret)
-   return ret;
-#endif
-

[U-Boot] [PATCH 06/36] rockchip: add IRAM_START_ADDR for all SoCs

[Kever Yang]

We add this for get the location for boot device of bootrom.

Signed-off-by: Kever Yang 
---

 arch/arm/mach-rockchip/Kconfig | 17 +
 1 file changed, 17 insertions(+)

diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index 5dfe452..98bf935 100644
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -209,6 +209,23 @@ config ROCKCHIP_STIMER_BASE
  The secure timer inited in SPL/TPL in secure word, ARM generic timer
  works after this timer work.
 
+config ROCKCHIP_IRAM_START_ADDR
+   hex "Rockchip Secure timer base address"
+   default 0xff0e if ROCKCHIP_PX30
+   default 0x1008 if ROCKCHIP_RK3036
+   default 0x1008 if ROCKCHIP_RK3128
+   default 0x1008 if ROCKCHIP_RK3188
+   default 0x1008 if ROCKCHIP_RK322X
+   default 0xff70 if ROCKCHIP_RK3288
+   default 0xff091000 if ROCKCHIP_RK3328
+   default 0xff8c if ROCKCHIP_RK3368
+   default 0xff8c if ROCKCHIP_RK3399
+   default 0x1008 if ROCKCHIP_RV1108
+   default 0
+   help
+ The IRAM start addr is to locate variant of the boot device from
+ bootrom.
+
 config ROCKCHIP_SPL_RESERVE_IRAM
hex "Size of IRAM reserved in SPL"
default 0
-- 
1.9.1

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[U-Boot] [PATCH 05/36] rockchip: add STIMER_BASE for all SoCs

[Kever Yang]

STIMER is can only access in secure mode if the SoCs supports trust,
and it locate in alive power domain, as the source of ARM arch/generic
timer, we add a base addr for all SoCs so that we can init with a common
function.

Signed-off-by: Kever Yang 
---

 arch/arm/mach-rockchip/Kconfig | 19 +++
 1 file changed, 19 insertions(+)

diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index 007cb22..5dfe452 100644
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -190,6 +190,25 @@ config ROCKCHIP_BOOT_MODE_REG
  The Soc will enter to different boot mode(defined in 
asm/arch/boot_mode.h)
  according to the value from this register.
 
+config ROCKCHIP_STIMER_BASE
+   hex "Rockchip Secure timer base address"
+   default 0xff220020 if ROCKCHIP_PX30
+   default 0x200440a0 if ROCKCHIP_RK3036
+   default 0x2000e000 if ROCKCHIP_RK3066
+   default 0x20018020 if ROCKCHIP_RK3126
+   default 0x200440a0 if ROCKCHIP_RK3128
+   default 0x2000e000 if ROCKCHIP_RK3188
+   default 0x110d0020 if ROCKCHIP_RK322X
+   default 0xff810020 if ROCKCHIP_RK3288
+   default 0xff1d0020 if ROCKCHIP_RK3328
+   default 0xff830020 if ROCKCHIP_RK3368
+   default 0xff8680a0 if ROCKCHIP_RK3399
+   default 0x10350020 if ROCKCHIP_RV1108
+   default 0
+   help
+ The secure timer inited in SPL/TPL in secure word, ARM generic timer
+ works after this timer work.
+
 config ROCKCHIP_SPL_RESERVE_IRAM
hex "Size of IRAM reserved in SPL"
default 0
-- 
1.9.1

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[U-Boot] [PATCH 09/36] rockchip: rk322x: sdram: use common udelay instead of rockchip_udelay

[Kever Yang]

Do not need to use rockchip_udelay after we can use systimer.

Signed-off-by: Kever Yang 
---

 drivers/ram/rockchip/sdram_rk322x.c | 29 ++---
 1 file changed, 14 insertions(+), 15 deletions(-)

diff --git a/drivers/ram/rockchip/sdram_rk322x.c 
b/drivers/ram/rockchip/sdram_rk322x.c
index cc3138b..c4da000 100644
--- a/drivers/ram/rockchip/sdram_rk322x.c
+++ b/drivers/ram/rockchip/sdram_rk322x.c
@@ -17,7 +17,6 @@
 #include 
 #include 
 #include 
-#include 
 #include 
 #include 
 #include 
@@ -97,26 +96,26 @@ void phy_pctrl_reset(struct rk322x_cru *cru,
1 << DDRCTRL_PSRST_SHIFT | 1 << DDRCTRL_SRST_SHIFT |
1 << DDRPHY_PSRST_SHIFT | 1 << DDRPHY_SRST_SHIFT);
 
-   rockchip_udelay(10);
+   udelay(10);
 
rk_clrreg(>cru_softrst_con[5], 1 << DDRPHY_PSRST_SHIFT |
  1 << DDRPHY_SRST_SHIFT);
-   rockchip_udelay(10);
+   udelay(10);
 
rk_clrreg(>cru_softrst_con[5], 1 << DDRCTRL_PSRST_SHIFT |
  1 << DDRCTRL_SRST_SHIFT);
-   rockchip_udelay(10);
+   udelay(10);
 
clrbits_le32(_phy->ddrphy_reg[0],
 SOFT_RESET_MASK << SOFT_RESET_SHIFT);
-   rockchip_udelay(10);
+   udelay(10);
setbits_le32(_phy->ddrphy_reg[0],
 SOFT_DERESET_ANALOG);
-   rockchip_udelay(5);
+   udelay(5);
setbits_le32(_phy->ddrphy_reg[0],
 SOFT_DERESET_DIGITAL);
 
-   rockchip_udelay(1);
+   udelay(1);
 }
 
 void phy_dll_bypass_set(struct rk322x_ddr_phy *ddr_phy, u32 freq)
@@ -155,7 +154,7 @@ static void send_command(struct rk322x_ddr_pctl *pctl,
 u32 rank, u32 cmd, u32 arg)
 {
writel((START_CMD | (rank << 20) | arg | cmd), >mcmd);
-   rockchip_udelay(1);
+   udelay(1);
while (readl(>mcmd) & START_CMD)
;
 }
@@ -168,7 +167,7 @@ static void memory_init(struct chan_info *chan,
 
if (dramtype == DDR3) {
send_command(pctl, 3, DESELECT_CMD, 0);
-   rockchip_udelay(1);
+   udelay(1);
send_command(pctl, 3, PREA_CMD, 0);
send_command(pctl, 3, MRS_CMD,
 (0x02 & BANK_ADDR_MASK) << BANK_ADDR_SHIFT |
@@ -197,17 +196,17 @@ static void memory_init(struct chan_info *chan,
 (0x63 & LPDDR23_MA_MASK) << LPDDR23_MA_SHIFT |
 (0 & LPDDR23_OP_MASK) <<
 LPDDR23_OP_SHIFT);
-   rockchip_udelay(10);
+   udelay(10);
send_command(pctl, 3, MRS_CMD,
 (0x10 & LPDDR23_MA_MASK) << LPDDR23_MA_SHIFT |
 (0xff & LPDDR23_OP_MASK) <<
 LPDDR23_OP_SHIFT);
-   rockchip_udelay(1);
+   udelay(1);
send_command(pctl, 3, MRS_CMD,
 (0x10 & LPDDR23_MA_MASK) << LPDDR23_MA_SHIFT |
 (0xff & LPDDR23_OP_MASK) <<
 LPDDR23_OP_SHIFT);
-   rockchip_udelay(1);
+   udelay(1);
send_command(pctl, 3, MRS_CMD,
 (1 & LPDDR23_MA_MASK) << LPDDR23_MA_SHIFT |
 (sdram_params->phy_timing.mr[1] &
@@ -244,7 +243,7 @@ static u32 data_training(struct chan_info *chan)
DQS_SQU_CAL_SEL_CS0);
setbits_le32(_phy->ddrphy_reg[2], DQS_SQU_CAL_START);
 
-   rockchip_udelay(30);
+   udelay(30);
ret = readl(_phy->ddrphy_reg[0xff]);
 
clrbits_le32(_phy->ddrphy_reg[2],
@@ -368,9 +367,9 @@ static void phy_softreset(struct dram_info *dram)
 
writel(GRF_DDRPHY_BUFFEREN_CORE_EN, >soc_con[0]);
clrbits_le32(_phy->ddrphy_reg[0], 0x3 << 2);
-   rockchip_udelay(1);
+   udelay(1);
setbits_le32(_phy->ddrphy_reg[0], 1 << 2);
-   rockchip_udelay(5);
+   udelay(5);
setbits_le32(_phy->ddrphy_reg[0], 1 << 3);
writel(GRF_DDRPHY_BUFFEREN_CORE_DIS, >soc_con[0]);
 }
-- 
1.9.1

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