Re: [U-Boot] [PATCH 1/2] Makefile: Use -fno-strict-aliasing globally
Hi Tom, On Mon, Sep 17, 2018 at 1:30 PM Bin Meng wrote: > > The -fstrict-aliasing option is implicitly enabled at levels -O2, > -O3, -Os by GCC. This option allows the compiler to assume the > strictest aliasing rules applicable to the language being compiled. > For example, the practice of reading from a different union member > than the one most recently written to (called "type-punning") is > common. In this case, "type-punning" only works if the memory is > accessed through the union type, but might not work by taking the > address, casting the resulting pointer and dereferencing the result, > which is an undefined behavior per the "strict aliasing rules". > > GCC's -Wstrict-aliasing (included in -Wall) option does not catch > all cases, but does attempt to catch the more common pitfalls. So > there are cases that GCC does not report but the codes are violating > the "strict aliasing rules". > > Given lots of codes that may be written to rely on "type-punning", > and Linux kernel disables it by -fno-strict-aliasing globally, since > U-Boot currently does this on nds32/riscv/x86 builds only, extend > this for all architecture builds. > > Signed-off-by: Bin Meng > Reviewed-by: Tom Rini > Reviewed-by: Simon Glass > --- > > Makefile | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > When will this series be applied? Another risc-v series has conflicts in [PATCH 2/2] and if this is applied in mainline, I can respin my risc-v series on top of this to save some time for Rick's handle it himself. Regards, Bin ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [RESEND PATCH v2 15/15] riscv: Move do_reset() to a common place
> From: Bin Meng [mailto:bmeng...@gmail.com]
> Sent: Tuesday, September 11, 2018 12:55 PM
> To: Rick Jian-Zhi Chen(陳建志); U-Boot Mailing List
> Cc: Lukas Auer
> Subject: [RESEND PATCH v2 15/15] riscv: Move do_reset() to a common place
>
> We don't have a reset method on any RISC-V board yet. Instead of adding the
> same 'unsupported' message for each CPU variant it might make more sense to
> add a generic do_reset function for all CPU variants to lib/,
similar to the one for
> ARM (arch/arm/lib/reset.c).
>
> Suggested-by: Lukas Auer
> Signed-off-by: Bin Meng
>
> ---
>
> Changes in v2:
> - new patch to move do_reset() to a common place
>
> arch/riscv/cpu/ax25/cpu.c | 9 -
arch/riscv/cpu/qemu/cpu.c | 8
> arch/riscv/lib/Makefile | 1 +
> arch/riscv/lib/reset.c| 14 ++
> 4 files changed, 15 insertions(+), 17 deletions(-) create mode 100644
> arch/riscv/lib/reset.c
>
> diff --git a/arch/riscv/cpu/ax25/cpu.c b/arch/riscv/cpu/ax25/cpu.c index
> ab05b57..fddcc15 100644
> --- a/arch/riscv/cpu/ax25/cpu.c
> +++ b/arch/riscv/cpu/ax25/cpu.c
> @@ -6,9 +6,6 @@
>
> /* CPU specific code */
> #include
> -#include
> -#include
> -#include
>
> /*
> * cleanup_before_linux() is called just before we call linux @@ -24,9 +21,3
> @@ int cleanup_before_linux(void)
>
> return 0;
> }
> -
> -int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{
> - disable_interrupts();
> - panic("ax25-ae350 wdt not support yet.\n");
> -}
> diff --git a/arch/riscv/cpu/qemu/cpu.c b/arch/riscv/cpu/qemu/cpu.c index
> a064639..6c7a327 100644
> --- a/arch/riscv/cpu/qemu/cpu.c
> +++ b/arch/riscv/cpu/qemu/cpu.c
> @@ -4,7 +4,6 @@
> */
>
> #include
> -#include
>
> /*
> * cleanup_before_linux() is called just before we call linux @@
-20,10 +19,3
> @@ int cleanup_before_linux(void)
>
> return 0;
> }
> -
> -int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{
> - printf("reset unsupported yet\n");
> -
> - return 0;
> -}
> diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile index
> cc562f9..b58db89 100644
> --- a/arch/riscv/lib/Makefile
> +++ b/arch/riscv/lib/Makefile
> @@ -10,6 +10,7 @@ obj-$(CONFIG_CMD_BOOTM) += bootm.o
> obj-$(CONFIG_CMD_GO) += boot.o
> obj-y+= cache.o
> obj-y+= interrupts.o
> +obj-y+= reset.o
> obj-y += setjmp.o
>
> # For building EFI apps
> diff --git a/arch/riscv/lib/reset.c b/arch/riscv/lib/reset.c new
file mode 100644
> index 000..5d9b99c
> --- /dev/null
> +++ b/arch/riscv/lib/reset.c
> @@ -0,0 +1,14 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (C) 2018, Bin Meng */
> +
> +#include
> +#include
> +
> +int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
> +{
> + printf("reset unsupported yet\n");
> +
> + return 0;
> +}
Reviewed-by: Rick Chen
> --
> 2.7.4
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Re: [U-Boot] [RESEND PATCH v2 00/15] riscv: Add QEMU virt board support
Hi Rick, On Thu, Sep 20, 2018 at 11:00 AM Rick Chen wrote: > > > Hi Rick, > > > > On Tue, Sep 11, 2018 at 12:50 PM Bin Meng wrote: > > > > > > This series adds QEMU RISC-V 'virt' board target support, with the > > > hope of helping people easily test U-Boot on RISC-V. > > > > > > Some existing RISC-V codes have been changed to make it easily to > > > support new targets. Some spotted coding style issues are fixed. > > > > > > This series is available at u-boot-x86/riscv-working for testing. > > > > > > Resend v2 to rebase on top of v2018.09 release with Tom's tree on > > > github, as the git.denx.de is still out of sync ... > > > > > > Changes in v2: > > > - Change Linux kernel entry parameters' type to support 32/64 bit > > > - new patch to remove CSR read/write defines in encoding.h > > > - new patch to pass mhartid CSR value to kernel > > > - new patch to move do_reset() to a common place > > > > Any comments for the v2? > > Hi Bin > > Sorry for late response! > > I have reviewed the v2 patch sets, it looks fine. > And also verify the riscv-linux booting feature on ax25-ae350 board > via bootm command. > The verification is OK. :) Thank you. I will prepare and resend a v3 with all these tags added from you and Lukas, and hopefully the v3 can be applied without any problem. Regards, Bin ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [RESEND PATCH v2 10/15] riscv: bootm: Pass mhartid CSR value to kernel
> From: Bin Meng [mailto:bmeng...@gmail.com]
> Sent: Tuesday, September 11, 2018 12:55 PM
> To: Rick Jian-Zhi Chen(陳建志); U-Boot Mailing List
> Cc: Lukas Auer
> Subject: [RESEND PATCH v2 10/15] riscv: bootm: Pass mhartid CSR
value to kernel
>
> So far this is hardcoded to zero, and we should read the value from
mhartid CSR
> and pass it to Linux kernel.
>
> Suggested-by: Lukas Auer
> Signed-off-by: Bin Meng
>
> ---
>
> Changes in v2:
> - new patch to pass mhartid CSR value to kernel
>
> arch/riscv/lib/bootm.c | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
>
> > diff --git a/arch/riscv/lib/bootm.c b/arch/riscv/lib/bootm.c index
> 6893108..a7a9fb9 100644
> --- a/arch/riscv/lib/bootm.c
> +++ b/arch/riscv/lib/bootm.c
> @@ -11,6 +11,7 @@
> #include
> #include
> #include
> +#include
>
> DECLARE_GLOBAL_DATA_PTR;
>
> @@ -57,9 +58,9 @@ int do_bootm_linux(int flag, int argc, char *argv[],
> bootm_headers_t *images)
> printf("\nStarting kernel ...\n\n");
>
> cleanup_before_linux();
> - /* TODO: hardcode the hart id to zero for now */
> +
> if (IMAGE_ENABLE_OF_LIBFDT && images->ft_len)
> - kernel(0, images->ft_addr);
> + kernel(csr_read(mhartid), images->ft_addr);
>
> /* does not return */
>
Reviewed-by: Rick Chen
> > --
> 2.7.4
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Re: [U-Boot] [RESEND PATCH v2 09/15] riscv: Remove CSR read/write defines in encoding.h
> From: Bin Meng [mailto:bmeng...@gmail.com]
> Sent: Tuesday, September 11, 2018 12:55 PM
> To: Rick Jian-Zhi Chen(陳建志); U-Boot Mailing List
> Cc: Lukas Auer
> Subject: [RESEND PATCH v2 09/15] riscv: Remove CSR read/write defines in
> encoding.h
>
> There is no reason to keep two versions of CSR read/write defines
in encoding.h.
> We already have one set of defines in csr.h, which is from Linux
kernel, and let's
> drop the one in encoding.h.
>
> Signed-off-by: Bin Meng
>
> ---
>
> Changes in v2:
> - new patch to remove CSR read/write defines in encoding.h
>
> arch/riscv/include/asm/encoding.h | 50
---
> 1 file changed, 4 insertions(+), 46 deletions(-)
>
> diff --git a/arch/riscv/include/asm/encoding.h
> b/arch/riscv/include/asm/encoding.h
> index f237a72..9ea50ce 100644
> --- a/arch/riscv/include/asm/encoding.h
> +++ b/arch/riscv/include/asm/encoding.h
> @@ -128,6 +128,7 @@
> ((SUPERVISOR) ? PTE_SR(PTE) : PTE_UR(PTE)))
>
> #ifdef __riscv
> +
> #ifdef CONFIG_64BIT
> # define MSTATUS_SD MSTATUS64_SD
> # define SSTATUS_SD SSTATUS64_SD
> @@ -141,53 +142,10 @@
> # define MCAUSE_INT MCAUSE32_INT
> # define MCAUSE_CAUSE MCAUSE32_CAUSE
> #endif
> +
> #define RISCV_PGSHIFT 12
> #define RISCV_PGSIZE BIT(RISCV_PGSHIFT)
>
> -#ifndef __ASSEMBLER__
> -
> -#ifdef __GNUC__
> -
> -#define read_csr(reg) ({ unsigned long __tmp; \
> - asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \
> - __tmp; })
> -
> -#define write_csr(reg, _val) ({ \
> -typeof(_val) (val) = (_val); \
> -if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \
> - asm volatile ("csrw " #reg ", %0" :: "i"(val)); \
> -else \
> - asm volatile ("csrw " #reg ", %0" :: "r"(val)); })
> -
> -#define swap_csr(reg, _val) ({ unsigned long __tmp; \
> -typeof(_val) (val) = (_val); \
> -if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \
> - asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "i"(val)); \
> -else \
> - asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "r"(val)); \
> - __tmp; })
> -
> -#define set_csr(reg, _bit) ({ unsigned long __tmp; \
> -typeof(_bit) (bit) = (_bit); \
> -if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \
> - asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \
> -else \
> - asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \
> - __tmp; })
> -
> -#define clear_csr(reg, _bit) ({ unsigned long __tmp; \
> -typeof(_bit) (bit) = (_bit); \
> -if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \
> - asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \
> -else \
> - asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \
> - __tmp; })
> -
> -#define rdtime() read_csr(time)
> -#define rdcycle() read_csr(cycle)
> -#define rdinstret() read_csr(instret)
> +#endif /* __riscv */
>
> -#endif
> -#endif
> -#endif
> -#endif
> +#endif /* RISCV_CSR_ENCODING_H */
Reviewed-by: Rick Chen
> --
> 2.7.4
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Re: [U-Boot] [RESEND PATCH v2 03/15] riscv: bootm: Correct the 1st kernel argument to hart id
> From: Bin Meng [mailto:bmeng...@gmail.com]
> Sent: Tuesday, September 11, 2018 12:55 PM
> To: Rick Jian-Zhi Chen(陳建志); U-Boot Mailing List
> Cc: Lukas Auer
> Subject: [RESEND PATCH v2 03/15] riscv: bootm: Correct the 1st
kernel argument
> to hart id
>
> The first argument of Linux kernel is the risc-v core hart id, from
which the kernel
> is booted from. It is not the mach_id, which seems to be copied from arm.
>
> While we are here, this also changes the Linux kernel entry
parameters' type to
> support both 32-bit and 64-bit.
>
> Note the hart id is hardcoded to zero for now, and we should change
to fill in it
> with the value read from mhartid CSR of the hart which this routine
is currently
> running on.
>
> Signed-off-by: Bin Meng
>
> ---
>
> Changes in v2:
> - Change Linux kernel entry parameters' type to support 32/64 bit
>
> arch/riscv/lib/bootm.c | 18 +-
> 1 file changed, 5 insertions(+), 13 deletions(-)
>
> diff --git a/arch/riscv/lib/bootm.c b/arch/riscv/lib/bootm.c index
> 6662aff..6893108 100644
> --- a/arch/riscv/lib/bootm.c
> +++ b/arch/riscv/lib/bootm.c
> @@ -25,10 +25,7 @@ int arch_fixup_fdt(void *blob)
>
> int do_bootm_linux(int flag, int argc, char *argv[],
bootm_headers_t *images)
> {
> - bd_t*bd = gd->bd;
> - char*s;
> - int machid = bd->bi_arch_number;
> - void(*theKernel)(int arch, uint params);
> + void(*kernel)(ulong hart, void *dtb);
>
> /*
>* allow the PREP bootm subcommand, it is required for bootm to work
> @@ -39,18 +36,12 @@ int do_bootm_linux(int flag, int argc, char *argv[],
> bootm_headers_t *images)
> if ((flag != 0) && (flag != BOOTM_STATE_OS_GO))
> return 1;
>
> - theKernel = (void (*)(int, uint))images->ep;
> -
> - s = env_get("machid");
> - if (s) {
> - machid = simple_strtoul(s, NULL, 16);
> - printf("Using machid 0x%x from environment\n", machid);
> - }
> + kernel = (void (*)(ulong, void *))images->ep;
>
> bootstage_mark(BOOTSTAGE_ID_RUN_OS);
>
> debug("## Transferring control to Linux (at address %08lx) ...\n",
> -(ulong)theKernel);
> +(ulong)kernel);
>
> if (IMAGE_ENABLE_OF_LIBFDT && images->ft_len) { #ifdef
> CONFIG_OF_LIBFDT @@ -66,8 +57,9 @@ int do_bootm_linux(int flag, int argc,
> char *argv[], bootm_headers_t *images)
> printf("\nStarting kernel ...\n\n");
>
> cleanup_before_linux();
> + /* TODO: hardcode the hart id to zero for now */
> if (IMAGE_ENABLE_OF_LIBFDT && images->ft_len)
> - theKernel(machid, (unsigned long)images->ft_addr);
> + kernel(0, images->ft_addr);
>
> /* does not return */
>
Reviewed-by: Rick Chen
> --
> 2.7.4
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Re: [U-Boot] [RESEND PATCH v2 01/15] riscv: kconfig: Normalize architecture name spelling
> From: Bin Meng [mailto:bmeng...@gmail.com] > Sent: Tuesday, September 11, 2018 12:55 PM > To: Rick Jian-Zhi Chen(陳建志); U-Boot Mailing List > Cc: Lukas Auer > Subject: [RESEND PATCH v2 01/15] riscv: kconfig: Normalize architecture name > spelling > > It's RISC-V that is the official name, not RISCV. > > Signed-off-by: Bin Meng > --- > > Changes in v2: None > > arch/Kconfig | 2 +- > arch/riscv/Kconfig | 6 +++--- > 2 files changed, 4 insertions(+), 4 deletions(-) > > diff --git a/arch/Kconfig b/arch/Kconfig index bf1b4a9..42c23b5 100644 > --- a/arch/Kconfig > +++ b/arch/Kconfig > @@ -60,7 +60,7 @@ config PPC > select SYS_BOOT_GET_KBD > > config RISCV > - bool "riscv architecture" > + bool "RISC-V architecture" > select SUPPORT_OF_CONTROL > > config SANDBOX > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 20a43d8..49f87de > 100644 > --- a/arch/riscv/Kconfig > +++ b/arch/riscv/Kconfig > @@ -1,4 +1,4 @@ > -menu "RISCV architecture" > +menu "RISC-V architecture" > depends on RISCV > > config SYS_ARCH > @@ -20,13 +20,13 @@ choice > default CPU_RISCV_32 > > config CPU_RISCV_32 > - bool "RISCV 32 bit" > + bool "RISC-V 32-bit" > select 32BIT > help > Choose this option to build an U-Boot for RISCV32 architecture. > > config CPU_RISCV_64 > - bool "RISCV 64 bit" > + bool "RISC-V 64-bit" > select 64BIT > help > Choose this option to build an U-Boot for RISCV64 architecture. > -- > 2.7.4 Reviewed-by: Rick Chen ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [RESEND PATCH v2 00/15] riscv: Add QEMU virt board support
> Hi Rick, > > On Tue, Sep 11, 2018 at 12:50 PM Bin Meng wrote: > > > > This series adds QEMU RISC-V 'virt' board target support, with the > > hope of helping people easily test U-Boot on RISC-V. > > > > Some existing RISC-V codes have been changed to make it easily to > > support new targets. Some spotted coding style issues are fixed. > > > > This series is available at u-boot-x86/riscv-working for testing. > > > > Resend v2 to rebase on top of v2018.09 release with Tom's tree on > > github, as the git.denx.de is still out of sync ... > > > > Changes in v2: > > - Change Linux kernel entry parameters' type to support 32/64 bit > > - new patch to remove CSR read/write defines in encoding.h > > - new patch to pass mhartid CSR value to kernel > > - new patch to move do_reset() to a common place > > Any comments for the v2? Hi Bin Sorry for late response! I have reviewed the v2 patch sets, it looks fine. And also verify the riscv-linux booting feature on ax25-ae350 board via bootm command. The verification is OK. :) B.R Rick > > Regards, > Bin ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH V3 2/2] pci: Update documentation to make 'compatible' string optional
Hi Marek, On Wed, Sep 19, 2018 at 9:29 PM Marek Vasut wrote: > > On 09/18/2018 04:02 PM, Simon Glass wrote: > > Hi Marek, > > Hi, > > > On 18 September 2018 at 05:47, Marek Vasut wrote: > >> > >> On 09/14/2018 06:41 AM, Simon Glass wrote: > >>> Hi Marex, > >> > >> It's Marek btw ... > >> > >>> On 11 September 2018 at 14:58, Marek Vasut wrote: > Reword the documentation to make it clear the compatible string is now > optional, yet still matching on it takes precedence over PCI IDs and > PCI classes. > > Signed-off-by: Marek Vasut > Cc: Simon Glass > Cc: Tom Rini > --- > V3: No change > V2: New patch > --- > doc/driver-model/pci-info.txt | 14 +- > 1 file changed, 9 insertions(+), 5 deletions(-) > > diff --git a/doc/driver-model/pci-info.txt > b/doc/driver-model/pci-info.txt > index e1701d1fbc..14364c5c75 100644 > --- a/doc/driver-model/pci-info.txt > +++ b/doc/driver-model/pci-info.txt > @@ -34,11 +34,15 @@ under that bus. > Note that this is all done on a lazy basis, as needed, so until > something is > touched on PCI (eg: a call to pci_find_devices()) it will not be probed. > > -PCI devices can appear in the flattened device tree. If they do this > serves to > -specify the driver to use for the device. In this case they will be > bound at > -first. Each PCI device node must have a compatible string list as well > as a > - property, as defined by the IEEE Std 1275-1994 PCI bus binding > document > -v2.1. Note we must describe PCI devices with the same bus hierarchy as > the > +PCI devices can appear in the flattened device tree. If they do, their > node > +often contains extra information which cannot be derived from the PCI > IDs or > +PCI class of the device. Each PCI device node must have a > property, as > +defined by the IEEE Std 1275-1994 PCI bus binding document v2.1. > Compatible > +string list is optional and generally not needed, since PCI is > discoverable > >>> > >>> I really don't like 'generally not needed'. How about 'generally not > >>> essential'? Or that you can usually avoid it if desired. > >> > >> Must be a language nuance, but the compatible string is really not > >> needed. I am starting to understand where this mindset of "compat > >> strings are generally needed" comes from, which is the design of the > >> virtual PCI devices in sandbox, but that's not the usual case. > > > > Well it's more than that, as I mentioned before. Finding a compatible > > string in the source code is easier, and if we are matching with a DT > > node anyway, makes more sense IMO. > > It's about as easy as finding PCI ID. > > And PCI is a discoverable bus, so using a compatible string is some > obscure edge-case. > > > Anyway since DTs likely come from > > the newly pleasant Linux we'll just end up with what they have there. > > This mostly applies for things like x86 which don't use DT in Linux. > > > >> > >>> I'd like to say that it is optional since U_BOOT_PCI_DEVICE() can be > >>> used to specific the driver based on conditions like the PCI vendor/, > >>> PCI class, etc. If U-Boot does not find a compatible string then it > >>> will search these U_BOOT_PCI_DEVICE() records to find a driver; > >>> assuming it finds one it will then search for the device-tree node > >>> whose reg property matches the bus/device/function of the device, and > >>> attached that node to the device so that it is accessible to the > >>> driver. > >> > >> Can you rephrase it better then ? I can paste it into the docs. > > > > How about: > > > > The compatible string is optional since U_BOOT_PCI_DEVICE() can be > > used to specific > > specify ? > > > the driver based on conditions like the PCI vendor/ > > PCI class, etc. If U-Boot does not find a compatible string then it > > will search these U_BOOT_PCI_DEVICE() records to find a driver; > > This implies the compatible string is preferred, it is not. > I think Simon was describing the *current* U-Boot implementation, that "compatible" string is looked up first, then U_BOOT_PCI_DEVICE(). > > assuming it finds one it will then search for the device-tree node > > whose reg property matches the bus/device/function of the device, and > > attache that node to the device so that it is accessible to the > > driver. Regards, Bin ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH V2 1/2] pci: Support parsing PCI controller DT subnodes
Hi Marek, On Wed, Sep 19, 2018 at 9:28 PM Marek Vasut wrote: > > On 09/19/2018 11:41 AM, Bin Meng wrote: > > Hi Marek, > > > > On Wed, Sep 19, 2018 at 5:34 PM Marek Vasut wrote: > >> > >> On 09/19/2018 11:26 AM, Bin Meng wrote: > >>> Hi Marek, > >>> > >>> On Wed, Sep 19, 2018 at 4:21 PM Marek Vasut wrote: > > On 09/18/2018 03:52 PM, Simon Glass wrote: > > Hi Marek, > > > > On 18 September 2018 at 13:36, Marek Vasut > > wrote: > >> > >> On 09/14/2018 06:41 AM, Simon Glass wrote: > >>> Hi Marek, > >>> > >>> On 10 September 2018 at 01:38, Marek Vasut > >>> wrote: > > On 09/02/2018 03:07 AM, Simon Glass wrote: > > Hi Marek, > > Hi, > > > On 1 September 2018 at 16:45, Marek Vasut > > wrote: > >> > >> On 09/01/2018 11:50 PM, Simon Glass wrote: > >>> Hi Marek, > >>> > >>> On 30 August 2018 at 07:42, Marek Vasut > >>> wrote: > On 08/30/2018 03:32 PM, Bin Meng wrote: > > Hi Marek, > > > > On Thu, Aug 30, 2018 at 1:07 AM Marek Vasut > > wrote: > >> > >> On 08/29/2018 05:15 PM, Bin Meng wrote: > >>> +Simon > >>> > >>> Hi Marek, > >>> > >>> On Wed, Aug 29, 2018 at 10:22 PM Marek Vasut > >>> wrote: > > On 08/24/2018 08:27 PM, Marek Vasut wrote: > > The PCI controller can have DT subnodes describing extra > > properties > > of particular PCI devices, ie. a PHY attached to an EHCI > > controller > > on a PCI bus. This patch parses those DT subnodes and > > assigns a node > > to the PCI device instance, so that the driver can extract > > details > > from that node and ie. configure the PHY using the PHY > > subsystem. > > > > Signed-off-by: Marek Vasut > > Cc: Simon Glass > > Cc: Tom Rini > > Well, bump ? > > This is the only missing patch to get my hardware working > properly. > >>> > >>> I don't think we ever had an agreement on the v1 patch. Simon > >>> had a > >>> long email that pointed out what Linux does seems like a > >>> 'fallback' to > >>> find a node with no compatible string. > >>> > >>> Back to this, if we have to go with this way, please create a > >>> test > >>> case to cover this scenario. > >> > >> The fact that it works on a particular board is not tested > >> enough? > >> Do we need a custom, special, synthetic test ? > >> > > > > I believe that's always been the requirement against the DM code > > changes. I was requested in the past when I changed something > > in the > > DM and I see other people were asked to do so. Like Alex said, > > it does > > not mean this patch was not tested enough, but to ensure future > > commits won't break this. > > So, do you have any suggestion how to implement this test ? It > seems > Alex posed the same question. It doesn't seem to be trivial in > the > context of sandbox. > >>> > >>> I suppose you need a PCI_DEVICE() declaration for sandbox, with an > >>> associated DT node and no compatible string. Then check that you > >>> can > >>> locate the device and that it read a DT property correctly. > >> > >> Is there any example of this stuff already ? > > > > See the bottom of swap_case.c. You might be able to add a new one > > of those, > > > > If you look at pci-controller2 in test.dts it has a device with a > > compatible string. You could try adding a second device with no > > compatible string. > > And how does that test anything ? > >>> > >>> You can test that your code actually attaches the DT node to the > >>> probed device. Without you code the test would fail. Wit it, it would > >>> pass. > >> > >> Well it won't, because the sandbox swap_case.c requires the compatible. > >> This all seems like a big hack to support virtual PCI devices. > >> > >> The driver binds with a compatible and then pins the read/write config > >> reg accessors to emulate their return values. Those include PCI IDs. So > >> you cannot instantiate virtual PCI device without this
Re: [U-Boot] Please pull u-boot-dm
On Tue, Sep 18, 2018 at 06:13:24PM -0600, Simon Glass wrote: > Hi Tom, > > I was unable to get signed tags working, but here is a list of changes: I assume you read the link from before, can you talk about the issues a bit more? Thanks! > - MPC83xx device tree additions (CPU and RAM) > - Fix sandbox build error > - Sync bitrev with Linux > - Various ofnode/DT improvements > > > The following changes since commit 40e44c8bf516e7071c9b80113473be5757e8c3f3: > > Merge branch 'master' of git://git.denx.de/u-boot-coldfire (2018-09-16 > 10:32:33 -0400) > > are available in the Git repository at: > > git://git.denx.de/u-boot-dm.git > > for you to fetch changes up to 75629a25087cd9897305375421abe2248bc40e72: > > dm: uclass: Adding missing child_pre_probe description (2018-09-18 > 13:27:10 -0600) Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 4/4] rockchip: rk3399: Add Ficus EE board support
Add board support for Ficus EE board from Vamrs. This board utilizes
common Rock960 family support.
Following peripherals are tested and known to work:
* Gigabit Ethernet
* USB 2.0
* MMC
Signed-off-by: Ezequiel Garcia
[Reworked based on common Rock960 family support]
Signed-off-by: Manivannan Sadhasivam
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/rk3399-ficus.dts | 78 ++
configs/ficus-rk3399_defconfig | 71 +++
3 files changed, 150 insertions(+)
create mode 100644 arch/arm/dts/rk3399-ficus.dts
create mode 100644 configs/ficus-rk3399_defconfig
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 9b891826b73..e2bd9822aa2 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -42,6 +42,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
rk3288-veyron-minnie.dtb \
rk3288-vyasa.dtb \
rk3328-evb.dtb \
+ rk3399-ficus.dtb \
rk3368-lion.dtb \
rk3368-sheep.dtb \
rk3368-geekbox.dtb \
diff --git a/arch/arm/dts/rk3399-ficus.dts b/arch/arm/dts/rk3399-ficus.dts
new file mode 100644
index 000..de934cd61ab
--- /dev/null
+++ b/arch/arm/dts/rk3399-ficus.dts
@@ -0,0 +1,78 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 Collabora Ltd.
+ * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd.
+ *
+ * Schematics available at https://dl.vamrs.com/products/ficus/docs/hw
+ */
+
+/dts-v1/;
+#include "rk3399-rock960.dtsi"
+#include "rk3399-sdram-lpddr3-4GB-1600.dtsi"
+
+/ {
+ model = "96boards RK3399 Ficus";
+ compatible = "vamrs,ficus", "rockchip,rk3399";
+
+ chosen {
+ stdout-path = "serial2:150n8";
+ };
+
+ clkin_gmac: external-gmac-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <12500>;
+ clock-output-names = "clkin_gmac";
+ #clock-cells = <0>;
+ };
+};
+
+ {
+ assigned-clocks = < SCLK_RMII_SRC>;
+ assigned-clock-parents = <_gmac>;
+ clock_in_out = "input";
+ phy-supply = <_sys>;
+ phy-mode = "rgmii";
+ pinctrl-names = "default";
+ pinctrl-0 = <_pins>;
+ snps,reset-gpio = < RK_PB7 GPIO_ACTIVE_LOW>;
+ snps,reset-active-low;
+ snps,reset-delays-us = <0 1 5>;
+ tx_delay = <0x28>;
+ rx_delay = <0x11>;
+ status = "okay";
+};
+
+ {
+ ep-gpios = < RK_PD4 GPIO_ACTIVE_HIGH>;
+};
+
+ {
+ gmac {
+ rgmii_sleep_pins: rgmii-sleep-pins {
+ rockchip,pins =
+ <3 15 RK_FUNC_GPIO _output_low>;
+ };
+ };
+
+ pcie {
+ pcie_drv: pcie-drv {
+ rockchip,pins =
+ <1 24 RK_FUNC_GPIO _pull_none>;
+ };
+ };
+
+ usb2 {
+ host_vbus_drv: host-vbus-drv {
+ rockchip,pins =
+ <4 27 RK_FUNC_GPIO _pull_none>;
+ };
+ };
+};
+
+_pcie {
+ gpio = < 24 GPIO_ACTIVE_HIGH>;
+};
+
+_host {
+ gpio = < 27 GPIO_ACTIVE_HIGH>;
+};
diff --git a/configs/ficus-rk3399_defconfig b/configs/ficus-rk3399_defconfig
new file mode 100644
index 000..e890bc25238
--- /dev/null
+++ b/configs/ficus-rk3399_defconfig
@@ -0,0 +1,71 @@
+CONFIG_ARM=y
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SYS_TEXT_BASE=0x0020
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x4000
+CONFIG_ROCKCHIP_RK3399=y
+CONFIG_TARGET_ROCK960_RK3399=y
+CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x4000
+CONFIG_DEBUG_UART_BASE=0xFF1A
+CONFIG_DEBUG_UART_CLOCK=2400
+CONFIG_SPL_STACK_R_ADDR=0x8
+CONFIG_DEFAULT_DEVICE_TREE="rk3399-ficus"
+CONFIG_DEBUG_UART=y
+CONFIG_FIT=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.py"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000
+CONFIG_SPL_ATF=y
+CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_TIME=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names
interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_REGMAP=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_SPL_SYSCON=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_RGMII=y
+CONFIG_GMAC_ROCKCHIP=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_ROCKCHIP_RK3399=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_RK8XX=y
+CONFIG_REGULATOR_PWM=y
+CONFIG_DM_REGULATOR_FIXED=y
[U-Boot] [PATCH 2/4] rockchip: rk3399: Add common Rock960 family from Vamrs
Rock960 is a family of boards based on Rockchip RK3399 SoC from Vamrs.
It consists of Rock960 (Consumer Edition) and Ficus (Enterprise Edition)
96Boards.
Below are some of the key differences between both Rock960 and Ficus
boards:
1. Different host enable GPIO for USB
2. Different power and reset GPIO for PCI-E
3. No Ethernet port on Rock960
The common board support will be utilized by both boards. The device
tree has been organized in such a way that only the properties which
differ between both boards are placed in the board specific dts and
the reset of the nodes are placed in common dtsi file.
Signed-off-by: Manivannan Sadhasivam
[Added instructions for SD card boot]
Signed-off-by: Ezequiel Garcia
---
arch/arm/dts/rk3399-rock960.dtsi| 506
arch/arm/mach-rockchip/rk3399/Kconfig | 26 +
board/vamrs/rock960_rk3399/Kconfig | 15 +
board/vamrs/rock960_rk3399/MAINTAINERS | 6 +
board/vamrs/rock960_rk3399/Makefile | 6 +
board/vamrs/rock960_rk3399/README | 151 ++
board/vamrs/rock960_rk3399/rock960-rk3399.c | 50 ++
include/configs/rock960_rk3399.h| 15 +
8 files changed, 775 insertions(+)
create mode 100644 arch/arm/dts/rk3399-rock960.dtsi
create mode 100644 board/vamrs/rock960_rk3399/Kconfig
create mode 100644 board/vamrs/rock960_rk3399/MAINTAINERS
create mode 100644 board/vamrs/rock960_rk3399/Makefile
create mode 100644 board/vamrs/rock960_rk3399/README
create mode 100644 board/vamrs/rock960_rk3399/rock960-rk3399.c
create mode 100644 include/configs/rock960_rk3399.h
diff --git a/arch/arm/dts/rk3399-rock960.dtsi b/arch/arm/dts/rk3399-rock960.dtsi
new file mode 100644
index 000..51644d6d02d
--- /dev/null
+++ b/arch/arm/dts/rk3399-rock960.dtsi
@@ -0,0 +1,506 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2018 Linaro Ltd.
+ */
+
+#include
+#include
+#include "rk3399.dtsi"
+
+/ {
+ vcc1v8_s0: vcc1v8-s0 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc1v8_s0";
+ regulator-min-microvolt = <180>;
+ regulator-max-microvolt = <180>;
+ regulator-always-on;
+ };
+
+ vcc_sys: vcc-sys {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_sys";
+ regulator-min-microvolt = <500>;
+ regulator-max-microvolt = <500>;
+ regulator-always-on;
+ };
+
+ vcc3v3_sys: vcc3v3-sys {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_sys";
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ regulator-always-on;
+ vin-supply = <_sys>;
+ };
+
+ vcc3v3_pcie: vcc3v3-pcie-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ pinctrl-names = "default";
+ pinctrl-0 = <_drv>;
+ regulator-boot-on;
+ regulator-name = "vcc3v3_pcie";
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ vin-supply = <_sys>;
+ };
+
+ vcc5v0_host: vcc5v0-host-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ pinctrl-names = "default";
+ pinctrl-0 = <_vbus_drv>;
+ regulator-name = "vcc5v0_host";
+ regulator-min-microvolt = <500>;
+ regulator-max-microvolt = <500>;
+ regulator-always-on;
+ vin-supply = <_sys>;
+ };
+
+ vdd_log: vdd-log {
+ compatible = "pwm-regulator";
+ pwms = < 0 25000 0>;
+ regulator-name = "vdd_log";
+ regulator-min-microvolt = <80>;
+ regulator-max-microvolt = <140>;
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <_sys>;
+ };
+
+};
+
+_l0 {
+ cpu-supply = <_cpu_l>;
+};
+
+_l1 {
+ cpu-supply = <_cpu_l>;
+};
+
+_l2 {
+ cpu-supply = <_cpu_l>;
+};
+
+_l3 {
+ cpu-supply = <_cpu_l>;
+};
+
+_b0 {
+ cpu-supply = <_cpu_b>;
+};
+
+_b1 {
+ cpu-supply = <_cpu_b>;
+};
+
+_phy {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
+
+ {
+ clock-frequency = <40>;
+ i2c-scl-rising-time-ns = <168>;
+ i2c-scl-falling-time-ns = <4>;
+ status = "okay";
+
+ vdd_cpu_b: regulator@40 {
+ compatible = "silergy,syr827";
+ reg = <0x40>;
+ fcs,suspend-voltage-selector = <1>;
+ regulator-name = "vdd_cpu_b";
+ regulator-min-microvolt = <712500>;
+ regulator-max-microvolt = <150>;
+ regulator-ramp-delay = <1000>;
+ regulator-always-on;
+
[U-Boot] [PATCH 0/4] Add Rock960 and Ficus 96Board support
This patchset adds support for Rock960 and Ficus 96Boards from Vamrs. Since both boards share most of the configurations, a common Rock960 family support is added with common support and the actual boards are based on this. The previous version of the patchseries were adding Rock960 [1] and Ficus [2] board support individually, but this series fuses them together based on the common board support as per Linux kernel. [1] https://patchwork.ozlabs.org/cover/963239/ [2] https://lists.denx.de/pipermail/u-boot/2018-August/339059.html This patchseries has been tested on Rock960 v1.2 board and expecting Ezequiel to do the testing for Ficus. PS: I have explicitly removed the previous Ack's for the Ficus board since there has been a heavy modification done on these patches. Thanks, Mani Manivannan Sadhasivam (4): arm: dts: rockchip: add some common pin-settings to rk3399 rockchip: rk3399: Add common Rock960 family from Vamrs rockchip: rk3399: Add Rock960 CE board support rockchip: rk3399: Add Ficus EE board support arch/arm/dts/Makefile |2 + arch/arm/dts/rk3399-ficus.dts | 78 + arch/arm/dts/rk3399-rock960.dts | 45 + arch/arm/dts/rk3399-rock960.dtsi | 506 ++ .../arm/dts/rk3399-sdram-lpddr3-2GB-1600.dtsi | 1536 + arch/arm/dts/rk3399.dtsi | 55 +- arch/arm/mach-rockchip/rk3399/Kconfig | 26 + board/vamrs/rock960_rk3399/Kconfig| 15 + board/vamrs/rock960_rk3399/MAINTAINERS|6 + board/vamrs/rock960_rk3399/Makefile |6 + board/vamrs/rock960_rk3399/README | 151 ++ board/vamrs/rock960_rk3399/rock960-rk3399.c | 50 + configs/ficus-rk3399_defconfig| 71 + configs/rock960-rk3399_defconfig | 62 + include/configs/rock960_rk3399.h | 15 + 15 files changed, 2618 insertions(+), 6 deletions(-) create mode 100644 arch/arm/dts/rk3399-ficus.dts create mode 100644 arch/arm/dts/rk3399-rock960.dts create mode 100644 arch/arm/dts/rk3399-rock960.dtsi create mode 100644 arch/arm/dts/rk3399-sdram-lpddr3-2GB-1600.dtsi create mode 100644 board/vamrs/rock960_rk3399/Kconfig create mode 100644 board/vamrs/rock960_rk3399/MAINTAINERS create mode 100644 board/vamrs/rock960_rk3399/Makefile create mode 100644 board/vamrs/rock960_rk3399/README create mode 100644 board/vamrs/rock960_rk3399/rock960-rk3399.c create mode 100644 configs/ficus-rk3399_defconfig create mode 100644 configs/rock960-rk3399_defconfig create mode 100644 include/configs/rock960_rk3399.h -- 2.17.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 1/4] arm: dts: rockchip: add some common pin-settings to rk3399
From: Randy Li
Those pins would be used by many boards.
Commit grabbed from Linux:
commit b41023282d07b61a53e2c9b9508912b1e7ce7b4f
Author: Randy Li
Date: Thu Jun 21 21:32:10 2018 +0800
arm64: dts: rockchip: add some common pin-settings to rk3399
Those pins would be used by many boards.
Signed-off-by: Randy Li
Signed-off-by: Heiko Stuebner
Acked-by: Philipp Tomsich
Signed-off-by: Randy Li
Signed-off-by: Heiko Stuebner
Signed-off-by: Ezequiel Garcia
---
arch/arm/dts/rk3399.dtsi | 55 +++-
1 file changed, 49 insertions(+), 6 deletions(-)
diff --git a/arch/arm/dts/rk3399.dtsi b/arch/arm/dts/rk3399.dtsi
index 83c257b1228..8349451b03d 100644
--- a/arch/arm/dts/rk3399.dtsi
+++ b/arch/arm/dts/rk3399.dtsi
@@ -1602,19 +1602,49 @@
drive-strength = <12>;
};
+ pcfg_pull_none_13ma: pcfg-pull-none-13ma {
+ bias-disable;
+ drive-strength = <13>;
+ };
+
+ pcfg_pull_none_18ma: pcfg-pull-none-18ma {
+ bias-disable;
+ drive-strength = <18>;
+ };
+
+ pcfg_pull_none_20ma: pcfg-pull-none-20ma {
+ bias-disable;
+ drive-strength = <20>;
+ };
+
+ pcfg_pull_up_2ma: pcfg-pull-up-2ma {
+ bias-pull-up;
+ drive-strength = <2>;
+ };
+
pcfg_pull_up_8ma: pcfg-pull-up-8ma {
bias-pull-up;
drive-strength = <8>;
};
+ pcfg_pull_up_18ma: pcfg-pull-up-18ma {
+ bias-pull-up;
+ drive-strength = <18>;
+ };
+
+ pcfg_pull_up_20ma: pcfg-pull-up-20ma {
+ bias-pull-up;
+ drive-strength = <20>;
+ };
+
pcfg_pull_down_4ma: pcfg-pull-down-4ma {
bias-pull-down;
drive-strength = <4>;
};
- pcfg_pull_up_2ma: pcfg-pull-up-2ma {
- bias-pull-up;
- drive-strength = <2>;
+ pcfg_pull_down_8ma: pcfg-pull-down-8ma {
+ bias-pull-down;
+ drive-strength = <8>;
};
pcfg_pull_down_12ma: pcfg-pull-down-12ma {
@@ -1622,9 +1652,22 @@
drive-strength = <12>;
};
- pcfg_pull_none_13ma: pcfg-pull-none-13ma {
- bias-disable;
- drive-strength = <13>;
+ pcfg_pull_down_18ma: pcfg-pull-down-18ma {
+ bias-pull-down;
+ drive-strength = <18>;
+ };
+
+ pcfg_pull_down_20ma: pcfg-pull-down-20ma {
+ bias-pull-down;
+ drive-strength = <20>;
+ };
+
+ pcfg_output_high: pcfg-output-high {
+ output-high;
+ };
+
+ pcfg_output_low: pcfg-output-low {
+ output-low;
};
clock {
--
2.17.1
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[U-Boot] [PATCH 3/4] rockchip: rk3399: Add Rock960 CE board support
Add board support for Rock960 CE board from Vamrs. This board utilizes
common Rock960 family support.
Following peripherals are tested and known to work:
* USB 2.0
* MMC
This commit also adds DDR configuration for LPDDR3-2GiB-1866MHz.
Signed-off-by: Manivannan Sadhasivam
---
arch/arm/dts/Makefile |1 +
arch/arm/dts/rk3399-rock960.dts | 45 +
.../arm/dts/rk3399-sdram-lpddr3-2GB-1600.dtsi | 1536 +
configs/rock960-rk3399_defconfig | 62 +
4 files changed, 1644 insertions(+)
create mode 100644 arch/arm/dts/rk3399-rock960.dts
create mode 100644 arch/arm/dts/rk3399-sdram-lpddr3-2GB-1600.dtsi
create mode 100644 configs/rock960-rk3399_defconfig
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index ebfa2272627..9b891826b73 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -51,6 +51,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
rk3399-puma-ddr1333.dtb \
rk3399-puma-ddr1600.dtb \
rk3399-puma-ddr1866.dtb \
+ rk3399-rock960.dtb \
rv1108-evb.dtb
dtb-$(CONFIG_ARCH_MESON) += \
meson-gxbb-nanopi-k2.dtb \
diff --git a/arch/arm/dts/rk3399-rock960.dts b/arch/arm/dts/rk3399-rock960.dts
new file mode 100644
index 000..25c58b42611
--- /dev/null
+++ b/arch/arm/dts/rk3399-rock960.dts
@@ -0,0 +1,45 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Manivannan Sadhasivam
+ */
+
+/dts-v1/;
+#include "rk3399-rock960.dtsi"
+#include "rk3399-sdram-lpddr3-2GB-1600.dtsi"
+
+/ {
+ model = "96boards Rock960";
+ compatible = "vamrs,rock960", "rockchip,rk3399";
+
+ chosen {
+ stdout-path = "serial2:150n8";
+ };
+};
+
+ {
+ ep-gpios = < RK_PA2 GPIO_ACTIVE_HIGH>;
+};
+
+ {
+ pcie {
+ pcie_drv: pcie-drv {
+ rockchip,pins =
+ <2 RK_PA5 RK_FUNC_GPIO _pull_none>;
+ };
+ };
+
+ usb2 {
+ host_vbus_drv: host-vbus-drv {
+ rockchip,pins =
+ <4 RK_PD1 RK_FUNC_GPIO _pull_none>;
+ };
+ };
+};
+
+_pcie {
+ gpio = < 5 GPIO_ACTIVE_HIGH>;
+};
+
+_host {
+ gpio = < 25 GPIO_ACTIVE_HIGH>;
+};
diff --git a/arch/arm/dts/rk3399-sdram-lpddr3-2GB-1600.dtsi
b/arch/arm/dts/rk3399-sdram-lpddr3-2GB-1600.dtsi
new file mode 100644
index 000..d14e833d228
--- /dev/null
+++ b/arch/arm/dts/rk3399-sdram-lpddr3-2GB-1600.dtsi
@@ -0,0 +1,1536 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ * (C) Copyright 2018 Manivannan Sadhasivam
+ */
+
+ {
+ rockchip,sdram-params = <
+ 0x1
+ 0xa
+ 0x3
+ 0x2
+ 0x2
+ 0x0
+ 0xf
+ 0xf
+ 1
+ 0x1d191519
+ 0x14040808
+ 0x0002
+ 0x6226
+ 0x0054
+ 0x
+ 0x1
+ 0xa
+ 0x3
+ 0x2
+ 0x2
+ 0x0
+ 0xf
+ 0xf
+ 1
+ 0x1d191519
+ 0x14040808
+ 0x0002
+ 0x6226
+ 0x0054
+ 0x
+ 800
+ 6
+ 2
+ 9
+ 1
+ 0x0700
+ 0x
+ 0x
+ 0x
+ 0x
+ 0x0050
+ 0x00027100
+ 0x0320
+ 0x1f40
+ 0x0050
+ 0x00027100
+ 0x0320
+ 0x1f40
+ 0x0050
+ 0x00027100
+ 0x0320
+ 0x01001f40
+ 0x
+ 0x0101
+ 0x00020100
+ 0x00a0
+ 0x0190
+ 0x
+ 0x0618
+ 0x00061800
+ 0x04000618
+ 0x33080004
+ 0x280f0622
+ 0x22330800
+ 0x00280f06
+ 0x06223308
+ 0x0600280f
+ 0x0a0a
+ 0x0600dac0
+ 0x0a0a060c
+ 0x0600dac0
+ 0x0a0a060c
+ 0x0600dac0
+ 0x0203000c
+ 0x0f0c0f00
+ 0x040c0f0c
+ 0x14000a0a
+ 0x03030a0a
+ 0x00010003
+ 0x031b1b1b
+ 0x0011
+ 0x
+ 0x0301
+ 0x0c2800a8
+ 0x0c2800a8
+ 0x0c2800a8
+ 0x
+ 0x00060006
+ 0x00140006
+ 0x00140014
+
Re: [U-Boot] [PATCH] nios2: 10m50: Add CPU pre-relocation in device tree
On 09/13/2017 02:19 PM, Marek Vasut wrote:
On 07/28/2017 07:07 AM, Gan, Yau Wai wrote:
Tag CPU with dm-pre-reloc to enable driver before
relocation.
Signed-off-by: Gan, Yau Wai
Cc: Thomas Chou
Reviewed-by: Marek Vasut
Tom, please apply directly as the maintainer seems N/A.
Dear all,
Sorry for being missing for a long long time. I am looking at this right
now.
Best regards,
Thomas
---
arch/nios2/dts/10m50_devboard.dts | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/nios2/dts/10m50_devboard.dts
b/arch/nios2/dts/10m50_devboard.dts
index 05eac30..461ae68 100644
--- a/arch/nios2/dts/10m50_devboard.dts
+++ b/arch/nios2/dts/10m50_devboard.dts
@@ -19,6 +19,7 @@
#size-cells = <0>;
cpu: cpu@0 {
+ u-boot,dm-pre-reloc;
device_type = "cpu";
compatible = "altr,nios2-1.1";
reg = <0x>;
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[U-Boot] [Patch V3] ARM: da850evm_direct_nor_defconfig: Enable DM_SERIAL
With DM enabled, this patch enables DM_SERIAL and removes the NS16550 initialization from da850_lowlevel since the driver will take care of that itself. Signed-off-by: Adam Ford --- V3: Make the include items referencing the serial info dependent on DM_SERIAL and not SPL or NOR since both of these options will eventually use DM_SERIAL. V2: Rebase against Master Use CONFIG_IS_ENABLED instead of defined so this can be enabled/disabled in SPL independently. Enable CONFIG_SYS_MALLOC_F to allow relocation allowing the serial to build correctly diff --git a/arch/arm/mach-davinci/da850_lowlevel.c b/arch/arm/mach-davinci/da850_lowlevel.c index 95dc93a24f..822e0dc4a1 100644 --- a/arch/arm/mach-davinci/da850_lowlevel.c +++ b/arch/arm/mach-davinci/da850_lowlevel.c @@ -288,10 +288,10 @@ int arch_cpu_init(void) /* GPIO setup */ board_gpio_init(); - +#if !CONFIG_IS_ENABLED(DM_SERIAL) NS16550_init((NS16550_t)(CONFIG_SYS_NS16550_COM1), CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE); - +#endif /* * Fix Power and Emulation Management Register * see sprufw3a.pdf page 37 Table 24 diff --git a/configs/da850evm_direct_nor_defconfig b/configs/da850evm_direct_nor_defconfig index 4039d0ee59..42cb4127fd 100644 --- a/configs/da850evm_direct_nor_defconfig +++ b/configs/da850evm_direct_nor_defconfig @@ -5,7 +5,6 @@ CONFIG_TARGET_DA850EVM=y CONFIG_DA850_LOWLEVEL=y CONFIG_TI_COMMON_CMD_OPTIONS=y CONFIG_NR_DRAM_BANKS=1 -# CONFIG_SYS_MALLOC_F is not set CONFIG_SYS_EXTRA_OPTIONS="USE_NOR,DIRECT_NOR_BOOT" CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y @@ -50,6 +49,8 @@ CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_MII=y CONFIG_DRIVER_TI_EMAC=y +CONFIG_SPECIFY_CONSOLE_INDEX=y +CONFIG_DM_SERIAL=y CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h index 14a6b9e591..319f6aadf5 100644 --- a/include/configs/da850evm.h +++ b/include/configs/da850evm.h @@ -116,7 +116,7 @@ * Serial Driver info */ -#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_DIRECT_NOR_BOOT) +#if !CONFIG_IS_ENABLED(DM_SERIAL) #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE-4 /* NS16550 register size */ #define CONFIG_SYS_NS16550_COM1DAVINCI_UART2_BASE /* Base address of UART2 */ -- 2.17.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 2/2] colibri_imx7: prime get_ram_size() using imx_ddr_size()
Hi Stefan, On Wed, Sep 19, 2018 at 12:48 PM, Stefan Agner wrote: > Hm, with that we take the MMDC register information as the upper bound, and > use regular U-Boot get_ram_size() to determine size by poking memory > addresses. Seems sensible. > > Acked-by: Stefan Agner > > Fabio, I guess other boards use SPL to use different MMDC configuration for > different memory size? Is there a downside doing this size over-provisioning? That's correct: the imx7 boards that use imx_ddr_size() are cl-som-imx7 and pico-imx7d, which uses SPL and provide different MMDC configuration depending on the memory density. I don't see a downside in doing this over-provisioning. Regards, Fabio Estevam ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 1/3] net: designware: socfpga: Add Arria10 extras
Hi Marek, On Mon, Aug 13, 2018 at 1:56 PM, Marek Vasut wrote: > Add wrapper around the designware MAC driver to handle the SoCFPGA > specific configuration bits. On Arria10, this is configuration of > syscon phy_intf. > > Signed-off-by: Marek Vasut > Cc: Chin Liang See > Cc: Dinh Nguyen > Cc: Ley Foon Tan > Cc: Joe Hershberger Looks good, but can you add something in doc/device-tree-bindings? Acked-by: Joe Hershberger > --- > NOTE: This driver is not enabled on Gen5 or Stratix10 as the > implementation for its specifics is missing thus far. > The driver can be safely enabled though, as the behavior > of the plain designware mac driver will be retained. > --- ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v1 03/13] dts: db410c: add alias for USB
> > This should go into a -u-boot.dtsi file so that the
> > dragonboard410c.dts can be synced from the linux kernel without
> > change.
> >
> Hi Peter.
> I thought that -u-boot.dtsi is only for u-boot specific stuff,
> The alias is not specific to u-boot AFAIK.
Yes, I did wonder if some of these changes should also into linux.
Peter
> I'll look how other boards handle that.
> Thanks,
> Ramon.
> > Peter
> >
> > On Wed, Sep 19, 2018 at 7:31 PM Ramon Fried wrote:
> > >
> > > Alias is required so req-seq will be filled.
> > >
> > > Signed-off-by: Ramon Fried
> > > ---
> > >
> > > arch/arm/dts/dragonboard410c.dts | 4
> > > 1 file changed, 4 insertions(+)
> > >
> > > diff --git a/arch/arm/dts/dragonboard410c.dts
> > > b/arch/arm/dts/dragonboard410c.dts
> > > index f4f7c350ec..75f28300b7 100644
> > > --- a/arch/arm/dts/dragonboard410c.dts
> > > +++ b/arch/arm/dts/dragonboard410c.dts
> > > @@ -18,6 +18,10 @@
> > > #address-cells = <0x2>;
> > > #size-cells = <0x2>;
> > >
> > > + aliases {
> > > + usb0 = "/soc/ehci@78d9000";
> > > + };
> > > +
> > > memory {
> > > device_type = "memory";
> > > reg = <0 0x8000 0 0x3da0>;
> > > --
> > > 2.18.0
> > >
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> > > U-Boot@lists.denx.de
> > > https://lists.denx.de/listinfo/u-boot
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[U-Boot] [PATCH v2 3/4] dm: core: Scan "/firmware" node by default
All Linux firmware drivers are put under "/firmware" node
and it has support to populate "/firmware" node by default.
u-boot and Linux can share same DTB. In this case, driver
probe for devices under "/firmware" will not be invoked
as "/firmware" does not have its own "compatible" property.
This patch scans "/firmware" node by default like "/clocks".
Signed-off-by: Rajan Vaja
Reviewed-by: Simon Glass
---
Changes in v2:
* None
---
drivers/core/root.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/core/root.c b/drivers/core/root.c
index 1ab4c38..47d10b8 100644
--- a/drivers/core/root.c
+++ b/drivers/core/root.c
@@ -357,8 +357,14 @@ int dm_extended_scan_fdt(const void *blob, bool
pre_reloc_only)
}
ret = dm_scan_fdt_ofnode_path("/clocks", pre_reloc_only);
- if (ret)
+ if (ret) {
debug("scan for /clocks failed: %d\n", ret);
+ return ret;
+ }
+
+ ret = dm_scan_fdt_ofnode_path("/firmware", pre_reloc_only);
+ if (ret)
+ debug("scan for /firmware failed: %d\n", ret);
return ret;
}
--
2.7.4
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[U-Boot] [PATCH v1 00/13] Introduce fastboot support for dragonboard410c
This set of patches introduce fastboot support for Qualcomm db410c. As part of the patch, a small quirk is added to ci_udc through a weaklly linked function. Ramon Fried (13): ehci: Replace board_prepare_usb with board_usb_init ehci: msm: Add missing platdata dts: db410c: add alias for USB db410c: serial# env using msm board serial phy: db410c: Add MSM USB PHY driver dts: db410c: Add bindings for MSM USB phy configs: db410c: Enable USB PHY ehci: msm: switch to generic PHY uclass ehci: msm: use init_type in probe usb:ci_udc: Introduce init_after_reset phy function usb: ehci-msm: Add init_after_reset for CI_UDC DB410c: Enable fastboot support db410c: automatically launch fastboot MAINTAINERS | 1 + arch/arm/dts/dragonboard410c.dts | 11 ++ arch/arm/mach-snapdragon/Kconfig | 1 + .../dragonboard410c/dragonboard410c.c | 17 ++- configs/dragonboard410c_defconfig | 11 ++ drivers/phy/Kconfig | 8 ++ drivers/phy/Makefile | 1 + drivers/phy/msm8916-usbh-phy.c| 109 ++ drivers/usb/gadget/ci_udc.c | 6 + drivers/usb/host/Kconfig | 3 +- drivers/usb/host/ehci-msm.c | 78 + 11 files changed, 190 insertions(+), 56 deletions(-) create mode 100644 drivers/phy/msm8916-usbh-phy.c -- 2.18.0 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v2 2/4] dm: core: Move "/clock" node scan into function
Create separate function for scanning node by path and
move "/clock" node scan code into that function.
This will be usable if scanning of more node is required.
Signed-off-by: Rajan Vaja
Reviewed-by: Simon Glass
---
Changes in v2:
* None
---
drivers/core/root.c | 33 ++---
1 file changed, 18 insertions(+), 15 deletions(-)
diff --git a/drivers/core/root.c b/drivers/core/root.c
index 72bcc7d..1ab4c38 100644
--- a/drivers/core/root.c
+++ b/drivers/core/root.c
@@ -330,10 +330,25 @@ static int dm_scan_fdt_node(struct udevice *parent, const
void *blob,
}
#endif
+static int dm_scan_fdt_ofnode_path(const char *path, bool pre_reloc_only)
+{
+ ofnode node;
+
+ node = ofnode_path(path);
+ if (!ofnode_valid(node))
+ return 0;
+
+#if CONFIG_IS_ENABLED(OF_LIVE)
+ if (of_live_active())
+ return dm_scan_fdt_live(gd->dm_root, node.np, pre_reloc_only);
+#endif
+ return dm_scan_fdt_node(gd->dm_root, gd->fdt_blob, node.of_offset,
+ pre_reloc_only);
+}
+
int dm_extended_scan_fdt(const void *blob, bool pre_reloc_only)
{
int ret;
- ofnode node;
ret = dm_scan_fdt(gd->fdt_blob, pre_reloc_only);
if (ret) {
@@ -341,21 +356,9 @@ int dm_extended_scan_fdt(const void *blob, bool
pre_reloc_only)
return ret;
}
- /* bind fixed-clock */
- node = ofnode_path("/clocks");
- /* if no DT "clocks" node, no need to go further */
- if (!ofnode_valid(node))
- return ret;
-
-#if CONFIG_IS_ENABLED(OF_LIVE)
- if (of_live_active())
- ret = dm_scan_fdt_live(gd->dm_root, node.np, pre_reloc_only);
- else
-#endif
- ret = dm_scan_fdt_node(gd->dm_root, gd->fdt_blob,
node.of_offset,
- pre_reloc_only);
+ ret = dm_scan_fdt_ofnode_path("/clocks", pre_reloc_only);
if (ret)
- debug("dm_scan_fdt_node() failed: %d\n", ret);
+ debug("scan for /clocks failed: %d\n", ret);
return ret;
}
--
2.7.4
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[U-Boot] [PATCH v2 0/4] dm: core: Scan "/firmware" node by default
All Linux firmware drivers are put under "/firmware" node and it has support to populate "/firmware" node by default. u-boot and Linux can share same DTB. In this case, driver probe for devices under "/firmware" will not be invoked as "/firmware" does not have its own "compatible" property. This patch series scans "/firmware" node by default like "/clocks". To avoid duplication of code, first patch moves, node scan code into separate function. This series also test to make sure "/firmware" nodes are scanned properly. Rajan Vaja (4): firmware: Add FIRMWARE config prompt string dm: core: Move "/clock" node scan into function dm: core: Scan "/firmware" node by default dm: test: Add "/firmware" node scan test arch/sandbox/dts/test.dts | 7 +++ drivers/core/root.c | 35 ++- drivers/firmware/Kconfig| 2 +- drivers/firmware/Makefile | 1 + drivers/firmware/firmware-sandbox.c | 20 test/dm/Makefile| 1 + test/dm/firmware.c | 22 ++ 7 files changed, 74 insertions(+), 14 deletions(-) create mode 100644 drivers/firmware/firmware-sandbox.c create mode 100644 test/dm/firmware.c -- Changes in v2: * Add firmware device for sanbox and its test * Fix Kconfig to enable FIRMWARE config -- 2.7.4 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v2 4/4] dm: test: Add "/firmware" node scan test
Add a test which verifies that all subnodes under "/firmware"
nodes are scanned.
Signed-off-by: Rajan Vaja
---
Changes in v2:
* New patch
---
arch/sandbox/dts/test.dts | 7 +++
drivers/firmware/Makefile | 1 +
drivers/firmware/firmware-sandbox.c | 20
test/dm/Makefile| 1 +
test/dm/firmware.c | 22 ++
5 files changed, 51 insertions(+)
create mode 100644 drivers/firmware/firmware-sandbox.c
create mode 100644 test/dm/firmware.c
diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts
index 3668263..94c603a 100644
--- a/arch/sandbox/dts/test.dts
+++ b/arch/sandbox/dts/test.dts
@@ -630,6 +630,13 @@
};
};
};
+
+ firmware {
+ sandbox_firmware: sandbox-firmware {
+ compatible = "sandbox,firmware";
+ };
+ };
+
};
#include "sandbox_pmic.dtsi"
diff --git a/drivers/firmware/Makefile b/drivers/firmware/Makefile
index 1cdda14..6cb8358 100644
--- a/drivers/firmware/Makefile
+++ b/drivers/firmware/Makefile
@@ -1,3 +1,4 @@
obj-$(CONFIG_FIRMWARE) += firmware-uclass.o
obj-$(CONFIG_ARM_PSCI_FW) += psci.o
obj-$(CONFIG_TI_SCI_PROTOCOL) += ti_sci.o
+obj-$(CONFIG_SANDBOX) += firmware-sandbox.o
diff --git a/drivers/firmware/firmware-sandbox.c
b/drivers/firmware/firmware-sandbox.c
new file mode 100644
index 000..d970d75
--- /dev/null
+++ b/drivers/firmware/firmware-sandbox.c
@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * sandbox firmware driver
+ *
+ * Copyright (C) 2018 Xilinx, Inc.
+ */
+
+#include
+#include
+
+static const struct udevice_id generic_sandbox_firmware_ids[] = {
+ { .compatible = "sandbox,firmware" },
+ { }
+};
+
+U_BOOT_DRIVER(sandbox_firmware) = {
+ .name = "sandbox_firmware",
+ .id = UCLASS_FIRMWARE,
+ .of_match = generic_sandbox_firmware_ids,
+};
diff --git a/test/dm/Makefile b/test/dm/Makefile
index 3f5a634..3f54710 100644
--- a/test/dm/Makefile
+++ b/test/dm/Makefile
@@ -47,4 +47,5 @@ obj-$(CONFIG_WDT) += wdt.o
obj-$(CONFIG_AXI) += axi.o
obj-$(CONFIG_MISC) += misc.o
obj-$(CONFIG_DM_SERIAL) += serial.o
+obj-$(CONFIG_FIRMWARE) += firmware.o
endif
diff --git a/test/dm/firmware.c b/test/dm/firmware.c
new file mode 100644
index 000..60fdcbb
--- /dev/null
+++ b/test/dm/firmware.c
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Xilinx, Inc.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+/* Base test of firmware probe */
+static int dm_test_firmware_probe(struct unit_test_state *uts)
+{
+ struct udevice *dev;
+
+ ut_assertok(uclass_get_device_by_name(UCLASS_FIRMWARE,
+ "sandbox-firmware", ));
+ return 0;
+}
+DM_TEST(dm_test_firmware_probe, DM_TESTF_SCAN_FDT);
--
2.7.4
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[U-Boot] [PATCH v2 1/4] firmware: Add FIRMWARE config prompt string
There is no prompt string for FIRMWARE config. Without this, FIRMWARE config cannot be enabled through menuconfing or config file. Fix this by adding prompt summary. Signed-off-by: Rajan Vaja --- Changes in v2: * New patch --- drivers/firmware/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/firmware/Kconfig b/drivers/firmware/Kconfig index cb73b70..feaea81 100644 --- a/drivers/firmware/Kconfig +++ b/drivers/firmware/Kconfig @@ -1,5 +1,5 @@ config FIRMWARE - bool + bool "Enable Firmware driver support" config ARM_PSCI_FW bool -- 2.7.4 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH] u-boot: align cache flushes in load_elf_image_shdr to line boundaries
Prevent cache warning messages when using the 'bootelf' command on an Arm target. Round down each section start address and round up the respective section end to the nearest cache line. Signed-off-by: Neil Stainton --- This is a repeat of commit 8744d6c5 as this file changed significantly between patch submission and the patch being applied. --- cmd/elf.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/cmd/elf.c b/cmd/elf.c index eafea38..1199e5d 100644 --- a/cmd/elf.c +++ b/cmd/elf.c @@ -141,7 +141,9 @@ static unsigned long load_elf_image_shdr(unsigned long addr) memcpy((void *)(uintptr_t)shdr->sh_addr, (const void *)image, shdr->sh_size); } - flush_cache(shdr->sh_addr, shdr->sh_size); + flush_cache(rounddown(shdr->sh_addr, ARCH_DMA_MINALIGN), + roundup((shdr->sh_addr + shdr->sh_size), ARCH_DMA_MINALIGN) - + rounddown(shdr->sh_addr, ARCH_DMA_MINALIGN)); } return ehdr->e_entry; -- 2.7.4 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v1 03/13] dts: db410c: add alias for USB
On Wed, Sep 19, 2018 at 10:28 PM Peter Robinson wrote:
>
> This should go into a -u-boot.dtsi file so that the
> dragonboard410c.dts can be synced from the linux kernel without
> change.
>
Hi Peter.
I thought that -u-boot.dtsi is only for u-boot specific stuff,
The alias is not specific to u-boot AFAIK.
I'll look how other boards handle that.
Thanks,
Ramon.
> Peter
>
> On Wed, Sep 19, 2018 at 7:31 PM Ramon Fried wrote:
> >
> > Alias is required so req-seq will be filled.
> >
> > Signed-off-by: Ramon Fried
> > ---
> >
> > arch/arm/dts/dragonboard410c.dts | 4
> > 1 file changed, 4 insertions(+)
> >
> > diff --git a/arch/arm/dts/dragonboard410c.dts
> > b/arch/arm/dts/dragonboard410c.dts
> > index f4f7c350ec..75f28300b7 100644
> > --- a/arch/arm/dts/dragonboard410c.dts
> > +++ b/arch/arm/dts/dragonboard410c.dts
> > @@ -18,6 +18,10 @@
> > #address-cells = <0x2>;
> > #size-cells = <0x2>;
> >
> > + aliases {
> > + usb0 = "/soc/ehci@78d9000";
> > + };
> > +
> > memory {
> > device_type = "memory";
> > reg = <0 0x8000 0 0x3da0>;
> > --
> > 2.18.0
> >
> > ___
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Re: [U-Boot] [PATCH v12 1/3] Consolidating UDP header functions.
On Wed, Sep 19, 2018 at 2:24 PM, Duncan Hare wrote: > >>On Sun, Jun 24, 2018 at 5:40 PM, wrote:. >>From: Duncan Hare >> >>> To make it possible to add TCP versions of the same, while reusing >>> IP portions. This patch should not change any behavior. >>> >>> All references to TCP removed >>> Used most recent version of u-boot June 22 13, 2918 >>> Series to fix patman errors over Licensing declaration >>> END >>> >>> Series-notes > >>See how it didn't work? It's still in this patch log instead of below >>"---". Missing colon. Why so opposed to a dry run? You are having such >>trouble using the patman tool properly, it seems so much time is spent >>saying the same things over and over. >> >>I have tested this patch and it breaks UDP functionality. I have fixed >>the regression. I have also fixed formatting issues that I've asked >>you to fix and you have not. > >>With your permission I will pull in the fixed version of this patch. >>Or if you prefer, I can send it to the list. > >>-Joe > >>> TCP with Selective Acknowledgment (SACK) is currently the protocol >>> with highest speed transfers, for fast multi-hop networks. >>> END >>> > >>Joe > With your permission I will pull in the fixed version of this patch.Or if you > prefer, I can send it to the list. > You have my permission. I have the disadvantage that in Patman I do not know > what is correct behavior,so when I run a dry run, I do not know if what I'm > seeing is right or wrong. http://www.denx.de/wiki/U-Boot/Patches tells you what is right and wrong. "tools/patman/README" in the source tells you how to do it with patman > > Thanks > > Duncan Hare > 714 931 7952 > > > > ___ > U-Boot mailing list > U-Boot@lists.denx.de > https://lists.denx.de/listinfo/u-boot ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 1/1] dm: video: support more escape sequences
The EFI subsystems needs to know the size of the terminal. If the
environment variable
stdout = serial,vidconsole
this size cannot be read from the video console. So the EFI subsystem
sends escape sequences to read the size. With this patch we get support
for the following escape sequences:
ESC "7" Save cursor position
ESC "8" Restore cursor position
Signed-off-by: Heinrich Schuchardt
---
drivers/video/vidconsole-uclass.c | 75 +--
include/video_console.h | 28 +++-
2 files changed, 78 insertions(+), 25 deletions(-)
diff --git a/drivers/video/vidconsole-uclass.c
b/drivers/video/vidconsole-uclass.c
index 0c36a5de0a..7f95e9c6e5 100644
--- a/drivers/video/vidconsole-uclass.c
+++ b/drivers/video/vidconsole-uclass.c
@@ -165,6 +165,43 @@ static char *parsenum(char *s, int *num)
return end;
}
+/**
+ * set_cursor_position() - set cursor position
+ *
+ * @priv: private data of the video console
+ * @row: new row
+ * @col: new column
+ */
+static void set_cursor_position(struct vidconsole_priv *priv, int row, int col)
+{
+ /*
+* Ensure we stay in the bounds of the screen.
+*/
+ if (row >= priv->rows)
+ row = priv->rows - 1;
+ if (col >= priv->cols)
+ col = priv->cols - 1;
+
+ priv->ycur = row * priv->y_charsize;
+ priv->xcur_frac = priv->xstart_frac +
+ VID_TO_POS(col * priv->x_charsize);
+}
+
+/**
+ * get_cursor_position() - get cursor position
+ *
+ * @priv: private data of the video console
+ * @row: row
+ * @col: column
+ */
+static void get_cursor_position(struct vidconsole_priv *priv,
+ int *row, int *col)
+{
+ *row = priv->ycur / priv->y_charsize;
+ *col = VID_TO_PIXEL(priv->xcur_frac - priv->xstart_frac) /
+ priv->x_charsize;
+}
+
/*
* Process a character while accumulating an escape string. Chars are
* accumulated into escape_buf until the end of escape sequence is
@@ -180,8 +217,30 @@ static void vidconsole_escape_char(struct udevice *dev,
char ch)
/* Sanity checking for bogus ESC sequences: */
if (priv->escape_len >= sizeof(priv->escape_buf))
goto error;
- if (priv->escape_len == 0 && ch != '[')
- goto error;
+ if (priv->escape_len == 0) {
+ switch (ch) {
+ case '7':
+ /* Save cursor position */
+ get_cursor_position(priv, >row_saved,
+ >col_saved);
+ priv->escape = 0;
+
+ return;
+ case '8': {
+ /* Restore cursor position */
+ int row = priv->row_saved;
+ int col = priv->col_saved;
+
+ set_cursor_position(priv, row, col);
+ priv->escape = 0;
+ return;
+ }
+ case '[':
+ break;
+ default:
+ goto error;
+ }
+ }
priv->escape_buf[priv->escape_len++] = ch;
@@ -213,17 +272,7 @@ static void vidconsole_escape_char(struct udevice *dev,
char ch)
s++;/* ; */
s = parsenum(s, );
- /*
-* Ensure we stay in the bounds of the screen.
-*/
- if (row >= priv->rows)
- row = priv->rows - 1;
- if (col >= priv->cols)
- col = priv->cols - 1;
-
- priv->ycur = row * priv->y_charsize;
- priv->xcur_frac = priv->xstart_frac +
- VID_TO_POS(col * priv->x_charsize);
+ set_cursor_position(priv, row, col);
break;
}
diff --git a/include/video_console.h b/include/video_console.h
index 44e7bdbe29..52a41ac200 100644
--- a/include/video_console.h
+++ b/include/video_console.h
@@ -43,20 +43,22 @@ enum color_idx {
* Drivers must set up @rows, @cols, @x_charsize, @y_charsize in their probe()
* method. Drivers may set up @xstart_frac if desired.
*
- * @sdev: stdio device, acting as an output sink
- * @xcur_frac: Current X position, in fractional units (VID_TO_POS(x))
- * @ycur: Current Y position in pixels (0=top)
- * @rows: Number of text rows
- * @cols: Number of text columns
- * @x_charsize:Character width in pixels
- * @y_charsize:Character height in pixels
+ * @sdev: stdio device, acting as an output sink
+ * @xcur_frac: Current X position, in fractional units (VID_TO_POS(x))
+ * @ycur: Current Y position in pixels (0=top)
+ * @rows: Number of text rows
+ * @cols: Number of text columns
+ * @x_charsize:Character width in pixels
+ *
Re: [U-Boot] [PATCH v1 03/13] dts: db410c: add alias for USB
This should go into a -u-boot.dtsi file so that the
dragonboard410c.dts can be synced from the linux kernel without
change.
Peter
On Wed, Sep 19, 2018 at 7:31 PM Ramon Fried wrote:
>
> Alias is required so req-seq will be filled.
>
> Signed-off-by: Ramon Fried
> ---
>
> arch/arm/dts/dragonboard410c.dts | 4
> 1 file changed, 4 insertions(+)
>
> diff --git a/arch/arm/dts/dragonboard410c.dts
> b/arch/arm/dts/dragonboard410c.dts
> index f4f7c350ec..75f28300b7 100644
> --- a/arch/arm/dts/dragonboard410c.dts
> +++ b/arch/arm/dts/dragonboard410c.dts
> @@ -18,6 +18,10 @@
> #address-cells = <0x2>;
> #size-cells = <0x2>;
>
> + aliases {
> + usb0 = "/soc/ehci@78d9000";
> + };
> +
> memory {
> device_type = "memory";
> reg = <0 0x8000 0 0x3da0>;
> --
> 2.18.0
>
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Re: [U-Boot] [PATCH v12 1/3] Consolidating UDP header functions.
>On Sun, Jun 24, 2018 at 5:40 PM, wrote:. >From: Duncan Hare > >> To make it possible to add TCP versions of the same, while reusing >> IP portions. This patch should not change any behavior. >> >> All references to TCP removed >> Used most recent version of u-boot June 22 13, 2918 >> Series to fix patman errors over Licensing declaration >> END >> >> Series-notes >See how it didn't work? It's still in this patch log instead of below >"---". Missing colon. Why so opposed to a dry run? You are having such >trouble using the patman tool properly, it seems so much time is spent >saying the same things over and over. > >I have tested this patch and it breaks UDP functionality. I have fixed >the regression. I have also fixed formatting issues that I've asked >you to fix and you have not. >With your permission I will pull in the fixed version of this patch. >Or if you prefer, I can send it to the list. >-Joe >> TCP with Selective Acknowledgment (SACK) is currently the protocol >> with highest speed transfers, for fast multi-hop networks. >> END >> >Joe With your permission I will pull in the fixed version of this patch.Or if you prefer, I can send it to the list. You have my permission. I have the disadvantage that in Patman I do not know what is correct behavior,so when I run a dry run, I do not know if what I'm seeing is right or wrong. Thanks Duncan Hare 714 931 7952 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v12 1/3] Consolidating UDP header functions.
On Sun, Jun 24, 2018 at 5:40 PM, wrote: > From: Duncan Hare > > To make it possible to add TCP versions of the same, while reusing > IP portions. This patch should not change any behavior. > > All references to TCP removed > Used most recent version of u-boot June 22 13, 2918 > Series to fix patman errors over Licensing declaration > END > > Series-notes See how it didn't work? It's still in this patch log instead of below "---". Missing colon. Why so opposed to a dry run? You are having such trouble using the patman tool properly, it seems so much time is spent saying the same things over and over. I have tested this patch and it breaks UDP functionality. I have fixed the regression. I have also fixed formatting issues that I've asked you to fix and you have not. With your permission I will pull in the fixed version of this patch. Or if you prefer, I can send it to the list. -Joe > TCP with Selective Acknowledgment (SACK) is currently the protocol > with highest speed transfers, for fast multi-hop networks. > END > ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v1 10/13] usb:ci_udc: Introduce init_after_reset phy function
MSM variant of Chipidea must reinitalize the phy
after controller reset.
Introduce ci_init_after_reset() weak function that
can be used to achieve the above init.
Signed-off-by: Ramon Fried
---
drivers/usb/gadget/ci_udc.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/usb/gadget/ci_udc.c b/drivers/usb/gadget/ci_udc.c
index 2b9dbf06b9..8d23fab3b7 100644
--- a/drivers/usb/gadget/ci_udc.c
+++ b/drivers/usb/gadget/ci_udc.c
@@ -104,6 +104,10 @@ static struct usb_ep_ops ci_ep_ops = {
.free_request = ci_ep_free_request,
};
+__weak void ci_init_after_reset(struct ehci_ctrl *ctrl)
+{
+}
+
/* Init values for USB endpoints. */
static const struct usb_ep ci_ep_init[5] = {
[0] = { /* EP 0 */
@@ -887,6 +891,8 @@ static int ci_pullup(struct usb_gadget *gadget, int is_on)
writel(USBCMD_ITC(MICRO_8FRAME) | USBCMD_RST, >usbcmd);
udelay(200);
+ ci_init_after_reset(controller.ctrl);
+
writel((unsigned long)controller.epts, >epinitaddr);
/* select DEVICE mode */
--
2.18.0
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[U-Boot] [PATCH v1 11/13] usb: ehci-msm: Add init_after_reset for CI_UDC
MSM uses the chipidea controller IP, however it requires
to reinit the phy after controller reset. in EHCI mode there's a
dedicated callback for it.
In device mode however there's no such callback.
Add implementaion of ci_init_after_reset() to implement the above
requirement in case CI_UDC driver is used.
Signed-off-by: Ramon Fried
---
drivers/usb/host/ehci-msm.c | 12
1 file changed, 12 insertions(+)
diff --git a/drivers/usb/host/ehci-msm.c b/drivers/usb/host/ehci-msm.c
index 00d6bb8231..5c257ccf4d 100644
--- a/drivers/usb/host/ehci-msm.c
+++ b/drivers/usb/host/ehci-msm.c
@@ -121,6 +121,18 @@ static int ehci_usb_ofdata_to_platdata(struct udevice *dev)
return 0;
}
+#if defined(CONFIG_CI_UDC)
+/* Little quirk that MSM needs with Chipidea controller
+ * Must reinit phy after reset
+ */
+void ci_init_after_reset(struct ehci_ctrl *ctrl)
+{
+ struct msm_ehci_priv *p = ctrl->priv;
+
+ generic_phy_reset(>phy);
+}
+#endif
+
static const struct udevice_id ehci_usb_ids[] = {
{ .compatible = "qcom,ehci-host", },
{ }
--
2.18.0
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[U-Boot] [PATCH v1 07/13] configs: db410c: Enable USB PHY
Enable USB PHY driver. Also fixed the alphabetically ordering of the config. Signed-off-by: Ramon Fried --- configs/dragonboard410c_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/dragonboard410c_defconfig b/configs/dragonboard410c_defconfig index 96a831443a..0d9008deb7 100644 --- a/configs/dragonboard410c_defconfig +++ b/configs/dragonboard410c_defconfig @@ -29,6 +29,7 @@ CONFIG_LED_GPIO=y CONFIG_DM_MMC=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_MSM=y +CONFIG_PHY=y CONFIG_PINCTRL=y CONFIG_PINCONF=y CONFIG_DM_PMIC=y -- 2.18.0 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v1 13/13] db410c: automatically launch fastboot
If during boot the key-vol-down press is detected
we'll fall back to fastboot.
Signed-off-by: Ramon Fried
---
board/qualcomm/dragonboard410c/dragonboard410c.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/board/qualcomm/dragonboard410c/dragonboard410c.c
b/board/qualcomm/dragonboard410c/dragonboard410c.c
index b2a72bce38..9ceed3ad9b 100644
--- a/board/qualcomm/dragonboard410c/dragonboard410c.c
+++ b/board/qualcomm/dragonboard410c/dragonboard410c.c
@@ -140,7 +140,8 @@ int misc_init_r(void)
if (dm_gpio_get_value()) {
env_set("bootdelay", "-1");
- printf("Power button pressed - dropping to console.\n");
+ env_set("bootcmd", "fastboot 0");
+ printf("key_vol_down pressed - Starting fastboot.\n");
}
return 0;
--
2.18.0
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[U-Boot] [PATCH v1 09/13] ehci: msm: use init_type in probe
Change ehci_usb_probe() function to initialize the
USB according to the init_type provided.
Signed-off-by: Ramon Fried
---
drivers/usb/host/ehci-msm.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/usb/host/ehci-msm.c b/drivers/usb/host/ehci-msm.c
index a27a5833dd..00d6bb8231 100644
--- a/drivers/usb/host/ehci-msm.c
+++ b/drivers/usb/host/ehci-msm.c
@@ -49,6 +49,7 @@ static int ehci_usb_probe(struct udevice *dev)
{
struct msm_ehci_priv *p = dev_get_priv(dev);
struct usb_ehci *ehci = p->ehci;
+ struct usb_platdata *plat = dev_get_platdata(dev);
struct ehci_hccr *hccr;
struct ehci_hcor *hcor;
int ret;
@@ -61,11 +62,12 @@ static int ehci_usb_probe(struct udevice *dev)
if (ret)
return ret;
- ret = board_usb_init(0, USB_INIT_HOST);
+ ret = board_usb_init(0, plat->init_type);
if (ret < 0)
return ret;
- return ehci_register(dev, hccr, hcor, _ehci_ops, 0, USB_INIT_HOST);
+ return ehci_register(dev, hccr, hcor, _ehci_ops, 0,
+plat->init_type);
}
static int ehci_usb_remove(struct udevice *dev)
--
2.18.0
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[U-Boot] [PATCH v1 05/13] phy: db410c: Add MSM USB PHY driver
Add a PHY driver for the Qualcomm dragonboard 410c which
allows switching on/off and resetting the phy connected
to the EHCI controllers and USBHS controller.
Signed-off-by: Ramon Fried
---
MAINTAINERS| 1 +
drivers/phy/Kconfig| 8 +++
drivers/phy/Makefile | 1 +
drivers/phy/msm8916-usbh-phy.c | 109 +
4 files changed, 119 insertions(+)
create mode 100644 drivers/phy/msm8916-usbh-phy.c
diff --git a/MAINTAINERS b/MAINTAINERS
index 39d28e5d45..1a5b543dc7 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -209,6 +209,7 @@ S: Maintained
F: arch/arm/mach-snapdragon/
F: drivers/gpio/msm_gpio.c
F: drivers/mmc/msm_sdhci.c
+F: drivers/phy/msm8916-usbh-phy.c
F: drivers/serial/serial_msm.c
F: drivers/smem/msm_smem.c
F: drivers/usb/host/ehci-msm.c
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index e0822bb775..bcc8e22795 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -139,4 +139,12 @@ config MESON_GXL_USB_PHY
This is the generic phy driver for the Amlogic Meson GXL
USB2 and USB3 PHYS.
+config MSM8916_USB_PHY
+ bool "Qualcomm MSM8916 USB PHY support"
+ depends on PHY
+ help
+ Support the USB PHY in msm8916
+
+ This PHY is found on qualcomm dragonboard410c development board.
+
endmenu
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index 178fb4530e..1e1e4ca11e 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -15,3 +15,4 @@ obj-$(CONFIG_STI_USB_PHY) += sti_usb_phy.o
obj-$(CONFIG_PHY_RCAR_GEN2) += phy-rcar-gen2.o
obj-$(CONFIG_PHY_STM32_USBPHYC) += phy-stm32-usbphyc.o
obj-$(CONFIG_MESON_GXL_USB_PHY) += meson-gxl-usb2.o meson-gxl-usb3.o
+obj-$(CONFIG_MSM8916_USB_PHY) += msm8916-usbh-phy.o
diff --git a/drivers/phy/msm8916-usbh-phy.c b/drivers/phy/msm8916-usbh-phy.c
new file mode 100644
index 00..2c90738fca
--- /dev/null
+++ b/drivers/phy/msm8916-usbh-phy.c
@@ -0,0 +1,109 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Ramon Fried
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+/* PHY viewport regs */
+#define ULPI_MISC_A_READ 0x96
+#define ULPI_MISC_A_SET0x97
+#define ULPI_MISC_A_CLEAR 0x98
+#define ULPI_MISC_A_VBUSVLDEXT BIT(0)
+#define ULPI_MISC_A_VBUSVLDEXTSEL BIT(1)
+#define GEN2_SESS_VLD_CTRL_EN BIT(7)
+#define SESS_VLD_CTRL BIT(25)
+
+struct msm_phy_priv {
+ void __iomem *regs;
+ struct usb_ehci *ehci; /* Start of IP core*/
+ struct ulpi_viewport ulpi_vp; /* ULPI Viewport */
+};
+
+static int msm_phy_power_on(struct phy *phy)
+{
+ struct msm_phy_priv *priv = dev_get_priv(phy->dev);
+
+ /* Select and enable external configuration with USB PHY */
+ ulpi_write(>ulpi_vp, (u8 *)ULPI_MISC_A_SET,
+ ULPI_MISC_A_VBUSVLDEXTSEL | ULPI_MISC_A_VBUSVLDEXT);
+
+ return 0;
+}
+
+static int msm_phy_power_off(struct phy *phy)
+{
+ struct msm_phy_priv *priv = dev_get_priv(phy->dev);
+
+ /* Disable VBUS mimicing in the controller. */
+ ulpi_write(>ulpi_vp, (u8 *)ULPI_MISC_A_CLEAR,
+ ULPI_MISC_A_VBUSVLDEXTSEL | ULPI_MISC_A_VBUSVLDEXT);
+ return 0;
+}
+
+static int msm_phy_reset(struct phy *phy)
+{
+ struct msm_phy_priv *p = dev_get_priv(phy->dev);
+
+ /* select ULPI phy */
+ writel(PORT_PTS_ULPI, >ehci->portsc);
+
+ /* Enable sess_vld */
+ setbits_le32(>ehci->genconfig2, GEN2_SESS_VLD_CTRL_EN);
+
+ /* Enable external vbus configuration in the LINK */
+ setbits_le32(>ehci->usbcmd, SESS_VLD_CTRL);
+
+ /* USB_OTG_HS_AHB_BURST */
+ writel(0x0, >ehci->sbuscfg);
+
+ /* USB_OTG_HS_AHB_MODE: HPROT_MODE */
+ /* Bus access related config. */
+ writel(0x08, >ehci->sbusmode);
+
+ return 0;
+}
+
+static int msm_phy_probe(struct udevice *dev)
+{
+ struct msm_phy_priv *priv = dev_get_priv(dev);
+
+ priv->regs = dev_remap_addr(dev);
+ if (!priv->regs)
+ return -EINVAL;
+
+ priv->ehci = (struct usb_ehci *)priv->regs;
+ priv->ulpi_vp.port_num = 0;
+
+ /* Warning: this will not work if viewport address is > 64 bit due to
+* ULPI design.
+*/
+ priv->ulpi_vp.viewport_addr = (phys_addr_t)>ehci->ulpi_viewpoint;
+
+ return 0;
+}
+
+static struct phy_ops msm_phy_ops = {
+ .power_on = msm_phy_power_on,
+ .power_off = msm_phy_power_off,
+ .reset = msm_phy_reset,
+};
+
+static const struct udevice_id msm_phy_ids[] = {
+ { .compatible = "qcom,apq8016-usbphy" },
+ { }
+};
+
+U_BOOT_DRIVER(msm8916_usbphy) = {
+ .name = "msm8916_usbphy",
+ .id = UCLASS_PHY,
+ .of_match = msm_phy_ids,
+ .ops= _phy_ops,
+ .probe = msm_phy_probe,
+
[U-Boot] [PATCH v1 12/13] DB410c: Enable fastboot support
Signed-off-by: Ramon Fried --- configs/dragonboard410c_defconfig | 10 ++ 1 file changed, 10 insertions(+) diff --git a/configs/dragonboard410c_defconfig b/configs/dragonboard410c_defconfig index 0d9008deb7..a55abaf8df 100644 --- a/configs/dragonboard410c_defconfig +++ b/configs/dragonboard410c_defconfig @@ -4,6 +4,7 @@ CONFIG_SYS_TEXT_BASE=0x8008 CONFIG_IDENT_STRING="\nQualcomm-DragonBoard 410C" CONFIG_DISTRO_DEFAULTS=y CONFIG_NR_DRAM_BANKS=1 +# CONFIG_ANDROID_BOOT_IMAGE is not set CONFIG_FIT=y CONFIG_OF_BOARD_SETUP=y CONFIG_MISC_INIT_R=y @@ -22,6 +23,10 @@ CONFIG_CMD_TIMER=y CONFIG_DEFAULT_DEVICE_TREE="dragonboard410c" CONFIG_ENV_IS_IN_MMC=y CONFIG_CLK=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x9100 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 CONFIG_MSM_GPIO=y CONFIG_PM8916_GPIO=y CONFIG_LED=y @@ -43,6 +48,11 @@ CONFIG_USB_EHCI_MSM=y CONFIG_USB_ULPI_VIEWPORT=y CONFIG_USB_ULPI=y CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_VENDOR_NUM=0x18d1 +CONFIG_USB_GADGET_PRODUCT_NUM=0xd00d +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DUALSPEED=n CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_USB_ETHER_ASIX88179=y -- 2.18.0 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v1 03/13] dts: db410c: add alias for USB
Alias is required so req-seq will be filled.
Signed-off-by: Ramon Fried
---
arch/arm/dts/dragonboard410c.dts | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/dts/dragonboard410c.dts b/arch/arm/dts/dragonboard410c.dts
index f4f7c350ec..75f28300b7 100644
--- a/arch/arm/dts/dragonboard410c.dts
+++ b/arch/arm/dts/dragonboard410c.dts
@@ -18,6 +18,10 @@
#address-cells = <0x2>;
#size-cells = <0x2>;
+ aliases {
+ usb0 = "/soc/ehci@78d9000";
+ };
+
memory {
device_type = "memory";
reg = <0 0x8000 0 0x3da0>;
--
2.18.0
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[U-Boot] [PATCH v1 04/13] db410c: serial# env using msm board serial
The serial# environment variable needs to be
defined so it will be used by fastboot as serial
for the endpoint descriptor.
Signed-off-by: Ramon Fried
---
arch/arm/mach-snapdragon/Kconfig | 1 +
board/qualcomm/dragonboard410c/dragonboard410c.c | 10 ++
2 files changed, 11 insertions(+)
diff --git a/arch/arm/mach-snapdragon/Kconfig b/arch/arm/mach-snapdragon/Kconfig
index bfd99db6e2..e562d693c6 100644
--- a/arch/arm/mach-snapdragon/Kconfig
+++ b/arch/arm/mach-snapdragon/Kconfig
@@ -14,6 +14,7 @@ choice
config TARGET_DRAGONBOARD410C
bool "96Boards Dragonboard 410C"
+ select BOARD_LATE_INIT
help
Support for 96Boards Dragonboard 410C. This board complies with
96Board Open Platform Specifications. Features:
diff --git a/board/qualcomm/dragonboard410c/dragonboard410c.c
b/board/qualcomm/dragonboard410c/dragonboard410c.c
index e8a3ed0450..b2a72bce38 100644
--- a/board/qualcomm/dragonboard410c/dragonboard410c.c
+++ b/board/qualcomm/dragonboard410c/dragonboard410c.c
@@ -151,6 +151,16 @@ int board_init(void)
return 0;
}
+int board_late_init(void)
+{
+ char serial[16];
+
+ memset(serial, 0, 16);
+ snprintf(serial, 13, "%x", msm_board_serial());
+ env_set("serial#", serial);
+ return 0;
+}
+
/* Fixup of DTB for Linux Kernel
* 1. Fixup installed DRAM.
* 2. Fixup WLAN/BT Mac address:
--
2.18.0
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[U-Boot] [PATCH v1 08/13] ehci: msm: switch to generic PHY uclass
All the underlying USB PHY was handled in the ehci driver.
Use the generic phy API instead.
Signed-off-by: Ramon Fried
---
drivers/usb/host/Kconfig| 3 +--
drivers/usb/host/ehci-msm.c | 52 +++--
2 files changed, 10 insertions(+), 45 deletions(-)
diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index b4dd005651..a213c918bc 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -167,12 +167,11 @@ config USB_EHCI_MSM
bool "Support for Qualcomm on-chip EHCI USB controller"
depends on DM_USB
select USB_ULPI_VIEWPORT
+ select MSM8916_USB_PHY
default n
---help---
Enables support for the on-chip EHCI controller on Qualcomm
Snapdragon SoCs.
- This driver supports combination of Chipidea USB controller
- and Synapsys USB PHY in host mode only.
config USB_EHCI_PCI
bool "Support for PCI-based EHCI USB controller"
diff --git a/drivers/usb/host/ehci-msm.c b/drivers/usb/host/ehci-msm.c
index e7fb76d6da..a27a5833dd 100644
--- a/drivers/usb/host/ehci-msm.c
+++ b/drivers/usb/host/ehci-msm.c
@@ -21,59 +21,19 @@
#include
#include "ehci.h"
-/* PHY viewport regs */
-#define ULPI_MISC_A_READ 0x96
-#define ULPI_MISC_A_SET 0x97
-#define ULPI_MISC_A_CLEAR0x98
-#define ULPI_MISC_A_VBUSVLDEXTSEL(1 << 1)
-#define ULPI_MISC_A_VBUSVLDEXT (1 << 0)
-
-#define GEN2_SESS_VLD_CTRL_EN (1 << 7)
-
-#define SESS_VLD_CTRL (1 << 25)
-
struct msm_ehci_priv {
struct ehci_ctrl ctrl; /* Needed by EHCI */
struct usb_ehci *ehci; /* Start of IP core*/
struct ulpi_viewport ulpi_vp; /* ULPI Viewport */
+ struct phy phy;
};
-static void setup_usb_phy(struct msm_ehci_priv *priv)
-{
- /* Select and enable external configuration with USB PHY */
- ulpi_write(>ulpi_vp, (u8 *)ULPI_MISC_A_SET,
- ULPI_MISC_A_VBUSVLDEXTSEL | ULPI_MISC_A_VBUSVLDEXT);
-}
-
-static void reset_usb_phy(struct msm_ehci_priv *priv)
-{
- /* Disable VBUS mimicing in the controller. */
- ulpi_write(>ulpi_vp, (u8 *)ULPI_MISC_A_CLEAR,
- ULPI_MISC_A_VBUSVLDEXTSEL | ULPI_MISC_A_VBUSVLDEXT);
-}
-
-
static int msm_init_after_reset(struct ehci_ctrl *dev)
{
struct msm_ehci_priv *p = container_of(dev, struct msm_ehci_priv, ctrl);
struct usb_ehci *ehci = p->ehci;
- /* select ULPI phy */
- writel(PORT_PTS_ULPI, >portsc);
- setup_usb_phy(p);
-
- /* Enable sess_vld */
- setbits_le32(>genconfig2, GEN2_SESS_VLD_CTRL_EN);
-
- /* Enable external vbus configuration in the LINK */
- setbits_le32(>usbcmd, SESS_VLD_CTRL);
-
- /* USB_OTG_HS_AHB_BURST */
- writel(0x0, >sbuscfg);
-
- /* USB_OTG_HS_AHB_MODE: HPROT_MODE */
- /* Bus access related config. */
- writel(0x08, >sbusmode);
+ generic_phy_reset(>phy);
/* set mode to host controller */
writel(CM_HOST, >usbmode);
@@ -97,6 +57,10 @@ static int ehci_usb_probe(struct udevice *dev)
hcor = (struct ehci_hcor *)((phys_addr_t)hccr +
HC_LENGTH(ehci_readl(&(hccr)->cr_capbase)));
+ ret = ehci_setup_phy(dev, >phy, 0);
+ if (ret)
+ return ret;
+
ret = board_usb_init(0, USB_INIT_HOST);
if (ret < 0)
return ret;
@@ -117,7 +81,9 @@ static int ehci_usb_remove(struct udevice *dev)
/* Stop controller. */
clrbits_le32(>usbcmd, CMD_RUN);
- reset_usb_phy(p);
+ ret = ehci_shutdown_phy(dev, >phy);
+ if (ret)
+ return ret;
ret = board_usb_init(0, USB_INIT_DEVICE); /* Board specific hook */
if (ret < 0)
--
2.18.0
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[U-Boot] [PATCH v1 06/13] dts: db410c: Add bindings for MSM USB phy
Signed-off-by: Ramon Fried
---
arch/arm/dts/dragonboard410c.dts | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/dts/dragonboard410c.dts b/arch/arm/dts/dragonboard410c.dts
index 75f28300b7..fa348bc621 100644
--- a/arch/arm/dts/dragonboard410c.dts
+++ b/arch/arm/dts/dragonboard410c.dts
@@ -97,6 +97,13 @@
ehci@78d9000 {
compatible = "qcom,ehci-host";
reg = <0x78d9000 0x400>;
+ phys = <_phy>;
+ };
+
+ ehci_phy: ehci_phy@78d9000 {
+ compatible = "qcom,apq8016-usbphy";
+ reg = <0x78d9000 0x400>;
+ #phy-cells = <0>;
};
sdhci@07824000 {
--
2.18.0
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[U-Boot] [PATCH v1 02/13] ehci: msm: Add missing platdata
platdata_auto_alloc_size was not initialized in structure.
Caused null pointer dereference when configuring device as
gadget.
Signed-off-by: Ramon Fried
---
drivers/usb/host/ehci-msm.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/usb/host/ehci-msm.c b/drivers/usb/host/ehci-msm.c
index db982624dc..e7fb76d6da 100644
--- a/drivers/usb/host/ehci-msm.c
+++ b/drivers/usb/host/ehci-msm.c
@@ -167,5 +167,6 @@ U_BOOT_DRIVER(usb_ehci) = {
.remove = ehci_usb_remove,
.ops= _usb_ops,
.priv_auto_alloc_size = sizeof(struct msm_ehci_priv),
+ .platdata_auto_alloc_size = sizeof(struct usb_platdata),
.flags = DM_FLAG_ALLOC_PRIV_DMA,
};
--
2.18.0
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[U-Boot] [PATCH v1 01/13] ehci: Replace board_prepare_usb with board_usb_init
Use standard board_usb_init() instead of the specific board_prepare_usb.
Signed-off-by: Ramon Fried
---
board/qualcomm/dragonboard410c/dragonboard410c.c | 4 ++--
drivers/usb/host/ehci-msm.c | 9 ++---
2 files changed, 4 insertions(+), 9 deletions(-)
diff --git a/board/qualcomm/dragonboard410c/dragonboard410c.c
b/board/qualcomm/dragonboard410c/dragonboard410c.c
index 53e231e55a..e8a3ed0450 100644
--- a/board/qualcomm/dragonboard410c/dragonboard410c.c
+++ b/board/qualcomm/dragonboard410c/dragonboard410c.c
@@ -44,7 +44,7 @@ int dram_init_banksize(void)
return 0;
}
-int board_prepare_usb(enum usb_init_type type)
+int board_usb_init(int index, enum usb_init_type init)
{
static struct udevice *pmic_gpio;
static struct gpio_desc hub_reset, usb_sel;
@@ -93,7 +93,7 @@ int board_prepare_usb(enum usb_init_type type)
}
}
- if (type == USB_INIT_HOST) {
+ if (init == USB_INIT_HOST) {
/* Start USB Hub */
dm_gpio_set_dir_flags(_reset,
GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
diff --git a/drivers/usb/host/ehci-msm.c b/drivers/usb/host/ehci-msm.c
index 17bfa7c02f..db982624dc 100644
--- a/drivers/usb/host/ehci-msm.c
+++ b/drivers/usb/host/ehci-msm.c
@@ -38,11 +38,6 @@ struct msm_ehci_priv {
struct ulpi_viewport ulpi_vp; /* ULPI Viewport */
};
-int __weak board_prepare_usb(enum usb_init_type type)
-{
- return 0;
-}
-
static void setup_usb_phy(struct msm_ehci_priv *priv)
{
/* Select and enable external configuration with USB PHY */
@@ -102,7 +97,7 @@ static int ehci_usb_probe(struct udevice *dev)
hcor = (struct ehci_hcor *)((phys_addr_t)hccr +
HC_LENGTH(ehci_readl(&(hccr)->cr_capbase)));
- ret = board_prepare_usb(USB_INIT_HOST);
+ ret = board_usb_init(0, USB_INIT_HOST);
if (ret < 0)
return ret;
@@ -124,7 +119,7 @@ static int ehci_usb_remove(struct udevice *dev)
reset_usb_phy(p);
- ret = board_prepare_usb(USB_INIT_DEVICE); /* Board specific hook */
+ ret = board_usb_init(0, USB_INIT_DEVICE); /* Board specific hook */
if (ret < 0)
return ret;
--
2.18.0
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[U-Boot] [PATCH 1/1] dm: video: adjust struct vidconsole_priv description
The third component of struct vidconsole_priv is ycur.
Signed-off-by: Heinrich Schuchardt
---
include/video_console.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/video_console.h b/include/video_console.h
index 63af741778..44e7bdbe29 100644
--- a/include/video_console.h
+++ b/include/video_console.h
@@ -45,7 +45,7 @@ enum color_idx {
*
* @sdev: stdio device, acting as an output sink
* @xcur_frac: Current X position, in fractional units (VID_TO_POS(x))
- * @curr_row: Current Y position in pixels (0=top)
+ * @ycur: Current Y position in pixels (0=top)
* @rows: Number of text rows
* @cols: Number of text columns
* @x_charsize:Character width in pixels
--
2.18.0
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[U-Boot] [PATCH 1/1] MAINTAINERS: assign include/video*.h
The include/video*.h files are part of the drivers in drivers/video. So it makes sense to assign them to the same maintainer. Signed-off-by: Heinrich Schuchardt --- MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/MAINTAINERS b/MAINTAINERS index 5e740d85b9..ec9635a4c9 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -624,6 +624,7 @@ T: git git://git.denx.de/u-boot-video.git F: drivers/video/ F: common/lcd*.c F: include/lcd*.h +F: include/video*.h X86 M: Simon Glass -- 2.18.0 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] net: macb: Clean 64b dma addresses if they are not detected
On Wed, Sep 19, 2018 at 06:08:18PM +0200, Michal Simek wrote: > Clear ADDR64 dma bit in DMACFG register in case that HW_DMA_CAP_64B > is not detected on 64bit system. > The issue was observed when bootloader(u-boot) does not check macb > feature at DCFG6 register (DAW64_OFFSET) and enabling 64bit dma support > by default. Then macb driver is reading DMACFG register back and only > adding 64bit dma configuration but not cleaning it out. > > This is also align with other features which are also cleared if they are not > present. Hi Michal, > > Signed-off-by: Michal Simek > --- > > drivers/net/ethernet/cadence/macb_main.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/drivers/net/ethernet/cadence/macb_main.c > b/drivers/net/ethernet/cadence/macb_main.c > index 16e4ef7d7185..79707dff3f13 100644 > --- a/drivers/net/ethernet/cadence/macb_main.c > +++ b/drivers/net/ethernet/cadence/macb_main.c > @@ -2163,6 +2163,8 @@ static void macb_configure_dma(struct macb *bp) > #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT > if (bp->hw_dma_cap & HW_DMA_CAP_64B) > dmacfg |= GEM_BIT(ADDR64); > + else > + dmacfg &= ~GEM_BIT(ADDR64); > #endif I think you might want to do this clearing outside of the #ifdef. If CONFIG_ARCH_DMA_ADDR_T_64BIT is not defined, we'd want to make sure the ADDR64 is cleared. E.g something like: dmacfg &= ~GEM_BIT(ADDR64); #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT if (bp->hw_dma_cap & HW_DMA_CAP_64B) dmacfg |= GEM_BIT(ADDR64); #endif Same thing for the USE_HWSTAMP/PTP flags below. Best regards, Edgar > #ifdef CONFIG_MACB_USE_HWSTAMP > if (bp->hw_dma_cap & HW_DMA_CAP_PTP) > -- > 1.9.1 > ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 1/1] dm: video: check bounds for column and row
CSI H can be used to position the cursor. The calling application may specify a location that is beyond the limits of the screen. This may lead to an illegal memory access. Signed-off-by: Heinrich Schuchardt --- drivers/video/vidconsole-uclass.c | 8 1 file changed, 8 insertions(+) diff --git a/drivers/video/vidconsole-uclass.c b/drivers/video/vidconsole-uclass.c index f1d3ad3611..0c36a5de0a 100644 --- a/drivers/video/vidconsole-uclass.c +++ b/drivers/video/vidconsole-uclass.c @@ -213,6 +213,14 @@ static void vidconsole_escape_char(struct udevice *dev, char ch) s++;/* ; */ s = parsenum(s, ); + /* +* Ensure we stay in the bounds of the screen. +*/ + if (row >= priv->rows) + row = priv->rows - 1; + if (col >= priv->cols) + col = priv->cols - 1; + priv->ycur = row * priv->y_charsize; priv->xcur_frac = priv->xstart_frac + VID_TO_POS(col * priv->x_charsize); -- 2.18.0 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] net: macb: Clean 64b dma addresses if they are not detected
On Wed, Sep 19, 2018 at 11:08 AM Michal Simek wrote: > > Clear ADDR64 dma bit in DMACFG register in case that HW_DMA_CAP_64B > is not detected on 64bit system. > The issue was observed when bootloader(u-boot) does not check macb > feature at DCFG6 register (DAW64_OFFSET) and enabling 64bit dma support > by default. Then macb driver is reading DMACFG register back and only > adding 64bit dma configuration but not cleaning it out. > > This is also align with other features which are also cleared if they are not > present. > > Signed-off-by: Michal Simek Acked-by: Joe Hershberger ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 1/1] test/py: catch errors occurring when reading the console
On 09/19/2018 05:24 PM, Stephen Warren wrote: > On 09/18/2018 06:43 PM, Heinrich Schuchardt wrote: >> On 09/18/2018 07:23 PM, Stephen Warren wrote: >>> On 09/18/2018 11:21 AM, Heinrich Schuchardt wrote: Spawn.exept has a try block without 'except'. If no output is available an OSError may arise. Catch this exception and continue testing. Signed-off-by: Heinrich Schuchardt Reviewed-by: Simon Glass --- I suggest that Alex takes the patch because we need it when working on the efi-next branch. v2 replace TAB by spaces fix typo in subject >>> >>> I'll point out that I still object to this. >> >> On 09/18/2018 07:06 PM, Stephen Warren wrote: >>> This doesn't make sense at all. It catches all errors and ignores them. >>> It'll turn any error condition into a timeout (presumably, the expected >>> data being waited for will never appear) rather than dealing with it >>> immediately (due to the thrown exception). Why is this needed? >> >> When the py test is running it is connected via pipes to the U-Boot >> process. If the U-Boot process ends due to a segmentation fault the >> pipes are broken. Trying to read from a broken pipe results in an >> OSError. >> >> Before this patch this leads to an uncaught error in the Python script. >> The output that has occured up to this point is lost and not displayed. >> All further tests for the configuration are not run. > > Ah. I think that's because Python is throwing an error rather than an > exception. I would have assumed that py.test caught errors as well as > exceptions, but perhaps not. I think what we should do here is catch > errors and translate them into a new thrown exception. That way, > everything outside the function would treat this as just another type of > exception, and hence still capture/flush the output, mark the test > immediately failed rather than having to wait for a timeout, etc. > Hello Stephen, the above confuses me. OSError is an exception. What do you mean by error in this context? The method Spawn.expect() is used to compare actual output to expected output. If a pipe is closed, this is obviously the end of the output. Why should we treat it differently to any other end of output? The except OSError statement is right at the end of the method. Why would you expect the method to wait for a timeout? If the OSError excepton is caught, the method returns None and the test is known to have failed. Best regards Heinrich ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] uclass: Use uclass_foreach_dev() macro instead of open coding
On Wed, Sep 19, 2018 at 09:30:37AM -0600, Simon Glass wrote:
> Hi,
>
> On 18 September 2018 at 02:08, Liviu Dudau wrote:
> >
> > On Tue, Sep 18, 2018 at 04:06:13AM +0200, Simon Glass wrote:
> > > On 17 September 2018 at 10:44, Liviu Dudau
> > > wrote:
> > > > Use the uclass_foreach_dev() macro instead of the open coded version.
> > > >
> > > > Signed-off-by: Liviu Dudau
> > > > ---
> > > > drivers/core/uclass.c | 2 +-
> > > > 1 file changed, 1 insertion(+), 1 deletion(-)
> > >
> > > Reviewed-by: Simon Glass
> > >
> > > Perhaps you could also convert a few usages?
> >
> > Not sure what you mean. Are you suggesting that I should convert more of
> > the code that uses the open coded version into uclass_foreach_dev() ?
>
> Yes. After all, at present your macro is just dead code :-)
I think there is some confusion here. I didn't write the macro, it is
present in include/dm/uclass.h since you have introduced it in commit
6494d708bfc630ac0
("dm: Add base driver model support"). All I have done was to notice
that in uclass.c the list_for_each_entry() line can be replaced by the
macro with the same effect.
I also didn't get what you meant by "your macro is just dead code".
Best regards,
Liviu
>
> Regards,
> Simon
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| I would like to |
| fix the world, |
| but they're not |
| giving me the |
\ source code! /
---
¯\_(ツ)_/¯
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[U-Boot] [PATCH] net: macb: Clean 64b dma addresses if they are not detected
Clear ADDR64 dma bit in DMACFG register in case that HW_DMA_CAP_64B is not detected on 64bit system. The issue was observed when bootloader(u-boot) does not check macb feature at DCFG6 register (DAW64_OFFSET) and enabling 64bit dma support by default. Then macb driver is reading DMACFG register back and only adding 64bit dma configuration but not cleaning it out. This is also align with other features which are also cleared if they are not present. Signed-off-by: Michal Simek --- drivers/net/ethernet/cadence/macb_main.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/net/ethernet/cadence/macb_main.c b/drivers/net/ethernet/cadence/macb_main.c index 16e4ef7d7185..79707dff3f13 100644 --- a/drivers/net/ethernet/cadence/macb_main.c +++ b/drivers/net/ethernet/cadence/macb_main.c @@ -2163,6 +2163,8 @@ static void macb_configure_dma(struct macb *bp) #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT if (bp->hw_dma_cap & HW_DMA_CAP_64B) dmacfg |= GEM_BIT(ADDR64); + else + dmacfg &= ~GEM_BIT(ADDR64); #endif #ifdef CONFIG_MACB_USE_HWSTAMP if (bp->hw_dma_cap & HW_DMA_CAP_PTP) -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 2/2] colibri_imx7: prime get_ram_size() using imx_ddr_size()
Hi,
On 9/19/18 4:01 AM, Marcel Ziswiler wrote:
> From: Fabio Estevam
>
> Rather than passing a hardcoded maxsize to the generic get_ram_size()
> function use the i.MX 7 specific imx_ddr_size() function, which extracts
> the memory size at runtime by reading the DDR controller registers.
>
> This is a purely cosmetic change as the generic get_ram_size() function
> already took care of properly automatically detecting 256MB, 512MB or 1GB
> modules.
>
> Signed-off-by: Fabio Estevam
> Signed-off-by: Marcel Ziswiler
Hm, with that we take the MMDC register information as the upper bound, and use
regular U-Boot get_ram_size() to determine size by poking memory addresses.
Seems sensible.
Acked-by: Stefan Agner
Fabio, I guess other boards use SPL to use different MMDC configuration for
different memory size? Is there a downside doing this size over-provisioning?
--
Stefan
>
> ---
>
> board/toradex/colibri_imx7/colibri_imx7.c | 2 +-
> include/configs/colibri_imx7.h| 1 -
> 2 files changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/board/toradex/colibri_imx7/colibri_imx7.c
> b/board/toradex/colibri_imx7/colibri_imx7.c
> index 2b7591eb00..a4c99626b4 100644
> --- a/board/toradex/colibri_imx7/colibri_imx7.c
> +++ b/board/toradex/colibri_imx7/colibri_imx7.c
> @@ -52,7 +52,7 @@ DECLARE_GLOBAL_DATA_PTR;
>
> int dram_init(void)
> {
> - gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
> + gd->ram_size = get_ram_size((void *)PHYS_SDRAM, imx_ddr_size());
>
> return 0;
> }
> diff --git a/include/configs/colibri_imx7.h b/include/configs/colibri_imx7.h
> index ff6bd678cf..02849ba35f 100644
> --- a/include/configs/colibri_imx7.h
> +++ b/include/configs/colibri_imx7.h
> @@ -14,7 +14,6 @@
> #include "mx7_common.h"
>
> /*#define CONFIG_DBG_MONITOR*/
> -#define PHYS_SDRAM_SIZE SZ_1G
>
> /* Size of malloc() pool */
> #define CONFIG_SYS_MALLOC_LEN(32 * SZ_1M)
>
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Re: [U-Boot] [PATCH] i2c: rcar_iic: Scale delays
On 09/19/2018 04:52 PM, Heiko Schocher wrote: > Hello Marek, > > Am 19.09.2018 um 16:31 schrieb Marek Vasut: >> On 09/19/2018 02:42 PM, Marek Vasut wrote: >>> The delays in this driver used to depend on an incorrect timer >>> frequency. >>> This was corrected in 7984ac8d1635, which caused this driver to function >>> incorrectly. Scale the delays accordingly to repair the malfunction. >>> >>> Signed-off-by: Marek Vasut >>> Cc: Nobuhiro Iwamatsu >> >> This is wrong, ignore. > > What is wrong ? This patch? > > May a define for the delay value is better here ... > > Hmm, thinking about it .. is this driver really only working with > correct delays ? The delays are correct and this driver is correct too, the timer was misconfigured, it's fixed by a different patch. -- Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] uclass: Use uclass_foreach_dev() macro instead of open coding
Hi, On 18 September 2018 at 02:08, Liviu Dudau wrote: > > On Tue, Sep 18, 2018 at 04:06:13AM +0200, Simon Glass wrote: > > On 17 September 2018 at 10:44, Liviu Dudau wrote: > > > Use the uclass_foreach_dev() macro instead of the open coded version. > > > > > > Signed-off-by: Liviu Dudau > > > --- > > > drivers/core/uclass.c | 2 +- > > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > Reviewed-by: Simon Glass > > > > Perhaps you could also convert a few usages? > > Not sure what you mean. Are you suggesting that I should convert more of > the code that uses the open coded version into uclass_foreach_dev() ? Yes. After all, at present your macro is just dead code :-) Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v4 12/17] board_f: Use static print_cpuinfo if CONFIG_CPU is active
Hi Mario, On 6 August 2018 at 02:23, Mario Six wrote: > When the DM CPU drivers are active, printing information about a CPU > should be delegated to a matching driver. > > Hence, add a static print_cpuinfo that implements this delegation when > DM CPU drivers are active. > > Reviewed-by: Simon Glass > Signed-off-by: Mario Six > --- > > Notes: > v3 -> v4: > * Print error if CPU description could not be retrieved > * Improved error handling and debug reporting > * Added documentation > > v2 -> v3: > No changes > > v1 -> v2: > New in v2 > > common/board_f.c | 28 > include/init.h | 7 +++ > 2 files changed, 35 insertions(+) > I have applied this, but with a change to use CONFIG_IS_ENABLED(CPU). At present chromebook_link64 calls print_cpuinfo() from SPL, so we need something like this. Perhaps a better fix is to move the function into common/init ? Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 1/1] test/py: catch errors occurring when reading the console
Hi Heinrich, On 18 September 2018 at 18:43, Heinrich Schuchardt wrote: > On 09/18/2018 07:23 PM, Stephen Warren wrote: >> On 09/18/2018 11:21 AM, Heinrich Schuchardt wrote: >>> Spawn.exept has a try block without 'except'. >>> >>> If no output is available an OSError may arise. Catch this exception and >>> continue testing. >>> >>> Signed-off-by: Heinrich Schuchardt >>> Reviewed-by: Simon Glass >>> --- >>> I suggest that Alex takes the patch because we need it when working on >>> the >>> efi-next branch. >>> >>> v2 >>> replace TAB by spaces >>> fix typo in subject >> >> I'll point out that I still object to this. >> > > On 09/18/2018 07:06 PM, Stephen Warren wrote: >> This doesn't make sense at all. It catches all errors and ignores them. >> It'll turn any error condition into a timeout (presumably, the expected >> data being waited for will never appear) rather than dealing with it >> immediately (due to the thrown exception). Why is this needed? >> > > When the py test is running it is connected via pipes to the U-Boot > process. If the U-Boot process ends due to a segmentation fault the > pipes are broken. Trying to read from a broken pipe results in an OSError. Your explanation makes sense to me. Did I miss Stephen's objection? What is it? Can you please add the above paragraph or part of it to the commit message and to a code comment? Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 1/1] test/py: catch errors occurring when reading the console
On 09/18/2018 06:43 PM, Heinrich Schuchardt wrote: On 09/18/2018 07:23 PM, Stephen Warren wrote: On 09/18/2018 11:21 AM, Heinrich Schuchardt wrote: Spawn.exept has a try block without 'except'. If no output is available an OSError may arise. Catch this exception and continue testing. Signed-off-by: Heinrich Schuchardt Reviewed-by: Simon Glass --- I suggest that Alex takes the patch because we need it when working on the efi-next branch. v2 replace TAB by spaces fix typo in subject I'll point out that I still object to this. On 09/18/2018 07:06 PM, Stephen Warren wrote: This doesn't make sense at all. It catches all errors and ignores them. It'll turn any error condition into a timeout (presumably, the expected data being waited for will never appear) rather than dealing with it immediately (due to the thrown exception). Why is this needed? When the py test is running it is connected via pipes to the U-Boot process. If the U-Boot process ends due to a segmentation fault the pipes are broken. Trying to read from a broken pipe results in an OSError. Before this patch this leads to an uncaught error in the Python script. The output that has occured up to this point is lost and not displayed. All further tests for the configuration are not run. Ah. I think that's because Python is throwing an error rather than an exception. I would have assumed that py.test caught errors as well as exceptions, but perhaps not. I think what we should do here is catch errors and translate them into a new thrown exception. That way, everything outside the function would treat this as just another type of exception, and hence still capture/flush the output, mark the test immediately failed rather than having to wait for a timeout, etc. ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PULL] Please pull u-boot-imx
Hi Tom, please pull from u-boot-imx with following changes: - changes in pico-* boards - fix imx6ull pinmux Thanks, Stefano The following changes since commit b57f1895b669e3fbdca486e7c40dfea00f22bb93: Merge git://git.denx.de/u-boot-x86 (2018-09-17 08:04:25 -0400) are available in the Git repository at: git://www.denx.de/git/u-boot-imx.git master for you to fetch changes up to f7df8932ccaec97c8c422de8adadb3a0491543ed: pico-imx7d: Add a new defconfig with PICO-Hobbit selected (2018-09-18 16:55:21 +0200) Fabio Estevam (8): pico-imx6ul: Convert to distro config pico-imx6ul: Convert to SPL pico-imx6ul: Add fastboot support pico-imx6ul: Add bmode support pico-imx6ul: Add support for the 512MB module pico-imx6ul: Update the README file wandboard: README: Include the mx6qp variant in the list pico-imx6ul: Add instructions for booting in Falcon mode Heiko Schocher (1): imx: imx6ull: fix pinmux input_val for uart5 rx pin Lukasz Majewski (4): ARM: bootscript: Remove hard-coded rootpath from K+P's tpcboot.cmd ARM: bootscript: Replace tftpboot with dhcp when downloading kernel ARM: bootscript: Fix the nfsargs and addip in K+P's tpcboot.cmd ARM: bootscript: For nfsargs only use rootpath (and remove not needed serverip) Otavio Salvador (13): pico-imx6ul: Sync defconfig with new changes pico-imx6ul: Add bootmenu to choose the baseboard pico-imx6ul: Improve default DFU settings pico-imx6ul: Sync README with pico-imx7d pico-imx6ul: Add new pico-hobbit config pico-imx6ul: Remove CONFIG_FSL_USDHC from .h pico-imx6ul: Add Falcon mode support pico-imx6ul: Fix TechNexion spelling on MAINTAINERS file pico-imx6ul: Add PICO-Pi baseboard support pico-imx6ul: Add a new defconfig with PICO-Pi selected pico-imx7d: Fix TechNexion spelling on MAINTAINERS file pico-imx7d: Add PICO-Hobbit baseboard support pico-imx7d: Add a new defconfig with PICO-Hobbit selected Stefano Babic (1): Merge branch 'master' of git://git.denx.de/u-boot into master arch/arm/include/asm/arch-mx6/mx6ull_pins.h | 2 +- arch/arm/mach-imx/mx6/Kconfig | 1 + board/k+p/bootscripts/tpcboot.cmd | 12 +++- board/technexion/pico-imx6ul/MAINTAINERS| 12 +++- board/technexion/pico-imx6ul/Makefile | 2 +- board/technexion/pico-imx6ul/README | 138 board/technexion/pico-imx6ul/spl.c | 144 board/technexion/pico-imx7d/MAINTAINERS | 9 -- board/wandboard/README | 2 +- configs/pico-hobbit-imx6ul_defconfig| 53 ++ configs/pico-hobbit-imx7d_defconfig | 61 +++ configs/pico-imx6ul_defconfig | 39 +++-- configs/pico-pi-imx6ul_defconfig| 53 ++ include/configs/pico-imx6ul.h | 107 +--- include/configs/pico-imx7d.h| 5 +++- 15 files changed, 536 insertions(+), 104 deletions(-) create mode 100644 board/technexion/pico-imx6ul/spl.c create mode 100644 configs/pico-hobbit-imx6ul_defconfig create mode 100644 configs/pico-hobbit-imx7d_defconfig create mode 100644 configs/pico-pi-imx6ul_defconfig -- = DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de = ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] Please pull u-boot-marvell/master
Hi Tom,
please pull the Marvell U-Boot patches with these changes:
- Multiples updates to the turris boards / platform
- Changes / enhancements to the Marvell PHY drivers, mainly
to support the turris platform
- Many fixes and enhancements to the pxa3xx NAND driver
- Fixes for the UART boot mode in kwboot
- Misc minor changes to other 32bit and 64bit boards
Thanks,
Stefan
The following changes since commit b57f1895b669e3fbdca486e7c40dfea00f22bb93:
Merge git://git.denx.de/u-boot-x86 (2018-09-17 08:04:25 -0400)
are available in the Git repository at:
git://www.denx.de/git/u-boot-marvell.git
for you to fetch changes up to e32ac37119394f2d3c579b2cdd549bed59fb583f:
arm: mvebu: clearfog: enable eMMC boot partitions support (2018-09-19
14:00:06 +0200)
Baruch Siach (4):
doc/git-mailrc: add Stefan Roese to the kirkwood alias
arm64: mvebu: armada-8k: support environment in SD/eMMC
dts: mvebu: mcbin: drop redundant SD slot node
arm: mvebu: clearfog: enable eMMC boot partitions support
Boris Brezillon (1):
mtd: nand: pxa3xx: Fix READOOB implementation
Chris Packham (2):
Revert "arm: mvebu: fix boot from UART when in fallback mode"
ARM: mach-mvebu: handle fall-back to UART boot
David Sniatkiwicz (1):
fix: nand: pxa3xx: Add WA for eliminating flash ready timeout
Evgeni Dobrev (1):
Kirkwood: NAS220: remove bootdelay from CONFIG_EXTRA_ENV_SETTINGS
Jon Nettleton (1):
tools: kwboot: Make kwboot more robust on a38x
Konstantin Porotchkin (7):
mtd: nand: pxa3xx: add support for Toshiba flash
fix: nand: Replace hardcoded page chunk size with calculated one
nand: pxa3xx: cosmetic: add comments to the timing layout structures
nand: pxa3xx: Add support for 8KB page 4 and 8 bit ECC NAND
fix: env: Fix the SPI flash device setup for DM mode
fix: mvebu: Add SPI parameters for environment setup
fix: cmd: mvebu: Exclude mvebu commands from SPL builds
Marek Behún (6):
phy: marvell: Support changing SERDES map in board file
clk: armada-37xx-periph: Support changing clock parent and rate
board: turris_mox: Fix watchdog macro name
board: turris_mox: Enable PCI in defconfig
arch/arm/dts: Update Turris Mox device tree
board: turris_mox: Fixup U-Boot's device tree if PCIe connected
Ofer Heifetz (10):
mtd: nand: pxa3xx_nand: Increase initial buffer size
mtd: nand: pxa3xx_nand: use nand_to_mtd()
mtd: nand: pxa3xx_nand: sync pxa3xx_nand_set_sdr_timing()
mtd: nand: pxa3xx_nand: fix early spurious interrupt
mtd: nand: pxa3xx-nand: fix random command timeouts
nand: pxa3xx: Increase READ_ID buffer and make the size static
mtd: pxa3xx_nand: Increase the initial chunk size
mtd: pxa3xx_nand: Fix initial controller configuration
mtd: pxa3xx_nand: Simplify pxa3xx_nand_scan
mtd: nand: pxa3xx_nand: add support for partial chunks
Rabeeh Khoury (1):
phy: marvell: add SATA comphy RX/TX polarity invert support
Victor Axelrod (1):
mtd: nand: pxa3xx: add support for 2KB 8-bit flash
MAINTAINERS | 3 +-
arch/arm/dts/armada-3720-turris-mox.dts | 17 +-
arch/arm/dts/armada-8040-mcbin.dts | 8 -
arch/arm/mach-mvebu/armada8k/cpu.c | 24 ++
arch/arm/mach-mvebu/include/mach/soc.h | 8 +-
arch/arm/mach-mvebu/spl.c | 15 +-
board/CZ.NIC/turris_mox/turris_mox.c| 88 -
cmd/Makefile| 3 +-
configs/turris_mox_defconfig| 6 +
doc/git-mailrc | 2 +-
drivers/clk/mvebu/armada-37xx-periph.c | 130 ++-
drivers/mtd/nand/pxa3xx_nand.c | 447
drivers/phy/marvell/comphy_a3700.h | 2 +-
drivers/phy/marvell/comphy_core.c | 12 +-
drivers/phy/marvell/{comphy.h => comphy_core.h} | 16 +-
drivers/phy/marvell/comphy_cp110.c | 21 +-
drivers/phy/marvell/comphy_hpipe.h | 6 +
drivers/phy/marvell/comphy_mux.c| 2 +-
env/sf.c| 3 +-
include/configs/clearfog.h | 4 +
include/configs/db-88f6820-gp.h | 6 +
include/configs/mvebu_armada-8k.h | 3 +
include/configs/nas220.h| 1 -
include/mvebu/comphy.h | 22 ++
tools/kwboot.c | 14 +-
25 files changed, 664 insertions(+), 199 deletions(-)
rename drivers/phy/marvell/{comphy.h => comphy_core.h} (96%)
create mode 100644 include/mvebu/comphy.h
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Re: [U-Boot] [PATCH] i2c: rcar_iic: Scale delays
Hello Marek, Am 19.09.2018 um 16:31 schrieb Marek Vasut: On 09/19/2018 02:42 PM, Marek Vasut wrote: The delays in this driver used to depend on an incorrect timer frequency. This was corrected in 7984ac8d1635, which caused this driver to function incorrectly. Scale the delays accordingly to repair the malfunction. Signed-off-by: Marek Vasut Cc: Nobuhiro Iwamatsu This is wrong, ignore. What is wrong ? This patch? May a define for the delay value is better here ... Hmm, thinking about it .. is this driver really only working with correct delays ? bye, Heiko -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-52 Fax: +49-8142-66989-80 Email: h...@denx.de ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH] ARM: rmobile: Repair TMU clock on Gen2
The CPfi/4 is derived from XTAL clock and is not fixed. Undo the previous commit 7984ac8d1635aebd11175c96b07f937a39f0384d. Signed-off-by: Marek Vasut --- include/configs/rcar-gen2-common.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/rcar-gen2-common.h b/include/configs/rcar-gen2-common.h index df13d864bd..a79e877fd3 100644 --- a/include/configs/rcar-gen2-common.h +++ b/include/configs/rcar-gen2-common.h @@ -60,6 +60,6 @@ #define CONFIG_TMU_TIMER #define CONFIG_SYS_TIMER_COUNTS_DOWN #define CONFIG_SYS_TIMER_COUNTER (TMU_BASE + 0xc)/* TCNT0 */ -#define CONFIG_SYS_TIMER_RATE (3250 / 4) /* CP/4 */ +#define CONFIG_SYS_TIMER_RATE (CONFIG_SYS_CLK_FREQ / 8) #endif /* __RCAR_GEN2_COMMON_H */ -- 2.18.0 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] i2c: rcar_iic: Scale delays
On 09/19/2018 02:42 PM, Marek Vasut wrote: > The delays in this driver used to depend on an incorrect timer frequency. > This was corrected in 7984ac8d1635, which caused this driver to function > incorrectly. Scale the delays accordingly to repair the malfunction. > > Signed-off-by: Marek Vasut > Cc: Nobuhiro Iwamatsu This is wrong, ignore. -- Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH V3 2/2] pci: Update documentation to make 'compatible' string optional
On 09/18/2018 04:02 PM, Simon Glass wrote: > Hi Marek, Hi, > On 18 September 2018 at 05:47, Marek Vasut wrote: >> >> On 09/14/2018 06:41 AM, Simon Glass wrote: >>> Hi Marex, >> >> It's Marek btw ... >> >>> On 11 September 2018 at 14:58, Marek Vasut wrote: Reword the documentation to make it clear the compatible string is now optional, yet still matching on it takes precedence over PCI IDs and PCI classes. Signed-off-by: Marek Vasut Cc: Simon Glass Cc: Tom Rini --- V3: No change V2: New patch --- doc/driver-model/pci-info.txt | 14 +- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/doc/driver-model/pci-info.txt b/doc/driver-model/pci-info.txt index e1701d1fbc..14364c5c75 100644 --- a/doc/driver-model/pci-info.txt +++ b/doc/driver-model/pci-info.txt @@ -34,11 +34,15 @@ under that bus. Note that this is all done on a lazy basis, as needed, so until something is touched on PCI (eg: a call to pci_find_devices()) it will not be probed. -PCI devices can appear in the flattened device tree. If they do this serves to -specify the driver to use for the device. In this case they will be bound at -first. Each PCI device node must have a compatible string list as well as a - property, as defined by the IEEE Std 1275-1994 PCI bus binding document -v2.1. Note we must describe PCI devices with the same bus hierarchy as the +PCI devices can appear in the flattened device tree. If they do, their node +often contains extra information which cannot be derived from the PCI IDs or +PCI class of the device. Each PCI device node must have a property, as +defined by the IEEE Std 1275-1994 PCI bus binding document v2.1. Compatible +string list is optional and generally not needed, since PCI is discoverable >>> >>> I really don't like 'generally not needed'. How about 'generally not >>> essential'? Or that you can usually avoid it if desired. >> >> Must be a language nuance, but the compatible string is really not >> needed. I am starting to understand where this mindset of "compat >> strings are generally needed" comes from, which is the design of the >> virtual PCI devices in sandbox, but that's not the usual case. > > Well it's more than that, as I mentioned before. Finding a compatible > string in the source code is easier, and if we are matching with a DT > node anyway, makes more sense IMO. It's about as easy as finding PCI ID. And PCI is a discoverable bus, so using a compatible string is some obscure edge-case. > Anyway since DTs likely come from > the newly pleasant Linux we'll just end up with what they have there. > This mostly applies for things like x86 which don't use DT in Linux. > >> >>> I'd like to say that it is optional since U_BOOT_PCI_DEVICE() can be >>> used to specific the driver based on conditions like the PCI vendor/, >>> PCI class, etc. If U-Boot does not find a compatible string then it >>> will search these U_BOOT_PCI_DEVICE() records to find a driver; >>> assuming it finds one it will then search for the device-tree node >>> whose reg property matches the bus/device/function of the device, and >>> attached that node to the device so that it is accessible to the >>> driver. >> >> Can you rephrase it better then ? I can paste it into the docs. > > How about: > > The compatible string is optional since U_BOOT_PCI_DEVICE() can be > used to specific specify ? > the driver based on conditions like the PCI vendor/ > PCI class, etc. If U-Boot does not find a compatible string then it > will search these U_BOOT_PCI_DEVICE() records to find a driver; This implies the compatible string is preferred, it is not. > assuming it finds one it will then search for the device-tree node > whose reg property matches the bus/device/function of the device, and > attache that node to the device so that it is accessible to the > driver. > >> +bus, albeit there are justified exceptions. If the compatible string is +present, matching on it takes precedence over PCI IDs and PCI classes. + +Note we must describe PCI devices with the same bus hierarchy as the hardware, otherwise driver model cannot detect the correct parent/children relationship during PCI bus enumeration thus PCI devices won't be bound to their drivers accordingly. A working example like below: -- 2.18.0 >>> >>> Regards, >>> Simon >>> > > Regards, > Simon > -- Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH V2 1/2] pci: Support parsing PCI controller DT subnodes
On 09/19/2018 11:41 AM, Bin Meng wrote: > Hi Marek, > > On Wed, Sep 19, 2018 at 5:34 PM Marek Vasut wrote: >> >> On 09/19/2018 11:26 AM, Bin Meng wrote: >>> Hi Marek, >>> >>> On Wed, Sep 19, 2018 at 4:21 PM Marek Vasut wrote: On 09/18/2018 03:52 PM, Simon Glass wrote: > Hi Marek, > > On 18 September 2018 at 13:36, Marek Vasut wrote: >> >> On 09/14/2018 06:41 AM, Simon Glass wrote: >>> Hi Marek, >>> >>> On 10 September 2018 at 01:38, Marek Vasut >>> wrote: On 09/02/2018 03:07 AM, Simon Glass wrote: > Hi Marek, Hi, > On 1 September 2018 at 16:45, Marek Vasut > wrote: >> >> On 09/01/2018 11:50 PM, Simon Glass wrote: >>> Hi Marek, >>> >>> On 30 August 2018 at 07:42, Marek Vasut >>> wrote: On 08/30/2018 03:32 PM, Bin Meng wrote: > Hi Marek, > > On Thu, Aug 30, 2018 at 1:07 AM Marek Vasut > wrote: >> >> On 08/29/2018 05:15 PM, Bin Meng wrote: >>> +Simon >>> >>> Hi Marek, >>> >>> On Wed, Aug 29, 2018 at 10:22 PM Marek Vasut >>> wrote: On 08/24/2018 08:27 PM, Marek Vasut wrote: > The PCI controller can have DT subnodes describing extra > properties > of particular PCI devices, ie. a PHY attached to an EHCI > controller > on a PCI bus. This patch parses those DT subnodes and assigns > a node > to the PCI device instance, so that the driver can extract > details > from that node and ie. configure the PHY using the PHY > subsystem. > > Signed-off-by: Marek Vasut > Cc: Simon Glass > Cc: Tom Rini Well, bump ? This is the only missing patch to get my hardware working properly. >>> >>> I don't think we ever had an agreement on the v1 patch. Simon >>> had a >>> long email that pointed out what Linux does seems like a >>> 'fallback' to >>> find a node with no compatible string. >>> >>> Back to this, if we have to go with this way, please create a >>> test >>> case to cover this scenario. >> >> The fact that it works on a particular board is not tested >> enough? >> Do we need a custom, special, synthetic test ? >> > > I believe that's always been the requirement against the DM code > changes. I was requested in the past when I changed something in > the > DM and I see other people were asked to do so. Like Alex said, it > does > not mean this patch was not tested enough, but to ensure future > commits won't break this. So, do you have any suggestion how to implement this test ? It seems Alex posed the same question. It doesn't seem to be trivial in the context of sandbox. >>> >>> I suppose you need a PCI_DEVICE() declaration for sandbox, with an >>> associated DT node and no compatible string. Then check that you can >>> locate the device and that it read a DT property correctly. >> >> Is there any example of this stuff already ? > > See the bottom of swap_case.c. You might be able to add a new one of > those, > > If you look at pci-controller2 in test.dts it has a device with a > compatible string. You could try adding a second device with no > compatible string. And how does that test anything ? >>> >>> You can test that your code actually attaches the DT node to the >>> probed device. Without you code the test would fail. Wit it, it would >>> pass. >> >> Well it won't, because the sandbox swap_case.c requires the compatible. >> This all seems like a big hack to support virtual PCI devices. >> >> The driver binds with a compatible and then pins the read/write config >> reg accessors to emulate their return values. Those include PCI IDs. So >> you cannot instantiate virtual PCI device without this compatible string >> and thus also cannot write such a test easily. >> >> Now I also understand where this whole discussion about compatible >> strings came from though. > > The compatible string is needed for the emulation driver but not for > the thing that connects to it. However as things stand you can't > attach
Re: [U-Boot] [PATCH] arm: mvebu: clearfog: enable eMMC boot partitions support
On 13.09.2018 11:41, Baruch Siach wrote: The Clearfog SOM can optionally have eMMC installed. Enable support for eMMC boot partitions by default. Signed-off-by: Baruch Siach --- include/configs/clearfog.h | 4 1 file changed, 4 insertions(+) diff --git a/include/configs/clearfog.h b/include/configs/clearfog.h index 7d56dfd86e96..77ab6caf52c0 100644 --- a/include/configs/clearfog.h +++ b/include/configs/clearfog.h @@ -29,6 +29,10 @@ */ #define CONFIG_SYS_MMC_BASE MVEBU_SDIO_BASE +#ifdef CONFIG_CMD_MMC +#define CONFIG_SUPPORT_EMMC_BOOT +#endif + /* USB/EHCI configuration */ #define CONFIG_EHCI_IS_TDI Applied to u-boot-marvell/master Thanks, Stefan ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] phy: marvell: add SATA comphy RX/TX polarity invert support
On 06.09.2018 11:37, Baruch Siach wrote:
From: Rabeeh Khoury
This patch adds support to Armada 7k/8k comphy RX/TX lane swap. The
'phy-invert' DT property defines the inverted signals.
Signed-off-by: Rabeeh Khoury
Signed-off-by: Baruch Siach
---
drivers/phy/marvell/comphy_cp110.c | 19 +--
drivers/phy/marvell/comphy_hpipe.h | 6 ++
2 files changed, 23 insertions(+), 2 deletions(-)
diff --git a/drivers/phy/marvell/comphy_cp110.c
b/drivers/phy/marvell/comphy_cp110.c
index b0d5d5ca26b9..7dd968f00d79 100644
--- a/drivers/phy/marvell/comphy_cp110.c
+++ b/drivers/phy/marvell/comphy_cp110.c
@@ -641,7 +641,8 @@ static int comphy_usb3_power_up(u32 lane, void __iomem
*hpipe_base,
}
static int comphy_sata_power_up(u32 lane, void __iomem *hpipe_base,
- void __iomem *comphy_base, int cp_index)
+ void __iomem *comphy_base, int cp_index,
+ u32 invert)
{
u32 mask, data, i, ret = 1;
void __iomem *hpipe_addr = HPIPE_ADDR(hpipe_base, lane);
@@ -927,6 +928,19 @@ static int comphy_sata_power_up(u32 lane, void __iomem
*hpipe_base,
reg_set(hpipe_addr + HPIPE_PWR_CTR_REG,
0x0 << HPIPE_PWR_CTR_RST_DFE_OFFSET,
HPIPE_PWR_CTR_RST_DFE_MASK);
+
+ /* Set RX / TX swaps */
+ data = mask = 0;
+ if (invert & PHY_POLARITY_TXD_INVERT) {
+ data |= (1 << HPIPE_SYNC_PATTERN_TXD_SWAP_OFFSET);
+ mask |= HPIPE_SYNC_PATTERN_TXD_SWAP_MASK;
+ }
+ if (invert & PHY_POLARITY_RXD_INVERT) {
+ data |= (1 << HPIPE_SYNC_PATTERN_RXD_SWAP_OFFSET);
+ mask |= HPIPE_SYNC_PATTERN_RXD_SWAP_MASK;
+ }
+ reg_set(hpipe_addr + HPIPE_SYNC_PATTERN_REG, data, mask);
+
/* SW reset for interupt logic */
reg_set(hpipe_addr + HPIPE_PWR_CTR_REG,
0x1 << HPIPE_PWR_CTR_SFT_RST_OFFSET,
@@ -2006,7 +2020,8 @@ int comphy_cp110_init(struct chip_serdes_phy_config
*ptr_chip_cfg,
case PHY_TYPE_SATA3:
ret = comphy_sata_power_up(
lane, hpipe_base_addr, comphy_base_addr,
- ptr_chip_cfg->cp_index);
+ ptr_chip_cfg->cp_index,
+ serdes_map[lane].invert);
break;
case PHY_TYPE_USB3_HOST0:
case PHY_TYPE_USB3_HOST1:
diff --git a/drivers/phy/marvell/comphy_hpipe.h
b/drivers/phy/marvell/comphy_hpipe.h
index d99da7b9ffcd..a692035c9417 100644
--- a/drivers/phy/marvell/comphy_hpipe.h
+++ b/drivers/phy/marvell/comphy_hpipe.h
@@ -221,6 +221,12 @@
(0x7 << HPIPE_LOOPBACK_SEL_OFFSET)
#define HPIPE_SYNC_PATTERN_REG 0x090
+#define HPIPE_SYNC_PATTERN_TXD_SWAP_OFFSET 10
+#define HPIPE_SYNC_PATTERN_TXD_SWAP_MASK \
+ (0x1 << HPIPE_SYNC_PATTERN_TXD_SWAP_OFFSET)
+#define HPIPE_SYNC_PATTERN_RXD_SWAP_OFFSET 11
+#define HPIPE_SYNC_PATTERN_RXD_SWAP_MASK \
+ (0x1 << HPIPE_SYNC_PATTERN_RXD_SWAP_OFFSET)
#define HPIPE_INTERFACE_REG 0x94
#define HPIPE_INTERFACE_GEN_MAX_OFFSET10
Applied to u-boot-marvell/master
Thanks,
Stefan
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Re: [U-Boot] [PATCH 5/5] defconfig: db-88f6820-gp: Add bubt command to the build
On 29.08.2018 15:34, kos...@marvell.com wrote: From: Konstantin Porotchkin Add Marvell bubt command to db-88f6820-gp defconfig Signed-off-by: Konstantin Porotchkin Cc: Igal Liberman Cc: Stefan Roese --- configs/db-88f6820-gp_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/db-88f6820-gp_defconfig b/configs/db-88f6820-gp_defconfig index 131262d..4a8fa2e 100644 --- a/configs/db-88f6820-gp_defconfig +++ b/configs/db-88f6820-gp_defconfig @@ -39,6 +39,7 @@ CONFIG_CMD_EXT2=y CONFIG_CMD_EXT4=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y +CONFIG_CMD_MVEBU_BUBT=y CONFIG_EFI_PARTITION=y # CONFIG_PARTITION_UUIDS is not set # CONFIG_SPL_PARTITION_UUIDS is not set Dropped for now, as a result of your discussion in this thread. Thanks, Stefan ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 4/5] cmd: mvebu: bubt: Add support for legacy Marvell SoCs
On 29.08.2018 15:34, kos...@marvell.com wrote:
From: Konstantin Porotchkin
Add support for image load and basic verification in bubt
for legacy Marvell SoCs (A38x, A39x, ...)
Signed-off-by: Konstantin Porotchkin
Cc: Igal Liberman
Cc: Stefan Roese
---
cmd/mvebu/bubt.c | 75 +---
1 file changed, 72 insertions(+), 3 deletions(-)
diff --git a/cmd/mvebu/bubt.c b/cmd/mvebu/bubt.c
index b4d371f..e10d079 100644
--- a/cmd/mvebu/bubt.c
+++ b/cmd/mvebu/bubt.c
@@ -83,6 +83,33 @@ struct mvebu_image_info {
u32 encrypt_start_offset;
u32 encrypt_size;
};
+
+#else /* Older Armada SoCs - A38x, A39x, ... */
+
+#defineLEGACY_HDR_VERSION 1
+
+struct legacy_image_header {
+/* typenamebyte order */
+ u8 block_id; /* 0 */
+ u8 flags; /* 1 */
+ u16 nand_pge_size; /* 2-3 */
+ u32 block_size; /* 4-7 */
+ u8 version;/* 8 */
+ u8 hdr_size_msb; /* 9 */
+ u16 hdr_size_lsb; /* 10-11 */
+ u32 source_addr;/* 12-15 */
+ u32 destination_addr; /* 16-19 */
+ u32 execution_addr; /* 20-23 */
+ u8 options;/* 24 */
+ u8 nand_block_size;/* 25 */
+ u8 nand_technology;/* 26 */
+ u8 rsvd4; /* 27 */
+ u16 rsvd2; /* 28-29 */
+ u8 ext;/* 30 */
+ u8 checksum; /* 31 */
+
+};
+
#endif /* CONFIG_ARMADA_XXX */
struct bubt_dev {
@@ -618,11 +645,53 @@ static int check_image_header(void)
return 0;
}
-#else /* Not ARMADA? */
+#else /* Legacy SoCs */
+u8 do_checksum8(u8 *start, u32 len)
+{
+ u8 sum = 0;
+ u8 *startp = start;
+
+ do {
+ sum += *startp;
+ startp++;
+ } while (--len);
+
+ return sum;
+}
+
static int check_image_header(void)
{
- printf("bubt cmd does not support this SoC device or family!\n");
- return -ENOEXEC;
+ struct legacy_image_header *hdr =
+ (struct legacy_image_header *)get_load_addr();
+ u32 header_len = hdr->hdr_size_lsb + (hdr->hdr_size_msb << 16);
+ u8 checksum;
+ u8 checksum_ref = hdr->checksum;
+
+ /*
+* For now compare checksum, and header version. Later we can
+* verify more stuff on the header like interface type, etc
+*/
+ if (hdr->version != LEGACY_HDR_VERSION) {
+ printf("ERROR: Bad HDR Version 0x%x != 0x%x\n",
+ hdr->version, LEGACY_HDR_VERSION);
+ return -ENOEXEC;
+ }
+
+ /* The checksum value is discarded from checksum calculation */
+ hdr->checksum = 0;
+
+ checksum = do_checksum8((u8 *)hdr, header_len);
+ if (checksum != checksum_ref) {
+ printf("Error: Bad Image checksum. 0x%x != 0x%x\n",
+ checksum, checksum_ref);
+ return -ENOEXEC;
+ }
+
+ /* Restore the checksum before writing */
+ hdr->checksum = checksum_ref;
+ printf("Image checksum...OK!\n");
+
+ return 0;
}
#endif
Dropped for now, as a result of your discussion in this thread.
Thanks,
Stefan
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Re: [U-Boot] [PATCH 3/5] fix: cmd: mvebu: Eclude mvebu commands from SPL builds
On 29.08.2018 15:34, kos...@marvell.com wrote: From: Konstantin Porotchkin Exclude mvebu commands from SPL builds Signed-off-by: Konstantin Porotchkin Cc: Igal Liberman Cc: Stefan Roese --- cmd/Makefile | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/cmd/Makefile b/cmd/Makefile index 3487c80..a61fab6 100644 --- a/cmd/Makefile +++ b/cmd/Makefile @@ -163,12 +163,13 @@ obj-$(CONFIG_CMD_BLOB) += blob.o obj-$(CONFIG_CMD_AVB) += avb.o obj-$(CONFIG_X86) += x86/ + +obj-$(CONFIG_ARCH_MVEBU) += mvebu/ endif # !CONFIG_SPL_BUILD # core command obj-y += nvedit.o -obj-$(CONFIG_ARCH_MVEBU) += mvebu/ obj-$(CONFIG_TI_COMMON_CMD_OPTIONS) += ti/ filechk_data_gz = (echo "static const char data_gz[] ="; cat $< | scripts/bin2c; echo ";") Applied to u-boot-marvell/master Thanks, Stefan ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 2/5] fix: mvebu: Add SPI parameters for environment setup
On 29.08.2018 15:34, kos...@marvell.com wrote: From: Konstantin Porotchkin Add definitions for CONFIG_ENV_SPI_BUS and CONFIG_ENV_SPI_CS to Armada-388-GP board configuration Signed-off-by: Konstantin Porotchkin Cc: Igal Liberman Cc: Stefan Roese --- include/configs/db-88f6820-gp.h | 6 ++ 1 file changed, 6 insertions(+) diff --git a/include/configs/db-88f6820-gp.h b/include/configs/db-88f6820-gp.h index ac810b0..f2aa21a 100644 --- a/include/configs/db-88f6820-gp.h +++ b/include/configs/db-88f6820-gp.h @@ -28,6 +28,12 @@ #define CONFIG_SYS_I2C_SLAVE 0x0 #define CONFIG_SYS_I2C_SPEED 10 +/* + * SPI Flash configuration for the environemnt access + */ +#define CONFIG_ENV_SPI_BUS 0 +#define CONFIG_ENV_SPI_CS 0 + /* SPI NOR flash default params, used by sf commands */ #define CONFIG_SF_DEFAULT_SPEED 100 #define CONFIG_SF_DEFAULT_MODESPI_MODE_3 Applied to u-boot-marvell/master Thanks, Stefan ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 1/5] fix: env: Fix the SPI flash device setup for DM mode
On 29.08.2018 15:34, kos...@marvell.com wrote:
From: Konstantin Porotchkin
For some reason the spi_flash_probe_bus_cs() is called
inside the setup_flash_device() with zero values in place
of configurated SPI flash mode and maximum flash speed.
This code causes HALT error during startup environment
relocation on some platforms - namely Armada-38x-GP board.
Fix the function call by replacing zeros with the appropriate
values - CONFIG_ENV_SPI_MAX_HZ and CONFIG_ENV_SPI_MODE.
Signed-off-by: Konstantin Porotchkin
Cc: Igal Liberman
Cc: Stefan Roese
---
env/sf.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/env/sf.c b/env/sf.c
index 4945105..2e3c600 100644
--- a/env/sf.c
+++ b/env/sf.c
@@ -58,7 +58,8 @@ static int setup_flash_device(void)
/* speed and mode will be read from DT */
ret = spi_flash_probe_bus_cs(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS,
-0, 0, );
+CONFIG_ENV_SPI_MAX_HZ, CONFIG_ENV_SPI_MODE,
+);
if (ret) {
set_default_env("spi_flash_probe_bus_cs() failed", 0);
return ret;
Applied to u-boot-marvell/master
Thanks,
Stefan
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[U-Boot] [PATCH] ARM: dts: rmobile: Reinstate missing i2c6 on Porter
The I2C6 is used to communicate with the PMIC and it was removed
during DT sync with Linux 4.17. Reinstate it.
Signed-off-by: Marek Vasut
Cc: Nobuhiro Iwamatsu
---
arch/arm/dts/r8a7791-porter.dts | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/dts/r8a7791-porter.dts b/arch/arm/dts/r8a7791-porter.dts
index f2d5723fbd..fa9a57d770 100644
--- a/arch/arm/dts/r8a7791-porter.dts
+++ b/arch/arm/dts/r8a7791-porter.dts
@@ -372,6 +372,11 @@
clock-frequency = <40>;
};
+ {
+ status = "okay";
+ clock-frequency = <40>;
+};
+
{
status = "okay";
};
--
2.18.0
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[U-Boot] [PATCH] i2c: rcar_iic: Scale delays
The delays in this driver used to depend on an incorrect timer frequency.
This was corrected in 7984ac8d1635, which caused this driver to function
incorrectly. Scale the delays accordingly to repair the malfunction.
Signed-off-by: Marek Vasut
Cc: Nobuhiro Iwamatsu
---
drivers/i2c/rcar_iic.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/i2c/rcar_iic.c b/drivers/i2c/rcar_iic.c
index e91fc86c1a..86a74430ec 100644
--- a/drivers/i2c/rcar_iic.c
+++ b/drivers/i2c/rcar_iic.c
@@ -51,7 +51,7 @@ static void sh_irq_dte(struct udevice *dev)
for (i = 0; i < IRQ_WAIT; i++) {
if (RCAR_IC_DTE & readb(priv->base + RCAR_IIC_ICSR))
break;
- udelay(10);
+ udelay(3);
}
}
@@ -65,7 +65,7 @@ static int sh_irq_dte_with_tack(struct udevice *dev)
break;
if (RCAR_IC_TACK & readb(priv->base + RCAR_IIC_ICSR))
return -ETIMEDOUT;
- udelay(10);
+ udelay(3);
}
return 0;
}
@@ -78,7 +78,7 @@ static void sh_irq_busy(struct udevice *dev)
for (i = 0; i < IRQ_WAIT; i++) {
if (!(RCAR_IC_BUSY & readb(priv->base + RCAR_IIC_ICSR)))
break;
- udelay(10);
+ udelay(3);
}
}
@@ -118,7 +118,7 @@ static int rcar_iic_read_common(struct udevice *dev, struct
i2c_msg *msg)
if (rcar_iic_set_addr(dev, msg->addr, 1) != 0)
goto err;
- udelay(10);
+ udelay(3);
writeb(RCAR_IIC_ICCR_ICE | RCAR_IIC_ICCR_SCP,
priv->base + RCAR_IIC_ICCR);
@@ -151,7 +151,7 @@ static int rcar_iic_write_common(struct udevice *dev,
struct i2c_msg *msg)
if (rcar_iic_set_addr(dev, msg->addr, 0) != 0)
goto err;
- udelay(10);
+ udelay(3);
for (i = 0; i < msg->len; i++) {
writeb(msg->buf[i], priv->base + RCAR_IIC_ICDR);
--
2.18.0
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Re: [U-Boot] [PATCH 16/19] fix: nand: Replace hardcoded page chunk size with calculated one
On 29.08.2018 10:56, kos...@marvell.com wrote:
From: Konstantin Porotchkin
Replace the hardcoded value of page chink with value that
depends on flash page size and ECC strength.
This fixes nand access errors for 2K page flashes with 8-bit ECC.
Move the initial flash commannd function assignment past the ECC
structures initialization for eliminating usage of hardcoded page
chunk size value.
Signed-off-by: Konstantin Porotchkin
Reviewed-by: Igal Liberman
Cc: Stefan Roese
Cc: Simon Glass
---
drivers/mtd/nand/pxa3xx_nand.c | 42 --
1 file changed, 20 insertions(+), 22 deletions(-)
diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c
index a7b9864..a7ca28c 100644
--- a/drivers/mtd/nand/pxa3xx_nand.c
+++ b/drivers/mtd/nand/pxa3xx_nand.c
@@ -24,7 +24,6 @@ DECLARE_GLOBAL_DATA_PTR;
#define TIMEOUT_DRAIN_FIFO5 /* in ms */
#define CHIP_DELAY_TIMEOUT 200
#define NAND_STOP_DELAY 40
-#define PAGE_CHUNK_SIZE(2048)
/*
* Define a buffer size for the initial command that detects the flash device:
@@ -729,7 +728,7 @@ static void set_command_address(struct pxa3xx_nand_info
*info,
unsigned int page_size, uint16_t column, int page_addr)
{
/* small page addr setting */
- if (page_size < PAGE_CHUNK_SIZE) {
+ if (page_size < info->chunk_size) {
info->ndcb1 = ((page_addr & 0xFF) << 8)
| (column & 0xFF);
@@ -839,9 +838,9 @@ static int prepare_set_command(struct pxa3xx_nand_info *info, int command,
* which is either naked-read or last-read according to the
* state.
*/
- if (mtd->writesize == PAGE_CHUNK_SIZE) {
+ if (mtd->writesize == info->chunk_size) {
info->ndcb0 |= NDCB0_DBC | (NAND_CMD_READSTART << 8);
- } else if (mtd->writesize > PAGE_CHUNK_SIZE) {
+ } else if (mtd->writesize > info->chunk_size) {
info->ndcb0 |= NDCB0_DBC | (NAND_CMD_READSTART << 8)
| NDCB0_LEN_OVRD
| NDCB0_EXT_CMD_TYPE(ext_cmd_type);
@@ -861,7 +860,7 @@ static int prepare_set_command(struct pxa3xx_nand_info
*info, int command,
* Multiple page programming needs to execute the initial
* SEQIN command that sets the page address.
*/
- if (mtd->writesize > PAGE_CHUNK_SIZE) {
+ if (mtd->writesize > info->chunk_size) {
info->ndcb0 |= NDCB0_CMD_TYPE(0x1)
| NDCB0_EXT_CMD_TYPE(ext_cmd_type)
| addr_cycle
@@ -886,7 +885,7 @@ static int prepare_set_command(struct pxa3xx_nand_info
*info, int command,
}
/* Second command setting for large pages */
- if (mtd->writesize > PAGE_CHUNK_SIZE) {
+ if (mtd->writesize > info->chunk_size) {
/*
* Multiple page write uses the 'extended command'
* field. This can be used to issue a command dispatch
@@ -1312,7 +1311,6 @@ static int pxa3xx_nand_config_ident(struct
pxa3xx_nand_info *info)
struct pxa3xx_nand_platform_data *pdata = info->pdata;
/* Configure default flash values */
- info->chunk_size = PAGE_CHUNK_SIZE;
info->reg_ndcr = 0x0; /* enable all interrupts */
info->reg_ndcr |= (pdata->enable_arbiter) ? NDCR_ND_ARB_EN : 0;
info->reg_ndcr |= NDCR_RD_ID_CNT(READ_ID_BYTES);
@@ -1529,21 +1527,6 @@ static int pxa3xx_nand_scan(struct mtd_info *mtd)
chip->bbt_md = _mirror_descr;
#endif
- /*
-* If the page size is bigger than the FIFO size, let's check
-* we are given the right variant and then switch to the extended
-* (aka splitted) command handling,
-*/
- if (mtd->writesize > PAGE_CHUNK_SIZE) {
- if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370) {
- chip->cmdfunc = nand_cmdfunc_extended;
- } else {
- dev_err(>pdev->dev,
- "unsupported page size on this variant\n");
- return -ENODEV;
- }
- }
-
if (pdata->ecc_strength && pdata->ecc_step_size) {
ecc_strength = pdata->ecc_strength;
ecc_step = pdata->ecc_step_size;
@@ -1563,6 +1546,21 @@ static int pxa3xx_nand_scan(struct mtd_info *mtd)
if (ret)
return ret;
+ /*
+* If the page size is bigger than the FIFO size, let's check
+* we are given the right variant and then switch to the extended
+* (aka split) command handling,
+*/
+ if (mtd->writesize > info->chunk_size) {
+ if
Re: [U-Boot] [PATCH 18/19] nand: pxa3xx: Add support for 8KB page 4 and 8 bit ECC NAND
On 29.08.2018 10:56, kos...@marvell.com wrote:
From: Konstantin Porotchkin
Add support for NAND chips with 8KB page, 4 and 8 bit ECC (ONFI).
Signed-off-by: Konstantin Porotchkin
Reviewed-by: Ofer Heifetz
Cc: Stefan Roese
Cc: Simon Glass
---
drivers/mtd/nand/pxa3xx_nand.c | 72 ++
1 file changed, 66 insertions(+), 6 deletions(-)
diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c
index e08ad00..b1bd430 100644
--- a/drivers/mtd/nand/pxa3xx_nand.c
+++ b/drivers/mtd/nand/pxa3xx_nand.c
@@ -356,6 +356,33 @@ static struct nand_ecclayout ecc_layout_4KB_bch4bit = {
.oobfree = { {6, 26}, { 64, 32} }
};
+static struct nand_ecclayout ecc_layout_8KB_bch4bit = {
+ .eccbytes = 128,
+ .eccpos = {
+ 32, 33, 34, 35, 36, 37, 38, 39,
+ 40, 41, 42, 43, 44, 45, 46, 47,
+ 48, 49, 50, 51, 52, 53, 54, 55,
+ 56, 57, 58, 59, 60, 61, 62, 63,
+
+ 96, 97, 98, 99, 100, 101, 102, 103,
+ 104, 105, 106, 107, 108, 109, 110, 111,
+ 112, 113, 114, 115, 116, 117, 118, 119,
+ 120, 121, 122, 123, 124, 125, 126, 127,
+
+ 160, 161, 162, 163, 164, 165, 166, 167,
+ 168, 169, 170, 171, 172, 173, 174, 175,
+ 176, 177, 178, 179, 180, 181, 182, 183,
+ 184, 185, 186, 187, 188, 189, 190, 191,
+
+ 224, 225, 226, 227, 228, 229, 230, 231,
+ 232, 233, 234, 235, 236, 237, 238, 239,
+ 240, 241, 242, 243, 244, 245, 246, 247,
+ 248, 249, 250, 251, 252, 253, 254, 255},
+
+ /* Bootrom looks in bytes 0 & 5 for bad blocks */
+ .oobfree = { {1, 4}, {6, 26}, { 64, 32}, {128, 32}, {192, 32} }
+};
+
static struct nand_ecclayout ecc_layout_4KB_bch8bit = {
.eccbytes = 128,
.eccpos = {
@@ -366,6 +393,13 @@ static struct nand_ecclayout ecc_layout_4KB_bch8bit = {
.oobfree = { }
};
+static struct nand_ecclayout ecc_layout_8KB_bch8bit = {
+ .eccbytes = 256,
+ .eccpos = {},
+ /* HW ECC handles all ECC data and all spare area is free for OOB */
+ .oobfree = {{0, 160} }
+};
+
#define NDTR0_tCH(c) (min((c), 7) << 19)
#define NDTR0_tCS(c) (min((c), 7) << 16)
#define NDTR0_tWH(c) (min((c), 7) << 11)
@@ -1454,10 +1488,36 @@ static int pxa_ecc_init(struct pxa3xx_nand_info *info,
ecc->layout = _layout_4KB_bch4bit;
ecc->strength = 16;
+ } else if (strength == 4 && ecc_stepsize == 512 && page_size == 8192) {
+ info->ecc_bch = 1;
+ info->nfullchunks = 4;
+ info->ntotalchunks = 4;
+ info->chunk_size = 2048;
+ info->spare_size = 32;
+ info->ecc_size = 32;
+ ecc->mode = NAND_ECC_HW;
+ ecc->size = info->chunk_size;
+ ecc->layout = _layout_8KB_bch4bit;
+ ecc->strength = 16;
+
/*
* Required ECC: 8-bit correction per 512 bytes
* Select: 16-bit correction per 1024 bytes
*/
+ } else if (strength == 8 && ecc_stepsize == 512 && page_size == 2048) {
+ info->ecc_bch = 1;
+ info->nfullchunks = 1;
+ info->ntotalchunks = 2;
+ info->chunk_size = 1024;
+ info->spare_size = 0;
+ info->last_chunk_size = 1024;
+ info->last_spare_size = 64;
+ info->ecc_size = 32;
+ ecc->mode = NAND_ECC_HW;
+ ecc->size = info->chunk_size;
+ ecc->layout = _layout_2KB_bch8bit;
+ ecc->strength = 16;
+
} else if (strength == 8 && ecc_stepsize == 512 && page_size == 4096) {
info->ecc_bch = 1;
info->nfullchunks = 4;
@@ -1472,18 +1532,18 @@ static int pxa_ecc_init(struct pxa3xx_nand_info *info,
ecc->layout = _layout_4KB_bch8bit;
ecc->strength = 16;
- } else if (strength == 8 && ecc_stepsize == 512 && page_size == 2048) {
+ } else if (strength == 8 && ecc_stepsize == 512 && page_size == 8192) {
info->ecc_bch = 1;
- info->nfullchunks = 1;
- info->ntotalchunks = 2;
+ info->nfullchunks = 8;
+ info->ntotalchunks = 9;
info->chunk_size = 1024;
info->spare_size = 0;
- info->last_chunk_size = 1024;
- info->last_spare_size = 64;
+ info->last_chunk_size = 0;
+ info->last_spare_size = 160;
info->ecc_size = 32;
ecc->mode = NAND_ECC_HW;
ecc->size = info->chunk_size;
- ecc->layout = _layout_2KB_bch8bit;
+ ecc->layout = _layout_8KB_bch8bit;
ecc->strength = 16;
} else {
Applied to u-boot-marvell/master
Re: [U-Boot] [PATCH 14/19] mtd: nand: pxa3xx: add support for 2KB 8-bit flash
On 29.08.2018 10:56, kos...@marvell.com wrote:
From: Victor Axelrod
Add support for 2KB page 8-bit ECC strength flash layout
Signed-off-by: Victor Axelrod
Reviewed-by: Igal Liberman
Cc: Stefan Roese
Cc: Simon Glass
---
drivers/mtd/nand/pxa3xx_nand.c | 27 +++
1 file changed, 27 insertions(+)
diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c
index c1f7d61..81e75f2 100644
--- a/drivers/mtd/nand/pxa3xx_nand.c
+++ b/drivers/mtd/nand/pxa3xx_nand.c
@@ -308,6 +308,20 @@ static struct nand_ecclayout ecc_layout_2KB_bch4bit = {
.oobfree = { {2, 30} }
};
+static struct nand_ecclayout ecc_layout_2KB_bch8bit = {
+ .eccbytes = 64,
+ .eccpos = {
+ 64, 65, 66, 67, 68, 69, 70, 71,
+ 72, 73, 74, 75, 76, 77, 78, 79,
+ 80, 81, 82, 83, 84, 85, 86, 87,
+ 88, 89, 90, 91, 92, 93, 94, 95,
+ 96, 97, 98, 99, 100, 101, 102, 103,
+ 104, 105, 106, 107, 108, 109, 110, 111,
+ 112, 113, 114, 115, 116, 117, 118, 119,
+ 120, 121, 122, 123, 124, 125, 126, 127},
+ .oobfree = { {1, 4}, {6, 26} }
+};
+
static struct nand_ecclayout ecc_layout_4KB_bch4bit = {
.eccbytes = 64,
.eccpos = {
@@ -1439,6 +1453,19 @@ static int pxa_ecc_init(struct pxa3xx_nand_info *info,
ecc->size = info->chunk_size;
ecc->layout = _layout_4KB_bch8bit;
ecc->strength = 16;
+ } else if (strength == 8 && ecc_stepsize == 512 && page_size == 2048) {
+ info->ecc_bch = 1;
+ info->nfullchunks = 1;
+ info->ntotalchunks = 2;
+ info->chunk_size = 1024;
+ info->spare_size = 0;
+ info->last_chunk_size = 1024;
+ info->last_spare_size = 64;
+ info->ecc_size = 32;
+ ecc->mode = NAND_ECC_HW;
+ ecc->size = info->chunk_size;
+ ecc->layout = _layout_2KB_bch8bit;
+ ecc->strength = 16;
} else {
dev_err(>pdev->dev,
"ECC strength %d at page size %d is not supported\n",
Applied to u-boot-marvell/master
Thanks,
Stefan
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Re: [U-Boot] [PATCH 17/19] nand: pxa3xx: cosmetic: add comments to the timing layout structures
On 29.08.2018 10:56, kos...@marvell.com wrote:
From: Konstantin Porotchkin
Add comments with timing parameter names and some details about
nand layout fileds.
Remove unneeded definition.
Signed-off-by: Konstantin Porotchkin
Reviewed-by: Igal Liberman
Cc: Stefan Roese
Cc: Simon Glass
---
drivers/mtd/nand/pxa3xx_nand.c | 21 -
1 file changed, 20 insertions(+), 1 deletion(-)
diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c
index a7ca28c..e08ad00 100644
--- a/drivers/mtd/nand/pxa3xx_nand.c
+++ b/drivers/mtd/nand/pxa3xx_nand.c
@@ -61,7 +61,6 @@ DECLARE_GLOBAL_DATA_PTR;
#define NDCR_NAND_MODE(0x0)
#define NDCR_CLR_PG_CNT (0x1 << 20)
#define NFCV1_NDCR_ARB_CNTL (0x1 << 19)
-#define NFCV2_NDCR_STOP_ON_UNCOR (0x1 << 19)
#define NDCR_RD_ID_CNT_MASK (0x7 << 16)
#define NDCR_RD_ID_CNT(x) (((x) << 16) & NDCR_RD_ID_CNT_MASK)
@@ -255,6 +254,17 @@ struct pxa3xx_nand_info {
};
static struct pxa3xx_nand_timing timing[] = {
+ /*
+* tCH Enable signal hold time
+* tCS Enable signal setup time
+* tWH ND_nWE high duration
+* tWP ND_nWE pulse time
+* tRH ND_nRE high duration
+* tRP ND_nRE pulse width
+* tR ND_nWE high to ND_nRE low for read
+* tWHR ND_nWE high to ND_nRE low for status read
+* tAR ND_ALE low to ND_nRE low delay
+*/
/*ch cs wh wp rh rp r whr ar */
{ 40, 80, 60, 100, 80, 100, 9, 400, 40, },
{ 10, 0, 20, 40, 30, 40, 11123, 110, 10, },
@@ -264,6 +274,13 @@ static struct pxa3xx_nand_timing timing[] = {
};
static struct pxa3xx_nand_flash builtin_flash_types[] = {
+ /*
+* chip_id
+* flash_width Width of Flash memory (DWIDTH_M)
+* dfc_widthWidth of flash controller(DWIDTH_C)
+* *timing
+* http://www.linux-mtd.infradead.org/nand-data/nanddata.html
+*/
{ 0x46ec, 16, 16, [1] },
{ 0xdaec, 8, 8, [1] },
{ 0xd7ec, 8, 8, [1] },
@@ -1454,6 +1471,7 @@ static int pxa_ecc_init(struct pxa3xx_nand_info *info,
ecc->size = info->chunk_size;
ecc->layout = _layout_4KB_bch8bit;
ecc->strength = 16;
+
} else if (strength == 8 && ecc_stepsize == 512 && page_size == 2048) {
info->ecc_bch = 1;
info->nfullchunks = 1;
@@ -1467,6 +1485,7 @@ static int pxa_ecc_init(struct pxa3xx_nand_info *info,
ecc->size = info->chunk_size;
ecc->layout = _layout_2KB_bch8bit;
ecc->strength = 16;
+
} else {
dev_err(>pdev->dev,
"ECC strength %d at page size %d is not supported\n",
Applied to u-boot-marvell/master
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Stefan
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Re: [U-Boot] [PATCH 15/19] mtd: nand: pxa3xx: add support for Toshiba flash
On 29.08.2018 10:56, kos...@marvell.com wrote:
From: Konstantin Porotchkin
Add timings and device ID for Toshiba TC58NVG1S3HTA00 flash
Signed-off-by: Konstantin Porotchkin
Reviewed-by: Igal Liberman
Cc: Stefan Roese
Cc: Simon Glass
---
drivers/mtd/nand/pxa3xx_nand.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c
index 81e75f2..a7b9864 100644
--- a/drivers/mtd/nand/pxa3xx_nand.c
+++ b/drivers/mtd/nand/pxa3xx_nand.c
@@ -256,10 +256,12 @@ struct pxa3xx_nand_info {
};
static struct pxa3xx_nand_timing timing[] = {
+ /*ch cs wh wp rh rp r whr ar */
{ 40, 80, 60, 100, 80, 100, 9, 400, 40, },
{ 10, 0, 20, 40, 30, 40, 11123, 110, 10, },
{ 10, 25, 15, 25, 15, 30, 25000, 60, 10, },
{ 10, 35, 15, 25, 15, 25, 25000, 60, 10, },
+ { 5, 20, 10, 12, 10, 12, 25000, 60, 10, },
};
static struct pxa3xx_nand_flash builtin_flash_types[] = {
@@ -271,6 +273,7 @@ static struct pxa3xx_nand_flash builtin_flash_types[] = {
{ 0xdc2c, 8, 8, [2] },
{ 0xcc2c, 16, 16, [2] },
{ 0xba20, 16, 16, [3] },
+ { 0xda98, 8, 8, [4] },
};
#ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
Applied to u-boot-marvell/master
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Stefan
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Re: [U-Boot] [PATCH 13/19] mtd: nand: pxa3xx: Fix READOOB implementation
On 29.08.2018 10:56, kos...@marvell.com wrote:
From: Boris Brezillon
In the current driver, OOB bytes are accessed in raw mode, and when a
page access is done with NDCR_SPARE_EN set and NDCR_ECC_EN cleared, the
driver must read the whole spare area (64 bytes in case of a 2k page,
16 bytes for a 512 page). The driver was only reading the free OOB
bytes, which was leaving some unread data in the FIFO and was somehow
leading to a timeout.
We could patch the driver to read ->spare_size + ->ecc_size instead of
just ->spare_size when READOOB is requested, but we'd better make
in-band and OOB accesses consistent.
Since the driver is always accessing in-band data in non-raw mode (with
the ECC engine enabled), we should also access OOB data in this mode.
That's particularly useful when using the BCH engine because in this
mode the free OOB bytes are also ECC protected.
Fixes: 43bcfd2bb24a ("mtd: nand: pxa3xx: Add driver-specific ECC BCH support")
Cc: sta...@vger.kernel.org
Reported-by: Sean Nyekjær
Tested-by: Willy Tarreau
Signed-off-by: Boris Brezillon
Acked-by: Ezequiel Garcia
Tested-by: Sean Nyekjaer
Acked-by: Robert Jarzmik
Signed-off-by: Richard Weinberger
Signed-off-by: Ofer Heifetz
Reviewed-by: Igal Liberman
Cc: Stefan Roese
Cc: Simon Glass
---
drivers/mtd/nand/pxa3xx_nand.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c
index b64dd0d..c1f7d61 100644
--- a/drivers/mtd/nand/pxa3xx_nand.c
+++ b/drivers/mtd/nand/pxa3xx_nand.c
@@ -750,6 +750,7 @@ static void prepare_start_command(struct pxa3xx_nand_info
*info, int command)
switch (command) {
case NAND_CMD_READ0:
+ case NAND_CMD_READOOB:
case NAND_CMD_PAGEPROG:
info->use_ecc = 1;
break;
Applied to u-boot-marvell/master
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Re: [U-Boot] [PATCH 12/19] fix: nand: pxa3xx: Add SoC-specific enable function
On 29.08.2018 10:56, kos...@marvell.com wrote:
From: Igal Liberman
Add SoC-dependent function to the NAND driver for selecting
NAND interface in DEVBUS MUX register.
This selection is done in the BootROM if the boot device is NAND,
but may be missing othervise.
The NAND is selected only if it is enabled in the DT file.
This patch is fixing NAND access problems for configurations
that use non-NAND devices for boot (like SPI).
Signed-off-by: Igal Liberman
Signed-off-by: Konstantin Porotchkin
Signed-off-by: David Sniatkiwicz
Cc: Stefan Roese
Cc: Simon Glass
---
arch/arm/dts/armada-cp110-master.dtsi | 7 +++-
arch/arm/mach-mvebu/armada8k/cpu.c | 18 -
arch/arm/mach-mvebu/armada8k/soc.c | 30 ++
arch/arm/mach-mvebu/cpu.c | 12 +-
arch/arm/mach-mvebu/include/mach/cpu.h | 3 +-
drivers/mtd/nand/pxa3xx_nand.c | 74 +-
6 files changed, 114 insertions(+), 30 deletions(-)
diff --git a/arch/arm/dts/armada-cp110-master.dtsi
b/arch/arm/dts/armada-cp110-master.dtsi
index 551d00d..02cee94 100644
--- a/arch/arm/dts/armada-cp110-master.dtsi
+++ b/arch/arm/dts/armada-cp110-master.dtsi
@@ -276,7 +276,12 @@
cpm_nand: nand@72 {
compatible = "marvell,mvebu-pxa3xx-nand";
- reg = <0x72 0x100>;
+ reg = <0x72 0x100>,
+ <0x440700 0x20>,
+ <0x440208 0x20>;
+ reg-names = "ctrl_base",
+ "flash_clock",
+ "dev_mux";
#address-cells = <1>;
clocks = <_syscon0 1 2>;
diff --git a/arch/arm/mach-mvebu/armada8k/cpu.c
b/arch/arm/mach-mvebu/armada8k/cpu.c
index dd028e5..77e9400 100644
--- a/arch/arm/mach-mvebu/armada8k/cpu.c
+++ b/arch/arm/mach-mvebu/armada8k/cpu.c
@@ -109,24 +109,6 @@ void reset_cpu(ulong ignored)
writel(reg, RFU_GLOBAL_SW_RST);
}
-/*
- * TODO - implement this functionality using platform
- *clock driver once it gets available
- * Return NAND clock in Hz
- */
-u32 mvebu_get_nand_clock(void)
-{
- unsigned long NAND_FLASH_CLK_CTRL = 0xF2440700UL;
- unsigned long NF_CLOCK_SEL_MASK = 0x1;
- u32 reg;
-
- reg = readl(NAND_FLASH_CLK_CTRL);
- if (reg & NF_CLOCK_SEL_MASK)
- return 400 * 100;
- else
- return 250 * 100;
-}
-
#if defined(CONFIG_DISPLAY_BOARDINFO)
int print_cpuinfo(void)
{
diff --git a/arch/arm/mach-mvebu/armada8k/soc.c
b/arch/arm/mach-mvebu/armada8k/soc.c
index 511c734..faf1405 100644
--- a/arch/arm/mach-mvebu/armada8k/soc.c
+++ b/arch/arm/mach-mvebu/armada8k/soc.c
@@ -14,6 +14,10 @@
#define SW_REV_STATUS_OFFSET 16
#define SW_REV_STATUS_MASK0xf
+#define NF_CLOCK_SEL_MASK 0x1
+#define SOC_MUX_NAND_EN_MASK 0x1
+#define CLOCK_1Mhz 100
+
struct mochi_module {
u32 module_type;
u32 module_rev;
@@ -128,3 +132,29 @@ void soc_print_device_info(void)
else
printf("CP%x-A%d\n", cp_type, cp_rev);
}
+#ifdef CONFIG_NAND_PXA3XX
+/* Return NAND clock in Hz */
+u32 mvebu_get_nand_clock(void __iomem *nand_flash_clk_ctrl_reg)
+{
+ u32 reg;
+
+ if (!nand_flash_clk_ctrl_reg)
+ return 0;
+
+ reg = readl(nand_flash_clk_ctrl_reg);
+ if (reg & NF_CLOCK_SEL_MASK)
+ return 400 * CLOCK_1Mhz;
+ else
+ return 250 * CLOCK_1Mhz;
+}
+
+/* Select NAND in the device bus multiplexer */
+void mvebu_nand_select(void __iomem *soc_dev_multiplex_reg)
+{
+ if (!soc_dev_multiplex_reg)
+ return;
+
+ setbits_le32(soc_dev_multiplex_reg, SOC_MUX_NAND_EN_MASK);
+}
+#endif
+
diff --git a/arch/arm/mach-mvebu/cpu.c b/arch/arm/mach-mvebu/cpu.c
index 0d2d398..b1d1b1d 100644
--- a/arch/arm/mach-mvebu/cpu.c
+++ b/arch/arm/mach-mvebu/cpu.c
@@ -15,6 +15,8 @@
#define DDR_BASE_CS_OFF(n)(0x + ((n) << 3))
#define DDR_SIZE_CS_OFF(n)(0x0004 + ((n) << 3))
+#define SOC_MUX_NAND_EN_MASK 0x1
+
static struct mbus_win windows[] = {
/* SPI */
{ MBUS_SPI_BASE, MBUS_SPI_SIZE,
@@ -465,7 +467,7 @@ int arch_cpu_init(void)
}
#endif /* CONFIG_ARCH_CPU_INIT */
-u32 mvebu_get_nand_clock(void)
+u32 mvebu_get_nand_clock(void __iomem *unused)
{
u32 reg;
@@ -479,6 +481,14 @@ u32 mvebu_get_nand_clock(void)
NAND_ECC_DIVCKL_RATIO_MASK) >> NAND_ECC_DIVCKL_RATIO_OFFS);
}
+void mvebu_nand_select(void __iomem *soc_dev_multiplex_reg)
+{
+ if (!soc_dev_multiplex_reg)
+ return;
+
+ setbits_le32(soc_dev_multiplex_reg, SOC_MUX_NAND_EN_MASK);
+}
+
/*
* SOC specific misc init
*/
diff --git a/arch/arm/mach-mvebu/include/mach/cpu.h
Re: [U-Boot] [PATCH 11/19] a70x0: a80x0: add soc type and revision printing in boot log
On 29.08.2018 10:56, kos...@marvell.com wrote:
From: zachary zhang
This patch adds SoC type and revision and each module's type
and revision printing for a7k and a8k boards.
Signed-off-by: zachary zhang
Reviewed-by: Igal Liberman
Cc: Stefan Roese
Cc: Simon Glass
---
arch/arm/mach-mvebu/armada8k/Makefile | 1 +
arch/arm/mach-mvebu/armada8k/cpu.c | 9 +++
arch/arm/mach-mvebu/armada8k/soc.c | 130 +
arch/arm/mach-mvebu/include/mach/soc.h | 3 +
common/board_f.c | 6 +-
5 files changed, 146 insertions(+), 3 deletions(-)
create mode 100644 arch/arm/mach-mvebu/armada8k/soc.c
diff --git a/arch/arm/mach-mvebu/armada8k/Makefile
b/arch/arm/mach-mvebu/armada8k/Makefile
index 82cb25b..19503f7 100644
--- a/arch/arm/mach-mvebu/armada8k/Makefile
+++ b/arch/arm/mach-mvebu/armada8k/Makefile
@@ -3,4 +3,5 @@
# Copyright (C) 2016 Stefan Roese
obj-y = cpu.o
+obj-y += soc.o
obj-y += cache_llc.o
diff --git a/arch/arm/mach-mvebu/armada8k/cpu.c
b/arch/arm/mach-mvebu/armada8k/cpu.c
index f8e8e73..dd028e5 100644
--- a/arch/arm/mach-mvebu/armada8k/cpu.c
+++ b/arch/arm/mach-mvebu/armada8k/cpu.c
@@ -12,6 +12,7 @@
#include
#include
#include
+#include
/* Armada 7k/8k */
#define MVEBU_RFU_BASE(MVEBU_REGISTER(0x6f))
@@ -125,3 +126,11 @@ u32 mvebu_get_nand_clock(void)
else
return 250 * 100;
}
+
+#if defined(CONFIG_DISPLAY_BOARDINFO)
+int print_cpuinfo(void)
+{
+ soc_print_device_info();
+ return 0;
+}
+#endif
diff --git a/arch/arm/mach-mvebu/armada8k/soc.c
b/arch/arm/mach-mvebu/armada8k/soc.c
new file mode 100644
index 000..511c734
--- /dev/null
+++ b/arch/arm/mach-mvebu/armada8k/soc.c
@@ -0,0 +1,130 @@
+/*
+ * Copyright (C) 2018 Marvell International Ltd.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ * https://spdx.org/licenses
+ */
+
+#include
+#include
+#include
+
+#define CP_DEV_ID_STATUS_REG (MVEBU_REGISTER(0x2400240))
+#define DEVICE_ID_STATUS_MASK 0x
+#define SW_REV_STATUS_OFFSET 16
+#define SW_REV_STATUS_MASK 0xf
+
+struct mochi_module {
+ u32 module_type;
+ u32 module_rev;
+};
+
+struct soc_info {
+ struct mochi_module soc;
+ char *soc_name;
+ struct mochi_module ap;
+ struct mochi_module cp;
+ u32 ap_num;
+ u32 cp_num;
+};
+
+static struct soc_info soc_info_table[] = {
+ { {0x7040, 1}, "Armada7040-A1", {0x806, 1}, {0x110, 1}, 1, 1 },
+ { {0x7040, 2}, "Armada7040-A2", {0x806, 1}, {0x110, 2}, 1, 1 },
+ { {0x8040, 1}, "Armada8040-A1", {0x806, 1}, {0x110, 1}, 1, 2 },
+ { {0x8040, 2}, "Armada8040-A2", {0x806, 1}, {0x110, 2}, 1, 2 },
+};
+
+static int get_soc_type_rev(u32 *type, u32 *rev)
+{
+ *type = readl(CP_DEV_ID_STATUS_REG) & DEVICE_ID_STATUS_MASK;
+ *rev = (readl(CP_DEV_ID_STATUS_REG) >> SW_REV_STATUS_OFFSET) &
+ SW_REV_STATUS_MASK;
+
+ return 0;
+}
+
+static int get_soc_table_index(u32 *index)
+{
+ u32 soc_type;
+ u32 rev, i, ret = 1;
+
+ *index = 0;
+ get_soc_type_rev(_type, );
+
+ for (i = 0; i < sizeof(soc_info_table) / sizeof(struct soc_info); i++) {
+ if ((soc_type ==
+ soc_info_table[i].soc.module_type) &&
+ (rev == soc_info_table[i].soc.module_rev)) {
+ *index = i;
+ ret = 0;
+ }
+ }
+
+ return ret;
+}
+
+static int get_soc_name(char **soc_name)
+{
+ u32 index;
+
+ get_soc_table_index();
+ *soc_name = soc_info_table[index].soc_name;
+
+ return 0;
+}
+
+static int get_ap_cp_num(u32 *ap_num, u32 *cp_num)
+{
+ u32 index;
+
+ get_soc_table_index();
+ *ap_num = soc_info_table[index].ap_num;
+ *cp_num = soc_info_table[index].cp_num;
+
+ return 0;
+}
+
+/* Get SoC's Application Processor (AP) module type and revision */
+static int get_ap_type_rev(u32 *type, u32 *rev)
+{
+ u32 index;
+
+ get_soc_table_index();
+ *type = soc_info_table[index].ap.module_type;
+ *rev = soc_info_table[index].ap.module_rev;
+
+ return 0;
+}
+
+/* Get SoC's Communication Processor (CP) module type and revision */
+static int get_cp_type_rev(u32 *type, u32 *rev)
+{
+ u32 index;
+
+ get_soc_table_index();
+ *type = soc_info_table[index].cp.module_type;
+ *rev = soc_info_table[index].cp.module_rev;
+
+ return 0;
+}
+
+/* Print device's SoC name and AP & CP information */
+void soc_print_device_info(void)
+{
+ u32 ap_num, cp_num, ap_type, ap_rev, cp_type, cp_rev;
+ char *soc_name = NULL;
+
+ get_ap_cp_num(_num, _num);
+
+ get_soc_name(_name);
+ get_ap_type_rev(_type, _rev);
+ get_cp_type_rev(_type, _rev);
+
+ printf("SoC: %s; AP%x-A%d; ", soc_name, ap_type, ap_rev);
+ /* more than one cp module */
+
Re: [U-Boot] [PATCH 10/19] mtd: nand: pxa3xx_nand: add support for partial chunks
On 29.08.2018 10:56, kos...@marvell.com wrote:
From: Ofer Heifetz
This commit is needed to properly support the 8-bits ECC configuration
with 4KB pages.
When pages larger than 2 KB are used on platforms using the PXA3xx
NAND controller, the reading/programming operations need to be split
in chunks of 2 KBs or less because the controller FIFO is limited to
about 2 KB (i.e a bit more than 2 KB to accommodate OOB data). Due to
this requirement, the data layout on NAND is a bit strange, with ECC
interleaved with data, at the end of each chunk.
When a 4-bits ECC configuration is used with 4 KB pages, the physical
data layout on the NAND looks like this:
| 2048 data | 32 spare | 30 ECC | 2048 data | 32 spare | 30 ECC |
So the data chunks have an equal size, 2080 bytes for each chunk,
which the driver supports properly.
When a 8-bits ECC configuration is used with 4KB pages, the physical
data layout on the NAND looks like this:
| 1024 data | 30 ECC | 1024 data | 30 ECC | 1024 data | 30 ECC | 1024 data | 30
ECC | 64 spare | 30 ECC |
So, the spare area is stored in its own chunk, which has a different
size than the other chunks. Since OOB is not used by UBIFS, the initial
implementation of the driver has chosen to not support reading this
additional "spare" chunk of data.
Unfortunately, Marvell has chosen to store the BBT signature in the
OOB area. Therefore, if the driver doesn't read this spare area, Linux
has no way of finding the BBT. It thinks there is no BBT, and rewrites
one, which U-Boot does not recognize, causing compatibility problems
between the bootloader and the kernel in terms of NAND usage.
To fix this, this commit implements the support for reading a partial
last chunk. This support is currently only useful for the case of 8
bits ECC with 4 KB pages, but it will be useful in the future to
enable other configurations such as 12 bits and 16 bits ECC with 4 KB
pages, or 8 bits ECC with 8 KB pages, etc. All those configurations
have a "last" chunk that doesn't have the same size as the other
chunks.
In order to implement reading of the last chunk, this commit:
- Adds a number of new fields to the pxa3xx_nand_info to describe how
many full chunks and how many chunks we have, the size of full
chunks and partial chunks, both in terms of data area and spare
area.
- Fills in the step_chunk_size and step_spare_size variables to
describe how much data and spare should be read/written for the
current read/program step.
- Reworks the state machine to accommodate doing the additional read
or program step when a last partial chunk is used.
This commit is taken from Linux:
'commit c2cdace755b'
("mtd: nand: pxa3xx_nand: add support for partial chunks")
Signed-off-by: Chris Packham
Signed-off-by: Ofer Heifetz
Reviewed-by: Igal Liberman
Cc: Stefan Roese
Cc: Simon Glass
---
drivers/mtd/nand/pxa3xx_nand.c | 154 ++---
1 file changed, 99 insertions(+), 55 deletions(-)
diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c
index 4faf787..5cc75de 100644
--- a/drivers/mtd/nand/pxa3xx_nand.c
+++ b/drivers/mtd/nand/pxa3xx_nand.c
@@ -201,15 +201,44 @@ struct pxa3xx_nand_info {
int use_spare; /* use spare ? */
int need_wait;
- unsigned int data_size; /* data to be read from FIFO */
- unsigned intchunk_size; /* split commands chunk size */
- unsigned intoob_size;
+ /* Amount of real data per full chunk */
+ unsigned intchunk_size;
+
+ /* Amount of spare data per full chunk */
unsigned intspare_size;
+
+ /* Number of full chunks (i.e chunk_size + spare_size) */
+ unsigned intnfullchunks;
+
+ /*
+* Total number of chunks. If equal to nfullchunks, then there
+* are only full chunks. Otherwise, there is one last chunk of
+* size (last_chunk_size + last_spare_size)
+*/
+ unsigned intntotalchunks;
+
+ /* Amount of real data in the last chunk */
+ unsigned intlast_chunk_size;
+
+ /* Amount of spare data in the last chunk */
+ unsigned intlast_spare_size;
+
unsigned intecc_size;
unsigned intecc_err_cnt;
unsigned intmax_bitflips;
int retcode;
+ /*
+* Variables only valid during command
+* execution. step_chunk_size and step_spare_size is the
+* amount of real data and spare data in the current
+* chunk. cur_chunk is the current chunk being
+* read/programmed.
+*/
+ unsigned intstep_chunk_size;
+ unsigned intstep_spare_size;
+ unsigned intcur_chunk;
+
/* cached register value */
uint32_treg_ndcr;
uint32_t
Re: [U-Boot] [PATCH 09/19] mtd: pxa3xx_nand: Simplify pxa3xx_nand_scan
On 29.08.2018 10:56, kos...@marvell.com wrote:
From: Ofer Heifetz
This commit simplifies the initial configuration performed
by pxa3xx_nand_scan. No functionality change is intended.
This commit is taken from Linux:
'commit 154f50fbde53'
("mtd: pxa3xx_nand: Simplify pxa3xx_nand_scan")
Signed-off-by: Chris Packham
Signed-off-by: Ofer Heifetz
Reviewed-by: Igal Liberman
Cc: Stefan Roese
Cc: Simon Glass
---
drivers/mtd/nand/pxa3xx_nand.c | 30 ++
1 file changed, 14 insertions(+), 16 deletions(-)
diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c
index 674496d..4faf787 100644
--- a/drivers/mtd/nand/pxa3xx_nand.c
+++ b/drivers/mtd/nand/pxa3xx_nand.c
@@ -1256,7 +1256,7 @@ static void pxa3xx_nand_config_tail(struct
pxa3xx_nand_info *info)
info->reg_ndcr |= (mtd->writesize == 2048) ? NDCR_PAGE_SZ : 0;
}
-static int pxa3xx_nand_detect_config(struct pxa3xx_nand_info *info)
+static void pxa3xx_nand_detect_config(struct pxa3xx_nand_info *info)
{
struct pxa3xx_nand_platform_data *pdata = info->pdata;
uint32_t ndcr = nand_readl(info, NDCR);
@@ -1268,7 +1268,6 @@ static int pxa3xx_nand_detect_config(struct
pxa3xx_nand_info *info)
info->reg_ndcr |= (pdata->enable_arbiter) ? NDCR_ND_ARB_EN : 0;
info->ndtr0cs0 = nand_readl(info, NDTR0CS0);
info->ndtr1cs0 = nand_readl(info, NDTR1CS0);
- return 0;
}
static int pxa3xx_nand_init_buff(struct pxa3xx_nand_info *info)
@@ -1388,22 +1387,21 @@ static int pxa3xx_nand_scan(struct mtd_info *mtd)
int ret;
uint16_t ecc_strength, ecc_step;
- if (pdata->keep_config && !pxa3xx_nand_detect_config(info))
- goto KEEP_CONFIG;
-
- ret = pxa3xx_nand_config_ident(info);
- if (ret)
- return ret;
-
- ret = pxa3xx_nand_sensing(host);
- if (ret) {
- dev_info(>pdev->dev, "There is no chip on cs %d!\n",
-info->cs);
-
- return ret;
+ if (pdata->keep_config) {
+ pxa3xx_nand_detect_config(info);
+ } else {
+ ret = pxa3xx_nand_config_ident(info);
+ if (ret)
+ return ret;
+ ret = pxa3xx_nand_sensing(host);
+ if (ret) {
+ dev_info(>pdev->dev,
+"There is no chip on cs %d!\n",
+info->cs);
+ return ret;
+ }
}
-KEEP_CONFIG:
/* Device detection must be done with ECC disabled */
if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370)
nand_writel(info, NDECCCTRL, 0x0);
Applied to u-boot-marvell/master
Thanks,
Stefan
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Re: [U-Boot] [PATCH 06/19] nand: pxa3xx: Increase READ_ID buffer and make the size static
On 29.08.2018 10:56, kos...@marvell.com wrote:
From: Ofer Heifetz
The read ID count should be made as large as the maximum READ_ID size,
so there's no need to have dynamic size. This commit sets the hardware
maximum read ID count, which should be more than enough on all cases.
Also, we get rid of the read_id_bytes, and use a macro instead.
This commit is taken from Linux:
'commit b226eca2088'
("nand: pxa3xx: Increase READ_ID buffer and make the size static")
Signed-off-by: Chris Packham
Signed-off-by: Ofer Heifetz
Reviewed-by: Igal Liberman
Cc: Stefan Roese
Cc: Simon Glass
---
drivers/mtd/nand/pxa3xx_nand.c | 29 ++---
1 file changed, 10 insertions(+), 19 deletions(-)
diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c
index 98bb4c6..575fdd2 100644
--- a/drivers/mtd/nand/pxa3xx_nand.c
+++ b/drivers/mtd/nand/pxa3xx_nand.c
@@ -112,6 +112,13 @@ DECLARE_GLOBAL_DATA_PTR;
#define EXT_CMD_TYPE_LAST_RW 1 /* Last naked read/write */
#define EXT_CMD_TYPE_MONO 0 /* Monolithic read/write */
+/*
+ * This should be large enough to read 'ONFI' and 'JEDEC'.
+ * Let's use 7 bytes, which is the maximum ID count supported
+ * by the controller (see NDCR_RD_ID_CNT_MASK).
+ */
+#define READ_ID_BYTES 7
+
/* macros for registers read/write */
#define nand_writel(info, off, val) \
writel((val), (info)->mmio_base + (off))
@@ -158,8 +165,6 @@ struct pxa3xx_nand_host {
/* calculated from pxa3xx_nand_flash data */
unsigned intcol_addr_cycles;
unsigned introw_addr_cycles;
- size_t read_id_bytes;
-
};
struct pxa3xx_nand_info {
@@ -860,7 +865,7 @@ static int prepare_set_command(struct pxa3xx_nand_info
*info, int command,
break;
case NAND_CMD_READID:
- info->buf_count = host->read_id_bytes;
+ info->buf_count = READ_ID_BYTES;
info->ndcb0 |= NDCB0_CMD_TYPE(3)
| NDCB0_ADDR_CYC(1)
| command;
@@ -1240,23 +1245,10 @@ static int pxa3xx_nand_config_flash(struct
pxa3xx_nand_info *info)
static int pxa3xx_nand_detect_config(struct pxa3xx_nand_info *info)
{
- /*
-* We set 0 by hard coding here, for we don't support keep_config
-* when there is more than one chip attached to the controller
-*/
- struct pxa3xx_nand_host *host = info->host[0];
uint32_t ndcr = nand_readl(info, NDCR);
- if (ndcr & NDCR_PAGE_SZ) {
- /* Controller's FIFO size */
- info->chunk_size = 2048;
- host->read_id_bytes = 4;
- } else {
- info->chunk_size = 512;
- host->read_id_bytes = 2;
- }
-
/* Set an initial chunk size */
+ info->chunk_size = ndcr & NDCR_PAGE_SZ ? 2048 : 512;
info->reg_ndcr = ndcr & ~NDCR_INT_MASK;
info->ndtr0cs0 = nand_readl(info, NDTR0CS0);
info->ndtr1cs0 = nand_readl(info, NDTR1CS0);
@@ -1286,7 +1278,7 @@ static int pxa3xx_nand_sensing(struct pxa3xx_nand_host
*host)
/* configure default flash values */
info->reg_ndcr = 0x0; /* enable all interrupts */
info->reg_ndcr |= (pdata->enable_arbiter) ? NDCR_ND_ARB_EN : 0;
- info->reg_ndcr |= NDCR_RD_ID_CNT(host->read_id_bytes);
+ info->reg_ndcr |= NDCR_RD_ID_CNT(READ_ID_BYTES);
info->reg_ndcr |= NDCR_SPARE_EN; /* enable spare by default */
/* use the common timing to make a try */
@@ -1503,7 +1495,6 @@ static int alloc_nand_resource(struct pxa3xx_nand_info
*info)
info->host[cs] = host;
host->cs = cs;
host->info_data = info;
- host->read_id_bytes = 4;
mtd->owner = THIS_MODULE;
nand_set_controller_data(chip, host);
Applied to u-boot-marvell/master
Thanks,
Stefan
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Re: [U-Boot] [PATCH 05/19] mtd: nand: pxa3xx-nand: fix random command timeouts
On 29.08.2018 10:56, kos...@marvell.com wrote:
From: Ofer Heifetz
When 2 commands are submitted in a row, and the second is very quick,
the completion of the second command might never come. This happens
especially if the second command is quick, such as a status read
after an erase
This patch is taken from Linux:
'commit 21fc0ef9652f'
("mtd: nand: pxa3xx-nand: fix random command timeouts")
Signed-off-by: Chris Packham
Signed-off-by: Ofer Heifetz
Reviewed-by: Igal Liberman
Cc: Stefan Roese
Cc: Simon Glass
---
drivers/mtd/nand/pxa3xx_nand.c | 10 +++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c
index 7b1dcb2..98bb4c6 100644
--- a/drivers/mtd/nand/pxa3xx_nand.c
+++ b/drivers/mtd/nand/pxa3xx_nand.c
@@ -623,8 +623,14 @@ static irqreturn_t pxa3xx_nand_irq(struct pxa3xx_nand_info
*info)
is_ready = 1;
}
+ /*
+* Clear all status bit before issuing the next command, which
+* can and will alter the status bits and will deserve a new
+* interrupt on its own. This lets the controller exit the IRQ
+*/
+ nand_writel(info, NDSR, status);
+
if (status & NDSR_WRCMDREQ) {
- nand_writel(info, NDSR, NDSR_WRCMDREQ);
status &= ~NDSR_WRCMDREQ;
info->state = STATE_CMD_HANDLE;
@@ -645,8 +651,6 @@ static irqreturn_t pxa3xx_nand_irq(struct pxa3xx_nand_info *info)
nand_writel(info, NDCB0, info->ndcb3);
}
- /* clear NDSR to let the controller exit the IRQ */
- nand_writel(info, NDSR, status);
if (is_completed)
info->cmd_complete = 1;
if (is_ready)
Applied to u-boot-marvell/master
Thanks,
Stefan
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Re: [U-Boot] [PATCH 07/19] mtd: pxa3xx_nand: Increase the initial chunk size
On 29.08.2018 10:56, kos...@marvell.com wrote:
From: Ofer Heifetz
The chunk size represents the size of the data chunks, which
is used by the controllers that allow to split transferred data.
However, the initial chunk size is used in a non-split way,
during device identification. Therefore, it must be large enough
for all the NAND commands issued during device identification.
This includes NAND_CMD_PARAM which was recently changed to
transfer up to 2048 bytes (for the redundant parameter pages).
Thus, the initial chunk size should be 2048 as well.
On Armada 370/XP platforms (NFCv2) booted without the keep-config
devicetree property, this commit fixes a timeout on the NAND_CMD_PARAM
command:
[..]
pxa3xx-nand f10d.nand: This platform can't do DMA on this device
pxa3xx-nand f10d.nand: Wait time out!!!
nand: device found, Manufacturer ID: 0x2c, Chip ID: 0x38
nand: Micron MT29F8G08ABABAWP
nand: 1024 MiB, SLC, erase size: 512 KiB, page size: 4096, OOB size: 224
This commit is taken from Linux:
'commit c7f00c29aa8'
("mtd: pxa3xx_nand: Increase the initial chunk size")
Signed-off-by: Chris Packham
Signed-off-by: Ofer Heifetz
Reviewed-by: Igal Liberman
Cc: Stefan Roese
Cc: Simon Glass
---
drivers/mtd/nand/pxa3xx_nand.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c
index 575fdd2..835b419 100644
--- a/drivers/mtd/nand/pxa3xx_nand.c
+++ b/drivers/mtd/nand/pxa3xx_nand.c
@@ -1376,7 +1376,7 @@ static int pxa3xx_nand_scan(struct mtd_info *mtd)
goto KEEP_CONFIG;
/* Set a default chunk size */
- info->chunk_size = 512;
+ info->chunk_size = PAGE_CHUNK_SIZE;
ret = pxa3xx_nand_sensing(host);
if (ret) {
Applied to u-boot-marvell/master
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Re: [U-Boot] [PATCH 08/19] mtd: pxa3xx_nand: Fix initial controller configuration
On 29.08.2018 10:56, kos...@marvell.com wrote:
From: Ofer Heifetz
The Data Flash Control Register (NDCR) contains two types
of parameters: those that are needed for device identification,
and those that can only be set after device identification.
Therefore, the driver can't set them all at once and instead
needs to configure the first group before nand_scan_ident()
and the second group later.
Let's split pxa3xx_nand_config in two halves, and set the
parameters that depend on the device geometry once this is known.
This commit is taken from Linux:
'commit 66e8e47eae65'
("mtd: pxa3xx_nand: Fix initial controller configuration")
Signed-off-by: Chris Packham
Signed-off-by: Ofer Heifetz
Reviewed-by: Igal Liberman
Cc: Stefan Roese
Cc: Simon Glass
---
drivers/mtd/nand/pxa3xx_nand.c | 41 +
1 file changed, 29 insertions(+), 12 deletions(-)
diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c
index 835b419..674496d 100644
--- a/drivers/mtd/nand/pxa3xx_nand.c
+++ b/drivers/mtd/nand/pxa3xx_nand.c
@@ -61,7 +61,8 @@ DECLARE_GLOBAL_DATA_PTR;
#define NDCR_ND_MODE (0x3 << 21)
#define NDCR_NAND_MODE(0x0)
#define NDCR_CLR_PG_CNT (0x1 << 20)
-#define NDCR_STOP_ON_UNCOR (0x1 << 19)
+#define NFCV1_NDCR_ARB_CNTL(0x1 << 19)
+#define NFCV2_NDCR_STOP_ON_UNCOR (0x1 << 19)
#define NDCR_RD_ID_CNT_MASK (0x7 << 16)
#define NDCR_RD_ID_CNT(x) (((x) << 16) & NDCR_RD_ID_CNT_MASK)
@@ -1230,26 +1231,41 @@ static int pxa3xx_nand_waitfunc(struct mtd_info *mtd, struct nand_chip *this)
return NAND_STATUS_READY;
}
-static int pxa3xx_nand_config_flash(struct pxa3xx_nand_info *info)
+static int pxa3xx_nand_config_ident(struct pxa3xx_nand_info *info)
+{
+ struct pxa3xx_nand_platform_data *pdata = info->pdata;
+
+ /* Configure default flash values */
+ info->chunk_size = PAGE_CHUNK_SIZE;
+ info->reg_ndcr = 0x0; /* enable all interrupts */
+ info->reg_ndcr |= (pdata->enable_arbiter) ? NDCR_ND_ARB_EN : 0;
+ info->reg_ndcr |= NDCR_RD_ID_CNT(READ_ID_BYTES);
+ info->reg_ndcr |= NDCR_SPARE_EN;
+
+ return 0;
+}
+
+static void pxa3xx_nand_config_tail(struct pxa3xx_nand_info *info)
{
struct pxa3xx_nand_host *host = info->host[info->cs];
- struct mtd_info *mtd = nand_to_mtd(>chip);
+ struct mtd_info *mtd = nand_to_mtd(>host[info->cs]->chip);
struct nand_chip *chip = mtd_to_nand(mtd);
info->reg_ndcr |= (host->col_addr_cycles == 2) ? NDCR_RA_START : 0;
info->reg_ndcr |= (chip->page_shift == 6) ? NDCR_PG_PER_BLK : 0;
info->reg_ndcr |= (mtd->writesize == 2048) ? NDCR_PAGE_SZ : 0;
-
- return 0;
}
static int pxa3xx_nand_detect_config(struct pxa3xx_nand_info *info)
{
+ struct pxa3xx_nand_platform_data *pdata = info->pdata;
uint32_t ndcr = nand_readl(info, NDCR);
/* Set an initial chunk size */
info->chunk_size = ndcr & NDCR_PAGE_SZ ? 2048 : 512;
- info->reg_ndcr = ndcr & ~NDCR_INT_MASK;
+ info->reg_ndcr = ndcr &
+ ~(NDCR_INT_MASK | NDCR_ND_ARB_EN | NFCV1_NDCR_ARB_CNTL);
+ info->reg_ndcr |= (pdata->enable_arbiter) ? NDCR_ND_ARB_EN : 0;
info->ndtr0cs0 = nand_readl(info, NDTR0CS0);
info->ndtr1cs0 = nand_readl(info, NDTR1CS0);
return 0;
@@ -1375,8 +1391,9 @@ static int pxa3xx_nand_scan(struct mtd_info *mtd)
if (pdata->keep_config && !pxa3xx_nand_detect_config(info))
goto KEEP_CONFIG;
- /* Set a default chunk size */
- info->chunk_size = PAGE_CHUNK_SIZE;
+ ret = pxa3xx_nand_config_ident(info);
+ if (ret)
+ return ret;
ret = pxa3xx_nand_sensing(host);
if (ret) {
@@ -1403,10 +1420,6 @@ KEEP_CONFIG:
}
}
- ret = pxa3xx_nand_config_flash(info);
- if (ret)
- return ret;
-
#ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
/*
* We'll use a bad block table stored in-flash and don't
@@ -1471,6 +1484,10 @@ KEEP_CONFIG:
host->row_addr_cycles = 3;
else
host->row_addr_cycles = 2;
+
+ if (!pdata->keep_config)
+ pxa3xx_nand_config_tail(info);
+
return nand_scan_tail(mtd);
}
Applied to u-boot-marvell/master
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Stefan
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Re: [U-Boot] [PATCH 03/19] mtd: nand: pxa3xx_nand: sync pxa3xx_nand_set_sdr_timing()
On 29.08.2018 10:56, kos...@marvell.com wrote: From: Ofer Heifetz Since the pxa3xx_nand driver was added there has been a discrepancy in pxa3xx_nand_set_sdr_timing() around the setting of tWP_min and tRP_min. This brings us into line with the current Linux code. Signed-off-by: Chris Packham Signed-off-by: Ofer Heifetz Reviewed-by: Igal Liberman Cc: Stefan Roese Cc: Simon Glass --- drivers/mtd/nand/pxa3xx_nand.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c index 6295886..8e450fb 100644 --- a/drivers/mtd/nand/pxa3xx_nand.c +++ b/drivers/mtd/nand/pxa3xx_nand.c @@ -349,9 +349,9 @@ static void pxa3xx_nand_set_sdr_timing(struct pxa3xx_nand_host *host, u32 tCH_min = DIV_ROUND_UP(t->tCH_min, 1000); u32 tCS_min = DIV_ROUND_UP(t->tCS_min, 1000); u32 tWH_min = DIV_ROUND_UP(t->tWH_min, 1000); - u32 tWP_min = DIV_ROUND_UP(t->tWC_min - tWH_min, 1000); + u32 tWP_min = DIV_ROUND_UP(t->tWC_min - t->tWH_min, 1000); u32 tREH_min = DIV_ROUND_UP(t->tREH_min, 1000); - u32 tRP_min = DIV_ROUND_UP(t->tRC_min - tREH_min, 1000); + u32 tRP_min = DIV_ROUND_UP(t->tRC_min - t->tREH_min, 1000); u32 tR = chip->chip_delay * 1000; u32 tWHR_min = DIV_ROUND_UP(t->tWHR_min, 1000); u32 tAR_min = DIV_ROUND_UP(t->tAR_min, 1000); Applied to u-boot-marvell/master Thanks, Stefan ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 04/19] mtd: nand: pxa3xx_nand: fix early spurious interrupt
On 29.08.2018 10:56, kos...@marvell.com wrote:
From: Ofer Heifetz
When the nand is first probe, and upon the first command start, the
status bits should be cleared before the interrupts are unmasked.
This commit is taken from Linux:
'commit 0b14392db2e'
("mtd: nand: pxa3xx_nand: fix early spurious interrupt")
Signed-off-by: Chris Packham
Signed-off-by: Ofer Heifetz
Reviewed-by: Igal Liberman
Cc: Stefan Roese
Cc: Simon Glass
---
drivers/mtd/nand/pxa3xx_nand.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c
index 8e450fb..7b1dcb2 100644
--- a/drivers/mtd/nand/pxa3xx_nand.c
+++ b/drivers/mtd/nand/pxa3xx_nand.c
@@ -481,8 +481,8 @@ static void pxa3xx_nand_start(struct pxa3xx_nand_info *info)
ndcr |= NDCR_ND_RUN;
/* clear status bits and run */
- nand_writel(info, NDCR, 0);
nand_writel(info, NDSR, NDSR_MASK);
+ nand_writel(info, NDCR, 0);
nand_writel(info, NDCR, ndcr);
}
Applied to u-boot-marvell/master
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Stefan
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Re: [U-Boot] [PATCH 02/19] mtd: nand: pxa3xx_nand: use nand_to_mtd()
On 29.08.2018 10:56, kos...@marvell.com wrote:
From: Ofer Heifetz
Don't store struct mtd_info in struct pxa3xx_nand_host. Instead use the
one that is already part of struct nand_chip. This brings us in line
with current U-boot and Linux conventions.
Signed-off-by: Chris Packham
Signed-off-by: Ofer Heifetz
Reviewed-by: Igal Liberman
Cc: Stefan Roese
Cc: Simon Glass
---
drivers/mtd/nand/pxa3xx_nand.c | 19 +--
1 file changed, 9 insertions(+), 10 deletions(-)
diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c
index ead5624..6295886 100644
--- a/drivers/mtd/nand/pxa3xx_nand.c
+++ b/drivers/mtd/nand/pxa3xx_nand.c
@@ -149,7 +149,6 @@ enum pxa3xx_nand_variant {
struct pxa3xx_nand_host {
struct nand_chipchip;
- struct mtd_info *mtd;
void*info_data;
/* page size of attached chip */
@@ -384,16 +383,17 @@ static int pxa3xx_nand_init_timings(struct
pxa3xx_nand_host *host)
struct nand_chip *chip = >chip;
struct pxa3xx_nand_info *info = host->info_data;
const struct pxa3xx_nand_flash *f = NULL;
+ struct mtd_info *mtd = nand_to_mtd(>chip);
int mode, id, ntypes, i;
mode = onfi_get_async_timing_mode(chip);
if (mode == ONFI_TIMING_MODE_UNKNOWN) {
ntypes = ARRAY_SIZE(builtin_flash_types);
- chip->cmdfunc(host->mtd, NAND_CMD_READID, 0x00, -1);
+ chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
- id = chip->read_byte(host->mtd);
- id |= chip->read_byte(host->mtd) << 0x8;
+ id = chip->read_byte(mtd);
+ id |= chip->read_byte(mtd) << 0x8;
for (i = 0; i < ntypes; i++) {
f = _flash_types[i];
@@ -686,7 +686,7 @@ static void set_command_address(struct pxa3xx_nand_info
*info,
static void prepare_start_command(struct pxa3xx_nand_info *info, int command)
{
struct pxa3xx_nand_host *host = info->host[info->cs];
- struct mtd_info *mtd = host->mtd;
+ struct mtd_info *mtd = nand_to_mtd(>chip);
/* reset data and oob column point to handle data */
info->buf_start = 0;
@@ -737,7 +737,7 @@ static int prepare_set_command(struct pxa3xx_nand_info
*info, int command,
struct mtd_info *mtd;
host = info->host[info->cs];
- mtd = host->mtd;
+ mtd = nand_to_mtd(>chip);
addr_cycle = 0;
exec_cmd = 1;
@@ -1224,7 +1224,7 @@ static int pxa3xx_nand_waitfunc(struct mtd_info *mtd, struct nand_chip *this)
static int pxa3xx_nand_config_flash(struct pxa3xx_nand_info *info)
{
struct pxa3xx_nand_host *host = info->host[info->cs];
- struct mtd_info *mtd = host->mtd;
+ struct mtd_info *mtd = nand_to_mtd(>chip);
struct nand_chip *chip = mtd_to_nand(mtd);
info->reg_ndcr |= (host->col_addr_cycles == 2) ? NDCR_RA_START : 0;
@@ -1276,7 +1276,7 @@ static int pxa3xx_nand_sensing(struct pxa3xx_nand_host
*host)
const struct nand_sdr_timings *timings;
int ret;
- mtd = info->host[info->cs]->mtd;
+ mtd = nand_to_mtd(>host[info->cs]->chip);
chip = mtd_to_nand(mtd);
/* configure default flash values */
@@ -1497,7 +1497,6 @@ static int alloc_nand_resource(struct pxa3xx_nand_info
*info)
mtd = nand_to_mtd(chip);
host = (struct pxa3xx_nand_host *)chip;
info->host[cs] = host;
- host->mtd = mtd;
host->cs = cs;
host->info_data = info;
host->read_id_bytes = 4;
@@ -1615,7 +1614,7 @@ static int pxa3xx_nand_probe(struct pxa3xx_nand_info
*info)
probe_success = 0;
for (cs = 0; cs < pdata->num_cs; cs++) {
- struct mtd_info *mtd = info->host[cs]->mtd;
+ struct mtd_info *mtd = nand_to_mtd(>host[cs]->chip);
/*
* The mtd name matches the one used in 'mtdparts' kernel
Applied to u-boot-marvell/master
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Stefan
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Re: [U-Boot] [PATCH 01/19] mtd: nand: pxa3xx_nand: Increase initial buffer size
On 29.08.2018 10:56, kos...@marvell.com wrote:
From: Ofer Heifetz
The initial buffer is used for the initial commands used to detect
a flash device (STATUS, READID and PARAM).
ONFI param page is 256 bytes, and there are three redundant copies
to be read. JEDEC param page is 512 bytes, and there are also three
redundant copies to be read. Hence this buffer should be at least
512 x 3. This commits rounds the buffer size to 2048.
This commit is taken from Linux:
'commit c16340973fcb64614' ("nand: pxa3xx: Increase initial buffer size")
Signed-off-by: Chris Packham
Signed-off-by: Ofer Heifetz
Reviewed-by: Igal Liberman
Cc: Stefan Roese
Cc: Simon Glass
---
drivers/mtd/nand/pxa3xx_nand.c | 15 +--
1 file changed, 9 insertions(+), 6 deletions(-)
diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c
index 9d02fd8..ead5624 100644
--- a/drivers/mtd/nand/pxa3xx_nand.c
+++ b/drivers/mtd/nand/pxa3xx_nand.c
@@ -28,10 +28,13 @@ DECLARE_GLOBAL_DATA_PTR;
/*
* Define a buffer size for the initial command that detects the flash device:
- * STATUS, READID and PARAM. The largest of these is the PARAM command,
- * needing 256 bytes.
+ * STATUS, READID and PARAM.
+ * ONFI param page is 256 bytes, and there are three redundant copies
+ * to be read. JEDEC param page is 512 bytes, and there are also three
+ * redundant copies to be read.
+ * Hence this buffer should be at least 512 x 3. Let's pick 2048.
*/
-#define INIT_BUFFER_SIZE 256
+#define INIT_BUFFER_SIZE 2048
/* registers and bit definitions */
#define NDCR (0x00) /* Control register */
@@ -842,14 +845,14 @@ static int prepare_set_command(struct pxa3xx_nand_info
*info, int command,
break;
case NAND_CMD_PARAM:
- info->buf_count = 256;
+ info->buf_count = INIT_BUFFER_SIZE;
info->ndcb0 |= NDCB0_CMD_TYPE(0)
| NDCB0_ADDR_CYC(1)
| NDCB0_LEN_OVRD
| command;
info->ndcb1 = (column & 0xFF);
- info->ndcb3 = 256;
- info->data_size = 256;
+ info->ndcb3 = INIT_BUFFER_SIZE;
+ info->data_size = INIT_BUFFER_SIZE;
break;
case NAND_CMD_READID:
Applied to u-boot-marvell/master
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Re: [U-Boot] [PATCH u-boot-marvell v3 04/12] board: turris_mox: Fixup U-Boot's device tree if PCIe connected
On 21.08.2018 12:22, Marek Behún wrote:
If PCIe Mox module is connected we want to have PCIe node enabled
in U-Boot's device tree.
Signed-off-by: Marek Behun
---
arch/arm/dts/armada-3720-turris-mox.dts | 7 +++
board/CZ.NIC/turris_mox/turris_mox.c| 82 +
configs/turris_mox_defconfig| 1 +
3 files changed, 90 insertions(+)
diff --git a/arch/arm/dts/armada-3720-turris-mox.dts
b/arch/arm/dts/armada-3720-turris-mox.dts
index bef100afce..a817f20920 100644
--- a/arch/arm/dts/armada-3720-turris-mox.dts
+++ b/arch/arm/dts/armada-3720-turris-mox.dts
@@ -130,3 +130,10 @@
vbus-supply = <_usb3_vbus>;
status = "okay";
};
+
+ {
+ pinctrl-names = "default";
+ pinctrl-0 = <_pins>;
+ reset-gpio = < 3 GPIO_ACTIVE_HIGH>;
+ status = "disabled";
+};
diff --git a/board/CZ.NIC/turris_mox/turris_mox.c
b/board/CZ.NIC/turris_mox/turris_mox.c
index b6a0ca4626..c4622a49c2 100644
--- a/board/CZ.NIC/turris_mox/turris_mox.c
+++ b/board/CZ.NIC/turris_mox/turris_mox.c
@@ -4,17 +4,99 @@
*/
#include
+#include
#include
#include
#include
#include
+#include
+#include
#ifdef CONFIG_WDT_ARMADA_37XX
#include
#endif
+#define MAX_MOX_MODULES 10
+
+#define MOX_MODULE_SFP 0x1
+#define MOX_MODULE_PCI 0x2
+#define MOX_MODULE_TOPAZ 0x3
+#define MOX_MODULE_PERIDOT 0x4
+#define MOX_MODULE_USB30x5
+#define MOX_MODULE_PASSPCI 0x6
+
+#define ARMADA_37XX_NB_GPIO_SEL0xd0013830
+#define ARMADA_37XX_SPI_CTRL 0xd0010600
+#define ARMADA_37XX_SPI_CFG0xd0010604
+#define ARMADA_37XX_SPI_DOUT 0xd0010608
+#define ARMADA_37XX_SPI_DIN0xd001060c
+
+#define PCIE_PATH "/soc/pcie@d007"
+
DECLARE_GLOBAL_DATA_PTR;
+#if defined(CONFIG_OF_BOARD_FIXUP)
+int board_fix_fdt(void *blob)
+{
+ u8 topology[MAX_MOX_MODULES];
+ int i, size, node;
+ bool enable;
+
+ /*
+* SPI driver is not loaded in driver model yet, but we have to find out
+* if pcie should be enabled in U-Boot's device tree. Therefore we have
+* to read SPI by reading/writing SPI registers directly
+*/
+
+ writel(0x563fa, ARMADA_37XX_NB_GPIO_SEL);
+ writel(0x10df, ARMADA_37XX_SPI_CFG);
+ writel(0x2005b, ARMADA_37XX_SPI_CTRL);
+
+ while (!(readl(ARMADA_37XX_SPI_CTRL) & 0x2))
+ udelay(1);
+
+ for (i = 0; i < MAX_MOX_MODULES; ++i) {
+ writel(0x0, ARMADA_37XX_SPI_DOUT);
+
+ while (!(readl(ARMADA_37XX_SPI_CTRL) & 0x2))
+ udelay(1);
+
+ topology[i] = readl(ARMADA_37XX_SPI_DIN) & 0xff;
+ if (topology[i] == 0xff)
+ break;
+
+ topology[i] &= 0xf;
+ }
+
+ size = i;
+
+ writel(0x5b, ARMADA_37XX_SPI_CTRL);
+
+ if (size > 1 && (topology[1] == MOX_MODULE_PCI ||
+topology[1] == MOX_MODULE_USB3 ||
+topology[1] == MOX_MODULE_PASSPCI))
+ enable = true;
+ else
+ enable = false;
+
+ node = fdt_path_offset(blob, PCIE_PATH);
+
+ if (node < 0) {
+ printf("Cannot find PCIe node in U-Boot's device tree!\n");
+ return 0;
+ }
+
+ if (fdt_setprop_string(blob, node, "status",
+ enable ? "okay" : "disabled") < 0) {
+ printf("Cannot %s PCIe in U-Boot's device tree!\n",
+ enable ? "enable" : "disable");
+ return 0;
+ }
+
+ return 0;
+}
+#endif
+
#ifdef CONFIG_WDT_ARMADA_37XX
static struct udevice *watchdog_dev;
diff --git a/configs/turris_mox_defconfig b/configs/turris_mox_defconfig
index de9aedc764..47ab914ce9 100644
--- a/configs/turris_mox_defconfig
+++ b/configs/turris_mox_defconfig
@@ -13,6 +13,7 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARCH_EARLY_INIT_R=y
+CONFIG_OF_BOARD_FIXUP=y
CONFIG_CMD_CLK=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_I2C=y
Applied to u-boot-marvell/master
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Stefan
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Re: [U-Boot] [PATCH] dts: mvebu: mcbin: drop redundant SD slot node
On 20.08.2018 14:12, Baruch Siach wrote:
Commit 61dccf73d302 (dts: mvebu: a80x0: Enable SD/eMMC interfaces) added
a redundant DT node for SD card slot. Drop it.
Cc: Konstantin Porotchkin
Signed-off-by: Baruch Siach
---
arch/arm/dts/armada-8040-mcbin.dts | 8
1 file changed, 8 deletions(-)
diff --git a/arch/arm/dts/armada-8040-mcbin.dts
b/arch/arm/dts/armada-8040-mcbin.dts
index 08f1d7df69aa..f912596c2cde 100644
--- a/arch/arm/dts/armada-8040-mcbin.dts
+++ b/arch/arm/dts/armada-8040-mcbin.dts
@@ -154,14 +154,6 @@
status = "okay";
};
-/* uSD slot */
-_sdhci0 {
- pinctrl-names = "default";
- pinctrl-0 = <_sdhci_pins>;
- bus-width = <4>;
- status = "okay";
-};
-
_comphy {
/*
* CP0 Serdes Configuration:
Applied to u-boot-marvell/master
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Re: [U-Boot] [PATCH u-boot-marvell v2 12/12] arch/arm/mvebu: Support 1 GB version of Turris Mox
On 17.08.2018 12:59, Marek Behún wrote:
Add configuration variables to differentiate between the 512 MB and 1 GB
versions of Turris Mox and change the RAM size in U-Boot's device tree
accordingly.
Signed-off-by: Marek Behun
---
MAINTAINERS | 7 +++
arch/arm/dts/armada-3720-turris-mox-u-boot.dtsi | 16
arch/arm/mach-mvebu/Kconfig | 15 +++
configs/turris_mox_defconfig| 1 +
4 files changed, 39 insertions(+)
create mode 100644 arch/arm/dts/armada-3720-turris-mox-u-boot.dtsi
diff --git a/MAINTAINERS b/MAINTAINERS
index 1893090b8f..1a55d80c13 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -360,6 +360,13 @@ S: Maintained
T:git git://git.denx.de/u-boot-coldfire.git
F:arch/m68k/
+CZ.NIC TURRIS
+M: Marek Behun
+S: Maintained
+F: arch/arm/dts/armada-3720-turris-mox.dts
+F: arch/arm/dts/armada-3720-turris-mox-u-boot.dtsi
+F: board/CZ.NIC/
+
DFU
M:Lukasz Majewski
S:Maintained
diff --git a/arch/arm/dts/armada-3720-turris-mox-u-boot.dtsi
b/arch/arm/dts/armada-3720-turris-mox-u-boot.dtsi
new file mode 100644
index 00..122f5c8ae1
--- /dev/null
+++ b/arch/arm/dts/armada-3720-turris-mox-u-boot.dtsi
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0+ or X11
+/*
+ * 2018 by Marek Behun
+ */
+
+#include
+
+/ {
+ memory {
+#ifdef CONFIG_TARGET_TURRIS_MOX_1GB
+ reg = <0x 0x 0x 0x4000>;
+#else
+ reg = <0x 0x 0x 0x2000>;
+#endif
+ };
+};
diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
index d1f71338ac..3e88b3757b 100644
--- a/arch/arm/mach-mvebu/Kconfig
+++ b/arch/arm/mach-mvebu/Kconfig
@@ -198,6 +198,21 @@ config MVEBU_SPL_BOOT_DEVICE_UART
endchoice
+if TARGET_TURRIS_MOX
+
+choice
+ prompt "Turris Mox RAM size"
+
+config TARGET_TURRIS_MOX_512MB
+ bool "512 MB"
+
+config TARGET_TURRIS_MOX_1GB
+ bool "1 GB"
+
+endchoice
+
+endif
+
config MVEBU_EFUSE
bool "Enable eFuse support"
default n
diff --git a/configs/turris_mox_defconfig b/configs/turris_mox_defconfig
index cc28a1fe95..2bcbdd8133 100644
--- a/configs/turris_mox_defconfig
+++ b/configs/turris_mox_defconfig
@@ -3,6 +3,7 @@ CONFIG_ARCH_MVEBU=y
CONFIG_SYS_TEXT_BASE=0x
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_TURRIS_MOX=y
+CONFIG_TARGET_TURRIS_MOX_512MB=y
CONFIG_DEBUG_UART_BASE=0xd0012000
CONFIG_DEBUG_UART_CLOCK=25804800
CONFIG_DEFAULT_DEVICE_TREE="armada-3720-turris-mox"
This patch does not apply currently. I'm skipping it from this
series for now. I'm currently pushing my Marvell branch upstream
and would like to get the first batch of patches accepted. After
Tom has pulled these patches, please rebase on top of this new
master.
Thanks,
Stefan
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Re: [U-Boot] [PATCH u-boot-marvell v2 11/12] arch/arm/dts: Update Turris Mox device tree
On 17.08.2018 12:59, Marek Behún wrote:
Remove smi_pins definition since it is already in armada-37xx.dtsi.
Add assigned-clocks definitions to spi0.
Signed-off-by: Marek Behun
---
arch/arm/dts/armada-3720-turris-mox.dts | 10 +++---
1 file changed, 3 insertions(+), 7 deletions(-)
diff --git a/arch/arm/dts/armada-3720-turris-mox.dts
b/arch/arm/dts/armada-3720-turris-mox.dts
index 05904387d2..9c96dd39a9 100644
--- a/arch/arm/dts/armada-3720-turris-mox.dts
+++ b/arch/arm/dts/armada-3720-turris-mox.dts
@@ -94,17 +94,13 @@
};
};
-_sb {
- smi_pins: smi-pins {
- groups = "smi";
- function = "smi";
- };
-};
-
{
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <_cs1_pins>;
+ assigned-clocks = <_periph_clk 7>;
+ assigned-clock-parents = < 1>;
+ assigned-clock-rates = <2000>;
spi-flash@0 {
#address-cells = <1>;
Applied to u-boot-marvell/master
Thanks,
Stefan
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Re: [U-Boot] [PATCH u-boot-marvell v2 10/12] board: turris_mox: Add gpio command to defconfig
On 17.08.2018 12:59, Marek Behún wrote: This can be used to detect whether the button is pressed or light LEDs. Signed-off-by: Marek Behun --- configs/turris_mox_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/turris_mox_defconfig b/configs/turris_mox_defconfig index fb4192df56..cc28a1fe95 100644 --- a/configs/turris_mox_defconfig +++ b/configs/turris_mox_defconfig @@ -16,6 +16,7 @@ CONFIG_ARCH_EARLY_INIT_R=y CONFIG_OF_BOARD_FIXUP=y CONFIG_OF_BOARD_SETUP=y CONFIG_CMD_CLK=y +CONFIG_CMD_GPIO=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y This patch does not apply currently. I'm skipping it from this series for now. I'm currently pushing my Marvell branch upstream and would like to get the first batch of patches accepted. After Tom has pulled these patches, please rebase on top of this new master. Thanks, Stefan ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
