On 22.10.18 06:37, AKASHI Takahiro wrote:
> On Thu, Oct 18, 2018 at 10:46:36AM +0200, Alexander Graf wrote:
>>
>>
>> On 18.10.18 07:48, AKASHI Takahiro wrote:
>>> On Wed, Oct 17, 2018 at 10:43:22AM +0200, Alexander Graf wrote:
On 17.10.18 09:32, AKASHI Takahiro wrote:
> With th
On Sat, Oct 20, 2018 at 6:09 AM Lukas Auer
wrote:
>
> CONFIG_PHYS_64BIT should be enabled on RV64I systems. Select it.
>
> Signed-off-by: Lukas Auer
> ---
>
> arch/riscv/Kconfig | 1 +
> 1 file changed, 1 insertion(+)
>
Reviewed-by: Bin Meng
___
U-Bo
Hi Lukas,
On Sat, Oct 20, 2018 at 6:09 AM Lukas Auer
wrote:
>
> RISC-V defines the base integer instruction sets as RV32I and RV64I.
> Rename CPU_RISCV_32 and CPU_RISCV_64 to ARCH_RV32I and ARCH_64I to match
ARCH_RV64I
> this convention.
>
> Signed-off-by: Lukas Auer
> ---
>
> arch/riscv/Kcon
On Sat, Oct 20, 2018 at 6:08 AM Lukas Auer
wrote:
>
> Ignore tools/prelink-riscv.
>
> Signed-off-by: Lukas Auer
> ---
>
> tools/.gitignore | 1 +
> 1 file changed, 1 insertion(+)
>
Reviewed-by: Bin Meng
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On Sat, Oct 20, 2018 at 6:09 AM Lukas Auer
wrote:
>
> Signed-off-by: Lukas Auer
> ---
>
> dts/Makefile | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
Reviewed-by: Bin Meng
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Hi Lukas,
On Sat, Oct 20, 2018 at 6:08 AM Lukas Auer
wrote:
>
> Ignore all device tree binaries in arch/riscv/dts.
I don't think this patch is necessary.
>
> Signed-off-by: Lukas Auer
> ---
>
> arch/riscv/dts/.gitignore | 1 +
> 1 file changed, 1 insertion(+)
> create mode 100644 arch/riscv/
On Thu, Oct 18, 2018 at 10:39:30AM +0200, Alexander Graf wrote:
>
>
> On 18.10.18 09:57, AKASHI Takahiro wrote:
> > On Wed, Oct 17, 2018 at 10:40:26AM +0200, Alexander Graf wrote:
> >>
> >>
> >> On 17.10.18 09:32, AKASHI Takahiro wrote:
> >>> In this patch, helper functions for an load option var
Hello Anatolij,
Am 18.10.2018 um 16:36 schrieb Anatolij Gustschin:
Output the register base address in hex notation.
Signed-off-by: Anatolij Gustschin
---
drivers/i2c/imx_lpi2c.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
builds fine on travis:
https://travis-ci.org/hsdenx
On Thu, Oct 18, 2018 at 10:46:36AM +0200, Alexander Graf wrote:
>
>
> On 18.10.18 07:48, AKASHI Takahiro wrote:
> > On Wed, Oct 17, 2018 at 10:43:22AM +0200, Alexander Graf wrote:
> >>
> >>
> >> On 17.10.18 09:32, AKASHI Takahiro wrote:
> >>> With this patch applied, we will be able to selectivel
Hi Takahiro,
On Mon, Oct 22, 2018 at 12:35 PM AKASHI Takahiro
wrote:
>
> On Fri, Oct 19, 2018 at 06:16:30PM +0800, Bin Meng wrote:
> > Hi,
> >
> > On Fri, Oct 19, 2018 at 4:55 PM AKASHI Takahiro
> > wrote:
> > >
> > > Define a missing CONFIG_SYS_SOC and move some CONFIG_SYS_* to a more
> > > can
Define a missing CONFIG_SYS_SOC and move some CONFIG_SYS_* to a more
canonical place (i.e. under board).
Signed-off-by: AKASHI Takahiro
---
arch/arm/mach-qemu/Kconfig | 18 ++
board/emulation/qemu-arm/Kconfig | 6 ++
2 files changed, 16 insertions(+), 8 deletions(-)
d
This variable, fdt_addr_t, is missing in the current qemu-arm.h while it
seems to be mandatory, at least, to run distro_bootcmd as expected.
So just add its definition. A size of 1MB would be enough.
Signed-off-by: AKASHI Takahiro
---
include/configs/qemu-arm.h | 1 +
1 file changed, 1 insertion
The current scenario for default UEFI booting, scan_dev_for_efi, has
several issues:
* load dtb dynamically even if its loacation (device) is not the same
as BOOTEFI_NAME binary's, (reported by Alex)
* invoke 'bootmgr' only if BOOTEFI_NAME binary does exit even though
'bootmgr' can and should w
The current distro_bootcmd has several issues regarding efi boot.
(See the patch#1 for details.)
Patch#1: fix distro's issues and make its intent clear
Patch#2,#3: address related issues on qemu-arm
Please note that patch#2 is now rebased on Bin's patch[1].
[1] https://lists.denx.de/pipermail/u-
On Fri, Oct 19, 2018 at 06:16:30PM +0800, Bin Meng wrote:
> Hi,
>
> On Fri, Oct 19, 2018 at 4:55 PM AKASHI Takahiro
> wrote:
> >
> > Define a missing CONFIG_SYS_SOC and move some CONFIG_SYS_* to a more
> > canonical place (i.e. under board).
> >
> > Signed-off-by: AKASHI Takahiro
> > ---
> > ar
Hi Poonam,
On Mon, Oct 22, 2018 at 11:43 AM Poonam Aggrwal wrote:
>
>
>
> > -Original Message-
> > From: Bin Meng [mailto:bmeng...@gmail.com]
> > Sent: Monday, October 22, 2018 7:41 AM
> > To: York Sun
> > Cc: Poonam Aggrwal ; U-Boot Mailing List > b...@lists.denx.de>
> > Subject: Re: [
> -Original Message-
> From: Bin Meng [mailto:bmeng...@gmail.com]
> Sent: Monday, October 22, 2018 7:41 AM
> To: York Sun
> Cc: Poonam Aggrwal ; U-Boot Mailing List b...@lists.denx.de>
> Subject: Re: [PATCH 1/2] powerpc: t1040: Correct RCW MAC2_GMII_SEL value
>
> On Mon, Oct 15, 2018 a
Enable related configs to support sata DM feature.
Signed-off-by: Peng Ma
---
configs/ls2080aqds_defconfig |5 +
configs/ls2080ardb_defconfig |5 +
2 files changed, 10 insertions(+), 0 deletions(-)
diff --git a/configs/ls2080aqds_defconfig b/configs/ls2080aqds_defconfig
index 30
One ls2080a, there is one SATA 3.0 advanced host controller interface
which is a high-performance SATA solution that delivers comprehensive
and fully-compliant generation 3 (1.5 Gb/s - 6.0 Gb/s) serial ATA
capabilities, in accordance with the serial ATA revision 3.0 of Serial
ATA International Orga
Add ahci compatible support for ls2080a soc.
Signed-off-by: Peng Ma
---
depend on:
- https://patchwork.ozlabs.org/patch/987497/
drivers/ata/sata_ceva.c |3 +++
1 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/drivers/ata/sata_ceva.c b/drivers/ata/sata_ceva.c
index fa867
One ls1088a, there is one SATA 3.0 advanced host controller interface
which is a high-performance SATA solution that delivers comprehensive
and fully-compliant generation 3 (1.5 Gb/s - 6.0 Gb/s) serial ATA
capabilities, in accordance with the serial ATA revision 3.0 of Serial
ATA International Orga
Enable related configs to support sata DM feature.
Signed-off-by: Peng Ma
---
configs/ls1088aqds_defconfig |5 +
configs/ls1088ardb_qspi_defconfig |5 +
2 files changed, 10 insertions(+), 0 deletions(-)
diff --git a/configs/ls1088aqds_defconfig b/configs/ls1088aqds_defconfi
Add ahci compatible support for ls1088a soc.
Signed-off-by: Peng Ma
---
depend on:
- https://patchwork.ozlabs.org/patch/982386/
drivers/ata/sata_ceva.c | 22 ++
1 files changed, 18 insertions(+), 4 deletions(-)
diff --git a/drivers/ata/sata_ceva.c b/drivers/ata/sa
On Mon, Oct 15, 2018 at 1:21 PM Bin Meng wrote:
>
> On Mon, Oct 8, 2018 at 11:07 PM York Sun wrote:
> >
> > On 10/08/2018 06:51 AM, Bin Meng wrote:
> > > Per T1040RM (Rev. 1, 08/2015), the value of
> > > FSL_CORENET_RCWSR13_MAC2_GMII_SEL_ENET_PORT is wrong
> > > and should be 0x0080 (bit 440
> From: Lukas Auer [mailto:lukas.a...@aisec.fraunhofer.de]
> Sent: Saturday, October 20, 2018 6:08 AM
> To: u-boot@lists.denx.de
> Cc: Bin Meng; Lukas Auer; Greentime Hu; Alexander Graf; Rick Jian-Zhi
> Chen(陳建志)
> Subject: [PATCH 18/30] riscv: invalidate the instruction cache before jumping
> to
On Wed, Oct 10, 2018 at 09:27:09PM +0200, Marek Vasut wrote:
> Add test which checks if a PCI device described in DT with an
> entry and reg = <...> property, but without compatible string
> results in a valid U-Boot PCI udevice with the udevice.node
> populated with reference to this DT node. Als
On Wed, Oct 10, 2018 at 09:27:08PM +0200, Marek Vasut wrote:
> Add PCI entry without compatible string and with a DT node only with
> reg = <...> property into the DT. This is needed for the tests to
> verify whether such a setup creates an U-Boot PCI device with the
> DT node associated with it i
On Wed, Oct 10, 2018 at 09:27:07PM +0200, Marek Vasut wrote:
> Reword the documentation to make it clear the compatible string is now
> optional, yet still matching on it takes precedence over PCI IDs and
> PCI classes.
>
> Signed-off-by: Marek Vasut
> Cc: Simon Glass
> Cc: Tom Rini
> Reviewed
On Wed, Oct 10, 2018 at 09:27:06PM +0200, Marek Vasut wrote:
> The PCI controller can have DT subnodes describing extra properties
> of particular PCI devices, ie. a PHY attached to an EHCI controller
> on a PCI bus. This patch parses those DT subnodes and assigns a node
> to the PCI device instan
在 2018-05-17四的 09:16 +0100，Andre Przywara写道：
> This series tries to solve three issues we currently have on
> Allwinner boards:
> - The DRAM sizing routine can only cope with power-of-two sized DRAM.
> - The DRAM sizing routine steps through all DRAM, possibly hitting
> secure
> memory.
> - The S
README.omap3 has two options. For option 1, CONFIG_SYS_TEXT_BASE
is set to 0x8010. Option 2 lists 0x80008000. The existing
value is neither of these, so this patch makes it equivalent to
Option 1.
Signed-off-by: Adam Ford
diff --git a/configs/omap35_logic_defconfig b/configs/omap35_logic_
In an effort to free up more resources in SPL and U-Boot, building
for Thumb shrinks the code side.
Before:
text data bss dec hex filename
685588 25808 275724 987120 f0ff0 u-boot
text data bss dec hex filename
55324 417 67460 123201 1e141 spl
The AM3517 is mostly am omap3, so this partch removes the custom
memory configurations and just uses the default common entries
for omap3 and armv7.
Signed-off-by: Adam Ford
diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h
index 0463e42048..4e7e5209d4 100644
--- a/include
Some minor changes have been made to the AM3517-evm and the underlying
am3517.dtsi files. This patch re-sync's the DTS and DTSI files with
Linux.
Signed-off-by: Adam Ford
diff --git a/arch/arm/dts/am3517-evm.dts b/arch/arm/dts/am3517-evm.dts
index 98aadb0f81..1d158cfda1 100644
--- a/arch/arm/dt
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