From: Tien Fong Chee
Ensure the string for filename is always constant, otherwise it can be
corrupted by the writing.
Signed-off-by: Tien Fong Chee
---
drivers/fpga/zynqpl.c |3 ++-
include/fpga.h|2 +-
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git
On Wed, 13 Feb 2019 17:46:44 +0100
Krzysztof Kozlowski wrote:
> Fix detection of Odroid HC1 (Exynos5422) after reboot if kernel
> disabled the LDO4/VDD_ADC regulator.
>
> The LDO4 supplies both ADC block and the ADC input AIN9. Voltage on
> AIN9 will rise slowly, so be patient and wait for it
On Wed, 13 Feb 2019 17:46:46 +0100
Krzysztof Kozlowski wrote:
> According to datasheet, the output on LDO regulators will start
> appearing after 10-15 us.
>
> Signed-off-by: Krzysztof Kozlowski
> ---
> drivers/power/regulator/s2mps11_regulator.c | 9 -
> 1 file changed, 8
On Wed, 13 Feb 2019 17:46:47 +0100
Krzysztof Kozlowski wrote:
> The ADC block requires VDD supply to be on so provide one.
>
> Signed-off-by: Krzysztof Kozlowski
> ---
> arch/arm/dts/exynos5422-odroidxu3.dts | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git
On Fri, Feb 15, 2019 at 3:12 PM Chris Packham wrote:
>
> Enable the hardware watchdog to guard against system lock ups when
> running in the SPL or U-Boot. Stop the watchdog just before booting so
> that the OS.
D'oh managed to cut off the sentence.
so that the OS can re-enable it if needed.
On Wed, 13 Feb 2019 17:46:41 +0100
Krzysztof Kozlowski wrote:
> LDO27 and LDO35 have 25 mV step, not 50 mV.
>
> Signed-off-by: Krzysztof Kozlowski
> ---
> drivers/power/regulator/s2mps11_regulator.c | 4
> 1 file changed, 4 insertions(+)
>
> diff --git
On Wed, 13 Feb 2019 17:46:40 +0100
Krzysztof Kozlowski wrote:
> When stopping the ADC_V2_CON1_STC_EN should be cleared.
>
> Signed-off-by: Krzysztof Kozlowski
> ---
> drivers/adc/exynos-adc.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/adc/exynos-adc.c
Hi Lukas
> > From: Lukas Auer [mailto:lukas.a...@aisec.fraunhofer.de]
> > Sent: Tuesday, February 12, 2019 6:14 AM
> > To: u-boot@lists.denx.de
> > Cc: Atish Patra; Anup Patel; Bin Meng; Andreas Schwab; Palmer Dabbelt;
> > Alexander Graf; Lukas Auer; Anup Patel; Rick Jian-Zhi Chen(陳建志); Baruch
>
On 2/15/19 1:56 AM, André Przywara wrote:
On 14/02/2019 08:36, Jagan Teki wrote:
Allwinner support two different SPI controllers one for A10 and
another for A31 with minimal changes in register offsets and
respective register bits, but the logic for accessing the SPI
master via SPI slave
From: Tien Fong Chee
In previously label which will be expanded to the node's full path was
used, and now replacing label with most commonly used DT phandle. The
codes were changed accordingly to the use of DT phandle and supporting
multiple instances.
Signed-off-by: Tien Fong Chee
---
When TFA is used as EL3 firmware, then u-boot is crashing
because DDR is not coherent.
Changing DDR memory attributes to device type fix the issue.
Signed-off-by: Meenakshi Aggarwal
Signed-off-by: Udit Kumar
---
arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 7 ---
1 file changed, 4
On 14/02/19 10:39 PM, Jagan Teki wrote:
> + Vignesh
>
> On Mon, Jan 7, 2019 at 11:05 AM Ye Li wrote:
>>
>> On i.MX7ULP EVK board, we use MX25R6435F NOR flash, add its parameters
>> and IDs to flash parameter array. Otherwise, the flash probe will fails.
>>
>> Signed-off-by: Ye Li
>> ---
>>
> -Original Message-
> From: Y.b. Lu
> Sent: 2019年2月15日 10:26
> To: u-boot@lists.denx.de
> Cc: Jaehoon Chung ; Prabhakar Kushwaha
> ; Peng Fan ; Y.b. Lu
>
> Subject: [v2, 1/3] mmc: fsl_esdhc: add esdhc_imx flag
>
> The fsl_esdhc driver was for Freescale eSDHC on MPC83XX/MPC85XX
> -Original Message-
> From: Fabio Estevam [mailto:feste...@gmail.com]
> Sent: 2019年2月14日 21:36
> To: sba...@denx.de
> Cc: u-boot@lists.denx.de; Peng Fan ; Fabio Estevam
>
> Subject: [PATCH v2] mx6ul_14x14_evk: Simplify the PMIC register writes
>
> There is no need to store the values
> -Original Message-
> From: Peng Fan
> Sent: Thursday, February 14, 2019 5:11 PM
> To: Y.b. Lu ; u-boot@lists.denx.de
> Cc: Jaehoon Chung ; Prabhakar Kushwaha
>
> Subject: RE: [PATCH 1/3] mmc: fsl_esdhc: add esdhc_imx flag
>
>
>
> > -Original Message-
> > From: Y.b. Lu
> >
The fsl_esdhc driver was for Freescale eSDHC on MPC83XX/MPC85XX
initially. The later QoriQ series processors (which are evolutions
of MPC83XX/MPC85XX) and i.MX series processors were using this
driver for their eSDHCs too.
So there are two evolution directions for eSDHC now. For the two
series
A previous patch had added SDR104/HS200 support for fsl_esdhc.
However this was only for i.MX eSDHC, and QorIQ eSDHC used
different registers and method.
This patch is to clarify i.MX eSDHC specific functions defined
in that patch, and to use them only for i.MX eSDHC. The QorIQ
eSDHC SDR104/HS200
The fsl_esdhc driver was for Freescale eSDHC on MPC83XX/MPC85XX
initially. The later QoriQ series processors (which were evolutions
of MPC83XX/MPC85XX) and i.MX series processors were using this
driver for their eSDHCs too.
So there are two evolution directions for eSDHC now. For the two
series
The README.da850 file continues information on how to burn NAND
for the LCDK, but not the DA850-EVM. This patch adds both the
commands and dip switch instructions for burning and booting
NAND.
Signed-off-by: Adam Ford
diff --git a/board/davinci/da8xxevm/README.da850
We've seen some issues with the x530 under extreme conditions where the
DDR gets into a bad state. Generally this results in an application
crash, kernel panic then a lock-up in u-boot (generally just as the SPL
hands off to u-boot proper).
Enabling the watchdog prevents the lock up and will let
When run from the SPL the mvebu targets are using the hardware default
offset for the SoC peripherals. devfdt_get_addr_size_index() understands
how to deal with this via dm_get_translation_offset() so use this
instead of fdtdec_get_addr_size_auto_noparent().
Signed-off-by: Chris Packham
---
Enable the hardware watchdog to guard against system lock ups when
running in the SPL or U-Boot. Stop the watchdog just before booting so
that the OS.
Signed-off-by: Chris Packham
---
arch/arm/dts/armada-385-atl-x530-u-boot.dtsi | 4 ++
board/alliedtelesis/x530/x530.c | 48
Am 15.02.2019 00:42 schrieb Stephen Warren :
>
> On 2/14/19 4:25 PM, Tristan Bastian wrote:
> > This patch enables UMS on the nyan devices like the nyan-big.
> > A patch like this has been sent in by Stephen Warren some time ago for
> > other tegra devices: commit
Signed-off-by: Masahiro Yamada
---
arch/arm/dts/uniphier-ld20.dtsi | 11 ---
arch/arm/dts/uniphier-ld4.dtsi | 14 ++
arch/arm/dts/uniphier-pro4.dtsi | 16
arch/arm/dts/uniphier-pxs2.dtsi | 6 --
arch/arm/dts/uniphier-sld8.dtsi | 14 ++
5
On 14/02/2019 08:36, Jagan Teki wrote:
> - drop unused macros.
> - use base instead of base_addr, for better code readability
Actually this part is now pretty pointless, since we use it only a few
times, and base_addr is actually more descriptive than just "base".
> - move .probe and
On 14/02/2019 08:36, Jagan Teki wrote:
Hi,
> Add A31 spi controller support for existing sun4i_spi driver via driver
> data, this would simply add A31 register along with proper register bits
> via enum sets.
>
> Signed-off-by: Jagan Teki
> ---
> drivers/spi/Kconfig | 4 +-
>
On 14/02/2019 08:36, Jagan Teki wrote:
> Allwinner support two different SPI controllers one for A10 and
> another for A31 with minimal changes in register offsets and
> respective register bits, but the logic for accessing the SPI
> master via SPI slave remains nearly similar.
>
> Add enum
On 14/02/2019 08:36, Jagan Teki wrote:
> Add CLK support to enable AHB and MOD SPI clocks on sun4i_spi driver.
>
> Note, that the code will enable and disable clock in claim and release
> calls to make proper clock and reset handling between claiming and
> releasing SPI bus.
That doesn't really
On 14/02/2019 08:36, Jagan Teki wrote:
> To drain rx fifo the fifo need to poll till the fifo
> count become empty.
Thanks for the changes!
Just realised, the description is somewhat misleading: We are not
waiting for the FIFO count to become empty, but actually for the RX FIFO
to fill up. Can
On 2/14/19 4:25 PM, Tristan Bastian wrote:
This patch enables UMS on the nyan devices like the nyan-big.
A patch like this has been sent in by Stephen Warren some time ago for other
tegra devices: commit e6607cffef965011ef0ddc0fbe6f4b7c0d53aeec
But the nyan devices never received that
Le 15/02/2019 à 00:08, Fabio Estevam a écrit :
Hi Joris,
On Thu, Feb 14, 2019 at 8:46 PM Joris Offouga wrote:
it is not possible to convert that i2c and do not convert the pmic. on
Ok, we can skip I2C and PMIC for now.
the other hand, even without pmic and usb conversion there is always
This patch enables UMS on the nyan devices like the nyan-big.
A patch like this has been sent in by Stephen Warren some time ago for other
tegra devices: commit e6607cffef965011ef0ddc0fbe6f4b7c0d53aeec
But the nyan devices never received that functionality.
v2: fixed corrupted patch
Hi Joris,
On Thu, Feb 14, 2019 at 8:46 PM Joris Offouga wrote:
> it is not possible to convert that i2c and do not convert the pmic. on
Ok, we can skip I2C and PMIC for now.
> the other hand, even without pmic and usb conversion there is always the
> dfu error when i try to update u-boot via
On 2/13/19 9:46 PM, Lokesh Vutla wrote:
>
>
> On 14/02/19 12:07 AM, Andrew F. Davis wrote:
>> K3 HS devices require signed binaries for boot, use the SECDEV tools
>> to sign the boot artifacts during build.
>>
>> Signed-off-by: Andrew F. Davis
>> ---
>> MAINTAINERS | 1 +
On 2/14/19 3:49 PM, Tristan Bastian wrote:
This patch enables UMS on the nyan devices like the nyan-big.
A patch like this has been sent in by Stephen Warren some time ago for
other tegra devices: commit e6607cffef965011ef0ddc0fbe6f4b7c0d53aeec
But the nyan devices never received that
This patch enables UMS on the nyan devices like the nyan-big.
A patch like this has been sent in by Stephen Warren some time ago for
other tegra devices: commit e6607cffef965011ef0ddc0fbe6f4b7c0d53aeec
But the nyan devices never received that functionality.
Signed-off-by: Tristan Bastian
---
Hi Fabio
On 14 Feb 2019, at 17:48, Fabio Estevam wrote:
Hi Joris,
On Thu, Feb 14, 2019 at 2:42 PM Joris Offouga wrote:
Since I do not convert the pmic, I do not convert the i2c either ?
I think it is OK to convert I2C now.
it is not possible to convert that i2c and do not convert the
Hello,
On my nyan-big Chromebook(tegra124) efi booting is broken since stable
v2019.01.
v2018.11 is working fine..
I'm not sure if other tegra devices are working or not..
I'm getting the following output with u-boot v2019.01 if I try to start
grub-efi-arm to boot ubuntu:
[...]
67482
Hi Jon, Hi Stephen,
could you take a look at these two patches since I didn't get heard
anything from Tom..
Thanks,
Tristan
Am 21.01.19 um 22:55 schrieb Simon Glass:
On Thu, 17 Jan 2019 at 10:33, Simon Glass wrote:
On Wed, 16 Jan 2019 at 11:50, Tristan Bastian wrote:
Internal keyboard
On 2/13/19 9:32 PM, Lokesh Vutla wrote:
>
>
> On 14/02/19 12:07 AM, Andrew F. Davis wrote:
>> On HS devices the 512b region of reset isolated memory called
>> MCU_PSRAM0 is firewalled by default. Until SYSFW is loaded we
>> cannot use this memory. It is only used to store a single value
>> left
> On 13.02.2019, at 22:38, Heinrich Schuchardt wrote:
>
> The SPL image for the Tinker Board has to fit into 32 KiB. This includes
> 4 KiB for the device tree and up to 2 KiB for the file header.
>
> A new configuration variable CONFIG_SPL_WITH_DTB_SIZE_LIMIT is introduced
> to define the
On Thu, Feb 14, 2019 at 10:42:51PM +0530, Jagan Teki wrote:
> Hi Anatolij,
>
> On Wed, Dec 19, 2018 at 6:36 PM Priit Laes wrote:
> >
> > From: Priit Laes
> >
> > Current EDID detailed timing parser errors out when either
> > horizontal or vertical pulse sync width is 0, thus not
> > allowing a
On 14/02/2019 16:36, Philipp Tomsich wrote:
>
>
>> On 14.02.2019, at 16:58, Michael Trimarchi
>> wrote:
>>
>> Set two rank timing and exit self-refresh timing seems not done
>> properly. We know use the same write that we are using
>> on H5 silicon. Tested was done in A33 allwinner cpu, dual
The other OMAP3 based Logic PD boards have Falcon Mode enabled,
so this patch makes it possible on the AM3517-evm as well.
Signed-off-by: Adam Ford
diff --git a/configs/am3517_evm_defconfig b/configs/am3517_evm_defconfig
index 7a74e9e90d..9ba518f3d2 100644
--- a/configs/am3517_evm_defconfig
+++
Am 19.01.2019 um 17:57 schrieb Tom Rini:
On Sat, Jan 19, 2019 at 05:52:46PM +0100, Simon Goldschmidt wrote:
Hi Tom,
Am Fr., 18. Jan. 2019, 23:02 hat Tom Rini geschrieben:
On Mon, Jan 07, 2019 at 10:12:42AM +0100, Simon Goldschmidt wrote:
On Wed, Jan 2, 2019 at 9:13 PM Simon Goldschmidt
On 2/14/19 2:35 PM, Alexander Graf wrote:
> Heinrich is going to take over maintainership of the efi_loader tree
> going forward.
>
> To ensure that I will still receive review mails at least, add me as
> reviewer with a stable email address.
>
> Signed-off-by: Alexander Graf
Signed-off-by:
On Thu, 2019-02-14 at 17:26 +0100, Marek Vasut wrote:
> On 2/14/19 4:47 PM, Chee, Tien Fong wrote:
> >
> > On Thu, 2019-02-14 at 16:13 +0100, Marek Vasut wrote:
> > >
> > > On 2/14/19 4:11 PM, Chee, Tien Fong wrote:
> > > >
> > > >
> > > > On Thu, 2019-02-14 at 13:24 +0100, Marek Vasut wrote:
On Thu, 2019-02-14 at 17:27 +0100, Marek Vasut wrote:
> On 2/14/19 4:37 PM, Chee, Tien Fong wrote:
> >
> > On Thu, 2019-02-14 at 16:21 +0100, Marek Vasut wrote:
> > >
> > > On 2/14/19 4:15 PM, Chee, Tien Fong wrote:
> > > >
> > > >
> > > > On Thu, 2019-02-14 at 13:28 +0100, Marek Vasut wrote:
On 2/14/19 4:37 PM, Chee, Tien Fong wrote:
> On Thu, 2019-02-14 at 16:21 +0100, Marek Vasut wrote:
>> On 2/14/19 4:15 PM, Chee, Tien Fong wrote:
>>>
>>> On Thu, 2019-02-14 at 13:28 +0100, Marek Vasut wrote:
On 2/14/19 12:38 PM, Chee, Tien Fong wrote:
>
>
> On Thu, 2019-02-14
On 2/14/19 4:47 PM, Chee, Tien Fong wrote:
> On Thu, 2019-02-14 at 16:13 +0100, Marek Vasut wrote:
>> On 2/14/19 4:11 PM, Chee, Tien Fong wrote:
>>>
>>> On Thu, 2019-02-14 at 13:24 +0100, Marek Vasut wrote:
On 2/14/19 12:23 PM, Chee, Tien Fong wrote:
>
>
> On Thu, 2019-02-14
On Thu, 2019-02-14 at 16:33 +, Westergreen, Dalon wrote:
> On Thu, 2019-02-14 at 15:15 +, Chee, Tien Fong wrote:
> >
> > On Thu, 2019-02-14 at 13:28 +0100, Marek Vasut wrote:
> > >
> > > On 2/14/19 12:38 PM, Chee, Tien Fong wrote:
> > > >
> > > > On Thu, 2019-02-14 at 11:42 +0100, Marek
On Thu, 2019-02-14 at 16:59 +, Chee, Tien Fong wrote:
> On Thu, 2019-02-14 at 16:33 +, Westergreen, Dalon wrote:
> > On Thu, 2019-02-14 at 15:15 +, Chee, Tien Fong wrote:
> > > On Thu, 2019-02-14 at 13:28 +0100, Marek Vasut wrote:
> > > > On 2/14/19 12:38 PM, Chee, Tien Fong wrote:
> >
Hi Tom,
PR about some random fixes.
Summary:
- MMC CD pin fix on Orangepi Zero plus
- SPI boot for Olinuxino Lime2-eMMC boards
- Change in dram frequnecy for tbs_a711
The following changes since commit dbe70c7d4e3d5c705a98d82952e05a591efd0683:
Merge branch 'master' of
Hi Anatolij,
On Wed, Dec 19, 2018 at 6:36 PM Priit Laes wrote:
>
> From: Priit Laes
>
> Current EDID detailed timing parser errors out when either
> horizontal or vertical pulse sync width is 0, thus not
> allowing a display with EDID listed below work properly.
>
> Of-course, this is somewhat
+ Vignesh
On Mon, Jan 7, 2019 at 11:05 AM Ye Li wrote:
>
> On i.MX7ULP EVK board, we use MX25R6435F NOR flash, add its parameters
> and IDs to flash parameter array. Otherwise, the flash probe will fails.
>
> Signed-off-by: Ye Li
> ---
> drivers/mtd/spi/spi_flash_ids.c | 1 +
> 1 file changed,
On Tue, Feb 12, 2019 at 7:14 PM Patrick DELAUNAY
wrote:
>
> Hi Jagan
>
> > From: Jagan Teki
> > Sent: samedi 9 février 2019 17:22
> > Subject: Re: [PATCH v3] dm: spi: Read default speed and mode values from DT
> >
> > On Mon, Jan 28, 2019 at 2:37 PM Patrick Delaunay
> > wrote:
> > >
> > > This
On Thu, 2019-02-14 at 16:33 +, Westergreen, Dalon wrote:
> On Thu, 2019-02-14 at 15:15 +, Chee, Tien Fong wrote:
> >
> > On Thu, 2019-02-14 at 13:28 +0100, Marek Vasut wrote:
> > >
> > > On 2/14/19 12:38 PM, Chee, Tien Fong wrote:
> > > >
> > > > On Thu, 2019-02-14 at 11:42 +0100, Marek
On 2019-02-14, Baruch Siach wrote:
> On Thu, Feb 14 2019, Vagrant Cascadian wrote:
>> On 2019-02-14, Baruch Siach wrote:
>>> On Wed, Feb 13 2019, Fabio Estevam wrote:
On Wed, Feb 13, 2019 at 2:52 PM Vagrant Cascadian
wrote:
>
> I *think* this board is getting the wrong fdtfile
Hi Joris,
On Thu, Feb 14, 2019 at 2:42 PM Joris Offouga wrote:
> Since I do not convert the pmic, I do not convert the i2c either ?
I think it is OK to convert I2C now.
Thanks
___
U-Boot mailing list
U-Boot@lists.denx.de
Le 14/02/2019 à 13:58, Fabio Estevam a écrit :
Hi Joris,
On Thu, Feb 14, 2019 at 10:15 AM Offouga Joris wrote:
Hi Fabio
I am preparing the next and I hope to be able to send it soon. give me the
instructions to follow and I will add them
Please check the series I have just sent converting
Hi Philipp
On Thu, Feb 14, 2019 at 5:36 PM Philipp Tomsich
wrote:
>
>
>
> > On 14.02.2019, at 16:58, Michael Trimarchi
> > wrote:
> >
> > Set two rank timing and exit self-refresh timing seems not done
> > properly. We know use the same write that we are using
> > on H5 silicon. Tested was
> On 14.02.2019, at 16:58, Michael Trimarchi
> wrote:
>
> Set two rank timing and exit self-refresh timing seems not done
> properly. We know use the same write that we are using
> on H5 silicon. Tested was done in A33 allwinner cpu, dual rank
> connection connected with two
On Thu, 2019-02-14 at 15:15 +, Chee, Tien Fong wrote:
> On Thu, 2019-02-14 at 13:28 +0100, Marek Vasut wrote:
> > On 2/14/19 12:38 PM, Chee, Tien Fong wrote:
> > > On Thu, 2019-02-14 at 11:42 +0100, Marek Vasut wrote:
> > > > On 2/14/19 7:50 AM, Chee, Tien Fong wrote:
> > > > >
> > > > > On
Hi Igor,
On Thu, 14 Feb 2019 at 17:19, Igor Opaniuk wrote:
>
> Hi Simon,
>
> I've fixed failing test on sandbox_flattree by keeping all defined
> global variables in a driver-private data struct(as you suggested),
> which
> permits to probe multiple tee sandbox devices (sent v5, kept you R-b
>
HI Igor,
On Wed, 13 Feb 2019 at 16:39, Igor Opaniuk wrote:
>
> Hi Simon,
>
> Seems that there is an issue in dm test framework (if understood
> everything correctly),
>
> I've noticed that dm_root is updated when dm tests are being invoked,
> and that's why the new tee udevice is allocated,
Hi Simon,
I've fixed failing test on sandbox_flattree by keeping all defined
global variables in a driver-private data struct(as you suggested),
which
permits to probe multiple tee sandbox devices (sent v5, kept you R-b
tag, please let me know if there are any objections from your side).
But the
On 01/02/2019 16:23, Tom Rini wrote:
On Fri, Feb 01, 2019 at 03:33:34PM +0100, Jean-Jacques Hiblot wrote:
u-boot does not supports updating the metadata chacksums
Signed-off-by: Jean-Jacques Hiblot
---
Changes in v2:
- Prevent write access if metadata checksum is enabled
Set two rank timing and exit self-refresh timing seems not done
properly. We know use the same write that we are using
on H5 silicon. Tested was done in A33 allwinner cpu, dual rank
connection connected with two MT41K512M16HA-125:A memory model.
Memory is configure as DDR3 1.5V
Signed-off-by:
Change the size create a glitch in the clken signal on second
bank. According to the ddr manual the clken need to be sent
accros the reset signal coming the cpu. The rank is calculated
just before this function is called and the mctl_set_cr should
not change this value anymore
Signed-off-by:
Signed-off-by: Michael Trimarchi
---
V1->V2: none
---
arch/arm/mach-sunxi/dram_sun8i_a33.c | 8 ++--
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/arch/arm/mach-sunxi/dram_sun8i_a33.c
b/arch/arm/mach-sunxi/dram_sun8i_a33.c
index 1da2727f98..83212aaddf 100644
---
On Thu, 2019-02-14 at 16:13 +0100, Marek Vasut wrote:
> On 2/14/19 4:11 PM, Chee, Tien Fong wrote:
> >
> > On Thu, 2019-02-14 at 13:24 +0100, Marek Vasut wrote:
> > >
> > > On 2/14/19 12:23 PM, Chee, Tien Fong wrote:
> > > >
> > > >
> > > > On Thu, 2019-02-14 at 11:35 +0100, Marek Vasut wrote:
On Thu, Feb 14, 2019 at 4:37 PM Dinh Nguyen wrote:
>
> Hi Marek,
>
> On 2/9/19 4:01 AM, Marek Vasut wrote:
> > On 2/7/19 10:23 PM, Simon Goldschmidt wrote:
> >> To clean up reset handling for socfpga gen5, let's move the code snippet
> >> taking the DDR controller out of reset from SPL to the DDR
Hi Joris,
On Thu, Feb 14, 2019 at 11:43 AM Joris Offouga wrote:
> Hi Fabio
>
> Fix typo warp7_config into warp7_defconig
make warp7_config
make
Also works fine.
I agree with you that "make warp_defconfig" is preferable and I will
make such change after this one gets applied.
Thanks for
Hi Marek,
On 2/9/19 4:01 AM, Marek Vasut wrote:
> On 2/7/19 10:23 PM, Simon Goldschmidt wrote:
>> To clean up reset handling for socfpga gen5, let's move the code snippet
>> taking the DDR controller out of reset from SPL to the DDR driver.
>>
>> While at it, port the ddr driver to UCLASS_RAM and
On Thu, 2019-02-14 at 16:21 +0100, Marek Vasut wrote:
> On 2/14/19 4:15 PM, Chee, Tien Fong wrote:
> >
> > On Thu, 2019-02-14 at 13:28 +0100, Marek Vasut wrote:
> > >
> > > On 2/14/19 12:38 PM, Chee, Tien Fong wrote:
> > > >
> > > >
> > > > On Thu, 2019-02-14 at 11:42 +0100, Marek Vasut wrote:
On 2/14/19 4:23 PM, Chee, Tien Fong wrote:
> On Thu, 2019-02-14 at 16:15 +0100, Marek Vasut wrote:
>> On 2/14/19 4:14 PM, Chee, Tien Fong wrote:
>>>
>>> On Thu, 2019-02-14 at 13:29 +0100, Marek Vasut wrote:
On 2/14/19 1:14 PM, Chee, Tien Fong wrote:
>
>
> On Thu, 2019-02-14
On Thu, 2019-02-14 at 16:15 +0100, Marek Vasut wrote:
> On 2/14/19 4:14 PM, Chee, Tien Fong wrote:
> >
> > On Thu, 2019-02-14 at 13:29 +0100, Marek Vasut wrote:
> > >
> > > On 2/14/19 1:14 PM, Chee, Tien Fong wrote:
> > > >
> > > >
> > > > On Thu, 2019-02-14 at 11:41 +0100, Marek Vasut wrote:
On 2/14/19 4:15 PM, Chee, Tien Fong wrote:
> On Thu, 2019-02-14 at 13:28 +0100, Marek Vasut wrote:
>> On 2/14/19 12:38 PM, Chee, Tien Fong wrote:
>>>
>>> On Thu, 2019-02-14 at 11:42 +0100, Marek Vasut wrote:
On 2/14/19 7:50 AM, Chee, Tien Fong wrote:
>
>
> On Wed, 2019-02-13
On 2/14/19 4:11 PM, Chee, Tien Fong wrote:
> On Thu, 2019-02-14 at 13:24 +0100, Marek Vasut wrote:
>> On 2/14/19 12:23 PM, Chee, Tien Fong wrote:
>>>
>>> On Thu, 2019-02-14 at 11:35 +0100, Marek Vasut wrote:
On 2/14/19 7:04 AM, Chee, Tien Fong wrote:
>
>
> On Thu, 2019-02-14
On Thu, 2019-02-14 at 13:28 +0100, Marek Vasut wrote:
> On 2/14/19 12:38 PM, Chee, Tien Fong wrote:
> >
> > On Thu, 2019-02-14 at 11:42 +0100, Marek Vasut wrote:
> > >
> > > On 2/14/19 7:50 AM, Chee, Tien Fong wrote:
> > > >
> > > >
> > > > On Wed, 2019-02-13 at 17:25 +0100, Marek Vasut wrote:
On 2/14/19 4:14 PM, Chee, Tien Fong wrote:
> On Thu, 2019-02-14 at 13:29 +0100, Marek Vasut wrote:
>> On 2/14/19 1:14 PM, Chee, Tien Fong wrote:
>>>
>>> On Thu, 2019-02-14 at 11:41 +0100, Marek Vasut wrote:
On 2/14/19 7:44 AM, Chee, Tien Fong wrote:
>
>
> On Wed, 2019-02-13
On Thu, 2019-02-14 at 13:29 +0100, Marek Vasut wrote:
> On 2/14/19 1:14 PM, Chee, Tien Fong wrote:
> >
> > On Thu, 2019-02-14 at 11:41 +0100, Marek Vasut wrote:
> > >
> > > On 2/14/19 7:44 AM, Chee, Tien Fong wrote:
> > > >
> > > >
> > > > On Wed, 2019-02-13 at 17:20 +0100, Marek Vasut wrote:
On Thu, 2019-02-14 at 13:28 +0100, Marek Vasut wrote:
> On 2/14/19 12:51 PM, Chee, Tien Fong wrote:
> >
> > On Wed, 2019-02-13 at 17:11 +0100, Marek Vasut wrote:
> > >
> > > On 2/13/19 3:18 PM, tien.fong.c...@intel.com wrote:
> > > >
> > > >
> > > > From: Tien Fong Chee
> > > >
> > > >
On Thu, 2019-02-14 at 13:24 +0100, Marek Vasut wrote:
> On 2/14/19 12:23 PM, Chee, Tien Fong wrote:
> >
> > On Thu, 2019-02-14 at 11:35 +0100, Marek Vasut wrote:
> > >
> > > On 2/14/19 7:04 AM, Chee, Tien Fong wrote:
> > > >
> > > >
> > > > On Thu, 2019-02-14 at 00:04 +0100, Marek Vasut wrote:
On 2/14/19 1:14 PM, Chee, Tien Fong wrote:
> On Thu, 2019-02-14 at 11:41 +0100, Marek Vasut wrote:
>> On 2/14/19 7:44 AM, Chee, Tien Fong wrote:
>>>
>>> On Wed, 2019-02-13 at 17:20 +0100, Marek Vasut wrote:
On 2/13/19 3:18 PM, tien.fong.c...@intel.com wrote:
>
>
> From: Tien
On 2/14/19 12:38 PM, Chee, Tien Fong wrote:
> On Thu, 2019-02-14 at 11:42 +0100, Marek Vasut wrote:
>> On 2/14/19 7:50 AM, Chee, Tien Fong wrote:
>>>
>>> On Wed, 2019-02-13 at 17:25 +0100, Marek Vasut wrote:
On 2/13/19 3:18 PM, tien.fong.c...@intel.com wrote:
>
>
> From: Tien
On 2/14/19 12:23 PM, Chee, Tien Fong wrote:
> On Thu, 2019-02-14 at 11:35 +0100, Marek Vasut wrote:
>> On 2/14/19 7:04 AM, Chee, Tien Fong wrote:
>>>
>>> On Thu, 2019-02-14 at 00:04 +0100, Marek Vasut wrote:
On 2/13/19 11:45 PM, Dalon L Westergreen wrote:
>
>
> On Wed,
On 2/14/19 12:51 PM, Chee, Tien Fong wrote:
> On Wed, 2019-02-13 at 17:11 +0100, Marek Vasut wrote:
>> On 2/13/19 3:18 PM, tien.fong.c...@intel.com wrote:
>>>
>>> From: Tien Fong Chee
>>>
>>> Adding some function declarations to the header file, so these
>>> functions can be referred by other C
Le 09/02/2019 à 15:01, Fabio Estevam a écrit :
After the conversion to DM the U-Boot binary is called u-boot-dtb.imx,
so fix the README file accordingly.
Signed-off-by: Fabio Estevam
---
Changes since v1:
- Fix all occurrances
board/warp7/README | 12 ++--
1 file changed, 6
On 30.01.19 23:24, Jonathan Gray wrote:
> Add Raspberry Pi Compute Module 3+ to list of models, the revision code
> is 0x10 according to the list on raspberrypi.org.
>
> v2: Use the same dtb name as CM3 as CM3+ is a drop in replacement
> for CM3.
>
> Signed-off-by: Jonathan Gray
The third parameter of the pmic_clrsetbits() function is the mask
to the register and the correct mask is 1 not 0.
Since the LDOGCTL only contains a single valid bit (bit 0),
we can use pmic_reg_write() and write 1 directly, which fixes
the problem in a simpler way and use the original pmic
Matthias Brugger agreed to take over maintainership from me for the
Raspberry Pi tree. Add him to the MAINTAINERS file instead.
Signed-off-by: Alexander Graf
---
MAINTAINERS | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index
There is no need to store the values written to the PMIC inside the
'reg' variable. Make it simpler by writing the values directly.
Signed-off-by: Fabio Estevam
---
Changes since v1:
- Remove 1/2 notation, since this is a standalome patch
- Add Peng Fan on Cc
Heinrich is going to take over maintainership of the efi_loader tree
going forward.
To ensure that I will still receive review mails at least, add me as
reviewer with a stable email address.
Signed-off-by: Alexander Graf
---
MAINTAINERS | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
There is no need to store the values written to the PMIC inside the
'reg' variable. Make it simpler by writing the values directly.
Signed-off-by: Fabio Estevam
---
board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c | 9 +++--
1 file changed, 3 insertions(+), 6 deletions(-)
diff --git
The third parameter of the pmic_clrsetbits() function is the mask
to the register and the correct mask is 1 not 0.
Since the LDOGCTL only contains a single valid register (bit 0),
we can use pmic_reg_write() and write 1 directly, which fixes
the problem in a simpler way and use the original pmic
On 12.02.19 22:01, Heinrich Schuchardt wrote:
> In efi_selftest we are in EFI land. We cannot call U-Boot library
> functions malloc() and free() but should use the boot time services
> instead.
>
> Signed-off-by: Heinrich Schuchardt
Reviewed-by: Alexander Graf
Alex
On 12.02.19 22:02, Heinrich Schuchardt wrote:
> In efi_selftest we are in EFI land. We should not use U-Boot library
> functions but boot time services for memory management.
>
> Signed-off-by: Heinrich Schuchardt
Reviewed-by: Alexander Graf
Alex
Older kernel versions or systems which do not connect eMMC reset line
properly may not be able to handle situations where either the eMMC
is left in HS200/HS400 mode or SD card in UHS modes by the bootloader
and may misbehave. Downgrade the eMMC to HS/HS52 mode and/or SD card
to non-UHS mode
On 2/14/19 1:26 PM, Michal Simek wrote:
On 14. 02. 19 8:52, Hannes Schmelzer wrote:
Hi,
Hi Michal,
first of all I would rephrase subject a little bit.
Something like:
"ARM: zynq: Add missing i2c get_rate for fixing i2c SPL"
OK.
On 14. 02. 19 6:50, Hannes Schmelzer wrote:
The commit
1 - 100 of 165 matches
Mail list logo
