[U-Boot] [PATCH] sunxi: set PIO voltage to hardware-detected value on startup on H6

2019-04-23 Thread Icenowy Zheng
The Allwinner H6 SoC has a register to set the PIO banks' voltage. When
it mismatches the real voltage supplied to the VCC to the PIO supply,
the PIO will work improperly.

The PIO controller also has a register that contains the status of each
VCC rail of the PIO supplies, and it has the same definition with the
configuration register. so we can just copy the content of this register
to the configuration register at startup, to ensure the configuration is
correct at startup stage.

Signed-off-by: Icenowy Zheng 
---
 arch/arm/include/asm/arch-sunxi/gpio.h | 3 +++
 arch/arm/mach-sunxi/board.c| 9 +
 2 files changed, 12 insertions(+)

diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h 
b/arch/arm/include/asm/arch-sunxi/gpio.h
index 40a3f845d0..a646ea6a3c 100644
--- a/arch/arm/include/asm/arch-sunxi/gpio.h
+++ b/arch/arm/include/asm/arch-sunxi/gpio.h
@@ -73,6 +73,9 @@ struct sunxi_gpio_reg {
struct sunxi_gpio_int gpio_int;
 };
 
+#define SUN50I_H6_GPIO_POW_MOD_SEL 0x340
+#define SUN50I_H6_GPIO_POW_MOD_VAL 0x348
+
 #define BANK_TO_GPIO(bank) (((bank) < SUNXI_GPIO_L) ? \
&((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[bank] : \
&((struct sunxi_gpio_reg *)SUNXI_R_PIO_BASE)->gpio_bank[(bank) - 
SUNXI_GPIO_L])
diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c
index c6dd7b8e54..bd3b5d8303 100644
--- a/arch/arm/mach-sunxi/board.c
+++ b/arch/arm/mach-sunxi/board.c
@@ -65,6 +65,7 @@ struct mm_region *mem_map = sunxi_mem_map;
 
 static int gpio_init(void)
 {
+   __maybe__unused uint val;
 #if CONFIG_CONS_INDEX == 1 && defined(CONFIG_UART0_PORT_F)
 #if defined(CONFIG_MACH_SUN4I) || \
 defined(CONFIG_MACH_SUN7I) || \
@@ -139,6 +140,14 @@ static int gpio_init(void)
 #error Unsupported console port number. Please fix pin mux settings in board.c
 #endif
 
+#ifdef CONFIG_MACH_SUN50I_H6
+   /* Update PIO power bias configuration by copy hardware detected value 
*/
+   val = readl(SUNXI_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_VAL);
+   writel(val, SUNXI_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_SEL);
+   val = readl(SUNXI_R_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_VAL);
+   writel(val, SUNXI_R_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_SEL);
+#endif
+
return 0;
 }
 
-- 
2.18.1

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[U-Boot] [PATCH v2 1/1] common: fdt_support: Check mtdparts cell size

2019-04-23 Thread Stefan Mavrodiev
When using fdt_fixup_mtdparts() offset and length cell sizes
are limited to 4 bytes (1 cell). However if the mtd device is
bigger then 4GiB, then #address-cells and #size-cells are
8 bytes (2 cells) [1].

This patch read #size-cells and uses either fdt32_t or
fdt64_t cell size. The default is fdt32_t.

[1] Documentation/devicetree/bindings/mtd/partition.txt

Signed-off-by: Stefan Mavrodiev 
---
Changes for v2:
- Use fdt_setprop_u64() and ..._u32() instead of fdt_setprop()
- Add size value using fdt_appendprop_u64() and ..._u32()

 common/fdt_support.c | 31 ++-
 1 file changed, 22 insertions(+), 9 deletions(-)

diff --git a/common/fdt_support.c b/common/fdt_support.c
index 42583e3ed8..1c1a954829 100644
--- a/common/fdt_support.c
+++ b/common/fdt_support.c
@@ -724,11 +724,6 @@ int fdt_increase_size(void *fdt, int add_len)
 #include 
 #include 
 
-struct reg_cell {
-   unsigned int r0;
-   unsigned int r1;
-};
-
 static int fdt_del_subnodes(const void *blob, int parent_offset)
 {
int off, ndepth;
@@ -787,15 +782,22 @@ int fdt_node_set_part_info(void *blob, int parent_offset,
 {
struct list_head *pentry;
struct part_info *part;
-   struct reg_cell cell;
int off, ndepth = 0;
int part_num, ret;
+   int sizecell;
char buf[64];
 
ret = fdt_del_partitions(blob, parent_offset);
if (ret < 0)
return ret;
 
+   /*
+* Check if size/address is 1 or 2 cells.
+* We assume #address-cells and #size-cells have same value.
+*/
+   sizecell = fdt_getprop_u32_default_node(blob, parent_offset,
+   0, "#size-cells", 1);
+
/*
 * Check if it is nand {}; subnode, adjust
 * the offset in this case
@@ -844,10 +846,21 @@ add_ro:
goto err_prop;
}
 
-   cell.r0 = cpu_to_fdt32(part->offset);
-   cell.r1 = cpu_to_fdt32(part->size);
 add_reg:
-   ret = fdt_setprop(blob, newoff, "reg", , sizeof(cell));
+   if (sizecell == 2) {
+   ret = fdt_setprop_u64(blob, newoff,
+ "reg", part->offset);
+   if (!ret)
+   ret = fdt_appendprop_u64(blob, newoff,
+"reg", part->size);
+   } else {
+   ret = fdt_setprop_u32(blob, newoff,
+ "reg", part->offset);
+   if (!ret)
+   ret = fdt_appendprop_u32(blob, newoff,
+"reg", part->size);
+   }
+
if (ret == -FDT_ERR_NOSPACE) {
ret = fdt_increase_size(blob, 512);
if (!ret)
-- 
2.17.1

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Re: [U-Boot] [PATCH v4] arm: socfpga: mailbox: Fix off-by-one error on command length checking

2019-04-23 Thread Simon Goldschmidt
Ley Foon Tan  schrieb am Mi., 24. Apr. 2019, 07:21:

> A mailbox command contains 1-u32 header + arguments. The "len" variable
> only contains the length of the arguments, but not the 1-u32 header.
> Include the length of header when checking the ring buffer space to
> prevent off-by-one error.
>
> Signed-off-by: Ley Foon Tan 
> Signed-off-by: Chee Hong Ang 
>

Reviewed-by: Simon Goldschmidt 

---
> v3->v4:
> - Change DWORD to u32 in commit message
> - Add note len is in u32 unit in code
>
> v2->v3:
> - Update commit description.
> ---
>  arch/arm/mach-socfpga/mailbox_s10.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/mach-socfpga/mailbox_s10.c
> b/arch/arm/mach-socfpga/mailbox_s10.c
> index 3c33223936..4498ab55df 100644
> --- a/arch/arm/mach-socfpga/mailbox_s10.c
> +++ b/arch/arm/mach-socfpga/mailbox_s10.c
> @@ -55,11 +55,11 @@ static __always_inline int
> mbox_fill_cmd_circular_buff(u32 header, u32 len,
> cout = MBOX_READL(MBOX_COUT) % MBOX_CMD_BUFFER_SIZE;
>
> /* if command buffer is full or not enough free space
> -* to fit the data
> +* to fit the data. Note, len is in u32 unit.
>  */
> if (((cin + 1) % MBOX_CMD_BUFFER_SIZE) == cout ||
> ((MBOX_CMD_BUFFER_SIZE - cin + cout - 1) %
> -MBOX_CMD_BUFFER_SIZE) < len)
> +MBOX_CMD_BUFFER_SIZE) < (len + 1))
> return -ENOMEM;
>
> /* write header to circular buffer */
> --
> 2.19.0
>
>
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[U-Boot] [PATCH v4] arm: socfpga: mailbox: Fix off-by-one error on command length checking

2019-04-23 Thread Ley Foon Tan
A mailbox command contains 1-u32 header + arguments. The "len" variable
only contains the length of the arguments, but not the 1-u32 header.
Include the length of header when checking the ring buffer space to
prevent off-by-one error.

Signed-off-by: Ley Foon Tan 
Signed-off-by: Chee Hong Ang 
---
v3->v4:
- Change DWORD to u32 in commit message
- Add note len is in u32 unit in code

v2->v3:
- Update commit description.
---
 arch/arm/mach-socfpga/mailbox_s10.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-socfpga/mailbox_s10.c 
b/arch/arm/mach-socfpga/mailbox_s10.c
index 3c33223936..4498ab55df 100644
--- a/arch/arm/mach-socfpga/mailbox_s10.c
+++ b/arch/arm/mach-socfpga/mailbox_s10.c
@@ -55,11 +55,11 @@ static __always_inline int mbox_fill_cmd_circular_buff(u32 
header, u32 len,
cout = MBOX_READL(MBOX_COUT) % MBOX_CMD_BUFFER_SIZE;
 
/* if command buffer is full or not enough free space
-* to fit the data
+* to fit the data. Note, len is in u32 unit.
 */
if (((cin + 1) % MBOX_CMD_BUFFER_SIZE) == cout ||
((MBOX_CMD_BUFFER_SIZE - cin + cout - 1) %
-MBOX_CMD_BUFFER_SIZE) < len)
+MBOX_CMD_BUFFER_SIZE) < (len + 1))
return -ENOMEM;
 
/* write header to circular buffer */
-- 
2.19.0

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Re: [U-Boot] [PATCH v3 7/9] pico-imx7d: Add device tree for pico-imx7d

2019-04-23 Thread Peng Fan

> Subject: [PATCH v3 7/9] pico-imx7d: Add device tree for pico-imx7d
> 
> Copy device tree files from Linux directly.

Please describe which specific commit from Linux kernel upstream

Regards,
Peng.

> 
> Signed-off-by: Jun Nie 
> ---
>  arch/arm/dts/Makefile  |   1 +
>  arch/arm/dts/imx7d-pico-pi.dts |  93 +++
>  arch/arm/dts/imx7d-pico.dtsi   | 585
> +
>  3 files changed, 679 insertions(+)
>  create mode 100644 arch/arm/dts/imx7d-pico-pi.dts  create mode 100644
> arch/arm/dts/imx7d-pico.dtsi
> 
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index
> 0aee8df..e6cb1d3 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -555,6 +555,7 @@ dtb-$(CONFIG_ARCH_MX6) += \
> 
>  dtb-$(CONFIG_MX7) += imx7d-sdb.dtb \
>   imx7d-sdb-qspi.dtb \
> + imx7d-pico-pi.dtb \
>   imx7-colibri-emmc.dtb \
>   imx7-colibri-rawnand.dtb \
>   imx7s-warp.dtb
> diff --git a/arch/arm/dts/imx7d-pico-pi.dts b/arch/arm/dts/imx7d-pico-pi.dts
> new file mode 100644 index 000..70bea95
> --- /dev/null
> +++ b/arch/arm/dts/imx7d-pico-pi.dts
> @@ -0,0 +1,93 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) // // Copyright 2017 NXP
> +
> +#include "imx7d-pico.dtsi"
> +
> +/ {
> + model = "TechNexion PICO-IMX7D Board and PI baseboard";
> + compatible = "technexion,imx7d-pico-pi", "fsl,imx7d";
> +
> + leds {
> + compatible = "gpio-leds";
> + pinctrl-names = "default";
> + pinctrl-0 = <_gpio_leds>;
> +
> + led {
> + label = "gpio-led";
> + gpios = < 6 GPIO_ACTIVE_HIGH>;
> + };
> + };
> +
> + sound {
> + compatible = "simple-audio-card";
> + simple-audio-card,name = "imx7-sgtl5000";
> + simple-audio-card,format = "i2s";
> + simple-audio-card,bitclock-master = <_master>;
> + simple-audio-card,frame-master = <_master>;
> + simple-audio-card,cpu {
> + sound-dai = <>;
> + };
> +
> + dailink_master: simple-audio-card,codec {
> + sound-dai = <>;
> + clocks = < IMX7D_AUDIO_MCLK_ROOT_CLK>;
> + };
> + };
> +};
> +
> + {
> + sgtl5000: codec@a {
> + #sound-dai-cells = <0>;
> + reg = <0x0a>;
> + compatible = "fsl,sgtl5000";
> + clocks = < IMX7D_AUDIO_MCLK_ROOT_CLK>;
> + VDDA-supply = <_2p5v>;
> + VDDIO-supply = <_vref_1v8>;
> + };
> +};
> +
> + {
> + polytouch: touchscreen@38 {
> + compatible = "edt,edt-ft5x06";
> + reg = <0x38>;
> + pinctrl-names = "default";
> + pinctrl-0 = <_touchscreen>;
> + interrupt-parent = <>;
> + interrupts = <13 IRQ_TYPE_EDGE_FALLING>;
> + reset-gpios = < 4 GPIO_ACTIVE_LOW>;
> + touchscreen-size-x = <800>;
> + touchscreen-size-y = <480>;
> + };
> +};
> +
> + {
> + pinctrl-names = "default";
> + pinctrl-0 = <_hog>;
> +
> + pinctrl_hog: hoggrp {
> + fsl,pins = <
> + MX7D_PAD_EPDC_DATA00__GPIO2_IO0 0x14
> + MX7D_PAD_EPDC_DATA01__GPIO2_IO1 0x14
> + MX7D_PAD_EPDC_DATA02__GPIO2_IO2 0x14
> + MX7D_PAD_EPDC_DATA03__GPIO2_IO3 0x14
> + MX7D_PAD_EPDC_DATA05__GPIO2_IO5 0x14
> + MX7D_PAD_EPDC_DATA12__GPIO2_IO120x14
> + MX7D_PAD_EPDC_DATA07__GPIO2_IO7 0x14
> + >;
> + };
> +
> + pinctrl_gpio_leds: gpioledsgrp {
> + fsl,pins = <
> + MX7D_PAD_EPDC_DATA06__GPIO2_IO6 0x14
> + >;
> + };
> +
> + pinctrl_touchscreen: touchscreengrp {
> + fsl,pins = <
> + MX7D_PAD_EPDC_DATA04__GPIO2_IO4 0x14
> + MX7D_PAD_EPDC_DATA13__GPIO2_IO130x14
> + >;
> + };
> +
> +};
> diff --git a/arch/arm/dts/imx7d-pico.dtsi b/arch/arm/dts/imx7d-pico.dtsi new
> file mode 100644 index 000..3fd595a
> --- /dev/null
> +++ b/arch/arm/dts/imx7d-pico.dtsi
> @@ -0,0 +1,585 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) // // Copyright 2017 NXP
> +
> +/dts-v1/;
> +
> +#include "imx7d.dtsi"
> +
> +/ {
> + /* Will be filled by the bootloader */
> + memory@8000 {
> + device_type = "memory";
> + reg = <0x8000 0>;
> + };
> +
> + reg_wlreg_on: regulator-wlreg_on {
> + compatible = "regulator-fixed";
> + pinctrl-names = "default";
> + pinctrl-0 = <_reg_wlreg_on>;
> + regulator-name = "wlreg_on";
> + regulator-min-microvolt = <330>;
> + regulator-max-microvolt = <330>;
> + gpio = < 16 

Re: [U-Boot] [PATCH v3 5/9] pico-imx7d: Reserve region of memory to OPTEE

2019-04-23 Thread Peng Fan

> Subject: [PATCH v3 5/9] pico-imx7d: Reserve region of memory to OPTEE
> 
> Subtracts CONFIG_OPTEE_TZDRAM_SIZE from the available DRAM size so
> that the OPTEE memory is not override during u-boot relocation.
> 
> Note the OPTEE boot process will itself subtract the DRAM region it lives in
> from the memory map passed to Linux.
> 
> Signed-off-by: Jun Nie 
> ---
>  board/technexion/pico-imx7d/pico-imx7d.c | 5 +
>  1 file changed, 5 insertions(+)
> 
> diff --git a/board/technexion/pico-imx7d/pico-imx7d.c
> b/board/technexion/pico-imx7d/pico-imx7d.c
> index 53e1469..7c9e145 100644
> --- a/board/technexion/pico-imx7d/pico-imx7d.c
> +++ b/board/technexion/pico-imx7d/pico-imx7d.c
> @@ -60,6 +60,11 @@ int dram_init(void)
>  {
>   gd->ram_size = imx_ddr_size();
> 
> + /* Subtract the defined OPTEE runtime firmware length */ #ifdef
> +CONFIG_OPTEE_TZDRAM_SIZE
> + gd->ram_size -= CONFIG_OPTEE_TZDRAM_SIZE; #endif
> +
Better describe that OP-TEE runs at the top of DRAM. Actually the best
method should be modify dram banks, because OP-TEE not always
runs at top DRAM. Since this is pico board specific, so

Reviewed-by: Peng Fan 

Regards,
Peng.

>   return 0;
>  }
> 
> --
> 2.7.4

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Re: [U-Boot] [PATCH v3 4/9] pico-imx7d: Correct uart clock root

2019-04-23 Thread Peng Fan

> Subject: [PATCH v3 4/9] pico-imx7d: Correct uart clock root
> 
> Correct uart clock root ID. Incorrect ID may result the clock is gated because
> rate value 0 is returned in
> imx_get_uartclk()

Yes. hardcoding to UART1_ROOT_CLK in imx_get_uartclk is not good.
But actually init_clk_uart configures all the uart with same root clk,
so it should work as expected.

Regards,
Peng.

> 
> Signed-off-by: Jun Nie 
> ---
>  arch/arm/include/asm/arch-mx7/clock.h | 18 ++
>  arch/arm/mach-imx/Kconfig |  7 +++
>  arch/arm/mach-imx/mx7/clock.c |  2 +-
>  3 files changed, 26 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm/include/asm/arch-mx7/clock.h
> b/arch/arm/include/asm/arch-mx7/clock.h
> index f56564e..dc9 100644
> --- a/arch/arm/include/asm/arch-mx7/clock.h
> +++ b/arch/arm/include/asm/arch-mx7/clock.h
> @@ -175,6 +175,24 @@ enum clk_root_index {
>   CLK_ROOT_MAX,
>  };
> 
> +#if (CONFIG_IMX_CONSOLE_UART_ID == 1)
> +#define UART_CLK_ROOT UART1_CLK_ROOT
> +#elif (CONFIG_IMX_CONSOLE_UART_ID == 2) #define UART_CLK_ROOT
> +UART2_CLK_ROOT #elif (CONFIG_IMX_CONSOLE_UART_ID == 3) #define
> +UART_CLK_ROOT UART3_CLK_ROOT #elif
> (CONFIG_IMX_CONSOLE_UART_ID == 4)
> +#define UART_CLK_ROOT UART4_CLK_ROOT #elif
> (CONFIG_IMX_CONSOLE_UART_ID
> +== 5) #define UART_CLK_ROOT UART5_CLK_ROOT #elif
> +(CONFIG_IMX_CONSOLE_UART_ID == 6) #define UART_CLK_ROOT
> UART6_CLK_ROOT
> +#elif (CONFIG_IMX_CONSOLE_UART_ID == 7) #define UART_CLK_ROOT
> +UART7_CLK_ROOT #else #error "Invalid IMX UART ID for serial console is
> +defined"
> +#endif
> +
>  struct clk_root_setting {
>   enum clk_root_index root;
>   u32 setting;
> diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index
> ec09ef2..7c5db30 100644
> --- a/arch/arm/mach-imx/Kconfig
> +++ b/arch/arm/mach-imx/Kconfig
> @@ -27,6 +27,13 @@ config IMX_BOOTAUX
>   help
> bootaux [addr] to boot auxiliary core.
> 
> +config IMX_CONSOLE_UART_ID
> + int "UART ID for console"
> + default 1
> + depends on ARCH_MX7
> + help
> +   Specify the UART ID that's for serial console.
> +
>  config USE_IMXIMG_PLUGIN
>   bool "Use imximage plugin code"
>   depends on ARCH_MX7 || ARCH_MX6
> diff --git a/arch/arm/mach-imx/mx7/clock.c
> b/arch/arm/mach-imx/mx7/clock.c index 8cda71c..e364b16 100644
> --- a/arch/arm/mach-imx/mx7/clock.c
> +++ b/arch/arm/mach-imx/mx7/clock.c
> @@ -53,7 +53,7 @@ static u32 get_ipg_clk(void)
> 
>  u32 imx_get_uartclk(void)
>  {
> - return get_root_clk(UART1_CLK_ROOT);
> + return get_root_clk(UART_CLK_ROOT);
>  }
> 
>  u32 imx_get_fecclk(void)
> --
> 2.7.4

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Re: [U-Boot] [PATCH v3 3/9] imx: mx7: Add empty arch_cpu_init if skipped

2019-04-23 Thread Peng Fan
Hi Jun

> Subject: [PATCH v3 3/9] imx: mx7: Add empty arch_cpu_init if skipped
> 
> Add empty arch_cpu_init if low level init is skipped. So that it does not 
> break
> spl compile though spl is not needed in the skipped case actually.
> 
> Signed-off-by: Jun Nie 
> ---
>  arch/arm/mach-imx/mx7/soc.c | 5 +
>  1 file changed, 5 insertions(+)
> 
> diff --git a/arch/arm/mach-imx/mx7/soc.c b/arch/arm/mach-imx/mx7/soc.c
> index 7cfdff0..9b04013 100644
> --- a/arch/arm/mach-imx/mx7/soc.c
> +++ b/arch/arm/mach-imx/mx7/soc.c
> @@ -286,6 +286,11 @@ int arch_cpu_init(void)
> 
>   return 0;
>  }
> +#else
> +int arch_cpu_init(void)
> +{
> + return 0;
> +}
>  #endif

Please describe what ATF/OP-TEE initialization has done
when booting into uboot.

I think SKIP_LOWLEVEL_INIT is mostly for lowlevel_init,
not arch_cpu_init.

init_aips/init_csu/isolate_resources/init_snvs might be
done in your ATF, I am not sure, but imx_enet_mdio_fixup,
mxs_dma_init, imx_gpcv2_init, are these also done in ATF?

Regards,
Peng.

> 
>  #ifdef CONFIG_ARCH_MISC_INIT
> --
> 2.7.4

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[U-Boot] [PATCH v3 9/9] pico-imx7d: README: Add BL33 usage case

2019-04-23 Thread Jun Nie
Add Documentation of BL33 usage case. U-boot is in
non-secure world in this case.

Signed-off-by: Jun Nie 
---
 board/technexion/pico-imx7d/README.pico-imx7d_BL33 | 44 ++
 1 file changed, 44 insertions(+)
 create mode 100644 board/technexion/pico-imx7d/README.pico-imx7d_BL33

diff --git a/board/technexion/pico-imx7d/README.pico-imx7d_BL33 
b/board/technexion/pico-imx7d/README.pico-imx7d_BL33
new file mode 100644
index 000..40324ff
--- /dev/null
+++ b/board/technexion/pico-imx7d/README.pico-imx7d_BL33
@@ -0,0 +1,44 @@
+This document describes the instruction to build and flash ATF/OPTEE/U-Boot on
+pico-imx7d board. U-Boot is loaded as part of FIP image by ATF in this setup.
+The boot sequence is ATF -> OPTEE -> U-Boot -> Linux. U-Boot is in non-secure
+world in this case.
+
+- Build u-boot
+Set environment variable of CROSS_COMPILE for your toolchain and ARCH=arm
+$ make pico-imx7d_bl33_defconfig
+$ make all
+
+- Download and build OPTEE
+$ git clone g...@github.com:OP-TEE/optee_os.git
+$ make PLATFORM=imx PLATFORM_FLAVOR=mx7dpico_mbl 
CFG_BOOT_SECONDARY_REQUEST=y ARCH=arm
+
+- Download and build ATF
+$ git clone 
https://git.linaro.org/landing-teams/working/mbl/arm-trusted-firmware.git -b 
linaro-imx7
+$ make DEBUG=1 PLAT=picopi ARCH=aarch32 ARM_ARCH_MAJOR=7 \
+CROSS_COMPILE=arm-linux-gnueabihf- LOG_LEVEL=50 V=1 \
+CRASH_REPORTING=1 AARCH32_SP=optee all
+Save file content in this link to file pico-imx7d.cfg:
+  
http://git.linaro.org/landing-teams/working/mbl/u-boot.git/tree/board/technexion/pico-imx7d/pico-imx7d.cfg?h=linaro-imx
+$ u-boot/tools/mkimage -n pico-imx7d.cfg -T imximage -e 0x9df0 -d \
+build/picopi/debug/bl2.bin bl2.imx
+
+- Create FIP image
+Create a  fiptool_images/ folder in ATF folder, copy u-boot.bin in u-boot
+folder and tee*.bin in optee out/arm-plat-imx/core/tee/ folder to
+fiptool_images. Run below command in ATF folder to generate FIP image.
+$ make -C tools/fiptool/
+$ tools/fiptool/fiptool create --tos-fw fiptool_images/tee-header_v2.bin \
+  --tos-fw-extra1 fiptool_images/tee-pager_v2.bin \
+  --tos-fw-extra2 fiptool_images/tee-pageable_v2.bin \
+  --nt-fw fiptool_images/u-boot.bin \
+  fip.bin
+
+- Burn the images to eMMC for test.
+Run below command in atf folder:
+$ dd if=build/picopi/debug/bl2.bin.imx of=/dev/disk/by-id/usb-  bs=1024 seek=1;sync
+$ dd if=fip.bin of=/dev/disk/by-id/usb-  bs=1024 seek=1;sync
+
+- Test
+Just boot up your board and wait for u-boot start up after ATF's log.
+For booting Linux in FIT image, please reference the FIT files in
+u-boot doc/uImage.FIT/ folder.
-- 
2.7.4

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[U-Boot] [PATCH v3 8/9] pico-imx7d: Add bl33 config

2019-04-23 Thread Jun Nie
Add default configuration to run u-boot as BL33 in the boot flow case
of ATF(ARM Trusted Firmware) -> OPTEE -> U-boot.

Signed-off-by: Jun Nie 
---
 configs/pico-imx7d_bl33_defconfig | 63 +++
 1 file changed, 63 insertions(+)
 create mode 100644 configs/pico-imx7d_bl33_defconfig

diff --git a/configs/pico-imx7d_bl33_defconfig 
b/configs/pico-imx7d_bl33_defconfig
new file mode 100644
index 000..a896cb3
--- /dev/null
+++ b/configs/pico-imx7d_bl33_defconfig
@@ -0,0 +1,63 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX7=y
+CONFIG_SYS_TEXT_BASE=0x8780
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SECURE_BOOT=y
+CONFIG_TARGET_PICO_IMX7D=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL=y
+CONFIG_ARMV7_BOOT_SEC_DEFAULT=y
+CONFIG_IMX_CONSOLE_UART_ID=5
+CONFIG_FIT=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
+CONFIG_DEFAULT_FDT_FILE="imx7d-pico-pi.dtb"
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_USB_HOST_SUPPORT=y
+CONFIG_SPL_USB_GADGET=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
+CONFIG_HUSH_PARSER=y
+# CONFIG_CMD_BOOTD is not set
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_SPL=y
+CONFIG_CMD_SPL_WRITE_SIZE=0x2
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_SDP=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PXE=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="imx7d-pico-pi"
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DFU_MMC=y
+CONFIG_FSL_ESDHC=y
+CONFIG_PHYLIB=y
+CONFIG_MII=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_MXC_USB_OTG_HACTIVE=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x0525
+CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_ETHER=y
+CONFIG_USB_ETH_CDC=y
+CONFIG_USBNET_HOST_ADDR="de:ad:be:af:00:00"
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_OPTEE_TZDRAM_SIZE=0x200
-- 
2.7.4

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[U-Boot] [PATCH v3 4/9] pico-imx7d: Correct uart clock root

2019-04-23 Thread Jun Nie
Correct uart clock root ID. Incorrect ID may result the
clock is gated because rate value 0 is returned in
imx_get_uartclk()

Signed-off-by: Jun Nie 
---
 arch/arm/include/asm/arch-mx7/clock.h | 18 ++
 arch/arm/mach-imx/Kconfig |  7 +++
 arch/arm/mach-imx/mx7/clock.c |  2 +-
 3 files changed, 26 insertions(+), 1 deletion(-)

diff --git a/arch/arm/include/asm/arch-mx7/clock.h 
b/arch/arm/include/asm/arch-mx7/clock.h
index f56564e..dc9 100644
--- a/arch/arm/include/asm/arch-mx7/clock.h
+++ b/arch/arm/include/asm/arch-mx7/clock.h
@@ -175,6 +175,24 @@ enum clk_root_index {
CLK_ROOT_MAX,
 };
 
+#if (CONFIG_IMX_CONSOLE_UART_ID == 1)
+#define UART_CLK_ROOT UART1_CLK_ROOT
+#elif (CONFIG_IMX_CONSOLE_UART_ID == 2)
+#define UART_CLK_ROOT UART2_CLK_ROOT
+#elif (CONFIG_IMX_CONSOLE_UART_ID == 3)
+#define UART_CLK_ROOT UART3_CLK_ROOT
+#elif (CONFIG_IMX_CONSOLE_UART_ID == 4)
+#define UART_CLK_ROOT UART4_CLK_ROOT
+#elif (CONFIG_IMX_CONSOLE_UART_ID == 5)
+#define UART_CLK_ROOT UART5_CLK_ROOT
+#elif (CONFIG_IMX_CONSOLE_UART_ID == 6)
+#define UART_CLK_ROOT UART6_CLK_ROOT
+#elif (CONFIG_IMX_CONSOLE_UART_ID == 7)
+#define UART_CLK_ROOT UART7_CLK_ROOT
+#else
+#error "Invalid IMX UART ID for serial console is defined"
+#endif
+
 struct clk_root_setting {
enum clk_root_index root;
u32 setting;
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index ec09ef2..7c5db30 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -27,6 +27,13 @@ config IMX_BOOTAUX
help
  bootaux [addr] to boot auxiliary core.
 
+config IMX_CONSOLE_UART_ID
+   int "UART ID for console"
+   default 1
+   depends on ARCH_MX7
+   help
+ Specify the UART ID that's for serial console.
+
 config USE_IMXIMG_PLUGIN
bool "Use imximage plugin code"
depends on ARCH_MX7 || ARCH_MX6
diff --git a/arch/arm/mach-imx/mx7/clock.c b/arch/arm/mach-imx/mx7/clock.c
index 8cda71c..e364b16 100644
--- a/arch/arm/mach-imx/mx7/clock.c
+++ b/arch/arm/mach-imx/mx7/clock.c
@@ -53,7 +53,7 @@ static u32 get_ipg_clk(void)
 
 u32 imx_get_uartclk(void)
 {
-   return get_root_clk(UART1_CLK_ROOT);
+   return get_root_clk(UART_CLK_ROOT);
 }
 
 u32 imx_get_fecclk(void)
-- 
2.7.4

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[U-Boot] [PATCH v3 6/9] pico-imx7d: Add boot option for verified boot

2019-04-23 Thread Jun Nie
Add boot option to boot from fitimage to support verified boot.
The boot script plain text file should be packed into fit blob as
image with name of bootscr.

Signed-off-by: Jun Nie 
---
 include/configs/pico-imx7d.h | 38 +++---
 1 file changed, 35 insertions(+), 3 deletions(-)

diff --git a/include/configs/pico-imx7d.h b/include/configs/pico-imx7d.h
index 1884c58..8eb9064 100644
--- a/include/configs/pico-imx7d.h
+++ b/include/configs/pico-imx7d.h
@@ -52,11 +52,29 @@
"/boot/imx7d-pico-pi.dtb ext4 0 1;" \
"rootfs part 0 1\0" \
 
-#define BOOTMENU_ENV \
+/* When booting with FIT specify the node entry containing boot.scr */
+#if defined(CONFIG_FIT)
+#define PICO_BOOT_ENV \
+   "bootscr_fitimage_name=bootscr\0" \
+   "bootscriptaddr=0x8320\0" \
+   "fdtovaddr=0x8310\0" \
+   "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
+   "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
+   "mmcargs=setenv bootargs console=${console},${baudrate} " \
+   "rootwait rw;\0" \
+   "loadbootscript=" \
+   "load mmc ${mmcdev}:${mmcpart} ${bootscriptaddr} ${script};\0" \
+   "bootscript=echo Running bootscript from mmc ...; " \
+   "source ${bootscriptaddr}:${bootscr_fitimage_name}\0"
+#else
+#define PICO_BOOT_ENV \
"bootmenu_0=Boot using PICO-Hobbit baseboard=" \
"setenv fdtfile imx7d-pico-hobbit.dtb\0" \
"bootmenu_1=Boot using PICO-Pi baseboard=" \
"setenv fdtfile imx7d-pico-pi.dtb\0" \
+   BOOTENV
+#endif
+
 
 #define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
 #define CONFIG_SYS_MMC_IMG_LOAD_PART   1
@@ -68,7 +86,6 @@
"fdt_high=0x\0" \
"initrd_high=0x\0" \
"fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
-   BOOTMENU_ENV \
"fdt_addr=0x8300\0" \
"fdt_addr_r=0x8300\0" \
"kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
@@ -88,7 +105,22 @@
"name=rootfs,size=0,uuid=${uuid_gpt_rootfs}\0" \
"fastboot_partition_alias_system=rootfs\0" \
"setup_emmc=mmc dev 0; gpt write mmc 0 $partitions; reset;\0" \
-   BOOTENV
+   PICO_BOOT_ENV
+
+#if defined(CONFIG_FIT)
+#define CONFIG_BOOTCOMMAND \
+   "mmc dev ${mmcdev};" \
+   "mmc dev ${mmcdev}; if mmc rescan; then " \
+   "if run loadbootscript; then " \
+   "iminfo ${bootscriptaddr};" \
+   "if test $? -eq 1; then hab_failsafe; fi;" \
+   "run bootscript; " \
+   "else " \
+   "echo Fail to load fitImage with boot script;" \
+   "hab_failsafe;" \
+   "fi; " \
+   "fi"
+#endif
 
 #define BOOT_TARGET_DEVICES(func) \
func(MMC, mmc, 0) \
-- 
2.7.4

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[U-Boot] [PATCH 3/3] sound: Add codec enable to the sound bindings

2019-04-23 Thread Simon Glass
For U-Boot we allow a GPIO to be specified to enable the codec. Add this
to the relevant binding files.

Signed-off-by: Simon Glass 
---

 doc/device-tree-bindings/sound/intel-hda.txt   | 1 +
 doc/device-tree-bindings/sound/nvidia,tegra-audio-max98090.txt | 1 +
 doc/device-tree-bindings/sound/snow.txt| 1 +
 3 files changed, 3 insertions(+)

diff --git a/doc/device-tree-bindings/sound/intel-hda.txt 
b/doc/device-tree-bindings/sound/intel-hda.txt
index fb2ce550063..aa96be06e9b 100644
--- a/doc/device-tree-bindings/sound/intel-hda.txt
+++ b/doc/device-tree-bindings/sound/intel-hda.txt
@@ -12,6 +12,7 @@ Required properties:
 
 Optional properties
 - intel,beep-nid: Node ID to use for beep (will be detected if not provided)
+- codec-enable-gpio : The GPIO used to enable the audio codec
 
 Required subnodes:
 - codecs: Contains a list of codec nodes
diff --git a/doc/device-tree-bindings/sound/nvidia,tegra-audio-max98090.txt 
b/doc/device-tree-bindings/sound/nvidia,tegra-audio-max98090.txt
index c3495beba35..25c63eac628 100644
--- a/doc/device-tree-bindings/sound/nvidia,tegra-audio-max98090.txt
+++ b/doc/device-tree-bindings/sound/nvidia,tegra-audio-max98090.txt
@@ -27,6 +27,7 @@ Required properties:
 Optional properties:
 - nvidia,hp-det-gpios : The GPIO that detect headphones are plugged in
 - nvidia,mic-det-gpios : The GPIO that detect microphones are plugged in
+- codec-enable-gpio : The GPIO used to enable the audio codec
 
 Example:
 
diff --git a/doc/device-tree-bindings/sound/snow.txt 
b/doc/device-tree-bindings/sound/snow.txt
index 80fd9a87bb3..fa06956e772 100644
--- a/doc/device-tree-bindings/sound/snow.txt
+++ b/doc/device-tree-bindings/sound/snow.txt
@@ -19,6 +19,7 @@ Required sub-nodes:
 
 Optional:
 - samsung,model: The name of the sound-card
+- codec-enable-gpio : The GPIO used to enable the audio codec
 
 Example:
 
-- 
2.21.0.593.g511ec345e18-goog

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[U-Boot] [PATCH v3 3/9] imx: mx7: Add empty arch_cpu_init if skipped

2019-04-23 Thread Jun Nie
Add empty arch_cpu_init if low level init is skipped. So that
it does not break spl compile though spl is not needed in the
skipped case actually.

Signed-off-by: Jun Nie 
---
 arch/arm/mach-imx/mx7/soc.c | 5 +
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/mach-imx/mx7/soc.c b/arch/arm/mach-imx/mx7/soc.c
index 7cfdff0..9b04013 100644
--- a/arch/arm/mach-imx/mx7/soc.c
+++ b/arch/arm/mach-imx/mx7/soc.c
@@ -286,6 +286,11 @@ int arch_cpu_init(void)
 
return 0;
 }
+#else
+int arch_cpu_init(void)
+{
+   return 0;
+}
 #endif
 
 #ifdef CONFIG_ARCH_MISC_INIT
-- 
2.7.4

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[U-Boot] [PATCH 2/3] sound: tegra: Add the binding file for tegra-audio

2019-04-23 Thread Simon Glass
This file was missed when adding the sound driver to U-Boot. Bring it in
from Linux 5.0.

Signed-off-by: Simon Glass 
---

 .../sound/nvidia,tegra-audio-max98090.txt | 53 +++
 1 file changed, 53 insertions(+)
 create mode 100644 
doc/device-tree-bindings/sound/nvidia,tegra-audio-max98090.txt

diff --git a/doc/device-tree-bindings/sound/nvidia,tegra-audio-max98090.txt 
b/doc/device-tree-bindings/sound/nvidia,tegra-audio-max98090.txt
new file mode 100644
index 000..c3495beba35
--- /dev/null
+++ b/doc/device-tree-bindings/sound/nvidia,tegra-audio-max98090.txt
@@ -0,0 +1,53 @@
+NVIDIA Tegra audio complex, with MAX98090 CODEC
+
+Required properties:
+- compatible : "nvidia,tegra-audio-max98090"
+- clocks : Must contain an entry for each entry in clock-names.
+  See ../clocks/clock-bindings.txt for details.
+- clock-names : Must include the following entries:
+  - pll_a
+  - pll_a_out0
+  - mclk (The Tegra cdev1/extern1 clock, which feeds the CODEC's mclk)
+- nvidia,model : The user-visible name of this sound complex.
+- nvidia,audio-routing : A list of the connections between audio components.
+  Each entry is a pair of strings, the first being the connection's sink,
+  the second being the connection's source. Valid names for sources and
+  sinks are the MAX98090's pins (as documented in its binding), and the jacks
+  on the board:
+
+  * Headphones
+  * Speakers
+  * Mic Jack
+  * Int Mic
+
+- nvidia,i2s-controller : The phandle of the Tegra I2S controller that's
+  connected to the CODEC.
+- nvidia,audio-codec : The phandle of the MAX98090 audio codec.
+
+Optional properties:
+- nvidia,hp-det-gpios : The GPIO that detect headphones are plugged in
+- nvidia,mic-det-gpios : The GPIO that detect microphones are plugged in
+
+Example:
+
+sound {
+   compatible = "nvidia,tegra-audio-max98090-venice2",
+"nvidia,tegra-audio-max98090";
+   nvidia,model = "NVIDIA Tegra Venice2";
+
+   nvidia,audio-routing =
+   "Headphones", "HPR",
+   "Headphones", "HPL",
+   "Speakers", "SPKR",
+   "Speakers", "SPKL",
+   "Mic Jack", "MICBIAS",
+   "IN34", "Mic Jack";
+
+   nvidia,i2s-controller = <_i2s1>;
+   nvidia,audio-codec = <>;
+
+   clocks = <_car TEGRA124_CLK_PLL_A>,
+<_car TEGRA124_CLK_PLL_A_OUT0>,
+<_car TEGRA124_CLK_EXTERN1>;
+   clock-names = "pll_a", "pll_a_out0", "mclk";
+};
-- 
2.21.0.593.g511ec345e18-goog

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[U-Boot] [PATCH v3 5/9] pico-imx7d: Reserve region of memory to OPTEE

2019-04-23 Thread Jun Nie
Subtracts CONFIG_OPTEE_TZDRAM_SIZE from the available DRAM size so that
the OPTEE memory is not override during u-boot relocation.

Note the OPTEE boot process will itself subtract the DRAM region it lives
in from the memory map passed to Linux.

Signed-off-by: Jun Nie 
---
 board/technexion/pico-imx7d/pico-imx7d.c | 5 +
 1 file changed, 5 insertions(+)

diff --git a/board/technexion/pico-imx7d/pico-imx7d.c 
b/board/technexion/pico-imx7d/pico-imx7d.c
index 53e1469..7c9e145 100644
--- a/board/technexion/pico-imx7d/pico-imx7d.c
+++ b/board/technexion/pico-imx7d/pico-imx7d.c
@@ -60,6 +60,11 @@ int dram_init(void)
 {
gd->ram_size = imx_ddr_size();
 
+   /* Subtract the defined OPTEE runtime firmware length */
+#ifdef CONFIG_OPTEE_TZDRAM_SIZE
+   gd->ram_size -= CONFIG_OPTEE_TZDRAM_SIZE;
+#endif
+
return 0;
 }
 
-- 
2.7.4

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[U-Boot] [PATCH v3 0/9] pico-imx7d: Add support for BL33 case

2019-04-23 Thread Jun Nie
Add configuration to boot U-boot as BL33 case. The boot flow
is ATF -> OPTEE -> U-boot.

Changes vs V2:
- Revise fix to UART clock ID.
- Add documentation of build and test for BL33 usage case.
- Add device tree to store public key for FIT image verfication usage.
- Add revert patch to LCD support. Pico-pi does not boot with it.
I see it is suggested to be reverted in maillist.

Changes vs V1:
- Remove DCD file.
- Add a patch to fix uart clock root ID.
- Change file name from pico-pi-imx7d_bl33_defconfig to 
pico-imx7d_bl33_defconfig


Jun Nie (9):
  Revert "pico-imx7d: Add LCD support"
  mx7_common: Share configs to skip low level init
  imx: mx7: Add empty arch_cpu_init if skipped
  pico-imx7d: Correct uart clock root
  pico-imx7d: Reserve region of memory to OPTEE
  pico-imx7d: Add boot option for verified boot
  pico-imx7d: Add device tree for pico-imx7d
  pico-imx7d: Add bl33 config
  pico-imx7d: README: Add BL33 usage case

 arch/arm/dts/Makefile  |   1 +
 arch/arm/dts/imx7d-pico-pi.dts |  93 
 arch/arm/dts/imx7d-pico.dtsi   | 585 +
 arch/arm/include/asm/arch-mx7/clock.h  |  18 +
 arch/arm/mach-imx/Kconfig  |   7 +
 arch/arm/mach-imx/mx7/clock.c  |   2 +-
 arch/arm/mach-imx/mx7/soc.c|   5 +
 board/technexion/pico-imx7d/README.pico-imx7d_BL33 |  44 ++
 board/technexion/pico-imx7d/pico-imx7d.c   |  60 +--
 configs/pico-hobbit-imx7d_defconfig|   1 -
 ...i-imx7d_defconfig => pico-imx7d_bl33_defconfig} |  40 +-
 configs/pico-imx7d_defconfig   |   1 -
 configs/pico-pi-imx7d_defconfig|   1 -
 include/configs/mx7_common.h   |  11 +
 include/configs/pico-imx7d.h   |  50 +-
 include/configs/warp7.h|  11 -
 16 files changed, 826 insertions(+), 104 deletions(-)
 create mode 100644 arch/arm/dts/imx7d-pico-pi.dts
 create mode 100644 arch/arm/dts/imx7d-pico.dtsi
 create mode 100644 board/technexion/pico-imx7d/README.pico-imx7d_BL33
 copy configs/{pico-pi-imx7d_defconfig => pico-imx7d_bl33_defconfig} (65%)

-- 
2.7.4

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[U-Boot] [PATCH v3 7/9] pico-imx7d: Add device tree for pico-imx7d

2019-04-23 Thread Jun Nie
Copy device tree files from Linux directly.

Signed-off-by: Jun Nie 
---
 arch/arm/dts/Makefile  |   1 +
 arch/arm/dts/imx7d-pico-pi.dts |  93 +++
 arch/arm/dts/imx7d-pico.dtsi   | 585 +
 3 files changed, 679 insertions(+)
 create mode 100644 arch/arm/dts/imx7d-pico-pi.dts
 create mode 100644 arch/arm/dts/imx7d-pico.dtsi

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 0aee8df..e6cb1d3 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -555,6 +555,7 @@ dtb-$(CONFIG_ARCH_MX6) += \
 
 dtb-$(CONFIG_MX7) += imx7d-sdb.dtb \
imx7d-sdb-qspi.dtb \
+   imx7d-pico-pi.dtb \
imx7-colibri-emmc.dtb \
imx7-colibri-rawnand.dtb \
imx7s-warp.dtb
diff --git a/arch/arm/dts/imx7d-pico-pi.dts b/arch/arm/dts/imx7d-pico-pi.dts
new file mode 100644
index 000..70bea95
--- /dev/null
+++ b/arch/arm/dts/imx7d-pico-pi.dts
@@ -0,0 +1,93 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+//
+// Copyright 2017 NXP
+
+#include "imx7d-pico.dtsi"
+
+/ {
+   model = "TechNexion PICO-IMX7D Board and PI baseboard";
+   compatible = "technexion,imx7d-pico-pi", "fsl,imx7d";
+
+   leds {
+   compatible = "gpio-leds";
+   pinctrl-names = "default";
+   pinctrl-0 = <_gpio_leds>;
+
+   led {
+   label = "gpio-led";
+   gpios = < 6 GPIO_ACTIVE_HIGH>;
+   };
+   };
+
+   sound {
+   compatible = "simple-audio-card";
+   simple-audio-card,name = "imx7-sgtl5000";
+   simple-audio-card,format = "i2s";
+   simple-audio-card,bitclock-master = <_master>;
+   simple-audio-card,frame-master = <_master>;
+   simple-audio-card,cpu {
+   sound-dai = <>;
+   };
+
+   dailink_master: simple-audio-card,codec {
+   sound-dai = <>;
+   clocks = < IMX7D_AUDIO_MCLK_ROOT_CLK>;
+   };
+   };
+};
+
+ {
+   sgtl5000: codec@a {
+   #sound-dai-cells = <0>;
+   reg = <0x0a>;
+   compatible = "fsl,sgtl5000";
+   clocks = < IMX7D_AUDIO_MCLK_ROOT_CLK>;
+   VDDA-supply = <_2p5v>;
+   VDDIO-supply = <_vref_1v8>;
+   };
+};
+
+ {
+   polytouch: touchscreen@38 {
+   compatible = "edt,edt-ft5x06";
+   reg = <0x38>;
+   pinctrl-names = "default";
+   pinctrl-0 = <_touchscreen>;
+   interrupt-parent = <>;
+   interrupts = <13 IRQ_TYPE_EDGE_FALLING>;
+   reset-gpios = < 4 GPIO_ACTIVE_LOW>;
+   touchscreen-size-x = <800>;
+   touchscreen-size-y = <480>;
+   };
+};
+
+ {
+   pinctrl-names = "default";
+   pinctrl-0 = <_hog>;
+
+   pinctrl_hog: hoggrp {
+   fsl,pins = <
+   MX7D_PAD_EPDC_DATA00__GPIO2_IO0 0x14
+   MX7D_PAD_EPDC_DATA01__GPIO2_IO1 0x14
+   MX7D_PAD_EPDC_DATA02__GPIO2_IO2 0x14
+   MX7D_PAD_EPDC_DATA03__GPIO2_IO3 0x14
+   MX7D_PAD_EPDC_DATA05__GPIO2_IO5 0x14
+   MX7D_PAD_EPDC_DATA12__GPIO2_IO120x14
+   MX7D_PAD_EPDC_DATA07__GPIO2_IO7 0x14
+   >;
+   };
+
+   pinctrl_gpio_leds: gpioledsgrp {
+   fsl,pins = <
+   MX7D_PAD_EPDC_DATA06__GPIO2_IO6 0x14
+   >;
+   };
+
+   pinctrl_touchscreen: touchscreengrp {
+   fsl,pins = <
+   MX7D_PAD_EPDC_DATA04__GPIO2_IO4 0x14
+   MX7D_PAD_EPDC_DATA13__GPIO2_IO130x14
+   >;
+   };
+
+};
diff --git a/arch/arm/dts/imx7d-pico.dtsi b/arch/arm/dts/imx7d-pico.dtsi
new file mode 100644
index 000..3fd595a
--- /dev/null
+++ b/arch/arm/dts/imx7d-pico.dtsi
@@ -0,0 +1,585 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+//
+// Copyright 2017 NXP
+
+/dts-v1/;
+
+#include "imx7d.dtsi"
+
+/ {
+   /* Will be filled by the bootloader */
+   memory@8000 {
+   device_type = "memory";
+   reg = <0x8000 0>;
+   };
+
+   reg_wlreg_on: regulator-wlreg_on {
+   compatible = "regulator-fixed";
+   pinctrl-names = "default";
+   pinctrl-0 = <_reg_wlreg_on>;
+   regulator-name = "wlreg_on";
+   regulator-min-microvolt = <330>;
+   regulator-max-microvolt = <330>;
+   gpio = < 16 GPIO_ACTIVE_HIGH>;
+   enable-active-high;
+   };
+
+   reg_2p5v: regulator-2p5v {
+   compatible = "regulator-fixed";
+   regulator-name = "2P5V";
+   regulator-min-microvolt = <250>;
+   

[U-Boot] [PATCH 1/3] sound: snow: Add the binding file for snow

2019-04-23 Thread Simon Glass
This file was missed when adding the sound driver to U-Boot. Bring it in
from Linux 5.0.

Signed-off-by: Simon Glass 
---

 doc/device-tree-bindings/sound/snow.txt | 31 +
 1 file changed, 31 insertions(+)
 create mode 100644 doc/device-tree-bindings/sound/snow.txt

diff --git a/doc/device-tree-bindings/sound/snow.txt 
b/doc/device-tree-bindings/sound/snow.txt
new file mode 100644
index 000..80fd9a87bb3
--- /dev/null
+++ b/doc/device-tree-bindings/sound/snow.txt
@@ -0,0 +1,31 @@
+Audio Binding for Snow boards
+
+Required properties:
+- compatible : Can be one of the following,
+   "google,snow-audio-max98090" or
+   "google,snow-audio-max98091" or
+   "google,snow-audio-max98095"
+- samsung,i2s-controller (deprecated): The phandle of the Samsung I2S 
controller
+- samsung,audio-codec (deprecated): The phandle of the audio codec
+
+Required sub-nodes:
+
+ - 'cpu' subnode with a 'sound-dai' property containing the phandle of the I2S
+controller
+ - 'codec' subnode with a 'sound-dai' property containing list of phandles
+to the CODEC nodes, first entry must be the phandle of the MAX98090,
+MAX98091 or MAX98095 CODEC (exact device type is indicated by the 
compatible
+string) and the second entry must be the phandle of the HDMI IP block node
+
+Optional:
+- samsung,model: The name of the sound-card
+
+Example:
+
+sound {
+   compatible = "google,snow-audio-max98095";
+
+   samsung,model = "Snow-I2S-MAX98095";
+   samsung,i2s-controller = <>;
+   samsung,audio-codec = <>;
+};
-- 
2.21.0.593.g511ec345e18-goog

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[U-Boot] [PATCH v3 2/9] mx7_common: Share configs to skip low level init

2019-04-23 Thread Jun Nie
Share configs in mx7 to skip low level init if we are in the case where
OPTEE is loaded already (maybe by ARM Trusted Firmware) and that most of
the low level initialization is already done and that we may/should skip
it doing them here.

Fix the definition detection with size detection to decide whether to skip
it.

Signed-off-by: Jun Nie 
---
 include/configs/mx7_common.h | 11 +++
 include/configs/warp7.h  | 11 ---
 2 files changed, 11 insertions(+), 11 deletions(-)

diff --git a/include/configs/mx7_common.h b/include/configs/mx7_common.h
index cc7e872..57fbec7 100644
--- a/include/configs/mx7_common.h
+++ b/include/configs/mx7_common.h
@@ -54,4 +54,15 @@
 #endif
 #endif
 
+/*
+ * If we have defined the OPTEE ram size and not OPTEE it means that we were
+ * launched by OPTEE, because of that we shall skip all the low level
+ * initialization since it was already done by ATF or OPTEE
+ */
+#if (CONFIG_OPTEE_TZDRAM_SIZE != 0)
+#ifndef CONFIG_OPTEE
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#endif
+#endif
+
 #endif
diff --git a/include/configs/warp7.h b/include/configs/warp7.h
index 043f286..80ddd72 100644
--- a/include/configs/warp7.h
+++ b/include/configs/warp7.h
@@ -13,17 +13,6 @@
 
 #define PHYS_SDRAM_SIZESZ_512M
 
-/*
- * If we have defined the OPTEE ram size and not OPTEE it means that we were
- * launched by OPTEE, because of that we shall skip all the low level
- * initialization since it was already done by ATF or OPTEE
- */
-#ifdef CONFIG_OPTEE_TZDRAM_SIZE
-#ifndef CONFIG_OPTEE
-#define CONFIG_SKIP_LOWLEVEL_INIT
-#endif
-#endif
-
 #define CONFIG_MXC_UART_BASE   UART1_IPS_BASE_ADDR
 
 /* Size of malloc() pool */
-- 
2.7.4

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Re: [U-Boot] [PATCH 1/2] disk: efi: unify code for finding a valid gpt

2019-04-23 Thread Simon Glass
On Wed, 3 Apr 2019 at 06:25, Urja Rannikko  wrote:
>
> There were 3 copies of the same sequence, make it into a function.
>
> Signed-off-by: Urja Rannikko 
> ---
>  disk/part_efi.c | 73 +++--
>  1 file changed, 34 insertions(+), 39 deletions(-)
>

Reviewed-by: Simon Glass 
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Re: [U-Boot] [PATCH v2 02/10] pinctrl: rockchip: Remove redundant spaces

2019-04-23 Thread Simon Glass
On Wed, 3 Apr 2019 at 21:52, David Wu  wrote:
>
> Some files have the redundant spaces, remove them.
>
> Signed-off-by: David Wu 
> ---
>
>  drivers/pinctrl/rockchip/pinctrl-rk3036.c | 12 ++--
>  drivers/pinctrl/rockchip/pinctrl-rk3188.c | 12 ++--
>  drivers/pinctrl/rockchip/pinctrl-rk322x.c | 18 -
>  drivers/pinctrl/rockchip/pinctrl-rk3288.c | 20 +--
>  drivers/pinctrl/rockchip/pinctrl-rk3328.c | 24 +++
>  drivers/pinctrl/rockchip/pinctrl-rk3368.c | 16 +++
>  drivers/pinctrl/rockchip/pinctrl-rk3399.c | 24 +++
>  7 files changed, 63 insertions(+), 63 deletions(-)
>

Reviewed-by: Simon Glass 
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[U-Boot] [PATCH v3 1/9] Revert "pico-imx7d: Add LCD support"

2019-04-23 Thread Jun Nie
This reverts commit 9e3c0174da842dd88f5feaffbf843ba332233897.
---
 board/technexion/pico-imx7d/pico-imx7d.c | 55 
 configs/pico-hobbit-imx7d_defconfig  |  1 -
 configs/pico-imx7d_defconfig |  1 -
 configs/pico-pi-imx7d_defconfig  |  1 -
 include/configs/pico-imx7d.h | 12 ---
 5 files changed, 70 deletions(-)

diff --git a/board/technexion/pico-imx7d/pico-imx7d.c 
b/board/technexion/pico-imx7d/pico-imx7d.c
index 767d13d..53e1469 100644
--- a/board/technexion/pico-imx7d/pico-imx7d.c
+++ b/board/technexion/pico-imx7d/pico-imx7d.c
@@ -39,16 +39,8 @@ DECLARE_GLOBAL_DATA_PTR;
 #define I2C_PAD_CTRL(PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU100KOHM)
 
-
-#define LCD_PAD_CTRL(PAD_CTL_HYS | PAD_CTL_PUS_PU100KOHM | \
-PAD_CTL_DSE_3P3V_49OHM)
-
-#define LCD_SYNC_PAD_CTRL(PAD_CTL_HYS | PAD_CTL_PUS_PU100KOHM | \
- PAD_CTL_DSE_3P3V_196OHM)
-
 #ifdef CONFIG_SYS_I2C_MXC
 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
-
 /* I2C4 for PMIC */
 static struct i2c_pads_info i2c_pad_info4 = {
.scl = {
@@ -254,58 +246,11 @@ int board_early_init_f(void)
return 0;
 }
 
-#ifdef CONFIG_VIDEO_MXS
-static iomux_v3_cfg_t const lcd_pads[] = {
-   MX7D_PAD_LCD_CLK__LCD_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL),
-   MX7D_PAD_LCD_ENABLE__LCD_ENABLE | MUX_PAD_CTRL(LCD_SYNC_PAD_CTRL),
-   MX7D_PAD_LCD_HSYNC__LCD_HSYNC | MUX_PAD_CTRL(LCD_SYNC_PAD_CTRL),
-   MX7D_PAD_LCD_VSYNC__LCD_VSYNC | MUX_PAD_CTRL(LCD_SYNC_PAD_CTRL),
-   MX7D_PAD_LCD_DATA00__LCD_DATA0 | MUX_PAD_CTRL(LCD_PAD_CTRL),
-   MX7D_PAD_LCD_DATA01__LCD_DATA1 | MUX_PAD_CTRL(LCD_PAD_CTRL),
-   MX7D_PAD_LCD_DATA02__LCD_DATA2 | MUX_PAD_CTRL(LCD_PAD_CTRL),
-   MX7D_PAD_LCD_DATA03__LCD_DATA3 | MUX_PAD_CTRL(LCD_PAD_CTRL),
-   MX7D_PAD_LCD_DATA04__LCD_DATA4 | MUX_PAD_CTRL(LCD_PAD_CTRL),
-   MX7D_PAD_LCD_DATA05__LCD_DATA5 | MUX_PAD_CTRL(LCD_PAD_CTRL),
-   MX7D_PAD_LCD_DATA06__LCD_DATA6 | MUX_PAD_CTRL(LCD_PAD_CTRL),
-   MX7D_PAD_LCD_DATA07__LCD_DATA7 | MUX_PAD_CTRL(LCD_PAD_CTRL),
-   MX7D_PAD_LCD_DATA08__LCD_DATA8 | MUX_PAD_CTRL(LCD_PAD_CTRL),
-   MX7D_PAD_LCD_DATA09__LCD_DATA9 | MUX_PAD_CTRL(LCD_PAD_CTRL),
-   MX7D_PAD_LCD_DATA10__LCD_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL),
-   MX7D_PAD_LCD_DATA11__LCD_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL),
-   MX7D_PAD_LCD_DATA12__LCD_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL),
-   MX7D_PAD_LCD_DATA13__LCD_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL),
-   MX7D_PAD_LCD_DATA14__LCD_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL),
-   MX7D_PAD_LCD_DATA15__LCD_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL),
-   MX7D_PAD_LCD_DATA16__LCD_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL),
-   MX7D_PAD_LCD_DATA17__LCD_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL),
-   MX7D_PAD_LCD_DATA18__LCD_DATA18 | MUX_PAD_CTRL(LCD_PAD_CTRL),
-   MX7D_PAD_LCD_DATA19__LCD_DATA19 | MUX_PAD_CTRL(LCD_PAD_CTRL),
-   MX7D_PAD_LCD_DATA20__LCD_DATA20 | MUX_PAD_CTRL(LCD_PAD_CTRL),
-   MX7D_PAD_LCD_DATA21__LCD_DATA21 | MUX_PAD_CTRL(LCD_PAD_CTRL),
-   MX7D_PAD_LCD_DATA22__LCD_DATA22 | MUX_PAD_CTRL(LCD_PAD_CTRL),
-   MX7D_PAD_LCD_DATA23__LCD_DATA23 | MUX_PAD_CTRL(LCD_PAD_CTRL),
-   MX7D_PAD_GPIO1_IO06__GPIO1_IO6  | MUX_PAD_CTRL(LCD_PAD_CTRL),
-   MX7D_PAD_GPIO1_IO11__GPIO1_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
-};
-
-void setup_lcd(void)
-{
-   imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
-   /* Set Brightness to high */
-   gpio_direction_output(IMX_GPIO_NR(1, 11) , 1);
-   /* Set LCD enable to high */
-   gpio_direction_output(IMX_GPIO_NR(1, 6) , 1);
-}
-#endif
-
 int board_init(void)
 {
/* address of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 
-#ifdef CONFIG_VIDEO_MXS
-   setup_lcd();
-#endif
 #ifdef CONFIG_FEC_MXC
setup_fec();
 #endif
diff --git a/configs/pico-hobbit-imx7d_defconfig 
b/configs/pico-hobbit-imx7d_defconfig
index f58d517..cb4a6bf 100644
--- a/configs/pico-hobbit-imx7d_defconfig
+++ b/configs/pico-hobbit-imx7d_defconfig
@@ -57,5 +57,4 @@ CONFIG_USB_GADGET_MANUFACTURER="FSL"
 CONFIG_USB_GADGET_VENDOR_NUM=0x0525
 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
 CONFIG_CI_UDC=y
-CONFIG_VIDEO=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/pico-imx7d_defconfig b/configs/pico-imx7d_defconfig
index 7e13923..f90d757 100644
--- a/configs/pico-imx7d_defconfig
+++ b/configs/pico-imx7d_defconfig
@@ -57,5 +57,4 @@ CONFIG_USB_GADGET_MANUFACTURER="FSL"
 CONFIG_USB_GADGET_VENDOR_NUM=0x0525
 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
 CONFIG_CI_UDC=y
-CONFIG_VIDEO=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/pico-pi-imx7d_defconfig b/configs/pico-pi-imx7d_defconfig
index c8ac2ff..8e48ba7 100644
--- a/configs/pico-pi-imx7d_defconfig
+++ b/configs/pico-pi-imx7d_defconfig
@@ -57,5 +57,4 @@ CONFIG_USB_GADGET_MANUFACTURER="FSL"
 CONFIG_USB_GADGET_VENDOR_NUM=0x0525
 

Re: [U-Boot] [PATCH] rk8xx: implement poweroff

2019-04-23 Thread Simon Glass
Hi,

On Wed, 3 Apr 2019 at 06:21, Urja Rannikko  wrote:
>
> Based on snooping around the linux kernel rk8xx driver, and
> tested to work on the ASUS C201.
>
> Signed-off-by: Urja Rannikko 
> ---
> This is really handy to be able to poweroff (without pressing power button
> for a long time) the C201 from u-boot, so i'm sending this as is.
> The thing that is bothering me is the pmic_get --- i checked that
> every rk8xx is named "pmic" in the device tree so it should work, but
> it just feels really weird that this seems to be the best way to access
> the driver...
>
>  drivers/power/pmic/rk8xx.c | 34 ++
>  include/power/rk8xx_pmic.h |  4 
>  2 files changed, 38 insertions(+)

This should really use a sysreset driver.

You can make the PMIC have a child sysreset driver to implement this function.

Regards,
Simon
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Re: [U-Boot] [PATCH v2 3/7] tegra: sound: Add an audio hub driver

2019-04-23 Thread Simon Glass
Hi Jon,

On Wed, 3 Apr 2019 at 03:05, Jon Hunter  wrote:
>
>
> On 01/04/2019 21:38, Simon Glass wrote:
> > Add a driver for the audio hub. This is modelled as a misc device which
> > supports writing audio data from I2S.
> >
> > Signed-off-by: Simon Glass 
> > ---
> >
> > Changes in v2:
> > - Fix 'I2C' typo
> >
> >  arch/arm/include/asm/arch-tegra/tegra_ahub.h | 475 +++
> >  drivers/sound/Kconfig|   9 +
> >  drivers/sound/Makefile   |   1 +
> >  drivers/sound/tegra_ahub.c   | 256 ++
> >  4 files changed, 741 insertions(+)
> >  create mode 100644 arch/arm/include/asm/arch-tegra/tegra_ahub.h
> >  create mode 100644 drivers/sound/tegra_ahub.c
> >
> > diff --git a/arch/arm/include/asm/arch-tegra/tegra_ahub.h
> > b/arch/arm/include/asm/arch-tegra/tegra_ahub.h
> > new file mode 100644
> > index 000..96d542a91ca
> > --- /dev/null
> > +++ b/arch/arm/include/asm/arch-tegra/tegra_ahub.h
> > @@ -0,0 +1,475 @@
> > +/* SPDX-License-Identifier: GPL-2.0 */
> > +/*
> > + * tegra_ahub.h - Definitions for Tegra124 audio hub driver
> > + * Taken from dc tegra_ahub.h
> > + *
> > + * Copyright 2018 Google LLC
> > + * Copyright (c) 2013, NVIDIA CORPORATION.  All rights reserved.
> > + */
>
> Looks fine to me, although you may wish to update your copyright date
> now ;-)
>
> Acked-by: Jon Hunter 

Feel free to update it when applying, but I'm OK with it. It's been
sitting around for a while!

Regards,
Simon
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Re: [U-Boot] [PATCH v2 5/7] sound: tegra: Add a sound driver

2019-04-23 Thread Simon Glass
Hi Jon,

On Wed, 3 Apr 2019 at 03:15, Jon Hunter  wrote:
>
>
> On 01/04/2019 21:38, Simon Glass wrote:
> > Add a sound driver for tegra devices. This connects the audio hub, I2S
> > controller and audio codec to allow sound output.
> >
> > Signed-off-by: Simon Glass 
> > ---
> >
> > Changes in v2: None
> >
> >  drivers/sound/Makefile  |   2 +-
> >  drivers/sound/tegra_sound.c | 100 
> >  2 files changed, 101 insertions(+), 1 deletion(-)
> >  create mode 100644 drivers/sound/tegra_sound.c
> >
> > diff --git a/drivers/sound/Makefile b/drivers/sound/Makefile
> > index 358d5f920b2..73ed7fe53c3 100644
> > --- a/drivers/sound/Makefile
> > +++ b/drivers/sound/Makefile
> > @@ -11,7 +11,7 @@ obj-$(CONFIG_I2S_SAMSUNG)   += samsung-i2s.o
> >  obj-$(CONFIG_SOUND_SANDBOX)  += sandbox.o
> >  obj-$(CONFIG_I2S_ROCKCHIP)   += rockchip_i2s.o rockchip_sound.o
> >  obj-$(CONFIG_I2S_SAMSUNG)+= samsung_sound.o
> > -obj-$(CONFIG_I2S_TEGRA)  += tegra_ahub.o tegra_i2s.o
> > +obj-$(CONFIG_I2S_TEGRA)  += tegra_ahub.o tegra_i2s.o 
> > tegra_sound.o
> >  obj-$(CONFIG_SOUND_WM8994)   += wm8994.o
> >  obj-$(CONFIG_SOUND_MAX98088) += max98088.o maxim_codec.o
> >  obj-$(CONFIG_SOUND_MAX98090) += max98090.o maxim_codec.o
> > diff --git a/drivers/sound/tegra_sound.c b/drivers/sound/tegra_sound.c
> > new file mode 100644
> > index 000..7c2ed53f5a7
> > --- /dev/null
> > +++ b/drivers/sound/tegra_sound.c
> > @@ -0,0 +1,100 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * Copyright 2018 Google, LLC
> > + * Written by Simon Glass 
> > + */
> > +
> > +#define LOG_CATEGORY UCLASS_I2S
> > +
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include "tegra_i2s_priv.h"
> > +
> > +static int tegra_sound_setup(struct udevice *dev)
> > +{
> > + struct sound_uc_priv *uc_priv = dev_get_uclass_priv(dev);
> > + struct i2s_uc_priv *i2c_priv = dev_get_uclass_priv(uc_priv->i2s);
> > + int ret;
> > +
> > + if (uc_priv->setup_done)
> > + return -EALREADY;
> > + ret = audio_codec_set_params(uc_priv->codec, i2c_priv->id,
> > +  i2c_priv->samplingrate,
> > +  i2c_priv->samplingrate * i2c_priv->rfs,
> > +  i2c_priv->bitspersample,
> > +  i2c_priv->channels);
> > + if (ret)
> > + return ret;
> > + uc_priv->setup_done = true;
> > +
> > + return 0;
> > +}
> > +
> > +static int tegra_sound_play(struct udevice *dev, void *data, uint 
> > data_size)
> > +{
> > + struct sound_uc_priv *uc_priv = dev_get_uclass_priv(dev);
> > +
> > + return i2s_tx_data(uc_priv->i2s, data, data_size);
> > +}
> > +
> > +static int tegra_sound_probe(struct udevice *dev)
> > +{
> > + struct sound_uc_priv *uc_priv = dev_get_uclass_priv(dev);
> > + struct gpio_desc en_gpio;
> > + struct udevice *ahub;
> > + int ret;
> > +
> > + ret = gpio_request_by_name(dev, "codec-enable-gpio", 0, _gpio,
> > +GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
>
>
> This looks a bit odd. I am not sure if this is supposed to be optional
> or not, but there is no checking of the return value although you store it.

Yes. If there is an error then en_gpio will not be set up. Then later
on we won't set the GPIO when enabling the codec.

>
> Is there DT binding documentation that does along with this that
> describes these properties?

Unfortunately not. The binding is actually board-specific in many
cases. I'll do a little series to in these files for all boards
including nyan.

Regards,
Simon
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Re: [U-Boot] [PATCH V2] mmc: dw_mmc: Calculate timeout from transfer length

2019-04-23 Thread Simon Glass
On Mon, 1 Apr 2019 at 21:39, Marek Vasut  wrote:
>
> The current 4-minute data transfer timeout is misleading and broken.
> Instead of such a long wait, calculate the timeout duration based on
> the length of the data transfer. The current formula is the transfer
> length in bits, divided by a multiplication of bus frequency in Hz,
> bus width, DDR mode and converted the mSec. The value is bounded from
> the bottom to 1000 mSec.
>
> Signed-off-by: Marek Vasut 
> Cc: Jaehoon Chung 
> Cc: Simon Glass 
> ---
> V2: Pull the timeout calculation into separate function
> ---
>  drivers/mmc/dw_mmc.c | 24 +---
>  1 file changed, 21 insertions(+), 3 deletions(-)

Reviewed-by: Simon Glass 
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Re: [U-Boot] [PATCH 2/2] disk: efi: ignore 'IGNOREME' GPT header found on cros eMMCs

2019-04-23 Thread Simon Glass
Hi Urja,

On Wed, 3 Apr 2019 at 06:25, Urja Rannikko  wrote:
>
> Some ChromeOS devices (atleast veyron speedy) have the first 8MiB of
> the eMMC write protected and equipped with a dummy 'IGNOREME' GPT
> header - instead of spewing error messages about it, just silently
> try the backup GPT.
>
> Note: this does not touch the gpt cmd writing/verifying functions,
> those will still complain.
>
> Signed-off-by: Urja Rannikko 
> ---
>  disk/part_efi.c| 28 +---
>  include/part_efi.h |  2 ++
>  2 files changed, 23 insertions(+), 7 deletions(-)

Could we add a Kconfig to control this? Other devices shouldn't have this code.

Regards,
SImon
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Re: [U-Boot] [PATCH 3/3] configs: update rk3288 veyron defconfigs

2019-04-23 Thread Simon Glass
On Wed, 3 Apr 2019 at 03:34, Urja Rannikko  wrote:
>
> Updates jerry, mickey, minnie and speedy defconfigs to:
> - fit the SPL in 32k
> - boot from SPI (only)
> - remove gadget support (these have no OTG port)
>
> Signed-off-by: Urja Rannikko 
> ---
>  configs/chromebit_mickey_defconfig  | 26 --
>  configs/chromebook_jerry_defconfig  | 26 --
>  configs/chromebook_minnie_defconfig | 26 --
>  configs/chromebook_speedy_defconfig | 26 ++
>  4 files changed, 62 insertions(+), 42 deletions(-)

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Re: [U-Boot] [PATCH 1/1] test: env: Enable env unit tests by default

2019-04-23 Thread Simon Glass
On Sun, 7 Apr 2019 at 09:58, Heinrich Schuchardt  wrote:
>
> If CONFIG_UNIT_TEST is enabled we should enable the individual tests by
> default to ensure good test coverage.
>
> Signed-off-by: Heinrich Schuchardt 
> ---
> Tests ok on Travis CI:
> https://travis-ci.org/xypron2/u-boot/builds/516825681
> ---
>  test/env/Kconfig | 1 +
>  1 file changed, 1 insertion(+)

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Re: [U-Boot] [PATCH 1/3] configs: Move CONFIG_SPI_FLASH_GIGADEVICE properly into Kconfig

2019-04-23 Thread Simon Glass
On Wed, 3 Apr 2019 at 03:34, Urja Rannikko  wrote:
>
> Affects rk3288 veyrons and rk3036, this was mostly done by
> moveconfig.py.
>
> Signed-off-by: Urja Rannikko 
> ---
>  configs/chromebit_mickey_defconfig  | 1 +
>  configs/chromebook_jerry_defconfig  | 1 +
>  configs/chromebook_minnie_defconfig | 1 +
>  configs/chromebook_speedy_defconfig | 1 +
>  configs/evb-rk3036_defconfig| 1 +
>  configs/kylin-rk3036_defconfig  | 1 +
>  include/configs/rk3036_common.h | 2 --
>  include/configs/veyron.h| 2 --
>  8 files changed, 6 insertions(+), 4 deletions(-)

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Re: [U-Boot] [RFC PATCH v1 2/2] power: regulator: support ROHM BD71837 PMIC

2019-04-23 Thread Simon Glass
Hi Matti,

On Wed, 27 Mar 2019 at 06:40, Matti Vaittinen
 wrote:
>
> Add regulator driver for ROHM BD71837 PMIC. BD71837 contains
> 8 bucks and 7 LDOS. Voltages for bucks 1-4 can be adjusted
> when regulators are enabled. For other bucks and LDOs we may
> have over- or undershooting if voltage is adjusted when
> regulator is enabled. Thus this is prevented by default.
>
> BD71837 has a quirk which may leave power output disabled
> after reset if enable/disable state was controlled by SW.
> Thus the SW control is only allowed for bucks3 and 4 by
> default.
>
> Signed-off-by: Matti Vaittinen 
> ---
>  drivers/power/regulator/Kconfig   |  15 ++
>  drivers/power/regulator/Makefile  |   1 +
>  drivers/power/regulator/bd71837.c | 373 ++
>  include/power/bd71837.h   |  20 ++
>  4 files changed, 409 insertions(+)
>

Reviewed-by: Simon Glass 

But please see nits below.


> diff --git a/drivers/power/regulator/Kconfig b/drivers/power/regulator/Kconfig
> index 3ed0dd2264..323516587c 100644
> --- a/drivers/power/regulator/Kconfig
> +++ b/drivers/power/regulator/Kconfig
> @@ -43,6 +43,21 @@ config REGULATOR_AS3722
>   but does not yet support change voltages. Currently this must be
>   done using direct register writes to the PMIC.
>
> +config DM_REGULATOR_BD71837
> +   bool "Enable Driver Model for REGULATOR BD71837"
> +   depends on DM_REGULATOR && DM_PMIC_BD71837
> +   help
> +   This config enables implementation of driver-model regulator uclass
> +   features for REGULATOR BD71837. The driver implements get/set api for:
> +   value and enable.
> +
> +config SPL_DM_REGULATOR_BD71837
> +   bool "Enable Driver Model for REGULATOR BD71837 in SPL"
> +   depends on DM_REGULATOR_BD71837
> +   help
> +   This config enables implementation of driver-model regulator uclass
> +   features for REGULATOR BD71837 in SPL.
> +
>  config DM_REGULATOR_PFUZE100
> bool "Enable Driver Model for REGULATOR PFUZE100"
> depends on DM_REGULATOR && DM_PMIC_PFUZE100
> diff --git a/drivers/power/regulator/Makefile 
> b/drivers/power/regulator/Makefile
> index f617ce723a..898ed5f084 100644
> --- a/drivers/power/regulator/Makefile
> +++ b/drivers/power/regulator/Makefile
> @@ -9,6 +9,7 @@ obj-$(CONFIG_REGULATOR_ACT8846) += act8846.o
>  obj-$(CONFIG_REGULATOR_AS3722) += as3722_regulator.o
>  obj-$(CONFIG_DM_REGULATOR_MAX77686) += max77686.o
>  obj-$(CONFIG_$(SPL_)DM_PMIC_PFUZE100) += pfuze100.o
> +obj-$(CONFIG_$(SPL_)DM_REGULATOR_BD71837) += bd71837.o
>  obj-$(CONFIG_$(SPL_)REGULATOR_PWM) += pwm_regulator.o
>  obj-$(CONFIG_$(SPL_)DM_REGULATOR_FAN53555) += fan53555.o
>  obj-$(CONFIG_$(SPL_)DM_REGULATOR_FIXED) += fixed.o
> diff --git a/drivers/power/regulator/bd71837.c 
> b/drivers/power/regulator/bd71837.c
> new file mode 100644
> index 00..5b32425ba9
> --- /dev/null
> +++ b/drivers/power/regulator/bd71837.c
> @@ -0,0 +1,373 @@
> +// SPDX-License-Identifier: GPL-2.0-or-later
> +//
> +// Copyright (C) 2019 ROHM Semiconductors
> +//
> +// ROHM BD71837 regulator driver

The SPDX line has a // comment but everything else should use C comments:

/*
 * Copyright ...
 *
 * ROHM ...
 */

> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +#define HW_STATE_CONTROL 0
> +

Need struct comment.

/**
 * struct bd71837_vrange - description here
 *
 * @min_volt: Description here
 * ...
 */

> +struct bd71837_vrange {
> +   unsigned intmin_volt;
> +   unsigned intstep;
> +   u8  min_sel;
> +   u8  max_sel;
> +   u8  rangeval;
> +};
> +

Need struct comment

> +struct bd71837_data {

How about bd71837_platdata?

> +   const char  *name;
> +   u8  enable_reg;
> +   u8  enablemask;
> +   u8  volt_reg;
> +   u8  volt_mask;
> +   struct bd71837_vrange   *ranges;
> +   unsigned intnumranges;
> +   u8  rangemask;
> +   u8  sel_mask;
> +   booldvs;
> +};
> +
> +#define BD_RANGE(_min, _vstep, _sel_low, _sel_hi, _range_sel) \
> +{ \
> +   .min_volt = (_min), .step = (_vstep), .min_sel = (_sel_low), \
> +   .max_sel = (_sel_hi), .rangeval = (_range_sel) \
> +}
> +
> +#define BD_DATA(_name, enreg, enmask, vreg, vmask, _range, rmask, _dvs, sel) 
> \
> +{ \
> +   .name = (_name), .enable_reg = (enreg), .enablemask = (enmask), \
> +   .volt_reg = (vreg), .volt_mask = (vmask), .ranges = (_range), \
> +   .numranges = ARRAY_SIZE(_range), .rangemask = (rmask), .dvs = (_dvs), 
> \
> +   .sel_mask = (sel) \
> +}
> +
> +static struct bd71837_vrange buck1to4_vranges[] = {
> +   BD_RANGE(70, 1, 0, 0x3C, 0),

Please use lower-case hex throughout.

> +   BD_RANGE(130, 0, 0x3D, 0x3F, 0),
> +};
> +
> +static 

Re: [U-Boot] [PATCH v1 1/2] regulator: bd71837: copy the bd71837 pmic driver from NXP imx u-boot

2019-04-23 Thread Simon Glass
Hi Matti,

On Mon, 8 Apr 2019 at 04:28, Matti Vaittinen
 wrote:
>
> https://source.codeaurora.org/external/imx/uboot-imx
>
> cherry picked, styled and merged commits:
> - MLK-18387 pmic: Add pmic driver for BD71837: e9a3bec2e95a
> - MLK-18590 pmic: bd71837: Change to use new fdt API: acdc5c297a96
>
> Signed-off-by: Ye Li 
> Signed-off-by: Matti Vaittinen 
> ---
>
> Based on RFC:
> https://lists.denx.de/pipermail/u-boot/2019-March/363076.html
>
>  drivers/power/pmic/Kconfig|  7 +++
>  drivers/power/pmic/Makefile   |  2 +
>  drivers/power/pmic/bd71837.c  | 89 +++
>  drivers/power/pmic/pmic_bd71837.c | 31 +++
>  include/power/bd71837.h   | 64 ++
>  5 files changed, 193 insertions(+)
>  create mode 100644 drivers/power/pmic/bd71837.c
>  create mode 100644 drivers/power/pmic/pmic_bd71837.c
>  create mode 100644 include/power/bd71837.h
>
> diff --git a/drivers/power/pmic/Kconfig b/drivers/power/pmic/Kconfig
> index 8cf60ebcf3..e154d0a57b 100644
> --- a/drivers/power/pmic/Kconfig
> +++ b/drivers/power/pmic/Kconfig
> @@ -48,6 +48,13 @@ config PMIC_AS3722
>   interface and is designs to cover most of the power managementment
>   required for a tablets or laptop.
>
> +config DM_PMIC_BD71837
> +   bool "Enable Driver Model for PMIC BD71837"
> +   depends on DM_PMIC
> +   help
> + This config enables implementation of driver-model pmic uclass 
> features
> + for PMIC BD71837. The driver implements read/write operations.
> +
>  config DM_PMIC_FAN53555
> bool "Enable support for OnSemi FAN53555"
> depends on DM_PMIC && DM_REGULATOR && DM_I2C
> diff --git a/drivers/power/pmic/Makefile b/drivers/power/pmic/Makefile
> index 637352ab2b..e74c6190a8 100644
> --- a/drivers/power/pmic/Makefile
> +++ b/drivers/power/pmic/Makefile
> @@ -8,6 +8,7 @@ obj-$(CONFIG_DM_PMIC_FAN53555) += fan53555.o
>  obj-$(CONFIG_DM_PMIC_MAX77686) += max77686.o
>  obj-$(CONFIG_DM_PMIC_MAX8998) += max8998.o
>  obj-$(CONFIG_DM_PMIC_MC34708) += mc34708.o
> +obj-$(CONFIG_$(SPL_)DM_PMIC_BD71837) += bd71837.o
>  obj-$(CONFIG_$(SPL_)DM_PMIC_PFUZE100) += pfuze100.o
>  obj-$(CONFIG_PMIC_S2MPS11) += s2mps11.o
>  obj-$(CONFIG_DM_PMIC_SANDBOX) += sandbox.o i2c_pmic_emul.o
> @@ -30,6 +31,7 @@ obj-$(CONFIG_POWER_MAX77696) += pmic_max77696.o
>  obj-$(CONFIG_POWER_MAX8998) += pmic_max8998.o
>  obj-$(CONFIG_POWER_MAX8997) += pmic_max8997.o
>  obj-$(CONFIG_POWER_MUIC_MAX8997) += muic_max8997.o
> +obj-$(CONFIG_POWER_BD71837) += pmic_bd71837.o
>  obj-$(CONFIG_POWER_PFUZE100) += pmic_pfuze100.o
>  obj-$(CONFIG_POWER_PFUZE3000) += pmic_pfuze3000.o
>  obj-$(CONFIG_POWER_TPS65217) += pmic_tps65217.o
> diff --git a/drivers/power/pmic/bd71837.c b/drivers/power/pmic/bd71837.c
> new file mode 100644
> index 00..eadf373a18
> --- /dev/null
> +++ b/drivers/power/pmic/bd71837.c
> @@ -0,0 +1,89 @@
> +// SPDX-License-Identifier:  GPL-2.0+
> +//
> +// Copyright 2018 NXP  *
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +static const struct pmic_child_info pmic_children_info[] = {
> +   /* buck */
> +   { .prefix = "b", .driver = BD71837_REGULATOR_DRIVER},
> +   /* ldo */
> +   { .prefix = "l", .driver = BD71837_REGULATOR_DRIVER},
> +   { },
> +};
> +
> +static int bd71837_reg_count(struct udevice *dev)
> +{
> +   return BD71837_REG_NUM;
> +}
> +
> +static int bd71837_write(struct udevice *dev, uint reg, const uint8_t *buff,
> +int len)
> +{
> +   if (dm_i2c_write(dev, reg, buff, len)) {
> +   pr_err("write error to device: %p register: %#x!", dev, reg);
> +   return -EIO;
> +   }
> +
> +   return 0;
> +}
> +
> +static int bd71837_read(struct udevice *dev, uint reg, uint8_t *buff, int 
> len)
> +{
> +   if (dm_i2c_read(dev, reg, buff, len)) {
> +   pr_err("read error from device: %p register: %#x!", dev, reg);
> +   return -EIO;
> +   }
> +
> +   return 0;
> +}
> +
> +static int bd71837_bind(struct udevice *dev)
> +{
> +   int children;
> +   ofnode regulators_node;
> +
> +   regulators_node = dev_read_subnode(dev, "regulators");
> +   if (!ofnode_valid(regulators_node)) {
> +   debug("%s: %s regulators subnode not found!", __func__,
> + dev->name);
> +   return -ENXIO;
> +   }
> +
> +   debug("%s: '%s' - found regulators subnode\n", __func__, dev->name);
> +
> +   children = pmic_bind_children(dev, regulators_node, 
> pmic_children_info);
> +   if (!children)
> +   debug("%s: %s - no child found\n", __func__, dev->name);
> +
> +   /* Always return success for this device */
> +   return 0;
> +}
> +
> +static struct dm_pmic_ops bd71837_ops = {
> +   .reg_count = bd71837_reg_count,
> +   .read = bd71837_read,
> +   

Re: [U-Boot] [PATCH v4 1/2] dlmalloc: fix malloc range at end of ram

2019-04-23 Thread Simon Glass
On Mon, 1 Apr 2019 at 14:01, Simon Goldschmidt
 wrote:
>
> If the malloc range passed to mem_malloc_init() is at the end of address
> range and 'start + size' overflows to 0, following allocations fail as
> mem_malloc_end is zero (which looks like uninitialized).
>
> Fix this by subtracting 1 of 'start + size' overflows to zero.
>
> Signed-off-by: Simon Goldschmidt 
> ---
>
> Changes in v4: None
> Changes in v3: None
>
>  common/dlmalloc.c | 4 
>  1 file changed, 4 insertions(+)

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Re: [U-Boot] [PATCH] mmc: Move tegra loopback disable option to be under tegra

2019-04-23 Thread Simon Glass
On Mon, 1 Apr 2019 at 17:05, Trent Piepho  wrote:
>
> This is a configuration option specific to the tegra controller.
>
> Doing it this way makes it show up directly under the tegra controller
> option, indented one level, as "Disable external clock loopback".
>
> The way it is now, it shows up at the end of the controller list, not
> indented, as if it's some kind of generic MMC configuration option.
>
> Cc: Marcel Ziswiler 
> Cc: Simon Glass 
> Cc: Jaehoon Chung 
> Cc: Tom Warren 
> Signed-off-by: Trent Piepho 
> ---
>  drivers/mmc/Kconfig | 22 +++---
>  1 file changed, 11 insertions(+), 11 deletions(-)
>

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Re: [U-Boot] [PATCH v4 2/2] dlmalloc: be compatible to tiny printf

2019-04-23 Thread Simon Glass
On Mon, 1 Apr 2019 at 14:01, Simon Goldschmidt
 wrote:
>
> Convert debug output from '%#lx' to '0x%lx' to be compatible with tiny
> printf used in SPL.
>
> Signed-off-by: Simon Goldschmidt 
> ---
>
> Changes in v4:
> - dumped clearing BSS before SPL board_init_f, only real bugfixes remain
>
> Changes in v3:
> - fixed summary ("stack" -> "heap")
> - enable CONFIG_SPL_CLEAR_BSS_F for socfpga_arria10 using full malloc
>   early in SPL
> - rebased
>
>  common/dlmalloc.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)

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Re: [U-Boot] Booting MX6 via Serial Download after DM conversion

2019-04-23 Thread Peng Fan
Hi Fabio

> -Original Message-
> From: Fabio Estevam [mailto:feste...@gmail.com]
> Sent: 2019年4月24日 10:01
> To: Peng Fan ; Abel Vesa 
> Cc: Stefano Babic ; Lukasz Majewski ;
> Michael Trimarchi ; dl-uboot-imx
> ; Jagan Teki ; Marcel
> Ziswiler ; U-Boot-Denx
> ; Adam Ford ; Ye Li
> ; Otavio Salvador 
> Subject: Re: Booting MX6 via Serial Download after DM conversion
> 
> Hi Peng and Abel,
> 
> On Mon, Apr 22, 2019 at 11:00 PM Peng Fan  wrote:
> 
> > Honestly I am not familiar with imx_usb, we use mfgtool previously and not
> uuu tool.
> 
> Is the UUU tool capable of loading SPL + u-boot-dtb.img generated from
> mainline U-Boot for mx6sabresd?

Not try this. 
uuu should support SPL file being loaded, then if SPL could runs into fastboot 
mode
to interactive with uuu, then u-boot-dtb.img could be loaded I think.

Regards,
Peng.

> 
> Thanks
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Re: [U-Boot] [PATCH 1/4] riscv: hart_lottery and available harts feature can be seletable

2019-04-23 Thread Rick Chen
Hi Bin

Bin Meng  於 2019年4月23日 週二 下午8:19寫道:
>
> On Tue, Apr 23, 2019 at 8:14 PM Bin Meng  wrote:
> >
> > Hi Rick,
> >
> > On Tue, Apr 23, 2019 at 1:47 PM Andes  wrote:
> > >
> > > From: Rick Chen 
> > >
> >
> > typo in the commit title: seletable -> selectable

OK

> >
> > > In smp flow this two features only can be enabled when U-Boot
> >
> > this->these

OK

> >
> > > boot from ram. It shall be disabled when U-Boot boot from flash.
> >
> > boot->boots

OK

> >
> > >
> > > Add CONFIG_HART_LOTTERY and CONFIG_AVAILABLE_HARTS to select
>
> BTW: is it possible to use a single option for such feature, like
> CONFIG_XIP? Basically these two options are used for the same reason.

Yes. This is my initial idea. But I worry the connection seem a little weak.
But if you say so, I will do it as you say.

Thanks
Rick

>
> > > this two features. Their default value will say YES for booting
> >
> > this->these
> >
> > > from ram.
>
> Regards,
> Bin
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Re: [U-Boot] Booting MX6 via Serial Download after DM conversion

2019-04-23 Thread Fabio Estevam
Hi Peng and Abel,

On Mon, Apr 22, 2019 at 11:00 PM Peng Fan  wrote:

> Honestly I am not familiar with imx_usb, we use mfgtool previously and not 
> uuu tool.

Is the UUU tool capable of loading SPL + u-boot-dtb.img generated from
mainline U-Boot for mx6sabresd?

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Re: [U-Boot] [PATCH 4/4] riscv: configs: AE350 will use OF_PRIOR_STAGE when boot from ram

2019-04-23 Thread Rick Chen
Hi Bin

Bin Meng  於 2019年4月23日 週二 下午8:14寫道:
>
> Hi Rick,
>
> On Tue, Apr 23, 2019 at 1:47 PM Andes  wrote:
> >
> > From: Rick Chen 
> >
>
> nits in the commit title: boot->booting

OK

>
> > When AE350 was booting from ram, use OF_PRIOR_STAGE instead
> > of OF_PRIOR_STAGE.
>
> This should be CONFIG_OF_BOARD

OK

Thanks
Rick

>
> >
> > Signed-off-by: Rick Chen 
> > Cc: Greentime Hu 
> > ---
> >  configs/ae350_rv32_defconfig | 2 +-
> >  configs/ae350_rv64_defconfig | 2 +-
> >  2 files changed, 2 insertions(+), 2 deletions(-)
> >
> > diff --git a/configs/ae350_rv32_defconfig b/configs/ae350_rv32_defconfig
> > index e13c7de..54b65f1 100644
> > --- a/configs/ae350_rv32_defconfig
> > +++ b/configs/ae350_rv32_defconfig
> > @@ -14,7 +14,7 @@ CONFIG_CMD_SF_TEST=y
> >  # CONFIG_CMD_SETEXPR is not set
> >  CONFIG_BOOTP_PREFER_SERVERIP=y
> >  CONFIG_CMD_CACHE=y
> > -CONFIG_OF_BOARD=y
> > +CONFIG_OF_PRIOR_STAGE=y
> >  CONFIG_DEFAULT_DEVICE_TREE="ae350_32"
> >  CONFIG_ENV_IS_IN_SPI_FLASH=y
> >  CONFIG_NET_RANDOM_ETHADDR=y
> > diff --git a/configs/ae350_rv64_defconfig b/configs/ae350_rv64_defconfig
> > index a41f918..0ff4de8 100644
> > --- a/configs/ae350_rv64_defconfig
> > +++ b/configs/ae350_rv64_defconfig
> > @@ -15,7 +15,7 @@ CONFIG_CMD_SF_TEST=y
> >  # CONFIG_CMD_SETEXPR is not set
> >  CONFIG_BOOTP_PREFER_SERVERIP=y
> >  CONFIG_CMD_CACHE=y
> > -CONFIG_OF_BOARD=y
> > +CONFIG_OF_PRIOR_STAGE=y
> >  CONFIG_DEFAULT_DEVICE_TREE="ae350_64"
> >  CONFIG_ENV_IS_IN_SPI_FLASH=y
> >  CONFIG_NET_RANDOM_ETHADDR=y
>
> Regards,
> Bin
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Re: [U-Boot] [PATCH 3/4] riscv: prior_stage_fdt_address only be used when OF_PRIOR_STAGE is enable

2019-04-23 Thread Rick Chen
Hi Bin

Bin Meng  於 2019年4月23日 週二 下午8:14寫道:
>
> Hi Rick,
>
> On Tue, Apr 23, 2019 at 1:47 PM Andes  wrote:
> >
> > From: Rick Chen 
> >
>
> commit title should read: prior_stage_fdt_address should only be used
> when OF_PRIOR_STAGE is enabled

OK

>
> > This patch will fix prior_stage_fdt_address write failure problem, when
> > AE350 was booting from flash.
> >
> > When AE350 was booting from falsh, prior_stage_fdt_address will be in
> > flash address, we shall avoid it to be written.
> >
> > Signed-off-by: Rick Chen 
> > Cc: Greentime Hu 
> > ---
> >  arch/riscv/cpu/start.S | 2 ++
> >  1 file changed, 2 insertions(+)
> >
> > diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
> > index d030d4a..0e672e0 100644
> > --- a/arch/riscv/cpu/start.S
> > +++ b/arch/riscv/cpu/start.S
> > @@ -111,7 +111,9 @@ call_board_init_f_0:
> > bneztp, secondary_hart_loop
> >  #endif
> >
> > +#  if CONFIG_IS_ENABLED(OF_PRIOR_STAGE)
> > la  t0, prior_stage_fdt_address
> > +#endif
>
> I think you should also surround the declaration of
> prior_stage_fdt_address in arch/riscv/cpu/cpu.c with OF_PRIOR_STAGE

OK
I will surround it.

Thanks for review
Rick

>
> > SREGs1, 0(t0)
> >
> > jal board_init_f_init_reserve
> > --
>
> Regards,
> Bin
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Re: [U-Boot] [PATCH 2/4] riscv: configs: Support AE350 SMP boot from flash flow

2019-04-23 Thread Rick Chen
Hi Bin

Bin Meng  於 2019年4月23日 週二 下午8:14寫道:
>
> Hi Rick,
>
> On Tue, Apr 23, 2019 at 1:47 PM Andes  wrote:
> >
> > From: Rick Chen 
>
> nits in the commit title: boot->booting

OK

>
> >
> > Add two defconfig to support AE350 SMP boot from flash
>
> boot->bootings

OK

>
> > by disable CONFIG_HART_LOTTERY and CONFIG_AVAILABLE_HARTS.
>
> disable->disabling

OK

>
> >
> > Signed-off-by: Rick Chen 
> > Cc: Greentime Hu 
> > ---
> >  configs/ae350_rv32_xip_defconfig | 37 +
> >  configs/ae350_rv64_xip_defconfig | 38 
> > ++
> >  2 files changed, 75 insertions(+)
> >  create mode 100644 configs/ae350_rv32_xip_defconfig
> >  create mode 100644 configs/ae350_rv64_xip_defconfig
> >
> > diff --git a/configs/ae350_rv32_xip_defconfig 
> > b/configs/ae350_rv32_xip_defconfig
> > new file mode 100644
> > index 000..1639367
> > --- /dev/null
> > +++ b/configs/ae350_rv32_xip_defconfig
> > @@ -0,0 +1,37 @@
> > +CONFIG_RISCV=y
> > +CONFIG_HART_LOTTERY=n
> > +CONFIG_AVAILABLE_HARTS=n
>
> I think this should be:
>
> # CONFIG_HART_LOTTERY is not set
> # CONFIG_AVAILABLE_HARTS is not set

OK

>
> > +CONFIG_SYS_TEXT_BASE=0x8000
> > +CONFIG_TARGET_AX25_AE350=y
> > +CONFIG_DISTRO_DEFAULTS=y
> > +CONFIG_NR_DRAM_BANKS=2
> > +CONFIG_FIT=y
> > +CONFIG_BOOTDELAY=3
> > +CONFIG_BOARD_EARLY_INIT_F=y
> > +CONFIG_SYS_PROMPT="RISC-V # "
> > +CONFIG_CMD_IMLS=y
> > +CONFIG_CMD_MMC=y
> > +CONFIG_CMD_SF=y
> > +CONFIG_CMD_SF_TEST=y
> > +# CONFIG_CMD_SETEXPR is not set
> > +CONFIG_BOOTP_PREFER_SERVERIP=y
> > +CONFIG_CMD_CACHE=y
> > +CONFIG_OF_BOARD=y
> > +CONFIG_DEFAULT_DEVICE_TREE="ae350_32"
> > +CONFIG_ENV_IS_IN_SPI_FLASH=y
> > +CONFIG_NET_RANDOM_ETHADDR=y
> > +CONFIG_MMC=y
> > +CONFIG_FTSDC010=y
> > +CONFIG_FTSDC010_SDIO=y
> > +CONFIG_MTD_NOR_FLASH=y
> > +CONFIG_FLASH_CFI_DRIVER=y
> > +CONFIG_CFI_FLASH=y
> > +CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
> > +CONFIG_SYS_FLASH_CFI=y
> > +CONFIG_SPI_FLASH=y
> > +CONFIG_SPI_FLASH_MACRONIX=y
> > +CONFIG_FTMAC100=y
> > +CONFIG_BAUDRATE=38400
> > +CONFIG_SYS_NS16550=y
> > +CONFIG_SPI=y
> > +CONFIG_ATCSPI200_SPI=y
> > diff --git a/configs/ae350_rv64_xip_defconfig 
> > b/configs/ae350_rv64_xip_defconfig
> > new file mode 100644
> > index 000..d6a502c
> > --- /dev/null
> > +++ b/configs/ae350_rv64_xip_defconfig
> > @@ -0,0 +1,38 @@
> > +CONFIG_RISCV=y
> > +CONFIG_HART_LOTTERY=n
> > +CONFIG_AVAILABLE_HARTS=n
>
> ditto

OK

>
> > +CONFIG_SYS_TEXT_BASE=0x8000
> > +CONFIG_TARGET_AX25_AE350=y
> > +CONFIG_ARCH_RV64I=y
> > +CONFIG_DISTRO_DEFAULTS=y
> > +CONFIG_NR_DRAM_BANKS=2
> > +CONFIG_FIT=y
> > +CONFIG_BOOTDELAY=3
> > +CONFIG_BOARD_EARLY_INIT_F=y
> > +CONFIG_SYS_PROMPT="RISC-V # "
> > +CONFIG_CMD_IMLS=y
> > +CONFIG_CMD_MMC=y
> > +CONFIG_CMD_SF=y
> > +CONFIG_CMD_SF_TEST=y
> > +# CONFIG_CMD_SETEXPR is not set
> > +CONFIG_BOOTP_PREFER_SERVERIP=y
> > +CONFIG_CMD_CACHE=y
> > +CONFIG_OF_BOARD=y
> > +CONFIG_DEFAULT_DEVICE_TREE="ae350_64"
> > +CONFIG_ENV_IS_IN_SPI_FLASH=y
> > +CONFIG_NET_RANDOM_ETHADDR=y
> > +CONFIG_MMC=y
> > +CONFIG_FTSDC010=y
> > +CONFIG_FTSDC010_SDIO=y
> > +CONFIG_MTD_NOR_FLASH=y
> > +CONFIG_FLASH_CFI_DRIVER=y
> > +CONFIG_CFI_FLASH=y
> > +CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
> > +CONFIG_SYS_FLASH_CFI=y
> > +CONFIG_SPI_FLASH=y
> > +CONFIG_SPI_FLASH_MACRONIX=y
> > +CONFIG_FTMAC100=y
> > +CONFIG_BAUDRATE=38400
> > +CONFIG_SYS_NS16550=y
> > +CONFIG_SPI=y
> > +CONFIG_ATCSPI200_SPI=y
>

Thanks for your review.
Rick

> Regards,
> Bin
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Re: [U-Boot] [PATCH v2] pinctrl: imx: Define imx6_pinctrl_soc_info in .data section

2019-04-23 Thread Peng Fan


> -Original Message-
> From: Lukasz Majewski [mailto:lu...@denx.de]
> Sent: 2019年4月23日 22:45
> To: Stefano Babic ; u-boot@lists.denx.de; Fabio Estevam
> ; Fabio Estevam ;
> dl-uboot-imx ; Jagan Teki
> ; Adam Ford 
> Cc: Lukasz Majewski ; Bin Meng ;
> Simon Glass 
> Subject: [PATCH v2] pinctrl: imx: Define imx6_pinctrl_soc_info in .data 
> section
> 
> This commit is necessary to be able to re-use the pinctrl code in early SPL to
> properly configure pins.
> 
> The problem is that those "static" structures (without explicit
> initialization) are placed in the SDRAM area, which corresponds to u-boot
> proper (not even SPL).
> Hence, when one wants to configure pins before relocation via DTS/DM, the
> board hangs (imx6q SoC powered one) as only OCRAM area is available
> (0x009x).
> 
> This commit prevents from this issue by moving the imx6_pinctrl_soc_info
> structure to data section (from BSS).
> 
> Signed-off-by: Lukasz Majewski 
> 
> ---
> 
> Changes in v2:
> - Use __section(".data") instead of rewritting the code to use calloc()
>   (less intrusive commit)
> 
>  drivers/pinctrl/nxp/pinctrl-imx6.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/pinctrl/nxp/pinctrl-imx6.c
> b/drivers/pinctrl/nxp/pinctrl-imx6.c
> index d7c95bb738..0c1e7a9c05 100644
> --- a/drivers/pinctrl/nxp/pinctrl-imx6.c
> +++ b/drivers/pinctrl/nxp/pinctrl-imx6.c
> @@ -10,7 +10,7 @@
> 
>  #include "pinctrl-imx.h"
> 
> -static struct imx_pinctrl_soc_info imx6_pinctrl_soc_info;
> +static struct imx_pinctrl_soc_info imx6_pinctrl_soc_info
> +__section(".data");
> 
>  /* FIXME Before reloaction, BSS is overlapped with DT area */  static struct
> imx_pinctrl_soc_info imx6ul_pinctrl_soc_info = {

Reviewed-by: Peng Fan 

> --
> 2.11.0

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Re: [U-Boot] [PATCH 0/4] AE350 support SMP boot from flash

2019-04-23 Thread Rick Chen
Hi Lukas

Auer, Lukas  於 2019年4月24日 週三 上午3:58寫道:
>
> Hi Rick,
>
> On Tue, 2019-04-23 at 13:42 +0800, Andes wrote:
> > From: Rick Chen 
> >
> > In current RISC-V SMP flow, AE350 will encounter the the write
> > failure problem since hart_lottery and available_harts_lock was
> > not in ram address but in flash address when booing from flash.
> >
> > This patch can help to fix the failure problem when AE350 was
> > booting from flash by disable this two features.
> >
>
> Can you describe the issue you are seeing a bit more. The write
> failures are both to variables in the .data section, which should be
> writable. Perhaps the write failures can be avoided by moving the .data
> section or just the variable to RAM?
>

When I compile AE350's CONFIG_SYS_TEXT_BASE=0x8000 which is spi flash base.
And burn u-boot.bin into AE350 spi flash. Power off / on, U-Boot will
run in XIP mode.
At this time prior_stage_fdt_address will be in flash address(0x8004e9e8)
So it is not writable.

8042:   16021563bneztp,81ac

8046:   0004f297auipc   t0,0x4f
804a:   9a22a283lw  t0,-1630(t0) #
8004e9e8 
804e:   0092a023sw  s1,0(t0)

Rick

> Thanks,
> Lukas
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Re: [U-Boot] EFIBootGuard for CIP and SecureBoot

2019-04-23 Thread daniel.sangorrin
Hello Francois, Jan, Christian, and all

Sorry for the late reply, I was waiting for the administrator of the Boot 
Architecture mailing list to accept my subscription request, but it seems it 
will take a bit more time. I will send this reply and hope it will not be 
blocked. I have also added the u-boot mailing list to Cc, as Tom suggested 
(although I'm not a member), the CIP mailing list, Jan Kiszka (one of the main 
developers of Efibootguard) and Christian (an expert in software updates).

Background: during the last Linaro connect in Bangkok I was told that Linaro 
Edge (LEDGE) were working on a secure software update mechanism based on UEFI 
capsules that would flash firmware updates from a UEFI application, instead of 
using a Linux agent such as SWUpdate. Then, I had an online meeting with 
Francois, director of LEDGE. I explained to Francois that in CIP we are using 
the Linux agent approach right now, and we are also considering the use of a 
UEFI application (Efibootguard) to arm a watchdog and deal with the 
state-machine variables (installed, testing, ok, failed..) needed for A/B 
software updates. Efibootguard sounds like an excellent place to collaborate 
with Linaro (particularly on the watchdog drivers front) because it does not 
strictly depend on where the firmware is flashed (UEFI capsule or Linux agent). 

> On Fri, Apr 19, 2019 at 12:48:51PM +0200, Francois Ozog wrote:
> > Hi Daniel,
> >
> > We will be conducting a UEFI gap analysis to support EFIBootGuard in U-Boot.
> >
> > As we are working on UEFI SecureBoot implementation in U-Boot, how do
> > you expect the boot process to be secured? Would U-Boot UEFI
> > SecureBoot verify EFIBootGuard signature and in turn EFIBootGuard will
> > check either grub or Linux signature?
> >
> > Please elaborate on your vision of a secured boot process.

Efibootguard is composed of two parts.
  - A UEFI application that can arm a watchdog and decide what environment 
(kernel, boot args, etc.) to use next depending on a set of variables (update 
status, highest revision, etc.) stored in FAT16 partitions.
  - A Linux application that can read and set those variables from Linux 
(similar to u-boot's fw_setenv). This functionality is also available in the 
form of a library.

As far as I know, there is no concept of "Secure Booting" in Efibootguard at 
the moment. Adding signature checks before booting into the selected kernel 
would be a possible solution. 

Thanks,
Daniel



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[U-Boot] [PATCH 3/4] warp7: configs: bl33: Tidy up OPTEE defines

2019-04-23 Thread Bryan O'Donoghue
When booting in BL33 mode i.e. with u-boot loaded by OP-TEE we get the
following print-out.

Board: WARP7 in secure mode OPTEE DRAM 0xa000-0xa000

This is incorrect the right range is 0x9e00-0xa000. This patch
fixes the defines on the warp7_bl33_defconfig file to tidy up the output.

Signed-off-by: Bryan O'Donoghue 
Cc: Fabio Estevam 
---
 configs/warp7_bl33_defconfig | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/configs/warp7_bl33_defconfig b/configs/warp7_bl33_defconfig
index 6eaf152bac..8cc622fe47 100644
--- a/configs/warp7_bl33_defconfig
+++ b/configs/warp7_bl33_defconfig
@@ -50,4 +50,6 @@ CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_USB_ETHER=y
 CONFIG_USB_ETH_CDC=y
 CONFIG_USBNET_HOST_ADDR="de:ad:be:af:00:00"
-CONFIG_OPTEE_TZDRAM_SIZE=0x200
+CONFIG_OPTEE=y
+CONFIG_OPTEE_TZDRAM_BASE=0x9e00
+CONFIG_OPTEE_TZDRAM_SIZE=0x0200
-- 
2.20.1

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[U-Boot] [PATCH 2/4] warp7: include: configs: Skip low-level init if BOOTM_OPTEE false

2019-04-23 Thread Bryan O'Donoghue
Commit c7b3a7ee5351 ("optee: adjust dependencies and default values for
dram") wants to skip low-level init of i.MX7 hardware in the case where
OP-TEE has already run and u-boot is being run as BL33 in normal world.

Currently we check for both #ifdef CONFIG_OPTEE_TZDRAM_SIZE and #ifndef
CONFIG_OPTEE to determine if lowlevel init should be skipped, however, in
order to ensure non-OPTEE users never see OPTEE related defines we cannot
rely on this method.

Fortunately we can use CONFIG_BOOTM_OPTEE for the same purpose.
CONFIG_BOOTM_OPTEE is only relevant if you want u-boot to load OP-TEE not
if u-boot has already been loaded by OP-TEE.

Signed-off-by: Bryan O'Donoghue 
Cc: Fabio Estevam 
Cc: Breno Lima 
Cc: Rui Miguel Silva 
---
 include/configs/warp7.h | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/include/configs/warp7.h b/include/configs/warp7.h
index 043f2861b6..458cb8fe10 100644
--- a/include/configs/warp7.h
+++ b/include/configs/warp7.h
@@ -18,11 +18,9 @@
  * launched by OPTEE, because of that we shall skip all the low level
  * initialization since it was already done by ATF or OPTEE
  */
-#ifdef CONFIG_OPTEE_TZDRAM_SIZE
-#ifndef CONFIG_OPTEE
+#ifndef CONFIG_BOOTM_OPTEE
 #define CONFIG_SKIP_LOWLEVEL_INIT
 #endif
-#endif
 
 #define CONFIG_MXC_UART_BASE   UART1_IPS_BASE_ADDR
 
-- 
2.20.1

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[U-Boot] [PATCH 4/4] MAINTAINERS: Update lib/optee with my details

2019-04-23 Thread Bryan O'Donoghue
Commit 32ce6179fb99 ("optee: Add lib entries for sharing OPTEE code across
ports") adds code into lib/optee but neglects to update MAINTAINERS to make
me buggable for questions and maintenance.

Signed-off-by: Bryan O'Donoghue 
Suggested-by: Jens Wiklander 
---
 MAINTAINERS | 5 +
 1 file changed, 5 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index aa4b3bc650..16ea180fe2 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -754,6 +754,11 @@ F: drivers/tee/
 F: include/tee.h
 F: include/tee/
 
+TEE-lib
+M: Bryan O'Donoghue 
+S: Maintained
+F: lib/optee
+
 UBI
 M: Kyungmin Park 
 M: Heiko Schocher 
-- 
2.20.1

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[U-Boot] [PATCH 0/4] Tidy up some dangling OP-TEE gotchas

2019-04-23 Thread Bryan O'Donoghue
Rober P Day rightly pointed out that some odd OP-TEE specific defines were
appearing in his defconfig, despite not having CONFIG_OPTEE=y set in his
defconfig.

Looking into this with a small bit of restructure we can fix this corner
case.

- Make sure OP-TEE CONFIG options only appear when you are compiling for
  OPTEE
- Fix WaRP7 BL33 so that the low-level init skipping routines can tolerate
  the afore mentioned change.
- Update MAINTAINERS with my own details so that questions pertaining to
  lib/optee comes my way.

Bryan O'Donoghue (4):
  optee: Make TZDRAM config options contingent on CONFIG_OPTEE
  warp7: include: configs: Skip low-level init if BOOTM_OPTEE false
  warp7: configs: bl33: Tidy up OPTEE defines
  MAINTAINERS: Update lib/optee with my details

 MAINTAINERS  | 5 +
 configs/warp7_bl33_defconfig | 4 +++-
 include/configs/warp7.h  | 4 +---
 lib/optee/Kconfig| 2 ++
 4 files changed, 11 insertions(+), 4 deletions(-)

-- 
2.20.1

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[U-Boot] [PATCH 1/4] optee: Make TZDRAM config options contingent on CONFIG_OPTEE

2019-04-23 Thread Bryan O'Donoghue
Commit c7b3a7ee5351 ("optee: adjust dependencies and default values for
dram") makes the TZDRAM defines for OPTEE show up for all configs as a
side-effect. While not harmful its not what we really want.

This patch makes the following defines contingent on CONFIG_OPTEE=y

CONFIG_OPTEE_TZDRAM_BASE
CONFIG_OPTEE_TZDRAM_SIZE

Rightly, if you don't have CONFIG_OPTEE=y you don't care about the above
two defines.

Signed-off-by: Bryan O'Donoghue 
Cc: Rui Miguel Silva 
---
 lib/optee/Kconfig | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/lib/optee/Kconfig b/lib/optee/Kconfig
index 3773d89c31..c398f9b953 100644
--- a/lib/optee/Kconfig
+++ b/lib/optee/Kconfig
@@ -17,6 +17,7 @@ config OPTEE_LOAD_ADDR
 config OPTEE_TZDRAM_SIZE
hex "Amount of Trust-Zone RAM for the OPTEE image"
default 0x000
+   depends on OPTEE
help
  The size of pre-allocated Trust Zone DRAM to allocate for the OPTEE
  runtime.
@@ -24,6 +25,7 @@ config OPTEE_TZDRAM_SIZE
 config OPTEE_TZDRAM_BASE
hex "Base address of Trust-Zone RAM for the OPTEE image"
default 0x
+   depends on OPTEE
help
  The base address of pre-allocated Trust Zone DRAM for
  the OPTEE runtime.
-- 
2.20.1

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Re: [U-Boot] [PATCH] RISCV: image: Add booti support.

2019-04-23 Thread Marek Vasut
On 4/24/19 1:36 AM, Atish Patra wrote:
> This patch adds booti support for RISC-V Linux kernel. The existing
> bootm method will also continue to work as it is.
> 
> It depends on the following kernel patch which adds the header to the
> flat Image.
> 
> https://patchwork.kernel.org/patch/10913869/
> 
> Tested on HiFive Unleashed and QEMU.
> Currently, compressed images such as Image.gz are not supported.
> 
> Signed-off-by: Atish Patra 
> ---
>  arch/riscv/lib/Makefile |  1 +
>  arch/riscv/lib/image.c  | 60 +
>  cmd/Kconfig |  2 +-
>  cmd/booti.c |  8 --
>  4 files changed, 68 insertions(+), 3 deletions(-)
>  create mode 100644 arch/riscv/lib/image.c
> 
> diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile
> index 1c332db436a9..6ae6ebbeafda 100644
> --- a/arch/riscv/lib/Makefile
> +++ b/arch/riscv/lib/Makefile
> @@ -7,6 +7,7 @@
>  # Rick Chen, Andes Technology Corporation 
>  
>  obj-$(CONFIG_CMD_BOOTM) += bootm.o
> +obj-$(CONFIG_CMD_BOOTI) += bootm.o image.o
>  obj-$(CONFIG_CMD_GO) += boot.o
>  obj-y+= cache.o
>  obj-$(CONFIG_RISCV_RDTIME) += rdtime.o
> diff --git a/arch/riscv/lib/image.c b/arch/riscv/lib/image.c
> new file mode 100644
> index ..99c2e31066a3
> --- /dev/null
> +++ b/arch/riscv/lib/image.c
> @@ -0,0 +1,60 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (C) 2019 Western Digital Corporation or its affiliates.
> + * Authors:
> + *   Atish Patra 
> + * Based on arm/lib/image.c
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +/* ASCII version of "RISCV" defined in Linux kernel */
> +#define LINUX_RISCV_IMAGE_MAGIC 0x5643534952
> +
> +struct linux_image_h {
> + uint32_tcode0;  /* Executable code */
> + uint32_tcode1;  /* Executable code */
> + uint64_ttext_offset;/* Image load offset */
> + uint64_timage_size; /* Effective Image size */
> + uint64_tres1;   /* reserved */
> + uint64_tmagic;  /* Magic number */
> + uint32_tres2;   /* reserved */
> + uint32_tres3;   /* reserved */
> +};
> +
> +int booti_setup(ulong image, ulong *relocated_addr, ulong *size,
> + bool force_reloc)
> +{
> + struct linux_image_h *lhdr;
> + uint64_t dst;
> + uint64_t image_size, text_offset;
> +
> + *relocated_addr = image;

You're setting this here to $image, but you're overriding this at the
end of the function again with gd->ram_base + text_offset , is that
intended?

> + lhdr = (struct linux_image_h *)map_sysmem(image, 0);
> +
> + if (lhdr->magic != LINUX_RISCV_IMAGE_MAGIC) {
> + puts("Bad Linux RISCV Image magic!\n");
> + return 1;
> + }
> +
> + if (lhdr->image_size != 0) {
> + image_size = lhdr->image_size;
> + text_offset = lhdr->text_offset;

Maybe you can use lhdr->* directly and get rid of these local variables ?

> + } else {
> + puts("Image lacks image_size field, Error!!\n");

error, lowercase . And use one exclamation mark.

> + return 1;

Use errno.h return code instead.

> + }
> + *size = image_size;
> + dst = gd->ram_base;
> + *relocated_addr = dst + text_offset;

Use gd->ram_base instead of $dst and drop $dst altogether.

> +
[...]

-- 
Best regards,
Marek Vasut
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[U-Boot] [PATCH] RISCV: image: Add booti support.

2019-04-23 Thread Atish Patra
This patch adds booti support for RISC-V Linux kernel. The existing
bootm method will also continue to work as it is.

It depends on the following kernel patch which adds the header to the
flat Image.

https://patchwork.kernel.org/patch/10913869/

Tested on HiFive Unleashed and QEMU.
Currently, compressed images such as Image.gz are not supported.

Signed-off-by: Atish Patra 
---
 arch/riscv/lib/Makefile |  1 +
 arch/riscv/lib/image.c  | 60 +
 cmd/Kconfig |  2 +-
 cmd/booti.c |  8 --
 4 files changed, 68 insertions(+), 3 deletions(-)
 create mode 100644 arch/riscv/lib/image.c

diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile
index 1c332db436a9..6ae6ebbeafda 100644
--- a/arch/riscv/lib/Makefile
+++ b/arch/riscv/lib/Makefile
@@ -7,6 +7,7 @@
 # Rick Chen, Andes Technology Corporation 
 
 obj-$(CONFIG_CMD_BOOTM) += bootm.o
+obj-$(CONFIG_CMD_BOOTI) += bootm.o image.o
 obj-$(CONFIG_CMD_GO) += boot.o
 obj-y  += cache.o
 obj-$(CONFIG_RISCV_RDTIME) += rdtime.o
diff --git a/arch/riscv/lib/image.c b/arch/riscv/lib/image.c
new file mode 100644
index ..99c2e31066a3
--- /dev/null
+++ b/arch/riscv/lib/image.c
@@ -0,0 +1,60 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Western Digital Corporation or its affiliates.
+ * Authors:
+ * Atish Patra 
+ * Based on arm/lib/image.c
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* ASCII version of "RISCV" defined in Linux kernel */
+#define LINUX_RISCV_IMAGE_MAGIC 0x5643534952
+
+struct linux_image_h {
+   uint32_tcode0;  /* Executable code */
+   uint32_tcode1;  /* Executable code */
+   uint64_ttext_offset;/* Image load offset */
+   uint64_timage_size; /* Effective Image size */
+   uint64_tres1;   /* reserved */
+   uint64_tmagic;  /* Magic number */
+   uint32_tres2;   /* reserved */
+   uint32_tres3;   /* reserved */
+};
+
+int booti_setup(ulong image, ulong *relocated_addr, ulong *size,
+   bool force_reloc)
+{
+   struct linux_image_h *lhdr;
+   uint64_t dst;
+   uint64_t image_size, text_offset;
+
+   *relocated_addr = image;
+
+   lhdr = (struct linux_image_h *)map_sysmem(image, 0);
+
+   if (lhdr->magic != LINUX_RISCV_IMAGE_MAGIC) {
+   puts("Bad Linux RISCV Image magic!\n");
+   return 1;
+   }
+
+   if (lhdr->image_size != 0) {
+   image_size = lhdr->image_size;
+   text_offset = lhdr->text_offset;
+   } else {
+   puts("Image lacks image_size field, Error!!\n");
+   return 1;
+   }
+   *size = image_size;
+   dst = gd->ram_base;
+   *relocated_addr = dst + text_offset;
+
+   unmap_sysmem(lhdr);
+
+   return 0;
+}
diff --git a/cmd/Kconfig b/cmd/Kconfig
index 2bdbfcb3d091..d427b66d3714 100644
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -212,7 +212,7 @@ config CMD_BOOTZ
 
 config CMD_BOOTI
bool "booti"
-   depends on ARM64
+   depends on ARM64 || RISCV
default y
help
  Boot an AArch64 Linux Kernel image from memory.
diff --git a/cmd/booti.c b/cmd/booti.c
index 04353b68eccc..c22ba9bae2e4 100644
--- a/cmd/booti.c
+++ b/cmd/booti.c
@@ -77,7 +77,11 @@ int do_booti(cmd_tbl_t *cmdtp, int flag, int argc, char * 
const argv[])
bootm_disable_interrupts();
 
images.os.os = IH_OS_LINUX;
+   #ifdef CONFIG_RISCV_SMODE
+   images.os.arch = IH_ARCH_RISCV;
+   #elif CONFIG_ARM64
images.os.arch = IH_ARCH_ARM64;
+   #endif
ret = do_bootm_states(cmdtp, flag, argc, argv,
 #ifdef CONFIG_SYS_BOOT_RAMDISK_HIGH
  BOOTM_STATE_RAMDISK |
@@ -92,7 +96,7 @@ int do_booti(cmd_tbl_t *cmdtp, int flag, int argc, char * 
const argv[])
 #ifdef CONFIG_SYS_LONGHELP
 static char booti_help_text[] =
"[addr [initrd[:size]] [fdt]]\n"
-   "- boot arm64 Linux Image stored in memory\n"
+   "- boot arm64/riscv Linux Image stored in memory\n"
"\tThe argument 'initrd' is optional and specifies the address\n"
"\tof an initrd in memory. The optional parameter ':size' allows\n"
"\tspecifying the size of a RAW initrd.\n"
@@ -107,5 +111,5 @@ static char booti_help_text[] =
 
 U_BOOT_CMD(
booti,  CONFIG_SYS_MAXARGS, 1,  do_booti,
-   "boot arm64 Linux Image image from memory", booti_help_text
+   "boot arm64/riscv Linux Image image from memory", booti_help_text
 );
-- 
2.21.0

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Re: [U-Boot] [PATCHv5 0/6] dm: cache: add dm cache driver

2019-04-23 Thread Tom Rini
On Tue, Apr 23, 2019 at 04:55:00PM -0500, Dinh Nguyen wrote:
> Hi,
> 
> This is V4 of the series to add a UCLASS_CACHE dm driver to handling
> the configuration of cache settings. Place this new driver under
> /drivers/cache. In this initial revision, the driver is only configuring
> what I think are essential cache settings. The more comprehensive cache
> settings can be done in the OS.
> 
> Diffs from v4:
> - Fix compile error found in sandbox_cache.c

Thanks.  I'd greatly appreciate it if you can throw this whole series at
travis (or just do a world build locally) and report back that
everything is OK now.

-- 
Tom


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[U-Boot] [PATCHv5 4/6] dm: cache: add the pl310 cache controller driver

2019-04-23 Thread Dinh Nguyen
Add a PL310 cache controller driver that is usually found on
ARMv7(32-bit) devices. The driver configures the cache settings that can
be found in the device tree files.

This initial revision only configures basic settings(data & instruction
prefetch, shared-override, data & tag latency). I believe these are the
settings that affect performance the most. Comprehensive settings can be
done by the OS.

Reviewed-by: Simon Glass 
Signed-off-by: Dinh Nguyen 
---
v4: no change
v3: Add Reviewed-by and fix nits
v2: split out patch and address comments from Simon Glass
---
 drivers/cache/Kconfig  |  9 +
 drivers/cache/Makefile |  1 +
 drivers/cache/cache-l2x0.c | 76 ++
 3 files changed, 86 insertions(+)
 create mode 100644 drivers/cache/cache-l2x0.c

diff --git a/drivers/cache/Kconfig b/drivers/cache/Kconfig
index 8b7c9c7f9f..24def7ac0f 100644
--- a/drivers/cache/Kconfig
+++ b/drivers/cache/Kconfig
@@ -13,4 +13,13 @@ config CACHE
  is usually located on the same chip. This uclass can be used for
  configuring settings that be found from a device tree file.
 
+config L2X0_CACHE
+   tristate "PL310 cache driver"
+   select CACHE
+   depends on ARM
+   help
+ This driver is for the PL310 cache controller commonly found on
+ ARMv7(32-bit) devices. The driver configures the cache settings
+ found in the device tree.
+
 endmenu
diff --git a/drivers/cache/Makefile b/drivers/cache/Makefile
index 2ba68060c1..9deb961d91 100644
--- a/drivers/cache/Makefile
+++ b/drivers/cache/Makefile
@@ -1,3 +1,4 @@
 
 obj-$(CONFIG_CACHE) += cache-uclass.o
 obj-$(CONFIG_SANDBOX) += sandbox_cache.o
+obj-$(CONFIG_L2X0_CACHE) += cache-l2x0.o
diff --git a/drivers/cache/cache-l2x0.c b/drivers/cache/cache-l2x0.c
new file mode 100644
index 00..67c752d076
--- /dev/null
+++ b/drivers/cache/cache-l2x0.c
@@ -0,0 +1,76 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 Intel Corporation 
+ */
+#include 
+#include 
+#include 
+
+#include 
+#include 
+
+static void l2c310_of_parse_and_init(struct udevice *dev)
+{
+   u32 tag[3] = { 0, 0, 0 };
+   u32 saved_reg, prefetch;
+   struct pl310_regs *regs = (struct pl310_regs *)dev_read_addr(dev);
+
+   /* Disable the L2 Cache */
+   clrbits_le32(>pl310_ctrl, L2X0_CTRL_EN);
+
+   saved_reg = readl(>pl310_aux_ctrl);
+   if (!dev_read_u32(dev, "prefetch-data", )) {
+   if (prefetch)
+   saved_reg |= L310_AUX_CTRL_DATA_PREFETCH_MASK;
+   else
+   saved_reg &= ~L310_AUX_CTRL_DATA_PREFETCH_MASK;
+   }
+
+   if (!dev_read_u32(dev, "prefetch-instr", )) {
+   if (prefetch)
+   saved_reg |= L310_AUX_CTRL_INST_PREFETCH_MASK;
+   else
+   saved_reg &= ~L310_AUX_CTRL_INST_PREFETCH_MASK;
+   }
+
+   saved_reg |= dev_read_bool(dev, "arm,shared-override");
+   writel(saved_reg, >pl310_aux_ctrl);
+
+   saved_reg = readl(>pl310_tag_latency_ctrl);
+   if (!dev_read_u32_array(dev, "arm,tag-latency", tag, 3))
+   saved_reg |= L310_LATENCY_CTRL_RD(tag[0] - 1) |
+L310_LATENCY_CTRL_WR(tag[1] - 1) |
+L310_LATENCY_CTRL_SETUP(tag[2] - 1);
+   writel(saved_reg, >pl310_tag_latency_ctrl);
+
+   saved_reg = readl(>pl310_data_latency_ctrl);
+   if (!dev_read_u32_array(dev, "arm,data-latency", tag, 3))
+   saved_reg |= L310_LATENCY_CTRL_RD(tag[0] - 1) |
+L310_LATENCY_CTRL_WR(tag[1] - 1) |
+L310_LATENCY_CTRL_SETUP(tag[2] - 1);
+   writel(saved_reg, >pl310_data_latency_ctrl);
+
+   /* Enable the L2 cache */
+   setbits_le32(>pl310_ctrl, L2X0_CTRL_EN);
+}
+
+static int l2x0_probe(struct udevice *dev)
+{
+   l2c310_of_parse_and_init(dev);
+
+   return 0;
+}
+
+
+static const struct udevice_id l2x0_ids[] = {
+   { .compatible = "arm,pl310-cache" },
+   {}
+};
+
+U_BOOT_DRIVER(pl310_cache) = {
+   .name   = "pl310_cache",
+   .id = UCLASS_CACHE,
+   .of_match = l2x0_ids,
+   .probe  = l2x0_probe,
+   .flags  = DM_FLAG_PRE_RELOC,
+};
-- 
2.20.0

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[U-Boot] [PATCHv5 6/6] configs: socfpga: add imply pl310 cache controller

2019-04-23 Thread Dinh Nguyen
Select the PL310 UCLASS_CACHE driver for SoCFPGA.

Reviewed-by: Marek Vasut 
Reviewed-by: Simon Glass 
Signed-off-by: Dinh Nguyen 
---
 arch/arm/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index f58f8fb235..f5132d8174 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -845,6 +845,7 @@ config ARCH_SOCFPGA
imply SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE
imply SPL_SPI_FLASH_SUPPORT
imply SPL_SPI_SUPPORT
+   imply L2X0_CACHE
 
 config ARCH_SUNXI
bool "Support sunxi (Allwinner) SoCs"
-- 
2.20.0

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[U-Boot] [PATCHv5 3/6] dm: cache: Create a uclass for cache

2019-04-23 Thread Dinh Nguyen
The cache UCLASS will be used for configure settings that can be found
in a CPU's L2 cache controller.

Add a uclass and a test for cache.

Reviewed-by: Simon Glass 
Signed-off-by: Dinh Nguyen 
---
v5: fix compile error for sandbox_cache.c
v4: re-order includes and add Reviewed-by:
v3: Add cache_get_info() to check for non-zero value
Add comments to cache_info struct
v2: separate out uclass patch from driver and add test
---
 drivers/Kconfig   |  2 ++
 drivers/Makefile  |  1 +
 drivers/cache/Kconfig | 16 +++
 drivers/cache/Makefile|  3 +++
 drivers/cache/cache-uclass.c  | 24 ++
 drivers/cache/sandbox_cache.c | 34 +++
 include/cache.h   | 38 +++
 include/dm/uclass-id.h|  1 +
 test/dm/cache.c   | 20 ++
 9 files changed, 139 insertions(+)
 create mode 100644 drivers/cache/Kconfig
 create mode 100644 drivers/cache/Makefile
 create mode 100644 drivers/cache/cache-uclass.c
 create mode 100644 drivers/cache/sandbox_cache.c
 create mode 100644 include/cache.h
 create mode 100644 test/dm/cache.c

diff --git a/drivers/Kconfig b/drivers/Kconfig
index e6702eced4..96ff4f566a 100644
--- a/drivers/Kconfig
+++ b/drivers/Kconfig
@@ -14,6 +14,8 @@ source "drivers/block/Kconfig"
 
 source "drivers/bootcount/Kconfig"
 
+source "drivers/cache/Kconfig"
+
 source "drivers/clk/Kconfig"
 
 source "drivers/cpu/Kconfig"
diff --git a/drivers/Makefile b/drivers/Makefile
index a7bba3ed56..0a00096332 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -77,6 +77,7 @@ obj-$(CONFIG_BIOSEMU) += bios_emulator/
 obj-y += block/
 obj-y += board/
 obj-$(CONFIG_BOOTCOUNT_LIMIT) += bootcount/
+obj-y += cache/
 obj-$(CONFIG_CPU) += cpu/
 obj-y += crypto/
 obj-$(CONFIG_FASTBOOT) += fastboot/
diff --git a/drivers/cache/Kconfig b/drivers/cache/Kconfig
new file mode 100644
index 00..8b7c9c7f9f
--- /dev/null
+++ b/drivers/cache/Kconfig
@@ -0,0 +1,16 @@
+#
+# Cache controllers
+#
+
+menu "Cache Controller drivers"
+
+config CACHE
+   bool "Enable Driver Model for Cache controllers"
+   depends on DM
+   help
+ Enable driver model for cache controllers that are found on
+ most CPU's. Cache is memory that the CPU can access directly and
+ is usually located on the same chip. This uclass can be used for
+ configuring settings that be found from a device tree file.
+
+endmenu
diff --git a/drivers/cache/Makefile b/drivers/cache/Makefile
new file mode 100644
index 00..2ba68060c1
--- /dev/null
+++ b/drivers/cache/Makefile
@@ -0,0 +1,3 @@
+
+obj-$(CONFIG_CACHE) += cache-uclass.o
+obj-$(CONFIG_SANDBOX) += sandbox_cache.o
diff --git a/drivers/cache/cache-uclass.c b/drivers/cache/cache-uclass.c
new file mode 100644
index 00..97ce0249a4
--- /dev/null
+++ b/drivers/cache/cache-uclass.c
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Intel Corporation 
+ */
+
+#include 
+#include 
+#include 
+
+int cache_get_info(struct udevice *dev, struct cache_info *info)
+{
+   struct cache_ops *ops = cache_get_ops(dev);
+
+   if (!ops->get_info)
+   return -ENOSYS;
+
+   return ops->get_info(dev, info);
+}
+
+UCLASS_DRIVER(cache) = {
+   .id = UCLASS_CACHE,
+   .name   = "cache",
+   .post_bind  = dm_scan_fdt_dev,
+};
diff --git a/drivers/cache/sandbox_cache.c b/drivers/cache/sandbox_cache.c
new file mode 100644
index 00..14cc6b0c0a
--- /dev/null
+++ b/drivers/cache/sandbox_cache.c
@@ -0,0 +1,34 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 Intel Corporation 
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static int sandbox_get_info(struct udevice *dev, struct cache_info *info)
+{
+   info->base = 0x11223344;
+
+   return 0;
+}
+
+static const struct cache_ops sandbox_cache_ops = {
+   .get_info   = sandbox_get_info,
+};
+
+static const struct udevice_id sandbox_cache_ids[] = {
+   { .compatible = "sandbox,cache" },
+   { }
+};
+
+U_BOOT_DRIVER(cache_sandbox) = {
+   .name   = "cache_sandbox",
+   .id = UCLASS_CACHE,
+   .of_match   = sandbox_cache_ids,
+   .ops= _cache_ops,
+};
diff --git a/include/cache.h b/include/cache.h
new file mode 100644
index 00..c6334ca27f
--- /dev/null
+++ b/include/cache.h
@@ -0,0 +1,38 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 Intel Corporation 
+ */
+
+#ifndef __CACHE_H
+#define __CACHE_H
+
+/*
+ * Structure for the cache controller
+ */
+struct cache_info {
+   phys_addr_t base; /* Base physical address of cache device. */
+};
+
+struct cache_ops {
+   /**
+* get_info() - Get basic cache info
+*
+* @dev:Device to check (UCLASS_CACHE)
+* @info:   Place to put info
+* @return 

[U-Boot] [PATCHv5 5/6] ARM: socfpga: use the pl310 driver to configure the cache

2019-04-23 Thread Dinh Nguyen
Find the UCLASS_CACHE driver to configure the cache controller's
settings.

Reviewed-by: Marek Vasut 
Reviewed-by: Simon Glass 
Signed-off-by: Dinh Nguyen 
---
 arch/arm/mach-socfpga/misc.c | 16 +++-
 1 file changed, 3 insertions(+), 13 deletions(-)

diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index ec8339e045..34d8c4c51b 100644
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -59,20 +59,10 @@ void enable_caches(void)
 #ifdef CONFIG_SYS_L2_PL310
 void v7_outer_cache_enable(void)
 {
-   /* Disable the L2 cache */
-   clrbits_le32(>pl310_ctrl, L2X0_CTRL_EN);
-
-   writel(0x0, >pl310_tag_latency_ctrl);
-   writel(0x10, >pl310_data_latency_ctrl);
-
-   /* enable BRESP, instruction and data prefetch, full line of zeroes */
-   setbits_le32(>pl310_aux_ctrl,
-L310_AUX_CTRL_DATA_PREFETCH_MASK |
-L310_AUX_CTRL_INST_PREFETCH_MASK |
-L310_SHARED_ATT_OVERRIDE_ENABLE);
+   struct udevice *dev;
 
-   /* Enable the L2 cache */
-   setbits_le32(>pl310_ctrl, L2X0_CTRL_EN);
+   if (uclass_get_device(UCLASS_CACHE, 0, ))
+   pr_err("cache controller driver NOT found!\n");
 }
 
 void v7_outer_cache_disable(void)
-- 
2.20.0

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[U-Boot] [PATCHv5 2/6] ARM: pl310: Add macro's for handling tag and data latency mask

2019-04-23 Thread Dinh Nguyen
Add the PL310 macros for latency control setup, read and write bits.

Reviewed-by: Marek Vasut 
Reviewed-by: Simon Glass 
Signed-off-by: Dinh Nguyen 
---
 arch/arm/include/asm/pl310.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm/include/asm/pl310.h b/arch/arm/include/asm/pl310.h
index b83978b1cc..f69e9e45f8 100644
--- a/arch/arm/include/asm/pl310.h
+++ b/arch/arm/include/asm/pl310.h
@@ -18,6 +18,9 @@
 #define L310_SHARED_ATT_OVERRIDE_ENABLE(1 << 22)
 #define L310_AUX_CTRL_DATA_PREFETCH_MASK   (1 << 28)
 #define L310_AUX_CTRL_INST_PREFETCH_MASK   (1 << 29)
+#define L310_LATENCY_CTRL_SETUP(n) ((n) << 0)
+#define L310_LATENCY_CTRL_RD(n)((n) << 4)
+#define L310_LATENCY_CTRL_WR(n)((n) << 8)
 
 #define L2X0_CACHE_ID_PART_MASK (0xf << 6)
 #define L2X0_CACHE_ID_PART_L310 (3 << 6)
-- 
2.20.0

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[U-Boot] [PATCHv5 1/6] Documentation: dts: Add pl310 cache controller dts documentation

2019-04-23 Thread Dinh Nguyen
Linux commit 8ecd7f5970c5 ("ARM: 8483/1: Documentation: l2c: Rename
l2cc to l2c2x0")

Linux docs:
Documentation/devicetree/bindings/arm/l2c2x0.txt

Copied from Linux kernel v5.0.

"The documentation in the l2cc.txt is specific to the L2 cache
controllers L2C210/L2C220/L2C310 (also known as PL210/PL220/PL310
and variants) and not generic as the file name implies. It's not
valid for integrated L2 controllers as found in e.g.
Cortex-A15/A7/A57/A53."

Reviewed-by: Simon Glass 
Signed-off-by: Dinh Nguyen 
---
 .../devicetree/bindings/arm/l2c2x0.txt| 114 ++
 1 file changed, 114 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/l2c2x0.txt

diff --git a/Documentation/devicetree/bindings/arm/l2c2x0.txt 
b/Documentation/devicetree/bindings/arm/l2c2x0.txt
new file mode 100644
index 00..fbe6cb21f4
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/l2c2x0.txt
@@ -0,0 +1,114 @@
+* ARM L2 Cache Controller
+
+ARM cores often have a separate L2C210/L2C220/L2C310 (also known as 
PL210/PL220/
+PL310 and variants) based level 2 cache controller. All these various 
implementations
+of the L2 cache controller have compatible programming models (Note 1).
+Some of the properties that are just prefixed "cache-*" are taken from section
+3.7.3 of the Devicetree Specification which can be found at:
+https://www.devicetree.org/specifications/
+
+The ARM L2 cache representation in the device tree should be done as follows:
+
+Required properties:
+
+- compatible : should be one of:
+  "arm,pl310-cache"
+  "arm,l220-cache"
+  "arm,l210-cache"
+  "bcm,bcm11351-a2-pl310-cache": DEPRECATED by "brcm,bcm11351-a2-pl310-cache"
+  "brcm,bcm11351-a2-pl310-cache": For Broadcom bcm11351 chipset where an
+ offset needs to be added to the address before passing down to the L2
+ cache controller
+  "marvell,aurora-system-cache": Marvell Controller designed to be
+ compatible with the ARM one, with system cache mode (meaning
+ maintenance operations on L1 are broadcasted to the L2 and L2
+ performs the same operation).
+  "marvell,aurora-outer-cache": Marvell Controller designed to be
+ compatible with the ARM one with outer cache mode.
+  "marvell,tauros3-cache": Marvell Tauros3 cache controller, compatible
+ with arm,pl310-cache controller.
+- cache-unified : Specifies the cache is a unified cache.
+- cache-level : Should be set to 2 for a level 2 cache.
+- reg : Physical base address and size of cache controller's memory mapped
+  registers.
+
+Optional properties:
+
+- arm,data-latency : Cycles of latency for Data RAM accesses. Specifies 3 
cells of
+  read, write and setup latencies. Minimum valid values are 1. Controllers
+  without setup latency control should use a value of 0.
+- arm,tag-latency : Cycles of latency for Tag RAM accesses. Specifies 3 cells 
of
+  read, write and setup latencies. Controllers without setup latency control
+  should use 0. Controllers without separate read and write Tag RAM latency
+  values should only use the first cell.
+- arm,dirty-latency : Cycles of latency for Dirty RAMs. This is a single cell.
+- arm,filter-ranges :  Starting address and length of window to
+  filter. Addresses in the filter window are directed to the M1 port. Other
+  addresses will go to the M0 port.
+- arm,io-coherent : indicates that the system is operating in an hardware
+  I/O coherent mode. Valid only when the arm,pl310-cache compatible
+  string is used.
+- interrupts : 1 combined interrupt.
+- cache-size : specifies the size in bytes of the cache
+- cache-sets : specifies the number of associativity sets of the cache
+- cache-block-size : specifies the size in bytes of a cache block
+- cache-line-size : specifies the size in bytes of a line in the cache,
+  if this is not specified, the line size is assumed to be equal to the
+  cache block size
+- cache-id-part: cache id part number to be used if it is not present
+  on hardware
+- wt-override: If present then L2 is forced to Write through mode
+- arm,double-linefill : Override double linefill enable setting. Enable if
+  non-zero, disable if zero.
+- arm,double-linefill-incr : Override double linefill on INCR read. Enable
+  if non-zero, disable if zero.
+- arm,double-linefill-wrap : Override double linefill on WRAP read. Enable
+  if non-zero, disable if zero.
+- arm,prefetch-drop : Override prefetch drop enable setting. Enable if 
non-zero,
+  disable if zero.
+- arm,prefetch-offset : Override prefetch offset value. Valid values are
+  0-7, 15, 23, and 31.
+- arm,shared-override : The default behavior of the L220 or PL310 cache
+  controllers with respect to the shareable attribute is to transform "normal
+  memory non-cacheable transactions" into "cacheable no allocate" (for reads)
+  or "write through no write allocate" (for writes).
+  On systems where this may cause DMA buffer corruption, this property must be
+  specified to indicate that such transforms are precluded.
+- 

[U-Boot] [PATCHv5 0/6] dm: cache: add dm cache driver

2019-04-23 Thread Dinh Nguyen
Hi,

This is V4 of the series to add a UCLASS_CACHE dm driver to handling
the configuration of cache settings. Place this new driver under
/drivers/cache. In this initial revision, the driver is only configuring
what I think are essential cache settings. The more comprehensive cache
settings can be done in the OS.

Diffs from v4:
- Fix compile error found in sandbox_cache.c


Dinh Nguyen (6):
  Documentation: dts: Add pl310 cache controller dts documentation
  ARM: pl310: Add macro's for handling tag and data latency mask
  dm: cache: Create a uclass for cache
  dm: cache: add the pl310 cache controller driver
  ARM: socfpga: use the pl310 driver to configure the cache
  configs: socfpga: add imply pl310 cache controller

 .../devicetree/bindings/arm/l2c2x0.txt| 114 ++
 arch/arm/Kconfig  |   1 +
 arch/arm/include/asm/pl310.h  |   3 +
 arch/arm/mach-socfpga/misc.c  |  16 +--
 drivers/Kconfig   |   2 +
 drivers/Makefile  |   1 +
 drivers/cache/Kconfig |  25 
 drivers/cache/Makefile|   4 +
 drivers/cache/cache-l2x0.c|  76 
 drivers/cache/cache-uclass.c  |  24 
 drivers/cache/sandbox_cache.c |  34 ++
 include/cache.h   |  38 ++
 include/dm/uclass-id.h|   1 +
 test/dm/cache.c   |  20 +++
 14 files changed, 346 insertions(+), 13 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/l2c2x0.txt
 create mode 100644 drivers/cache/Kconfig
 create mode 100644 drivers/cache/Makefile
 create mode 100644 drivers/cache/cache-l2x0.c
 create mode 100644 drivers/cache/cache-uclass.c
 create mode 100644 drivers/cache/sandbox_cache.c
 create mode 100644 include/cache.h
 create mode 100644 test/dm/cache.c

-- 
2.20.0

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Re: [U-Boot] [PATCH v4 0/4] arm: socfpga: clean up socfpga_common.h

2019-04-23 Thread Marek Vasut
On 4/23/19 10:51 PM, Simon Goldschmidt wrote:
> 
> 
> Marek Vasut mailto:ma...@denx.de>> schrieb am Di., 23.
> Apr. 2019, 22:43:
> 
> On 4/23/19 9:36 PM, Simon Goldschmidt wrote:
> > This series cleans up the include/configs/socfpga_common.h file a bit.
> >
> > It removes some defines that are used nowhere and cleans up some
> > leftovers after various subsystems have been converted to use DM.
> >
> > Changes in v4:
> > - fix DM_I2C case: don't call i2c_set_bus_num() since this is
> >   done in cmd/eeprom already
> >
> > Changes in v3:
> > - changed commit message: s/defines/macros and comments/
> >
> > Changes in v2:
> > - added (this) patch to move socfpga_vining to DM_I2C
> > - remove even more outdated things
> > - added (this) patch with further cleanups to the socfpga board config
> >   files
> >
> > Simon Goldschmidt (4):
> >   arm: socfpga: move vining_fpga to DM_I2C
> >   arm: socfpga: clean up socfpga_common.h
> >   arm: socfpga: remove CONFIG_SYS_BOOTMAPSZ
> >   arm: socfpga: clean up board config files
> >
> >  board/samtec/vining_fpga/socfpga.c       |  9 +---
> >  configs/socfpga_vining_fpga_defconfig    |  8 ++-
> >  include/configs/socfpga_arria10_socdk.h  |  6 ---
> >  include/configs/socfpga_arria5_socdk.h   |  2 -
> >  include/configs/socfpga_common.h         | 68
> 
> >  include/configs/socfpga_cyclone5_socdk.h |  2 -
> >  include/configs/socfpga_de0_nano_soc.h   |  2 -
> >  include/configs/socfpga_de10_nano.h      |  2 -
> >  include/configs/socfpga_de1_soc.h        |  2 -
> >  include/configs/socfpga_is1.h            |  2 -
> >  include/configs/socfpga_sockit.h         |  2 -
> >  include/configs/socfpga_socrates.h       |  2 -
> >  include/configs/socfpga_sr1500.h         | 11 
> >  include/configs/socfpga_vining_fpga.h    | 18 ---
> >  14 files changed, 8 insertions(+), 128 deletions(-)
> 
> Neither of these apply to u-boot-socfpga/master :-(
> 
> 
> Sorry for the confusion, these are again meant to apply on top of other
> patches in a PR. Sent to the ML for reference, mainly, as the diffs are
> tiny.
> 
> How should I mark such patches to prevent such misunderstandings in the
> future?

Just send an incremental patch on top of u-boot-socfpga/master please .
If you want me to squash it into another patch, note it somewhere around
the diffstat.

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Re: [U-Boot] [U-Boot, PATCHv4, 3/6] dm: cache: Create a uclass for cache

2019-04-23 Thread Dinh Nguyen


On 4/22/19 12:48 PM, Tom Rini wrote:
> On Mon, Apr 01, 2019 at 05:32:17PM -0500, Dinh Nguyen wrote:
> 
>> The cache UCLASS will be used for configure settings that can be found
>> in a CPU's L2 cache controller.
>>
>> Add a uclass and a test for cache.
>>
>> Reviewed-by: Simon Glass 
>> Signed-off-by: Dinh Nguyen 
>> ---
>> v4: re-order includes and add Reviewed-by:
>> v3: Add cache_get_info() to check for non-zero value
>> Add comments to cache_info struct
>> v2: separate out uclass patch from driver and add test
> 
> NAK:
>sandbox:  +   tools-only
> +(tools-only) In file included from drivers/cache/sandbox_cache.c:6:0:
> +(tools-only) include/cache.h:13:2: error: unknown type name 'phys_addr_t'
> +(tools-only)   phys_addr_t base; /* Base physical address of cache device. */
> +(tools-only)   ^~~
> +(tools-only)   int (*get_info)(struct udevice *dev, struct cache_info *info);
> +(tools-only)  ^~~
> +(tools-only)  int cache_get_info(struct udevice *dev, struct cache_info 
> *info);
> +(tools-only)^~~
> +(tools-only)   .get_info = sandbox_get_info,
> +(tools-only)   ^~~~
> +(tools-only) drivers/cache/sandbox_cache.c:21:14: note: (near initialization 
> for 'sandbox_cach
> e_ops.get_info')
> +(tools-only) make[3]: *** [drivers/cache/sandbox_cache.o] Error 1
> +(tools-only) make[2]: *** [drivers/cache] Error 2
> +(tools-only) make[1]: *** [drivers] Error 2
> +(tools-only) make: *** [sub-make] Error 2
> w+(tools-only) include/cache.h:24:25: warning: 'struct udevice' declared 
> inside parameter list will not be visible outside of this definition or 
> declaration
> w+(tools-only) include/cache.h:36:27: warning: 'struct udevice' declared 
> inside parameter list will not be visible outside of this definition or 
> declaration
> w+(tools-only) drivers/cache/sandbox_cache.c:21:14: warning: initialization 
> from incompatible pointer type [-Wincompatible-pointer-types]
> 

I apologize for that! V5 is enroute and should be error free.

Dinh



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Re: [U-Boot] [PATCH v4 0/4] arm: socfpga: clean up socfpga_common.h

2019-04-23 Thread Simon Goldschmidt
Marek Vasut  schrieb am Di., 23. Apr. 2019, 22:43:

> On 4/23/19 9:36 PM, Simon Goldschmidt wrote:
> > This series cleans up the include/configs/socfpga_common.h file a bit.
> >
> > It removes some defines that are used nowhere and cleans up some
> > leftovers after various subsystems have been converted to use DM.
> >
> > Changes in v4:
> > - fix DM_I2C case: don't call i2c_set_bus_num() since this is
> >   done in cmd/eeprom already
> >
> > Changes in v3:
> > - changed commit message: s/defines/macros and comments/
> >
> > Changes in v2:
> > - added (this) patch to move socfpga_vining to DM_I2C
> > - remove even more outdated things
> > - added (this) patch with further cleanups to the socfpga board config
> >   files
> >
> > Simon Goldschmidt (4):
> >   arm: socfpga: move vining_fpga to DM_I2C
> >   arm: socfpga: clean up socfpga_common.h
> >   arm: socfpga: remove CONFIG_SYS_BOOTMAPSZ
> >   arm: socfpga: clean up board config files
> >
> >  board/samtec/vining_fpga/socfpga.c   |  9 +---
> >  configs/socfpga_vining_fpga_defconfig|  8 ++-
> >  include/configs/socfpga_arria10_socdk.h  |  6 ---
> >  include/configs/socfpga_arria5_socdk.h   |  2 -
> >  include/configs/socfpga_common.h | 68 
> >  include/configs/socfpga_cyclone5_socdk.h |  2 -
> >  include/configs/socfpga_de0_nano_soc.h   |  2 -
> >  include/configs/socfpga_de10_nano.h  |  2 -
> >  include/configs/socfpga_de1_soc.h|  2 -
> >  include/configs/socfpga_is1.h|  2 -
> >  include/configs/socfpga_sockit.h |  2 -
> >  include/configs/socfpga_socrates.h   |  2 -
> >  include/configs/socfpga_sr1500.h | 11 
> >  include/configs/socfpga_vining_fpga.h| 18 ---
> >  14 files changed, 8 insertions(+), 128 deletions(-)
>
> Neither of these apply to u-boot-socfpga/master :-(
>

Sorry for the confusion, these are again meant to apply on top of other
patches in a PR. Sent to the ML for reference, mainly, as the diffs are
tiny.

How should I mark such patches to prevent such misunderstandings in the
future?

Regards,
Simon
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Re: [U-Boot] [PATCH v4 0/4] arm: socfpga: clean up socfpga_common.h

2019-04-23 Thread Marek Vasut
On 4/23/19 9:36 PM, Simon Goldschmidt wrote:
> This series cleans up the include/configs/socfpga_common.h file a bit.
> 
> It removes some defines that are used nowhere and cleans up some
> leftovers after various subsystems have been converted to use DM.
> 
> Changes in v4:
> - fix DM_I2C case: don't call i2c_set_bus_num() since this is
>   done in cmd/eeprom already
> 
> Changes in v3:
> - changed commit message: s/defines/macros and comments/
> 
> Changes in v2:
> - added (this) patch to move socfpga_vining to DM_I2C
> - remove even more outdated things
> - added (this) patch with further cleanups to the socfpga board config
>   files
> 
> Simon Goldschmidt (4):
>   arm: socfpga: move vining_fpga to DM_I2C
>   arm: socfpga: clean up socfpga_common.h
>   arm: socfpga: remove CONFIG_SYS_BOOTMAPSZ
>   arm: socfpga: clean up board config files
> 
>  board/samtec/vining_fpga/socfpga.c   |  9 +---
>  configs/socfpga_vining_fpga_defconfig|  8 ++-
>  include/configs/socfpga_arria10_socdk.h  |  6 ---
>  include/configs/socfpga_arria5_socdk.h   |  2 -
>  include/configs/socfpga_common.h | 68 
>  include/configs/socfpga_cyclone5_socdk.h |  2 -
>  include/configs/socfpga_de0_nano_soc.h   |  2 -
>  include/configs/socfpga_de10_nano.h  |  2 -
>  include/configs/socfpga_de1_soc.h|  2 -
>  include/configs/socfpga_is1.h|  2 -
>  include/configs/socfpga_sockit.h |  2 -
>  include/configs/socfpga_socrates.h   |  2 -
>  include/configs/socfpga_sr1500.h | 11 
>  include/configs/socfpga_vining_fpga.h| 18 ---
>  14 files changed, 8 insertions(+), 128 deletions(-)

Neither of these apply to u-boot-socfpga/master :-(

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Re: [U-Boot] [PATCH v3 1/2] eeprom: fix DM_I2C support without CONFIG_SYS_I2C_EEPROM_BUS

2019-04-23 Thread Lukasz Majewski
Hi Simon,

> The current device model enabled eeprom code only works if
> CONFIG_SYS_I2C_EEPROM_BUS is set.
> 
> This patch makes it work without that define so that the bus
> number passed to 'eeprom_init' is used.

Reviewed-by: Lukasz Majewski 

> 
> Signed-off-by: Simon Goldschmidt 
> Reviewed-by: Heiko Schocher 
> ---
> 
> Changes in v3:
> - use eeprom_init() to set CONFIG_SYS_I2C_EEPROM_BUS, not
>   i2c_set_bus_num to make things work with CONFIG_DM_I2C
> 
> Changes in v2: None
> 
>  cmd/eeprom.c | 23 +++
>  1 file changed, 15 insertions(+), 8 deletions(-)
> 
> diff --git a/cmd/eeprom.c b/cmd/eeprom.c
> index 6c29b33ba3..7b1f81477f 100644
> --- a/cmd/eeprom.c
> +++ b/cmd/eeprom.c
> @@ -59,6 +59,10 @@
>  #endif
>  #endif
>  
> +#if defined(CONFIG_DM_I2C)
> +int eeprom_i2c_bus;
> +#endif
> +
>  __weak int eeprom_write_enable(unsigned dev_addr, int state)
>  {
>   return 0;
> @@ -67,7 +71,9 @@ __weak int eeprom_write_enable(unsigned dev_addr,
> int state) void eeprom_init(int bus)
>  {
>   /* I2C EEPROM */
> -#if defined(CONFIG_SYS_I2C)
> +#if defined(CONFIG_DM_I2C)
> + eeprom_i2c_bus = bus;
> +#elif defined(CONFIG_SYS_I2C)
>   if (bus >= 0)
>   i2c_set_bus_num(bus);
>   i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
> @@ -124,14 +130,14 @@ static int eeprom_rw_block(unsigned offset,
> uchar *addr, unsigned alen, {
>   int ret = 0;
>  
> -#if defined(CONFIG_DM_I2C) && defined(CONFIG_SYS_I2C_EEPROM_BUS)
> +#if defined(CONFIG_DM_I2C)
>   struct udevice *dev;
>  
> - ret = i2c_get_chip_for_busnum(CONFIG_SYS_I2C_EEPROM_BUS,
> addr[0],
> + ret = i2c_get_chip_for_busnum(eeprom_i2c_bus, addr[0],
> alen - 1, );
>   if (ret) {
>   printf("%s: Cannot find udev for a bus %d\n",
> __func__,
> -CONFIG_SYS_I2C_EEPROM_BUS);
> +eeprom_i2c_bus);
>   return CMD_RET_FAILURE;
>   }
>  
> @@ -141,15 +147,12 @@ static int eeprom_rw_block(unsigned offset,
> uchar *addr, unsigned alen, ret = dm_i2c_write(dev, offset, buffer,
> len); 
>  #else /* Non DM I2C support - will be removed */
> -#if defined(CONFIG_SYS_I2C_EEPROM_BUS)
> - i2c_set_bus_num(CONFIG_SYS_I2C_EEPROM_BUS);
> -#endif
>  
>   if (read)
>   ret = i2c_read(addr[0], offset, alen - 1, buffer,
> len); else
>   ret = i2c_write(addr[0], offset, alen - 1, buffer,
> len); -#endif /* CONFIG_DM_I2C && CONFIG_SYS_I2C_EEPROM_BUS */
> +#endif /* CONFIG_DM_I2C */
>   if (ret)
>   ret = CMD_RET_FAILURE;
>  
> @@ -164,6 +167,10 @@ static int eeprom_rw(unsigned dev_addr, unsigned
> offset, uchar *buffer, int rcode = 0;
>   uchar addr[3];
>  
> +#if defined(CONFIG_SYS_I2C_EEPROM_BUS)
> + eeprom_init(CONFIG_SYS_I2C_EEPROM_BUS);
> +#endif
> +
>   while (offset < end) {
>   alen = eeprom_addr(dev_addr, offset, addr);
>  




Best regards,

Lukasz Majewski

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Re: [U-Boot] [PATCH 0/4] AE350 support SMP boot from flash

2019-04-23 Thread Auer, Lukas
Hi Rick,

On Tue, 2019-04-23 at 13:42 +0800, Andes wrote:
> From: Rick Chen 
> 
> In current RISC-V SMP flow, AE350 will encounter the the write
> failure problem since hart_lottery and available_harts_lock was
> not in ram address but in flash address when booing from flash.
> 
> This patch can help to fix the failure problem when AE350 was
> booting from flash by disable this two features.
> 

Can you describe the issue you are seeing a bit more. The write
failures are both to variables in the .data section, which should be
writable. Perhaps the write failures can be avoided by moving the .data
section or just the variable to RAM?

Thanks,
Lukas
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[U-Boot] [PATCH v4 2/4] arm: socfpga: clean up socfpga_common.h

2019-04-23 Thread Simon Goldschmidt
Remove outdated macros and comments (not used any more, outdated due to
DM conversion) from socfpga_common.h.

Signed-off-by: Simon Goldschmidt 
---

Changes in v4: None
Changes in v3:
- changed commit message: s/defines/macros and comments/

Changes in v2:
- remove even more outdated things

 include/configs/socfpga_common.h | 40 
 1 file changed, 40 deletions(-)

diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index a65fc804e3..5b5e5f5d43 100644
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -72,29 +72,12 @@
 #define CONFIG_SYS_BARGSIZECONFIG_SYS_CBSIZE
/* Boot argument buffer size */
 
-#ifndef CONFIG_SYS_HOSTNAME
-#define CONFIG_SYS_HOSTNAMECONFIG_SYS_BOARD
-#endif
-
 /*
  * Cache
  */
 #define CONFIG_SYS_L2_PL310
 #define CONFIG_SYS_PL310_BASE  SOCFPGA_MPUL2_ADDRESS
 
-/*
- * EPCS/EPCQx1 Serial Flash Controller
- */
-#ifdef CONFIG_ALTERA_SPI
-/*
- * The base address is configurable in QSys, each board must specify the
- * base address based on it's particular FPGA configuration. Please note
- * that the address here is incremented by  0x400  from the Base address
- * selected in QSys, since the SPI registers are at offset +0x400.
- * #define CONFIG_SYS_SPI_BASE 0xff240400
- */
-#endif
-
 /*
  * Ethernet on SoC (EMAC)
  */
@@ -162,15 +145,6 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
 #define CONFIG_CQSPI_REF_CLK   cm_get_qspi_controller_clk_hz()
 #endif
 
-/*
- * Designware SPI support
- */
-
-/*
- * Serial Driver
- */
-#define CONFIG_SYS_NS16550_SERIAL
-
 /*
  * USB
  */
@@ -206,20 +180,6 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
 #define CONFIG_ENV_SECT_SIZE   (64 * 1024)
 #endif
 
-/*
- * mtd partitioning for serial NOR flash
- *
- * device nor0 , # parts = 6
- * #: namesizeoffset  mask_flags
- * 0: u-boot  0x0010  0x  0
- * 1: env10x0004  0x0010  0
- * 2: env20x0004  0x0014  0
- * 3: UBI 0x03e8  0x0018  0
- * 4: boot0x00e8  0x0018  0
- * 5: rootfs  0x0100  0x0100  0
- *
- */
-
 /*
  * SPL
  *
-- 
2.17.1

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[U-Boot] [PATCH v4 4/4] arm: socfpga: clean up board config files

2019-04-23 Thread Simon Goldschmidt
Remove outdated defines (not used any more, outdated due to DM
conversion) from various socfpga files in include/config.

Signed-off-by: Simon Goldschmidt 
Acked-by: Marek Vasut 
---

Changes in v4: None
Changes in v3: None
Changes in v2:
- added (this) patch with further cleanups to the socfpga board config
  files

 include/configs/socfpga_arria10_socdk.h  |  6 --
 include/configs/socfpga_arria5_socdk.h   |  2 --
 include/configs/socfpga_cyclone5_socdk.h |  2 --
 include/configs/socfpga_de0_nano_soc.h   |  2 --
 include/configs/socfpga_de10_nano.h  |  2 --
 include/configs/socfpga_de1_soc.h|  2 --
 include/configs/socfpga_is1.h|  2 --
 include/configs/socfpga_sockit.h |  2 --
 include/configs/socfpga_socrates.h   |  2 --
 include/configs/socfpga_sr1500.h | 11 ---
 include/configs/socfpga_vining_fpga.h|  9 -
 11 files changed, 42 deletions(-)

diff --git a/include/configs/socfpga_arria10_socdk.h 
b/include/configs/socfpga_arria10_socdk.h
index 0f116fbf2d..92630c5e6e 100644
--- a/include/configs/socfpga_arria10_socdk.h
+++ b/include/configs/socfpga_arria10_socdk.h
@@ -19,12 +19,6 @@
 /* Memory configurations  */
 #define PHYS_SDRAM_1_SIZE  0x4000
 
-/* Ethernet on SoC (EMAC) */
-
-/*
- * U-Boot environment configurations
- */
-
 /*
  * Serial / UART configurations
  */
diff --git a/include/configs/socfpga_arria5_socdk.h 
b/include/configs/socfpga_arria5_socdk.h
index 24fcdd8b5a..af6137aeb1 100644
--- a/include/configs/socfpga_arria5_socdk.h
+++ b/include/configs/socfpga_arria5_socdk.h
@@ -14,8 +14,6 @@
 #define CONFIG_LOADADDR0x0100
 #define CONFIG_SYS_LOAD_ADDR   CONFIG_LOADADDR
 
-/* Ethernet on SoC (EMAC) */
-
 /* The rest of the configuration is shared */
 #include 
 
diff --git a/include/configs/socfpga_cyclone5_socdk.h 
b/include/configs/socfpga_cyclone5_socdk.h
index 18da8496ef..028db2a09e 100644
--- a/include/configs/socfpga_cyclone5_socdk.h
+++ b/include/configs/socfpga_cyclone5_socdk.h
@@ -14,8 +14,6 @@
 #define CONFIG_LOADADDR0x0100
 #define CONFIG_SYS_LOAD_ADDR   CONFIG_LOADADDR
 
-/* Ethernet on SoC (EMAC) */
-
 /* The rest of the configuration is shared */
 #include 
 
diff --git a/include/configs/socfpga_de0_nano_soc.h 
b/include/configs/socfpga_de0_nano_soc.h
index d3224d5bd3..21108e3447 100644
--- a/include/configs/socfpga_de0_nano_soc.h
+++ b/include/configs/socfpga_de0_nano_soc.h
@@ -14,8 +14,6 @@
 #define CONFIG_LOADADDR0x0100
 #define CONFIG_SYS_LOAD_ADDR   CONFIG_LOADADDR
 
-/* Ethernet on SoC (EMAC) */
-
 /* The rest of the configuration is shared */
 #include 
 
diff --git a/include/configs/socfpga_de10_nano.h 
b/include/configs/socfpga_de10_nano.h
index 2fcabff8af..d85f98fbd4 100644
--- a/include/configs/socfpga_de10_nano.h
+++ b/include/configs/socfpga_de10_nano.h
@@ -14,8 +14,6 @@
 #define CONFIG_LOADADDR0x0100
 #define CONFIG_SYS_LOAD_ADDR   CONFIG_LOADADDR
 
-/* Ethernet on SoC (EMAC) */
-
 /* The rest of the configuration is shared */
 #include 
 
diff --git a/include/configs/socfpga_de1_soc.h 
b/include/configs/socfpga_de1_soc.h
index f37099c58f..9919d292dc 100644
--- a/include/configs/socfpga_de1_soc.h
+++ b/include/configs/socfpga_de1_soc.h
@@ -14,8 +14,6 @@
 #define CONFIG_LOADADDR0x0100
 #define CONFIG_SYS_LOAD_ADDR   CONFIG_LOADADDR
 
-/* Ethernet on SoC (EMAC) */
-
 /* The rest of the configuration is shared */
 #include 
 
diff --git a/include/configs/socfpga_is1.h b/include/configs/socfpga_is1.h
index c233c208a5..c4da5947f3 100644
--- a/include/configs/socfpga_is1.h
+++ b/include/configs/socfpga_is1.h
@@ -19,8 +19,6 @@
 /* Ethernet on SoC (EMAC) */
 #if defined(CONFIG_CMD_NET)
 #define CONFIG_ARP_TIMEOUT 500UL
-
-/* PHY */
 #endif
 
 /* The rest of the configuration is shared */
diff --git a/include/configs/socfpga_sockit.h b/include/configs/socfpga_sockit.h
index 3a7f354914..97249a 100644
--- a/include/configs/socfpga_sockit.h
+++ b/include/configs/socfpga_sockit.h
@@ -14,8 +14,6 @@
 #define CONFIG_LOADADDR0x0100
 #define CONFIG_SYS_LOAD_ADDR   CONFIG_LOADADDR
 
-/* Ethernet on SoC (EMAC) */
-
 /* The rest of the configuration is shared */
 #include 
 
diff --git a/include/configs/socfpga_socrates.h 
b/include/configs/socfpga_socrates.h
index f0d9347891..7faea150a9 100644
--- a/include/configs/socfpga_socrates.h
+++ b/include/configs/socfpga_socrates.h
@@ -14,8 +14,6 @@
 #define CONFIG_LOADADDR0x0100
 #define CONFIG_SYS_LOAD_ADDR   CONFIG_LOADADDR
 
-/* Ethernet on SoC (EMAC) */
-
 /* The rest of the configuration is shared */
 #include 
 
diff --git a/include/configs/socfpga_sr1500.h b/include/configs/socfpga_sr1500.h
index b6a98611c0..3a8ccc3021 100644
--- a/include/configs/socfpga_sr1500.h
+++ b/include/configs/socfpga_sr1500.h
@@ -19,8 +19,6 @@
 /* The PHY is autodetected, so no MII PHY address is needed here */
 #define 

[U-Boot] [PATCH v4 3/4] arm: socfpga: remove CONFIG_SYS_BOOTMAPSZ

2019-04-23 Thread Simon Goldschmidt
socfpga_common.h defines CONFIG_SYS_BOOTMAPSZ to 64 MiB.

Since having this define overrides the 'bootm_size' env variable for
the whole socfpga platform, let's remove this define from socfpga_common.h
and instead rely on the 'bootm_size' env variable (which is initialized
to 160 MiB in the same file's default env). This gives users the
chance to override it in their own environment.

Signed-off-by: Simon Goldschmidt 
Acked-by: Marek Vasut 
---

Changes in v4: None
Changes in v3: None
Changes in v2: None

 include/configs/socfpga_common.h | 2 --
 1 file changed, 2 deletions(-)

diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index 5b5e5f5d43..5eccb01d1d 100644
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -10,8 +10,6 @@
  */
 #define CONFIG_CLOCKS
 
-#define CONFIG_SYS_BOOTMAPSZ   (64 * 1024 * 1024)
-
 #define CONFIG_TIMESTAMP   /* Print image info with timestamp */
 
 /*
-- 
2.17.1

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[U-Boot] [PATCH v4 1/4] arm: socfpga: move vining_fpga to DM_I2C

2019-04-23 Thread Simon Goldschmidt
All socfpga boards except for vining_fpga use DM_I2C. Enable
DM_I2C for this board and set the EEPROM defines via Kconfig
(enabling CONFIG_I2C_EEPROM from MISC).

Signed-off-by: Simon Goldschmidt 
---

Changes in v4:
- fix DM_I2C case: don't call i2c_set_bus_num() since this is
  done in cmd/eeprom already

Changes in v3: None
Changes in v2:
- added (this) patch to move socfpga_vining to DM_I2C

 board/samtec/vining_fpga/socfpga.c|  9 +
 configs/socfpga_vining_fpga_defconfig |  8 +++-
 include/configs/socfpga_common.h  | 26 --
 include/configs/socfpga_vining_fpga.h |  9 -
 4 files changed, 8 insertions(+), 44 deletions(-)

diff --git a/board/samtec/vining_fpga/socfpga.c 
b/board/samtec/vining_fpga/socfpga.c
index d99aac6828..efc8ddf162 100644
--- a/board/samtec/vining_fpga/socfpga.c
+++ b/board/samtec/vining_fpga/socfpga.c
@@ -52,14 +52,7 @@ int misc_init_r(void)
u32 serial;
int ret;
 
-   /* EEPROM is at bus 0. */
-   ret = i2c_set_bus_num(0);
-   if (ret) {
-   puts("Cannot select EEPROM I2C bus.\n");
-   return 0;
-   }
-
-   /* EEPROM is at address 0x50. */
+   /* EEPROM is at address 0x50 (at bus CONFIG_SYS_EEPROM_BUS_NUM). */
ret = eeprom_read(0x50, 0, data, sizeof(data));
if (ret) {
puts("Cannot read I2C EEPROM.\n");
diff --git a/configs/socfpga_vining_fpga_defconfig 
b/configs/socfpga_vining_fpga_defconfig
index 7b47b111b7..4a7f775337 100644
--- a/configs/socfpga_vining_fpga_defconfig
+++ b/configs/socfpga_vining_fpga_defconfig
@@ -16,8 +16,8 @@ CONFIG_VERSION_VARIABLE=y
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_SPI_LOAD=y
 CONFIG_CMD_ASKENV=y
-CONFIG_CMD_GREPENV=y
 CONFIG_CMD_EEPROM=y
+CONFIG_CMD_GREPENV=y
 CONFIG_CMD_DFU=y
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
@@ -44,6 +44,7 @@ CONFIG_DFU_RAM=y
 CONFIG_DFU_SF=y
 CONFIG_DM_GPIO=y
 CONFIG_DWAPB_GPIO=y
+CONFIG_DM_I2C=y
 CONFIG_LED_STATUS=y
 CONFIG_LED_STATUS_GPIO=y
 CONFIG_LED_STATUS0=y
@@ -55,6 +56,11 @@ CONFIG_LED_STATUS_BIT2=54
 CONFIG_LED_STATUS3=y
 CONFIG_LED_STATUS_BIT3=65
 CONFIG_LED_STATUS_CMD=y
+CONFIG_MISC=y
+CONFIG_I2C_EEPROM=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x50
+CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=70
 CONFIG_DM_MMC=y
 CONFIG_MMC_DW=y
 CONFIG_MTD_DEVICE=y
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index a501b5209f..a65fc804e3 100644
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -149,32 +149,6 @@
 #define CONFIG_SYS_NAND_DATA_BASE  SOCFPGA_NANDDATA_ADDRESS
 #endif
 
-/*
- * I2C support
- */
-#ifndef CONFIG_DM_I2C
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_BASESOCFPGA_I2C0_ADDRESS
-#define CONFIG_SYS_I2C_BASE1   SOCFPGA_I2C1_ADDRESS
-#define CONFIG_SYS_I2C_BASE2   SOCFPGA_I2C2_ADDRESS
-#define CONFIG_SYS_I2C_BASE3   SOCFPGA_I2C3_ADDRESS
-/* Using standard mode which the speed up to 100Kb/s */
-#define CONFIG_SYS_I2C_SPEED   10
-#define CONFIG_SYS_I2C_SPEED1  10
-#define CONFIG_SYS_I2C_SPEED2  10
-#define CONFIG_SYS_I2C_SPEED3  10
-/* Address of device when used as slave */
-#define CONFIG_SYS_I2C_SLAVE   0x02
-#define CONFIG_SYS_I2C_SLAVE1  0x02
-#define CONFIG_SYS_I2C_SLAVE2  0x02
-#define CONFIG_SYS_I2C_SLAVE3  0x02
-#ifndef __ASSEMBLY__
-/* Clock supplied to I2C controller in unit of MHz */
-unsigned int cm_get_l4_sp_clk_hz(void);
-#define IC_CLK (cm_get_l4_sp_clk_hz() / 100)
-#endif
-#endif /* CONFIG_DM_I2C */
-
 /*
  * QSPI support
  */
diff --git a/include/configs/socfpga_vining_fpga.h 
b/include/configs/socfpga_vining_fpga.h
index 5517ed722d..0e547a1295 100644
--- a/include/configs/socfpga_vining_fpga.h
+++ b/include/configs/socfpga_vining_fpga.h
@@ -16,15 +16,6 @@
 #define CONFIG_LOADADDR0x0100
 #define CONFIG_SYS_LOAD_ADDR   CONFIG_LOADADDR
 
-/* I2C EEPROM */
-#ifdef CONFIG_CMD_EEPROM
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_I2C_EEPROM_BUS  0
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS  3
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS  70
-#endif
-
 /*
  * Status LEDs:
  *   0 ... Top Green
-- 
2.17.1

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[U-Boot] [PATCH v4 0/4] arm: socfpga: clean up socfpga_common.h

2019-04-23 Thread Simon Goldschmidt
This series cleans up the include/configs/socfpga_common.h file a bit.

It removes some defines that are used nowhere and cleans up some
leftovers after various subsystems have been converted to use DM.

Changes in v4:
- fix DM_I2C case: don't call i2c_set_bus_num() since this is
  done in cmd/eeprom already

Changes in v3:
- changed commit message: s/defines/macros and comments/

Changes in v2:
- added (this) patch to move socfpga_vining to DM_I2C
- remove even more outdated things
- added (this) patch with further cleanups to the socfpga board config
  files

Simon Goldschmidt (4):
  arm: socfpga: move vining_fpga to DM_I2C
  arm: socfpga: clean up socfpga_common.h
  arm: socfpga: remove CONFIG_SYS_BOOTMAPSZ
  arm: socfpga: clean up board config files

 board/samtec/vining_fpga/socfpga.c   |  9 +---
 configs/socfpga_vining_fpga_defconfig|  8 ++-
 include/configs/socfpga_arria10_socdk.h  |  6 ---
 include/configs/socfpga_arria5_socdk.h   |  2 -
 include/configs/socfpga_common.h | 68 
 include/configs/socfpga_cyclone5_socdk.h |  2 -
 include/configs/socfpga_de0_nano_soc.h   |  2 -
 include/configs/socfpga_de10_nano.h  |  2 -
 include/configs/socfpga_de1_soc.h|  2 -
 include/configs/socfpga_is1.h|  2 -
 include/configs/socfpga_sockit.h |  2 -
 include/configs/socfpga_socrates.h   |  2 -
 include/configs/socfpga_sr1500.h | 11 
 include/configs/socfpga_vining_fpga.h| 18 ---
 14 files changed, 8 insertions(+), 128 deletions(-)

-- 
2.17.1

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[U-Boot] [PATCH v3 2/2] Revert "cmd: Kconfig: Do not include EEPROM if DM_I2C is used without DM_I2C_COMPAT"

2019-04-23 Thread Simon Goldschmidt
This reverts commit 65a97e7fcf54feb7c4ebe1aee8a572830af4cf51.

The 'eeprom' command has been converted to work with DM_I2C in a patch
submitted around the same time as this commit:
commit 0c07a9b4078d ("eeprom: Add device model based I2C support to eeprom 
command")

Signed-off-by: Simon Goldschmidt 
Reviewed-by: Heiko Schocher 
Reviewed-by: Simon Glass 
---

Changes in v3: None
Changes in v2:
- added patch to fix DM_I2C eeprom code to work without
  CONFIG_SYS_I2C_EEPROM_BUS

 cmd/Kconfig | 1 -
 1 file changed, 1 deletion(-)

diff --git a/cmd/Kconfig b/cmd/Kconfig
index 2bdbfcb3d0..87012670e0 100644
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -455,7 +455,6 @@ config CRC32_VERIFY
 
 config CMD_EEPROM
bool "eeprom - EEPROM subsystem"
-   depends on !DM_I2C || DM_I2C_COMPAT
help
  (deprecated, needs conversion to driver model)
  Provides commands to read and write EEPROM (Electrically Erasable
-- 
2.17.1

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[U-Boot] [PATCH v3 1/2] eeprom: fix DM_I2C support without CONFIG_SYS_I2C_EEPROM_BUS

2019-04-23 Thread Simon Goldschmidt
The current device model enabled eeprom code only works if
CONFIG_SYS_I2C_EEPROM_BUS is set.

This patch makes it work without that define so that the bus
number passed to 'eeprom_init' is used.

Signed-off-by: Simon Goldschmidt 
Reviewed-by: Heiko Schocher 
---

Changes in v3:
- use eeprom_init() to set CONFIG_SYS_I2C_EEPROM_BUS, not
  i2c_set_bus_num to make things work with CONFIG_DM_I2C

Changes in v2: None

 cmd/eeprom.c | 23 +++
 1 file changed, 15 insertions(+), 8 deletions(-)

diff --git a/cmd/eeprom.c b/cmd/eeprom.c
index 6c29b33ba3..7b1f81477f 100644
--- a/cmd/eeprom.c
+++ b/cmd/eeprom.c
@@ -59,6 +59,10 @@
 #endif
 #endif
 
+#if defined(CONFIG_DM_I2C)
+int eeprom_i2c_bus;
+#endif
+
 __weak int eeprom_write_enable(unsigned dev_addr, int state)
 {
return 0;
@@ -67,7 +71,9 @@ __weak int eeprom_write_enable(unsigned dev_addr, int state)
 void eeprom_init(int bus)
 {
/* I2C EEPROM */
-#if defined(CONFIG_SYS_I2C)
+#if defined(CONFIG_DM_I2C)
+   eeprom_i2c_bus = bus;
+#elif defined(CONFIG_SYS_I2C)
if (bus >= 0)
i2c_set_bus_num(bus);
i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
@@ -124,14 +130,14 @@ static int eeprom_rw_block(unsigned offset, uchar *addr, 
unsigned alen,
 {
int ret = 0;
 
-#if defined(CONFIG_DM_I2C) && defined(CONFIG_SYS_I2C_EEPROM_BUS)
+#if defined(CONFIG_DM_I2C)
struct udevice *dev;
 
-   ret = i2c_get_chip_for_busnum(CONFIG_SYS_I2C_EEPROM_BUS, addr[0],
+   ret = i2c_get_chip_for_busnum(eeprom_i2c_bus, addr[0],
  alen - 1, );
if (ret) {
printf("%s: Cannot find udev for a bus %d\n", __func__,
-  CONFIG_SYS_I2C_EEPROM_BUS);
+  eeprom_i2c_bus);
return CMD_RET_FAILURE;
}
 
@@ -141,15 +147,12 @@ static int eeprom_rw_block(unsigned offset, uchar *addr, 
unsigned alen,
ret = dm_i2c_write(dev, offset, buffer, len);
 
 #else /* Non DM I2C support - will be removed */
-#if defined(CONFIG_SYS_I2C_EEPROM_BUS)
-   i2c_set_bus_num(CONFIG_SYS_I2C_EEPROM_BUS);
-#endif
 
if (read)
ret = i2c_read(addr[0], offset, alen - 1, buffer, len);
else
ret = i2c_write(addr[0], offset, alen - 1, buffer, len);
-#endif /* CONFIG_DM_I2C && CONFIG_SYS_I2C_EEPROM_BUS */
+#endif /* CONFIG_DM_I2C */
if (ret)
ret = CMD_RET_FAILURE;
 
@@ -164,6 +167,10 @@ static int eeprom_rw(unsigned dev_addr, unsigned offset, 
uchar *buffer,
int rcode = 0;
uchar addr[3];
 
+#if defined(CONFIG_SYS_I2C_EEPROM_BUS)
+   eeprom_init(CONFIG_SYS_I2C_EEPROM_BUS);
+#endif
+
while (offset < end) {
alen = eeprom_addr(dev_addr, offset, addr);
 
-- 
2.17.1

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[U-Boot] mdio error on ar9344

2019-04-23 Thread muaddib


Hi, I am using device based on Atheros AR9344.

When U-Boot initialize net device I get error
mdio_register: non unique device name 'gmac0'

dm tree command shows that eth_ag7xxx is not probed.

ag7xxx_eth_probe -> ag7xxx_mac_probe -> ag933x_phy_setup -> 
ag933x_phy_setup_reset_set -> ag7xxx_mdio_write -> ag7xxx_mdio_rw
return -ETIMEDOUT

because ag7xxx_switch_reg_read return 0x, see below

static int ag7xxx_mdio_rw(struct mii_dev *bus, int addr, int reg, u32 val)
{
    u32 data;
    unsigned long start;
    int ret;
    // No idea if this is long enough or too long
    int timeout_ms = 1000;

    // Dummy read followed by PHY read/write command.
    ret = ag7xxx_switch_reg_read(bus, 0x98, );
    if (ret < 0)
    return ret;
    data = val | (reg << 16) | (addr << 21) | BIT(30) | BIT(31);
    ret = ag7xxx_switch_reg_write(bus, 0x98, data);
    if (ret < 0)
    return ret;

    start = get_timer(0);

    // Wait for operation to finish
    do {
    ret = ag7xxx_switch_reg_read(bus, 0x98, );
    if (ret < 0)
    return ret;
    if (get_timer(start) > timeout_ms)
    return -ETIMEDOUT;
    } while (data & BIT(31));
 
    return data & 0x;
}

I use tplink_wdr4320 u-boot profile for my device.



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[U-Boot] Pull request for UEFI sub-system for v2019.07-rc1 (3)

2019-04-23 Thread Heinrich Schuchardt

Cc: U-Boot Mailing List

The following changes since commit 6c5f8dd540d7a8eff244d4c27a09451ca12c8d20:

  Merge branch 'master' of git://git.denx.de/u-boot-usb (2019-04-21
19:00:04 -0400)

are available in the Git repository at:

  git://git.denx.de/u-boot-efi.git tags/efi-2019-07-rc1-3

for you to fetch changes up to 7d1e4b73e3f321cd4f0e039aa0387484cf97b25c:

  efi_loader: check length in CreateDeviceNode() (2019-04-23 00:51:01
+0200)

Travis CI testing was successful:
https://travis-ci.org/xypron2/u-boot/builds/523322671

Primary key fingerprint:
6DC4 F9C7 1F29 A6FA 06B7  6D33 C481 DBBC 2C05 1AC4


Pull request for UEFI sub-system for v2019.07-rc1 (3)

This patch series reworks the implementation of the `bootefi` command to
remove code duplication by using the LoadImage() boot service to load
binaries.

Missing short texts for UEFI protocols are added for display by the
`efidebug dh` command.

Missing parameter checks for AllocatePages() and CreateDeviceNode() are
implemented.

The constants for protocol GUIDs are changed to match the names in the
UEFI specification.


AKASHI Takahiro (10):
  efi_loader: efi_setup_loaded_image() handle missing file name
  efi_loader: export root node handle
  cmd: bootefi: rework set_load_options()
  cmd: bootefi: carve out fdt handling from do_bootefi()
  cmd: bootefi: merge efi_install_fdt() and efi_process_fdt()
  cmd: bootefi: carve out efi_selftest code from do_bootefi()
  cmd: bootefi: move do_bootefi_bootmgr_exec() forward
  cmd: bootefi: carve out bootmgr code from do_bootefi()
  cmd: bootefi: carve out do_bootefi_image() from do_bootefi()
  efi_loader: rework bootmgr/bootefi using load_image API

Heinrich Schuchardt (9):
  efi_loader: consistent naming of protocol GUIDs
  efi_loader: more short texts for protocols in efidebug
  efi_loader: correctly split device path of loaded image
  efi_loader: disable EFI_LOADER on vexpress_ca15_tc2 and ca9x4
  test/py: pytest.mark.notbuildconfigspec()
  efi_selftest: do not run FDT test with ACPI table.
  efi_loader: need either ACPI table or device tree
  efi_loader: check memory type in AllocatePages()
  efi_loader: check length in CreateDeviceNode()

 cmd/bootefi.c| 532
+--
 cmd/efidebug.c   |  30 +-
 configs/vexpress_ca15_tc2_defconfig  |   1 +
 configs/vexpress_ca9x4_defconfig |   1 +
 include/efi.h|   4 +
 include/efi_api.h|  18 +-
 include/efi_loader.h |   8 +-
 lib/efi/efi.c|   2 +-
 lib/efi/efi_stub.c   |   2 +-
 lib/efi_loader/efi_bootmgr.c |  42 ++-
 lib/efi_loader/efi_boottime.c|  14 +-
 lib/efi_loader/efi_device_path.c |  10 +-
 lib/efi_loader/efi_disk.c|   2 +-
 lib/efi_loader/efi_gop.c |   2 +-
 lib/efi_loader/efi_image_loader.c|   8 +-
 lib/efi_loader/efi_memory.c  |   4 +
 lib/efi_loader/efi_net.c |   4 +-
 lib/efi_loader/efi_root_node.c   |   5 +-
 lib/efi_loader/helloworld.c  |   2 +-
 lib/efi_selftest/Makefile|   5 +-
 lib/efi_selftest/efi_selftest_bitblt.c   |   2 +-
 lib/efi_selftest/efi_selftest_block_device.c |   4 +-
 lib/efi_selftest/efi_selftest_devicepath.c   |   2 +-
 lib/efi_selftest/efi_selftest_fdt.c  |  41 ++-
 lib/efi_selftest/efi_selftest_gop.c  |   2 +-
 lib/efi_selftest/efi_selftest_loadimage.c|   2 +-
 lib/efi_selftest/efi_selftest_miniapp_exit.c |   2 +-
 lib/efi_selftest/efi_selftest_snp.c  |   2 +-
 test/py/README.md|   1 +
 test/py/conftest.py  |  14 +-
 test/py/tests/test_efi_selftest.py   |   3 +-
 31 files changed, 494 insertions(+), 277 deletions(-)
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[U-Boot] [PATCH] ARM: socfpga: Remove socfpga_sdram_apply_static_cfg()

2019-04-23 Thread Marek Vasut
The usage of socfpga_sdram_apply_static_cfg() seems rather dubious and
is confirmed to lead to a rare system hang when enabling bridges. This
patch removes the socfpga_sdram_apply_static_cfg() altogether, because
it's use seems unjustified and problematic.

The socfpga_sdram_apply_static_cfg() triggers write to SDRAM staticcfg
register to set the applycfg bit, which according to old vendor U-Boot
sources can only be written when there is no traffic between the SDRAM
controller and the rest of the system. Empirical measurements confirm
this, setting the applycfg bit when there is traffic between the SDRAM
controller and CPU leads to the SDRAM controller accesses being blocked
shortly after.

Altera originally solved this by moving the entire code which sets the
staticcfg register to OCRAM [1]. The commit message claims that the
applycfg bit needs to be set after write to fpgaportrst register. This
is however inverted by Altera shortly after in [2], where the order
becomes the exact opposite of what commit message [1] claims to be the
required order. The explanation points to a possible problem in AMP
use-case, where the FPGA might be sending transactions through the F2S
bridge.

However, the AMP is only the tip of the iceberg here. Any of the other
L2, L3 or L4 masters can trigger transactions to the SDRAM. It becomes
rather non-trivial to guarantee there are no transactions to the SDRAM
controller.

The SoCFPGA SDRAM driver always writes the applycfg bit in SPL. Thus,
writing the applycfg again in bridge enable code seems redundant and
can presumably be dropped.

[1] 
https://github.com/altera-opensource/u-boot-socfpga/commit/75905816ec95b0ccd515700b922628d7aa9036f8
[2] 
https://github.com/altera-opensource/u-boot-socfpga/commit/8ba6986b04a91d23c7adf529186b34c8d2967ad5

Signed-off-by: Marek Vasut 
Cc: Chin Liang See 
Cc: Dinh Nguyen 
Cc: Simon Goldschmidt 
Cc: Tien Fong Chee 
---
 arch/arm/mach-socfpga/misc_gen5.c | 31 ---
 1 file changed, 31 deletions(-)

diff --git a/arch/arm/mach-socfpga/misc_gen5.c 
b/arch/arm/mach-socfpga/misc_gen5.c
index 7876953595..eeba199edc 100644
--- a/arch/arm/mach-socfpga/misc_gen5.c
+++ b/arch/arm/mach-socfpga/misc_gen5.c
@@ -220,35 +220,6 @@ static struct socfpga_reset_manager *reset_manager_base =
 static struct socfpga_sdr_ctrl *sdr_ctrl =
(struct socfpga_sdr_ctrl *)SDR_CTRLGRP_ADDRESS;
 
-static void socfpga_sdram_apply_static_cfg(void)
-{
-   const u32 applymask = 0x8;
-   u32 val = readl(_ctrl->static_cfg) | applymask;
-
-   /*
-* SDRAM staticcfg register specific:
-* When applying the register setting, the CPU must not access
-* SDRAM. Luckily for us, we can abuse i-cache here to help us
-* circumvent the SDRAM access issue. The idea is to make sure
-* that the code is in one full i-cache line by branching past
-* it and back. Once it is in the i-cache, we execute the core
-* of the code and apply the register settings.
-*
-* The code below uses 7 instructions, while the Cortex-A9 has
-* 32-byte cachelines, thus the limit is 8 instructions total.
-*/
-   asm volatile(
-   ".align 5   \n"
-   "   b   2f  \n"
-   "1: str %0, [%1]\n"
-   "   dsb \n"
-   "   isb \n"
-   "   b   3f  \n"
-   "2: b   1b  \n"
-   "3: nop \n"
-   : : "r"(val), "r"(_ctrl->static_cfg) : "memory", "cc");
-}
-
 void do_bridge_reset(int enable, unsigned int mask)
 {
int i;
@@ -263,14 +234,12 @@ void do_bridge_reset(int enable, unsigned int mask)
}
 
writel(iswgrp_handoff[2], _regs->fpgaintfgrp_module);
-   socfpga_sdram_apply_static_cfg();
writel(iswgrp_handoff[3], _ctrl->fpgaport_rst);
writel(iswgrp_handoff[0], _manager_base->brg_mod_reset);
writel(iswgrp_handoff[1], _regs->remap);
} else {
writel(0, _regs->fpgaintfgrp_module);
writel(0, _ctrl->fpgaport_rst);
-   socfpga_sdram_apply_static_cfg();
writel(0, _manager_base->brg_mod_reset);
writel(1, _regs->remap);
}
-- 
2.20.1

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[U-Boot] [PATCH v2] pinctrl: imx: Define imx6_pinctrl_soc_info in .data section

2019-04-23 Thread Lukasz Majewski
This commit is necessary to be able to re-use the pinctrl code in early
SPL to properly configure pins.

The problem is that those "static" structures (without explicit
initialization) are placed in the SDRAM area, which corresponds to
u-boot proper (not even SPL).
Hence, when one wants to configure pins before relocation via DTS/DM,
the board hangs (imx6q SoC powered one) as only OCRAM area is available
(0x009x).

This commit prevents from this issue by moving the imx6_pinctrl_soc_info
structure to data section (from BSS).

Signed-off-by: Lukasz Majewski 

---

Changes in v2:
- Use __section(".data") instead of rewritting the code to use calloc()
  (less intrusive commit)

 drivers/pinctrl/nxp/pinctrl-imx6.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/pinctrl/nxp/pinctrl-imx6.c 
b/drivers/pinctrl/nxp/pinctrl-imx6.c
index d7c95bb738..0c1e7a9c05 100644
--- a/drivers/pinctrl/nxp/pinctrl-imx6.c
+++ b/drivers/pinctrl/nxp/pinctrl-imx6.c
@@ -10,7 +10,7 @@
 
 #include "pinctrl-imx.h"
 
-static struct imx_pinctrl_soc_info imx6_pinctrl_soc_info;
+static struct imx_pinctrl_soc_info imx6_pinctrl_soc_info __section(".data");
 
 /* FIXME Before reloaction, BSS is overlapped with DT area */
 static struct imx_pinctrl_soc_info imx6ul_pinctrl_soc_info = {
-- 
2.11.0

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Re: [U-Boot] [U-Boot, 1/4] pinctrl: exit pinconfig_post_bind if there are no subnodes

2019-04-23 Thread Philipp Tomsich
> This fixes RK3288 SPL hanging or hitting this assert:
> drivers/core/ofnode.c:183: ofnode_first_subnode: Assertion 
> `ofnode_valid(node)' failed.
> 
> Signed-off-by: Urja Rannikko 
> Reviewed-by: Simon Glass 
> Reviewed-by: Philipp Tomsich 
> ---
>  drivers/pinctrl/pinctrl-uclass.c | 3 +++
>  1 file changed, 3 insertions(+)
> 

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Re: [U-Boot] [U-Boot, 2/4] rk3288-board: remove pinctrl call for debug uart

2019-04-23 Thread Philipp Tomsich
> This failed and caused a boot failure on c201, and afaik
> the pins should be setup by the new pinctrl driver.
> 
> Signed-off-by: Urja Rannikko 
> Reviewed-by: Simon Glass 
> Reviewed-by: Philipp Tomsich 
> ---
>  arch/arm/mach-rockchip/rk3288-board.c | 12 
>  1 file changed, 12 deletions(-)
> 

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Re: [U-Boot] [U-Boot,v2] rockchip: arm: remove no use macro

2019-04-23 Thread Philipp Tomsich
> TIMER7_BASE is no used by source code now, remove it.
> 
> Signed-off-by: Kever Yang 
> Reviewed-by: Philipp Tomsich 
> ---
> 
>  arch/arm/include/asm/arch-rockchip/hardware.h | 2 --
>  1 file changed, 2 deletions(-)
> 

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Re: [U-Boot] [U-Boot, 2/8] rockchip: spi: remove unused code and fields in priv

2019-04-23 Thread Philipp Tomsich
> Even though the priv-structure and the claim-bus function contain
> logic for 16bit frames and for unidirectional transfer modes, neither
> of these is used anywhere in the driver.
> 
> This removes the unused (as in "has no effect") logic and fields.
> 
> Signed-off-by: Philipp Tomsich 
> ---
> 
>  drivers/spi/rk_spi.c | 29 +++--
>  1 file changed, 3 insertions(+), 26 deletions(-)
> 

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Re: [U-Boot] [U-Boot, 3/8] rockchip: spi: fix off-by-one in chunk size computation

2019-04-23 Thread Philipp Tomsich
> The maximum transfer length (in a single transaction) for the Rockchip
> SPI controller is 64Kframes (i.e. 0x1 frames) of 8bit or 16bit
> frames and is encoded as (num_frames - 1) in CTRLR1.  The existing
> code subtracted the "minus 1" twice for a maximum transfer length of
> 0x (64K - 1) frames.
> 
> While this is not strictly an error (the existing code is correct, but
> leads to a bit of head-scrating), fix this off-by-one situation.
> 
> Signed-off-by: Philipp Tomsich 
> ---
> 
>  drivers/spi/rk_spi.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 

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Re: [U-Boot] [U-Boot, 8/8] rockchip: spi: make optimised receive-handler unaligned-safe

2019-04-23 Thread Philipp Tomsich
> To support unaligned output buffers (i.e. 'in' in the terminology of
> the SPI framework), this change splits each 16bit FIFO element after
> reading and writes them to memory in two 8bit transactions.  With this
> change, we can now always use the optimised mode for receive-only
> transcations independent on the alignment of the target buffer.
> 
> Given that we'll run with caches on, the impact should be negligible:
> as expected, this has no adverse impact on throughput if running with
> a 960MHz LPLL configuration.
> 
> Signed-off-by: Philipp Tomsich 
> ---
> 
>  drivers/spi/rk_spi.c | 19 ++-
>  1 file changed, 6 insertions(+), 13 deletions(-)
> 

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Re: [U-Boot] [U-Boot, 5/8] rockchip: spi: only wait for completion, if transmitting

2019-04-23 Thread Philipp Tomsich
> The logic in the main transmit loop took a bit of reading the TRM to
> fully understand (due to silent assumptions based in internal logic):
> the "wait until idle" at the end of each iteration through the loop is
> required for the transmit-path as each clearing of the ENA register
> (to update run-length in the CTRLR1 register) will implicitly flush
> the FIFOs... transmisson can therefore not overlap loop iterations.
> 
> This change adds a comment to clarify the reason/need for waiting
> until the controller becomes idle and wraps the entire check into an
> 'if (out)' to make it clear that this is required for transfers with a
> transmit-component only (for transfers having a receive-component,
> completion of the transmit-side is trivially ensured by having
> received the correct number of bytes).
> 
> The change does not increase execution time measurably in any of my
> tests.
> 
> Signed-off-by: Philipp Tomsich 
> ---
> 
>  drivers/spi/rk_spi.c | 15 ---
>  1 file changed, 12 insertions(+), 3 deletions(-)
> 

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Re: [U-Boot] [U-Boot, 7/8] rockchip: spi: add driver-data and a 'rxonly_manages_fifo' flag

2019-04-23 Thread Philipp Tomsich
> The SPI controller's documentation (I only had access to the RK3399,
> RK3368 and PX30 TRMs) specifies that, when operating in master-mode,
> the controller will stop the SCLK to avoid RXFIFO overruns and TXFIFO
> underruns.  Looks like my worries that we'd need to support DMA-330
> (aka PL330) to make any further progress were unfounded.
> 
> This adds a driver-data structure to capture hardware-specific
> settings of individual controller instances (after all, we don't know
> if all versions are well-behaved) and adds a 'master_manages_fifo'
> flag to it.  The first use of said flag is in the optimised
> receive-only transfer-handler, which can now request 64Kframe
> (i.e. 128KByte) bursts of data on each reprogramming of CTRLR1
> (i.e. every time through the loop).
> 
> This improves throughput to 46.85MBit/s (a 94.65% bus-utilisation).
> 
> Signed-off-by: Philipp Tomsich 
> ---
> 
>  drivers/spi/rk_spi.c | 24 ++--
>  1 file changed, 22 insertions(+), 2 deletions(-)
> 

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Re: [U-Boot] [U-Boot, 6/8] rockchip: spi: add optimised receive-only implementation

2019-04-23 Thread Philipp Tomsich
> For the RK3399-Q7 we recommend storing SPL and u-boot.itb in the
> on-module 32MBit (and sometimes even larger, if requested as part of a
> configure-to-order configuration) SPI-NOR flash that is clocked for a
> bitrate of 49.5MBit/s and connected in a single-IO configuration (the
> RK3399 only supports single-IO for SPI).
> 
> Unfortunately, the existing SPI driver is excruciatingly slow at
> reading out large chunks of data (in fact it is just as slow for small
> chunks of data, but the overheads of the driver-framework make it less
> noticeable): before this change, the throughput on a 4MB read from
> SPI-NOR is 8.47MBit/s which equates a 17.11% bus-utilisation.
> 
> To improve on this, this commit adds an optimised receive-only
> transfer (i.e.: out == NULL) handler that hooks into the main transfer
> function and processes data in 16bit frames (utilising the full with
> of each FIFO element).  As of now, the receive-only handler requires
> the in-buffer to be 16bit aligned.  Any lingering data (i.e. either if
> the in-buffer was not 16-bit aligned or if an odd number of bytes are
> to be received) will be handled by the original 8bit reader/wirter.
> 
> Given that the SPI controller's documentation does not guarantuee any
> interlocking between the RXFIFO and the master SCLK, the transfer loop
> will be restarted for each chunk of 32 frames (i.e. 64 bytes).
> 
> With this new receive-only transfer handler, the throughput for a 4MB
> read increases to 36.28MBit/s (i.e. 73.29% bus-utilisation): this is a
> 4x improvement over the baseline.
> 
> Signed-off-by: Philipp Tomsich 
> Reported-by: Klaus Goger 
> 
> Series-Cc: Klaus Goger 
> Series-Cc: Christoph Muellner 
> ---
> 
>  drivers/spi/rk_spi.c | 89 
> +++-
>  1 file changed, 88 insertions(+), 1 deletion(-)
> 

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Re: [U-Boot] rockchip: rk3399-puma: support Gigadevice SPI-NOR flash

2019-04-23 Thread Philipp Tomsich
> Over the last quarter, a part of our production has used NOR flash
> from Gigadevice in addition to the Winbond parts that we typically
> source.  This requires the SPI_FLASH_GIGADEVICE config to be set.
> 
> Enable SPI_FLASH_GIGADEVICE in the board's default defconfig.
> 
> Signed-off-by: Philipp Tomsich 
> Reviewed-by: Klaus Goger 
> ---
> 
>  configs/puma-rk3399_defconfig | 1 +
>  1 file changed, 1 insertion(+)
> 

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Re: [U-Boot] [U-Boot, 4/8] rockchip: spi: consistently use false/true with rkspi_enable_chip

2019-04-23 Thread Philipp Tomsich
> While rkspi_enable_chip is called with true/false everywhere else in
> the file, one call site uses '0' to denot 'false'.
> This change this one parameter to 'false' and effects consistency.
> 
> Signed-off-by: Philipp Tomsich 
> ---
> 
>  drivers/spi/rk_spi.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 

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Re: [U-Boot] [U-Boot, 1/8] rockchip: spi: add debug message for delay in CS toggle

2019-04-23 Thread Philipp Tomsich
> In analysing delays introduced for large SPI reads, the absence of any
> indication when a delay was inserted (to ensure the CS toggling is
> observed by devices) became apparent.
> 
> Add an additional debug-only debug message to record the insertion and
> duration of any delay (note that the debug-message will cause a delay
> on-top of the delay-duration).
> 
> Signed-off-by: Philipp Tomsich 
> ---
> 
>  drivers/spi/rk_spi.c | 9 +++--
>  1 file changed, 7 insertions(+), 2 deletions(-)
> 

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Re: [U-Boot] [PULL] u-boot-stm32 for v2019.07-rc1​ (round 2)

2019-04-23 Thread Patrice CHOTARD
Hi Tom

On 4/22/19 12:59 AM, Tom Rini wrote:
> On Fri, Apr 19, 2019 at 04:03:24PM +, Patrice CHOTARD wrote:
> 
>> Hi Tom
>>
>> Please find the pull request for STM32 round 2
>>
>> The following changes since commit 1f4ae66eaab29bfb5d1eb44996f7826c9cd01ed1:
>>
>>   Merge tag 'arc-for-2019.07' of git://git.denx.de/u-boot-arc
>> (2019-04-18 12:12:16 -0400)
>>
>> are available in the git repository at:
>>
>>
>>   https://github.com/pchotard/u-boot.git tags/u-boot-stm32-mcu-20190419
>>
>> for you to fetch changes up to 5b37873ff04f082efa0a74ba04185599ccec165b:
>>
>>   mmc: stm32_sdmmc2: Fix r1b timeout issue (2019-04-19 17:19:32 +0200)
>>
> 
> The content is fine, but looking at checkpatch.pl --git output I see a
> ton of Change-Ids.  Can you please re-spin with the commits reworded to
> drop those?  Thanks!
> 

Sorry for that, i sent a new pull request:
http://patchwork.ozlabs.org/patch/1089434/

Thanks

Patrice
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[U-Boot] [RESEND] [PULL] u-boot-stm32 for v2019.07-rc1​ (round 2)

2019-04-23 Thread Patrice CHOTARD
Hi Tom

Please find the pull request for STM32 round 2
As requested, i removed the Change-Id in commit messages.

The following changes since commit 1f4ae66eaab29bfb5d1eb44996f7826c9cd01ed1:

  Merge tag 'arc-for-2019.07' of git://git.denx.de/u-boot-arc
(2019-04-18 12:12:16 -0400)

are available in the git repository at:


  https://github.com/pchotard/u-boot.git tags/u-boot-stm32-mcu-20190423

for you to fetch changes up to c406a474311c1ee3c4303a7e85db4a8e45966e31:

  mmc: stm32_sdmmc2: Fix r1b timeout issue (2019-04-23 15:42:28 +0200)


STM32 MCUs update:
_ DT rework and alignment with DT kernel v4.20
_ mmc: arm_pl180_mmci: Synchronize compatible with kernel v4.20
_ mmc: stm32_sdmmc2: Synchronize properties with kernel v4.20
_ configs: update for F746/769 boards


Christophe Kerello (1):
  mmc: stm32_sdmmc2: Fix r1b timeout issue

Patrice Chotard (15):
  ARM:dts: stm32: sort nodes by alphabetical order in f4 u-boot files
  ARM: dts: stm32: Sync DT files with v4.20 kernel for stm32f4
  ARM: dts: stm32: Migrate U-boot nodes to U-boot DT files for stm32f7
  ARM: dts: stm32: Sync DT with v4.20 kernel for stm32f7
  ARM: dts: Migrate U-boot nodes to U-boot DT files for stm32h7
  ARM: dts: stm32: Sync DT with v4.20 kernel for stm32h7
  ARM: dts: stm32: Restore old usart1 clock bindings for stm32f7
  pinctrl: stm32: Add st,stm32f769-pinctrl compatible string
  mmc: arm_pl180_mmci: Sync compatible with kernel
  configs: stm32f746-disco: update EXTRA_ENV_SETTINGS
  configs: stm32f746-disco: enable CONFIG_DISTRO_DEFAULTS
  configs: stm32f746-disco: Enable SPI_FLASH_MACRONIX
  board: stm32f746-disco: Get MII/RMII phy_mode from DT
  ARM: dts: stm32: Update sdmmc binding for stm32h743i-eval
  ARM: dts: stm32: Update sdmmc binding for stm32mp157c-ed1

Patrick Delaunay (1):
  mmc: stm32_sdmmc2: Update DT properties with v4.19 bindings

 arch/arm/dts/stm32746g-eval-u-boot.dtsi |  188 +++
 arch/arm/dts/stm32746g-eval.dts |  222 +---
 arch/arm/dts/stm32f4-pinctrl.dtsi   |   27 +-
 arch/arm/dts/stm32f429-disco-u-boot.dtsi|   18 +-
 arch/arm/dts/stm32f429-disco.dts|4 +-
 arch/arm/dts/stm32f429-pinctrl.dtsi |3 +-
 arch/arm/dts/stm32f429.dtsi |   33 +-
 arch/arm/dts/stm32f469-disco-u-boot.dtsi|   46 +-
 arch/arm/dts/stm32f469-disco.dts|   86 +-
 arch/arm/dts/stm32f469-pinctrl.dtsi |3 +-
 arch/arm/dts/stm32f469.dtsi |   19 +
 arch/arm/dts/stm32f7-pinctrl.dtsi   |  289 
 arch/arm/dts/stm32f7-u-boot.dtsi|  139 +-
 arch/arm/dts/stm32f746-disco-u-boot.dtsi|  251 
 arch/arm/dts/stm32f746-disco.dts|  279 +---
 arch/arm/dts/stm32f746-pinctrl.dtsi |   11 +
 arch/arm/dts/stm32f746.dtsi |  747 +++
 arch/arm/dts/stm32f769-disco-u-boot.dtsi|  165 +++
 arch/arm/dts/stm32f769-disco.dts|  236 +---
 arch/arm/dts/stm32f769-pinctrl.dtsi |   11 +
 arch/arm/dts/stm32h7-u-boot.dtsi|  197 ++-
 arch/arm/dts/stm32h743-pinctrl.dtsi |  160 +--
 arch/arm/dts/stm32h743.dtsi |  462 ++-
 arch/arm/dts/stm32h743i-disco-u-boot.dtsi   |   11 +
 arch/arm/dts/stm32h743i-disco.dts   |   44 +-
 arch/arm/dts/stm32h743i-eval-u-boot.dtsi|   12 +
 arch/arm/dts/stm32h743i-eval.dts|   79 +-
 arch/arm/dts/stm32mp157c-ed1.dts|   10 +-
 board/st/stm32f746-disco/stm32f746-disco.c  |   23 +-
 configs/stm32f746-disco_defconfig   |   14 +-
 drivers/mmc/arm_pl180_mmci.c|   14 +-
 drivers/mmc/arm_pl180_mmci.h|3 +-
 drivers/mmc/stm32_sdmmc2.c  |   67 +-
 drivers/pinctrl/pinctrl_stm32.c |1 +
 include/configs/stm32f746-disco.h   |   22 +-
 include/dt-bindings/clock/stm32fx-clock.h   |7 +-
 include/dt-bindings/pinctrl/stm32f746-pinfunc.h | 1341 ---
 include/dt-bindings/pinctrl/stm32h7-pinfunc.h   | 1612
---
 38 files changed, 2740 insertions(+), 4116 deletions(-)
 create mode 100644 arch/arm/dts/stm32746g-eval-u-boot.dtsi
 create mode 100644 arch/arm/dts/stm32f469.dtsi
 create mode 100644 arch/arm/dts/stm32f7-pinctrl.dtsi
 create mode 100644 arch/arm/dts/stm32f746-disco-u-boot.dtsi
 create mode 100644 arch/arm/dts/stm32f746-pinctrl.dtsi
 create mode 100644 arch/arm/dts/stm32f769-disco-u-boot.dtsi
 create mode 100644 arch/arm/dts/stm32f769-pinctrl.dtsi
 create mode 100644 arch/arm/dts/stm32h743i-disco-u-boot.dtsi
 create mode 100644 arch/arm/dts/stm32h743i-eval-u-boot.dtsi
 delete mode 100644 include/dt-bindings/pinctrl/stm32f746-pinfunc.h

[U-Boot] should all include/configs/*.h headers be included via SYS_CONFIG_NAME?

2019-04-23 Thread Robert P. J. Day

  pretty sure i know the answer to this, but i'm going to ask it
anyway ... should all header files under include/configs/ be included
in a build either directly or indirectly via the value in
CONFIG_SYS_CONFIG_NAME?

  i'm aware of that Kbuild setting and what it's used for:

  config SYS_CONFIG_NAME
 string "Board configuration name"
 default "zynq-common"
 help
   This option contains information about board configuration name.
   Based on this option include/configs/.h header
   will be used for board configuration.

at which point that header file might well include further header
files under include/configs/ and so on. so the question is, are
include/configs/ header files meant to be included *exclusively* via
CONFIG_SYS_CONFIG_NAME?

  i ask since, out of curiosity, i did a quick grep to see if any of
them were included from anywhere else, and i found all of one hit in
the entire code base:

  $ git grep '#include 
  $

i thought it was odd that there would be a single example of that in
the whole code base, even more so since the board file Kconfig
board/renesas/ecovec/Kconfig includes:

  config SYS_CONFIG_NAME
default "ecovec"

which suggests that header file would have been included anyway.

  thoughts?

rday

-- 


Robert P. J. Day Ottawa, Ontario, CANADA
 http://crashcourse.ca

Twitter:   http://twitter.com/rpjday
LinkedIn:   http://ca.linkedin.com/in/rpjday

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Re: [U-Boot] [PATCH] riscv:Add Microchip MPFS Icicle Board support

2019-04-23 Thread Bin Meng
Hi Padmarao,

On Thu, Apr 18, 2019 at 2:21 AM Padmarao Begari
 wrote:
>
> This patch adds Microchip MPFS Icicle Board support.

nits: Board->board. Please fix the commit message too.

> For now, NS16550 serial driver is only enabled.
> The Microchip MPFS Icicle defconfig by default builds
> U-Boot for M-Mode with SMP support.
>
> Signed-off-by: Padmarao Begari 
> ---
>  arch/riscv/Kconfig|  4 ++
>  board/microchip/mpfs-icicle/Kconfig   | 20 ++
>  board/microchip/mpfs-icicle/MAINTAINERS   |  7 
>  board/microchip/mpfs-icicle/Makefile  |  7 
>  board/microchip/mpfs-icicle/mpfs-icicle.c | 31 +++
>  configs/microchip-mpfs-icicle_defconfig   | 16 
>  include/configs/microchip-mpfs-icicle.h   | 63 
> +++
>  7 files changed, 148 insertions(+)
>  create mode 100644 board/microchip/mpfs-icicle/Kconfig
>  create mode 100644 board/microchip/mpfs-icicle/MAINTAINERS
>  create mode 100644 board/microchip/mpfs-icicle/Makefile
>  create mode 100644 board/microchip/mpfs-icicle/mpfs-icicle.c
>  create mode 100644 configs/microchip-mpfs-icicle_defconfig
>  create mode 100644 include/configs/microchip-mpfs-icicle.h
>
> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> index ae8ff7b..df9b2ea 100644
> --- a/arch/riscv/Kconfig
> +++ b/arch/riscv/Kconfig
> @@ -17,12 +17,16 @@ config TARGET_QEMU_VIRT
>  config TARGET_SIFIVE_FU540
> bool "Support SiFive FU540 Board"
>
> +config TARGET_MICROCHIP_MPFS

I assume MPFS stands for Microchip PolarFire-SoC? And the board is
called Icicle? If yes, shouldn't this be TARGET_MICROCHIP_ICICLE?

nits: TARGET_MICROCHIP_xxx should come before TARGET_SIFIVE_

> +   bool "Support Microchip PolarFire-SoC Icicle Board"
> +
>  endchoice
>
>  # board-specific options below
>  source "board/AndesTech/ax25-ae350/Kconfig"
>  source "board/emulation/qemu-riscv/Kconfig"
>  source "board/sifive/fu540/Kconfig"
> +source "board/microchip/mpfs-icicle/Kconfig"

nits: please put it in the alphabetical order

For naming convention, please use mpfs_icicle (_ instead of -)

>
>  # platform-specific options below
>  source "arch/riscv/cpu/ax25/Kconfig"
> diff --git a/board/microchip/mpfs-icicle/Kconfig 
> b/board/microchip/mpfs-icicle/Kconfig
> new file mode 100644
> index 000..e17ba78
> --- /dev/null
> +++ b/board/microchip/mpfs-icicle/Kconfig
> @@ -0,0 +1,20 @@
> +if TARGET_MICROCHIP_MPFS
> +
> +config SYS_BOARD
> +   default "mpfs-icicle"
> +
> +config SYS_VENDOR
> +   default "microchip"
> +
> +config SYS_CPU
> +   default "generic"
> +
> +config SYS_CONFIG_NAME
> +   default "microchip-mpfs-icicle"

nits: use _ instead of -

> +
> +config BOARD_SPECIFIC_OPTIONS # dummy
> +   def_bool y
> +   select GENERIC_RISCV
> +   imply SMP
> +
> +endif
> diff --git a/board/microchip/mpfs-icicle/MAINTAINERS 
> b/board/microchip/mpfs-icicle/MAINTAINERS
> new file mode 100644
> index 000..9987efe
> --- /dev/null
> +++ b/board/microchip/mpfs-icicle/MAINTAINERS
> @@ -0,0 +1,7 @@
> +Microchip MPFS icicle
> +M: Padmarao Begari 
> +M: Cyril Jean 
> +S: Maintained
> +F: board/microchip/mpfs-icicle/
> +F: include/configs/microchip-mpfs-icicle.h
> +F: configs/microchip-mpfs-icicle_defconfig
> diff --git a/board/microchip/mpfs-icicle/Makefile 
> b/board/microchip/mpfs-icicle/Makefile
> new file mode 100644
> index 000..4706586
> --- /dev/null
> +++ b/board/microchip/mpfs-icicle/Makefile
> @@ -0,0 +1,7 @@
> +# SPDX-License-Identifier: GPL-2.0+
> +#
> +# Copyright (C) 2019 Microchip Technology Inc.
> +# Padmarao Begari 
> +#
> +
> +obj-y  += mpfs-icicle.o
> diff --git a/board/microchip/mpfs-icicle/mpfs-icicle.c 
> b/board/microchip/mpfs-icicle/mpfs-icicle.c
> new file mode 100644
> index 000..5a23a7d
> --- /dev/null
> +++ b/board/microchip/mpfs-icicle/mpfs-icicle.c
> @@ -0,0 +1,31 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (C) 2019 Microchip Technology Inc.
> + * Padmarao Begari 
> + */
> +
> +#include 
> +#include 
> +#include 
> +
> +#define MPFS_SYSREG_SOFT_RESET ((unsigned int *)0x20002088)
> +
> +int board_init(void)
> +{
> +   /* For now nothing to do here. */
> +
> +   return 0;
> +}
> +
> +#ifdef CONFIG_BOARD_EARLY_INIT_F

Can this be optionally turned off? If not, please select it in
BOARD_SPECIFIC_OPTIONS, and remove the #ifdef here.

> +int board_early_init_f(void)
> +{
> +   unsigned int val;

nits: should have a blank line here

> +   /* Reset uart peripheral */
> +   val = readl(MPFS_SYSREG_SOFT_RESET);
> +   val = (val & ~(1u << 5u));
> +   writel(val, MPFS_SYSREG_SOFT_RESET);
> +
> +   return 0;
> +}
> +#endif
> diff --git a/configs/microchip-mpfs-icicle_defconfig 
> b/configs/microchip-mpfs-icicle_defconfig
> new file mode 100644
> index 000..2d1bd4a
> --- /dev/null
> +++ b/configs/microchip-mpfs-icicle_defconfig
> @@ -0,0 +1,16 @@
> +CONFIG_RISCV=y
> +CONFIG_SYS_TEXT_BASE=0x8000
> 

Re: [U-Boot] Booting MX6 via Serial Download after DM conversion

2019-04-23 Thread Fabio Estevam
Hi Peng,

On Mon, Apr 22, 2019 at 11:00 PM Peng Fan  wrote:

> Honestly I am not familiar with imx_usb, we use mfgtool previously and not 
> uuu tool.
> Would you share where to download imx_usb and any doc,
> Then we will debug this issue.

You can get imx_usb_loader tool from
https://github.com/boundarydevices/imx_usb_loader

Install it, connect the board in USB download mode and then:

sudo ./imx_usb SPL
sudo ./imx_usb u-boot-dtb.img

I suggest you to try U-boot 2019.01 first, which works fine and then
2019.04, which is broken.

I could get imx usb loader to successfully load 2019.04 if I manually
change the defconfig like this:

--- a/configs/mx6sabresd_defconfig
+++ b/configs/mx6sabresd_defconfig
@@ -12,8 +12,6 @@ CONFIG_SPL_LIBDISK_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=1
 # CONFIG_SYS_MALLOC_F is not set
 CONFIG_FIT=y
-CONFIG_SPL_FIT_PRINT=y
-CONFIG_SPL_LOAD_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
 # CONFIG_CONSOLE_MUX is not set
 CONFIG_SYS_CONSOLE_IS_IN_ENV=y
@@ -21,7 +19,6 @@ CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
 CONFIG_SUPPORT_RAW_INITRD=y
 CONFIG_BOUNCE_BUFFER=y
 CONFIG_SPL_SEPARATE_BSS=y
-CONFIG_SPL_FIT_IMAGE_TINY=y
 CONFIG_SPL_FS_EXT4=y
 CONFIG_SPL_I2C_SUPPORT=y
 CONFIG_SPL_OS_BOOT=y
@@ -56,15 +53,10 @@ CONFIG_CMD_FS_GENERIC=y
 CONFIG_EFI_PARTITION=y
 # CONFIG_SPL_EFI_PARTITION is not set
 CONFIG_OF_CONTROL=y
-CONFIG_SPL_OF_CONTROL=y
 CONFIG_DEFAULT_DEVICE_TREE="imx6q-sabresd"
 CONFIG_OF_LIST="imx6q-sabresd imx6qp-sabresd imx6dl-sabresd"
-CONFIG_MULTI_DTB_FIT=y
-CONFIG_SPL_MULTI_DTB_FIT=y
-CONFIG_SPL_OF_LIST="imx6dl-sabresd imx6q-sabresd imx6qp-sabresd"
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
-CONFIG_SPL_DM=y
 CONFIG_USB_FUNCTION_FASTBOOT=y
 CONFIG_FASTBOOT_BUF_ADDR=0x1200
 CONFIG_FASTBOOT_BUF_SIZE=0x1000
@@ -95,6 +87,4 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
 CONFIG_CI_UDC=y
 CONFIG_USB_HOST_ETHER=y
 CONFIG_USB_ETHER_ASIX=y
-CONFIG_DM_VIDEO=y
-CONFIG_VIDEO_IPUV3=y
 # CONFIG_VIDEO_SW_CURSOR is not set
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Re: [U-Boot] [PATCH 1/4] riscv: hart_lottery and available harts feature can be seletable

2019-04-23 Thread Bin Meng
On Tue, Apr 23, 2019 at 8:14 PM Bin Meng  wrote:
>
> Hi Rick,
>
> On Tue, Apr 23, 2019 at 1:47 PM Andes  wrote:
> >
> > From: Rick Chen 
> >
>
> typo in the commit title: seletable -> selectable
>
> > In smp flow this two features only can be enabled when U-Boot
>
> this->these
>
> > boot from ram. It shall be disabled when U-Boot boot from flash.
>
> boot->boots
>
> >
> > Add CONFIG_HART_LOTTERY and CONFIG_AVAILABLE_HARTS to select

BTW: is it possible to use a single option for such feature, like
CONFIG_XIP? Basically these two options are used for the same reason.

> > this two features. Their default value will say YES for booting
>
> this->these
>
> > from ram.

Regards,
Bin
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Re: [U-Boot] [PATCH 4/4] riscv: configs: AE350 will use OF_PRIOR_STAGE when boot from ram

2019-04-23 Thread Bin Meng
Hi Rick,

On Tue, Apr 23, 2019 at 1:47 PM Andes  wrote:
>
> From: Rick Chen 
>

nits in the commit title: boot->booting

> When AE350 was booting from ram, use OF_PRIOR_STAGE instead
> of OF_PRIOR_STAGE.

This should be CONFIG_OF_BOARD

>
> Signed-off-by: Rick Chen 
> Cc: Greentime Hu 
> ---
>  configs/ae350_rv32_defconfig | 2 +-
>  configs/ae350_rv64_defconfig | 2 +-
>  2 files changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/configs/ae350_rv32_defconfig b/configs/ae350_rv32_defconfig
> index e13c7de..54b65f1 100644
> --- a/configs/ae350_rv32_defconfig
> +++ b/configs/ae350_rv32_defconfig
> @@ -14,7 +14,7 @@ CONFIG_CMD_SF_TEST=y
>  # CONFIG_CMD_SETEXPR is not set
>  CONFIG_BOOTP_PREFER_SERVERIP=y
>  CONFIG_CMD_CACHE=y
> -CONFIG_OF_BOARD=y
> +CONFIG_OF_PRIOR_STAGE=y
>  CONFIG_DEFAULT_DEVICE_TREE="ae350_32"
>  CONFIG_ENV_IS_IN_SPI_FLASH=y
>  CONFIG_NET_RANDOM_ETHADDR=y
> diff --git a/configs/ae350_rv64_defconfig b/configs/ae350_rv64_defconfig
> index a41f918..0ff4de8 100644
> --- a/configs/ae350_rv64_defconfig
> +++ b/configs/ae350_rv64_defconfig
> @@ -15,7 +15,7 @@ CONFIG_CMD_SF_TEST=y
>  # CONFIG_CMD_SETEXPR is not set
>  CONFIG_BOOTP_PREFER_SERVERIP=y
>  CONFIG_CMD_CACHE=y
> -CONFIG_OF_BOARD=y
> +CONFIG_OF_PRIOR_STAGE=y
>  CONFIG_DEFAULT_DEVICE_TREE="ae350_64"
>  CONFIG_ENV_IS_IN_SPI_FLASH=y
>  CONFIG_NET_RANDOM_ETHADDR=y

Regards,
Bin
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Re: [U-Boot] [PATCH 3/4] riscv: prior_stage_fdt_address only be used when OF_PRIOR_STAGE is enable

2019-04-23 Thread Bin Meng
Hi Rick,

On Tue, Apr 23, 2019 at 1:47 PM Andes  wrote:
>
> From: Rick Chen 
>

commit title should read: prior_stage_fdt_address should only be used
when OF_PRIOR_STAGE is enabled

> This patch will fix prior_stage_fdt_address write failure problem, when
> AE350 was booting from flash.
>
> When AE350 was booting from falsh, prior_stage_fdt_address will be in
> flash address, we shall avoid it to be written.
>
> Signed-off-by: Rick Chen 
> Cc: Greentime Hu 
> ---
>  arch/riscv/cpu/start.S | 2 ++
>  1 file changed, 2 insertions(+)
>
> diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
> index d030d4a..0e672e0 100644
> --- a/arch/riscv/cpu/start.S
> +++ b/arch/riscv/cpu/start.S
> @@ -111,7 +111,9 @@ call_board_init_f_0:
> bneztp, secondary_hart_loop
>  #endif
>
> +#  if CONFIG_IS_ENABLED(OF_PRIOR_STAGE)
> la  t0, prior_stage_fdt_address
> +#endif

I think you should also surround the declaration of
prior_stage_fdt_address in arch/riscv/cpu/cpu.c with OF_PRIOR_STAGE

> SREGs1, 0(t0)
>
> jal board_init_f_init_reserve
> --

Regards,
Bin
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Re: [U-Boot] [PATCH 2/4] riscv: configs: Support AE350 SMP boot from flash flow

2019-04-23 Thread Bin Meng
Hi Rick,

On Tue, Apr 23, 2019 at 1:47 PM Andes  wrote:
>
> From: Rick Chen 

nits in the commit title: boot->booting

>
> Add two defconfig to support AE350 SMP boot from flash

boot->bootings

> by disable CONFIG_HART_LOTTERY and CONFIG_AVAILABLE_HARTS.

disable->disabling

>
> Signed-off-by: Rick Chen 
> Cc: Greentime Hu 
> ---
>  configs/ae350_rv32_xip_defconfig | 37 +
>  configs/ae350_rv64_xip_defconfig | 38 ++
>  2 files changed, 75 insertions(+)
>  create mode 100644 configs/ae350_rv32_xip_defconfig
>  create mode 100644 configs/ae350_rv64_xip_defconfig
>
> diff --git a/configs/ae350_rv32_xip_defconfig 
> b/configs/ae350_rv32_xip_defconfig
> new file mode 100644
> index 000..1639367
> --- /dev/null
> +++ b/configs/ae350_rv32_xip_defconfig
> @@ -0,0 +1,37 @@
> +CONFIG_RISCV=y
> +CONFIG_HART_LOTTERY=n
> +CONFIG_AVAILABLE_HARTS=n

I think this should be:

# CONFIG_HART_LOTTERY is not set
# CONFIG_AVAILABLE_HARTS is not set

> +CONFIG_SYS_TEXT_BASE=0x8000
> +CONFIG_TARGET_AX25_AE350=y
> +CONFIG_DISTRO_DEFAULTS=y
> +CONFIG_NR_DRAM_BANKS=2
> +CONFIG_FIT=y
> +CONFIG_BOOTDELAY=3
> +CONFIG_BOARD_EARLY_INIT_F=y
> +CONFIG_SYS_PROMPT="RISC-V # "
> +CONFIG_CMD_IMLS=y
> +CONFIG_CMD_MMC=y
> +CONFIG_CMD_SF=y
> +CONFIG_CMD_SF_TEST=y
> +# CONFIG_CMD_SETEXPR is not set
> +CONFIG_BOOTP_PREFER_SERVERIP=y
> +CONFIG_CMD_CACHE=y
> +CONFIG_OF_BOARD=y
> +CONFIG_DEFAULT_DEVICE_TREE="ae350_32"
> +CONFIG_ENV_IS_IN_SPI_FLASH=y
> +CONFIG_NET_RANDOM_ETHADDR=y
> +CONFIG_MMC=y
> +CONFIG_FTSDC010=y
> +CONFIG_FTSDC010_SDIO=y
> +CONFIG_MTD_NOR_FLASH=y
> +CONFIG_FLASH_CFI_DRIVER=y
> +CONFIG_CFI_FLASH=y
> +CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
> +CONFIG_SYS_FLASH_CFI=y
> +CONFIG_SPI_FLASH=y
> +CONFIG_SPI_FLASH_MACRONIX=y
> +CONFIG_FTMAC100=y
> +CONFIG_BAUDRATE=38400
> +CONFIG_SYS_NS16550=y
> +CONFIG_SPI=y
> +CONFIG_ATCSPI200_SPI=y
> diff --git a/configs/ae350_rv64_xip_defconfig 
> b/configs/ae350_rv64_xip_defconfig
> new file mode 100644
> index 000..d6a502c
> --- /dev/null
> +++ b/configs/ae350_rv64_xip_defconfig
> @@ -0,0 +1,38 @@
> +CONFIG_RISCV=y
> +CONFIG_HART_LOTTERY=n
> +CONFIG_AVAILABLE_HARTS=n

ditto

> +CONFIG_SYS_TEXT_BASE=0x8000
> +CONFIG_TARGET_AX25_AE350=y
> +CONFIG_ARCH_RV64I=y
> +CONFIG_DISTRO_DEFAULTS=y
> +CONFIG_NR_DRAM_BANKS=2
> +CONFIG_FIT=y
> +CONFIG_BOOTDELAY=3
> +CONFIG_BOARD_EARLY_INIT_F=y
> +CONFIG_SYS_PROMPT="RISC-V # "
> +CONFIG_CMD_IMLS=y
> +CONFIG_CMD_MMC=y
> +CONFIG_CMD_SF=y
> +CONFIG_CMD_SF_TEST=y
> +# CONFIG_CMD_SETEXPR is not set
> +CONFIG_BOOTP_PREFER_SERVERIP=y
> +CONFIG_CMD_CACHE=y
> +CONFIG_OF_BOARD=y
> +CONFIG_DEFAULT_DEVICE_TREE="ae350_64"
> +CONFIG_ENV_IS_IN_SPI_FLASH=y
> +CONFIG_NET_RANDOM_ETHADDR=y
> +CONFIG_MMC=y
> +CONFIG_FTSDC010=y
> +CONFIG_FTSDC010_SDIO=y
> +CONFIG_MTD_NOR_FLASH=y
> +CONFIG_FLASH_CFI_DRIVER=y
> +CONFIG_CFI_FLASH=y
> +CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
> +CONFIG_SYS_FLASH_CFI=y
> +CONFIG_SPI_FLASH=y
> +CONFIG_SPI_FLASH_MACRONIX=y
> +CONFIG_FTMAC100=y
> +CONFIG_BAUDRATE=38400
> +CONFIG_SYS_NS16550=y
> +CONFIG_SPI=y
> +CONFIG_ATCSPI200_SPI=y

Regards,
Bin
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Re: [U-Boot] [PATCH 1/4] riscv: hart_lottery and available harts feature can be seletable

2019-04-23 Thread Bin Meng
Hi Rick,

On Tue, Apr 23, 2019 at 1:47 PM Andes  wrote:
>
> From: Rick Chen 
>

typo in the commit title: seletable -> selectable

> In smp flow this two features only can be enabled when U-Boot

this->these

> boot from ram. It shall be disabled when U-Boot boot from flash.

boot->boots

>
> Add CONFIG_HART_LOTTERY and CONFIG_AVAILABLE_HARTS to select
> this two features. Their default value will say YES for booting

this->these

> from ram.
>
> AE350 will encounter the the write failure problem since
> hart_lottery and available_harts_lock was not in ram address

was->is

> but in flash address when booing from flash.

booing->booting

>
> This patch can help to fix the failure problem when AE350 was

was->is

> booting from flash by disable this two features.

disable->disabling

>
> Signed-off-by: Rick Chen 
> Cc: Greentime Hu 
> ---
>  arch/riscv/Kconfig   | 21 +
>  arch/riscv/cpu/cpu.c |  4 
>  arch/riscv/cpu/start.S   |  9 -
>  arch/riscv/include/asm/global_data.h |  2 ++
>  arch/riscv/lib/asm-offsets.c |  2 ++
>  arch/riscv/lib/smp.c |  2 ++
>  6 files changed, 39 insertions(+), 1 deletion(-)
>
> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> index ae8ff7b..4354396 100644
> --- a/arch/riscv/Kconfig
> +++ b/arch/riscv/Kconfig
> @@ -162,6 +162,27 @@ config SBI_IPI
> default y if RISCV_SMODE
> depends on SMP
>
> +config HART_LOTTERY
> +   bool "Hart lottery support"

nits: I would use "hart"

> +   default y
> +   depends on SMP
> +   help
> + This will upport hart lottery, all harts have changce to become

upport->support, changce->chance

> + main hart. But if you say N here, hart 0 will be the main hart.
> + It only can be enabled when U-Boot boot from ram, but shall be

boot->boots

> + disabled when boot from flash.

boot->booting

> +
> +config AVAILABLE_HARTS
> +   bool "available harts support"
> +   default y
> +   depends on SMP
> +   depends on HART_LOTTERY
> +   help
> + This will help to record active harts and compare with dts' cpus.
> + So it will not send ipi to in-active harts.

in-active->inactive

> + It only can be enabled when U-Boot boot from ram, but shall be

boot->boots

> + disabled when boot from flash.

boot->booting

> +
>  config STACK_SIZE_SHIFT
> int
> default 13
> diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c
> index c32de8a..0add783 100644
> --- a/arch/riscv/cpu/cpu.c
> +++ b/arch/riscv/cpu/cpu.c
> @@ -16,13 +16,17 @@
>   * before the bss section is available.
>   */
>  phys_addr_t prior_stage_fdt_address __attribute__((section(".data")));
> +#ifdef CONFIG_HART_LOTTERY
>  u32 hart_lottery __attribute__((section(".data"))) = 0;
> +#endif
>
> +#ifdef CONFIG_AVAILABLE_HARTS
>  /*
>   * The main hart running U-Boot has acquired available_harts_lock until it 
> has
>   * finished initialization of global data.
>   */
>  u32 available_harts_lock = 1;
> +#endif
>
>  static inline bool supports_extension(char ext)
>  {
> diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
> index a4433fb..d030d4a 100644
> --- a/arch/riscv/cpu/start.S
> +++ b/arch/riscv/cpu/start.S
> @@ -98,6 +98,7 @@ call_board_init_f_0:
> mv  sp, a0
>  #endif
>
> +#ifdef CONFIG_HART_LOTTERY
> /*
>  * Pick hart to initialize global data and run U-Boot. The other harts
>  * wait for initialization to complete.
> @@ -106,6 +107,9 @@ call_board_init_f_0:
> li  s2, 1
> amoswap.w s2, t1, 0(t0)
> bnezs2, wait_for_gd_init
> +#else
> +   bneztp, secondary_hart_loop
> +#endif
>
> la  t0, prior_stage_fdt_address
> SREGs1, 0(t0)
> @@ -115,6 +119,7 @@ call_board_init_f_0:
> /* save the boot hart id to global_data */
> SREGtp, GD_BOOT_HART(gp)
>
> +#ifdef CONFIG_AVAILABLE_HARTS
> la  t0, available_harts_lock
> fence   rw, w
> amoswap.w zero, zero, 0(t0)
> @@ -135,13 +140,15 @@ wait_for_gd_init:
>
> fence   rw, w
> amoswap.w zero, zero, 0(t0)
> +#endif
>
> +#ifdef CONFIG_HART_LOTTERY
> /*
>  * Continue on hart lottery winner, others branch to
>  * secondary_hart_loop.
>  */
> bnezs2, secondary_hart_loop
> -

This blank line should not be deleted.

> +#endif
> /* Enable cache */
> jal icache_enable
> jal dcache_enable
> diff --git a/arch/riscv/include/asm/global_data.h 
> b/arch/riscv/include/asm/global_data.h
> index dffcd45..e2e8b65 100644
> --- a/arch/riscv/include/asm/global_data.h
> +++ b/arch/riscv/include/asm/global_data.h
> @@ -27,7 +27,9 @@ struct arch_global_data {
>  #ifdef CONFIG_SMP
> struct ipi_data ipi[CONFIG_NR_CPUS];
>  #endif
> +#ifdef CONFIG_AVAILABLE_HARTS
> ulong available_harts;
> +#endif
>  };

Re: [U-Boot] Pull request: goldsimon/u-boot

2019-04-23 Thread Marek Vasut
On 4/23/19 7:40 AM, Simon Goldschmidt wrote:
> On Mon, Apr 22, 2019 at 9:08 PM Marek Vasut  wrote:
>>
>> On 4/22/19 8:31 PM, Simon Goldschmidt wrote:
>>> The following changes since commit
>>> 6c5f8dd540d7a8eff244d4c27a09451ca12c8d20:
>>>
>>>   Merge branch 'master' of git://git.denx.de/u-boot-usb (2019-04-21
>>> 19:00:04 -0400)
>>>
>>> are available in the Git repository at:
>>>
>>>   https://github.com/goldsimon/u-boot.git
>>>
>>> for you to fetch changes up to 5ff194620a5ada0bf05d9dc2668d2233289742a6:
>>>
>>>   arm: socfpga: clean up board config files (2019-04-22 20:08:59 +0200)
>>
>> Applied, thanks.
> 
> Sorry, but I have to take that back. I've somehow managed to get a build error
> for socfpga_vining_fpga.
> 
> I'll send another one as soon as I have fixed this.

Subsequent patch please.

-- 
Best regards,
Marek Vasut
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