Re: [U-Boot] [PATCH v3] qemu-x86: Use config_distro_bootcmd
On Thu, Jul 4, 2019 at 1:46 AM Joshua Watt wrote: > > Converts qemu x86 machines to boot using distro_config. The intent is to > allow u-boot in qemu to be maximally compatible with many boot methods > without having to change the config. Previously, u-boot would only boot > in a very limited set of circumstances where there was a /boot/vmlinuz > on scsi 0:3 with no ramdisk. > > Signed-off-by: Joshua Watt > --- > configs/qemu-x86_64_defconfig | 1 + > configs/qemu-x86_defconfig| 1 + > doc/README.x86| 17 + > include/configs/qemu-x86.h| 25 + > 4 files changed, 44 insertions(+) > Reviewed-by: Bin Meng ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 2/3] pico-imx7d: Support distro boot for FIT image case
Hi Jun,
Le mar. 16 juil. 2019 à 09:48, Jun Nie a écrit :
> Support distro boot for pico imx7d in FIT image case.
>
> Signed-off-by: Jun Nie
> ---
> include/configs/pico-imx7d.h | 37 +++--
> 1 file changed, 11 insertions(+), 26 deletions(-)
>
> diff --git a/include/configs/pico-imx7d.h b/include/configs/pico-imx7d.h
> index 9101540..7b2bd00 100644
> --- a/include/configs/pico-imx7d.h
> +++ b/include/configs/pico-imx7d.h
> @@ -55,17 +55,17 @@
> /* When booting with FIT specify the node entry containing boot.scr */
> #if defined(CONFIG_FIT)
> #define PICO_BOOT_ENV \
> - "bootscr_fitimage_name=bootscr\0" \
> - "bootscriptaddr=0x8320\0" \
> - "fdtovaddr=0x8310\0" \
> - "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
> - "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
> - "mmcargs=setenv bootargs console=${console},${baudrate} " \
> - "rootwait rw;\0" \
> - "loadbootscript=" \
> - "load mmc ${mmcdev}:${mmcpart} ${bootscriptaddr}
> ${script};\0" \
> - "bootscript=echo Running bootscript from mmc ...; " \
> - "source ${bootscriptaddr}:${bootscr_fitimage_name}\0"
> + BOOTENV \
> + "fdtovaddr=0x8310\0"\
> + "scriptaddr=0x8320\0" \
> + "mmcargs=setenv bootargs console=${console},${baudrate} " \
> + "rootwait rw\0" \
> + "boot_a_script="\
> + "load ${devtype} ${devnum}:${distro_bootpart} " \
> + "${scriptaddr} ${prefix}${script}; "\
> + "iminfo ${scriptaddr};" \
> + "if test $? -eq 1; then hab_failsafe; fi;" \
> + "source ${scriptaddr}:bootscr\0"
> #else
> #define PICO_BOOT_ENV \
> "bootmenu_0=Boot using PICO-Hobbit baseboard=" \
> @@ -107,21 +107,6 @@
> "setup_emmc=mmc dev 0; gpt write mmc 0 $partitions; reset;\0" \
> PICO_BOOT_ENV
>
> -#if defined(CONFIG_FIT)
> -#define CONFIG_BOOTCOMMAND \
> - "mmc dev ${mmcdev};" \
> - "mmc dev ${mmcdev}; if mmc rescan; then " \
> - "if run loadbootscript; then " \
> - "iminfo ${bootscriptaddr};" \
> - "if test $? -eq 1; then hab_failsafe; fi;" \
> - "run bootscript; " \
> - "else " \
> - "echo Fail to load fitImage with boot script;" \
> - "hab_failsafe;" \
> - "fi; " \
> - "fi"
> -#endif
> -
> #define BOOT_TARGET_DEVICES(func) \
> func(MMC, mmc, 0) \
> func(USB, usb, 0) \
> --
> 2.7.4
>
> It's work from my side
for my setup i disable iminfo and hab_failsafe
See log:
run bootcmd
switch to partitions #0, OK
mmc0(part 0) is current device
Scanning mmc 0:1...
Found U-Boot script /boot.scr
245 bytes read in 8 ms (29.3 KiB/s)
Unknown command 'iminfo' - try 'help'
Unknown command 'hab_failsafe' - try 'help'
## Executing script at 8320
8961308 bytes read in 217 ms (39.4 MiB/s)
## Loading kernel from FIT Image at 8600 ...
Using 'c...@imx7d-pico-pi.dtb' configuration
Trying 'kernel@1' kernel subimage
Description: Linux kernel
Type: Kernel Image
Compression: uncompressed
Data Start: 0x86000114
Data Size:8925040 Bytes = 8.5 MiB
Architecture: ARM
OS: Linux
Load Address: 0x80008000
Entry Point: 0x80008000
Hash algo:sha1
Hash value: 7d8af1016b4cf8ea90fa1a767bfbeda052043f6c
Verifying Hash Integrity ... sha1+ OK
## Loading fdt from FIT Image at 8600 ...
Using 'c...@imx7d-pico-pi.dtb' configuration
Trying 'f...@imx7d-pico-pi.dtb' fdt subimage
Description: Flattened Device Tree blob
Type: Flat Device Tree
Compression: uncompressed
Data Start: 0x86883188
Data Size:34325 Bytes = 33.5 KiB
Architecture: ARM
Hash algo:sha1
Hash value: 75c81556e9bb9681cd14c96c4627da04205b2583
Verifying Hash Integrity ... sha1+ OK
Booting using the fdt blob at 0x86883188
Loading Kernel Image ... OK
Using Device Tree in place at 86883188, end 8688e79c
Starting kernel ...
Tested-by: Joris Offouga
Best Regards,
Joris Offouga
> ___
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>
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Re: [U-Boot] [PATCH v5 0/4] SiFive SPI MMC Support
On Wed, Jul 17, 2019 at 10:46 AM Jagan Teki wrote: > > On Wed, Jul 17, 2019 at 10:00 AM Anup Patel wrote: > > > > On Wed, Jul 17, 2019 at 9:38 AM Jagan Teki > > wrote: > > > > > > On Wed, Jul 17, 2019 at 9:20 AM Anup Patel wrote: > > > > > > > > This patchset adds: > > > > 1. SiFive SPI driver > > > > 2. New MMC SPI driver based on DM_MMC and DM_SPI > > > > 3. Enables SiFive SPI driver and MMC SPI driver for SiFive Unleashed > > > > board > > > > > > > > With this patch series, we can now load files from SD card on SiFive > > > > Unleashed board. Many thanks to Bhargav for porting SiFive SPI driver > > > > and updating MMC SPI driver for us. > > > > > > > > These patches can be also found in riscv_unleashed_mmc_spi_v5 branch of: > > > > https//github.com/avpatel/u-boot.git > > > > > > > > Changes since v4: > > > > - Renamed kconfig option from SIFIVE_SPI to SPI_SIFIVE for consistency > > > > - Added dummy claim_bus() and release_bus() callbacks > > > > > > > > Changes since v3: > > > > - Removed PATCH2, PATCH3, and PATCH4 because these are already merged > > > > - Added separate patch to use SPI_XFER_xyz flags in MMC_SPI driver > > > > - Use readl/writel directly instead of sifive_spi_read/sifi_spi_write > > > > - Use SPI_XFER_xyz flags to enable/disable chipselect > > > > - Remove unused callback sifive_spi_cs_info() > > > > > > > > Changes since v2: > > > > - Minor fixes in PATCH1 which adds SiFive SPI driver > > > > - Removed CONFIG_MMC_SPI_xyz from scripts/config_whitelist.txt > > > > - Removed cmd/mmc_spi and all its refrences as separate patch > > > > - Removed DM_SPI and DM_MMC from SiFive FU540 Kconfig > > > > > > > > Changes since v1: > > > > - Make response matching part belongs to mmc_spi_sendcmd() > > > > - Match response to zero for SEND_STATUS (CMD13) > > > > - Add separate patch for updating SiFive FU540 Documentation > > > > > > > > Anup Patel (2): > > > > mmc: mmc_spi: Use SPI_XFER_BEGIN and SPI_XFER_END flags > > > > doc: sifive-fu540: Update README for SiFive SPI and MMC SPI drivers > > > > > > > > Bhargav Shah (2): > > > > spi: Add SiFive SPI driver > > > > riscv: sifive: fu540: Enable SiFive SPI and MMC SPI drivers > > > > > > > > board/sifive/fu540/Kconfig | 6 + > > > > doc/README.sifive-fu540| 4 +- > > > > drivers/mmc/mmc_spi.c | 4 +- > > > > drivers/spi/Kconfig| 8 + > > > > drivers/spi/Makefile | 1 + > > > > drivers/spi/spi-sifive.c | 375 + > > > > 6 files changed, 394 insertions(+), 4 deletions(-) > > > > create mode 100644 drivers/spi/spi-sifive.c > > > > > > I would like to pick entire series on spi tree, but it has some boards > > > changes so I would like to ask the board maintainers to give a > > > permissions to do so, if not possible I can take only spi changes. > > > > Last 2 patches depend on below mentioned series so won't apply > > for you. I guess you can pickup SPI driver and MMC_SPI change. > > Haa., only SPI driver rest has dependencies on respective trees so I > picked spi driver only. Thanks Jagan. Regards, Anup ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v5 1/4] mmc: mmc_spi: Use SPI_XFER_BEGIN and SPI_XFER_END flags
On Wed, Jul 17, 2019 at 9:40 AM Jagan Teki wrote: > > Hi Peng, > > On Wed, Jul 17, 2019 at 9:34 AM Jagan Teki wrote: > > > > On Wed, Jul 17, 2019 at 9:20 AM Anup Patel wrote: > > > > > > Most DM based SPI host controller drivers use SPI_XFER_BEGIN and > > > SPI_XFER_END flags to enable/disable slave chip select. > > > > > > This patch extends MMC SPI driver to pass SPI_XFER_BEGIN flag when > > > MMC command is send at start and pass SPI_XFER_END flag using a > > > dummy transfer (of bitlen = 0) at the end of MMC command. > > > > > > Suggested-by: Jagan Teki > > > Signed-off-by: Anup Patel > > > > Reviewed-by: Jagan Teki > > Would like to pick this via spi tree, let me know if it fine for you? Look like it has dependency on your tree, please take this from mmc. ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v6 2/4] spi: Add SiFive SPI driver
On Wed, Jul 17, 2019 at 9:53 AM Anup Patel wrote: > > From: Bhargav Shah > > This patch adds SiFive SPI driver. The driver is 100% DM driver > and it determines input clock using clk framework. > > The SiFive SPI block is found on SiFive FU540 SOC and is used to > access flash and MMC devices on SiFive Unleashed board. > > This driver implementation is inspired from the Linux SiFive SPI > driver available in Linux-5.2 or higher and SiFive FSBL sources. > > Signed-off-by: Bhargav Shah > Signed-off-by: Anup Patel > Reviewed-by: Bin Meng > Tested-by: Bin Meng > --- Applied to u-boot-spi/master ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v5 0/4] SiFive SPI MMC Support
On Wed, Jul 17, 2019 at 10:00 AM Anup Patel wrote: > > On Wed, Jul 17, 2019 at 9:38 AM Jagan Teki wrote: > > > > On Wed, Jul 17, 2019 at 9:20 AM Anup Patel wrote: > > > > > > This patchset adds: > > > 1. SiFive SPI driver > > > 2. New MMC SPI driver based on DM_MMC and DM_SPI > > > 3. Enables SiFive SPI driver and MMC SPI driver for SiFive Unleashed board > > > > > > With this patch series, we can now load files from SD card on SiFive > > > Unleashed board. Many thanks to Bhargav for porting SiFive SPI driver > > > and updating MMC SPI driver for us. > > > > > > These patches can be also found in riscv_unleashed_mmc_spi_v5 branch of: > > > https//github.com/avpatel/u-boot.git > > > > > > Changes since v4: > > > - Renamed kconfig option from SIFIVE_SPI to SPI_SIFIVE for consistency > > > - Added dummy claim_bus() and release_bus() callbacks > > > > > > Changes since v3: > > > - Removed PATCH2, PATCH3, and PATCH4 because these are already merged > > > - Added separate patch to use SPI_XFER_xyz flags in MMC_SPI driver > > > - Use readl/writel directly instead of sifive_spi_read/sifi_spi_write > > > - Use SPI_XFER_xyz flags to enable/disable chipselect > > > - Remove unused callback sifive_spi_cs_info() > > > > > > Changes since v2: > > > - Minor fixes in PATCH1 which adds SiFive SPI driver > > > - Removed CONFIG_MMC_SPI_xyz from scripts/config_whitelist.txt > > > - Removed cmd/mmc_spi and all its refrences as separate patch > > > - Removed DM_SPI and DM_MMC from SiFive FU540 Kconfig > > > > > > Changes since v1: > > > - Make response matching part belongs to mmc_spi_sendcmd() > > > - Match response to zero for SEND_STATUS (CMD13) > > > - Add separate patch for updating SiFive FU540 Documentation > > > > > > Anup Patel (2): > > > mmc: mmc_spi: Use SPI_XFER_BEGIN and SPI_XFER_END flags > > > doc: sifive-fu540: Update README for SiFive SPI and MMC SPI drivers > > > > > > Bhargav Shah (2): > > > spi: Add SiFive SPI driver > > > riscv: sifive: fu540: Enable SiFive SPI and MMC SPI drivers > > > > > > board/sifive/fu540/Kconfig | 6 + > > > doc/README.sifive-fu540| 4 +- > > > drivers/mmc/mmc_spi.c | 4 +- > > > drivers/spi/Kconfig| 8 + > > > drivers/spi/Makefile | 1 + > > > drivers/spi/spi-sifive.c | 375 + > > > 6 files changed, 394 insertions(+), 4 deletions(-) > > > create mode 100644 drivers/spi/spi-sifive.c > > > > I would like to pick entire series on spi tree, but it has some boards > > changes so I would like to ask the board maintainers to give a > > permissions to do so, if not possible I can take only spi changes. > > Last 2 patches depend on below mentioned series so won't apply > for you. I guess you can pickup SPI driver and MMC_SPI change. Haa., only SPI driver rest has dependencies on respective trees so I picked spi driver only. ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [RFC PATCH 9/9] doc: board: Add Intel Crown Bay board doc
Hi Heinrich, On Wed, Jul 17, 2019 at 2:03 AM Heinrich Schuchardt wrote: > > On 7/16/19 6:42 PM, Bin Meng wrote: > > This extracts Intel Crown Bay board specific information from > > README.x86, converts plain text documentation to reST format and > > adds it to Sphinx TOC tree. No essential content change. > > > > Signed-off-by: Bin Meng > > > > --- > > > > doc/README.x86 | 37 - > > doc/board/index.rst | 2 ++ > > doc/board/intel/crownbay.rst | 49 > > > > doc/board/intel/index.rst| 4 > > 4 files changed, 55 insertions(+), 37 deletions(-) > > create mode 100644 doc/board/intel/crownbay.rst > > create mode 100644 doc/board/intel/index.rst > > > > diff --git a/doc/README.x86 b/doc/README.x86 > > index 8e0a3f3..8077ff3 100644 > > --- a/doc/README.x86 > > +++ b/doc/README.x86 > > @@ -203,43 +203,6 @@ Flash map for samus / broadwell: > > > > --- > > > > -Intel Crown Bay specific instructions for bare mode: > > - > > -U-Boot support of Intel Crown Bay board [4] relies on a binary blob called > > -Firmware Support Package [5] to perform all the necessary initialization > > steps > > -as documented in the BIOS Writer Guide, including initialization of the > > CPU, > > -memory controller, chipset and certain bus interfaces. > > - > > -Download the Intel FSP for Atom E6xx series and Platform Controller Hub > > EG20T, > > -install it on your host and locate the FSP binary blob. Note this platform > > -also requires a Chipset Micro Code (CMC) state machine binary to be > > present in > > -the SPI flash where u-boot.rom resides, and this CMC binary blob can be > > found > > -in this FSP package too. > > - > > -* ./FSP/QUEENSBAY_FSP_GOLD_001_20-DECEMBER-2013.fd > > -* ./Microcode/C0_22211.BIN > > - > > -Rename the first one to fsp.bin and second one to cmc.bin and put them in > > the > > -board directory. > > - > > -Note the FSP release version 001 has a bug which could cause random endless > > -loop during the FspInit call. This bug was published by Intel although > > Intel > > -did not describe any details. We need manually apply the patch to the FSP > > -binary using any hex editor (eg: bvi). Go to the offset 0x1fcd8 of the FSP > > -binary, change the following five bytes values from orginally E8 42 FF FF > > FF > > -to B8 00 80 0B 00. > > - > > -As for the video ROM, you need manually extract it from the Intel provided > > -BIOS for Crown Bay here [6], using the AMI MMTool [7]. Check PCI option ROM > > -ID 8086:4108, extract and save it as vga.bin in the board directory. > > - > > -Now you can build U-Boot and obtain u-boot.rom > > - > > -$ make crownbay_defconfig > > -$ make all > > - > > > > - > > Intel Cougar Canyon 2 specific instructions for bare mode: > > > > This uses Intel FSP for 3rd generation Intel Core and Intel Celeron > > processors > > diff --git a/doc/board/index.rst b/doc/board/index.rst > > index 4a65def..34e59de 100644 > > --- a/doc/board/index.rst > > +++ b/doc/board/index.rst > > @@ -4,3 +4,5 @@ Board-specific doc > > > > .. toctree:: > > :maxdepth: 2 > > + > > + intel/index > > diff --git a/doc/board/intel/crownbay.rst b/doc/board/intel/crownbay.rst > > new file mode 100644 > > index 000..d77cece > > --- /dev/null > > +++ b/doc/board/intel/crownbay.rst > > @@ -0,0 +1,49 @@ > > +.. SPDX-License-Identifier: GPL-2.0+ > > + > > +:author: Bin Meng > > + > > +.. toctree:: > > + :maxdepth: 2 > > + > > +Intel CrownBay CRB > > +== > > + > > +U-Boot support of Intel Crown Bay board `[1]`_ relies on a binary blob > > called > > +Firmware Support Package `[2]`_ to perform all the necessary initialization > > +steps as documented in the BIOS Writer Guide, including initialization of > > the > > +CPU, memory controller, chipset and certain bus interfaces. > > + > > +Download the Intel FSP for Atom E6xx series and Platform Controller Hub > > EG20T, > > +install it on your host and locate the FSP binary blob. Note this platform > > +also requires a Chipset Micro Code (CMC) state machine binary to be > > present in > > +the SPI flash where u-boot.rom resides, and this CMC binary blob can be > > found > > +in this FSP package too. > > + > > +* ./FSP/QUEENSBAY_FSP_GOLD_001_20-DECEMBER-2013.fd > > +* ./Microcode/C0_22211.BIN > > + > > +Rename the first one to fsp.bin and second one to cmc.bin and put them in > > the > > +board directory. > > + > > +Note the FSP release version 001 has a bug which could cause random endless > > +loop during the FspInit call. This bug was published by Intel although > > Intel > > +did not describe any details. We need manually apply the patch to the FSP > > +binary using any hex editor (eg: bvi). Go to the offset 0x1fcd8 of the FSP > > +binary, change the following five bytes values from orginally E8 42 FF FF > > FF > > +to B8 00 80 0B 00. > > + > > +As for the video ROM, you need manually extract it from the
[U-Boot] [PATCH v1] gpio: fixes for gpio-hog support
recently added gpio hog patch was "in discussion"
state with Simon Glass. This patch now adds most
of comments from Simon Glass.
Signed-off-by: Heiko Schocher
---
clean travis build, see result:
https://travis-ci.org/hsdenx/u-boot-test/builds/558774593
Based on mainline:
6070ef409c - Merge branch '2019-07-12-master-imports'
Tom applied version 4 of the patchset, but patch is
in discussion with Simon and I prepared already a v5
This patch includes now comments from Simon:
- add example for line-name in Documentation
- drop .gpio-hog suffix in Documentation
as not longer needed.
- rework gpio_hog_lookup_name() which now returns
error code and pointer to gpio desc is passed.
- rename DM_GPIO_HOG to GPIO_HOG
- set device name only if line-name property is set
- remove dm_gpio_set_dir() call as this is already done
through gpio_dev_request_index()
- check some error codes
- tried to add a comment to gpio_dev_request_index())
and renamed function paramter "dev" to "gpio_dev"
- use IS_ENABLED()
- fix comments for gpio_dev_request_index()
- add warning if probing one gpio_hog fails and continue
with probing the next gpio hog.
not yet implemented:
- question if gpio_desc can be stored in private device
data, but this can be fixed later.
common/board_r.c | 4 +-
doc/device-tree-bindings/gpio/gpio.txt | 17 ++--
drivers/gpio/Kconfig | 2 +-
drivers/gpio/gpio-uclass.c | 103 ++---
include/asm-generic/gpio.h | 12 +--
5 files changed, 96 insertions(+), 42 deletions(-)
diff --git a/common/board_r.c b/common/board_r.c
index abc31b17b8..e7ce11c30a 100644
--- a/common/board_r.c
+++ b/common/board_r.c
@@ -49,7 +49,7 @@
#include
#include
#include
-#if defined(CONFIG_DM_GPIO_HOG)
+#if defined(CONFIG_GPIO_HOG)
#include
#endif
@@ -799,7 +799,7 @@ static init_fnc_t init_sequence_r[] = {
#ifdef CONFIG_CMD_NET
initr_ethaddr,
#endif
-#if defined(CONFIG_DM_GPIO_HOG)
+#if defined(CONFIG_GPIO_HOG)
gpio_hog_probe_all,
#endif
#ifdef CONFIG_BOARD_LATE_INIT
diff --git a/doc/device-tree-bindings/gpio/gpio.txt
b/doc/device-tree-bindings/gpio/gpio.txt
index e774439369..e146917ff3 100644
--- a/doc/device-tree-bindings/gpio/gpio.txt
+++ b/doc/device-tree-bindings/gpio/gpio.txt
@@ -252,6 +252,7 @@ Example:
boot_rescue {
gpio-hog;
input;
+line-name = "foo-bar-gpio";
gpios = <7 GPIO_ACTIVE_LOW>;
};
};
@@ -259,9 +260,13 @@ Example:
For the above Example you can than access the gpio in your boardcode
with:
-desc = gpio_hog_lookup_name("boot_rescue.gpio-hog");
-if (desc) {
-if (dm_gpio_get_value(desc))
-printf("\nBooting into Rescue System\n");
- else
- printf("\nBoot normal\n");
+ struct gpio_desc *desc;
+ int ret;
+
+ ret = gpio_hog_lookup_name("boot_rescue", );
+ if (ret)
+ return;
+ if (dm_gpio_get_value(desc) == 1)
+ printf("\nBooting into Rescue System\n");
+ else if (dm_gpio_get_value(desc) == 0)
+ printf("\nBoot normal\n");
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index fa1c99700f..3f1a24013c 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -14,7 +14,7 @@ config DM_GPIO
particular GPIOs that they provide. The uclass interface
is defined in include/asm-generic/gpio.h.
-config DM_GPIO_HOG
+config GPIO_HOG
bool "Enable GPIO hog support"
depends on DM_GPIO
default n
diff --git a/drivers/gpio/gpio-uclass.c b/drivers/gpio/gpio-uclass.c
index 308d0863ad..01cfa2f788 100644
--- a/drivers/gpio/gpio-uclass.c
+++ b/drivers/gpio/gpio-uclass.c
@@ -144,7 +144,7 @@ static int gpio_find_and_xlate(struct gpio_desc *desc,
return gpio_xlate_offs_flags(desc->dev, desc, args);
}
-#if defined(CONFIG_DM_GPIO_HOG)
+#if defined(CONFIG_GPIO_HOG)
struct gpio_hog_priv {
struct gpio_desc gpiod;
@@ -181,9 +181,8 @@ static int gpio_hog_ofdata_to_platdata(struct udevice *dev)
return ret;
}
nodename = dev_read_string(dev, "line-name");
- if (!nodename)
- nodename = dev_read_name(dev);
- device_set_name(dev, nodename);
+ if (nodename)
+ device_set_name(dev, nodename);
return 0;
}
@@ -202,9 +201,15 @@ static int gpio_hog_probe(struct udevice *dev)
dev->name);
return ret;
}
- dm_gpio_set_dir(>gpiod);
- if (plat->gpiod_flags == GPIOD_IS_OUT)
- dm_gpio_set_value(>gpiod, plat->value);
+
+ if (plat->gpiod_flags == GPIOD_IS_OUT) {
+ ret = dm_gpio_set_value(>gpiod, plat->value);
+ if (ret < 0) {
+
[U-Boot] [PATCH v5 5/8] x86: slimbootloader: Set TSC information for timer driver
Slim Bootloader provides TSC clock information in its performance
info hob. For now, TSC clock information is only used for timer driver
from the performance info hob.
- Get TSC frequency from performance info hob
- Set tsc_base and clock_rate for timer driver
Signed-off-by: Aiden Park
Reviewed-by: Bin Meng
---
Changes in v3:
* Use HOB function from the common HOB library
arch/x86/cpu/slimbootloader/slimbootloader.c | 34 +++
.../asm/arch-slimbootloader/slimbootloader.h | 30
2 files changed, 64 insertions(+)
diff --git a/arch/x86/cpu/slimbootloader/slimbootloader.c
b/arch/x86/cpu/slimbootloader/slimbootloader.c
index 9f3a61ec61..2153d2ac66 100644
--- a/arch/x86/cpu/slimbootloader/slimbootloader.c
+++ b/arch/x86/cpu/slimbootloader/slimbootloader.c
@@ -4,9 +4,43 @@
*/
#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/**
+ * This sets tsc_base and clock_rate for early_timer and tsc_timer.
+ * The performance info guid hob has all performance timestamp data, but
+ * the only tsc frequency info is used for the timer driver for now.
+ */
+static void tsc_init(void)
+{
+ struct performance_info *data = NULL;
+ const struct efi_guid guid = LOADER_PERFORMANCE_INFO_GUID;
+
+ if (!gd->arch.hob_list)
+ panic("hob list not found!");
+
+ gd->arch.tsc_base = rdtsc();
+ debug("tsc_base=0x%llx\n", gd->arch.tsc_base);
+
+ data = (struct performance_info *)
+ hob_get_guid_hob_data(gd->arch.hob_list, NULL, );
+
+ if (!data) {
+ debug("performance info hob not found\n");
+ return;
+ }
+
+ /* frequency is in KHz, so to Hz */
+ gd->arch.clock_rate = data->frequency * 1000;
+ debug("freq=0x%lx\n", gd->arch.clock_rate);
+}
int arch_cpu_init(void)
{
+ tsc_init();
+
return x86_cpu_init_f();
}
diff --git a/arch/x86/include/asm/arch-slimbootloader/slimbootloader.h
b/arch/x86/include/asm/arch-slimbootloader/slimbootloader.h
index 5a0994544a..e0edbdddf5 100644
--- a/arch/x86/include/asm/arch-slimbootloader/slimbootloader.h
+++ b/arch/x86/include/asm/arch-slimbootloader/slimbootloader.h
@@ -27,6 +27,15 @@
{ 0xbb, 0x98, 0x95, 0x8d, 0x62, 0xde, 0x87, 0xf1 } \
}
+/**
+ * A GUID to get boot performance info hob which is provided by Slim Bootloader
+ */
+#define LOADER_PERFORMANCE_INFO_GUID \
+ { \
+ 0x868204be, 0x23d0, 0x4ff9, \
+ { 0xac, 0x34, 0xb9, 0x95, 0xac, 0x04, 0xb1, 0xb9 } \
+ }
+
/**
* A single entry of memory map information
*
@@ -71,6 +80,27 @@ struct serial_port_info {
u32 rsvd1;
} __packed;
+/**
+ * This includes timestamp data which has been collected in Slim Bootloader
+ * stages from the reset vector. In addition, this has TSC frequency in KHz to
+ * calculate each timestamp.
+ *
+ * @rev : revision of performance_info structure. currently 1.
+ * @rsvd : padding for alignment
+ * @count : the number of collected timestamp data
+ * @flags : only used in Slim Bootloader
+ * @frequency: tsc frequency in KHz
+ * @timestamp: the array of timestamp data which has 64-bit tsc value
+ */
+struct performance_info {
+ u8 rev;
+ u8 rsvd[3];
+ u16 count;
+ u16 flags;
+ u32 frequency;
+ u64 timestamp[0];
+} __packed;
+
/**
* This includes all memory map entries which is sorted based on physical start
* address, from low to high, and carved out reserved, acpi nvs, acpi reclaim
--
2.20.1
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[U-Boot] [PATCH v5 6/8] x86: slimbootloader: Add a slimbootloader device tree
Add a new device tree which has very minimum nodes
- x86 reset
- x86 tsc_timer
- x86 pci
- Slim Bootloader serial
Signed-off-by: Aiden Park
Reviewed-by: Bin Meng
---
Changes in v3:
* Move slimbootloader.dtb before baytrail_som-db5800-som-6867.dtb
arch/x86/dts/Makefile | 1 +
arch/x86/dts/slimbootloader.dts | 27 +++
2 files changed, 28 insertions(+)
create mode 100644 arch/x86/dts/slimbootloader.dts
diff --git a/arch/x86/dts/Makefile b/arch/x86/dts/Makefile
index fa717bc096..d4bdf62be6 100644
--- a/arch/x86/dts/Makefile
+++ b/arch/x86/dts/Makefile
@@ -18,6 +18,7 @@ dtb-y += bayleybay.dtb \
qemu-x86_i440fx.dtb \
qemu-x86_q35.dtb \
theadorable-x86-dfi-bt700.dtb \
+ slimbootloader.dtb \
baytrail_som-db5800-som-6867.dtb
targets += $(dtb-y)
diff --git a/arch/x86/dts/slimbootloader.dts b/arch/x86/dts/slimbootloader.dts
new file mode 100644
index 00..d04095c4f8
--- /dev/null
+++ b/arch/x86/dts/slimbootloader.dts
@@ -0,0 +1,27 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Intel Corporation
+ */
+
+/dts-v1/;
+
+/include/ "skeleton.dtsi"
+/include/ "reset.dtsi"
+/include/ "tsc_timer.dtsi"
+
+/ {
+ model = "slimbootloader x86 payload";
+ compatible = "slimbootloader,x86-payload";
+
+ chosen {
+ stdout-path =
+ };
+
+ serial: serial {
+ compatible = "intel,slimbootloader-uart";
+ };
+
+ pci {
+ compatible = "pci-x86";
+ };
+};
--
2.20.1
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[U-Boot] [PATCH v5 8/8] x86: Skip setting up MTRRs in slimbootloader
The setting up MTRRs have already been done in previous
Slim Bootloader stages.
Signed-off-by: Aiden Park
Reviewed-by: Bin Meng
---
arch/x86/lib/init_helpers.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/x86/lib/init_helpers.c b/arch/x86/lib/init_helpers.c
index 0481f453ca..5e19f13720 100644
--- a/arch/x86/lib/init_helpers.c
+++ b/arch/x86/lib/init_helpers.c
@@ -18,7 +18,8 @@ __weak ulong board_get_usable_ram_top(ulong total_size)
int init_cache_f_r(void)
{
-#if CONFIG_IS_ENABLED(X86_32BIT_INIT) && !defined(CONFIG_HAVE_FSP)
+#if CONFIG_IS_ENABLED(X86_32BIT_INIT) && !defined(CONFIG_HAVE_FSP) && \
+ !defined(CONFIG_SYS_SLIMBOOTLOADER)
int ret;
ret = mtrr_commit(false);
--
2.20.1
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[U-Boot] [PATCH v5 7/8] board: intel: Add new slimbootloader board
Add slimbootloader board to run U-boot as a Slim Bootloader payload - Add new board/intel/slimbootloader directory with minimum codes - Add slimbootloader configuration files - Add README in board/intel/slimbootloader Signed-off-by: Aiden Park Reviewed-by: Bin Meng --- Changes in v5: * Remove X86_LOAD_FROM_32_BIT from slimbootloader_defconfig Changes in v3: * Remove VENDOR_SLIMBOOTLOADER * Use VENDOR_INTEL * Move slimbootloader under board/intel/ * Enable generic CONFIGs in slimbootloader_defconfig * Add more description in board/intel/slimbootloader/README board/intel/Kconfig | 14 +++ board/intel/slimbootloader/Kconfig | 51 board/intel/slimbootloader/Makefile | 5 + board/intel/slimbootloader/README | 133 board/intel/slimbootloader/slimbootloader.c | 17 +++ board/intel/slimbootloader/start.S | 9 ++ configs/slimbootloader_defconfig| 21 include/configs/slimbootloader.h| 59 + 8 files changed, 309 insertions(+) create mode 100644 board/intel/slimbootloader/Kconfig create mode 100644 board/intel/slimbootloader/Makefile create mode 100644 board/intel/slimbootloader/README create mode 100644 board/intel/slimbootloader/slimbootloader.c create mode 100644 board/intel/slimbootloader/start.S create mode 100644 configs/slimbootloader_defconfig create mode 100644 include/configs/slimbootloader.h diff --git a/board/intel/Kconfig b/board/intel/Kconfig index 5131836cb0..01702ae502 100644 --- a/board/intel/Kconfig +++ b/board/intel/Kconfig @@ -73,6 +73,19 @@ config TARGET_MINNOWMAX Note that PCIE_ECAM_BASE is set up by the FSP so the value used by U-Boot matches that value. +config TARGET_SLIMBOOTLOADER + bool "slimbootloader" + help + This target is used for running U-Boot on top of Slim Bootloader + boot firmware as a payload. Slim Bootloader does memory initialization + and silicon initialization, and it passes necessary information in + HOB(Hand Off Block) to a payload. The payload consumes HOB data + which is generated by Slim Bootloader for its driver initialization. + Slim Bootloader consumes FSP and its HOB, but FSP HOB is cleared + Before launching a payload. Instead, Slim Bootloader generates its + HOB data such as memory info, serial port info and so on. + Refer to board/intel/slimbootloader/README for the details. + endchoice source "board/intel/bayleybay/Kconfig" @@ -82,5 +95,6 @@ source "board/intel/crownbay/Kconfig" source "board/intel/edison/Kconfig" source "board/intel/galileo/Kconfig" source "board/intel/minnowmax/Kconfig" +source "board/intel/slimbootloader/Kconfig" endif diff --git a/board/intel/slimbootloader/Kconfig b/board/intel/slimbootloader/Kconfig new file mode 100644 index 00..b0c15f4ba2 --- /dev/null +++ b/board/intel/slimbootloader/Kconfig @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2019 Intel Corporation + +if TARGET_SLIMBOOTLOADER + +config SYS_BOARD + default "slimbootloader" + +config SYS_VENDOR + default "intel" + +config SYS_SOC + default "slimbootloader" + +config SYS_TEXT_BASE + default 0x0010 + +comment "slimbootloader-specific options" + +config SYS_CONFIG_NAME + string "Board configuration file" + default "slimbootloader" + help + This option selects the board configuration file in include/configs/ + directory to be used to build U-Boot for Slim Bootloader. + +config DEFAULT_DEVICE_TREE + string "Board Device Tree Source (dts) file" + default "slimbootloader" + help + This option selects the board Device Tree Source (dts) file in + arch/x86/dts/ directory to be used to build U-Boot for Slim Bootloader. + +config SYS_CAR_ADDR + hex "Board specific Cache-As-RAM (CAR) address" + default 0x + help + This option specifies the board specific Cache-As-RAM (CAR) address. + But, CAR is not required for Slim Bootloader environment since it + has already initialized memory and launched u-boot as a payload. + +config SYS_CAR_SIZE + hex "Board specific Cache-As-RAM (CAR) size" + default 0x + help + This option specifies the board specific Cache-As-RAM (CAR) size. + But, CAR is not required for Slim Bootloader environment since it + has already initialized memory and launched u-boot as a payload. + +endif diff --git a/board/intel/slimbootloader/Makefile b/board/intel/slimbootloader/Makefile new file mode 100644 index 00..fd8fa98a8d --- /dev/null +++ b/board/intel/slimbootloader/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2019 Intel Corporation + +obj-y += start.o slimbootloader.o diff --git a/board/intel/slimbootloader/README
[U-Boot] [PATCH v5 3/8] x86: slimbootloader: Add memory configuration
Slim Bootloader provides memory map info thru its HOB list pointer.
Configure memory size and relocation memory from the HOB data, and
provide e820 entries as well.
- Get memory size from the memory map info hob
- Set ram top for U-Boot relocation lower than 4GB
- Provide e820 entries from the memory map info hob
Signed-off-by: Aiden Park
Reviewed-by: Bin Meng
---
Changes in v3:
* Use HOB function from the common HOB library
* Add more description
arch/x86/cpu/slimbootloader/Makefile | 2 +-
arch/x86/cpu/slimbootloader/dram.c| 151 ++
.../asm/arch-slimbootloader/slimbootloader.h | 44 +
3 files changed, 196 insertions(+), 1 deletion(-)
create mode 100644 arch/x86/cpu/slimbootloader/dram.c
diff --git a/arch/x86/cpu/slimbootloader/Makefile
b/arch/x86/cpu/slimbootloader/Makefile
index 627a721e8c..05d0ca4a19 100644
--- a/arch/x86/cpu/slimbootloader/Makefile
+++ b/arch/x86/cpu/slimbootloader/Makefile
@@ -2,4 +2,4 @@
#
# Copyright (C) 2019 Intel Corporation
-obj-y += car.o slimbootloader.o
+obj-y += car.o slimbootloader.o dram.o
diff --git a/arch/x86/cpu/slimbootloader/dram.c
b/arch/x86/cpu/slimbootloader/dram.c
new file mode 100644
index 00..b52cbe7ec4
--- /dev/null
+++ b/arch/x86/cpu/slimbootloader/dram.c
@@ -0,0 +1,151 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Intel Corporation
+ */
+
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/**
+ * This returns a data pointer of memory map info from the guid hob.
+ *
+ * @return: A data pointer of memory map info hob
+ */
+static void *get_memory_map_info(void)
+{
+ const struct efi_guid guid = LOADER_MEMORY_MAP_INFO_GUID;
+
+ if (!gd->arch.hob_list)
+ return NULL;
+
+ return hob_get_guid_hob_data(gd->arch.hob_list, NULL, );
+}
+
+/**
+ * This is to give usable memory region information for u-boot relocation.
+ * so search usable memory region lower than 4GB.
+ * The memory map entries from Slim Bootloader hob are already sorted.
+ *
+ * @total_size: The memory size that u-boot occupies
+ * @return: The top available memory address lower than 4GB
+ */
+ulong board_get_usable_ram_top(ulong total_size)
+{
+ struct memory_map_info *data = NULL;
+ int i = 0;
+ phys_addr_t addr_start = 0;
+ phys_addr_t addr_end = 0;
+ ulong ram_top = 0;
+
+ data = (struct memory_map_info *)get_memory_map_info();
+ if (!data)
+ panic("memory map info hob not found\n");
+
+ /**
+* sorted memory map entries from Slim Bootloader based on physical
+* start memory address, from low to high. So do reversed search to
+* get highest usable, suitable size, 4KB aligned available memory
+* under 4GB.
+*/
+ for (i = data->count - 1; i >= 0; i--) {
+ if (data->entry[i].type != E820_RAM)
+ continue;
+
+ addr_start = data->entry[i].addr;
+ addr_end = addr_start + data->entry[i].size;
+
+ if (addr_start > SZ_4G)
+ continue;
+
+ if (addr_end > SZ_4G)
+ addr_end = SZ_4G;
+
+ if (addr_end < total_size)
+ continue;
+
+ /* to relocate u-boot at 4K aligned memory */
+ addr_end = rounddown(addr_end - total_size, SZ_4K);
+ if (addr_end >= addr_start) {
+ ram_top = (ulong)addr_end + total_size;
+ break;
+ }
+ }
+
+ if (!ram_top)
+ panic("failed to find available memory for relocation!");
+
+ return ram_top;
+}
+
+/**
+ * The memory initialization has already been done in previous Slim Bootloader
+ * stage thru FSP-M. Instead, this sets the ram_size from the memory map info
+ * hob.
+ */
+int dram_init(void)
+{
+ struct memory_map_info *data = NULL;
+ int i = 0;
+ phys_size_t ram_size = 0;
+
+ data = (struct memory_map_info *)get_memory_map_info();
+ if (!data)
+ panic("memory map info hob not found\n");
+
+ /**
+* sorted memory map entries from Slim Bootloader based on physical
+* start memory address, from low to high. So do reversed search to
+* simply get highest usable memory address as ram size
+*/
+ for (i = data->count - 1; i >= 0; i--) {
+ if (data->entry[i].type != E820_RAM)
+ continue;
+
+ /* simply use the highest usable memory address as ram size */
+ ram_size = data->entry[i].addr + data->entry[i].size;
+ break;
+ }
+
+ if (!ram_size)
+ panic("failed to detect memory size");
+
+ gd->ram_size = ram_size;
+ return 0;
+}
+
+int dram_init_banksize(void)
+{
+ /* simply use a single bank to have whole size for now */
+ if
[U-Boot] [PATCH v5 4/8] x86: slimbootloader: Add serial driver
Slim Bootloader provides serial port info thru its HOB list pointer.
All these HOBs are eligible for Slim Bootloader based board only.
- Get serial port information from the serial port info hob
- Leverage ns16550 driver with slimbootloader specific platform data
Signed-off-by: Aiden Park
Reviewed-by: Bin Meng
---
Changes in v4:
* Add static keyword in static function
Changes in v3:
* Use HOB function from the common HOB library
arch/x86/cpu/slimbootloader/Makefile | 2 +-
arch/x86/cpu/slimbootloader/serial.c | 69 +++
.../asm/arch-slimbootloader/slimbootloader.h | 36 ++
3 files changed, 106 insertions(+), 1 deletion(-)
create mode 100644 arch/x86/cpu/slimbootloader/serial.c
diff --git a/arch/x86/cpu/slimbootloader/Makefile
b/arch/x86/cpu/slimbootloader/Makefile
index 05d0ca4a19..68c4a91955 100644
--- a/arch/x86/cpu/slimbootloader/Makefile
+++ b/arch/x86/cpu/slimbootloader/Makefile
@@ -2,4 +2,4 @@
#
# Copyright (C) 2019 Intel Corporation
-obj-y += car.o slimbootloader.o dram.o
+obj-y += car.o slimbootloader.o dram.o serial.o
diff --git a/arch/x86/cpu/slimbootloader/serial.c
b/arch/x86/cpu/slimbootloader/serial.c
new file mode 100644
index 00..5a8591889f
--- /dev/null
+++ b/arch/x86/cpu/slimbootloader/serial.c
@@ -0,0 +1,69 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Intel Corporation
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+/**
+ * The serial port info hob is generated by Slim Bootloader, so eligible for
+ * Slim Bootloader based boards only.
+ */
+static int slimbootloader_serial_ofdata_to_platdata(struct udevice *dev)
+{
+ const struct efi_guid guid = LOADER_SERIAL_PORT_INFO_GUID;
+ struct serial_port_info *serial_info = NULL;
+ struct ns16550_platdata *plat = dev->platdata;
+
+ if (!gd->arch.hob_list)
+ panic("hob list not found!");
+
+ serial_info = (struct serial_port_info *)
+ hob_get_guid_hob_data(gd->arch.hob_list, NULL, );
+
+ if (!serial_info) {
+ debug("failed to get serial port information\n");
+ return -ENOENT;
+ }
+ debug("type:%d base=0x%08x baudrate=%d stride=%d clk=%d\n",
+ serial_info->type,
+ serial_info->base,
+ serial_info->baud,
+ serial_info->stride,
+ serial_info->clk);
+
+ /*
+* The serial_info->type provides port io or mmio access type info,
+* but the access type will be controlled by
+* CONFIG_SYS_NS16550_PORT_MAPPED or CONFIG_SYS_NS16550_MEM32.
+*
+* TBD: ns16550 access type configuration in runtime.
+* ex) plat->access_type = serial_info->type
+*/
+ plat->base = serial_info->base;
+ /* ns16550 uses reg_shift, then covert stride to shift */
+ plat->reg_shift = (serial_info->stride >> 1);
+ plat->clock = serial_info->clk;
+
+ return 0;
+}
+
+static const struct udevice_id slimbootloader_serial_ids[] = {
+ { .compatible = "intel,slimbootloader-uart" },
+ {}
+};
+
+U_BOOT_DRIVER(serial_slimbootloader) = {
+ .name = "serial_slimbootloader",
+ .id = UCLASS_SERIAL,
+ .of_match = slimbootloader_serial_ids,
+ .ofdata_to_platdata = slimbootloader_serial_ofdata_to_platdata,
+ .platdata_auto_alloc_size = sizeof(struct ns16550_platdata),
+ .priv_auto_alloc_size = sizeof(struct NS16550),
+ .probe = ns16550_serial_probe,
+ .ops= _serial_ops,
+};
diff --git a/arch/x86/include/asm/arch-slimbootloader/slimbootloader.h
b/arch/x86/include/asm/arch-slimbootloader/slimbootloader.h
index d9265ac534..5a0994544a 100644
--- a/arch/x86/include/asm/arch-slimbootloader/slimbootloader.h
+++ b/arch/x86/include/asm/arch-slimbootloader/slimbootloader.h
@@ -18,6 +18,15 @@
{ 0xa9, 0xe4, 0x92, 0xf3, 0x57, 0xd1, 0x28, 0x32 } \
}
+/**
+ * A GUID to get SerialPort info hob which is provided by Slim Bootloader
+ */
+#define LOADER_SERIAL_PORT_INFO_GUID \
+ { \
+ 0x6c6872fe, 0x56a9, 0x4403, \
+ { 0xbb, 0x98, 0x95, 0x8d, 0x62, 0xde, 0x87, 0xf1 } \
+ }
+
/**
* A single entry of memory map information
*
@@ -35,6 +44,33 @@ struct memory_map_entry {
u8 rsvd[6];
} __packed;
+/**
+ * This includes serial port info which has already been initialized in
previous
+ * Slim Bootloader stage.
+ * The Slim Bootloader initializes serial port regardless of debug/release
build
+ * modes, and it passes the information to a payload thru hob. So, a payload
can
+ * re-use the serial information without re-initializing serial port.
+ *
+ * @rev : revision of serial_port_info structure. currently 1.
+ * @rsvd : padding for alignment
+ * @type : port io: 1, mmio: 2
+ * @base : io base address. ex) 0x3f8, 0x80001000
+ * @baud : uart baud rate
+ * @stride: register stride in Bytes
+ * @clk : uart frequency in Hz
+ * @rsvd1 :
[U-Boot] [PATCH v5 1/8] x86: Add new slimbootloader CPU type
This slimbootloader cpu type is to enable U-Boot as a payload which runs on top of Slim Bootloader(https://github.com/slimbootloader). The Slim Bootloader is designed with multi-stage architecture for the execution from reset vector to OS booting, and supports qemu, Apollolake, Whiskeylake and Coffeelake platforms consuming Intel FSP (https://github.com/IntelFsp) for silicon initialization including CAR and memory initialization. The Slim Bootloader generates new HOB(Hand Off Block) which are serial port info, memory map info, performance data info and so on, and passes it to a Payload. U-Boot as a payload will use these HOB information for basic initialization such as serial console. As an initial commit, - Add CONFIG_SYS_SLIMBOOTLOADER to enable slimbootloader CPU type - Add new arch/x86/cpu/slimbootloader directory with minimum codes - Get hob_list pointer from Slim Bootloader Signed-off-by: Aiden Park Reviewed-by: Bin Meng --- Changes in v4: * Use common arch/x86/cpu/start.S * Update U-boot or u-boot to U-Boot in commit message Changes in v3: * Add a brief description about Slim Bootloader * Enable USB_KEYBOARD, E1000 and RTL8169 by default * Fix comment from code review arch/x86/Kconfig | 1 + arch/x86/cpu/Makefile | 1 + arch/x86/cpu/slimbootloader/Kconfig | 26 +++ arch/x86/cpu/slimbootloader/Makefile | 5 arch/x86/cpu/slimbootloader/car.S | 14 ++ arch/x86/cpu/slimbootloader/slimbootloader.c | 21 +++ arch/x86/cpu/start.S | 6 +++-- .../asm/arch-slimbootloader/slimbootloader.h | 11 arch/x86/include/asm/global_data.h| 2 +- arch/x86/lib/asm-offsets.c| 2 +- 10 files changed, 85 insertions(+), 4 deletions(-) create mode 100644 arch/x86/cpu/slimbootloader/Kconfig create mode 100644 arch/x86/cpu/slimbootloader/Makefile create mode 100644 arch/x86/cpu/slimbootloader/car.S create mode 100644 arch/x86/cpu/slimbootloader/slimbootloader.c create mode 100644 arch/x86/include/asm/arch-slimbootloader/slimbootloader.h diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 70f939869a..27b7b767b9 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -115,6 +115,7 @@ source "arch/x86/cpu/efi/Kconfig" source "arch/x86/cpu/qemu/Kconfig" source "arch/x86/cpu/quark/Kconfig" source "arch/x86/cpu/queensbay/Kconfig" +source "arch/x86/cpu/slimbootloader/Kconfig" source "arch/x86/cpu/tangier/Kconfig" # architecture-specific options below diff --git a/arch/x86/cpu/Makefile b/arch/x86/cpu/Makefile index 85fd5e616e..3f1f62da2b 100644 --- a/arch/x86/cpu/Makefile +++ b/arch/x86/cpu/Makefile @@ -42,6 +42,7 @@ obj-$(CONFIG_INTEL_BAYTRAIL) += baytrail/ obj-$(CONFIG_INTEL_BRASWELL) += braswell/ obj-$(CONFIG_INTEL_BROADWELL) += broadwell/ obj-$(CONFIG_SYS_COREBOOT) += coreboot/ +obj-$(CONFIG_SYS_SLIMBOOTLOADER) += slimbootloader/ obj-$(CONFIG_EFI) += efi/ obj-$(CONFIG_QEMU) += qemu/ obj-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) += ivybridge/ diff --git a/arch/x86/cpu/slimbootloader/Kconfig b/arch/x86/cpu/slimbootloader/Kconfig new file mode 100644 index 00..439e4b1e2c --- /dev/null +++ b/arch/x86/cpu/slimbootloader/Kconfig @@ -0,0 +1,26 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2019 Intel Corporation + +if TARGET_SLIMBOOTLOADER + +config SYS_SLIMBOOTLOADER + bool + default y + imply SYS_NS16550 + imply AHCI_PCI + imply SCSI + imply SCSI_AHCI + imply MMC + imply MMC_PCI + imply MMC_SDHCI + imply MMC_SDHCI_SDMA + imply USB + imply USB_EHCI_HCD + imply USB_XHCI_HCD + imply USB_STORAGE + imply USB_KEYBOARD + imply E1000 + imply RTL8169 + +endif diff --git a/arch/x86/cpu/slimbootloader/Makefile b/arch/x86/cpu/slimbootloader/Makefile new file mode 100644 index 00..627a721e8c --- /dev/null +++ b/arch/x86/cpu/slimbootloader/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2019 Intel Corporation + +obj-y += car.o slimbootloader.o diff --git a/arch/x86/cpu/slimbootloader/car.S b/arch/x86/cpu/slimbootloader/car.S new file mode 100644 index 00..6e0304333c --- /dev/null +++ b/arch/x86/cpu/slimbootloader/car.S @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2019 Intel Corporation + */ + +#include + +.section .text + +.globl car_init +car_init: + /* Get hob pointer parameter from previous stage's stack */ + mov 0x4(%esp), %esi + jmp car_init_ret diff --git a/arch/x86/cpu/slimbootloader/slimbootloader.c b/arch/x86/cpu/slimbootloader/slimbootloader.c new file mode 100644 index 00..9f3a61ec61 --- /dev/null +++ b/arch/x86/cpu/slimbootloader/slimbootloader.c @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 Intel Corporation + */ + +#include
[U-Boot] [PATCH v5 2/8] x86: Add a common hob library
FSP(CONFIG_HAVE_FSP) and Slim Bootloader(CONFIG_SYS_SLIMBOOTLOADER)
consume HOB data from the each HOB list pointer.
Add a common hob library/header in lib/hob.c and include/asm/hob.h.
Signed-off-by: Aiden Park
Reviewed-by: Bin Meng
---
Changes in v3:
* Create a common HOB libary from fsp_hob and fsp_support
arch/x86/include/asm/fsp/fsp_hob.h | 183 +-
arch/x86/include/asm/fsp/fsp_support.h | 37 +---
arch/x86/include/asm/fsp/fsp_types.h | 8 -
arch/x86/include/asm/hob.h | 250 +
arch/x86/lib/Makefile | 3 +-
arch/x86/lib/fsp/fsp_support.c | 78 +---
arch/x86/lib/hob.c | 104 ++
7 files changed, 361 insertions(+), 302 deletions(-)
create mode 100644 arch/x86/include/asm/hob.h
create mode 100644 arch/x86/lib/hob.c
diff --git a/arch/x86/include/asm/fsp/fsp_hob.h
b/arch/x86/include/asm/fsp/fsp_hob.h
index 00657b62c7..2e29de3af5 100644
--- a/arch/x86/include/asm/fsp/fsp_hob.h
+++ b/arch/x86/include/asm/fsp/fsp_hob.h
@@ -7,124 +7,7 @@
#ifndef __FSP_HOB_H__
#define __FSP_HOB_H__
-#include
-
-/* Type of HOB Header */
-#define HOB_TYPE_MEM_ALLOC 0x0002
-#define HOB_TYPE_RES_DESC 0x0003
-#define HOB_TYPE_GUID_EXT 0x0004
-#define HOB_TYPE_UNUSED0xFFFE
-#define HOB_TYPE_EOH 0x
-
-/*
- * Describes the format and size of the data inside the HOB.
- * All HOBs must contain this generic HOB header.
- */
-struct hob_header {
- u16 type; /* HOB type */
- u16 len;/* HOB length */
- u32 reserved; /* always zero */
-};
-
-/*
- * Describes all memory ranges used during the HOB producer phase that
- * exist outside the HOB list. This HOB type describes how memory is used,
- * not the physical attributes of memory.
- */
-struct hob_mem_alloc {
- struct hob_header hdr;
- /*
-* A GUID that defines the memory allocation region's type and purpose,
-* as well as other fields within the memory allocation HOB. This GUID
-* is used to define the additional data within the HOB that may be
-* present for the memory allocation HOB. Type efi_guid is defined in
-* InstallProtocolInterface() in the UEFI 2.0 specification.
-*/
- struct efi_guid name;
- /*
-* The base address of memory allocated by this HOB.
-* Type phys_addr_t is defined in AllocatePages() in the UEFI 2.0
-* specification.
-*/
- phys_addr_t mem_base;
- /* The length in bytes of memory allocated by this HOB */
- phys_size_t mem_len;
- /*
-* Defines the type of memory allocated by this HOB.
-* The memory type definition follows the EFI_MEMORY_TYPE definition.
-* Type EFI_MEMORY_TYPE is defined in AllocatePages() in the UEFI 2.0
-* specification.
-*/
- enum efi_mem_type mem_type;
- /* padding */
- u8 reserved[4];
-};
-
-/* Value of ResourceType in HOB_RES_DESC */
-#define RES_SYS_MEM0x
-#define RES_MMAP_IO0x0001
-#define RES_IO 0x0002
-#define RES_FW_DEVICE 0x0003
-#define RES_MMAP_IO_PORT 0x0004
-#define RES_MEM_RESERVED 0x0005
-#define RES_IO_RESERVED0x0006
-#define RES_MAX_MEM_TYPE 0x0007
-
-/*
- * These types can be ORed together as needed.
- *
- * The first three enumerations describe settings
- * The rest of the settings describe capabilities
- */
-#define RES_ATTR_PRESENT 0x0001
-#define RES_ATTR_INITIALIZED 0x0002
-#define RES_ATTR_TESTED0x0004
-#define RES_ATTR_SINGLE_BIT_ECC0x0008
-#define RES_ATTR_MULTIPLE_BIT_ECC 0x0010
-#define RES_ATTR_ECC_RESERVED_10x0020
-#define RES_ATTR_ECC_RESERVED_20x0040
-#define RES_ATTR_READ_PROTECTED0x0080
-#define RES_ATTR_WRITE_PROTECTED 0x0100
-#define RES_ATTR_EXECUTION_PROTECTED 0x0200
-#define RES_ATTR_UNCACHEABLE 0x0400
-#define RES_ATTR_WRITE_COMBINEABLE 0x0800
-#define RES_ATTR_WRITE_THROUGH_CACHEABLE 0x1000
-#define RES_ATTR_WRITE_BACK_CACHEABLE 0x2000
-#define RES_ATTR_16_BIT_IO 0x4000
-#define RES_ATTR_32_BIT_IO 0x8000
-#define RES_ATTR_64_BIT_IO 0x0001
-#define RES_ATTR_UNCACHED_EXPORTED 0x0002
-
-/*
- * Describes the resource properties of all fixed, nonrelocatable resource
- * ranges found on the processor host bus during the HOB producer phase.
- */
-struct hob_res_desc {
- struct hob_header hdr;
- /*
-* A GUID
[U-Boot] [PATCH v5 0/8] x86: Add basic Slim Bootloader payload support
This patch is to enable U-Boot as a payload which runs on top of Slim Bootloader(https://github.com/slimbootloader/slimbootloader) boot firmware for x86 platforms. The Slim Bootloader is designed with multi-stage architecture for the execution from reset vector to OS hand-off, and supports qemu, Apollolake, Whiskeylake and Coffeelake platforms consuming Intel FSP(https://github.com/IntelFsp/FSP) for silicon initialization including CAR and memory initialization. As multi-stage architecture, the Slim Bootloader adopts payload concept which is responsible for OS load from media devices and boot OS and it supports 32-bit PE32, EFI FV, ELF and RAW format payloads. The Slim Bootloader generate HOB(Hand Off Block) list pointer, which has debug serial port info, memory map info, performance data info and etc., and passes it to a payload. U-Boot configures serial port, dram, pci, tsc and others with the information from the HOB. The compiled U-Boot supports usb, sata and sd/mmc boot which have been verified on qemu and other supported platforms. Changes in v5: * Remove X86_LOAD_FROM_32_BIT from slimbootloader_defconfig Changes in v4: * Use arch/x86/cpu/start.S with CONFIG_SYS_SLIMBOOTLOADER condition * Update U-boot or u-boot to U-Boot in commit message * Add static keyword in static function Changes in v3: * Add a brief description about Slim Bootloader in 1st patch * Add a common HOB library to be used by both FSP and Slim Bootloader * Move board/slimbootloader/slimbootloader to board/intel/slimbootloader * Add more description board/intel/slimbootloader/README * Fix comments from the code review Changes in v2: * Split a single patch to 8 patches * Add more comment for each structure and functions Aiden Park (8): x86: Add new slimbootloader CPU type x86: Add a common hob library x86: slimbootloader: Add memory configuration x86: slimbootloader: Add serial driver x86: slimbootloader: Set TSC information for timer driver x86: slimbootloader: Add a slimbootloader device tree board: intel: Add new slimbootloader board x86: Skip setting up MTRRs in slimbootloader arch/x86/Kconfig | 1 + arch/x86/cpu/Makefile | 1 + arch/x86/cpu/slimbootloader/Kconfig | 26 ++ arch/x86/cpu/slimbootloader/Makefile | 5 + arch/x86/cpu/slimbootloader/car.S | 14 + arch/x86/cpu/slimbootloader/dram.c| 151 +++ arch/x86/cpu/slimbootloader/serial.c | 69 + arch/x86/cpu/slimbootloader/slimbootloader.c | 55 arch/x86/cpu/start.S | 6 +- arch/x86/dts/Makefile | 1 + arch/x86/dts/slimbootloader.dts | 27 ++ .../asm/arch-slimbootloader/slimbootloader.h | 121 + arch/x86/include/asm/fsp/fsp_hob.h| 183 + arch/x86/include/asm/fsp/fsp_support.h| 37 +-- arch/x86/include/asm/fsp/fsp_types.h | 8 - arch/x86/include/asm/global_data.h| 2 +- arch/x86/include/asm/hob.h| 250 ++ arch/x86/lib/Makefile | 3 +- arch/x86/lib/asm-offsets.c| 2 +- arch/x86/lib/fsp/fsp_support.c| 78 +- arch/x86/lib/hob.c| 104 arch/x86/lib/init_helpers.c | 3 +- board/intel/Kconfig | 14 + board/intel/slimbootloader/Kconfig| 51 board/intel/slimbootloader/Makefile | 5 + board/intel/slimbootloader/README | 133 ++ board/intel/slimbootloader/slimbootloader.c | 17 ++ board/intel/slimbootloader/start.S| 9 + configs/slimbootloader_defconfig | 21 ++ include/configs/slimbootloader.h | 59 + 30 files changed, 1149 insertions(+), 307 deletions(-) create mode 100644 arch/x86/cpu/slimbootloader/Kconfig create mode 100644 arch/x86/cpu/slimbootloader/Makefile create mode 100644 arch/x86/cpu/slimbootloader/car.S create mode 100644 arch/x86/cpu/slimbootloader/dram.c create mode 100644 arch/x86/cpu/slimbootloader/serial.c create mode 100644 arch/x86/cpu/slimbootloader/slimbootloader.c create mode 100644 arch/x86/dts/slimbootloader.dts create mode 100644 arch/x86/include/asm/arch-slimbootloader/slimbootloader.h create mode 100644 arch/x86/include/asm/hob.h create mode 100644 arch/x86/lib/hob.c create mode 100644 board/intel/slimbootloader/Kconfig create mode 100644 board/intel/slimbootloader/Makefile create mode 100644 board/intel/slimbootloader/README create mode 100644 board/intel/slimbootloader/slimbootloader.c create mode 100644 board/intel/slimbootloader/start.S create mode 100644 configs/slimbootloader_defconfig create mode 100644 include/configs/slimbootloader.h -- 2.20.1 ___ U-Boot mailing list U-Boot@lists.denx.de
Re: [U-Boot] [PATCH v4] spl: kconfig: separate sysreset and firmware drivers from misc
On 17/07/19 12:59 AM, Simon Goldschmidt wrote: > This adds separate kconfig options for drivers/sysreset and > drivers/firmware. > > Up to now, CONFIG_SPL_DRIVERS_MISC_SUPPORT added drivers/misc to SPL > build but also added drivers/firmware and drivers/sysreset at the same > time. > > Since that is confusing, this patch uses CONFIG_SPL_SYSRESET for > drivers/sysreset and adds CONFIG_SPL_FIRMWARE for > drivers/firmware (and accordingly for the TPL options). > > CONFIG_SPL_DRIVERS_MISC_SUPPORT stays for including drivers/misc into > the SPL build (and accordingly for TPL) since there are boards using > non-DM (non UCLASS_MISC) files from drivers/misc. Such boards don't > have CONFIG_SPL_MISC enabled, so cannot use this to include > drivers/misc into the SPL build. > > Signed-off-by: Simon Goldschmidt Reviewed-by: Lokesh Vutla Thanks and regards, Lokesh ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v5 0/4] SiFive SPI MMC Support
On Wed, Jul 17, 2019 at 9:38 AM Jagan Teki wrote: > > On Wed, Jul 17, 2019 at 9:20 AM Anup Patel wrote: > > > > This patchset adds: > > 1. SiFive SPI driver > > 2. New MMC SPI driver based on DM_MMC and DM_SPI > > 3. Enables SiFive SPI driver and MMC SPI driver for SiFive Unleashed board > > > > With this patch series, we can now load files from SD card on SiFive > > Unleashed board. Many thanks to Bhargav for porting SiFive SPI driver > > and updating MMC SPI driver for us. > > > > These patches can be also found in riscv_unleashed_mmc_spi_v5 branch of: > > https//github.com/avpatel/u-boot.git > > > > Changes since v4: > > - Renamed kconfig option from SIFIVE_SPI to SPI_SIFIVE for consistency > > - Added dummy claim_bus() and release_bus() callbacks > > > > Changes since v3: > > - Removed PATCH2, PATCH3, and PATCH4 because these are already merged > > - Added separate patch to use SPI_XFER_xyz flags in MMC_SPI driver > > - Use readl/writel directly instead of sifive_spi_read/sifi_spi_write > > - Use SPI_XFER_xyz flags to enable/disable chipselect > > - Remove unused callback sifive_spi_cs_info() > > > > Changes since v2: > > - Minor fixes in PATCH1 which adds SiFive SPI driver > > - Removed CONFIG_MMC_SPI_xyz from scripts/config_whitelist.txt > > - Removed cmd/mmc_spi and all its refrences as separate patch > > - Removed DM_SPI and DM_MMC from SiFive FU540 Kconfig > > > > Changes since v1: > > - Make response matching part belongs to mmc_spi_sendcmd() > > - Match response to zero for SEND_STATUS (CMD13) > > - Add separate patch for updating SiFive FU540 Documentation > > > > Anup Patel (2): > > mmc: mmc_spi: Use SPI_XFER_BEGIN and SPI_XFER_END flags > > doc: sifive-fu540: Update README for SiFive SPI and MMC SPI drivers > > > > Bhargav Shah (2): > > spi: Add SiFive SPI driver > > riscv: sifive: fu540: Enable SiFive SPI and MMC SPI drivers > > > > board/sifive/fu540/Kconfig | 6 + > > doc/README.sifive-fu540| 4 +- > > drivers/mmc/mmc_spi.c | 4 +- > > drivers/spi/Kconfig| 8 + > > drivers/spi/Makefile | 1 + > > drivers/spi/spi-sifive.c | 375 + > > 6 files changed, 394 insertions(+), 4 deletions(-) > > create mode 100644 drivers/spi/spi-sifive.c > > I would like to pick entire series on spi tree, but it has some boards > changes so I would like to ask the board maintainers to give a > permissions to do so, if not possible I can take only spi changes. Last 2 patches depend on below mentioned series so won't apply for you. I guess you can pickup SPI driver and MMC_SPI change. Refer, https://www.mail-archive.com/u-boot@lists.denx.de/msg331405.html Regards, Anup ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v6 3/4] riscv: sifive: fu540: Enable SiFive SPI and MMC SPI drivers
From: Bhargav Shah This patch enables SiFive SPI and MMC SPI drivers for the SiFive Unleashed board. Signed-off-by: Bhargav Shah Signed-off-by: Anup Patel Reviewed-by: Bin Meng Tested-by: Bin Meng Reviewed-by: Jagan Teki --- board/sifive/fu540/Kconfig | 6 ++ 1 file changed, 6 insertions(+) diff --git a/board/sifive/fu540/Kconfig b/board/sifive/fu540/Kconfig index f46437901d..5d65080429 100644 --- a/board/sifive/fu540/Kconfig +++ b/board/sifive/fu540/Kconfig @@ -38,6 +38,12 @@ config BOARD_SPECIFIC_OPTIONS # dummy imply PHY_LIB imply PHY_MSCC imply SIFIVE_SERIAL + imply SPI + imply SPI_SIFIVE + imply MMC + imply MMC_SPI + imply MMC_BROKEN_CD + imply CMD_MMC imply SMP endif -- 2.17.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v6 4/4] doc: sifive-fu540: Update README for SiFive SPI and MMC SPI drivers
This patch removes SiFive SPI driver and MMC SPI drive from the TODO
list in SiFive FU540 README.
Signed-off-by: Anup Patel
Reviewed-by: Bin Meng
Tested-by: Bin Meng
Reviewed-by: Jagan Teki
---
doc/README.sifive-fu540 | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/doc/README.sifive-fu540 b/doc/README.sifive-fu540
index 33e03dc861..944ba1c8a0 100644
--- a/doc/README.sifive-fu540
+++ b/doc/README.sifive-fu540
@@ -13,9 +13,7 @@ The support for following drivers are already enabled:
3. Cadence MACB ethernet driver for networking support.
TODO:
-1. SPI host driver is still missing.
-2. SPI MMC driver does not compile and needs a re-write using U-Boot DM.
-2. U-Boot expects the serial console device entry to be present under /chosen
+1. U-Boot expects the serial console device entry to be present under /chosen
DT node. Example:
chosen {
stdout-path = "/soc/serial@1001:115200";
--
2.17.1
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[U-Boot] [PATCH v6 2/4] spi: Add SiFive SPI driver
From: Bhargav Shah This patch adds SiFive SPI driver. The driver is 100% DM driver and it determines input clock using clk framework. The SiFive SPI block is found on SiFive FU540 SOC and is used to access flash and MMC devices on SiFive Unleashed board. This driver implementation is inspired from the Linux SiFive SPI driver available in Linux-5.2 or higher and SiFive FSBL sources. Signed-off-by: Bhargav Shah Signed-off-by: Anup Patel Reviewed-by: Bin Meng Tested-by: Bin Meng --- drivers/spi/Kconfig | 8 + drivers/spi/Makefile | 1 + drivers/spi/spi-sifive.c | 370 +++ 3 files changed, 379 insertions(+) create mode 100644 drivers/spi/spi-sifive.c diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index eb32f082fe..030f3377d4 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -224,6 +224,14 @@ config SANDBOX_SPI }; }; +config SPI_SIFIVE + bool "SiFive SPI driver" + help + This driver supports the SiFive SPI IP. If unsure say N. + Enable the SiFive SPI controller driver. + + The SiFive SPI controller driver is found on various SiFive SoCs. + config SPI_SUNXI bool "Allwinner SoC SPI controllers" help diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 8be9a4baa2..a53b9f4217 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -49,6 +49,7 @@ obj-$(CONFIG_PL022_SPI) += pl022_spi.o obj-$(CONFIG_RENESAS_RPC_SPI) += renesas_rpc_spi.o obj-$(CONFIG_ROCKCHIP_SPI) += rk_spi.o obj-$(CONFIG_SANDBOX_SPI) += sandbox_spi.o +obj-$(CONFIG_SPI_SIFIVE) += spi-sifive.o obj-$(CONFIG_SPI_SUNXI) += spi-sunxi.o obj-$(CONFIG_SH_SPI) += sh_spi.o obj-$(CONFIG_SH_QSPI) += sh_qspi.o diff --git a/drivers/spi/spi-sifive.c b/drivers/spi/spi-sifive.c new file mode 100644 index 00..969bd4b75c --- /dev/null +++ b/drivers/spi/spi-sifive.c @@ -0,0 +1,370 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 SiFive, Inc. + * Copyright 2019 Bhargav Shah + * + * SiFive SPI controller driver (master mode only) + */ + +#include +#include +#include +#include +#include +#include +#include + +#define SIFIVE_SPI_MAX_CS 32 + +#define SIFIVE_SPI_DEFAULT_DEPTH 8 +#define SIFIVE_SPI_DEFAULT_BITS8 + +/* register offsets */ +#define SIFIVE_SPI_REG_SCKDIV0x00 /* Serial clock divisor */ +#define SIFIVE_SPI_REG_SCKMODE 0x04 /* Serial clock mode */ +#define SIFIVE_SPI_REG_CSID 0x10 /* Chip select ID */ +#define SIFIVE_SPI_REG_CSDEF 0x14 /* Chip select default */ +#define SIFIVE_SPI_REG_CSMODE0x18 /* Chip select mode */ +#define SIFIVE_SPI_REG_DELAY00x28 /* Delay control 0 */ +#define SIFIVE_SPI_REG_DELAY10x2c /* Delay control 1 */ +#define SIFIVE_SPI_REG_FMT 0x40 /* Frame format */ +#define SIFIVE_SPI_REG_TXDATA0x48 /* Tx FIFO data */ +#define SIFIVE_SPI_REG_RXDATA0x4c /* Rx FIFO data */ +#define SIFIVE_SPI_REG_TXMARK0x50 /* Tx FIFO watermark */ +#define SIFIVE_SPI_REG_RXMARK0x54 /* Rx FIFO watermark */ +#define SIFIVE_SPI_REG_FCTRL 0x60 /* SPI flash interface control */ +#define SIFIVE_SPI_REG_FFMT 0x64 /* SPI flash instruction format */ +#define SIFIVE_SPI_REG_IE0x70 /* Interrupt Enable Register */ +#define SIFIVE_SPI_REG_IP0x74 /* Interrupt Pendings Register */ + +/* sckdiv bits */ +#define SIFIVE_SPI_SCKDIV_DIV_MASK 0xfffU + +/* sckmode bits */ +#define SIFIVE_SPI_SCKMODE_PHA BIT(0) +#define SIFIVE_SPI_SCKMODE_POL BIT(1) +#define SIFIVE_SPI_SCKMODE_MODE_MASK (SIFIVE_SPI_SCKMODE_PHA | \ + SIFIVE_SPI_SCKMODE_POL) + +/* csmode bits */ +#define SIFIVE_SPI_CSMODE_MODE_AUTO 0U +#define SIFIVE_SPI_CSMODE_MODE_HOLD 2U +#define SIFIVE_SPI_CSMODE_MODE_OFF 3U + +/* delay0 bits */ +#define SIFIVE_SPI_DELAY0_CSSCK(x) ((u32)(x)) +#define SIFIVE_SPI_DELAY0_CSSCK_MASK 0xffU +#define SIFIVE_SPI_DELAY0_SCKCS(x) ((u32)(x) << 16) +#define SIFIVE_SPI_DELAY0_SCKCS_MASK (0xffU << 16) + +/* delay1 bits */ +#define SIFIVE_SPI_DELAY1_INTERCS(x) ((u32)(x)) +#define SIFIVE_SPI_DELAY1_INTERCS_MASK 0xffU +#define SIFIVE_SPI_DELAY1_INTERXFR(x)((u32)(x) << 16) +#define SIFIVE_SPI_DELAY1_INTERXFR_MASK (0xffU << 16) + +/* fmt bits */ +#define SIFIVE_SPI_FMT_PROTO_SINGLE 0U +#define SIFIVE_SPI_FMT_PROTO_DUAL1U +#define SIFIVE_SPI_FMT_PROTO_QUAD2U +#define SIFIVE_SPI_FMT_PROTO_MASK3U +#define SIFIVE_SPI_FMT_ENDIANBIT(2) +#define SIFIVE_SPI_FMT_DIR BIT(3) +#define SIFIVE_SPI_FMT_LEN(x)((u32)(x) << 16) +#define SIFIVE_SPI_FMT_LEN_MASK (0xfU << 16) + +/* txdata bits */ +#define SIFIVE_SPI_TXDATA_DATA_MASK 0xffU +#define SIFIVE_SPI_TXDATA_FULL BIT(31) +
[U-Boot] [PATCH v6 1/4] mmc: mmc_spi: Use SPI_XFER_BEGIN and SPI_XFER_END flags
Most DM based SPI host controller drivers use SPI_XFER_BEGIN and SPI_XFER_END flags to enable/disable slave chip select. This patch extends MMC SPI driver to pass SPI_XFER_BEGIN flag when MMC command is send at start and pass SPI_XFER_END flag using a dummy transfer (of bitlen = 0) at the end of MMC command. Suggested-by: Jagan Teki Signed-off-by: Anup Patel --- drivers/mmc/mmc_spi.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/mmc_spi.c b/drivers/mmc/mmc_spi.c index f3d687ae80..350812a04b 100644 --- a/drivers/mmc/mmc_spi.c +++ b/drivers/mmc/mmc_spi.c @@ -84,7 +84,7 @@ static int mmc_spi_sendcmd(struct udevice *dev, cmdo[4] = cmdarg >> 8; cmdo[5] = cmdarg; cmdo[6] = (crc7(0, [1], 5) << 1) | 0x01; - ret = dm_spi_xfer(dev, sizeof(cmdo) * 8, cmdo, NULL, 0); + ret = dm_spi_xfer(dev, sizeof(cmdo) * 8, cmdo, NULL, SPI_XFER_BEGIN); if (ret) return ret; @@ -360,6 +360,8 @@ static int dm_mmc_spi_request(struct udevice *dev, struct mmc_cmd *cmd, } done: + dm_spi_xfer(dev, 0, NULL, NULL, SPI_XFER_END); + dm_spi_release_bus(dev); return ret; -- 2.17.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v6 0/4] SiFive SPI MMC Support
This patchset adds: 1. SiFive SPI driver 2. New MMC SPI driver based on DM_MMC and DM_SPI 3. Enables SiFive SPI driver and MMC SPI driver for SiFive Unleashed board With this patch series, we can now load files from SD card on SiFive Unleashed board. Many thanks to Bhargav for porting SiFive SPI driver and updating MMC SPI driver for us. These patches can be also found in riscv_unleashed_mmc_spi_v6 branch of: https//github.com/avpatel/u-boot.git Changes since v5: - Added sifive_spi_cs_info() callback with sanity check on valid chip-select Changes since v4: - Renamed kconfig option from SIFIVE_SPI to SPI_SIFIVE for consistency - Added dummy claim_bus() and release_bus() callbacks Changes since v3: - Removed PATCH2, PATCH3, and PATCH4 because these are already merged - Added separate patch to use SPI_XFER_xyz flags in MMC_SPI driver - Use readl/writel directly instead of sifive_spi_read/sifi_spi_write - Use SPI_XFER_xyz flags to enable/disable chipselect - Remove unused callback sifive_spi_cs_info() Changes since v2: - Minor fixes in PATCH1 which adds SiFive SPI driver - Removed CONFIG_MMC_SPI_xyz from scripts/config_whitelist.txt - Removed cmd/mmc_spi and all its refrences as separate patch - Removed DM_SPI and DM_MMC from SiFive FU540 Kconfig Changes since v1: - Make response matching part belongs to mmc_spi_sendcmd() - Match response to zero for SEND_STATUS (CMD13) - Add separate patch for updating SiFive FU540 Documentation Anup Patel (2): mmc: mmc_spi: Use SPI_XFER_BEGIN and SPI_XFER_END flags doc: sifive-fu540: Update README for SiFive SPI and MMC SPI drivers Bhargav Shah (2): spi: Add SiFive SPI driver riscv: sifive: fu540: Enable SiFive SPI and MMC SPI drivers board/sifive/fu540/Kconfig | 6 + doc/README.sifive-fu540| 4 +- drivers/mmc/mmc_spi.c | 4 +- drivers/spi/Kconfig| 8 + drivers/spi/Makefile | 1 + drivers/spi/spi-sifive.c | 370 + 6 files changed, 389 insertions(+), 4 deletions(-) create mode 100644 drivers/spi/spi-sifive.c -- 2.17.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v5 1/4] mmc: mmc_spi: Use SPI_XFER_BEGIN and SPI_XFER_END flags
Hi Peng, On Wed, Jul 17, 2019 at 9:34 AM Jagan Teki wrote: > > On Wed, Jul 17, 2019 at 9:20 AM Anup Patel wrote: > > > > Most DM based SPI host controller drivers use SPI_XFER_BEGIN and > > SPI_XFER_END flags to enable/disable slave chip select. > > > > This patch extends MMC SPI driver to pass SPI_XFER_BEGIN flag when > > MMC command is send at start and pass SPI_XFER_END flag using a > > dummy transfer (of bitlen = 0) at the end of MMC command. > > > > Suggested-by: Jagan Teki > > Signed-off-by: Anup Patel > > Reviewed-by: Jagan Teki Would like to pick this via spi tree, let me know if it fine for you? ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v5 0/4] SiFive SPI MMC Support
On Wed, Jul 17, 2019 at 9:20 AM Anup Patel wrote: > > This patchset adds: > 1. SiFive SPI driver > 2. New MMC SPI driver based on DM_MMC and DM_SPI > 3. Enables SiFive SPI driver and MMC SPI driver for SiFive Unleashed board > > With this patch series, we can now load files from SD card on SiFive > Unleashed board. Many thanks to Bhargav for porting SiFive SPI driver > and updating MMC SPI driver for us. > > These patches can be also found in riscv_unleashed_mmc_spi_v5 branch of: > https//github.com/avpatel/u-boot.git > > Changes since v4: > - Renamed kconfig option from SIFIVE_SPI to SPI_SIFIVE for consistency > - Added dummy claim_bus() and release_bus() callbacks > > Changes since v3: > - Removed PATCH2, PATCH3, and PATCH4 because these are already merged > - Added separate patch to use SPI_XFER_xyz flags in MMC_SPI driver > - Use readl/writel directly instead of sifive_spi_read/sifi_spi_write > - Use SPI_XFER_xyz flags to enable/disable chipselect > - Remove unused callback sifive_spi_cs_info() > > Changes since v2: > - Minor fixes in PATCH1 which adds SiFive SPI driver > - Removed CONFIG_MMC_SPI_xyz from scripts/config_whitelist.txt > - Removed cmd/mmc_spi and all its refrences as separate patch > - Removed DM_SPI and DM_MMC from SiFive FU540 Kconfig > > Changes since v1: > - Make response matching part belongs to mmc_spi_sendcmd() > - Match response to zero for SEND_STATUS (CMD13) > - Add separate patch for updating SiFive FU540 Documentation > > Anup Patel (2): > mmc: mmc_spi: Use SPI_XFER_BEGIN and SPI_XFER_END flags > doc: sifive-fu540: Update README for SiFive SPI and MMC SPI drivers > > Bhargav Shah (2): > spi: Add SiFive SPI driver > riscv: sifive: fu540: Enable SiFive SPI and MMC SPI drivers > > board/sifive/fu540/Kconfig | 6 + > doc/README.sifive-fu540| 4 +- > drivers/mmc/mmc_spi.c | 4 +- > drivers/spi/Kconfig| 8 + > drivers/spi/Makefile | 1 + > drivers/spi/spi-sifive.c | 375 + > 6 files changed, 394 insertions(+), 4 deletions(-) > create mode 100644 drivers/spi/spi-sifive.c I would like to pick entire series on spi tree, but it has some boards changes so I would like to ask the board maintainers to give a permissions to do so, if not possible I can take only spi changes. Jagan. ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v5 2/4] spi: Add SiFive SPI driver
On Wed, Jul 17, 2019 at 9:31 AM Jagan Teki wrote: > > On Wed, Jul 17, 2019 at 9:20 AM Anup Patel wrote: > > > > From: Bhargav Shah > > > > This patch adds SiFive SPI driver. The driver is 100% DM driver > > and it determines input clock using clk framework. > > > > The SiFive SPI block is found on SiFive FU540 SOC and is used to > > access flash and MMC devices on SiFive Unleashed board. > > > > This driver implementation is inspired from the Linux SiFive SPI > > driver available in Linux-5.2 or higher and SiFive FSBL sources. > > > > Signed-off-by: Bhargav Shah > > Signed-off-by: Anup Patel > > Reviewed-by: Bin Meng > > Tested-by: Bin Meng > > --- > > drivers/spi/Kconfig | 8 + > > drivers/spi/Makefile | 1 + > > drivers/spi/spi-sifive.c | 375 +++ > > 3 files changed, 384 insertions(+) > > create mode 100644 drivers/spi/spi-sifive.c > > > > diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig > > index eb32f082fe..030f3377d4 100644 > > --- a/drivers/spi/Kconfig > > +++ b/drivers/spi/Kconfig > > @@ -224,6 +224,14 @@ config SANDBOX_SPI > > }; > > }; > > > > +config SPI_SIFIVE > > + bool "SiFive SPI driver" > > + help > > + This driver supports the SiFive SPI IP. If unsure say N. > > + Enable the SiFive SPI controller driver. > > + > > + The SiFive SPI controller driver is found on various SiFive SoCs. > > + > > config SPI_SUNXI > > bool "Allwinner SoC SPI controllers" > > help > > diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile > > index 8be9a4baa2..a53b9f4217 100644 > > --- a/drivers/spi/Makefile > > +++ b/drivers/spi/Makefile > > @@ -49,6 +49,7 @@ obj-$(CONFIG_PL022_SPI) += pl022_spi.o > > obj-$(CONFIG_RENESAS_RPC_SPI) += renesas_rpc_spi.o > > obj-$(CONFIG_ROCKCHIP_SPI) += rk_spi.o > > obj-$(CONFIG_SANDBOX_SPI) += sandbox_spi.o > > +obj-$(CONFIG_SPI_SIFIVE) += spi-sifive.o > > obj-$(CONFIG_SPI_SUNXI) += spi-sunxi.o > > obj-$(CONFIG_SH_SPI) += sh_spi.o > > obj-$(CONFIG_SH_QSPI) += sh_qspi.o > > diff --git a/drivers/spi/spi-sifive.c b/drivers/spi/spi-sifive.c > > new file mode 100644 > > index 00..08f30f3f21 > > --- /dev/null > > +++ b/drivers/spi/spi-sifive.c > > @@ -0,0 +1,375 @@ > > +// SPDX-License-Identifier: GPL-2.0+ > > +/* > > + * Copyright 2018 SiFive, Inc. > > + * Copyright 2019 Bhargav Shah > > + * > > + * SiFive SPI controller driver (master mode only) > > + */ > > + > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > + > > +#define SIFIVE_SPI_MAX_CS 32 > > + > > +#define SIFIVE_SPI_DEFAULT_DEPTH 8 > > +#define SIFIVE_SPI_DEFAULT_BITS8 > > + > > +/* register offsets */ > > +#define SIFIVE_SPI_REG_SCKDIV0x00 /* Serial clock divisor */ > > +#define SIFIVE_SPI_REG_SCKMODE 0x04 /* Serial clock mode */ > > +#define SIFIVE_SPI_REG_CSID 0x10 /* Chip select ID */ > > +#define SIFIVE_SPI_REG_CSDEF 0x14 /* Chip select default */ > > +#define SIFIVE_SPI_REG_CSMODE0x18 /* Chip select mode */ > > +#define SIFIVE_SPI_REG_DELAY00x28 /* Delay control 0 */ > > +#define SIFIVE_SPI_REG_DELAY10x2c /* Delay control 1 */ > > +#define SIFIVE_SPI_REG_FMT 0x40 /* Frame format */ > > +#define SIFIVE_SPI_REG_TXDATA0x48 /* Tx FIFO data */ > > +#define SIFIVE_SPI_REG_RXDATA0x4c /* Rx FIFO data */ > > +#define SIFIVE_SPI_REG_TXMARK0x50 /* Tx FIFO watermark */ > > +#define SIFIVE_SPI_REG_RXMARK0x54 /* Rx FIFO watermark */ > > +#define SIFIVE_SPI_REG_FCTRL 0x60 /* SPI flash interface > > control */ > > +#define SIFIVE_SPI_REG_FFMT 0x64 /* SPI flash instruction > > format */ > > +#define SIFIVE_SPI_REG_IE0x70 /* Interrupt Enable Register > > */ > > +#define SIFIVE_SPI_REG_IP0x74 /* Interrupt Pendings > > Register */ > > + > > +/* sckdiv bits */ > > +#define SIFIVE_SPI_SCKDIV_DIV_MASK 0xfffU > > + > > +/* sckmode bits */ > > +#define SIFIVE_SPI_SCKMODE_PHA BIT(0) > > +#define SIFIVE_SPI_SCKMODE_POL BIT(1) > > +#define SIFIVE_SPI_SCKMODE_MODE_MASK (SIFIVE_SPI_SCKMODE_PHA | \ > > + SIFIVE_SPI_SCKMODE_POL) > > + > > +/* csmode bits */ > > +#define SIFIVE_SPI_CSMODE_MODE_AUTO 0U > > +#define SIFIVE_SPI_CSMODE_MODE_HOLD 2U > > +#define SIFIVE_SPI_CSMODE_MODE_OFF 3U > > + > > +/* delay0 bits */ > > +#define SIFIVE_SPI_DELAY0_CSSCK(x) ((u32)(x)) > > +#define SIFIVE_SPI_DELAY0_CSSCK_MASK 0xffU > > +#define SIFIVE_SPI_DELAY0_SCKCS(x) ((u32)(x) << 16) > > +#define SIFIVE_SPI_DELAY0_SCKCS_MASK (0xffU << 16) > > + > > +/* delay1 bits */ > > +#define SIFIVE_SPI_DELAY1_INTERCS(x) ((u32)(x)) > > +#define SIFIVE_SPI_DELAY1_INTERCS_MASK 0xffU > > +#define
Re: [U-Boot] [PATCH v5 3/4] riscv: sifive: fu540: Enable SiFive SPI and MMC SPI drivers
On Wed, Jul 17, 2019 at 9:20 AM Anup Patel wrote: > > From: Bhargav Shah > > This patch enables SiFive SPI and MMC SPI drivers for the > SiFive Unleashed board. > > Signed-off-by: Bhargav Shah > Signed-off-by: Anup Patel > Reviewed-by: Bin Meng > Tested-by: Bin Meng > --- Reviewed-by: Jagan Teki ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v5 1/4] mmc: mmc_spi: Use SPI_XFER_BEGIN and SPI_XFER_END flags
On Wed, Jul 17, 2019 at 9:20 AM Anup Patel wrote: > > Most DM based SPI host controller drivers use SPI_XFER_BEGIN and > SPI_XFER_END flags to enable/disable slave chip select. > > This patch extends MMC SPI driver to pass SPI_XFER_BEGIN flag when > MMC command is send at start and pass SPI_XFER_END flag using a > dummy transfer (of bitlen = 0) at the end of MMC command. > > Suggested-by: Jagan Teki > Signed-off-by: Anup Patel Reviewed-by: Jagan Teki ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v5 2/4] spi: Add SiFive SPI driver
On Wed, Jul 17, 2019 at 9:20 AM Anup Patel wrote: > > From: Bhargav Shah > > This patch adds SiFive SPI driver. The driver is 100% DM driver > and it determines input clock using clk framework. > > The SiFive SPI block is found on SiFive FU540 SOC and is used to > access flash and MMC devices on SiFive Unleashed board. > > This driver implementation is inspired from the Linux SiFive SPI > driver available in Linux-5.2 or higher and SiFive FSBL sources. > > Signed-off-by: Bhargav Shah > Signed-off-by: Anup Patel > Reviewed-by: Bin Meng > Tested-by: Bin Meng > --- > drivers/spi/Kconfig | 8 + > drivers/spi/Makefile | 1 + > drivers/spi/spi-sifive.c | 375 +++ > 3 files changed, 384 insertions(+) > create mode 100644 drivers/spi/spi-sifive.c > > diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig > index eb32f082fe..030f3377d4 100644 > --- a/drivers/spi/Kconfig > +++ b/drivers/spi/Kconfig > @@ -224,6 +224,14 @@ config SANDBOX_SPI > }; > }; > > +config SPI_SIFIVE > + bool "SiFive SPI driver" > + help > + This driver supports the SiFive SPI IP. If unsure say N. > + Enable the SiFive SPI controller driver. > + > + The SiFive SPI controller driver is found on various SiFive SoCs. > + > config SPI_SUNXI > bool "Allwinner SoC SPI controllers" > help > diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile > index 8be9a4baa2..a53b9f4217 100644 > --- a/drivers/spi/Makefile > +++ b/drivers/spi/Makefile > @@ -49,6 +49,7 @@ obj-$(CONFIG_PL022_SPI) += pl022_spi.o > obj-$(CONFIG_RENESAS_RPC_SPI) += renesas_rpc_spi.o > obj-$(CONFIG_ROCKCHIP_SPI) += rk_spi.o > obj-$(CONFIG_SANDBOX_SPI) += sandbox_spi.o > +obj-$(CONFIG_SPI_SIFIVE) += spi-sifive.o > obj-$(CONFIG_SPI_SUNXI) += spi-sunxi.o > obj-$(CONFIG_SH_SPI) += sh_spi.o > obj-$(CONFIG_SH_QSPI) += sh_qspi.o > diff --git a/drivers/spi/spi-sifive.c b/drivers/spi/spi-sifive.c > new file mode 100644 > index 00..08f30f3f21 > --- /dev/null > +++ b/drivers/spi/spi-sifive.c > @@ -0,0 +1,375 @@ > +// SPDX-License-Identifier: GPL-2.0+ > +/* > + * Copyright 2018 SiFive, Inc. > + * Copyright 2019 Bhargav Shah > + * > + * SiFive SPI controller driver (master mode only) > + */ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +#define SIFIVE_SPI_MAX_CS 32 > + > +#define SIFIVE_SPI_DEFAULT_DEPTH 8 > +#define SIFIVE_SPI_DEFAULT_BITS8 > + > +/* register offsets */ > +#define SIFIVE_SPI_REG_SCKDIV0x00 /* Serial clock divisor */ > +#define SIFIVE_SPI_REG_SCKMODE 0x04 /* Serial clock mode */ > +#define SIFIVE_SPI_REG_CSID 0x10 /* Chip select ID */ > +#define SIFIVE_SPI_REG_CSDEF 0x14 /* Chip select default */ > +#define SIFIVE_SPI_REG_CSMODE0x18 /* Chip select mode */ > +#define SIFIVE_SPI_REG_DELAY00x28 /* Delay control 0 */ > +#define SIFIVE_SPI_REG_DELAY10x2c /* Delay control 1 */ > +#define SIFIVE_SPI_REG_FMT 0x40 /* Frame format */ > +#define SIFIVE_SPI_REG_TXDATA0x48 /* Tx FIFO data */ > +#define SIFIVE_SPI_REG_RXDATA0x4c /* Rx FIFO data */ > +#define SIFIVE_SPI_REG_TXMARK0x50 /* Tx FIFO watermark */ > +#define SIFIVE_SPI_REG_RXMARK0x54 /* Rx FIFO watermark */ > +#define SIFIVE_SPI_REG_FCTRL 0x60 /* SPI flash interface control > */ > +#define SIFIVE_SPI_REG_FFMT 0x64 /* SPI flash instruction > format */ > +#define SIFIVE_SPI_REG_IE0x70 /* Interrupt Enable Register */ > +#define SIFIVE_SPI_REG_IP0x74 /* Interrupt Pendings Register > */ > + > +/* sckdiv bits */ > +#define SIFIVE_SPI_SCKDIV_DIV_MASK 0xfffU > + > +/* sckmode bits */ > +#define SIFIVE_SPI_SCKMODE_PHA BIT(0) > +#define SIFIVE_SPI_SCKMODE_POL BIT(1) > +#define SIFIVE_SPI_SCKMODE_MODE_MASK (SIFIVE_SPI_SCKMODE_PHA | \ > + SIFIVE_SPI_SCKMODE_POL) > + > +/* csmode bits */ > +#define SIFIVE_SPI_CSMODE_MODE_AUTO 0U > +#define SIFIVE_SPI_CSMODE_MODE_HOLD 2U > +#define SIFIVE_SPI_CSMODE_MODE_OFF 3U > + > +/* delay0 bits */ > +#define SIFIVE_SPI_DELAY0_CSSCK(x) ((u32)(x)) > +#define SIFIVE_SPI_DELAY0_CSSCK_MASK 0xffU > +#define SIFIVE_SPI_DELAY0_SCKCS(x) ((u32)(x) << 16) > +#define SIFIVE_SPI_DELAY0_SCKCS_MASK (0xffU << 16) > + > +/* delay1 bits */ > +#define SIFIVE_SPI_DELAY1_INTERCS(x) ((u32)(x)) > +#define SIFIVE_SPI_DELAY1_INTERCS_MASK 0xffU > +#define SIFIVE_SPI_DELAY1_INTERXFR(x)((u32)(x) << 16) > +#define SIFIVE_SPI_DELAY1_INTERXFR_MASK (0xffU << 16) > + > +/* fmt bits */ > +#define SIFIVE_SPI_FMT_PROTO_SINGLE 0U > +#define SIFIVE_SPI_FMT_PROTO_DUAL1U > +#define SIFIVE_SPI_FMT_PROTO_QUAD2U > +#define SIFIVE_SPI_FMT_PROTO_MASK3U > +#define
[U-Boot] [PATCH v5 3/4] riscv: sifive: fu540: Enable SiFive SPI and MMC SPI drivers
From: Bhargav Shah This patch enables SiFive SPI and MMC SPI drivers for the SiFive Unleashed board. Signed-off-by: Bhargav Shah Signed-off-by: Anup Patel Reviewed-by: Bin Meng Tested-by: Bin Meng --- board/sifive/fu540/Kconfig | 6 ++ 1 file changed, 6 insertions(+) diff --git a/board/sifive/fu540/Kconfig b/board/sifive/fu540/Kconfig index f46437901d..5d65080429 100644 --- a/board/sifive/fu540/Kconfig +++ b/board/sifive/fu540/Kconfig @@ -38,6 +38,12 @@ config BOARD_SPECIFIC_OPTIONS # dummy imply PHY_LIB imply PHY_MSCC imply SIFIVE_SERIAL + imply SPI + imply SPI_SIFIVE + imply MMC + imply MMC_SPI + imply MMC_BROKEN_CD + imply CMD_MMC imply SMP endif -- 2.17.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v5 4/4] doc: sifive-fu540: Update README for SiFive SPI and MMC SPI drivers
This patch removes SiFive SPI driver and MMC SPI drive from the TODO
list in SiFive FU540 README.
Signed-off-by: Anup Patel
Reviewed-by: Bin Meng
Tested-by: Bin Meng
---
doc/README.sifive-fu540 | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/doc/README.sifive-fu540 b/doc/README.sifive-fu540
index 33e03dc861..944ba1c8a0 100644
--- a/doc/README.sifive-fu540
+++ b/doc/README.sifive-fu540
@@ -13,9 +13,7 @@ The support for following drivers are already enabled:
3. Cadence MACB ethernet driver for networking support.
TODO:
-1. SPI host driver is still missing.
-2. SPI MMC driver does not compile and needs a re-write using U-Boot DM.
-2. U-Boot expects the serial console device entry to be present under /chosen
+1. U-Boot expects the serial console device entry to be present under /chosen
DT node. Example:
chosen {
stdout-path = "/soc/serial@1001:115200";
--
2.17.1
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[U-Boot] [PATCH v5 2/4] spi: Add SiFive SPI driver
From: Bhargav Shah This patch adds SiFive SPI driver. The driver is 100% DM driver and it determines input clock using clk framework. The SiFive SPI block is found on SiFive FU540 SOC and is used to access flash and MMC devices on SiFive Unleashed board. This driver implementation is inspired from the Linux SiFive SPI driver available in Linux-5.2 or higher and SiFive FSBL sources. Signed-off-by: Bhargav Shah Signed-off-by: Anup Patel Reviewed-by: Bin Meng Tested-by: Bin Meng --- drivers/spi/Kconfig | 8 + drivers/spi/Makefile | 1 + drivers/spi/spi-sifive.c | 375 +++ 3 files changed, 384 insertions(+) create mode 100644 drivers/spi/spi-sifive.c diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index eb32f082fe..030f3377d4 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -224,6 +224,14 @@ config SANDBOX_SPI }; }; +config SPI_SIFIVE + bool "SiFive SPI driver" + help + This driver supports the SiFive SPI IP. If unsure say N. + Enable the SiFive SPI controller driver. + + The SiFive SPI controller driver is found on various SiFive SoCs. + config SPI_SUNXI bool "Allwinner SoC SPI controllers" help diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 8be9a4baa2..a53b9f4217 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -49,6 +49,7 @@ obj-$(CONFIG_PL022_SPI) += pl022_spi.o obj-$(CONFIG_RENESAS_RPC_SPI) += renesas_rpc_spi.o obj-$(CONFIG_ROCKCHIP_SPI) += rk_spi.o obj-$(CONFIG_SANDBOX_SPI) += sandbox_spi.o +obj-$(CONFIG_SPI_SIFIVE) += spi-sifive.o obj-$(CONFIG_SPI_SUNXI) += spi-sunxi.o obj-$(CONFIG_SH_SPI) += sh_spi.o obj-$(CONFIG_SH_QSPI) += sh_qspi.o diff --git a/drivers/spi/spi-sifive.c b/drivers/spi/spi-sifive.c new file mode 100644 index 00..08f30f3f21 --- /dev/null +++ b/drivers/spi/spi-sifive.c @@ -0,0 +1,375 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 SiFive, Inc. + * Copyright 2019 Bhargav Shah + * + * SiFive SPI controller driver (master mode only) + */ + +#include +#include +#include +#include +#include +#include +#include + +#define SIFIVE_SPI_MAX_CS 32 + +#define SIFIVE_SPI_DEFAULT_DEPTH 8 +#define SIFIVE_SPI_DEFAULT_BITS8 + +/* register offsets */ +#define SIFIVE_SPI_REG_SCKDIV0x00 /* Serial clock divisor */ +#define SIFIVE_SPI_REG_SCKMODE 0x04 /* Serial clock mode */ +#define SIFIVE_SPI_REG_CSID 0x10 /* Chip select ID */ +#define SIFIVE_SPI_REG_CSDEF 0x14 /* Chip select default */ +#define SIFIVE_SPI_REG_CSMODE0x18 /* Chip select mode */ +#define SIFIVE_SPI_REG_DELAY00x28 /* Delay control 0 */ +#define SIFIVE_SPI_REG_DELAY10x2c /* Delay control 1 */ +#define SIFIVE_SPI_REG_FMT 0x40 /* Frame format */ +#define SIFIVE_SPI_REG_TXDATA0x48 /* Tx FIFO data */ +#define SIFIVE_SPI_REG_RXDATA0x4c /* Rx FIFO data */ +#define SIFIVE_SPI_REG_TXMARK0x50 /* Tx FIFO watermark */ +#define SIFIVE_SPI_REG_RXMARK0x54 /* Rx FIFO watermark */ +#define SIFIVE_SPI_REG_FCTRL 0x60 /* SPI flash interface control */ +#define SIFIVE_SPI_REG_FFMT 0x64 /* SPI flash instruction format */ +#define SIFIVE_SPI_REG_IE0x70 /* Interrupt Enable Register */ +#define SIFIVE_SPI_REG_IP0x74 /* Interrupt Pendings Register */ + +/* sckdiv bits */ +#define SIFIVE_SPI_SCKDIV_DIV_MASK 0xfffU + +/* sckmode bits */ +#define SIFIVE_SPI_SCKMODE_PHA BIT(0) +#define SIFIVE_SPI_SCKMODE_POL BIT(1) +#define SIFIVE_SPI_SCKMODE_MODE_MASK (SIFIVE_SPI_SCKMODE_PHA | \ + SIFIVE_SPI_SCKMODE_POL) + +/* csmode bits */ +#define SIFIVE_SPI_CSMODE_MODE_AUTO 0U +#define SIFIVE_SPI_CSMODE_MODE_HOLD 2U +#define SIFIVE_SPI_CSMODE_MODE_OFF 3U + +/* delay0 bits */ +#define SIFIVE_SPI_DELAY0_CSSCK(x) ((u32)(x)) +#define SIFIVE_SPI_DELAY0_CSSCK_MASK 0xffU +#define SIFIVE_SPI_DELAY0_SCKCS(x) ((u32)(x) << 16) +#define SIFIVE_SPI_DELAY0_SCKCS_MASK (0xffU << 16) + +/* delay1 bits */ +#define SIFIVE_SPI_DELAY1_INTERCS(x) ((u32)(x)) +#define SIFIVE_SPI_DELAY1_INTERCS_MASK 0xffU +#define SIFIVE_SPI_DELAY1_INTERXFR(x)((u32)(x) << 16) +#define SIFIVE_SPI_DELAY1_INTERXFR_MASK (0xffU << 16) + +/* fmt bits */ +#define SIFIVE_SPI_FMT_PROTO_SINGLE 0U +#define SIFIVE_SPI_FMT_PROTO_DUAL1U +#define SIFIVE_SPI_FMT_PROTO_QUAD2U +#define SIFIVE_SPI_FMT_PROTO_MASK3U +#define SIFIVE_SPI_FMT_ENDIANBIT(2) +#define SIFIVE_SPI_FMT_DIR BIT(3) +#define SIFIVE_SPI_FMT_LEN(x)((u32)(x) << 16) +#define SIFIVE_SPI_FMT_LEN_MASK (0xfU << 16) + +/* txdata bits */ +#define SIFIVE_SPI_TXDATA_DATA_MASK 0xffU +#define SIFIVE_SPI_TXDATA_FULL BIT(31) +
[U-Boot] [PATCH v5 0/4] SiFive SPI MMC Support
This patchset adds: 1. SiFive SPI driver 2. New MMC SPI driver based on DM_MMC and DM_SPI 3. Enables SiFive SPI driver and MMC SPI driver for SiFive Unleashed board With this patch series, we can now load files from SD card on SiFive Unleashed board. Many thanks to Bhargav for porting SiFive SPI driver and updating MMC SPI driver for us. These patches can be also found in riscv_unleashed_mmc_spi_v5 branch of: https//github.com/avpatel/u-boot.git Changes since v4: - Renamed kconfig option from SIFIVE_SPI to SPI_SIFIVE for consistency - Added dummy claim_bus() and release_bus() callbacks Changes since v3: - Removed PATCH2, PATCH3, and PATCH4 because these are already merged - Added separate patch to use SPI_XFER_xyz flags in MMC_SPI driver - Use readl/writel directly instead of sifive_spi_read/sifi_spi_write - Use SPI_XFER_xyz flags to enable/disable chipselect - Remove unused callback sifive_spi_cs_info() Changes since v2: - Minor fixes in PATCH1 which adds SiFive SPI driver - Removed CONFIG_MMC_SPI_xyz from scripts/config_whitelist.txt - Removed cmd/mmc_spi and all its refrences as separate patch - Removed DM_SPI and DM_MMC from SiFive FU540 Kconfig Changes since v1: - Make response matching part belongs to mmc_spi_sendcmd() - Match response to zero for SEND_STATUS (CMD13) - Add separate patch for updating SiFive FU540 Documentation Anup Patel (2): mmc: mmc_spi: Use SPI_XFER_BEGIN and SPI_XFER_END flags doc: sifive-fu540: Update README for SiFive SPI and MMC SPI drivers Bhargav Shah (2): spi: Add SiFive SPI driver riscv: sifive: fu540: Enable SiFive SPI and MMC SPI drivers board/sifive/fu540/Kconfig | 6 + doc/README.sifive-fu540| 4 +- drivers/mmc/mmc_spi.c | 4 +- drivers/spi/Kconfig| 8 + drivers/spi/Makefile | 1 + drivers/spi/spi-sifive.c | 375 + 6 files changed, 394 insertions(+), 4 deletions(-) create mode 100644 drivers/spi/spi-sifive.c -- 2.17.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v5 1/4] mmc: mmc_spi: Use SPI_XFER_BEGIN and SPI_XFER_END flags
Most DM based SPI host controller drivers use SPI_XFER_BEGIN and SPI_XFER_END flags to enable/disable slave chip select. This patch extends MMC SPI driver to pass SPI_XFER_BEGIN flag when MMC command is send at start and pass SPI_XFER_END flag using a dummy transfer (of bitlen = 0) at the end of MMC command. Suggested-by: Jagan Teki Signed-off-by: Anup Patel --- drivers/mmc/mmc_spi.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/mmc_spi.c b/drivers/mmc/mmc_spi.c index f3d687ae80..350812a04b 100644 --- a/drivers/mmc/mmc_spi.c +++ b/drivers/mmc/mmc_spi.c @@ -84,7 +84,7 @@ static int mmc_spi_sendcmd(struct udevice *dev, cmdo[4] = cmdarg >> 8; cmdo[5] = cmdarg; cmdo[6] = (crc7(0, [1], 5) << 1) | 0x01; - ret = dm_spi_xfer(dev, sizeof(cmdo) * 8, cmdo, NULL, 0); + ret = dm_spi_xfer(dev, sizeof(cmdo) * 8, cmdo, NULL, SPI_XFER_BEGIN); if (ret) return ret; @@ -360,6 +360,8 @@ static int dm_mmc_spi_request(struct udevice *dev, struct mmc_cmd *cmd, } done: + dm_spi_xfer(dev, 0, NULL, NULL, SPI_XFER_END); + dm_spi_release_bus(dev); return ret; -- 2.17.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 0/5] travis: Build and test ASPEED board
Hello, On Thu, 4 Jul 2019 at 01:35, Joel Stanley wrote: > > Tom suggested I add support for booting the ASPEED EVB configuration in > Qemu. This series fixes up a few things with the defconfig so buildman > passes, and makes u-boot testable: > > https://travis-ci.com/shenki/u-boot/builds/117772801 > > I've sent some patches to Stephen for uboot-test-scripts tools > that need to be merged before this Travis configuration can go in. Stephen has merged the uboot-test-scripts patches now. How do I go about getting this series merged? Cheers, Joel > > Joel Stanley (5): > configs: aspeed: Unset CONFIG_MMC > configs: aspeed: Add HUSH and random ethernet addr > traivs: Build aspeed boards > travis: Add ASPEED ast2500 to qemu tests > travis: Build aspeed board with qemu HEAD > > .travis.yml | 10 ++ > configs/evb-ast2500_defconfig | 3 +++ > 2 files changed, 13 insertions(+) > > -- > 2.20.1 > ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 1/1] efi_loader: add more sources to Sphinx documentation
On Sun, Jul 14, 2019 at 8:47 PM Heinrich Schuchardt wrote: > > Add more C files as sources to the Sphinx generated documentaton > (make htmldocs). > > Signed-off-by: Heinrich Schuchardt > --- > doc/efi.rst | 87 +++-- > 1 file changed, 85 insertions(+), 2 deletions(-) > Reviewed-by: Bin Meng ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 1/1] travis-ci: qemu-system-riscv64: Parameter 'id' is missing
On Wed, Jul 17, 2019 at 7:36 AM Heinrich Schuchardt wrote:
>
> When testing qemu-riscv64_defconfig on Travis CI I got a QEMU erorr
> "Parameter 'id' is missing".
>
> A command launching qemu-riscv64_defconfig successfully on Debian is:
>
> qemu-system-riscv64 \
> -machine virt \
> -kernel u-boot \
> -m 1G -nographic -netdev user,id=net0,tftp=$tftpdir \
> -device virtio-net-device,netdev=net0
>
> Add the missing id.
>
> Fixes: 990b317fdcc4 ("travis-ci: add qemu-riscv64")
> Signed-off-by: Heinrich Schuchardt
> ---
> bin/travis-ci/conf.qemu-riscv64_na | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
Reviewed-by: Bin Meng
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Re: [U-Boot] [RFC PATCH 1/9] doc: Move existing rst files into api sub-directory
Hi Heinrich, On Wed, Jul 17, 2019 at 7:43 AM Heinrich Schuchardt wrote: > > On 7/16/19 8:03 PM, Heinrich Schuchardt wrote: > > On 7/16/19 6:42 PM, Bin Meng wrote: > >> Currently the Sphinx doc only contains API descriptions of several > >> U-Boot subsystems. For future extension, group these existing docs > >> into an API sub-directory. > >> > >> Signed-off-by: Bin Meng > > > > Reviewed-by: Heinrich Schuchardt > > > > Hello Bin, > > efi_loader: add more sources to Sphinx documentation > https://lists.denx.de/pipermail/u-boot/2019-July/376382.html > https://patchwork.ozlabs.org/patch/1131726/ > > This patch may lead to a merge conflict. > > If you resubmit, consider rebasing on it. Thanks for the review. I will rebase on that when I resubmit this series. Regards, Bin ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v3 1/2] rockchip: make_fit_atf.py: Eliminate pyelftools dependency
Hi Chris:
On 7/17/19 3:52 AM, Chris Webb wrote:
make_fit_aft.py depends on the non-standard library pyelftools to pull
out PT_LOAD segments from ELF files. However, this is as easy to do
manually, without imposing the extra dependency on users.
Structures in the ELF file are unpacked into variables named to exactly
match the ELF spec to ensure the destructuring code is reasonably
self-documenting.
Signed-off-by: Chris Webb
Reviewed-by: Andy Yan
---
arch/arm/mach-rockchip/make_fit_atf.py | 75 +++---
1 file changed, 32 insertions(+), 43 deletions(-)
diff --git a/arch/arm/mach-rockchip/make_fit_atf.py
b/arch/arm/mach-rockchip/make_fit_atf.py
index db0ae96ca8..b9a1988298 100755
--- a/arch/arm/mach-rockchip/make_fit_atf.py
+++ b/arch/arm/mach-rockchip/make_fit_atf.py
@@ -13,16 +13,7 @@ import os
import sys
import getopt
import logging
-
-# pip install pyelftools
-from elftools.elf.elffile import ELFFile
-
-ELF_SEG_P_TYPE = 'p_type'
-ELF_SEG_P_PADDR = 'p_paddr'
-ELF_SEG_P_VADDR = 'p_vaddr'
-ELF_SEG_P_OFFSET = 'p_offset'
-ELF_SEG_P_FILESZ = 'p_filesz'
-ELF_SEG_P_MEMSZ = 'p_memsz'
+import struct
DT_HEADER = """
/*
@@ -118,33 +109,19 @@ def append_conf_node(file, dtbs, segments):
file.write('\n')
def generate_atf_fit_dts_uboot(fit_file, uboot_file_name):
-num_load_seg = 0
-p_paddr = 0x
-with open(uboot_file_name, 'rb') as uboot_file:
-uboot = ELFFile(uboot_file)
-for i in range(uboot.num_segments()):
-seg = uboot.get_segment(i)
-if seg.__getitem__(ELF_SEG_P_TYPE) == 'PT_LOAD':
-p_paddr = seg.__getitem__(ELF_SEG_P_PADDR)
-num_load_seg = num_load_seg + 1
-
-assert (p_paddr != 0x and num_load_seg == 1)
-
+segments = unpack_elf(uboot_file_name)
+if len(segments) != 1:
+raise ValueError("Invalid u-boot ELF image '%s'" % uboot_file_name)
+index, entry, p_paddr, data = segments[0]
fit_file.write(DT_UBOOT % p_paddr)
def generate_atf_fit_dts_bl31(fit_file, bl31_file_name, dtbs_file_name):
-with open(bl31_file_name, 'rb') as bl31_file:
-bl31 = ELFFile(bl31_file)
-elf_entry = bl31.header['e_entry']
-segments = bl31.num_segments()
-for i in range(segments):
-seg = bl31.get_segment(i)
-if seg.__getitem__(ELF_SEG_P_TYPE) == 'PT_LOAD':
-paddr = seg.__getitem__(ELF_SEG_P_PADDR)
-append_bl31_node(fit_file, i + 1, paddr, elf_entry)
+segments = unpack_elf(bl31_file_name)
+for index, entry, paddr, data in segments:
+append_bl31_node(fit_file, index + 1, paddr, entry)
append_fdt_node(fit_file, dtbs_file_name)
fit_file.write(DT_IMAGES_NODE_END)
-append_conf_node(fit_file, dtbs_file_name, segments)
+append_conf_node(fit_file, dtbs_file_name, len(segments))
def generate_atf_fit_dts(fit_file_name, bl31_file_name, uboot_file_name, dtbs_file_name):
# Generate FIT script for ATF image.
@@ -162,17 +139,29 @@ def generate_atf_fit_dts(fit_file_name, bl31_file_name,
uboot_file_name, dtbs_fi
fit_file.close()
def generate_atf_binary(bl31_file_name):
-with open(bl31_file_name, 'rb') as bl31_file:
-bl31 = ELFFile(bl31_file)
-
-num = bl31.num_segments()
-for i in range(num):
-seg = bl31.get_segment(i)
-if seg.__getitem__(ELF_SEG_P_TYPE) == 'PT_LOAD':
-paddr = seg.__getitem__(ELF_SEG_P_PADDR)
-file_name = 'bl31_0x%08x.bin' % paddr
-with open(file_name, "wb") as atf:
-atf.write(seg.data())
+for index, entry, paddr, data in unpack_elf(bl31_file_name):
+file_name = 'bl31_0x%08x.bin' % paddr
+with open(file_name, "wb") as atf:
+atf.write(data)
+
+def unpack_elf(filename):
+with open(filename, 'rb') as file:
+elf = file.read()
+if elf[0:7] != b'\x7fELF\x02\x01\x01' or elf[18:20] != b'\xb7\x00':
+raise ValueError("Invalid arm64 ELF file '%s'" % filename)
+
+e_entry, e_phoff = struct.unpack_from('<2Q', elf, 0x18)
+e_phentsize, e_phnum = struct.unpack_from('<2H', elf, 0x36)
+segments = []
+
+for index in range(e_phnum):
+offset = e_phoff + e_phentsize * index
+p_type, p_flags, p_offset = struct.unpack_from('
def main():
uboot_elf = "./u-boot"
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Re: [U-Boot] [RFC PATCH 1/9] doc: Move existing rst files into api sub-directory
On 7/16/19 8:03 PM, Heinrich Schuchardt wrote: On 7/16/19 6:42 PM, Bin Meng wrote: Currently the Sphinx doc only contains API descriptions of several U-Boot subsystems. For future extension, group these existing docs into an API sub-directory. Signed-off-by: Bin Meng Reviewed-by: Heinrich Schuchardt Hello Bin, efi_loader: add more sources to Sphinx documentation https://lists.denx.de/pipermail/u-boot/2019-July/376382.html https://patchwork.ozlabs.org/patch/1131726/ This patch may lead to a merge conflict. If you resubmit, consider rebasing on it. Best regards Heinrich ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 1/1] travis-ci: qemu-system-riscv64: Parameter 'id' is missing
When testing qemu-riscv64_defconfig on Travis CI I got a QEMU erorr
"Parameter 'id' is missing".
A command launching qemu-riscv64_defconfig successfully on Debian is:
qemu-system-riscv64 \
-machine virt \
-kernel u-boot \
-m 1G -nographic -netdev user,id=net0,tftp=$tftpdir \
-device virtio-net-device,netdev=net0
Add the missing id.
Fixes: 990b317fdcc4 ("travis-ci: add qemu-riscv64")
Signed-off-by: Heinrich Schuchardt
---
bin/travis-ci/conf.qemu-riscv64_na | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/bin/travis-ci/conf.qemu-riscv64_na
b/bin/travis-ci/conf.qemu-riscv64_na
index b375e2b..65b2096 100644
--- a/bin/travis-ci/conf.qemu-riscv64_na
+++ b/bin/travis-ci/conf.qemu-riscv64_na
@@ -5,7 +5,7 @@
console_impl=qemu
qemu_machine="virt"
qemu_binary="qemu-system-riscv64"
-qemu_extra_args="-m 1G -nographic -netdev user,tftp=${UBOOT_TRAVIS_BUILD_DIR}
-device virtio-net-device,netdev=user"
+qemu_extra_args="-m 1G -nographic -netdev
user,id=net0,tftp=${UBOOT_TRAVIS_BUILD_DIR} -device
virtio-net-device,netdev=net0"
qemu_kernel_args="-kernel ${U_BOOT_BUILD_DIR}/u-boot"
reset_impl=none
flash_impl=none
--
2.20.1
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[U-Boot] [PATCH v2 1/1] disk: efi: avoid unaligned pointer error
When building with GCC 9.1 an error occurs:
disk/part_efi.c: In function ‘gpt_verify_partitions’:
disk/part_efi.c:737:49: error: taking address of packed member of
‘struct _gpt_entry’ may result in an unaligned pointer value
[-Werror=address-of-packed-member]
737 | gpt_convert_efi_name_to_char(efi_str, gpt_e[i].partition_name,
| ^~~
cc1: all warnings being treated as errors
make[1]: *** [scripts/Makefile.build:279: disk/part_efi.o] Error 1
make: *** [Makefile:1594: disk] Error 2
Adjust gpt_convert_efi_name_to_char() to accept unaligned strings.
Reported-by: Ramon Fried
Signed-off-by: Heinrich Schuchardt
---
v2
remove unrelated change
---
disk/part_efi.c | 13 +++--
1 file changed, 11 insertions(+), 2 deletions(-)
diff --git a/disk/part_efi.c b/disk/part_efi.c
index 3e026697db..359b55a818 100644
--- a/disk/part_efi.c
+++ b/disk/part_efi.c
@@ -670,9 +670,18 @@ err:
return ret;
}
-static void gpt_convert_efi_name_to_char(char *s, efi_char16_t *es, int n)
+/**
+ * gpt_convert_efi_name_to_char() - convert u16 string to char string
+ *
+ * TODO: this conversion only supports ANSI characters
+ *
+ * @s: target buffer
+ * @es:u16 string to be converted
+ * @n: size of target buffer
+ */
+static void gpt_convert_efi_name_to_char(char *s, void *es, int n)
{
- char *ess = (char *)es;
+ char *ess = es;
int i, j;
memset(s, '\0', n);
--
2.20.1
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[U-Boot] [PATCH] spl: implement stack usage check
This implements a stack usage check in SPL.
Many boards start up SPL to run code + data from one common, rather small
SRAM. To implement a sophisticated SPL binary size limit on such boards,
the stack size (as well as malloc size and global data size) must be
subtracted from this SRAM size.
However, to do that properly, the stack size first needs to be known.
This patch adds a new Kconfig option:
- SPL_SYS_REPORT_STACK_F_USAGE: memset(0xaa) the whole area of the stack
very early and check stack usage based on this constant later before the
stack is switched to DRAM
Initializing the stack and checking it is implemented in weak functions,
in case a board does not use the stack as saved in gd->start_addr_sp.
Signed-off-by: Simon Goldschmidt
---
common/init/board_init.c | 20
common/spl/Kconfig | 19 +++
common/spl/spl.c | 25 +
3 files changed, 64 insertions(+)
diff --git a/common/init/board_init.c b/common/init/board_init.c
index 526fee35ff..e52106966d 100644
--- a/common/init/board_init.c
+++ b/common/init/board_init.c
@@ -18,6 +18,23 @@ __weak void arch_setup_gd(struct global_data *gd_ptr)
}
#endif /* !CONFIG_X86 && !CONFIG_ARM */
+/**
+ * This function is called after the position of the initial stack is
+ * determined in gd->start_addr_sp. Boards can override it to set up
+ * stack-checking markers.
+ */
+__weak void board_init_f_init_stack_protection(void)
+{
+#if CONFIG_IS_ENABLED(SYS_REPORT_STACK_F_USAGE)
+ ulong stack_bottom = gd->start_addr_sp -
+ CONFIG_VAL(SIZE_LIMIT_PROVIDE_STACK);
+
+ /* substact some safety margin (0x20) since stack is in use here */
+ memset((void *)stack_bottom, CONFIG_VAL(SYS_STACK_F_CHECK_BYTE),
+ CONFIG_VAL(SIZE_LIMIT_PROVIDE_STACK) - 0x20);
+#endif
+}
+
/*
* Allocate reserved space for use as 'globals' from 'top' address and
* return 'bottom' address of allocated space
@@ -126,6 +143,9 @@ void board_init_f_init_reserve(ulong base)
/* next alloc will be higher by one 'early malloc arena' size */
base += CONFIG_VAL(SYS_MALLOC_F_LEN);
#endif
+
+ if (CONFIG_IS_ENABLED(SYS_REPORT_STACK_F_USAGE))
+ board_init_f_init_stack_protection();
}
/*
diff --git a/common/spl/Kconfig b/common/spl/Kconfig
index 126931bace..85e1c9158c 100644
--- a/common/spl/Kconfig
+++ b/common/spl/Kconfig
@@ -62,6 +62,25 @@ config SPL_SIZE_LIMIT_PROVIDE_STACK
of SRAM available for SPL when the stack required before reolcation
uses this SRAM, too.
+config SPL_SYS_STACK_F_CHECK_BYTE
+ hex
+ default 0xaa
+ help
+ Constant used to check the stack
+
+config SPL_SYS_REPORT_STACK_F_USAGE
+ depends on SPL_SIZE_LIMIT_PROVIDE_STACK != 0
+ bool "Check and report stack usage in SPL before relocation"
+ help
+ If this option is enabled, the initial SPL stack is filled with 0xaa
+ very early, up to the size configured with
+ SPL_SIZE_LIMIT_PROVIDE_STACK.
+ Later when SPL is done using this initial stack and switches to a
+ stack in DRAM, the actually used size of this initial stack is
+ reported by examining the memory and searching for the lowest
+ occurrence of non 0xaa bytes.
+ This default implementation works for stacks growing down only.
+
menu "PowerPC SPL Boot options"
depends on PPC && (SUPPORT_SPL && !SPL_FRAMEWORK)
diff --git a/common/spl/spl.c b/common/spl/spl.c
index d5e3f680f4..4918e4f320 100644
--- a/common/spl/spl.c
+++ b/common/spl/spl.c
@@ -709,6 +709,28 @@ void preloader_console_init(void)
}
#endif
+/**
+ * This function is called before the stack is changed from initial stack to
+ * relocated stack. It tries to dump the stack size used
+ */
+__weak void spl_relocate_stack_check(void)
+{
+#if CONFIG_IS_ENABLED(SYS_REPORT_STACK_F_USAGE)
+ ulong init_sp = gd->start_addr_sp;
+ ulong stack_bottom = init_sp - CONFIG_VAL(SIZE_LIMIT_PROVIDE_STACK);
+ u8 *ptr = (u8 *)stack_bottom;
+ ulong i;
+
+ for (i = 0; i < CONFIG_VAL(SIZE_LIMIT_PROVIDE_STACK); i++) {
+ if (*ptr != CONFIG_VAL(SYS_STACK_F_CHECK_BYTE))
+ break;
+ ptr++;
+ }
+ printf("SPL initial stack usage: %lu bytes\n",
+ CONFIG_VAL(SIZE_LIMIT_PROVIDE_STACK) - i);
+#endif
+}
+
/**
* spl_relocate_stack_gd() - Relocate stack ready for board_init_r() execution
*
@@ -733,6 +755,9 @@ ulong spl_relocate_stack_gd(void)
gd_t *new_gd;
ulong ptr = CONFIG_SPL_STACK_R_ADDR;
+ if (CONFIG_IS_ENABLED(SYS_REPORT_STACK_F_USAGE))
+ spl_relocate_stack_check();
+
#if defined(CONFIG_SPL_SYS_MALLOC_SIMPLE) && CONFIG_VAL(SYS_MALLOC_F_LEN)
if (CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN) {
debug("SPL malloc() before relocation used 0x%lx bytes (%ld
KB)\n",
--
2.20.1
[U-Boot] [PATCH v3 2/2] rockchip: Remove obsolete references to pyelftools
make_fit_atf.py no longer requires pyelftools, and nothing else in the rockchip build requires it either, so remove references to installing it from the documentation. Signed-off-by: Chris Webb --- board/rockchip/evb_rk3399/README | 6 -- doc/README.rockchip | 4 2 files changed, 10 deletions(-) diff --git a/board/rockchip/evb_rk3399/README b/board/rockchip/evb_rk3399/README index 6469821987..ea3258cf37 100644 --- a/board/rockchip/evb_rk3399/README +++ b/board/rockchip/evb_rk3399/README @@ -35,12 +35,6 @@ Get the Source and prebuild binary > git clone https://github.com/rockchip-linux/rkbin.git > git clone https://github.com/rockchip-linux/rkdeveloptool.git -Get some prerequisites -== - -You need the Python elftools.elf.elffile library for make_fit_atf.py to work: - - > sudo apt-get install python-pyelftools Compile ATF === diff --git a/doc/README.rockchip b/doc/README.rockchip index 02e2497b15..8ccbb87264 100644 --- a/doc/README.rockchip +++ b/doc/README.rockchip @@ -123,10 +123,6 @@ For example: Option 2: Package the image with SPL: - - We need the Python elftools.elf.elffile library for make_fit_atf.py to work - - => sudo apt-get install python-pyelftools - - Export cross compiler path for aarch64 - Compile ATF ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v3 1/2] rockchip: make_fit_atf.py: Eliminate pyelftools dependency
make_fit_aft.py depends on the non-standard library pyelftools to pull
out PT_LOAD segments from ELF files. However, this is as easy to do
manually, without imposing the extra dependency on users.
Structures in the ELF file are unpacked into variables named to exactly
match the ELF spec to ensure the destructuring code is reasonably
self-documenting.
Signed-off-by: Chris Webb
---
arch/arm/mach-rockchip/make_fit_atf.py | 75 +++---
1 file changed, 32 insertions(+), 43 deletions(-)
diff --git a/arch/arm/mach-rockchip/make_fit_atf.py
b/arch/arm/mach-rockchip/make_fit_atf.py
index db0ae96ca8..b9a1988298 100755
--- a/arch/arm/mach-rockchip/make_fit_atf.py
+++ b/arch/arm/mach-rockchip/make_fit_atf.py
@@ -13,16 +13,7 @@ import os
import sys
import getopt
import logging
-
-# pip install pyelftools
-from elftools.elf.elffile import ELFFile
-
-ELF_SEG_P_TYPE = 'p_type'
-ELF_SEG_P_PADDR = 'p_paddr'
-ELF_SEG_P_VADDR = 'p_vaddr'
-ELF_SEG_P_OFFSET = 'p_offset'
-ELF_SEG_P_FILESZ = 'p_filesz'
-ELF_SEG_P_MEMSZ = 'p_memsz'
+import struct
DT_HEADER = """
/*
@@ -118,33 +109,19 @@ def append_conf_node(file, dtbs, segments):
file.write('\n')
def generate_atf_fit_dts_uboot(fit_file, uboot_file_name):
-num_load_seg = 0
-p_paddr = 0x
-with open(uboot_file_name, 'rb') as uboot_file:
-uboot = ELFFile(uboot_file)
-for i in range(uboot.num_segments()):
-seg = uboot.get_segment(i)
-if seg.__getitem__(ELF_SEG_P_TYPE) == 'PT_LOAD':
-p_paddr = seg.__getitem__(ELF_SEG_P_PADDR)
-num_load_seg = num_load_seg + 1
-
-assert (p_paddr != 0x and num_load_seg == 1)
-
+segments = unpack_elf(uboot_file_name)
+if len(segments) != 1:
+raise ValueError("Invalid u-boot ELF image '%s'" % uboot_file_name)
+index, entry, p_paddr, data = segments[0]
fit_file.write(DT_UBOOT % p_paddr)
def generate_atf_fit_dts_bl31(fit_file, bl31_file_name, dtbs_file_name):
-with open(bl31_file_name, 'rb') as bl31_file:
-bl31 = ELFFile(bl31_file)
-elf_entry = bl31.header['e_entry']
-segments = bl31.num_segments()
-for i in range(segments):
-seg = bl31.get_segment(i)
-if seg.__getitem__(ELF_SEG_P_TYPE) == 'PT_LOAD':
-paddr = seg.__getitem__(ELF_SEG_P_PADDR)
-append_bl31_node(fit_file, i + 1, paddr, elf_entry)
+segments = unpack_elf(bl31_file_name)
+for index, entry, paddr, data in segments:
+append_bl31_node(fit_file, index + 1, paddr, entry)
append_fdt_node(fit_file, dtbs_file_name)
fit_file.write(DT_IMAGES_NODE_END)
-append_conf_node(fit_file, dtbs_file_name, segments)
+append_conf_node(fit_file, dtbs_file_name, len(segments))
def generate_atf_fit_dts(fit_file_name, bl31_file_name, uboot_file_name,
dtbs_file_name):
# Generate FIT script for ATF image.
@@ -162,17 +139,29 @@ def generate_atf_fit_dts(fit_file_name, bl31_file_name,
uboot_file_name, dtbs_fi
fit_file.close()
def generate_atf_binary(bl31_file_name):
-with open(bl31_file_name, 'rb') as bl31_file:
-bl31 = ELFFile(bl31_file)
-
-num = bl31.num_segments()
-for i in range(num):
-seg = bl31.get_segment(i)
-if seg.__getitem__(ELF_SEG_P_TYPE) == 'PT_LOAD':
-paddr = seg.__getitem__(ELF_SEG_P_PADDR)
-file_name = 'bl31_0x%08x.bin' % paddr
-with open(file_name, "wb") as atf:
-atf.write(seg.data())
+for index, entry, paddr, data in unpack_elf(bl31_file_name):
+file_name = 'bl31_0x%08x.bin' % paddr
+with open(file_name, "wb") as atf:
+atf.write(data)
+
+def unpack_elf(filename):
+with open(filename, 'rb') as file:
+elf = file.read()
+if elf[0:7] != b'\x7fELF\x02\x01\x01' or elf[18:20] != b'\xb7\x00':
+raise ValueError("Invalid arm64 ELF file '%s'" % filename)
+
+e_entry, e_phoff = struct.unpack_from('<2Q', elf, 0x18)
+e_phentsize, e_phnum = struct.unpack_from('<2H', elf, 0x36)
+segments = []
+
+for index in range(e_phnum):
+offset = e_phoff + e_phentsize * index
+p_type, p_flags, p_offset = struct.unpack_from('https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v3 0/2] rockchip: make_fit_atf.py Eliminate pyelftools dependency
Building for rockchip, make_fit_atf.py depends on pyelftools, a non-bundled python module that is not used elsewhere in building u-boot or the kernel. We only use pyelftools to pull out PT_LOAD segments. ELF is very simple, so doing this manually is easy and spares users the extra dependency. In fact, a straightforward implementation shrinks make_fit_aft.py rather than adding complexity. Andy Yan's patch https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip/commit/619f002db864ef8caa30863bde62df5c651a7312 is a prerequisite for this. The new code does not erroneously count GNU_STACK sections and therefore without the above patch, the loadables in the conf section will always be one short, even where GNU_STACK is present. I have tested this script with python 2 and 3 against all bl31 elf files at https://github.com/rockchip-linux/rkbin/tree/master/bin/rk33 as well as an rk3399 bl31.elf built locally from the master branch of https://github.com/ARM-software/arm-trusted-firmware to which my toolchain added the extra GNU_STACK segment. In each case, identical *.bin files were produced compared to the pyelftools implementation, and a correct .its configuration (without off-by-one error) was emitted, with and without dtbs supplied to the script. Changes in v2: - no exception on a valid but completely empty bl31 ELF file - restrict documentation updates to the Rockchip docs (!) Changes in v3: - code style: add correct whitespace around multiply operator ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v4] spl: kconfig: separate sysreset and firmware drivers from misc
This adds separate kconfig options for drivers/sysreset and drivers/firmware. Up to now, CONFIG_SPL_DRIVERS_MISC_SUPPORT added drivers/misc to SPL build but also added drivers/firmware and drivers/sysreset at the same time. Since that is confusing, this patch uses CONFIG_SPL_SYSRESET for drivers/sysreset and adds CONFIG_SPL_FIRMWARE for drivers/firmware (and accordingly for the TPL options). CONFIG_SPL_DRIVERS_MISC_SUPPORT stays for including drivers/misc into the SPL build (and accordingly for TPL) since there are boards using non-DM (non UCLASS_MISC) files from drivers/misc. Such boards don't have CONFIG_SPL_MISC enabled, so cannot use this to include drivers/misc into the SPL build. Signed-off-by: Simon Goldschmidt --- Changes in v4: - drivers/Makefile: combine subdirectory include statements for SPL, TPL and U-Boot instead of duplicating lines Changes in v3: - Revert to keeping CONFIG_SPL_DRIVERS_MISC_SUPPORT as there are boards that need to include drivers/misc without UCLASS_MISC being enabled - Only CONFIG_SPL_FIRMWARE is added as new config symbol. To ensure no arch Kconfig files need to be changed, add dependencies to ensure this is enabled where required. Changes in v2: - adapt config names to match the non-SPL config options: - changed CONFIG_SPL_SYSRESET_SUPPORT to CONFIG_SPL_SYSRESET - changed CONFIG_SPL_DRIVERS_FIRMWARE_SUPPORT to CONFIG_SPL_FIRMWARE - changed CONFIG_SPL_DRIVERS_MISC_SUPPORT to CONFIG_SPL_MISC configs/evb-rk3036_defconfig | 1 + configs/kylin-rk3036_defconfig | 1 + configs/sandbox_spl_defconfig | 1 + drivers/Makefile | 6 +++--- drivers/firmware/Kconfig | 7 ++- drivers/sysreset/Kconfig | 1 + 6 files changed, 13 insertions(+), 4 deletions(-) diff --git a/configs/evb-rk3036_defconfig b/configs/evb-rk3036_defconfig index 5e6bb54551..0eb7384340 100644 --- a/configs/evb-rk3036_defconfig +++ b/configs/evb-rk3036_defconfig @@ -47,6 +47,7 @@ CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_SPEED=2000 CONFIG_PINCTRL=y # CONFIG_SPL_DM_SERIAL is not set +# CONFIG_SPL_SYSRESET is not set CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYSRESET=y CONFIG_USB=y diff --git a/configs/kylin-rk3036_defconfig b/configs/kylin-rk3036_defconfig index 921af0d476..a76ae9d326 100644 --- a/configs/kylin-rk3036_defconfig +++ b/configs/kylin-rk3036_defconfig @@ -49,6 +49,7 @@ CONFIG_SF_DEFAULT_SPEED=2000 CONFIG_PINCTRL=y CONFIG_DM_REGULATOR_FIXED=y # CONFIG_SPL_DM_SERIAL is not set +# CONFIG_SPL_SYSRESET is not set CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYSRESET=y CONFIG_USB=y diff --git a/configs/sandbox_spl_defconfig b/configs/sandbox_spl_defconfig index 27034cfaa9..5b7dae9be6 100644 --- a/configs/sandbox_spl_defconfig +++ b/configs/sandbox_spl_defconfig @@ -3,6 +3,7 @@ CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL_FIRMWARE=y CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_BOOTSTAGE_STASH_ADDR=0x0 diff --git a/drivers/Makefile b/drivers/Makefile index 603aa98590..41933605ce 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -4,7 +4,9 @@ obj-$(CONFIG_$(SPL_TPL_)CLK) += clk/ obj-$(CONFIG_$(SPL_TPL_)DM) += core/ obj-$(CONFIG_$(SPL_TPL_)DFU) += dfu/ obj-$(CONFIG_$(SPL_TPL_)GPIO_SUPPORT) += gpio/ -obj-$(CONFIG_$(SPL_TPL_)DRIVERS_MISC_SUPPORT) += misc/ sysreset/ firmware/ +obj-$(CONFIG_$(SPL_TPL_)DRIVERS_MISC_SUPPORT) += misc/ +obj-$(CONFIG_$(SPL_TPL_)SYSRESET) += sysreset/ +obj-$(CONFIG_$(SPL_TPL_)FIRMWARE) +=firmware/ obj-$(CONFIG_$(SPL_TPL_)I2C_SUPPORT) += i2c/ obj-$(CONFIG_$(SPL_TPL_)INPUT) += input/ obj-$(CONFIG_$(SPL_TPL_)LED) += led/ @@ -81,7 +83,6 @@ obj-y += cache/ obj-$(CONFIG_CPU) += cpu/ obj-y += crypto/ obj-$(CONFIG_FASTBOOT) += fastboot/ -obj-y += firmware/ obj-$(CONFIG_FPGA) += fpga/ obj-y += misc/ obj-$(CONFIG_MMC) += mmc/ @@ -96,7 +97,6 @@ obj-y += rtc/ obj-y += scsi/ obj-y += sound/ obj-y += spmi/ -obj-y += sysreset/ obj-y += video/ obj-y += watchdog/ obj-$(CONFIG_QE) += qe/ diff --git a/drivers/firmware/Kconfig b/drivers/firmware/Kconfig index 7d8f161b26..873bc8c796 100644 --- a/drivers/firmware/Kconfig +++ b/drivers/firmware/Kconfig @@ -1,9 +1,13 @@ config FIRMWARE bool "Enable Firmware driver support" +config SPL_FIRMWARE + bool "Enable Firmware driver support in SPL" + depends on FIRMWARE + config SPL_ARM_PSCI_FW bool - select FIRMWARE + select SPL_FIRMWARE config ARM_PSCI_FW bool @@ -13,6 +17,7 @@ config TI_SCI_PROTOCOL tristate "TI System Control Interface (TISCI) Message Protocol" depends on K3_SEC_PROXY select FIRMWARE + select SPL_FIRMWARE if SPL help TI System Control Interface (TISCI) Message Protocol is used to manage compute systems such as ARM, DSP etc with the system controller in diff --git a/drivers/sysreset/Kconfig b/drivers/sysreset/Kconfig index 30aed2c4c1..a69b74cee2 100644 ---
[U-Boot] pci_ep dm test failure
Hi Tom, Can you please merge this patch https://patchwork.ozlabs.org/patch/1132255/ which fixes the pcie_ep dm test that failed in travis ? you can later re-enable the test of course. Thanks and sorry for the mess.. Ramon. ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v2 3/6] net: macb: use bit access macro from header file
macb.h provides macros for reading/setting bitfields,
in macb registers and descriptors. use that instead
of redefining them in the source file.
Signed-off-by: Ramon Fried
Reviewed-by: Anup Patel
Tested-by: Anup Patel
Acked-by: Joe Hershberger
---
v2: nothing.
drivers/net/macb.c | 48 +++---
1 file changed, 15 insertions(+), 33 deletions(-)
diff --git a/drivers/net/macb.c b/drivers/net/macb.c
index 0fed43bbe2..a968a4bd06 100644
--- a/drivers/net/macb.c
+++ b/drivers/net/macb.c
@@ -77,27 +77,8 @@ struct macb_dma_desc {
#define MACB_RX_DMA_DESC_SIZE (DMA_DESC_BYTES(MACB_RX_RING_SIZE))
#define MACB_TX_DUMMY_DMA_DESC_SIZE(DMA_DESC_BYTES(1))
-#define RXADDR_USED0x0001
-#define RXADDR_WRAP0x0002
-
#define RXBUF_FRMLEN_MASK 0x0fff
-#define RXBUF_FRAME_START 0x4000
-#define RXBUF_FRAME_END0x8000
-#define RXBUF_TYPEID_MATCH 0x0040
-#define RXBUF_ADDR4_MATCH 0x0080
-#define RXBUF_ADDR3_MATCH 0x0100
-#define RXBUF_ADDR2_MATCH 0x0200
-#define RXBUF_ADDR1_MATCH 0x0400
-#define RXBUF_BROADCAST0x8000
-
#define TXBUF_FRMLEN_MASK 0x07ff
-#define TXBUF_FRAME_END0x8000
-#define TXBUF_NOCRC0x0001
-#define TXBUF_EXHAUSTED0x0800
-#define TXBUF_UNDERRUN 0x1000
-#define TXBUF_MAXRETRY 0x2000
-#define TXBUF_WRAP 0x4000
-#define TXBUF_USED 0x8000
struct macb_device {
void*regs;
@@ -316,9 +297,9 @@ static int _macb_send(struct macb_device *macb, const char
*name, void *packet,
paddr = dma_map_single(packet, length, DMA_TO_DEVICE);
ctrl = length & TXBUF_FRMLEN_MASK;
- ctrl |= TXBUF_FRAME_END;
+ ctrl |= MACB_BIT(TX_LAST);
if (tx_head == (MACB_TX_RING_SIZE - 1)) {
- ctrl |= TXBUF_WRAP;
+ ctrl |= MACB_BIT(TX_WRAP);
macb->tx_head = 0;
} else {
macb->tx_head++;
@@ -340,7 +321,7 @@ static int _macb_send(struct macb_device *macb, const char
*name, void *packet,
barrier();
macb_invalidate_ring_desc(macb, TX);
ctrl = macb->tx_ring[tx_head].ctrl;
- if (ctrl & TXBUF_USED)
+ if (ctrl & MACB_BIT(TX_USED))
break;
udelay(1);
}
@@ -348,9 +329,9 @@ static int _macb_send(struct macb_device *macb, const char
*name, void *packet,
dma_unmap_single(packet, length, paddr);
if (i <= MACB_TX_TIMEOUT) {
- if (ctrl & TXBUF_UNDERRUN)
+ if (ctrl & MACB_BIT(TX_UNDERRUN))
printf("%s: TX underrun\n", name);
- if (ctrl & TXBUF_EXHAUSTED)
+ if (ctrl & MACB_BIT(TX_BUF_EXHAUSTED))
printf("%s: TX buffers exhausted in mid frame\n", name);
} else {
printf("%s: TX timeout\n", name);
@@ -369,14 +350,14 @@ static void reclaim_rx_buffers(struct macb_device *macb,
macb_invalidate_ring_desc(macb, RX);
while (i > new_tail) {
- macb->rx_ring[i].addr &= ~RXADDR_USED;
+ macb->rx_ring[i].addr &= ~MACB_BIT(RX_USED);
i++;
if (i > MACB_RX_RING_SIZE)
i = 0;
}
while (i < new_tail) {
- macb->rx_ring[i].addr &= ~RXADDR_USED;
+ macb->rx_ring[i].addr &= ~MACB_BIT(RX_USED);
i++;
}
@@ -396,17 +377,17 @@ static int _macb_recv(struct macb_device *macb, uchar
**packetp)
for (;;) {
macb_invalidate_ring_desc(macb, RX);
- if (!(macb->rx_ring[next_rx_tail].addr & RXADDR_USED))
+ if (!(macb->rx_ring[next_rx_tail].addr & MACB_BIT(RX_USED)))
return -EAGAIN;
status = macb->rx_ring[next_rx_tail].ctrl;
- if (status & RXBUF_FRAME_START) {
+ if (status & MACB_BIT(RX_SOF)) {
if (next_rx_tail != macb->rx_tail)
reclaim_rx_buffers(macb, next_rx_tail);
macb->wrapped = false;
}
- if (status & RXBUF_FRAME_END) {
+ if (status & MACB_BIT(RX_EOF)) {
buffer = macb->rx_buffer + 128 * macb->rx_tail;
length = status & RXBUF_FRMLEN_MASK;
@@ -699,7 +680,7 @@ static int gmac_init_multi_queues(struct macb_device *macb)
if (queue_mask & (1 << i))
num_queues++;
- macb->dummy_desc->ctrl = TXBUF_USED;
+ macb->dummy_desc->ctrl = MACB_BIT(TX_USED);
macb->dummy_desc->addr = 0;
flush_dcache_range(macb->dummy_desc_dma, macb->dummy_desc_dma +
[U-Boot] [PATCH v2 6/6] net: macb: apply sane DMA configuration
DMA configuration was heavily dependent on the HW
defaults, add function to properly set the required
fields, including the new dma_burst_length.
Signed-off-by: Ramon Fried
Reviewed-by: Anup Patel
Tested-by: Anup Patel
Acked-by: Joe Hershberger
---
v2: nothing.
drivers/net/macb.c | 28
1 file changed, 28 insertions(+)
diff --git a/drivers/net/macb.c b/drivers/net/macb.c
index dc6aa6deda..035109dc43 100644
--- a/drivers/net/macb.c
+++ b/drivers/net/macb.c
@@ -47,6 +47,7 @@ DECLARE_GLOBAL_DATA_PTR;
#define MACB_RX_BUFFER_SIZE4096
#define MACB_RX_RING_SIZE (MACB_RX_BUFFER_SIZE / 128)
+#define RX_BUFFER_MULTIPLE 64
#define MACB_TX_RING_SIZE 16
#define MACB_TX_TIMEOUT1000
#define MACB_AUTONEG_TIMEOUT 500
@@ -697,6 +698,31 @@ static int gmac_init_multi_queues(struct macb_device *macb)
return 0;
}
+static void gmac_configure_dma(struct macb_device *macb)
+{
+ u32 buffer_size;
+ u32 dmacfg;
+
+ buffer_size = 128 / RX_BUFFER_MULTIPLE;
+ dmacfg = gem_readl(macb, DMACFG) & ~GEM_BF(RXBS, -1L);
+ dmacfg |= GEM_BF(RXBS, buffer_size);
+
+ if (macb->dma_burst_length)
+ dmacfg = GEM_BFINS(FBLDO, macb->dma_burst_length, dmacfg);
+
+ dmacfg |= GEM_BIT(TXPBMS) | GEM_BF(RXBMS, -1L);
+ dmacfg &= ~GEM_BIT(ENDIA_PKT);
+
+#ifdef CONFIG_SYS_LITTLE_ENDIAN
+ dmacfg &= ~GEM_BIT(ENDIA_DESC);
+#else
+ dmacfg |= GEM_BIT(ENDIA_DESC); /* CPU in big endian */
+#endif
+
+ dmacfg &= ~GEM_BIT(ADDR64);
+ gem_writel(macb, DMACFG, dmacfg);
+}
+
#ifdef CONFIG_DM_ETH
static int _macb_init(struct udevice *dev, const char *name)
#else
@@ -750,6 +776,8 @@ static int _macb_init(struct macb_device *macb, const char
*name)
macb_writel(macb, TBQP, macb->tx_ring_dma);
if (macb_is_gem(macb)) {
+ /* Initialize DMA properties */
+ gmac_configure_dma(macb);
/* Check the multi queue and initialize the queue for tx */
gmac_init_multi_queues(macb);
--
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[U-Boot] [PATCH v2 2/6] net: macb: add support for faster clk rates
add support for clock rates higher than 2.4Mhz Signed-off-by: Ramon Fried Reviewed-by: Anup Patel Tested-by: Anup Patel Acked-by: Joe Hershberger --- v2: nothing. drivers/net/macb.c | 6 +- drivers/net/macb.h | 2 ++ 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/net/macb.c b/drivers/net/macb.c index 0032d4e000..0fed43bbe2 100644 --- a/drivers/net/macb.c +++ b/drivers/net/macb.c @@ -903,8 +903,12 @@ static u32 gem_mdc_clk_div(int id, struct macb_device *macb) config = GEM_BF(CLK, GEM_CLK_DIV48); else if (macb_hz < 16000) config = GEM_BF(CLK, GEM_CLK_DIV64); - else + else if (macb_hz < 24000) config = GEM_BF(CLK, GEM_CLK_DIV96); + else if (macb_hz < 32000) + config = GEM_BF(CLK, GEM_CLK_DIV128); + else + config = GEM_BF(CLK, GEM_CLK_DIV224); return config; } diff --git a/drivers/net/macb.h b/drivers/net/macb.h index 8966c793a7..9b16383eba 100644 --- a/drivers/net/macb.h +++ b/drivers/net/macb.h @@ -613,6 +613,8 @@ #define GEM_CLK_DIV48 3 #define GEM_CLK_DIV64 4 #define GEM_CLK_DIV96 5 +#define GEM_CLK_DIV128 6 +#define GEM_CLK_DIV224 7 /* Constants for MAN register */ #define MACB_MAN_SOF 1 -- 2.22.0 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v2 5/6] net: macb: add dma_burst_length config
GEM support higher DMA burst writes/reads than the default (4).
add configuration structure with dma burst length so it could be
applied later to DMA configuration.
Signed-off-by: Ramon Fried
Reviewed-by: Anup Patel
Tested-by: Anup Patel
Acked-by: Joe Hershberger
---
v2: nothing.
drivers/net/macb.c | 22 +-
1 file changed, 21 insertions(+), 1 deletion(-)
diff --git a/drivers/net/macb.c b/drivers/net/macb.c
index cf76270ad8..dc6aa6deda 100644
--- a/drivers/net/macb.c
+++ b/drivers/net/macb.c
@@ -82,6 +82,7 @@ struct macb_dma_desc {
struct macb_device {
void*regs;
+ unsigned intdma_burst_length;
unsigned intrx_tail;
unsigned inttx_head;
@@ -118,6 +119,11 @@ struct macb_device {
phy_interface_t phy_interface;
#endif
};
+
+struct macb_config {
+ unsigned intdma_burst_length;
+};
+
#ifndef CONFIG_DM_ETH
#define to_macb(_nd) container_of(_nd, struct macb_device, netdev)
#endif
@@ -1135,8 +1141,13 @@ static int macb_enable_clk(struct udevice *dev)
}
#endif
+static const struct macb_config default_gem_config = {
+ .dma_burst_length = 16,
+};
+
static int macb_eth_probe(struct udevice *dev)
{
+ const struct macb_config *macb_config;
struct eth_pdata *pdata = dev_get_platdata(dev);
struct macb_device *macb = dev_get_priv(dev);
const char *phy_mode;
@@ -1153,6 +1164,11 @@ static int macb_eth_probe(struct udevice *dev)
macb->regs = (void *)pdata->iobase;
+ macb_config = (struct macb_config *)dev_get_driver_data(dev);
+ if (!macb_config)
+ macb_config = _gem_config;
+
+ macb->dma_burst_length = macb_config->dma_burst_length;
#ifdef CONFIG_CLK
ret = macb_enable_clk(dev);
if (ret)
@@ -1213,12 +1229,16 @@ static int macb_eth_ofdata_to_platdata(struct udevice
*dev)
return macb_late_eth_ofdata_to_platdata(dev);
}
+static const struct macb_config sama5d4_config = {
+ .dma_burst_length = 4,
+};
+
static const struct udevice_id macb_eth_ids[] = {
{ .compatible = "cdns,macb" },
{ .compatible = "cdns,at91sam9260-macb" },
{ .compatible = "atmel,sama5d2-gem" },
{ .compatible = "atmel,sama5d3-gem" },
- { .compatible = "atmel,sama5d4-gem" },
+ { .compatible = "atmel,sama5d4-gem", .data = (ulong)_config },
{ .compatible = "cdns,zynq-gem" },
{ }
};
--
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[U-Boot] [PATCH v2 4/6] net: macb: add support for SGMII phy interface
This patch adds support for the sgmii phy interface,
available only to DM users, dictated by current driver
design.
Signed-off-by: Ramon Fried
Reviewed-by: Anup Patel
Tested-by: Anup Patel
Acked-by: Joe Hershberger
---
v2: nothing.
drivers/net/macb.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/net/macb.c b/drivers/net/macb.c
index a968a4bd06..cf76270ad8 100644
--- a/drivers/net/macb.c
+++ b/drivers/net/macb.c
@@ -759,6 +759,13 @@ static int _macb_init(struct macb_device *macb, const char
*name)
gem_writel(macb, USRIO, GEM_BIT(RGMII));
else
gem_writel(macb, USRIO, 0);
+
+ if (macb->phy_interface == PHY_INTERFACE_MODE_SGMII) {
+ unsigned int ncfgr = macb_readl(macb, NCFGR);
+
+ ncfgr |= GEM_BIT(SGMIIEN) | GEM_BIT(PCSSEL);
+ macb_writel(macb, NCFGR, ncfgr);
+ }
#else
#if defined(CONFIG_RGMII) || defined(CONFIG_RMII)
gem_writel(macb, USRIO, GEM_BIT(RGMII));
--
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[U-Boot] [PATCH 4/6] net: macb: add support for SGMII phy interface
This patch adds support for the sgmii phy interface,
available only to DM users, dictated by current driver
design.
Signed-off-by: Ramon Fried
Reviewed-by: Anup Patel
Tested-by: Anup Patel
Acked-by: Joe Hershberger
---
v2: nothing.
drivers/net/macb.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/net/macb.c b/drivers/net/macb.c
index a968a4bd06..cf76270ad8 100644
--- a/drivers/net/macb.c
+++ b/drivers/net/macb.c
@@ -759,6 +759,13 @@ static int _macb_init(struct macb_device *macb, const char
*name)
gem_writel(macb, USRIO, GEM_BIT(RGMII));
else
gem_writel(macb, USRIO, 0);
+
+ if (macb->phy_interface == PHY_INTERFACE_MODE_SGMII) {
+ unsigned int ncfgr = macb_readl(macb, NCFGR);
+
+ ncfgr |= GEM_BIT(SGMIIEN) | GEM_BIT(PCSSEL);
+ macb_writel(macb, NCFGR, ncfgr);
+ }
#else
#if defined(CONFIG_RGMII) || defined(CONFIG_RMII)
gem_writel(macb, USRIO, GEM_BIT(RGMII));
--
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[U-Boot] [PATCH 5/6] net: macb: add dma_burst_length config
GEM support higher DMA burst writes/reads than the default (4).
add configuration structure with dma burst length so it could be
applied later to DMA configuration.
Signed-off-by: Ramon Fried
Reviewed-by: Anup Patel
Tested-by: Anup Patel
Acked-by: Joe Hershberger
---
v2: nothing.
drivers/net/macb.c | 22 +-
1 file changed, 21 insertions(+), 1 deletion(-)
diff --git a/drivers/net/macb.c b/drivers/net/macb.c
index cf76270ad8..dc6aa6deda 100644
--- a/drivers/net/macb.c
+++ b/drivers/net/macb.c
@@ -82,6 +82,7 @@ struct macb_dma_desc {
struct macb_device {
void*regs;
+ unsigned intdma_burst_length;
unsigned intrx_tail;
unsigned inttx_head;
@@ -118,6 +119,11 @@ struct macb_device {
phy_interface_t phy_interface;
#endif
};
+
+struct macb_config {
+ unsigned intdma_burst_length;
+};
+
#ifndef CONFIG_DM_ETH
#define to_macb(_nd) container_of(_nd, struct macb_device, netdev)
#endif
@@ -1135,8 +1141,13 @@ static int macb_enable_clk(struct udevice *dev)
}
#endif
+static const struct macb_config default_gem_config = {
+ .dma_burst_length = 16,
+};
+
static int macb_eth_probe(struct udevice *dev)
{
+ const struct macb_config *macb_config;
struct eth_pdata *pdata = dev_get_platdata(dev);
struct macb_device *macb = dev_get_priv(dev);
const char *phy_mode;
@@ -1153,6 +1164,11 @@ static int macb_eth_probe(struct udevice *dev)
macb->regs = (void *)pdata->iobase;
+ macb_config = (struct macb_config *)dev_get_driver_data(dev);
+ if (!macb_config)
+ macb_config = _gem_config;
+
+ macb->dma_burst_length = macb_config->dma_burst_length;
#ifdef CONFIG_CLK
ret = macb_enable_clk(dev);
if (ret)
@@ -1213,12 +1229,16 @@ static int macb_eth_ofdata_to_platdata(struct udevice
*dev)
return macb_late_eth_ofdata_to_platdata(dev);
}
+static const struct macb_config sama5d4_config = {
+ .dma_burst_length = 4,
+};
+
static const struct udevice_id macb_eth_ids[] = {
{ .compatible = "cdns,macb" },
{ .compatible = "cdns,at91sam9260-macb" },
{ .compatible = "atmel,sama5d2-gem" },
{ .compatible = "atmel,sama5d3-gem" },
- { .compatible = "atmel,sama5d4-gem" },
+ { .compatible = "atmel,sama5d4-gem", .data = (ulong)_config },
{ .compatible = "cdns,zynq-gem" },
{ }
};
--
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[U-Boot] [PATCH 3/6] net: macb: use bit access macro from header file
macb.h provides macros for reading/setting bitfields,
in macb registers and descriptors. use that instead
of redefining them in the source file.
Signed-off-by: Ramon Fried
Reviewed-by: Anup Patel
Tested-by: Anup Patel
Acked-by: Joe Hershberger
---
v2: nothing.
drivers/net/macb.c | 48 +++---
1 file changed, 15 insertions(+), 33 deletions(-)
diff --git a/drivers/net/macb.c b/drivers/net/macb.c
index 0fed43bbe2..a968a4bd06 100644
--- a/drivers/net/macb.c
+++ b/drivers/net/macb.c
@@ -77,27 +77,8 @@ struct macb_dma_desc {
#define MACB_RX_DMA_DESC_SIZE (DMA_DESC_BYTES(MACB_RX_RING_SIZE))
#define MACB_TX_DUMMY_DMA_DESC_SIZE(DMA_DESC_BYTES(1))
-#define RXADDR_USED0x0001
-#define RXADDR_WRAP0x0002
-
#define RXBUF_FRMLEN_MASK 0x0fff
-#define RXBUF_FRAME_START 0x4000
-#define RXBUF_FRAME_END0x8000
-#define RXBUF_TYPEID_MATCH 0x0040
-#define RXBUF_ADDR4_MATCH 0x0080
-#define RXBUF_ADDR3_MATCH 0x0100
-#define RXBUF_ADDR2_MATCH 0x0200
-#define RXBUF_ADDR1_MATCH 0x0400
-#define RXBUF_BROADCAST0x8000
-
#define TXBUF_FRMLEN_MASK 0x07ff
-#define TXBUF_FRAME_END0x8000
-#define TXBUF_NOCRC0x0001
-#define TXBUF_EXHAUSTED0x0800
-#define TXBUF_UNDERRUN 0x1000
-#define TXBUF_MAXRETRY 0x2000
-#define TXBUF_WRAP 0x4000
-#define TXBUF_USED 0x8000
struct macb_device {
void*regs;
@@ -316,9 +297,9 @@ static int _macb_send(struct macb_device *macb, const char
*name, void *packet,
paddr = dma_map_single(packet, length, DMA_TO_DEVICE);
ctrl = length & TXBUF_FRMLEN_MASK;
- ctrl |= TXBUF_FRAME_END;
+ ctrl |= MACB_BIT(TX_LAST);
if (tx_head == (MACB_TX_RING_SIZE - 1)) {
- ctrl |= TXBUF_WRAP;
+ ctrl |= MACB_BIT(TX_WRAP);
macb->tx_head = 0;
} else {
macb->tx_head++;
@@ -340,7 +321,7 @@ static int _macb_send(struct macb_device *macb, const char
*name, void *packet,
barrier();
macb_invalidate_ring_desc(macb, TX);
ctrl = macb->tx_ring[tx_head].ctrl;
- if (ctrl & TXBUF_USED)
+ if (ctrl & MACB_BIT(TX_USED))
break;
udelay(1);
}
@@ -348,9 +329,9 @@ static int _macb_send(struct macb_device *macb, const char
*name, void *packet,
dma_unmap_single(packet, length, paddr);
if (i <= MACB_TX_TIMEOUT) {
- if (ctrl & TXBUF_UNDERRUN)
+ if (ctrl & MACB_BIT(TX_UNDERRUN))
printf("%s: TX underrun\n", name);
- if (ctrl & TXBUF_EXHAUSTED)
+ if (ctrl & MACB_BIT(TX_BUF_EXHAUSTED))
printf("%s: TX buffers exhausted in mid frame\n", name);
} else {
printf("%s: TX timeout\n", name);
@@ -369,14 +350,14 @@ static void reclaim_rx_buffers(struct macb_device *macb,
macb_invalidate_ring_desc(macb, RX);
while (i > new_tail) {
- macb->rx_ring[i].addr &= ~RXADDR_USED;
+ macb->rx_ring[i].addr &= ~MACB_BIT(RX_USED);
i++;
if (i > MACB_RX_RING_SIZE)
i = 0;
}
while (i < new_tail) {
- macb->rx_ring[i].addr &= ~RXADDR_USED;
+ macb->rx_ring[i].addr &= ~MACB_BIT(RX_USED);
i++;
}
@@ -396,17 +377,17 @@ static int _macb_recv(struct macb_device *macb, uchar
**packetp)
for (;;) {
macb_invalidate_ring_desc(macb, RX);
- if (!(macb->rx_ring[next_rx_tail].addr & RXADDR_USED))
+ if (!(macb->rx_ring[next_rx_tail].addr & MACB_BIT(RX_USED)))
return -EAGAIN;
status = macb->rx_ring[next_rx_tail].ctrl;
- if (status & RXBUF_FRAME_START) {
+ if (status & MACB_BIT(RX_SOF)) {
if (next_rx_tail != macb->rx_tail)
reclaim_rx_buffers(macb, next_rx_tail);
macb->wrapped = false;
}
- if (status & RXBUF_FRAME_END) {
+ if (status & MACB_BIT(RX_EOF)) {
buffer = macb->rx_buffer + 128 * macb->rx_tail;
length = status & RXBUF_FRMLEN_MASK;
@@ -699,7 +680,7 @@ static int gmac_init_multi_queues(struct macb_device *macb)
if (queue_mask & (1 << i))
num_queues++;
- macb->dummy_desc->ctrl = TXBUF_USED;
+ macb->dummy_desc->ctrl = MACB_BIT(TX_USED);
macb->dummy_desc->addr = 0;
flush_dcache_range(macb->dummy_desc_dma, macb->dummy_desc_dma +
[U-Boot] [PATCH 6/6] net: macb: apply sane DMA configuration
DMA configuration was heavily dependent on the HW
defaults, add function to properly set the required
fields, including the new dma_burst_length.
Signed-off-by: Ramon Fried
Reviewed-by: Anup Patel
Tested-by: Anup Patel
Acked-by: Joe Hershberger
---
v2: nothing.
drivers/net/macb.c | 28
1 file changed, 28 insertions(+)
diff --git a/drivers/net/macb.c b/drivers/net/macb.c
index dc6aa6deda..035109dc43 100644
--- a/drivers/net/macb.c
+++ b/drivers/net/macb.c
@@ -47,6 +47,7 @@ DECLARE_GLOBAL_DATA_PTR;
#define MACB_RX_BUFFER_SIZE4096
#define MACB_RX_RING_SIZE (MACB_RX_BUFFER_SIZE / 128)
+#define RX_BUFFER_MULTIPLE 64
#define MACB_TX_RING_SIZE 16
#define MACB_TX_TIMEOUT1000
#define MACB_AUTONEG_TIMEOUT 500
@@ -697,6 +698,31 @@ static int gmac_init_multi_queues(struct macb_device *macb)
return 0;
}
+static void gmac_configure_dma(struct macb_device *macb)
+{
+ u32 buffer_size;
+ u32 dmacfg;
+
+ buffer_size = 128 / RX_BUFFER_MULTIPLE;
+ dmacfg = gem_readl(macb, DMACFG) & ~GEM_BF(RXBS, -1L);
+ dmacfg |= GEM_BF(RXBS, buffer_size);
+
+ if (macb->dma_burst_length)
+ dmacfg = GEM_BFINS(FBLDO, macb->dma_burst_length, dmacfg);
+
+ dmacfg |= GEM_BIT(TXPBMS) | GEM_BF(RXBMS, -1L);
+ dmacfg &= ~GEM_BIT(ENDIA_PKT);
+
+#ifdef CONFIG_SYS_LITTLE_ENDIAN
+ dmacfg &= ~GEM_BIT(ENDIA_DESC);
+#else
+ dmacfg |= GEM_BIT(ENDIA_DESC); /* CPU in big endian */
+#endif
+
+ dmacfg &= ~GEM_BIT(ADDR64);
+ gem_writel(macb, DMACFG, dmacfg);
+}
+
#ifdef CONFIG_DM_ETH
static int _macb_init(struct udevice *dev, const char *name)
#else
@@ -750,6 +776,8 @@ static int _macb_init(struct macb_device *macb, const char
*name)
macb_writel(macb, TBQP, macb->tx_ring_dma);
if (macb_is_gem(macb)) {
+ /* Initialize DMA properties */
+ gmac_configure_dma(macb);
/* Check the multi queue and initialize the queue for tx */
gmac_init_multi_queues(macb);
--
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[U-Boot] [PATCH 2/6] net: macb: add support for faster clk rates
add support for clock rates higher than 2.4Mhz Signed-off-by: Ramon Fried Reviewed-by: Anup Patel Tested-by: Anup Patel Acked-by: Joe Hershberger --- v2: nothing. drivers/net/macb.c | 6 +- drivers/net/macb.h | 2 ++ 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/net/macb.c b/drivers/net/macb.c index 0032d4e000..0fed43bbe2 100644 --- a/drivers/net/macb.c +++ b/drivers/net/macb.c @@ -903,8 +903,12 @@ static u32 gem_mdc_clk_div(int id, struct macb_device *macb) config = GEM_BF(CLK, GEM_CLK_DIV48); else if (macb_hz < 16000) config = GEM_BF(CLK, GEM_CLK_DIV64); - else + else if (macb_hz < 24000) config = GEM_BF(CLK, GEM_CLK_DIV96); + else if (macb_hz < 32000) + config = GEM_BF(CLK, GEM_CLK_DIV128); + else + config = GEM_BF(CLK, GEM_CLK_DIV224); return config; } diff --git a/drivers/net/macb.h b/drivers/net/macb.h index 8966c793a7..9b16383eba 100644 --- a/drivers/net/macb.h +++ b/drivers/net/macb.h @@ -613,6 +613,8 @@ #define GEM_CLK_DIV48 3 #define GEM_CLK_DIV64 4 #define GEM_CLK_DIV96 5 +#define GEM_CLK_DIV128 6 +#define GEM_CLK_DIV224 7 /* Constants for MAN register */ #define MACB_MAN_SOF 1 -- 2.22.0 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v2 1/6] net: macb: sync header definitions as taken from Linux
Few registers and bits were added by Cadence and
they were not updated in the headers.
Take the latest definitions as defined in Linux
header (5.1) that also includes some comments
about existing registers.
One register was improperly named (UR), fix that.
Signed-off-by: Ramon Fried
Reviewed-by: Anup Patel
Tested-by: Anup Patel
Acked-by: Joe Hershberger
---
V2: Fix missed UR registers.
drivers/net/macb.c | 8 +-
drivers/net/macb.h | 868 ++---
2 files changed, 662 insertions(+), 214 deletions(-)
diff --git a/drivers/net/macb.c b/drivers/net/macb.c
index a7eddd647d..0032d4e000 100644
--- a/drivers/net/macb.c
+++ b/drivers/net/macb.c
@@ -774,14 +774,14 @@ static int _macb_init(struct macb_device *macb, const
char *name)
#ifdef CONFIG_DM_ETH
if ((macb->phy_interface == PHY_INTERFACE_MODE_RMII) ||
(macb->phy_interface == PHY_INTERFACE_MODE_RGMII))
- gem_writel(macb, UR, GEM_BIT(RGMII));
+ gem_writel(macb, USRIO, GEM_BIT(RGMII));
else
- gem_writel(macb, UR, 0);
+ gem_writel(macb, USRIO, 0);
#else
#if defined(CONFIG_RGMII) || defined(CONFIG_RMII)
- gem_writel(macb, UR, GEM_BIT(RGMII));
+ gem_writel(macb, USRIO, GEM_BIT(RGMII));
#else
- gem_writel(macb, UR, 0);
+ gem_writel(macb, USRIO, 0);
#endif
#endif
} else {
diff --git a/drivers/net/macb.h b/drivers/net/macb.h
index 3cc27f8560..8966c793a7 100644
--- a/drivers/net/macb.h
+++ b/drivers/net/macb.h
@@ -5,221 +5,410 @@
#ifndef __DRIVERS_MACB_H__
#define __DRIVERS_MACB_H__
+#define MACB_GREGS_NBR 16
+#define MACB_GREGS_VERSION 2
+#define MACB_MAX_QUEUES 8
+
/* MACB register offsets */
-#define MACB_NCR 0x
-#define MACB_NCFGR 0x0004
-#define MACB_NSR 0x0008
-#define GEM_UR 0x000c
-#define MACB_DMACFG0x0010
-#define MACB_TSR 0x0014
-#define MACB_RBQP 0x0018
-#define MACB_TBQP 0x001c
-#define MACB_RSR 0x0020
-#define MACB_ISR 0x0024
-#define MACB_IER 0x0028
-#define MACB_IDR 0x002c
-#define MACB_IMR 0x0030
-#define MACB_MAN 0x0034
-#define MACB_PTR 0x0038
-#define MACB_PFR 0x003c
-#define MACB_FTO 0x0040
-#define MACB_SCF 0x0044
-#define MACB_MCF 0x0048
-#define MACB_FRO 0x004c
-#define MACB_FCSE 0x0050
-#define MACB_ALE 0x0054
-#define MACB_DTF 0x0058
-#define MACB_LCOL 0x005c
-#define MACB_EXCOL 0x0060
-#define MACB_TUND 0x0064
-#define MACB_CSE 0x0068
-#define MACB_RRE 0x006c
-#define MACB_ROVR 0x0070
-#define MACB_RSE 0x0074
-#define MACB_ELE 0x0078
-#define MACB_RJA 0x007c
-#define MACB_USF 0x0080
-#define MACB_STE 0x0084
-#define MACB_RLE 0x0088
-#define MACB_TPF 0x008c
-#define MACB_HRB 0x0090
-#define MACB_HRT 0x0094
-#define MACB_SA1B 0x0098
-#define MACB_SA1T 0x009c
-#define MACB_SA2B 0x00a0
-#define MACB_SA2T 0x00a4
-#define MACB_SA3B 0x00a8
-#define MACB_SA3T 0x00ac
-#define MACB_SA4B 0x00b0
-#define MACB_SA4T 0x00b4
-#define MACB_TID 0x00b8
-#define MACB_TPQ 0x00bc
-#define MACB_USRIO 0x00c0
-#define MACB_WOL 0x00c4
-#define MACB_MID 0x00fc
-
-/* GEM specific register offsets */
-#define GEM_DCFG1 0x0280
-#define GEM_DCFG6 0x0294
-
-#define MACB_MAX_QUEUES8
-
-/* GEM specific multi queues register offset */
-/* hw_q can be 0~7 */
-#define GEM_TBQP(hw_q) (0x0440 + ((hw_q) << 2))
+#define MACB_NCR
Re: [U-Boot] [PATCH 00/16] Raspberry Pi 32/64 support
Hi, On 16 July 2019 15:17:46 BST, Matthias Brugger wrote: > > >On 16/07/2019 15:37, and...@gherzan.ro wrote: >> From: Andrei Gherzan >> >> This PR consolidates the work we've done to support the new Raspberry >Pi > >I don't understand why you posted these while you asked me if I'll >submit them. >That's not a good way to collaborate on upstream. As I have mentioned privately, I've done that due to the fact that I haven't gotten any feedback from you. Nevertheless, I will sync up with you for the next iteration for this PR which will include the changes requested. -- Andrei Gherzan gpg: rsa4096/D4D94F67AD0E9640 | t: @agherzan ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 1/6] net: macb: sync header definitions as taken from Linux
On Tue, Jul 16, 2019 at 9:42 PM Joe Hershberger wrote: > > On Tue, Jul 16, 2019 at 12:03 AM Ramon Fried wrote: > > > > On Mon, Jul 15, 2019 at 11:48 PM Joe Hershberger > > wrote: > > > > > > On Mon, Jul 15, 2019 at 3:26 PM Ramon Fried wrote: > > > > > > > > On Mon, Jul 15, 2019 at 11:19 PM Ramon Fried > > > > wrote: > > > > > > > > > > On Mon, Jul 15, 2019 at 9:31 PM Joe Hershberger > > > > > wrote: > > > > > > > > > > > > On Tue, Jun 11, 2019 at 10:51 AM Ramon Fried > > > > > > wrote: > > > > > > > > > > > > > > Few registers and bits were added by Cadence and > > > > > > > they were not updated in the headers. > > > > > > > Take the latest definitions as defined in Linux > > > > > > > header (5.1) that also includes some comments > > > > > > > about existing registers. > > > > > > > > > > > > > > One register was improperly named (UR), fix that. > > > > > > > > > > > > This is breaking the build. "UR" is still referred to in > > > > > > drivers/net/macb.c line 805. > > > > > > > > > > > > Did you build test this? > > > > > Well of course, but apparently I screwed this one in rebasing, prior > > > > > to submit. > > > > > Didn't run buildman afterwards. sorry. > > > > > Will issue a revised patchset. > > > > > Sorry. > > > > > Ramon. > > > > Actually, now that I look at this. it looks fine. the patch replaces > > > > the line you mentioned: > > > > https://patchwork.ozlabs.org/patch/1114041/ > > > > Can take a look ? > > > > > > It addresses some of them, but not the ones a few lines below. > > Just cherry-picked to a brand new master branch. there are no UR left > > on the file > > and it compiles correctly. > > Did you apply something else beforehand ? > > One of them is even in the context of this patch... > > - gem_writel(macb, UR, 0); > + gem_writel(macb, USRIO, 0); > #else > #if defined(CONFIG_RGMII) || defined(CONFIG_RMII) > gem_writel(macb, UR, GEM_BIT(RGMII)); > > This right here, and another > a few lines later. Face palm I tested with SGMII, that's why it worked on my setup. I'll fix it shortly, sorry for the trouble :) Thanks, Ramon. ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 1/6] net: macb: sync header definitions as taken from Linux
On Tue, Jul 16, 2019 at 12:03 AM Ramon Fried wrote: > > On Mon, Jul 15, 2019 at 11:48 PM Joe Hershberger > wrote: > > > > On Mon, Jul 15, 2019 at 3:26 PM Ramon Fried wrote: > > > > > > On Mon, Jul 15, 2019 at 11:19 PM Ramon Fried wrote: > > > > > > > > On Mon, Jul 15, 2019 at 9:31 PM Joe Hershberger > > > > wrote: > > > > > > > > > > On Tue, Jun 11, 2019 at 10:51 AM Ramon Fried > > > > > wrote: > > > > > > > > > > > > Few registers and bits were added by Cadence and > > > > > > they were not updated in the headers. > > > > > > Take the latest definitions as defined in Linux > > > > > > header (5.1) that also includes some comments > > > > > > about existing registers. > > > > > > > > > > > > One register was improperly named (UR), fix that. > > > > > > > > > > This is breaking the build. "UR" is still referred to in > > > > > drivers/net/macb.c line 805. > > > > > > > > > > Did you build test this? > > > > Well of course, but apparently I screwed this one in rebasing, prior to > > > > submit. > > > > Didn't run buildman afterwards. sorry. > > > > Will issue a revised patchset. > > > > Sorry. > > > > Ramon. > > > Actually, now that I look at this. it looks fine. the patch replaces > > > the line you mentioned: > > > https://patchwork.ozlabs.org/patch/1114041/ > > > Can take a look ? > > > > It addresses some of them, but not the ones a few lines below. > Just cherry-picked to a brand new master branch. there are no UR left > on the file > and it compiles correctly. > Did you apply something else beforehand ? One of them is even in the context of this patch... - gem_writel(macb, UR, 0); + gem_writel(macb, USRIO, 0); #else #if defined(CONFIG_RGMII) || defined(CONFIG_RMII) gem_writel(macb, UR, GEM_BIT(RGMII)); This right here, and another a few lines later. > > > > > > > > > > > > > > > > > > > Signed-off-by: Ramon Fried > > > ___ > > > U-Boot mailing list > > > U-Boot@lists.denx.de > > > https://lists.denx.de/listinfo/u-boot > ___ > U-Boot mailing list > U-Boot@lists.denx.de > https://lists.denx.de/listinfo/u-boot ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [RFC PATCH 0/9] Initial layout for Sphinx HTML docs
On 7/16/19 6:42 PM, Bin Meng wrote:
> At present there is Sphinx doc build system in U-Boot, however the
> contents are very limited, that only a few API descriptions for EFI,
> are included.
>
> This series proposes an initial Sphinx doc layout for future extension,
> by converting some of the plain text documentation to reStructuredText
> format and add it to Sphinx TOC tree.
>
> @Wolfgang, is it possible to host the Sphinx HTML docs on denx.de?
>
> This series is available at u-boot-x86/doc for testing.
Thanks a lot for this patch series. For proof-reading I have uploaded
the generated pages to https://www.xypron.de/u-boot/index.html
The necessary theme for HTML generation is available here:
https://github.com/readthedocs/sphinx_rtd_theme
I applied this patch series:
scripts/kernel-doc: update script from Linux 5.2
https://lists.denx.de/pipermail/u-boot/2019-July/376371.html
Best regards
Heinrich
>
>
> Bin Meng (9):
> doc: Move existing rst files into api sub-directory
> doc: Add top-level description about U-Boot documentation
> doc: Add driver-model to Sphinx TOC tree
> doc: driver-model: Convert README.txt to reST
> doc: driver-model: Convert MIGRATION.txt to reST
> doc: Add architecture specific info to Sphinx TOC tree
> doc: arch: Convert README.mips to reST
> doc: Add board to Sphinx TOC tree
> doc: board: Add Intel Crown Bay board doc
>
> doc/README.x86| 37 --
> doc/{ => api}/efi.rst | 3 +
> doc/api/index.rst | 10 +
> doc/{ => api}/linker_lists.rst| 3 +
> doc/{ => api}/serial.rst | 3 +
> doc/arch/index.rst| 8 +
> doc/{README.mips => arch/mips.rst}| 14 +-
> doc/board/index.rst | 8 +
> doc/board/intel/crownbay.rst | 49 ++
> doc/board/intel/index.rst | 4 +
> doc/driver-model/{README.txt => design.rst} | 538
> --
> doc/driver-model/index.rst| 9 +
> doc/driver-model/{MIGRATION.txt => migration.rst} | 42 +-
> doc/index.rst | 69 ++-
> 14 files changed, 469 insertions(+), 328 deletions(-)
> rename doc/{ => api}/efi.rst (92%)
> create mode 100644 doc/api/index.rst
> rename doc/{ => api}/linker_lists.rst (99%)
> rename doc/{ => api}/serial.rst (80%)
> create mode 100644 doc/arch/index.rst
> rename doc/{README.mips => arch/mips.rst} (87%)
> create mode 100644 doc/board/index.rst
> create mode 100644 doc/board/intel/crownbay.rst
> create mode 100644 doc/board/intel/index.rst
> rename doc/driver-model/{README.txt => design.rst} (68%)
> create mode 100644 doc/driver-model/index.rst
> rename doc/driver-model/{MIGRATION.txt => migration.rst} (85%)
>
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Re: [U-Boot] [RFC PATCH 1/9] doc: Move existing rst files into api sub-directory
On 7/16/19 6:42 PM, Bin Meng wrote: > Currently the Sphinx doc only contains API descriptions of several > U-Boot subsystems. For future extension, group these existing docs > into an API sub-directory. > > Signed-off-by: Bin Meng Reviewed-by: Heinrich Schuchardt ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [RFC PATCH 9/9] doc: board: Add Intel Crown Bay board doc
On 7/16/19 6:42 PM, Bin Meng wrote: > This extracts Intel Crown Bay board specific information from > README.x86, converts plain text documentation to reST format and > adds it to Sphinx TOC tree. No essential content change. > > Signed-off-by: Bin Meng > > --- > > doc/README.x86 | 37 - > doc/board/index.rst | 2 ++ > doc/board/intel/crownbay.rst | 49 > > doc/board/intel/index.rst| 4 > 4 files changed, 55 insertions(+), 37 deletions(-) > create mode 100644 doc/board/intel/crownbay.rst > create mode 100644 doc/board/intel/index.rst > > diff --git a/doc/README.x86 b/doc/README.x86 > index 8e0a3f3..8077ff3 100644 > --- a/doc/README.x86 > +++ b/doc/README.x86 > @@ -203,43 +203,6 @@ Flash map for samus / broadwell: > > --- > > -Intel Crown Bay specific instructions for bare mode: > - > -U-Boot support of Intel Crown Bay board [4] relies on a binary blob called > -Firmware Support Package [5] to perform all the necessary initialization > steps > -as documented in the BIOS Writer Guide, including initialization of the CPU, > -memory controller, chipset and certain bus interfaces. > - > -Download the Intel FSP for Atom E6xx series and Platform Controller Hub > EG20T, > -install it on your host and locate the FSP binary blob. Note this platform > -also requires a Chipset Micro Code (CMC) state machine binary to be present > in > -the SPI flash where u-boot.rom resides, and this CMC binary blob can be found > -in this FSP package too. > - > -* ./FSP/QUEENSBAY_FSP_GOLD_001_20-DECEMBER-2013.fd > -* ./Microcode/C0_22211.BIN > - > -Rename the first one to fsp.bin and second one to cmc.bin and put them in the > -board directory. > - > -Note the FSP release version 001 has a bug which could cause random endless > -loop during the FspInit call. This bug was published by Intel although Intel > -did not describe any details. We need manually apply the patch to the FSP > -binary using any hex editor (eg: bvi). Go to the offset 0x1fcd8 of the FSP > -binary, change the following five bytes values from orginally E8 42 FF FF FF > -to B8 00 80 0B 00. > - > -As for the video ROM, you need manually extract it from the Intel provided > -BIOS for Crown Bay here [6], using the AMI MMTool [7]. Check PCI option ROM > -ID 8086:4108, extract and save it as vga.bin in the board directory. > - > -Now you can build U-Boot and obtain u-boot.rom > - > -$ make crownbay_defconfig > -$ make all > - > > - > Intel Cougar Canyon 2 specific instructions for bare mode: > > This uses Intel FSP for 3rd generation Intel Core and Intel Celeron > processors > diff --git a/doc/board/index.rst b/doc/board/index.rst > index 4a65def..34e59de 100644 > --- a/doc/board/index.rst > +++ b/doc/board/index.rst > @@ -4,3 +4,5 @@ Board-specific doc > > .. toctree:: > :maxdepth: 2 > + > + intel/index > diff --git a/doc/board/intel/crownbay.rst b/doc/board/intel/crownbay.rst > new file mode 100644 > index 000..d77cece > --- /dev/null > +++ b/doc/board/intel/crownbay.rst > @@ -0,0 +1,49 @@ > +.. SPDX-License-Identifier: GPL-2.0+ > + > +:author: Bin Meng > + > +.. toctree:: > + :maxdepth: 2 > + > +Intel CrownBay CRB > +== > + > +U-Boot support of Intel Crown Bay board `[1]`_ relies on a binary blob called > +Firmware Support Package `[2]`_ to perform all the necessary initialization > +steps as documented in the BIOS Writer Guide, including initialization of the > +CPU, memory controller, chipset and certain bus interfaces. > + > +Download the Intel FSP for Atom E6xx series and Platform Controller Hub > EG20T, > +install it on your host and locate the FSP binary blob. Note this platform > +also requires a Chipset Micro Code (CMC) state machine binary to be present > in > +the SPI flash where u-boot.rom resides, and this CMC binary blob can be found > +in this FSP package too. > + > +* ./FSP/QUEENSBAY_FSP_GOLD_001_20-DECEMBER-2013.fd > +* ./Microcode/C0_22211.BIN > + > +Rename the first one to fsp.bin and second one to cmc.bin and put them in the > +board directory. > + > +Note the FSP release version 001 has a bug which could cause random endless > +loop during the FspInit call. This bug was published by Intel although Intel > +did not describe any details. We need manually apply the patch to the FSP > +binary using any hex editor (eg: bvi). Go to the offset 0x1fcd8 of the FSP > +binary, change the following five bytes values from orginally E8 42 FF FF FF > +to B8 00 80 0B 00. > + > +As for the video ROM, you need manually extract it from the Intel provided > +BIOS for Crown Bay here `[3]`_, using the AMI MMTool `[4]`_. Check PCI option > +ROM ID 8086:4108, extract and save it as vga.bin in the board directory. > + > +Now you can build U-Boot and obtain u-boot.rom > + > +.. code-block:: shell > + > + $ make crownbay_defconfig > + $ make all > + The following lines do not show up in the generated HTML.
Re: [U-Boot] [RFC PATCH 8/9] doc: Add board to Sphinx TOC tree
On 7/16/19 6:42 PM, Bin Meng wrote: > Add index.rst for board. More docs will be added later. > > Signed-off-by: Bin Meng Reviewed-by: Heinrich Schuchardt ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [RFC PATCH 7/9] doc: arch: Convert README.mips to reST
On 7/16/19 6:42 PM, Bin Meng wrote: > Convert plain text documentation to reStructuredText format and add > it to Sphinx TOC tree. No essential content change. > > Signed-off-by: Bin Meng Reviewed-by: Heinrich Schuchardt ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [RFC PATCH 6/9] doc: Add architecture specific info to Sphinx TOC tree
On 7/16/19 6:42 PM, Bin Meng wrote: > Add index.rst for architecture specific info. More docs will be > added later. > > Signed-off-by: Bin Meng Reviewed-by: Heinrich Schuchardt ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [RFC PATCH 5/9] doc: driver-model: Convert MIGRATION.txt to reST
On 7/16/19 6:42 PM, Bin Meng wrote: > Convert plain text documentation to reStructuredText format and add > it to Sphinx TOC tree. No essential content change. > > Signed-off-by: Bin Meng The conversion to RST is correct but we should rethink the values and effect of the deadlines. Reviewed-by: Heinrich Schuchardt ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [RFC PATCH 4/9] doc: driver-model: Convert README.txt to reST
On 7/16/19 6:42 PM, Bin Meng wrote: > Convert plain text documentation to reStructuredText format and add > it to Sphinx TOC tree. No essential content change. > > Signed-off-by: Bin Meng > --- I think these could be converted to level 3 sub-headings 1. Bind stage 2. Activation/probe 3. Running stage 4. Removal stage 5. Unbind stage And then convert a) - h) to an unnumbered list. But that can also be done in a later patch. Otherwise Reviewed-by: Heinrich Schuchardt ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [RFC PATCH 3/9] doc: Add driver-model to Sphinx TOC tree
On 7/16/19 6:42 PM, Bin Meng wrote: > Add index.rst for driver model. More docs will be added later. > > Signed-off-by: Bin Meng Reviewed-by: Heinrich Schuchardt ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [RFC PATCH 2/9] doc: Add top-level description about U-Boot documentation
On 7/16/19 6:42 PM, Bin Meng wrote: > This updates the index.rst to add top-level description about > U-Boot documentation. Words are taken from Linux kernel docs > and modified for U-Boot. > > Signed-off-by: Bin Meng Reviewe-by: Heinrich Schuchardt ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v4 1/1] efi_loader: Change return type of efi_add_memory_map()
On 7/15/19 1:00 PM, Bryan O'Donoghue wrote:
> We currently have some inconsistent use of efi_add_memory_map()
> throughout the code. In particular the return value of efi_add_memory_map()
> is not interpreted the same way by various users in the codebase.
>
> This patch does the following:
>
> - Changes efi_add_memory_map() to return efi_status_t.
> - Adds a method description to efi_add_memory_map().
> - Changes efi_add_memory_map() to return EFI_SUCCESS
> - Returns non-zero for error in efi_add_memory_map()
> - Updates efi_allocate_pages() to new efi_add_memory_map()
> - Updates efi_free_pages() to new efi_add_memory_map()
> - Updates efi_carve_out_dt_rsv() to new efi_add_memory_map()
> - Updates efi_add_runtime_mmio() to new efi_add_memory_map()
>
> Fixes: 5d00995c361c ("efi_loader: Implement memory allocation and map")
> Fixes: 74c16acce30b ("efi_loader: Don't allocate from memory holes")
> Suggested-by: Heinrich Schuchardt
> Reviewed-by: Heinrich Schuchardt
> Cc: Alexander Graf
> Signed-off-by: Bryan O'Donoghue
Applied to efi-2019-10.
https://gitlab.denx.de/u-boot/custodians/u-boot-efi/tree/efi-2019-10
Best regards
Heinrich
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[U-Boot] [RFC PATCH 2/9] doc: Add top-level description about U-Boot documentation
This updates the index.rst to add top-level description about U-Boot documentation. Words are taken from Linux kernel docs and modified for U-Boot. Signed-off-by: Bin Meng --- doc/index.rst | 22 +++--- 1 file changed, 19 insertions(+), 3 deletions(-) diff --git a/doc/index.rst b/doc/index.rst index 1946d09..cfcf1dd 100644 --- a/doc/index.rst +++ b/doc/index.rst @@ -1,8 +1,19 @@ .. SPDX-License-Identifier: GPL-2.0+ -### -U-Boot Developer Manual -### +.. _u-boot_doc: + +The U-Boot documentation + + +This is the top level of the U-Boot's documentation tree. U-Boot +documentation, like the U-Boot itself, is very much a work in progress; +that is especially true as we work to integrate our many scattered +documents into a coherent whole. Please note that improvements to the +documentation are welcome; join the U-Boot list at http://lists.denx.de +if you want to help out. + +.. toctree:: + :maxdepth: 2 U-Boot API documentation @@ -17,3 +28,8 @@ needed). :maxdepth: 2 api/index + +Indices and tables +== + +* :ref:`genindex` -- 2.7.4 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [RFC PATCH 9/9] doc: board: Add Intel Crown Bay board doc
This extracts Intel Crown Bay board specific information from README.x86, converts plain text documentation to reST format and adds it to Sphinx TOC tree. No essential content change. Signed-off-by: Bin Meng --- doc/README.x86 | 37 - doc/board/index.rst | 2 ++ doc/board/intel/crownbay.rst | 49 doc/board/intel/index.rst| 4 4 files changed, 55 insertions(+), 37 deletions(-) create mode 100644 doc/board/intel/crownbay.rst create mode 100644 doc/board/intel/index.rst diff --git a/doc/README.x86 b/doc/README.x86 index 8e0a3f3..8077ff3 100644 --- a/doc/README.x86 +++ b/doc/README.x86 @@ -203,43 +203,6 @@ Flash map for samus / broadwell: --- -Intel Crown Bay specific instructions for bare mode: - -U-Boot support of Intel Crown Bay board [4] relies on a binary blob called -Firmware Support Package [5] to perform all the necessary initialization steps -as documented in the BIOS Writer Guide, including initialization of the CPU, -memory controller, chipset and certain bus interfaces. - -Download the Intel FSP for Atom E6xx series and Platform Controller Hub EG20T, -install it on your host and locate the FSP binary blob. Note this platform -also requires a Chipset Micro Code (CMC) state machine binary to be present in -the SPI flash where u-boot.rom resides, and this CMC binary blob can be found -in this FSP package too. - -* ./FSP/QUEENSBAY_FSP_GOLD_001_20-DECEMBER-2013.fd -* ./Microcode/C0_22211.BIN - -Rename the first one to fsp.bin and second one to cmc.bin and put them in the -board directory. - -Note the FSP release version 001 has a bug which could cause random endless -loop during the FspInit call. This bug was published by Intel although Intel -did not describe any details. We need manually apply the patch to the FSP -binary using any hex editor (eg: bvi). Go to the offset 0x1fcd8 of the FSP -binary, change the following five bytes values from orginally E8 42 FF FF FF -to B8 00 80 0B 00. - -As for the video ROM, you need manually extract it from the Intel provided -BIOS for Crown Bay here [6], using the AMI MMTool [7]. Check PCI option ROM -ID 8086:4108, extract and save it as vga.bin in the board directory. - -Now you can build U-Boot and obtain u-boot.rom - -$ make crownbay_defconfig -$ make all - - Intel Cougar Canyon 2 specific instructions for bare mode: This uses Intel FSP for 3rd generation Intel Core and Intel Celeron processors diff --git a/doc/board/index.rst b/doc/board/index.rst index 4a65def..34e59de 100644 --- a/doc/board/index.rst +++ b/doc/board/index.rst @@ -4,3 +4,5 @@ Board-specific doc .. toctree:: :maxdepth: 2 + + intel/index diff --git a/doc/board/intel/crownbay.rst b/doc/board/intel/crownbay.rst new file mode 100644 index 000..d77cece --- /dev/null +++ b/doc/board/intel/crownbay.rst @@ -0,0 +1,49 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +:author: Bin Meng + +.. toctree:: + :maxdepth: 2 + +Intel CrownBay CRB +== + +U-Boot support of Intel Crown Bay board `[1]`_ relies on a binary blob called +Firmware Support Package `[2]`_ to perform all the necessary initialization +steps as documented in the BIOS Writer Guide, including initialization of the +CPU, memory controller, chipset and certain bus interfaces. + +Download the Intel FSP for Atom E6xx series and Platform Controller Hub EG20T, +install it on your host and locate the FSP binary blob. Note this platform +also requires a Chipset Micro Code (CMC) state machine binary to be present in +the SPI flash where u-boot.rom resides, and this CMC binary blob can be found +in this FSP package too. + +* ./FSP/QUEENSBAY_FSP_GOLD_001_20-DECEMBER-2013.fd +* ./Microcode/C0_22211.BIN + +Rename the first one to fsp.bin and second one to cmc.bin and put them in the +board directory. + +Note the FSP release version 001 has a bug which could cause random endless +loop during the FspInit call. This bug was published by Intel although Intel +did not describe any details. We need manually apply the patch to the FSP +binary using any hex editor (eg: bvi). Go to the offset 0x1fcd8 of the FSP +binary, change the following five bytes values from orginally E8 42 FF FF FF +to B8 00 80 0B 00. + +As for the video ROM, you need manually extract it from the Intel provided +BIOS for Crown Bay here `[3]`_, using the AMI MMTool `[4]`_. Check PCI option +ROM ID 8086:4108, extract and save it as vga.bin in the board directory. + +Now you can build U-Boot and obtain u-boot.rom + +.. code-block:: shell + + $ make crownbay_defconfig + $ make all + +.. _[1]: http://www.intel.com/content/www/us/en/embedded/design-tools/evaluation-platforms/atom-e660-eg20t-development-kit.html +.. _[2]: http://www.intel.com/fsp +.. _[3]: http://www.intel.com/content/www/us/en/secure/intelligent-systems/privileged/e6xx-35-b1-cmc22211.html +.. _[4]:
[U-Boot] [RFC PATCH 8/9] doc: Add board to Sphinx TOC tree
Add index.rst for board. More docs will be added later. Signed-off-by: Bin Meng --- doc/board/index.rst | 6 ++ doc/index.rst | 11 +++ 2 files changed, 17 insertions(+) create mode 100644 doc/board/index.rst diff --git a/doc/board/index.rst b/doc/board/index.rst new file mode 100644 index 000..4a65def --- /dev/null +++ b/doc/board/index.rst @@ -0,0 +1,6 @@ +== +Board-specific doc +== + +.. toctree:: + :maxdepth: 2 diff --git a/doc/index.rst b/doc/index.rst index 562f1b7..fbdf50b 100644 --- a/doc/index.rst +++ b/doc/index.rst @@ -51,6 +51,17 @@ implementation. arch/index +Board-specific doc +-- + +These books provide details about board-specific information. They are +organized in a vendor subdirectory. + +.. toctree:: + :maxdepth: 2 + + board/index + Indices and tables == -- 2.7.4 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [RFC PATCH 7/9] doc: arch: Convert README.mips to reST
Convert plain text documentation to reStructuredText format and add
it to Sphinx TOC tree. No essential content change.
Signed-off-by: Bin Meng
---
doc/arch/index.rst | 2 ++
doc/{README.mips => arch/mips.rst} | 14 --
2 files changed, 10 insertions(+), 6 deletions(-)
rename doc/{README.mips => arch/mips.rst} (87%)
diff --git a/doc/arch/index.rst b/doc/arch/index.rst
index 920043a..bdeccdb 100644
--- a/doc/arch/index.rst
+++ b/doc/arch/index.rst
@@ -4,3 +4,5 @@ Architecture-specific doc
.. toctree::
:maxdepth: 2
+
+ mips
diff --git a/doc/README.mips b/doc/arch/mips.rst
similarity index 87%
rename from doc/README.mips
rename to doc/arch/mips.rst
index b28f628..b51d0a1 100644
--- a/doc/README.mips
+++ b/doc/arch/mips.rst
@@ -1,17 +1,19 @@
+MIPS
+
Notes for the MIPS architecture port of U-Boot
Toolchains
--
- http://www.denx.de/wiki/DULG/ELDK
- ELDK < DULG < DENX
+ * http://www.denx.de/wiki/DULG/ELDK
+ELDK < DULG < DENX
- http://www.emdebian.org/crosstools.html
- Embedded Debian -- Cross-development toolchains
+ * http://www.emdebian.org/crosstools.html
+Embedded Debian -- Cross-development toolchains
- http://buildroot.uclibc.org/
- Buildroot
+ * http://buildroot.uclibc.org/
+Buildroot
Known Issues
--
2.7.4
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[U-Boot] [RFC PATCH 4/9] doc: driver-model: Convert README.txt to reST
Convert plain text documentation to reStructuredText format and add
it to Sphinx TOC tree. No essential content change.
Signed-off-by: Bin Meng
---
doc/driver-model/{README.txt => design.rst} | 538 +++-
doc/driver-model/index.rst | 2 +
2 files changed, 284 insertions(+), 256 deletions(-)
rename doc/driver-model/{README.txt => design.rst} (68%)
diff --git a/doc/driver-model/README.txt b/doc/driver-model/design.rst
similarity index 68%
rename from doc/driver-model/README.txt
rename to doc/driver-model/design.rst
index 532a771..c8ec2be 100644
--- a/doc/driver-model/README.txt
+++ b/doc/driver-model/design.rst
@@ -1,40 +1,43 @@
-Driver Model
-
+Design Details
+==
This README contains high-level information about driver model, a unified
way of declaring and accessing drivers in U-Boot. The original work was done
by:
- Marek Vasut
- Pavel Herrmann
- Viktor KÅivák
- Tomas Hlavacek
+ * Marek Vasut
+ * Pavel Herrmann
+ * Viktor KÅivák
+ * Tomas Hlavacek
This has been both simplified and extended into the current implementation
by:
- Simon Glass
+ * Simon Glass
Terminology
---
-Uclass - a group of devices which operate in the same way. A uclass provides
- a way of accessing individual devices within the group, but always
- using the same interface. For example a GPIO uclass provides
- operations for get/set value. An I2C uclass may have 10 I2C ports,
- 4 with one driver, and 6 with another.
+Uclass
+ a group of devices which operate in the same way. A uclass provides
+ a way of accessing individual devices within the group, but always
+ using the same interface. For example a GPIO uclass provides
+ operations for get/set value. An I2C uclass may have 10 I2C ports,
+ 4 with one driver, and 6 with another.
-Driver - some code which talks to a peripheral and presents a higher-level
- interface to it.
+Driver
+ some code which talks to a peripheral and presents a higher-level
+ interface to it.
-Device - an instance of a driver, tied to a particular port or peripheral.
+Device
+ an instance of a driver, tied to a particular port or peripheral.
How to try it
-
-Build U-Boot sandbox and run it:
+Build U-Boot sandbox and run it::
make sandbox_defconfig
make
@@ -56,31 +59,31 @@ provide good code coverage of them. It does have multiple
drivers, it
handles parameter data and platdata (data which tells the driver how
to operate on a particular platform) and it uses private driver data.
-To try it, see the example session below:
-
-=>demo hello 1
-Hello '@' from 07981110: red 4
-=>demo status 2
-Status: 0
-=>demo hello 2
-g
-r@
-e@@
-e@@@
-n
-g@
-=>demo status 2
-Status: 21
-=>demo hello 4 ^
- y^^^
- e^
-l^^^
-l^^^
- o^
- w^^^
-=>demo status 4
-Status: 36
-=>
+To try it, see the example session below::
+
+ =>demo hello 1
+ Hello '@' from 07981110: red 4
+ =>demo status 2
+ Status: 0
+ =>demo hello 2
+ g
+ r@
+ e@@
+ e@@@
+ n
+ g@
+ =>demo status 2
+ Status: 21
+ =>demo hello 4 ^
+ y^^^
+e^
+ l^^^
+ l^^^
+o^
+ w^^^
+ =>demo status 4
+ Status: 36
+ =>
Running the tests
@@ -88,139 +91,139 @@ Running the tests
The intent with driver model is that the core portion has 100% test coverage
in sandbox, and every uclass has its own test. As a move towards this, tests
-are provided in test/dm. To run them, try:
+are provided in test/dm. To run them, try::
./test/py/test.py --bd sandbox --build -k ut_dm -v
-You should see something like this:
-
-(venv)$ ./test/py/test.py --bd sandbox --build -k ut_dm -v
-+make O=/root/u-boot/build-sandbox -s sandbox_defconfig
-+make O=/root/u-boot/build-sandbox -s -j8
-= test session starts
==
-platform linux2 -- Python 2.7.5, pytest-2.9.0, py-1.4.31, pluggy-0.3.1 --
/root/u-boot/venv/bin/python
-cachedir: .cache
-rootdir: /root/u-boot, inifile:
-collected 199 items
-
-test/py/tests/test_ut.py::test_ut_dm_init PASSED
-test/py/tests/test_ut.py::test_ut[ut_dm_adc_bind] PASSED
-test/py/tests/test_ut.py::test_ut[ut_dm_adc_multi_channel_conversion] PASSED
-test/py/tests/test_ut.py::test_ut[ut_dm_adc_multi_channel_shot] PASSED
-test/py/tests/test_ut.py::test_ut[ut_dm_adc_single_channel_conversion] PASSED
-test/py/tests/test_ut.py::test_ut[ut_dm_adc_single_channel_shot] PASSED
-test/py/tests/test_ut.py::test_ut[ut_dm_adc_supply] PASSED
-test/py/tests/test_ut.py::test_ut[ut_dm_adc_wrong_channel_selection] PASSED
-test/py/tests/test_ut.py::test_ut[ut_dm_autobind] PASSED
-test/py/tests/test_ut.py::test_ut[ut_dm_autobind_uclass_pdata_alloc] PASSED
-test/py/tests/test_ut.py::test_ut[ut_dm_autobind_uclass_pdata_valid] PASSED
-test/py/tests/test_ut.py::test_ut[ut_dm_autoprobe] PASSED
[U-Boot] [RFC PATCH 3/9] doc: Add driver-model to Sphinx TOC tree
Add index.rst for driver model. More docs will be added later. Signed-off-by: Bin Meng --- doc/driver-model/index.rst | 6 ++ doc/index.rst | 11 +++ 2 files changed, 17 insertions(+) create mode 100644 doc/driver-model/index.rst diff --git a/doc/driver-model/index.rst b/doc/driver-model/index.rst new file mode 100644 index 000..c16a544 --- /dev/null +++ b/doc/driver-model/index.rst @@ -0,0 +1,6 @@ + +Driver Model + + +.. toctree:: + :maxdepth: 2 diff --git a/doc/index.rst b/doc/index.rst index cfcf1dd..835decf 100644 --- a/doc/index.rst +++ b/doc/index.rst @@ -15,6 +15,17 @@ if you want to help out. .. toctree:: :maxdepth: 2 +Driver-Model documentation +-- +The following holds information on the U-Boot device driver framework: +driver-model, including the design details of itself and several driver +subsystems. + +.. toctree:: + :maxdepth: 2 + + driver-model/index + U-Boot API documentation -- 2.7.4 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [RFC PATCH 5/9] doc: driver-model: Convert MIGRATION.txt to reST
Convert plain text documentation to reStructuredText format and add
it to Sphinx TOC tree. No essential content change.
Signed-off-by: Bin Meng
---
doc/driver-model/index.rst| 1 +
doc/driver-model/{MIGRATION.txt => migration.rst} | 42 ++-
2 files changed, 20 insertions(+), 23 deletions(-)
rename doc/driver-model/{MIGRATION.txt => migration.rst} (85%)
diff --git a/doc/driver-model/index.rst b/doc/driver-model/index.rst
index ae28dc0..7d5faf3 100644
--- a/doc/driver-model/index.rst
+++ b/doc/driver-model/index.rst
@@ -6,3 +6,4 @@ Driver Model
:maxdepth: 2
design
+ migration
diff --git a/doc/driver-model/MIGRATION.txt b/doc/driver-model/migration.rst
similarity index 85%
rename from doc/driver-model/MIGRATION.txt
rename to doc/driver-model/migration.rst
index d38be35..73e22ed 100644
--- a/doc/driver-model/MIGRATION.txt
+++ b/doc/driver-model/migration.rst
@@ -1,5 +1,5 @@
Migration Schedule
-
+==
U-Boot has been migrating to a new driver model since its introduction in
2014. This file describes the schedule for deprecation of pre-driver-model
@@ -8,8 +8,8 @@ features.
CONFIG_DM_MMC
-
-Status: In progress
-Deadline: 2019.04
+* Status: In progress
+* Deadline: 2019.04
The subsystem itself has been converted and maintainers should submit patches
switching over to using CONFIG_DM_MMC and other base driver model options in
@@ -18,8 +18,8 @@ time for inclusion in the 2019.04 rerelease.
CONFIG_DM_USB
-
-Status: In progress
-Deadline: 2019.07
+* Status: In progress
+* Deadline: 2019.07
The subsystem itself has been converted along with many of the host controller
and maintainers should submit patches switching over to using CONFIG_DM_USB and
@@ -28,8 +28,8 @@ other base driver model options in time for inclusion in the
2019.07 rerelease.
CONFIG_SATA
---
-Status: In progress
-Deadline: 2019.07
+* Status: In progress
+* Deadline: 2019.07
The subsystem itself has been converted along with many of the host controller
and maintainers should submit patches switching over to using CONFIG_AHCI and
@@ -38,8 +38,8 @@ other base driver model options in time for inclusion in the
2019.07 rerelease.
CONFIG_BLK
--
-Status: In progress
-Deadline: 2019.07
+* Status: In progress
+* Deadline: 2019.07
In concert with maintainers migrating their block device usage to the
appropriate DM driver, CONFIG_BLK needs to be set as well. The final deadline
@@ -48,14 +48,14 @@ subsystems. At this point we will be able to audit and
correct the logic in
Kconfig around using CONFIG_PARTITIONS and CONFIG_HAVE_BLOCK_DEVICE and make
use of CONFIG_BLK / CONFIG_SPL_BLK as needed.
-CONFIG_DM_SPI
-CONFIG_DM_SPI_FLASH
+CONFIG_DM_SPI / CONFIG_DM_SPI_FLASH
+---
Board Maintainers should submit the patches for enabling DM_SPI and
DM_SPI_FLASH
to move the migration with in the deadline.
-No dm conversion yet:
+No dm conversion yet::
+
drivers/spi/cf_spi.c
drivers/spi/fsl_espi.c
drivers/spi/lpc32xx_ssp.c
@@ -63,10 +63,11 @@ No dm conversion yet:
drivers/spi/sh_spi.c
drivers/spi/soft_spi_legacy.c
- Status: In progress
- Deadline: 2019.04
+* Status: In progress
+* Deadline: 2019.04
+
+Partially converted::
-Partially converted:
drivers/spi/davinci_spi.c
drivers/spi/fsl_dspi.c
drivers/spi/kirkwood_spi.c
@@ -74,13 +75,8 @@ Partially converted:
drivers/spi/omap3_spi.c
drivers/spi/sh_qspi.c
- Status: In progress
- Deadline: 2019.07
-
---
-Jagan Teki
-12/24/2018
-03/14/2018
+* Status: In progress
+* Deadline: 2019.07
CONFIG_DM_PCI
--
2.7.4
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[U-Boot] [RFC PATCH 6/9] doc: Add architecture specific info to Sphinx TOC tree
Add index.rst for architecture specific info. More docs will be added later. Signed-off-by: Bin Meng --- doc/arch/index.rst | 6 ++ doc/index.rst | 11 +++ 2 files changed, 17 insertions(+) create mode 100644 doc/arch/index.rst diff --git a/doc/arch/index.rst b/doc/arch/index.rst new file mode 100644 index 000..920043a --- /dev/null +++ b/doc/arch/index.rst @@ -0,0 +1,6 @@ += +Architecture-specific doc += + +.. toctree:: + :maxdepth: 2 diff --git a/doc/index.rst b/doc/index.rst index 835decf..562f1b7 100644 --- a/doc/index.rst +++ b/doc/index.rst @@ -40,6 +40,17 @@ needed). api/index +Architecture-specific doc +- + +These books provide programming details about architecture-specific +implementation. + +.. toctree:: + :maxdepth: 2 + + arch/index + Indices and tables == -- 2.7.4 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [RFC PATCH 1/9] doc: Move existing rst files into api sub-directory
Currently the Sphinx doc only contains API descriptions of several
U-Boot subsystems. For future extension, group these existing docs
into an API sub-directory.
Signed-off-by: Bin Meng
---
doc/{ => api}/efi.rst | 3 +++
doc/api/index.rst | 10 ++
doc/{ => api}/linker_lists.rst | 3 +++
doc/{ => api}/serial.rst | 3 +++
doc/index.rst | 14 +++---
5 files changed, 30 insertions(+), 3 deletions(-)
rename doc/{ => api}/efi.rst (92%)
create mode 100644 doc/api/index.rst
rename doc/{ => api}/linker_lists.rst (99%)
rename doc/{ => api}/serial.rst (80%)
diff --git a/doc/efi.rst b/doc/api/efi.rst
similarity index 92%
rename from doc/efi.rst
rename to doc/api/efi.rst
index 5337a55..3b2d544 100644
--- a/doc/efi.rst
+++ b/doc/api/efi.rst
@@ -1,5 +1,8 @@
.. SPDX-License-Identifier: GPL-2.0+
+.. toctree::
+ :maxdepth: 2
+
EFI subsystem
=
diff --git a/doc/api/index.rst b/doc/api/index.rst
new file mode 100644
index 000..8e1e1a1
--- /dev/null
+++ b/doc/api/index.rst
@@ -0,0 +1,10 @@
+
+U-Boot API documentation
+
+
+.. toctree::
+ :maxdepth: 2
+
+ efi
+ linker_lists
+ serial
diff --git a/doc/linker_lists.rst b/doc/api/linker_lists.rst
similarity index 99%
rename from doc/linker_lists.rst
rename to doc/api/linker_lists.rst
index 72f514e..477bbae 100644
--- a/doc/linker_lists.rst
+++ b/doc/api/linker_lists.rst
@@ -1,5 +1,8 @@
.. SPDX-License-Identifier: GPL-2.0+
+.. toctree::
+ :maxdepth: 2
+
Linker-Generated Arrays
===
diff --git a/doc/serial.rst b/doc/api/serial.rst
similarity index 80%
rename from doc/serial.rst
rename to doc/api/serial.rst
index ed34e59..65f10d3 100644
--- a/doc/serial.rst
+++ b/doc/api/serial.rst
@@ -1,5 +1,8 @@
.. SPDX-License-Identifier: GPL-2.0+
+.. toctree::
+ :maxdepth: 2
+
Serial system
=
diff --git a/doc/index.rst b/doc/index.rst
index 0353c10..1946d09 100644
--- a/doc/index.rst
+++ b/doc/index.rst
@@ -4,8 +4,16 @@
U-Boot Developer Manual
###
+U-Boot API documentation
+
+
+These books get into the details of how specific U-Boot subsystems work
+from the point of view of a U-Boot developer. Much of the information here
+is taken directly from the U-Boot source, with supplemental material added
+as needed (or at least as we managed to add it - probably *not* all that is
+needed).
+
.. toctree::
+ :maxdepth: 2
- efi
- linker_lists
- serial
+ api/index
--
2.7.4
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[U-Boot] [RFC PATCH 0/9] Initial layout for Sphinx HTML docs
At present there is Sphinx doc build system in U-Boot, however the
contents are very limited, that only a few API descriptions for EFI,
are included.
This series proposes an initial Sphinx doc layout for future extension,
by converting some of the plain text documentation to reStructuredText
format and add it to Sphinx TOC tree.
@Wolfgang, is it possible to host the Sphinx HTML docs on denx.de?
This series is available at u-boot-x86/doc for testing.
Bin Meng (9):
doc: Move existing rst files into api sub-directory
doc: Add top-level description about U-Boot documentation
doc: Add driver-model to Sphinx TOC tree
doc: driver-model: Convert README.txt to reST
doc: driver-model: Convert MIGRATION.txt to reST
doc: Add architecture specific info to Sphinx TOC tree
doc: arch: Convert README.mips to reST
doc: Add board to Sphinx TOC tree
doc: board: Add Intel Crown Bay board doc
doc/README.x86| 37 --
doc/{ => api}/efi.rst | 3 +
doc/api/index.rst | 10 +
doc/{ => api}/linker_lists.rst| 3 +
doc/{ => api}/serial.rst | 3 +
doc/arch/index.rst| 8 +
doc/{README.mips => arch/mips.rst}| 14 +-
doc/board/index.rst | 8 +
doc/board/intel/crownbay.rst | 49 ++
doc/board/intel/index.rst | 4 +
doc/driver-model/{README.txt => design.rst} | 538 --
doc/driver-model/index.rst| 9 +
doc/driver-model/{MIGRATION.txt => migration.rst} | 42 +-
doc/index.rst | 69 ++-
14 files changed, 469 insertions(+), 328 deletions(-)
rename doc/{ => api}/efi.rst (92%)
create mode 100644 doc/api/index.rst
rename doc/{ => api}/linker_lists.rst (99%)
rename doc/{ => api}/serial.rst (80%)
create mode 100644 doc/arch/index.rst
rename doc/{README.mips => arch/mips.rst} (87%)
create mode 100644 doc/board/index.rst
create mode 100644 doc/board/intel/crownbay.rst
create mode 100644 doc/board/intel/index.rst
rename doc/driver-model/{README.txt => design.rst} (68%)
create mode 100644 doc/driver-model/index.rst
rename doc/driver-model/{MIGRATION.txt => migration.rst} (85%)
--
2.7.4
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[U-Boot] [PATCH 2/2] doc: Add the U-Boot logo to the html doc
Now we have a logo for U-Boot, we can include it in the Sphinx html doc. Signed-off-by: Bin Meng --- doc/conf.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/doc/conf.py b/doc/conf.py index 168c313..0772fb6 100644 --- a/doc/conf.py +++ b/doc/conf.py @@ -170,7 +170,7 @@ except ImportError: # The name of an image file (relative to this directory) to place at the top # of the sidebar. -#html_logo = None +html_logo = '../tools/logos/u-boot_logo.svg' # The name of an image file (within the static path) to use as favicon of the # docs. This file should be a Windows icon file (.ico) being 16x16 or 32x32 -- 2.7.4 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 1/2] doc: Add .gitignore for the Sphinx build output directory
With Sphinx documentation moving from Documentation directory to doc directory, we missed updating .gitignore for the Sphinx build output directory. Signed-off-by: Bin Meng --- Documentation/.gitignore | 1 - doc/.gitignore | 1 + 2 files changed, 1 insertion(+), 1 deletion(-) create mode 100644 doc/.gitignore diff --git a/Documentation/.gitignore b/Documentation/.gitignore index e74fec8..0d20b64 100644 --- a/Documentation/.gitignore +++ b/Documentation/.gitignore @@ -1,2 +1 @@ -output *.pyc diff --git a/doc/.gitignore b/doc/.gitignore new file mode 100644 index 000..53752db --- /dev/null +++ b/doc/.gitignore @@ -0,0 +1 @@ +output -- 2.7.4 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH] fpga: arria10: Fix error in fpga pin configuration
From: Dalon Westergreen
Pin configuration of the FPGA devicetree block should be done
after core configuration in the arria10 fpga driver. This fix
corrects the check of status, and ensures that the fpga pin mux
is configured on correct configuration of the core fpga image.
Signed-off-by: Dalon Westergreen
---
drivers/fpga/socfpga_arria10.c | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/drivers/fpga/socfpga_arria10.c b/drivers/fpga/socfpga_arria10.c
index 285280e507..5fb9d6a191 100644
--- a/drivers/fpga/socfpga_arria10.c
+++ b/drivers/fpga/socfpga_arria10.c
@@ -936,10 +936,11 @@ int socfpga_load(Altera_desc *desc, const void *rbf_data,
size_t rbf_size)
fpgamgr_program_write(rbf_data, rbf_size);
status = fpgamgr_program_finish();
- if (status) {
- config_pins(gd->fdt_blob, "fpga");
- puts("FPGA: Enter user mode.\n");
- }
+ if (status)
+ return status;
+
+ config_pins(gd->fdt_blob, "fpga");
+ puts("FPGA: Enter user mode.\n");
return status;
}
--
2.21.0
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Re: [U-Boot] [PATCH v2 1/2] flash: Script to create a flash image from u-boot
On 7/15/19 5:14 PM, Joel Stanley wrote: This creates an empty flash image and places u-boot at the start of it. It will be used by the ASPEED Qemu tests which boot u-boot from an emaulated flash device. diff --git a/bin/flash.create_image_32mb b/bin/flash.create_image_32mb I can foresee a future where we rename this flash.create_image and pass in the image size via a variable that's set by the conf.xxx file. But this is fine for now. I've applied both patches. Thanks. ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 12/16] config: rpi4: Add defconfig for rpi4-32
On Tue, Jul 16, 2019 at 3:25 PM Matthias Brugger wrote: > > > > On 16/07/2019 15:37, and...@gherzan.ro wrote: > > From: Andrei Gherzan > > > > Signed-off-by: Andrei Gherzan > > --- > > configs/rpi_4_32b_defconfig | 43 + > > 1 file changed, 43 insertions(+) > > create mode 100644 configs/rpi_4_32b_defconfig > > > > diff --git a/configs/rpi_4_32b_defconfig b/configs/rpi_4_32b_defconfig > > new file mode 100644 > > index 00..9f2b805d0f > > --- /dev/null > > +++ b/configs/rpi_4_32b_defconfig > > @@ -0,0 +1,43 @@ > > +CONFIG_ARM=y > > +CONFIG_ARCH_BCM283X=y > > +CONFIG_SYS_TEXT_BASE=0x8000 > > +CONFIG_TARGET_RPI_4_32B=y > > +CONFIG_SYS_MALLOC_F_LEN=0x2000 > > +CONFIG_DISTRO_DEFAULTS=y > > +CONFIG_NR_DRAM_BANKS=1 > > +CONFIG_OF_BOARD_SETUP=y > > +CONFIG_MISC_INIT_R=y > > +# CONFIG_DISPLAY_CPUINFO is not set > > +# CONFIG_DISPLAY_BOARDINFO is not set > > +CONFIG_SYS_PROMPT="U-Boot> " > > +# CONFIG_CMD_FLASH is not set > > +CONFIG_CMD_GPIO=y > > +CONFIG_CMD_MMC=y > > +CONFIG_CMD_USB=y > > +CONFIG_CMD_FS_UUID=y > > +CONFIG_OF_EMBED=y > > +CONFIG_DEFAULT_DEVICE_TREE="bcm2838-rpi-4-b" > > +CONFIG_ENV_FAT_INTERFACE="mmc" > > +CONFIG_ENV_FAT_DEVICE_AND_PART="0:1" > > +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y > > +CONFIG_DM_KEYBOARD=y > > +CONFIG_DM_MMC=y > > +CONFIG_MMC_SDHCI=y > > +CONFIG_MMC_SDHCI_BCM2835=y > > +CONFIG_PHYLIB=y > > +CONFIG_DM_ETH=y > > +CONFIG_PINCTRL=y > > +# CONFIG_PINCTRL_GENERIC is not set > > +# CONFIG_REQUIRE_SERIAL_CONSOLE is not set > > +CONFIG_USB=y > > +CONFIG_DM_USB=y > > +CONFIG_USB_DWC2=y > > +CONFIG_USB_KEYBOARD=y > > +CONFIG_USB_HOST_ETHER=y > > +CONFIG_USB_ETHER_LAN78XX=y > > +CONFIG_USB_ETHER_SMSC95XX=y > > Network is connected via PCI, why do we need this options here? Network is attached to a PHY not via PCI, that would be the USB. It seems they're removed in patch 15 but the two should be squashed together. > > +CONFIG_DM_VIDEO=y > > +CONFIG_SYS_WHITE_ON_BLACK=y > > +CONFIG_CONSOLE_SCROLL_LINES=10 > > +CONFIG_PHYS_TO_BUS=y > > +CONFIG_OF_LIBFDT_OVERLAY=y > > > ___ > U-Boot mailing list > U-Boot@lists.denx.de > https://lists.denx.de/listinfo/u-boot ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] ARM: bcm283x mbox: Fix send status register
On 7/16/19 5:09 AM, matthias@kernel.org wrote: From: Fabian Vogt Before we can send a message to the mailbox we have to check that there is space to do so. Therefore we poll the status register. But up to now the wrong status register, the one of mailbox 0, was checked. Fix this by polling the status regiser of mailbox 1. This sounds plausible at least (I didn't check which of mbox 0/1 was TX/RX), so, Acked-by: Stephen Warren ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] Pull request: u-boot-sunxi/master
Hi Tom, Please pull this PR. Summary: - Beelink-x2 STB support (Marcus) - H6 DDR3, LPDDR3 changes (Andre, Jernej) - H6 pin controller, USB PHY (Andre) thanks, Jagan. The following changes since commit 6070ef409c1018860e8dd1f077297546d9d80115: Merge branch '2019-07-12-master-imports' (2019-07-14 09:05:20 -0400) are available in the Git repository at: https://gitlab.denx.de/u-boot/custodians/u-boot-sunxi master for you to fetch changes up to f96238e253661b43168352010a2628957940bd4b: sunxi: H6: Enable USB for existing boards (2019-07-16 17:13:15 +0530) Andre Przywara (11): sunxi: move CONFIG_SPL_TEXT_BASE from *_defconfig to Kconfig sunxi: H6: DRAM: avoid memcpy() on MMIO registers sunxi: H6: DRAM: follow recommended PHY init algorithm sunxi: H6: move LPDDR3 timing definition into separate file sunxi: H6: Add DDR3 support to DRAM controller driver sunxi: H6: Add DDR3-1333 timings sunxi: move SUNXI_GPIO to Kconfig sunxi: gpio: Enable support for H6 pin controller sunxi: clocks: Add H6 USB clock gates and resets sunxi: phy: Add USB PHY support for Allwinner H6 sunxi: H6: Enable USB for existing boards Jernej Skrabec (1): sunxi: H6: Add DDR3 DRAM delay values Marcus Cooper (1): sun8i: h3: Add support for the Beelink-x2 STB arch/arm/Kconfig | 1 + arch/arm/dts/Makefile| 1 + arch/arm/dts/sun8i-h3-beelink-x2.dts | 216 +++ arch/arm/include/asm/arch-sunxi/dram_sun50i_h6.h | 35 arch/arm/mach-sunxi/Kconfig | 19 +- arch/arm/mach-sunxi/Makefile | 1 + arch/arm/mach-sunxi/dram_sun50i_h6.c | 251 +++ arch/arm/mach-sunxi/dram_timings/Makefile| 2 + arch/arm/mach-sunxi/dram_timings/h6_ddr3_1333.c | 144 + arch/arm/mach-sunxi/dram_timings/h6_lpddr3.c | 132 board/sunxi/MAINTAINERS | 6 + common/spl/Kconfig | 3 + configs/A10-OLinuXino-Lime_defconfig | 1 - configs/A10s-OLinuXino-M_defconfig | 1 - configs/A13-OLinuXinoM_defconfig | 1 - configs/A13-OLinuXino_defconfig | 1 - configs/A20-OLinuXino-Lime2-eMMC_defconfig | 1 - configs/A20-OLinuXino-Lime2_defconfig| 1 - configs/A20-OLinuXino-Lime_defconfig | 1 - configs/A20-OLinuXino_MICRO-eMMC_defconfig | 1 - configs/A20-OLinuXino_MICRO_defconfig| 1 - configs/A20-Olimex-SOM-EVB_defconfig | 1 - configs/A20-Olimex-SOM204-EVB-eMMC_defconfig | 1 - configs/A20-Olimex-SOM204-EVB_defconfig | 1 - configs/A33-OLinuXino_defconfig | 1 - configs/Ainol_AW1_defconfig | 1 - configs/Ampe_A76_defconfig | 1 - configs/Auxtek-T003_defconfig| 1 - configs/Auxtek-T004_defconfig| 1 - configs/Bananapi_M2_Ultra_defconfig | 1 - configs/Bananapi_defconfig | 1 - configs/Bananapi_m2m_defconfig | 1 - configs/Bananapro_defconfig | 1 - configs/CHIP_defconfig | 1 - configs/CHIP_pro_defconfig | 1 - configs/CSQ_CS908_defconfig | 1 - configs/Chuwi_V7_CW0825_defconfig| 1 - configs/Colombus_defconfig | 1 - configs/Cubieboard2_defconfig| 1 - configs/Cubieboard4_defconfig| 1 - configs/Cubieboard_defconfig | 1 - configs/Cubietruck_defconfig | 1 - configs/Cubietruck_plus_defconfig| 1 - configs/Empire_electronix_d709_defconfig | 1 - configs/Empire_electronix_m712_defconfig | 1 - configs/Hummingbird_A31_defconfig| 1 - configs/Hyundai_A7HD_defconfig | 1 - configs/Itead_Ibox_A20_defconfig | 1 - configs/Lamobo_R1_defconfig | 1 - configs/LicheePi_Zero_defconfig | 1 - configs/Linksprite_pcDuino3_Nano_defconfig | 1 - configs/Linksprite_pcDuino3_defconfig| 1 - configs/Linksprite_pcDuino_defconfig | 1 - configs/MK808C_defconfig | 1 - configs/MSI_Primo73_defconfig| 1 - configs/MSI_Primo81_defconfig| 1 - configs/Marsboard_A10_defconfig | 1 - configs/Mele_A1000G_quad_defconfig | 1 - configs/Mele_A1000_defconfig | 1 - configs/Mele_I7_defconfig| 1 - configs/Mele_M3_defconfig|
Re: [U-Boot] Pull request: u-boot-net.git master
On Mon, Jul 15, 2019 at 05:49:01PM -0500, Joe Hershberger wrote: > Hi Tom, > > These patches passed travis [1] and are ready for master. > > Thanks, > -Joe > > [1] - https://travis-ci.org/jhershbe/u-boot/builds/559064493 > > The following changes since commit a9a3a37f92b072a56693ad665ab4c5cc73028d16: > > Merge tag 'u-boot-stm32-20190712' of > https://gitlab.denx.de/u-boot/custodians/u-boot-stm (2019-07-14 09:09:49 > -0400) > > are available in the git repository at: > > git://git.denx.de/u-boot-net.git master > > for you to fetch changes up to 0dc97fc3d8cd8c4154f63c9ea74f5e73ee48fa6c: > > net: macb: Add support for 1000-baseX (2019-07-15 13:32:26 -0500) > Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 08/16] mmc: bcm2835_sdhci: Add support for bcm2711 device
On 16/07/2019 15:37, and...@gherzan.ro wrote:
> From: Matthias Brugger
>
> The bcm2711 has two emmc controller. The difference is the clocks
> they use. Add support for the second emmc contoller.
>
> Signed-off-by: Matthias Brugger
missing your signed-off-by.
> ---
> drivers/mmc/bcm2835_sdhci.c | 12 ++--
> 1 file changed, 10 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/mmc/bcm2835_sdhci.c b/drivers/mmc/bcm2835_sdhci.c
> index 08bddd410e..e68dec3be7 100644
> --- a/drivers/mmc/bcm2835_sdhci.c
> +++ b/drivers/mmc/bcm2835_sdhci.c
> @@ -178,12 +178,13 @@ static int bcm2835_sdhci_probe(struct udevice *dev)
> fdt_addr_t base;
> int emmc_freq;
> int ret;
> + int clock_id = (int)dev_get_driver_data(dev);
>
> base = devfdt_get_addr(dev);
> if (base == FDT_ADDR_T_NONE)
> return -EINVAL;
>
> - ret = bcm2835_get_mmc_clock(BCM2835_MBOX_CLOCK_ID_EMMC);
> + ret = bcm2835_get_mmc_clock(clock_id);
> if (ret < 0) {
> debug("%s: Failed to set MMC clock (err=%d)\n", __func__, ret);
> return ret;
> @@ -228,7 +229,14 @@ static int bcm2835_sdhci_probe(struct udevice *dev)
> }
>
> static const struct udevice_id bcm2835_sdhci_match[] = {
> - { .compatible = "brcm,bcm2835-sdhci" },
> + {
> + .compatible = "brcm,bcm2835-sdhci",
> + .data = BCM2835_MBOX_CLOCK_ID_EMMC
> + },
> + {
> + .compatible = "brcm,bcm2711-emmc2",
> + .data = BCM2835_MBOX_CLOCK_ID_EMMC2
> + },
> { /* sentinel */ }
> };
>
>
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Re: [U-Boot] [PATCH 05/16] rpi: Add rpi_model entry for RaspberryPi 4
On 16/07/2019 15:37, and...@gherzan.ro wrote:
> From: Andrei Gherzan
>
> Signed-off-by: Andrei Gherzan
Commit message missing.
> ---
> board/raspberrypi/rpi/rpi.c | 5 +
> 1 file changed, 5 insertions(+)
>
> diff --git a/board/raspberrypi/rpi/rpi.c b/board/raspberrypi/rpi/rpi.c
> index 617c892dde..6d6f1ef39a 100644
> --- a/board/raspberrypi/rpi/rpi.c
> +++ b/board/raspberrypi/rpi/rpi.c
> @@ -148,6 +148,11 @@ static const struct rpi_model rpi_models_new_scheme[] = {
> DTB_DIR "bcm2837-rpi-cm3.dtb",
> false,
> },
> + [0x11] = {
> + "4 Model B",
> + DTB_DIR "bcm2711-rpi-4-b.dtb",
> + true,
> + },
> };
>
> static const struct rpi_model rpi_models_old_scheme[] = {
>
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Re: [U-Boot] [PATCH 13/16] dts: bcm2838-rpi-4-b: Use the emmc2 interface for sdhci
On 16/07/2019 15:38, and...@gherzan.ro wrote:
> From: Andrei Gherzan
>
> Signed-off-by: Andrei Gherzan
Commit message.
You fix a file that you introduced in this series. Any reason why you don't just
send the file already fixed?
> ---
> arch/arm/dts/bcm2838-rpi-4-b.dts | 16 ++--
> 1 file changed, 6 insertions(+), 10 deletions(-)
>
> diff --git a/arch/arm/dts/bcm2838-rpi-4-b.dts
> b/arch/arm/dts/bcm2838-rpi-4-b.dts
> index 07e9a78e8d..168179c17c 100644
> --- a/arch/arm/dts/bcm2838-rpi-4-b.dts
> +++ b/arch/arm/dts/bcm2838-rpi-4-b.dts
> @@ -30,21 +30,17 @@
> status = "okay";
> };
>
> -/* SDHCI is used to control the SDIO for wireless */
> {
> - pinctrl-names = "default";
> - pinctrl-0 = <_gpio34>;
> - status = "okay";
> - bus-width = <4>;
> - non-removable;
> + status = "disabled";
> };
>
> -/* SDHOST is used to drive the SD card */
> {
> - pinctrl-names = "default";
> - pinctrl-0 = <_gpio48>;
> + status = "disabled";
> +};
> +
> + {
> + compatible = "brcm,bcm2835-sdhci";
> status = "okay";
> - bus-width = <4>;
> };
>
> {
>
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Re: [U-Boot] [PATCH 12/16] config: rpi4: Add defconfig for rpi4-32
On 16/07/2019 15:37, and...@gherzan.ro wrote: > From: Andrei Gherzan > > Signed-off-by: Andrei Gherzan > --- > configs/rpi_4_32b_defconfig | 43 + > 1 file changed, 43 insertions(+) > create mode 100644 configs/rpi_4_32b_defconfig > > diff --git a/configs/rpi_4_32b_defconfig b/configs/rpi_4_32b_defconfig > new file mode 100644 > index 00..9f2b805d0f > --- /dev/null > +++ b/configs/rpi_4_32b_defconfig > @@ -0,0 +1,43 @@ > +CONFIG_ARM=y > +CONFIG_ARCH_BCM283X=y > +CONFIG_SYS_TEXT_BASE=0x8000 > +CONFIG_TARGET_RPI_4_32B=y > +CONFIG_SYS_MALLOC_F_LEN=0x2000 > +CONFIG_DISTRO_DEFAULTS=y > +CONFIG_NR_DRAM_BANKS=1 > +CONFIG_OF_BOARD_SETUP=y > +CONFIG_MISC_INIT_R=y > +# CONFIG_DISPLAY_CPUINFO is not set > +# CONFIG_DISPLAY_BOARDINFO is not set > +CONFIG_SYS_PROMPT="U-Boot> " > +# CONFIG_CMD_FLASH is not set > +CONFIG_CMD_GPIO=y > +CONFIG_CMD_MMC=y > +CONFIG_CMD_USB=y > +CONFIG_CMD_FS_UUID=y > +CONFIG_OF_EMBED=y > +CONFIG_DEFAULT_DEVICE_TREE="bcm2838-rpi-4-b" > +CONFIG_ENV_FAT_INTERFACE="mmc" > +CONFIG_ENV_FAT_DEVICE_AND_PART="0:1" > +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y > +CONFIG_DM_KEYBOARD=y > +CONFIG_DM_MMC=y > +CONFIG_MMC_SDHCI=y > +CONFIG_MMC_SDHCI_BCM2835=y > +CONFIG_PHYLIB=y > +CONFIG_DM_ETH=y > +CONFIG_PINCTRL=y > +# CONFIG_PINCTRL_GENERIC is not set > +# CONFIG_REQUIRE_SERIAL_CONSOLE is not set > +CONFIG_USB=y > +CONFIG_DM_USB=y > +CONFIG_USB_DWC2=y > +CONFIG_USB_KEYBOARD=y > +CONFIG_USB_HOST_ETHER=y > +CONFIG_USB_ETHER_LAN78XX=y > +CONFIG_USB_ETHER_SMSC95XX=y Network is connected via PCI, why do we need this options here? > +CONFIG_DM_VIDEO=y > +CONFIG_SYS_WHITE_ON_BLACK=y > +CONFIG_CONSOLE_SCROLL_LINES=10 > +CONFIG_PHYS_TO_BUS=y > +CONFIG_OF_LIBFDT_OVERLAY=y > ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 06/16] dt-bindings: Define BCM2838_CLOCK_EMMC2 needed for RaspberryPi 4
On 16/07/2019 15:37, and...@gherzan.ro wrote: > From: Andrei Gherzan > > On BCM2838 there is an additional clock. This clock was added in the > same bcm2835-cprman driver and is used by the emmc2 dt node. > > Signed-off-by: Andrei Gherzan > --- > include/dt-bindings/clock/bcm2835.h | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/include/dt-bindings/clock/bcm2835.h > b/include/dt-bindings/clock/bcm2835.h > index 2cec01f968..457fd4e23c 100644 > --- a/include/dt-bindings/clock/bcm2835.h > +++ b/include/dt-bindings/clock/bcm2835.h > @@ -58,3 +58,5 @@ > #define BCM2835_CLOCK_DSI1E 48 > #define BCM2835_CLOCK_DSI0P 49 > #define BCM2835_CLOCK_DSI1P 50 > + > +#define BCM2838_CLOCK_EMMC251 no new line please. ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 04/16] arm: mach-bcm283x: Define mbox address for BCM2838
On 16/07/2019 15:37, and...@gherzan.ro wrote:
> From: Andrei Gherzan
>
> Signed-off-by: Andrei Gherzan
> ---
> arch/arm/mach-bcm283x/include/mach/mbox.h | 5 +
> 1 file changed, 5 insertions(+)
>
> diff --git a/arch/arm/mach-bcm283x/include/mach/mbox.h
> b/arch/arm/mach-bcm283x/include/mach/mbox.h
> index e3a893e49c..2d711daaa8 100644
> --- a/arch/arm/mach-bcm283x/include/mach/mbox.h
> +++ b/arch/arm/mach-bcm283x/include/mach/mbox.h
> @@ -38,11 +38,16 @@
> /* Raw mailbox HW */
>
> #ifndef CONFIG_BCM2835
> +#ifdef CONFIG_BCM2838
> +#define BCM2835_MBOX_PHYSADDR0xfe00b880
> +#else
That gets really complicated. I prefer to add CONFIG_BCM283x_BASE or something
like that and then add the offset in the header files.
> #define BCM2835_MBOX_PHYSADDR0x3f00b880
> +#endif
> #else
> #define BCM2835_MBOX_PHYSADDR0x2000b880
> #endif
>
> +
> struct bcm2835_mbox_regs {
> u32 read;
> u32 rsvd0[5];
>
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Re: [U-Boot] [PATCH 02/16] dts: Add initial support for bcm2838
On 16/07/2019 15:37, and...@gherzan.ro wrote:
> From: Andrei Gherzan
>
> Signed-off-by: Andrei Gherzan
> ---
> arch/arm/dts/Makefile| 4 +-
> arch/arm/dts/bcm2838-rpi-4-b.dts | 56
> arch/arm/dts/bcm2838.dtsi| 237 +++
> 3 files changed, 296 insertions(+), 1 deletion(-)
> create mode 100644 arch/arm/dts/bcm2838-rpi-4-b.dts
> create mode 100644 arch/arm/dts/bcm2838.dtsi
>
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> index 20dbc2ff84..16790af1e1 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -749,7 +749,9 @@ dtb-$(CONFIG_ARCH_BCM283X) += \
> bcm2837-rpi-3-a-plus.dtb \
> bcm2837-rpi-3-b.dtb \
> bcm2837-rpi-3-b-plus.dtb \
> - bcm2837-rpi-cm3-io3.dtb
> + bcm2837-rpi-cm3-io3.dtb \
> + bcm2837-rpi-3-b.dtb \
You added rpi-3-b again, no need for that.
> + bcm2838-rpi-4-b.dtb
>
> dtb-$(CONFIG_ARCH_BCM63158) += \
> bcm963158.dtb
> diff --git a/arch/arm/dts/bcm2838-rpi-4-b.dts
> b/arch/arm/dts/bcm2838-rpi-4-b.dts
> new file mode 100644
> index 00..07e9a78e8d
> --- /dev/null
> +++ b/arch/arm/dts/bcm2838-rpi-4-b.dts
> @@ -0,0 +1,56 @@
> +/dts-v1/;
> +#include "bcm2838.dtsi"
> +
> +/ {
> + compatible = "raspberrypi,4-model-b","brcm,bcm2838","brcm,bcm2837";
> + model = "Raspberry Pi 4 Model B";
> +
> + memory {
> + reg = <0 0 0x4000>;
> + };
> +
> + leds {
> + act {
> + gpios = < 47 0>;
> + };
> + };
> +};
> +
> +/* uart0 communicates with the BT module */
> + {
> + pinctrl-names = "default";
> + pinctrl-0 = <_gpio32 _gpio43>;
> + status = "okay";
> +};
> +
> +/* uart1 is mapped to the pin header */
> + {
> + pinctrl-names = "default";
> + pinctrl-0 = <_pins>;
> + status = "okay";
> +};
> +
> +/* SDHCI is used to control the SDIO for wireless */
> + {
> + pinctrl-names = "default";
> + pinctrl-0 = <_gpio34>;
> + status = "okay";
> + bus-width = <4>;
> + non-removable;
> +};
> +
> +/* SDHOST is used to drive the SD card */
> + {
> + pinctrl-names = "default";
> + pinctrl-0 = <_gpio48>;
> + status = "okay";
> + bus-width = <4>;
> +};
> +
> + {
> + uart1_pins: uart1_pins {
>
>
> + brcm,pins;
>
>
> + brcm,function;
>
>
> + brcm,pull;
>
>
> + };
> +};
> diff --git a/arch/arm/dts/bcm2838.dtsi b/arch/arm/dts/bcm2838.dtsi
> new file mode 100644
> index 00..19b2d7b905
> --- /dev/null
> +++ b/arch/arm/dts/bcm2838.dtsi
> @@ -0,0 +1,237 @@
> +#include "bcm283x.dtsi"
> +#include
> +#include
> +
> +/ {
> + compatible = "brcm,bcm2838";
> +
> + #address-cells = <2>;
> + #size-cells = <1>;
> +
> + interrupt-parent = <>;
> +
> + soc {
> + ranges = <0x7e00 0x0 0xfe00 0x0180>,
> + <0x7c00 0x0 0xfc00 0x0200>,
> + <0x4000 0x0 0xff80 0x0080>;
> + dma-ranges = <0xc000 0x0 0x 0x3c00>;
> +
> + gic: gic400@40041000 {
> + interrupt-controller;
> + #interrupt-cells = <3>;
> + compatible = "arm,gic-400";
> + reg = <0x40041000 0x1000>,
> + <0x40042000 0x2000>,
> + <0x40044000 0x2000>,
> + <0x40046000 0x2000>;
> + };
> +
> + thermal: thermal@7d5d2200 {
> + compatible = "brcm,avs-tmon-bcm2838";
> + reg = <0x7d5d2200 0x2c>;
> + interrupts = ;
> + interrupt-names = "tmon";
> + clocks = < BCM2835_CLOCK_TSENS>;
> + #thermal-sensor-cells = <0>;
> + status = "okay";
> + };
> +
> + spi@7e204000 {
> +reg = <0x7e204000 0x0200>;
>
> +interrupts = ;
> +};
> +
> +pixelvalve@7e206000 {
> +
Re: [U-Boot] [PATCH 01/16] dts: Create a dtsi for BCM2835/6/7 specific configuration
On 16/07/2019 15:37, and...@gherzan.ro wrote:
> From: Andrei Gherzan
>
> This follows a similar change in kernel[1]. The change moves
> configuration that was not applicable for all bcm2835/6/7/8 out of
> bcm283x.dtsi. The new file is bcm2835-common.dtsi and contains
> conifguration that is common for bcm2835/6/7 (not bcm2838).
>
> [1]
> https://github.com/raspberrypi/linux/commit/769a7330aa5bebcc98b1ff12ecb767db4e5c644d#diff-5979fba23a5bab2cf66dde09db872dfc
>
> Signed-off-by: Andrei Gherzan
My opinion is that we should wait for official dts instead of using some
work-in-progress ones. So my opinion is to use the DTB from the FW for now until
we have something stable.
> ---
> arch/arm/dts/bcm2835-common.dtsi | 53
> arch/arm/dts/bcm2835.dtsi| 1 +
> arch/arm/dts/bcm2836.dtsi| 1 +
> arch/arm/dts/bcm2837.dtsi| 1 +
> arch/arm/dts/bcm283x.dtsi| 45 +--
> 5 files changed, 57 insertions(+), 44 deletions(-)
> create mode 100644 arch/arm/dts/bcm2835-common.dtsi
>
> diff --git a/arch/arm/dts/bcm2835-common.dtsi
> b/arch/arm/dts/bcm2835-common.dtsi
> new file mode 100644
> index 00..17771730a3
> --- /dev/null
> +++ b/arch/arm/dts/bcm2835-common.dtsi
> @@ -0,0 +1,53 @@
> +// SPDX-License-Identifier: GPL-2.0
> +
> +/* This include file covers the common peripherals and configuration between
> + * bcm2835, bcm2836 and bcm2837 implementations.
> + */
> +
> +/ {
> + soc {
> + timer@7e003000 {
> + compatible = "brcm,bcm2835-system-timer";
> + reg = <0x7e003000 0x1000>;
> + interrupts = <1 0>, <1 1>, <1 2>, <1 3>;
> + /* This could be a reference to BCM2835_CLOCK_TIMER,
> + * but we don't have the driver using the common clock
> + * support yet.
> + */
> + clock-frequency = <100>;
> + };
> +
> + intc: interrupt-controller@7e00b200 {
> + compatible = "brcm,bcm2835-armctrl-ic";
> + reg = <0x7e00b200 0x200>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + thermal: thermal@7e212000 {
> + compatible = "brcm,bcm2835-thermal";
> + reg = <0x7e212000 0x8>;
> + clocks = < BCM2835_CLOCK_TSENS>;
> + #thermal-sensor-cells = <0>;
> + status = "disabled";
> + };
> +
> + v3d: v3d@7ec0 {
> + compatible = "brcm,bcm2835-v3d";
> + reg = <0x7ec0 0x1000>;
> + interrupts = <1 10>;
> + };
> + };
> +};
> +
> + {
> + i2c_slave_gpio18: i2c_slave_gpio18 {
> + brcm,pins = <18 19 20 21>;
> + brcm,function = ;
> + };
> +
> + jtag_gpio4: jtag_gpio4 {
> + brcm,pins = <4 5 6 12 13>;
> + brcm,function = ;
> + };
> +};
> diff --git a/arch/arm/dts/bcm2835.dtsi b/arch/arm/dts/bcm2835.dtsi
> index a5c3824c80..53bf4579cc 100644
> --- a/arch/arm/dts/bcm2835.dtsi
> +++ b/arch/arm/dts/bcm2835.dtsi
> @@ -1,5 +1,6 @@
> // SPDX-License-Identifier: GPL-2.0
> #include "bcm283x.dtsi"
> +#include "bcm2835-common.dtsi"
>
> / {
> compatible = "brcm,bcm2835";
> diff --git a/arch/arm/dts/bcm2836.dtsi b/arch/arm/dts/bcm2836.dtsi
> index c933e84138..82d6c4662a 100644
> --- a/arch/arm/dts/bcm2836.dtsi
> +++ b/arch/arm/dts/bcm2836.dtsi
> @@ -1,5 +1,6 @@
> // SPDX-License-Identifier: GPL-2.0
> #include "bcm283x.dtsi"
> +#include "bcm2835-common.dtsi"
>
> / {
> compatible = "brcm,bcm2836";
> diff --git a/arch/arm/dts/bcm2837.dtsi b/arch/arm/dts/bcm2837.dtsi
> index beb6c502da..9e95fee78e 100644
> --- a/arch/arm/dts/bcm2837.dtsi
> +++ b/arch/arm/dts/bcm2837.dtsi
> @@ -1,4 +1,5 @@
> #include "bcm283x.dtsi"
> +#include "bcm2835-common.dtsi"
>
> / {
> compatible = "brcm,bcm2837";
> diff --git a/arch/arm/dts/bcm283x.dtsi b/arch/arm/dts/bcm283x.dtsi
> index 9777644c6c..a024727e4d 100644
> --- a/arch/arm/dts/bcm283x.dtsi
> +++ b/arch/arm/dts/bcm283x.dtsi
> @@ -56,17 +56,6 @@
> #address-cells = <1>;
> #size-cells = <1>;
>
> - timer@7e003000 {
> - compatible = "brcm,bcm2835-system-timer";
> - reg = <0x7e003000 0x1000>;
> - interrupts = <1 0>, <1 1>, <1 2>, <1 3>;
> - /* This could be a reference to BCM2835_CLOCK_TIMER,
> - * but we don't have the driver using the common clock
> - * support yet.
> - */
> - clock-frequency = <100>;
> - };
> -
> txp@7e004000 {
> compatible = "brcm,bcm2835-txp";
>
