[U-Boot] [PATCH] arm: baltos: switch to driver model for the watchdog timer
From: Yegor Yefremov Also disable OMAP watchdog timer till it is converted to the driver model. Signed-off-by: Yegor Yefremov --- configs/am335x_baltos_defconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/configs/am335x_baltos_defconfig b/configs/am335x_baltos_defconfig index aa8fee5125..6f1395925a 100644 --- a/configs/am335x_baltos_defconfig +++ b/configs/am335x_baltos_defconfig @@ -69,4 +69,7 @@ CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_USB_FUNCTION_MASS_STORAGE=y CONFIG_USB_ETHER=y CONFIG_USBNET_HOST_ADDR="de:ad:be:af:00:00" +# CONFIG_WATCHDOG is not set +# CONFIG_OMAP_WATCHDOG is not set +CONFIG_WDT=y CONFIG_FAT_WRITE=y -- 2.17.0 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH] arm: baltos: use device tree alias to access Ethernet slave
From: Yegor Yefremov
The full path has changed in the recent kernels so that it is
not possible to load them. Aliases "ethernet0" and "ethernet1"
are still present in both legacy and new kernels.
Also, fix error messages to correspond to the taken actions.
Signed-off-by: Yegor Yefremov
---
board/vscom/baltos/board.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/board/vscom/baltos/board.c b/board/vscom/baltos/board.c
index c5949ad267..036a356578 100644
--- a/board/vscom/baltos/board.c
+++ b/board/vscom/baltos/board.c
@@ -288,15 +288,15 @@ int ft_board_setup(void *blob, bd_t *bd)
mac_addr[5] = header.MAC1[5];
- node = fdt_path_offset(blob, "/ocp/ethernet/slave@4a100200");
+ node = fdt_path_offset(blob, "ethernet0");
if (node < 0) {
- printf("no /soc/fman/ethernet path offset\n");
+ printf("no ethernet0 path offset\n");
return -ENODEV;
}
ret = fdt_setprop(blob, node, "mac-address", _addr, 6);
if (ret) {
- printf("error setting local-mac-address property\n");
+ printf("error setting mac-address property\n");
return -ENODEV;
}
@@ -308,15 +308,15 @@ int ft_board_setup(void *blob, bd_t *bd)
mac_addr[4] = header.MAC2[4];
mac_addr[5] = header.MAC2[5];
- node = fdt_path_offset(blob, "/ocp/ethernet/slave@4a100300");
+ node = fdt_path_offset(blob, "ethernet1");
if (node < 0) {
- printf("no /soc/fman/ethernet path offset\n");
+ printf("no ethernet1 path offset\n");
return -ENODEV;
}
ret = fdt_setprop(blob, node, "mac-address", _addr, 6);
if (ret) {
- printf("error setting local-mac-address property\n");
+ printf("error setting mac-address property\n");
return -ENODEV;
}
--
2.17.0
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 18/22] imx8m: restructure clock.h
i.MX8MQ and i.MX8MM use different analog pll design, but they
share same ccm design.
Add clock_imx8mq.h for i.MX8MQ
keep common part in clock.h
Signed-off-by: Peng Fan
---
arch/arm/include/asm/arch-imx8m/clock.h| 491 +++--
arch/arm/include/asm/arch-imx8m/clock_imx8mq.h | 424 +
arch/arm/mach-imx/imx8m/clock_imx8mq.c | 5 +-
3 files changed, 467 insertions(+), 453 deletions(-)
create mode 100644 arch/arm/include/asm/arch-imx8m/clock_imx8mq.h
diff --git a/arch/arm/include/asm/arch-imx8m/clock.h
b/arch/arm/include/asm/arch-imx8m/clock.h
index e7c1670f6b..7225c760fe 100644
--- a/arch/arm/include/asm/arch-imx8m/clock.h
+++ b/arch/arm/include/asm/arch-imx8m/clock.h
@@ -1,28 +1,29 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
- * Copyright 2017 NXP
- *
- * Peng Fan
+ * Copyright 2017-2019 NXP
*/
-#ifndef _ASM_ARCH_IMX8M_CLOCK_H
-#define _ASM_ARCH_IMX8M_CLOCK_H
-
#include
+#ifdef CONFIG_IMX8MQ
+#include
+#else
+#error "Error no clock.h"
+#endif
+
#define MHZ(X) ((X) * 100UL)
-enum pll_clocks {
- ANATOP_ARM_PLL,
- ANATOP_GPU_PLL,
- ANATOP_SYSTEM_PLL1,
- ANATOP_SYSTEM_PLL2,
- ANATOP_SYSTEM_PLL3,
- ANATOP_AUDIO_PLL1,
- ANATOP_AUDIO_PLL2,
- ANATOP_VIDEO_PLL1,
- ANATOP_VIDEO_PLL2,
- ANATOP_DRAM_PLL,
+/* Mainly for compatible to imx common code. */
+enum mxc_clock {
+ MXC_ARM_CLK = 0,
+ MXC_IPG_CLK,
+ MXC_CSPI_CLK,
+ MXC_ESDHC_CLK,
+ MXC_ESDHC2_CLK,
+ MXC_ESDHC3_CLK,
+ MXC_I2C_CLK,
+ MXC_UART_CLK,
+ MXC_QSPI_CLK,
};
enum clk_slice_type {
@@ -35,297 +36,6 @@ enum clk_slice_type {
DRAM_SEL_CLOCK_SLICE,
};
-enum clk_root_index {
- MXC_ARM_CLK = 0,
- ARM_A53_CLK_ROOT= 0,
- ARM_M4_CLK_ROOT = 1,
- VPU_A53_CLK_ROOT= 2,
- GPU_CORE_CLK_ROOT = 3,
- GPU_SHADER_CLK_ROOT = 4,
- MAIN_AXI_CLK_ROOT = 16,
- ENET_AXI_CLK_ROOT = 17,
- NAND_USDHC_BUS_CLK_ROOT = 18,
- VPU_BUS_CLK_ROOT= 19,
- DISPLAY_AXI_CLK_ROOT= 20,
- DISPLAY_APB_CLK_ROOT= 21,
- DISPLAY_RTRM_CLK_ROOT = 22,
- USB_BUS_CLK_ROOT= 23,
- GPU_AXI_CLK_ROOT= 24,
- GPU_AHB_CLK_ROOT= 25,
- NOC_CLK_ROOT= 26,
- NOC_APB_CLK_ROOT= 27,
- AHB_CLK_ROOT= 32,
- IPG_CLK_ROOT= 33,
- MXC_IPG_CLK = 33,
- AUDIO_AHB_CLK_ROOT = 34,
- MIPI_DSI_ESC_RX_CLK_ROOT= 36,
- DRAM_SEL_CFG= 48,
- CORE_SEL_CFG= 49,
- DRAM_ALT_CLK_ROOT = 64,
- DRAM_APB_CLK_ROOT = 65,
- VPU_G1_CLK_ROOT = 66,
- VPU_G2_CLK_ROOT = 67,
- DISPLAY_DTRC_CLK_ROOT = 68,
- DISPLAY_DC8000_CLK_ROOT = 69,
- PCIE1_CTRL_CLK_ROOT = 70,
- PCIE1_PHY_CLK_ROOT = 71,
- PCIE1_AUX_CLK_ROOT = 72,
- DC_PIXEL_CLK_ROOT = 73,
- LCDIF_PIXEL_CLK_ROOT= 74,
- SAI1_CLK_ROOT = 75,
- SAI2_CLK_ROOT = 76,
- SAI3_CLK_ROOT = 77,
- SAI4_CLK_ROOT = 78,
- SAI5_CLK_ROOT = 79,
- SAI6_CLK_ROOT = 80,
- SPDIF1_CLK_ROOT = 81,
- SPDIF2_CLK_ROOT = 82,
- ENET_REF_CLK_ROOT = 83,
- ENET_TIMER_CLK_ROOT = 84,
- ENET_PHY_REF_CLK_ROOT = 85,
- NAND_CLK_ROOT = 86,
- QSPI_CLK_ROOT = 87,
- MXC_ESDHC_CLK = 88,
- USDHC1_CLK_ROOT = 88,
- MXC_ESDHC2_CLK = 89,
- USDHC2_CLK_ROOT = 89,
- I2C1_CLK_ROOT = 90,
- MXC_I2C_CLK = 90,
- I2C2_CLK_ROOT = 91,
- I2C3_CLK_ROOT = 92,
- I2C4_CLK_ROOT = 93,
- UART1_CLK_ROOT = 94,
- UART2_CLK_ROOT = 95,
- UART3_CLK_ROOT = 96,
- UART4_CLK_ROOT = 97,
- USB_CORE_REF_CLK_ROOT = 98,
- USB_PHY_REF_CLK_ROOT= 99,
- GIC_CLK_ROOT= 100,
- ECSPI1_CLK_ROOT = 101,
- ECSPI2_CLK_ROOT = 102,
- PWM1_CLK_ROOT = 103,
- PWM2_CLK_ROOT = 104,
- PWM3_CLK_ROOT = 105,
- PWM4_CLK_ROOT
[U-Boot] [PATCH 22/22] imx: Add i.MX8MM EVK board support.
Add board and SoC dts
Add ddr training code
support SD/MMC/GPIO/PINCTRL/UART
Signed-off-by: Peng Fan
---
arch/arm/dts/Makefile |3 +-
arch/arm/dts/imx8mm-evk-u-boot.dtsi| 92 ++
arch/arm/dts/imx8mm-evk.dts| 235
arch/arm/mach-imx/imx8m/Kconfig|7 +
board/freescale/imx8mm_evk/Kconfig | 12 +
board/freescale/imx8mm_evk/MAINTAINERS |6 +
board/freescale/imx8mm_evk/Makefile| 12 +
board/freescale/imx8mm_evk/imx8mm_evk.c| 90 ++
board/freescale/imx8mm_evk/lpddr4_timing.c | 1980
board/freescale/imx8mm_evk/spl.c | 102 ++
configs/imx8mm_evk_defconfig | 70 +
include/configs/imx8mm_evk.h | 164 +++
12 files changed, 2772 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/dts/imx8mm-evk-u-boot.dtsi
create mode 100644 arch/arm/dts/imx8mm-evk.dts
create mode 100644 board/freescale/imx8mm_evk/Kconfig
create mode 100644 board/freescale/imx8mm_evk/MAINTAINERS
create mode 100644 board/freescale/imx8mm_evk/Makefile
create mode 100644 board/freescale/imx8mm_evk/imx8mm_evk.c
create mode 100644 board/freescale/imx8mm_evk/lpddr4_timing.c
create mode 100644 board/freescale/imx8mm_evk/spl.c
create mode 100644 configs/imx8mm_evk_defconfig
create mode 100644 include/configs/imx8mm_evk.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index ad4d2357bb..f7b674873f 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -622,7 +622,8 @@ dtb-$(CONFIG_ARCH_IMX8) += \
fsl-imx8qxp-colibri.dtb \
fsl-imx8qxp-mek.dtb
-dtb-$(CONFIG_ARCH_IMX8M) += fsl-imx8mq-evk.dtb
+dtb-$(CONFIG_ARCH_IMX8M) += fsl-imx8mq-evk.dtb \
+ imx8mm-evk.dtb
dtb-$(CONFIG_RCAR_GEN2) += \
r8a7790-lager-u-boot.dtb \
diff --git a/arch/arm/dts/imx8mm-evk-u-boot.dtsi
b/arch/arm/dts/imx8mm-evk-u-boot.dtsi
new file mode 100644
index 00..1095d36e31
--- /dev/null
+++ b/arch/arm/dts/imx8mm-evk-u-boot.dtsi
@@ -0,0 +1,92 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ */
+
+&{/soc} {
+ u-boot,dm-pre-reloc;
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+ u-boot,dm-pre-reloc;
+};
+
+_24m {
+ u-boot,dm-spl;
+ u-boot,dm-pre-reloc;
+};
+
+ {
+ u-boot,dm-spl;
+ u-boot,dm-pre-reloc;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+_reg_usdhc2_vmmc {
+ u-boot,dm-spl;
+};
+
+_uart2 {
+ u-boot,dm-spl;
+};
+
+_usdhc2_gpio {
+ u-boot,dm-spl;
+};
+
+_usdhc2 {
+ u-boot,dm-spl;
+};
+
+_usdhc3 {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
diff --git a/arch/arm/dts/imx8mm-evk.dts b/arch/arm/dts/imx8mm-evk.dts
new file mode 100644
index 00..2d5d89475b
--- /dev/null
+++ b/arch/arm/dts/imx8mm-evk.dts
@@ -0,0 +1,235 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2019 NXP
+ */
+
+/dts-v1/;
+
+#include "imx8mm.dtsi"
+
+/ {
+ model = "FSL i.MX8MM EVK board";
+ compatible = "fsl,imx8mm-evk", "fsl,imx8mm";
+
+ chosen {
+ stdout-path =
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <_gpio_led>;
+
+ status {
+ label = "status";
+ gpios = < 16 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ };
+ };
+
+ reg_usdhc2_vmmc: regulator-usdhc2 {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <_reg_usdhc2_vmmc>;
+ regulator-name = "VSD_3V3";
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ gpio = < 19 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+};
+
+ {
+ pinctrl-names = "default";
+ pinctrl-0 = <_fec1>;
+ phy-mode = "rgmii-id";
+ phy-handle = <>;
+ fsl,magic-packet;
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy0: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0>;
+ at803x,led-act-blind-workaround;
+ at803x,eee-okay;
+ at803x,vddio-1p8v;
+ };
+ };
+};
+
+ { /* console */
+ pinctrl-names = "default";
+ pinctrl-0 = <_uart2>;
+ status = "okay";
+};
+
+ {
+ pinctrl-names = "default", "state_100mhz",
[U-Boot] [PATCH 17/22] imx8m: rename clock to clock_imx8mq
i.MX8MQ and i.MX8MM has totally different pll design, so
rename clock to clock_imx8mq.
Signed-off-by: Peng Fan
---
arch/arm/mach-imx/imx8m/Makefile| 3 ++-
arch/arm/mach-imx/imx8m/{clock.c => clock_imx8mq.c} | 0
2 files changed, 2 insertions(+), 1 deletion(-)
rename arch/arm/mach-imx/imx8m/{clock.c => clock_imx8mq.c} (100%)
diff --git a/arch/arm/mach-imx/imx8m/Makefile b/arch/arm/mach-imx/imx8m/Makefile
index feff4941c1..42a1544c6b 100644
--- a/arch/arm/mach-imx/imx8m/Makefile
+++ b/arch/arm/mach-imx/imx8m/Makefile
@@ -3,4 +3,5 @@
# Copyright 2017 NXP
obj-y += lowlevel_init.o
-obj-y += clock.o clock_slice.o soc.o
+obj-y += clock_slice.o soc.o
+obj-$(CONFIG_IMX8MQ) += clock_imx8mq.o
diff --git a/arch/arm/mach-imx/imx8m/clock.c
b/arch/arm/mach-imx/imx8m/clock_imx8mq.c
similarity index 100%
rename from arch/arm/mach-imx/imx8m/clock.c
rename to arch/arm/mach-imx/imx8m/clock_imx8mq.c
--
2.16.4
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 13/22] imx8m: Fix MMU table issue for OPTEE memory
When running with OPTEE, the MMU table in u-boot does not remove the OPTEE
memory from its settings. So ARM speculative prefetch in u-boot may access
that OPTEE memory. Due to trust zone is enabled by OPTEE and that memory
is set to secure access, then the speculative prefetch will fail and cause
various memory issue in u-boot.
The fail address register and int_status register in trustzone has logged
that speculative access from u-boot.
Signed-off-by: Peng Fan
---
arch/arm/mach-imx/imx8m/soc.c | 20 ++--
1 file changed, 18 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c
index 5115471eff..dd393b581b 100644
--- a/arch/arm/mach-imx/imx8m/soc.c
+++ b/arch/arm/mach-imx/imx8m/soc.c
@@ -112,16 +112,18 @@ static struct mm_region imx8m_mem_map[] = {
/* DRAM1 */
.virt = 0x4000UL,
.phys = 0x4000UL,
- .size = 0xC000UL,
+ .size = PHYS_SDRAM_SIZE,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_OUTER_SHARE
+#ifdef PHYS_SDRAM_2_SIZE
}, {
/* DRAM2 */
.virt = 0x1UL,
.phys = 0x1UL,
- .size = 0x04000UL,
+ .size = PHYS_SDRAM_2_SIZE,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_OUTER_SHARE
+#endif
}, {
/* List terminator */
0,
@@ -130,6 +132,20 @@ static struct mm_region imx8m_mem_map[] = {
struct mm_region *mem_map = imx8m_mem_map;
+void enable_caches(void)
+{
+ /*
+* If OPTEE runs, remove OPTEE memory from MMU table to
+* avoid speculative prefetch. OPTEE runs at the top of
+* the first memory bank
+*/
+ if (rom_pointer[1])
+ imx8m_mem_map[5].size -= rom_pointer[1];
+
+ icache_enable();
+ dcache_enable();
+}
+
static u32 get_cpu_variant_type(u32 type)
{
struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
--
2.16.4
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 15/22] imx8m: Configure trustzone region 0 for non-secure access
From: Ye Li Set trustzone region 0 to allow both non-secure and secure access when trust zone is enabled. We found USB controller fails to access DDR if the default region 0 is secure access only. Signed-off-by: Ye Li Signed-off-by: Peng Fan --- arch/arm/mach-imx/imx8m/soc.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c index 261f586fc0..a33ca35653 100644 --- a/arch/arm/mach-imx/imx8m/soc.c +++ b/arch/arm/mach-imx/imx8m/soc.c @@ -57,6 +57,12 @@ void enable_tzc380(void) setbits_le32(>gpr[10], GPR_TZASC_EN_LOCK); if (IS_ENABLED(CONFIG_IMX8MM)) setbits_le32(>gpr[10], BIT(1)); + /* +* set Region 0 attribute to allow secure and non-secure +* read/write permission. Found some masters like usb dwc3 +* controllers can't work with secure memory. +*/ + writel(0xf000, TZASC_BASE_ADDR + 0x108); } void set_wdog_reset(struct wdog_regs *wdog) -- 2.16.4 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 11/22] imx8m: add pin header for i.MX8MM
Add pin header file for i.MX8MM
To IMX8MM_PAD_NAND_WE_B_USDHC3_CLK, IOMUX_CONFIG_SION needs to be
selected.
Signed-off-by: Peng Fan
---
arch/arm/include/asm/arch-imx8m/imx8mm_pins.h | 691 ++
1 file changed, 691 insertions(+)
create mode 100644 arch/arm/include/asm/arch-imx8m/imx8mm_pins.h
diff --git a/arch/arm/include/asm/arch-imx8m/imx8mm_pins.h
b/arch/arm/include/asm/arch-imx8m/imx8mm_pins.h
new file mode 100644
index 00..210e96e1db
--- /dev/null
+++ b/arch/arm/include/asm/arch-imx8m/imx8mm_pins.h
@@ -0,0 +1,691 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2018-2019 NXP
+ */
+
+#ifndef __ASM_ARCH_IMX8MM_PINS_H__
+#define __ASM_ARCH_IMX8MM_PINS_H__
+
+#include
+
+enum {
+ IMX8MM_PAD_GPIO1_IO00_GPIO1_IO0 =
IOMUX_PAD(0x0290, 0x0028, 0, 0x, 0, 0),
+ IMX8MM_PAD_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT =
IOMUX_PAD(0x0290, 0x0028, 1, 0x, 0, 0),
+ IMX8MM_PAD_GPIO1_IO00_XTALOSC_REF_CLK_32K =
IOMUX_PAD(0x0290, 0x0028, 5, 0x, 0, 0),
+ IMX8MM_PAD_GPIO1_IO00_CCM_EXT_CLK1=
IOMUX_PAD(0x0290, 0x0028, 6, 0x, 0, 0),
+
+ IMX8MM_PAD_GPIO1_IO01_GPIO1_IO1 =
IOMUX_PAD(0x0294, 0x002C, 0, 0x, 0, 0),
+ IMX8MM_PAD_GPIO1_IO01_PWM1_OUT=
IOMUX_PAD(0x0294, 0x002C, 1, 0x, 0, 0),
+ IMX8MM_PAD_GPIO1_IO01_XTALOSC_REF_CLK_24M =
IOMUX_PAD(0x0294, 0x002C, 5, 0x, 0, 0),
+ IMX8MM_PAD_GPIO1_IO01_CCM_EXT_CLK2=
IOMUX_PAD(0x0294, 0x002C, 6, 0x, 0, 0),
+
+ IMX8MM_PAD_GPIO1_IO02_GPIO1_IO2 =
IOMUX_PAD(0x0298, 0x0030, 0, 0x, 0, 0),
+ IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B=
IOMUX_PAD(0x0298, 0x0030, 1, 0x, 0, 0),
+ IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_ANY =
IOMUX_PAD(0x0298, 0x0030, 5, 0x, 0, 0),
+
+ IMX8MM_PAD_GPIO1_IO03_GPIO1_IO3 =
IOMUX_PAD(0x029C, 0x0034, 0, 0x, 0, 0),
+ IMX8MM_PAD_GPIO1_IO03_USDHC1_VSELECT =
IOMUX_PAD(0x029C, 0x0034, 1, 0x, 0, 0),
+ IMX8MM_PAD_GPIO1_IO03_SDMA1_EXT_EVENT0=
IOMUX_PAD(0x029C, 0x0034, 5, 0x, 0, 0),
+
+ IMX8MM_PAD_GPIO1_IO04_GPIO1_IO4 =
IOMUX_PAD(0x02A0, 0x0038, 0, 0x, 0, 0),
+ IMX8MM_PAD_GPIO1_IO04_USDHC2_VSELECT =
IOMUX_PAD(0x02A0, 0x0038, 1, 0x, 0, 0),
+ IMX8MM_PAD_GPIO1_IO04_SDMA1_EXT_EVENT1=
IOMUX_PAD(0x02A0, 0x0038, 5, 0x, 0, 0),
+
+ IMX8MM_PAD_GPIO1_IO05_GPIO1_IO5 =
IOMUX_PAD(0x02A4, 0x003C, 0, 0x, 0, 0),
+ IMX8MM_PAD_GPIO1_IO05_ARM_PLATFORM_M4_NMI =
IOMUX_PAD(0x02A4, 0x003C, 1, 0x, 0, 0),
+ IMX8MM_PAD_GPIO1_IO05_CCM_PMIC_READY =
IOMUX_PAD(0x02A4, 0x003C, 5, 0x04BC, 0, 0),
+ IMX8MM_PAD_GPIO1_IO05_SRC_INT_BOOT=
IOMUX_PAD(0x02A4, 0x003C, 6, 0x, 0, 0),
+
+ IMX8MM_PAD_GPIO1_IO06_GPIO1_IO6 =
IOMUX_PAD(0x02A8, 0x0040, 0, 0x, 0, 0),
+ IMX8MM_PAD_GPIO1_IO06_ENET1_MDC =
IOMUX_PAD(0x02A8, 0x0040, 1, 0x, 0, 0),
+ IMX8MM_PAD_GPIO1_IO06_USDHC1_CD_B =
IOMUX_PAD(0x02A8, 0x0040, 5, 0x, 0, 0),
+ IMX8MM_PAD_GPIO1_IO06_CCM_EXT_CLK3=
IOMUX_PAD(0x02A8, 0x0040, 6, 0x, 0, 0),
+
+ IMX8MM_PAD_GPIO1_IO07_GPIO1_IO7 =
IOMUX_PAD(0x02AC, 0x0044, 0, 0x, 0, 0),
+ IMX8MM_PAD_GPIO1_IO07_ENET1_MDIO =
IOMUX_PAD(0x02AC, 0x0044, 1, 0x04C0, 0, 0),
+ IMX8MM_PAD_GPIO1_IO07_USDHC1_WP =
IOMUX_PAD(0x02AC, 0x0044, 5, 0x, 0, 0),
+ IMX8MM_PAD_GPIO1_IO07_CCM_EXT_CLK4=
IOMUX_PAD(0x02AC, 0x0044, 6, 0x, 0, 0),
+
+ IMX8MM_PAD_GPIO1_IO08_GPIO1_IO8 =
IOMUX_PAD(0x02B0, 0x0048, 0, 0x, 0, 0),
+ IMX8MM_PAD_GPIO1_IO08_ENET1_1588_EVENT0_IN=
IOMUX_PAD(0x02B0, 0x0048, 1, 0x, 0, 0),
+ IMX8MM_PAD_GPIO1_IO08_USDHC2_RESET_B =
IOMUX_PAD(0x02B0, 0x0048, 5, 0x, 0, 0),
+ IMX8MM_PAD_GPIO1_IO08_CCM_WAIT=
IOMUX_PAD(0x02B0, 0x0048, 6, 0x, 0, 0),
+
+ IMX8MM_PAD_GPIO1_IO09_GPIO1_IO9 =
IOMUX_PAD(0x02B4, 0x004C, 0, 0x, 0, 0),
+ IMX8MM_PAD_GPIO1_IO09_ENET1_1588_EVENT0_OUT =
IOMUX_PAD(0x02B4, 0x004C, 1, 0x, 0, 0),
+ IMX8MM_PAD_GPIO1_IO09_USDHC3_RESET_B =
IOMUX_PAD(0x02B4, 0x004C, 4, 0x,
[U-Boot] [PATCH 14/22] imx8m: set BYPASS ID SWAP to avoid AXI bus errors
set the BYPASS ID SWAP bit (GPR10 bit 1) in order for GPU not to generated AXI bus errors with TZC380 enabled. Signed-off-by: Peng Fan --- arch/arm/mach-imx/imx8m/soc.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c index dd393b581b..261f586fc0 100644 --- a/arch/arm/mach-imx/imx8m/soc.c +++ b/arch/arm/mach-imx/imx8m/soc.c @@ -55,6 +55,8 @@ void enable_tzc380(void) /* Enable TZASC and lock setting */ setbits_le32(>gpr[10], GPR_TZASC_EN); setbits_le32(>gpr[10], GPR_TZASC_EN_LOCK); + if (IS_ENABLED(CONFIG_IMX8MM)) + setbits_le32(>gpr[10], BIT(1)); } void set_wdog_reset(struct wdog_regs *wdog) -- 2.16.4 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 12/22] imx: add i.MX8MM PE property
i.MX8MM does not have LVTTL, it has a PE property Signed-off-by: Peng Fan --- arch/arm/include/asm/mach-imx/iomux-v3.h | 4 1 file changed, 4 insertions(+) diff --git a/arch/arm/include/asm/mach-imx/iomux-v3.h b/arch/arm/include/asm/mach-imx/iomux-v3.h index b899a4ff6f..720e8f7043 100644 --- a/arch/arm/include/asm/mach-imx/iomux-v3.h +++ b/arch/arm/include/asm/mach-imx/iomux-v3.h @@ -104,7 +104,11 @@ typedef u64 iomux_v3_cfg_t; #define PAD_CTL_ODE(0x1 << 5) #define PAD_CTL_PUE(0x1 << 6) #define PAD_CTL_HYS(0x1 << 7) +#ifdef CONFIG_IMX8MM +#define PAD_CTL_PE (0x1 << 8) +#else #define PAD_CTL_LVTTL (0x1 << 8) +#endif #elif defined CONFIG_MX7 -- 2.16.4 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 19/22] imx8m: add clk support for i.MX8MM
Introduce clk implementation for i.MX8MM, including pll configuration,
ccm configuration. Mostly will be done clk dm driver,
but such as DRAM part, we still use non clk dm driver, because we
have limited sram.
Signed-off-by: Peng Fan
---
arch/arm/include/asm/arch-imx8m/clock.h| 2 +
arch/arm/include/asm/arch-imx8m/clock_imx8mm.h | 387 +
arch/arm/mach-imx/imx8m/Makefile | 1 +
arch/arm/mach-imx/imx8m/clock_imx8mm.c | 306 +++
arch/arm/mach-imx/imx8m/clock_slice.c | 63
5 files changed, 759 insertions(+)
create mode 100644 arch/arm/include/asm/arch-imx8m/clock_imx8mm.h
create mode 100644 arch/arm/mach-imx/imx8m/clock_imx8mm.c
diff --git a/arch/arm/include/asm/arch-imx8m/clock.h
b/arch/arm/include/asm/arch-imx8m/clock.h
index 7225c760fe..ead4b8d3dc 100644
--- a/arch/arm/include/asm/arch-imx8m/clock.h
+++ b/arch/arm/include/asm/arch-imx8m/clock.h
@@ -7,6 +7,8 @@
#ifdef CONFIG_IMX8MQ
#include
+#elif defined(CONFIG_IMX8MM)
+#include
#else
#error "Error no clock.h"
#endif
diff --git a/arch/arm/include/asm/arch-imx8m/clock_imx8mm.h
b/arch/arm/include/asm/arch-imx8m/clock_imx8mm.h
new file mode 100644
index 00..305514a4ec
--- /dev/null
+++ b/arch/arm/include/asm/arch-imx8m/clock_imx8mm.h
@@ -0,0 +1,387 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2018-2019 NXP
+ *
+ * Peng Fan
+ */
+
+#ifndef _ASM_ARCH_IMX8MM_CLOCK_H
+#define _ASM_ARCH_IMX8MM_CLOCK_H
+
+#define PLL_1443X_RATE(_rate, _m, _p, _s, _k) \
+ { \
+ .rate = (_rate),\
+ .mdiv = (_m), \
+ .pdiv = (_p), \
+ .sdiv = (_s), \
+ .kdiv = (_k), \
+ }
+
+#define LOCK_STATUSBIT(31)
+#define LOCK_SEL_MASK BIT(29)
+#define CLKE_MASK BIT(11)
+#define RST_MASK BIT(9)
+#define BYPASS_MASKBIT(4)
+#defineMDIV_SHIFT 12
+#defineMDIV_MASK GENMASK(21, 12)
+#define PDIV_SHIFT 4
+#define PDIV_MASK GENMASK(9, 4)
+#define SDIV_SHIFT 0
+#define SDIV_MASK GENMASK(2, 0)
+#define KDIV_SHIFT 0
+#define KDIV_MASK GENMASK(15, 0)
+
+struct imx_int_pll_rate_table {
+ u32 rate;
+ int mdiv;
+ int pdiv;
+ int sdiv;
+ int kdiv;
+};
+
+enum pll_clocks {
+ ANATOP_ARM_PLL,
+ ANATOP_VPU_PLL,
+ ANATOP_GPU_PLL,
+ ANATOP_SYSTEM_PLL1,
+ ANATOP_SYSTEM_PLL2,
+ ANATOP_SYSTEM_PLL3,
+ ANATOP_AUDIO_PLL1,
+ ANATOP_AUDIO_PLL2,
+ ANATOP_VIDEO_PLL,
+ ANATOP_DRAM_PLL,
+};
+
+enum clk_root_index {
+ ARM_A53_CLK_ROOT= 0,
+ ARM_M4_CLK_ROOT = 1,
+ VPU_A53_CLK_ROOT= 2,
+ GPU3D_CLK_ROOT = 3,
+ GPU2D_CLK_ROOT = 4,
+ MAIN_AXI_CLK_ROOT = 16,
+ ENET_AXI_CLK_ROOT = 17,
+ NAND_USDHC_BUS_CLK_ROOT = 18,
+ VPU_BUS_CLK_ROOT= 19,
+ DISPLAY_AXI_CLK_ROOT= 20,
+ DISPLAY_APB_CLK_ROOT= 21,
+ DISPLAY_RTRM_CLK_ROOT = 22,
+ USB_BUS_CLK_ROOT= 23,
+ GPU_AXI_CLK_ROOT= 24,
+ GPU_AHB_CLK_ROOT= 25,
+ NOC_CLK_ROOT= 26,
+ NOC_APB_CLK_ROOT= 27,
+ AHB_CLK_ROOT= 32,
+ IPG_CLK_ROOT= 33,
+ AUDIO_AHB_CLK_ROOT = 34,
+ MIPI_DSI_ESC_RX_CLK_ROOT= 36,
+ DRAM_SEL_CFG= 48,
+ CORE_SEL_CFG= 49,
+ DRAM_ALT_CLK_ROOT = 64,
+ DRAM_APB_CLK_ROOT = 65,
+ VPU_G1_CLK_ROOT = 66,
+ VPU_G2_CLK_ROOT = 67,
+ DISPLAY_DTRC_CLK_ROOT = 68,
+ DISPLAY_DC8000_CLK_ROOT = 69,
+ PCIE_CTRL_CLK_ROOT = 70,
+ PCIE_PHY_CLK_ROOT = 71,
+ PCIE_AUX_CLK_ROOT = 72,
+ DC_PIXEL_CLK_ROOT = 73,
+ LCDIF_PIXEL_CLK_ROOT= 74,
+ SAI1_CLK_ROOT = 75,
+ SAI2_CLK_ROOT = 76,
+ SAI3_CLK_ROOT = 77,
+ SAI4_CLK_ROOT = 78,
+ SAI5_CLK_ROOT = 79,
+ SAI6_CLK_ROOT = 80,
+ SPDIF1_CLK_ROOT = 81,
+ SPDIF2_CLK_ROOT = 82,
+ ENET_REF_CLK_ROOT = 83,
+ ENET_TIMER_CLK_ROOT = 84,
+ ENET_PHY_REF_CLK_ROOT = 85,
+ NAND_CLK_ROOT = 86,
+ QSPI_CLK_ROOT
[U-Boot] [PATCH 20/22] arm: dts: import i.MX8MM dtsi
Import i.MX8MM dtsi from Linux Kernel,
commit <0a8ad0ffa4d8> ("Merge tag 'for-linus-5.3-ofs1' of
git://git.kernel.org/pub/scm/linux/kernel/git/hubcap/linux")
Signed-off-by: Peng Fan
---
arch/arm/dts/imx8mm.dtsi | 733 +++
1 file changed, 733 insertions(+)
create mode 100644 arch/arm/dts/imx8mm.dtsi
diff --git a/arch/arm/dts/imx8mm.dtsi b/arch/arm/dts/imx8mm.dtsi
new file mode 100644
index 00..6b407a94c0
--- /dev/null
+++ b/arch/arm/dts/imx8mm.dtsi
@@ -0,0 +1,733 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2019 NXP
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+#include "imx8mm-pinfunc.h"
+
+/ {
+ compatible = "fsl,imx8mm";
+ interrupt-parent = <>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ aliases {
+ ethernet0 =
+ i2c0 =
+ i2c1 =
+ i2c2 =
+ i2c3 =
+ serial0 =
+ serial1 =
+ serial2 =
+ serial3 =
+ spi0 =
+ spi1 =
+ spi2 =
+ mmc0 =
+ mmc1 =
+ mmc2 =
+ gpio0 =
+ gpio1 =
+ gpio2 =
+ gpio3 =
+ gpio4 =
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ A53_0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x0>;
+ clock-latency = <61036>; /* two CLK32 periods */
+ clocks = < IMX8MM_CLK_ARM>;
+ enable-method = "psci";
+ next-level-cache = <_L2>;
+ operating-points-v2 = <_opp_table>;
+ };
+
+ A53_1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x1>;
+ clock-latency = <61036>; /* two CLK32 periods */
+ clocks = < IMX8MM_CLK_ARM>;
+ enable-method = "psci";
+ next-level-cache = <_L2>;
+ operating-points-v2 = <_opp_table>;
+ };
+
+ A53_2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x2>;
+ clock-latency = <61036>; /* two CLK32 periods */
+ clocks = < IMX8MM_CLK_ARM>;
+ enable-method = "psci";
+ next-level-cache = <_L2>;
+ operating-points-v2 = <_opp_table>;
+ };
+
+ A53_3: cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x3>;
+ clock-latency = <61036>; /* two CLK32 periods */
+ clocks = < IMX8MM_CLK_ARM>;
+ enable-method = "psci";
+ next-level-cache = <_L2>;
+ operating-points-v2 = <_opp_table>;
+ };
+
+ A53_L2: l2-cache0 {
+ compatible = "cache";
+ };
+ };
+
+ a53_opp_table: opp-table {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-12 {
+ opp-hz = /bits/ 64 <12>;
+ opp-microvolt = <85>;
+ clock-latency-ns = <15>;
+ };
+
+ opp-16 {
+ opp-hz = /bits/ 64 <16>;
+ opp-microvolt = <90>;
+ clock-latency-ns = <15>;
+ opp-suspend;
+ };
+ };
+
+ memory@4000 {
+ device_type = "memory";
+ reg = <0x0 0x4000 0 0x8000>;
+ };
+
+ osc_32k: clock-osc-32k {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ clock-output-names = "osc_32k";
+ };
+
+ osc_24m: clock-osc-24m {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <2400>;
+ clock-output-names = "osc_24m";
+ };
+
+ clk_ext1: clock-ext1 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <13300>;
+ clock-output-names = "clk_ext1";
+ };
+
+ clk_ext2: clock-ext2 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <13300>;
+
[U-Boot] [PATCH 09/22] imx8m: update imx-regs for i.MX8MM
i.MX8MM has similar architecture with i.MX8MQ, but it has totally
different PLL design and some register layout change.
Note: Some registers in this file are not updated because not used now.
Signed-off-by: Peng Fan
---
arch/arm/include/asm/arch-imx8m/imx-regs.h | 75 --
1 file changed, 71 insertions(+), 4 deletions(-)
diff --git a/arch/arm/include/asm/arch-imx8m/imx-regs.h
b/arch/arm/include/asm/arch-imx8m/imx-regs.h
index 68666a535b..a5be2e85da 100644
--- a/arch/arm/include/asm/arch-imx8m/imx-regs.h
+++ b/arch/arm/include/asm/arch-imx8m/imx-regs.h
@@ -10,8 +10,8 @@
#include
-#define ROM_VERSION_A0 0x800
-#define ROM_VERSION_B0 0x83C
+#define ROM_VERSION_A0 IS_ENABLED(CONFIG_IMX8MQ) ? 0x800 : 0x800
+#define ROM_VERSION_B0 IS_ENABLED(CONFIG_IMX8MQ) ? 0x83C : 0x800
#define M4_BOOTROM_BASE_ADDR 0x007E
@@ -93,7 +93,11 @@
#define SEMAPHOR_HS_BASE_ADDR 0x30AC
#define USDHC1_BASE_ADDR 0x30B4
#define USDHC2_BASE_ADDR 0x30B5
+#ifdef CONFIG_IMX8MM
+#define USDHC3_BASE_ADDR 0x30B6
+#else
#define MIPI_CS2_BASE_ADDR 0x30B6
+#endif
#define MIPI_CSI_PHY2_BASE_ADDR0x30B7
#define CSI2_BASE_ADDR 0x30B8
#define QSPI0_BASE_ADDR0x30BB
@@ -120,7 +124,8 @@
#define USB1_PHY_BASE_ADDR 0x381F
#define USB2_PHY_BASE_ADDR 0x382F
-#define MXS_LCDIF_BASE LCDIF_BASE_ADDR
+#define MXS_LCDIF_BASE is_enable(CONFIG_IMX8MQ) ? \
+ 0x3032 : 0x32e0
#define SRC_IPS_BASE_ADDR 0x3039
#define SRC_DDRC_RCR_ADDR 0x30391000
@@ -149,6 +154,9 @@
#define SRC_DDR1_RCR_CORE_RESET_N_MASK BIT(1)
#define SRC_DDR1_RCR_PRESET_N_MASK BIT(0)
+#define IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK 0x2000u
+#define IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_SHIFT 13
+
struct iomuxc_gpr_base_regs {
u32 gpr[47];
};
@@ -205,6 +213,7 @@ struct fuse_bank1_regs {
u32 rsvd3[3];
};
+#ifdef CONFIG_IMX8MQ
struct anamix_pll {
u32 audio_pll1_cfg0;
u32 audio_pll1_cfg1;
@@ -239,6 +248,60 @@ struct anamix_pll {
u32 frac_pllout_div_cfg;
u32 sscg_pllout_div_cfg;
};
+#else
+struct anamix_pll {
+ u32 audio_pll1_gnrl_ctl;
+ u32 audio_pll1_fdiv_ctl0;
+ u32 audio_pll1_fdiv_ctl1;
+ u32 audio_pll1_sscg_ctl;
+ u32 audio_pll1_mnit_ctl;
+ u32 audio_pll2_gnrl_ctl;
+ u32 audio_pll2_fdiv_ctl0;
+ u32 audio_pll2_fdiv_ctl1;
+ u32 audio_pll2_sscg_ctl;
+ u32 audio_pll2_mnit_ctl;
+ u32 video_pll1_gnrl_ctl;
+ u32 video_pll1_fdiv_ctl0;
+ u32 video_pll1_fdiv_ctl1;
+ u32 video_pll1_sscg_ctl;
+ u32 video_pll1_mnit_ctl;
+ u32 reserved[5];
+ u32 dram_pll_gnrl_ctl;
+ u32 dram_pll_fdiv_ctl0;
+ u32 dram_pll_fdiv_ctl1;
+ u32 dram_pll_sscg_ctl;
+ u32 dram_pll_mnit_ctl;
+ u32 gpu_pll_gnrl_ctl;
+ u32 gpu_pll_div_ctl;
+ u32 gpu_pll_locked_ctl1;
+ u32 gpu_pll_mnit_ctl;
+ u32 vpu_pll_gnrl_ctl;
+ u32 vpu_pll_div_ctl;
+ u32 vpu_pll_locked_ctl1;
+ u32 vpu_pll_mnit_ctl;
+ u32 arm_pll_gnrl_ctl;
+ u32 arm_pll_div_ctl;
+ u32 arm_pll_locked_ctl1;
+ u32 arm_pll_mnit_ctl;
+ u32 sys_pll1_gnrl_ctl;
+ u32 sys_pll1_div_ctl;
+ u32 sys_pll1_locked_ctl1;
+ u32 reserved2[24];
+ u32 sys_pll1_mnit_ctl;
+ u32 sys_pll2_gnrl_ctl;
+ u32 sys_pll2_div_ctl;
+ u32 sys_pll2_locked_ctl1;
+ u32 sys_pll2_mnit_ctl;
+ u32 sys_pll3_gnrl_ctl;
+ u32 sys_pll3_div_ctl;
+ u32 sys_pll3_locked_ctl1;
+ u32 sys_pll3_mnit_ctl;
+ u32 anamix_misc_ctl;
+ u32 anamix_clk_mnit_ctl;
+ u32 reserved3[437];
+ u32 digprog;
+};
+#endif
struct fuse_bank9_regs {
u32 mac_addr0;
@@ -258,11 +321,13 @@ struct src {
u32 usbophy2_rcr;
u32 mipiphy_rcr;
u32 pciephy_rcr;
+ /* Exits on i.MX8MQ */
u32 hdmi_rcr;
u32 disp_rcr;
u32 reserved2[2];
u32 gpu_rcr;
u32 vpu_rcr;
+ /* The following four exits on i.MX8MQ */
u32 pcie2_rcr;
u32 mipiphy1_rcr;
u32 mipiphy2_rcr;
@@ -285,6 +350,7 @@ struct src {
u32 gpr10;
u32 reserved5[985];
u32 ddr1_rcr;
+ /* Exist on i.MX8MQ */
u32 ddr2_rcr;
};
@@ -459,7 +525,8 @@ struct bootrom_sw_info {
u32 reserved_3[3];
};
-#define ROM_SW_INFO_ADDR_B00x0968
+#define ROM_SW_INFO_ADDR_B0(IS_ENABLED(CONFIG_IMX8MQ) ? 0x0968 :\
+0x09e8)
#define ROM_SW_INFO_ADDR_A00x09e8
#define ROM_SW_INFO_ADDR is_soc_rev(CHIP_REV_1_0) ? \
--
2.16.4
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 07/22] imx: add i.MX8MM cpu type
Add i.MX8MM cpu type and related helper functions
Signed-off-by: Peng Fan
---
arch/arm/include/asm/arch-imx/cpu.h | 6 ++
arch/arm/include/asm/mach-imx/sys_proto.h | 8
arch/arm/mach-imx/cpu.c | 12
3 files changed, 26 insertions(+)
diff --git a/arch/arm/include/asm/arch-imx/cpu.h
b/arch/arm/include/asm/arch-imx/cpu.h
index d4a83eef72..4296e47b9e 100644
--- a/arch/arm/include/asm/arch-imx/cpu.h
+++ b/arch/arm/include/asm/arch-imx/cpu.h
@@ -25,6 +25,12 @@
#define MXC_CPU_MX7S 0x71 /* dummy ID */
#define MXC_CPU_MX7D 0x72
#define MXC_CPU_IMX8MQ 0x82
+#define MXC_CPU_IMX8MM 0x85 /* dummy ID */
+#define MXC_CPU_IMX8MML0x86 /* dummy ID */
+#define MXC_CPU_IMX8MMD0x87 /* dummy ID */
+#define MXC_CPU_IMX8MMDL 0x88 /* dummy ID */
+#define MXC_CPU_IMX8MMS0x89 /* dummy ID */
+#define MXC_CPU_IMX8MMSL 0x8a /* dummy ID */
#define MXC_CPU_IMX8QXP_A0 0x90 /* dummy ID */
#define MXC_CPU_IMX8QM 0x91 /* dummy ID */
#define MXC_CPU_IMX8QXP0x92 /* dummy ID */
diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h
b/arch/arm/include/asm/mach-imx/sys_proto.h
index 4925dd7894..d01e71f506 100644
--- a/arch/arm/include/asm/mach-imx/sys_proto.h
+++ b/arch/arm/include/asm/mach-imx/sys_proto.h
@@ -43,6 +43,14 @@
#define is_mx7ulp() (is_cpu_type(MXC_CPU_MX7ULP))
#define is_imx8mq() (is_cpu_type(MXC_CPU_IMX8MQ))
+#define is_imx8mm() (is_cpu_type(MXC_CPU_IMX8MM) ||
is_cpu_type(MXC_CPU_IMX8MML) ||\
+ is_cpu_type(MXC_CPU_IMX8MMD) || is_cpu_type(MXC_CPU_IMX8MMDL) || \
+ is_cpu_type(MXC_CPU_IMX8MMS) || is_cpu_type(MXC_CPU_IMX8MMSL))
+#define is_imx8mml() (is_cpu_type(MXC_CPU_IMX8MML))
+#define is_imx8mmd() (is_cpu_type(MXC_CPU_IMX8MMD))
+#define is_imx8mmdl() (is_cpu_type(MXC_CPU_IMX8MMDL))
+#define is_imx8mms() (is_cpu_type(MXC_CPU_IMX8MMS))
+#define is_imx8mmsl() (is_cpu_type(MXC_CPU_IMX8MMSL))
#define is_imx8qxp() (is_cpu_type(MXC_CPU_IMX8QXP))
#ifdef CONFIG_MX6
diff --git a/arch/arm/mach-imx/cpu.c b/arch/arm/mach-imx/cpu.c
index 6e9a175210..60d12e6884 100644
--- a/arch/arm/mach-imx/cpu.c
+++ b/arch/arm/mach-imx/cpu.c
@@ -145,6 +145,18 @@ unsigned imx_ddr_size(void)
const char *get_imx_type(u32 imxtype)
{
switch (imxtype) {
+ case MXC_CPU_IMX8MM:
+ return "8MMQ"; /* Quad-core version of the imx8mm */
+ case MXC_CPU_IMX8MML:
+ return "8MMQL"; /* Quad-core Lite version of the imx8mm */
+ case MXC_CPU_IMX8MMD:
+ return "8MMD"; /* Dual-core version of the imx8mm */
+ case MXC_CPU_IMX8MMDL:
+ return "8MMDL"; /* Dual-core Lite version of the imx8mm */
+ case MXC_CPU_IMX8MMS:
+ return "8MMS"; /* Single-core version of the imx8mm */
+ case MXC_CPU_IMX8MMSL:
+ return "8MMSL"; /* Single-core Lite version of the imx8mm */
case MXC_CPU_IMX8MQ:
return "8MQ"; /* Quad-core version of the imx8m */
case MXC_CPU_MX7S:
--
2.16.4
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 16/22] imx8m: soc: enable SCTR clock before timer init
To i.MX8MM SCTR clock is disabled by ROM, so before timer init
need to enable it.
To i.MX8MQ, it does not hurt the clock is enabled again.
Signed-off-by: Peng Fan
---
arch/arm/mach-imx/imx8m/soc.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c
index a33ca35653..ac80266010 100644
--- a/arch/arm/mach-imx/imx8m/soc.c
+++ b/arch/arm/mach-imx/imx8m/soc.c
@@ -231,6 +231,12 @@ static void imx_set_wdog_powerdown(bool enable)
int arch_cpu_init(void)
{
struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
+ /*
+* ROM might disable clock for SCTR,
+* enable the clock before timer_init.
+*/
+ if (IS_ENABLED(CONFIG_SPL_BUILD))
+ clock_enable(CCGR_SCTR, 1);
/*
* Init timer at very early state, because sscg pll setting
* will use it
--
2.16.4
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 21/22] arm: dts: add i.MX8MM pin func
Import i.MX8MM pin func from Linux Kernel,
commit <0a8ad0ffa4d8> ("Merge tag 'for-linus-5.3-ofs1' of
git://git.kernel.org/pub/scm/linux/kernel/git/hubcap/linux")
Signed-off-by: Peng Fan
---
arch/arm/dts/imx8mm-pinfunc.h | 629 ++
1 file changed, 629 insertions(+)
create mode 100644 arch/arm/dts/imx8mm-pinfunc.h
diff --git a/arch/arm/dts/imx8mm-pinfunc.h b/arch/arm/dts/imx8mm-pinfunc.h
new file mode 100644
index 00..e25f7fcd79
--- /dev/null
+++ b/arch/arm/dts/imx8mm-pinfunc.h
@@ -0,0 +1,629 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2017-2018 NXP
+ */
+
+#ifndef __DTS_IMX8MM_PINFUNC_H
+#define __DTS_IMX8MM_PINFUNC_H
+
+/*
+ * The pin function ID is a tuple of
+ *
+ */
+
+#define MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0
0x028 0x290 0x000 0x0 0x0
+#define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT
0x028 0x290 0x4C0 0x1 0x0
+#define MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K
0x028 0x290 0x000 0x5 0x0
+#define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1
0x028 0x290 0x000 0x6 0x0
+#define MX8MM_IOMUXC_GPIO1_IO00_SJC_FAIL
0x028 0x290 0x000 0x7 0x0
+#define MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1
0x02C 0x294 0x000 0x0 0x0
+#define MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT
0x02C 0x294 0x000 0x1 0x0
+#define MX8MM_IOMUXC_GPIO1_IO01_ANAMIX_REF_CLK_24M
0x02C 0x294 0x4BC 0x5 0x0
+#define MX8MM_IOMUXC_GPIO1_IO01_CCMSRCGPCMIX_EXT_CLK2
0x02C 0x294 0x000 0x6 0x0
+#define MX8MM_IOMUXC_GPIO1_IO01_SJC_ACTIVE
0x02C 0x294 0x000 0x7 0x0
+#define MX8MM_IOMUXC_GPIO1_IO02_GPIO1_IO2
0x030 0x298 0x000 0x0 0x0
+#define MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B
0x030 0x298 0x000 0x1 0x0
+#define MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_ANY
0x030 0x298 0x000 0x5 0x0
+#define MX8MM_IOMUXC_GPIO1_IO02_SJC_DE_B
0x030 0x298 0x000 0x7 0x0
+#define MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3
0x034 0x29C 0x000 0x0 0x0
+#define MX8MM_IOMUXC_GPIO1_IO03_USDHC1_VSELECT
0x034 0x29C 0x000 0x1 0x0
+#define MX8MM_IOMUXC_GPIO1_IO03_SDMA1_EXT_EVENT0
0x034 0x29C 0x000 0x5 0x0
+#define MX8MM_IOMUXC_GPIO1_IO03_ANAMIX_XTAL_OK
0x034 0x29C 0x000 0x6 0x0
+#define MX8MM_IOMUXC_GPIO1_IO03_SJC_DONE
0x034 0x29C 0x000 0x7 0x0
+#define MX8MM_IOMUXC_GPIO1_IO04_GPIO1_IO4
0x038 0x2A0 0x000 0x0 0x0
+#define MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT
0x038 0x2A0 0x000 0x1 0x0
+#define MX8MM_IOMUXC_GPIO1_IO04_SDMA1_EXT_EVENT1
0x038 0x2A0 0x000 0x5 0x0
+#define MX8MM_IOMUXC_GPIO1_IO04_ANAMIX_XTAL_OK_LV
0x038 0x2A0 0x000 0x6 0x0
+#define MX8MM_IOMUXC_GPIO1_IO04_USDHC1_TEST_TRIG
0x038 0x2A0 0x000 0x7 0x0
+#define MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5
0x03C 0x2A4 0x000 0x0 0x0
+#define MX8MM_IOMUXC_GPIO1_IO05_M4_NMI
0x03C 0x2A4 0x000 0x1 0x0
+#define MX8MM_IOMUXC_GPIO1_IO05_CCMSRCGPCMIX_PMIC_READY
0x03C 0x2A4 0x000 0x5 0x0
+#define MX8MM_IOMUXC_GPIO1_IO05_CCMSRCGPCMIX_INT_BOOT
0x03C 0x2A4 0x000 0x6 0x0
+#define MX8MM_IOMUXC_GPIO1_IO05_USDHC2_TEST_TRIG
0x03C 0x2A4 0x000 0x7 0x0
+#define MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6
0x040 0x2A8 0x000 0x0 0x0
+#define MX8MM_IOMUXC_GPIO1_IO06_ENET1_MDC
0x040 0x2A8 0x000 0x1 0x0
+#define MX8MM_IOMUXC_GPIO1_IO06_USDHC1_CD_B
0x040 0x2A8 0x000 0x5 0x0
+#define MX8MM_IOMUXC_GPIO1_IO06_CCMSRCGPCMIX_EXT_CLK3
0x040 0x2A8 0x000 0x6 0x0
+#define MX8MM_IOMUXC_GPIO1_IO06_ECSPI1_TEST_TRIG
0x040 0x2A8 0x000 0x7 0x0
+#define MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7
0x044 0x2AC 0x000 0x0 0x0
+#define MX8MM_IOMUXC_GPIO1_IO07_ENET1_MDIO
0x044 0x2AC 0x000 0x1 0x0
+#define MX8MM_IOMUXC_GPIO1_IO07_USDHC1_WP
0x044 0x2AC 0x000 0x5 0x0
+#define MX8MM_IOMUXC_GPIO1_IO07_CCMSRCGPCMIX_EXT_CLK4
0x044 0x2AC 0x000 0x6 0x0
+#define MX8MM_IOMUXC_GPIO1_IO07_ECSPI2_TEST_TRIG
0x044 0x2AC 0x000 0x7 0x0
+#define MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8
0x048 0x2B0 0x000 0x0 0x0
+#define MX8MM_IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN
0x048
[U-Boot] [PATCH 08/22] imx: spl: add spl_board_boot_device for i.MX8MM
Differnet board has different controller used, it is
hard to use one layout for them all.
Signed-off-by: Peng Fan
---
arch/arm/mach-imx/spl.c | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm/mach-imx/spl.c b/arch/arm/mach-imx/spl.c
index 1f230aca33..7ada60d7a2 100644
--- a/arch/arm/mach-imx/spl.c
+++ b/arch/arm/mach-imx/spl.c
@@ -18,6 +18,11 @@
DECLARE_GLOBAL_DATA_PTR;
+__weak int spl_board_boot_device(enum boot_device boot_dev_spl)
+{
+ return 0;
+}
+
#if defined(CONFIG_MX6)
/* determine boot device from SRC_SBMR1 (BOOT_CFG[4:1]) or SRC_GPR9 register */
u32 spl_boot_device(void)
@@ -127,6 +132,9 @@ u32 spl_boot_device(void)
enum boot_device boot_device_spl = get_boot_device();
+ if (IS_ENABLED(CONFIG_IMX8MM))
+ return spl_board_boot_device(boot_device_spl);
+
switch (boot_device_spl) {
#if defined(CONFIG_MX7)
case SD1_BOOT:
--
2.16.4
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 05/22] imx: add IMX8MM kconfig entry
Add IMX8MM kconfig entry Signed-off-by: Peng Fan --- arch/arm/mach-imx/imx8m/Kconfig | 4 1 file changed, 4 insertions(+) diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig index 9c487870a6..35c978e863 100644 --- a/arch/arm/mach-imx/imx8m/Kconfig +++ b/arch/arm/mach-imx/imx8m/Kconfig @@ -8,6 +8,10 @@ config IMX8MQ bool select IMX8M +config IMX8MM + bool + select IMX8M + config SYS_SOC default "imx8m" -- 2.16.4 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 10/22] imx: add get_cpu_rev support for i.MX8MM
There are several variants based on i.MX8MM, add the support in
get_cpu_rev
Signed-off-by: Peng Fan
---
arch/arm/mach-imx/imx8m/soc.c | 57 +++
1 file changed, 47 insertions(+), 10 deletions(-)
diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c
index 7ec39b3e47..5115471eff 100644
--- a/arch/arm/mach-imx/imx8m/soc.c
+++ b/arch/arm/mach-imx/imx8m/soc.c
@@ -130,25 +130,62 @@ static struct mm_region imx8m_mem_map[] = {
struct mm_region *mem_map = imx8m_mem_map;
+static u32 get_cpu_variant_type(u32 type)
+{
+ struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
+ struct fuse_bank *bank = >bank[1];
+ struct fuse_bank1_regs *fuse =
+ (struct fuse_bank1_regs *)bank->fuse_regs;
+
+ u32 value = readl(>tester4);
+
+ if (type == MXC_CPU_IMX8MM) {
+ switch (value & 0x3) {
+ case 2:
+ if (value & 0x1c)
+ return MXC_CPU_IMX8MMDL;
+ else
+ return MXC_CPU_IMX8MMD;
+ case 3:
+ if (value & 0x1c)
+ return MXC_CPU_IMX8MMSL;
+ else
+ return MXC_CPU_IMX8MMS;
+ default:
+ if (value & 0x1c)
+ return MXC_CPU_IMX8MML;
+ break;
+ }
+ }
+
+ return type;
+}
+
u32 get_cpu_rev(void)
{
struct anamix_pll *ana_pll = (struct anamix_pll *)ANATOP_BASE_ADDR;
u32 reg = readl(_pll->digprog);
u32 type = (reg >> 16) & 0xff;
+ u32 major_low = (reg >> 8) & 0xff;
u32 rom_version;
reg &= 0xff;
- if (reg == CHIP_REV_1_0) {
- /*
-* For B0 chip, the DIGPROG is not updated, still TO1.0.
-* we have to check ROM version further
-*/
- rom_version = readl((void __iomem *)ROM_VERSION_A0);
- if (rom_version != CHIP_REV_1_0) {
- rom_version = readl((void __iomem *)ROM_VERSION_B0);
- if (rom_version >= CHIP_REV_2_0)
- reg = CHIP_REV_2_0;
+ /* i.MX8MM */
+ if (major_low == 0x41) {
+ type = get_cpu_variant_type(MXC_CPU_IMX8MM);
+ } else {
+ if (reg == CHIP_REV_1_0) {
+ /*
+* For B0 chip, the DIGPROG is not updated, still TO1.0.
+* we have to check ROM version further
+*/
+ rom_version = readl((void __iomem *)ROM_VERSION_A0);
+ if (rom_version != CHIP_REV_1_0) {
+ rom_version = readl((void __iomem
*)ROM_VERSION_B0);
+ if (rom_version >= CHIP_REV_2_0)
+ reg = CHIP_REV_2_0;
+ }
}
}
--
2.16.4
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 06/22] imx: imx8mm: add clock bindings header
Import clock bindings header file from Linux 5.3.0-rc2 Signed-off-by: Peng Fan --- include/dt-bindings/clock/imx8mm-clock.h | 253 +++ 1 file changed, 253 insertions(+) create mode 100644 include/dt-bindings/clock/imx8mm-clock.h diff --git a/include/dt-bindings/clock/imx8mm-clock.h b/include/dt-bindings/clock/imx8mm-clock.h new file mode 100644 index 00..07e6c686f3 --- /dev/null +++ b/include/dt-bindings/clock/imx8mm-clock.h @@ -0,0 +1,253 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright 2017-2018 NXP + */ + +#ifndef __DT_BINDINGS_CLOCK_IMX8MM_H +#define __DT_BINDINGS_CLOCK_IMX8MM_H + +#define IMX8MM_CLK_DUMMY 0 +#define IMX8MM_CLK_32K 1 +#define IMX8MM_CLK_24M 2 +#define IMX8MM_OSC_HDMI_CLK3 +#define IMX8MM_CLK_EXT14 +#define IMX8MM_CLK_EXT25 +#define IMX8MM_CLK_EXT36 +#define IMX8MM_CLK_EXT47 +#define IMX8MM_AUDIO_PLL1_REF_SEL 8 +#define IMX8MM_AUDIO_PLL2_REF_SEL 9 +#define IMX8MM_VIDEO_PLL1_REF_SEL 10 +#define IMX8MM_DRAM_PLL_REF_SEL11 +#define IMX8MM_GPU_PLL_REF_SEL 12 +#define IMX8MM_VPU_PLL_REF_SEL 13 +#define IMX8MM_ARM_PLL_REF_SEL 14 +#define IMX8MM_SYS_PLL1_REF_SEL15 +#define IMX8MM_SYS_PLL2_REF_SEL16 +#define IMX8MM_SYS_PLL3_REF_SEL17 +#define IMX8MM_AUDIO_PLL1 18 +#define IMX8MM_AUDIO_PLL2 19 +#define IMX8MM_VIDEO_PLL1 20 +#define IMX8MM_DRAM_PLL21 +#define IMX8MM_GPU_PLL 22 +#define IMX8MM_VPU_PLL 23 +#define IMX8MM_ARM_PLL 24 +#define IMX8MM_SYS_PLL125 +#define IMX8MM_SYS_PLL226 +#define IMX8MM_SYS_PLL327 +#define IMX8MM_AUDIO_PLL1_BYPASS 28 +#define IMX8MM_AUDIO_PLL2_BYPASS 29 +#define IMX8MM_VIDEO_PLL1_BYPASS 30 +#define IMX8MM_DRAM_PLL_BYPASS 31 +#define IMX8MM_GPU_PLL_BYPASS 32 +#define IMX8MM_VPU_PLL_BYPASS 33 +#define IMX8MM_ARM_PLL_BYPASS 34 +#define IMX8MM_SYS_PLL1_BYPASS 35 +#define IMX8MM_SYS_PLL2_BYPASS 36 +#define IMX8MM_SYS_PLL3_BYPASS 37 +#define IMX8MM_AUDIO_PLL1_OUT 38 +#define IMX8MM_AUDIO_PLL2_OUT 39 +#define IMX8MM_VIDEO_PLL1_OUT 40 +#define IMX8MM_DRAM_PLL_OUT41 +#define IMX8MM_GPU_PLL_OUT 42 +#define IMX8MM_VPU_PLL_OUT 43 +#define IMX8MM_ARM_PLL_OUT 44 +#define IMX8MM_SYS_PLL1_OUT45 +#define IMX8MM_SYS_PLL2_OUT46 +#define IMX8MM_SYS_PLL3_OUT47 +#define IMX8MM_SYS_PLL1_40M48 +#define IMX8MM_SYS_PLL1_80M49 +#define IMX8MM_SYS_PLL1_100M 50 +#define IMX8MM_SYS_PLL1_133M 51 +#define IMX8MM_SYS_PLL1_160M 52 +#define IMX8MM_SYS_PLL1_200M 53 +#define IMX8MM_SYS_PLL1_266M 54 +#define IMX8MM_SYS_PLL1_400M 55 +#define IMX8MM_SYS_PLL1_800M 56 +#define IMX8MM_SYS_PLL2_50M57 +#define IMX8MM_SYS_PLL2_100M 58 +#define IMX8MM_SYS_PLL2_125M 59 +#define IMX8MM_SYS_PLL2_166M 60 +#define IMX8MM_SYS_PLL2_200M 61 +#define IMX8MM_SYS_PLL2_250M 62 +#define IMX8MM_SYS_PLL2_333M 63 +#define IMX8MM_SYS_PLL2_500M 64 +#define IMX8MM_SYS_PLL2_1000M 65 + +/* core */ +#define IMX8MM_CLK_A53_SRC 66 +#define IMX8MM_CLK_M4_SRC 67 +#define IMX8MM_CLK_VPU_SRC 68 +#define IMX8MM_CLK_GPU3D_SRC 69 +#define IMX8MM_CLK_GPU2D_SRC 70 +#define IMX8MM_CLK_A53_CG 71 +#define IMX8MM_CLK_M4_CG 72 +#define IMX8MM_CLK_VPU_CG 73 +#define IMX8MM_CLK_GPU3D_CG74 +#define IMX8MM_CLK_GPU2D_CG75 +#define IMX8MM_CLK_A53_DIV 76 +#define IMX8MM_CLK_M4_DIV 77 +#define IMX8MM_CLK_VPU_DIV 78 +#define IMX8MM_CLK_GPU3D_DIV 79 +#define IMX8MM_CLK_GPU2D_DIV 80 + +/* bus */ +#define IMX8MM_CLK_MAIN_AXI81 +#define IMX8MM_CLK_ENET_AXI82
[U-Boot] [PATCH 03/22] imx8m: add image cfg for i.MX8MM lpddr4
There is no HDMI on i.MX8MM, so we need to remove HDMI entry, then we could not reuse imximage.cfg, so create a new one. Signed-off-by: Peng Fan --- arch/arm/mach-imx/imx8m/imximage-8mm-lpddr4.cfg | 16 1 file changed, 16 insertions(+) create mode 100644 arch/arm/mach-imx/imx8m/imximage-8mm-lpddr4.cfg diff --git a/arch/arm/mach-imx/imx8m/imximage-8mm-lpddr4.cfg b/arch/arm/mach-imx/imx8m/imximage-8mm-lpddr4.cfg new file mode 100644 index 00..1a2e43e671 --- /dev/null +++ b/arch/arm/mach-imx/imx8m/imximage-8mm-lpddr4.cfg @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2019 NXP + */ + +#define __ASSEMBLY__ + +FIT +BOOT_FROM sd +LOADER spl/u-boot-spl-ddr.bin 0x7E1000 +SECOND_LOADER u-boot.itb 0x4020 0x6 + +DDR_FW lpddr4_pmu_train_1d_imem.bin +DDR_FW lpddr4_pmu_train_1d_dmem.bin +DDR_FW lpddr4_pmu_train_2d_imem.bin +DDR_FW lpddr4_pmu_train_2d_dmem.bin -- 2.16.4 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 02/22] ddr: imx8m: fix ddr firmware location when enable SPL OF
With SPL_OF_SPERATE, the device tree will be padded to
end of the u-boot-spl-nodtb.bin, however we also put
the ddr firmware file to this location, so need to adapt
the code with SPL OF and align to 16bytes to ease copy firmware.
Signed-off-by: Peng Fan
---
drivers/ddr/imx/imx8m/helper.c | 12 +++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/drivers/ddr/imx/imx8m/helper.c b/drivers/ddr/imx/imx8m/helper.c
index 61cd4f6db1..3e605353ea 100644
--- a/drivers/ddr/imx/imx8m/helper.c
+++ b/drivers/ddr/imx/imx8m/helper.c
@@ -31,7 +31,17 @@ void ddr_load_train_firmware(enum fw_type type)
unsigned long pr_to32, pr_from32;
unsigned long fw_offset = type ? IMEM_2D_OFFSET : 0;
unsigned long imem_start = (unsigned long)&_end + fw_offset;
- unsigned long dmem_start = imem_start + IMEM_LEN;
+ unsigned long dmem_start;
+
+#ifdef CONFIG_SPL_OF_CONTROL
+ if (gd->fdt_blob && !fdt_check_header(gd->fdt_blob)) {
+ imem_start = roundup((unsigned long)&_end +
+fdt_totalsize(gd->fdt_blob), 4) +
+ fw_offset;
+ }
+#endif
+
+ dmem_start = imem_start + IMEM_LEN;
pr_from32 = imem_start;
pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * IMEM_OFFSET_ADDR;
--
2.16.4
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 01/22] tools: imx8m_image: align spl bin image size
Align spl bin image size to 4 byte aligned, because we need to pad ddr firmware in the end of spl bin. However when enable SPL OF, the spl dtb will be padded to u-boot-nodtb.bin, then u-boot-spl.bin size might not be 4 bytes aligned. ddr_load_train_firmware in drivers/ddr/imx/imx8m/helper.c use 4 bytes aligned address to load ddr firmware, so we need make sure u-boot-spl.bin is 4 bytes aligned, in this patch we use dd to create a new file named u-boot-spl-pad.bin, then pad ddr firmware. If SPL OF not enabled, this patch not hurt, because `_end` already is 4 bytes aligned. Signed-off-by: Peng Fan --- tools/imx8m_image.sh | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/tools/imx8m_image.sh b/tools/imx8m_image.sh index ec0881a128..08a6a48180 100755 --- a/tools/imx8m_image.sh +++ b/tools/imx8m_image.sh @@ -35,8 +35,9 @@ if [ $post_process = 1 ]; then objcopy -I binary -O binary --pad-to 0x8000 --gap-fill=0x0 $srctree/lpddr4_pmu_train_2d_imem.bin lpddr4_pmu_train_2d_imem_pad.bin cat lpddr4_pmu_train_1d_imem_pad.bin lpddr4_pmu_train_1d_dmem_pad.bin > lpddr4_pmu_train_1d_fw.bin cat lpddr4_pmu_train_2d_imem_pad.bin $srctree/lpddr4_pmu_train_2d_dmem.bin > lpddr4_pmu_train_2d_fw.bin - cat spl/u-boot-spl.bin lpddr4_pmu_train_1d_fw.bin lpddr4_pmu_train_2d_fw.bin > spl/u-boot-spl-ddr.bin - rm -f lpddr4_pmu_train_1d_fw.bin lpddr4_pmu_train_2d_fw.bin lpddr4_pmu_train_1d_imem_pad.bin lpddr4_pmu_train_1d_dmem_pad.bin lpddr4_pmu_train_2d_imem_pad.bin + dd if=spl/u-boot-spl.bin of=spl/u-boot-spl-pad.bin bs=4 conv=sync + cat spl/u-boot-spl-pad.bin lpddr4_pmu_train_1d_fw.bin lpddr4_pmu_train_2d_fw.bin > spl/u-boot-spl-ddr.bin + rm -f lpddr4_pmu_train_1d_fw.bin lpddr4_pmu_train_2d_fw.bin lpddr4_pmu_train_1d_imem_pad.bin lpddr4_pmu_train_1d_dmem_pad.bin lpddr4_pmu_train_2d_imem_pad.bin spl/u-boot-spl-pad.bin fi fi -- 2.16.4 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 04/22] imx: add IMX8MQ kconfig entry
Add IMX8MQ kconfig entry, preparing support IMX8MM Signed-off-by: Peng Fan --- arch/arm/mach-imx/imx8m/Kconfig | 6 +- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig index 317dee9bc1..9c487870a6 100644 --- a/arch/arm/mach-imx/imx8m/Kconfig +++ b/arch/arm/mach-imx/imx8m/Kconfig @@ -4,6 +4,10 @@ config IMX8M bool select ROM_UNIFIED_SECTIONS +config IMX8MQ + bool + select IMX8M + config SYS_SOC default "imx8m" @@ -13,7 +17,7 @@ choice config TARGET_IMX8MQ_EVK bool "imx8mq_evk" - select IMX8M + select IMX8MQ select IMX8M_LPDDR4 endchoice -- 2.16.4 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 00/22] i.MX8MM support
This is a splitted and updated patch from
https://patchwork.ozlabs.org/cover/1128799/ which is to support both
i.MX8MM and i.MX8MN.
This patchset only covers i.MX8MM and depends on the following patch
to work,
https://patchwork.ozlabs.org/cover/1144317/
https://patchwork.ozlabs.org/patch/1142686/
https://patchwork.ozlabs.org/patch/1142690/
https://patchwork.ozlabs.org/patch/1142691/
https://patchwork.ozlabs.org/patch/1143291/
https://patchwork.ozlabs.org/patch/1143765/
There is a README added, following that to test if you would like to.
Peng Fan (21):
tools: imx8m_image: align spl bin image size
ddr: imx8m: fix ddr firmware location when enable SPL OF
imx8m: add image cfg for i.MX8MM lpddr4
imx: add IMX8MQ kconfig entry
imx: add IMX8MM kconfig entry
imx: imx8mm: add clock bindings header
imx: add i.MX8MM cpu type
imx: spl: add spl_board_boot_device for i.MX8MM
imx8m: update imx-regs for i.MX8MM
imx: add get_cpu_rev support for i.MX8MM
imx8m: add pin header for i.MX8MM
imx: add i.MX8MM PE property
imx8m: Fix MMU table issue for OPTEE memory
imx8m: set BYPASS ID SWAP to avoid AXI bus errors
imx8m: soc: enable SCTR clock before timer init
imx8m: rename clock to clock_imx8mq
imx8m: restructure clock.h
imx8m: add clk support for i.MX8MM
arm: dts: import i.MX8MM dtsi
arm: dts: add i.MX8MM pin func
imx: Add i.MX8MM EVK board support.
Ye Li (1):
imx8m: Configure trustzone region 0 for non-secure access
arch/arm/dts/Makefile |3 +-
arch/arm/dts/imx8mm-evk-u-boot.dtsi| 92 +
arch/arm/dts/imx8mm-evk.dts| 235 +++
arch/arm/dts/imx8mm-pinfunc.h | 629 +++
arch/arm/dts/imx8mm.dtsi | 733
arch/arm/include/asm/arch-imx/cpu.h|6 +
arch/arm/include/asm/arch-imx8m/clock.h| 493 +
arch/arm/include/asm/arch-imx8m/clock_imx8mm.h | 387
arch/arm/include/asm/arch-imx8m/clock_imx8mq.h | 424 +
arch/arm/include/asm/arch-imx8m/imx-regs.h | 75 +-
arch/arm/include/asm/arch-imx8m/imx8mm_pins.h | 691 +++
arch/arm/include/asm/mach-imx/iomux-v3.h |4 +
arch/arm/include/asm/mach-imx/sys_proto.h |8 +
arch/arm/mach-imx/cpu.c| 12 +
arch/arm/mach-imx/imx8m/Kconfig| 17 +-
arch/arm/mach-imx/imx8m/Makefile |4 +-
arch/arm/mach-imx/imx8m/clock_imx8mm.c | 306 +++
.../arm/mach-imx/imx8m/{clock.c => clock_imx8mq.c} |5 +-
arch/arm/mach-imx/imx8m/clock_slice.c | 63 +
arch/arm/mach-imx/imx8m/imximage-8mm-lpddr4.cfg| 16 +
arch/arm/mach-imx/imx8m/soc.c | 91 +-
arch/arm/mach-imx/spl.c|8 +
board/freescale/imx8mm_evk/Kconfig | 12 +
board/freescale/imx8mm_evk/MAINTAINERS |6 +
board/freescale/imx8mm_evk/Makefile| 12 +
board/freescale/imx8mm_evk/imx8mm_evk.c| 90 +
board/freescale/imx8mm_evk/lpddr4_timing.c | 1980
board/freescale/imx8mm_evk/spl.c | 102 +
configs/imx8mm_evk_defconfig | 70 +
drivers/ddr/imx/imx8m/helper.c | 12 +-
include/configs/imx8mm_evk.h | 164 ++
include/dt-bindings/clock/imx8mm-clock.h | 253 +++
tools/imx8m_image.sh |5 +-
33 files changed, 6533 insertions(+), 475 deletions(-)
create mode 100644 arch/arm/dts/imx8mm-evk-u-boot.dtsi
create mode 100644 arch/arm/dts/imx8mm-evk.dts
create mode 100644 arch/arm/dts/imx8mm-pinfunc.h
create mode 100644 arch/arm/dts/imx8mm.dtsi
create mode 100644 arch/arm/include/asm/arch-imx8m/clock_imx8mm.h
create mode 100644 arch/arm/include/asm/arch-imx8m/clock_imx8mq.h
create mode 100644 arch/arm/include/asm/arch-imx8m/imx8mm_pins.h
create mode 100644 arch/arm/mach-imx/imx8m/clock_imx8mm.c
rename arch/arm/mach-imx/imx8m/{clock.c => clock_imx8mq.c} (99%)
create mode 100644 arch/arm/mach-imx/imx8m/imximage-8mm-lpddr4.cfg
create mode 100644 board/freescale/imx8mm_evk/Kconfig
create mode 100644 board/freescale/imx8mm_evk/MAINTAINERS
create mode 100644 board/freescale/imx8mm_evk/Makefile
create mode 100644 board/freescale/imx8mm_evk/imx8mm_evk.c
create mode 100644 board/freescale/imx8mm_evk/lpddr4_timing.c
create mode 100644 board/freescale/imx8mm_evk/spl.c
create mode 100644 configs/imx8mm_evk_defconfig
create mode 100644 include/configs/imx8mm_evk.h
create mode 100644 include/dt-bindings/clock/imx8mm-clock.h
--
2.16.4
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH V2 4/4] clk: imx: add i.MX8MM clk driver
Add i.MX8MM clk driver support.
Signed-off-by: Peng Fan
---
drivers/clk/imx/Makefile | 2 +
drivers/clk/imx/clk-imx8mm.c | 414 +++
2 files changed, 416 insertions(+)
create mode 100644 drivers/clk/imx/clk-imx8mm.c
diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile
index 105a58ca90..5ad7967fe9 100644
--- a/drivers/clk/imx/Makefile
+++ b/drivers/clk/imx/Makefile
@@ -10,3 +10,5 @@ ifdef CONFIG_CLK_IMX8
obj-$(CONFIG_IMX8QXP) += clk-imx8qxp.o
obj-$(CONFIG_IMX8QM) += clk-imx8qm.o
endif
+obj-$(CONFIG_$(SPL_TPL_)CLK_IMX8MM) += clk-imx8mm.o clk-pll14xx.o \
+ clk-composite-8m.o
diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c
new file mode 100644
index 00..9459d8ab8e
--- /dev/null
+++ b/drivers/clk/imx/clk-imx8mm.c
@@ -0,0 +1,414 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2019 NXP
+ * Peng Fan
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "clk.h"
+
+#define PLL_1416X_RATE(_rate, _m, _p, _s) \
+ { \
+ .rate = (_rate),\
+ .mdiv = (_m), \
+ .pdiv = (_p), \
+ .sdiv = (_s), \
+ }
+
+#define PLL_1443X_RATE(_rate, _m, _p, _s, _k) \
+ { \
+ .rate = (_rate),\
+ .mdiv = (_m), \
+ .pdiv = (_p), \
+ .sdiv = (_s), \
+ .kdiv = (_k), \
+ }
+
+static const struct imx_pll14xx_rate_table imx8mm_pll1416x_tbl[] = {
+ PLL_1416X_RATE(18U, 225, 3, 0),
+ PLL_1416X_RATE(16U, 200, 3, 0),
+ PLL_1416X_RATE(12U, 300, 3, 1),
+ PLL_1416X_RATE(10U, 250, 3, 1),
+ PLL_1416X_RATE(8U, 200, 3, 1),
+ PLL_1416X_RATE(75000U, 250, 2, 2),
+ PLL_1416X_RATE(7U, 350, 3, 2),
+ PLL_1416X_RATE(6U, 300, 3, 2),
+};
+
+static const struct imx_pll14xx_rate_table imx8mm_drampll_tbl[] = {
+ PLL_1443X_RATE(65000U, 325, 3, 2, 0),
+};
+
+static struct imx_pll14xx_clk imx8mm_dram_pll __initdata = {
+ .type = PLL_1443X,
+ .rate_table = imx8mm_drampll_tbl,
+ .rate_count = ARRAY_SIZE(imx8mm_drampll_tbl),
+};
+
+static struct imx_pll14xx_clk imx8mm_arm_pll __initdata = {
+ .type = PLL_1416X,
+ .rate_table = imx8mm_pll1416x_tbl,
+ .rate_count = ARRAY_SIZE(imx8mm_pll1416x_tbl),
+};
+
+static struct imx_pll14xx_clk imx8mm_sys_pll __initdata = {
+ .type = PLL_1416X,
+ .rate_table = imx8mm_pll1416x_tbl,
+ .rate_count = ARRAY_SIZE(imx8mm_pll1416x_tbl),
+};
+
+static const char *pll_ref_sels[] = { "clock-osc-24m", "dummy", "dummy",
"dummy", };
+static const char *dram_pll_bypass_sels[] = {"dram_pll", "dram_pll_ref_sel", };
+static const char *arm_pll_bypass_sels[] = {"arm_pll", "arm_pll_ref_sel", };
+static const char *sys_pll1_bypass_sels[] = {"sys_pll1", "sys_pll1_ref_sel", };
+static const char *sys_pll2_bypass_sels[] = {"sys_pll2", "sys_pll2_ref_sel", };
+static const char *sys_pll3_bypass_sels[] = {"sys_pll3", "sys_pll3_ref_sel", };
+
+static const char *imx8mm_a53_sels[] = {"clock-osc-24m", "arm_pll_out",
"sys_pll2_500m", "sys_pll2_1000m",
+ "sys_pll1_800m", "sys_pll1_400m",
"audio_pll1_out", "sys_pll3_out", };
+
+static const char *imx8mm_ahb_sels[] = {"osc_24m", "sys_pll1_133m",
"sys_pll1_800m", "sys_pll1_400m",
+ "sys_pll2_125m", "sys_pll3_out",
"audio_pll1_out", "video_pll1_out", };
+
+static const char *imx8mm_enet_axi_sels[] = {"clock-osc-24m", "sys_pll1_266m",
"sys_pll1_800m", "sys_pll2_250m",
+"sys_pll2_200m", "audio_pll1_out",
"video_pll1_out", "sys_pll3_out", };
+
+static const char *imx8mm_nand_usdhc_sels[] = {"clock-osc-24m",
"sys_pll1_266m", "sys_pll1_800m", "sys_pll2_200m",
+ "sys_pll1_133m", "sys_pll3_out",
"sys_pll2_250m", "audio_pll1_out", };
+
+static const char *imx8mm_usdhc1_sels[] = {"clock-osc-24m", "sys_pll1_400m",
"sys_pll1_800m", "sys_pll2_500m",
+ "sys_pll3_out", "sys_pll1_266m",
"audio_pll2_out", "sys_pll1_100m", };
+
+static const char *imx8mm_usdhc2_sels[] = {"clock-osc-24m", "sys_pll1_400m",
"sys_pll1_800m", "sys_pll2_500m",
+ "sys_pll3_out", "sys_pll1_266m",
"audio_pll2_out", "sys_pll1_100m", };
+
+static const char *imx8mm_i2c1_sels[] = {"clock-osc-24m",
[U-Boot] [PATCH V2 2/4] clk: imx: add pll14xx driver
Add pll14xx driver
Signed-off-by: Peng Fan
---
drivers/clk/imx/clk-pll14xx.c | 371 ++
drivers/clk/imx/clk.h | 25 +++
2 files changed, 396 insertions(+)
create mode 100644 drivers/clk/imx/clk-pll14xx.c
diff --git a/drivers/clk/imx/clk-pll14xx.c b/drivers/clk/imx/clk-pll14xx.c
new file mode 100644
index 00..8b47b0dea9
--- /dev/null
+++ b/drivers/clk/imx/clk-pll14xx.c
@@ -0,0 +1,371 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2017-2019 NXP.
+ *
+ * Peng Fan
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "clk.h"
+
+#define UBOOT_DM_CLK_IMX_PLL1443X "imx_clk_pll1443x"
+#define UBOOT_DM_CLK_IMX_PLL1416X "imx_clk_pll1416x"
+
+#define GNRL_CTL 0x0
+#define DIV_CTL0x4
+#define LOCK_STATUSBIT(31)
+#define LOCK_SEL_MASK BIT(29)
+#define CLKE_MASK BIT(11)
+#define RST_MASK BIT(9)
+#define BYPASS_MASKBIT(4)
+#define MDIV_SHIFT 12
+#define MDIV_MASK GENMASK(21, 12)
+#define PDIV_SHIFT 4
+#define PDIV_MASK GENMASK(9, 4)
+#define SDIV_SHIFT 0
+#define SDIV_MASK GENMASK(2, 0)
+#define KDIV_SHIFT 0
+#define KDIV_MASK GENMASK(15, 0)
+
+#define LOCK_TIMEOUT_US1
+
+struct clk_pll14xx {
+ struct clk clk;
+ void __iomem*base;
+ enum imx_pll14xx_type type;
+ const struct imx_pll14xx_rate_table *rate_table;
+ int rate_count;
+};
+
+#define to_clk_pll14xx(_clk) container_of(_clk, struct clk_pll14xx, clk)
+
+static const struct imx_pll14xx_rate_table *imx_get_pll_settings(
+ struct clk_pll14xx *pll, unsigned long rate)
+{
+ const struct imx_pll14xx_rate_table *rate_table = pll->rate_table;
+ int i;
+
+ for (i = 0; i < pll->rate_count; i++)
+ if (rate == rate_table[i].rate)
+ return _table[i];
+
+ return NULL;
+}
+
+static unsigned long clk_pll1416x_recalc_rate(struct clk *clk)
+{
+ struct clk_pll14xx *pll = to_clk_pll14xx(dev_get_clk_ptr(clk->dev));
+ u64 fvco = clk_get_parent_rate(clk);
+ u32 mdiv, pdiv, sdiv, pll_div;
+
+ pll_div = readl(pll->base + 4);
+ mdiv = (pll_div & MDIV_MASK) >> MDIV_SHIFT;
+ pdiv = (pll_div & PDIV_MASK) >> PDIV_SHIFT;
+ sdiv = (pll_div & SDIV_MASK) >> SDIV_SHIFT;
+
+ fvco *= mdiv;
+ do_div(fvco, pdiv << sdiv);
+
+ return fvco;
+}
+
+static unsigned long clk_pll1443x_recalc_rate(struct clk *clk)
+{
+ struct clk_pll14xx *pll = to_clk_pll14xx(dev_get_clk_ptr(clk->dev));
+ u64 fvco = clk_get_parent_rate(clk);
+ u32 mdiv, pdiv, sdiv, pll_div_ctl0, pll_div_ctl1;
+ short int kdiv;
+
+ pll_div_ctl0 = readl(pll->base + 4);
+ pll_div_ctl1 = readl(pll->base + 8);
+ mdiv = (pll_div_ctl0 & MDIV_MASK) >> MDIV_SHIFT;
+ pdiv = (pll_div_ctl0 & PDIV_MASK) >> PDIV_SHIFT;
+ sdiv = (pll_div_ctl0 & SDIV_MASK) >> SDIV_SHIFT;
+ kdiv = pll_div_ctl1 & KDIV_MASK;
+
+ /* fvco = (m * 65536 + k) * Fin / (p * 65536) */
+ fvco *= (mdiv * 65536 + kdiv);
+ pdiv *= 65536;
+
+ do_div(fvco, pdiv << sdiv);
+
+ return fvco;
+}
+
+static inline bool clk_pll1416x_mp_change(const struct imx_pll14xx_rate_table
*rate,
+ u32 pll_div)
+{
+ u32 old_mdiv, old_pdiv;
+
+ old_mdiv = (pll_div & MDIV_MASK) >> MDIV_SHIFT;
+ old_pdiv = (pll_div & PDIV_MASK) >> PDIV_SHIFT;
+
+ return rate->mdiv != old_mdiv || rate->pdiv != old_pdiv;
+}
+
+static inline bool clk_pll1443x_mpk_change(const struct imx_pll14xx_rate_table
*rate,
+ u32 pll_div_ctl0, u32 pll_div_ctl1)
+{
+ u32 old_mdiv, old_pdiv, old_kdiv;
+
+ old_mdiv = (pll_div_ctl0 & MDIV_MASK) >> MDIV_SHIFT;
+ old_pdiv = (pll_div_ctl0 & PDIV_MASK) >> PDIV_SHIFT;
+ old_kdiv = (pll_div_ctl1 & KDIV_MASK) >> KDIV_SHIFT;
+
+ return rate->mdiv != old_mdiv || rate->pdiv != old_pdiv ||
+ rate->kdiv != old_kdiv;
+}
+
+static inline bool clk_pll1443x_mp_change(const struct imx_pll14xx_rate_table
*rate,
+ u32 pll_div_ctl0, u32 pll_div_ctl1)
+{
+ u32 old_mdiv, old_pdiv, old_kdiv;
+
+ old_mdiv = (pll_div_ctl0 & MDIV_MASK) >> MDIV_SHIFT;
+ old_pdiv = (pll_div_ctl0 & PDIV_MASK) >> PDIV_SHIFT;
+ old_kdiv = (pll_div_ctl1 & KDIV_MASK) >> KDIV_SHIFT;
+
+ return rate->mdiv != old_mdiv || rate->pdiv != old_pdiv ||
+ rate->kdiv != old_kdiv;
+}
+
+static int clk_pll14xx_wait_lock(struct clk_pll14xx *pll)
+{
+ u32 val;
+
+ return readl_poll_timeout(pll->base, val, val & LOCK_TIMEOUT_US,
+ LOCK_TIMEOUT_US);
+}
+
+static ulong clk_pll1416x_set_rate(struct clk *clk, unsigned long drate)
+{
+ struct clk_pll14xx *pll =
[U-Boot] [PATCH V2 1/4] clk: imx: add Kconfig entry for i.MX8MM
Add Kconfig entry for i.MX8MM Signed-off-by: Peng Fan --- drivers/clk/Kconfig | 4 ++-- drivers/clk/imx/Kconfig | 16 2 files changed, 18 insertions(+), 2 deletions(-) diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index a3f0171b45..fce595b4b3 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -48,7 +48,7 @@ config CLK_BOSTON config SPL_CLK_CCF bool "SPL Common Clock Framework [CCF] support " - depends on SPL_CLK_IMX6Q + depends on SPL_CLK_IMX6Q || ARCH_IMX8M help Enable this option if you want to (re-)use the Linux kernel's Common Clock Framework [CCF] code in U-Boot's SPL. @@ -62,7 +62,7 @@ config SPL_CLK_COMPOSITE_CCF config CLK_CCF bool "Common Clock Framework [CCF] support " - depends on CLK_IMX6Q || SANDBOX_CLK_CCF + depends on CLK_IMX6Q || ARCH_IMX8M || SANDBOX_CLK_CCF help Enable this option if you want to (re-)use the Linux kernel's Common Clock Framework [CCF] code in U-Boot's clock driver. diff --git a/drivers/clk/imx/Kconfig b/drivers/clk/imx/Kconfig index 3e6a980c8c..aae69cf9b0 100644 --- a/drivers/clk/imx/Kconfig +++ b/drivers/clk/imx/Kconfig @@ -20,3 +20,19 @@ config CLK_IMX8 select CLK help This enables support clock driver for i.MX8 platforms. + +config SPL_CLK_IMX8MM + bool "SPL clock support for i.MX8MM" + depends on ARCH_IMX8M && SPL + select SPL_CLK + select SPL_CLK_CCF + help + This enables SPL DM/DTS support for clock driver in i.MX8MM + +config CLK_IMX8MM + bool "Clock support for i.MX8MM" + depends on ARCH_IMX8M + select CLK + select CLK_CCF + help + This enables support clock driver for i.MX8MM platforms. -- 2.16.4 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH V2 3/4] clk: imx: add i.MX8M composite clk support
Import i.MX8M composite clk from Linux Kernel 5.3.0-rc2
Signed-off-by: Peng Fan
---
drivers/clk/imx/clk-composite-8m.c | 170 +
1 file changed, 170 insertions(+)
create mode 100644 drivers/clk/imx/clk-composite-8m.c
diff --git a/drivers/clk/imx/clk-composite-8m.c
b/drivers/clk/imx/clk-composite-8m.c
new file mode 100644
index 00..57ebbc3bb0
--- /dev/null
+++ b/drivers/clk/imx/clk-composite-8m.c
@@ -0,0 +1,170 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2019 NXP
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include "clk.h"
+
+#define UBOOT_DM_CLK_IMX_COMPOSITE "imx_clk_composite"
+
+#define PCG_PREDIV_SHIFT 16
+#define PCG_PREDIV_WIDTH 3
+#define PCG_PREDIV_MAX 8
+
+#define PCG_DIV_SHIFT 0
+#define PCG_DIV_WIDTH 6
+#define PCG_DIV_MAX64
+
+#define PCG_PCS_SHIFT 24
+#define PCG_PCS_MASK 0x7
+
+#define PCG_CGC_SHIFT 28
+
+static unsigned long imx8m_clk_composite_divider_recalc_rate(struct clk *clk)
+{
+ struct clk_divider *divider = (struct clk_divider *)to_clk_divider(clk);
+ struct clk_composite *composite = (struct clk_composite *)clk->data;
+ ulong parent_rate = clk_get_parent_rate(>clk);
+ unsigned long prediv_rate;
+ unsigned int prediv_value;
+ unsigned int div_value;
+
+ debug("%s: name %s prate: %lu reg: %p\n", __func__,
+ (>clk)->dev->name, parent_rate, divider->reg);
+ prediv_value = readl(divider->reg) >> divider->shift;
+ prediv_value &= clk_div_mask(divider->width);
+
+ prediv_rate = divider_recalc_rate(clk, parent_rate, prediv_value,
+ NULL, divider->flags,
+ divider->width);
+
+ div_value = readl(divider->reg) >> PCG_DIV_SHIFT;
+ div_value &= clk_div_mask(PCG_DIV_WIDTH);
+
+ return divider_recalc_rate(clk, prediv_rate, div_value, NULL,
+ divider->flags, PCG_DIV_WIDTH);
+}
+
+static int imx8m_clk_composite_compute_dividers(unsigned long rate,
+ unsigned long parent_rate,
+ int *prediv, int *postdiv)
+{
+ int div1, div2;
+ int error = INT_MAX;
+ int ret = -EINVAL;
+
+ *prediv = 1;
+ *postdiv = 1;
+
+ for (div1 = 1; div1 <= PCG_PREDIV_MAX; div1++) {
+ for (div2 = 1; div2 <= PCG_DIV_MAX; div2++) {
+ int new_error = ((parent_rate / div1) / div2) - rate;
+
+ if (abs(new_error) < abs(error)) {
+ *prediv = div1;
+ *postdiv = div2;
+ error = new_error;
+ ret = 0;
+ }
+ }
+ }
+ return ret;
+}
+
+/*
+ * The clk are not binded to a dev, because it is part of composite clk
+ * use composite clk to get dev
+ */
+static ulong imx8m_clk_composite_divider_set_rate(struct clk *clk,
+ unsigned long rate)
+{
+ struct clk_divider *divider = (struct clk_divider *)to_clk_divider(clk);
+ struct clk_composite *composite = (struct clk_composite *)clk->data;
+ ulong parent_rate = clk_get_parent_rate(>clk);
+ int prediv_value;
+ int div_value;
+ int ret;
+ u32 val;
+
+ ret = imx8m_clk_composite_compute_dividers(rate, parent_rate,
+ _value, _value);
+ if (ret)
+ return -EINVAL;
+
+ val = readl(divider->reg);
+ val &= ~((clk_div_mask(divider->width) << divider->shift) |
+ (clk_div_mask(PCG_DIV_WIDTH) << PCG_DIV_SHIFT));
+
+ val |= (u32)(prediv_value - 1) << divider->shift;
+ val |= (u32)(div_value - 1) << PCG_DIV_SHIFT;
+ writel(val, divider->reg);
+
+ return clk_get_rate(>clk);
+}
+
+static const struct clk_ops imx8m_clk_composite_divider_ops = {
+ .get_rate = imx8m_clk_composite_divider_recalc_rate,
+ .set_rate = imx8m_clk_composite_divider_set_rate,
+};
+
+struct clk *imx8m_clk_composite_flags(const char *name,
+ const char * const *parent_names,
+ int num_parents, void __iomem *reg,
+ unsigned long flags)
+{
+ struct clk *clk = ERR_PTR(-ENOMEM);
+ struct clk_divider *div = NULL;
+ struct clk_gate *gate = NULL;
+ struct clk_mux *mux = NULL;
+
+ mux = kzalloc(sizeof(*mux), GFP_KERNEL);
+ if (!mux)
+ goto fail;
+
+ mux->reg = reg;
+ mux->shift = PCG_PCS_SHIFT;
+ mux->mask = PCG_PCS_MASK;
+ mux->num_parents = num_parents;
+ mux->flags = flags;
+ mux->parent_names =
[U-Boot] [PATCH V2 0/4] Prepare i.MX8MM clk
V2: 2/4: fix MASK/SHIFT usage 4/4: ARM clk not use 24M for switch, use pll2_500m Add R-b/A-b tag This is to support i.MX8MM clk driver. i.MX8MM use similar clock design as i.MX7D, but it has use different PLL, so we need to add pll14xx driver. And to simplify the clock usage, import the composite clk driver from Linux Kernel, then we could have simple clk tree. This is to split the previous patchset https://github.com/MrVan/u-boot/commits/imx8mmn-ccf for i.MX8MM/N support There are some checkpatch warnings that not addressed, because import from Linux Kernel. Peng Fan (4): clk: imx: add Kconfig entry for i.MX8MM clk: imx: add pll14xx driver clk: imx: add i.MX8M composite clk support clk: imx: add i.MX8MM clk driver drivers/clk/Kconfig| 4 +- drivers/clk/imx/Kconfig| 16 ++ drivers/clk/imx/Makefile | 2 + drivers/clk/imx/clk-composite-8m.c | 170 +++ drivers/clk/imx/clk-imx8mm.c | 414 + drivers/clk/imx/clk-pll14xx.c | 371 + drivers/clk/imx/clk.h | 25 +++ 7 files changed, 1000 insertions(+), 2 deletions(-) create mode 100644 drivers/clk/imx/clk-composite-8m.c create mode 100644 drivers/clk/imx/clk-imx8mm.c create mode 100644 drivers/clk/imx/clk-pll14xx.c -- 2.16.4 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH u-boot-marvell 1/1] pci: pci_mvebu: set BAR0 after memory space is set
Hi Marek, On Thu, Aug 8, 2019 at 1:02 AM Marek Behún wrote: > > The non-DM version of this driver used to set BAR0 register after the > calls to pci_set_region. > I found out that for some strange reason the ath10k driver in kernel > fails to work if this is done the other way around. > I know that Linux's driver should not depend on how U-Boot does things, > but for some strange reason it does and this seems to be the simplest > solution. Fix it since it caused regressions on Omnia. > > Signed-off-by: Marek Behún > Cc: Stefan Roese > Cc: Dirk Eibach > Cc: Mario Six > Cc: Chris Packham > Cc: Phil Sutter > Cc: VlaoMao Tested-by: Chris Packham > --- > drivers/pci/pci_mvebu.c | 8 > 1 file changed, 4 insertions(+), 4 deletions(-) > > diff --git a/drivers/pci/pci_mvebu.c b/drivers/pci/pci_mvebu.c > index e21dc10c2f..f9b08f38a1 100644 > --- a/drivers/pci/pci_mvebu.c > +++ b/drivers/pci/pci_mvebu.c > @@ -313,10 +313,6 @@ static int mvebu_pcie_probe(struct udevice *dev) > reg |= BIT(10); /* disable interrupts */ > writel(reg, pcie->base + PCIE_CMD_OFF); > > - /* Set BAR0 to internal registers */ > - writel(SOC_REGS_PHY_BASE, pcie->base + PCIE_BAR_LO_OFF(0)); > - writel(0, pcie->base + PCIE_BAR_HI_OFF(0)); > - > /* PCI memory space */ > pci_set_region(hose->regions + 0, pcie->mem.start, >pcie->mem.start, PCIE_MEM_SIZE, PCI_REGION_MEM); > @@ -326,6 +322,10 @@ static int mvebu_pcie_probe(struct udevice *dev) >PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); > hose->region_count = 2; > > + /* Set BAR0 to internal registers */ > + writel(SOC_REGS_PHY_BASE, pcie->base + PCIE_BAR_LO_OFF(0)); > + writel(0, pcie->base + PCIE_BAR_HI_OFF(0)); > + > bus++; > > return 0; > -- > 2.21.0 > > ___ > U-Boot mailing list > U-Boot@lists.denx.de > https://lists.denx.de/listinfo/u-boot ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] Please pull u-boot-marvell/master (watchdog related)
On Mon, Aug 05, 2019 at 04:46:43PM +0200, Stefan Roese wrote: > Hi Tom, > > please pull the following watchdog related patches: > Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v9 8/9] board: intel: Add new slimbootloader board
On Thu, Aug 8, 2019 at 10:54 PM Bin Meng wrote: > > On Thu, Aug 8, 2019 at 10:35 PM Bin Meng wrote: > > > > On Sat, Aug 3, 2019 at 4:31 PM Park, Aiden wrote: > > > > > > Add slimbootloader board to run U-boot as a Slim Bootloader payload > > > - Add new board/intel/slimbootloader directory with minimum codes > > > - Add slimbootloader configuration files > > > - Add doc/board/intel/slimbootloader.rst > > > > > > Signed-off-by: Aiden Park > > > Reviewed-by: Bin Meng > > > Reviewed-by: Andy Shevchenko > > > --- > > > Changes in v8: > > > * Add a space between acronym and (definition) > > > > > > Changes in v7: > > > * Adding slimbootloader.rst in index.rst > > > > > > Changes in v6: > > > * Select CONFIG_SYS_SLIMBOOTLOADER in board Kconfig > > > * Move USB_STORAGE and USB_KEYBOARD to board Kconfig > > > * Convert README to reST doc/board/intel/slimbootloader.rst > > > > > > Changes in v5: > > > * Remove X86_LOAD_FROM_32_BIT from slimbootloader_defconfig > > > > > > Changes in v3: > > > * Remove VENDOR_SLIMBOOTLOADER > > > * Use VENDOR_INTEL > > > * Move slimbootloader under board/intel/ > > > * Enable generic CONFIGs in slimbootloader_defconfig > > > * Add more description in board/intel/slimbootloader/README > > > > > > board/intel/Kconfig | 14 ++ > > > board/intel/slimbootloader/Kconfig | 28 > > > board/intel/slimbootloader/Makefile | 5 + > > > board/intel/slimbootloader/slimbootloader.c | 21 +++ > > > board/intel/slimbootloader/start.S | 9 + > > > configs/slimbootloader_defconfig| 22 +++ > > > doc/board/intel/index.rst | 1 + > > > doc/board/intel/slimbootloader.rst | 174 > > > include/configs/slimbootloader.h| 62 +++ > > > 9 files changed, 336 insertions(+) > > > create mode 100644 board/intel/slimbootloader/Kconfig > > > create mode 100644 board/intel/slimbootloader/Makefile > > > create mode 100644 board/intel/slimbootloader/slimbootloader.c > > > create mode 100644 board/intel/slimbootloader/start.S > > > create mode 100644 configs/slimbootloader_defconfig > > > create mode 100644 doc/board/intel/slimbootloader.rst > > > create mode 100644 include/configs/slimbootloader.h > > > > > > > Tested-by: Bin Meng > > applied to u-boot-x86, thanks! The patch missed slimbootloader board MAINTAINERS file that caused gitlab CI failure. I have added the MAINTAINERS to this commit. Regards, Bin ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 1/3] spl: imx6: Let spl_boot_device return USDHC1 or USDHC2
> Subject: Re: [U-Boot] [PATCH 1/3] spl: imx6: Let spl_boot_device return
> USDHC1 or USDHC2
>
> On Wed, Aug 7, 2019 at 6:44 PM Ricardo Salveti
> wrote:
> >
> > Hi Adam,
> >
> > On Thu, May 23, 2019 at 4:11 PM Adam Ford
> wrote:
> > >
> > > Currently, when the spl_boot_device checks the boot device, it will
> > > only return MMC1 when it's either sd or eMMC regardless of whether
> > > or not it's MMC1 or MMC2. This is a problem when booting from MMC2
> > > if MMC isn't being manually configured like in the DM_SPL case with
> > > SPL_OF_CONTROL.
> > >
> > > This patch will check the register and return either MMC1 or MMC2.
> > >
> > > Signed-off-by: Adam Ford
> > >
> > > diff --git a/arch/arm/mach-imx/spl.c b/arch/arm/mach-imx/spl.c index
> > > 9f1e0f6a72..1f230aca33 100644
> > > --- a/arch/arm/mach-imx/spl.c
> > > +++ b/arch/arm/mach-imx/spl.c
> > > @@ -24,6 +24,7 @@ u32 spl_boot_device(void) {
> > > unsigned int bmode = readl(_base->sbmr2);
> > > u32 reg = imx6_src_get_boot_mode();
> > > + u32 mmc_index = ((reg >> 11) & 0x03);
> > >
> > > /*
> > > * Check for BMODE if serial downloader is enabled
> > > @@ -84,11 +85,12 @@ u32 spl_boot_device(void)
> > > /* SD/eSD: 8.5.3, Table 8-15 */
> > > case IMX6_BMODE_SD:
> > > case IMX6_BMODE_ESD:
> > > - return BOOT_DEVICE_MMC1;
> > > - /* MMC/eMMC: 8.5.3 */
> > > case IMX6_BMODE_MMC:
> > > case IMX6_BMODE_EMMC:
> > > - return BOOT_DEVICE_MMC1;
> > > + if (mmc_index == 1)
> > > + return BOOT_DEVICE_MMC2;
> > > + else
> > > + return BOOT_DEVICE_MMC1;
> >
> > I just got to test v2019.10-rc1, which includes this change, and I'm
> > unable to boot SPL on my Hummingboard 2, which uses USDHC-2 for
> > sdcard.
>
> I wondered if it would break a board. It's why I originally sent it
> as an RFC. In my mind, it seems like we've created a system that only
> supports one MMC, then we created a work-around to correctly identify
> the MMC because the original implementation didn't. I will admit, my
> patch only checks for MMC1 or MMC2, but I don't have hardware to test
> MMC3.
> >
> > Looks like this change breaks devices that are not using device
> > tree/dynamic mmc initialization, as the MMC index will not necessarily
> > be correct.
>
> How hard would it be to use the device tree/dynamic initialization for
> your board? It seems to be the trend, and at least in some cases,
> they've made it required and boards that don't comply get removed. It
> seems like we're prolonging. I'd be open for an #ifdef hook around
> it, but I am not sure how that would fly with the maintainers. My
> goal is to remove as much board-specific code as possible and move it
> to the shared code to reduce the overhead and code size. Checking for
> SPL_OF_CONTROL && DM_MMC might be potential work-around to the
> work-around.
>
> >
> > Looking at mx6cuboxi.c in particular, fsl_esdhc_initialize will only
> > be called once as it already knows which MMC device to initialize
> > based on the BOOT_CFG register, causing the device mmc devnum to be 1
> > only. The issue shows up when booting SPL as find_mmc_device will look
> > for a matching dev_num index, which gets automatically increased when
> > fsl_esdhc_initialize gets called (and which is only called once in my
> > case, for MMC2).
> >
> > This is not an issue with imx6q_logic as at
> > 8f4691e31a18254d225524a4b018b8cbcddc70b1 you removed
> > fsl_esdhc_initialize, but all the other boards using MMC2 and doing
> > only one single call will have the same problem.
> >
> > Not sure if there is an easy fix here, but converting everything to
> > dynamic mmc initialization will required quite a bit of effort.
The short term workaround would be create multiple mmc in SPL stage.
For long term, it would be better to use DM.
Regards,
Peng.
>
> A bunch of boards have already started migrating to SPL_OF_CONTROL and
> DM_MMC. The imx6q_logic board was just a matter of changing some
> config options and fixing and/or creating a -u-boot.dtsi file to
> enable the various drivers in SPL, then removing the legacy code.
>
> Stefano, what would your preference be?
>
> adam
> >
> > Thanks,
> > --
> > Ricardo Salveti de Araujo
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 3/4] driver: ddr: Refine the ddr init driver on imx8m
Hi Troy,
> -Original Message-
> From: Troy Kisky
> Sent: 2019年8月9日 3:52
> To: Peng Fan ; sba...@denx.de; feste...@gmail.com
> Cc: u-boot@lists.denx.de; Jacky Bai ; dl-uboot-imx
>
> Subject: Re: [U-Boot] [PATCH 3/4] driver: ddr: Refine the ddr init driver on
> imx8m
>
> On 8/8/2019 2:59 AM, Peng Fan wrote:
> > From: Jacky Bai
> >
> > Refine the ddr init driver to make it more reusable for different DDR
> > type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code.
> >
> > Signed-off-by: Jacky Bai
> > Reviewed-by: Ye Li
> > Signed-off-by: Peng Fan
> > ---
> > drivers/ddr/imx/imx8m/Kconfig| 6 ++
> > drivers/ddr/imx/imx8m/Makefile | 4 +-
> > drivers/ddr/imx/imx8m/ddr4_init.c| 112
> > drivers/ddr/imx/imx8m/ddr_init.c | 168
> ++
> > drivers/ddr/imx/imx8m/ddrphy_utils.c | 4 +
> > drivers/ddr/imx/imx8m/helper.c | 10 +-
> > drivers/ddr/imx/imx8m/lpddr4_init.c | 191
> > ---
> > 7 files changed, 184 insertions(+), 311 deletions(-) delete mode
> > 100644 drivers/ddr/imx/imx8m/ddr4_init.c create mode 100644
> > drivers/ddr/imx/imx8m/ddr_init.c delete mode 100644
> > drivers/ddr/imx/imx8m/lpddr4_init.c
> >
> > diff --git a/drivers/ddr/imx/imx8m/Kconfig
> > b/drivers/ddr/imx/imx8m/Kconfig index a83b0f43d7..5bf61eb258 100644
> > --- a/drivers/ddr/imx/imx8m/Kconfig
> > +++ b/drivers/ddr/imx/imx8m/Kconfig
> > @@ -16,6 +16,12 @@ config IMX8M_DDR4
> > help
> > Select the i.MX8M DDR4 driver support on i.MX8M SOC.
> >
> > +config IMX8M_DDR3L
> > + bool "imx8m ddr3l"
> > + select IMX8M_DRAM
> > + help
> > + Select the i.MX8M DDR3L driver support on i.MX8M SOC.
> > +
> > config SAVED_DRAM_TIMING_BASE
> > hex "Define the base address for saved dram timing"
> > help
> > diff --git a/drivers/ddr/imx/imx8m/Makefile
> > b/drivers/ddr/imx/imx8m/Makefile index 64f9ab20e6..bd9bcb8d53 100644
> > --- a/drivers/ddr/imx/imx8m/Makefile
> > +++ b/drivers/ddr/imx/imx8m/Makefile
> > @@ -5,7 +5,5 @@
> > #
> >
> > ifdef CONFIG_SPL_BUILD
> > -obj-$(CONFIG_IMX8M_DRAM) += helper.o ddrphy_utils.o ddrphy_train.o
> > ddrphy_csr.o
> > -obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_init.o
> > -obj-$(CONFIG_IMX8M_DDR4) += ddr4_init.o
> > +obj-$(CONFIG_IMX8M_DRAM) += helper.o ddrphy_utils.o ddrphy_train.o
> > +ddrphy_csr.o ddr_init.o
> > endif
> > diff --git a/drivers/ddr/imx/imx8m/ddr4_init.c
> > b/drivers/ddr/imx/imx8m/ddr4_init.c
> > deleted file mode 100644
> > index b8aa104536..00
> > --- a/drivers/ddr/imx/imx8m/ddr4_init.c
> > +++ /dev/null
> > @@ -1,112 +0,0 @@
> > -// SPDX-License-Identifier: GPL-2.0+
> > -/*
> > - * Copyright 2018 NXP
> > - */
> > -
> > -#include
> > -#include
> > -#include
> > -#include
> > -#include
> > -#include
> > -
> > -void ddr4_cfg_umctl2(struct dram_cfg_param *ddrc_cfg, int num) -{
> > - int i = 0;
> > -
> > - for (i = 0; i < num; i++) {
> > - reg32_write(ddrc_cfg->reg, ddrc_cfg->val);
> > - ddrc_cfg++;
> > - }
> > -}
> > -
> > -void ddr_init(struct dram_timing_info *dram_timing) -{
> > - volatile unsigned int tmp_t;
> > - /*
> > -* assert [0]ddr1_preset_n, [1]ddr1_core_reset_n,
> > -* [2]ddr1_phy_reset, [3]ddr1_phy_pwrokin_n,
> > -* [4]src_system_rst_b!
> > -*/
> > - reg32_write(SRC_DDRC_RCR_ADDR, 0x8F3F);
> > - /* deassert [4]src_system_rst_b! */
> > - reg32_write(SRC_DDRC_RCR_ADDR, 0x8F0F);
> > -
> > - /*
> > -* change the clock source of dram_apb_clk_root
> > -* to source 4 --800MHz/4
> > -*/
> > - clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON |
> > -CLK_ROOT_SOURCE_SEL(4) |
> > -CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV4));
> > -
> > - dram_pll_init(MHZ(600));
> > -
> > - reg32_write(0x303A00EC, 0x); /* PGC_CPU_MAPPING */
> > - reg32setbit(0x303A00F8, 5); /* PU_PGC_SW_PUP_REQ */
> > -
> > - /* release [0]ddr1_preset_n, [3]ddr1_phy_pwrokin_n */
> > - reg32_write(SRC_DDRC_RCR_ADDR, 0x8F06);
> > -
> > - reg32_write(DDRC_DBG1(0), 0x0001);
> > - reg32_write(DDRC_PWRCTL(0), 0x0001);
> > -
> > - while (0 != (0x7 & reg32_read(DDRC_STAT(0
> > - ;
> > -
> > - /* config the uMCTL2's registers */
> > - ddr4_cfg_umctl2(dram_timing->ddrc_cfg, dram_timing->ddrc_cfg_num);
> > -
> > - reg32_write(DDRC_RFSHCTL3(0), 0x0001);
> > - /* RESET: DEASSERTED */
> > - /* RESET: > - reg32_write(SRC_DDRC_RCR_ADDR, 0x8F04);
> > - reg32_write(SRC_DDRC_RCR_ADDR, 0x8F00);
> > -
> > - reg32_write(DDRC_DBG1(0), 0x);
> > - reg32_write(DDRC_PWRCTL(0), 0x0aa);
> > - reg32_write(DDRC_SWCTL(0), 0x);
> > -
> > - reg32_write(DDRC_DFIMISC(0), 0x);
> > -
> > - /* config the DDR PHY's registers */
> > - ddr_cfg_phy(dram_timing);
> > -
> > - do {
> > - tmp_t = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) +
> > -
[U-Boot] [PATCH] board_f: reserve noncached space below malloc area
Noncached area at present is being initialized to random space after malloc
area. It works in most the cases as it goes to stack area & stack is not
overwriting it being far from it.
Signed-off-by: Vikas Manocha
---
common/board_f.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/common/board_f.c b/common/board_f.c
index 59745d5..4910051 100644
--- a/common/board_f.c
+++ b/common/board_f.c
@@ -439,12 +439,25 @@ static int reserve_uboot(void)
return 0;
}
+#ifdef CONFIG_SYS_NONCACHED_MEMORY
+static int reserve_noncached(void)
+{
+ /* round down to SECTION SIZE (typicaly 1MB) limit */
+ gd->start_addr_sp &= ~(MMU_SECTION_SIZE - 1);
+ gd->start_addr_sp -= CONFIG_SYS_NONCACHED_MEMORY;
+ return 0;
+}
+#endif
+
/* reserve memory for malloc() area */
static int reserve_malloc(void)
{
gd->start_addr_sp = gd->start_addr_sp - TOTAL_MALLOC_LEN;
debug("Reserving %dk for malloc() at: %08lx\n",
TOTAL_MALLOC_LEN >> 10, gd->start_addr_sp);
+#ifdef CONFIG_SYS_NONCACHED_MEMORY
+ reserve_noncached(void);
+#endif
return 0;
}
--
2.7.4
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] drivers: net: driver for MDIO muxes controlled over I2C
Hi Joe, On 7/25/2019 9:41 PM, Joe Hershberger wrote: Hi Alex, https://patchwork.ozlabs.org/patch/1132514/ was applied to http://git.denx.de/?p=u-boot/u-boot-net.git can you please check this commit (d9a9174), I think mdio_mux_i2creg.c was lost at merge. Do you want me to send a new patch with just the .c file? Thank you! Alex Thanks! -Joe ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v2 05/12] armV7R: K3: am654: Allow using SPL BSS pre-relocation
Am 08.08.2019 um 21:43 schrieb Andreas Dannenberg: Hi Simon, On Thu, Aug 08, 2019 at 09:01:03PM +0200, Simon Goldschmidt wrote: Am 08.08.2019 um 20:29 schrieb Andreas Dannenberg: Ok back to my specific scenario, hopefully I'm adding at least some new aspects now rather than repeating what was discussed already in different threads... From SPL I'm required to load (and start) our "System Firmware" which is a prerequisite for bringing up DDR. We know that DDR bringup itself should happen in SPL's board_init_f(), hence the need for loading stuff from board_init_f() when no DDR is yet available (only on-chip memory). I'm using the same loader framework to do the loading from board_init_f() that SPL later uses from a board_init_r() context to load U-Boot proper, ATF, and other files depending on the platform. > Now let's focus on two static variables that play a role in this context, 'fat_registered' spl_fat.c and '*mmc' in spl_mmc.c. Those static variables are essentially used to remember the initialization state of the FAT driver and the MMC loader, so that it doesn't get re-initialized the second time those get called (during SPL's main usage of loading U-Boot, etc.). So essentially the desire is to carry this initialization state from SPL's board_init_f() to board_init_r(). OK, so essentially, you've added CONFIG_SPL_EARLY_BSS because FAT and MMC contain variables in BSS? That would mean we could drop that config option after fixing those two (given that they can be fixed)? Yes I think I could drop it in this case, I'm not married to CONFIG_SPL_EARLY_BSS in any way. But we still have all the other platforms that use memset() to directly clear BSS from SPL's board_init_f()... Ideally any improvements should be made across the board. (And I just need to throw that out there) one could also imagine moving said platforms to also use CONFIG_SPL_EARLY_BSS (replacing their custom memset approach) to at least unify the approach... That could well be a valid approach. However, ideally, we'd first check why these boards really need that memset. I fixed socfgpa_gen5 by fixing the sdram driver to not use BSS... (a rather simple fix that even ended up reducing code size by keeping the data on the stack). it), but how could this play in here? Sure I can reserve some memory from board_init_f(), or the drivers under discussion, and store the initialization state there, but now I'd have the need to carry the pointer to that initialization data forward somehow. spl_fat.c is not a DM driver, it inherently doesn't have anything I can "tack on" additional data fields. I don't quite see how I can make this work more elegantly but I'm open to suggestions... No, sorry, what I wrote was probably a bit confusing. I wrote that as a result of my work on socfpga_a10. There, we have the firmware loader framework loading things e.g. from MMC. During my test of unifying the socfpga config header files (both gen5 and a10 combined), I stumbled accross the fact that you cannot use standard malloc in SPL when the devicetree is initialized during board_init_f as dlmalloc.c makes heavy use of BSS. You can only use simple malloc there, because its state is kept in 'gd'. But it seems that wasn't your problem? A next problem with simple malloc is that you can't free anything and I think I remember code passages around file system loading that make heavy use of malloc/free. But that again doesn't seem to be your problem here? I had this exact problem initially, as I was loading two files from board_init_f (the "system firmware" and it's config data), which I since consolidated into a FIT image avoiding the issue altogether. The FAT driver specifically is very wasteful allocating 64KB chunks of memory (you can reduce the sector size to alleviate some of that) and with simple malloc it would eat through the little RAM I had too quickly... So for a while I was using full malloc from board_init_f() to make the FAT driver happy. And I had also found I need BSS for that after a little pain and suffering with the JTAG debugger. But this is no longer n issue when only loading one file. Yeah, well, that issue remains even if we'd fix the already mentioned problems... (Mr. Glass had suggested in one of the threads why I don't do the DDR initialization in board_init_r() then, which I experimented with, but the changes I had to make to common U-Boot files were rather drastic so I abandoned this attempt). Yes, I can understand that that's not an ideal way to move forward... To come back on the original issue, I'd still propose to add these static variables to 'gd' or to some sub-struct referenced from 'gd'. I see a high risk for others to run into these issues that you have hidden for your platform by enabling CONFIG_SPL_EARLY_BSS. I was always hesitant even thinking about adding stuff to gd due to the large impact so I haven't really considered this as a feasible path. But if we were to go down this road
Re: [U-Boot] [PATCH 3/4] driver: ddr: Refine the ddr init driver on imx8m
On 8/8/2019 2:59 AM, Peng Fan wrote:
> From: Jacky Bai
>
> Refine the ddr init driver to make it more reusable for different
> DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant
> code.
>
> Signed-off-by: Jacky Bai
> Reviewed-by: Ye Li
> Signed-off-by: Peng Fan
> ---
> drivers/ddr/imx/imx8m/Kconfig| 6 ++
> drivers/ddr/imx/imx8m/Makefile | 4 +-
> drivers/ddr/imx/imx8m/ddr4_init.c| 112
> drivers/ddr/imx/imx8m/ddr_init.c | 168 ++
> drivers/ddr/imx/imx8m/ddrphy_utils.c | 4 +
> drivers/ddr/imx/imx8m/helper.c | 10 +-
> drivers/ddr/imx/imx8m/lpddr4_init.c | 191
> ---
> 7 files changed, 184 insertions(+), 311 deletions(-)
> delete mode 100644 drivers/ddr/imx/imx8m/ddr4_init.c
> create mode 100644 drivers/ddr/imx/imx8m/ddr_init.c
> delete mode 100644 drivers/ddr/imx/imx8m/lpddr4_init.c
>
> diff --git a/drivers/ddr/imx/imx8m/Kconfig b/drivers/ddr/imx/imx8m/Kconfig
> index a83b0f43d7..5bf61eb258 100644
> --- a/drivers/ddr/imx/imx8m/Kconfig
> +++ b/drivers/ddr/imx/imx8m/Kconfig
> @@ -16,6 +16,12 @@ config IMX8M_DDR4
> help
> Select the i.MX8M DDR4 driver support on i.MX8M SOC.
>
> +config IMX8M_DDR3L
> + bool "imx8m ddr3l"
> + select IMX8M_DRAM
> + help
> + Select the i.MX8M DDR3L driver support on i.MX8M SOC.
> +
> config SAVED_DRAM_TIMING_BASE
> hex "Define the base address for saved dram timing"
> help
> diff --git a/drivers/ddr/imx/imx8m/Makefile b/drivers/ddr/imx/imx8m/Makefile
> index 64f9ab20e6..bd9bcb8d53 100644
> --- a/drivers/ddr/imx/imx8m/Makefile
> +++ b/drivers/ddr/imx/imx8m/Makefile
> @@ -5,7 +5,5 @@
> #
>
> ifdef CONFIG_SPL_BUILD
> -obj-$(CONFIG_IMX8M_DRAM) += helper.o ddrphy_utils.o ddrphy_train.o
> ddrphy_csr.o
> -obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_init.o
> -obj-$(CONFIG_IMX8M_DDR4) += ddr4_init.o
> +obj-$(CONFIG_IMX8M_DRAM) += helper.o ddrphy_utils.o ddrphy_train.o
> ddrphy_csr.o ddr_init.o
> endif
> diff --git a/drivers/ddr/imx/imx8m/ddr4_init.c
> b/drivers/ddr/imx/imx8m/ddr4_init.c
> deleted file mode 100644
> index b8aa104536..00
> --- a/drivers/ddr/imx/imx8m/ddr4_init.c
> +++ /dev/null
> @@ -1,112 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0+
> -/*
> - * Copyright 2018 NXP
> - */
> -
> -#include
> -#include
> -#include
> -#include
> -#include
> -#include
> -
> -void ddr4_cfg_umctl2(struct dram_cfg_param *ddrc_cfg, int num)
> -{
> - int i = 0;
> -
> - for (i = 0; i < num; i++) {
> - reg32_write(ddrc_cfg->reg, ddrc_cfg->val);
> - ddrc_cfg++;
> - }
> -}
> -
> -void ddr_init(struct dram_timing_info *dram_timing)
> -{
> - volatile unsigned int tmp_t;
> - /*
> - * assert [0]ddr1_preset_n, [1]ddr1_core_reset_n,
> - * [2]ddr1_phy_reset, [3]ddr1_phy_pwrokin_n,
> - * [4]src_system_rst_b!
> - */
> - reg32_write(SRC_DDRC_RCR_ADDR, 0x8F3F);
> - /* deassert [4]src_system_rst_b! */
> - reg32_write(SRC_DDRC_RCR_ADDR, 0x8F0F);
> -
> - /*
> - * change the clock source of dram_apb_clk_root
> - * to source 4 --800MHz/4
> - */
> - clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON |
> - CLK_ROOT_SOURCE_SEL(4) |
> - CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV4));
> -
> - dram_pll_init(MHZ(600));
> -
> - reg32_write(0x303A00EC, 0x); /* PGC_CPU_MAPPING */
> - reg32setbit(0x303A00F8, 5); /* PU_PGC_SW_PUP_REQ */
> -
> - /* release [0]ddr1_preset_n, [3]ddr1_phy_pwrokin_n */
> - reg32_write(SRC_DDRC_RCR_ADDR, 0x8F06);
> -
> - reg32_write(DDRC_DBG1(0), 0x0001);
> - reg32_write(DDRC_PWRCTL(0), 0x0001);
> -
> - while (0 != (0x7 & reg32_read(DDRC_STAT(0
> - ;
> -
> - /* config the uMCTL2's registers */
> - ddr4_cfg_umctl2(dram_timing->ddrc_cfg, dram_timing->ddrc_cfg_num);
> -
> - reg32_write(DDRC_RFSHCTL3(0), 0x0001);
> - /* RESET: DEASSERTED */
> - /* RESET: - reg32_write(SRC_DDRC_RCR_ADDR, 0x8F04);
> - reg32_write(SRC_DDRC_RCR_ADDR, 0x8F00);
> -
> - reg32_write(DDRC_DBG1(0), 0x);
> - reg32_write(DDRC_PWRCTL(0), 0x0aa);
> - reg32_write(DDRC_SWCTL(0), 0x);
> -
> - reg32_write(DDRC_DFIMISC(0), 0x);
> -
> - /* config the DDR PHY's registers */
> - ddr_cfg_phy(dram_timing);
> -
> - do {
> - tmp_t = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) +
> -4 * 0x00020097);
> - } while (tmp_t != 0);
> -
> - reg32_write(DDRC_DFIMISC(0), 0x0020);
> -
> - /* wait DFISTAT.dfi_init_complete to 1 */
> - while (0 == (0x1 & reg32_read(DDRC_DFISTAT(0
> - ;
> -
> - /* clear DFIMISC.dfi_init_complete_en */
> - reg32_write(DDRC_DFIMISC(0), 0x);
> - /* set DFIMISC.dfi_init_complete_en again */
> - reg32_write(DDRC_DFIMISC(0),
Re: [U-Boot] [PATCH v2 05/12] armV7R: K3: am654: Allow using SPL BSS pre-relocation
Hi Simon, On Thu, Aug 08, 2019 at 09:01:03PM +0200, Simon Goldschmidt wrote: > Am 08.08.2019 um 20:29 schrieb Andreas Dannenberg: > > Ok back to my specific scenario, hopefully I'm adding at least some new > > aspects now rather than repeating what was discussed already in different > > threads... > > > > From SPL I'm required to load (and start) our "System Firmware" which is > > a prerequisite for bringing up DDR. We know that DDR bringup itself > > should happen in SPL's board_init_f(), hence the need for loading stuff > > from board_init_f() when no DDR is yet available (only on-chip memory). > > > > I'm using the same loader framework to do the loading from > > board_init_f() that SPL later uses from a board_init_r() context to > > load U-Boot proper, ATF, and other files depending on the platform. > > > Now let's focus on two static variables that play a role in this > > context, 'fat_registered' spl_fat.c and '*mmc' in spl_mmc.c. Those > > static variables are essentially used to remember the initialization > > state of the FAT driver and the MMC loader, so that it doesn't get > > re-initialized the second time those get called (during SPL's main usage > > of loading U-Boot, etc.). So essentially the desire is to carry this > > initialization state from SPL's board_init_f() to board_init_r(). > > OK, so essentially, you've added CONFIG_SPL_EARLY_BSS because FAT and MMC > contain variables in BSS? That would mean we could drop that config option > after fixing those two (given that they can be fixed)? Yes I think I could drop it in this case, I'm not married to CONFIG_SPL_EARLY_BSS in any way. But we still have all the other platforms that use memset() to directly clear BSS from SPL's board_init_f()... Ideally any improvements should be made across the board. (And I just need to throw that out there) one could also imagine moving said platforms to also use CONFIG_SPL_EARLY_BSS (replacing their custom memset approach) to at least unify the approach... > > it), but how could this play in here? Sure I can reserve some memory > > from board_init_f(), or the drivers under discussion, and store the > > initialization state there, but now I'd have the need to carry the > > pointer to that initialization data forward somehow. spl_fat.c is not a > > DM driver, it inherently doesn't have anything I can "tack on" additional > > data fields. I don't quite see how I can make this work more elegantly > > but I'm open to suggestions... > > No, sorry, what I wrote was probably a bit confusing. I wrote that as a > result of my work on socfpga_a10. There, we have the firmware loader > framework loading things e.g. from MMC. During my test of unifying the > socfpga config header files (both gen5 and a10 combined), I stumbled accross > the fact that you cannot use standard malloc in SPL when the devicetree is > initialized during board_init_f as dlmalloc.c makes heavy use of BSS. You > can only use simple malloc there, because its state is kept in 'gd'. > > But it seems that wasn't your problem? > > A next problem with simple malloc is that you can't free anything and I > think I remember code passages around file system loading that make heavy > use of malloc/free. But that again doesn't seem to be your problem here? I had this exact problem initially, as I was loading two files from board_init_f (the "system firmware" and it's config data), which I since consolidated into a FIT image avoiding the issue altogether. The FAT driver specifically is very wasteful allocating 64KB chunks of memory (you can reduce the sector size to alleviate some of that) and with simple malloc it would eat through the little RAM I had too quickly... So for a while I was using full malloc from board_init_f() to make the FAT driver happy. And I had also found I need BSS for that after a little pain and suffering with the JTAG debugger. But this is no longer n issue when only loading one file. > > (Mr. Glass had suggested in one of the threads why I don't do the > > DDR initialization in board_init_r() then, which I experimented with, > > but the changes I had to make to common U-Boot files were rather drastic > > so I abandoned this attempt). > > Yes, I can understand that that's not an ideal way to move forward... > > To come back on the original issue, I'd still propose to add these static > variables to 'gd' or to some sub-struct referenced from 'gd'. I see a high > risk for others to run into these issues that you have hidden for your > platform by enabling CONFIG_SPL_EARLY_BSS. I was always hesitant even thinking about adding stuff to gd due to the large impact so I haven't really considered this as a feasible path. But if we were to go down this road possibly we could add a bitfield variable of some type (to be considerate of memory use) containing a collection of "initialized" flags used by different drivers that really need it? -- Andreas Dannenberg Texas Instruments Inc
Re: [U-Boot] [PATCH 00/11] Aquantia PHY driver updates to reduce FW dependency
On 8/8/2019 7:45 PM, Alex Marginean wrote: The main purpose of this patch series is to allow the AQR driver to run on a larger number of boards without having to use a custom aquantia FW on each of them. Configuration points that are exclusively controlled by PHY firmware are not configured based on phydev->interface as well as new DT node properties. ^ s/not/now/ The patch set introduces a couple of new interface types (XFI and USXGMII), introduces a couple of binding documents and updates the ENETC eth driver to use the new interface types. Alex Marginean (11): include: phy: define XFI and USXGMII interface types include: phy: add data field for private driver data drivers: net: aquantia: use XFI, USXGMII interface types drivers: net: aquantia: add PHY generation information drivers: net: aquantia: set up SI protocol based on interface type drivers: net: aquantia: set MDI reversal based on DT property drivers: net: aquantia: set SMBus addr based on DT property drivers: net: aquantia: use SI and LI status in loop waiting for link up doc: bindings: add bindings document for PHY nodes doc: bindings: Aquantia PHY node binding drivers: net: fsl_enetc: use XFI, USXGMII interface type macros doc/device-tree-bindings/net/aquantia-phy.txt | 25 ++ doc/device-tree-bindings/net/phy.txt | 24 ++ drivers/net/fsl_enetc.c | 2 + drivers/net/phy/aquantia.c| 219 -- include/phy.h | 3 + include/phy_interface.h | 4 + 6 files changed, 263 insertions(+), 14 deletions(-) create mode 100644 doc/device-tree-bindings/net/aquantia-phy.txt create mode 100644 doc/device-tree-bindings/net/phy.txt ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [RFC PATCH 0/2] Add a driver for the Felix Ethernet switch on NXP LS1028A
On 8/8/2019 7:07 PM, Alex Marginean wrote: The driver sets up the switch during probe making external and internal ports available to use. It does not support direct I/O through these switch ports in this version and I'm not sure that is a feature useful in U-Boot. Instead ENETC ethernet interfaces that are internally linked to the switch can be used after the switch is set up. This is where the RFC part comes in. Both the switch as a device and its ports are probed as ethernet devices. That's handy as accessors to connect to the PHY can be used but otherwise they are useful as the user can't ping to these ^ I mean to say useless, not useful :) interfaces. I'd like to get some feedback on whether this is acceptable or instead I should use some other structure for describing the switch and its ports, maybe have a new DM uclass. Other switch devices are registered as PHYs but that's not too useful if the external ports of the switch have PHYs of their own and they need to be driven too. Using a complete DTS the switch looks like this: => dm tree Class Index Probed DriverName --- pci 2 [ + ] pci_generic_ecam |-- pcie@1f000 eth 1 [ + ] enetc_eth | |-- enetc-0 eth 2 [ + ] enetc_eth | |-- enetc-1 eth 3 [ + ] enetc_eth | |-- enetc-2 mdio 5 [ + ] enetc_mdio| |-- emdio-3 pci_generi 0 [ ] pci_generic_drv | |-- pci_3:0.4 eth 4 [ + ] felix_ethsw | |-- felix_ethsw eth 6 [ + ] felix-port| | |-- port@0 eth 7 [ + ] felix-port| | |-- port@1 eth 8 [ + ] felix-port| | |-- port@2 eth 9 [ + ] felix-port| | |-- port@3 eth 10 [ + ] felix-port| | |-- port@4 eth 11 [ + ] felix-port| | `-- port@5 eth 5 [ + ] enetc_eth | |-- enetc-6 pci_generi 1 [ ] pci_generic_drv | `-- pci_3:1f.0 => mdio list felix_ethsw: emdio-3: mdio@50: 0 - Aquantia AQR412 <--> port@0 1 - Aquantia AQR412 <--> port@1 2 - Aquantia AQR412 <--> port@2 3 - Aquantia AQR412 <--> port@3 mdio@00: 5 - AR8035 <--> enetc-1 mdio@40: 2 - Aquantia AQR112 <--> enetc-0 mdio@60: mdio@70: Any feedback is welcome, of course :) Thank you! Alex Depends on https://patchwork.ozlabs.org/project/uboot/list/?series=123813 Alex Marginean (2): drivers: net: Add a driver for the Felix Ethernet switch on NXP LS1028A arm: dts: ls1028a: add node for the integrated Ethernet switch arch/arm/dts/fsl-ls1028a.dtsi | 31 +++ drivers/net/Kconfig | 7 + drivers/net/Makefile | 1 + drivers/net/fsl_enetc.h | 5 + drivers/net/fsl_felix.c | 414 ++ 5 files changed, 458 insertions(+) create mode 100644 drivers/net/fsl_felix.c ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v2 05/12] armV7R: K3: am654: Allow using SPL BSS pre-relocation
Am 08.08.2019 um 20:29 schrieb Andreas Dannenberg: Simon, On Thu, Aug 08, 2019 at 09:29:03AM +0200, Simon Goldschmidt wrote: Hi Andreas, On Wed, Aug 7, 2019 at 11:24 PM Andreas Dannenberg wrote: Hi Simon, thanks for your patience waiting for a response. Please see comments inlined... On Thu, Jul 25, 2019 at 11:52:55AM +0200, Simon Goldschmidt wrote: On Thu, Jul 25, 2019 at 10:23 AM Lokesh Vutla wrote: Hi Simon, On 25/07/19 12:31 PM, Simon Goldschmidt wrote: Hi Lokesh, thanks for following up on this. On Thu, Jul 25, 2019 at 6:36 AM Lokesh Vutla wrote: Hi Tom, On 20/07/19 9:21 PM, Tom Rini wrote: On Fri, Jul 19, 2019 at 07:29:37AM +0200, Simon Goldschmidt wrote: On Fri, Jul 19, 2019 at 2:29 AM Tom Rini wrote: On Tue, Jun 04, 2019 at 05:55:48PM -0500, Andreas Dannenberg wrote: In order to be able to use more advanced driver functionality which often relies on having BSS initialized during early boot prior to relocation several things need to be in place: 1) Memory needs to be available for BSS to use. For this, we locate BSS at the top of the MCU SRAM area, with the stack starting right below it, 2) We need to move the initialization of BSS prior to entering board_init_f(). We will do this with a separate commit by turning on the respective CONFIG option. In this commit we also clean up the assignment of the initial SP address as part of the refactoring, taking into account the pre-decrement post- increment nature in which the SP is used on ARM. Signed-off-by: Andreas Dannenberg Applied to u-boot/master, thanks! Wait, why has this been merged? Unfortunately, I haven't followed this series, but in a discussion about a similar patch I sent [1], using BSS from board_init_f was turned down. And Simon Glass rather convinced me that this is the current API U-Boot has (and is documented in README). So either we must change this API and its documentation (and I would expect the author of this patch to combine the README change with the code change), or this patch would have to be rejected. Again, I'm sorry I only see this now. In thought to remember a discussion in this thread, but I clearly remember that wrong... [1] https://patchwork.ozlabs.org/patch/1057237/ And I had missed that other thread. Lokesh, since I think Andreas is out currently can you expand a little on what we can/can't do on this platform? Thanks! The reason why BSS is needed very early in this platform is for the following reasons: - System co-processor is the central resource manager in SoC and should be loaded and started very early in the boot process. Without that no peripheral or memory can be initialized. So for loading system co-processor image, we only have limited SRAM and a peripheral initialized by ROM. - System co-processor(DMSC) is being represented as remote-core in Device-tree(We are strictly following DM and DT model for the entire SoC). - Since DM is also followed by each peripheral device and remote core, DM should be enabled very early and many peripheral drivers are dependent on BSS usage. So, BSS has been made available very early. Hope this is clear. Let me know if more details are required, I will be happy to explain. Don't get me wrong: I'm not against using BSS early. I just want to ensure this stays consistent throught U-Boot. I understand and agree that it should be consistent. Just discussed this with Andreas, who is courteous enough to update the details in his vacation. We don't have to rush here, I don't have a problem waiting for Andreas to answer when he's back. The reasons you stated still don't make it clear to me *why* bss is needed early. There are other boards using DM early that don't need this. In my opinion, DM drivers normally don't rely on BSS but keep all their state in This statement doesn't hold true for all the drviers. At least the mmc driver uses "initialized" variable stored in BSS to avoid initializing mmc multiple times[0]. In the past we en counted other drivers using it. I guess the idea here is to enable the BSS support generically instead of fixing each of every driver. So this driver is generally not usable in pre-relocation phase? The README document is pretty clear about BSS not being available in board_init_f. I know this text is old, but it seems still valid. And if this is really a workaround because it's easier to use this workaround instead of fixing drivers that invalidly use BSS, is this what we want? heap memory. If you only need BSS early because drivers rely on BSS, you might have to fix those drivers? So, correct me here, why should driver be restricted to not use BSS? Post-relocation drivers might be free to use BSS (although you lose the per-instance storage when using BSS instead of the driver's priv data), but pre-relocation drivers are not. That's the current definition in U-Boot. This patch changes it by adding the option to use BSS early. This bears the danger of code being changed in a
Re: [U-Boot] [PATCH v2] ARM: imx: Support larger SPL size on IMX6DQ
On Thu, Aug 8, 2019 at 1:14 PM Robert Hancock wrote: > > Previously the SPL size on all iMX6 platforms was restricted to 68KB > because the OCRAM size on iMX6SL/DL parts is only 128KB. However, the > other iMX6 variants have 256KB of OCRAM. Add an option > CONFIG_MX6_OCRAM_256KB which allows using the full size on boards which > don't need to support the SL/DL variants. This allows for an SPL size of > 196KB, which makes it much easier to use configurations such as SPL with > driver model and FDT control. > Tested-by: Adam Ford #imx6q_logic > Signed-off-by: Robert Hancock > --- > > Changed since v2: Remove "default n" in Kconfig since that is the default. > > arch/arm/mach-imx/mx6/Kconfig | 9 + > common/spl/Kconfig| 3 ++- > include/configs/imx6_spl.h| 28 ++-- > 3 files changed, 37 insertions(+), 3 deletions(-) > > diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig > index fe5991e..9c27176 100644 > --- a/arch/arm/mach-imx/mx6/Kconfig > +++ b/arch/arm/mach-imx/mx6/Kconfig > @@ -87,6 +87,15 @@ config MX6ULL > select SYSCOUNTER_TIMER > select SYS_L2CACHE_OFF > > +config MX6_OCRAM_256KB > + bool "Support 256KB OCRAM" > + depends on MX6D || MX6Q > + help > +Allows using the full 256KB size of the OCRAM on the MX6Q/MX6D series > +of chips, such as for SPL. The OCRAM of the Lite series of chips is > +only 128KB, so using this option will prevent the resulting code from > +working on those chips. > + > config MX6_DDRCAL > bool "Include dynamic DDR calibration routines" > depends on SPL > diff --git a/common/spl/Kconfig b/common/spl/Kconfig > index 54154b9..c5ad047 100644 > --- a/common/spl/Kconfig > +++ b/common/spl/Kconfig > @@ -28,7 +28,8 @@ config SPL_FRAMEWORK > config SPL_SIZE_LIMIT > int "Maximum size of SPL image" > depends on SPL > - default 69632 if ARCH_MX6 > + default 69632 if ARCH_MX6 && !MX6_OCRAM_256KB > + default 200704 if ARCH_MX6 && MX6_OCRAM_256KB > default 0 > help > Specifies the maximum length of the U-Boot SPL image. > diff --git a/include/configs/imx6_spl.h b/include/configs/imx6_spl.h > index 212dee7..a223930 100644 > --- a/include/configs/imx6_spl.h > +++ b/include/configs/imx6_spl.h > @@ -7,10 +7,32 @@ > #define __IMX6_SPL_CONFIG_H > > #ifdef CONFIG_SPL > + > +#ifdef CONFIG_MX6_OCRAM_256KB > /* > - * see Figure 8-3 in IMX6DQ/IMX6SDL Reference manuals: > + * see Figure 8.4.1 in IMX6DQ Reference manuals: > + * - IMX6DQ OCRAM (IRAM) is from 0x00907000 to 0x0093 > + * - BOOT ROM stack is at 0x0093FFB8 > + * - if icache/dcache is enabled (eFuse/strapping controlled) then the > + *IMX BOOT ROM will setup MMU table at 0x00938000, therefore we need to > + *fit between 0x00907000 and 0x00938000. > + * - Additionally the BOOT ROM loads what they consider the firmware image > + *which consists of a 4K header in front of us that contains the IVT, DCD > + *and some padding thus 'our' max size is really 0x00908000 - 0x00938000 > + *or 192KB > + */ > +#define CONFIG_SPL_MAX_SIZE0x3 > +#define CONFIG_SPL_STACK 0x0093FFB8 > +/* > + * Pad SPL to 196KB (4KB header + 192KB max size). This allows to write the > + * SPL/U-Boot combination generated with u-boot-with-spl.imx directly to a > + * boot media (given that boot media specific offset is configured properly). > + */ > +#define CONFIG_SPL_PAD_TO 0x31000 > +#else > +/* > + * see Figure 8-3 in IMX6SDL Reference manuals: > * - IMX6SDL OCRAM (IRAM) is from 0x00907000 to 0x0091 > - * - IMX6DQ has 2x IRAM of IMX6SDL but we intend to support IMX6SDL as well > * - BOOT ROM stack is at 0x0091FFB8 > * - if icache/dcache is enabled (eFuse/strapping controlled) then the > *IMX BOOT ROM will setup MMU table at 0x00918000, therefore we need to > @@ -29,6 +51,8 @@ > */ > #define CONFIG_SPL_PAD_TO 0x11000 > > +#endif > + > /* MMC support */ > #if defined(CONFIG_SPL_MMC_SUPPORT) > #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 > -- > 1.8.3.1 > ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v2 05/12] armV7R: K3: am654: Allow using SPL BSS pre-relocation
Simon, On Thu, Aug 08, 2019 at 09:29:03AM +0200, Simon Goldschmidt wrote: > Hi Andreas, > > On Wed, Aug 7, 2019 at 11:24 PM Andreas Dannenberg wrote: > > > > Hi Simon, > > thanks for your patience waiting for a response. Please see comments > > inlined... > > > > On Thu, Jul 25, 2019 at 11:52:55AM +0200, Simon Goldschmidt wrote: > > > On Thu, Jul 25, 2019 at 10:23 AM Lokesh Vutla wrote: > > > > > > > > Hi Simon, > > > > > > > > On 25/07/19 12:31 PM, Simon Goldschmidt wrote: > > > > > Hi Lokesh, > > > > > > > > > > thanks for following up on this. > > > > > > > > > > On Thu, Jul 25, 2019 at 6:36 AM Lokesh Vutla > > > > > wrote: > > > > >> > > > > >> Hi Tom, > > > > >> > > > > >> On 20/07/19 9:21 PM, Tom Rini wrote: > > > > >>> On Fri, Jul 19, 2019 at 07:29:37AM +0200, Simon Goldschmidt wrote: > > > > On Fri, Jul 19, 2019 at 2:29 AM Tom Rini > > > > wrote: > > > > > > > > > > On Tue, Jun 04, 2019 at 05:55:48PM -0500, Andreas Dannenberg > > > > > wrote: > > > > > > > > > >> In order to be able to use more advanced driver functionality > > > > >> which often > > > > >> relies on having BSS initialized during early boot prior to > > > > >> relocation > > > > >> several things need to be in place: > > > > >> > > > > >> 1) Memory needs to be available for BSS to use. For this, we > > > > >> locate BSS > > > > >>at the top of the MCU SRAM area, with the stack starting > > > > >> right below > > > > >>it, > > > > >> 2) We need to move the initialization of BSS prior to entering > > > > >>board_init_f(). We will do this with a separate commit by > > > > >> turning on > > > > >>the respective CONFIG option. > > > > >> > > > > >> In this commit we also clean up the assignment of the initial SP > > > > >> address > > > > >> as part of the refactoring, taking into account the > > > > >> pre-decrement post- > > > > >> increment nature in which the SP is used on ARM. > > > > >> > > > > >> Signed-off-by: Andreas Dannenberg > > > > > > > > > > Applied to u-boot/master, thanks! > > > > > > > > Wait, why has this been merged? Unfortunately, I haven't followed > > > > this series, > > > > but in a discussion about a similar patch I sent [1], using BSS > > > > from > > > > board_init_f > > > > was turned down. And Simon Glass rather convinced me that this is > > > > the current > > > > API U-Boot has (and is documented in README). > > > > > > > > So either we must change this API and its documentation (and I > > > > would expect the > > > > author of this patch to combine the README change with the code > > > > change), or this > > > > patch would have to be rejected. > > > > > > > > Again, I'm sorry I only see this now. In thought to remember a > > > > discussion in this > > > > thread, but I clearly remember that wrong... > > > > > > > > [1] https://patchwork.ozlabs.org/patch/1057237/ > > > > >>> > > > > >>> And I had missed that other thread. Lokesh, since I think Andreas > > > > >>> is > > > > >>> out currently can you expand a little on what we can/can't do on > > > > >>> this > > > > >>> platform? Thanks! > > > > >> > > > > >> The reason why BSS is needed very early in this platform is for the > > > > >> following > > > > >> reasons: > > > > >> - System co-processor is the central resource manager in SoC and > > > > >> should be > > > > >> loaded and started very early in the boot process. Without that no > > > > >> peripheral or > > > > >> memory can be initialized. So for loading system co-processor image, > > > > >> we only > > > > >> have limited SRAM and a peripheral initialized by ROM. > > > > >> - System co-processor(DMSC) is being represented as remote-core in > > > > >> Device-tree(We are strictly following DM and DT model for the entire > > > > >> SoC). > > > > >> - Since DM is also followed by each peripheral device and remote > > > > >> core, DM should > > > > >> be enabled very early and many peripheral drivers are dependent on > > > > >> BSS usage. > > > > >> So, BSS has been made available very early. > > > > >> > > > > >> Hope this is clear. Let me know if more details are required, I will > > > > >> be happy to > > > > >> explain. > > > > > > > > > > Don't get me wrong: I'm not against using BSS early. I just want to > > > > > ensure this > > > > > stays consistent throught U-Boot. > > > > > > > > I understand and agree that it should be consistent. Just discussed > > > > this with > > > > Andreas, who is courteous enough to update the details in his vacation. > > > > > > We don't have to rush here, I don't have a problem waiting for Andreas to > > > answer when he's back. > > > > > > > > > > > > > > > > > The reasons you stated still don't make it clear to me *why* bss is > > > > > needed > > > > > early. There are other
Re: [U-Boot] [PATCH] README: Clarify use of BSS during SPL board_init_f()
Am 08.08.2019 um 19:54 schrieb Andreas Dannenberg:
The earlier commit
commit a5a5d997b41a ("spl: Allow performing BSS init early before
board_init_f()")
...introduced the ability to use BSS from SPL's board_init_f() as it may
be required in certain exceptional use cases so go ahead and update the
README to reflect this change. Note that as highlighted with the changes
the use of the associated CONFIG option is generally not recommended.
Signed-off-by: Andreas Dannenberg
Since I expect the patch adding CONFIG_SPL_EARLY_BSS will stay with us:
Reviewed-by: Simon Goldschmidt
Still, I'd be very happy if someone could come up with an idea of how we
can detect usage of BSS before board_init_r. And patches fixing such
invalid usage would be cool as well.
Regards,
Simon
---
Simon, as per separate discussion thread here is a proposal for an
update to the README. I tried to limit the changes to the what I
thought was the most relevant section (the details section) of the
document to strike a balance between documenting it and limiting the
amount of attention drawn to it...
--
Andreas Dannenberg
Texas Instruments Inc
README | 7 +++
1 file changed, 7 insertions(+)
diff --git a/README b/README
index b493ffeb2d..be3805689e 100644
--- a/README
+++ b/README
@@ -267,6 +267,13 @@ board_init_f():
- preloader_console_init() can be called here in extremis
- should set up SDRAM, and anything needed to make the UART work
- these is no need to clear BSS, it will be done by crt0.S
+ - for specific scenarios on certain architectures an early BSS *can*
+ be made available (via CONFIG_SPL_EARLY_BSS by moving the clearing
+ of BSS prior to entering board_init_f()) but doing so is discouraged.
+ Instead it is strongly recommended to architect any code changes
+ or additions such to not depend on the availability of BSS during
+ board_init_f() as indicated in other sections of this README to
+ maintain compatibility and consistency across the entire code base.
- must return normally from this function (don't call board_init_r()
directly)
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v2] ARM: imx: Support larger SPL size on IMX6DQ
Previously the SPL size on all iMX6 platforms was restricted to 68KB because the OCRAM size on iMX6SL/DL parts is only 128KB. However, the other iMX6 variants have 256KB of OCRAM. Add an option CONFIG_MX6_OCRAM_256KB which allows using the full size on boards which don't need to support the SL/DL variants. This allows for an SPL size of 196KB, which makes it much easier to use configurations such as SPL with driver model and FDT control. Signed-off-by: Robert Hancock --- Changed since v2: Remove "default n" in Kconfig since that is the default. arch/arm/mach-imx/mx6/Kconfig | 9 + common/spl/Kconfig| 3 ++- include/configs/imx6_spl.h| 28 ++-- 3 files changed, 37 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig index fe5991e..9c27176 100644 --- a/arch/arm/mach-imx/mx6/Kconfig +++ b/arch/arm/mach-imx/mx6/Kconfig @@ -87,6 +87,15 @@ config MX6ULL select SYSCOUNTER_TIMER select SYS_L2CACHE_OFF +config MX6_OCRAM_256KB + bool "Support 256KB OCRAM" + depends on MX6D || MX6Q + help +Allows using the full 256KB size of the OCRAM on the MX6Q/MX6D series +of chips, such as for SPL. The OCRAM of the Lite series of chips is +only 128KB, so using this option will prevent the resulting code from +working on those chips. + config MX6_DDRCAL bool "Include dynamic DDR calibration routines" depends on SPL diff --git a/common/spl/Kconfig b/common/spl/Kconfig index 54154b9..c5ad047 100644 --- a/common/spl/Kconfig +++ b/common/spl/Kconfig @@ -28,7 +28,8 @@ config SPL_FRAMEWORK config SPL_SIZE_LIMIT int "Maximum size of SPL image" depends on SPL - default 69632 if ARCH_MX6 + default 69632 if ARCH_MX6 && !MX6_OCRAM_256KB + default 200704 if ARCH_MX6 && MX6_OCRAM_256KB default 0 help Specifies the maximum length of the U-Boot SPL image. diff --git a/include/configs/imx6_spl.h b/include/configs/imx6_spl.h index 212dee7..a223930 100644 --- a/include/configs/imx6_spl.h +++ b/include/configs/imx6_spl.h @@ -7,10 +7,32 @@ #define __IMX6_SPL_CONFIG_H #ifdef CONFIG_SPL + +#ifdef CONFIG_MX6_OCRAM_256KB /* - * see Figure 8-3 in IMX6DQ/IMX6SDL Reference manuals: + * see Figure 8.4.1 in IMX6DQ Reference manuals: + * - IMX6DQ OCRAM (IRAM) is from 0x00907000 to 0x0093 + * - BOOT ROM stack is at 0x0093FFB8 + * - if icache/dcache is enabled (eFuse/strapping controlled) then the + *IMX BOOT ROM will setup MMU table at 0x00938000, therefore we need to + *fit between 0x00907000 and 0x00938000. + * - Additionally the BOOT ROM loads what they consider the firmware image + *which consists of a 4K header in front of us that contains the IVT, DCD + *and some padding thus 'our' max size is really 0x00908000 - 0x00938000 + *or 192KB + */ +#define CONFIG_SPL_MAX_SIZE0x3 +#define CONFIG_SPL_STACK 0x0093FFB8 +/* + * Pad SPL to 196KB (4KB header + 192KB max size). This allows to write the + * SPL/U-Boot combination generated with u-boot-with-spl.imx directly to a + * boot media (given that boot media specific offset is configured properly). + */ +#define CONFIG_SPL_PAD_TO 0x31000 +#else +/* + * see Figure 8-3 in IMX6SDL Reference manuals: * - IMX6SDL OCRAM (IRAM) is from 0x00907000 to 0x0091 - * - IMX6DQ has 2x IRAM of IMX6SDL but we intend to support IMX6SDL as well * - BOOT ROM stack is at 0x0091FFB8 * - if icache/dcache is enabled (eFuse/strapping controlled) then the *IMX BOOT ROM will setup MMU table at 0x00918000, therefore we need to @@ -29,6 +51,8 @@ */ #define CONFIG_SPL_PAD_TO 0x11000 +#endif + /* MMC support */ #if defined(CONFIG_SPL_MMC_SUPPORT) #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 -- 1.8.3.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH] README: Clarify use of BSS during SPL board_init_f()
The earlier commit
commit a5a5d997b41a ("spl: Allow performing BSS init early before
board_init_f()")
...introduced the ability to use BSS from SPL's board_init_f() as it may
be required in certain exceptional use cases so go ahead and update the
README to reflect this change. Note that as highlighted with the changes
the use of the associated CONFIG option is generally not recommended.
Signed-off-by: Andreas Dannenberg
---
Simon, as per separate discussion thread here is a proposal for an
update to the README. I tried to limit the changes to the what I
thought was the most relevant section (the details section) of the
document to strike a balance between documenting it and limiting the
amount of attention drawn to it...
--
Andreas Dannenberg
Texas Instruments Inc
README | 7 +++
1 file changed, 7 insertions(+)
diff --git a/README b/README
index b493ffeb2d..be3805689e 100644
--- a/README
+++ b/README
@@ -267,6 +267,13 @@ board_init_f():
- preloader_console_init() can be called here in extremis
- should set up SDRAM, and anything needed to make the UART work
- these is no need to clear BSS, it will be done by crt0.S
+ - for specific scenarios on certain architectures an early BSS *can*
+ be made available (via CONFIG_SPL_EARLY_BSS by moving the clearing
+ of BSS prior to entering board_init_f()) but doing so is discouraged.
+ Instead it is strongly recommended to architect any code changes
+ or additions such to not depend on the availability of BSS during
+ board_init_f() as indicated in other sections of this README to
+ maintain compatibility and consistency across the entire code base.
- must return normally from this function (don't call board_init_r()
directly)
--
2.17.1
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 04/11] drivers: net: aquantia: add PHY generation information
Uses the data field in phy_driver structure to identify the PHY generation.
This is useful for custom configuration as non-generic PHY registers are
not 100% compatible between generations.
Signed-off-by: Alex Marginean
---
drivers/net/phy/aquantia.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/net/phy/aquantia.c b/drivers/net/phy/aquantia.c
index 9dda87c4c9..6425ba2021 100644
--- a/drivers/net/phy/aquantia.c
+++ b/drivers/net/phy/aquantia.c
@@ -69,6 +69,12 @@
#define VERSION_STRING_OFFSET 0x0200
#define HEADER_OFFSET 0x300
+/* driver private data */
+#define AQUANTIA_NA0
+#define AQUANTIA_GEN1 1
+#define AQUANTIA_GEN2 2
+#define AQUANTIA_GEN3 3
+
#pragma pack(1)
struct fw_header {
u8 padding[4];
@@ -453,6 +459,7 @@ struct phy_driver aqr105_driver = {
.config = _config,
.startup = _startup,
.shutdown = _shutdown,
+ .data = AQUANTIA_GEN1,
};
struct phy_driver aqr106_driver = {
@@ -479,6 +486,7 @@ struct phy_driver aqr107_driver = {
.config = _config,
.startup = _startup,
.shutdown = _shutdown,
+ .data = AQUANTIA_GEN2,
};
struct phy_driver aqr112_driver = {
@@ -492,6 +500,7 @@ struct phy_driver aqr112_driver = {
.config = _config,
.startup = _startup,
.shutdown = _shutdown,
+ .data = AQUANTIA_GEN3,
};
struct phy_driver aqr405_driver = {
@@ -505,6 +514,7 @@ struct phy_driver aqr405_driver = {
.config = _config,
.startup = _startup,
.shutdown = _shutdown,
+ .data = AQUANTIA_GEN1,
};
struct phy_driver aqr412_driver = {
@@ -518,6 +528,7 @@ struct phy_driver aqr412_driver = {
.config = _config,
.startup = _startup,
.shutdown = _shutdown,
+ .data = AQUANTIA_GEN3,
};
int phy_aquantia_init(void)
--
2.17.1
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 02/11] include: phy: add data field for private driver data
This is useful to carry custom information between the driver structure
associated with a specific HW and the driver code.
Signed-off-by: Alex Marginean
---
include/phy.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/include/phy.h b/include/phy.h
index f4530faeb9..58455d6493 100644
--- a/include/phy.h
+++ b/include/phy.h
@@ -110,6 +110,9 @@ struct phy_driver {
u16 val);
struct list_head list;
+
+ /* driver private data */
+ ulong data;
};
struct phy_device {
--
2.17.1
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 07/11] drivers: net: aquantia: set SMBus addr based on DT property
Aquantia PHYs have a SMBus interface mostly used for debug. The addresses
on this interface are normally set up by PHY firmware, but depending on the
board they may end up not being unique. Add an optional DT property used
to change SMBus address if needed.
Signed-off-by: Alex Marginean
---
drivers/net/phy/aquantia.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/drivers/net/phy/aquantia.c b/drivers/net/phy/aquantia.c
index 62a4d1ea6e..34df069f97 100644
--- a/drivers/net/phy/aquantia.c
+++ b/drivers/net/phy/aquantia.c
@@ -91,6 +91,9 @@
#define AQUANTIA_VND1_GSYSCFG_5G 3
#define AQUANTIA_VND1_GSYSCFG_10G 4
+#define AQUANTIA_VND1_SMBUS0 0xc485
+#define AQUANTIA_VND1_SMBUS1 0xc495
+
/* addresses of memory segments in the phy */
#define DRAM_BASE_ADDR 0x3FFE
#define IRAM_BASE_ADDR 0x4000
@@ -356,6 +359,18 @@ static int aquantia_dts_config(struct phy_device *phydev)
phy_write(phydev, MDIO_MMD_PMAPMD, AQUANTIA_PMA_RX_VENDOR_P1,
reg);
}
+ if (!ofnode_read_u32(node, "smb-addr", )) {
+ debug("smb-addr = %x\n", (int)prop);
+ /*
+* there are two addresses here, normally just one bus would
+* be in use so we're setting both regs using the same DT
+* property.
+*/
+ phy_write(phydev, MDIO_MMD_VEND1, AQUANTIA_VND1_SMBUS0,
+ (u16)(prop << 1));
+ phy_write(phydev, MDIO_MMD_VEND1, AQUANTIA_VND1_SMBUS1,
+ (u16)(prop << 1));
+ }
#endif
return 0;
--
2.17.1
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 08/11] drivers: net: aquantia: use SI and LI status in loop waiting for link up
In some cases the link on the system interface of the aquantia PHY comes up
after the link on line interface. The link state loop only checks the line
side, which may result in first packet sent being lost.
Use aquantia_link_is_up instead, which checks both system and line side on
gen 2/3 PHYs to avoid losing the 1st packet.
Signed-off-by: Alex Marginean
---
drivers/net/phy/aquantia.c | 7 ++-
1 file changed, 2 insertions(+), 5 deletions(-)
diff --git a/drivers/net/phy/aquantia.c b/drivers/net/phy/aquantia.c
index 34df069f97..70180e3e4e 100644
--- a/drivers/net/phy/aquantia.c
+++ b/drivers/net/phy/aquantia.c
@@ -543,17 +543,14 @@ int aquantia_startup(struct phy_device *phydev)
phydev->duplex = DUPLEX_FULL;
/* if the AN is still in progress, wait till timeout. */
- phy_read(phydev, MDIO_MMD_AN, MDIO_STAT1);
- reg = phy_read(phydev, MDIO_MMD_AN, MDIO_STAT1);
- if (!(reg & MDIO_AN_STAT1_COMPLETE)) {
+ if (!aquantia_link_is_up(phydev)) {
printf("%s Waiting for PHY auto negotiation to complete",
phydev->dev->name);
do {
udelay(1000);
- reg = phy_read(phydev, MDIO_MMD_AN, MDIO_STAT1);
if ((i++ % 500) == 0)
printf(".");
- } while (!(reg & MDIO_AN_STAT1_COMPLETE) &&
+ } while (!aquantia_link_is_up(phydev) &&
i < (4 * PHY_ANEG_TIMEOUT));
if (i > PHY_ANEG_TIMEOUT)
--
2.17.1
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 06/11] drivers: net: aquantia: set MDI reversal based on DT property
MDI pins up to the RJ45 connector may be reversed on the board and the
default PHY configuration applied by firmware may or may not match that.
Add an optional DT property to configure MDI reversal for this case.
Signed-off-by: Alex Marginean
---
drivers/net/phy/aquantia.c | 39 ++
1 file changed, 39 insertions(+)
diff --git a/drivers/net/phy/aquantia.c b/drivers/net/phy/aquantia.c
index ab165e76f5..62a4d1ea6e 100644
--- a/drivers/net/phy/aquantia.c
+++ b/drivers/net/phy/aquantia.c
@@ -64,6 +64,13 @@
#define UP_RUN_STALL_OVERRIDE BIT(6)
#define UP_RUN_STALL BIT(0)
+#define AQUANTIA_PMA_RX_VENDOR_P1 0xe400
+#define AQUANTIA_PMA_RX_VENDOR_P1_MDI_MSK GENMASK(1, 0)
+/* MDI reversal configured through registers */
+#define AQUANTIA_PMA_RX_VENDOR_P1_MDI_CFG BIT(1)
+/* MDI reversal enabled */
+#define AQUANTIA_PMA_RX_VENDOR_P1_MDI_REV BIT(0)
+
/*
* global start rate, the protocol associated with this speed is used by
default
* on SI.
@@ -324,6 +331,36 @@ static int aquantia_set_proto(struct phy_device *phydev,
int if_type)
return 0;
}
+static int aquantia_dts_config(struct phy_device *phydev)
+{
+#ifdef CONFIG_OF_CONTROL
+ ofnode node = phydev->node;
+ u32 prop;
+ u16 reg;
+
+ /* this code only works on gen2 and gen3 PHYs */
+ if (phydev->drv->data != AQUANTIA_GEN2 &&
+ phydev->drv->data != AQUANTIA_GEN3)
+ return -ENOTSUPP;
+
+ if (!ofnode_valid(node))
+ return 0;
+
+ if (!ofnode_read_u32(node, "mdi-reversal", )) {
+ debug("mdi-reversal = %d\n", (int)prop);
+ reg = phy_read(phydev, MDIO_MMD_PMAPMD,
+ AQUANTIA_PMA_RX_VENDOR_P1);
+ reg &= ~AQUANTIA_PMA_RX_VENDOR_P1_MDI_MSK;
+ reg |= AQUANTIA_PMA_RX_VENDOR_P1_MDI_CFG;
+ reg |= prop ? AQUANTIA_PMA_RX_VENDOR_P1_MDI_REV : 0;
+ phy_write(phydev, MDIO_MMD_PMAPMD, AQUANTIA_PMA_RX_VENDOR_P1,
+ reg);
+ }
+
+#endif
+ return 0;
+}
+
static bool aquantia_link_is_up(struct phy_device *phydev)
{
u16 reg, regmask;
@@ -403,6 +440,8 @@ int aquantia_config(struct phy_device *phydev)
/* configure protocol based on phydev->interface */
aquantia_set_proto(phydev, if_type);
+ /* apply custom configuration based on DT */
+ aquantia_dts_config(phydev);
/* wake PHY back up */
phy_write(phydev, MDIO_MMD_VEND1, AQUANTIA_VND1_GLOBAL_SC, 0);
--
2.17.1
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 05/11] drivers: net: aquantia: set up SI protocol based on interface type
If PHY is not ready for data by the time _config is called, reconfigure the
PHY system interface to use the proper protocol based on phydev->interface,
just in case the defaults set by PHY firmware don't match current
configuration.
Signed-off-by: Razvan Ionut Cirjan
Signed-off-by: Alex Marginean
---
drivers/net/phy/aquantia.c | 109 +
1 file changed, 109 insertions(+)
diff --git a/drivers/net/phy/aquantia.c b/drivers/net/phy/aquantia.c
index 6425ba2021..ab165e76f5 100644
--- a/drivers/net/phy/aquantia.c
+++ b/drivers/net/phy/aquantia.c
@@ -21,6 +21,7 @@
#define AQUNTIA_SPEED_MSB_MASK 0x40
#define AQUANTIA_SYSTEM_INTERFACE_SR 0xe812
+#define AQUANTIA_SYSTEM_INTERFACE_SR_READYBIT(0)
#define AQUANTIA_VENDOR_PROVISIONING_REG 0xC441
#define AQUANTIA_FIRMWARE_ID0x20
#define AQUANTIA_RESERVED_STATUS0xc885
@@ -33,6 +34,9 @@
#define AQUANTIA_SI_USXGMII 0x0018
/* registers in MDIO_MMD_VEND1 region */
+#define AQUANTIA_VND1_GLOBAL_SC0x000
+#define AQUANTIA_VND1_GLOBAL_SC_LPBIT(0xb)
+
#define GLOBAL_FIRMWARE_ID 0x20
#define GLOBAL_FAULT 0xc850
#define GLOBAL_RSTATUS_1 0xc885
@@ -60,6 +64,26 @@
#define UP_RUN_STALL_OVERRIDE BIT(6)
#define UP_RUN_STALL BIT(0)
+/*
+ * global start rate, the protocol associated with this speed is used by
default
+ * on SI.
+ */
+#define AQUANTIA_VND1_GSTART_RATE 0x31a
+#define AQUANTIA_VND1_GSTART_RATE_OFF 0
+#define AQUANTIA_VND1_GSTART_RATE_100M1
+#define AQUANTIA_VND1_GSTART_RATE_1G 2
+#define AQUANTIA_VND1_GSTART_RATE_10G 3
+#define AQUANTIA_VND1_GSTART_RATE_2_5G4
+#define AQUANTIA_VND1_GSTART_RATE_5G 5
+
+/* SYSCFG registers for 100M, 1G, 2.5G, 5G, 10G */
+#define AQUANTIA_VND1_GSYSCFG_BASE 0x31b
+#define AQUANTIA_VND1_GSYSCFG_100M 0
+#define AQUANTIA_VND1_GSYSCFG_1G 1
+#define AQUANTIA_VND1_GSYSCFG_2_5G 2
+#define AQUANTIA_VND1_GSYSCFG_5G 3
+#define AQUANTIA_VND1_GSYSCFG_10G 4
+
/* addresses of memory segments in the phy */
#define DRAM_BASE_ADDR 0x3FFE
#define IRAM_BASE_ADDR 0x4000
@@ -260,6 +284,72 @@ static int aquantia_upload_firmware(struct phy_device
*phydev)
}
#endif
+struct {
+ u16 syscfg;
+ int cnt;
+ u16 start_rate;
+} aquantia_syscfg[PHY_INTERFACE_MODE_COUNT] = {
+ [PHY_INTERFACE_MODE_SGMII] = {0x04b, AQUANTIA_VND1_GSYSCFG_1G,
+ AQUANTIA_VND1_GSTART_RATE_1G},
+ [PHY_INTERFACE_MODE_SGMII_2500] = {0x144, AQUANTIA_VND1_GSYSCFG_2_5G,
+ AQUANTIA_VND1_GSTART_RATE_2_5G},
+ [PHY_INTERFACE_MODE_XGMII] = {0x100, AQUANTIA_VND1_GSYSCFG_10G,
+ AQUANTIA_VND1_GSTART_RATE_10G},
+ [PHY_INTERFACE_MODE_XFI] ={0x100, AQUANTIA_VND1_GSYSCFG_10G,
+ AQUANTIA_VND1_GSTART_RATE_10G},
+ [PHY_INTERFACE_MODE_USXGMII] ={0x080, AQUANTIA_VND1_GSYSCFG_10G,
+ AQUANTIA_VND1_GSTART_RATE_10G},
+};
+
+static int aquantia_set_proto(struct phy_device *phydev, int if_type)
+{
+ int i;
+
+ /* this code only works on gen2 and gen3 PHYs */
+ if (phydev->drv->data != AQUANTIA_GEN2 &&
+ phydev->drv->data != AQUANTIA_GEN3)
+ return -ENOTSUPP;
+
+ if (!aquantia_syscfg[if_type].cnt)
+ return 0;
+
+ /* set the default rate to enable the SI link */
+ phy_write(phydev, MDIO_MMD_VEND1, AQUANTIA_VND1_GSTART_RATE,
+ aquantia_syscfg[if_type].start_rate);
+
+ for (i = 0; i <= aquantia_syscfg[if_type].cnt; i++)
+ phy_write(phydev, MDIO_MMD_VEND1,
+ AQUANTIA_VND1_GSYSCFG_BASE + i,
+ aquantia_syscfg[if_type].syscfg);
+ return 0;
+}
+
+static bool aquantia_link_is_up(struct phy_device *phydev)
+{
+ u16 reg, regmask;
+ int devad, regnum;
+
+ /*
+* On Gen 2 and 3 we have a bit that indicates that both system and
+* line side are ready for data, use that if possible.
+*/
+ if (phydev->drv->data == AQUANTIA_GEN2 ||
+ phydev->drv->data == AQUANTIA_GEN3) {
+ devad = MDIO_MMD_PHYXS;
+ regnum = AQUANTIA_SYSTEM_INTERFACE_SR;
+ regmask = AQUANTIA_SYSTEM_INTERFACE_SR_READY;
+ } else {
+ devad = MDIO_MMD_AN;
+ regnum = MDIO_STAT1;
+ regmask = MDIO_AN_STAT1_COMPLETE;
+ }
+ /* the register should be latched, do a double read */
+ phy_read(phydev, devad, regnum);
+ reg = phy_read(phydev, devad, regnum);
+
+ return !!(reg & regmask);
+}
+
int aquantia_config(struct phy_device *phydev)
{
int if_type = phydev->interface;
[U-Boot] [PATCH 03/11] drivers: net: aquantia: use XFI, USXGMII interface types
The PHY supports XFI and USXGMII, the notable difference being that USX AN
is enabled for USXGMII. Legacy code uses XGMII for any 10G proto and
detects whether USX AN should be enabled or not using a PHY status
register. Keep that functionality too, so we don't break existing drivers.
Signed-off-by: Razvan Ionut Cirjan
Signed-off-by: Alex Marginean
---
drivers/net/phy/aquantia.c | 38 +-
1 file changed, 29 insertions(+), 9 deletions(-)
diff --git a/drivers/net/phy/aquantia.c b/drivers/net/phy/aquantia.c
index 465ec2d342..9dda87c4c9 100644
--- a/drivers/net/phy/aquantia.c
+++ b/drivers/net/phy/aquantia.c
@@ -256,8 +256,10 @@ static int aquantia_upload_firmware(struct phy_device
*phydev)
int aquantia_config(struct phy_device *phydev)
{
+ int if_type = phydev->interface;
u32 val, id, rstatus, fault;
u32 reg_val1 = 0;
+ int usx_an = 0;
id = phy_read(phydev, MDIO_MMD_VEND1, GLOBAL_FIRMWARE_ID);
rstatus = phy_read(phydev, MDIO_MMD_VEND1, GLOBAL_RSTATUS_1);
@@ -278,17 +280,35 @@ int aquantia_config(struct phy_device *phydev)
if (ret != 0)
return ret;
}
+ /*
+* for backward compatibility convert XGMII into either XFI or USX based
+* on FW config
+*/
+ if (if_type == PHY_INTERFACE_MODE_XGMII) {
+ reg_val1 = phy_read(phydev, MDIO_MMD_PHYXS,
+ AQUANTIA_SYSTEM_INTERFACE_SR);
+ if ((reg_val1 & AQUANTIA_SI_IN_USE_MASK) == AQUANTIA_SI_USXGMII)
+ if_type = PHY_INTERFACE_MODE_USXGMII;
+ else
+ if_type = PHY_INTERFACE_MODE_XFI;
+ }
+
val = phy_read(phydev, MDIO_MMD_PMAPMD, MII_BMCR);
- if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
+ switch (if_type) {
+ case PHY_INTERFACE_MODE_SGMII:
/* 1000BASE-T mode */
phydev->advertising = SUPPORTED_1000baseT_Full;
phydev->supported = phydev->advertising;
val = (val & ~AQUNTIA_SPEED_LSB_MASK) | AQUNTIA_SPEED_MSB_MASK;
phy_write(phydev, MDIO_MMD_PMAPMD, MII_BMCR, val);
- } else if (phydev->interface == PHY_INTERFACE_MODE_XGMII) {
+ break;
+ case PHY_INTERFACE_MODE_USXGMII:
+ usx_an = 1;
+ /* FALLTHROUGH */
+ case PHY_INTERFACE_MODE_XFI:
/* 10GBASE-T mode */
phydev->advertising = SUPPORTED_1baseT_Full;
phydev->supported = phydev->advertising;
@@ -299,10 +319,8 @@ int aquantia_config(struct phy_device *phydev)
AQUNTIA_SPEED_LSB_MASK |
AQUNTIA_SPEED_MSB_MASK);
- val = phy_read(phydev, MDIO_MMD_PHYXS,
- AQUANTIA_SYSTEM_INTERFACE_SR);
/* If SI is USXGMII then start USXGMII autoneg */
- if ((val & AQUANTIA_SI_IN_USE_MASK) == AQUANTIA_SI_USXGMII) {
+ if (usx_an) {
reg_val1 = phy_read(phydev, MDIO_MMD_PHYXS,
AQUANTIA_VENDOR_PROVISIONING_REG);
@@ -317,22 +335,24 @@ int aquantia_config(struct phy_device *phydev)
printf("%s: system interface XFI\n",
phydev->dev->name);
}
-
- } else if (phydev->interface == PHY_INTERFACE_MODE_SGMII_2500) {
+ break;
+ case PHY_INTERFACE_MODE_SGMII_2500:
/* 2.5GBASE-T mode */
phydev->advertising = SUPPORTED_1000baseT_Full;
phydev->supported = phydev->advertising;
phy_write(phydev, MDIO_MMD_AN, AQUNTIA_10G_CTL, 1);
phy_write(phydev, MDIO_MMD_AN, AQUNTIA_VENDOR_P1, 0x9440);
- } else if (phydev->interface == PHY_INTERFACE_MODE_MII) {
+ break;
+ case PHY_INTERFACE_MODE_MII:
/* 100BASE-TX mode */
phydev->advertising = SUPPORTED_100baseT_Full;
phydev->supported = phydev->advertising;
val = (val & ~AQUNTIA_SPEED_MSB_MASK) | AQUNTIA_SPEED_LSB_MASK;
phy_write(phydev, MDIO_MMD_PMAPMD, MII_BMCR, val);
- }
+ break;
+ };
val = phy_read(phydev, MDIO_MMD_VEND1, AQUANTIA_RESERVED_STATUS);
reg_val1 = phy_read(phydev, MDIO_MMD_VEND1, AQUANTIA_FIRMWARE_ID);
--
2.17.1
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 11/11] drivers: net: fsl_enetc: use XFI, USXGMII interface type macros
Apply 10G PCS init for USXGMII, XFI interface types. Signed-off-by: Alex Marginean --- drivers/net/fsl_enetc.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/net/fsl_enetc.c b/drivers/net/fsl_enetc.c index 145d66bb16..a4472c7c50 100644 --- a/drivers/net/fsl_enetc.c +++ b/drivers/net/fsl_enetc.c @@ -194,6 +194,8 @@ static void enetc_start_pcs(struct udevice *dev) enetc_init_rgmii(dev); break; case PHY_INTERFACE_MODE_XGMII: + case PHY_INTERFACE_MODE_USXGMII: + case PHY_INTERFACE_MODE_XFI: enetc_init_sxgmii(dev); break; }; -- 2.17.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 09/11] doc: bindings: add bindings document for PHY nodes
It defines that PHY nodes must be children on MDIO bus nodes and defines
the only required property in U-Boot, reg. This property along with the
example provided are copied over from Linux.
Signed-off-by: Alex Marginean
---
doc/device-tree-bindings/net/phy.txt | 24
1 file changed, 24 insertions(+)
create mode 100644 doc/device-tree-bindings/net/phy.txt
diff --git a/doc/device-tree-bindings/net/phy.txt
b/doc/device-tree-bindings/net/phy.txt
new file mode 100644
index 00..6599c667b5
--- /dev/null
+++ b/doc/device-tree-bindings/net/phy.txt
@@ -0,0 +1,24 @@
+PHY nodes
+
+If the device tree is used to describe networking interfaces, U-Boot expects a
+node for each PHY. Parent node for such a PHY node is expected to correspond
to
+a MDIO bus and the bus is used to access the PHY.
+
+Required properties:
+
+ - reg : The ID number for the phy, usually a small integer
+
+Example:
+
+ethernet-phy@0 {
+ compatible = "ethernet-phy-id0141.0e90", "ethernet-phy-ieee802.3-c22";
+ interrupt-parent = <>;
+ interrupts = <35 IRQ_TYPE_EDGE_RISING>;
+ reg = <0>;
+
+ resets = < 8>;
+ reset-names = "phy";
+ reset-gpios = < 4 GPIO_ACTIVE_LOW>;
+ reset-assert-us = <1000>;
+ reset-deassert-us = <2000>;
+};
--
2.17.1
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 10/11] doc: bindings: Aquantia PHY node binding
A couple of optional properties have been introduced for Aquantia PHY
allowing the driver to set up wiring related configuration points that
are otherwise driven by firmware.
Signed-off-by: Alex Marginean
---
doc/device-tree-bindings/net/aquantia-phy.txt | 25 +++
1 file changed, 25 insertions(+)
create mode 100644 doc/device-tree-bindings/net/aquantia-phy.txt
diff --git a/doc/device-tree-bindings/net/aquantia-phy.txt
b/doc/device-tree-bindings/net/aquantia-phy.txt
new file mode 100644
index 00..89ce61e05b
--- /dev/null
+++ b/doc/device-tree-bindings/net/aquantia-phy.txt
@@ -0,0 +1,25 @@
+PHY nodes for Aquantia devices.
+
+This text describes properties that are applicable to Aquantia PHY nodes in
+addition to the bindings in phy.txt.
+
+Aquantia PHYs allow some flexibility in the way they are wired in a system,
+they allow MDI pins to be reversed, LEDs linked up in different weays, have an
+I2C slave interface that can be used for debug. Normally the configuration
+corresponding to these is driven by the PHY firmware with the downside that
+a custom firmware is needed for each integration of a PHY.
+Several optional bindings are defined that allow these configuration points to
+be driven by the PHY driver and reduce dependency on specific FW versions.
+
+Optional properties:
+mdi-reversal: 0 or 1 indicating that reversal must be disabled/enabled.
+ Firmware default is used if the property is missing.
+smb-addr: I2C/SMBus address to use, firmware default is used if the
property
+ is missing.
+
+Example node:
+phy@00 {
+ reg = <0x00>;
+ mdi-reversal = <1>;
+ smb-addr = <0x25>;
+};
--
2.17.1
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 01/11] include: phy: define XFI and USXGMII interface types
Drivers currently use XGMII for XFI and USXGMII and, where needed, use
other information to identify the actual protocol on the board. With these
two defined drivers can now rely on DT phy-mode property.
Signed-off-by: Alex Marginean
---
include/phy_interface.h | 4
1 file changed, 4 insertions(+)
diff --git a/include/phy_interface.h b/include/phy_interface.h
index c6823189f8..73f3a3679c 100644
--- a/include/phy_interface.h
+++ b/include/phy_interface.h
@@ -31,6 +31,8 @@ typedef enum {
PHY_INTERFACE_MODE_XLAUI,
PHY_INTERFACE_MODE_CAUI2,
PHY_INTERFACE_MODE_CAUI4,
+ PHY_INTERFACE_MODE_XFI,
+ PHY_INTERFACE_MODE_USXGMII,
PHY_INTERFACE_MODE_NONE,/* Must be last */
PHY_INTERFACE_MODE_COUNT,
@@ -58,6 +60,8 @@ static const char * const phy_interface_strings[] = {
[PHY_INTERFACE_MODE_XLAUI] = "xlaui4",
[PHY_INTERFACE_MODE_CAUI2] = "caui2",
[PHY_INTERFACE_MODE_CAUI4] = "caui4",
+ [PHY_INTERFACE_MODE_XFI]= "xfi",
+ [PHY_INTERFACE_MODE_USXGMII]= "usxgmii",
[PHY_INTERFACE_MODE_NONE] = "",
};
--
2.17.1
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 00/11] Aquantia PHY driver updates to reduce FW dependency
The main purpose of this patch series is to allow the AQR driver to run on a larger number of boards without having to use a custom aquantia FW on each of them. Configuration points that are exclusively controlled by PHY firmware are not configured based on phydev->interface as well as new DT node properties. The patch set introduces a couple of new interface types (XFI and USXGMII), introduces a couple of binding documents and updates the ENETC eth driver to use the new interface types. Alex Marginean (11): include: phy: define XFI and USXGMII interface types include: phy: add data field for private driver data drivers: net: aquantia: use XFI, USXGMII interface types drivers: net: aquantia: add PHY generation information drivers: net: aquantia: set up SI protocol based on interface type drivers: net: aquantia: set MDI reversal based on DT property drivers: net: aquantia: set SMBus addr based on DT property drivers: net: aquantia: use SI and LI status in loop waiting for link up doc: bindings: add bindings document for PHY nodes doc: bindings: Aquantia PHY node binding drivers: net: fsl_enetc: use XFI, USXGMII interface type macros doc/device-tree-bindings/net/aquantia-phy.txt | 25 ++ doc/device-tree-bindings/net/phy.txt | 24 ++ drivers/net/fsl_enetc.c | 2 + drivers/net/phy/aquantia.c| 219 -- include/phy.h | 3 + include/phy_interface.h | 4 + 6 files changed, 263 insertions(+), 14 deletions(-) create mode 100644 doc/device-tree-bindings/net/aquantia-phy.txt create mode 100644 doc/device-tree-bindings/net/phy.txt -- 2.17.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [RFC PATCH 1/2] drivers: net: Add a driver for the Felix Ethernet switch on NXP LS1028A
The driver sets up the switch at probe allowing traffic though. Both the
switch as a whole and the ports are registered as network devices in
U-Boot, although neither supports direct I/O in this version. Traffic can
originate from SoC though one of the internally linked ENETC interfaces,
external ports can also be used in basic switching mode too.
Signed-off-by: Alex Marginean
---
drivers/net/Kconfig | 7 +
drivers/net/Makefile| 1 +
drivers/net/fsl_enetc.h | 5 +
drivers/net/fsl_felix.c | 414
4 files changed, 427 insertions(+)
create mode 100644 drivers/net/fsl_felix.c
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 084e095229..1669e55fcd 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -603,4 +603,11 @@ config MDIO_MUX_I2CREG
an I2C chip. The board it was developed for uses a mux controlled by
on-board FPGA which in turn is accessed as a chip over I2C.
+config FSL_FELIX
+ bool "LS1028 Felix Ethernet switch"
+ depends on DM_PCI && DM_ETH && DM_MDIO
+ help
+ This driver supports the Ethernet switch integrated in LS1028A NXP
+ SoC.
+
endif # NETDEVICES
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 71c0889355..96d4a3cdc5 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -81,3 +81,4 @@ obj-y += mscc_eswitch/
obj-$(CONFIG_HIGMACV300_ETH) += higmacv300.o
obj-$(CONFIG_MDIO_SANDBOX) += mdio_sandbox.o
obj-$(CONFIG_FSL_ENETC) += fsl_enetc.o fsl_enetc_mdio.o
+obj-$(CONFIG_FSL_FELIX) += fsl_felix.o
diff --git a/drivers/net/fsl_enetc.h b/drivers/net/fsl_enetc.h
index 9a36cdad80..29e7781b5e 100644
--- a/drivers/net/fsl_enetc.h
+++ b/drivers/net/fsl_enetc.h
@@ -200,6 +200,11 @@ struct enetc_priv {
/* PCS replicator block for USXGMII */
#define ENETC_PCS_DEVAD_REPL 0x1f
+#define ENETC_PCS_REPL_LINK_TIMER_10x12
+#define ENETC_PCS_REPL_LINK_TIMER_1_DEF 0x0003
+#define ENETC_PCS_REPL_LINK_TIMER_20x13
+#define ENETC_PCS_REPL_LINK_TIMER_2_DEF 0x06a0
+
/* ENETC external MDIO registers */
#define ENETC_MDIO_BASE0x1c00
#define ENETC_MDIO_CFG 0x00
diff --git a/drivers/net/fsl_felix.c b/drivers/net/fsl_felix.c
new file mode 100644
index 00..9689c025ef
--- /dev/null
+++ b/drivers/net/fsl_felix.c
@@ -0,0 +1,414 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Felix ethernet switch driver
+ * Copyright 2018-2019 NXP
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+/* defines especially around PCS are reused from enetc */
+#include "fsl_enetc.h"
+
+#define FELIX_PORT_DRV_NAME"felix-port"
+
+#define PCI_DEVICE_ID_FELIX_ETHSW 0xEEF0
+#define FELIX_PM_IMDIO_BASE0x8030
+
+/* Max port count, including any internal ports */
+#define FELIX_PORT_COUNT 6
+
+/* Register map for BAR4 */
+#define FELIX_SYS 0x01
+#define FELIX_ES0 0x04
+#define FELIX_IS1 0x05
+#define FELIX_IS2 0x06
+#define FELIX_GMII(port) (0x10 + (port) * 0x1)
+#define FELIX_QSYS 0x20
+
+#define FELIX_SYS_SYSTEM (FELIX_SYS + 0x0E00)
+#define FELIX_SYS_SYSTEM_EN BIT(0)
+#define FELIX_SYS_RAM_CTRL (FELIX_SYS + 0x0F24)
+#define FELIX_SYS_RAM_CTRL_INIT BIT(1)
+
+#define FELIX_ES0_TCAM_CTRL(FELIX_ES0 + 0x03C0)
+#define FELIX_ES0_TCAM_CTRL_ENBIT(0)
+#define FELIX_IS1_TCAM_CTRL(FELIX_IS1 + 0x03C0)
+#define FELIX_IS1_TCAM_CTRL_ENBIT(0)
+#define FELIX_IS2_TCAM_CTRL(FELIX_IS2 + 0x03C0)
+#define FELIX_IS2_TCAM_CTRL_ENBIT(0)
+
+#define FELIX_GMII_CLOCK_CFG(port) (FELIX_GMII(port) + 0x)
+#define FELIX_GMII_CLOCK_CFG_LINK_1G 1
+#define FELIX_GMII_CLOCK_CFG_LINK_100M2
+#define FELIX_GMII_CLOCK_CFG_LINK_10M 3
+#define FELIX_GMII_MAC_ENA_CFG(port) (FELIX_GMII(port) + 0x001C)
+#define FELIX_GMII_MAX_ENA_CFG_TX BIT(0)
+#define FELIX_GMII_MAX_ENA_CFG_RX BIT(4)
+#define FELIX_GMII_MAC_IFG_CFG(port) (FELIX_GMII(port) + 0x001C + 0x14)
+#define FELIX_GMII_MAC_IFG_CFG_DEF0x515
+
+#define FELIX_QSYS_SYSTEM (FELIX_QSYS + 0xF460)
+#define FELIX_QSYS_SYSTEM_SW_PORT_MODE(port) \
+ (FELIX_QSYS_SYSTEM + 0x20 + (port) * 4)
+#define FELIX_QSYS_SYSTEM_SW_PORT_ENA BIT(14)
+#define FELIX_QSYS_SYSTEM_SW_PORT_LOSSY BIT(9)
+#define FELIX_QSYS_SYSTEM_SW_PORT_SCH(a) (((a) & 0x3800) << 11)
+
+/* internal MDIO in BAR0 */
+#define FELIX_PM_IMDIO_BASE0x8030
+
+/* Serdes block on LS1028A */
+#define FELIX_SERDES_BASE 0x1eaL
+#define FELIX_SERDES_LNATECR0(lane)(FELIX_SERDES_BASE + 0x818 + \
+
[U-Boot] [RFC PATCH 2/2] arm: dts: ls1028a: add node for the integrated Ethernet switch
Adds a device tree node to ls1028a dtsi that describes the Ethernet switch
integrated in LS1028A SoC.
Signed-off-by: Alex Marginean
---
arch/arm/dts/fsl-ls1028a.dtsi | 31 +++
1 file changed, 31 insertions(+)
diff --git a/arch/arm/dts/fsl-ls1028a.dtsi b/arch/arm/dts/fsl-ls1028a.dtsi
index 43a154e8e7..21595713df 100644
--- a/arch/arm/dts/fsl-ls1028a.dtsi
+++ b/arch/arm/dts/fsl-ls1028a.dtsi
@@ -136,6 +136,37 @@
reg = <0x000300 0 0 0 0>;
status = "disabled";
};
+ ethsw: pci@0,5 {
+ #address-cells=<0>;
+ #size-cells=<1>;
+ reg = <0x000500 0 0 0 0>;
+ port@0 {
+ reg = <0>;
+ status = "disabled";
+ };
+ port@1 {
+ reg = <1>;
+ status = "disabled";
+ };
+ port@2 {
+ reg = <2>;
+ status = "disabled";
+ };
+ port@3 {
+ reg = <3>;
+ status = "disabled";
+ };
+ port@4 {
+ reg = <4>;
+ phy-mode = "internal";
+ status = "okay";
+ };
+ port@5 {
+ reg = <5>;
+ phy-mode = "internal";
+ status = "okay";
+ };
+ };
enetc6: pci@0,6 {
reg = <0x000600 0 0 0 0>;
status = "okay";
--
2.17.1
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot
[U-Boot] [RFC PATCH 0/2] Add a driver for the Felix Ethernet switch on NXP LS1028A
The driver sets up the switch during probe making external and internal ports available to use. It does not support direct I/O through these switch ports in this version and I'm not sure that is a feature useful in U-Boot. Instead ENETC ethernet interfaces that are internally linked to the switch can be used after the switch is set up. This is where the RFC part comes in. Both the switch as a device and its ports are probed as ethernet devices. That's handy as accessors to connect to the PHY can be used but otherwise they are useful as the user can't ping to these interfaces. I'd like to get some feedback on whether this is acceptable or instead I should use some other structure for describing the switch and its ports, maybe have a new DM uclass. Other switch devices are registered as PHYs but that's not too useful if the external ports of the switch have PHYs of their own and they need to be driven too. Using a complete DTS the switch looks like this: => dm tree Class Index Probed DriverName --- pci 2 [ + ] pci_generic_ecam |-- pcie@1f000 eth 1 [ + ] enetc_eth | |-- enetc-0 eth 2 [ + ] enetc_eth | |-- enetc-1 eth 3 [ + ] enetc_eth | |-- enetc-2 mdio 5 [ + ] enetc_mdio| |-- emdio-3 pci_generi 0 [ ] pci_generic_drv | |-- pci_3:0.4 eth 4 [ + ] felix_ethsw | |-- felix_ethsw eth 6 [ + ] felix-port| | |-- port@0 eth 7 [ + ] felix-port| | |-- port@1 eth 8 [ + ] felix-port| | |-- port@2 eth 9 [ + ] felix-port| | |-- port@3 eth 10 [ + ] felix-port| | |-- port@4 eth 11 [ + ] felix-port| | `-- port@5 eth 5 [ + ] enetc_eth | |-- enetc-6 pci_generi 1 [ ] pci_generic_drv | `-- pci_3:1f.0 => mdio list felix_ethsw: emdio-3: mdio@50: 0 - Aquantia AQR412 <--> port@0 1 - Aquantia AQR412 <--> port@1 2 - Aquantia AQR412 <--> port@2 3 - Aquantia AQR412 <--> port@3 mdio@00: 5 - AR8035 <--> enetc-1 mdio@40: 2 - Aquantia AQR112 <--> enetc-0 mdio@60: mdio@70: Any feedback is welcome, of course :) Thank you! Alex Depends on https://patchwork.ozlabs.org/project/uboot/list/?series=123813 Alex Marginean (2): drivers: net: Add a driver for the Felix Ethernet switch on NXP LS1028A arm: dts: ls1028a: add node for the integrated Ethernet switch arch/arm/dts/fsl-ls1028a.dtsi | 31 +++ drivers/net/Kconfig | 7 + drivers/net/Makefile | 1 + drivers/net/fsl_enetc.h | 5 + drivers/net/fsl_felix.c | 414 ++ 5 files changed, 458 insertions(+) create mode 100644 drivers/net/fsl_felix.c -- 2.17.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] riscv: cpu: Skip unavailable hart in the get_count() op
Hi Lukas, On Thu, Aug 8, 2019 at 10:03 PM Auer, Lukas wrote: > > Hi Bin, > > On Thu, 2019-08-08 at 21:25 +0800, Bin Meng wrote: > > Hi Lukas, > > > > On Thu, Aug 8, 2019 at 7:22 PM Auer, Lukas > > wrote: > > > Hi Bin, > > > > > > On Thu, 2019-08-08 at 00:52 -0700, Bin Meng wrote: > > > > We should not count in hart that is marked as not available in the > > > > device tree in riscv_cpu_get_count(). > > > > > > > > > > I think it might make sense to also exclude harts that are not listed > > > as available in the available_harts mask. So the same logic as in > > > arch/riscv/lib/smp.c. In this case, the bind function should probably > > > check the mask as well. > > > > > > > Yes, the check to available_harts mask can be added in > > riscv_cpu_get_count(). I will do that. > > > > However, I doubt we could do available_harts mask check in the bind > > function. If it returns error for non-available harts, the whole > > initialization process fails. > > > > You are right, I did not think about that. Perhaps it's best to ignore > the available_harts mask in the count function as well then. > Agreed. I will leave this patch as it is. > It just checked where cpu_get_count() is used. The Andes PLIC driver > (lib/andes_plic.c) uses it in a way that the patch might break the > driver. It iterates over all harts, assuming the first hart is 0 and > the last hart the result of cpu_get_count(). If any of the harts is set > to disabled, this will no longer be true. It's probably best to update > the driver to use the ofnode_for_each_subnode() macro to iterate over > all harts. Rick, can you update the driver? > Good catch! Regards, Bin ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v9 9/9] x86: Skip setting up MTRRs in slimbootloader
On Thu, Aug 8, 2019 at 10:35 PM Bin Meng wrote: > > On Sat, Aug 3, 2019 at 4:31 PM Park, Aiden wrote: > > > > The setting up MTRRs have already been done in previous > > Slim Bootloader stages. > > > > Signed-off-by: Aiden Park > > Reviewed-by: Bin Meng > > Reviewed-by: Andy Shevchenko > > --- > > arch/x86/lib/init_helpers.c | 3 ++- > > 1 file changed, 2 insertions(+), 1 deletion(-) > > > > Tested-by: Bin Meng applied to u-boot-x86, thanks! ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v9 8/9] board: intel: Add new slimbootloader board
On Thu, Aug 8, 2019 at 10:35 PM Bin Meng wrote: > > On Sat, Aug 3, 2019 at 4:31 PM Park, Aiden wrote: > > > > Add slimbootloader board to run U-boot as a Slim Bootloader payload > > - Add new board/intel/slimbootloader directory with minimum codes > > - Add slimbootloader configuration files > > - Add doc/board/intel/slimbootloader.rst > > > > Signed-off-by: Aiden Park > > Reviewed-by: Bin Meng > > Reviewed-by: Andy Shevchenko > > --- > > Changes in v8: > > * Add a space between acronym and (definition) > > > > Changes in v7: > > * Adding slimbootloader.rst in index.rst > > > > Changes in v6: > > * Select CONFIG_SYS_SLIMBOOTLOADER in board Kconfig > > * Move USB_STORAGE and USB_KEYBOARD to board Kconfig > > * Convert README to reST doc/board/intel/slimbootloader.rst > > > > Changes in v5: > > * Remove X86_LOAD_FROM_32_BIT from slimbootloader_defconfig > > > > Changes in v3: > > * Remove VENDOR_SLIMBOOTLOADER > > * Use VENDOR_INTEL > > * Move slimbootloader under board/intel/ > > * Enable generic CONFIGs in slimbootloader_defconfig > > * Add more description in board/intel/slimbootloader/README > > > > board/intel/Kconfig | 14 ++ > > board/intel/slimbootloader/Kconfig | 28 > > board/intel/slimbootloader/Makefile | 5 + > > board/intel/slimbootloader/slimbootloader.c | 21 +++ > > board/intel/slimbootloader/start.S | 9 + > > configs/slimbootloader_defconfig| 22 +++ > > doc/board/intel/index.rst | 1 + > > doc/board/intel/slimbootloader.rst | 174 > > include/configs/slimbootloader.h| 62 +++ > > 9 files changed, 336 insertions(+) > > create mode 100644 board/intel/slimbootloader/Kconfig > > create mode 100644 board/intel/slimbootloader/Makefile > > create mode 100644 board/intel/slimbootloader/slimbootloader.c > > create mode 100644 board/intel/slimbootloader/start.S > > create mode 100644 configs/slimbootloader_defconfig > > create mode 100644 doc/board/intel/slimbootloader.rst > > create mode 100644 include/configs/slimbootloader.h > > > > Tested-by: Bin Meng applied to u-boot-x86, thanks! ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v9 6/9] x86: slimbootloader: Set TSC information for tsc_timer
On Thu, Aug 8, 2019 at 10:35 PM Bin Meng wrote: > > On Sat, Aug 3, 2019 at 4:30 PM Park, Aiden wrote: > > > > Slim Bootloader already calibrated TSC and provides it to U-Boot. > > Therefore, U-Boot does not have to re-calibrate TSC. > > Configuring tsc_base and clock_rate makes x86 tsc_timer driver bypass > > TSC calibration and use the provided TSC frequency. > > - Get TSC frequency from performance info hob > > - Set tsc_base and clock_rate for tsc_timer driver > > > > Signed-off-by: Aiden Park > > Reviewed-by: Bin Meng > > --- > > Changes in v6: > > * Use EFI_GUID > > * Add more comments while setting tsc_base and clock_rate > > * Apply code-review comments > > > > Changes in v3: > > * Use HOB function from the common HOB library > > > > arch/x86/cpu/slimbootloader/slimbootloader.c | 37 +++ > > .../asm/arch-slimbootloader/slimbootloader.h | 28 ++ > > 2 files changed, 65 insertions(+) > > > > Tested-by: Bin Meng applied to u-boot-x86, thanks! ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v9 7/9] x86: slimbootloader: Add a slimbootloader device tree
On Thu, Aug 8, 2019 at 10:35 PM Bin Meng wrote: > > On Sat, Aug 3, 2019 at 4:31 PM Park, Aiden wrote: > > > > Add a new device tree which has very minimum nodes > > - x86 reset > > - x86 tsc_timer > > - x86 pci > > - Slim Bootloader serial > > > > Signed-off-by: Aiden Park > > Reviewed-by: Bin Meng > > Reviewed-by: Andy Shevchenko > > --- > > Changes in v3: > > * Move slimbootloader.dtb before baytrail_som-db5800-som-6867.dtb > > > > arch/x86/dts/Makefile | 1 + > > arch/x86/dts/slimbootloader.dts | 27 +++ > > 2 files changed, 28 insertions(+) > > create mode 100644 arch/x86/dts/slimbootloader.dts > > > > Tested-by: Bin Meng applied to u-boot-x86, thanks! ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v9 4/9] x86: slimbootloader: Add memory configuration
On Thu, Aug 8, 2019 at 10:35 PM Bin Meng wrote: > > On Sat, Aug 3, 2019 at 4:30 PM Park, Aiden wrote: > > > > Slim Bootloader provides memory map info thru its HOB list pointer. > > Configure memory size and relocation memory from the HOB data, and > > provide e820 entries as well. > > - Get memory size from the memory map info HOB > > - Set available top memory lower than 4GB for U-Boot relocation > > - Provide e820 entries from the memory map info HOB > > > > Signed-off-by: Aiden Park > > Reviewed-by: Bin Meng > > Reviewed-by: Andy Shevchenko > > --- > > Changes in v9: > > * Use for_each_if macro to avoid checkpatch ERROR > > > > Changes in v8: > > * Change for_each condition check to avoid ERROR from checkpatch > > > > Changes in v7: > > * Use for_each macro instead of while_each > > * Move for_each macro before its first use > > > > Changes in v6: > > * Change dram.c to sdram.c > > * Use EFI_GUID > > * Use a macro to do reversed search in memory map entries > > * Apply code-review comments > > > > Changes in v3: > > * Use HOB function from the common HOB library > > * Add more description > > > > arch/x86/cpu/slimbootloader/Makefile | 2 +- > > arch/x86/cpu/slimbootloader/sdram.c | 151 ++ > > .../asm/arch-slimbootloader/slimbootloader.h | 53 ++ > > 3 files changed, 205 insertions(+), 1 deletion(-) > > create mode 100644 arch/x86/cpu/slimbootloader/sdram.c > > create mode 100644 > > arch/x86/include/asm/arch-slimbootloader/slimbootloader.h > > > > Tested-by: Bin Meng applied to u-boot-x86, thanks! ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v9 5/9] x86: slimbootloader: Add serial driver
On Thu, Aug 8, 2019 at 10:35 PM Bin Meng wrote: > > On Sat, Aug 3, 2019 at 4:30 PM Park, Aiden wrote: > > > > Slim Bootloader provides serial port info thru its HOB list pointer. > > All these HOBs are eligible for Slim Bootloader based board only. > > - Get serial port information from the serial port info HOB > > - Leverage ns16550 driver with slimbootloader specific platform data > > > > Signed-off-by: Aiden Park > > Reviewed-by: Bin Meng > > Reviewed-by: Andy Shevchenko > > --- > > Changes in v6: > > * Use EFI_GUID > > * Apply code-review comments > > > > Changes in v4: > > * Add static keyword in static function > > > > Changes in v3: > > * Use HOB function from the common HOB library > > > > arch/x86/cpu/slimbootloader/Makefile | 2 +- > > arch/x86/cpu/slimbootloader/serial.c | 67 +++ > > .../asm/arch-slimbootloader/slimbootloader.h | 34 ++ > > 3 files changed, 102 insertions(+), 1 deletion(-) > > create mode 100644 arch/x86/cpu/slimbootloader/serial.c > > > > Tested-by: Bin Meng applied to u-boot-x86, thanks! ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v9 2/9] x86: lib: fsp: Use EFI_GUID and efi_guid_t
On Sat, Aug 3, 2019 at 4:30 PM Park, Aiden wrote: > > Use existing EFI_GUID and efi_guid_t instead of struct efi_guid. > This is pre-work before making a common HOB library. > - Change 'struct efi_guid' to efi_guit_t > - Remove 'struct efi_guid' > - Define GUIDs with EFI_GUID() macro > - Use guidcmp() instead of compare_guid() > - Remove compare_guid() > > Signed-off-by: Aiden Park > Reviewed-by: Andy Shevchenko > Reviewed-by: Bin Meng > > Tested on MinnowMax > Tested-by: Bin Meng > --- > Changes in v8: > * Remove unnecessary parentheses reported from checkpatch > > Changes in v7: > * Split HOB library into EFI_GUID pre-work and making a common lirary > > arch/x86/include/asm/fsp/fsp_ffs.h | 4 +- > arch/x86/include/asm/fsp/fsp_fv.h | 4 +- > arch/x86/include/asm/fsp/fsp_hob.h | 76 + > arch/x86/include/asm/fsp/fsp_support.h | 6 +- > arch/x86/include/asm/fsp/fsp_types.h | 8 --- > arch/x86/lib/fsp/fsp_support.c | 78 ++ > cmd/x86/fsp.c | 10 ++-- > 7 files changed, 81 insertions(+), 105 deletions(-) > applied to u-boot-x86, thanks! ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v9 3/9] x86: Add a common HOB library
On Sat, Aug 3, 2019 at 4:30 PM Park, Aiden wrote:
>
> FSP (CONFIG_HAVE_FSP) and Slim Bootloader (CONFIG_SYS_SLIMBOOTLOADER)
> consume HOB (CONFIG_USE_HOB) data from the each HOB list pointer.
> Add a common HOB library in lib/hob.c and include/asm/hob.h.
>
> Signed-off-by: Aiden Park
> Reviewed-by: Andy Shevchenko
> Reviewed-by: Bin Meng
> Tested-by: Bin Meng
> ---
> Changes in v8:
> * Add a space between acronym and (definition)
>
> Changes in v7:
> * Split HOB library into EFI_GUID pre-work and making a common lirary
>
> Changes in v6:
> * Use CONFIG_USE_HOB
> * Change struct efi_guid to efi_guid_t
> * Use EFI_GUID to define GUIDs
>
> Changes in v3:
> * Create a common HOB libary from fsp_hob and fsp_support
>
> arch/x86/include/asm/fsp/fsp_hob.h| 184 +---
> arch/x86/include/asm/fsp/fsp_support.h| 37 +---
> arch/x86/include/asm/{fsp/fsp_hob.h => hob.h} | 196 +++---
> arch/x86/lib/Makefile | 1 +
> arch/x86/lib/fsp/fsp_support.c| 57 +
> arch/x86/lib/hob.c| 84
> cmd/x86/Makefile | 1 +
> cmd/x86/fsp.c | 65 +-
> cmd/x86/hob.c | 77 +++
> 9 files changed, 242 insertions(+), 460 deletions(-)
> copy arch/x86/include/asm/{fsp/fsp_hob.h => hob.h} (67%)
> create mode 100644 arch/x86/lib/hob.c
> create mode 100644 cmd/x86/hob.c
>
applied to u-boot-x86, thanks!
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v9 1/9] x86: Add new slimbootloader CPU type
On Thu, Aug 8, 2019 at 10:44 PM Bin Meng wrote: > > On Sat, Aug 3, 2019 at 4:30 PM Park, Aiden wrote: > > > > This slimbootloader CPU type is to enable U-Boot as a payload which > > runs on top of Slim Bootloader (https://github.com/slimbootloader). > > The Slim Bootloader is designed with multi-stage architecture for > > the execution from reset vector to OS booting, and supports QEMU, > > Apollolake, Whiskeylake and Coffeelake platforms consuming Intel > > FSP (https://github.com/IntelFsp) for silicon initialization > > including CAR and memory initialization. > > The Slim Bootloader generates new HOB (Hand Off Block) which are > > serial port info, memory map info, performance data info and so on, > > and passes it to a Payload. U-Boot as a payload will use these HOB > > information for basic initialization such as serial console. > > > > As an initial commit, > > - Add CONFIG_SYS_SLIMBOOTLOADER to enable slimbootloader CPU type > > - Add new arch/x86/cpu/slimbootloader directory with minimum codes > > - Get hob_list pointer from Slim Bootloader > > > > Signed-off-by: Aiden Park > > Reviewed-by: Bin Meng > > Reviewed-by: Andy Shevchenko > > --- > > Changes in v8: > > * Add a space between acronym and (definition) > > > > Changes in v6: > > * Add CONFIG_USE_HOB > > * Move some CONFIGs to board Kconfig > > * Remove arch-slimbootloader/slimbooloader.h > > * Apply code-review comments > > > > Changes in v4: > > * Use common arch/x86/cpu/start.S > > * Update U-boot or u-boot to U-Boot in commit message > > > > Changes in v3: > > * Add a brief description about Slim Bootloader > > * Enable USB_KEYBOARD, E1000 and RTL8169 by default > > * Fix comment from code review > > > > arch/x86/Kconfig | 9 + > > arch/x86/cpu/Makefile| 1 + > > arch/x86/cpu/slimbootloader/Kconfig | 19 ++ > > arch/x86/cpu/slimbootloader/Makefile | 5 + > > arch/x86/cpu/slimbootloader/car.S| 14 + > > arch/x86/cpu/slimbootloader/slimbootloader.c | 21 > > arch/x86/cpu/start.S | 6 -- > > arch/x86/include/asm/global_data.h | 2 +- > > arch/x86/lib/asm-offsets.c | 2 +- > > 9 files changed, 75 insertions(+), 4 deletions(-) > > create mode 100644 arch/x86/cpu/slimbootloader/Kconfig > > create mode 100644 arch/x86/cpu/slimbootloader/Makefile > > create mode 100644 arch/x86/cpu/slimbootloader/car.S > > create mode 100644 arch/x86/cpu/slimbootloader/slimbootloader.c > > > > Tested-by: Bin Meng applied to u-boot-x86, thanks! ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v4] x86: ich-spi: Convert driver to spi-mem ops
On Thu, Aug 8, 2019 at 9:50 PM Bin Meng wrote: > > On Fri, Aug 2, 2019 at 2:38 PM Bernhard Messerklinger > wrote: > > > > With the introduction of the new spi-mem model operations changed > > slightly. The new spi-mem operations make things a bit easier to > > handle for ich-spi flash interface. This patch converts the ich-spi > > driver by using spi-mem operations. > > > > Signed-off-by: Bernhard Messerklinger > > > > --- > > > > Changes in v4: > > - fix changelog; fix local variable types and order > > Changes in v3: > > - update erase op code handling to work with latest master > > spi-nor driver > > Changes in v2: > > - make 2 routines static; update commit message a little bit > > > > drivers/spi/ich.c | 258 +- > > drivers/spi/ich.h | 9 +- > > 2 files changed, 95 insertions(+), 172 deletions(-) > > > > Reviewed-by: Bin Meng > > Tested on Intel CrownBay and MinnowMax > Tested-by: Bin Meng applied to u-boot-x86, thanks! ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] x86: qemu: Fix non-working ramboot and nfsboot environment variables
On Sun, Jul 28, 2019 at 11:14 PM Bin Meng wrote: > > With qemu-x86 starting to use config_distro_bootcmd, the pre-defined > ramboot and nfsboot commands do not work any more. This is caused by > undefined environment variable 'ramdiskaddr' that was previously set > in CONFIG_EXTRA_ENV_SETTINGS but later CONFIG_EXTRA_ENV_SETTINGS was > redefined for distro boot. > > Update the x86 generic CONFIG_EXTRA_ENV_SETTINGS to consider distro > boot, and remove the one in qemu-x86.h. > > Signed-off-by: Bin Meng > --- > > include/configs/qemu-x86.h | 10 -- > include/configs/x86-common.h | 21 ++--- > 2 files changed, 14 insertions(+), 17 deletions(-) > applied to u-boot-x86, thanks! ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 1/1] bios_emulator: remove stray break
On Thu, Aug 8, 2019 at 9:31 PM Bin Meng wrote: > > On Fri, Aug 2, 2019 at 1:37 AM Heinrich Schuchardt wrote: > > > > Remove a stray break which suppresses some debug messages. > > > > Indicated by cppcheck. > > > > Signed-off-by: Heinrich Schuchardt > > --- > > @Simon: > > Please, test on an x86 Chromebook. I have no access to a test device. > > --- > > drivers/bios_emulator/atibios.c | 1 - > > 1 file changed, 1 deletion(-) > > > > Acked-by: Bin Meng applied to u-boot-x86, thanks! ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v9 1/9] x86: Add new slimbootloader CPU type
On Sat, Aug 3, 2019 at 4:30 PM Park, Aiden wrote: > > This slimbootloader CPU type is to enable U-Boot as a payload which > runs on top of Slim Bootloader (https://github.com/slimbootloader). > The Slim Bootloader is designed with multi-stage architecture for > the execution from reset vector to OS booting, and supports QEMU, > Apollolake, Whiskeylake and Coffeelake platforms consuming Intel > FSP (https://github.com/IntelFsp) for silicon initialization > including CAR and memory initialization. > The Slim Bootloader generates new HOB (Hand Off Block) which are > serial port info, memory map info, performance data info and so on, > and passes it to a Payload. U-Boot as a payload will use these HOB > information for basic initialization such as serial console. > > As an initial commit, > - Add CONFIG_SYS_SLIMBOOTLOADER to enable slimbootloader CPU type > - Add new arch/x86/cpu/slimbootloader directory with minimum codes > - Get hob_list pointer from Slim Bootloader > > Signed-off-by: Aiden Park > Reviewed-by: Bin Meng > Reviewed-by: Andy Shevchenko > --- > Changes in v8: > * Add a space between acronym and (definition) > > Changes in v6: > * Add CONFIG_USE_HOB > * Move some CONFIGs to board Kconfig > * Remove arch-slimbootloader/slimbooloader.h > * Apply code-review comments > > Changes in v4: > * Use common arch/x86/cpu/start.S > * Update U-boot or u-boot to U-Boot in commit message > > Changes in v3: > * Add a brief description about Slim Bootloader > * Enable USB_KEYBOARD, E1000 and RTL8169 by default > * Fix comment from code review > > arch/x86/Kconfig | 9 + > arch/x86/cpu/Makefile| 1 + > arch/x86/cpu/slimbootloader/Kconfig | 19 ++ > arch/x86/cpu/slimbootloader/Makefile | 5 + > arch/x86/cpu/slimbootloader/car.S| 14 + > arch/x86/cpu/slimbootloader/slimbootloader.c | 21 > arch/x86/cpu/start.S | 6 -- > arch/x86/include/asm/global_data.h | 2 +- > arch/x86/lib/asm-offsets.c | 2 +- > 9 files changed, 75 insertions(+), 4 deletions(-) > create mode 100644 arch/x86/cpu/slimbootloader/Kconfig > create mode 100644 arch/x86/cpu/slimbootloader/Makefile > create mode 100644 arch/x86/cpu/slimbootloader/car.S > create mode 100644 arch/x86/cpu/slimbootloader/slimbootloader.c > Tested-by: Bin Meng ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v9 8/9] board: intel: Add new slimbootloader board
Hi Aiden, On Thu, Aug 8, 2019 at 10:35 PM Bin Meng wrote: > > On Sat, Aug 3, 2019 at 4:31 PM Park, Aiden wrote: > > > > Add slimbootloader board to run U-boot as a Slim Bootloader payload > > - Add new board/intel/slimbootloader directory with minimum codes > > - Add slimbootloader configuration files > > - Add doc/board/intel/slimbootloader.rst > > > > Signed-off-by: Aiden Park > > Reviewed-by: Bin Meng > > Reviewed-by: Andy Shevchenko > > --- > > Changes in v8: > > * Add a space between acronym and (definition) > > > > Changes in v7: > > * Adding slimbootloader.rst in index.rst > > > > Changes in v6: > > * Select CONFIG_SYS_SLIMBOOTLOADER in board Kconfig > > * Move USB_STORAGE and USB_KEYBOARD to board Kconfig > > * Convert README to reST doc/board/intel/slimbootloader.rst > > > > Changes in v5: > > * Remove X86_LOAD_FROM_32_BIT from slimbootloader_defconfig > > > > Changes in v3: > > * Remove VENDOR_SLIMBOOTLOADER > > * Use VENDOR_INTEL > > * Move slimbootloader under board/intel/ > > * Enable generic CONFIGs in slimbootloader_defconfig > > * Add more description in board/intel/slimbootloader/README > > > > board/intel/Kconfig | 14 ++ > > board/intel/slimbootloader/Kconfig | 28 > > board/intel/slimbootloader/Makefile | 5 + > > board/intel/slimbootloader/slimbootloader.c | 21 +++ > > board/intel/slimbootloader/start.S | 9 + > > configs/slimbootloader_defconfig| 22 +++ > > doc/board/intel/index.rst | 1 + > > doc/board/intel/slimbootloader.rst | 174 > > include/configs/slimbootloader.h| 62 +++ > > 9 files changed, 336 insertions(+) > > create mode 100644 board/intel/slimbootloader/Kconfig > > create mode 100644 board/intel/slimbootloader/Makefile > > create mode 100644 board/intel/slimbootloader/slimbootloader.c > > create mode 100644 board/intel/slimbootloader/start.S > > create mode 100644 configs/slimbootloader_defconfig > > create mode 100644 doc/board/intel/slimbootloader.rst > > create mode 100644 include/configs/slimbootloader.h > > > > Tested-by: Bin Meng This time I successfully built the slimbootloader payload by following the instructions in the documentation and it succeeded to boot. Thanks for the efforts! However when testing zboot from U-Boot, I got: Error: Invalid Boot Flag (found 0x5aa5, expected 0xaa55) ## Kernel loading failed ... zboot - Boot bzImage The same kernel bzImage boots fine with "qemu-x86_defconfig" target. Did you see such issue? This is not a show-stopper. I will apply this series soon. Regards, Bin ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v9 9/9] x86: Skip setting up MTRRs in slimbootloader
On Sat, Aug 3, 2019 at 4:31 PM Park, Aiden wrote: > > The setting up MTRRs have already been done in previous > Slim Bootloader stages. > > Signed-off-by: Aiden Park > Reviewed-by: Bin Meng > Reviewed-by: Andy Shevchenko > --- > arch/x86/lib/init_helpers.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > Tested-by: Bin Meng ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v9 8/9] board: intel: Add new slimbootloader board
On Sat, Aug 3, 2019 at 4:31 PM Park, Aiden wrote: > > Add slimbootloader board to run U-boot as a Slim Bootloader payload > - Add new board/intel/slimbootloader directory with minimum codes > - Add slimbootloader configuration files > - Add doc/board/intel/slimbootloader.rst > > Signed-off-by: Aiden Park > Reviewed-by: Bin Meng > Reviewed-by: Andy Shevchenko > --- > Changes in v8: > * Add a space between acronym and (definition) > > Changes in v7: > * Adding slimbootloader.rst in index.rst > > Changes in v6: > * Select CONFIG_SYS_SLIMBOOTLOADER in board Kconfig > * Move USB_STORAGE and USB_KEYBOARD to board Kconfig > * Convert README to reST doc/board/intel/slimbootloader.rst > > Changes in v5: > * Remove X86_LOAD_FROM_32_BIT from slimbootloader_defconfig > > Changes in v3: > * Remove VENDOR_SLIMBOOTLOADER > * Use VENDOR_INTEL > * Move slimbootloader under board/intel/ > * Enable generic CONFIGs in slimbootloader_defconfig > * Add more description in board/intel/slimbootloader/README > > board/intel/Kconfig | 14 ++ > board/intel/slimbootloader/Kconfig | 28 > board/intel/slimbootloader/Makefile | 5 + > board/intel/slimbootloader/slimbootloader.c | 21 +++ > board/intel/slimbootloader/start.S | 9 + > configs/slimbootloader_defconfig| 22 +++ > doc/board/intel/index.rst | 1 + > doc/board/intel/slimbootloader.rst | 174 > include/configs/slimbootloader.h| 62 +++ > 9 files changed, 336 insertions(+) > create mode 100644 board/intel/slimbootloader/Kconfig > create mode 100644 board/intel/slimbootloader/Makefile > create mode 100644 board/intel/slimbootloader/slimbootloader.c > create mode 100644 board/intel/slimbootloader/start.S > create mode 100644 configs/slimbootloader_defconfig > create mode 100644 doc/board/intel/slimbootloader.rst > create mode 100644 include/configs/slimbootloader.h > Tested-by: Bin Meng ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v9 7/9] x86: slimbootloader: Add a slimbootloader device tree
On Sat, Aug 3, 2019 at 4:31 PM Park, Aiden wrote: > > Add a new device tree which has very minimum nodes > - x86 reset > - x86 tsc_timer > - x86 pci > - Slim Bootloader serial > > Signed-off-by: Aiden Park > Reviewed-by: Bin Meng > Reviewed-by: Andy Shevchenko > --- > Changes in v3: > * Move slimbootloader.dtb before baytrail_som-db5800-som-6867.dtb > > arch/x86/dts/Makefile | 1 + > arch/x86/dts/slimbootloader.dts | 27 +++ > 2 files changed, 28 insertions(+) > create mode 100644 arch/x86/dts/slimbootloader.dts > Tested-by: Bin Meng ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v9 5/9] x86: slimbootloader: Add serial driver
On Sat, Aug 3, 2019 at 4:30 PM Park, Aiden wrote: > > Slim Bootloader provides serial port info thru its HOB list pointer. > All these HOBs are eligible for Slim Bootloader based board only. > - Get serial port information from the serial port info HOB > - Leverage ns16550 driver with slimbootloader specific platform data > > Signed-off-by: Aiden Park > Reviewed-by: Bin Meng > Reviewed-by: Andy Shevchenko > --- > Changes in v6: > * Use EFI_GUID > * Apply code-review comments > > Changes in v4: > * Add static keyword in static function > > Changes in v3: > * Use HOB function from the common HOB library > > arch/x86/cpu/slimbootloader/Makefile | 2 +- > arch/x86/cpu/slimbootloader/serial.c | 67 +++ > .../asm/arch-slimbootloader/slimbootloader.h | 34 ++ > 3 files changed, 102 insertions(+), 1 deletion(-) > create mode 100644 arch/x86/cpu/slimbootloader/serial.c > Tested-by: Bin Meng ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v9 4/9] x86: slimbootloader: Add memory configuration
On Sat, Aug 3, 2019 at 4:30 PM Park, Aiden wrote: > > Slim Bootloader provides memory map info thru its HOB list pointer. > Configure memory size and relocation memory from the HOB data, and > provide e820 entries as well. > - Get memory size from the memory map info HOB > - Set available top memory lower than 4GB for U-Boot relocation > - Provide e820 entries from the memory map info HOB > > Signed-off-by: Aiden Park > Reviewed-by: Bin Meng > Reviewed-by: Andy Shevchenko > --- > Changes in v9: > * Use for_each_if macro to avoid checkpatch ERROR > > Changes in v8: > * Change for_each condition check to avoid ERROR from checkpatch > > Changes in v7: > * Use for_each macro instead of while_each > * Move for_each macro before its first use > > Changes in v6: > * Change dram.c to sdram.c > * Use EFI_GUID > * Use a macro to do reversed search in memory map entries > * Apply code-review comments > > Changes in v3: > * Use HOB function from the common HOB library > * Add more description > > arch/x86/cpu/slimbootloader/Makefile | 2 +- > arch/x86/cpu/slimbootloader/sdram.c | 151 ++ > .../asm/arch-slimbootloader/slimbootloader.h | 53 ++ > 3 files changed, 205 insertions(+), 1 deletion(-) > create mode 100644 arch/x86/cpu/slimbootloader/sdram.c > create mode 100644 arch/x86/include/asm/arch-slimbootloader/slimbootloader.h > Tested-by: Bin Meng ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v9 6/9] x86: slimbootloader: Set TSC information for tsc_timer
On Sat, Aug 3, 2019 at 4:30 PM Park, Aiden wrote: > > Slim Bootloader already calibrated TSC and provides it to U-Boot. > Therefore, U-Boot does not have to re-calibrate TSC. > Configuring tsc_base and clock_rate makes x86 tsc_timer driver bypass > TSC calibration and use the provided TSC frequency. > - Get TSC frequency from performance info hob > - Set tsc_base and clock_rate for tsc_timer driver > > Signed-off-by: Aiden Park > Reviewed-by: Bin Meng > --- > Changes in v6: > * Use EFI_GUID > * Add more comments while setting tsc_base and clock_rate > * Apply code-review comments > > Changes in v3: > * Use HOB function from the common HOB library > > arch/x86/cpu/slimbootloader/slimbootloader.c | 37 +++ > .../asm/arch-slimbootloader/slimbootloader.h | 28 ++ > 2 files changed, 65 insertions(+) > Tested-by: Bin Meng ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v8 1/9] x86: Add new slimbootloader CPU type
On Fri, Aug 2, 2019 at 3:03 PM Park, Aiden wrote: > > This slimbootloader CPU type is to enable U-Boot as a payload which > runs on top of Slim Bootloader (https://github.com/slimbootloader). > The Slim Bootloader is designed with multi-stage architecture for > the execution from reset vector to OS booting, and supports QEMU, > Apollolake, Whiskeylake and Coffeelake platforms consuming Intel > FSP (https://github.com/IntelFsp) for silicon initialization > including CAR and memory initialization. > The Slim Bootloader generates new HOB (Hand Off Block) which are > serial port info, memory map info, performance data info and so on, > and passes it to a Payload. U-Boot as a payload will use these HOB > information for basic initialization such as serial console. > > As an initial commit, > - Add CONFIG_SYS_SLIMBOOTLOADER to enable slimbootloader CPU type > - Add new arch/x86/cpu/slimbootloader directory with minimum codes > - Get hob_list pointer from Slim Bootloader > > Signed-off-by: Aiden Park > Reviewed-by: Bin Meng > Reviewed-by: Andy Shevchenko > --- > Changes in v8: > * Add a space between acronym and (definition) > > Changes in v6: > * Add CONFIG_USE_HOB > * Move some CONFIGs to board Kconfig > * Remove arch-slimbootloader/slimbooloader.h > * Apply code-review comments > > Changes in v4: > * Use common arch/x86/cpu/start.S > * Update U-boot or u-boot to U-Boot in commit message > > Changes in v3: > * Add a brief description about Slim Bootloader > * Enable USB_KEYBOARD, E1000 and RTL8169 by default > * Fix comment from code review > > arch/x86/Kconfig | 9 + > arch/x86/cpu/Makefile| 1 + > arch/x86/cpu/slimbootloader/Kconfig | 19 ++ > arch/x86/cpu/slimbootloader/Makefile | 5 + > arch/x86/cpu/slimbootloader/car.S| 14 + > arch/x86/cpu/slimbootloader/slimbootloader.c | 21 > arch/x86/cpu/start.S | 6 -- > arch/x86/include/asm/global_data.h | 2 +- > arch/x86/lib/asm-offsets.c | 2 +- > 9 files changed, 75 insertions(+), 4 deletions(-) > create mode 100644 arch/x86/cpu/slimbootloader/Kconfig > create mode 100644 arch/x86/cpu/slimbootloader/Makefile > create mode 100644 arch/x86/cpu/slimbootloader/car.S > create mode 100644 arch/x86/cpu/slimbootloader/slimbootloader.c > Tested-by: Bin Meng ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] riscv: cpu: Skip unavailable hart in the get_count() op
Hi Bin, On Thu, 2019-08-08 at 21:25 +0800, Bin Meng wrote: > Hi Lukas, > > On Thu, Aug 8, 2019 at 7:22 PM Auer, Lukas > wrote: > > Hi Bin, > > > > On Thu, 2019-08-08 at 00:52 -0700, Bin Meng wrote: > > > We should not count in hart that is marked as not available in the > > > device tree in riscv_cpu_get_count(). > > > > > > > I think it might make sense to also exclude harts that are not listed > > as available in the available_harts mask. So the same logic as in > > arch/riscv/lib/smp.c. In this case, the bind function should probably > > check the mask as well. > > > > Yes, the check to available_harts mask can be added in > riscv_cpu_get_count(). I will do that. > > However, I doubt we could do available_harts mask check in the bind > function. If it returns error for non-available harts, the whole > initialization process fails. > You are right, I did not think about that. Perhaps it's best to ignore the available_harts mask in the count function as well then. It just checked where cpu_get_count() is used. The Andes PLIC driver (lib/andes_plic.c) uses it in a way that the patch might break the driver. It iterates over all harts, assuming the first hart is 0 and the last hart the result of cpu_get_count(). If any of the harts is set to disabled, this will no longer be true. It's probably best to update the driver to use the ofnode_for_each_subnode() macro to iterate over all harts. Rick, can you update the driver? Thanks, Lukas > > Looks good otherwise! > > > > Reviewed-by: Lukas Auer > > > > Regards, > Bin ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 1/3] spl: imx6: Let spl_boot_device return USDHC1 or USDHC2
On Thu, Aug 8, 2019 at 10:13 AM Adam Ford wrote:
> On Wed, Aug 7, 2019 at 6:44 PM Ricardo Salveti wrote:
> > Hi Adam,
> >
> > On Thu, May 23, 2019 at 4:11 PM Adam Ford wrote:
> > >
> > > Currently, when the spl_boot_device checks the boot device, it
> > > will only return MMC1 when it's either sd or eMMC regardless
> > > of whether or not it's MMC1 or MMC2. This is a problem when
> > > booting from MMC2 if MMC isn't being manually configured like in
> > > the DM_SPL case with SPL_OF_CONTROL.
> > >
> > > This patch will check the register and return either MMC1 or MMC2.
> > >
> > > Signed-off-by: Adam Ford
> > >
> > > diff --git a/arch/arm/mach-imx/spl.c b/arch/arm/mach-imx/spl.c
> > > index 9f1e0f6a72..1f230aca33 100644
> > > --- a/arch/arm/mach-imx/spl.c
> > > +++ b/arch/arm/mach-imx/spl.c
> > > @@ -24,6 +24,7 @@ u32 spl_boot_device(void)
> > > {
> > > unsigned int bmode = readl(_base->sbmr2);
> > > u32 reg = imx6_src_get_boot_mode();
> > > + u32 mmc_index = ((reg >> 11) & 0x03);
> > >
> > > /*
> > > * Check for BMODE if serial downloader is enabled
> > > @@ -84,11 +85,12 @@ u32 spl_boot_device(void)
> > > /* SD/eSD: 8.5.3, Table 8-15 */
> > > case IMX6_BMODE_SD:
> > > case IMX6_BMODE_ESD:
> > > - return BOOT_DEVICE_MMC1;
> > > - /* MMC/eMMC: 8.5.3 */
> > > case IMX6_BMODE_MMC:
> > > case IMX6_BMODE_EMMC:
> > > - return BOOT_DEVICE_MMC1;
> > > + if (mmc_index == 1)
> > > + return BOOT_DEVICE_MMC2;
> > > + else
> > > + return BOOT_DEVICE_MMC1;
> >
> > I just got to test v2019.10-rc1, which includes this change, and I'm
> > unable to boot SPL on my Hummingboard 2, which uses USDHC-2 for
> > sdcard.
>
> I wondered if it would break a board. It's why I originally sent it
> as an RFC. In my mind, it seems like we've created a system that only
> supports one MMC, then we created a work-around to correctly identify
> the MMC because the original implementation didn't. I will admit, my
> patch only checks for MMC1 or MMC2, but I don't have hardware to test
> MMC3.
> >
> > Looks like this change breaks devices that are not using device
> > tree/dynamic mmc initialization, as the MMC index will not necessarily
> > be correct.
>
> How hard would it be to use the device tree/dynamic initialization for
> your board? It seems to be the trend, and at least in some cases,
> they've made it required and boards that don't comply get removed. It
> seems like we're prolonging. I'd be open for an #ifdef hook around
> it, but I am not sure how that would fly with the maintainers. My
> goal is to remove as much board-specific code as possible and move it
> to the shared code to reduce the overhead and code size. Checking for
> SPL_OF_CONTROL && DM_MMC might be potential work-around to the
> work-around.
I agree that moving to use device tree/dynamic initialization is the
way to go, but in this case we should probably have an ifdef as you
suggested, so we can avoid breaking the boot process while everything
gets migrated to dt.
Cheers,
--
Ricardo Salveti de Araujo
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v4] x86: ich-spi: Convert driver to spi-mem ops
On Fri, Aug 2, 2019 at 2:38 PM Bernhard Messerklinger wrote: > > With the introduction of the new spi-mem model operations changed > slightly. The new spi-mem operations make things a bit easier to > handle for ich-spi flash interface. This patch converts the ich-spi > driver by using spi-mem operations. > > Signed-off-by: Bernhard Messerklinger > > --- > > Changes in v4: > - fix changelog; fix local variable types and order > Changes in v3: > - update erase op code handling to work with latest master > spi-nor driver > Changes in v2: > - make 2 routines static; update commit message a little bit > > drivers/spi/ich.c | 258 +- > drivers/spi/ich.h | 9 +- > 2 files changed, 95 insertions(+), 172 deletions(-) > Reviewed-by: Bin Meng Tested on Intel CrownBay and MinnowMax Tested-by: Bin Meng ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 1/1] bios_emulator: remove stray break
On Fri, Aug 2, 2019 at 1:37 AM Heinrich Schuchardt wrote: > > Remove a stray break which suppresses some debug messages. > > Indicated by cppcheck. > > Signed-off-by: Heinrich Schuchardt > --- > @Simon: > Please, test on an x86 Chromebook. I have no access to a test device. > --- > drivers/bios_emulator/atibios.c | 1 - > 1 file changed, 1 deletion(-) > Acked-by: Bin Meng ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] riscv: cpu: Skip unavailable hart in the get_count() op
Hi Lukas, On Thu, Aug 8, 2019 at 7:22 PM Auer, Lukas wrote: > > Hi Bin, > > On Thu, 2019-08-08 at 00:52 -0700, Bin Meng wrote: > > We should not count in hart that is marked as not available in the > > device tree in riscv_cpu_get_count(). > > > > I think it might make sense to also exclude harts that are not listed > as available in the available_harts mask. So the same logic as in > arch/riscv/lib/smp.c. In this case, the bind function should probably > check the mask as well. > Yes, the check to available_harts mask can be added in riscv_cpu_get_count(). I will do that. However, I doubt we could do available_harts mask check in the bind function. If it returns error for non-available harts, the whole initialization process fails. > Looks good otherwise! > > Reviewed-by: Lukas Auer > Regards, Bin ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 1/3] spl: imx6: Let spl_boot_device return USDHC1 or USDHC2
On Wed, Aug 7, 2019 at 6:44 PM Ricardo Salveti wrote:
>
> Hi Adam,
>
> On Thu, May 23, 2019 at 4:11 PM Adam Ford wrote:
> >
> > Currently, when the spl_boot_device checks the boot device, it
> > will only return MMC1 when it's either sd or eMMC regardless
> > of whether or not it's MMC1 or MMC2. This is a problem when
> > booting from MMC2 if MMC isn't being manually configured like in
> > the DM_SPL case with SPL_OF_CONTROL.
> >
> > This patch will check the register and return either MMC1 or MMC2.
> >
> > Signed-off-by: Adam Ford
> >
> > diff --git a/arch/arm/mach-imx/spl.c b/arch/arm/mach-imx/spl.c
> > index 9f1e0f6a72..1f230aca33 100644
> > --- a/arch/arm/mach-imx/spl.c
> > +++ b/arch/arm/mach-imx/spl.c
> > @@ -24,6 +24,7 @@ u32 spl_boot_device(void)
> > {
> > unsigned int bmode = readl(_base->sbmr2);
> > u32 reg = imx6_src_get_boot_mode();
> > + u32 mmc_index = ((reg >> 11) & 0x03);
> >
> > /*
> > * Check for BMODE if serial downloader is enabled
> > @@ -84,11 +85,12 @@ u32 spl_boot_device(void)
> > /* SD/eSD: 8.5.3, Table 8-15 */
> > case IMX6_BMODE_SD:
> > case IMX6_BMODE_ESD:
> > - return BOOT_DEVICE_MMC1;
> > - /* MMC/eMMC: 8.5.3 */
> > case IMX6_BMODE_MMC:
> > case IMX6_BMODE_EMMC:
> > - return BOOT_DEVICE_MMC1;
> > + if (mmc_index == 1)
> > + return BOOT_DEVICE_MMC2;
> > + else
> > + return BOOT_DEVICE_MMC1;
>
> I just got to test v2019.10-rc1, which includes this change, and I'm
> unable to boot SPL on my Hummingboard 2, which uses USDHC-2 for
> sdcard.
I wondered if it would break a board. It's why I originally sent it
as an RFC. In my mind, it seems like we've created a system that only
supports one MMC, then we created a work-around to correctly identify
the MMC because the original implementation didn't. I will admit, my
patch only checks for MMC1 or MMC2, but I don't have hardware to test
MMC3.
>
> Looks like this change breaks devices that are not using device
> tree/dynamic mmc initialization, as the MMC index will not necessarily
> be correct.
How hard would it be to use the device tree/dynamic initialization for
your board? It seems to be the trend, and at least in some cases,
they've made it required and boards that don't comply get removed. It
seems like we're prolonging. I'd be open for an #ifdef hook around
it, but I am not sure how that would fly with the maintainers. My
goal is to remove as much board-specific code as possible and move it
to the shared code to reduce the overhead and code size. Checking for
SPL_OF_CONTROL && DM_MMC might be potential work-around to the
work-around.
>
> Looking at mx6cuboxi.c in particular, fsl_esdhc_initialize will only
> be called once as it already knows which MMC device to initialize
> based on the BOOT_CFG register, causing the device mmc devnum to be 1
> only. The issue shows up when booting SPL as find_mmc_device will look
> for a matching dev_num index, which gets automatically increased when
> fsl_esdhc_initialize gets called (and which is only called once in my
> case, for MMC2).
>
> This is not an issue with imx6q_logic as at
> 8f4691e31a18254d225524a4b018b8cbcddc70b1 you removed
> fsl_esdhc_initialize, but all the other boards using MMC2 and doing
> only one single call will have the same problem.
>
> Not sure if there is an easy fix here, but converting everything to
> dynamic mmc initialization will required quite a bit of effort.
A bunch of boards have already started migrating to SPL_OF_CONTROL and
DM_MMC. The imx6q_logic board was just a matter of changing some
config options and fixing and/or creating a -u-boot.dtsi file to
enable the various drivers in SPL, then removing the legacy code.
Stefano, what would your preference be?
adam
>
> Thanks,
> --
> Ricardo Salveti de Araujo
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v1] MAINTAINERS: Add entries for Android A/B and AVB
Hi Tom On Thu, Aug 8, 2019 at 3:33 PM Igor Opaniuk wrote: > > 1. Add myself as Android A/B and AVB maintainer > 2. Add Sam Protsenko as Designated reviewer for A/B > > Signed-off-by: Igor Opaniuk > > --- > > MAINTAINERS | 20 > 1 file changed, 20 insertions(+) > > diff --git a/MAINTAINERS b/MAINTAINERS > index b443c5af75..5e601b5ff3 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -50,6 +50,26 @@ so much easier [Ed] > Maintainers List (try to look for most precise areas first) > > --- > +ANDROID AB > +M: Igor Opaniuk > +R: Sam Protsenko > +S: Maintained > +F: cmd/ab_select.c > +F: common/android_ab.c > +F: doc/android/ab.txt > +F: include/android_ab.h > +F: test/py/tests/test_android/test_ab.py > + > +ANDROID AVB > +M: Igor Opaniuk > +S: Maintained > +F: cmd/avb.c > +F: common/avb_verify.c > +F: doc/android/avb2.txt > +F: include/avb_verify.h > +F: lib/libavb/ > +F: test/py/tests/test_android/test_avb.py > + > ARC > M: Alexey Brodkin > M: Eugeniy Paltsev > -- > 2.17.1 > This is what we discussed yesterday in IRC. Also I'm looking forward for reply from Eugeniu Rosca (sent him email today) if he doesn't mind about adding him as designated reviewer for AVB/AB (as he is one of the top reviewers/contributors to these components). Thanks -- Best regards - Freundliche Grüsse - Meilleures salutations Igor Opaniuk mailto: igor.opan...@gmail.com skype: igor.opanyuk +380 (93) 836 40 67 http://ua.linkedin.com/in/iopaniuk ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v1] MAINTAINERS: Add entries for Android A/B and AVB
1. Add myself as Android A/B and AVB maintainer 2. Add Sam Protsenko as Designated reviewer for A/B Signed-off-by: Igor Opaniuk --- MAINTAINERS | 20 1 file changed, 20 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index b443c5af75..5e601b5ff3 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -50,6 +50,26 @@ so much easier [Ed] Maintainers List (try to look for most precise areas first) --- +ANDROID AB +M: Igor Opaniuk +R: Sam Protsenko +S: Maintained +F: cmd/ab_select.c +F: common/android_ab.c +F: doc/android/ab.txt +F: include/android_ab.h +F: test/py/tests/test_android/test_ab.py + +ANDROID AVB +M: Igor Opaniuk +S: Maintained +F: cmd/avb.c +F: common/avb_verify.c +F: doc/android/avb2.txt +F: include/avb_verify.h +F: lib/libavb/ +F: test/py/tests/test_android/test_avb.py + ARC M: Alexey Brodkin M: Eugeniy Paltsev -- 2.17.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] riscv: cpu: Skip unavailable hart in the get_count() op
Hi Bin,
On Thu, 2019-08-08 at 00:52 -0700, Bin Meng wrote:
> We should not count in hart that is marked as not available in the
> device tree in riscv_cpu_get_count().
>
I think it might make sense to also exclude harts that are not listed
as available in the available_harts mask. So the same logic as in
arch/riscv/lib/smp.c. In this case, the bind function should probably
check the mask as well.
Looks good otherwise!
Reviewed-by: Lukas Auer
Thanks,
Lukas
> Signed-off-by: Bin Meng
> ---
>
> drivers/cpu/riscv_cpu.c | 4
> 1 file changed, 4 insertions(+)
>
> diff --git a/drivers/cpu/riscv_cpu.c b/drivers/cpu/riscv_cpu.c
> index f77c126..28ad0aa 100644
> --- a/drivers/cpu/riscv_cpu.c
> +++ b/drivers/cpu/riscv_cpu.c
> @@ -46,6 +46,10 @@ static int riscv_cpu_get_count(struct udevice *dev)
> ofnode_for_each_subnode(node, dev_ofnode(dev->parent)) {
> const char *device_type;
>
> + /* skip if hart is marked as not available in the device tree */
> + if (!ofnode_is_available(node))
> + continue;
> +
> device_type = ofnode_read_string(node, "device_type");
> if (!device_type)
> continue;
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] GitLab: make pipeline status public
Hi Heinrich, On Wed, 2019-08-07 at 21:26 +0200, Heinrich Schuchardt wrote: > Hello Harald, > > Tom suggested you could help on this issue. > > I suggest that the pipeline status should be public on all custodian > gits, e.g. page > https://gitlab.denx.de/u-boot/custodians/u-boot-efi/pipelines. > > I set the flag "Public pipelines" in the CI settings but this seems > not be sufficient. I still get a 404 error code if I am not logged on. There is another setting you need to enable, IIRC: Under Settings -> General -> Visibility, Permissions -> Pipelines , you need to change the dropdown from "Only Project Members" to "Everyone With Access". Can you check whether that works? > Best regards > > Heinrich -- Harald DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-62 Fax: +49-8142-66989-80 Email: h...@denx.de ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] riscv: qemu: Fix kconfig build warning
On Wed, 2019-08-07 at 23:04 -0700, Bin Meng wrote: > When 'make qemu-riscv64_defconfig', there is a build warning: > > board/emulation/qemu-riscv/Kconfig:24: > warning: config symbol defined without type > > Fix it by specifying the config symbol type to 'hex'. > > Signed-off-by: Bin Meng > --- > > board/emulation/qemu-riscv/Kconfig | 1 + > 1 file changed, 1 insertion(+) > Ah, I missed this. Thanks! Reviewed-by: Lukas Auer ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] U-Boot/EBBR plugfest at ELC-EU?
On 28/06/2019 09:19, Grant Likely wrote: > Quick poll: who would be interested in a U-Boot/EBBR plugfest event > collocates with ELC-EU this year (week of 28th Oct)? > > In the EBBR meetings we’ve tossed around the idea of an U-Boot/EBBR plugfest > to work out compatibility issues between OS distros and upstream U-Boot SBC > support. The idea is to get a number of SBCs supported by mainline U-Boot > with UEFI features turned on, along with U-Boot & OS developers and hold a 1 > day debug sprint to work out how many platforms can work with ‘stock’ OS > images. Details to be worked out if this looks viable. > > I’ve asked the LF folks if they have space on either Thursday 31st Oct or > Friday 1st Nov. They are checking availability, but no commitments have been > made. It would help to know if this date and location is feasible. > > What do you think? Would you come to a plug fest attached to ELC-EU? Would > you be interested in helping to organise? Or, is there another time & > location that would work better? > > Cheers, > g. At this point I've only had about 3 people say they'd be able to attend. That's not enough for critical mass. I think we should defer to another event. I'm going to tell the LF that they can release the space they've reserved for us and I'll look at the calendar and come up with some new options. g. ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] (Offlist) Re: U-Boot/EBBR plugfest at ELC-EU?
On 31/07/2019 20:16, Daniel Kiper wrote: > On Tue, Jul 30, 2019 at 03:33:27PM +, Grant Likely wrote: >>> If you want to discuss something there please put a topic proposal on >>> LPC site. CfP closes on 2nd of August. If you need a pass or invite an >>> expert drop me a line. >> >> Thanks Daniel, >> >> It is certainly a worthy discussion topic for LPC. I’ll see if I can >> draft something for the CfP on Friday. Unfortunately, I may not be at > > Please do it! > >> LPC. I’m not even on the waiting list yet. > > I cannot promise anything but if we accept your proposal then there is a > chance that you will get a pass from us. > > Daniel Hi Daniel, Sorry, I wasn't able to get anything submitted before the deadline, and I'm not going to be able to attend LPC this year anyway. I think it is a worthwhile to discuss UEFI & UEFI Secure Boot support in U-Boot, but it depends entirely on who will be in the room. I'll let someone else pick up the thread if they are attending. g. ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 1/3] spl: imx6: Let spl_boot_device return USDHC1 or USDHC2
Hi Adam,
On Thu, May 23, 2019 at 4:11 PM Adam Ford wrote:
>
> Currently, when the spl_boot_device checks the boot device, it
> will only return MMC1 when it's either sd or eMMC regardless
> of whether or not it's MMC1 or MMC2. This is a problem when
> booting from MMC2 if MMC isn't being manually configured like in
> the DM_SPL case with SPL_OF_CONTROL.
>
> This patch will check the register and return either MMC1 or MMC2.
>
> Signed-off-by: Adam Ford
>
> diff --git a/arch/arm/mach-imx/spl.c b/arch/arm/mach-imx/spl.c
> index 9f1e0f6a72..1f230aca33 100644
> --- a/arch/arm/mach-imx/spl.c
> +++ b/arch/arm/mach-imx/spl.c
> @@ -24,6 +24,7 @@ u32 spl_boot_device(void)
> {
> unsigned int bmode = readl(_base->sbmr2);
> u32 reg = imx6_src_get_boot_mode();
> + u32 mmc_index = ((reg >> 11) & 0x03);
>
> /*
> * Check for BMODE if serial downloader is enabled
> @@ -84,11 +85,12 @@ u32 spl_boot_device(void)
> /* SD/eSD: 8.5.3, Table 8-15 */
> case IMX6_BMODE_SD:
> case IMX6_BMODE_ESD:
> - return BOOT_DEVICE_MMC1;
> - /* MMC/eMMC: 8.5.3 */
> case IMX6_BMODE_MMC:
> case IMX6_BMODE_EMMC:
> - return BOOT_DEVICE_MMC1;
> + if (mmc_index == 1)
> + return BOOT_DEVICE_MMC2;
> + else
> + return BOOT_DEVICE_MMC1;
I just got to test v2019.10-rc1, which includes this change, and I'm
unable to boot SPL on my Hummingboard 2, which uses USDHC-2 for
sdcard.
Looks like this change breaks devices that are not using device
tree/dynamic mmc initialization, as the MMC index will not necessarily
be correct.
Looking at mx6cuboxi.c in particular, fsl_esdhc_initialize will only
be called once as it already knows which MMC device to initialize
based on the BOOT_CFG register, causing the device mmc devnum to be 1
only. The issue shows up when booting SPL as find_mmc_device will look
for a matching dev_num index, which gets automatically increased when
fsl_esdhc_initialize gets called (and which is only called once in my
case, for MMC2).
This is not an issue with imx6q_logic as at
8f4691e31a18254d225524a4b018b8cbcddc70b1 you removed
fsl_esdhc_initialize, but all the other boards using MMC2 and doing
only one single call will have the same problem.
Not sure if there is an easy fix here, but converting everything to
dynamic mmc initialization will required quite a bit of effort.
Thanks,
--
Ricardo Salveti de Araujo
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v3 00/11] SPL support for RISC-V
Hi Lukas > > From: Lukas Auer [mailto:lukas.a...@aisec.fraunhofer.de] > > Sent: Thursday, August 08, 2019 5:12 AM > > To: u-boot@lists.denx.de > > Cc: Atish Patra; Rick Jian-Zhi Chen(陳建志); Bin Meng; Sagar Kadam; Alistair > > Francis; Anup Patel; Troy Benjegerdes; Lukas Auer; Abel Vesa; Alex Kiernan; > > Alex Marginean; Alexander Graf; Andreas Dannenberg; Andrew F. Davis; Anup > > Patel; Anup Patel; Atish Patra; Bartosz Golaszewski; Chris Packham; Eugeniu > > Rosca; Fabio Estevam; Heiko Schocher; Heinrich Schuchardt; Jagan Teki; > > Jean-Jacques Hiblot; Jens Wiklander; Julius Werner; Kever Yang; Lokesh > > Vutla; > > Lukasz Majewski; Marek Vasut; Marek Vasut; Markus Klotzbuecher; Michal > > Simek; Miquel Raynal; Paul Burton; Peng Fan; Philipp Tomsich; Philippe > > Reynes; Ryder Lee; Shawn Guo; Simon Glass; Simon Goldschmidt; Stefan > > Roese; Stefano Babic; Tien Fong Chee; Vignesh R; Ye Li > > Subject: [PATCH v3 00/11] SPL support for RISC-V > > > > This series adds support for SPL to RISC-V U-Boot. Images can be booted via > > OpenSBI (FW_DYNAMIC firmware) or by directly jumping to them. In the > > former case, OpenSBI and U-Boot proper are bundled as a FIT image and made > > available to U-Boot SPL. Currently, only the QEMU board enables U-Boot SPL > > with a dedicated configuration. It uses RAM as SPL boot device. > > > > On many RISC-V CPUs, the device tree is provided to U-Boot by the first > > stage > > bootloader. This requires changes to U-Boot SPL (patches 1, > > 2 and 3), which modify the behavior on other boards as well. > > > > To test this series, OpenSBI has to be compiled first. The fw_dynamic.bin > > binary must be copied into the U-Boot root directory. > > Alternatively, the location of the binary can be specified with the OPENSBI > > environment variable. U-Boot can then be build as normal using the > > configuration qemu-riscv64_spl_defconfig for 64-bit builds or > > qemu-riscv32_spl_defconfig for 32-bit builds. The outputs from the build > > process are the U-Boot SPL binary (spl/u-boot-spl.bin) and the U-Boot FIT > > image (u-boot.itb) containing U-Boot proper and OpenSBI. > > > > U-Boot can be run in QEMU with the following command. > > > > qemu-system-riscv64 -nographic -machine virt -kernel spl/u-boot-spl \ > > -device loader,file=u-boot.itb,addr=0x8020 > > > > Changes in v3: > > - Rebase on u-boot-riscv/master > > - Update commit message to include minimum version of OpenSBI > > - Rebase on u-boot/master > > - Add note on minimum version of OpenSBI > > I have applied the patchsets to u-boot-riscv/master, thanks! Regards, Rick > > Changes in v2: > > - Rebase on master and format documentation as reStructuredText > > > > Lukas Auer (11): > > fdtdec: make CONFIG_OF_PRIOR_STAGE available in SPL > > Makefile: support building SPL FIT images without device trees > > spl: fit: use U-Boot device tree when FIT image has no device tree > > riscv: add run mode configuration for SPL > > spl: support booting via RISC-V OpenSBI > > riscv: add SPL support > > riscv: support SPL stack and global data relocation > > riscv: add a generic FIT generator script > > riscv: set default FIT generator script and build target for SPL > > builds > > riscv: qemu: add SPL configuration > > doc: update QEMU RISC-V documentation > > > > Kconfig | 4 +- > > Makefile| 8 +- > > arch/Kconfig| 6 ++ > > arch/riscv/Kconfig | 36 +++-- > > arch/riscv/cpu/ax25/Kconfig | 6 +- > > arch/riscv/cpu/cpu.c| 6 +- > > arch/riscv/cpu/generic/Kconfig | 5 +- > > arch/riscv/cpu/start.S | 62 ++- > > arch/riscv/cpu/u-boot-spl.lds | 82 +++ > > arch/riscv/include/asm/encoding.h | 2 +- > > arch/riscv/include/asm/spl.h| 31 > > arch/riscv/lib/Makefile | 8 +- > > arch/riscv/lib/mkimage_fit_opensbi.sh | 100 > > > > arch/riscv/lib/spl.c| 48 > > board/emulation/qemu-riscv/Kconfig | 10 +++ > > board/emulation/qemu-riscv/MAINTAINERS | 2 + > > board/emulation/qemu-riscv/qemu-riscv.c | 17 > > common/image.c | 1 + > > common/spl/Kconfig | 17 > > common/spl/Makefile | 1 + > > common/spl/spl.c| 8 +- > > common/spl/spl_fit.c| 37 ++--- > > common/spl/spl_opensbi.c| 85 > > > > configs/qemu-riscv32_spl_defconfig | 11 +++ > > configs/qemu-riscv64_spl_defconfig | 12 +++ > > doc/board/emulation/qemu-riscv.rst | 60 +- > > include/configs/qemu-riscv.h| 14 > > include/fdtdec.h| 2 +- > > include/image.h
