[U-Boot] [U-BOOT PATCH] riscv: sifive: fu540: set serial environment variable from otp
This patch sets the serial# environment variable by reading the
board serial number from the OTP memory region.
Signed-off-by: Sagar Shrikant Kadam
---
board/sifive/fu540/fu540.c | 18 ++
1 file changed, 14 insertions(+), 4 deletions(-)
diff --git a/board/sifive/fu540/fu540.c b/board/sifive/fu540/fu540.c
index 11daf1a..06bf442 100644
--- a/board/sifive/fu540/fu540.c
+++ b/board/sifive/fu540/fu540.c
@@ -122,10 +122,20 @@ static void fu540_setup_macaddr(u32 serialnum)
int misc_init_r(void)
{
- /* Set ethaddr environment variable if not set */
- if (!env_get("ethaddr"))
- fu540_setup_macaddr(fu540_read_serialnum());
-
+ u32 serial_num;
+ char buf[11] = {0};
+
+ /* Set ethaddr environment variable from board serial number */
+ if (!env_get("serial#")) {
+ serial_num = fu540_read_serialnum();
+ if (!serial_num) {
+ WARN(1, "Board serial number should not be 0 !!");
+ return 0;
+ }
+ snprintf(buf, sizeof(buf), "%08x", serial_num);
+ env_set("serial#", buf);
+ fu540_setup_macaddr(serial_num);
+ }
return 0;
}
--
2.7.4
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[U-Boot] [U-BOOT PATCH] set serial environment variable
This patch sets serial environment variable by reading the OTP memory region of FU540-C000 SoC which is mounted on HiFive Unleashed A00 board. The patch is based on master branch of[1] [1] https://gitlab.denx.de/u-boot/custodians/u-boot-riscv Following is the result: U-Boot 2019.10-rc1-03748-gab38b00-dirty (Aug 11 2019 - 23:14:27 -0700) CPU: rv64imafdc Model: SiFive HiFive Unleashed A00 DRAM: 8 GiB MMC: spi@1005:mmc@0: 0 In:serial@1001 Out: serial@1001 Err: serial@1001 Net: eth0: ethernet@1009 Hit any key to stop autoboot: 0 => env print serial# serial#=00d0 Sagar Shrikant Kadam (1): riscv: sifive: fu540: set serial environment variable from otp board/sifive/fu540/fu540.c | 18 ++ 1 file changed, 14 insertions(+), 4 deletions(-) -- 2.7.4 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v2 07/11] imx: tpc70: dts: Add TPC70 board (imx6q based) device tree description
Hi Tom, > On Sun, Aug 11, 2019 at 11:25:37PM +0200, Lukasz Majewski wrote: > > Hi Peng, > > > > > > Subject: [PATCH v2 07/11] imx: tpc70: dts: Add TPC70 board > > > > (imx6q based) device tree description > > > > > > > > This commit defines the TPC70 imx6q board with device tree > > > > description. > > > > > > Is the imx6q-kp.dtsi usable for this board from Linux kernel? > > > > > > > The imx6q-kp.dtsi is defined in the Linux kernel [1]. > > > > However, not all features - like backlight, CAN, etc. are needed in > > U-Boot. To reduce SPL footprint, as the TPC70 is the first > > board (from i.MX6Q family of SoCs) which uses only DM in SPL and > > U-Boot proper, only the necessary subset of [1] was added to U-Boot. > > > > Note: > > > > [1] - > > https://elixir.bootlin.com/linux/v5.2.8/source/arch/arm/boot/dts/imx6q-kp.dtsi > > > > Right, and that's what we have CONFIG_OF_SPL_REMOVE_PROPS for, yes? > Not quite. For example I need "clocks" property, which is defined for almost all nodes. This incurs some extra cost in terms of footprint. To reduce the SPL size (to which dtb file size contributes), I had to not include full DTS from Linux in U-Boot. I only used a subset of it (only _really_ necessary description to run U-Boot) to reduce size of SPL binary. Best regards, Lukasz Majewski -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lu...@denx.de pgpTPaSORA5tc.pgp Description: OpenPGP digital signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] core: ofnode: do not assert if node not valid in ofnode_get_name()【请注意，邮件由s...@google.com代发】
Hi Simon, Who is suppose to apply this patch, it's delegate to Philipp now, should I take it? Thanks, - Kever On 2019/7/25 上午3:48, Simon Glass wrote: On Thu, 18 Jul 2019 at 20:24, Kever Yang wrote: In some case with LIVE DT, some node always not valid, or not have a valid name, eg. blk driver add by mmc. Return fail instead of Assert for this kind of ofnode, and this help with assert happen from time to time when of_live is enabled and DEBUG is enabled. Signed-off-by: Kever Yang --- drivers/core/ofnode.c | 6 +- 1 file changed, 5 insertions(+), 1 deletion(-) Reviewed-by: Simon Glass ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v0] rockchip: rk3399: Add ROC-RK3399-PC support
Hi Levin,
On 2019/7/26 下午3:43, d...@t-chip.com.cn wrote:
From: Levin Du
Add initial support for ROC-RK3399-PC board.
Specification
- Rockchip RK3399
- LPDDR4 4GiB
- eMMC slot
- SD card slot
- RTL8211E 1Gbps
- HDMI Out, DP, MIPI DSI/CSI, EDP
- PCIe M.2
- USB 2.0, USB-3.0
- USB C Type
Commit details of rk3399-roc-pc.dts sync from Linux v5.2:
"arm64: dts: rockchip: add support for ROC-RK3399-PC board"
(sha1: 8bb878cf20ae10809c36db96993bfce7026d062b)
Signed-off-by: Levin Du
Reviewed-by: Kever Yang
Thanks,
- Kever
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/rk3399-roc-pc-u-boot.dtsi | 18 +
arch/arm/dts/rk3399-roc-pc.dts | 680 +
board/rockchip/evb_rk3399/MAINTAINERS | 6 +
configs/roc-rk3399-pc_defconfig| 61 +++
5 files changed, 766 insertions(+)
create mode 100644 arch/arm/dts/rk3399-roc-pc-u-boot.dtsi
create mode 100644 arch/arm/dts/rk3399-roc-pc.dts
create mode 100644 configs/roc-rk3399-pc_defconfig
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index f5535078c720..547f609e63b0 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -115,6 +115,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \
rk3399-puma-ddr1333.dtb \
rk3399-puma-ddr1600.dtb \
rk3399-puma-ddr1866.dtb \
+ rk3399-roc-pc.dtb \
rk3399-rock-pi-4.dtb \
rk3399-rock960.dtb \
rk3399-rockpro64.dtb
diff --git a/arch/arm/dts/rk3399-roc-pc-u-boot.dtsi
b/arch/arm/dts/rk3399-roc-pc-u-boot.dtsi
new file mode 100644
index ..77d5cf5d3cd6
--- /dev/null
+++ b/arch/arm/dts/rk3399-roc-pc-u-boot.dtsi
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Levin Du
+ */
+
+#include "rk3399-u-boot.dtsi"
+#include "rk3399-sdram-lpddr4-100.dtsi"
+
+/ {
+ chosen {
+ u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc;
+ };
+};
+
+&vdd_log {
+ regulator-min-microvolt = <43>;
+ regulator-init-microvolt = <95>;
+};
diff --git a/arch/arm/dts/rk3399-roc-pc.dts b/arch/arm/dts/rk3399-roc-pc.dts
new file mode 100644
index ..19f7732d728c
--- /dev/null
+++ b/arch/arm/dts/rk3399-roc-pc.dts
@@ -0,0 +1,680 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2017 T-Chip Intelligent Technology Co., Ltd
+ */
+
+/dts-v1/;
+#include
+#include "rk3399.dtsi"
+#include "rk3399-opp.dtsi"
+
+/ {
+ model = "Firefly ROC-RK3399-PC Board";
+ compatible = "firefly,roc-rk3399-pc", "rockchip,rk3399";
+
+ chosen {
+ stdout-path = "serial2:150n8";
+ };
+
+ backlight: backlight {
+ compatible = "pwm-backlight";
+ pwms = <&pwm0 0 25000 0>;
+ };
+
+ clkin_gmac: external-gmac-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <12500>;
+ clock-output-names = "clkin_gmac";
+ #clock-cells = <0>;
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ clocks = <&rk808 1>;
+ clock-names = "ext_clock";
+ pinctrl-names = "default";
+ pinctrl-0 = <&wifi_enable_h>;
+
+ /*
+* On the module itself this is one of these (depending
+* on the actual card populated):
+* - SDIO_RESET_L_WL_REG_ON
+* - PDN (power down when low)
+*/
+ reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>;
+ };
+
+ vcc_vbus_typec0: vcc-vbus-typec0 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_vbus_typec0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <500>;
+ regulator-max-microvolt = <500>;
+ };
+
+ /*
+* should be placed inside mp8859, but not until mp8859 has
+* its own dt-binding.
+*/
+ vcc12v_sys: mp8859-dcdc1 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc12v_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1200>;
+ regulator-max-microvolt = <1200>;
+ vin-supply = <&vcc_vbus_typec0>;
+ };
+
+ /* switched by pmic_sleep */
+ vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc1v8_s3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <180>;
+ regulator-max-microvolt = <180>;
+ vin-supply = <&vcc_1v8>;
+ };
+
+ vcc3v3_sys: vcc3v3-sys {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_sys";
+ regulator-always-on;
+ re
Re: [U-Boot] [PATCH 1/1] cmd/bdinfo: sandbox: print the relocation offset
On Sat, Aug 10, 2019 at 5:35 AM Heinrich Schuchardt wrote:
>
> On the sandbox provide the relocation offset. This value can be used for
> debugging with GDB using the `add-symbol-file u-boot ' command.
>
> Signed-off-by: Heinrich Schuchardt
> ---
> cmd/bdinfo.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/cmd/bdinfo.c b/cmd/bdinfo.c
> index 86c17dc427..560c039d37 100644
> --- a/cmd/bdinfo.c
> +++ b/cmd/bdinfo.c
> @@ -395,6 +395,7 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char
> * const argv[])
>
> print_bi_boot_params(bd);
> print_bi_dram(bd);
> + print_num("reloc off", (uintptr_t)(gd->reloc_off + gd->arch.ram_buf));
Shouldn't we print gd->relocaddr directly?
> print_eth_ip_addr();
>
> #if defined(CONFIG_LCD) || defined(CONFIG_VIDEO)
> --
Regards,
Bin
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Re: [U-Boot] [PATCH v2 07/11] imx: tpc70: dts: Add TPC70 board (imx6q based) device tree description
On Sun, Aug 11, 2019 at 11:25:37PM +0200, Lukasz Majewski wrote: > Hi Peng, > > > > Subject: [PATCH v2 07/11] imx: tpc70: dts: Add TPC70 board (imx6q > > > based) device tree description > > > > > > This commit defines the TPC70 imx6q board with device tree > > > description. > > > > Is the imx6q-kp.dtsi usable for this board from Linux kernel? > > > > The imx6q-kp.dtsi is defined in the Linux kernel [1]. > > However, not all features - like backlight, CAN, etc. are needed in > U-Boot. To reduce SPL footprint, as the TPC70 is the first > board (from i.MX6Q family of SoCs) which uses only DM in SPL and U-Boot > proper, only the necessary subset of [1] was added to U-Boot. > > Note: > > [1] - > https://elixir.bootlin.com/linux/v5.2.8/source/arch/arm/boot/dts/imx6q-kp.dtsi Right, and that's what we have CONFIG_OF_SPL_REMOVE_PROPS for, yes? -- Tom signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 01/22] tools: imx8m_image: align spl bin image size
Hi Peng, > Align spl bin image size to 4 byte aligned, because we need > to pad ddr firmware in the end of spl bin. However when enable > SPL OF, the spl dtb will be padded to u-boot-nodtb.bin, then > u-boot-spl.bin size might not be 4 bytes aligned. > > ddr_load_train_firmware in drivers/ddr/imx/imx8m/helper.c I've poked around and there is a U-Boot commit: e3963c0943042afcb38d99041a8dc3d55f092f5f Which adds: "drivers: ddr: introduce DDR driver for i.MX8M" Is there any documentation on how to use it (any ./doc/ entry)? I guess that this code (from helper.c) helps with setting DDR4 controller properly. However, patch 22/22 in this series - which adds EVK imx8m board - doesn't use this function, but it has hardcoded long table of magic numbers to setup DDR controller. I guess that those magic numbers are created from running this code? If yes - would it be possible to train/setup the DDR4 controller in SPL as it is done on i.MX6Q? Or at least provide a detailed documentation on how to use it? > use 4 bytes > aligned address to load ddr firmware, so we need make sure > u-boot-spl.bin is 4 bytes aligned, in this patch we use dd > to create a new file named u-boot-spl-pad.bin, then pad ddr firmware. > > If SPL OF not enabled, this patch not hurt, because `_end` already > is 4 bytes aligned. > > Signed-off-by: Peng Fan > --- > tools/imx8m_image.sh | 5 +++-- > 1 file changed, 3 insertions(+), 2 deletions(-) > > diff --git a/tools/imx8m_image.sh b/tools/imx8m_image.sh > index ec0881a128..08a6a48180 100755 > --- a/tools/imx8m_image.sh > +++ b/tools/imx8m_image.sh > @@ -35,8 +35,9 @@ if [ $post_process = 1 ]; then > objcopy -I binary -O binary --pad-to 0x8000 > --gap-fill=0x0 $srctree/lpddr4_pmu_train_2d_imem.bin > lpddr4_pmu_train_2d_imem_pad.bin cat lpddr4_pmu_train_1d_imem_pad.bin > lpddr4_pmu_train_1d_dmem_pad.bin > lpddr4_pmu_train_1d_fw.bin cat > lpddr4_pmu_train_2d_imem_pad.bin > $srctree/lpddr4_pmu_train_2d_dmem.bin > lpddr4_pmu_train_2d_fw.bin > - cat spl/u-boot-spl.bin lpddr4_pmu_train_1d_fw.bin > lpddr4_pmu_train_2d_fw.bin > spl/u-boot-spl-ddr.bin > - rm -f lpddr4_pmu_train_1d_fw.bin > lpddr4_pmu_train_2d_fw.bin lpddr4_pmu_train_1d_imem_pad.bin > lpddr4_pmu_train_1d_dmem_pad.bin lpddr4_pmu_train_2d_imem_pad.bin > + dd if=spl/u-boot-spl.bin of=spl/u-boot-spl-pad.bin > bs=4 conv=sync > + cat spl/u-boot-spl-pad.bin > lpddr4_pmu_train_1d_fw.bin lpddr4_pmu_train_2d_fw.bin > > spl/u-boot-spl-ddr.bin > + rm -f lpddr4_pmu_train_1d_fw.bin > lpddr4_pmu_train_2d_fw.bin lpddr4_pmu_train_1d_imem_pad.bin > lpddr4_pmu_train_1d_dmem_pad.bin lpddr4_pmu_train_2d_imem_pad.bin > spl/u-boot-spl-pad.bin fi fi Best regards, Lukasz Majewski -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lu...@denx.de pgp_zgUO2V9Og.pgp Description: OpenPGP digital signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 18/22] imx8m: restructure clock.h
On Fri, 9 Aug 2019 04:15:37 +
Peng Fan wrote:
> i.MX8MQ and i.MX8MM use different analog pll design, but they
> share same ccm design.
> Add clock_imx8mq.h for i.MX8MQ
> keep common part in clock.h
>
> Signed-off-by: Peng Fan
> ---
> arch/arm/include/asm/arch-imx8m/clock.h| 491
> +++--
> arch/arm/include/asm/arch-imx8m/clock_imx8mq.h | 424
> + arch/arm/mach-imx/imx8m/clock_imx8mq.c
> | 5 +- 3 files changed, 467 insertions(+), 453 deletions(-) create
> mode 100644 arch/arm/include/asm/arch-imx8m/clock_imx8mq.h
>
> diff --git a/arch/arm/include/asm/arch-imx8m/clock.h
> b/arch/arm/include/asm/arch-imx8m/clock.h index
> e7c1670f6b..7225c760fe 100644 ---
> a/arch/arm/include/asm/arch-imx8m/clock.h +++
> b/arch/arm/include/asm/arch-imx8m/clock.h @@ -1,28 +1,29 @@
> /* SPDX-License-Identifier: GPL-2.0+ */
> /*
> - * Copyright 2017 NXP
> - *
> - * Peng Fan
> + * Copyright 2017-2019 NXP
> */
Is there any problem to not add your name and Copyright?
>
> -#ifndef _ASM_ARCH_IMX8M_CLOCK_H
> -#define _ASM_ARCH_IMX8M_CLOCK_H
> -
> #include
>
> +#ifdef CONFIG_IMX8MQ
> +#include
> +#else
> +#error "Error no clock.h"
> +#endif
> +
> #define MHZ(X) ((X) * 100UL)
>
> -enum pll_clocks {
> - ANATOP_ARM_PLL,
> - ANATOP_GPU_PLL,
> - ANATOP_SYSTEM_PLL1,
> - ANATOP_SYSTEM_PLL2,
> - ANATOP_SYSTEM_PLL3,
> - ANATOP_AUDIO_PLL1,
> - ANATOP_AUDIO_PLL2,
> - ANATOP_VIDEO_PLL1,
> - ANATOP_VIDEO_PLL2,
> - ANATOP_DRAM_PLL,
> +/* Mainly for compatible to imx common code. */
> +enum mxc_clock {
> + MXC_ARM_CLK = 0,
> + MXC_IPG_CLK,
> + MXC_CSPI_CLK,
> + MXC_ESDHC_CLK,
> + MXC_ESDHC2_CLK,
> + MXC_ESDHC3_CLK,
> + MXC_I2C_CLK,
> + MXC_UART_CLK,
> + MXC_QSPI_CLK,
> };
>
> enum clk_slice_type {
> @@ -35,297 +36,6 @@ enum clk_slice_type {
> DRAM_SEL_CLOCK_SLICE,
> };
>
> -enum clk_root_index {
> - MXC_ARM_CLK = 0,
> - ARM_A53_CLK_ROOT= 0,
> - ARM_M4_CLK_ROOT = 1,
> - VPU_A53_CLK_ROOT= 2,
> - GPU_CORE_CLK_ROOT = 3,
> - GPU_SHADER_CLK_ROOT = 4,
> - MAIN_AXI_CLK_ROOT = 16,
> - ENET_AXI_CLK_ROOT = 17,
> - NAND_USDHC_BUS_CLK_ROOT = 18,
> - VPU_BUS_CLK_ROOT= 19,
> - DISPLAY_AXI_CLK_ROOT= 20,
> - DISPLAY_APB_CLK_ROOT= 21,
> - DISPLAY_RTRM_CLK_ROOT = 22,
> - USB_BUS_CLK_ROOT= 23,
> - GPU_AXI_CLK_ROOT= 24,
> - GPU_AHB_CLK_ROOT= 25,
> - NOC_CLK_ROOT= 26,
> - NOC_APB_CLK_ROOT= 27,
> - AHB_CLK_ROOT= 32,
> - IPG_CLK_ROOT= 33,
> - MXC_IPG_CLK = 33,
> - AUDIO_AHB_CLK_ROOT = 34,
> - MIPI_DSI_ESC_RX_CLK_ROOT= 36,
> - DRAM_SEL_CFG= 48,
> - CORE_SEL_CFG= 49,
> - DRAM_ALT_CLK_ROOT = 64,
> - DRAM_APB_CLK_ROOT = 65,
> - VPU_G1_CLK_ROOT = 66,
> - VPU_G2_CLK_ROOT = 67,
> - DISPLAY_DTRC_CLK_ROOT = 68,
> - DISPLAY_DC8000_CLK_ROOT = 69,
> - PCIE1_CTRL_CLK_ROOT = 70,
> - PCIE1_PHY_CLK_ROOT = 71,
> - PCIE1_AUX_CLK_ROOT = 72,
> - DC_PIXEL_CLK_ROOT = 73,
> - LCDIF_PIXEL_CLK_ROOT= 74,
> - SAI1_CLK_ROOT = 75,
> - SAI2_CLK_ROOT = 76,
> - SAI3_CLK_ROOT = 77,
> - SAI4_CLK_ROOT = 78,
> - SAI5_CLK_ROOT = 79,
> - SAI6_CLK_ROOT = 80,
> - SPDIF1_CLK_ROOT = 81,
> - SPDIF2_CLK_ROOT = 82,
> - ENET_REF_CLK_ROOT = 83,
> - ENET_TIMER_CLK_ROOT = 84,
> - ENET_PHY_REF_CLK_ROOT = 85,
> - NAND_CLK_ROOT = 86,
> - QSPI_CLK_ROOT = 87,
> - MXC_ESDHC_CLK = 88,
> - USDHC1_CLK_ROOT = 88,
> - MXC_ESDHC2_CLK = 89,
> - USDHC2_CLK_ROOT = 89,
> - I2C1_CLK_ROOT = 90,
> - MXC_I2C_CLK = 90,
> - I2C2_CLK_ROOT = 91,
> - I2C3_CLK_ROOT = 92,
> - I2C4_CLK_ROOT = 93,
> - UART1_CLK_ROOT = 94,
> - UART2_CLK_ROOT = 95,
> - UART3_CLK_ROOT = 96,
> - UART4_CLK_ROOT = 97,
> - USB_CORE_REF_CLK_ROOT = 98,
> - USB_PHY_REF_CLK_ROOT= 99,
> - GIC_CLK_ROOT= 100,
> - ECSPI1_CLK_ROOT = 101,
> - ECSP
Re: [U-Boot] [PATCH 17/22] imx8m: rename clock to clock_imx8mq
On Fri, 9 Aug 2019 04:15:34 +
Peng Fan wrote:
> i.MX8MQ and i.MX8MM has totally different pll design, so
> rename clock to clock_imx8mq.
>
> Signed-off-by: Peng Fan
> ---
> arch/arm/mach-imx/imx8m/Makefile| 3 ++-
> arch/arm/mach-imx/imx8m/{clock.c => clock_imx8mq.c} | 0
> 2 files changed, 2 insertions(+), 1 deletion(-)
> rename arch/arm/mach-imx/imx8m/{clock.c => clock_imx8mq.c} (100%)
>
> diff --git a/arch/arm/mach-imx/imx8m/Makefile
> b/arch/arm/mach-imx/imx8m/Makefile index feff4941c1..42a1544c6b 100644
> --- a/arch/arm/mach-imx/imx8m/Makefile
> +++ b/arch/arm/mach-imx/imx8m/Makefile
> @@ -3,4 +3,5 @@
> # Copyright 2017 NXP
>
> obj-y += lowlevel_init.o
> -obj-y += clock.o clock_slice.o soc.o
> +obj-y += clock_slice.o soc.o
> +obj-$(CONFIG_IMX8MQ) += clock_imx8mq.o
Shouldn't there be then two CONFIG_ entries? LIke CONFIG_IMX8MM and
CONFIG_IMX8MQ?
> diff --git a/arch/arm/mach-imx/imx8m/clock.c
> b/arch/arm/mach-imx/imx8m/clock_imx8mq.c similarity index 100%
> rename from arch/arm/mach-imx/imx8m/clock.c
> rename to arch/arm/mach-imx/imx8m/clock_imx8mq.c
Best regards,
Lukasz Majewski
--
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HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lu...@denx.de
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Re: [U-Boot] [PATCH 13/22] imx8m: Fix MMU table issue for OPTEE memory
On Fri, 9 Aug 2019 04:15:21 +
Peng Fan wrote:
> When running with OPTEE, the MMU table in u-boot does not remove the
> OPTEE memory from its settings. So ARM speculative prefetch in u-boot
> may access that OPTEE memory. Due to trust zone is enabled by OPTEE
> and that memory is set to secure access, then the speculative
> prefetch will fail and cause various memory issue in u-boot.
> The fail address register and int_status register in trustzone has
> logged that speculative access from u-boot.
>
> Signed-off-by: Peng Fan
> ---
> arch/arm/mach-imx/imx8m/soc.c | 20 ++--
> 1 file changed, 18 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/mach-imx/imx8m/soc.c
> b/arch/arm/mach-imx/imx8m/soc.c index 5115471eff..dd393b581b 100644
> --- a/arch/arm/mach-imx/imx8m/soc.c
> +++ b/arch/arm/mach-imx/imx8m/soc.c
> @@ -112,16 +112,18 @@ static struct mm_region imx8m_mem_map[] = {
> /* DRAM1 */
> .virt = 0x4000UL,
> .phys = 0x4000UL,
> - .size = 0xC000UL,
> + .size = PHYS_SDRAM_SIZE,
Wouldn't this change break other imx8m boards?
> .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
>PTE_BLOCK_OUTER_SHARE
> +#ifdef PHYS_SDRAM_2_SIZE
> }, {
> /* DRAM2 */
> .virt = 0x1UL,
> .phys = 0x1UL,
> - .size = 0x04000UL,
> + .size = PHYS_SDRAM_2_SIZE,
The same here.
> .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
>PTE_BLOCK_OUTER_SHARE
> +#endif
> }, {
> /* List terminator */
> 0,
> @@ -130,6 +132,20 @@ static struct mm_region imx8m_mem_map[] = {
>
> struct mm_region *mem_map = imx8m_mem_map;
>
> +void enable_caches(void)
> +{
> + /*
> + * If OPTEE runs, remove OPTEE memory from MMU table to
> + * avoid speculative prefetch. OPTEE runs at the top of
> + * the first memory bank
> + */
> + if (rom_pointer[1])
> + imx8m_mem_map[5].size -= rom_pointer[1];
> +
> + icache_enable();
> + dcache_enable();
In the other patch (which adds board based on imx8mm - in this series
22/22) the D and I caches were disabled. Why you add code to enable
them and those are not enabled on imx8mm EVK board?
> +}
> +
> static u32 get_cpu_variant_type(u32 type)
> {
> struct ocotp_regs *ocotp = (struct ocotp_regs
> *)OCOTP_BASE_ADDR;
Best regards,
Lukasz Majewski
--
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HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lu...@denx.de
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Re: [U-Boot] [PATCH 11/22] imx8m: add pin header for i.MX8MM
Hi Peng,
> Add pin header file for i.MX8MM
>
What is the origin (e.g. SHA1, branch) of this file?
> To IMX8MM_PAD_NAND_WE_B_USDHC3_CLK, IOMUX_CONFIG_SION needs to be
> selected.
>
> Signed-off-by: Peng Fan
> ---
> arch/arm/include/asm/arch-imx8m/imx8mm_pins.h | 691
> ++ 1 file changed, 691 insertions(+)
> create mode 100644 arch/arm/include/asm/arch-imx8m/imx8mm_pins.h
>
> diff --git a/arch/arm/include/asm/arch-imx8m/imx8mm_pins.h
> b/arch/arm/include/asm/arch-imx8m/imx8mm_pins.h new file mode 100644
> index 00..210e96e1db
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-imx8m/imx8mm_pins.h
> @@ -0,0 +1,691 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright 2018-2019 NXP
> + */
> +
> +#ifndef __ASM_ARCH_IMX8MM_PINS_H__
> +#define __ASM_ARCH_IMX8MM_PINS_H__
> +
> +#include
> +
> +enum {
> + IMX8MM_PAD_GPIO1_IO00_GPIO1_IO0
> = IOMUX_PAD(0x0290, 0x0028, 0, 0x, 0, 0),
> + IMX8MM_PAD_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT
> = IOMUX_PAD(0x0290, 0x0028, 1, 0x, 0, 0),
> + IMX8MM_PAD_GPIO1_IO00_XTALOSC_REF_CLK_32K
> = IOMUX_PAD(0x0290, 0x0028, 5, 0x, 0, 0),
> + IMX8MM_PAD_GPIO1_IO00_CCM_EXT_CLK1
> = IOMUX_PAD(0x0290, 0x0028, 6, 0x, 0, 0), +
> + IMX8MM_PAD_GPIO1_IO01_GPIO1_IO1
> = IOMUX_PAD(0x0294, 0x002C, 0, 0x, 0, 0),
> + IMX8MM_PAD_GPIO1_IO01_PWM1_OUT
> = IOMUX_PAD(0x0294, 0x002C, 1, 0x, 0, 0),
> + IMX8MM_PAD_GPIO1_IO01_XTALOSC_REF_CLK_24M
> = IOMUX_PAD(0x0294, 0x002C, 5, 0x, 0, 0),
> + IMX8MM_PAD_GPIO1_IO01_CCM_EXT_CLK2
> = IOMUX_PAD(0x0294, 0x002C, 6, 0x, 0, 0), +
> + IMX8MM_PAD_GPIO1_IO02_GPIO1_IO2
> = IOMUX_PAD(0x0298, 0x0030, 0, 0x, 0, 0),
> + IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B
> = IOMUX_PAD(0x0298, 0x0030, 1, 0x, 0, 0),
> + IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_ANY
> = IOMUX_PAD(0x0298, 0x0030, 5, 0x, 0, 0), +
> + IMX8MM_PAD_GPIO1_IO03_GPIO1_IO3
> = IOMUX_PAD(0x029C, 0x0034, 0, 0x, 0, 0),
> + IMX8MM_PAD_GPIO1_IO03_USDHC1_VSELECT
> = IOMUX_PAD(0x029C, 0x0034, 1, 0x, 0, 0),
> + IMX8MM_PAD_GPIO1_IO03_SDMA1_EXT_EVENT0
> = IOMUX_PAD(0x029C, 0x0034, 5, 0x, 0, 0), +
> + IMX8MM_PAD_GPIO1_IO04_GPIO1_IO4
> = IOMUX_PAD(0x02A0, 0x0038, 0, 0x, 0, 0),
> + IMX8MM_PAD_GPIO1_IO04_USDHC2_VSELECT
> = IOMUX_PAD(0x02A0, 0x0038, 1, 0x, 0, 0),
> + IMX8MM_PAD_GPIO1_IO04_SDMA1_EXT_EVENT1
> = IOMUX_PAD(0x02A0, 0x0038, 5, 0x, 0, 0), +
> + IMX8MM_PAD_GPIO1_IO05_GPIO1_IO5
> = IOMUX_PAD(0x02A4, 0x003C, 0, 0x, 0, 0),
> + IMX8MM_PAD_GPIO1_IO05_ARM_PLATFORM_M4_NMI
> = IOMUX_PAD(0x02A4, 0x003C, 1, 0x, 0, 0),
> + IMX8MM_PAD_GPIO1_IO05_CCM_PMIC_READY
> = IOMUX_PAD(0x02A4, 0x003C, 5, 0x04BC, 0, 0),
> + IMX8MM_PAD_GPIO1_IO05_SRC_INT_BOOT
> = IOMUX_PAD(0x02A4, 0x003C, 6, 0x, 0, 0), +
> + IMX8MM_PAD_GPIO1_IO06_GPIO1_IO6
> = IOMUX_PAD(0x02A8, 0x0040, 0, 0x, 0, 0),
> + IMX8MM_PAD_GPIO1_IO06_ENET1_MDC
> = IOMUX_PAD(0x02A8, 0x0040, 1, 0x, 0, 0),
> + IMX8MM_PAD_GPIO1_IO06_USDHC1_CD_B
> = IOMUX_PAD(0x02A8, 0x0040, 5, 0x, 0, 0),
> + IMX8MM_PAD_GPIO1_IO06_CCM_EXT_CLK3
> = IOMUX_PAD(0x02A8, 0x0040, 6, 0x, 0, 0), +
> + IMX8MM_PAD_GPIO1_IO07_GPIO1_IO7
> = IOMUX_PAD(0x02AC, 0x0044, 0, 0x, 0, 0),
> + IMX8MM_PAD_GPIO1_IO07_ENET1_MDIO
> = IOMUX_PAD(0x02AC, 0x0044, 1, 0x04C0, 0, 0),
> + IMX8MM_PAD_GPIO1_IO07_USDHC1_WP
> = IOMUX_PAD(0x02AC, 0x0044, 5, 0x, 0, 0),
> + IMX8MM_PAD_GPIO1_IO07_CCM_EXT_CLK4
> = IOMUX_PAD(0x02AC, 0x0044, 6, 0x, 0, 0), +
> + IMX8MM_PAD_GPIO1_IO08_GPIO1_IO8
> = IOMUX_PAD(0x02B0, 0x0048, 0, 0x, 0, 0),
> + IMX8MM_PAD_GPIO1_IO08_ENET1_1588_EVENT0_IN
> = IOMUX_PAD(0x02B0, 0x0048, 1, 0x, 0, 0),
> + IMX8MM_PAD_GPIO1_IO08_USDHC2_RESET_B
> = IOMUX_PAD(0x02B0, 0x0048, 5, 0x, 0, 0),
> + IMX8MM_PAD_GPIO1_IO08_CCM_WAIT
> = IOMUX_PAD(0x02B0, 0x0048, 6, 0x, 0, 0), +
> + IMX8MM_PAD_GPIO1_IO09_GPIO1_IO9
> = IOMUX_PAD(0x02B4, 0x004C, 0, 0x, 0, 0),
> + IMX8MM_PAD_GPIO1_IO09_ENET1_1588_EVENT0_OUT
> = IOMUX_PAD(0x02B4, 0x004C, 1, 0x, 0, 0),
> + IMX8MM_PAD_GPIO1_IO09_USDHC3_RESET_B
> = IOMUX_PAD(0x02B4, 0x004C, 4, 0x, 0, 0),
> + IMX8MM_PAD_GPIO1_IO09_SDMA2_EXT_EVENT0
> = IOMUX_PAD(0x02B4, 0x004C, 5, 0x, 0, 0),
> + IMX8MM_PAD_GPIO1_IO09_CCM_STOP
> = IOMUX_PAD(0x02B4, 0x004C, 6, 0x, 0, 0), +
> + IMX8MM_PAD_GPIO1_IO10_GPIO1_IO10
> = IOMUX_PAD(0x02B8, 0x0050, 0, 0x, 0, 0),
> + IMX8MM_PAD_GPIO1_IO10_USB1_OTG_ID
> = IOMUX_PAD(0x02B8, 0x0050, 1, 0x, 0, 0), +
> + IMX8MM_PAD_GPIO1_IO11_GPIO1_IO11
> = IOMUX_PAD(0x02BC, 0x0054, 0, 0x, 0, 0),
> + IMX8MM_PAD_GPIO1_IO11_USB2_OTG_ID
> = IOMUX_PAD(0x02BC, 0x0054, 1, 0x, 0, 0),
> + IMX8MM_PAD_GPIO1_IO11_USDHC3_VSELECT
> = IOMUX_PAD(0x02BC, 0x0054, 4, 0x, 0, 0),
> + IMX8MM_PAD_GPIO1_IO11_CCM_PMIC_READY
> = IOMUX_PAD(0x02BC, 0x0054, 5, 0x04BC, 1, 0),
> +
Re: [U-Boot] [PATCH v2 05/11] imx: tpc70: cosmetic: Replace magic numbers when setting ENET clock
Hi Peng, > > Subject: [PATCH v2 05/11] imx: tpc70: cosmetic: Replace magic > > numbers when setting ENET clock > > > > This is a cosmetic change, just to use proper define instead of > > magic numbers. > > > > Signed-off-by: Lukasz Majewski > > --- > > > > board/k+p/kp_imx6q_tpc/kp_imx6q_tpc.c | 3 ++- > > 1 file changed, 2 insertions(+), 1 deletion(-) > > > > diff --git a/board/k+p/kp_imx6q_tpc/kp_imx6q_tpc.c > > b/board/k+p/kp_imx6q_tpc/kp_imx6q_tpc.c > > index 7bdc64b1be..1dbd03efd8 100644 > > --- a/board/k+p/kp_imx6q_tpc/kp_imx6q_tpc.c > > +++ b/board/k+p/kp_imx6q_tpc/kp_imx6q_tpc.c > > @@ -118,7 +118,8 @@ static int setup_fec_clock(void) > > struct iomuxc *iomuxc_regs = (struct iomuxc > > *)IOMUXC_BASE_ADDR; > > > > /* set gpr1[21] to select anatop clock */ > > - clrsetbits_le32(&iomuxc_regs->gpr[1], 0x1 << 21, 0x1 << > > 21); > > + clrsetbits_le32(&iomuxc_regs->gpr[1], > > IOMUXC_GPR1_ENET_CLK_SEL_MASK, > > + IOMUXC_GPR1_ENET_CLK_SEL_MASK); > > Would setbits_le32 work here? Good point. It shall be possible to use setbits_le32. I will try to use it. > > Regards, > Peng. > > > > > return enable_fec_anatop_clock(0, ENET_50MHZ); } > > -- > > 2.11.0 > Best regards, Lukasz Majewski -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lu...@denx.de pgpVtGtz5WOwO.pgp Description: OpenPGP digital signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v2 07/11] imx: tpc70: dts: Add TPC70 board (imx6q based) device tree description
Hi Peng,
> > Subject: [PATCH v2 07/11] imx: tpc70: dts: Add TPC70 board (imx6q
> > based) device tree description
> >
> > This commit defines the TPC70 imx6q board with device tree
> > description.
>
> Is the imx6q-kp.dtsi usable for this board from Linux kernel?
>
The imx6q-kp.dtsi is defined in the Linux kernel [1].
However, not all features - like backlight, CAN, etc. are needed in
U-Boot. To reduce SPL footprint, as the TPC70 is the first
board (from i.MX6Q family of SoCs) which uses only DM in SPL and U-Boot
proper, only the necessary subset of [1] was added to U-Boot.
Note:
[1] -
https://elixir.bootlin.com/linux/v5.2.8/source/arch/arm/boot/dts/imx6q-kp.dtsi
> Regards,
> Peng.
>
> >
> > Signed-off-by: Lukasz Majewski
> > ---
> >
> > arch/arm/dts/imx6q-kp.dts | 219
> > ++
> > 1 file changed, 219 insertions(+)
> > create mode 100644 arch/arm/dts/imx6q-kp.dts
> >
> > diff --git a/arch/arm/dts/imx6q-kp.dts b/arch/arm/dts/imx6q-kp.dts
> > new file mode 100644 index 00..12d6db6f80
> > --- /dev/null
> > +++ b/arch/arm/dts/imx6q-kp.dts
> > @@ -0,0 +1,219 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * Copyright 2018
> > + * Lukasz Majewski, DENX Software Engineering, lu...@denx.de
> > + *
> > + * SPDX-License-Identifier: GPL-2.0+ or X11
> > + */
> > +
> > +/dts-v1/;
> > +#include
> > +#include "imx6q.dtsi"
> > +
> > +/ {
> > + model = "K+P iMX6Q";
> > + compatible = "kp,imx6-kp", "fsl,imx6";
> > +
> > + aliases {
> > + mmc0 = &usdhc2;
> > + mmc1 = &usdhc4;
> > + usb1 = &usbh1;
> > + };
> > +
> > + chosen {
> > + stdout-path = &uart1;
> > + };
> > +
> > + leds {
> > + compatible = "gpio-leds";
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&pinctrl_leds>;
> > +
> > + green {
> > + label = "green";
> > + gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>;
> > + linux,default-trigger = "gpio";
> > + default-state = "off";
> > + };
> > +
> > + red {
> > + label = "red";
> > + gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
> > + linux,default-trigger = "gpio";
> > + default-state = "off";
> > + };
> > + };
> > +
> > + memory@1000 {
> > + reg = <0x1000 0x4000>;
> > + };
> > +
> > + reg_usb_h1_vbus: regulator-usb_h1_vbus {
> > + compatible = "regulator-fixed";
> > + regulator-name = "usb_h1_vbus";
> > + regulator-min-microvolt = <500>;
> > + regulator-max-microvolt = <500>;
> > + gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>;
> > + enable-active-high;
> > + };
> > +};
> > +
> > +&fec {
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&pinctrl_enet>;
> > + phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
> > + phy-reset-duration = <10>;
> > + phy-mode = "rgmii";
> > + fsl,magic-packet;
> > + fsl,enet-loopback-clk; /* anatop reference clk via PAD
> > loopback */
> > + fsl,enet-freq = <1>; /* ENET_25MHZ = 0, ENET_50MHZ = 1 */
> > +/* ENET_100MHZ = 2, ENET_125MHZ = 3 */
> > + status = "okay";
> > +};
> > +
> > +&i2c1 {
> > + clock-frequency = <40>;
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&pinctrl_i2c1>;
> > + status = "okay";
> > +};
> > +
> > +&i2c2 {
> > + clock-frequency = <40>;
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&pinctrl_i2c2>;
> > + status = "okay";
> > +};
> > +
> > +&iomuxc {
> > + pinctrl_enet: enetgrp {
> > + fsl,pins = <
> > + MX6QDL_PAD_ENET_MDIO__ENET_MDIO
> > 0x1b0b0
> > + MX6QDL_PAD_ENET_MDC__ENET_MDC
> > 0x1b0b0
> > + MX6QDL_PAD_RGMII_TXC__RGMII_TXC
> > 0x1b0b0
> > + MX6QDL_PAD_RGMII_TD0__RGMII_TD0
> > 0x1b0b0
> > + MX6QDL_PAD_RGMII_TD1__RGMII_TD1
> > 0x1b0b0
> > + MX6QDL_PAD_RGMII_TD2__RGMII_TD2
> > 0x1b0b0
> > + MX6QDL_PAD_RGMII_TD3__RGMII_TD3
> > 0x1b0b0
> > +
> > MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
> > +
> > MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK0x1b0b0
> > + MX6QDL_PAD_RGMII_RXC__RGMII_RXC
> > 0x1b0b0
> > + MX6QDL_PAD_RGMII_RD0__RGMII_RD0
> > 0x1b0b0
> > + MX6QDL_PAD_RGMII_RD1__RGMII_RD1
> > 0x1b0b0
> > + MX6QDL_PAD_RGMII_RD2__RGMII_RD2
> > 0x1b0b0
> > + MX6QDL_PAD_RGMII_RD3__RGMII_RD3
> > 0x1b0b0
> > +
> > MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
> > + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
> > + MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25
> > 0x1b0b0
> > + >;
> > + };
> > +
> > + pinctrl_leds: gpioledsgrp {
> > + fsl,pins = <
> > + MX6QDL_PAD_EIM_D2
[U-Boot] [PATCH] arm: dts: sync dts for Allwinner H6
Sync Kernel DTS for Allwinner H6 boards.
commit Linux 5.3-rc4
Signed-off-by: Clément Péron
---
arch/arm/dts/sun50i-h6-beelink-gs1.dts | 76 ++
arch/arm/dts/sun50i-h6-pine-h64.dts| 12
arch/arm/dts/sun50i-h6.dtsi| 43 ++-
3 files changed, 128 insertions(+), 3 deletions(-)
diff --git a/arch/arm/dts/sun50i-h6-beelink-gs1.dts
b/arch/arm/dts/sun50i-h6-beelink-gs1.dts
index 54b0882bed..0dc33c90dd 100644
--- a/arch/arm/dts/sun50i-h6-beelink-gs1.dts
+++ b/arch/arm/dts/sun50i-h6-beelink-gs1.dts
@@ -14,6 +14,7 @@
compatible = "azw,beelink-gs1", "allwinner,sun50i-h6";
aliases {
+ ethernet0 = &emac;
serial0 = &uart0;
};
@@ -21,6 +22,17 @@
stdout-path = "serial0:115200n8";
};
+ connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&hdmi_out_con>;
+ };
+ };
+ };
+
leds {
compatible = "gpio-leds";
@@ -41,6 +53,40 @@
};
};
+&de {
+ status = "okay";
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&emac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&ext_rgmii_pins>;
+ phy-mode = "rgmii";
+ phy-handle = <&ext_rgmii_phy>;
+ phy-supply = <®_aldo2>;
+ status = "okay";
+};
+
+&hdmi {
+ status = "okay";
+};
+
+&hdmi_out {
+ hdmi_out_con: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+};
+
+&mdio {
+ ext_rgmii_phy: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ };
+};
+
&mmc0 {
vmmc-supply = <®_cldo1>;
cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;
@@ -57,6 +103,15 @@
status = "okay";
};
+&ohci0 {
+ status = "okay";
+};
+
+&pio {
+ vcc-pd-supply = <®_cldo1>;
+ vcc-pg-supply = <®_aldo1>;
+};
+
&r_i2c {
status = "okay";
@@ -177,8 +232,29 @@
};
};
+&r_pio {
+ /*
+* PL0 and PL1 are used for PMIC I2C
+* don't enable the pl-supply else
+* it will fail at boot
+*
+* vcc-pl-supply = <®_aldo1>;
+*/
+ vcc-pm-supply = <®_aldo1>;
+};
+
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_ph_pins>;
status = "okay";
};
+
+&usb2otg {
+ dr_mode = "host";
+ status = "okay";
+};
+
+&usb2phy {
+ usb0_vbus-supply = <®_vcc5v>;
+ status = "okay";
+};
diff --git a/arch/arm/dts/sun50i-h6-pine-h64.dts
b/arch/arm/dts/sun50i-h6-pine-h64.dts
index 4802902e12..1898345183 100644
--- a/arch/arm/dts/sun50i-h6-pine-h64.dts
+++ b/arch/arm/dts/sun50i-h6-pine-h64.dts
@@ -127,6 +127,12 @@
status = "okay";
};
+&pio {
+ vcc-pc-supply = <®_bldo2>;
+ vcc-pd-supply = <®_cldo1>;
+ vcc-pg-supply = <®_aldo1>;
+};
+
&r_i2c {
status = "okay";
@@ -243,10 +249,16 @@
pcf8563: rtc@51 {
compatible = "nxp,pcf8563";
reg = <0x51>;
+ interrupt-parent = <&r_intc>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
#clock-cells = <0>;
};
};
+&r_pio {
+ vcc-pm-supply = <®_aldo1>;
+};
+
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_ph_pins>;
diff --git a/arch/arm/dts/sun50i-h6.dtsi b/arch/arm/dts/sun50i-h6.dtsi
index e0dc4a05c1..7628a7c830 100644
--- a/arch/arm/dts/sun50i-h6.dtsi
+++ b/arch/arm/dts/sun50i-h6.dtsi
@@ -101,7 +101,7 @@
#size-cells = <1>;
ranges;
- display-engine@100 {
+ bus@100 {
compatible = "allwinner,sun50i-h6-de3",
"allwinner,sun50i-a64-de2";
reg = <0x100 0x40>;
@@ -203,11 +203,32 @@
#reset-cells = <1>;
};
+ dma: dma-controller@3002000 {
+ compatible = "allwinner,sun50i-h6-dma";
+ reg = <0x03002000 0x1000>;
+ interrupts = ;
+ clocks = <&ccu CLK_BUS_DMA>, <&ccu CLK_MBUS_DMA>;
+ clock-names = "bus", "mbus";
+ dma-channels = <16>;
+ dma-requests = <46>;
+ resets = <&ccu RST_BUS_DMA>;
+ #dma-cells = <1>;
+ };
+
sid: sid@3006000 {
compatible = "allwinner,sun50i-h6-sid";
reg = <0x03006000 0x400>;
};
+ watchdog: watchdog@30090a0 {
+ compatible = "allwinner,sun50i-h6-wdt",
+"allwinner,sun6i-a31-wdt";
+ reg = <0x030090a0 0x20>;
+
Re: [U-Boot] [RFC PATCH] rockchip, Makefile: add u-boot-tpl-with-spl.img target
> From: "Matwey V. Kornilov" > Date: Sun, 11 Aug 2019 11:06:02 +0300 > > Many Rockchip platforms require the same u-boot deploy procedure > when TPL and SPL both enabled. > > The following examples are taken from doc/README.rockchip > and board/theobroma-systems/lion_rk3368/README: > > RK3288: > > ./tools/mkimage -n rk3288 -T rksd -d ./tpl/u-boot-tpl.bin out > cat ./spl/u-boot-spl-dtb.bin >> out > sudo dd if=out of=/dev/mmcblk0 seek=64 > > RK3328: > > ./tools/mkimage -n rk3328 -T rksd -d ./tpl/u-boot-tpl.bin idbloader.img > cat ./spl/u-boot-spl.bin >> idbloader.img > sudo dd if=idbloader.img of=/dev/mmcblk0 seek=64 > > RK3368: > > ./tools/mkimage -n rk3368 -T rksd -d tpl/u-boot-tpl.bin spl-3368.img > cat spl/u-boot-spl-dtb.bin >> spl-3368.img > dd if=spl-3368.img of=/dev/sdb seek=64 > > RK3399: > > ./tools/mkimage -n rk3399 -T rksd -d ./tpl/u-boot-tpl-dtb.bin out > cat ./spl/u-boot-spl-dtb.bin >> out > sudo dd if=out of=/dev/sdc seek=64 > > Here, we introduce generic u-boot-tpl-with-spl.img target > which is the TPL image followed by the SPL binary. Nice. Only comment/question I have is whether we should go with your name (which fits well with the way we name other U-Boot components) or use idbloader.img which is the name used in some external documentation such as: http://opensource.rock-chips.com/wiki_Boot_option Cheers, Mark > Signed-off-by: Matwey V. Kornilov > --- > Makefile | 12 > 1 file changed, 12 insertions(+) > > diff --git a/Makefile b/Makefile > index 8513db94e3..4d70b6ac2e 100644 > --- a/Makefile > +++ b/Makefile > @@ -882,6 +882,10 @@ ifeq ($(CONFIG_MPC85xx)$(CONFIG_OF_SEPARATE),yy) > ALL-y += u-boot-with-dtb.bin > endif > > +ifeq ($(CONFIG_ARCH_ROCKCHIP)$(CONFIG_SPL)$(CONFIG_TPL),yyy) > +ALL-y += u-boot-tpl-with-spl.img > +endif > + > LDFLAGS_u-boot += $(LDFLAGS_FINAL) > > # Avoid 'Not enough room for program headers' error on binutils 2.28 onwards. > @@ -1293,6 +1297,14 @@ OBJCOPYFLAGS_u-boot-with-spl.bin = -I binary -O binary > \ > u-boot-with-spl.bin: $(SPL_IMAGE) $(SPL_PAYLOAD) FORCE > $(call if_changed,pad_cat) > > +ifeq ($(CONFIG_ARCH_ROCKCHIP),y) > +MKIMAGEFLAGS_u-boot-tpl.img = -n $(CONFIG_SYS_SOC) -T rksd > +tpl/u-boot-tpl.img: tpl/u-boot-tpl.bin FORCE > + $(call if_changed,mkimage) > +u-boot-tpl-with-spl.img: tpl/u-boot-tpl.img spl/u-boot-spl.bin FORCE > + $(call if_changed,cat) > +endif > + > ifeq ($(CONFIG_ARCH_LPC32XX)$(CONFIG_SPL),yy) > MKIMAGEFLAGS_lpc32xx-spl.img = -T lpc32xximage -a $(CONFIG_SPL_TEXT_BASE) > > -- > 2.16.4 > > ___ > U-Boot mailing list > U-Boot@lists.denx.de > https://lists.denx.de/listinfo/u-boot ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [RFC PATCH] rockchip, Makefile: add u-boot-tpl-with-spl.img target
> From: Simon Glass > Date: Sun, 11 Aug 2019 12:37:13 -0600 > > Hi, > > On Sun, 11 Aug 2019 at 07:51, Chris Webb wrote: > > > > Matwey V. Kornilov wrote: > > > > > Here, we introduce generic u-boot-tpl-with-spl.img target which is the > > > TPL image followed by the SPL binary. > > > > Having built U-Boot TPL + SPL images over and over again for testing on > > various rk3399 hardware, something like this would certainly be a > > convenience. It would simplify instructions to end users too. > > How about using binman for rockchip? It is designed to put various > images together. For a simple concatenation? ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [RFC PATCH] rockchip, Makefile: add u-boot-tpl-with-spl.img target
Hi, On Sun, 11 Aug 2019 at 07:51, Chris Webb wrote: > > Matwey V. Kornilov wrote: > > > Here, we introduce generic u-boot-tpl-with-spl.img target which is the > > TPL image followed by the SPL binary. > > Having built U-Boot TPL + SPL images over and over again for testing on > various rk3399 hardware, something like this would certainly be a > convenience. It would simplify instructions to end users too. How about using binman for rockchip? It is designed to put various images together. I could have a crack at it if no one else wants to. Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [RFC PATCH] rockchip, Makefile: add u-boot-tpl-with-spl.img target
Matwey V. Kornilov wrote: Here, we introduce generic u-boot-tpl-with-spl.img target which is the TPL image followed by the SPL binary. Having built U-Boot TPL + SPL images over and over again for testing on various rk3399 hardware, something like this would certainly be a convenience. It would simplify instructions to end users too. Best wishes, Chris. ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH] riscv: update fix_rela_dyn
The addend is now added for RELOC_TYPE relocs. Also, changed the loop structure so that all the R_RISCV_RELATIVE relocs are not required to be at the beginning of the list. Signed-off-by: Marcus Comstedt Cc: Rick Chen --- arch/riscv/cpu/start.S | 10 +- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S index 60ac8c621e..cd969606e4 100644 --- a/arch/riscv/cpu/start.S +++ b/arch/riscv/cpu/start.S @@ -216,7 +216,7 @@ fix_rela_dyn: /* * skip first reserved entry: address, type, addend */ - bne t1, t2, 7f + j 10f 6: LREGt5, -(REGBYTES*2)(t1) /* t5 <-- relocation info:type */ @@ -227,9 +227,7 @@ fix_rela_dyn: add t5, t5, t6 /* t5 <-- location to fix up in RAM */ add t3, t3, t6 /* t3 <-- location to fix up in RAM */ SREGt5, 0(t3) -7: - addit1, t1, (REGBYTES*3) - ble t1, t2, 6b + j 10f 8: la t4, __dyn_sym_start @@ -246,13 +244,15 @@ fix_rela_dyn: li t5, SYM_SIZE mul t0, t0, t5 add s5, t4, t0 + LREGt0, -(REGBYTES)(t1) /* t0 <-- addend */ LREGt5, REGBYTES(s5) + add t5, t5, t0 add t5, t5, t6 /* t5 <-- location to fix up in RAM */ add t3, t3, t6 /* t3 <-- location to fix up in RAM */ SREGt5, 0(t3) 10: addit1, t1, (REGBYTES*3) - ble t1, t2, 9b + ble t1, t2, 6b /* * trap update -- 2.21.0 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH] riscv: tools: Handle addend to absolute reloc in prelink-riscv
Previously the handling of R_RISCV_32 and R_RISCV_64 would simply
insert the value of the symbol and ignore any addend. However, there
exist relocs where the addend is non-zero:
80250900 R_RISCV_64efi_runtime_services+0x0068
80250910 R_RISCV_64efi_runtime_services+0x0038
80250920 R_RISCV_64efi_runtime_services+0x0018
80250930 R_RISCV_64efi_runtime_services+0x0020
80250980 R_RISCV_64efi_runtime_services+0x0048
80250990 R_RISCV_64efi_runtime_services+0x0050
802509a0 R_RISCV_64efi_runtime_services+0x0058
80250940 R_RISCV_64systab+0x0030
80250950 R_RISCV_64systab+0x0040
80250960 R_RISCV_64systab+0x0050
80250970 R_RISCV_64systab+0x0060
In these cases the addend needs to be added to the symbol value to get
the correct value for the reloc.
Signed-off-by: Marcus Comstedt
Cc: Rick Chen
---
Note: This patch applies on top of the previous endianness patches.
While the bug is orthogonal to the endianness changes and indeed
existed before them, additional byteswaps are needed to perform the
actual arithmetic, which makes the changes interdependent. Also, the
endianness fixes are already on the custodian branch, so it should be
easier to merge this way.
Currently only the EFI runtime is affected by this bug, which is
probably why it was not noticed earlier.
tools/prelink-riscv.inc | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/tools/prelink-riscv.inc b/tools/prelink-riscv.inc
index 8b40ec430a..f2b5467f5b 100644
--- a/tools/prelink-riscv.inc
+++ b/tools/prelink-riscv.inc
@@ -27,6 +27,8 @@
#define target32_to_cpu CONCAT(PRELINK_BYTEORDER, 32_to_cpu)
#define target64_to_cpu CONCAT(PRELINK_BYTEORDER, 64_to_cpu)
#define targetnn_to_cpu CONCAT3(PRELINK_BYTEORDER, PRELINK_INC_BITS, _to_cpu)
+#define cpu_to_target32 CONCAT3(cpu_to_, PRELINK_BYTEORDER, 32)
+#define cpu_to_target64 CONCAT3(cpu_to_, PRELINK_BYTEORDER, 64)
static void* get_offset_bonn (void* data, Elf_Phdr* phdrs, size_t phnum,
Elf_Addr addr)
{
@@ -92,9 +94,9 @@ static void prelink_bonn(void *data)
if (ELF_R_TYPE(targetnn_to_cpu(r->r_info)) == R_RISCV_RELATIVE)
*((uintnn_t*) buf) = r->r_addend;
else if (ELF_R_TYPE(targetnn_to_cpu(r->r_info)) == R_RISCV_32)
- *((uint32_t*) buf) =
dynsym[ELF_R_SYM(targetnn_to_cpu(r->r_info))].st_value;
+ *((uint32_t*) buf) =
cpu_to_target32(targetnn_to_cpu(dynsym[ELF_R_SYM(targetnn_to_cpu(r->r_info))].st_value)
+ targetnn_to_cpu(r->r_addend));
else if (ELF_R_TYPE(targetnn_to_cpu(r->r_info)) == R_RISCV_64)
- *((uint64_t*) buf) =
dynsym[ELF_R_SYM(targetnn_to_cpu(r->r_info))].st_value;
+ *((uint64_t*) buf) =
cpu_to_target64(targetnn_to_cpu(dynsym[ELF_R_SYM(targetnn_to_cpu(r->r_info))].st_value)
+ targetnn_to_cpu(r->r_addend));
}
}
@@ -113,6 +115,8 @@ static void prelink_bonn(void *data)
#undef target32_to_cpu
#undef target64_to_cpu
#undef targetnn_to_cpu
+#undef cpu_to_target32
+#undef cpu_to_target64
#undef CONCAT_IMPL
#undef CONCAT
--
2.21.0
___
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U-Boot@lists.denx.de
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[U-Boot] [RFC PATCH] rockchip, Makefile: add u-boot-tpl-with-spl.img target
Many Rockchip platforms require the same u-boot deploy procedure when TPL and SPL both enabled. The following examples are taken from doc/README.rockchip and board/theobroma-systems/lion_rk3368/README: RK3288: ./tools/mkimage -n rk3288 -T rksd -d ./tpl/u-boot-tpl.bin out cat ./spl/u-boot-spl-dtb.bin >> out sudo dd if=out of=/dev/mmcblk0 seek=64 RK3328: ./tools/mkimage -n rk3328 -T rksd -d ./tpl/u-boot-tpl.bin idbloader.img cat ./spl/u-boot-spl.bin >> idbloader.img sudo dd if=idbloader.img of=/dev/mmcblk0 seek=64 RK3368: ./tools/mkimage -n rk3368 -T rksd -d tpl/u-boot-tpl.bin spl-3368.img cat spl/u-boot-spl-dtb.bin >> spl-3368.img dd if=spl-3368.img of=/dev/sdb seek=64 RK3399: ./tools/mkimage -n rk3399 -T rksd -d ./tpl/u-boot-tpl-dtb.bin out cat ./spl/u-boot-spl-dtb.bin >> out sudo dd if=out of=/dev/sdc seek=64 Here, we introduce generic u-boot-tpl-with-spl.img target which is the TPL image followed by the SPL binary. Signed-off-by: Matwey V. Kornilov --- Makefile | 12 1 file changed, 12 insertions(+) diff --git a/Makefile b/Makefile index 8513db94e3..4d70b6ac2e 100644 --- a/Makefile +++ b/Makefile @@ -882,6 +882,10 @@ ifeq ($(CONFIG_MPC85xx)$(CONFIG_OF_SEPARATE),yy) ALL-y += u-boot-with-dtb.bin endif +ifeq ($(CONFIG_ARCH_ROCKCHIP)$(CONFIG_SPL)$(CONFIG_TPL),yyy) +ALL-y += u-boot-tpl-with-spl.img +endif + LDFLAGS_u-boot += $(LDFLAGS_FINAL) # Avoid 'Not enough room for program headers' error on binutils 2.28 onwards. @@ -1293,6 +1297,14 @@ OBJCOPYFLAGS_u-boot-with-spl.bin = -I binary -O binary \ u-boot-with-spl.bin: $(SPL_IMAGE) $(SPL_PAYLOAD) FORCE $(call if_changed,pad_cat) +ifeq ($(CONFIG_ARCH_ROCKCHIP),y) +MKIMAGEFLAGS_u-boot-tpl.img = -n $(CONFIG_SYS_SOC) -T rksd +tpl/u-boot-tpl.img: tpl/u-boot-tpl.bin FORCE + $(call if_changed,mkimage) +u-boot-tpl-with-spl.img: tpl/u-boot-tpl.img spl/u-boot-spl.bin FORCE + $(call if_changed,cat) +endif + ifeq ($(CONFIG_ARCH_LPC32XX)$(CONFIG_SPL),yy) MKIMAGEFLAGS_lpc32xx-spl.img = -T lpc32xximage -a $(CONFIG_SPL_TEXT_BASE) -- 2.16.4 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
