Re: [U-Boot] [PATCHv2 1/3] dm: pcie_fsl: Fix workaround of P4080 erratum A003
Hi Prabhakar, On Mon, Aug 26, 2019 at 9:00 PM Bin Meng wrote: > > Hi Prabhakar, > > On Mon, Aug 26, 2019 at 5:10 PM Prabhakar Kushwaha > wrote: > > > > Dear Bin, > > > > > -Original Message- > > > From: Bin Meng > > > Sent: Monday, August 26, 2019 2:21 PM > > > To: Z.q. Hou > > > Cc: u-boot@lists.denx.de; Prabhakar Kushwaha > > > > > > Subject: Re: [PATCHv2 1/3] dm: pcie_fsl: Fix workaround of P4080 erratum > > > A003 > > > > > > Hi Zhiqiang, > > > > > > On Mon, Aug 26, 2019 at 4:34 PM Z.q. Hou wrote: > > > > > > > > Hi Bin, > > > > > > > > Thanks a lot for your comments! > > > > > > > > > -Original Message- > > > > > From: Bin Meng > > > > > Sent: 2019年8月26日 13:59 > > > > > To: Z.q. Hou > > > > > Cc: u-boot@lists.denx.de; Prabhakar Kushwaha > > > > > > > > > > Subject: Re: [PATCHv2 1/3] dm: pcie_fsl: Fix workaround of P4080 > > > > > erratum > > > > > A003 > > > > > > > > > > Hi Zhiqiang, > > > > > > > > > > On Sun, Aug 25, 2019 at 11:42 PM Z.q. Hou > > > > > wrote: > > > > > > > > > > > > From: Hou Zhiqiang > > > > > > > > > > > > In the workaround of P4080 erratum A003, it uses the macro > > > > > > CONFIG_SYS_FSL_CORENET_SERDES_ADDR to get the SerDes block > > > > > register > > > > > > address, the CONFIG_SYS_FSL_CORENET_SERDES_ADDR is defined as > > > > > > following: > > > > > > > > > > > > (CONFIG_SYS_IMMR + > > > > > CONFIG_SYS_FSL_CORENET_SERDES_OFFSET) > > > > > > > > > > > > The problem is the macro CONFIG_SYS_FSL_CORENET_SERDES_ADDR is > > > > > defined > > > > > > on both corenet and non-corenet platforms (though it should be > > > > > > defined only on corenet platforms), but the macro > > > > > > CONFIG_SYS_FSL_CORENET_SERDES_OFFSET is only defined on corenet > > > > > > platforms, so when enabled this driver on non-corenet platforms, > > > > > > > > > > so when enabling > > > > > > > > The following series will enable DM PCIe on some PowerPC platforms > > > > including MPC8548CDS, which isn't a CORENET platform. > > > > https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fpatch > > > > > > > work.ozlabs.org%2Fproject%2Fuboot%2Flist%2F%3Fseries%3D120966dat > > > a > > > > > > > =02%7C01%7Cprabhakar.kushwaha%40nxp.com%7C927d704c60734c63fb7708 > > > d72a02 > > > > > > > 7cd0%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C63702406248371 > > > 8776 > > > > > > > mp;sdata=HLHA1%2FXmSxPPz%2FOF%2BWu30kQDD0xGsWOhxyHBEuMs8hw% > > > 3Drese > > > > rved=0 > > > > > > Is this patch series merged? Or still in the review queue. I would like > > > to have a > > > look. > > > > > > > This patch series has not been merged. I am in process of integrating it. > > > > powerpc: Enable PCIe DM drvier for some platforms: > > http://patchwork.ozlabs.org/project/uboot/list/?series=120966 > > > > If you have feedback. Please do share. > > > > I can wait to send in in rc4 or rc5. > > Thanks for letting me know the patch status. I will take a look soon. > Thanks to Zhiqiang's quick response to my review comments, now I have finished the review for patch series http://patchwork.ozlabs.org/project/uboot/list/?series=120966. Regards, Bin ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 41/47] configs: P5040DS: Enable PCIe driver
On Tue, Jul 23, 2019 at 9:31 PM Hou Zhiqiang wrote: > > Enable the DM PCIe driver in P5040DS defconfig. > > Signed-off-by: Hou Zhiqiang > --- > configs/P5040DS_NAND_defconfig | 4 > configs/P5040DS_SDCARD_defconfig | 4 > configs/P5040DS_SPIFLASH_defconfig | 4 > configs/P5040DS_defconfig | 4 > 4 files changed, 16 insertions(+) > Reviewed-by: Bin Meng ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 47/47] configs: MPC8548CDS: Enable PCIe driver
On Tue, Jul 23, 2019 at 9:26 PM Hou Zhiqiang wrote: > > Enable the DM PCIe driver in MPC8548CDS defconfig. > > Signed-off-by: Hou Zhiqiang > --- > configs/MPC8548CDS_36BIT_defconfig | 4 > configs/MPC8548CDS_defconfig| 4 > configs/MPC8548CDS_legacy_defconfig | 4 > 3 files changed, 12 insertions(+) > Reviewed-by: Bin Meng ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 38/47] configs: P4080DS: Enable PCIe driver
On Tue, Jul 23, 2019 at 9:31 PM Hou Zhiqiang wrote: > > Enable the DM PCIe driver in P4080DS defconfig. > > Signed-off-by: Hou Zhiqiang > --- > configs/P4080DS_SDCARD_defconfig | 4 > configs/P4080DS_SPIFLASH_defconfig | 4 > configs/P4080DS_defconfig | 4 > 3 files changed, 12 insertions(+) > Reviewed-by: Bin Meng ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 35/47] configs: P3041DS: Enable PCIe driver
On Tue, Jul 23, 2019 at 9:32 PM Hou Zhiqiang wrote: > > Enable the DM PCIe driver in P3041DS defconfig. > > Signed-off-by: Hou Zhiqiang > --- > configs/P3041DS_NAND_defconfig | 4 > configs/P3041DS_SDCARD_defconfig | 4 > configs/P3041DS_SPIFLASH_defconfig | 4 > configs/P3041DS_defconfig | 4 > 4 files changed, 16 insertions(+) > Reviewed-by: Bin Meng ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 34/47] powerpc: corenet_ds: Disable legacy PCIe driver when DM_PCI is enabled
On Tue, Jul 23, 2019 at 9:29 PM Hou Zhiqiang wrote: > > Disable legacy PCIe driver and unused PCIe macros when DM_PCI enabled. > > Signed-off-by: Hou Zhiqiang > --- > include/configs/corenet_ds.h | 63 > +--- > 1 file changed, 19 insertions(+), 44 deletions(-) > Reviewed-by: Bin Meng ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 31/47] configs: P2041RDB: Enable PCIe driver
On Tue, Jul 23, 2019 at 9:43 PM Hou Zhiqiang wrote: > > Enable the DM PCIe driver in P2041RDB defconfig. > > Signed-off-by: Hou Zhiqiang > --- > configs/P2041RDB_NAND_defconfig | 4 > configs/P2041RDB_SDCARD_defconfig | 4 > configs/P2041RDB_SPIFLASH_defconfig | 4 > configs/P2041RDB_defconfig | 4 > 4 files changed, 16 insertions(+) > Reviewed-by: Bin Meng ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 30/47] powerpc: P2041RDB: Disable legacy PCIe driver when DM_PCI is enabled
On Tue, Jul 23, 2019 at 9:44 PM Hou Zhiqiang wrote: > > Disable legacy PCIe driver and unused PCIe macros when DM_PCI enabled. > > Signed-off-by: Hou Zhiqiang > --- > include/configs/P2041RDB.h | 55 > +- > 1 file changed, 15 insertions(+), 40 deletions(-) > Reviewed-by: Bin Meng ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 26/47] configs: P2020RDB: Enable PCIe driver
On Tue, Jul 23, 2019 at 9:40 PM Hou Zhiqiang wrote: > > Enable the DM PCIe driver in P2020RDB defconfig. > > Signed-off-by: Hou Zhiqiang > --- > configs/P2020RDB-PC_36BIT_NAND_defconfig | 4 > configs/P2020RDB-PC_36BIT_SDCARD_defconfig | 4 > configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig | 4 > configs/P2020RDB-PC_36BIT_defconfig | 4 > configs/P2020RDB-PC_NAND_defconfig | 4 > configs/P2020RDB-PC_SDCARD_defconfig | 4 > configs/P2020RDB-PC_SPIFLASH_defconfig | 4 > configs/P2020RDB-PC_defconfig| 4 > 8 files changed, 32 insertions(+) > Reviewed-by: Bin Meng ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 25/47] P2020: dts: Added PCIe DT nodes
On Tue, Jul 23, 2019 at 9:39 PM Hou Zhiqiang wrote: > > P2020 integrated 3 PCIe controllers, which is compatible with > the PCI Express™ Base Specification, Revision 1.0a, and this > patch is to add DT node for each PCIe controller. > > Signed-off-by: Hou Zhiqiang > --- > arch/powerpc/dts/p2020-post.dtsi | 30 ++ > arch/powerpc/dts/p2020rdb-pc.dts | 17 + > arch/powerpc/dts/p2020rdb-pc_36b.dts | 17 + > 3 files changed, 64 insertions(+) > Reviewed-by: Bin Meng ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 24/47] configs: P1020RDB: Enable PCIe driver
On Tue, Jul 23, 2019 at 9:41 PM Hou Zhiqiang wrote: > > Enable the DM PCIe driver in P1020RDB defconfig. > > Signed-off-by: Hou Zhiqiang > --- > configs/P1020RDB-PC_36BIT_NAND_defconfig | 4 > configs/P1020RDB-PC_36BIT_SDCARD_defconfig | 4 > configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig | 4 > configs/P1020RDB-PC_36BIT_defconfig | 4 > configs/P1020RDB-PC_NAND_defconfig | 4 > configs/P1020RDB-PC_SDCARD_defconfig | 4 > configs/P1020RDB-PC_SPIFLASH_defconfig | 4 > configs/P1020RDB-PC_defconfig| 4 > configs/P1020RDB-PD_NAND_defconfig | 4 > configs/P1020RDB-PD_SDCARD_defconfig | 4 > configs/P1020RDB-PD_SPIFLASH_defconfig | 4 > configs/P1020RDB-PD_defconfig| 4 > 12 files changed, 48 insertions(+) > Reviewed-by: Bin Meng ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 22/47] P1020: dts: Added PCIe DT nodes
On Tue, Jul 23, 2019 at 9:33 PM Hou Zhiqiang wrote: > > P1020 integrated 2 PCIe controllers, which is compatible with > the PCI Express™ Base Specification, Revision 1.0a, and this > patch is to add DT node for each PCIe controller. > > Signed-off-by: Hou Zhiqiang > --- > arch/powerpc/dts/p1020-post.dtsi | 20 > arch/powerpc/dts/p1020rdb-pc.dts | 12 > arch/powerpc/dts/p1020rdb-pc_36b.dts | 12 > arch/powerpc/dts/p1020rdb-pd.dts | 12 > 4 files changed, 56 insertions(+) > Reviewed-by: Bin Meng ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 19/47] configs: T1042D4RDB: Enable PCIe driver
On Tue, Jul 23, 2019 at 9:28 PM Hou Zhiqiang wrote: > > Enable the DM PCIe driver in T1042D4RDB defconfig. > > Signed-off-by: Hou Zhiqiang > --- > configs/T1042D4RDB_NAND_defconfig | 4 > configs/T1042D4RDB_SDCARD_defconfig | 4 > configs/T1042D4RDB_SPIFLASH_defconfig | 4 > configs/T1042D4RDB_defconfig | 4 > 4 files changed, 16 insertions(+) > Reviewed-by: Bin Meng ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 14/47] configs: T1024RDB: Enable PCIe driver
On Tue, Jul 23, 2019 at 9:29 PM Hou Zhiqiang wrote: > > Enable the DM PCIe driver in T1024RDB defconfig. > > Signed-off-by: Hou Zhiqiang > --- > configs/T1024RDB_NAND_defconfig | 4 > configs/T1024RDB_SDCARD_defconfig | 4 > configs/T1024RDB_SPIFLASH_defconfig | 4 > configs/T1024RDB_defconfig | 4 > 4 files changed, 16 insertions(+) > Reviewed-by: Bin Meng ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 08/47] configs: T4240RDB: Enable PCIe driver
On Tue, Jul 23, 2019 at 9:34 PM Hou Zhiqiang wrote: > > Enable the DM PCIe driver in T4240RDB defconfig. > > Signed-off-by: Hou Zhiqiang > --- > configs/T4240RDB_SDCARD_defconfig | 4 > configs/T4240RDB_defconfig| 4 > 2 files changed, 8 insertions(+) > Reviewed-by: Bin Meng ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 03/47] configs: T2080RDB: Enable PCIe driver
Hi Zhiqiang, On Tue, Aug 27, 2019 at 11:09 AM Z.q. Hou wrote: > > Hi Bin, > > > -Original Message- > > From: Bin Meng > > Sent: 2019年8月27日 10:51 > > To: Z.q. Hou > > Cc: U-Boot Mailing List ; Prabhakar Kushwaha > > ; Wolfgang Denk ; Priyanka > > Jain ; Shengzhou Liu > > Subject: Re: [U-Boot] [PATCH 03/47] configs: T2080RDB: Enable PCIe driver > > > > Hi Zhiqiang, > > > > On Tue, Aug 27, 2019 at 10:05 AM Z.q. Hou wrote: > > > > > > Hi Bin, > > > > > > Thanks a lot for your comments! > > > > > > > -Original Message- > > > > From: Bin Meng > > > > Sent: 2019年8月26日 22:48 > > > > To: Z.q. Hou > > > > Cc: U-Boot Mailing List ; Prabhakar Kushwaha > > > > ; Wolfgang Denk ; > > Priyanka > > > > Jain ; Shengzhou Liu > > > > > > Subject: Re: [U-Boot] [PATCH 03/47] configs: T2080RDB: Enable PCIe > > > > driver > > > > > > > > Hi Zhiqiang, > > > > > > > > On Tue, Jul 23, 2019 at 9:24 PM Hou Zhiqiang > > > > wrote: > > > > > > > > > > Enable the DM PCIe driver in T2080RDB defconfig. > > > > > > > > > > Signed-off-by: Hou Zhiqiang > > > > > --- > > > > > configs/T2080RDB_NAND_defconfig | 4 > > > > > configs/T2080RDB_SDCARD_defconfig | 4 > > > > > configs/T2080RDB_SPIFLASH_defconfig | 4 > > > > > configs/T2080RDB_defconfig | 4 > > > > > 4 files changed, 16 insertions(+) > > > > > > > > > > diff --git a/configs/T2080RDB_NAND_defconfig > > > > > b/configs/T2080RDB_NAND_defconfig index 7eb7058..30ec72b > > 100644 > > > > > --- a/configs/T2080RDB_NAND_defconfig > > > > > +++ b/configs/T2080RDB_NAND_defconfig > > > > > @@ -57,6 +57,10 @@ CONFIG_PHYLIB=y > > CONFIG_PHY_AQUANTIA=y > > > > > CONFIG_E1000=y CONFIG_MII=y > > > > > +CONFIG_DM=y > > > > > +CONFIG_DM_PCI=y > > > > > +CONFIG_DM_PCI_COMPAT=y > > > > > > > > Why do we need this option? I vaguely remember I commented in as > > > > similar patch for some other board (maybe layerscape arm?) > > > > > > We discussed this during adding PCIe DM driver on T2080QDS, so it's > > > the same reason. > > > > I dug into the mailing list archive, and I see: > > https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.d > > enx.de%2Fpipermail%2Fu-boot%2F2019-May%2F370756.htmldata=0 > > 2%7C01%7Czhiqiang.hou%40nxp.com%7C7e2ca21c87dd4d497e4008d72a99 > > 626b%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C63702471058 > > 1230533sdata=Ams8RKheHQcU9pgTAuTugXcLCrzbRFk5xOm6ubu84R > > Y%3Dreserved=0 > > > > In that thread, you wrote: > > > > "I will submit a patch to remove the DM_PCI_COMPAT when all driver has > > been converted." > > > > So I believe you guys have not converted all PowerPC drivers to DM, hence > > it's still left there? > > Yes, I will remove it when DM_ETH is added, otherwise there will be build > errors. > Great!, so, Reviewed-by: Bin Meng Regards, Bin ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH] rockchip: rk3399: dts: add boot order for rockpro64
The rk3399 rockpro64 board can boot from emmc and sdcard.
TODO: add spiflash as boot device.
Signed-off-by: Kever Yang
---
arch/arm/dts/rk3399-rockpro64-u-boot.dtsi | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi
b/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi
index f7f26d584f..a073ea25f5 100644
--- a/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi
+++ b/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi
@@ -5,6 +5,11 @@
#include "rk3399-u-boot.dtsi"
#include "rk3399-sdram-lpddr4-100.dtsi"
+/ {
+ chosen {
+ u-boot,spl-boot-order = "same-as-spl", ,
+ };
+};
_log {
regulator-init-microvolt = <95>;
--
2.17.1
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[U-Boot] [PATCHv3] armv8: fsl-layerscape: Fix a typo of Layerscape PCIe config entry
From: Hou Zhiqiang The correct config entry is CONFIG_PCIE_LAYERSCAPE and this typo results in skipping the fixup of Linux PCIe DT nodes. Also enable the fixup when Layerscape Gen4 controller driver is enabled. Fixes: 4da0e52c9dc0 (armv8: fsl-layerscape: fix config dependency for layerscape pci code) Signed-off-by: Hou Zhiqiang Reviewed-by: Bin Meng --- V3: - Fix grammar errors in change log. V2: - Enable this fixup for Layerscape Gen4 controller driver. arch/arm/cpu/armv8/fsl-layerscape/fdt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c index fabe0f0359..25b7afe064 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c @@ -435,7 +435,7 @@ void ft_cpu_setup(void *blob, bd_t *bd) do_fixup_by_path_u32(blob, "/sysclk", "clock-frequency", CONFIG_SYS_CLK_FREQ, 1); -#ifdef CONFIG_PCI_LAYERSCAPE +#if defined(CONFIG_PCIE_LAYERSCAPE) || defined(CONFIG_PCIE_LAYERSCAPE_GEN4) ft_pci_setup(blob, bd); #endif -- 2.17.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 22/22] imx: Add i.MX8MM EVK board support.
> -Original Message-
> From: Peng Fan
> Sent: 2019年8月27日 9:10
> To: Schrempf Frieder ; lu...@denx.de;
> sba...@denx.de; feste...@gmail.com
> Cc: dl-uboot-imx ; u-boot@lists.denx.de
> Subject: RE: [PATCH 22/22] imx: Add i.MX8MM EVK board support.
>
> > Subject: Re: [PATCH 22/22] imx: Add i.MX8MM EVK board support.
> >
> > On 15.08.19 02:57, Peng Fan wrote:
> > >> Subject: Re: [PATCH 22/22] imx: Add i.MX8MM EVK board support.
> > >>
> > >> On 09.08.19 06:15, Peng Fan wrote:
> > >>> Add board and SoC dts
> > >>> Add ddr training code
> > >>> support SD/MMC/GPIO/PINCTRL/UART
> > >>>
> > >>> Signed-off-by: Peng Fan
> > >>> ---
> > >>>arch/arm/dts/Makefile |3 +-
> > >
> > > []
> > >>> +}
> > >>> +#endif
> > >>> +
> > >>> +int dram_init(void)
> > >>> +{
> > >>> + /* rom_pointer[1] contains the size of TEE occupies */
> > >>> + if (rom_pointer[1])
> > >>> + gd->ram_size = PHYS_SDRAM_SIZE - rom_pointer[1];
> > >>> + else
> > >>
> > >> The above case should be guarded with "#ifdef CONFIG_OPTEE",
> > >> because if OPTEE is not used, rom_pointer[1] does not always seem to
> be zero.
> > >
> > > If OPTEE is not used, ATF will leave those registers as zero, so it will
> > > be
> zero.
> >
> > It wasn't working for me, but I can try again and check my ATF if it really
> does.
> > Maybe it would still be better to guard this check so we don't depend
> > on the ATF behavior.
>
> ok, I'll drop that.
>
> >
> > >
> > >>
> > >>> + gd->ram_size = PHYS_SDRAM_SIZE;
> > >>> +
> > >>> + return 0;
> > >>> +}
> > >>> +
> > >
> > > [...]
> > >>> +CONFIG_SPL_LOAD_FIT=y
> > >>>
> > +CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh"
> > >>
> > >> For my custom i.MX8MM board I also use mkimage_fit_atf.sh, but I
> > >> have done three modifications and I'm wondering how you are using
> > >> the unmodified version.
> > >>
> > >> 1. It sets ATF_LOAD_ADDR="0x91", but in imx-atf the BL31_BASE
> > >> for i.MX8MM is set to 0x92. How to handle this mismatch for
> > >> i.MX8M and i.MX8MM?
> > >
> > > I have added README in patchset, need export
> ATF_LOAD_ADDR=0x92
> >
> > This is not very convenient. It would be better if there is a default
> > value for each of i.MX8M and i.MX8MM.
>
> Ah, let me try.
The script only accepts dtb as input args, I do not find a good way to
runtime detect SoC types. Will leave this in future.
Thanks,
Peng.
>
> >
> > >
> > >>
> > >> 2. For the 'images' section of the its file, I added 'os = "u-boot";'
> > >> to the 'uboot@1' section and "os = 'arm-trusted-firmware";' to the
> 'atf@1'
> > >> section. Without this SPL does not detect the binaries from the FIT
> > >> image correctly.
> > >
> > > Thanks for the fix.
> >
> > Will you add a patch to fix this to your set?
>
> Ok.
>
> >
> > >
> > >>
> > >> 3. In the 'config' section of the its file, I swapped the atf and
> > >> uboot entries, so the atf binary is loaded as "firmware" and the
> > >> u-boot
> > binary as "loadable".
> > >> Together with the change above (2) this leads to SPL code using the
> > >> correct boot path as inteded by the code.
> > >
> > > Thanks for the fix.
> >
> > Ditto?
>
> Ok.
>
> Thanks,
> Peng.
> >
> > >
> > >>
> > >>> +CONFIG_OF_BOARD_SETUP=y
> > >>> +CONFIG_OF_SYSTEM_SETUP=y
> > >>>
> > >>
> >
> +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m
> > >> /imximage-8mm-lpddr4.cfg"
> > >>> +CONFIG_DEFAULT_FDT_FILE="fsl-imx8mm-evk.dtb"
> > >>> +CONFIG_BOARD_LATE_INIT=y
> > >>> +CONFIG_BOARD_EARLY_INIT_F=y
> > >>> +CONFIG_SPL_TEXT_BASE=0x7E1000
> > >>> +CONFIG_SPL_BOARD_INIT=y
> > >>> +CONFIG_SPL_SEPARATE_BSS=y
> > >>> +CONFIG_SPL_I2C_SUPPORT=y
> > >>> +CONFIG_HUSH_PARSER=y
> > >>> +CONFIG_SYS_PROMPT="u-boot=> "
> > >>> +# CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV
> is not
> > >>> +set # CONFIG_CMD_CRC32 is not set CONFIG_CMD_CLK=y
> > >>> +CONFIG_CMD_FUSE=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y
> > >>> +CONFIG_CMD_MMC=y CONFIG_CMD_CACHE=y
> CONFIG_CMD_REGULATOR=y
> > >>> +CONFIG_CMD_EXT2=y CONFIG_CMD_EXT4=y
> CONFIG_CMD_EXT4_WRITE=y
> > >>> +CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y
> CONFIG_SPL_OF_CONTROL=y
> > >>> +CONFIG_DEFAULT_DEVICE_TREE="imx8mm-evk"
> > >>> +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
> > >>> +CONFIG_SPL_DM=y
> > >>> +CONFIG_SPL_CLK_COMPOSITE_CCF=y
> > >>> +CONFIG_CLK_COMPOSITE_CCF=y
> > >>> +CONFIG_SPL_CLK_IMX8MM=y
> > >>> +CONFIG_CLK_IMX8MM=y
> > >>> +CONFIG_DM_GPIO=y
> > >>> +CONFIG_MXC_GPIO=y
> > >>> +CONFIG_DM_I2C=y
> > >>> +CONFIG_SYS_I2C_MXC=y
> > >>> +CONFIG_SYS_I2C_MXC_I2C1=y
> > >>> +CONFIG_SYS_I2C_MXC_I2C2=y
> > >>> +CONFIG_SYS_I2C_MXC_I2C3=y
> > >>> +CONFIG_DM_MMC=y
> > >>> +CONFIG_SUPPORT_EMMC_BOOT=y
> > >>> +CONFIG_FSL_ESDHC_IMX=y
> > >>> +CONFIG_PHYLIB=y
> > >>> +CONFIG_DM_ETH=y
> > >>> +CONFIG_PINCTRL=y
> > >>> +CONFIG_SPL_PINCTRL=y
> > >>> +CONFIG_PINCTRL_IMX8M=y
> > >>> +CONFIG_DM_REGULATOR=y
> > >>> +CONFIG_DM_REGULATOR_FIXED=y
> > >>>
Re: [U-Boot] [PATCH 22/47] P1020: dts: Added PCIe DT nodes
Hi Bin,
> -Original Message-
> From: Bin Meng
> Sent: 2019年8月27日 10:59
> To: Z.q. Hou
> Cc: U-Boot Mailing List ; Prabhakar Kushwaha
> ; Wolfgang Denk ; Priyanka
> Jain ; Shengzhou Liu
> Subject: Re: [U-Boot] [PATCH 22/47] P1020: dts: Added PCIe DT nodes
>
> Hi Zhiqiang,
>
> On Tue, Aug 27, 2019 at 10:46 AM Z.q. Hou wrote:
> >
> > Hi Bin,
> >
> > Thanks a lot for your comments!
> >
> > > -Original Message-
> > > From: Bin Meng
> > > Sent: 2019年8月26日 22:50
> > > To: Z.q. Hou
> > > Cc: U-Boot Mailing List ; Prabhakar Kushwaha
> > > ; Wolfgang Denk ;
> Priyanka
> > > Jain ; Shengzhou Liu
>
> > > Subject: Re: [U-Boot] [PATCH 22/47] P1020: dts: Added PCIe DT nodes
> > >
> > > Hi Zhiqiang,
> > >
> > > On Tue, Jul 23, 2019 at 9:33 PM Hou Zhiqiang
> > > wrote:
> > > >
> > > > P1020 integrated 2 PCIe controllers, which is compatible with the
> > > > PCI Express™ Base Specification, Revision 1.0a, and this patch is
> > > > to add DT node for each PCIe controller.
> > > >
> > > > Signed-off-by: Hou Zhiqiang
> > > > ---
> > > > arch/powerpc/dts/p1020-post.dtsi | 20
>
> > > > arch/powerpc/dts/p1020rdb-pc.dts | 12
> > > > arch/powerpc/dts/p1020rdb-pc_36b.dts | 12
> > > > arch/powerpc/dts/p1020rdb-pd.dts | 12
> > > > 4 files changed, 56 insertions(+)
> > > >
> > > > diff --git a/arch/powerpc/dts/p1020-post.dtsi
> > > > b/arch/powerpc/dts/p1020-post.dtsi
> > > > index e1a4f50..1e5e678 100644
> > > > --- a/arch/powerpc/dts/p1020-post.dtsi
> > > > +++ b/arch/powerpc/dts/p1020-post.dtsi
> > > > @@ -25,3 +25,23 @@
> > > > last-interrupt-source = <255>;
> > > > };
> > > > };
> > > > +
> > > > +/* PCIe controller base address 0x9000 */
> > > > + {
> > > > + compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq";
> > > > + law_trgt_if = <1>;
> > > > + #address-cells = <3>;
> > > > + #size-cells = <2>;
> > > > + device_type = "pci";
> > > > + bus-range = <0x0 0xff>;
> > > > +};
> > > > +
> > > > +/* PCIe controller base address 0xa000 */
> > > > + {
> > > > + compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq";
> > > > + law_trgt_if = <2>;
> > > > + #address-cells = <3>;
> > > > + #size-cells = <2>;
> > > > + device_type = "pci";
> > > > + bus-range = <0x0 0xff>;
> > > > +};
> > > > diff --git a/arch/powerpc/dts/p1020rdb-pc.dts
> > > > b/arch/powerpc/dts/p1020rdb-pc.dts
> > > > index fd68b8b..7ebaa61 100644
> > > > --- a/arch/powerpc/dts/p1020rdb-pc.dts
> > > > +++ b/arch/powerpc/dts/p1020rdb-pc.dts
> > > > @@ -18,6 +18,18 @@
> > > > soc: soc@ffe0 {
> > > > ranges = <0x0 0x0 0xffe0 0x10>;
> > > > };
> > > > +
> > > > + pci1: pcie@ffe09000 {
> > >
> > > Why this is named as pci1?
> >
> > The P1020 reference manual said the first controller registers offset
> > begin at 0xa000 and the second begin at 0x9000.
> >
> > >
> > > > + reg = <0x0 0xffe09000 0x0 0x1000>; /*
> registers
> > > */
> > >
> > > Shouldn't the property be put in the dtsi file?
> >
> > The registers starting addresses are different between 32bit and 36bit dts.
> >
>
> I see. But looks they are inconsistent. Some of the platforms put the reg in
> the dtsi, and some do not. I believe it's because some platforms force to
> select CONFIG_PHYS_64BIT hence no need to have two version of in
> DT?
Yes, you're right.
Thanks,
Zhiqiang
>
> Regards,
> Bin
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Re: [U-Boot] [PATCH 25/47] P2020: dts: Added PCIe DT nodes
Hi Bin,
> -Original Message-
> From: Bin Meng
> Sent: 2019年8月27日 10:56
> To: Z.q. Hou
> Cc: U-Boot Mailing List ; Prabhakar Kushwaha
> ; Wolfgang Denk ; Priyanka
> Jain ; Shengzhou Liu
> Subject: Re: [U-Boot] [PATCH 25/47] P2020: dts: Added PCIe DT nodes
>
> Hi Zhiqiang,
>
> On Tue, Aug 27, 2019 at 10:52 AM Z.q. Hou wrote:
> >
> > Hi Bin,
> >
> > Thanks a lot for your comments!
> >
> > > -Original Message-
> > > From: Bin Meng
> > > Sent: 2019年8月26日 22:50
> > > To: Z.q. Hou
> > > Cc: U-Boot Mailing List ; Prabhakar Kushwaha
> > > ; Wolfgang Denk ;
> Priyanka
> > > Jain ; Shengzhou Liu
>
> > > Subject: Re: [U-Boot] [PATCH 25/47] P2020: dts: Added PCIe DT nodes
> > >
> > > On Tue, Jul 23, 2019 at 9:39 PM Hou Zhiqiang
> > > wrote:
> > > >
> > > > P2020 integrated 3 PCIe controllers, which is compatible with the
> > > > PCI Express™ Base Specification, Revision 1.0a, and this patch is
> > > > to add DT node for each PCIe controller.
> > > >
> > > > Signed-off-by: Hou Zhiqiang
> > > > ---
> > > > arch/powerpc/dts/p2020-post.dtsi | 30
> > > ++
> > > > arch/powerpc/dts/p2020rdb-pc.dts | 17 +
> > > > arch/powerpc/dts/p2020rdb-pc_36b.dts | 17 +
> > > > 3 files changed, 64 insertions(+)
> > > >
> > > > diff --git a/arch/powerpc/dts/p2020-post.dtsi
> > > > b/arch/powerpc/dts/p2020-post.dtsi
> > > > index f20d1fa..f696f35 100644
> > > > --- a/arch/powerpc/dts/p2020-post.dtsi
> > > > +++ b/arch/powerpc/dts/p2020-post.dtsi
> > > > @@ -25,3 +25,33 @@
> > > > last-interrupt-source = <255>;
> > > > };
> > > > };
> > > > +
> > > > +/* PCIe controller base address 0x8000 */
> > > > + {
> > >
> > > pci0?
> >
> > Describe the controller index and starting address according to P2020 RM.
>
> OK, so will this weird index number (2, 1, 0) break the index calculation log
> in
> the following patch?
No, the code handled this.
Thanks,
Zhiqiang
> https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fpatch
> work.ozlabs.org%2Fpatch%2F1152811%2Fdata=02%7C01%7Czhiqian
> g.hou%40nxp.com%7Cb20f64bf19f445e50ce108d72a9a160a%7C686ea1d3b
> c2b4c6fa92cd99c5c301635%7C0%7C0%7C637024713598549064sdat
> a=WG5PXoeY0zriaxdITqzOJ%2BnT65uzrQ%2FUtwi4JuykXnA%3Dreser
> ved=0
>
> Regards,
> Bin
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Re: [U-Boot] [PATCH 03/47] configs: T2080RDB: Enable PCIe driver
Hi Bin, > -Original Message- > From: Bin Meng > Sent: 2019年8月27日 10:51 > To: Z.q. Hou > Cc: U-Boot Mailing List ; Prabhakar Kushwaha > ; Wolfgang Denk ; Priyanka > Jain ; Shengzhou Liu > Subject: Re: [U-Boot] [PATCH 03/47] configs: T2080RDB: Enable PCIe driver > > Hi Zhiqiang, > > On Tue, Aug 27, 2019 at 10:05 AM Z.q. Hou wrote: > > > > Hi Bin, > > > > Thanks a lot for your comments! > > > > > -Original Message- > > > From: Bin Meng > > > Sent: 2019年8月26日 22:48 > > > To: Z.q. Hou > > > Cc: U-Boot Mailing List ; Prabhakar Kushwaha > > > ; Wolfgang Denk ; > Priyanka > > > Jain ; Shengzhou Liu > > > > Subject: Re: [U-Boot] [PATCH 03/47] configs: T2080RDB: Enable PCIe > > > driver > > > > > > Hi Zhiqiang, > > > > > > On Tue, Jul 23, 2019 at 9:24 PM Hou Zhiqiang > > > wrote: > > > > > > > > Enable the DM PCIe driver in T2080RDB defconfig. > > > > > > > > Signed-off-by: Hou Zhiqiang > > > > --- > > > > configs/T2080RDB_NAND_defconfig | 4 > > > > configs/T2080RDB_SDCARD_defconfig | 4 > > > > configs/T2080RDB_SPIFLASH_defconfig | 4 > > > > configs/T2080RDB_defconfig | 4 > > > > 4 files changed, 16 insertions(+) > > > > > > > > diff --git a/configs/T2080RDB_NAND_defconfig > > > > b/configs/T2080RDB_NAND_defconfig index 7eb7058..30ec72b > 100644 > > > > --- a/configs/T2080RDB_NAND_defconfig > > > > +++ b/configs/T2080RDB_NAND_defconfig > > > > @@ -57,6 +57,10 @@ CONFIG_PHYLIB=y > CONFIG_PHY_AQUANTIA=y > > > > CONFIG_E1000=y CONFIG_MII=y > > > > +CONFIG_DM=y > > > > +CONFIG_DM_PCI=y > > > > +CONFIG_DM_PCI_COMPAT=y > > > > > > Why do we need this option? I vaguely remember I commented in as > > > similar patch for some other board (maybe layerscape arm?) > > > > We discussed this during adding PCIe DM driver on T2080QDS, so it's > > the same reason. > > I dug into the mailing list archive, and I see: > https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.d > enx.de%2Fpipermail%2Fu-boot%2F2019-May%2F370756.htmldata=0 > 2%7C01%7Czhiqiang.hou%40nxp.com%7C7e2ca21c87dd4d497e4008d72a99 > 626b%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C63702471058 > 1230533sdata=Ams8RKheHQcU9pgTAuTugXcLCrzbRFk5xOm6ubu84R > Y%3Dreserved=0 > > In that thread, you wrote: > > "I will submit a patch to remove the DM_PCI_COMPAT when all driver has > been converted." > > So I believe you guys have not converted all PowerPC drivers to DM, hence > it's still left there? Yes, I will remove it when DM_ETH is added, otherwise there will be build errors. Thanks, Zhiqiang > > Regards, > Bin ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] blk: Invalidate block cache when switching hwpart
On Mon, 2019-08-26 at 14:43 +0200, Felix Brack wrote:
> Hello Weijie,
>
> On 26.08.19 10:19, Weijie Gao wrote:
> > On Thu, 2019-08-22 at 15:58 +0200, Felix Brack wrote:
> >> On 11.07.19 09:10, Weijie Gao wrote:
> >>
> >>> Some storage devices have multiple hw partitions and both address from
> >>> zero, for example eMMC.
> >>> However currently block cache invalidation only applies to block
> >>> write/erase.
> >>> This can cause a problem that data of current hw partition is cached
> >>> before switching to another hw partition. And the following read
> >>> operation of the latter hw partition will get wrong data when reading
> >>> from the addresses that have been cached previously.
> >>>
> >>> To solve this problem, invalidate block cache after a successful
> >>> select_hwpart operation.
> >>>
> >>> Signed-off-by: Weijie Gao
> >>> ---
> >> This patch breaks correct operation of PDU001 board.
> >>
> >>> drivers/block/blk-uclass.c | 14 --
> >>> 1 file changed, 12 insertions(+), 2 deletions(-)
> >>>
> >>> diff --git a/drivers/block/blk-uclass.c b/drivers/block/blk-uclass.c
> >>> index baaf431e5e0..c23b6682a6c 100644
> >>> --- a/drivers/block/blk-uclass.c
> >>> +++ b/drivers/block/blk-uclass.c
> >>> @@ -208,7 +208,11 @@ int blk_select_hwpart_devnum(enum if_type if_type,
> >>> int devnum, int hwpart)
> >>> if (ret)
> >>> return ret;
> >>>
> >>> - return blk_select_hwpart(dev, hwpart);
> >>> + ret = blk_select_hwpart(dev, hwpart);
> >>> + if (!ret)
> >>> + blkcache_invalidate(if_type, devnum);
> >>> +
> >>> + return ret;
> >>> }
> >>>
> >>> int blk_list_part(enum if_type if_type)
> >>> @@ -348,7 +352,13 @@ int blk_select_hwpart(struct udevice *dev, int
> >>> hwpart)
> >>>
> >>> int blk_dselect_hwpart(struct blk_desc *desc, int hwpart)
> >>> {
> >>> - return blk_select_hwpart(desc->bdev, hwpart);
> >>> + int ret;
> >>> +
> >>> + ret = blk_select_hwpart(desc->bdev, hwpart);
> >>> + if (!ret)
> >>> + blkcache_invalidate(desc->if_type, desc->devnum);
> >>> +
> >> Commenting the invalidation of the block cache on this line results in
> >> proper working of the board.
> >>
> >>> + return ret;
> >>> }
> >>>
> >>> int blk_first_device(int if_type, struct udevice **devp)
> >>>
> >> With the patch active, files from the boot FAT partition of the SD-card
> >> (mmc device 1) do not load anymore, hence booting fails.
> >> Using the eMMC (mmc device 0) instead works fine, files can bee loaded
> >> and the board boots.
> >>
> >> To isolate the problem I have modified the configuration to only load a
> >> 10k test file (test.bin) instead of loading the DTB and zImage files
> >> followed by booting LINUX. Furthermore I have enabled debugging for some
> >> parts of the code.
> >>
> >> When I boot from the SD-card (which fails) I get the following logged:
> >> ===
> >> CPU : AM335X-GP rev 1.0
> >> ===
> >>
> >> This time the file test.bin gets loaded correctly.
> >>
> >> To be honest I don't really see why things are going wrong. It looks
> >> like the block cache gets filled but then again invalidated before it's
> >> data is used. I also feel that this problem is related to the SD-card
> >> not being the first (number 0) but the second device (number 1).
> >> Can anybody shed some light on this and give me a hint?
> >>
> >> many thanks, Felix
> >
> > Hi Felix,
> >
> > I've found the root cause.
> >
> Many thanks for looking into this!
>
> > There is a bug in the FAT driver. In function file_fat_read_at(),
> > malloc_cache_aligned() allocates memory for the itr. The itr is a
> > pointer to struct fat_itr. fat_itr has a member block[MAX_CLUSTSIZE]
> > used for storing blocks read from MMC.
> >
> > The FAT driver resolves the file table and stores the required dir entry
> > in the member block. Then the pointer of the dir entry is passed to
> > get_contents() to get the contents of the file.
> >
> > However the itr is freed BEFORE the call to get_contents(). This means
> > the contents dir entry points to is no longer valid. And it results to
> > your situation.
> >
> Indeed this is the root of all trouble. The freeing of itr of course
> also invalidates the assignment made earlier:
>
> dir_entry *dentptr = itr->dent;
>
> As dentptr is used in the call to get_contents() the evil takes its
> course...
>
> Again many thanks for analyzing and explaining this as detailed as you did.
>
> > But this only happens when CONFIG_BLOCK_CACHE=y and the patch applied.
> > I've also found its cause.
> >
> > The MMC driver calls blk_dselect_hwpart() unconditionally in
> > mmc_bread(). This causes block cache being invalidated and refilled many
> > times during the FAT load operation.
> >
> Yes I have noticed this frequent invalidations of the cache due to calls
> to blk_dselect_hwpart(). Some optimization, if possible, would be great.
>
> > The frequent block cache invalidation and refilling finally results in
> > frequent memory allocation and freeing. There is a
Re: [U-Boot] [PATCH 34/47] powerpc: corenet_ds: Disable legacy PCIe driver when DM_PCI is enabled
Hi Bin, Thanks a lot for your comments! > -Original Message- > From: Bin Meng > Sent: 2019年8月26日 22:50 > To: Z.q. Hou > Cc: U-Boot Mailing List ; Prabhakar Kushwaha > ; Wolfgang Denk ; Priyanka > Jain ; Shengzhou Liu > Subject: Re: [U-Boot] [PATCH 34/47] powerpc: corenet_ds: Disable legacy > PCIe driver when DM_PCI is enabled > > On Tue, Jul 23, 2019 at 9:29 PM Hou Zhiqiang > wrote: > > > > Disable legacy PCIe driver and unused PCIe macros when DM_PCI enabled. > > > > Signed-off-by: Hou Zhiqiang > > --- > > include/configs/corenet_ds.h | 63 > > +--- > > 1 file changed, 19 insertions(+), 44 deletions(-) > > > > diff --git a/include/configs/corenet_ds.h > > b/include/configs/corenet_ds.h index f974291..07844c1 100644 > > --- a/include/configs/corenet_ds.h > > +++ b/include/configs/corenet_ds.h > > @@ -54,7 +54,6 @@ > > #define CONFIG_SYS_NUM_CPC > CONFIG_SYS_NUM_DDR_CTLRS > > #define CONFIG_PCIE1 /* PCIE controller 1 */ > > #define CONFIG_PCIE2 /* PCIE controller 2 */ > > -#define CONFIG_FSL_PCI_INIT/* Use common FSL init > code */ > > #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI > resources */ > > > > #define CONFIG_ENV_OVERWRITE > > @@ -362,68 +361,25 @@ > > > > /* controller 1, direct to uli, tgtid 3, Base address 2 */ > > #define CONFIG_SYS_PCIE1_MEM_VIRT 0x8000 > > -#ifdef CONFIG_PHYS_64BIT > > -#define CONFIG_SYS_PCIE1_MEM_BUS 0xe000 > > #define CONFIG_SYS_PCIE1_MEM_PHYS 0xcull > > -#else > > -#define CONFIG_SYS_PCIE1_MEM_BUS 0x8000 > > -#define CONFIG_SYS_PCIE1_MEM_PHYS 0x8000 > > -#endif > > -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x2000 /* > 512M */ > > #define CONFIG_SYS_PCIE1_IO_VIRT 0xf800 > > -#define CONFIG_SYS_PCIE1_IO_BUS0x > > -#ifdef CONFIG_PHYS_64BIT > > #define CONFIG_SYS_PCIE1_IO_PHYS 0xff800ull > > -#else > > -#define CONFIG_SYS_PCIE1_IO_PHYS 0xf800 > > -#endif > > -#define CONFIG_SYS_PCIE1_IO_SIZE 0x0001 /* 64k */ > > > > /* controller 2, Slot 2, tgtid 2, Base address 201000 */ > > #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa000 > > -#ifdef CONFIG_PHYS_64BIT > > -#define CONFIG_SYS_PCIE2_MEM_BUS 0xe000 > > #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc2000ull > > -#else > > -#define CONFIG_SYS_PCIE2_MEM_BUS 0xa000 > > -#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa000 > > -#endif > > -#define CONFIG_SYS_PCIE2_MEM_SIZE 0x2000 /* > 512M */ > > #define CONFIG_SYS_PCIE2_IO_VIRT 0xf801 > > -#define CONFIG_SYS_PCIE2_IO_BUS0x > > -#ifdef CONFIG_PHYS_64BIT > > #define CONFIG_SYS_PCIE2_IO_PHYS 0xff801ull > > -#else > > -#define CONFIG_SYS_PCIE2_IO_PHYS 0xf801 > > -#endif > > -#define CONFIG_SYS_PCIE2_IO_SIZE 0x0001 /* 64k */ > > > > /* controller 3, Slot 1, tgtid 1, Base address 202000 */ > > #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc000 > > -#ifdef CONFIG_PHYS_64BIT > > -#define CONFIG_SYS_PCIE3_MEM_BUS 0xe000 > > #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc4000ull > > -#else > > -#define CONFIG_SYS_PCIE3_MEM_BUS 0xc000 > > -#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc000 > > -#endif > > -#define CONFIG_SYS_PCIE3_MEM_SIZE 0x2000 /* > 512M */ > > #define CONFIG_SYS_PCIE3_IO_VIRT 0xf802 > > -#define CONFIG_SYS_PCIE3_IO_BUS0x > > -#ifdef CONFIG_PHYS_64BIT > > #define CONFIG_SYS_PCIE3_IO_PHYS 0xff802ull > > -#else > > -#define CONFIG_SYS_PCIE3_IO_PHYS 0xf802 > > -#endif > > -#define CONFIG_SYS_PCIE3_IO_SIZE 0x0001 /* 64k */ > > > > /* controller 4, Base address 203000 */ > > -#define CONFIG_SYS_PCIE4_MEM_BUS 0xe000 > > #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc6000ull > > -#define CONFIG_SYS_PCIE4_MEM_SIZE 0x2000 /* > 512M */ > > -#define CONFIG_SYS_PCIE4_IO_BUS0x > > #define CONFIG_SYS_PCIE4_IO_PHYS 0xff803ull > > -#define CONFIG_SYS_PCIE4_IO_SIZE 0x0001 /* 64k */ > > > > /* Qman/Bman */ > > #define CONFIG_SYS_BMAN_NUM_PORTALS10 > > @@ -505,7 +461,26 @@ > > #endif > > > > #ifdef CONFIG_PCI > > +#if !defined(CONFIG_DM_PCI) > > +#define CONFIG_FSL_PCI_INIT/* Use common FSL init code */ > > #define CONFIG_PCI_INDIRECT_BRIDGE > > +#define CONFIG_SYS_PCIE1_MEM_BUS 0xe000 > > CONFIG_PHYS_64BIT? All CORENET DS boards selected PHYS_64BIT, so removed these unused macros. Thanks, Zhiqiang > > > +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x2000 /* > 512M */ > > +#define CONFIG_SYS_PCIE1_IO_BUS0x > > +#define CONFIG_SYS_PCIE1_IO_SIZE 0x0001 /* 64k */ > > +#define CONFIG_SYS_PCIE2_MEM_BUS 0xe000 > > +#define CONFIG_SYS_PCIE2_MEM_SIZE 0x2000 /* > 512M */
Re: [U-Boot] [PATCH 22/47] P1020: dts: Added PCIe DT nodes
Hi Zhiqiang,
On Tue, Aug 27, 2019 at 10:46 AM Z.q. Hou wrote:
>
> Hi Bin,
>
> Thanks a lot for your comments!
>
> > -Original Message-
> > From: Bin Meng
> > Sent: 2019年8月26日 22:50
> > To: Z.q. Hou
> > Cc: U-Boot Mailing List ; Prabhakar Kushwaha
> > ; Wolfgang Denk ; Priyanka
> > Jain ; Shengzhou Liu
> > Subject: Re: [U-Boot] [PATCH 22/47] P1020: dts: Added PCIe DT nodes
> >
> > Hi Zhiqiang,
> >
> > On Tue, Jul 23, 2019 at 9:33 PM Hou Zhiqiang
> > wrote:
> > >
> > > P1020 integrated 2 PCIe controllers, which is compatible with the PCI
> > > Express™ Base Specification, Revision 1.0a, and this patch is to add
> > > DT node for each PCIe controller.
> > >
> > > Signed-off-by: Hou Zhiqiang
> > > ---
> > > arch/powerpc/dts/p1020-post.dtsi | 20
> > > arch/powerpc/dts/p1020rdb-pc.dts | 12
> > > arch/powerpc/dts/p1020rdb-pc_36b.dts | 12
> > > arch/powerpc/dts/p1020rdb-pd.dts | 12
> > > 4 files changed, 56 insertions(+)
> > >
> > > diff --git a/arch/powerpc/dts/p1020-post.dtsi
> > > b/arch/powerpc/dts/p1020-post.dtsi
> > > index e1a4f50..1e5e678 100644
> > > --- a/arch/powerpc/dts/p1020-post.dtsi
> > > +++ b/arch/powerpc/dts/p1020-post.dtsi
> > > @@ -25,3 +25,23 @@
> > > last-interrupt-source = <255>;
> > > };
> > > };
> > > +
> > > +/* PCIe controller base address 0x9000 */
> > > + {
> > > + compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq";
> > > + law_trgt_if = <1>;
> > > + #address-cells = <3>;
> > > + #size-cells = <2>;
> > > + device_type = "pci";
> > > + bus-range = <0x0 0xff>;
> > > +};
> > > +
> > > +/* PCIe controller base address 0xa000 */
> > > + {
> > > + compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq";
> > > + law_trgt_if = <2>;
> > > + #address-cells = <3>;
> > > + #size-cells = <2>;
> > > + device_type = "pci";
> > > + bus-range = <0x0 0xff>;
> > > +};
> > > diff --git a/arch/powerpc/dts/p1020rdb-pc.dts
> > > b/arch/powerpc/dts/p1020rdb-pc.dts
> > > index fd68b8b..7ebaa61 100644
> > > --- a/arch/powerpc/dts/p1020rdb-pc.dts
> > > +++ b/arch/powerpc/dts/p1020rdb-pc.dts
> > > @@ -18,6 +18,18 @@
> > > soc: soc@ffe0 {
> > > ranges = <0x0 0x0 0xffe0 0x10>;
> > > };
> > > +
> > > + pci1: pcie@ffe09000 {
> >
> > Why this is named as pci1?
>
> The P1020 reference manual said the first controller registers offset begin
> at 0xa000
> and the second begin at 0x9000.
>
> >
> > > + reg = <0x0 0xffe09000 0x0 0x1000>; /* registers
> > */
> >
> > Shouldn't the property be put in the dtsi file?
>
> The registers starting addresses are different between 32bit and 36bit dts.
>
I see. But looks they are inconsistent. Some of the platforms put the
reg in the dtsi, and some do not. I believe it's because some
platforms force to select CONFIG_PHYS_64BIT hence no need to have two
version of in DT?
Regards,
Bin
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Re: [U-Boot] [PATCH 30/47] powerpc: P2041RDB: Disable legacy PCIe driver when DM_PCI is enabled
Hi Bin, Thanks a lot for your comments! > -Original Message- > From: Bin Meng > Sent: 2019年8月26日 22:50 > To: Z.q. Hou > Cc: U-Boot Mailing List ; Prabhakar Kushwaha > ; Wolfgang Denk ; Priyanka > Jain ; Shengzhou Liu > Subject: Re: [U-Boot] [PATCH 30/47] powerpc: P2041RDB: Disable legacy > PCIe driver when DM_PCI is enabled > > On Tue, Jul 23, 2019 at 9:44 PM Hou Zhiqiang > wrote: > > > > Disable legacy PCIe driver and unused PCIe macros when DM_PCI enabled. > > > > Signed-off-by: Hou Zhiqiang > > --- > > include/configs/P2041RDB.h | 55 > > +- > > 1 file changed, 15 insertions(+), 40 deletions(-) > > > > diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h > > index b433308..ba670d7 100644 > > --- a/include/configs/P2041RDB.h > > +++ b/include/configs/P2041RDB.h > > @@ -37,7 +37,6 @@ > > #define CONFIG_PCIE1 /* PCIE controller 1 */ > > #define CONFIG_PCIE2 /* PCIE controller 2 */ > > #define CONFIG_PCIE3 /* PCIE controller 3 */ > > -#define CONFIG_FSL_PCI_INIT/* Use common FSL init > code */ > > #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI > resources */ > > > > #define CONFIG_SYS_SRIO > > @@ -354,60 +353,21 @@ unsigned long get_board_sys_clk(unsigned long > > dummy); > > > > /* controller 1, direct to uli, tgtid 3, Base address 2 */ > > #define CONFIG_SYS_PCIE1_MEM_VIRT 0x8000 > > -#ifdef CONFIG_PHYS_64BIT > > -#define CONFIG_SYS_PCIE1_MEM_BUS 0xe000 > > #define CONFIG_SYS_PCIE1_MEM_PHYS 0xcull > > -#else > > -#define CONFIG_SYS_PCIE1_MEM_BUS 0x8000 > > -#define CONFIG_SYS_PCIE1_MEM_PHYS 0x8000 > > -#endif > > -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x2000 /* > 512M */ > > #define CONFIG_SYS_PCIE1_IO_VIRT 0xf800 > > -#define CONFIG_SYS_PCIE1_IO_BUS0x > > -#ifdef CONFIG_PHYS_64BIT > > #define CONFIG_SYS_PCIE1_IO_PHYS 0xff800ull > > -#else > > -#define CONFIG_SYS_PCIE1_IO_PHYS 0xf800 > > -#endif > > -#define CONFIG_SYS_PCIE1_IO_SIZE 0x0001 /* 64k */ > > > > /* controller 2, Slot 2, tgtid 2, Base address 201000 */ > > #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa000 > > -#ifdef CONFIG_PHYS_64BIT > > -#define CONFIG_SYS_PCIE2_MEM_BUS 0xe000 > > #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc2000ull > > -#else > > -#define CONFIG_SYS_PCIE2_MEM_BUS 0xa000 > > -#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa000 > > -#endif > > -#define CONFIG_SYS_PCIE2_MEM_SIZE 0x2000 /* > 512M */ > > #define CONFIG_SYS_PCIE2_IO_VIRT 0xf801 > > -#define CONFIG_SYS_PCIE2_IO_BUS0x > > -#ifdef CONFIG_PHYS_64BIT > > #define CONFIG_SYS_PCIE2_IO_PHYS 0xff801ull > > -#else > > -#define CONFIG_SYS_PCIE2_IO_PHYS 0xf801 > > -#endif > > -#define CONFIG_SYS_PCIE2_IO_SIZE 0x0001 /* 64k */ > > > > /* controller 3, Slot 1, tgtid 1, Base address 202000 */ > > #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc000 > > -#ifdef CONFIG_PHYS_64BIT > > -#define CONFIG_SYS_PCIE3_MEM_BUS 0xe000 > > #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc4000ull > > -#else > > -#define CONFIG_SYS_PCIE3_MEM_BUS 0xc000 > > -#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc000 > > -#endif > > -#define CONFIG_SYS_PCIE3_MEM_SIZE 0x2000 /* > 512M */ > > #define CONFIG_SYS_PCIE3_IO_VIRT 0xf802 > > -#define CONFIG_SYS_PCIE3_IO_BUS0x > > -#ifdef CONFIG_PHYS_64BIT > > #define CONFIG_SYS_PCIE3_IO_PHYS 0xff802ull > > -#else > > -#define CONFIG_SYS_PCIE3_IO_PHYS 0xf802 > > -#endif > > -#define CONFIG_SYS_PCIE3_IO_SIZE 0x0001 /* 64k */ > > > > /* Qman/Bman */ > > #define CONFIG_SYS_BMAN_NUM_PORTALS10 > > @@ -489,7 +449,22 @@ unsigned long get_board_sys_clk(unsigned long > > dummy); #endif > > > > #ifdef CONFIG_PCI > > +#if !defined(CONFIG_DM_PCI) > > +#define CONFIG_FSL_PCI_INIT/* Use common FSL init code */ > > #define CONFIG_PCI_INDIRECT_BRIDGE > > +#define CONFIG_SYS_PCIE1_MEM_BUS 0xe000 > > missing CONFIG_PHYS_64BIT? The P2041RDB board selected CONFIG_PHYS_64BIT, so removed these unused macros. Thanks, Zhiqiang > > > +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x2000 /* > 512M */ > > +#define CONFIG_SYS_PCIE1_IO_BUS0x > > +#define CONFIG_SYS_PCIE1_IO_SIZE 0x0001 /* 64k */ > > +#define CONFIG_SYS_PCIE2_MEM_BUS 0xe000 > > +#define CONFIG_SYS_PCIE2_MEM_SIZE 0x2000 /* > 512M */ > > +#define CONFIG_SYS_PCIE2_IO_BUS0x > > +#define CONFIG_SYS_PCIE2_IO_SIZE 0x0001 /* 64k */ > > +#define CONFIG_SYS_PCIE3_MEM_BUS 0xe000 > > +#define CONFIG_SYS_PCIE3_MEM_SIZE 0x2000 /* > 512M */ > > +#define CONFIG_SYS_PCIE3_IO_BUS
Re: [U-Boot] [PATCH 25/47] P2020: dts: Added PCIe DT nodes
Hi Zhiqiang,
On Tue, Aug 27, 2019 at 10:52 AM Z.q. Hou wrote:
>
> Hi Bin,
>
> Thanks a lot for your comments!
>
> > -Original Message-
> > From: Bin Meng
> > Sent: 2019年8月26日 22:50
> > To: Z.q. Hou
> > Cc: U-Boot Mailing List ; Prabhakar Kushwaha
> > ; Wolfgang Denk ; Priyanka
> > Jain ; Shengzhou Liu
> > Subject: Re: [U-Boot] [PATCH 25/47] P2020: dts: Added PCIe DT nodes
> >
> > On Tue, Jul 23, 2019 at 9:39 PM Hou Zhiqiang
> > wrote:
> > >
> > > P2020 integrated 3 PCIe controllers, which is compatible with the PCI
> > > Express™ Base Specification, Revision 1.0a, and this patch is to add
> > > DT node for each PCIe controller.
> > >
> > > Signed-off-by: Hou Zhiqiang
> > > ---
> > > arch/powerpc/dts/p2020-post.dtsi | 30
> > ++
> > > arch/powerpc/dts/p2020rdb-pc.dts | 17 +
> > > arch/powerpc/dts/p2020rdb-pc_36b.dts | 17 +
> > > 3 files changed, 64 insertions(+)
> > >
> > > diff --git a/arch/powerpc/dts/p2020-post.dtsi
> > > b/arch/powerpc/dts/p2020-post.dtsi
> > > index f20d1fa..f696f35 100644
> > > --- a/arch/powerpc/dts/p2020-post.dtsi
> > > +++ b/arch/powerpc/dts/p2020-post.dtsi
> > > @@ -25,3 +25,33 @@
> > > last-interrupt-source = <255>;
> > > };
> > > };
> > > +
> > > +/* PCIe controller base address 0x8000 */
> > > + {
> >
> > pci0?
>
> Describe the controller index and starting address according to P2020 RM.
OK, so will this weird index number (2, 1, 0) break the index
calculation log in the following patch?
http://patchwork.ozlabs.org/patch/1152811/
Regards,
Bin
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Re: [U-Boot] [PATCH] cmd: host: fix seg fault at "host info"
On 8/22/19 9:47 AM, AKASHI Takahiro wrote:
With the patch below applied, host_block_dev structure was switched
to be placed in platdata rather than priv. The command "host info"
must be aligned with this change. Otherwise, we will see "Segmentation
Fault."
Fixes: 8f994c860d91 ("sandbox: blk: Switch to use platdata_auto_alloc_size for the
driver data")
Signed-off-by: AKASHI Takahiro
Reviewed-by: Heinrich Schuchardt
---
cmd/host.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/cmd/host.c b/cmd/host.c
index f7d3eae5b1ad..98c4d2a099e9 100644
--- a/cmd/host.c
+++ b/cmd/host.c
@@ -89,7 +89,7 @@ static int do_host_info(cmd_tbl_t *cmdtp, int flag, int argc,
struct host_block_dev *host_dev;
#ifdef CONFIG_BLK
- host_dev = dev_get_priv(blk_dev->bdev);
+ host_dev = dev_get_platdata(blk_dev->bdev);
#else
host_dev = blk_dev->priv;
#endif
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Re: [U-Boot] [PATCH 25/47] P2020: dts: Added PCIe DT nodes
Hi Bin,
Thanks a lot for your comments!
> -Original Message-
> From: Bin Meng
> Sent: 2019年8月26日 22:50
> To: Z.q. Hou
> Cc: U-Boot Mailing List ; Prabhakar Kushwaha
> ; Wolfgang Denk ; Priyanka
> Jain ; Shengzhou Liu
> Subject: Re: [U-Boot] [PATCH 25/47] P2020: dts: Added PCIe DT nodes
>
> On Tue, Jul 23, 2019 at 9:39 PM Hou Zhiqiang
> wrote:
> >
> > P2020 integrated 3 PCIe controllers, which is compatible with the PCI
> > Express™ Base Specification, Revision 1.0a, and this patch is to add
> > DT node for each PCIe controller.
> >
> > Signed-off-by: Hou Zhiqiang
> > ---
> > arch/powerpc/dts/p2020-post.dtsi | 30
> ++
> > arch/powerpc/dts/p2020rdb-pc.dts | 17 +
> > arch/powerpc/dts/p2020rdb-pc_36b.dts | 17 +
> > 3 files changed, 64 insertions(+)
> >
> > diff --git a/arch/powerpc/dts/p2020-post.dtsi
> > b/arch/powerpc/dts/p2020-post.dtsi
> > index f20d1fa..f696f35 100644
> > --- a/arch/powerpc/dts/p2020-post.dtsi
> > +++ b/arch/powerpc/dts/p2020-post.dtsi
> > @@ -25,3 +25,33 @@
> > last-interrupt-source = <255>;
> > };
> > };
> > +
> > +/* PCIe controller base address 0x8000 */
> > + {
>
> pci0?
Describe the controller index and starting address according to P2020 RM.
>
> > + compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq";
> > + law_trgt_if = <0>;
> > + #address-cells = <3>;
> > + #size-cells = <2>;
> > + device_type = "pci";
> > + bus-range = <0x0 0xff>;
> > +};
> > +
> > +/* PCIe controller base address 0x9000 */
> > + {
> > + compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq";
> > + law_trgt_if = <1>;
> > + #address-cells = <3>;
> > + #size-cells = <2>;
> > + device_type = "pci";
> > + bus-range = <0x0 0xff>;
> > +};
> > +
> > +/* PCIe controller base address 0xa000 */
> > + {
>
> pci2?
>
> > + compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq";
> > + law_trgt_if = <2>;
> > + #address-cells = <3>;
> > + #size-cells = <2>;
> > + device_type = "pci";
> > + bus-range = <0x0 0xff>;
> > +};
> > diff --git a/arch/powerpc/dts/p2020rdb-pc.dts
> > b/arch/powerpc/dts/p2020rdb-pc.dts
> > index 4800b76..08befd4 100644
> > --- a/arch/powerpc/dts/p2020rdb-pc.dts
> > +++ b/arch/powerpc/dts/p2020rdb-pc.dts
> > @@ -18,6 +18,23 @@
> > soc: soc@ffe0 {
> > ranges = <0x0 0x0 0xffe0 0x10>;
> > };
> > +
> > + pci2: pcie@ffe08000 {
> > + reg = <0x0 0xffe08000 0x0 0x1000>; /* registers
> */
>
> put in dtsi?
The same reason as P1020, see #22 of this series.
Thanks,
Zhiqiang
>
> > + status = "disabled";
> > + };
> > +
> > + pci1: pcie@ffe09000 {
> > + reg = <0x0 0xffe09000 0x0 0x1000>; /* registers
> */
> > + ranges = <0x0100 0x0 0x 0x0 0xffc1
> 0x0 0x0001 /* downstream I/O */
> > + 0x0200 0x0 0xa000 0x0
> 0xa000 0x0 0x2000>; /* non-prefetchable memory */
> > + };
> > +
> > + pci0: pcie@ffe0a000 {
> > + reg = <0x0 0xffe0a000 0x0 0x1000>; /* registers
> */
> > + ranges = <0x0100 0x0 0x 0x0 0xffc0
> 0x0 0x0001 /* downstream I/O */
> > + 0x0200 0x0 0x8000 0x0
> 0x8000 0x0 0x2000>; /* non-prefetchable memory */
> > + };
> > };
> >
> > /include/ "p2020-post.dtsi"
> > diff --git a/arch/powerpc/dts/p2020rdb-pc_36b.dts
> > b/arch/powerpc/dts/p2020rdb-pc_36b.dts
> > index 8323b90..04b2519 100644
> > --- a/arch/powerpc/dts/p2020rdb-pc_36b.dts
> > +++ b/arch/powerpc/dts/p2020rdb-pc_36b.dts
> > @@ -18,6 +18,23 @@
> > soc: soc@fffe0 {
> > ranges = <0x0 0xf 0xffe0 0x10>;
> > };
> > +
> > + pci2: pcie@fffe08000 {
> > + reg = <0xf 0xffe08000 0x0 0x1000>; /* registers
> */
> > + status = "disabled";
> > + };
> > +
> > + pci1: pcie@fffe09000 {
> > + reg = <0xf 0xffe09000 0x0 0x1000>; /* registers
> */
> > + ranges = <0x0100 0x0 0x 0xf 0xffc1
> 0x0 0x0001 /* downstream I/O */
> > + 0x0200 0x0 0xc000 0xc
> 0x2000 0x0 0x2000>; /* non-prefetchable memory */
> > + };
> > +
> > + pci0: pcie@fffe0a000 {
> > + reg = <0xf 0xffe0a000 0x0 0x1000>; /* registers
> */
> > + ranges = <0x0100 0x0 0x 0xf 0xffc0
> 0x0 0x0001 /* downstream I/O */
> > + 0x0200 0x0 0x8000 0xc
> 0x 0x0 0x2000>; /* non-prefetchable memory */
> > + };
> > };
> >
> > /include/ "p2020-post.dtsi"
> > --
>
> Regards,
> Bin
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Re: [U-Boot] [PATCH 03/47] configs: T2080RDB: Enable PCIe driver
Hi Zhiqiang, On Tue, Aug 27, 2019 at 10:05 AM Z.q. Hou wrote: > > Hi Bin, > > Thanks a lot for your comments! > > > -Original Message- > > From: Bin Meng > > Sent: 2019年8月26日 22:48 > > To: Z.q. Hou > > Cc: U-Boot Mailing List ; Prabhakar Kushwaha > > ; Wolfgang Denk ; Priyanka > > Jain ; Shengzhou Liu > > Subject: Re: [U-Boot] [PATCH 03/47] configs: T2080RDB: Enable PCIe driver > > > > Hi Zhiqiang, > > > > On Tue, Jul 23, 2019 at 9:24 PM Hou Zhiqiang > > wrote: > > > > > > Enable the DM PCIe driver in T2080RDB defconfig. > > > > > > Signed-off-by: Hou Zhiqiang > > > --- > > > configs/T2080RDB_NAND_defconfig | 4 > > > configs/T2080RDB_SDCARD_defconfig | 4 > > > configs/T2080RDB_SPIFLASH_defconfig | 4 > > > configs/T2080RDB_defconfig | 4 > > > 4 files changed, 16 insertions(+) > > > > > > diff --git a/configs/T2080RDB_NAND_defconfig > > > b/configs/T2080RDB_NAND_defconfig index 7eb7058..30ec72b 100644 > > > --- a/configs/T2080RDB_NAND_defconfig > > > +++ b/configs/T2080RDB_NAND_defconfig > > > @@ -57,6 +57,10 @@ CONFIG_PHYLIB=y > > > CONFIG_PHY_AQUANTIA=y > > > CONFIG_E1000=y > > > CONFIG_MII=y > > > +CONFIG_DM=y > > > +CONFIG_DM_PCI=y > > > +CONFIG_DM_PCI_COMPAT=y > > > > Why do we need this option? I vaguely remember I commented in as similar > > patch for some other board (maybe layerscape arm?) > > We discussed this during adding PCIe DM driver on T2080QDS, so it's the same > reason. I dug into the mailing list archive, and I see: https://lists.denx.de/pipermail/u-boot/2019-May/370756.html In that thread, you wrote: "I will submit a patch to remove the DM_PCI_COMPAT when all driver has been converted." So I believe you guys have not converted all PowerPC drivers to DM, hence it's still left there? Regards, Bin ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 1/1] x86: show UEFI images involved in crash
Hi Heinrich,
On Tue, Aug 27, 2019 at 10:43 AM Heinrich Schuchardt wrote:
>
> On 8/27/19 3:18 AM, Bin Meng wrote:
> > Hi Heinrich,
> >
> > On Tue, Aug 27, 2019 at 1:26 AM Heinrich Schuchardt
> > wrote:
> >>
> >> On 8/26/19 8:13 AM, Bin Meng wrote:
> >>> Hi Heinrich,
> >>>
> >>> On Mon, Aug 26, 2019 at 1:55 AM Heinrich Schuchardt
> >>> wrote:
>
> If a crash occurs, show the loaded UEFI images to facilitate analysis.
>
> This is an example output:
>
> => bootefi 0x100
> Found 0 disks
> Hello world of bugs!
> Invalid Opcode (Undefined Opcode)
> EIP: 0010:[<06ceb06e>] EFLAGS: 00010206
> Original EIP :[]
> EAX: EBX: 06cec000 ECX: 0fd0 EDX: 0001
> ESI: 06ced18a EDI: 07d0fe10 EBP: 07fe27a0 ESP: 07d0fde0
> DS: 0018 ES: 0018 FS: 0020 GS: 0018 SS: 0018
> CR0: 0033 CR2: CR3: CR4:
> DR0: DR1: DR2: DR3:
> DR6: 0ff0 DR7: 0400
> Stack:
> 0x07d0fde8 : 0x
> 0x07d0fde4 : 0x06ced040
> --->0x07d0fde0 : 0x07fe27a0
> 0x07d0fddc : 0x00010206
> 0x07d0fdd8 : 0x0010
> 0x07d0fdd4 : 0x06ceb06e
> UEFI image [0x06cea000:0x06cf0fff] pc=0x106e '/bug-i386.efi'
> ### ERROR ### Please RESET the board ###
>
> With the additional information provided by this patch we know that the
> problem occurred 0x106e after the load address of bug-i386.efi.
>
> Signed-off-by: Heinrich Schuchardt
> ---
> arch/x86/cpu/i386/interrupt.c | 14 ++
> 1 file changed, 14 insertions(+)
>
> diff --git a/arch/x86/cpu/i386/interrupt.c
> b/arch/x86/cpu/i386/interrupt.c
> index 47df3172b7..1445204878 100644
> --- a/arch/x86/cpu/i386/interrupt.c
> +++ b/arch/x86/cpu/i386/interrupt.c
> @@ -12,6 +12,7 @@
>
> #include
> #include
> +#include
> #include
> #include
> #include
> @@ -64,6 +65,18 @@ static char *exceptions[] = {
> "Reserved"
> };
>
> +/**
> + * show_efi_loaded_images() - show loaded UEFI images
> + *
> + * List all loaded UEFI images.
> + *
> + * @eip: instruction pointer
> + */
> +static void show_efi_loaded_images(uintptr_t eip)
> +{
> + efi_print_image_infos((void *)eip);
> +}
> +
> static void dump_regs(struct irq_regs *regs)
> {
> unsigned long cs, eip, eflags;
> @@ -144,6 +157,7 @@ static void dump_regs(struct irq_regs *regs)
> printf("0x%8.8lx : 0x%8.8lx\n", sp, (ulong)readl(sp));
> sp -= 4;
> }
> + show_efi_loaded_images(eip);
> >>>
> >>> Should we wrap the call with #ifdef CONFIG_EFI_LOADER or something?
> >>
> >> In include/efi_loader.h we have
> >>
> >> static inline void efi_print_image_infos(void *pc) { }
> >>
> >> if EFI_LOADER is not defined.
> >>
> >> Best regards
> >>
> >
> > I feel a little bit strange of show_efi_loaded_images() being called
> > in the dump_regs(). The dump_regs() is called in the exception
> > handler. It's a bit odd we show the EFI image info in the exception
> > handler. Shouldn't we print the EFI image info from the command line
> > interface?
>
> We have a command to display loaded images from the command line
> (efidebug images). But when a crash occurs in an UEFI application, I
> cannot reach the command line anymore.
>
> When running complex UEFI applications like the SCT multiple UEFI images
> are involved with loading addresses which I cannot control from the
> command line. So it is hard to find out where a crash occurred.
>
> For ARM we already have the same information in crash dumps.
>
> If not UEFI image is loaded, no line is added to the crash dump.
OK, could you please provide a sample EFI image of such to trigger the
issue? I would like to have a test.
Regards,
Bin
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Re: [U-Boot] [PATCH 13/47] powerpc: T102xRDB: Disable legacy PCIe driver when DM_PCI is enabled
Hi Zhiqiang, On Tue, Aug 27, 2019 at 10:33 AM Z.q. Hou wrote: > > Hi Bin, > > Thanks a lot for your comments! > > > -Original Message- > > From: Bin Meng > > Sent: 2019年8月26日 22:49 > > To: Z.q. Hou > > Cc: U-Boot Mailing List ; Prabhakar Kushwaha > > ; Wolfgang Denk ; Priyanka > > Jain ; Shengzhou Liu > > Subject: Re: [U-Boot] [PATCH 13/47] powerpc: T102xRDB: Disable legacy > > PCIe driver when DM_PCI is enabled > > > > Hi Zhiqiang, > > > > On Tue, Jul 23, 2019 at 9:36 PM Hou Zhiqiang > > wrote: > > > > > > Disable legacy PCIe driver and unused PCIe macros when DM_PCI enabled. > > > > > > Signed-off-by: Hou Zhiqiang > > > --- > > > include/configs/T102xRDB.h | 54 > > > +- > > > 1 file changed, 15 insertions(+), 39 deletions(-) > > > > > > diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h > > > index 3715e25..4fb1709 100644 > > > --- a/include/configs/T102xRDB.h > > > +++ b/include/configs/T102xRDB.h > > > @@ -500,72 +500,48 @@ unsigned long get_board_ddr_clk(void); > > > #define CONFIG_PCIE1 /* PCIE controller 1 */ > > > #define CONFIG_PCIE2 /* PCIE controller 2 */ > > > #define CONFIG_PCIE3 /* PCIE controller 3 */ > > > -#define CONFIG_FSL_PCI_INIT/* Use common FSL init code */ > > > #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ > > > -#define CONFIG_PCI_INDIRECT_BRIDGE > > > > > > #ifdef CONFIG_PCI > > > /* controller 1, direct to uli, tgtid 3, Base address 2 */ > > > #ifdef CONFIG_PCIE1 > > > #defineCONFIG_SYS_PCIE1_MEM_VIRT 0x8000 > > > -#ifdef CONFIG_PHYS_64BIT > > > -#defineCONFIG_SYS_PCIE1_MEM_BUS0xe000 > > > #defineCONFIG_SYS_PCIE1_MEM_PHYS > > 0xcull > > > -#else > > > -#define CONFIG_SYS_PCIE1_MEM_BUS 0x8000 > > > -#define CONFIG_SYS_PCIE1_MEM_PHYS 0x8000 > > > -#endif > > > -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x1000 /* > > 256M */ > > > #define CONFIG_SYS_PCIE1_IO_VIRT 0xf800 > > > -#define CONFIG_SYS_PCIE1_IO_BUS0x > > > -#ifdef CONFIG_PHYS_64BIT > > > #define CONFIG_SYS_PCIE1_IO_PHYS 0xff800ull > > > -#else > > > -#define CONFIG_SYS_PCIE1_IO_PHYS 0xf800 > > > -#endif > > > -#define CONFIG_SYS_PCIE1_IO_SIZE 0x0001 /* 64k */ > > > #endif > > > > > > /* controller 2, Slot 2, tgtid 2, Base address 201000 */ #ifdef > > > CONFIG_PCIE2 > > > #define CONFIG_SYS_PCIE2_MEM_VIRT 0x9000 > > > -#ifdef CONFIG_PHYS_64BIT > > > -#define CONFIG_SYS_PCIE2_MEM_BUS 0xe000 > > > #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc1000ull > > > -#else > > > -#define CONFIG_SYS_PCIE2_MEM_BUS 0x9000 > > > -#define CONFIG_SYS_PCIE2_MEM_PHYS 0x9000 > > > -#endif > > > -#define CONFIG_SYS_PCIE2_MEM_SIZE 0x1000 /* > > 256M */ > > > #define CONFIG_SYS_PCIE2_IO_VIRT 0xf801 > > > -#define CONFIG_SYS_PCIE2_IO_BUS0x > > > -#ifdef CONFIG_PHYS_64BIT > > > #define CONFIG_SYS_PCIE2_IO_PHYS 0xff801ull > > > -#else > > > -#define CONFIG_SYS_PCIE2_IO_PHYS 0xf801 > > > -#endif > > > -#define CONFIG_SYS_PCIE2_IO_SIZE 0x0001 /* 64k */ > > > #endif > > > > > > /* controller 3, Slot 1, tgtid 1, Base address 202000 */ #ifdef > > > CONFIG_PCIE3 > > > #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa000 > > > -#ifdef CONFIG_PHYS_64BIT > > > -#define CONFIG_SYS_PCIE3_MEM_BUS 0xe000 > > > #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc2000ull > > > -#else > > > -#define CONFIG_SYS_PCIE3_MEM_BUS 0xa000 > > > -#define CONFIG_SYS_PCIE3_MEM_PHYS 0xa000 > > > -#endif > > > -#define CONFIG_SYS_PCIE3_MEM_SIZE 0x1000 /* > > 256M */ > > > #define CONFIG_SYS_PCIE3_IO_VIRT 0xf802 > > > -#define CONFIG_SYS_PCIE3_IO_BUS0x > > > -#ifdef CONFIG_PHYS_64BIT > > > #define CONFIG_SYS_PCIE3_IO_PHYS 0xff802ull > > > -#else > > > -#define CONFIG_SYS_PCIE3_IO_PHYS 0xf802 > > > #endif > > > + > > > +#if !defined(CONFIG_DM_PCI) > > > +#define CONFIG_FSL_PCI_INIT/* Use common FSL init code */ > > > +#define CONFIG_SYS_PCIE1_MEM_BUS 0xe000 > > > > What about the #ifdef CONFIG_PHYS_64BIT part? > > In the arch/powerpc/cpu/mpc85xx/Kconfig, all the T102x boards selected > the CONFIG_PHYS_64BIT, so removed the #else...#endif part. > Thanks for the clarification. With that info, Reviewed-by: Bin Meng Regards, Bin ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 22/47] P1020: dts: Added PCIe DT nodes
Hi Bin,
Thanks a lot for your comments!
> -Original Message-
> From: Bin Meng
> Sent: 2019年8月26日 22:50
> To: Z.q. Hou
> Cc: U-Boot Mailing List ; Prabhakar Kushwaha
> ; Wolfgang Denk ; Priyanka
> Jain ; Shengzhou Liu
> Subject: Re: [U-Boot] [PATCH 22/47] P1020: dts: Added PCIe DT nodes
>
> Hi Zhiqiang,
>
> On Tue, Jul 23, 2019 at 9:33 PM Hou Zhiqiang
> wrote:
> >
> > P1020 integrated 2 PCIe controllers, which is compatible with the PCI
> > Express™ Base Specification, Revision 1.0a, and this patch is to add
> > DT node for each PCIe controller.
> >
> > Signed-off-by: Hou Zhiqiang
> > ---
> > arch/powerpc/dts/p1020-post.dtsi | 20
> > arch/powerpc/dts/p1020rdb-pc.dts | 12
> > arch/powerpc/dts/p1020rdb-pc_36b.dts | 12
> > arch/powerpc/dts/p1020rdb-pd.dts | 12
> > 4 files changed, 56 insertions(+)
> >
> > diff --git a/arch/powerpc/dts/p1020-post.dtsi
> > b/arch/powerpc/dts/p1020-post.dtsi
> > index e1a4f50..1e5e678 100644
> > --- a/arch/powerpc/dts/p1020-post.dtsi
> > +++ b/arch/powerpc/dts/p1020-post.dtsi
> > @@ -25,3 +25,23 @@
> > last-interrupt-source = <255>;
> > };
> > };
> > +
> > +/* PCIe controller base address 0x9000 */
> > + {
> > + compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq";
> > + law_trgt_if = <1>;
> > + #address-cells = <3>;
> > + #size-cells = <2>;
> > + device_type = "pci";
> > + bus-range = <0x0 0xff>;
> > +};
> > +
> > +/* PCIe controller base address 0xa000 */
> > + {
> > + compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq";
> > + law_trgt_if = <2>;
> > + #address-cells = <3>;
> > + #size-cells = <2>;
> > + device_type = "pci";
> > + bus-range = <0x0 0xff>;
> > +};
> > diff --git a/arch/powerpc/dts/p1020rdb-pc.dts
> > b/arch/powerpc/dts/p1020rdb-pc.dts
> > index fd68b8b..7ebaa61 100644
> > --- a/arch/powerpc/dts/p1020rdb-pc.dts
> > +++ b/arch/powerpc/dts/p1020rdb-pc.dts
> > @@ -18,6 +18,18 @@
> > soc: soc@ffe0 {
> > ranges = <0x0 0x0 0xffe0 0x10>;
> > };
> > +
> > + pci1: pcie@ffe09000 {
>
> Why this is named as pci1?
The P1020 reference manual said the first controller registers offset begin at
0xa000
and the second begin at 0x9000.
>
> > + reg = <0x0 0xffe09000 0x0 0x1000>; /* registers
> */
>
> Shouldn't the property be put in the dtsi file?
The registers starting addresses are different between 32bit and 36bit dts.
Thanks,
Zhiqiang
>
> > + ranges = <0x0100 0x0 0x 0x0 0xffc1
> 0x0 0x0001 /* downstream I/O */
> > + 0x0200 0x0 0xa000 0x0
> 0xa000 0x0 0x2000>; /* non-prefetchable memory */
> > + };
> > +
> > + pci0: pcie@ffe0a000 {
>
> and this is pci0?
>
> > + reg = <0x0 0xffe0a000 0x0 0x1000>; /* registers
> */
> > + ranges = <0x0100 0x0 0x 0x0 0xffc0
> 0x0 0x0001 /* downstream I/O */
> > + 0x0200 0x0 0x8000 0x0
> 0x8000 0x0 0x2000>; /* non-prefetchable memory */
> > + };
> > };
> >
> > /include/ "p1020-post.dtsi"
> > diff --git a/arch/powerpc/dts/p1020rdb-pc_36b.dts
> > b/arch/powerpc/dts/p1020rdb-pc_36b.dts
> > index a23d031..c0e5ef4 100644
> > --- a/arch/powerpc/dts/p1020rdb-pc_36b.dts
> > +++ b/arch/powerpc/dts/p1020rdb-pc_36b.dts
> > @@ -18,6 +18,18 @@
> > soc: soc@fffe0 {
> > ranges = <0x0 0xf 0xffe0 0x10>;
> > };
> > +
> > + pci1: pcie@fffe09000 {
> > + reg = <0xf 0xffe09000 0x0 0x1000>; /* registers
> */
> > + ranges = <0x0100 0x0 0x 0xf 0xffc1
> 0x0 0x0001 /* downstream I/O */
> > + 0x0200 0x0 0xc000 0xc
> 0x2000 0x0 0x2000>; /* non-prefetchable memory */
> > + };
> > +
> > + pci0: pcie@fffe0a000 {
> > + reg = <0xf 0xffe0a000 0x0 0x1000>; /* registers
> */
> > + ranges = <0x0100 0x0 0x 0xf 0xffc0
> 0x0 0x0001 /* downstream I/O */
> > + 0x0200 0x0 0x8000 0xc
> 0x 0x0 0x2000>; /* non-prefetchable memory */
> > + };
> > };
> >
> > /include/ "p1020-post.dtsi"
> > diff --git a/arch/powerpc/dts/p1020rdb-pd.dts
> > b/arch/powerpc/dts/p1020rdb-pd.dts
> > index 81f25a3..21174a0 100644
> > --- a/arch/powerpc/dts/p1020rdb-pd.dts
> > +++ b/arch/powerpc/dts/p1020rdb-pd.dts
> > @@ -18,6 +18,18 @@
> > soc: soc@ffe0 {
> > ranges = <0x0 0x0 0xffe0 0x10>;
> > };
> > +
> > + pci1: pcie@ffe09000 {
> > + reg = <0x0 0xffe09000 0x0 0x1000>; /* registers
> */
> > + ranges = <0x0100 0x0 0x 0x0 0xffc1
> 0x0 0x0001 /* downstream I/O */
> > + 0x0200 0x0
Re: [U-Boot] [PATCH 1/1] x86: show UEFI images involved in crash
On 8/27/19 3:18 AM, Bin Meng wrote:
Hi Heinrich,
On Tue, Aug 27, 2019 at 1:26 AM Heinrich Schuchardt wrote:
On 8/26/19 8:13 AM, Bin Meng wrote:
Hi Heinrich,
On Mon, Aug 26, 2019 at 1:55 AM Heinrich Schuchardt wrote:
If a crash occurs, show the loaded UEFI images to facilitate analysis.
This is an example output:
=> bootefi 0x100
Found 0 disks
Hello world of bugs!
Invalid Opcode (Undefined Opcode)
EIP: 0010:[<06ceb06e>] EFLAGS: 00010206
Original EIP :[]
EAX: EBX: 06cec000 ECX: 0fd0 EDX: 0001
ESI: 06ced18a EDI: 07d0fe10 EBP: 07fe27a0 ESP: 07d0fde0
DS: 0018 ES: 0018 FS: 0020 GS: 0018 SS: 0018
CR0: 0033 CR2: CR3: CR4:
DR0: DR1: DR2: DR3:
DR6: 0ff0 DR7: 0400
Stack:
0x07d0fde8 : 0x
0x07d0fde4 : 0x06ced040
--->0x07d0fde0 : 0x07fe27a0
0x07d0fddc : 0x00010206
0x07d0fdd8 : 0x0010
0x07d0fdd4 : 0x06ceb06e
UEFI image [0x06cea000:0x06cf0fff] pc=0x106e '/bug-i386.efi'
### ERROR ### Please RESET the board ###
With the additional information provided by this patch we know that the
problem occurred 0x106e after the load address of bug-i386.efi.
Signed-off-by: Heinrich Schuchardt
---
arch/x86/cpu/i386/interrupt.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/arch/x86/cpu/i386/interrupt.c b/arch/x86/cpu/i386/interrupt.c
index 47df3172b7..1445204878 100644
--- a/arch/x86/cpu/i386/interrupt.c
+++ b/arch/x86/cpu/i386/interrupt.c
@@ -12,6 +12,7 @@
#include
#include
+#include
#include
#include
#include
@@ -64,6 +65,18 @@ static char *exceptions[] = {
"Reserved"
};
+/**
+ * show_efi_loaded_images() - show loaded UEFI images
+ *
+ * List all loaded UEFI images.
+ *
+ * @eip: instruction pointer
+ */
+static void show_efi_loaded_images(uintptr_t eip)
+{
+ efi_print_image_infos((void *)eip);
+}
+
static void dump_regs(struct irq_regs *regs)
{
unsigned long cs, eip, eflags;
@@ -144,6 +157,7 @@ static void dump_regs(struct irq_regs *regs)
printf("0x%8.8lx : 0x%8.8lx\n", sp, (ulong)readl(sp));
sp -= 4;
}
+ show_efi_loaded_images(eip);
Should we wrap the call with #ifdef CONFIG_EFI_LOADER or something?
In include/efi_loader.h we have
static inline void efi_print_image_infos(void *pc) { }
if EFI_LOADER is not defined.
Best regards
I feel a little bit strange of show_efi_loaded_images() being called
in the dump_regs(). The dump_regs() is called in the exception
handler. It's a bit odd we show the EFI image info in the exception
handler. Shouldn't we print the EFI image info from the command line
interface?
We have a command to display loaded images from the command line
(efidebug images). But when a crash occurs in an UEFI application, I
cannot reach the command line anymore.
When running complex UEFI applications like the SCT multiple UEFI images
are involved with loading addresses which I cannot control from the
command line. So it is hard to find out where a crash occurred.
For ARM we already have the same information in crash dumps.
If not UEFI image is loaded, no line is added to the crash dump.
Best regards
Heinrich
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Re: [U-Boot] [PATCH 13/47] powerpc: T102xRDB: Disable legacy PCIe driver when DM_PCI is enabled
Hi Bin, Thanks a lot for your comments! > -Original Message- > From: Bin Meng > Sent: 2019年8月26日 22:49 > To: Z.q. Hou > Cc: U-Boot Mailing List ; Prabhakar Kushwaha > ; Wolfgang Denk ; Priyanka > Jain ; Shengzhou Liu > Subject: Re: [U-Boot] [PATCH 13/47] powerpc: T102xRDB: Disable legacy > PCIe driver when DM_PCI is enabled > > Hi Zhiqiang, > > On Tue, Jul 23, 2019 at 9:36 PM Hou Zhiqiang > wrote: > > > > Disable legacy PCIe driver and unused PCIe macros when DM_PCI enabled. > > > > Signed-off-by: Hou Zhiqiang > > --- > > include/configs/T102xRDB.h | 54 > > +- > > 1 file changed, 15 insertions(+), 39 deletions(-) > > > > diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h > > index 3715e25..4fb1709 100644 > > --- a/include/configs/T102xRDB.h > > +++ b/include/configs/T102xRDB.h > > @@ -500,72 +500,48 @@ unsigned long get_board_ddr_clk(void); > > #define CONFIG_PCIE1 /* PCIE controller 1 */ > > #define CONFIG_PCIE2 /* PCIE controller 2 */ > > #define CONFIG_PCIE3 /* PCIE controller 3 */ > > -#define CONFIG_FSL_PCI_INIT/* Use common FSL init code */ > > #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ > > -#define CONFIG_PCI_INDIRECT_BRIDGE > > > > #ifdef CONFIG_PCI > > /* controller 1, direct to uli, tgtid 3, Base address 2 */ > > #ifdef CONFIG_PCIE1 > > #defineCONFIG_SYS_PCIE1_MEM_VIRT 0x8000 > > -#ifdef CONFIG_PHYS_64BIT > > -#defineCONFIG_SYS_PCIE1_MEM_BUS0xe000 > > #defineCONFIG_SYS_PCIE1_MEM_PHYS > 0xcull > > -#else > > -#define CONFIG_SYS_PCIE1_MEM_BUS 0x8000 > > -#define CONFIG_SYS_PCIE1_MEM_PHYS 0x8000 > > -#endif > > -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x1000 /* > 256M */ > > #define CONFIG_SYS_PCIE1_IO_VIRT 0xf800 > > -#define CONFIG_SYS_PCIE1_IO_BUS0x > > -#ifdef CONFIG_PHYS_64BIT > > #define CONFIG_SYS_PCIE1_IO_PHYS 0xff800ull > > -#else > > -#define CONFIG_SYS_PCIE1_IO_PHYS 0xf800 > > -#endif > > -#define CONFIG_SYS_PCIE1_IO_SIZE 0x0001 /* 64k */ > > #endif > > > > /* controller 2, Slot 2, tgtid 2, Base address 201000 */ #ifdef > > CONFIG_PCIE2 > > #define CONFIG_SYS_PCIE2_MEM_VIRT 0x9000 > > -#ifdef CONFIG_PHYS_64BIT > > -#define CONFIG_SYS_PCIE2_MEM_BUS 0xe000 > > #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc1000ull > > -#else > > -#define CONFIG_SYS_PCIE2_MEM_BUS 0x9000 > > -#define CONFIG_SYS_PCIE2_MEM_PHYS 0x9000 > > -#endif > > -#define CONFIG_SYS_PCIE2_MEM_SIZE 0x1000 /* > 256M */ > > #define CONFIG_SYS_PCIE2_IO_VIRT 0xf801 > > -#define CONFIG_SYS_PCIE2_IO_BUS0x > > -#ifdef CONFIG_PHYS_64BIT > > #define CONFIG_SYS_PCIE2_IO_PHYS 0xff801ull > > -#else > > -#define CONFIG_SYS_PCIE2_IO_PHYS 0xf801 > > -#endif > > -#define CONFIG_SYS_PCIE2_IO_SIZE 0x0001 /* 64k */ > > #endif > > > > /* controller 3, Slot 1, tgtid 1, Base address 202000 */ #ifdef > > CONFIG_PCIE3 > > #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa000 > > -#ifdef CONFIG_PHYS_64BIT > > -#define CONFIG_SYS_PCIE3_MEM_BUS 0xe000 > > #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc2000ull > > -#else > > -#define CONFIG_SYS_PCIE3_MEM_BUS 0xa000 > > -#define CONFIG_SYS_PCIE3_MEM_PHYS 0xa000 > > -#endif > > -#define CONFIG_SYS_PCIE3_MEM_SIZE 0x1000 /* > 256M */ > > #define CONFIG_SYS_PCIE3_IO_VIRT 0xf802 > > -#define CONFIG_SYS_PCIE3_IO_BUS0x > > -#ifdef CONFIG_PHYS_64BIT > > #define CONFIG_SYS_PCIE3_IO_PHYS 0xff802ull > > -#else > > -#define CONFIG_SYS_PCIE3_IO_PHYS 0xf802 > > #endif > > + > > +#if !defined(CONFIG_DM_PCI) > > +#define CONFIG_FSL_PCI_INIT/* Use common FSL init code */ > > +#define CONFIG_SYS_PCIE1_MEM_BUS 0xe000 > > What about the #ifdef CONFIG_PHYS_64BIT part? In the arch/powerpc/cpu/mpc85xx/Kconfig, all the T102x boards selected the CONFIG_PHYS_64BIT, so removed the #else...#endif part. Thanks, Zhiqiang > > > +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x1000 /* > 256M */ > > +#define CONFIG_SYS_PCIE1_IO_BUS0x > > +#define CONFIG_SYS_PCIE1_IO_SIZE 0x0001 /* 64k */ > > +#define CONFIG_SYS_PCIE2_MEM_BUS 0xe000 > > +#define CONFIG_SYS_PCIE2_MEM_SIZE 0x1000 /* 256M */ > > +#define CONFIG_SYS_PCIE2_IO_BUS0x > > +#define CONFIG_SYS_PCIE2_IO_SIZE 0x0001 /* 64k */ > > +#define CONFIG_SYS_PCIE3_MEM_BUS 0xe000 > > +#define CONFIG_SYS_PCIE3_MEM_SIZE 0x1000 /* > 256M */ > > +#define CONFIG_SYS_PCIE3_IO_BUS0x > > #define CONFIG_SYS_PCIE3_IO_SIZE 0x0001 /* 64k > */ > > +#define CONFIG_PCI_INDIRECT_BRIDGE > > #endif > > > >
Re: [U-Boot] [PATCH 03/47] configs: T2080RDB: Enable PCIe driver
Hi Bin, Thanks a lot for your comments! > -Original Message- > From: Bin Meng > Sent: 2019年8月26日 22:48 > To: Z.q. Hou > Cc: U-Boot Mailing List ; Prabhakar Kushwaha > ; Wolfgang Denk ; Priyanka > Jain ; Shengzhou Liu > Subject: Re: [U-Boot] [PATCH 03/47] configs: T2080RDB: Enable PCIe driver > > Hi Zhiqiang, > > On Tue, Jul 23, 2019 at 9:24 PM Hou Zhiqiang > wrote: > > > > Enable the DM PCIe driver in T2080RDB defconfig. > > > > Signed-off-by: Hou Zhiqiang > > --- > > configs/T2080RDB_NAND_defconfig | 4 > > configs/T2080RDB_SDCARD_defconfig | 4 > > configs/T2080RDB_SPIFLASH_defconfig | 4 > > configs/T2080RDB_defconfig | 4 > > 4 files changed, 16 insertions(+) > > > > diff --git a/configs/T2080RDB_NAND_defconfig > > b/configs/T2080RDB_NAND_defconfig index 7eb7058..30ec72b 100644 > > --- a/configs/T2080RDB_NAND_defconfig > > +++ b/configs/T2080RDB_NAND_defconfig > > @@ -57,6 +57,10 @@ CONFIG_PHYLIB=y > > CONFIG_PHY_AQUANTIA=y > > CONFIG_E1000=y > > CONFIG_MII=y > > +CONFIG_DM=y > > +CONFIG_DM_PCI=y > > +CONFIG_DM_PCI_COMPAT=y > > Why do we need this option? I vaguely remember I commented in as similar > patch for some other board (maybe layerscape arm?) We discussed this during adding PCIe DM driver on T2080QDS, so it's the same reason. Thanks, Zhiqiang > > > +CONFIG_PCIE_FSL=y > > CONFIG_SYS_NS16550=y > > CONFIG_SPI=y > > CONFIG_FSL_ESPI=y > > diff --git a/configs/T2080RDB_SDCARD_defconfig > > b/configs/T2080RDB_SDCARD_defconfig > > index 9ea6698..22c2e05 100644 > > --- a/configs/T2080RDB_SDCARD_defconfig > > +++ b/configs/T2080RDB_SDCARD_defconfig > > @@ -56,6 +56,10 @@ CONFIG_PHYLIB=y > > CONFIG_PHY_AQUANTIA=y > > CONFIG_E1000=y > > CONFIG_MII=y > > +CONFIG_DM=y > > +CONFIG_DM_PCI=y > > +CONFIG_DM_PCI_COMPAT=y > > +CONFIG_PCIE_FSL=y > > CONFIG_SYS_NS16550=y > > CONFIG_SPI=y > > CONFIG_FSL_ESPI=y > > diff --git a/configs/T2080RDB_SPIFLASH_defconfig > > b/configs/T2080RDB_SPIFLASH_defconfig > > index 988897b..e70fa0d 100644 > > --- a/configs/T2080RDB_SPIFLASH_defconfig > > +++ b/configs/T2080RDB_SPIFLASH_defconfig > > @@ -56,6 +56,10 @@ CONFIG_SPI_FLASH_STMICRO=y > CONFIG_PHYLIB=y > > CONFIG_PHY_AQUANTIA=y CONFIG_E1000=y > > +CONFIG_DM=y > > +CONFIG_DM_PCI=y > > +CONFIG_DM_PCI_COMPAT=y > > +CONFIG_PCIE_FSL=y > > CONFIG_MII=y > > CONFIG_SYS_NS16550=y > > CONFIG_SPI=y > > diff --git a/configs/T2080RDB_defconfig b/configs/T2080RDB_defconfig > > index 3f7e282..b620349 100644 > > --- a/configs/T2080RDB_defconfig > > +++ b/configs/T2080RDB_defconfig > > @@ -45,6 +45,10 @@ CONFIG_PHYLIB=y > > CONFIG_PHY_AQUANTIA=y > > CONFIG_E1000=y > > CONFIG_MII=y > > +CONFIG_DM=y > > +CONFIG_DM_PCI=y > > +CONFIG_DM_PCI_COMPAT=y > > +CONFIG_PCIE_FSL=y > > CONFIG_SYS_NS16550=y > > CONFIG_SPI=y > > CONFIG_FSL_ESPI=y > > -- > > Regards, > Bin ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 1/1] x86: show UEFI images involved in crash
Hi Heinrich,
On Tue, Aug 27, 2019 at 1:26 AM Heinrich Schuchardt wrote:
>
> On 8/26/19 8:13 AM, Bin Meng wrote:
> > Hi Heinrich,
> >
> > On Mon, Aug 26, 2019 at 1:55 AM Heinrich Schuchardt
> > wrote:
> >>
> >> If a crash occurs, show the loaded UEFI images to facilitate analysis.
> >>
> >> This is an example output:
> >>
> >> => bootefi 0x100
> >> Found 0 disks
> >> Hello world of bugs!
> >> Invalid Opcode (Undefined Opcode)
> >> EIP: 0010:[<06ceb06e>] EFLAGS: 00010206
> >> Original EIP :[]
> >> EAX: EBX: 06cec000 ECX: 0fd0 EDX: 0001
> >> ESI: 06ced18a EDI: 07d0fe10 EBP: 07fe27a0 ESP: 07d0fde0
> >> DS: 0018 ES: 0018 FS: 0020 GS: 0018 SS: 0018
> >> CR0: 0033 CR2: CR3: CR4:
> >> DR0: DR1: DR2: DR3:
> >> DR6: 0ff0 DR7: 0400
> >> Stack:
> >> 0x07d0fde8 : 0x
> >> 0x07d0fde4 : 0x06ced040
> >> --->0x07d0fde0 : 0x07fe27a0
> >> 0x07d0fddc : 0x00010206
> >> 0x07d0fdd8 : 0x0010
> >> 0x07d0fdd4 : 0x06ceb06e
> >> UEFI image [0x06cea000:0x06cf0fff] pc=0x106e '/bug-i386.efi'
> >> ### ERROR ### Please RESET the board ###
> >>
> >> With the additional information provided by this patch we know that the
> >> problem occurred 0x106e after the load address of bug-i386.efi.
> >>
> >> Signed-off-by: Heinrich Schuchardt
> >> ---
> >> arch/x86/cpu/i386/interrupt.c | 14 ++
> >> 1 file changed, 14 insertions(+)
> >>
> >> diff --git a/arch/x86/cpu/i386/interrupt.c b/arch/x86/cpu/i386/interrupt.c
> >> index 47df3172b7..1445204878 100644
> >> --- a/arch/x86/cpu/i386/interrupt.c
> >> +++ b/arch/x86/cpu/i386/interrupt.c
> >> @@ -12,6 +12,7 @@
> >>
> >> #include
> >> #include
> >> +#include
> >> #include
> >> #include
> >> #include
> >> @@ -64,6 +65,18 @@ static char *exceptions[] = {
> >> "Reserved"
> >> };
> >>
> >> +/**
> >> + * show_efi_loaded_images() - show loaded UEFI images
> >> + *
> >> + * List all loaded UEFI images.
> >> + *
> >> + * @eip: instruction pointer
> >> + */
> >> +static void show_efi_loaded_images(uintptr_t eip)
> >> +{
> >> + efi_print_image_infos((void *)eip);
> >> +}
> >> +
> >> static void dump_regs(struct irq_regs *regs)
> >> {
> >> unsigned long cs, eip, eflags;
> >> @@ -144,6 +157,7 @@ static void dump_regs(struct irq_regs *regs)
> >> printf("0x%8.8lx : 0x%8.8lx\n", sp, (ulong)readl(sp));
> >> sp -= 4;
> >> }
> >> + show_efi_loaded_images(eip);
> >
> > Should we wrap the call with #ifdef CONFIG_EFI_LOADER or something?
>
> In include/efi_loader.h we have
>
> static inline void efi_print_image_infos(void *pc) { }
>
> if EFI_LOADER is not defined.
>
> Best regards
>
I feel a little bit strange of show_efi_loaded_images() being called
in the dump_regs(). The dump_regs() is called in the exception
handler. It's a bit odd we show the EFI image info in the exception
handler. Shouldn't we print the EFI image info from the command line
interface?
Regards,
Bin
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Re: [U-Boot] [PATCH] cmd: host: fix seg fault at "host info"
On Thu, Aug 22, 2019 at 3:45 PM AKASHI Takahiro
wrote:
>
> With the patch below applied, host_block_dev structure was switched
> to be placed in platdata rather than priv. The command "host info"
> must be aligned with this change. Otherwise, we will see "Segmentation
> Fault."
>
> Fixes: 8f994c860d91 ("sandbox: blk: Switch to use platdata_auto_alloc_size
> for the driver data")
> Signed-off-by: AKASHI Takahiro
> ---
> cmd/host.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
Reviewed-by: Bin Meng
Tested-by: Bin Meng
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Re: [U-Boot] [PATCH 22/22] imx: Add i.MX8MM EVK board support.
> Subject: Re: [PATCH 22/22] imx: Add i.MX8MM EVK board support.
>
> On 15.08.19 02:57, Peng Fan wrote:
> >> Subject: Re: [PATCH 22/22] imx: Add i.MX8MM EVK board support.
> >>
> >> On 09.08.19 06:15, Peng Fan wrote:
> >>> Add board and SoC dts
> >>> Add ddr training code
> >>> support SD/MMC/GPIO/PINCTRL/UART
> >>>
> >>> Signed-off-by: Peng Fan
> >>> ---
> >>>arch/arm/dts/Makefile |3 +-
> >
> > []
> >>> +}
> >>> +#endif
> >>> +
> >>> +int dram_init(void)
> >>> +{
> >>> + /* rom_pointer[1] contains the size of TEE occupies */
> >>> + if (rom_pointer[1])
> >>> + gd->ram_size = PHYS_SDRAM_SIZE - rom_pointer[1];
> >>> + else
> >>
> >> The above case should be guarded with "#ifdef CONFIG_OPTEE", because
> >> if OPTEE is not used, rom_pointer[1] does not always seem to be zero.
> >
> > If OPTEE is not used, ATF will leave those registers as zero, so it will be
> > zero.
>
> It wasn't working for me, but I can try again and check my ATF if it really
> does.
> Maybe it would still be better to guard this check so we don't depend on the
> ATF behavior.
ok, I'll drop that.
>
> >
> >>
> >>> + gd->ram_size = PHYS_SDRAM_SIZE;
> >>> +
> >>> + return 0;
> >>> +}
> >>> +
> >
> > [...]
> >>> +CONFIG_SPL_LOAD_FIT=y
> >>>
> +CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh"
> >>
> >> For my custom i.MX8MM board I also use mkimage_fit_atf.sh, but I have
> >> done three modifications and I'm wondering how you are using the
> >> unmodified version.
> >>
> >> 1. It sets ATF_LOAD_ADDR="0x91", but in imx-atf the BL31_BASE for
> >> i.MX8MM is set to 0x92. How to handle this mismatch for i.MX8M
> >> and i.MX8MM?
> >
> > I have added README in patchset, need export ATF_LOAD_ADDR=0x92
>
> This is not very convenient. It would be better if there is a default value
> for
> each of i.MX8M and i.MX8MM.
Ah, let me try.
>
> >
> >>
> >> 2. For the 'images' section of the its file, I added 'os = "u-boot";'
> >> to the 'uboot@1' section and "os = 'arm-trusted-firmware";' to the 'atf@1'
> >> section. Without this SPL does not detect the binaries from the FIT
> >> image correctly.
> >
> > Thanks for the fix.
>
> Will you add a patch to fix this to your set?
Ok.
>
> >
> >>
> >> 3. In the 'config' section of the its file, I swapped the atf and
> >> uboot entries, so the atf binary is loaded as "firmware" and the u-boot
> binary as "loadable".
> >> Together with the change above (2) this leads to SPL code using the
> >> correct boot path as inteded by the code.
> >
> > Thanks for the fix.
>
> Ditto?
Ok.
Thanks,
Peng.
>
> >
> >>
> >>> +CONFIG_OF_BOARD_SETUP=y
> >>> +CONFIG_OF_SYSTEM_SETUP=y
> >>>
> >>
> +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m
> >> /imximage-8mm-lpddr4.cfg"
> >>> +CONFIG_DEFAULT_FDT_FILE="fsl-imx8mm-evk.dtb"
> >>> +CONFIG_BOARD_LATE_INIT=y
> >>> +CONFIG_BOARD_EARLY_INIT_F=y
> >>> +CONFIG_SPL_TEXT_BASE=0x7E1000
> >>> +CONFIG_SPL_BOARD_INIT=y
> >>> +CONFIG_SPL_SEPARATE_BSS=y
> >>> +CONFIG_SPL_I2C_SUPPORT=y
> >>> +CONFIG_HUSH_PARSER=y
> >>> +CONFIG_SYS_PROMPT="u-boot=> "
> >>> +# CONFIG_CMD_EXPORTENV is not set
> >>> +# CONFIG_CMD_IMPORTENV is not set
> >>> +# CONFIG_CMD_CRC32 is not set
> >>> +CONFIG_CMD_CLK=y
> >>> +CONFIG_CMD_FUSE=y
> >>> +CONFIG_CMD_GPIO=y
> >>> +CONFIG_CMD_I2C=y
> >>> +CONFIG_CMD_MMC=y
> >>> +CONFIG_CMD_CACHE=y
> >>> +CONFIG_CMD_REGULATOR=y
> >>> +CONFIG_CMD_EXT2=y
> >>> +CONFIG_CMD_EXT4=y
> >>> +CONFIG_CMD_EXT4_WRITE=y
> >>> +CONFIG_CMD_FAT=y
> >>> +CONFIG_OF_CONTROL=y
> >>> +CONFIG_SPL_OF_CONTROL=y
> >>> +CONFIG_DEFAULT_DEVICE_TREE="imx8mm-evk"
> >>> +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
> >>> +CONFIG_SPL_DM=y
> >>> +CONFIG_SPL_CLK_COMPOSITE_CCF=y
> >>> +CONFIG_CLK_COMPOSITE_CCF=y
> >>> +CONFIG_SPL_CLK_IMX8MM=y
> >>> +CONFIG_CLK_IMX8MM=y
> >>> +CONFIG_DM_GPIO=y
> >>> +CONFIG_MXC_GPIO=y
> >>> +CONFIG_DM_I2C=y
> >>> +CONFIG_SYS_I2C_MXC=y
> >>> +CONFIG_SYS_I2C_MXC_I2C1=y
> >>> +CONFIG_SYS_I2C_MXC_I2C2=y
> >>> +CONFIG_SYS_I2C_MXC_I2C3=y
> >>> +CONFIG_DM_MMC=y
> >>> +CONFIG_SUPPORT_EMMC_BOOT=y
> >>> +CONFIG_FSL_ESDHC_IMX=y
> >>> +CONFIG_PHYLIB=y
> >>> +CONFIG_DM_ETH=y
> >>> +CONFIG_PINCTRL=y
> >>> +CONFIG_SPL_PINCTRL=y
> >>> +CONFIG_PINCTRL_IMX8M=y
> >>> +CONFIG_DM_REGULATOR=y
> >>> +CONFIG_DM_REGULATOR_FIXED=y
> >>> +CONFIG_DM_REGULATOR_GPIO=y
> >>> +CONFIG_MXC_UART=y
> >>> +CONFIG_DM_THERMAL=y
> >>> diff --git a/include/configs/imx8mm_evk.h
> >>> b/include/configs/imx8mm_evk.h new file mode 100644 index
> >>> 00..cc63c44782
> >>> --- /dev/null
> >>> +++ b/include/configs/imx8mm_evk.h
> >>> @@ -0,0 +1,164 @@
> >>> +/* SPDX-License-Identifier: GPL-2.0+ */
> >>> +/*
> >>> + * Copyright 2018 NXP
> >>> + */
> >>> +
> >>> +#ifndef __IMX8MM_EVK_H
> >>> +#define __IMX8MM_EVK_H
> >>> +
> >>> +#include
> >>> +#include
> >>> +
> >>> +#ifdef CONFIG_SECURE_BOOT
> >>> +#define CONFIG_CSF_SIZE 0x2000 /* 8K region */
> >>> +#endif
> >>> +
> >>> +#define CONFIG_SPL_MAX_SIZE
Re: [U-Boot] [PATCH v2 00/26] i.MX8MM support
> Subject: Re: [PATCH v2 00/26] i.MX8MM support
>
> On 19.08.19 11:42, Peng Fan wrote:
> > V2:
> > Fixed comments from Lukasz and Frieder
>
> This set has 26 patches, while the previous version had 22. You should
> document all changes here, so one can easily figure out which patches were
> added/removed/merged/split.
The following 4 are new added. I'll address your comments and send out v3.
imx8m: imx-regs: drop unused register definitions
imx8m: restrict reset_cpu
imx: mmc_env: update runtime SD/MMC boot env device
imx8m: soc: probe clock device in arch_cpu_init_dm
Thanks,
Peng.
>
> >
> > V1:
> > https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpatc
> >
> hwork.ozlabs.org%2Fcover%2F1144326%2Fdata=02%7C01%7Cpeng.fa
> n%40nx
> >
> p.com%7C1809390d35d9451070f208d72a378af1%7C686ea1d3bc2b4c6fa92c
> d99c5c3
> >
> 01635%7C0%7C0%7C637024290371709641sdata=kZkJN9G%2F4vZu5c
> RqzHxMWS0
> > 6DENq9y2yUSZVjTfUjyY%3Dreserved=0
> > This is a splitted and updated patch from
> > https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpatc
> >
> hwork.ozlabs.org%2Fcover%2F1128799%2Fdata=02%7C01%7Cpeng.fa
> n%40nxp.com%7C1809390d35d9451070f208d72a378af1%7C686ea1d3bc2b4
> c6fa92cd99c5c301635%7C0%7C0%7C637024290371709641sdata=oh
> OMPQavonAd22u4tFvQTNQzOq%2FWr5YsZlZ3DfEGWRM%3Dreserved
> =0 which is to support both i.MX8MM and i.MX8MN.
> >
> > There is a README added, following that to test if you would like to.
> >
> > Peng Fan (25):
> >tools: imx8m_image: align spl bin image size
> >ddr: imx8m: fix ddr firmware location when enable SPL OF
> >imx8m: add image cfg for i.MX8MM lpddr4
> >imx: add IMX8MQ kconfig entry
> >imx: add IMX8MM kconfig entry
> >imx: imx8mm: add clock bindings header
> >imx: add i.MX8MM cpu type
> >imx: spl: add spl_board_boot_device for i.MX8MM
> >imx8m: imx-regs: drop unused register definitions
> >imx8m: update imx-regs for i.MX8MM
> >imx: add get_cpu_rev support for i.MX8MM
> >imx8m: add pin header for i.MX8MM
> >imx: add i.MX8MM PE property
> >imx8m: Fix MMU table issue for OPTEE memory
> >imx8m: set BYPASS ID SWAP to avoid AXI bus errors
> >imx8m: soc: enable SCTR clock before timer init
> >imx8m: restrict reset_cpu
> >imx8m: rename clock to clock_imx8mq
> >imx8m: restructure clock.h
> >imx8m: add clk support for i.MX8MM
> >imx: mmc_env: update runtime SD/MMC boot env device
> >imx8m: soc: probe clock device in arch_cpu_init_dm
> >arm: dts: import i.MX8MM dtsi
> >arm: dts: add i.MX8MM pin func
> >imx: Add i.MX8MM EVK board support.
> >
> > Ye Li (1):
> >imx8m: Configure trustzone region 0 for non-secure access
> >
> > arch/arm/dts/Makefile |3 +-
> > arch/arm/dts/imx8mm-evk-u-boot.dtsi| 92 +
> > arch/arm/dts/imx8mm-evk.dts| 235 +++
> > arch/arm/dts/imx8mm-pinfunc.h | 629
> +++
> > arch/arm/dts/imx8mm.dtsi | 733
>
> > arch/arm/include/asm/arch-imx/cpu.h|6 +
> > arch/arm/include/asm/arch-imx8m/clock.h| 491 +
> > arch/arm/include/asm/arch-imx8m/clock_imx8mm.h | 387
>
> > arch/arm/include/asm/arch-imx8m/clock_imx8mq.h | 424
> +
> > arch/arm/include/asm/arch-imx8m/imx-regs.h | 291 +--
> > arch/arm/include/asm/arch-imx8m/imx8mm_pins.h | 691
> +++
> > arch/arm/include/asm/mach-imx/iomux-v3.h |4 +
> > arch/arm/include/asm/mach-imx/sys_proto.h |8 +
> > arch/arm/mach-imx/cpu.c| 12 +
> > arch/arm/mach-imx/imx8m/Kconfig| 17 +-
> > arch/arm/mach-imx/imx8m/Makefile |4 +-
> > arch/arm/mach-imx/imx8m/clock_imx8mm.c | 306
> +++
> > .../arm/mach-imx/imx8m/{clock.c => clock_imx8mq.c} |5 +-
> > arch/arm/mach-imx/imx8m/clock_slice.c | 63 +
> > arch/arm/mach-imx/imx8m/imximage-8mm-lpddr4.cfg| 16 +
> > arch/arm/mach-imx/imx8m/soc.c | 129 +-
> > arch/arm/mach-imx/mmc_env.c|3 +
> > arch/arm/mach-imx/spl.c|8 +
> > board/freescale/imx8mm_evk/Kconfig | 12 +
> > board/freescale/imx8mm_evk/MAINTAINERS |6 +
> > board/freescale/imx8mm_evk/Makefile| 12 +
> > board/freescale/imx8mm_evk/imx8mm_evk.c| 45 +
> > board/freescale/imx8mm_evk/lpddr4_timing.c | 1980
>
> > board/freescale/imx8mm_evk/spl.c | 129 ++
> > configs/imx8mm_evk_defconfig | 74 +
> > drivers/ddr/imx/imx8m/helper.c | 12 +-
> > include/configs/imx8mm_evk.h | 153 ++
> > include/dt-bindings/clock/imx8mm-clock.h | 253 +++
> > tools/imx8m_image.sh
Re: [U-Boot] [PATCH v2 01/26] tools: imx8m_image: align spl bin image size
> Subject: Re: [PATCH v2 01/26] tools: imx8m_image: align spl bin image size > > On 19.08.19 11:42, Peng Fan wrote: > > The loader for the DDR firmware in drivers/ddr/imx/imx8m/helper.c uses > > a 4-byte-aligned address to load the firmware. In cases where OF is > > enabled in SPL the dtb will be appended to the SPL binary and can > > result in a binary that is not aligned correctly. If OF is not enabled > > in SPL, `_end` is already aligned correctly, but this patch does not hurt. > > > > To ensure the correct alignment we use dd to create a temporary file > > u-boot-spl-pad.bin with the correct padding. > > > > Reviewed-by: Frieder Schrempf > > I think the " at " in my e-mail address should be "@" here and in all other > patches/tags. Sorry, it is a copy paste error. I'll fix that before send pull request to Stefano if no other major comments. Thanks, Peng. > > > Tested-by: Frieder Schrempf > > Signed-off-by: Peng Fan > > --- > > tools/imx8m_image.sh | 5 +++-- > > 1 file changed, 3 insertions(+), 2 deletions(-) > > > > diff --git a/tools/imx8m_image.sh b/tools/imx8m_image.sh index > > ec0881a128..08a6a48180 100755 > > --- a/tools/imx8m_image.sh > > +++ b/tools/imx8m_image.sh > > @@ -35,8 +35,9 @@ if [ $post_process = 1 ]; then > > objcopy -I binary -O binary --pad-to 0x8000 --gap-fill=0x0 > $srctree/lpddr4_pmu_train_2d_imem.bin > lpddr4_pmu_train_2d_imem_pad.bin > > cat lpddr4_pmu_train_1d_imem_pad.bin > lpddr4_pmu_train_1d_dmem_pad.bin > lpddr4_pmu_train_1d_fw.bin > > cat lpddr4_pmu_train_2d_imem_pad.bin > $srctree/lpddr4_pmu_train_2d_dmem.bin > lpddr4_pmu_train_2d_fw.bin > > - cat spl/u-boot-spl.bin lpddr4_pmu_train_1d_fw.bin > lpddr4_pmu_train_2d_fw.bin > spl/u-boot-spl-ddr.bin > > - rm -f lpddr4_pmu_train_1d_fw.bin lpddr4_pmu_train_2d_fw.bin > lpddr4_pmu_train_1d_imem_pad.bin lpddr4_pmu_train_1d_dmem_pad.bin > lpddr4_pmu_train_2d_imem_pad.bin > > + dd if=spl/u-boot-spl.bin of=spl/u-boot-spl-pad.bin bs=4 > > conv=sync > > + cat spl/u-boot-spl-pad.bin lpddr4_pmu_train_1d_fw.bin > lpddr4_pmu_train_2d_fw.bin > spl/u-boot-spl-ddr.bin > > + rm -f lpddr4_pmu_train_1d_fw.bin lpddr4_pmu_train_2d_fw.bin > > +lpddr4_pmu_train_1d_imem_pad.bin > lpddr4_pmu_train_1d_dmem_pad.bin > > +lpddr4_pmu_train_2d_imem_pad.bin spl/u-boot-spl-pad.bin > > fi > > fi > > > > ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v4 1/1] nvme: Fix PRP Offset Invalid
On Thu, Aug 22, 2019 at 08:37:26PM -0700, Aaron Williams wrote: > When large writes take place I saw a Samsung EVO 970+ return a status > value of 0x13, PRP Offset Invalid. I tracked this down to the > improper handling of PRP entries. The blocks the PRP entries are > placed in cannot cross a page boundary and thus should be allocated > on page boundaries. This is how the Linux kernel driver works. > > With this patch, the PRP pool is allocated on a page boundary and > other than the very first allocation, the pool size is a multiple of > the page size. Each page can hold (4096 / 8) - 1 entries since the > last entry must point to the next page in the pool. > > Signed-off-by: Aaron Williams > Reviewed-by: Bin Meng Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [ANN] U-Boot v2019.10-rc3 released
Hey all, It's release day and here's v2019.10-rc3. We're well into what should be the stabilization period at this point. Going forward I am hoping for PRs that are bug fixes / regression fixes, Kconfig migrations or very self contained new boards and similar. If you have a series is "big" but doesn't quite fit into that list, please let me know with a patchwork link to the series in reply here. I'd like to get a handle on how much stuff like that it outstanding so that I can get an idea on what I should try and do about a "next" branch more often than I have and what rules might apply to it. In terms of a changelog, git log --merges v2019.10-rc2..v2019.10-rc3 continues to look pretty good but the content there varies based on what was given to me in the PR. So please, the more details in the request the better! I'm still planning on doing -rc4 on September 9th and -rc5 on September 23rd with the release scheduled on October 7th. Thanks all! -- Tom signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] ARM: omap3_logic: Fix SPL boot failure when EHCI enabled
On Thu, Aug 22, 2019 at 03:32:42PM -0500, Adam Ford wrote:
> Some of the USB code is still being built into SPL even when the
> SPL menu options have it explicitly disabled for SPL. Unit there is
> a better solution, This patch undefines CONFIG_USB_EHCI_OMAP when
> building SPL which reduces the code and lets the board boot again.
>
> Fixes: 25e4ff45b17d ("ARM: omap3_logic: Enable OMAP EHCI support
> for SOM-LV Boards")
>
> Signed-off-by: Adam Ford
>
> diff --git a/include/configs/omap3_logic.h b/include/configs/omap3_logic.h
> index b7c3ddf564..90292ae312 100644
Applied to u-boot/master, thanks!
--
Tom
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Re: [U-Boot] [PATCH] ARM: da850evm_direct_nor: Enable DM_GPIO
On Sun, Aug 25, 2019 at 10:01:14AM -0500, Adam Ford wrote: > The SPI and NAND variants enable DM_GPIO, so this patch enables > DM_GPIO for the NOR / XIP version of the da850-evm. > > Signed-off-by: Adam Ford > > diff --git a/configs/da850evm_direct_nor_defconfig > b/configs/da850evm_direct_nor_defconfig > index 2b5b0ea952..ac2d2fc8b8 100644 Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] ARM: da850evm_nand: Enable Ethernet
On Sun, Aug 25, 2019 at 09:34:49AM -0500, Adam Ford wrote: > The NAND configuration has had the ethernet missing, so this patch > enables the on-board ethernet interface. > > Signed-off-by: Adam Ford > > diff --git a/configs/da850evm_nand_defconfig b/configs/da850evm_nand_defconfig > index 8bc5b45ac2..90c4f4f5ee 100644 Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] mailmap: Update mail address
On Fri, Aug 23, 2019 at 03:59:55PM +0200, Ricardo Ribalda Delgado wrote: > Update my email address from gmail to my domain. > > Signed-off-by: Ricardo Ribalda Delgado Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] ARM: am3517-evm: Disable CONFIG_USB_EHCI_OMAP in SPL
On Thu, Aug 22, 2019 at 04:44:03PM -0500, Adam Ford wrote: > Found accidentally in omap3_logic, CONFIG_USB_EHCI_OMAP adds some > code size to SPL, so this patch disables it on the am3517-evm to > reduce the code a bit since it's tight for space. > > Signed-off-by: Adam Ford > > diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h > index 63489133a8..3e5f0b1992 100644 Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v2] board_f: reserve noncached space below malloc area
On Fri, Aug 16, 2019 at 09:57:44AM -0700, Vikas Manocha wrote: > Noncached area at present is being initialized to random space after malloc > area. It works in most the cases as it goes to stack area & stack is not > overwriting it being far from it. > > Signed-off-by: Vikas Manocha Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] cmd: pci: Adjust display of digits for 64bit address and size
On Fri, Aug 23, 2019 at 10:56:55AM +0900, Kunihiko Hayashi wrote: > The command "pci bar" and "pci region" display the address and size in > 16 characters including "0x", so the command can only display > 14 hexadecimal digits if the number of digits in the address and size is > less than 14. > > ID BaseSizeWidth Type > -- > 0 0x002000 0x10 64 MEM Prefetchable > 1 0x8000 0x10 64 MEM Prefetchable > > The 64-bit address and size should be displayed in 18(= 16+2) digits, > so this patch adjusts them. > > Cc: Yehuda Yitschak > Cc: Simon Glass > Signed-off-by: Kunihiko Hayashi > Reviewed-by: Bin Meng Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] board: ti: am43xx_evm_usbboot: Enable DM for USB, fix SPL build errors
On Fri, Aug 23, 2019 at 02:06:34PM +0530, suni...@techveda.org wrote: > From: Suniel Mahesh > > To address the following warning message: > > = WARNING == > This board does not use CONFIG_DM_USB. Please update > the board to use CONFIG_DM_USB before the v2019.07 release. > Failure to update by the deadline may result in board removal. > See doc/driver-model/MIGRATION.txt for more info. > > > CONFIG_DM_USB is enabled, this resulted in SPL build errors: > > drivers/built-in.o: In function 'xhci_dwc3_probe': > u-boot/drivers/usb/host/xhci-dwc3.c:155: undefined reference to > 'usb_get_dr_mode' > scripts/Makefile.spl:404: recipe for target 'spl/u-boot-spl' failed > make[1]: *** [spl/u-boot-spl] Error 1 > Makefile:1721: recipe for target 'spl/u-boot-spl' failed > make: *** [spl/u-boot-spl] Error 2 > > Enabling usb common library and usb ethernet drivers in SPL > does the job. Target was compile tested, build was clean. > > Signed-off-by: Suniel Mahesh Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] ARM: vexpress_*_defconfig: replace earlyprintk with earlycon
On Wed, Aug 21, 2019 at 06:29:09PM +0100, Sudeep Holla wrote: > earlyprintk no longer works on arm64 platforms. Replace it with earlycon > which works fine. > > Cc: Ryan Harkin > Cc: Liviu Dudau > Cc: Linus Walleij > Signed-off-by: Sudeep Holla > Reviewed-by: Peng Fan > Reviewed-by: Ryan Harkin > Reviewed-by: Linus Walleij Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 1/1] tools: remove easylogo and include/video_logo.h
On Thu, Aug 22, 2019 at 12:32:42PM +0200, Heinrich Schuchardt wrote: > include/video_logo.h once was created via the tool easylogo and than used > in cpu/mpc8xx/video.c to display Tux. video_logo.h has been replaced by > include/linux_logo.h and is not needed anymore. > > Delete the include and the tool, > > Signed-off-by: Heinrich Schuchardt Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] Kconfig: Varios: Fix more SPL, TPL dependencies
On Sat, Aug 24, 2019 at 01:50:34PM -0500, Adam Ford wrote: > Several options are presenting themselves on a various boards > where the options are clearly not used. (ie, SPL/TPL options > when SPL or TPL are not defined) > > This patch is not attempting to be a complete list of items, but > more like low hanging fruit. In some instances, I wasn't sure > of DM was required, so I simply made them SPL or TPL. > > This patch attempts to reduce some of the menuconfig noise > by defining dependencies so they don't appear when not used. > > Signed-off-by: Adam Ford > > diff --git a/common/spl/Kconfig b/common/spl/Kconfig > index 660aa66d84..5b70f1e4ff 100644 Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] MAINTAINERS,board/siemens: update maintainer
On Fri, Aug 23, 2019 at 04:11:45PM +0200, Samuel Egli wrote: > Signed-off-by: Samuel Egli > Acked-by: Roger Meier > Cc: Heiko Schocher Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] vexpress/aemv8a: drop CONFIG_ARMV8_SWITCH_TO_EL1
On Wed, Aug 21, 2019 at 06:29:10PM +0100, Sudeep Holla wrote: > To support KVM, we need to drop at EL2 and not EL1 before we boot Linux > kernel. This causes issues on platform with VHE and secondaries booting > at EL2 via TF-A PSCI CPU_ON call. > > Cc: Ryan Harkin > Cc: Liviu Dudau > Cc: Linus Walleij > Cc: David Feng > Signed-off-by: Sudeep Holla > Reviewed-by: Peng Fan Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 1/1] dm: scsi: Scan the actual number of ports
On Tue, Aug 20, 2019 at 04:47:42PM +, Park, Aiden wrote: > The scsi_scan_dev() is looping over the number of uc_plat->max_id. > The number of actual ports a AHCI controller has can be greater than > max_id. Update uc_plat->max_id to make SCSI scan all detected ports. > > Signed-off-by: Aiden Park > Reviewed-by: Bin Meng Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 1/1] cmd: gpio: remove redundant assignment
On Thu, Aug 22, 2019 at 10:19:41PM +0200, Heinrich Schuchardt wrote: > The assigned value NULL is overwritten before being used. Remove the > assignment. > > Signed-off-by: Heinrich Schuchardt > Reviewed-by: Bin Meng Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] ARM: dts: logicpd-som-lv: Fix i2c2 and i2c3 Pin mux
On Tue, Aug 20, 2019 at 07:20:58AM -0500, Adam Ford wrote: > When the pinmux configuration was added, it was accidentally placed into > the omap3_pmx_wkup node when it should have been placed into the > omap3_pmx_core. This error was accidentally propagated to U-Boot by > me when I blindly copied the device tree from Linux. > > This patch moves the i2c2_pins and i2c3_pins to the correct node > which should eliminate i2c bus errors and timeouts due to the fact > the bootloader uses the save device tree that no longer properly > assigns these pins. > > Signed-off-by: Adam Ford > > diff --git a/arch/arm/dts/logicpd-som-lv.dtsi > b/arch/arm/dts/logicpd-som-lv.dtsi > index 5563ee54c9..b56524cc7f 100644 Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] Regression after "distro: not taint environment variables if possible"
On Wed, Jul 10, 2019 at 01:46:57PM +0200, Nuno Gonçalves wrote: > Hi, > > I found out that my Beaglebone didn't boot after: > > https://github.com/u-boot/u-boot/commit/13dd6665ed18f72380ca596931d609bc108d4b82 > > I digged out the reason that this patch makes devnum a local variable, > and it ends up shadowed by other code that sets devnum as a env > variable. > > For example to boot on the beaglebone I had to remove the setenv as in > the patch below. > > This only fixes for my board. Many other will likely have regressions. > > Fixing it for all boards in a reliable way I think is very complex, > unless the strategy is to wait for board maintainers to fix it as they > need it, but I wonder how many latent bugs this will create for corner > boot cases. > > Maybe this change is not worth it? > > Thanks, > Nuno I've checked other usages here and only the TI case looks to have been a problem. I reworded the commit message as well. Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] fat: FAT filesystem premature release of info struct.
On Tue, Aug 20, 2019 at 10:18:30PM +0200, Martin Vystrčil wrote: > File was found on specified location. Info about file was read, > but then immediately destroyed using 'free' call. As a result > file size was set to 0, hence fat process didn't read any data. > > Premature 'free' call removed. Resources are freed right before > function return. File is read correctly. > > Signed-off-by: Martin Vystrcil Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] Pull request: u-boot-riscv/master
On Mon, Aug 26, 2019 at 04:25:31PM +0800, ub...@andestech.com wrote: > Hi Tom, > > Please pull some riscv updates: > > - Support SPL and OpenSBI (FW_DYNAMIC firmware) boot. > - Fix qemu kconfig build warning. > > https://travis-ci.org/rickchen36/u-boot-riscv/builds/576608303 > > Thanks > Rick > > > The following changes since commit 50b4b80f597b9f59b98adbdbad691b1027bd501a: > > Merge tag 'u-boot-rockchip-20190823' of > https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip (2019-08-24 08:33:27 > -0400) > > are available in the Git repository at: > > g...@gitlab.denx.de:u-boot/custodians/u-boot-riscv.git > > for you to fetch changes up to 44016bc59870c8816fe2cd4721dc5ff11038dd98: > > riscv: qemu: Fix kconfig build warning (2019-08-26 16:09:02 +0800) > Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 2/2] configs: am65x_hs_evm: Use FIT images when booting HS devices
HS devices use the FIT post processing step to authenticate boot images.
Set the configured boot command to load FIT by default.
Signed-off-by: Andrew F. Davis
---
configs/am65x_hs_evm_a53_defconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/configs/am65x_hs_evm_a53_defconfig
b/configs/am65x_hs_evm_a53_defconfig
index 87547ed9ab..28c92f9106 100644
--- a/configs/am65x_hs_evm_a53_defconfig
+++ b/configs/am65x_hs_evm_a53_defconfig
@@ -19,7 +19,7 @@ CONFIG_FIT_IMAGE_POST_PROCESS=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y
CONFIG_OF_BOARD_SETUP=y
-CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run
get_kern_${boot}; run get_fdt_${boot}; run get_overlay_${boot}; run run_kern"
+CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run
get_fit_${boot}; run get_overlaystring; run run_fit"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL_TEXT_BASE=0x8008
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
--
2.17.1
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[U-Boot] [PATCH 1/2] configs: ti: Add environment support commands for FIT loading
Some parts of these commands can be reused, add them to common files.
Signed-off-by: Andrew F. Davis
---
include/configs/am65x_evm.h | 3 +++
include/configs/ti_armv7_common.h | 8 +++-
2 files changed, 10 insertions(+), 1 deletion(-)
diff --git a/include/configs/am65x_evm.h b/include/configs/am65x_evm.h
index 6072e4a48c..0249a20ba8 100644
--- a/include/configs/am65x_evm.h
+++ b/include/configs/am65x_evm.h
@@ -94,11 +94,14 @@
"done;\0" \
"get_kern_mmc=load mmc ${bootpart} ${loadaddr} "\
"${bootdir}/${name_kern}\0" \
+ "get_fit_mmc=load mmc ${bootpart} ${addr_fit} " \
+ "${bootdir}/${name_fit}\0" \
"partitions=" PARTS_DEFAULT
/* Incorporate settings into the U-Boot environment */
#define CONFIG_EXTRA_ENV_SETTINGS \
DEFAULT_MMC_TI_ARGS \
+ DEFAULT_FIT_TI_ARGS \
EXTRA_ENV_AM65X_BOARD_SETTINGS \
EXTRA_ENV_AM65X_BOARD_SETTINGS_MMC
diff --git a/include/configs/ti_armv7_common.h
b/include/configs/ti_armv7_common.h
index 2058f8de0f..2de6bc2390 100644
--- a/include/configs/ti_armv7_common.h
+++ b/include/configs/ti_armv7_common.h
@@ -55,7 +55,13 @@
"addr_fit=0x9000\0" \
"name_fit=fitImage\0" \
"update_to_fit=setenv loadaddr ${addr_fit}; setenv bootfile
${name_fit}\0" \
- "loadfit=run args_mmc; bootm ${loadaddr}#${fdtfile};\0" \
+ "get_overlaystring=" \
+ "for overlay in $overlay_files;" \
+ "do;" \
+ "setenv overlaystring ${overlaystring}'#'${overlay};" \
+ "done;\0" \
+ "run_fit=bootm ${loadaddr}#${fdtfile}${overlaystring}\0" \
+ "loadfit=run args_mmc; run run_fit;\0" \
/*
* DDR information. If the CONFIG_NR_DRAM_BANKS is not defined,
--
2.17.1
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Re: [U-Boot] SPL building unwanted code
On Thu, Aug 22, 2019 at 03:41:45PM -0500, Adam Ford wrote: > I have boards (omap3_logic and omap3_logic_somlv) which do not want > USB enabled for SPL yet SPL is showing USB chunks being compiled into > it. > > I had to create a patch [1] which disables the USB host controller > when in SPL, yet some of the framework is still present. There appears > to be an option in the SPL menu for enabling/disabling "Support USB > host drivers" and an option for "Support USB Gadget drivers" and for > me, neither are selected. What I'd like to do is kill off all the USB > code inside SPL to shrink the size. > > When I look at the Makefile for the USB host, there doesn't appear to > be any checks for whether or not we're in SPL. > > There also appears to be an inconsistency in where to place the > options for enabling something in SPL. In some cases, high-level > options are listed in SPL/TPL menu, but in other instances, the > options are listed under the "Device Drivers" menu. What I'd like to > do is add a menu option for CONFIG_SPL_USB which lets people turn off > all USB code when in SPL if they don't want any, then fix up the > Makefiles to use the SPL/TPL macros to determine if we need to build > or not. > > My question is is...Where should the menu item for enabling > CONFIG_SPL_USB be used, in the SPL/TPL menu or the USB menu? We're indeed not consistent enough here. Given how large common/spl/Kconfig is already today I suspect the right answer is that more things should be grouped closer to their non-SPL/TPL counterpart questions, with correct depends on lines. And options with names such that we can't use CONFIG_IS_ENABLED(FOO)/obj-$(CONFIG_$(SPL_TPL_)_FOO) need to be renamed as well. That should in turn lead to being able to correctly drop USB out of SPL for example. -- Tom signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v2 15/16] rockchip: rk3399: Add bootcount support
Add bootcount support for Rockchip rk3399. The bootcount value is preserved in PMU_SYS_REG0 register, this would help to support redundent boot. Once the redundant boot triggers, the altboot command will look for extlinux-rollback.conf on particular bootable partition which supposed to be a recovery partition where redundant boot required. Signed-off-by: Jagan Teki --- arch/arm/mach-rockchip/Kconfig| 2 ++ arch/arm/mach-rockchip/rk3399/Kconfig | 10 ++ include/configs/rk3399_common.h | 5 - 3 files changed, 16 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index f5a80b4f0c..f3e4d72203 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -197,6 +197,8 @@ config ROCKCHIP_RK3399 imply TPL_CLK imply TPL_TINY_MEMSET imply TPL_ROCKCHIP_COMMON_BOARD + imply SYS_BOOTCOUNT_SINGLEWORD if BOOTCOUNT_LIMIT + imply CMD_BOOTCOUNT if BOOTCOUNT_LIMIT help The Rockchip RK3399 is a ARM-based SoC with a dual-core Cortex-A72 and quad-core Cortex-A53. diff --git a/arch/arm/mach-rockchip/rk3399/Kconfig b/arch/arm/mach-rockchip/rk3399/Kconfig index 6660d05349..68ac913bcb 100644 --- a/arch/arm/mach-rockchip/rk3399/Kconfig +++ b/arch/arm/mach-rockchip/rk3399/Kconfig @@ -91,6 +91,16 @@ config TPL_STACK config TPL_TEXT_BASE default 0xff8c2000 +if BOOTCOUNT_LIMIT + +config BOOTCOUNT_BOOTLIMIT + default 3 + +config SYS_BOOTCOUNT_ADDR + default 0xff3100f0 # PMU_SYS_REG0 + +endif # BOOTCOUNT_LIMIT + source "board/rockchip/evb_rk3399/Kconfig" source "board/theobroma-systems/puma_rk3399/Kconfig" source "board/vamrs/rock960_rk3399/Kconfig" diff --git a/include/configs/rk3399_common.h b/include/configs/rk3399_common.h index a5e69b26ad..724ea4cbfc 100644 --- a/include/configs/rk3399_common.h +++ b/include/configs/rk3399_common.h @@ -64,7 +64,10 @@ "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ "partitions=" PARTS_DEFAULT \ ROCKCHIP_DEVICE_SETTINGS \ - BOOTENV + BOOTENV \ + "altbootcmd=" \ + "setenv boot_syslinux_conf extlinux/extlinux-rollback.conf;" \ + "run distro_bootcmd\0" #endif -- 2.18.0.321.gffc6fa0e3 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v2 13/16] watchdog: Handle TPL build with watchdog disabled
This patch handle a checks to not enable watchdog in TPL,
if TPL won't require to enable that.
This is useful, in rockchip platforms where watchdog would
require in SPL and U-Boot proper and optional to have it
in TPL. So, without this check, the TPL build failed to get
the watchdog_reset function even though the watchdog is not
enable for it.
Signed-off-by: Jagan Teki
---
include/watchdog.h | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/include/watchdog.h b/include/watchdog.h
index a4a4e8e614..f04e3e7c4d 100644
--- a/include/watchdog.h
+++ b/include/watchdog.h
@@ -51,9 +51,10 @@ int init_func_watchdog_reset(void);
#if defined(__ASSEMBLY__)
#define WATCHDOG_RESET bl watchdog_reset
#else
- /* Don't require the watchdog to be enabled in SPL */
- #if defined(CONFIG_SPL_BUILD) &&\
- !defined(CONFIG_SPL_WATCHDOG_SUPPORT)
+ /* Don't require the watchdog to be enabled in TPL/SPL
*/
+ #if ((defined(CONFIG_TPL_BUILD) ||
defined(CONFIG_TPL_BUILD)) && \
+ (!defined(CONFIG_TPL_WATCHDOG_SUPPORT) || \
+ !defined(CONFIG_SPL_WATCHDOG_SUPPORT)))
#define WATCHDOG_RESET() {}
#else
extern void watchdog_reset(void);
--
2.18.0.321.gffc6fa0e3
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[U-Boot] [PATCH v2 09/16] rockchip: dts: rk3399: Add u-boot, dm-pre-reloc for watchdog
Add u-boot,dm-pre-reloc property for watchdog in rk3399-u-boot.dtsi
so-that SPL can access watchdog.
Signed-off-by: Jagan Teki
---
arch/arm/dts/rk3399-u-boot.dtsi | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/dts/rk3399-u-boot.dtsi b/arch/arm/dts/rk3399-u-boot.dtsi
index 2738a3889e..54286b585b 100644
--- a/arch/arm/dts/rk3399-u-boot.dtsi
+++ b/arch/arm/dts/rk3399-u-boot.dtsi
@@ -3,6 +3,12 @@
* Copyright (C) 2019 Jagan Teki
*/
+/ {
+ watchdog@ff848000 {
+ u-boot,dm-pre-reloc;
+ };
+};
+
{
u-boot,dm-pre-reloc;
};
--
2.18.0.321.gffc6fa0e3
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[U-Boot] [PATCH v2 10/16] wdt: Kconfig: Add WDT_DW entry
Add Kconfig entry for CONFIG_WDT_DW, and it indeed depends on DM WDT. So, it can be avialable on particular board defconfig only if they switch to use DW driver model code. Signed-off-by: Jagan Teki --- drivers/watchdog/Kconfig | 8 scripts/config_whitelist.txt | 1 - 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index a66a9bcbe2..8674633b90 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -90,6 +90,14 @@ config WDT_CDNS Select this to enable Cadence watchdog timer, which can be found on some Xilinx Microzed Platform. +config WDT_DW + bool "Synopsys DesignWare watchdog" + depends on WDT + default y if ROCKCHIP_RK3399 + help + Say Y here if to include support for the Synopsys DesignWare + watchdog timer found in many chips. + config WDT_MPC8xx bool "MPC8xx watchdog timer support" depends on WDT && MPC8xx diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 35c56262ed..0618cb9047 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -321,7 +321,6 @@ CONFIG_DEFAULT_IMMR CONFIG_DEF_HWCONFIG CONFIG_DELAY_ENVIRONMENT CONFIG_DESIGNWARE_ETH -CONFIG_WDT_DW CONFIG_DEVELOP CONFIG_DEVICE_TREE_LIST CONFIG_DFU_ALT -- 2.18.0.321.gffc6fa0e3 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v2 11/16] wdt: Kconfig: Add TPL_WDT entry
Add missing Kconfig entry for TPL_WDT. Signed-off-by: Jagan Teki --- drivers/watchdog/Kconfig | 7 +++ 1 file changed, 7 insertions(+) diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index 8674633b90..7c7f0c67a0 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -182,4 +182,11 @@ config SPL_WDT Enable driver model for watchdog timer in SPL. This is similar to CONFIG_WDT in U-Boot. +config TPL_WDT + bool "Enable driver model for watchdog timer drivers in TPL" + depends on TPL_DM + help + Enable driver model for watchdog timer in TPL. + This is similar to CONFIG_WDT in U-Boot. + endmenu -- 2.18.0.321.gffc6fa0e3 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [DO NOT MERGE] [PATCH v2 14/16] rk3399: rockpro64: Enable watchdog
Enable watchdog in SPL and U-Boot proper for Rockpro64. Signed-off-by: Jagan Teki --- configs/rockpro64-rk3399_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/configs/rockpro64-rk3399_defconfig b/configs/rockpro64-rk3399_defconfig index e05ea3e186..5ff38efa53 100644 --- a/configs/rockpro64-rk3399_defconfig +++ b/configs/rockpro64-rk3399_defconfig @@ -55,3 +55,5 @@ CONFIG_USB_ETHER_RTL8152=y CONFIG_USB_ETHER_SMSC95XX=y CONFIG_SPL_TINY_MEMSET=y CONFIG_ERRNO_STR=y +CONFIG_WDT=y +CONFIG_SPL_WATCHDOG_SUPPORT=y -- 2.18.0.321.gffc6fa0e3 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v2 12/16] spl: Add watchdog support fot TPL
Add support to build watchdog for TPL. Signed-off-by: Jagan Teki --- common/spl/Kconfig | 9 + drivers/Makefile | 2 +- 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/common/spl/Kconfig b/common/spl/Kconfig index 660aa66d84..d4c5956b18 100644 --- a/common/spl/Kconfig +++ b/common/spl/Kconfig @@ -1370,6 +1370,15 @@ config TPL_YMODEM_SUPPORT means of transmitting U-Boot over a serial line for using in TPL, with a checksum to ensure correctness. +config TPL_WATCHDOG_SUPPORT + bool "Support watchdog drivers" + imply TPL_WDT if !HW_WATCHDOG + help + Enable support for watchdog drivers in TPL. A watchdog is + typically a hardware peripheral which can reset the system when it + detects no activity for a while (such as a software crash). This + enables the drivers in drivers/watchdog as part of an TPL build. + endif # TPL config SPL_AT91_MCK_BYPASS diff --git a/drivers/Makefile b/drivers/Makefile index a4bb5e4975..82f9ac4445 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -23,6 +23,7 @@ obj-$(CONFIG_$(SPL_TPL_)SPI_FLASH_SUPPORT) += mtd/spi/ obj-$(CONFIG_$(SPL_TPL_)SPI_SUPPORT) += spi/ obj-$(CONFIG_$(SPL_TPL_)TIMER) += timer/ obj-$(CONFIG_$(SPL_TPL_)VIRTIO) += virtio/ +obj-$(CONFIG_$(SPL_TPL_)WATCHDOG_SUPPORT) += watchdog/ obj-$(CONFIG_$(SPL_)DM_MAILBOX) += mailbox/ obj-$(CONFIG_$(SPL_)REMOTEPROC) += remoteproc/ obj-$(CONFIG_$(SPL_TPL_)TPM) += tpm/ @@ -53,7 +54,6 @@ obj-$(CONFIG_SPL_MUSB_NEW_SUPPORT) += usb/musb-new/ obj-$(CONFIG_SPL_USB_GADGET) += usb/gadget/ obj-$(CONFIG_SPL_USB_GADGET) += usb/common/ obj-$(CONFIG_SPL_USB_GADGET) += usb/gadget/udc/ -obj-$(CONFIG_SPL_WATCHDOG_SUPPORT) += watchdog/ obj-$(CONFIG_SPL_USB_HOST_SUPPORT) += usb/host/ obj-$(CONFIG_OMAP_USB_PHY) += usb/phy/ obj-$(CONFIG_SPL_SATA_SUPPORT) += ata/ scsi/ -- 2.18.0.321.gffc6fa0e3 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [DO NOT MERGE] [PATCH v2 16/16] rk3399: rockpro64: Enable bootcount
Enable bootcount support for Rockpro64 boards, this would help to use it for redundent boot. Signed-off-by: Jagan Teki --- configs/rockpro64-rk3399_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/rockpro64-rk3399_defconfig b/configs/rockpro64-rk3399_defconfig index 5ff38efa53..84d050d743 100644 --- a/configs/rockpro64-rk3399_defconfig +++ b/configs/rockpro64-rk3399_defconfig @@ -57,3 +57,4 @@ CONFIG_SPL_TINY_MEMSET=y CONFIG_ERRNO_STR=y CONFIG_WDT=y CONFIG_SPL_WATCHDOG_SUPPORT=y +CONFIG_BOOTCOUNT_LIMIT=y -- 2.18.0.321.gffc6fa0e3 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v2 07/16] wdt: dw: Add driver-model support
Add driver-model code for designware watchdog.
Cc: Chin Liang See
Cc: Andy Shevchenko
Signed-off-by: Jagan Teki
---
drivers/watchdog/designware_wdt.c | 118 +-
1 file changed, 117 insertions(+), 1 deletion(-)
diff --git a/drivers/watchdog/designware_wdt.c
b/drivers/watchdog/designware_wdt.c
index 2979fda44e..c822b1e36b 100644
--- a/drivers/watchdog/designware_wdt.c
+++ b/drivers/watchdog/designware_wdt.c
@@ -4,7 +4,6 @@
*/
#include
-#include
#include
#include
@@ -16,6 +15,121 @@
#define DW_WDT_CR_RMOD_OFFSET 0x01
#define DW_WDT_CRR_RESTART_VAL 0x76
+#define DW_WDT_MIN_TOP 0
+#define DW_WDT_MAX_TOP 15
+#define DW_WDT_TOPINIT_SHIFT 4
+
+#ifdef CONFIG_WDT
+
+#include
+#include
+#include
+
+struct dw_wdt {
+ void __iomem *regs;
+ unsigned long clk_rate;
+};
+
+static inline int dw_wdt_is_enabled(struct dw_wdt *dw)
+{
+ return readl(dw->regs + DW_WDT_CR) & DW_WDT_CR_RMOD_OFFSET;
+}
+
+/*
+ * Set the watchdog time interval.
+ * Counter is 32 bit.
+ */
+static int dw_wdt_set_timeout(struct dw_wdt *dw, unsigned int timeout)
+{
+ int i, top_val;
+
+ /* calculate the timeout range value */
+ i = log_2_n_round_up(timeout * dw->clk_rate) - 16;
+ top_val = clamp_t(int, i, DW_WDT_MIN_TOP, DW_WDT_MAX_TOP);
+
+ writel((top_val | (top_val << DW_WDT_TOPINIT_SHIFT)),
+ dw->regs + DW_WDT_TORR);
+
+ return 0;
+}
+
+static void dw_wdt_enable(struct dw_wdt *dw)
+{
+ u32 val = readl(dw->regs + DW_WDT_CR);
+
+ /* Enable watchdog */
+ val |= DW_WDT_CR_RMOD_OFFSET;
+ writel(val, dw->regs + DW_WDT_CR);
+}
+
+static int dw_wdt_reset(struct udevice *dev)
+{
+ struct dw_wdt *dw = dev_get_priv(dev);
+
+ if (dw_wdt_is_enabled(dw))
+ writel(DW_WDT_CRR_RESTART_VAL, dw->regs + DW_WDT_CRR);
+ else
+ dw_wdt_enable(dw);
+
+ return 0;
+}
+
+static int dw_wdt_start(struct udevice *dev, u64 timeout, ulong flags)
+{
+ struct dw_wdt *dw = dev_get_priv(dev);
+
+ dw_wdt_set_timeout(dw, timeout);
+ dw_wdt_enable(dw);
+
+ return 0;
+}
+
+static int dw_wdt_probe(struct udevice *dev)
+{
+ struct dw_wdt *dw = dev_get_priv(dev);
+ struct clk clk;
+ int ret;
+
+ dw->regs = dev_remap_addr(dev);
+ if (!dw->regs)
+ return -EINVAL;
+
+ ret = clk_get_by_index(dev, 0, );
+ if (ret)
+ return ret;
+
+ dw->clk_rate = clk_get_rate();
+ if (!dw->clk_rate)
+ return -EINVAL;
+
+ dw_wdt_reset(dev);
+
+ return 0;
+}
+
+static const struct wdt_ops dw_wdt_ops = {
+ .reset = dw_wdt_reset,
+ .start = dw_wdt_start,
+};
+
+static const struct udevice_id dw_wdt_ids[] = {
+ { .compatible = "snps,dw-wdt" },
+ { /* sentinel */ }
+};
+
+U_BOOT_DRIVER(dw_wdt) = {
+ .name = "dw_wdt",
+ .id = UCLASS_WDT,
+ .of_match = dw_wdt_ids,
+ .ops = _wdt_ops,
+ .priv_auto_alloc_size = sizeof(struct dw_wdt),
+ .probe = dw_wdt_probe,
+};
+
+#else
+
+#include
+
/*
* Set the watchdog time interval.
* Counter is 32 bit.
@@ -70,3 +184,5 @@ void hw_watchdog_init(void)
hw_watchdog_reset();
}
#endif
+
+#endif /* CONFIG_WDT */
--
2.18.0.321.gffc6fa0e3
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[U-Boot] [PATCH v2 04/16] rockchip: Add rk3399 reset cause
Add reset cause for rk3399 in common cpu-info file.
This would help to print the reset cause for
various resets.
Common code for various rockchip reset cause
will add it in future.
Signed-off-by: Jagan Teki
---
arch/arm/include/asm/arch-rockchip/cru.h | 12 +++
arch/arm/mach-rockchip/cpu-info.c| 43
2 files changed, 55 insertions(+)
diff --git a/arch/arm/include/asm/arch-rockchip/cru.h
b/arch/arm/include/asm/arch-rockchip/cru.h
index 3d1927580f..e267a71ca6 100644
--- a/arch/arm/include/asm/arch-rockchip/cru.h
+++ b/arch/arm/include/asm/arch-rockchip/cru.h
@@ -11,4 +11,16 @@
# include
#endif
+/* CRU_GLB_RST_ST */
+enum {
+ GLB_POR_RST,
+ FST_GLB_RST_ST = BIT(0),
+ SND_GLB_RST_ST = BIT(1),
+ FST_GLB_TSADC_RST_ST= BIT(2),
+ SND_GLB_TSADC_RST_ST= BIT(3),
+ FST_GLB_WDT_RST_ST = BIT(4),
+ SND_GLB_WDT_RST_ST = BIT(5),
+ GLB_RST_ST_MASK = GENMASK(5, 0),
+};
+
#endif /* _ROCKCHIP_CLOCK_H */
diff --git a/arch/arm/mach-rockchip/cpu-info.c
b/arch/arm/mach-rockchip/cpu-info.c
index 90ce65d9ff..63d867fe78 100644
--- a/arch/arm/mach-rockchip/cpu-info.c
+++ b/arch/arm/mach-rockchip/cpu-info.c
@@ -5,10 +5,53 @@
*/
#include
+#include
+#include
+#include
+#include
+#include
+
+static char *get_reset_cause(void)
+{
+ struct rockchip_cru *cru = rockchip_get_cru();
+ char *cause = NULL;
+
+ if (IS_ERR(cru))
+ return cause;
+
+ switch (cru->glb_rst_st) {
+ case GLB_POR_RST:
+ cause = "POR";
+ break;
+ case FST_GLB_RST_ST:
+ case SND_GLB_RST_ST:
+ cause = "RST";
+ break;
+ case FST_GLB_TSADC_RST_ST:
+ case SND_GLB_TSADC_RST_ST:
+ cause = "THERMAL";
+ break;
+ case FST_GLB_WDT_RST_ST:
+ case SND_GLB_WDT_RST_ST:
+ cause = "WDOG";
+ break;
+ default:
+ cause = "unknown reset";
+ }
+
+ /*
+* Clear glb_rst_st, so we can determine the last reset cause
+* for following resets.
+*/
+ rk_clrreg(>glb_rst_st, GLB_RST_ST_MASK);
+
+ return cause;
+}
int print_cpuinfo(void)
{
printf("SoC: Rockchip %s\n", CONFIG_SYS_SOC);
+ printf("Reset cause: %s\n", get_reset_cause());
/* TODO print operating temparature and clock */
--
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[U-Boot] [PATCH v2 02/16] rockchip: rk3288/rk3399: Enable DISPLAY_CPUINFO
RK3288 and RK3399 are now support cpu-info, so enable them by default. Signed-off-by: Jagan Teki --- configs/evb-rk3288_defconfig | 1 - configs/evb-rk3399_defconfig | 1 - configs/ficus-rk3399_defconfig | 1 - configs/firefly-rk3288_defconfig | 1 - configs/firefly-rk3399_defconfig | 1 - configs/khadas-edge-captain-rk3399_defconfig | 1 - configs/khadas-edge-rk3399_defconfig | 1 - configs/khadas-edge-v-rk3399_defconfig | 1 - configs/miqi-rk3288_defconfig| 1 - configs/nanopc-t4-rk3399_defconfig | 1 - configs/nanopi-m4-rk3399_defconfig | 1 - configs/nanopi-neo4-rk3399_defconfig | 1 - configs/orangepi-rk3399_defconfig| 1 - configs/phycore-rk3288_defconfig | 1 - configs/popmetal-rk3288_defconfig| 1 - configs/puma-rk3399_defconfig| 1 - configs/rock-pi-4-rk3399_defconfig | 1 - configs/rock960-rk3399_defconfig | 1 - configs/rockpro64-rk3399_defconfig | 1 - configs/tinker-rk3288_defconfig | 1 - configs/vyasa-rk3288_defconfig | 1 - 21 files changed, 21 deletions(-) diff --git a/configs/evb-rk3288_defconfig b/configs/evb-rk3288_defconfig index 405fde0c80..68791cb417 100644 --- a/configs/evb-rk3288_defconfig +++ b/configs/evb-rk3288_defconfig @@ -12,7 +12,6 @@ CONFIG_DEBUG_UART=y CONFIG_USE_PREBOOT=y CONFIG_SILENT_CONSOLE=y CONFIG_DEFAULT_FDT_FILE="rk3288-evb-rk808.dtb" -# CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_TEXT_BASE=0 CONFIG_CMD_GPIO=y diff --git a/configs/evb-rk3399_defconfig b/configs/evb-rk3399_defconfig index a0d215a5f1..2dae9e86b7 100644 --- a/configs/evb-rk3399_defconfig +++ b/configs/evb-rk3399_defconfig @@ -9,7 +9,6 @@ CONFIG_DEBUG_UART_BASE=0xFF1A CONFIG_DEBUG_UART_CLOCK=2400 CONFIG_DEBUG_UART=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-evb.dtb" -# CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_STACK_R=y diff --git a/configs/ficus-rk3399_defconfig b/configs/ficus-rk3399_defconfig index 8b3692cdf0..4d05e0eb31 100644 --- a/configs/ficus-rk3399_defconfig +++ b/configs/ficus-rk3399_defconfig @@ -8,7 +8,6 @@ CONFIG_SPL_STACK_R_ADDR=0x8 CONFIG_DEBUG_UART_BASE=0xFF1A CONFIG_DEBUG_UART_CLOCK=2400 CONFIG_DEBUG_UART=y -# CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_TEXT_BASE=0xff8c2000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set diff --git a/configs/firefly-rk3288_defconfig b/configs/firefly-rk3288_defconfig index 7ca522b479..1ebaf0dd72 100644 --- a/configs/firefly-rk3288_defconfig +++ b/configs/firefly-rk3288_defconfig @@ -13,7 +13,6 @@ CONFIG_DEBUG_UART=y CONFIG_USE_PREBOOT=y CONFIG_SILENT_CONSOLE=y CONFIG_DEFAULT_FDT_FILE="rk3288-firefly.dtb" -# CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_TEXT_BASE=0xff704000 CONFIG_SPL_STACK_R=y diff --git a/configs/firefly-rk3399_defconfig b/configs/firefly-rk3399_defconfig index d022631465..6b5a43219e 100644 --- a/configs/firefly-rk3399_defconfig +++ b/configs/firefly-rk3399_defconfig @@ -9,7 +9,6 @@ CONFIG_DEBUG_UART_BASE=0xFF1A CONFIG_DEBUG_UART_CLOCK=2400 CONFIG_DEBUG_UART=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-firefly.dtb" -# CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_STACK_R=y diff --git a/configs/khadas-edge-captain-rk3399_defconfig b/configs/khadas-edge-captain-rk3399_defconfig index acfd91dbe7..b2bdc7c032 100644 --- a/configs/khadas-edge-captain-rk3399_defconfig +++ b/configs/khadas-edge-captain-rk3399_defconfig @@ -9,7 +9,6 @@ CONFIG_DEBUG_UART_BASE=0xFF1A CONFIG_DEBUG_UART_CLOCK=2400 CONFIG_DEBUG_UART=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-khadas-edge-captain.dtbi" -# CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_STACK_R=y diff --git a/configs/khadas-edge-rk3399_defconfig b/configs/khadas-edge-rk3399_defconfig index b71fd3a286..c3e3933d12 100644 --- a/configs/khadas-edge-rk3399_defconfig +++ b/configs/khadas-edge-rk3399_defconfig @@ -9,7 +9,6 @@ CONFIG_DEBUG_UART_BASE=0xFF1A CONFIG_DEBUG_UART_CLOCK=2400 CONFIG_DEBUG_UART=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-khadas-edge.dtb" -# CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_STACK_R=y diff --git a/configs/khadas-edge-v-rk3399_defconfig b/configs/khadas-edge-v-rk3399_defconfig index 0a789872dc..394c60f076 100644 --- a/configs/khadas-edge-v-rk3399_defconfig +++ b/configs/khadas-edge-v-rk3399_defconfig @@ -9,7 +9,6 @@ CONFIG_DEBUG_UART_BASE=0xFF1A CONFIG_DEBUG_UART_CLOCK=2400 CONFIG_DEBUG_UART=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-khadas-edge-v.dtbi" -#
[U-Boot] [PATCH v2 08/16] wdt: dw: Rename to dw_wdt.c
- use dw instead of designware for driver file since
Linux following the same.
- add CONFIG macro start with CONFIG_WDT since the
driver mode wdt drivers follow this.
Cc: Dinh Nguyen
Cc: Chin-Liang See
Signed-off-by: Jagan Teki
---
common/board_f.c| 2 +-
drivers/watchdog/Makefile | 2 +-
drivers/watchdog/{designware_wdt.c => dw_wdt.c} | 0
include/configs/socfpga_common.h| 2 +-
include/configs/socfpga_stratix10_socdk.h | 2 +-
scripts/config_whitelist.txt| 2 +-
6 files changed, 5 insertions(+), 5 deletions(-)
rename drivers/watchdog/{designware_wdt.c => dw_wdt.c} (100%)
diff --git a/common/board_f.c b/common/board_f.c
index 31181a9dc4..33e69c645a 100644
--- a/common/board_f.c
+++ b/common/board_f.c
@@ -97,7 +97,7 @@ static int init_func_watchdog_init(void)
# if defined(CONFIG_HW_WATCHDOG) && \
(defined(CONFIG_M68K) || defined(CONFIG_MICROBLAZE) || \
defined(CONFIG_SH) || \
- defined(CONFIG_DESIGNWARE_WATCHDOG) || \
+ defined(CONFIG_WDT_DW) || \
defined(CONFIG_IMX_WATCHDOG))
hw_watchdog_init();
puts(" Watchdog enabled\n");
diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile
index 955caef815..ecdc1ce54f 100644
--- a/drivers/watchdog/Makefile
+++ b/drivers/watchdog/Makefile
@@ -13,7 +13,6 @@ endif
obj-$(CONFIG_S5P) += s5p_wdt.o
obj-$(CONFIG_XILINX_TB_WATCHDOG) += xilinx_tb_wdt.o
obj-$(CONFIG_OMAP_WATCHDOG) += omap_wdt.o
-obj-$(CONFIG_DESIGNWARE_WATCHDOG) += designware_wdt.o
obj-$(CONFIG_ULP_WATCHDOG) += ulp_wdog.o
obj-$(CONFIG_$(SPL_TPL_)WDT) += wdt-uclass.o
obj-$(CONFIG_WDT_SANDBOX) += sandbox_wdt.o
@@ -22,6 +21,7 @@ obj-$(CONFIG_WDT_ASPEED) += ast_wdt.o
obj-$(CONFIG_WDT_BCM6345) += bcm6345_wdt.o
obj-$(CONFIG_WDT_ORION) += orion_wdt.o
obj-$(CONFIG_WDT_CDNS) += cdns_wdt.o
+obj-$(CONFIG_WDT_DW) += dw_wdt.o
obj-$(CONFIG_WDT_MPC8xx) += mpc8xx_wdt.o
obj-$(CONFIG_WDT_MT7621) += mt7621_wdt.o
obj-$(CONFIG_WDT_MTK) += mtk_wdt.o
diff --git a/drivers/watchdog/designware_wdt.c b/drivers/watchdog/dw_wdt.c
similarity index 100%
rename from drivers/watchdog/designware_wdt.c
rename to drivers/watchdog/dw_wdt.c
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index 36b0ed5459..902909216d 100644
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -105,7 +105,7 @@
* L4 Watchdog
*/
#ifdef CONFIG_HW_WATCHDOG
-#define CONFIG_DESIGNWARE_WATCHDOG
+#define CONFIG_WDT_DW
#define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS
#define CONFIG_DW_WDT_CLOCK_KHZ25000
#define CONFIG_WATCHDOG_TIMEOUT_MSECS 3
diff --git a/include/configs/socfpga_stratix10_socdk.h
b/include/configs/socfpga_stratix10_socdk.h
index 90ad8172e2..5d03bfd061 100644
--- a/include/configs/socfpga_stratix10_socdk.h
+++ b/include/configs/socfpga_stratix10_socdk.h
@@ -162,7 +162,7 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
*/
#ifdef CONFIG_SPL_BUILD
#define CONFIG_HW_WATCHDOG
-#define CONFIG_DESIGNWARE_WATCHDOG
+#define CONFIG_WDT_DW
#define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS
#ifndef __ASSEMBLY__
unsigned int cm_get_l4_sys_free_clk_hz(void);
diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
index 661c8b6427..35c56262ed 100644
--- a/scripts/config_whitelist.txt
+++ b/scripts/config_whitelist.txt
@@ -321,7 +321,7 @@ CONFIG_DEFAULT_IMMR
CONFIG_DEF_HWCONFIG
CONFIG_DELAY_ENVIRONMENT
CONFIG_DESIGNWARE_ETH
-CONFIG_DESIGNWARE_WATCHDOG
+CONFIG_WDT_DW
CONFIG_DEVELOP
CONFIG_DEVICE_TREE_LIST
CONFIG_DFU_ALT
--
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[U-Boot] [PATCH v2 03/16] arm: rockchip: Add common cru.h
Few of the rockchip family SoC atleast rk3288,
rk3399 are sharing some cru register bits so
adding common code between these SoC families
would require to include both cru include files
that indeed resulting function declarations error.
So, create a common cru include as cru.h then
include the rk3399 arch cru include file and move
the common cru register bit definitions into it.
The rest of rockchip cru files will add it in future.
Signed-off-by: Jagan Teki
---
arch/arm/include/asm/arch-rockchip/cru.h | 14
.../include/asm/arch-rockchip/cru_rk3399.h| 10 +++---
arch/arm/mach-rockchip/rk3399/clk_rk3399.c| 2 +-
arch/arm/mach-rockchip/rk3399/rk3399.c| 2 +-
drivers/clk/rockchip/clk_rk3399.c | 36 +--
drivers/ram/rockchip/sdram_rk3399.c | 10 +++---
drivers/video/rockchip/rk3399_mipi.c | 2 +-
drivers/video/rockchip/rk_mipi.c | 2 +-
8 files changed, 46 insertions(+), 32 deletions(-)
create mode 100644 arch/arm/include/asm/arch-rockchip/cru.h
diff --git a/arch/arm/include/asm/arch-rockchip/cru.h
b/arch/arm/include/asm/arch-rockchip/cru.h
new file mode 100644
index 00..3d1927580f
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/cru.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * (C) Copyright 2019 Amarula Solutions.
+ * Author: Jagan Teki
+ */
+
+#ifndef _ROCKCHIP_CLOCK_H
+#define _ROCKCHIP_CLOCK_H
+
+#if defined(CONFIG_ROCKCHIP_RK3399)
+# include
+#endif
+
+#endif /* _ROCKCHIP_CLOCK_H */
diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3399.h
b/arch/arm/include/asm/arch-rockchip/cru_rk3399.h
index 15eeb9c440..33ce190434 100644
--- a/arch/arm/include/asm/arch-rockchip/cru_rk3399.h
+++ b/arch/arm/include/asm/arch-rockchip/cru_rk3399.h
@@ -10,7 +10,7 @@
/* Private data for the clock driver - used by rockchip_get_cru() */
struct rk3399_clk_priv {
- struct rk3399_cru *cru;
+ struct rockchip_cru *cru;
};
struct rk3399_pmuclk_priv {
@@ -33,7 +33,7 @@ struct rk3399_pmucru {
};
check_member(rk3399_pmucru, pmucru_gatedis_con[1], 0x134);
-struct rk3399_cru {
+struct rockchip_cru {
u32 apll_l_con[6];
u32 reserved[2];
u32 apll_b_con[6];
@@ -65,7 +65,7 @@ struct rk3399_cru {
u32 sdio0_con[2];
u32 sdio1_con[2];
};
-check_member(rk3399_cru, sdio1_con[1], 0x594);
+check_member(rockchip_cru, sdio1_con[1], 0x594);
#define MHz100
#define KHz1000
#define OSC_HZ (24*MHz)
@@ -107,9 +107,9 @@ enum apll_b_frequencies {
APLL_B_600_MHZ,
};
-void rk3399_configure_cpu_l(struct rk3399_cru *cru,
+void rk3399_configure_cpu_l(struct rockchip_cru *cru,
enum apll_l_frequencies apll_l_freq);
-void rk3399_configure_cpu_b(struct rk3399_cru *cru,
+void rk3399_configure_cpu_b(struct rockchip_cru *cru,
enum apll_b_frequencies apll_b_freq);
#endif /* __ASM_ARCH_CRU_RK3399_H_ */
diff --git a/arch/arm/mach-rockchip/rk3399/clk_rk3399.c
b/arch/arm/mach-rockchip/rk3399/clk_rk3399.c
index f0411c0a21..a80a46f1db 100644
--- a/arch/arm/mach-rockchip/rk3399/clk_rk3399.c
+++ b/arch/arm/mach-rockchip/rk3399/clk_rk3399.c
@@ -8,7 +8,7 @@
#include
#include
#include
-#include
+#include
static int rockchip_get_cruclk(struct udevice **devp)
{
diff --git a/arch/arm/mach-rockchip/rk3399/rk3399.c
b/arch/arm/mach-rockchip/rk3399/rk3399.c
index 863024d071..dafa142824 100644
--- a/arch/arm/mach-rockchip/rk3399/rk3399.c
+++ b/arch/arm/mach-rockchip/rk3399/rk3399.c
@@ -240,7 +240,7 @@ static void rk3399_force_power_on_reset(void)
void spl_board_init(void)
{
#if defined(SPL_GPIO_SUPPORT)
- struct rk3399_cru *cru = rockchip_get_cru();
+ struct rockchip_cru *cru = rockchip_get_cru();
/*
* The RK3399 resets only 'almost all logic' (see also in the TRM
diff --git a/drivers/clk/rockchip/clk_rk3399.c
b/drivers/clk/rockchip/clk_rk3399.c
index d9950c159b..b79935c774 100644
--- a/drivers/clk/rockchip/clk_rk3399.c
+++ b/drivers/clk/rockchip/clk_rk3399.c
@@ -14,7 +14,7 @@
#include
#include
#include
-#include
+#include
#include
#include
#include
@@ -418,7 +418,7 @@ static int pll_para_config(u32 freq_hz, struct pll_div *div)
return 0;
}
-void rk3399_configure_cpu_l(struct rk3399_cru *cru,
+void rk3399_configure_cpu_l(struct rockchip_cru *cru,
enum apll_l_frequencies apll_l_freq)
{
u32 aclkm_div;
@@ -453,7 +453,7 @@ void rk3399_configure_cpu_l(struct rk3399_cru *cru,
atclk_div << ATCLK_CORE_L_DIV_SHIFT);
}
-void rk3399_configure_cpu_b(struct rk3399_cru *cru,
+void rk3399_configure_cpu_b(struct rockchip_cru *cru,
enum apll_b_frequencies apll_b_freq)
{
u32 aclkm_div;
@@ -505,7 +505,7 @@ void rk3399_configure_cpu_b(struct rk3399_cru *cru,
#define I2C_PMUCLK_REG_VALUE(bus, clk_div) \
((clk_div
[U-Boot] [PATCH v2 01/16] rockchip: Add cpu-info
Add cpu information for rockchip soc.
This would help to print the SoC family number, with
associated temparature, clock and reason for reset etc.
Signed-off-by: Jagan Teki
---
arch/arm/mach-rockchip/Makefile | 1 +
arch/arm/mach-rockchip/cpu-info.c | 16
2 files changed, 17 insertions(+)
create mode 100644 arch/arm/mach-rockchip/cpu-info.c
diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile
index 207f900011..76fc4942ee 100644
--- a/arch/arm/mach-rockchip/Makefile
+++ b/arch/arm/mach-rockchip/Makefile
@@ -20,6 +20,7 @@ ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TPL_BUILD),)
# we can have the preprocessor correctly recognise both 0x0 and 0
# meaning "turn it off".
obj-y += boot_mode.o
+obj-$(CONFIG_DISPLAY_CPUINFO) += cpu-info.o
obj-$(CONFIG_ROCKCHIP_COMMON_BOARD) += board.o
endif
diff --git a/arch/arm/mach-rockchip/cpu-info.c
b/arch/arm/mach-rockchip/cpu-info.c
new file mode 100644
index 00..90ce65d9ff
--- /dev/null
+++ b/arch/arm/mach-rockchip/cpu-info.c
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * (C) Copyright 2019 Amarula Solutions.
+ * Author: Jagan Teki
+ */
+
+#include
+
+int print_cpuinfo(void)
+{
+ printf("SoC: Rockchip %s\n", CONFIG_SYS_SOC);
+
+ /* TODO print operating temparature and clock */
+
+ return 0;
+}
--
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[U-Boot] [PATCH v2 06/16] wdt: designware: Simplify enable function
Simplify dw watchdog enable function by using
proper macro and drop unwanted macros.
Cc: Chin Liang See
Cc: Andy Shevchenko
Signed-off-by: Jagan Teki
---
drivers/watchdog/designware_wdt.c | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/drivers/watchdog/designware_wdt.c
b/drivers/watchdog/designware_wdt.c
index bd858f0608..2979fda44e 100644
--- a/drivers/watchdog/designware_wdt.c
+++ b/drivers/watchdog/designware_wdt.c
@@ -14,7 +14,6 @@
#define DW_WDT_CR_EN_OFFSET0x00
#define DW_WDT_CR_RMOD_OFFSET 0x01
-#define DW_WDT_CR_RMOD_VAL 0x00
#define DW_WDT_CRR_RESTART_VAL 0x76
/*
@@ -38,9 +37,11 @@ static int designware_wdt_settimeout(unsigned int timeout)
static void designware_wdt_enable(void)
{
- writel(((DW_WDT_CR_RMOD_VAL << DW_WDT_CR_RMOD_OFFSET) |
- (0x1 << DW_WDT_CR_EN_OFFSET)),
- (CONFIG_DW_WDT_BASE + DW_WDT_CR));
+ u32 val = readl(CONFIG_DW_WDT_BASE + DW_WDT_CR);
+
+ /* Enable watchdog */
+ val |= DW_WDT_CR_RMOD_OFFSET;
+ writel(val, CONFIG_DW_WDT_BASE + DW_WDT_CR);
}
static unsigned int designware_wdt_is_enabled(void)
--
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[U-Boot] [PATCH v2 00/16] rk3399: Add redundant boot support
Boot redundancy is one of the key criteria for switch recovery or golden partition based on the bootcount value, which indeed very much needed in production systems on the fields. This patchset support redundant boot on Rockchip rk3399. To make full functional redundancy below features would require from U-Boot level. - bootcount, for counting number reboots - altboot - watchdog support, if SPL or U-Boot reset because of WDT - add CPUINFO for more understanding about how SoC and reset reason. Changes for v2: - Handle TPL build for watchdog, if TPL won't enable - Fix comments for dw_wdt driver-model comments from Andy - Add Kconfig items for WDT_TPL - Support WDT on TPL as well - Use SYS_SOC for cpu-info I would like, not to merge watchdog and bootcount on Mainline devboards since these features will mostly required on production devices but any comments, please share. Any inputs? Jagan. Jagan Teki (16): rockchip: Add cpu-info rockchip: rk3288/rk3399: Enable DISPLAY_CPUINFO arm: rockchip: Add common cru.h rockchip: Add rk3399 reset cause wdt: designware: Simplify is_enabled function wdt: designware: Simplify enable function wdt: dw: Add driver-model support wdt: dw: Rename to dw_wdt.c rockchip: dts: rk3399: Add u-boot, dm-pre-reloc for watchdog wdt: Kconfig: Add WDT_DW entry wdt: Kconfig: Add TPL_WDT entry spl: Add watchdog support fot TPL watchdog: Handle TPL build with watchdog disabled [DO NOT MERGE] rk3399: rockpro64: Enable watchdog rockchip: rk3399: Add bootcount support [DO NOT MERGE] rk3399: rockpro64: Enable bootcount arch/arm/dts/rk3399-u-boot.dtsi | 6 + arch/arm/include/asm/arch-rockchip/cru.h | 26 +++ .../include/asm/arch-rockchip/cru_rk3399.h| 10 +- arch/arm/mach-rockchip/Kconfig| 2 + arch/arm/mach-rockchip/Makefile | 1 + arch/arm/mach-rockchip/cpu-info.c | 59 ++ arch/arm/mach-rockchip/rk3399/Kconfig | 10 + arch/arm/mach-rockchip/rk3399/clk_rk3399.c| 2 +- arch/arm/mach-rockchip/rk3399/rk3399.c| 2 +- common/board_f.c | 2 +- common/spl/Kconfig| 9 + configs/evb-rk3288_defconfig | 1 - configs/evb-rk3399_defconfig | 1 - configs/ficus-rk3399_defconfig| 1 - configs/firefly-rk3288_defconfig | 1 - configs/firefly-rk3399_defconfig | 1 - configs/khadas-edge-captain-rk3399_defconfig | 1 - configs/khadas-edge-rk3399_defconfig | 1 - configs/khadas-edge-v-rk3399_defconfig| 1 - configs/miqi-rk3288_defconfig | 1 - configs/nanopc-t4-rk3399_defconfig| 1 - configs/nanopi-m4-rk3399_defconfig| 1 - configs/nanopi-neo4-rk3399_defconfig | 1 - configs/orangepi-rk3399_defconfig | 1 - configs/phycore-rk3288_defconfig | 1 - configs/popmetal-rk3288_defconfig | 1 - configs/puma-rk3399_defconfig | 1 - configs/rock-pi-4-rk3399_defconfig| 1 - configs/rock960-rk3399_defconfig | 1 - configs/rockpro64-rk3399_defconfig| 4 +- configs/tinker-rk3288_defconfig | 1 - configs/vyasa-rk3288_defconfig| 1 - drivers/Makefile | 2 +- drivers/clk/rockchip/clk_rk3399.c | 36 ++-- drivers/ram/rockchip/sdram_rk3399.c | 10 +- drivers/video/rockchip/rk3399_mipi.c | 2 +- drivers/video/rockchip/rk_mipi.c | 2 +- drivers/watchdog/Kconfig | 15 ++ drivers/watchdog/Makefile | 2 +- drivers/watchdog/designware_wdt.c | 73 --- drivers/watchdog/dw_wdt.c | 188 ++ include/configs/rk3399_common.h | 5 +- include/configs/socfpga_common.h | 2 +- include/configs/socfpga_stratix10_socdk.h | 2 +- include/watchdog.h| 7 +- scripts/config_whitelist.txt | 1 - 46 files changed, 364 insertions(+), 136 deletions(-) create mode 100644 arch/arm/include/asm/arch-rockchip/cru.h create mode 100644 arch/arm/mach-rockchip/cpu-info.c delete mode 100644 drivers/watchdog/designware_wdt.c create mode 100644 drivers/watchdog/dw_wdt.c -- 2.18.0.321.gffc6fa0e3 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v2 05/16] wdt: designware: Simplify is_enabled function
Right now the designware is_enabled function is using
numeric number to check whether watchdog is enabled or
not, so use register macro and check the same.
Cc: Chin Liang See
Cc: Andy Shevchenko
Signed-off-by: Jagan Teki
---
drivers/watchdog/designware_wdt.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/watchdog/designware_wdt.c
b/drivers/watchdog/designware_wdt.c
index c668567c66..bd858f0608 100644
--- a/drivers/watchdog/designware_wdt.c
+++ b/drivers/watchdog/designware_wdt.c
@@ -45,9 +45,7 @@ static void designware_wdt_enable(void)
static unsigned int designware_wdt_is_enabled(void)
{
- unsigned long val;
- val = readl((CONFIG_DW_WDT_BASE + DW_WDT_CR));
- return val & 0x1;
+ return readl(CONFIG_DW_WDT_BASE + DW_WDT_CR) & DW_WDT_CR_RMOD_OFFSET;
}
#if defined(CONFIG_HW_WATCHDOG)
--
2.18.0.321.gffc6fa0e3
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Re: [U-Boot] [PATCH] qemu-riscv64_smode, sifive-fu540: fix extlinux (define preboot)
On Mon, Aug 26, 2019 at 5:43 AM Bin Meng wrote:
>
> Hi David,
>
> On Thu, Aug 22, 2019 at 3:07 AM David Abdurachmanov
> wrote:
> >
> > Commit 37304aaf60bf92a5dc3ef222ba520698bd862a44 removed preboot
> > commands in RISC-V targets and broke extlinux support as reported
> > by Fu Wei .
>
> I think you need add a "Reported-By" tag instead of writing this in
> the commit message.
Yes. I rushed to send the patch. There should also be Tested-By from him.
>
> And a "Fixes: commit-id ("commit title") format as well.
Okay. Basically same as for kernel patches.
>
> Please describe the commit title using something like:
>
> riscv: fix extlinux (define preboot)
>
> as it impacts more than one target.
I can only test two targets.
That's also the main (only?) used targets by Fedora/RISCV users.
I don't want to modify targets that I (or users) can test.
>
> >
> > The patch finishes migration of CONFIG_USE_PREBOOT and CONFIG_REBOOT
> > to Kconfig.
> >
> > Signed-off-by: David Abdurachmanov
> > ---
> > configs/qemu-riscv64_smode_defconfig | 2 ++
>
> What about other QEMU RISC-V targets?
That's the only two targets which I can test.
Also the only two targets that had this enabled.
>
> > configs/sifive_fu540_defconfig | 2 ++
> > include/configs/sifive-fu540.h | 4
> > 3 files changed, 4 insertions(+), 4 deletions(-)
> >
> > diff --git a/configs/qemu-riscv64_smode_defconfig
> > b/configs/qemu-riscv64_smode_defconfig
> > index 74743a5ebe..2e1f7fa91f 100644
> > --- a/configs/qemu-riscv64_smode_defconfig
> > +++ b/configs/qemu-riscv64_smode_defconfig
> > @@ -9,3 +9,5 @@ CONFIG_DISPLAY_CPUINFO=y
> > CONFIG_DISPLAY_BOARDINFO=y
> > # CONFIG_CMD_MII is not set
> > CONFIG_OF_PRIOR_STAGE=y
> > +CONFIG_USE_PREBOOT=y
> > +CONFIG_PREBOOT="setenv fdt_addr ${fdtcontroladdr}; fdt addr
> > ${fdtcontroladdr};"
>
> Please insert the config option to the correct place, eg: you can run
> it like this:
>
> $ make savedefconfig
> $ cp defconfig configs/qemu-riscv64_smode_defconfig
Will do.
>
> > diff --git a/configs/sifive_fu540_defconfig b/configs/sifive_fu540_defconfig
> > index 48865e5f11..a852579309 100644
> > --- a/configs/sifive_fu540_defconfig
> > +++ b/configs/sifive_fu540_defconfig
> > @@ -9,3 +9,5 @@ CONFIG_MISC_INIT_R=y
> > CONFIG_DISPLAY_CPUINFO=y
> > CONFIG_DISPLAY_BOARDINFO=y
> > CONFIG_OF_PRIOR_STAGE=y
> > +CONFIG_USE_PREBOOT=y
> > +CONFIG_PREBOOT="setenv fdt_addr ${fdtcontroladdr}; fdt addr
> > ${fdtcontroladdr};"
> > diff --git a/include/configs/sifive-fu540.h b/include/configs/sifive-fu540.h
> > index 858b7a7da1..ba4aa0652c 100644
> > --- a/include/configs/sifive-fu540.h
> > +++ b/include/configs/sifive-fu540.h
> > @@ -40,8 +40,4 @@
> > "ramdisk_addr_r=0x8830\0" \
> > BOOTENV
> >
> > -#define CONFIG_PREBOOT \
> > - "setenv fdt_addr ${fdtcontroladdr};" \
> > - "fdt addr ${fdtcontroladdr};"
> > -
> > #endif /* __CONFIG_H */
> > --
>
> Regards,
> Bin
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Re: [U-Boot] [RFC/RESEND 01/22] arm: introduce ARCH_THUNDERX
On Wed, Jul 31, 2019 at 5:32 PM Suneel Garapati wrote: > > Hi Matthias, > > Hard deadline is Aug 15th, so you should see first series before that. > Suneel, Update? I'm really wishing my patches posted last March were considered instead of all of this waiting. Regards, Tim ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 1/1] x86: show UEFI images involved in crash
On 8/26/19 8:13 AM, Bin Meng wrote:
Hi Heinrich,
On Mon, Aug 26, 2019 at 1:55 AM Heinrich Schuchardt wrote:
If a crash occurs, show the loaded UEFI images to facilitate analysis.
This is an example output:
=> bootefi 0x100
Found 0 disks
Hello world of bugs!
Invalid Opcode (Undefined Opcode)
EIP: 0010:[<06ceb06e>] EFLAGS: 00010206
Original EIP :[]
EAX: EBX: 06cec000 ECX: 0fd0 EDX: 0001
ESI: 06ced18a EDI: 07d0fe10 EBP: 07fe27a0 ESP: 07d0fde0
DS: 0018 ES: 0018 FS: 0020 GS: 0018 SS: 0018
CR0: 0033 CR2: CR3: CR4:
DR0: DR1: DR2: DR3:
DR6: 0ff0 DR7: 0400
Stack:
0x07d0fde8 : 0x
0x07d0fde4 : 0x06ced040
--->0x07d0fde0 : 0x07fe27a0
0x07d0fddc : 0x00010206
0x07d0fdd8 : 0x0010
0x07d0fdd4 : 0x06ceb06e
UEFI image [0x06cea000:0x06cf0fff] pc=0x106e '/bug-i386.efi'
### ERROR ### Please RESET the board ###
With the additional information provided by this patch we know that the
problem occurred 0x106e after the load address of bug-i386.efi.
Signed-off-by: Heinrich Schuchardt
---
arch/x86/cpu/i386/interrupt.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/arch/x86/cpu/i386/interrupt.c b/arch/x86/cpu/i386/interrupt.c
index 47df3172b7..1445204878 100644
--- a/arch/x86/cpu/i386/interrupt.c
+++ b/arch/x86/cpu/i386/interrupt.c
@@ -12,6 +12,7 @@
#include
#include
+#include
#include
#include
#include
@@ -64,6 +65,18 @@ static char *exceptions[] = {
"Reserved"
};
+/**
+ * show_efi_loaded_images() - show loaded UEFI images
+ *
+ * List all loaded UEFI images.
+ *
+ * @eip: instruction pointer
+ */
+static void show_efi_loaded_images(uintptr_t eip)
+{
+ efi_print_image_infos((void *)eip);
+}
+
static void dump_regs(struct irq_regs *regs)
{
unsigned long cs, eip, eflags;
@@ -144,6 +157,7 @@ static void dump_regs(struct irq_regs *regs)
printf("0x%8.8lx : 0x%8.8lx\n", sp, (ulong)readl(sp));
sp -= 4;
}
+ show_efi_loaded_images(eip);
Should we wrap the call with #ifdef CONFIG_EFI_LOADER or something?
In include/efi_loader.h we have
static inline void efi_print_image_infos(void *pc) { }
if EFI_LOADER is not defined.
Best regards
Heinrich
}
Regards,
Bin
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[U-Boot] [PATCH 1/1] cmd/host: avoid segmentation fault for 'host info'
Without the patch a segmentation fault is caused by 'host info' if
CONFIG_BLK=y:
make sandbox_defconfig
make
./u-boot
=> host bind 0 ../sct-amd64.img
=> host info 0
dev blocks path
0 Segmentation fault
Use the platform data to find the filename.
Fixes: 8f994c860d91 ("sandbox: blk: Switch to use platdata_auto_alloc_size
for the driver data")
Signed-off-by: Heinrich Schuchardt
---
cmd/host.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/cmd/host.c b/cmd/host.c
index f7d3eae5b1..98c4d2a099 100644
--- a/cmd/host.c
+++ b/cmd/host.c
@@ -89,7 +89,7 @@ static int do_host_info(cmd_tbl_t *cmdtp, int flag, int argc,
struct host_block_dev *host_dev;
#ifdef CONFIG_BLK
- host_dev = dev_get_priv(blk_dev->bdev);
+ host_dev = dev_get_platdata(blk_dev->bdev);
#else
host_dev = blk_dev->priv;
#endif
--
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Re: [U-Boot] [PATCH] core: of_addr: Correct the size type of of_get_address to fdt_size_t
Hi Keerthy,
Hi Simon,
cc: Tom
On Tue, Aug 20, 2019 at 09:39:32AM +0530, Keerthy wrote:
> On 19/08/19 3:54 PM, Eugeniu Rosca wrote:
[..]
> > I took some time to also review the changes in addition to testing.
> >
> > I can see that, since its inception in Linux [1], of_get_address() used
> > 'u64*' type for its 'size' argument. That's still valid in v5.3-rc5.
> > So, it looks to me that with this patch we diverge from Linux.
> >
> > I would barely think that the ASAN issue being fixed in this patch
> > exists in Linux, since the latter receives much more KASAN-enabled
> > testing on regular basis.
> >
> > Do you foresee any alternative fix w/o diverging from Linux?
>
> I am afraid No but isn't fdt_size_t also right type to represent size?
'fdt_size_t' is a U-Boot-ism, i.e. it exists nowhere else but in U-Boot.
Just for the record, it appears to be added by Simon's v2013.04 commit
4397a2a80baef ("fdt: Add fdtdec_get_addr_size() to read reg properties")
IMHO injecting a U-Boot-specific data type into the prototype of a
Linux-backported function has below major drawbacks:
- It is a non-upstream-able solution. Linux will unlikely accept
'fdt_size_t' as a new type simply b/c Linux OF code existed over
a decade and it didn't need this type so far.
- Mutilating Linux upstream code will make further U-Boot backports
painful, time consuming and error-prone.
Are we on the same page here?
> > [1]
> > https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=22ae782f86b7
> >
--
Best Regards,
Eugeniu.
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[U-Boot] [PATCH v2] Prevented possible null dereference.
Signed-off-by: Niv Shetrit
---
common/cli_hush.c | 73 ---
1 file changed, 38 insertions(+), 35 deletions(-)
diff --git a/common/cli_hush.c b/common/cli_hush.c
index 8f86e4aa4a..c14302c3ad 100644
--- a/common/cli_hush.c
+++ b/common/cli_hush.c
@@ -3539,41 +3539,44 @@ static char *insert_var_value_sub(char *inp, int
tag_subst)
}
inp = ++p;
/* find the ending marker */
- p = strchr(inp, SPECIAL_VAR_SYMBOL);
- *p = '\0';
- /* look up the value to substitute */
- if ((p1 = lookup_param(inp))) {
- if (tag_subst)
- len = res_str_len + strlen(p1) + 2;
- else
- len = res_str_len + strlen(p1);
- res_str = xrealloc(res_str, (1 + len));
- if (tag_subst) {
- /*
-* copy the variable value to the result
-* string
-*/
- strcpy((res_str + res_str_len + 1), p1);
-
- /*
-* mark the replaced text to be accepted as
-* is
-*/
- res_str[res_str_len] = SUBSTED_VAR_SYMBOL;
- res_str[res_str_len + 1 + strlen(p1)] =
- SUBSTED_VAR_SYMBOL;
- } else
- /*
-* copy the variable value to the result
-* string
-*/
- strcpy((res_str + res_str_len), p1);
-
- res_str_len = len;
- }
- *p = SPECIAL_VAR_SYMBOL;
- inp = ++p;
- done = 1;
+ p = strchr(inp, SPECIAL_VAR_SYMBOL)
+ if (p != NULL) {
+ *p = '\0';
+ /* look up the value to substitute */
+ p1 = lookup_param(inp)
+ if (p1 != NULL) {
+ if (tag_subst)
+ len = res_str_len + strlen(p1) + 2;
+ else
+ len = res_str_len + strlen(p1);
+ res_str = xrealloc(res_str, (1 + len));
+ if (tag_subst) {
+ /*
+* copy the variable value to the
+* result string
+*/
+ strcpy((res_str + res_str_len + 1), p1);
+
+ /*
+* mark the replaced text to be
+* accepted as is
+*/
+ res_str[res_str_len] =
SUBSTED_VAR_SYMBOL;
+ res_str[res_str_len + 1 + strlen(p1)] =
+ SUBSTED_VAR_SYMBOL;
+ } else
+ /*
+* copy the variable value to the result
+* string
+*/
+ strcpy((res_str + res_str_len), p1);
+
+ res_str_len = len;
+ }
+ *p = SPECIAL_VAR_SYMBOL;
+ inp = ++p;
+ done = 1;
+ }
}
if (done) {
res_str = xrealloc(res_str, (1 + res_str_len + strlen(inp)));
--
2.17.1
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[U-Boot] Running i.MX6Q @ 1GHz in U-Boot
I am looking at ways to decrease boot time, and one possibility I was considering was to increase the processor speed to 1GHz. Rather than writing custom code, I was trying to figure out if there is already some functions setup to do this. Is anyone already doing this? If so, can someone point me in the general direction? Thank you, adam ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 38/38] x86: Rename turbo ratio MSR to MSR_TURBO_RATIO_LIMIT
This MSR number is used on most modern Intel processors, so drop the
confusing NHM prefix (which might mean Nehalem).
Signed-off-by: Simon Glass
---
arch/x86/cpu/broadwell/cpu_full.c | 2 +-
arch/x86/include/asm/msr-index.h | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/x86/cpu/broadwell/cpu_full.c
b/arch/x86/cpu/broadwell/cpu_full.c
index bd0b2037fa..9686cf5e0e 100644
--- a/arch/x86/cpu/broadwell/cpu_full.c
+++ b/arch/x86/cpu/broadwell/cpu_full.c
@@ -346,7 +346,7 @@ static void set_max_ratio(void)
/* Check for configurable TDP option */
if (turbo_get_state() == TURBO_ENABLED) {
- msr = msr_read(MSR_NHM_TURBO_RATIO_LIMIT);
+ msr = msr_read(MSR_TURBO_RATIO_LIMIT);
perf_ctl.lo = (msr.lo & 0xff) << 8;
} else if (cpu_config_tdp_levels()) {
/* Set to nominal TDP ratio */
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index 1a02d8c8fe..7cb78beafa 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -101,7 +101,7 @@
#define MSR_OFFCORE_RSP_1 0x01a7
#define MSR_MISC_PWR_MGMT 0x1aa
#define MISC_PWR_MGMT_EIST_HW_DIS (1 << 0)
-#define MSR_NHM_TURBO_RATIO_LIMIT 0x01ad
+#define MSR_TURBO_RATIO_LIMIT 0x01ad
#define MSR_IVT_TURBO_RATIO_LIMIT 0x01ae
#define MSR_IA32_ENERGY_PERFORMANCE_BIAS 0x1b0
--
2.23.0.187.g17f5b7556c-goog
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[U-Boot] [PATCH 26/38] x86: Move common Intel CPU info code into a function
Add cpu_intel_get_info() to find out the CPU info on modern Intel CPUs.
Signed-off-by: Simon Glass
---
arch/x86/cpu/broadwell/cpu_full.c| 9 +
arch/x86/cpu/intel_common/cpu.c | 13 +
arch/x86/cpu/ivybridge/model_206ax.c | 8 ++--
arch/x86/include/asm/cpu_common.h| 11 +++
4 files changed, 27 insertions(+), 14 deletions(-)
diff --git a/arch/x86/cpu/broadwell/cpu_full.c
b/arch/x86/cpu/broadwell/cpu_full.c
index c1db184549..d8b8482658 100644
--- a/arch/x86/cpu/broadwell/cpu_full.c
+++ b/arch/x86/cpu/broadwell/cpu_full.c
@@ -645,14 +645,7 @@ void cpu_set_power_limits(int power_limit_1_time)
static int broadwell_get_info(struct udevice *dev, struct cpu_info *info)
{
- msr_t msr;
-
- msr = msr_read(IA32_PERF_CTL);
- info->cpu_freq = ((msr.lo >> 8) & 0xff) * BROADWELL_BCLK * 100;
- info->features = 1 << CPU_FEAT_L1_CACHE | 1 << CPU_FEAT_MMU |
- 1 << CPU_FEAT_UCODE | 1 << CPU_FEAT_DEVICE_ID;
-
- return 0;
+ return cpu_intel_get_info(info, BROADWELL_BCLK);
}
static int broadwell_get_count(struct udevice *dev)
diff --git a/arch/x86/cpu/intel_common/cpu.c b/arch/x86/cpu/intel_common/cpu.c
index d0ac17808c..9357626b5a 100644
--- a/arch/x86/cpu/intel_common/cpu.c
+++ b/arch/x86/cpu/intel_common/cpu.c
@@ -4,6 +4,7 @@
*/
#include
+#include
#include
#include
#include
@@ -110,3 +111,15 @@ int cpu_set_flex_ratio_to_tdp_nominal(void)
/* Not reached */
return -EINVAL;
}
+
+int cpu_intel_get_info(struct cpu_info *info, int bclk)
+{
+ msr_t msr;
+
+ msr = msr_read(IA32_PERF_CTL);
+ info->cpu_freq = ((msr.lo >> 8) & 0xff) * bclk * 100;
+ info->features = 1 << CPU_FEAT_L1_CACHE | 1 << CPU_FEAT_MMU |
+ 1 << CPU_FEAT_UCODE | 1 << CPU_FEAT_DEVICE_ID;
+
+ return 0;
+}
diff --git a/arch/x86/cpu/ivybridge/model_206ax.c
b/arch/x86/cpu/ivybridge/model_206ax.c
index 6edc3e233c..68e78e9478 100644
--- a/arch/x86/cpu/ivybridge/model_206ax.c
+++ b/arch/x86/cpu/ivybridge/model_206ax.c
@@ -12,6 +12,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -436,12 +437,7 @@ static int model_206ax_init(struct udevice *dev)
static int model_206ax_get_info(struct udevice *dev, struct cpu_info *info)
{
- msr_t msr;
-
- msr = msr_read(MSR_IA32_PERF_CTL);
- info->cpu_freq = ((msr.lo >> 8) & 0xff) * SANDYBRIDGE_BCLK * 100;
- info->features = 1 << CPU_FEAT_L1_CACHE | 1 << CPU_FEAT_MMU |
- 1 << CPU_FEAT_UCODE;
+ return cpu_intel_get_info(info, SANDYBRIDGE_BCLK);
return 0;
}
diff --git a/arch/x86/include/asm/cpu_common.h
b/arch/x86/include/asm/cpu_common.h
index 4c91a5dace..0d560262d5 100644
--- a/arch/x86/include/asm/cpu_common.h
+++ b/arch/x86/include/asm/cpu_common.h
@@ -8,6 +8,8 @@
#define IA32_PERF_CTL 0x199
+struct cpu_info;
+
/**
* cpu_common_init() - Set up common CPU init
*
@@ -31,4 +33,13 @@ int cpu_common_init(void);
*/
int cpu_set_flex_ratio_to_tdp_nominal(void);
+/**
+ * cpu_intel_get_info() - Obtain CPU info for Intel CPUs
+ *
+ * Most Intel CPUs use the same MSR to obtain the clock speed, and use the same
+ * features. This function fills in these values, given the value of the base
+ * clock in MHz (typically this should be set to 100).
+ */
+int cpu_intel_get_info(struct cpu_info *info, int bclk_mz);
+
#endif
--
2.23.0.187.g17f5b7556c-goog
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[U-Boot] [PATCH 37/38] x86: Add various MTRR indexes and values
Add some new MTRRs used by Apollolake as well as a mask for the MTRR type. Signed-off-by: Simon Glass --- arch/x86/include/asm/msr-index.h | 22 ++ arch/x86/include/asm/mtrr.h | 1 + 2 files changed, 23 insertions(+) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index 9c1dbe61d5..1a02d8c8fe 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -43,6 +43,12 @@ #define MSR_PIC_MSG_CONTROL0x2e #define PLATFORM_INFO_SET_TDP (1 << 29) +#define MSR_MTRR_CAP_MSR 0x0fe +#define MSR_MTRR_CAP_SMRR (1 << 11) +#define MSR_MTRR_CAP_WC(1 << 10) +#define MSR_MTRR_CAP_FIX (1 << 8) +#define MSR_MTRR_CAP_VCNT 0xff + #define MSR_IA32_PERFCTR0 0x00c1 #define MSR_IA32_PERFCTR1 0x00c2 #define MSR_FSB_FREQ 0x00cd @@ -67,6 +73,11 @@ #define ENABLE_ULFM_AUTOCM_MASK(1 << 2) #define ENABLE_INDP_AUTOCM_MASK(1 << 3) +#define MSR_EMULATE_PM_TIMER 0x121 +#define EMULATE_DELAY_OFFSET_VALUE20 +#define EMULATE_PM_TMR_EN (1 << 16) +#define EMULATE_DELAY_VALUE 0x13 + #define MSR_IA32_SYSENTER_CS 0x0174 #define MSR_IA32_SYSENTER_ESP 0x0175 #define MSR_IA32_SYSENTER_EIP 0x0176 @@ -78,9 +89,14 @@ #define MSR_FLEX_RATIO 0x194 #define FLEX_RATIO_LOCK (1 << 20) #define FLEX_RATIO_EN (1 << 16) +/* This is burst mode BIT 38 in IA32_MISC_ENABLE MSR at offset 1A0h */ +#define BURST_MODE_DISABLE (1 << 6) #define MSR_IA32_MISC_ENABLES 0x01a0 #define MSR_TEMPERATURE_TARGET 0x1a2 +#define MSR_PREFETCH_CTL 0x1a4 +#define PREFETCH_L1_DISABLE (1 << 0) +#define PREFETCH_L2_DISABLE (1 << 2) #define MSR_OFFCORE_RSP_0 0x01a6 #define MSR_OFFCORE_RSP_1 0x01a7 #define MSR_MISC_PWR_MGMT 0x1aa @@ -600,6 +616,12 @@ #define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x0490 #define MSR_IA32_VMX_VMFUNC 0x0491 +#define MSR_IA32_PQR_ASSOC 0xc8f +/* MSR bits 33:32 encode slot number 0-3 */ +#define MSR_IA32_PQR_ASSOC_MASK(1 << 0 | 1 << 1) + +#define MSR_L2_QOS_MASK(reg) (0xd10 + (reg)) + /* VMX_BASIC bits and bitmasks */ #define VMX_BASIC_VMCS_SIZE_SHIFT 32 #define VMX_BASIC_64 0x0001LLU diff --git a/arch/x86/include/asm/mtrr.h b/arch/x86/include/asm/mtrr.h index 2d897f82ef..6f29e75ce6 100644 --- a/arch/x86/include/asm/mtrr.h +++ b/arch/x86/include/asm/mtrr.h @@ -25,6 +25,7 @@ #define MTRR_CAP_FIX (1 << 8) #define MTRR_CAP_VCNT_MASK 0xff +#define MTRR_DEF_TYPE_MASK 0xff #define MTRR_DEF_TYPE_EN (1 << 11) #define MTRR_DEF_TYPE_FIX_EN (1 << 10) -- 2.23.0.187.g17f5b7556c-goog ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 30/38] x86: spl: Reduce priority of the basic SPL image loader
This image loader works on systems where the flash is directly mapped to
the last part of the 32-bit address space. On recent Intel systems (such
as apollolake) this is not the case.
Reduce the priority of this loader so that another one can override it.
While we are here, rename the loader to BOOT_DEVICE_SPI_MMAP since
BOOT_DEVICE_BOARD is not very descriptive.
Signed-off-by: Simon Glass
---
arch/x86/include/asm/spl.h | 3 +--
arch/x86/lib/spl.c | 5 +++--
arch/x86/lib/tpl.c | 4 ++--
3 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/arch/x86/include/asm/spl.h b/arch/x86/include/asm/spl.h
index 27432b2897..1bef4877eb 100644
--- a/arch/x86/include/asm/spl.h
+++ b/arch/x86/include/asm/spl.h
@@ -10,8 +10,7 @@
#define CONFIG_SPL_BOARD_LOAD_IMAGE
enum {
- BOOT_DEVICE_SPI = 10,
- BOOT_DEVICE_BOARD,
+ BOOT_DEVICE_SPI_MMAP= 10,
BOOT_DEVICE_CROS_VBOOT,
};
diff --git a/arch/x86/lib/spl.c b/arch/x86/lib/spl.c
index 01a96d294b..a739491303 100644
--- a/arch/x86/lib/spl.c
+++ b/arch/x86/lib/spl.c
@@ -11,6 +11,7 @@
#include
#include
#include
+#include
#include
DECLARE_GLOBAL_DATA_PTR;
@@ -142,7 +143,7 @@ void board_init_f_r(void)
u32 spl_boot_device(void)
{
- return BOOT_DEVICE_BOARD;
+ return BOOT_DEVICE_SPI_MMAP;
}
int spl_start_uboot(void)
@@ -168,7 +169,7 @@ static int spl_board_load_image(struct spl_image_info
*spl_image,
return 0;
}
-SPL_LOAD_IMAGE_METHOD("SPI", 0, BOOT_DEVICE_BOARD, spl_board_load_image);
+SPL_LOAD_IMAGE_METHOD("SPI", 5, BOOT_DEVICE_SPI_MMAP, spl_board_load_image);
int spl_spi_load_image(void)
{
diff --git a/arch/x86/lib/tpl.c b/arch/x86/lib/tpl.c
index 3e662a8bda..cfefa78045 100644
--- a/arch/x86/lib/tpl.c
+++ b/arch/x86/lib/tpl.c
@@ -71,7 +71,7 @@ void board_init_f_r(void)
u32 spl_boot_device(void)
{
return IS_ENABLED(CONFIG_CHROMEOS) ? BOOT_DEVICE_CROS_VBOOT :
- BOOT_DEVICE_BOARD;
+ BOOT_DEVICE_SPI_MMAP;
}
int spl_start_uboot(void)
@@ -97,7 +97,7 @@ static int spl_board_load_image(struct spl_image_info
*spl_image,
return 0;
}
-SPL_LOAD_IMAGE_METHOD("SPI", 0, BOOT_DEVICE_BOARD, spl_board_load_image);
+SPL_LOAD_IMAGE_METHOD("SPI", 5, BOOT_DEVICE_SPI_MMAP, spl_board_load_image);
int spl_spi_load_image(void)
{
--
2.23.0.187.g17f5b7556c-goog
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[U-Boot] [PATCH 31/38] x86: spl: Move broadwell-specific code out of generic x86 spl
When TPL is running, broadwell needs to do different init from SPL. There
is no need for this code to be in the generic x86 SPL file, so move it to
arch_cpu_init().
Signed-off-by: Simon Glass
---
arch/x86/cpu/broadwell/cpu.c | 5 +
arch/x86/cpu/broadwell/cpu_full.c | 7 +++
arch/x86/lib/spl.c| 5 -
3 files changed, 12 insertions(+), 5 deletions(-)
diff --git a/arch/x86/cpu/broadwell/cpu.c b/arch/x86/cpu/broadwell/cpu.c
index bb7c361408..bba8cd1e94 100644
--- a/arch/x86/cpu/broadwell/cpu.c
+++ b/arch/x86/cpu/broadwell/cpu.c
@@ -67,7 +67,12 @@ int arch_cpu_init(void)
{
post_code(POST_CPU_INIT);
+#ifdef CONFIG_TPL
+ /* Do a mini-init if TPL has already done the full init */
+ return x86_cpu_reinit_f();
+#else
return x86_cpu_init_f();
+#endif
}
int checkcpu(void)
diff --git a/arch/x86/cpu/broadwell/cpu_full.c
b/arch/x86/cpu/broadwell/cpu_full.c
index d8b8482658..bd0b2037fa 100644
--- a/arch/x86/cpu/broadwell/cpu_full.c
+++ b/arch/x86/cpu/broadwell/cpu_full.c
@@ -81,6 +81,13 @@ static const u8 power_limit_time_msr_to_sec[] = {
[0x11] = 128,
};
+#if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_TPL_BUILD)
+int arch_cpu_init(void)
+{
+ return 0;
+}
+#endif
+
/*
* The core 100MHz BLCK is disabled in deeper c-states. One needs to calibrate
* the 100MHz BCLCK against the 24MHz BLCK to restore the clocks properly
diff --git a/arch/x86/lib/spl.c b/arch/x86/lib/spl.c
index a739491303..2baac91383 100644
--- a/arch/x86/lib/spl.c
+++ b/arch/x86/lib/spl.c
@@ -40,12 +40,7 @@ static int x86_spl_init(void)
debug("%s: spl_init() failed\n", __func__);
return ret;
}
-#ifdef CONFIG_TPL
- /* Do a mini-init if TPL has already done the full init */
- ret = x86_cpu_reinit_f();
-#else
ret = arch_cpu_init();
-#endif
if (ret) {
debug("%s: arch_cpu_init() failed\n", __func__);
return ret;
--
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[U-Boot] [PATCH 17/38] x86: fsp: Create a common fsp_support.h header
Many support functions are common between FSP1 and FSP2. Add a new header to handle this. Signed-off-by: Simon Glass --- arch/x86/include/asm/fsp/fsp_support.h | 128 arch/x86/include/asm/fsp1/fsp_support.h | 123 +-- drivers/pci/pci-uclass.c| 2 +- 3 files changed, 132 insertions(+), 121 deletions(-) create mode 100644 arch/x86/include/asm/fsp/fsp_support.h diff --git a/arch/x86/include/asm/fsp/fsp_support.h b/arch/x86/include/asm/fsp/fsp_support.h new file mode 100644 index 00..0ecd5cb6c5 --- /dev/null +++ b/arch/x86/include/asm/fsp/fsp_support.h @@ -0,0 +1,128 @@ +/* SPDX-License-Identifier: Intel */ +/* + * Copyright (C) 2013, Intel Corporation + * Copyright (C) 2014, Bin Meng + */ + +#ifndef __FSP_SUPPORT_H__ +#define __FSP_SUPPORT_H__ + +#include +#include +#include +#include +#include +#include +#include + +#define FSP_LOWMEM_BASE0x10UL +#define FSP_HIGHMEM_BASE 0x1ULL +#define UPD_TERMINATOR 0x55AA + +struct fspinit_rtbuf; +struct fsp_config_data; + +/** + * Find FSP header offset in FSP image + * + * @retval: the offset of FSP header. If signature is invalid, returns 0. + */ +struct fsp_header *fsp_find_header(void); + +/** + * FSP notification wrapper function + * + * @fsp_hdr: Pointer to FSP information header + * @phase: FSP initialization phase defined in enum fsp_phase + * + * @retval: compatible status code with EFI_STATUS defined in PI spec + */ +u32 fsp_notify(struct fsp_header *fsp_hdr, u32 phase); + +/** + * This function retrieves the top of usable low memory. + * + * @hob_list: A HOB list pointer. + * + * @retval: Usable low memory top. + */ +u32 fsp_get_usable_lowmem_top(const void *hob_list); + +/** + * This function retrieves the top of usable high memory. + * + * @hob_list: A HOB list pointer. + * + * @retval: Usable high memory top. + */ +u64 fsp_get_usable_highmem_top(const void *hob_list); + +/** + * This function retrieves a special reserved memory region. + * + * @hob_list: A HOB list pointer. + * @len: A pointer to the GUID HOB data buffer length. + *If the GUID HOB is located, the length will be updated. + * @guid: A pointer to the owner guild. + * + * @retval: Reserved region start address. + *0 if this region does not exist. + */ +u64 fsp_get_reserved_mem_from_guid(const void *hob_list, + u64 *len, const efi_guid_t *guid); + +/** + * This function retrieves the FSP reserved normal memory. + * + * @hob_list: A HOB list pointer. + * @len: A pointer to the FSP reserved memory length buffer. + *If the GUID HOB is located, the length will be updated. + * @retval: FSP reserved memory base + *0 if this region does not exist. + */ +u32 fsp_get_fsp_reserved_mem(const void *hob_list, u32 *len); + +/** + * This function retrieves the TSEG reserved normal memory. + * + * @hob_list: A HOB list pointer. + * @len: A pointer to the TSEG reserved memory length buffer. + * If the GUID HOB is located, the length will be updated. + * + * @retval NULL: Failed to find the TSEG reserved memory. + * @retval others: TSEG reserved memory base. + */ +u32 fsp_get_tseg_reserved_mem(const void *hob_list, u32 *len); + +/** + * This function retrieves FSP Non-volatile Storage HOB buffer and size. + * + * @hob_list: A HOB list pointer. + * @len: A pointer to the NVS data buffer length. + * If the HOB is located, the length will be updated. + * + * @retval NULL: Failed to find the NVS HOB. + * @retval others: FSP NVS data buffer pointer. + */ +void *fsp_get_nvs_data(const void *hob_list, u32 *len); + +/** + * This function retrieves graphics information. + * + * @hob_list: A HOB list pointer. + * @len: A pointer to the graphics info HOB length. + * If the HOB is located, the length will be updated. + * + * @retval NULL: Failed to find the graphics info HOB. + * @retval others: A pointer to struct hob_graphics_info. + */ +void *fsp_get_graphics_info(const void *hob_list, u32 *len); + +/** + * fsp_init_phase_pci() - Tell the FSP that we have completed PCI init + * + * @return 0 if OK, -EPERM if the FSP gave an error. + */ +int fsp_init_phase_pci(void); + +#endif diff --git a/arch/x86/include/asm/fsp1/fsp_support.h b/arch/x86/include/asm/fsp1/fsp_support.h index 945a45c0fe..15c3a462e2 100644 --- a/arch/x86/include/asm/fsp1/fsp_support.h +++ b/arch/x86/include/asm/fsp1/fsp_support.h @@ -4,25 +4,11 @@ * Copyright (C) 2014, Bin Meng */ -#ifndef __FSP_SUPPORT_H__ -#define __FSP_SUPPORT_H__ +#ifndef __FSP1_SUPPORT_H__ +#define __FSP1_SUPPORT_H__ -#include -#include -#include -#include -#include +#include #include "fsp_ffs.h" -#include -#include - -#define FSP_LOWMEM_BASE0x10UL -#define FSP_HIGHMEM_BASE 0x1ULL -#define UPD_TERMINATOR
[U-Boot] [PATCH 24/38] x86: fsp: Add a few more definitions for FSP2
Add definitions for the FSP signature and the FSP init phase.
Signed-off-by: Simon Glass
---
arch/x86/include/asm/fsp/fsp_infoheader.h | 15 ++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/arch/x86/include/asm/fsp/fsp_infoheader.h
b/arch/x86/include/asm/fsp/fsp_infoheader.h
index 86f78014b7..e72c052ed1 100644
--- a/arch/x86/include/asm/fsp/fsp_infoheader.h
+++ b/arch/x86/include/asm/fsp/fsp_infoheader.h
@@ -33,6 +33,19 @@ struct __packed fsp_header {
#define FSP_HEADER_REVISION_1 1
#define FSP_HEADER_REVISION_2 2
-#define FSP_ATTR_GRAPHICS_SUPPORT (1 << 0)
+enum fsp_type {
+ FSP_ATTR_COMP_TYPE_FSP_T= 1,
+ FSP_ATTR_COMP_TYPE_FSP_M= 2,
+ FSP_ATTR_COMP_TYPE_FSP_S= 3,
+};
+
+enum {
+ FSP_ATTR_GRAPHICS_SUPPORT = 1 << 0,
+ FSP_ATTR_COMP_TYPE_SHIFT= 28,
+ FSP_ATTR_COMP_TYPE_MASK = 0xfU << FSP_ATTR_COMP_TYPE_SHIFT,
+
+};
+
+#define EFI_FSPH_SIGNATURE SIGNATURE_32('F', 'S', 'P', 'H')
#endif
--
2.23.0.187.g17f5b7556c-goog
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[U-Boot] [PATCH 23/38] efi: Move inline functions to unconditional part of header
At present these two functions are defined in efi_loader.h but only if
CONFIG_EFI_LOADER is enabled. But these are functions that are useful to
other code, such as that which deals with Intel Handoff Blocks (HOBs).
Move these to the top of the function.
Possibly ascii2unicode() should not be an inline function, since this
might impact code size.
Signed-off-by: Simon Glass
---
In general it seems to be bad form to include parts of headers
conditionally.
include/efi_loader.h | 42 +-
1 file changed, 21 insertions(+), 21 deletions(-)
diff --git a/include/efi_loader.h b/include/efi_loader.h
index 5298ea7997..82f236e295 100644
--- a/include/efi_loader.h
+++ b/include/efi_loader.h
@@ -12,6 +12,27 @@
#include
#include
+/**
+ * ascii2unicode() - convert ASCII string to UTF-16 string
+ *
+ * A zero terminated ASCII string is converted to a zero terminated UTF-16
+ * string. The output buffer must be preassigned.
+ *
+ * @unicode: preassigned output buffer for UTF-16 string
+ * @ascii: ASCII string to be converted
+ */
+static inline void ascii2unicode(u16 *unicode, const char *ascii)
+{
+ while (*ascii)
+ *(unicode++) = *(ascii++);
+ *unicode = 0;
+}
+
+static inline int guidcmp(const void *g1, const void *g2)
+{
+ return memcmp(g1, g2, sizeof(efi_guid_t));
+}
+
/* No need for efi loader support in SPL */
#if CONFIG_IS_ENABLED(EFI_LOADER)
@@ -551,27 +572,6 @@ efi_status_t efi_dp_from_name(const char *dev, const char
*devnr,
(((_dp)->type == DEVICE_PATH_TYPE_##_type) && \
((_dp)->sub_type == DEVICE_PATH_SUB_TYPE_##_subtype))
-/**
- * ascii2unicode() - convert ASCII string to UTF-16 string
- *
- * A zero terminated ASCII string is converted to a zero terminated UTF-16
- * string. The output buffer must be preassigned.
- *
- * @unicode: preassigned output buffer for UTF-16 string
- * @ascii: ASCII string to be converted
- */
-static inline void ascii2unicode(u16 *unicode, const char *ascii)
-{
- while (*ascii)
- *(unicode++) = *(ascii++);
- *unicode = 0;
-}
-
-static inline int guidcmp(const void *g1, const void *g2)
-{
- return memcmp(g1, g2, sizeof(efi_guid_t));
-}
-
/*
* Use these to indicate that your code / data should go into the EFI runtime
* section and thus still be available when the OS is running
--
2.23.0.187.g17f5b7556c-goog
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[U-Boot] [PATCH 34/38] x86: Change condition for using CAR
At present we assume that CAR (Cache-as-RAM) is used if HOBs (Hand-off bLocks) are not, since HOBs typically indicate that an FSP is in use, and FSPs handle the CAR init. However this is a bit indirect, and for FSP2 machines which use their own CAR implementation (such as apollolake) but use the FSP for other functions, the logic is wrong. To fix this, add a dedicated Kconfig option to indicate when CAR is used. Signed-off-by: Simon Glass --- arch/x86/Kconfig | 8 arch/x86/cpu/start.S | 4 ++-- configs/slimbootloader_defconfig | 1 + 3 files changed, 11 insertions(+), 2 deletions(-) diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 314f8def7a..47bf28c434 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -364,6 +364,14 @@ config HAVE_FSP Note: Without this binary U-Boot will not be able to set up its SDRAM so will not boot. +config USE_CAR + bool "Use Cache-As-RAM (CAR) to get temporary RAM at start-up" + default y if !HAVE_FSP + help + Select this option if your board uses CAR init code, typically in a + car.S file, to get some initial memory for code execution. This is + common with Intel CPUs which don't use FSP. + choice prompt "FSP version" depends on HAVE_FSP diff --git a/arch/x86/cpu/start.S b/arch/x86/cpu/start.S index 3c9bdf2a9d..9b76394274 100644 --- a/arch/x86/cpu/start.S +++ b/arch/x86/cpu/start.S @@ -90,7 +90,7 @@ early_board_init_ret: jmp car_init .globl car_init_ret car_init_ret: -#ifndef CONFIG_USE_HOB +#ifdef CONFIG_USE_CAR /* * We now have CONFIG_SYS_CAR_SIZE bytes of Cache-As-RAM (or SRAM, * or fully initialised SDRAM - we really don't care which) @@ -130,7 +130,7 @@ car_init_ret: /* Get address of global_data */ mov %fs:0, %edx -#ifdef CONFIG_USE_HOB +#if defined(CONFIG_USE_HOB) && !defined(CONFIG_USE_CAR) /* Store the HOB list if we have one */ test%esi, %esi jz skip_hob diff --git a/configs/slimbootloader_defconfig b/configs/slimbootloader_defconfig index f9fecff45e..3cbb83c7a4 100644 --- a/configs/slimbootloader_defconfig +++ b/configs/slimbootloader_defconfig @@ -18,3 +18,4 @@ CONFIG_REGMAP=y CONFIG_SYSCON=y # CONFIG_PCI_PNP is not set CONFIG_CONSOLE_SCROLL_LINES=5 +# CONFIG_USE_CAR is not set -- 2.23.0.187.g17f5b7556c-goog ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 32/38] x86: fsp: Save usable RAM and hob_list in the handoff area
The useable RAM is calculated when the RAM is inited. Save this value so
that it can be easily used in U-Boot proper.
Also save a pointer to the hob list so that it is accessible (before
relocation only) in U-Boot proper. This avoids having to scan it in SPL,
for everything U-Boot proper might need later.
Signed-off-by: Simon Glass
---
arch/x86/cpu/intel_common/cpu_from_spl.c | 6 ++
arch/x86/include/asm/handoff.h | 8
arch/x86/lib/fsp/fsp_dram.c | 10 ++
3 files changed, 24 insertions(+)
diff --git a/arch/x86/cpu/intel_common/cpu_from_spl.c
b/arch/x86/cpu/intel_common/cpu_from_spl.c
index a6233c75ce..b7bb524162 100644
--- a/arch/x86/cpu/intel_common/cpu_from_spl.c
+++ b/arch/x86/cpu/intel_common/cpu_from_spl.c
@@ -6,6 +6,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -21,6 +22,11 @@ int arch_cpu_init(void)
{
int ret;
+#if CONFIG_IS_ENABLED(HANDOFF) && IS_ENABLED(CONFIG_USE_HOB)
+ struct spl_handoff *ho = gd->spl_handoff;
+
+ gd->arch.hob_list = ho->arch.hob_list;
+#endif
ret = x86_cpu_reinit_f();
return ret;
diff --git a/arch/x86/include/asm/handoff.h b/arch/x86/include/asm/handoff.h
index 4d18d59efe..aec49b9b81 100644
--- a/arch/x86/include/asm/handoff.h
+++ b/arch/x86/include/asm/handoff.h
@@ -9,7 +9,15 @@
#ifndef __x86_asm_handoff_h
#define __x86_asm_handoff_h
+/**
+ * struct arch_spl_handoff - architecture-specific handoff info
+ *
+ * @usable_ram_top: Value returned by board_get_usable_ram_top() in SPL
+ * @hob_list: Start of FSP hand-off blocks (HOBs)
+ */
struct arch_spl_handoff {
+ ulong usable_ram_top;
+ void *hob_list;
};
#endif
diff --git a/arch/x86/lib/fsp/fsp_dram.c b/arch/x86/lib/fsp/fsp_dram.c
index 8fe1e0bf73..38cc25839e 100644
--- a/arch/x86/lib/fsp/fsp_dram.c
+++ b/arch/x86/lib/fsp/fsp_dram.c
@@ -88,3 +88,13 @@ unsigned int install_e820_map(unsigned int max_entries,
return num_entries;
}
+
+#if CONFIG_IS_ENABLED(HANDOFF)
+int handoff_arch_save(struct spl_handoff *ho)
+{
+ ho->arch.usable_ram_top = fsp_get_usable_lowmem_top(gd->arch.hob_list);
+ ho->arch.hob_list = gd->arch.hob_list;
+
+ return 0;
+}
+#endif
--
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[U-Boot] [PATCH 20/38] x86: fsp: Move common dram functions into a common file
Most of the DRAM functionality can be shared between FSP1 and FSP2. Move
it into a shared file.
Signed-off-by: Simon Glass
---
arch/x86/include/asm/fsp/fsp_support.h | 9 +++
arch/x86/lib/Makefile | 1 +
arch/x86/lib/fsp/Makefile | 5 ++
arch/x86/lib/fsp/fsp_dram.c| 90 ++
arch/x86/lib/fsp1/fsp_dram.c | 80 ++-
5 files changed, 111 insertions(+), 74 deletions(-)
create mode 100644 arch/x86/lib/fsp/Makefile
create mode 100644 arch/x86/lib/fsp/fsp_dram.c
diff --git a/arch/x86/include/asm/fsp/fsp_support.h
b/arch/x86/include/asm/fsp/fsp_support.h
index 8d29f9f5e4..8f8795415d 100644
--- a/arch/x86/include/asm/fsp/fsp_support.h
+++ b/arch/x86/include/asm/fsp/fsp_support.h
@@ -125,4 +125,13 @@ void *fsp_get_graphics_info(const void *hob_list, u32
*len);
*/
int fsp_init_phase_pci(void);
+/**
+ * fsp_scan_for_ram_size() - Scan the HOB list to find the RAM size
+ *
+ * This sets gd->ram_size based on what it finds.
+ *
+ * @return 0 if OK, -ve on error
+ */
+int fsp_scan_for_ram_size(void);
+
#endif
diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile
index a8c7448ee4..ca0ca1066b 100644
--- a/arch/x86/lib/Makefile
+++ b/arch/x86/lib/Makefile
@@ -43,6 +43,7 @@ ifndef CONFIG_SPL_BUILD
obj-$(CONFIG_CMD_ZBOOT)+= zimage.o
endif
obj-$(CONFIG_USE_HOB) += hob.o
+obj-$(CONFIG_HAVE_FSP) += fsp/
obj-$(CONFIG_FSP_VERSION1) += fsp1/
obj-$(CONFIG_FSP_VERSION2) += fsp2/
diff --git a/arch/x86/lib/fsp/Makefile b/arch/x86/lib/fsp/Makefile
new file mode 100644
index 00..e2160653de
--- /dev/null
+++ b/arch/x86/lib/fsp/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright 2019 Google LLC
+
+obj-y += fsp_dram.o
diff --git a/arch/x86/lib/fsp/fsp_dram.c b/arch/x86/lib/fsp/fsp_dram.c
new file mode 100644
index 00..8fe1e0bf73
--- /dev/null
+++ b/arch/x86/lib/fsp/fsp_dram.c
@@ -0,0 +1,90 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2014, Bin Meng
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int fsp_scan_for_ram_size(void)
+{
+ phys_size_t ram_size = 0;
+ const struct hob_header *hdr;
+ struct hob_res_desc *res_desc;
+
+ hdr = gd->arch.hob_list;
+ while (!end_of_hob(hdr)) {
+ if (hdr->type == HOB_TYPE_RES_DESC) {
+ res_desc = (struct hob_res_desc *)hdr;
+ if (res_desc->type == RES_SYS_MEM ||
+ res_desc->type == RES_MEM_RESERVED)
+ ram_size += res_desc->len;
+ }
+ hdr = get_next_hob(hdr);
+ }
+
+ gd->ram_size = ram_size;
+ post_code(POST_DRAM);
+
+ return 0;
+};
+
+int dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = 0;
+ gd->bd->bi_dram[0].size = gd->ram_size;
+
+ return 0;
+}
+
+unsigned int install_e820_map(unsigned int max_entries,
+ struct e820_entry *entries)
+{
+ unsigned int num_entries = 0;
+ const struct hob_header *hdr;
+ struct hob_res_desc *res_desc;
+
+ hdr = gd->arch.hob_list;
+
+ while (!end_of_hob(hdr)) {
+ if (hdr->type == HOB_TYPE_RES_DESC) {
+ res_desc = (struct hob_res_desc *)hdr;
+ entries[num_entries].addr = res_desc->phys_start;
+ entries[num_entries].size = res_desc->len;
+
+ if (res_desc->type == RES_SYS_MEM)
+ entries[num_entries].type = E820_RAM;
+ else if (res_desc->type == RES_MEM_RESERVED)
+ entries[num_entries].type = E820_RESERVED;
+
+ num_entries++;
+ }
+ hdr = get_next_hob(hdr);
+ }
+
+ /* Mark PCIe ECAM address range as reserved */
+ entries[num_entries].addr = CONFIG_PCIE_ECAM_BASE;
+ entries[num_entries].size = CONFIG_PCIE_ECAM_SIZE;
+ entries[num_entries].type = E820_RESERVED;
+ num_entries++;
+
+#ifdef CONFIG_HAVE_ACPI_RESUME
+ /*
+* Everything between U-Boot's stack and ram top needs to be
+* reserved in order for ACPI S3 resume to work.
+*/
+ entries[num_entries].addr = gd->start_addr_sp - CONFIG_STACK_SIZE;
+ entries[num_entries].size = gd->ram_top - gd->start_addr_sp +
+ CONFIG_STACK_SIZE;
+ entries[num_entries].type = E820_RESERVED;
+ num_entries++;
+#endif
+
+ return num_entries;
+}
diff --git a/arch/x86/lib/fsp1/fsp_dram.c b/arch/x86/lib/fsp1/fsp_dram.c
index 961e963362..6a3349b42a 100644
--- a/arch/x86/lib/fsp1/fsp_dram.c
+++ b/arch/x86/lib/fsp1/fsp_dram.c
@@ -4,30 +4,16 @@
*/
#include
-#include
-#include
-#include
-#include
-
-DECLARE_GLOBAL_DATA_PTR;
+#include
int dram_init(void)
{
- phys_size_t ram_size = 0;
-
