The memory and silicon init parts of the FSP need support code to work.
Add this for Apollo Lake.
Signed-off-by: Simon Glass
---
Changes in v6:
- Drop mention of devicetree for VTD feature
- Drop mention of ramstage
- Fix various coding style problems
- Make BOOT_FROM_FAST_SPI_FLASH a Kconfig
These are mostly specific to a particular SoC. Add the definitions for
Apollo Lake.
Signed-off-by: Simon Glass
---
Changes in v6:
- Fix FSP-M and FSP-S in comments
Changes in v5: None
Changes in v4:
- apollolake -> Apollo Lake
Changes in v3:
- Add VBT signature
- Add structures for FSP-S also
Add support for coral which is a range of Apollo Lake-based Chromebook
released in 2017. This also includes reef released in 2016, since it is
based on the same SoC.
Signed-off-by: Simon Glass
---
Changes in v6:
- Add a comment about the need for board_run_command()
- Use generic gpio
Add basic plumbing to allow Apollo Lake support to be used.
Signed-off-by: Simon Glass
---
Changes in v6:
- Make BOOT_FROM_FAST_SPI_FLASH a Kconfig option
Changes in v5:
- Enable SMP
Changes in v4:
- Enable HAVE_X86_FIT
- Enable INTEL_GPIO
- Switch over to use pinctrl for pad init/config
-
Adds a driver for the Apollo Lake Primary-to-sideband bus. This supports
various child devices. It supposed both device tree and of-platdata.
Signed-off-by: Simon Glass
---
Changes in v6: None
Changes in v5: None
Changes in v4:
- Detect zero mmio address
- Use BIT() macro bit more
- apollolake
Add code to init the system both in TPL and SPL. Each phase has its own
procedure.
Signed-off-by: Simon Glass
---
Changes in v6:
- Change comment to apl_hostbridge_early_init_pinctrl, not apl_gpio_early_init
- Change commented-out enable_rtc_upper_bank() call to a TODO
- Make
Add a bare-bones CPU driver so that CPUs can be probed.
Signed-off-by: Simon Glass
---
Changes in v6:
- Drop unnecessary priv struct and probe method
- Make BOOT_FROM_FAST_SPI_FLASH a Kconfig option
Changes in v5:
- Add L2 cache flush function
- Drop SAFETY_MARGIN
Changes in v4:
- Change
Binman supports writing the position and size of U-Boot proper and SPL
into the previous phase of U-Boot. This allows the next phase to be easily
located and loaded.
Add functions to return these useful values, along with symbols to allow
TPL to load SPL.
Signed-off-by: Simon Glass
---
Changes
Add a driver for the Apollo Lake P-unit (power unit). It is modelled as a
syscon driver since it only needs to be probed.
Signed-off-by: Simon Glass
---
Changes in v6:
- Drop Glacier Lake code
- Drop platform data and pre-PCI code, since DM PCI is available in SPL
Changes in v5: None
Changes
Add loaders for SPL and TPL so that the next stage can be loaded from
memory-mapped SPI or, failing that, the Fast SPI driver.
Signed-off-by: Simon Glass
---
Changes in v6:
- Make BOOT_FROM_FAST_SPI_FLASH a Kconfig option
- Move image pos/size access functions and symbols to generic SPL code
Add a driver for the Apollo Lake Platform Controller Hub. It does not have
any functionality and is just a placeholder for now.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v6: None
Changes in v5: None
Changes in v4:
- Tidy up header guards
- Update SPI flash protection only
This driver the LPC and provides a few functions to set up LPC features.
These should probably use ioctls() or perhaps, better, have specific
uclass methods.
Signed-off-by: Simon Glass
---
Changes in v6:
- Drop init of ComB since it is not used
- Drop lpc_configure_pads() and probe() function,
This driver models some sort of interrupt thingy but there are so many
abreviations that I cannot find out what it stands for. Possibly something
to do with interrupts.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v6: None
Changes in v5: None
Changes in v4:
- Tidy up header
This driver models the hostbridge as a northbridge. It simply sets up the
graphics BAR. It supports of-platdata.
Signed-off-by: Simon Glass
---
Changes in v6:
- Fix comments for struct apl_hostbridge_platdata
Changes in v5: None
Changes in v4:
- Avoid needing to know internals of pinctrl in
This driver handles communication with the systemagent which needs to be
told when U-Boot has completed its init.
Signed-off-by: Simon Glass
---
Changes in v6: None
Changes in v5: None
Changes in v4:
- Add a comment for enable_bios_reset_cpl()
- Tidy up header guards
- use GENMASK() for
Add a driver for the Apollo Lake UART. It uses the standard ns16550 device
but also sets up the input clock with LPSS and supports configuration via
of-platdata.
Signed-off-by: Simon Glass
---
Changes in v6:
- Drop code to handle !CONFIG_OF_TRANSLATE case
- Update comment to reference
Add a driver for the Apollo Lake pinctrl. This mostly makes use of the
common Intel pinctrl support.
Signed-off-by: Simon Glass
---
Changes in v6: None
Changes in v5: None
Changes in v4:
- Allow pinctrl nodes to have subnodes (i.e. GPIO nodes)
- Drop GPIO_NUM_PAD_CFG_REGS
- Switch over to use
For Apollo Lake we need to take the I2C bus controller out of reset before
using this. Add this functionality to the driver.
Signed-off-by: Simon Glass
Reviewed-by: Heiko Schocher
---
Changes in v6:
- Add .driver_data in the designware_pci_supported array
- Add a comment about VANILLA
- Move
Add a driver for the Apollo Lake SoC. It supports the basic operations and
can use device tree or of-platdata.
Signed-off-by: Simon Glass
---
Changes in v6:
- Use one space after #defines in pm.h
Changes in v5: None
Changes in v4:
- Fix Makefile copyright message
- Fix incorrect mask check in
This function is specific to qemu so it seems best to keep it separate
from the generic code.
Move it out to a new file and update the condition to use if() instead of
#ifdef
Signed-off-by: Simon Glass
---
Changes in v6:
- Add back '#ifdef' line to commit message
- Drop incorrect mention of
Recent Intel SoCs share a pinctrl mechanism with many common elements. Add
an implementation of this core functionality, allowing SoC-specific
drivers to avoid adding common code.
As well as a pinctrl driver this provides a GPIO driver based on the same
code.
Once other SoCs use this driver we
Add a GPIO driver which uses the pinctrl driver to access the pad
information. This driver relies on the GPIO nodes being subnodes to the
pinctrl device.
Signed-off-by: Simon Glass
---
Changes in v6:
- Fix 'hone' typo
- Remove the * in the first line of the binding file
- Use 'north' as the
Add some fixed IO and mmap addresses for use in the device tree and with
some early-init code.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v6: None
Changes in v5:
- Add ACPI base address and size
Changes in v4:
- Drop TCO_BASE_ADDRESS
- Tidy up header guards
Changes in
With of-platdata we need to create drivers for particular chips, or at
least drivers that are separate from the standard code, since C structures
are created by dtoc which are private to that driver.
To avoid duplicating the probing code, export this probe function for use
by these drivers.
If these phases are used we typically want to enable pinctrl in then, so
that pad setup and GPIO access are possible.
Signed-off-by: Simon Glass
---
Changes in v6: None
Changes in v5:
- Correct build error in chromebook_samus_tpl
Changes in v4: None
Changes in v3: None
Changes in v2: None
This subsystem is present on various Intel SoCs.
Add very basic support for taking an lpss device out of reset.
Signed-off-by: Simon Glass
---
Changes in v6: None
Changes in v5: None
Changes in v4:
- Add support for updating power state
- Move this to intel_common
Changes in v3: None
Changes
In TPL we want to reduce code size and support running with CONFIG_PCI
disabled. Add special code to handle this using a fixed BAR programmed
into the SPI on boot. Also cache the SPI flash to speed up boot.
Signed-off-by: Simon Glass
---
Changes in v6:
- Add a comment about why we should not
Add support for Apollo Lake to the ICH driver. This involves adjusting the
mmio address and skipping setting of the bbar.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v6: None
Changes in v5: None
Changes in v4:
- apollolake -> Apollo Lake
Changes in v3: None
Changes in v2:
Apollo Lake (APL) only supports hardware sequencing. Add support for this
into the SPI driver, as an option.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v6:
- Add a comment as to why dev_read_bool() is not used
Changes in v5: None
Changes in v4:
- Fix comment for
Add this method so that the memory-mapped location of the SPI flash can
be queried.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v6: None
Changes in v5: None
Changes in v4:
- Use the new pci_ofplat_get_devfn() function
Changes in v3: None
Changes in v2: None
We don't want to include dt-structs.h in header files, so add a note about
that.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v6: None
Changes in v5: None
Changes in v4:
- Add a patch to explain of-platdata and header files
Changes in v3: None
Changes in v2: None
The Intel Fast SPI interface is similar to ICH. Add of-platdata support
for this using the "intel,fast-spi" compatible string.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v6: None
Changes in v5: None
Changes in v4:
- Use the new pci_ofplat_get_devfn() function
Changes in
This incorrectly shortens read operations if there is a maximum write size
but no maximum read size. Fix it.
Signed-off-by: Simon Glass
---
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
drivers/spi/ich.c | 8 +---
1 file changed, 5
Use debug() instead of printf() to reduce code size and change a bool
return value to the use the 'bool' type. Also drop the global data
declaration since it not actually used. Finally, set the log category.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v6: None
Changes in
Move the header files into the right order.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
drivers/spi/ich.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git
Use dev_get_driver_data() to obtain the device type. It has the same
effect and is shorter.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
drivers/spi/ich.c | 22 +-
It is useful to store the mmio base in platdata. It reduces the amount of
casting needed. Update the code and move the struct to the C file at the
same time, as we will need to use with of-platdata.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v6: None
Changes in v5: None
Reduce the size of the probe function but putting this code into its own
function.
Also remove the assumption that the PCH is always a parent of the SPI
controller, as this is not the case APL platforms. Use driver model to
find the PCH instead.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
We don't normally need this on x86 unless the size of SPI flash devices is
larger than 16MB. This can be enabled by particular SoCs as needed, since
it adds to code size.
Drop the default enabling of this option on x86.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v6: None
This is used on several boards so add it to the common file. Also add a
useful power-limit value while we are here.
Reviewed-by: Bin Meng
Signed-off-by: Simon Glass
---
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
At present binman does not support updating a device tree that is part of
U-Boot (i.e u-boot.bin). Separate the entries into two so that we can get
updated entry information. This makes binman_entry_find() work correctly.
Do the same for SPL tool.
In both cases, group the two parts into a
It is annoying to have some of the init code in a different part of the
file. Move ich_init_controller() to just above probe() to keep things
together.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes
At present we have to have an xfer() method even if it does nothing. This
is not correct, so fix it.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
drivers/spi/ich.c| 9 +
At present if SPL sets up the microcode then it is still included in
U-Boot as well. This is wasteful as microcode is large. Adjust the logic
in the image to prevent this.
Reviewed-by: Bin Meng
Signed-off-by: Simon Glass
---
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes
The existing work-around for positioning U-Boot in the ROM when it
actually runs from RAM still exists and there is not obvious way to change
this.
Add a proper Kconfig option to handle this case. This also adds a new bool
property to indicate whether CONFIG_SYS_TEXT_BASE exists.
Signed-off-by:
The current 'fsp' command only works with FSP1. Update it to handle FSP2
as well. Convert everything to hex which is what U-Boot uses.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v6: None
Changes in v5: None
Changes in v4:
- Explain why FSP-M cannot be shown
- Use hex for
For Apollo Lake SPL is run from CAR (cache-as-RAM) which is in a different
location from where SPL must be placed in ROM. In other words, although
SPL runs before SDRAM is set up, it is not execute-in-place (XIP).
Add a Kconfig option for the ROM position.
Signed-off-by: Simon Glass
Add these entries to the ROM so that we can list the contents of an image
with 'binman ls'. The image-header is not essential but does speed up
access.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes
Include the IFWI section and the FSP-M binary. The FSP-T binary is not
currently used, as CAR is set up manually.
Also drop the FSP binary as this relates only to FSP1.
Reviewed-by: Bin Meng
Signed-off-by: Simon Glass
---
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in
Newer Intel SoCs have different ways of setting up cache-as-ram (CAR).
Add support for these along with suitable configuration options.
To make the code cleaner, adjust a few definitions in processor.h so that
they can be used from assembler.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
At present we don't support loading microcode with FSP2. The correct way
to do this is by adding it to the FIT. For now, disable including
microcode in the image.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3:
-
The fsp_notify() API is the same for FSP1 and FSP2. Move it into a new
common API file.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v6: None
Changes in v5: None
Changes in v4:
- Drop incorrect coreboot reference from header file
Changes in v3: None
Changes in v2: None
Many Intel SoCs require a FIT in order to boot properly. Add an option to
include this and enable it by default.
This term can be confused with FIT (Flat Image Tree) in U-Boot so the
CONFIG option has to include 'X86'.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v6: None
We don't generally have enough space to run this, so don't build it into
TPL. This helps reduce the size of TPL.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
arch/x86/lib/Makefile | 2
With FSP2 we need to run silicon init early after relocation. Add a new
hook for this.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
common/board_r.c | 3 +++
include/init.h | 11
The FSP-S may do this but at least for coral it does not. Set this up so
that graphics is not deathly slow.
It isn't clear whether the FSP is expected to set up MTRR. It is not
mentioned in the APL FSP document.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v6: None
Changes
Add support for some important configuration options and FSP memory init.
The memory init uses swizzle tables from the device tree.
Support for the FSP_S binary is also included.
Bootstage timing is used for both FSP_M and FSP_S and memory-mapped SPI
reads.
Signed-off-by: Simon Glass
---
This generic FSP file should include the generic FSP support header, not
the FSP1 version. Fix it.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
arch/x86/lib/fsp/fsp_support.c | 2 +-
1
FSP-S is used by the notify call after it has been used for silicon init.
To avoid having to load it again, add a field to store the location.
Reviewed-by: Bin Meng
Signed-off-by: Simon Glass
---
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2:
These drivers are not needed on all platforms. While they are small, it
is useful in TPL to drop then. Add Kconfig control to allow this.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2:
- Change
Set up MTRRs for the FSP SDRAM regions to improve performance.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v6: None
Changes in v5:
- Fix FST typo
Changes in v4: None
Changes in v3:
- Move mtrr_add_request() call into this patch
Changes in v2: None
At present the interrupt table is included in all phases of U-Boot. Allow
it to be omitted, e.g. in TPL, to reduce size.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3:
- Move write_pirq_routing_table() to avoid
We don't want to pull in libfdt if of-platdata is being used, since it
reduces the available code-size saves. Also, SPI flash is seldom needed
in TPL.
Drop these options.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes
Both versions of FSP can use the same graphics support, so move it into
the common directory.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
arch/x86/lib/fsp/Makefile | 3
At present with fsp a single DRAM bank is added which extends to the
whole size of memory. However there is typically only 2GB of memory
available below the 4GB boundary, and this is what is used by U-Boot while
running in 32-bit mode.
Scan the tables to set the banks correct. The first bank is
This function needs to be different for FSP2, so move the existing
function into the fsp1 directory. Since it is only called from one file,
drop it from the header file.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in
Add support for a second cache type, for Apollo Lake.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v6: None
Changes in v5: None
Changes in v4:
- apollolake -> Apollo Lake
Changes in v3:
- Move the mrccache_get_region() change into this patch
Changes in v2: None
With Apollo Lake we need to support a normal cache, which almost never
changes and a much smaller 'variable' cache which changes every time.
Update the code to add a cache type, use an array for the caches and use a
for loop to iterate over the caches.
Signed-off-by: Simon Glass
Reviewed-by:
This function is only used within the implementation so make it static.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v6: None
Changes in v5: None
Changes in v4:
- Add new patch to make mrccache_update() static
Changes in v3: None
Changes in v2: None
At present we reuse the mrc_output char * to also point to the cache
record after it has been set up. This is confusing and doesn't save much
data space.
Add a new mrc_cache member instead.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v6: None
Changes in v5: None
Changes in
This function is a bit confusing at present due to the error handling.
Update it to remove the goto, returning errors as they happen.
While we are here, use hex for the data size since this is the norm in
U-Boot.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v6: None
Changes
Change the algorithm to first find the flash device then read the
properties using the livetree API. With this change the device is not
probed so this needs to be done in mrccache_save().
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v6: None
Changes in v5: None
Changes in
This should take account of the end of the new cache record since a record
cannot extend beyond the end of the flash region. This problem was not
seen before due to the alignment of the relatively small amount of MRC
data.
But with Apollo Lake the MRC data is about 45KB, even if most of it is
At present the records are 4KB in size. This is unnecessarily large when
the SPI-flash erase size is 256 bytes. Reduce it so it will be more
efficient with Apollo Lake's 24-byte variable-data record.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v6: None
Changes in v5: None
It is now possible to obtain the memory map for a SPI controllers instead
of having it hard-coded in the device tree. Update the code to support
this.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in
Add a sandbox driver and PCI-device emulator for p2sb. Also add a test
which uses a simple 'adder' driver to test the p2sb functionality.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v6:
- Correct a few unrelated defconfig changes
- Drop unwanted debug printf()
Changes in
When reseting sandbox for tests, disable mmio support since that is the
default state.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v6: None
Changes in v5: None
Changes in v4:
- Split out into a separate patch
Changes in v3: None
Changes in v2: None
Update this uclass to support the needs of the Apollo Lake ITSS. It
supports four operations.
Move the uclass into a separate directory so that sandbox can use it too.
Add a new Kconfig to control it and enable this on x86.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v6:
Add a simple sandbox test for this uclass.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v6:
- Move setting of CONFIG_IRQ in sandbox to this patch
Changes in v5: None
Changes in v4:
- Drop itss uclass change in Makefile (now in previous patch)
- Drop sandbox defconfig change
Define this symbol so that we can use binman symbols correctly.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
arch/x86/cpu/u-boot-spl.lds | 5 -
1 file changed, 4 insertions(+), 1
The Primary-to-Sideband bus (P2SB) is used to access various peripherals
through memory-mapped I/O in a large chunk of PCI space. The space is
segmented into different channels and peripherals are accessed by
device-specific means within those channels. Devices should be added in
the device tree
Add a simple PMC for sandbox to permit tests to run.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3:
- Rename power-mgr uclass to acpi-pmc
- Tidy up Makefile rules to reduce duplication
Changes in v2: None
Intel x86 SoCs have a power manager/controller which handles several
power-related aspects of the platform. Add a uclass for this, with a few
useful operations.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v6: None
Changes in v5: None
Changes in v4:
- Fix alpha order in
We don't expect an exception in TPL and don't need to set up interrupts in
TPL. Drop this whole file.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v6: None
Changes in v5: None
Changes in v4:
- Drop the whole interrupt file for TPL
Changes in v3: None
Changes in v2: None
We don't need to know every detail about the CPU in TPL. Drop some
superfluous functions to reduce code size. Add a simple CPU detection
algorithm which just supports Intel and AMD, since we only support TPL
on Intel, so far.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v6:
These warnings appear every thing sandbox is run (see below) and dwarf the
actual useful output. Suppress them in two ways:
1. For the mismatch warnings, only set the ethaddr environment
variables when running tests.
2. For the 'MAC address from ROM' warning, never print this on sandbox.
This reverts commit 96ac4def8b6686de8566b91419ce98cd5765079b.
Signed-off-by: Simon Glass
---
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
arch/sandbox/cpu/state.c | 12 ++--
arch/sandbox/include/asm/state.h | 5 +
Most of the timer-calibration methods are not needed on recent Intel CPUs
and just increase code size. Add an option to use the known-good way to
get the clock frequency in TPL. Size reduction is about 700 bytes.
Note that version 1 of this commit caused bootstage to crash since the CPU
was not
On x86 platforms the timer is reset to 0 when the SoC is reset. Having
this as the timer base is useful since it provides an indication of how
long it takes before U-Boot is running.
When U-Boot sets the timer base to something else, time is lost and we
no-longer have an accurate account of the
At present the early timer init happens as soon as driver model is set up.
This makes it impossible to do anything that needs driver model but must
run before devices are probed (as needed with Intel's FSP-S, for example).
In any case it is not a good idea to tie probing of particular drivers too
At present these options cannot be enabled for SPL/TPL, but this can be
useful in some cases. Add Kconfig options to allow it.
Signed-off-by: Simon Glass
---
Changes in v6:
- Split out Kconfig change to new patch to enable full pinctrl in SPL/TPL
Changes in v5: None
Changes in v4: None
Changes
Drivers are not allowed to use static data since they may be used in SPL
where BSS is not available.
It is possible that driver model may provide support for numbering devices
in the future. But for now, move this to global_data.
Signed-off-by: Simon Glass
---
Changes in v6: None
Changes in
Allow this driver to set up an IO address in SPL using an 'early-regs'
property. This allows SPL to use the I2C driver without having to enable
the full PCI stack.
Also split out ofdata_to_platdata in designware driver since this is more
correct, and more convenient for the new logic.
Most x86 CPUs use a mechanism where the SPI flash is mapped into the very
top of 32-bit address space, so that it can be executed in place and read
simply by copying from memory. For an 8MB ROM the mapping starts at
0xff80.
However some recent Intel CPUs do not use a simple 1:1 memory map.
When device-tree compilation fails it is sometimes tricky to see which
line is broken, since the input file to dtc is a pre-processed version
of the device tree.
Add a line that points to the file that needs to be checked:
When the error is in the main .dts file, output is something like this:
This is hacked into the driver at present. It seems better to have it as
a separate driver that uses the base driver. Create a new file and put
the X86 code into it.
Actually the Baytrail settings should really come from the device tree.
Note that 'has_max_speed' is added as well. This is
These functions are used by code outside the network support, so move them
to lib/ to be more accessible.
Without this, the functions are only accessible in SPL/TPL only if
CONFIG_SPL/TPL_NET are defined. Many boards do not enable those option but
still want to do checksums in this format.
Fix
Early in boot it is necessary to decode the PCI device/function values for
particular peripherals in the device tree or of-platdata. This is needed
in TPL where CONFIG_PCI is not defined.
To handle this, move pci_get_devfn() into a file that is built even when
CONFIG_PCI is not defined.
Also add
At present if CONFIG_SPL_GPIO_SUPPORT is enabled then the GPIO uclass
is included in SPL/TPL without any control for boards. Some boards may
want to disable this to reduce code size where GPIOs are not needed in
SPL or TPL.
Add a new Kconfig option to permit this. Default it to 'y' so that
At present PCI auto-configuration happens in U-Boot both before and after
relocation. This is a waste of time and may mess up static addresses used
in board_init_f(). Adjust the code to supporting doing auto-configuration
once, after relocation, under control of a device-tree property.
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