Hi,
> From: U-Boot On Behalf Of Simon Glass
> Sent: jeudi 9 janvier 2020 21:04
>
> On Thu, 9 Jan 2020 at 09:35, Anatolij Gustschin wrote:
> >
> > With some device trees (i.e. i.MX6 SoC) and longer REMOVE_PROPS list
> > the fdtgrep tool stops with "Internal error with fdtgrep_find_regions()".
>
Adjust load address of Image(uncompressed)
from 0x8100 to 0x9600.
It will get rid of error message from uboot
when boot kernel with booti command as follows:
- ERROR: reserving fdt memory region failed (addr=8340 size=c0)
For example:
The Image of linux kernel is growing quite quic
Adjust load address(kernel_addr_r) of Image(uncompressed)
from 0x8100 to 0x9600.
It will get rid of error message from uboot
when boot kernel with booti command as follows:
- ERROR: reserving fdt memory region failed (addr=8340 size=c0)
For example:
The Image of linux kernel is
Update the loop executed in do_fdtgrep to find all the regions
and add a test for count > max_region only when the second passes
is executed.
This patch solve an issue if the number of region found (count)
is greater then the default value (max_region = count = 100):
the second pass is never execu
>
> >-Original Message-
> >From: U-Boot On Behalf Of Biwen Li
> >Sent: Friday, January 10, 2020 7:27 AM
> >To: Priyanka Jain ; Jagdish Gediya
> >; Anji Jagarlmudi
> >Cc: u-boot@lists.denx.de; Jiafei Pan ; Xiaobo Xie
> >
> >Subject: [PATCH 2/2] include/configs: ls1012afrwy: adjust kernel_
>
>
> >-Original Message-
> >From: U-Boot On Behalf Of Biwen Li
> >Sent: Friday, January 10, 2020 7:27 AM
> >To: Priyanka Jain ; Jagdish Gediya
> >; Anji Jagarlmudi
> >Cc: u-boot@lists.denx.de; Jiafei Pan ; Xiaobo Xie
> >
> >Subject: [PATCH 1/2] include/configs: ls1012ardb: adjust kerne
Fix the following in intel_gpio_get_value():
* The value of the register is contained in the variable 'reg', not in
'mode'. The variable 'mode' contains only the configuration whether
the gpio is currently an input or an output.
* The correct bitmasks for the input and output value are
Add missing 'PAD_CFG0_TX_STATE' to the clear mask for pcr_clrsetbits32().
Otherwise this bit cannot be cleared again after it has been set once.
Signed-off-by: Wolfgang Wallner
---
drivers/gpio/intel_gpio.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpio/intel_g
This series fixes some issues in the Intel gpio driver.
I have tested it on an Apollo Lake device, where U-Boot is booted as a
coreboot payload.
Wolfgang Wallner (3):
gpio: intel_gpio: Pass pinctrl device to pcr_clrsetbits32()
gpio: intel_gpio: Clear tx state bit when setting output
gpio:
The function pcr_clrsetbits32() expects a device with a P2SB parent
device.
The currently passed device 'dev' is a gpio-controller with a device
'pinctrl' as parent. This does not match the expectations of
pcr_clrsetbits32(). But he 'pinctrl'-device has a P2SB as parent.
Pass the 'pinctrl' device
Use the correct protocol in efi_uc_stop() when detaching the driver from
the controller.
Change the block IO unit test for the block device driver to throw an error
instead of a todo if teardown fails.
Signed-off-by: Heinrich Schuchardt
---
lib/efi_driver/efi_uclass.c | 7 -
On 09.01.20 17:30, Gregory CLEMENT wrote:
Now that CONFIG_SPL_SEPARATE_BSS is selected for all the AT91 based
boards, cleanups the defconfigs by removing it.
Signed-off-by: Gregory CLEMENT
---
configs/gardena-smart-gateway-at91sam_defconfig | 1 -
configs/sama5d27_som1_ek_mmc1_defconfig
On 09.01.20 17:30, Gregory CLEMENT wrote:
According to the linker script for both armv7 and arm926ejs based SoC,
BSS section was all the time separated for SPL but this symbol was
only enabled on some boards. However, it is necessary to have it
enabled for OF_SEPARATE configuration where DTB is a
Hi Mauro,
On 09.01.20 18:28, Mauro Condarelli wrote:
I managed to brick my target.
Situation:
I have a board with a paleolithic (1.1.3) version of u-boot.
I had been testing by loading in ram from USB:
usb reset; fatload usb 0 8001 u-boot.bin; go 8001
and everything was ok.
I chang
On Fri, Jan 10, 2020 at 1:05 PM Marek Vasut wrote:
>
> On 1/10/20 3:45 AM, Masahiro Yamada wrote:
> > On Fri, Jan 10, 2020 at 9:14 AM Marek Vasut wrote:
> >>
> >> While the Denali NAND is initialized by the BootROM in SPL, there
> >> are still a couple of settings which are missing.
> >
> >
> > T
In Cyclone 5 SoC platform, the first USB probing is failed but second
probing is success. DWC2 USB driver read gsnpsid register right after
de-assert reset, but controller is not ready yet and it returns gsnpsid 0.
Polling reset status after de-assert reset to solve the issue.
Retry with this fix
On Fri, Jan 10, 2020 at 1:05 PM Marek Vasut wrote:
>
> On 1/10/20 4:09 AM, Masahiro Yamada wrote:
> > On Fri, Jan 10, 2020 at 9:14 AM Marek Vasut wrote:
> >>
> >> The Denali NAND block loses configuration when put in reset.
> >> Specifically, RB_PIN_ENABLED, CHIP_ENABLE_DONT_CARE,
> >> SPARE_AREA
On 1/10/20 4:09 AM, Masahiro Yamada wrote:
> On Fri, Jan 10, 2020 at 9:14 AM Marek Vasut wrote:
>>
>> The Denali NAND block loses configuration when put in reset.
>> Specifically, RB_PIN_ENABLED, CHIP_ENABLE_DONT_CARE,
>> SPARE_AREA_SKIP_BYTES and SPARE_AREA_MARKER are lost.
>> Since mainline Linu
On 1/10/20 3:45 AM, Masahiro Yamada wrote:
> On Fri, Jan 10, 2020 at 9:14 AM Marek Vasut wrote:
>>
>> While the Denali NAND is initialized by the BootROM in SPL, there
>> are still a couple of settings which are missing.
>
>
> This statement is wrong.
>
> While the Denali NAND is initialized by
On Fri, Jan 10, 2020 at 9:14 AM Marek Vasut wrote:
>
> The Denali NAND block loses configuration when put in reset.
> Specifically, RB_PIN_ENABLED, CHIP_ENABLE_DONT_CARE,
> SPARE_AREA_SKIP_BYTES and SPARE_AREA_MARKER are lost.
> Since mainline Linux depends on the configuration programmed
> into t
On Fri, Jan 10, 2020 at 9:14 AM Marek Vasut wrote:
>
> The Denali NAND block loses configuration when put in reset.
> Specifically, RB_PIN_ENABLED, CHIP_ENABLE_DONT_CARE,
> SPARE_AREA_SKIP_BYTES and SPARE_AREA_MARKER are lost.
> Since mainline Linux depends on the configuration programmed
> into t
> -Original Message-
> From: Marek Vasut
> Sent: Thursday, January 9, 2020 10:44 PM
> To: Tan, Ley Foon ; u-boot@lists.denx.de
> Cc: Simon Goldschmidt ; Simon Glass
> ; Joe Hershberger ; Ley
> Foon Tan ; See, Chin Liang
> ; Chee, Tien Fong
> Subject: Re: [PATCH v4] reset: socfpga: Poll
On Fri, Jan 10, 2020 at 9:14 AM Marek Vasut wrote:
>
> While the Denali NAND is initialized by the BootROM in SPL, there
> are still a couple of settings which are missing.
This statement is wrong.
While the Denali NAND is initialized by the BootROM,
the SOCFPGA SPL calls socfpga_per_reset_all(
Adjust load address of Image(uncompressed).
It will get rid of error message from uboot
when boot kernel with booti command as follows:
- ERROR: reserving fdt memory region failed (addr=8340 size=c0)
For example:
The Image of linux kernel is growing quite quickly,
if Image size is 40 M
Adjust load address of Image(uncompressed).
It will get rid of error message from uboot
when boot kernel with booti command as follows:
- ERROR: reserving fdt memory region failed (addr=8340 size=c0)
For example:
The Image of linux kernel is growing quite quickly,
if Image size is 40 MiB,
Since commit 067e0b9684d4 ("sunxi: Allow booting from 128KB SD/eMMC offset")
we support having the SPL loaded from either the traditional 8KB SD
card/eMMC offset, or from the alternative location at 128KB. However the
sector to find the U-Boot image was still hard-coded at compile time,
and had to
The Allwinner Boot ROM on all later SoCs can load the initial SPL code
from offset 128KB or from offset 8KB of an SD card or eMMC.
We support this in the SPL for a while now, but so far needed to manually
adjust the U-Boot image MMC load sector during compile time.
Since the Boot ROM writes a diff
The Boot ROM write some boot source ID (SD card, eMMC, SPI, ...) into
a certain location in SRAM, so the SPL can easily determine where to
load U-Boot proper from.
Factor out reading this value, as it will come in handy again shortly.
Signed-off-by: Andre Przywara
---
arch/arm/mach-sunxi/board.c
Hello Simon,
We would like to get clarification on the expected return of do_gpio()?
Should it be returning function execution status or the value of the GPIO?
Thanks
Alex
> Subject: [PATCH 1/2] clk: imx8qxp: extend to support getting I2C IPG clock
>
> Since commit d02be21d3004 ("i2c: imx_lpi2c: add ipg clk") getting I2C clocks
> doesn't work. Add I2C IPG clock IDs to related switch statements to fix it.
>
> Signed-off-by: Anatolij Gustschin
> Cc: Lukasz Majewski
On 1/9/20 5:56 PM, Patrick DELAUNAY wrote:
> Hi Marek,
>
>> From: Marek Vasut
>> Sent: jeudi 9 janvier 2020 15:27
>>
>> On 1/9/20 2:50 PM, Patrick DELAUNAY wrote:
>>> Hi Marek,
>>
>> Hi,
>>
From: Marek Vasut
Sent: mercredi 18 décembre 2019 07:58
To: u-boot@lists.denx.de
Cc: M
Add support for DH Electronics DHCOM SoM and PDK2 rev. 400 carrier
board. This is an SoM with STM32MP157C and an evaluation kit. The
baseboard provides Ethernet, UART, USB, CAN and optional display.
Signed-off-by: Marek Vasut
Cc: Patrick Delaunay
Cc: Patrice Chotard
---
arch/arm/dts/Makefile
Add missing 'eth-ck' clock to the ethernet node. These clock are used to
generate external clock signal for the PHY in case 'st,eth_ref_clk_sel'
is specified.
Signed-off-by: Marek Vasut
Cc: Patrick Delaunay
Cc: Patrice Chotard
---
arch/arm/dts/stm32mp157c.dtsi | 2 ++
1 file changed, 2 inserti
Let board code override setup_mac_address(), which is useful e.g. if the
board derives the MAC address from another source, like an I2C EEPROM.
Signed-off-by: Marek Vasut
Cc: Patrick Delaunay
Cc: Patrice Chotard
---
V2: Add prototype to sys_proto.h
---
arch/arm/mach-stm32mp/cpu.c
Setting TARGET_STM32MP1 in Kconfig always forces SYS_BOARD, SYS_VENDOR
and SYS_CONFIG_NAME to values set by the ST reference platforms. Allow
changing that by pulling out the TARGET_STM32MP157C_DK2 and making the
ST reference platform settings conditional on TARGET_STM32MP157C_DK2 .
Other platforms
Since CONFIG_LOADADDR is not set, the default value of $loadaddr
variable is not set in the environment either. Set the default
load address to 256 MiB from the start of DRAM.
Signed-off-by: Marek Vasut
Cc: Patrick Delaunay
Cc: Patrice Chotard
---
include/configs/stm32mp1.h | 1 +
1 file chang
Not all systems have all the boot devices enabled, e.g. not all systems
have MTD devices and thus do not enable UBI. Make all the boot devices
in the distro bootcmd conditional to avoid failures.
Signed-off-by: Marek Vasut
Cc: Patrick Delaunay
Cc: Patrice Chotard
---
V2: Drop the _DEVICE from B
Not all systems have all the boot devices enabled, e.g. not all systems
have MTD devices and thus do not enable UBI. Make all the boot devices
in the distro bootcmd conditional to avoid failures.
Signed-off-by: Marek Vasut
Cc: Patrick Delaunay
Cc: Patrice Chotard
---
V2: Drop the _DEVICE from B
On 1/9/20 4:36 PM, Masahiro Yamada wrote:
> On Thu, Jan 9, 2020 at 10:20 PM Marek Vasut wrote:
>>
>> On 1/9/20 1:02 PM, Masahiro Yamada wrote:
>>> The "nand_x" and "ecc" clocks are currently optional. Make the core
>>> clock optional in the same way. This will allow platforms with no clock
>>> dri
From: Masahiro Yamada
The "nand_x" and "ecc" clocks are currently optional. Make the core
clock optional in the same way. This will allow platforms with no clock
driver support to use this driver.
Signed-off-by: Masahiro Yamada
Tested-by: Marek Vasut # On SoCFPGA Arria V
---
drivers/mtd/nand/
The Denali NAND block loses configuration when put in reset.
Specifically, RB_PIN_ENABLED, CHIP_ENABLE_DONT_CARE,
SPARE_AREA_SKIP_BYTES and SPARE_AREA_MARKER are lost.
Since mainline Linux depends on the configuration programmed
into the Denali NAND controller by the bootloader, do not
reset the co
While the Denali NAND is initialized by the BootROM in SPL, there
are still a couple of settings which are missing. These can trigger
subtle corruption of the data read out of the NAND. Fill these
settings in just like they are filled in by the full Denali NAND
driver in denali_hw_init().
Signed-o
On 1/9/20 4:01 PM, Masahiro Yamada wrote:
> On Thu, Jan 9, 2020 at 11:48 PM Marek Vasut wrote:
>>
>> On 1/9/20 1:11 PM, Masahiro Yamada wrote:
>>> On Thu, Jan 9, 2020 at 8:16 PM Marek Vasut wrote:
On 1/9/20 12:04 PM, Masahiro Yamada wrote:
> On Thu, Jan 9, 2020 at 7:08 PM Marek Vasu
SFI is quite poor and useless resource provider. Moreover it makes hard
to develop and extend functionality in the Linux kernel.
Enable a necessary minimum to use ACPI on Intel Edison.
Linux kernel have been prepared for this change since v5.4, where the last
crucial driver, i.e. for Basin Cove P
From: Marek Vasut
Enable command line editing, because it is extremely convenient.
Signed-off-by: Marek Vasut
Signed-off-by: Andy Shevchenko
---
configs/edison_defconfig | 1 -
1 file changed, 1 deletion(-)
diff --git a/configs/edison_defconfig b/configs/edison_defconfig
index 14b2eec3ba..12
Hi Cédric,
On Tue, 7 Jan 2020 at 21:20, Cédric Le Goater wrote:
>
> On 12/30/19 5:19 AM, Simon Glass wrote:
> > At present the clock driver reads its ofdata in the probe() method. This
> > is not correct although it is often harmless.
> >
> > However in this case it causes a problem, something li
On Thu, 9 Jan 2020 at 09:35, Anatolij Gustschin wrote:
>
> With some device trees (i.e. i.MX6 SoC) and longer REMOVE_PROPS list
> the fdtgrep tool stops with "Internal error with fdtgrep_find_regions()".
> Increase 'max_regions' count to avoid such errors.
>
> Signed-off-by: Anatolij Gustschin
>
On Thu, 9 Jan 2020 at 09:35, Anatolij Gustschin wrote:
>
> Fix function name and parenthesis.
>
> Signed-off-by: Anatolij Gustschin
> ---
> tools/fdtgrep.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Simon Glass
Hi Giulio,
On Thu, 9 Jan 2020 at 06:53, Giulio Benetti
wrote:
>
> Hi Simon,
>
> On 1/8/20 6:39 PM, Simon Glass wrote:
> > Hi Giulio,
> >
> > On Tue, 7 Jan 2020 at 10:23, Giulio Benetti
> > wrote:
> >>
> >> Hi Stefano, Simon, All,
> >>
> >> On 1/3/20 12:39 PM, Stefano Babic wrote:
> >>> Hi Giulio
On Thu, Jan 09, 2020 at 08:09:27PM +0100, Heinrich Schuchardt wrote:
> On 1/9/20 9:02 AM, Ilias Apalodimas wrote:
> > On Thu, Jan 09, 2020 at 01:08:35AM +0100, Heinrich Schuchardt wrote:
> > > On 12/18/19 1:44 AM, AKASHI Takahiro wrote:
> > > > One of major missing features in current UEFI implemen
Add the missing Sphinx documentation.
Signed-off-by: Heinrich Schuchardt
---
doc/api/efi.rst | 6 ++
lib/efi_loader/efi_rng.c | 35 +++
2 files changed, 41 insertions(+)
diff --git a/doc/api/efi.rst b/doc/api/efi.rst
index 2ca344932e..bc59382608 100
On Tue, 24 Dec 2019 at 12:55, Sam Protsenko wrote:
>
> Enable Android commands that will be needed for Android 10 boot flow
> implementation, for all AM57x variants. Commands enabled:
>
> 1. 'abootimg':
> - CONFIG_CMD_ABOOTIMG=y
> 2. 'ab_select':
> - CONFIG_ANDROID_AB=y
> - CONF
On Mon, 6 Jan 2020 at 15:00, Anatolij Gustschin wrote:
>
> Fix:
> >>> CID 280902: Control flow issues (MISSING_BREAK)
> >>> The case for value "VIDEO_BPP32" is not terminated
> >>> by a 'break' statement.
>
> Reported-by: Tom Rini
> Signed-off-by: Anatolij Gustschin
> ---
> drivers/video/v
On Tue, 24 Dec 2019 at 12:55, Sam Protsenko wrote:
>
> Unit test for 'abootimg' command. Right now it covers dtb/dtbo
> functionality in Android Boot Image v2, which was added recently.
>
> Running test:
>
> $ ./test/py/test.py --bd sandbox --build -k test_abootimg
>
> shows that 1/1 tests pas
On Tue, 24 Dec 2019 at 12:55, Sam Protsenko wrote:
>
> Describe Android Boot Image format, how its support is implemented in
> U-Boot and associated commands usage.
>
> Signed-off-by: Sam Protsenko
> ---
> cmd/Kconfig| 2 +
> doc/android/boot-image.rst | 154 +++
Use valid restructured text to avoid warnings like
WARNING: Title underline too short.
WARNING: Block quote ends without a blank line; unexpected unindent.
when building with `make htmldocs`.
Signed-off-by: Heinrich Schuchardt
---
doc/board/google/chromebook_coral.rst | 90 ++--
On 1/9/20 9:02 AM, Ilias Apalodimas wrote:
On Thu, Jan 09, 2020 at 01:08:35AM +0100, Heinrich Schuchardt wrote:
On 12/18/19 1:44 AM, AKASHI Takahiro wrote:
One of major missing features in current UEFI implementation is "secure boot."
The ultimate goal of my attempt is to implement image authen
On Thu, Jan 09, 2020 at 07:03:34AM +0100, Mario Six wrote:
> Hi Tom,
>
> A small PR with MC8309 fixes from Rasmus.
>
> CI: https://travis-ci.com/si-gdsys/u-boot-mpc83xx/builds/143550229
>
> The following changes since commit d8a3f5259a36e76d1de127f65714c40918e8ee4c:
>
> Merge tag 'u-boot-imx
All rockchip platforms support TPL or SPL-based bootloader
in mainline with U-Boot proper as final stage. For each
stage we need to burn the image on to flash with respective
offsets.
This patch creates a single boot image component using
- binman, for arm32 rockchip platforms
- pad_cat, for arm64
Rockchip has documentation file, doc/README.rockchip but
which is not so readable to add or understand the existing
contents. Even the format that support is legacy readme
in U-Boot.
Add rockchip specific documentation file using new rst
format, which describes the information about Rockchip
suppo
Add SPL-alone mkimage tooling support via Makefile for
few platforms or boards used in rockchip family.
With this users would get rid of explicitly creating
mkimage tool for rockchip rksd or rkspi boot modes.
Signed-off-by: Jagan Teki
Reviewed-by: Kever Yang
---
Makefile | 10 +-
1 fil
Add U-Boot specific dtsi file for rk3188 SoC. This
would help to add U-Boot specific dts nodes, properties
which are common across rk3188.
Right now, the file is empty, will add required changes
in future patches.
Signed-off-by: Jagan Teki
---
arch/arm/dts/rk3188-radxarock-u-boot.dtsi | 2 ++
a
Add U-Boot specific dtsi file for rk3036 SoC. This
would help to add U-Boot specific dts nodes, properties
which are common across rk3036.
Right now, the file is empty, will add required changes
in future patches.
Signed-off-by: Jagan Teki
Reviewed-by: Kever Yang
---
arch/arm/dts/rk3036-sdk-u-
This is v7 set for Binman support in rockchip, [1] here is
previous patchset.
This series add single boot image with binman for arm32 and
pad_cat for arm64 rockchip platforms both TPL + SPL and SPL-alone
targets.
Changes for v7:
- fix rock board
- fix phycore-rk3288 size blow issue
Changes for v6
Add rockchip image type support. right now the image
type marked with rksd, So create image type variable
with required image type like rksd or rkspi.
Cc: Matwey V. Kornilov
Signed-off-by: Jagan Teki
Reviewed-by: Kever Yang
---
Makefile | 10 +-
1 file changed, 9 insertions(+), 1 delet
Most of the platforms uses the platform type on their boot
stage image naming conventions in makefile like,
u-boot-x86-start16-tpl.bin - x86 start16 TPL bin
u-boot-spl-mtk.bin - Mediatek SPL bin
This would help to understand the users to what that
particular image belongs to? and less confused.
On Thu, Jan 9, 2020 at 8:58 PM Wadim Egorov wrote:
>
> Hi Jagan,
>
> On 09.01.20 14:59, Jagan Teki wrote:
> > On Wed, Jan 8, 2020 at 5:04 PM Wadim Egorov wrote:
> >> Hi,
> >>
> >> On 07.01.20 10:59, Kever Yang wrote:
> >>> Add Wadim in cc,
> >>>
> >>> Hi Jagan,
> >>>
> >>> After this patch set ap
Fastboot specification [1] requires MMC to be filled with 0xFF's on
"fastboot erase" command:
erase:%s Erase the indicated partition (clear to 0xFFs)
Current "fastboot erase" implementation uses actual MMC erase operation
blk_derase(), which can fill MMC either with 0x00 or 0xFF, de
On Wed, Jan 08, 2020 at 04:32:18PM +0100, Marek Vasut wrote:
> The following changes since commit 5a8fa095cb848c60c630a83edf30d4fc46101e90:
>
> Merge branch 'next' (2020-01-06 17:07:49 -0500)
>
> are available in the Git repository at:
>
> git://git.denx.de/u-boot-usb.git master
>
> for yo
On Wed, Jan 08, 2020 at 11:04:50AM -0700, Simon Glass wrote:
> Hi Tom,
>
> This series has the potential for breakage due to badly written
> drivers, so I'd like to get it in early in the merge window.
>
> Tests here:
>
> https://gitlab.denx.de/u-boot/custodians/u-boot-dm/pipelines/1790
>
>
>
On some i.MX8QXP MEK boards with no MAC address stored, the following
hang is seen:
Error: ethernet@5b04 address not set.
(Board hangs)
One way to avoid this issue is to select CONFIG_NET_RANDOM_ETHADDR, so
that a random MAC is provided and boot proceeds, but the lack of MAC
should not hang
On 1/9/20 3:09 PM, Sughosh Ganu wrote:
Take up maintainership of random number generator drivers with
Heinrich Schuchardt as the reviewer.
Signed-off-by: Sughosh Ganu
---
MAINTAINERS | 7 +++
1 file changed, 7 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 438fb22..a0f1eaf 1
Hi,
Sorry, I forgot to report the Reviewed-by of Miquel Raynal.
> Objet: [PATCH V3 1/2] tpm: add a helper to iterate on all tpm devices
> This add a helper for_each_tpm_device that run
> through all the tpm (1.x and 2.0) devices.
>
> Signed-off-by: Philippe Reynes
Reviewed-by: Miquel Raynal
Hi,
Sorry, I forgot to report the Reviewed-by of Miquel Raynal.
> Objet: [PATCH V3 2/2] cmd: tpm: add a subcommand device
> The command tpm (and tpm2) search the tpm and use it.
> On sandbox, there are two tpm (tpm 1.x and tpm 2.0).
> So the command tpm and tpm2 are always executed with
> the f
On 1/9/20 6:11 PM, Patrick Delaunay wrote:
Add a function reserve_sp() to reserved memory with 16 bits alignment
I guess this is a typo:
%s/bits/bytes/
Best regards
Heinrich
after the stack pointer (gd->start_addr_sp) and use this new function
in board_f.c to reserve all the memory area (m
On Thu, Jan 09, 2020 at 04:10:12PM +0800, Weijie Gao wrote:
> On Wed, 2020-01-08 at 08:22 +0100, Heinrich Schuchardt wrote:
> >
> > On 1/8/20 4:01 AM, Weijie Gao wrote:
> > > This patch enables LZMA decompression support for SPL build
> > >
> > > Signed-off-by: Weijie Gao
> > > ---
> > > lib/Kc
The command tpm (and tpm2) search the tpm and use it.
On sandbox, there are two tpm (tpm 1.x and tpm 2.0).
So the command tpm and tpm2 are always executed with
the first tpm (tpm 1.x), and the command tpm2 always
fails.
This add a subcommand device to command tpm and
command tpm2. Then the command
This add a helper for_each_tpm_device that run
through all the tpm (1.x and 2.0) devices.
Signed-off-by: Philippe Reynes
---
include/tpm-common.h | 3 +++
1 file changed, 3 insertions(+)
Changelog:
v3:
- use the helper uclass_foreach_dev_probe
v2:
- new patch, add an helper for tpm device (idea
I managed to brick my target.
Situation:
I have a board with a paleolithic (1.1.3) version of u-boot.
I had been testing by loading in ram from USB:
usb reset; fatload usb 0 8001 u-boot.bin; go 8001
and everything was ok.
I changed a few settings (both defconfigs are attached below)
an
Hi,
> From: Patrick DELAUNAY
> Sent: mardi 7 janvier 2020 13:07
>
> Hi Patrice and Tom
>
> > Sent: mercredi 18 décembre 2019 10:10
> >
> > Hi Simon,
> >
> > > From: Simon Glass
> > > Sent: mardi 17 décembre 2019 16:46
> > >
> > > Hi Patrice,
> > >
> > > On Wed, 27 Nov 2019 at 02:11, Patrice Cho
This reverts the workaround introduced by the
commit 16fec9b0bc1a ("stm32mp1: remove the imply BOOTSTAGE")
As the bootstage alignment issue is now solved.
Signed-off-by: Patrick Delaunay
---
arch/arm/mach-stm32mp/Kconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/mach-stm32m
Hi,
This serie depends on
http://patchwork.ozlabs.org/patch/1201452/
[U-Boot,v3] board_f.c: Insure gd->new_bootstage alignment reserve_sp
It should be applied only after this patch.
First I remove the stm32mp1 workaround as the issue of bootstage
alignment is solved.
The 3rd patch is a complete
Simplify the arm relocation behavior and get gd directly form new_gd,
as it is already done in crt0_64.S:
ldr x18, [x18, #GD_NEW_GD] /* x18 <- gd->new_gd */
This patch avoid assumption on new GD location (new GD is below bd -
with #GD_SIZE offset).
Signed-off-by: Patrick Del
Add a function reserve_sp() to reserved memory with 16 bits alignment
after the stack pointer (gd->start_addr_sp) and use this new function
in board_f.c to reserve all the memory area (malloc, board, gd, fdt,
bootstage, stacks).
This 16 byte alignment is needed for cast on struct pointer
for the r
Hi Marek,
> From: Marek Vasut
> Sent: jeudi 9 janvier 2020 15:27
>
> On 1/9/20 2:50 PM, Patrick DELAUNAY wrote:
> > Hi Marek,
>
> Hi,
>
> >> From: Marek Vasut
> >> Sent: mercredi 18 décembre 2019 07:58
> >> To: u-boot@lists.denx.de
> >> Cc: Marek Vasut ; Patrick DELAUNAY
> >> ; Patrice CHOTAR
Dear ladys and gentleman,
according the setup in [setup] I want to enable the SIL Image 3124/3132
PCI/SATA converter in UBOOT (u-boot-2018.03) on an IMX6SX CPU.
I tested the implementation and the setup via the Linux Kernel (see Kernel
config in [kernel config] in Linux (see lspci [kernel]).
In the function cmd_ut_category, the prefix is used with
the function strncmp to know if the prefix should be
removed from the test name, even if the prefix is NULL.
To avoid this issue, we consider that a prefix NULL
mean no prefix. So we only try to remove the prefix
from the test_name if the pr
Now that CONFIG_SPL_SEPARATE_BSS is selected for all the AT91 based
boards, cleanups the defconfigs by removing it.
Signed-off-by: Gregory CLEMENT
---
configs/gardena-smart-gateway-at91sam_defconfig | 1 -
configs/sama5d27_som1_ek_mmc1_defconfig | 1 -
configs/sama5d27_som1_ek_mmc_defcon
According to the linker script for both armv7 and arm926ejs based SoC,
BSS section was all the time separated for SPL but this symbol was
only enabled on some boards. However, it is necessary to have it
enabled for OF_SEPARATE configuration where DTB is appended to u-boot
with DTB.
Signed-off-by:
When using fitImage in AARCH64, the fdt is only 4 byte aligned. According
to linux kernel -> Documentation/arm64/booting.txt, the fdt *must* be 8
byte aligned. Therefore, it is somewhat random, if you build a kernel that
the fdt is 4 or 8 byte aligned. Removing fdt_high (or changing it to a
valid 8
When using fitImage in AARCH64, the fdt is only 4 byte aligned.
According to linux kernel -> Documentation/arm64/booting.txt, the
fdt *must* be 8 byte aligned. Therefore, it is somewhat random,
if you build a kernel that the fdt is 4 or 8 byte aligned.
Removing fdt_high (or changing it to a valid
On Thu, Jan 9, 2020 at 10:20 PM Marek Vasut wrote:
>
> On 1/9/20 1:02 PM, Masahiro Yamada wrote:
> > The "nand_x" and "ecc" clocks are currently optional. Make the core
> > clock optional in the same way. This will allow platforms with no clock
> > driver support to use this driver.
> >
> > Signed
Hi Jagan,
On 09.01.20 14:59, Jagan Teki wrote:
> On Wed, Jan 8, 2020 at 5:04 PM Wadim Egorov wrote:
>> Hi,
>>
>> On 07.01.20 10:59, Kever Yang wrote:
>>> Add Wadim in cc,
>>>
>>> Hi Jagan,
>>>
>>> After this patch set apply, the phycore-rk3288 board's SPL size is
>>> overflow:
>>>
>>>arm:
On Thu, 2020-01-09 at 15:57 +0100, Matthias Brugger wrote:
[...]
> The property expects size-cells to be two, but U-Boot will use one
> cell if no
> size-cells are defined in the device node (which is not the case) and
> therefor
> will see
>
> Bank1: Flashbase 0x0 0x0 Flashsize 0x40
On Thu, Jan 9, 2020 at 11:48 PM Marek Vasut wrote:
>
> On 1/9/20 1:11 PM, Masahiro Yamada wrote:
> > On Thu, Jan 9, 2020 at 8:16 PM Marek Vasut wrote:
> >>
> >> On 1/9/20 12:04 PM, Masahiro Yamada wrote:
> >>> On Thu, Jan 9, 2020 at 7:08 PM Marek Vasut wrote:
>
> Legacy kernel versions
[adding Stefan as the maintainer of drivers/mtd/cfi_*]
On 09/01/2020 14:11, Robin Randhawa wrote:
> Hi Matthias.
>
> On Thu, 2020-01-09 at 12:12 +0100, Matthias Brugger wrote:
>
> [...]
>
>> Can you pinpoint me to where I can find the DTS used by U-boot.
>
> As per my understanding the DTB for
On 1/9/20 1:11 PM, Masahiro Yamada wrote:
> On Thu, Jan 9, 2020 at 8:16 PM Marek Vasut wrote:
>>
>> On 1/9/20 12:04 PM, Masahiro Yamada wrote:
>>> On Thu, Jan 9, 2020 at 7:08 PM Marek Vasut wrote:
Legacy kernel versions for SoCFPGA may not implement proper reset
handling. Apply the
On 1/8/20 10:14 AM, Ley Foon Tan wrote:
> In Cyclone 5 SoC platform, the first USB probing is failed but second
> probing is success. DWC2 USB driver read gsnpsid register right after
> de-assert reset, but controller is not ready yet and it returns gsnpsid 0.
> Polling reset status after de-assert
On 1/8/20 12:25 PM, Jagan Teki wrote:
> On Mon, Jan 6, 2020 at 7:44 PM Marek Vasut wrote:
>>
>> Migrate CONFIG_DESIGNWARE_WATCHDOG to Kconfig and update the headers
>> accordingly, no functional change. The S10 enables the WDT only in
>> SPL, but does not enable it in U-Boot itself, hence disable
Hi Fabio,
On Thu, 9 Jan 2020 10:58:30 -0300
Fabio Estevam feste...@gmail.com wrote:
> Hi Anatolij,
>
> On Tue, Jan 7, 2020 at 10:03 AM Anatolij Gustschin wrote:
> >
> > Since commit d02be21d3004 ("i2c: imx_lpi2c: add ipg clk") getting
> > I2C clocks doesn't work. Add I2C IPG clock IDs to relate
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