This patch appends CMA configuration to bootargs for LS1021ATWR board.
Signed-off-by: Shengzhou Liu
Signed-off-by: Alison Wang
---
Changes for v2:
- Append CMA configuration to bootargs directly
include/configs/ls1021atwr.h | 8
1 file changed, 4 insertions(+), 4 deletions(-)
On Tue, Mar 24, 2020 at 3:11 PM Heinrich Schuchardt wrote:
>
> On 3/24/20 8:15 AM, Atish Patra wrote:
> > On Mon, Mar 23, 2020 at 11:23 PM Heinrich Schuchardt
> > wrote:
> >>
> >> On 3/24/20 5:16 AM, Atish Patra wrote:
> >>> The DT used by U-Boot may be different from the DT being passed to
>
Hi,
I was looking at the STM32MP1 boot time and I noticed it takes about 2
seconds to get to U-Boot.
One problem is the insane I2C timing calculation in stm32f7 i2c driver,
which is almost a mallocator and CPU stress test and takes about 1
second to complete in SPL -- we need some simpler
Use phys2bus macro when dma address is accessed.
Some targets need to use pyhs2bus macro. (e.g, RPI4)
After applied it, SDMA mode can be used.
Signed-off-by: Jaehoon Chung
Reviewed-by: Peng Fan
Reviewed-by: Minkyu Kang
---
drivers/mmc/sdhci.c | 6 --
1 file changed, 4 insertions(+), 2
RPI4's SDHCI controller is supported SDMA mode. (Checked on kernel side)
But It doesn't use on u-boot side. Then it's too slow about read/write
performance.
This patchset is supported SDMA mode on RPI4 target(32bit).
- I didn't test on RPI4 64bit.
Read/write time about 8MB file
Before
- Read :
If Host controller doesn't support SDMA, it doesn't need to return
error. Because it can be worked with PIO mode.
Signed-off-by: Jaehoon Chung
Reviewed-by: Peng Fan
Reviewed-by: Minkyu Kang
---
drivers/mmc/sdhci.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git
Enable SDHCI_SDMA configuration.
Signed-off-by: Jaehoon Chung
Reviewed-by: Peng Fan
Reviewed-by: Minkyu Kang
---
configs/rpi_4_32b_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/configs/rpi_4_32b_defconfig b/configs/rpi_4_32b_defconfig
index 72cda5d949..7189914606 100644
---
On 3/24/20 11:46 PM, Marek Vasut wrote:
> WARNING: This is NOT a fix, but rather a bug report / notice of a problem.
> Disable the I2C timing calculation. The calculation is adding 1 second (!)
> to the SPL boot time only to calculate I2C timing parameters, that is not
> acceptable. Moreover, it
WARNING: This is NOT a fix, but rather a bug report / notice of a problem.
Disable the I2C timing calculation. The calculation is adding 1 second (!)
to the SPL boot time only to calculate I2C timing parameters, that is not
acceptable. Moreover, it is exercising the memory allocator massively.
Is
On 3/24/20 8:15 AM, Atish Patra wrote:
On Mon, Mar 23, 2020 at 11:23 PM Heinrich Schuchardt wrote:
On 3/24/20 5:16 AM, Atish Patra wrote:
The DT used by U-Boot may be different from the DT being passed to
the OS if the DT is loaded from external media such as network or
mmc. In that case,
Hi Jaehoon,
We incorporated your comments locally. We will release the next series as v4
once all feedback is received
for the rest of the patches in the series. Thank you for your feedback.
-BR
AN
> On Mar 24, 2020, at 12:16 AM, Jaehoon Chung wrote:
>
> Hi,
>
> On 3/20/20 9:57 AM, Alex
On 19/02/2020 10.47, Rasmus Villemoes wrote:
> The various env storage drivers almost all have their own logic [1]
> for deciding whether to compile and provide the .save method, many of
> which fail to honour CONFIG_SPL_SAVEENV. For example, fat.c and sf.c
> define a CMD_SAVEENV macro only for
Commit 07906b3dad15 ("ARC: Switch to generic accessors") introduces
a regression as it removes compiler barriers from __raw_readX \
__raw_writeX accessors. It breaks DW SPI driver (and possibly others)
Let's fix that and return compiler barriers back. However that's
not all. Let's add read/write
From: Tom Warren
The Jetson Nano Developer Kit is a Tegra X1-based development board. It
is similar to Jetson TX1 but it is not pin compatible. It features 4GB
of LPDDR4, a SPI NOR flash for early boot firmware and an SD card slot
used for storage.
HDMI 2.0 or DP 1.2 are available for display,
On 3/24/20 7:11 PM, Lukasz Majewski wrote:
> Hi Marek,
Hi,
>> On 3/24/20 8:06 AM, Lukasz Majewski wrote:
>>> Hi Marek,
>>
>> Hi,
>>
>> [...]
>>
>> You should probably figure out why this doesn't work first and
>> then add fixes on top.
>
> Haven't you seen such problem
On Mon, Mar 23, 2020 at 11:55 PM Heinrich Schuchardt wrote:
>
> Sub-nodes of /reserved-memory may be disabled. In this case we should not
> reserve memory in the memory map.
>
> Reported-by: Patrick DELAUNAY
> Fixes: fef907b2e440 ("efi_loader: create reservations after
> ft_board_setup")
>
Hi Marek,
> On 3/24/20 8:06 AM, Lukasz Majewski wrote:
> > Hi Marek,
>
> Hi,
>
> [...]
>
> You should probably figure out why this doesn't work first and
> then add fixes on top.
> >>>
> >>> Haven't you seen such problem during code development on your
> >>> setup when
Thank you very much Wolfgang,
reinstalling U-Boot helped.
Cheers,
udo.
On 24/03/2020 15:18, Wolfgang Denk wrote:
> Dear Udo,
>
> In message you wrote:
>>
>> while trying to set the mac-address of a device in u-boot I somehow
>> wrecked the whole thing.
>>
>> I think I did 'setenv eth0addr
Added command "fstypes" to list supported/included filesystems.
Signed-off-by: Niel Fourie
Cc: Simon Glass
Reviewed-by: Simon Glass
---
Changes in v2:
- Add Python test
Changes in v3:
- Rewrote comment for do_fs_types() in fs.h
cmd/fs.c | 11 +++
fs/fs.c
Add a subcommand "types" to the part command, which lists the supported
partition table types.
Signed-off-by: Niel Fourie
Cc: Simon Glass
Reviewed-by: Simon Glass
---
Changes in v2:
- Add Python test
Changes in v3:
- none
cmd/part.c | 27 +--
This series adds commands for listing the supported partition tables,
listing supported filesystems and expands Driver Model listing commands.
The existing "dm drivers" command, which lists the DM drivers and their
compatibility strings, segmentation faulted on drivers for which of_match
was
Renamed dm "drivers" subcommand to "compat" (as it listed
compatibility strings) and prevent it from segfaulting when
drivers have no of_match populated.
Added a new "drivers" subcommand to dump a list of all known DM
drivers and for each, their uclass id, uclass driver and names of
attached
On 3/24/20 8:06 AM, Lukasz Majewski wrote:
> Hi Marek,
Hi,
[...]
You should probably figure out why this doesn't work first and then
add fixes on top.
>>>
>>> Haven't you seen such problem during code development on your setup
>>> when developing this patch?
>>
>> During the
I cannot get the u-boot cli.
Device: BeagleBone Green Wireless
Connection: BBGW -> Serial -> PL2303 -> PC
Build:
---
cd u-boot-v2020.01/
export CROSS_COMPILE='arm-linux-gnueabihf-'
export KBUILD_OUTPUT='O'
make -j3 am335x_evm_defconfig
make -j3 all
Dear Vignesh,
In message <05694b0e-50a1-de5d-25d8-0444a2cae...@ti.com> you wrote:
>
> Aim of spi-nor-tiny.c is to have a tiny stack that can be used in
> SPL/TPL or on resource constraint boards to only support _reading_ from
> the flash. So tiny stack would be subset of spi-nor-core.
I fully
When a mismatch is found trying to write an image for one boot method
to a different boot device, print an error message including the image
header marked target boot device type.
Signed-off-by: Joel Johnson
Reviewed-by: Stefan Roese
---
v2 changes:
- newly added in v2 series
v3 changes:
Add support for Armada 38x devices in bubt flashing utility.
This is based on (and streamlined from) the support in the SolidRun
master-a38x vendor fork.
Signed-off-by: Joel Johnson
Reviewed-by: Stefan Roese
---
v2 changes
- none
v3 changes
- none
v4 changes
- none
v5 changes
- none
Ensure that the device to which an image is being written includes
header information indicating boot support for the destination
device.
This is derived from the support in the SolidRun master-a38x vendor
fork.
Signed-off-by: Joel Johnson
Reviewed-by: Stefan Roese
---
v2 changes:
- none
With support added for Armada 38x, include the bubt command in
ClearFog defconfig.
Signed-off-by: Joel Johnson
Reviewed-by: Stefan Roese
---
v2 changes:
- none
v3 changes:
- none
v4 changes:
- none
v5 changes:
- none
---
configs/clearfog_defconfig | 1 +
1 file changed, 1
Replace "U-BOOT" text with correct spelling
Signed-off-by: Joel Johnson
Reviewed-by: Stefan Roese
---
v2 changes:
- none
v3 changes:
- none
v4 changes:
- none
v5 changes:
- none
---
cmd/mvebu/bubt.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git
Dear Udo,
In message you wrote:
>
> while trying to set the mac-address of a device in u-boot I somehow
> wrecked the whole thing.
>
> I think I did 'setenv eth0addr xx:xx:xx:xx:xx:xx' followed by 'saveenv'
> After that, my device tells me "Unknown command 'run' - try 'help'" and
> also "Unknown
On 2020-03-24 01:28, Stefan Roese wrote:
On 23.03.20 18:43, Joel Johnson wrote:
When a mismatch is found trying to write an image for one boot method
to a different boot device, print an error message including the image
header marked target boot device type.
Signed-off-by: Joel Johnson
Dear Wolfgang,
On 20/03/20 4:48 pm, Wolfgang Denk wrote:
> Dear Vignesh,
>
> In message <20200320101448.10714-1-rasmus.villem...@prevas.dk> Rasmus
> Villemoes wrote:
>> I have a board for which doing "sf erase 0x10 0x8"
>> consistently causes the external watchdog circuit to reset the
At present we query the memory map on boards which don't support it. Fix
this by only doing it on Apollo Lake.
This fixes booting on chromebook_link.
Signed-off-by: Simon Glass
Fixes: 92842147c31 ("spi: ich: Add support for get_mmap() method")
---
drivers/spi/ich.c | 3 +++
1 file changed, 3
Update the command stboard to support the updated coding of OTP 59 with
finished good.
The ST product codification have several element
- "Commercial Product Name" (CPN): type of product board (DKX, EVX)
associated to the board ID "MB"
- "Finished Good" or "Finish Good" (FG):
effective
We have a board with several revisions. The older ones use a nor flash
with 64k erase size, while the newer have a flash with 4k sectors. The
environment size is 8k.
Currently, we have to put a column containing 0x1 (64k) in
fw_env.config in order for it to work on the older boards. But that
Please note this email has two parts: the technical / working on stuff
part and some footnotes[1]. Please do not reply to the footnotes on
list. While they are u-boot related they are only included for reasons
outlined in[2].
I know I'm late to the party but I ended up wanting to replace
The commit a673025535ae ("serial: zynq: Initialize uart only before
relocation") introduced code which detects relocation which is working for
single uart instance. With multiple instances in place there is a need to
enable and setup every instance. That's why detect if TX is enabled. If it
is
On 2020/3/20 上午12:28, David Sterba wrote:
> On Thu, Mar 19, 2020 at 03:34:12PM +0100, Matthias Brugger wrote:
>>
>>
>> On 19/03/2020 14:56, David Sterba wrote:
>>> On Thu, Mar 19, 2020 at 02:33:28PM +0100, Matthias Brugger wrote:
> dlen -= out_len;
>
> res +=
On 2020/3/20 上午12:28, David Sterba wrote:
> On Thu, Mar 19, 2020 at 03:34:12PM +0100, Matthias Brugger wrote:
>>
>>
>> On 19/03/2020 14:56, David Sterba wrote:
>>> On Thu, Mar 19, 2020 at 02:33:28PM +0100, Matthias Brugger wrote:
> dlen -= out_len;
>
> res +=
Hi Patrick
On 3/24/20 9:05 AM, Patrick Delaunay wrote:
> Update the command stboard to support the updated coding of OTP 59 with
> finished good.
>
> The ST product codification have several element
> - "Commercial Product Name" (CPN): type of product board (DKX, EVX)
> associated to the board
Hi
> From: Patrick DELAUNAY
> Sent: vendredi 6 mars 2020 11:09
>
> From: Alain Volmat
>
> Do not limit to 3 (100KHz, 400KHz, 1MHz) bus frequencies, but instead allow
> for
> any frequency. Depending on the requested frequency (via the clock-frequency
> DT entry), use the spec data from
Hi,
> From: Patrick DELAUNAY
> Sent: vendredi 6 mars 2020 11:14
>
> This parameter "st,phy-cal" becomes optional and when it is absent the
> built-in
> PHY calibration is done.
>
> It is the case in the helper dtsi file "stm32mp15-ddr.dtsi"
> except if DDR_PHY_CAL_SKIP is defined.
>
> This
Hi,
> From: Patrick DELAUNAY
> Sent: vendredi 6 mars 2020 11:14
>
> Update the BIST config to compute the real use mask for the real bank, row and
> col of the used DDR. The values are get from addrmap register value.
>
> Signed-off-by: Patrick Delaunay
> ---
Applied to u-boot-stm/next,
Hi,
> From: Patrick DELAUNAY
> Sent: vendredi 6 mars 2020 11:14
>
> Reduce the delay after BIST delay, from 1ms to 10us which is enough accoriding
> datasheet.
>
> Signed-off-by: Patrick Delaunay
> ---
Applied to u-boot-stm/next, thanks!
Regards
Patrick
Hi,
> From: Patrick DELAUNAY
> Sent: vendredi 6 mars 2020 11:14
>
> DDRCTRL_PWRCTL.SELFREF_EN needs to be reset before DQS training step,
> not to enter in self refresh mode during the execution of this phase.
> Depending on settings, it can be set after the DQS training.
>
> Signed-off-by:
Hi,
> From: Patrick DELAUNAY
> Sent: vendredi 6 mars 2020 11:14
>
> Avoid to block the tuning procedure on BIST error (not finished BIST
> procedure)
> by adding a 1000us timeout on the polling of BISTGSR.BDDONE executed to
> detect the end of BIST.
>
> The normal duration of the BIST test is
Hi,
> From: Patrick DELAUNAY
> Sent: vendredi 6 mars 2020 11:14
>
> The derating (timing parameter derating using MR4 read value) can't be
> activated
> during BIST test, as the MR4 read answer will be not understood by BIST
> (BISTGSR.BDONE bit stay at 0, BISTWCSR.DXWCNT = 0x206 instead of
>
Hi,
> From: Patrick DELAUNAY
> Sent: vendredi 6 mars 2020 11:14
>
> Display result information for software read DQS gating, the tuning 0 which be
> used by CubeMX DDR tuning tools.
>
> Signed-off-by: Patrick Delaunay
> ---
Applied to u-boot-stm/next, thanks!
Regards
Patrick
Hi,
> From: Patrick DELAUNAY
> Sent: vendredi 6 mars 2020 11:14
>
> Remove one "DDR>" display on command
> - next
> - step
> - go
>
> Signed-off-by: Patrick Delaunay
> ---
Applied to u-boot-stm/next, thanks!
Regards
Patrick
Hi,
> From: Patrick DELAUNAY
> Sent: vendredi 6 mars 2020 11:14
>
> Need to increase the LPDDR2/LPDDR3 the voltage vdd2_ddr: buck2 form 1.2V to
> 1.25V for 32bits configuration.
>
> Signed-off-by: Patrick Delaunay
> ---
Applied to u-boot-stm/next, thanks!
Regards
Patrick
Hi,
> From: Patrick DELAUNAY
> Sent: vendredi 6 mars 2020 17:55
>
> This commit manages diversity for STM32M15x SOCs with:
> - dedicated files to support all STM32MP15 SOCs family.
> The differences between those SOCs are:
> -STM32MP151 [1]: common file.
> -STM32MP153 [2]: STM32MP151 +
Heinrich Schuchardt writes:
> The runtime service GetNextVariable() returns the length of the next
> variable including the closing 0x. This length should be in bytes.
>
> Comparing the output of EDK2 and U-Boot shows that this is currently not
> correctly implemented:
>
> EDK2:
>
Hi,
> From: Patrick DELAUNAY
> Sent: lundi 9 mars 2020 14:59
>
> Add clock support for SPI5, as this instance is available on extension
> connector of
> ST board.
>
> Signed-off-by: Patrick Delaunay
> ---
Applied to u-boot-stm/next, thanks!
Regards
Patrick
Hi,
> From: Patrick DELAUNAY
> Sent: lundi 9 mars 2020 14:59
>
> Correct three masks used to access on the RCC register RCC_QSPICKSELR,
> RCC_FMCCKSELR and RCC_ADCCKSELR: only 3 bits.
>
> Signed-off-by: Patrick Delaunay
> ---
Applied to u-boot-stm/next, thanks!
Regards
Patrick
Hi Heinrich,
Heinrich Schuchardt writes:
> The runtime service GetNextVariable() returns the length of the next
> variable including the closing 0x. This length should be in bytes.
>
> Comparing the output of EDK2 and U-Boot shows that this is currently not
> correctly implemented:
>
>
Hi,
> From: Patrick DELAUNAY
> Sent: lundi 2 mars 2020 11:27
>
> From: Ludovic Barre
>
> This path allows to set the cntfrq register of targeted cpu.
>
> Signed-off-by: Ludovic Barre
> Reviewed-by: Patrick DELAUNAY
> Signed-off-by: Patrick Delaunay
> ---
Applied to u-boot-stm/next,
Hi,
> From: Patrick DELAUNAY
> Sent: mercredi 26 février 2020 11:27
>
> The STM32MP1 series is available in 3 different lines which are pin-to-pin
> compatible:
> - STM32MP157: Dual Cortex-A7 cores, Cortex-M4 core @ 209 MHz,
> 3D GPU, DSI display interface and CAN FD
> -
Hi,
> From: Patrick DELAUNAY
> Sent: mercredi 12 février 2020 19:38
>
> Update the kernel device tree for STM32MP15x product lines according the used
> soc and its part number, when CONFIG_OF_SYSTEM_SETUP is activated:
> - STM32MP15XA hasn't Crypto (cryp1/2)
> - STM32M151 and STM32M153 hasn't
Hi,
> From: Patrick DELAUNAY
> Sent: mercredi 12 février 2020 19:38
>
> Add a function get_soc_name to get a string with the full name of the SOC
> "STM32MP15xxx Rev.x"
>
> Signed-off-by: Patrick Delaunay
> ---
Applied to u-boot-stm/next, thanks!
Regards
Patrick
Hi,
> From: Patrick DELAUNAY
> Sent: mercredi 12 février 2020 19:38
>
> Display the reference MB found in OTP49 only for STMicroelectronics boards
> when CONFIG_CMD_STBOARD is activated.
>
> Signed-off-by: Patrick Delaunay
> ---
Applied to u-boot-stm/next, thanks!
Regards
Patrick
Hi,
> From: Patrick DELAUNAY
> Sent: mercredi 12 février 2020 19:38
>
> Add the SMC code and operation for trace on errors.
>
> Signed-off-by: Patrick Delaunay
> ---
Applied to u-boot-stm/next, thanks!
Regards
Patrick
Hi,
> From: Patrick DELAUNAY
> Sent: mercredi 12 février 2020 19:38
>
> Lock the OTP used for board identification for the ST boards after
> programming.
>
> Signed-off-by: Patrick Delaunay
> ---
Applied to u-boot-stm/next, thanks!
Regards
Patrick
Hi,
> From: Patrick DELAUNAY
> Sent: mercredi 12 février 2020 19:38
>
> Add BSEC lock access (read / write) at 0xC000 offset of misc driver.
> The write access only available for Trusted boot mode, based on new SMC
> STM32_SMC_WRLOCK_OTP.
>
> With the fuse command, the permanent lock
Hi,
> From: Patrick DELAUNAY
> Sent: mercredi 12 février 2020 19:38
>
> Remove the test offs < 0 , as offs is unsigned.
>
> This patch solves the warnings when compiling with W=1 on stm32mp1 board:
>
> In function ‘stm32mp_bsec_read’:
> arch/arm/mach-stm32mp/bsec.c:368:11: warning:
>
Hi,
> From: Patrick DELAUNAY
> Sent: mercredi 12 février 2020 19:38
>
> Update management of misc_write, which now return length of data after the
> commit 8729b1ae2cbd ("misc: Update read() and write() methods to return bytes
> xfered")
>
> Signed-off-by: Patrick Delaunay
> ---
Applied to
Hi,
> From: Patrick DELAUNAY
> Sent: mercredi 12 février 2020 19:38
>
> Read the value directly from the OTP and no more of the shadows to avoid the
> need of reboot after stboard command to have correct value.
>
> Signed-off-by: Patrick Delaunay
> ---
Applied to u-boot-stm/next, thanks!
Hi Heinrich,
Heinrich Schuchardt writes:
> Up to now for MBR and GPT partitions the info field 'bootable' was set to 1
> if either the partition was an EFI system partition or the bootable flag
> was set.
>
> Turn info field 'bootable' into a bit mask with separate bits for bootable
> and EFI
From: Hou Zhiqiang
Enable GIC_V3_ITS config to initialize the GIC redistributor
tables.
Signed-off-by: Hou Zhiqiang
---
V2:
- No change.
configs/ls1028aqds_tfa_SECURE_BOOT_defconfig | 1 +
configs/ls1028aqds_tfa_defconfig | 1 +
configs/ls1028ardb_tfa_SECURE_BOOT_defconfig | 1 +
From: Hou Zhiqiang
The GIC redistributor tables initialization depends on RESV_RAM config,
so select RESV_RAM if GIC_V3_ITS is enabled.
Signed-off-by: Hou Zhiqiang
---
V2:
- The #6 of v1 patchset.
arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 4
1 file changed, 4 insertions(+)
diff
From: Hou Zhiqiang
Move GIC redistributor tables initialization to CPU setup function.
This patch introduces a GIC redistributor tables init function, and
moves the function of reserving memory for GIC redistributor tables
to soc.c and adds a argument for the memory size to reserve, BTW
rename
From: Hou Zhiqiang
Enable GIC_V3_ITS config to initialize the GIC redistributor
tables.
Signed-off-by: Hou Zhiqiang
---
V2:
- No change.
configs/ls2080aqds_SECURE_BOOT_defconfig | 1 +
configs/ls2080aqds_defconfig | 1 +
configs/ls2080aqds_nand_defconfig |
From: Hou Zhiqiang
As the lower 16bit of the redistributor pending table is reserved
for describing the memory attributes, we must give a 64KB aligned
address to the GIC LPI initialization function.
Signed-off-by: Hou Zhiqiang
---
V2:
- The #5 of v1 patchset.
From: Hou Zhiqiang
Enable GIC_V3_ITS config to initialize the GIC redistributor
tables.
Signed-off-by: Hou Zhiqiang
---
V2:
- No change.
configs/ls1088aqds_defconfig | 1 +
configs/ls1088aqds_qspi_SECURE_BOOT_defconfig| 1 +
configs/ls1088aqds_qspi_defconfig
From: Hou Zhiqiang
Program the GIC redistributor tables only when succeeded to reserve memory
for them, otherwise kernel will lose the chance to program them using
allocated memory.
Signed-off-by: Hou Zhiqiang
---
V2:
- The #4 of v1 patchset.
board/freescale/lx2160a/lx2160a.c | 6 --
1
From: Hou Zhiqiang
The initialization of gd->arch.resv_ram pointer should depend on if the
RESV_RAM config is enabled.
Signed-off-by: Hou Zhiqiang
---
V2:
- No change.
arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git
From: Hou Zhiqiang
This patch set is to initialize the GIC redistributor tables and add the
tables to kernel DT's reserved memeory node.
Hou Zhiqiang (9):
board: lx2160a: Add header file cpu_func.h
arm64: fsl-layerscape: Assign addr to resv_ram if enabled RESV_RAM
config
board:
From: Hou Zhiqiang
The declaration of the function cpu_numcores() has been moved to
cpu_func.h, so add including of the header file to avoid build
error.
Signed-off-by: Hou Zhiqiang
---
V2:
- No change.
board/freescale/lx2160a/lx2160a.c | 1 +
1 file changed, 1 insertion(+)
diff --git
Update the command stboard to support the updated coding of OTP 59 with
finished good.
The ST product codification have several element
- "Commercial Product Name" (CPN): type of product board (DKX, EVX)
associated to the board ID "MB"
- "Finished Good" or "Finish Good" (FG):
effective
On 23.03.20 15:47, Michal Simek wrote:
From: Ashok Reddy Soma
Add support for Xilinx window watchdog, which can be found on
Versal platforms.
Signed-off-by: Ashok Reddy Soma
Signed-off-by: Michal Simek
---
Changes in v2:
- Reverse subject prefixes
- Convert to regmap as was asked
- Rename
On 23.03.20 21:21, Joel Johnson wrote:
Add a unique entry for ClearFog Base variant, reflected in the board
name and adjusted SerDes topology.
Signed-off-by: Joel Johnson
Reviewed-by: Stefan Roese
Thanks,
Stefan
---
v2 changes:
- reworked based on Baruch's run-time TLV EEPROM
On 23.03.20 18:43, Joel Johnson wrote:
When a mismatch is found trying to write an image for one boot method
to a different boot device, print an error message including the image
header marked target boot device type.
Signed-off-by: Joel Johnson
Reviewed-by: Stefan Roese
---
v2 changes:
On 23.03.20 18:43, Joel Johnson wrote:
Ensure that the device to which an image is being written includes
header information indicating boot support for the destination
device.
This is derived from the support in the SolidRun master-a38x vendor
fork.
Signed-off-by: Joel Johnson
---
v2
On 23.03.20 18:26, Joel Johnson wrote:
Enable distro bootcmd support for additional SATA ports if enabled.
Signed-off-by: Joel Johnson
Reviewed-by: Stefan Roese
Thanks,
Stefan
---
This patch builds on and requires the separate patch in the
"ClearFog Base static variant support" series
Hi,
On 3/20/20 9:57 AM, Alex Nemirovsky wrote:
> From: Arthur Li
>
> Initial DesignWare based DM support for Cortina Access CA SoCs.
>
> Signed-off-by: Arthur Li
> Signed-off-by: Alex Nemirovsky
> CC: Peng Fan
I didn't receive any reply about my previous comments.
And Is there patch v3
On Mon, Mar 23, 2020 at 11:14 PM Heinrich Schuchardt wrote:
>
> On 3/24/20 5:16 AM, Atish Patra wrote:
> > In RISC-V, M-mode software can reserve physical memory regions
> > by setting appropriate physical memory protection (PMP) csr. As the
> > PMP csr are accessible only in M-mode, S-mode
On Mon, Mar 23, 2020 at 11:23 PM Heinrich Schuchardt wrote:
>
> On 3/24/20 5:16 AM, Atish Patra wrote:
> > The DT used by U-Boot may be different from the DT being passed to
> > the OS if the DT is loaded from external media such as network or
> > mmc. In that case, the reserved-memory node needs
On 3/23/20 10:14 AM, Peng Fan wrote:
> Hi Jaehoon,
>
>> Subject: Re: [PATCH v2 0/3] Support SDMA mode on RPI4 target - 32bit
>>
>> On 3/18/20 10:00 AM, Peng Fan wrote:
Subject: Re: [PATCH v2 0/3] Support SDMA mode on RPI4 target - 32bit
Hi
Is there any comment or plan to
Hi Marek,
> On 3/23/20 1:41 PM, Lukasz Majewski wrote:
> > Hi Marek,
>
> Hi,
>
> >> On 3/23/20 7:57 AM, Lukasz Majewski wrote:
> >>> Hi Marek,
> >>
> >> Hi,
> >>
> On 3/22/20 2:00 PM, Lukasz Majewski wrote:
> > This reverts commit 02b0e1a36c5bc20174299312556ec4e266872bd6.
Sub-nodes of /reserved-memory may be disabled. In this case we should not
reserve memory in the memory map.
Reported-by: Patrick DELAUNAY
Fixes: fef907b2e440 ("efi_loader: create reservations after
ft_board_setup")
Signed-off-by: Heinrich Schuchardt
---
cmd/bootefi.c | 3 ++-
1 file changed, 2
On 3/24/20 5:16 AM, Atish Patra wrote:
The DT used by U-Boot may be different from the DT being passed to
the OS if the DT is loaded from external media such as network or
mmc. In that case, the reserved-memory node needs to be copied to
the DT passed to the OS.
The bootefi command works in
On 3/24/20 5:16 AM, Atish Patra wrote:
In RISC-V, M-mode software can reserve physical memory regions
by setting appropriate physical memory protection (PMP) csr. As the
PMP csr are accessible only in M-mode, S-mode U-Boot can not read
this configuration directly. However, M-mode software can
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