On Thu, Apr 30, 2020 at 7:47 AM Frank Wang wrote:
>
> Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls
> whether the PHY receives the suspend signal from the controller.
>
> Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk")
> in Linux Kernel.
>
> Signed-off-by: Fra
On Wed, Apr 29, 2020 at 11:38 AM Chunfeng Yun wrote:
>
> Add a test item for the phy_bulk API
>
> Signed-off-by: Chunfeng Yun
> Reviewed-by: Weijie Gao
> Reviewed-by: Simon Glass
> ---
Reviewed-by: Jagan Teki
On 4/21/20 2:39 AM, AKASHI Takahiro wrote:
> efi_set_secure_stat() provides the common code for each stat transition
> caused by efi_transfer_secure_state().
>
> Signed-off-by: AKASHI Takahiro
> Suggested-by: Heinrich Schuchardt
> ---
> lib/efi_loader/efi_variable.c | 194 +++
On 4/21/20 2:38 AM, AKASHI Takahiro wrote:
> "if (left < esl->signature_size)" is not reachable in a while loop.
> But it is still valuable in case that a given signature database is
> somehow corrupted. So fix the while loop condition.
>
> Signed-off-by: AKASHI Takahiro
> Reported-by: Heinrich Sc
On Fri, 1 May 2020 at 00:57, Tom Rini wrote:
> On Fri, May 01, 2020 at 12:38:45AM +0530, Sughosh Ganu wrote:
> > On Fri, 1 May 2020 at 00:07, Heinrich Schuchardt
> wrote:
> >
> > > On 4/30/20 7:36 PM, Sughosh Ganu wrote:
> > > > Add documentation highlighting the steps for using the uefi capsule
On 5/1/20 6:02 AM, Simon Glass wrote:
> It is useful to know what mode U-Boot is running in. Add a message at the
> end of the 'bdinfo' output.
>
> Signed-off-by: Simon Glass
> Suggested-by: Mark Kettenis
Reviewed-by: Heinrich Schuchardt
> ---
>
> Changes in v4:
> - Fix signed/unsigned mismatc
Am May 1, 2020 4:04:06 AM UTC schrieb Simon Glass :
>HI Heinrich,
>
>On Thu, 30 Apr 2020 at 21:57, Heinrich Schuchardt
>wrote:
>>
>> Am May 1, 2020 3:21:45 AM UTC schrieb Simon Glass :
>> >Add a build for running 64-bit U-Boot from coreboot (which is
>32-bit).
>> >This uses binman to create an ima
HI Heinrich,
On Thu, 30 Apr 2020 at 21:57, Heinrich Schuchardt wrote:
>
> Am May 1, 2020 3:21:45 AM UTC schrieb Simon Glass :
> >Add a build for running 64-bit U-Boot from coreboot (which is 32-bit).
> >This uses binman to create an image with a 32-bit SPL and a 64-bit
> >U-Boot.
> >
> >Coreboot
Hi Tom,
On Thu, 30 Apr 2020 at 09:05, Tom Rini wrote:
> On Tue, Apr 28, 2020 at 04:40:47PM -0600, Simon Glass wrote:
> > Hi Tom,
> >
> > On Tue, 28 Apr 2020 at 09:52, Tom Rini wrote:
> > >
> > > On Tue, Apr 28, 2020 at 09:41:14AM -0600, Simon Glass wrote:
> > > > Hi Tom.
> > > >
> > > > On Tue,
It is useful to know what mode U-Boot is running in. Add a message at the
end of the 'bdinfo' output.
Signed-off-by: Simon Glass
Suggested-by: Mark Kettenis
---
Changes in v4:
- Fix signed/unsigned mismatch in printf()
Changes in v3:
- Show bit width for all archs, use sizeof(void *)
Changes
Hi Heinrich,
On Thu, 30 Apr 2020 at 21:39, Heinrich Schuchardt wrote:
>
> Am May 1, 2020 3:21:44 AM UTC schrieb Simon Glass :
> >It is useful to know what mode U-Boot is running in. Add a message at
> >the
> >end of the 'bdinfo' output.
> >
> >Signed-off-by: Simon Glass
> >Suggested-by: Mark Ket
Am May 1, 2020 3:21:45 AM UTC schrieb Simon Glass :
>Add a build for running 64-bit U-Boot from coreboot (which is 32-bit).
>This uses binman to create an image with a 32-bit SPL and a 64-bit
>U-Boot.
>
>Coreboot boots into SPL and then SPL boots into U-Boot.
>
>This allows running 64-bit EFI image
Am May 1, 2020 3:21:44 AM UTC schrieb Simon Glass :
>It is useful to know what mode U-Boot is running in. Add a message at
>the
>end of the 'bdinfo' output.
>
>Signed-off-by: Simon Glass
>Suggested-by: Mark Kettenis
>---
>
>Changes in v3:
>- Show bit width for all archs, use sizeof(void *)
>
>Cha
It is useful to know what mode U-Boot is running in. Add a message at the
end of the 'bdinfo' output.
Signed-off-by: Simon Glass
Suggested-by: Mark Kettenis
---
Changes in v3:
- Show bit width for all archs, use sizeof(void *)
Changes in v2:
- Add a new patch to indicate 32/64-bit in bdinfo
Make a few adjustments to allow us to build an SPL image for coreboot.
Signed-off-by: Simon Glass
---
Changes in v3: None
Changes in v2: None
arch/x86/cpu/Makefile| 4 +++-
arch/x86/cpu/coreboot/Makefile | 8 +++-
arch/x86/cpu/coreboot/coreboot.c | 3 ++-
arch/
Add a build for running 64-bit U-Boot from coreboot (which is 32-bit).
This uses binman to create an image with a 32-bit SPL and a 64-bit U-Boot.
Coreboot boots into SPL and then SPL boots into U-Boot.
This allows running 64-bit EFI images on x86.
Signed-off-by: Simon Glass
---
Changes in v3: N
At present SPL only works on bare-metal builds. With a few tweaks it can
be used for coreboot also.
Signed-off-by: Simon Glass
---
Changes in v3: None
Changes in v2: None
arch/x86/lib/spl.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/arch/x86/lib/spl.c b/arch
At present this function copies U-Boot from the last 1MB of ROM. This is
not the right way to do it. Instead, the binman symbol should provide the
location.
But in any case the code should live in the caller,
spl_board_load_image(), so that the 64-bit jump function can be used
elsewhere. Move it.
At present this function is only available in 32-bit code. Move it to the
common cpu file so it can be used by 64-bit U-Boot too.
Signed-off-by: Simon Glass
---
Changes in v3:
- Add new patch to make coreboot detection work in 64-bit code
Changes in v2: None
arch/x86/cpu/cpu.c | 25 +
Coreboot runs in 32-bit mode and cannot run a 64-bit U-Boot. To get around
this we can build a combined image with 32-bit SPL and 64-bit U-Boot. Add
a build rule and binman definition for this.
Signed-off-by: Simon Glass
---
Changes in v3: None
Changes in v2: None
Makefile
This series creates a new 64-bit 'coreboot64' build which can be launched
from coreboot. It uses SPL to effect the jump to 64-bit mode.
This was done in an attempt to get the Ubuntu FirmwareTestSuite[1]
working. Unfortunately the latest version shows a splash screen and hangs,
perhaps due to some
On 4/30/20 4:45 AM, David Wu wrote:
> Change the original data structure so that Rockchip's Soc
> gmac controller can support the designware.c and dwc_eth_qos.c
> drivers, a Soc can only support one.
I'm really confused; with a filename like gmac_rockchip.c that sounds
like it's driver for a MAC d
On 4/30/20 4:45 AM, David Wu wrote:
> Open structure data and interface, so that Soc using dw_eth_qos
> controller can reference.
This shouldn't be necessary; nothing outside of this driver should need
access to the registers.
At most, perhaps implement some additional functions so that other cod
On 4/30/20 4:43 AM, David Wu wrote:
> For others using, clk_rx and clk_tx may not be necessary,
> and their clock names are different.
> diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
> @@ -1691,20 +1699,16 @@ static int eqos_probe_resources_stm32(struct udevice
> *dev)
>
On 4/30/20 4:36 PM, Stephen Warren wrote:
> On 4/30/20 4:36 AM, David Wu wrote:
>> It can be seen that most of the Socs using STM mac, "snps,reset-gpio"
>> gpio is used, adding this option makes reset function more general.
>
>> diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
>
On 4/30/20 4:36 AM, David Wu wrote:
> After moving to eqos_ops, if eqos_config is defined
> outside, can not export interface() definition.
Looking at the patch itself, I think this patch just moves a function
pointer from the config to the ops structure which makes sense. However,
I can't underst
On 4/30/20 4:36 AM, David Wu wrote:
> It can be seen that most of the Socs using STM mac, "snps,reset-gpio"
> gpio is used, adding this option makes reset function more general.
> diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
> @@ -1712,11 +1724,29 @@ static int eqos_probe_re
On 4/30/20 4:36 AM, David Wu wrote:
> When using rgmii Gigabit mode, the wait_for_bit_le32()
> reset method resulting in RX can not receive data, after
> this patch, works well.
> diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
> + limit = eqos->config->swr_wait / 10;
> +
On Wed, Apr 29, 2020 at 03:24:28PM +0200, Frank Wunderlich wrote:
> Hi,
>
> I hope the mtk xhci series can be merged because further xhci-development for
> mt7622/23 depends on this.
If Marek is happy with the code, I won't object.
>
> Regards Frank
>
> Am 29. April 2020 14:49:05 MESZ schrieb
On Fri, May 01, 2020 at 02:33:17AM +0530, Jagan Teki wrote:
> On Thu, Apr 30, 2020 at 8:16 PM Tom Rini wrote:
> >
> > On Thu, Apr 30, 2020 at 12:34:05PM +0530, Jagan Teki wrote:
> >
> > > Some drivers and other bsp code not only poll the
> > > register with timeout but also required to delay
> > >
On Thu, Apr 30, 2020 at 05:54:26PM +0200, Heinrich Schuchardt wrote:
> The following changes since commit 6864fc8704661878294d1f0f981f47e864ef470f:
>
> Merge https://gitlab.denx.de/u-boot/custodians/u-boot-sh (2020-04-29
> 10:39:18 -0400)
>
> are available in the Git repository at:
>
> http
Now, we have a PCIe PHY driver as part of the Generic
PHY framework. Let's use it instead of legacy PHY driver.
Signed-off-by: Jagan Teki
---
drivers/pci/pcie_rockchip.c | 20 ++--
drivers/pci/pcie_rockchip.h | 5 +
2 files changed, 15 insertions(+), 10 deletions(-)
diff --
Drop the legacy PHY driver and it's associated code since
the PHY handling driver now part of Generic PHY framework.
Signed-off-by: Jagan Teki
---
drivers/pci/Makefile| 2 +-
drivers/pci/pcie_rockchip.c | 75 +++-
drivers/pci/pcie_rockchip.h | 147 -
Yes, This is changing the actual device tree pcie_phy
structure but the problem with the current Generic PHY
subsystem is unable to find PHY if the PHY node is not
part of the root structure and also PHY parent is
non-PHY type.
This will be reverted once we support the PHY subsystem
to get the PHY
Yes, This is changing the actual device tree u2phy
structure but the problem with the current Generic
PHY subsystem is unable to find PHY if the PHY node
is not part of the root structure.
This will be reverted once we support the PHY subsystem
to get the PHY even though it is not part of the root
Add Rockchip USB2PHY driver with initial support.
This will help to use it for EHCI controller in host
mode, and USB 3.0 controller in otg mode.
More functionality like charge, vbus detection will
add it in future changes.
Signed-off-by: Jagan Teki
---
drivers/phy/rockchip/Kconfig
Enable/Disable the USB2PHY clk for rk3399.
CLK is clear in enable and set in disable functionality.
Signed-off-by: Jagan Teki
---
drivers/clk/rockchip/clk_rk3399.c | 12
1 file changed, 12 insertions(+)
diff --git a/drivers/clk/rockchip/clk_rk3399.c
b/drivers/clk/rockchip/clk_rk3
This patch add support for USB2PHY and PCIe PHY driver
on rockchip platform and tested the same in rk3399.
Basic code is referenced from Linux, hence all the
license SPDX are reused.
The reason behind sending this as RFC is PHY devices
for u2phy, pcie_phy nodes are unable to get via
Generic PHY
Add the Rockchip PCIe PHY driver as part of
Generic PHY framework.
Signed-off-by: Jagan Teki
---
drivers/Kconfig | 2 +
drivers/Makefile | 1 +
drivers/phy/rockchip/Kconfig | 9 +
drivers/phy/rockchip/Makefile| 6 +
Hi All,
I noticed some recent(ish) commits in u-boot.git are missing a
sign-off from the maintainer. Is this an omission or an intentional
change in process?
I don't have a problem either way but if it was an omission I thought
I'd point it out. If it's intentional then this message can go to
/de
On 4/30/20 3:03 PM, Jan Kiszka wrote:
> Hi all,
>
> I've noticed that building am65x_evm_a53_defconfig causes the dtbs to be
> built twice, once for the main u-boot and once for the spl. This is
> because of an extra dependency in mach-k3/config_secure.mk added by
> 508369672ca3. Why should the pr
On Thu, Apr 30, 2020 at 8:16 PM Tom Rini wrote:
>
> On Thu, Apr 30, 2020 at 12:34:05PM +0530, Jagan Teki wrote:
>
> > Some drivers and other bsp code not only poll the
> > register with timeout but also required to delay
> > on each transaction.
> >
> > This patch add that requirement by adding sl
On 4/30/20 2:52 PM, Sughosh Ganu wrote:
>
> On Tue, 28 Apr 2020 at 05:58, AKASHI Takahiro
> mailto:takahiro.aka...@linaro.org>> wrote:
>
> Heinrich,
>
> On Mon, Apr 27, 2020 at 10:28:35PM +0200, Heinrich Schuchardt wrote:
> > On 4/27/20 11:48 AM, AKASHI Takahiro wrote:
> > > Capsule
On Fri, May 01, 2020 at 12:38:45AM +0530, Sughosh Ganu wrote:
> On Fri, 1 May 2020 at 00:07, Heinrich Schuchardt wrote:
>
> > On 4/30/20 7:36 PM, Sughosh Ganu wrote:
> > > Add documentation highlighting the steps for using the uefi capsule
> > > update feature for updating the u-boot firmware ima
On Fri, 1 May 2020 at 00:09, Heinrich Schuchardt wrote:
> On 4/30/20 7:36 PM, Sughosh Ganu wrote:
> > Add support for the get_image_info and set_image routines, which are
> > part of the efi firmware management protocol.
> >
> > The current implementation uses the set_image routine for updating t
The memory allocated to store the FIT image containing SYSFW and board
configuration data is statically defined to the largest size expected.
Some additions to the board configuration data has pushed us slightly
over the current defined size on some HS devices, expand to 278000.
Signed-off-by: And
On Thu, Apr 30, 2020 at 09:53:46PM +0800, Bin Meng wrote:
> Hi Tom,
>
> This PR includes the following x86 changes for v2020.07 release:
>
> - DM ACPI support (Part A)
> - Improve support for chain-loading x86 U-Boot
>
> The following changes since commit 6864fc8704661878294d1f0f981f47e864ef470
On Fri, 1 May 2020 at 00:07, Heinrich Schuchardt wrote:
> On 4/30/20 7:36 PM, Sughosh Ganu wrote:
> > Add documentation highlighting the steps for using the uefi capsule
> > update feature for updating the u-boot firmware image.
> >
> > Signed-off-by: Sughosh Ganu
>
> UEFI capsule updates should
On 30/04/2020 17.03, Christophe Leroy wrote:
>
>
> Le 30/04/2020 à 16:44, Rasmus Villemoes a écrit :
>> Hi,
>>
>> I'm wondering why the sysreset_mpc83xx driver (as well as the similar
>> code in arch/powerpc/cpu/mpc83xx/cpu.c) removes the MSR_IR and MSR_DR
>> bits from MSR.
>>
[snip]
>>
>> But si
Hi all,
I've noticed that building am65x_evm_a53_defconfig causes the dtbs to be
built twice, once for the main u-boot and once for the spl. This is
because of an extra dependency in mach-k3/config_secure.mk added by
508369672ca3. Why should the produced dtbs depend on the target that
produces the
On 4/30/20 7:36 PM, Sughosh Ganu wrote:
> Add support for the get_image_info and set_image routines, which are
> part of the efi firmware management protocol.
>
> The current implementation uses the set_image routine for updating the
> u-boot binary image for the qemu arm64 platform. This is suppor
On 4/30/20 7:36 PM, Sughosh Ganu wrote:
> Add documentation highlighting the steps for using the uefi capsule
> update feature for updating the u-boot firmware image.
>
> Signed-off-by: Sughosh Ganu
UEFI capsule updates should be architecture independent. I would expect
that the submitted code sh
Add documentation highlighting the steps for using the uefi capsule
update feature for updating the u-boot firmware image.
Signed-off-by: Sughosh Ganu
---
doc/board/emulation/qemu-arm.rst | 112 +++
1 file changed, 112 insertions(+)
diff --git a/doc/board/emulation/q
Add support for uefi capsule authentication feature for the qemu arm64
platform. This feature is enabled by setting the environment variable
"capsule_authentication_enabled".
The following configs are needed for enabling uefi capsule update and
capsule authentication features on the platform.
CON
Change the semihosting file operation functions into external symbols
so that they can be called from outside the file. These functions
would be required to be called for implementing firmware update
functionality for the qemu arm64 platform.
Signed-off-by: Sughosh Ganu
---
arch/arm/lib/semihost
Add support for authenticating uefi capsules. Most of the signature
verification functionality is shared with the uefi secure boot
feature.
The root certificate containing the public key used for the signature
verification is stored as an efi variable, similar to the variables
used for uefi secure
The current function to parse the signature database(sigdb) only
allows parsing of secure boot related sigdb variables, namely PK, KEK,
db and dbx. Allow the function to parse any other sigdb
variables. This would be useful for the capsule authenticate feature,
which would be storing it's root cert
The pkcs7 header parsing functionality is pretty generic, and can be
used by other features like capsule authentication. Make the function
as an extern, also changing it's name to efi_parse_pkcs7_header.
Signed-off-by: Sughosh Ganu
---
include/efi_loader.h | 2 +
lib/efi_loader/efi_si
Add a function to enable writing to a file. Currently, support is
added for writing to a binary file. This would be used for
implementing the firmware update functionality for the qemu arm64
platform.
Signed-off-by: Sughosh Ganu
---
arch/arm/lib/semihosting.c | 41 +++
This series is based on the capsule update series sent by Takahiro
Akashi[1].
These routines have been tested on the qemu arm64 platform for
updating the u-boot firmware through the capsule-on-disk functionality
of the uefi spec. This series supports updating the u-boot binary
image on platforms b
Add support for the get_image_info and set_image routines, which are
part of the efi firmware management protocol.
The current implementation uses the set_image routine for updating the
u-boot binary image for the qemu arm64 platform. This is supported
using the capsule-on-disk feature of the uefi
Hi Tom,
Please pull this PR.
Travis-ci: https://travis-ci.org/github/openedev/u-boot-amarula/builds/681057652
thanks,
Jagan.
The following changes since commit dd2c676a659a03daeef31d1221da2edff009d426:
Prepare v2020.07-rc1 (2020-04-28 15:55:57 -0400)
are available in the Git repository at:
On Thu, Apr 30, 2020 at 09:38:06AM +0200, Michal Simek wrote:
> Hi Tom,
>
> Please pull these patches to your tree.
> Travis looks good.
> https://travis-ci.org/github/michalsimek/u-boot/builds/680070323
>
> Gitlab CI too
> https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze/pipelines/295
Fix kernel doc warnings in phy.h. Mostly the warnings were due to the
return missing the semi-colon.
Signed-off-by: Dan Murphy
---
include/phy.h | 19 ---
1 file changed, 8 insertions(+), 11 deletions(-)
diff --git a/include/phy.h b/include/phy.h
index c1f6509e42fc..34c2af719b6
On DK1/2 board, when a 1.5A power supply is detected, a warning
message is displayed. In this message, "1.5mA" is displayed instead
of "1.5A".
Signed-off-by: Patrice Chotard
---
board/st/stm32mp1/stm32mp1.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/board/st/stm32mp1/st
ti_phy_init function was allocated to the DP83867 PHY. This function
name is to generic for a specific PHY. The function can be moved to a
TI specific file that can register all TI PHYs that are defined in the
defconfig. The ti_phy_init file will contain all TI PHYs initialization
so that only p
Add the DP8382X generic PHY registration to the TI PHY init file.
Acked-by: Michal Simek
Signed-off-by: Dan Murphy
---
drivers/net/phy/ti_phy_init.c | 83 +++
1 file changed, 83 insertions(+)
diff --git a/drivers/net/phy/ti_phy_init.c b/drivers/net/phy/ti_phy_in
Add phy_set/clear_bit helper routines so that ported drivers from the
kernel can use these functions.
Signed-off-by: Dan Murphy
---
include/phy.h | 54 +++
1 file changed, 54 insertions(+)
diff --git a/include/phy.h b/include/phy.h
index 34c2af719
Add kernel doc to the phy_read/write utility functions in phy.h
Signed-off-by: Dan Murphy
---
include/phy.h | 39 +++
1 file changed, 39 insertions(+)
diff --git a/include/phy.h b/include/phy.h
index b5de14cbfc29..c1f6509e42fc 100644
--- a/include/phy.h
+++ b
Hello
The addition of the DP83867 driver to uboot was done in a generic way that
made it a bit difficult to bring in new PHY drivers. The difficulty came in the
config flags and the phy_init function. The change is to make the flags and
init for the DP83867 more specific to the DP83867 device to
The following changes since commit 6864fc8704661878294d1f0f981f47e864ef470f:
Merge https://gitlab.denx.de/u-boot/custodians/u-boot-sh (2020-04-29
10:39:18 -0400)
are available in the Git repository at:
https://gitlab.denx.de/u-boot/custodians/u-boot-efi.git
tags/efi-2020-07-rc2
for you to f
Hi David
On 4/30/20 12:36 PM, David Wu wrote:
> It can be seen that most of the Socs using STM mac, "snps,reset-gpio"
> gpio is used, adding this option makes reset function more general.
>
> Signed-off-by: David Wu
> ---
>
> drivers/net/dwc_eth_qos.c | 40 ++-
Hi David
On 4/30/20 12:44 PM, David Wu wrote:
> Before enabling mac and mac working, we need to obtain
> the current link speed to configure the clock, so split
> eqos_start into two functions.
>
> Signed-off-by: David Wu
> ---
>
> drivers/net/dwc_eth_qos.c | 56 ++---
On Thu, Apr 30, 2020 at 11:37:32AM +, Priyanka Jain wrote:
> Dear Tom,
> Please find my pull-request for u-boot-fsl-qoriq/master
> https://travis-ci.org/github/p-priyanka-jain/u-boot/builds/680868706
>
> Summary
> Add DM_ETH support for DPAA1, DPAA2 based RDB platforms: ls1046ardb,
> ls
Hi David
On 4/30/20 12:36 PM, David Wu wrote:
> When using rgmii Gigabit mode, the wait_for_bit_le32()
> reset method resulting in RX can not receive data, after
> this patch, works well.
>
> Signed-off-by: David Wu
> ---
>
> drivers/net/dwc_eth_qos.c | 21 +++--
> 1 file changed
On Thu, Apr 30, 2020 at 06:11:19PM +0300, Andy Shevchenko wrote:
> On Thu, Apr 30, 2020 at 5:13 PM Tom Rini wrote:
> >
> > On Thu, Apr 30, 2020 at 12:35:20PM +0300, Andy Shevchenko wrote:
> > > On Thu, Apr 30, 2020 at 12:34 PM Andy Shevchenko
> > > wrote:
> > > >
> > > > HI!
> > > >
> > > > Did I
On Thu, Apr 30, 2020 at 5:13 PM Tom Rini wrote:
>
> On Thu, Apr 30, 2020 at 12:35:20PM +0300, Andy Shevchenko wrote:
> > On Thu, Apr 30, 2020 at 12:34 PM Andy Shevchenko
> > wrote:
> > >
> > > HI!
> > >
> > > Did I miss anything myself?
> >
> > U-Boot v2020.04
> >
> > > U-Boot:
> > > => ext4ls mm
On Tue, Apr 28, 2020 at 04:40:47PM -0600, Simon Glass wrote:
> Hi Tom,
>
> On Tue, 28 Apr 2020 at 09:52, Tom Rini wrote:
> >
> > On Tue, Apr 28, 2020 at 09:41:14AM -0600, Simon Glass wrote:
> > > Hi Tom.
> > >
> > > On Tue, 28 Apr 2020 at 08:19, Tom Rini wrote:
> > > >
> > > > On Mon, Apr 27, 20
Le 30/04/2020 à 16:44, Rasmus Villemoes a écrit :
Hi,
I'm wondering why the sysreset_mpc83xx driver (as well as the similar
code in arch/powerpc/cpu/mpc83xx/cpu.c) removes the MSR_IR and MSR_DR
bits from MSR.
On my mpc8309, that seems to simply make the board hang right after
writing the new
On Thu, Apr 30, 2020 at 12:34:05PM +0530, Jagan Teki wrote:
> Some drivers and other bsp code not only poll the
> register with timeout but also required to delay
> on each transaction.
>
> This patch add that requirement by adding sleep_us
> variable so-that read_poll_timeout now support
> delay
Hi,
I'm wondering why the sysreset_mpc83xx driver (as well as the similar
code in arch/powerpc/cpu/mpc83xx/cpu.c) removes the MSR_IR and MSR_DR
bits from MSR.
On my mpc8309, that seems to simply make the board hang right after
writing the new MSR value - i.e., it never gets to write the magic val
Fix Palmer's email address
Signed-off-by: Pragnesh Patel
Reviewed-by: Bin Meng
---
board/sifive/fu540/MAINTAINERS | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/board/sifive/fu540/MAINTAINERS b/board/sifive/fu540/MAINTAINERS
index 702d803ad8..5381fc0639 100644
--- a/board/s
from
https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/blob/u-boot-2018.03-armada-18.12/arch/arm/dts/armada-3720-espressobin.dts
fix comphy mode settings for USB3 (working)
fix comphy mode setting for network (working)
fix comphy mode setting for SATA (not yet working)
add config for SD
activate MMC_BROKEN_CD because drivers/mmc/mvebu_mmc.c does not
yet follow the driver model, so the card detection GPIO is not polled.
activate network switch, tested with bootp and random MAC generation
Signed-off-by: Peter Vollmer
---
configs/mvebu_espressobin-88f3720_defconfig | 4 +++-
1 fi
With current u-boot mainline espressobin is not working:
- SATA causes synchronous abort on startup
- USB3, SD card, EMMC flash and ethernet are not working out of the box
This patch series fixes above (with SATA not yet working) and makes
espressobin usable again with mainline u-boot, based on t
V4 = cosmetic update of the previous serie V3
"arm: stm32mp1: activate data cache in SPL and before relocation"
http://patchwork.ozlabs.org/project/uboot/list/?series=172557
This serie depends on the ARM cache serie:
"arm: caches: allow to activate dcache in SPL and in U-Boot pre-reloc"
http://p
Activate cache on DDR to improve the accesses to DDR used by SPL:
- CONFIG_SPL_BSS_START_ADDR
- CONFIG_SYS_SPL_MALLOC_START
Cache is configured only when DDR is fully initialized,
to avoid speculative access and issue in get_ram_size().
Data cache is deactivated at the end of SPL, to flush the dat
Activate the data cache in SPL and in U-Boot before relocation.
In arch_cpu_init(), the function early_enable_caches() sets the early
TLB, early_tlb[] located .init section, and set cacheable:
- for SPL, all the SYSRAM
- for U-Boot, all the DDR
After relocation, the function enable_caches() (call
On Thu, Apr 30, 2020 at 12:35:20PM +0300, Andy Shevchenko wrote:
> On Thu, Apr 30, 2020 at 12:34 PM Andy Shevchenko
> wrote:
> >
> > HI!
> >
> > Did I miss anything myself?
>
> U-Boot v2020.04
>
> > U-Boot:
> > => ext4ls mmc 0:8 /home/root
> >4096 .
> >4096 ..
> >4096 .no
Hi David
On 4/30/20 12:43 PM, David Wu wrote:
> For others using, clk_rx and clk_tx may not be necessary,
> and their clock names are different.
>
> Signed-off-by: David Wu
> ---
>
> drivers/net/dwc_eth_qos.c | 65 +++
> 1 file changed, 31 insertions(+), 34 de
Hi Simon,
On Mon, Apr 27, 2020 at 3:38 AM Simon Glass wrote:
>
> This series creates a new 64-bit 'coreboot64' build which can be launched
> from coreboot. It uses SPL to effect the jump to 64-bit mode.
>
> This was done in an attempt to get the Ubuntu FirmwareTestSuite[1]
> working. Unfortunatel
Hi Tom,
This PR includes the following x86 changes for v2020.07 release:
- DM ACPI support (Part A)
- Improve support for chain-loading x86 U-Boot
The following changes since commit 6864fc8704661878294d1f0f981f47e864ef470f:
Merge https://gitlab.denx.de/u-boot/custodians/u-boot-sh (2020-04-29
Hi Simon,
-"Simon Glass" schrieb: -
>Betreff: [PATCH v1 02/35] acpi: Add a function to get a device path
>and scope
>
>Add a function to build up the ACPI path for a device and another for
>its
>scope.
>
>Signed-off-by: Simon Glass
>---
>
>Changes in v1:
>- Split into more patches for re
DT alignment with Linux 5.7-rc2, including the kernel commits
431c89e6f323 ARM: dts: stm32: use correct vqmmc regu for eMMC on stm32mp1
ED1/EV1 boards
79e965053872 ARM: dts: stm32: add disable-wp property for SD-card on STM32MP1
boards
877db62ea516 ARM: dts: stm32: add cd-gpios properties for SD
On Thu, 2020-04-30 at 15:31 +0200, Mark Kettenis wrote:
> > From: Nicolas Saenz Julienne
> > Date: Thu, 30 Apr 2020 15:04:32 +0200
> >
> > On the Raspberry Pi 4, after a PCI reset, VL805's (a xHCI chip) firmware
> > may either be loaded directly from an EEPROM or, if not present, by the
> > SoC's
> From: Nicolas Saenz Julienne
> Date: Thu, 30 Apr 2020 15:04:32 +0200
>
> On the Raspberry Pi 4, after a PCI reset, VL805's (a xHCI chip) firmware
> may either be loaded directly from an EEPROM or, if not present, by the
> SoC's VideoCore (the SoC's co-processor). Introduce the function that
> i
In case CONFIG_DM_ETH is enabled, no hardcoding is necessary for DPAA2
Ethernet devices. Compile out any unnecessary setup when CONFIG_DM_ETH
is activated. Also, force the PCI devices to be enumerated at probe
time.
Signed-off-by: Ioana Ciornei
---
board/freescale/ls1088a/eth_ls1088aqds.c | 2 +
Add support for selecting the appropriate DTS file depending on the
SERDES protocol used. The fsl-ls2088a-qds DTS will be used by default if
there isn't a DTS file specifically made for the current SERDES
protocol.
This patch adds support for the on-board ports (DPMAC 1,2 and 4,5) found
on the SER
This patch set targets to add support for CONFIG_DM_ETH for the NXP
LS1088AQDS board.
The main focus is on changing the DTS based on the SERDES protocol used.
In order to accomplish this, the MULTI_DTB_FIT feature is employed and
the appropriate DTS is chosed on boot from a list of predefined file
Enable CONFIG_DM_ETH and CONFIG_DM_MDIO and related configs for the
LS1088AQDS board.
Signed-off-by: Ioana Ciornei
---
configs/ls1088aqds_tfa_defconfig | 11 ++-
include/configs/ls1088aqds.h | 2 ++
2 files changed, 12 insertions(+), 1 deletion(-)
diff --git a/configs/ls1088aqds_tf
1 - 100 of 241 matches
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