[PATCH 2/2] arm: dts: k3-j721e: Fix interconnect node names
The various CBASS interconnect nodes on K3 J721E SoCs are defined
using the node name "interconnect". This is not a valid node name
as per the dt-schema. Fix these node names to use the standard name
used for SoC interconnects, "bus".
Signed-off-by: Suman Anna
---
arch/arm/dts/k3-j721e.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/dts/k3-j721e.dtsi b/arch/arm/dts/k3-j721e.dtsi
index 6bd5aabe2374..b2670752dcd4 100644
--- a/arch/arm/dts/k3-j721e.dtsi
+++ b/arch/arm/dts/k3-j721e.dtsi
@@ -131,7 +131,7 @@
interrupts = ;
};
- cbass_main: interconnect@10 {
+ cbass_main: bus@10 {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
@@ -164,7 +164,7 @@
<0x05 0x 0x05 0x 0x01 0x>,
<0x07 0x 0x07 0x 0x01 0x>;
- cbass_mcu_wakeup: interconnect@2838 {
+ cbass_mcu_wakeup: bus@2838 {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
--
2.26.0
[PATCH 1/2] arm: dts: k3-am65: Fix interconnect node names
The various CBASS interconnect nodes on K3 AM65x SoCs are defined
using the node name "interconnect". This is not a valid node name
as per the dt-schema. Fix these node names to use the standard name
used for SoC interconnects, "bus".
Signed-off-by: Suman Anna
---
arch/arm/dts/k3-am65.dtsi | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/dts/k3-am65.dtsi b/arch/arm/dts/k3-am65.dtsi
index 3d89bf32a9d1..4d6d196b2aa3 100644
--- a/arch/arm/dts/k3-am65.dtsi
+++ b/arch/arm/dts/k3-am65.dtsi
@@ -62,7 +62,7 @@
interrupts = ;
};
- cbass_main: interconnect@10 {
+ cbass_main: bus@10 {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
@@ -87,7 +87,7 @@
<0x05 0x 0x05 0x 0x01 0x000>,
<0x07 0x 0x07 0x 0x01 0x000>;
- cbass_mcu: interconnect@2838 {
+ cbass_mcu: bus@2838 {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
@@ -104,7 +104,7 @@
<0x05 0x 0x05 0x 0x01
0x000>, /* FSS OSPI0 data region 3*/
<0x07 0x 0x07 0x 0x01
0x000>; /* FSS OSPI1 data region 3*/
- cbass_wakeup: interconnect@4204 {
+ cbass_wakeup: bus@4204 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
--
2.26.0
[PATCH 0/2] Update TI K3 cbass interconnect node names
Hi Lokesh, The following 2 patches are minor cleanups that fix the various CBASS interconnect node names from "interconnect" to "bus" on K3 AM65x and J721E SoCs. "bus" is the correct dt-schema acceptible node name. regards Suman Suman Anna (2): arm: dts: k3-am65: Fix interconnect node names arm: dts: k3-j721e: Fix interconnect node names arch/arm/dts/k3-am65.dtsi | 6 +++--- arch/arm/dts/k3-j721e.dtsi | 4 ++-- 2 files changed, 5 insertions(+), 5 deletions(-) -- 2.26.0
[PATCH 8/9] bcmgenet: fix DMA buffer management
This commit fixes a serious issue occurring when several network
commands are run on a raspberry pi 4 board: for instance a "dhcp"
command and then one or several "tftp" commands. In this case,
packet recv callbacks were called several times on the same packets,
and send function was failing most of the time.
note: if the boot procedure is made of a single network
command, the issue is not visible.
The issue is related to management of the packet ring buffers
(producer / consumer) and DMA.
Each time a packet is received, the ethernet device stores it
in the buffer and increments an index called RDMA_PROD_INDEX.
Each time the driver outputs a received packet, it increments
another index called RDMA_CONS_INDEX.
Between each pair of network commands, as part of the driver
'start' function, previous code tried to reset both RDMA_CONS_INDEX
and RDMA_PROD_INDEX to 0. But RDMA_PROD_INDEX cannot be written from
driver side, thus its value was actually not updated, and only
RDMA_CONS_INDEX was reset to 0. This was resulting in a major
synchronization issue between the driver and the device. Most
visible behavior was that the driver seemed to receive again the
packets from the previous commands (e.g. DHCP response packets
"received" again when performing the first TFTP command).
This fix consists in setting RDMA_CONS_INDEX to the same
value as RDMA_PROD_INDEX, when resetting the driver.
The same kind of fix was needed on the TX side, and a few variables
had to be reset accordingly (c_index, tx_index, rx_index).
The rx_index and tx_index have only 256 entries so the bottom 8 bits
must be masked off.
Originated-by: Etienne Dublé
Signed-off-by: Jason Wessel
---
drivers/net/bcmgenet.c | 17 +
1 file changed, 9 insertions(+), 8 deletions(-)
diff --git a/drivers/net/bcmgenet.c b/drivers/net/bcmgenet.c
index 11b6148ab6..1b7e7ba2bf 100644
--- a/drivers/net/bcmgenet.c
+++ b/drivers/net/bcmgenet.c
@@ -378,8 +378,6 @@ static void rx_descs_init(struct bcmgenet_eth_priv *priv)
u32 len_stat, i;
void *desc_base = priv->rx_desc_base;
- priv->c_index = 0;
-
len_stat = (RX_BUF_LENGTH << DMA_BUFLENGTH_SHIFT) | DMA_OWN;
for (i = 0; i < RX_DESCS; i++) {
@@ -403,8 +401,11 @@ static void rx_ring_init(struct bcmgenet_eth_priv *priv)
writel(RX_DESCS * DMA_DESC_SIZE / 4 - 1,
priv->mac_reg + RDMA_RING_REG_BASE + DMA_END_ADDR);
- writel(0x0, priv->mac_reg + RDMA_PROD_INDEX);
- writel(0x0, priv->mac_reg + RDMA_CONS_INDEX);
+ /* cannot init RDMA_PROD_INDEX to 0, so align RDMA_CONS_INDEX on it
instead */
+ priv->c_index = readl(priv->mac_reg + RDMA_PROD_INDEX);
+ writel(priv->c_index, priv->mac_reg + RDMA_CONS_INDEX);
+ priv->rx_index = priv->c_index;
+ priv->rx_index &= 0xFF;
writel((RX_DESCS << DMA_RING_SIZE_SHIFT) | RX_BUF_LENGTH,
priv->mac_reg + RDMA_RING_REG_BASE + DMA_RING_BUF_SIZE);
writel(DMA_FC_THRESH_VALUE, priv->mac_reg + RDMA_XON_XOFF_THRESH);
@@ -421,8 +422,10 @@ static void tx_ring_init(struct bcmgenet_eth_priv *priv)
writel(0x0, priv->mac_reg + TDMA_WRITE_PTR);
writel(TX_DESCS * DMA_DESC_SIZE / 4 - 1,
priv->mac_reg + TDMA_RING_REG_BASE + DMA_END_ADDR);
- writel(0x0, priv->mac_reg + TDMA_PROD_INDEX);
- writel(0x0, priv->mac_reg + TDMA_CONS_INDEX);
+ /* cannot init TDMA_CONS_INDEX to 0, so align TDMA_PROD_INDEX on it
instead */
+ priv->tx_index = readl(priv->mac_reg + TDMA_CONS_INDEX);
+ writel(priv->tx_index, priv->mac_reg + TDMA_PROD_INDEX);
+ priv->tx_index &= 0xFF;
writel(0x1, priv->mac_reg + TDMA_RING_REG_BASE + DMA_MBUF_DONE_THRESH);
writel(0x0, priv->mac_reg + TDMA_FLOW_PERIOD);
writel((TX_DESCS << DMA_RING_SIZE_SHIFT) | RX_BUF_LENGTH,
@@ -469,8 +472,6 @@ static int bcmgenet_gmac_eth_start(struct udevice *dev)
priv->tx_desc_base = priv->mac_reg + GENET_TX_OFF;
priv->rx_desc_base = priv->mac_reg + GENET_RX_OFF;
- priv->tx_index = 0x0;
- priv->rx_index = 0x0;
bcmgenet_umac_reset(priv);
--
2.17.1
[PATCH 1/9] fs/fat/fat.c: Do not perform zero block reads if there are no blocks left
While using u-boot with qemu's virtio driver I stumbled across a
problem reading files less than sector size. On the real hardware the
block reader seems ok with reading zero blocks, and while we could fix
the virtio host side of qemu to deal with a zero block read instead of
crashing, the u-boot fat driver should not be doing zero block reads
in the first place. If you ask hardware to read zero blocks you are
just going to get zero data. There may also be other hardware that
responds similarly to the virtio interface so this is worth fixing.
Without the patch I get the following and have to restart qemu because
it dies.
-
=> fatls virtio 0:1
30 cmdline.txt
=> fatload virtio 0:1 ${loadaddr} cmdline.txt
qemu-system-aarch64: virtio: zero sized buffers are not allowed
-
With the patch I get the expected results.
-
=> fatls virtio 0:1
30 cmdline.txt
=> fatload virtio 0:1 ${loadaddr} cmdline.txt
30 bytes read in 11 ms (2 KiB/s)
=> md.b ${loadaddr} 0x1E
4008: 64 77 63 5f 6f 74 67 2e 6c 70 6d 5f 65 6e 61 62dwc_otg.lpm_enab
40080010: 6c 65 3d 30 20 72 6f 6f 74 77 61 69 74 0a le=0 rootwait.
-
Signed-off-by: Jason Wessel
Reviewed-by: Tom Rini
---
fs/fat/fat.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/fs/fat/fat.c b/fs/fat/fat.c
index 9578b74bae..28aa5aaa9f 100644
--- a/fs/fat/fat.c
+++ b/fs/fat/fat.c
@@ -278,7 +278,10 @@ get_cluster(fsdata *mydata, __u32 clustnum, __u8 *buffer,
unsigned long size)
}
} else {
idx = size / mydata->sect_size;
- ret = disk_read(startsect, idx, buffer);
+ if (idx == 0)
+ ret = 0;
+ else
+ ret = disk_read(startsect, idx, buffer);
if (ret != idx) {
debug("Error reading data (got %d)\n", ret);
return -1;
--
2.17.1
[PULL][PATCH 0/9] Raspberry pi improvements qemu/usb/ethernet
I would like to get these patches merged for the next release, but
there has been no movement on some of them in over a month. I would
fix any problems with the patches, but I am not aware of any. The
patch set has been tested on all the generations of the raspberry pi
hardware and qemu and passed the travis ci checks.
-- Travis CI checks --
Pull Request #35 Rpi master
The commit 57805f2270c4 ("net: bcmgenet: Don't set ID_MODE_DIS when
not using RGMII") needed to be extended for the case of using the
rgmii-rxid. The latest version of the Rasbperry Pi4 dtb files for the
5.4 now specify the rgmii-rxid.
Signed-off-by: Jason Wessel
Commit 9a21770 #35: Rpi master Branch master
-- End Travis CI checks --
Prior to this patch set, I had just a small number of USB keyboards
function properly with the Rasbpberry Pi boards. Nearly every
composite USB keyboard/mouse I had access to including the Raritan
IP/KVM devices would not initialize properly.
v1-consoldiated:
- Consolidated all the usb and ethernet patches into a single set
- No changes to any of the patches
v1:
- Testing completed against all generations of raspberry pi boards
- check patch warnings add errors have been fixed
rfc v3:
- Add in patch 6
- Finally got the GearHead keyboard + mouse composite USB device working
rfc v2:
- Minor cleanups to patches 1-3 based on prior review
- Patch 4 & 5 are new to fix various xhchi crashes
while having additional devices plugged in along with
booting off the usb port. The nonblocking mode turned
out to be somewhat complex.
rfc v1:
The original purpose of the patch set was to fix problems with the USB
keyboard support with the rpi4. The generic xhci code lacks a non
blocking call to read an event. This causes major problems for the
sleep function as well as for ethernet downloads where a keyboard poll
for interrupting the download blocks for 5 seconds.
The following changes since commit fee68b98fe3890631a9bdf8f8db328179011ee3f:
Merge tag 'efi-2020-10-rc1-4' of
https://gitlab.denx.de/u-boot/custodians/u-boot-efi (2020-07-16 16:35:15 -0400)
are available in the Git repository at:
https://github.com/jwessel/u-boot
for you to fetch changes up to fb5b89c4f2aa2a95c4024b156099c838d1199bd0:
bcmgenet: Add support for rgmii-rxid (2020-07-17 06:35:11 -0700)
Jason Wessel (9):
fs/fat/fat.c: Do not perform zero block reads if there are no blocks left
xhci: Add polling support for USB keyboards
usb_kbd: succeed even if no interrupt is pending
common/usb.c: Work around keyboard reporting "USB device not accepting
new address"
xhci-ring.c: Add the poll_pend state to properly abort transactions
xhci-ring: Fix crash when issuing "usb reset"
usb.c: Add a retry in the usb_prepare_device()
bcmgenet: fix DMA buffer management
bcmgenet: Add support for rgmii-rxid
common/usb.c | 16 --
common/usb_kbd.c | 4 +-
drivers/net/bcmgenet.c | 20 +++
drivers/usb/host/xhci-ring.c | 123 +--
drivers/usb/host/xhci.c | 11 ++--
fs/fat/fat.c | 5 +-
include/usb/xhci.h | 5 +-
7 files changed, 136 insertions(+), 48 deletions(-)
[PATCH 7/9] usb.c: Add a retry in the usb_prepare_device()
I have found through testing some USB 2 composite mouse/keyboard
devices do not response to the usb_set_address call immediately
following the port reset. It can take anywhere from 2ms to 20ms.
This patch adds a retry and delay for usb_prepare_device() and allows
all the USB keyboards I tried to function properly.
Signed-off-by: Jason Wessel
---
common/usb.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/common/usb.c b/common/usb.c
index 0eb5d40a2d..39bae86a11 100644
--- a/common/usb.c
+++ b/common/usb.c
@@ -1032,6 +1032,7 @@ static int usb_prepare_device(struct usb_device *dev, int
addr, bool do_read,
struct usb_device *parent)
{
int err;
+ int retry_msec = 0;
/*
* Allocate usb 3.0 device context.
@@ -1054,6 +1055,14 @@ static int usb_prepare_device(struct usb_device *dev,
int addr, bool do_read,
dev->devnum = addr;
err = usb_set_address(dev); /* set address */
+ /* Retry for old composite keyboard/mouse usb2 hardware */
+ while (err < 0 && retry_msec <= 40) {
+ retry_msec += 20;
+ mdelay(20);
+ err = usb_set_address(dev); /* set address */
+ }
+ if (retry_msec > 0)
+ debug("usb_set_address delay: %i\n", retry_msec);
if (err < 0)
debug("\n usb_set_address return < 0\n");
if (err < 0 && dev->status != 0) {
--
2.17.1
[PATCH 2/9] xhci: Add polling support for USB keyboards
The xhci driver was causing intermittent 5 second delays from the USB
keyboard polling hook. Executing something like a "sleep 1" for
example would sleep for 5 seconds, unless an event occurred on
the USB bus to shorten the delay.
Modeled after the code in the DWC2 driver, a nonblock state was added
to quickly return instead of blocking for up to 5 seconds waiting for
an event before timing out.
Signed-off-by: Jason Wessel
---
drivers/usb/host/xhci-ring.c | 26 +-
drivers/usb/host/xhci.c | 11 ++-
include/usb/xhci.h | 5 +++--
3 files changed, 26 insertions(+), 16 deletions(-)
diff --git a/drivers/usb/host/xhci-ring.c b/drivers/usb/host/xhci-ring.c
index 86aeaab412..b7b2e16410 100644
--- a/drivers/usb/host/xhci-ring.c
+++ b/drivers/usb/host/xhci-ring.c
@@ -432,9 +432,11 @@ static int event_ready(struct xhci_ctrl *ctrl)
*
* @param ctrl Host controller data structure
* @param expected TRB type expected from Event TRB
+ * @param nonblock when true do not block waiting for response
* @return pointer to event trb
*/
-union xhci_trb *xhci_wait_for_event(struct xhci_ctrl *ctrl, trb_type expected)
+union xhci_trb *xhci_wait_for_event(struct xhci_ctrl *ctrl, trb_type expected,
+ bool nonblock)
{
trb_type type;
unsigned long ts = get_timer(0);
@@ -442,8 +444,11 @@ union xhci_trb *xhci_wait_for_event(struct xhci_ctrl
*ctrl, trb_type expected)
do {
union xhci_trb *event = ctrl->event_ring->dequeue;
- if (!event_ready(ctrl))
+ if (!event_ready(ctrl)) {
+ if (nonblock)
+ return NULL;
continue;
+ }
type = TRB_FIELD_TO_TYPE(le32_to_cpu(event->event_cmd.flags));
if (type == expected)
@@ -493,7 +498,7 @@ static void abort_td(struct usb_device *udev, int ep_index)
xhci_queue_command(ctrl, NULL, udev->slot_id, ep_index, TRB_STOP_RING);
- event = xhci_wait_for_event(ctrl, TRB_TRANSFER);
+ event = xhci_wait_for_event(ctrl, TRB_TRANSFER, false);
field = le32_to_cpu(event->trans_event.flags);
BUG_ON(TRB_TO_SLOT_ID(field) != udev->slot_id);
BUG_ON(TRB_TO_EP_INDEX(field) != ep_index);
@@ -501,7 +506,7 @@ static void abort_td(struct usb_device *udev, int ep_index)
!= COMP_STOP)));
xhci_acknowledge_event(ctrl);
- event = xhci_wait_for_event(ctrl, TRB_COMPLETION);
+ event = xhci_wait_for_event(ctrl, TRB_COMPLETION, false);
BUG_ON(TRB_TO_SLOT_ID(le32_to_cpu(event->event_cmd.flags))
!= udev->slot_id || GET_COMP_CODE(le32_to_cpu(
event->event_cmd.status)) != COMP_SUCCESS);
@@ -509,7 +514,7 @@ static void abort_td(struct usb_device *udev, int ep_index)
xhci_queue_command(ctrl, (void *)((uintptr_t)ring->enqueue |
ring->cycle_state), udev->slot_id, ep_index, TRB_SET_DEQ);
- event = xhci_wait_for_event(ctrl, TRB_COMPLETION);
+ event = xhci_wait_for_event(ctrl, TRB_COMPLETION, false);
BUG_ON(TRB_TO_SLOT_ID(le32_to_cpu(event->event_cmd.flags))
!= udev->slot_id || GET_COMP_CODE(le32_to_cpu(
event->event_cmd.status)) != COMP_SUCCESS);
@@ -552,10 +557,11 @@ static void record_transfer_result(struct usb_device
*udev,
* @param pipe contains the DIR_IN or OUT , devnum
* @param length length of the buffer
* @param buffer buffer to be read/written based on the request
+ * @param nonblock when true do not block waiting for response
* @return returns 0 if successful else -1 on failure
*/
int xhci_bulk_tx(struct usb_device *udev, unsigned long pipe,
- int length, void *buffer)
+ int length, void *buffer, bool nonblock)
{
int num_trbs = 0;
struct xhci_generic_trb *start_trb;
@@ -714,8 +720,10 @@ int xhci_bulk_tx(struct usb_device *udev, unsigned long
pipe,
giveback_first_trb(udev, ep_index, start_cycle, start_trb);
- event = xhci_wait_for_event(ctrl, TRB_TRANSFER);
+ event = xhci_wait_for_event(ctrl, TRB_TRANSFER, nonblock);
if (!event) {
+ if (nonblock)
+ return -EINVAL;
debug("XHCI bulk transfer timed out, aborting...\n");
abort_td(udev, ep_index);
udev->status = USB_ST_NAK_REC; /* closest thing to a timeout */
@@ -911,7 +919,7 @@ int xhci_ctrl_tx(struct usb_device *udev, unsigned long
pipe,
giveback_first_trb(udev, ep_index, start_cycle, start_trb);
- event = xhci_wait_for_event(ctrl, TRB_TRANSFER);
+ event = xhci_wait_for_event(ctrl, TRB_TRANSFER, false);
if (!event)
goto abort;
field = le32_to_cpu(event->trans_event.flags);
@@ -929,7 +937,7 @@ int xhci_ctrl_tx(struct usb_device
[PATCH 5/9] xhci-ring.c: Add the poll_pend state to properly abort transactions
xhci_trl_tx and xhchi_bulk_tx can be called synchronously by other
drivers such as the usb storage or network, while the keyboard driver
exclusively uses the polling mode.
And pending polling transactions must be aborted before switching
modes to avoid corrupting the state of the controller.
Signed-off-by: Jason Wessel
---
drivers/usb/host/xhci-ring.c | 86 +---
1 file changed, 70 insertions(+), 16 deletions(-)
diff --git a/drivers/usb/host/xhci-ring.c b/drivers/usb/host/xhci-ring.c
index b7b2e16410..d6339f4f0a 100644
--- a/drivers/usb/host/xhci-ring.c
+++ b/drivers/usb/host/xhci-ring.c
@@ -24,6 +24,12 @@
#include
+static void *last_bulk_tx_buf;
+static struct usb_device *poll_last_udev;
+int poll_last_ep_index;
+static unsigned long bulk_tx_poll_ts;
+static bool poll_pend;
+
/**
* Is this TRB a link TRB or was the last TRB the last TRB in this event ring
* segment? I.e. would the updated event TRB pointer step off the end of the
@@ -549,19 +555,8 @@ static void record_transfer_result(struct usb_device *udev,
}
}
-/ Bulk and Control transfer methods /
-/**
- * Queues up the BULK Request
- *
- * @param udev pointer to the USB device structure
- * @param pipe contains the DIR_IN or OUT , devnum
- * @param length length of the buffer
- * @param buffer buffer to be read/written based on the request
- * @param nonblock when true do not block waiting for response
- * @return returns 0 if successful else -1 on failure
- */
-int xhci_bulk_tx(struct usb_device *udev, unsigned long pipe,
- int length, void *buffer, bool nonblock)
+static int _xhci_bulk_tx_queue(struct usb_device *udev, unsigned long pipe,
+ int length, void *buffer)
{
int num_trbs = 0;
struct xhci_generic_trb *start_trb;
@@ -575,7 +570,6 @@ int xhci_bulk_tx(struct usb_device *udev, unsigned long
pipe,
struct xhci_virt_device *virt_dev;
struct xhci_ep_ctx *ep_ctx;
struct xhci_ring *ring; /* EP transfer ring */
- union xhci_trb *event;
int running_total, trb_buff_len;
unsigned int total_packet_count;
@@ -719,20 +713,73 @@ int xhci_bulk_tx(struct usb_device *udev, unsigned long
pipe,
} while (running_total < length);
giveback_first_trb(udev, ep_index, start_cycle, start_trb);
+ return 0;
+}
+/ Bulk and Control transfer methods /
+/**
+ * Queues up the BULK Request
+ *
+ * @param udev pointer to the USB device structure
+ * @param pipe contains the DIR_IN or OUT , devnum
+ * @param length length of the buffer
+ * @param buffer buffer to be read/written based on the request
+ * @param nonblock when true do not block waiting for response
+ * @return returns 0 if successful else -1 on failure
+ */
+int xhci_bulk_tx(struct usb_device *udev, unsigned long pipe,
+int length, void *buffer, bool nonblock)
+{
+ u32 field;
+ int ret;
+ union xhci_trb *event;
+ struct xhci_ctrl *ctrl = xhci_get_ctrl(udev);
+ int ep_index = usb_pipe_ep_index(pipe);
+
+ if (poll_pend) {
+ /*
+* Abort a pending poll operation if it should have
+* timed out, or if this is a different buffer from a
+* separate request
+*/
+ if (get_timer(bulk_tx_poll_ts) > XHCI_TIMEOUT ||
+ last_bulk_tx_buf != buffer || poll_last_udev != udev ||
+ ep_index != poll_last_ep_index) {
+ abort_td(poll_last_udev, poll_last_ep_index);
+ poll_last_udev->status = USB_ST_NAK_REC; /* closest
thing to a timeout */
+ poll_last_udev->act_len = 0;
+ poll_pend = false;
+ }
+ } /* No else here because poll_pend might have changed above */
+ if (!poll_pend) {
+ last_bulk_tx_buf = buffer;
+ ret = _xhci_bulk_tx_queue(udev, pipe, length, buffer);
+ if (ret)
+ return ret;
+ }
event = xhci_wait_for_event(ctrl, TRB_TRANSFER, nonblock);
if (!event) {
- if (nonblock)
+ if (nonblock) {
+ if (!poll_pend) {
+ /* Start the timer */
+ bulk_tx_poll_ts = get_timer(0);
+ poll_last_udev = udev;
+ poll_last_ep_index = ep_index;
+ poll_pend = true;
+ }
return -EINVAL;
+ }
debug("XHCI bulk transfer timed out, aborting...\n");
abort_td(udev, ep_index);
udev->status = USB_ST_NAK_REC; /* closest thing to a timeout */
udev->act_len = 0;
+ poll_pend
[PATCH 6/9] xhci-ring: Fix crash when issuing "usb reset"
If a "usb reset" is issued when the poll_pend state is set the
abort_td() function will hit one of the BUG() statements in abort_td()
or the BUG() statement at the end of xhci_wait_for_event().
The controller has been reset, so the rest of the cleanup should be
skipped and poll_pend flag should be cleared.
Signed-off-by: Jason Wessel
---
drivers/usb/host/xhci-ring.c | 17 -
1 file changed, 12 insertions(+), 5 deletions(-)
diff --git a/drivers/usb/host/xhci-ring.c b/drivers/usb/host/xhci-ring.c
index d6339f4f0a..f2a07204cd 100644
--- a/drivers/usb/host/xhci-ring.c
+++ b/drivers/usb/host/xhci-ring.c
@@ -483,6 +483,8 @@ union xhci_trb *xhci_wait_for_event(struct xhci_ctrl *ctrl,
trb_type expected,
if (expected == TRB_TRANSFER)
return NULL;
+ if (poll_pend)
+ return NULL;
printf("XHCI timeout on event type %d... cannot recover.\n", expected);
BUG();
}
@@ -505,11 +507,16 @@ static void abort_td(struct usb_device *udev, int
ep_index)
xhci_queue_command(ctrl, NULL, udev->slot_id, ep_index, TRB_STOP_RING);
event = xhci_wait_for_event(ctrl, TRB_TRANSFER, false);
- field = le32_to_cpu(event->trans_event.flags);
- BUG_ON(TRB_TO_SLOT_ID(field) != udev->slot_id);
- BUG_ON(TRB_TO_EP_INDEX(field) != ep_index);
- BUG_ON(GET_COMP_CODE(le32_to_cpu(event->trans_event.transfer_len
- != COMP_STOP)));
+ if (event) {
+ field = le32_to_cpu(event->trans_event.flags);
+ BUG_ON(TRB_TO_SLOT_ID(field) != udev->slot_id);
+ BUG_ON(TRB_TO_EP_INDEX(field) != ep_index);
+ BUG_ON(GET_COMP_CODE(le32_to_cpu(event->trans_event.transfer_len
+!= COMP_STOP)));
+ } else {
+ debug("XHCI abort timeout\n");
+ return;
+ }
xhci_acknowledge_event(ctrl);
event = xhci_wait_for_event(ctrl, TRB_COMPLETION, false);
--
2.17.1
[PATCH 9/9] bcmgenet: Add support for rgmii-rxid
The commit 57805f2270c4 ("net: bcmgenet: Don't set ID_MODE_DIS when
not using RGMII") needed to be extended for the case of using the
rgmii-rxid. The latest version of the Rasbperry Pi4 dtb files for the
5.4 now specify the rgmii-rxid.
Signed-off-by: Jason Wessel
---
drivers/net/bcmgenet.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/net/bcmgenet.c b/drivers/net/bcmgenet.c
index 1b7e7ba2bf..ace1331362 100644
--- a/drivers/net/bcmgenet.c
+++ b/drivers/net/bcmgenet.c
@@ -457,7 +457,8 @@ static int bcmgenet_adjust_link(struct bcmgenet_eth_priv
*priv)
clrsetbits_32(priv->mac_reg + EXT_RGMII_OOB_CTRL, OOB_DISABLE,
RGMII_LINK | RGMII_MODE_EN);
- if (phy_dev->interface == PHY_INTERFACE_MODE_RGMII)
+ if (phy_dev->interface == PHY_INTERFACE_MODE_RGMII ||
+ phy_dev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
setbits_32(priv->mac_reg + EXT_RGMII_OOB_CTRL, ID_MODE_DIS);
writel(speed << CMD_SPEED_SHIFT, (priv->mac_reg + UMAC_CMD));
--
2.17.1
[PATCH 3/9] usb_kbd: succeed even if no interrupt is pending
After the initial configuration some USB keyboard+mouse devices never
return any kind of event on the interrupt line. In particular, the
device identified by "Cypress Cypress USB Keyboard / PS2 Mouse as
3f98.usb/usb1/1-1/1-1.3/1-1.3:1.0/0003:04B4:0101.0001/input/input0"
never returns a data packet until the first external input event.
I found this was also true with some newer model Dell keyboards.
When the device is plugged into a xhci controller there is also no
point in waiting 5 seconds for a device that is never going to present
data, so the call to the interrupt service was changed to a
nonblocking operation for the controllers that support this.
With the patch applied, the rpi3 and rpi4 work well with the more
complex keyboard devices.
Signed-off-by: Jason Wessel
---
common/usb_kbd.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/common/usb_kbd.c b/common/usb_kbd.c
index b316807844..3c0056e1b9 100644
--- a/common/usb_kbd.c
+++ b/common/usb_kbd.c
@@ -519,7 +519,9 @@ static int usb_kbd_probe_dev(struct usb_device *dev,
unsigned int ifnum)
1, 0, data->new, USB_KBD_BOOT_REPORT_SIZE) < 0) {
#else
if (usb_int_msg(dev, data->intpipe, data->new, data->intpktsize,
- data->intinterval, false) < 0) {
+ data->intinterval, true) < 0) {
+ /* Read first packet if the device provides it, else pick it up
later */
+ return 1;
#endif
printf("Failed to get keyboard state from device %04x:%04x\n",
dev->descriptor.idVendor, dev->descriptor.idProduct);
--
2.17.1
[PATCH 4/9] common/usb.c: Work around keyboard reporting "USB device not accepting new address"
When resetting the rpi3 board sometimes it will display:
USB device not accepting new address (error=0)
After the message appears, the usb keyboard will not work. It seems
that the configuration actually did succeed however. Checking the
device status for a return code of zero and continuing allows the usb
keyboard and other usb devices to work function.
Signed-off-by: Jason Wessel
---
common/usb.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/common/usb.c b/common/usb.c
index aad13fd9c5..0eb5d40a2d 100644
--- a/common/usb.c
+++ b/common/usb.c
@@ -1054,11 +1054,12 @@ static int usb_prepare_device(struct usb_device *dev,
int addr, bool do_read,
dev->devnum = addr;
err = usb_set_address(dev); /* set address */
-
- if (err < 0) {
+ if (err < 0)
+ debug("\n usb_set_address return < 0\n");
+ if (err < 0 && dev->status != 0) {
printf("\n USB device not accepting new address " \
"(error=%lX)\n", dev->status);
- return err;
+ return err;
}
mdelay(10); /* Let the SET_ADDRESS settle */
--
2.17.1
[PATCH] Convert CONFIG_SYS_MMC_ENV_DEV et al to Kconfig
This converts the following to Kconfig: CONFIG_SYS_MMC_ENV_DEV CONFIG_SYS_MMC_ENV_PART Cc: Priyanka Jain Cc: Madalin Bucur Signed-off-by: Tom Rini --- Due to some non-environment usage of the variables, cc'ing a few folks. --- configs/am335x_boneblack_vboot_defconfig | 1 + configs/am335x_shc_defconfig | 1 + configs/am335x_shc_ict_defconfig | 1 + configs/am335x_sl50_defconfig | 2 ++ configs/am57xx_evm_defconfig | 1 + configs/am57xx_hs_evm_defconfig | 1 + configs/am57xx_hs_evm_usb_defconfig | 1 + configs/am65x_evm_a53_defconfig | 1 + configs/am65x_hs_evm_a53_defconfig| 1 + configs/apalis-imx8qm_defconfig | 1 + configs/apalis-tk1_defconfig | 1 + configs/apalis_imx6_defconfig | 1 + configs/apalis_t30_defconfig | 1 + configs/bcm11130_defconfig| 1 - configs/beaver_defconfig | 1 + configs/brppt1_mmc_defconfig | 2 ++ configs/brxre1_defconfig | 2 ++ configs/cardhu_defconfig | 1 + configs/cei-tk1-som_defconfig | 1 + configs/colibri-imx8qxp_defconfig | 1 + configs/colibri_imx6_defconfig| 1 + configs/colibri_imx7_emmc_defconfig | 1 + configs/colibri_t30_defconfig | 1 + configs/dalmore_defconfig | 1 + configs/deneb_defconfig | 1 + configs/dra7xx_evm_defconfig | 1 + configs/dra7xx_hs_evm_defconfig | 1 + configs/dra7xx_hs_evm_usb_defconfig | 1 + configs/dragonboard410c_defconfig | 1 + configs/e2220-1170_defconfig | 1 + configs/evb-rk3328_defconfig | 1 + configs/ficus-rk3399_defconfig| 1 + configs/giedi_defconfig | 1 + configs/gwventana_emmc_defconfig | 1 + configs/gwventana_gw5904_defconfig| 1 + configs/hikey_defconfig | 1 + configs/imx6dl_mamoj_defconfig| 1 + configs/imx8mm_beacon_defconfig | 1 + configs/imx8mm_evk_defconfig | 1 + configs/imx8mp_evk_defconfig | 1 + configs/imx8mq_evk_defconfig | 1 + configs/imx8mq_phanbell_defconfig | 1 + configs/imx8qm_mek_defconfig | 1 + configs/imx8qm_rom7720_a1_4G_defconfig| 1 + configs/imx8qxp_mek_defconfig | 1 + configs/j721e_evm_a72_defconfig | 1 + configs/j721e_hs_evm_a72_defconfig| 1 + configs/j721e_hs_evm_r5_defconfig | 1 + configs/jetson-tk1_defconfig | 1 + configs/kp_imx6q_tpc_defconfig| 1 + configs/mx6dlarm2_defconfig | 1 + configs/mx6dlarm2_lpddr2_defconfig| 1 + configs/mx6qarm2_defconfig| 1 + configs/mx6qarm2_lpddr2_defconfig | 1 + configs/mx6sabresd_defconfig | 1 + configs/mx6slevk_defconfig| 1 + configs/mx6slevk_spl_defconfig| 1 + configs/mx6sxsabresd_defconfig| 1 + configs/mx6ul_14x14_evk_defconfig | 1 + configs/mx6ul_9x9_evk_defconfig | 1 + configs/mx6ull_14x14_evk_defconfig| 1 + configs/mx6ull_14x14_evk_plugin_defconfig | 1 + configs/mx6ulz_14x14_evk_defconfig| 1 + configs/nyan-big_defconfig| 1 + configs/omap4_sdp4430_defconfig | 1 + configs/omap5_uevm_defconfig | 1 + configs/opos6uldev_defconfig | 1 + configs/p2371-_defconfig | 1 + configs/p2371-2180_defconfig | 1 + configs/p2571_defconfig | 1 + configs/p2771--000_defconfig | 1 + configs/p2771--500_defconfig | 1 + configs/paz00_defconfig | 1 + configs/phycore-rk3288_defconfig | 1 + configs/pico-imx8mq_defconfig | 1 + configs/puma-rk3399_defconfig | 1 + configs/r8a77990_ebisu_defconfig | 2 ++ configs/r8a77995_draak_defconfig | 1 + configs/rcar3_salvator-x_defconfig| 2 ++ configs/rcar3_ulcb_defconfig | 2 ++ configs/riotboard_defconfig | 1 + configs/riotboard_spl_defconfig | 1 + configs/roc-cc-rk3328_defconfig | 1 + configs/rock-pi-e-rk3328_defconfig| 1 + configs/rock64-rk3328_defconfig | 1 + configs/rock960-rk3399_defconfig | 1 + configs/seaboard_defconfig| 1 + configs/sei510_defconfig | 2 ++ configs/sei610_defconfig | 2 ++ configs/somlabs_visionsom_6ull_defconfig | 1 + configs/tbs2910_defconfig | 2 ++ configs/tec-ng_defconfig | 1 + configs/tinker-rk3288_defconfig | 1 + configs/tinker-s-rk3288_defconfig | 1 + configs/venice2_defconfig | 1 +
[PATCH] mvebu: bubt: Drop dead code
The code around CONFIG_SYS_MMC_ENV_PART has been untested since merge.
This can be seen by it referencing 'mmc->part_num' which was migrated
elsewhere prior to this code being merged.
Cc: Joel Johnson
Cc: Stefan Roese
Signed-off-by: Tom Rini
---
cmd/mvebu/bubt.c | 15 ---
1 file changed, 15 deletions(-)
diff --git a/cmd/mvebu/bubt.c b/cmd/mvebu/bubt.c
index a27b0df8ae78..85ae588676fe 100644
--- a/cmd/mvebu/bubt.c
+++ b/cmd/mvebu/bubt.c
@@ -176,16 +176,6 @@ static int mmc_burn_image(size_t image_size)
return err;
}
-#ifdef CONFIG_SYS_MMC_ENV_PART
- if (mmc->part_num != CONFIG_SYS_MMC_ENV_PART) {
- err = mmc_switch_part(mmc_dev_num, CONFIG_SYS_MMC_ENV_PART);
- if (err) {
- printf("MMC partition switch failed\n");
- return err;
- }
- }
-#endif
-
/* SD reserves LBA-0 for MBR and boots from LBA-1,
* MMC/eMMC boots from LBA-0
*/
@@ -217,11 +207,6 @@ static int mmc_burn_image(size_t image_size)
}
printf("Done!\n");
-#ifdef CONFIG_SYS_MMC_ENV_PART
- if (mmc->part_num != CONFIG_SYS_MMC_ENV_PART)
- mmc_switch_part(mmc_dev_num, mmc->part_num);
-#endif
-
return 0;
}
--
2.17.1
Re: [PATCH] CONFIG_NR_DRAM_BANKS: Remove unreferenced code as its always defined
> Since commit 86cf1c82850f ("configs: Migrate CONFIG_NR_DRAM_BANKS") &
> commit 999a772d9f24 ("Kconfig: Migrate CONFIG_NR_DRAM_BANKS"),
> CONFIG_NR_DRAM_BANKS is always defined with a value (4 is default).
> It makes no sense to still carry code that is guarded with
> "#ifndef CONFIG_NR_DRAM_BANKS" (and similar). This patch removes
> all these unreferenced code paths.
I wasn't aware of this change but this likely broke some boards or some
functionality for archs like MIPS or PPC at the time. Unconditionally
enabling CONFIG_NR_DRAM_BANKS was actually incorrect without migrating
all users of bd->bi_memstart and bd->bi_memsize to bd->bi_dram[0].
Maybe most stuff kept working because board_f.c
executed setup_board_part1() and dram_init_banksize() in parallel on
archs like MIPS or PPC and redundant DRAM information had been carried
around since then.
To make this patch complete, we should finally remove the redundant
bi_memstart and bi_memsize. The replacement with bi_dram[0].start and
bi_dram[0].size should be rather trivial.
$ git grep -n bi_memstart
api/api_platform-mips.c:27: platform_set_mr(si, gd->bd-
>bi_memstart,
api/api_platform-powerpc.c:45: platform_set_mr(si, gd->bd-
>bi_memstart, gd->bd->bi_memsize, MR_ATTR_DRAM);
arch/arc/lib/cpu.c:30: gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
arch/mips/lib/boot.c:20:flush_cache(gd->bd->bi_memstart, gd-
>ram_top - gd->bd->bi_memstart);
arch/mips/lib/bootm.c:245: u64 mem_start = virt_to_phys((void
*)gd->bd->bi_memstart);
arch/powerpc/cpu/mpc83xx/fdt.c:124: fdt_fixup_memory(blob, (u64)bd-
>bi_memstart, (u64)bd->bi_memsize);
arch/powerpc/cpu/mpc83xx/traps.c:26:#define END_OF_MEM (gd->bd-
>bi_memstart + gd->bd->bi_memsize)
arch/powerpc/cpu/mpc85xx/fdt.c:675: fdt_fixup_memory(blob, (u64)bd-
>bi_memstart, (u64)bd->bi_memsize);
arch/powerpc/cpu/mpc85xx/fdt.c:678: ft_fixup_cpu(blob, (u64)bd-
>bi_memstart + (u64)bd->bi_memsize);
arch/powerpc/cpu/mpc85xx/traps.c:40:#define END_OF_MEM (gd->bd-
>bi_memstart + get_effective_memsize())
arch/powerpc/cpu/mpc86xx/fdt.c:30: fdt_fixup_memory(blob, (u64)bd-
>bi_memstart, (u64)bd->bi_memsize);
arch/powerpc/cpu/mpc86xx/traps.c:33:#define END_OF_MEM (gd->bd-
>bi_memstart + get_effective_memsize())
arch/powerpc/cpu/mpc8xx/fdt.c:28: fdt_fixup_memory(blob, (u64)bd-
>bi_memstart, (u64)bd->bi_memsize);
arch/powerpc/lib/bootm.c:301: base = (u64)gd->bd->bi_memstart;
arch/xtensa/lib/bootm.c:51: mem->start = bd->bi_memstart;
arch/xtensa/lib/bootm.c:52: mem->end = bd->bi_memstart + bd-
>bi_memsize;
board/Arcturus/ucp1020/spl.c:86:bd->bi_memstart =
CONFIG_SYS_INIT_L2_ADDR;
board/cadence/xtfpga/xtfpga.c:54: gd->bd->bi_memstart =
PHYSADDR(CONFIG_SYS_SDRAM_BASE);
board/freescale/p1010rdb/spl.c:72: bd->bi_memstart =
CONFIG_SYS_INIT_L2_ADDR;
board/freescale/p1_p2_rdb_pc/spl.c:78: bd->bi_memstart =
CONFIG_SYS_INIT_L2_ADDR;
board/freescale/t102xrdb/spl.c:106: bd->bi_memstart =
CONFIG_SYS_INIT_L3_ADDR;
board/freescale/t104xrdb/spl.c:97: bd->bi_memstart =
CONFIG_SYS_INIT_L3_ADDR;
board/freescale/t208xqds/spl.c:105: bd->bi_memstart =
CONFIG_SYS_INIT_L3_ADDR;
board/freescale/t208xrdb/spl.c:75: bd->bi_memstart =
CONFIG_SYS_INIT_L3_ADDR;
board/freescale/t4rdb/spl.c:78: bd->bi_memstart =
CONFIG_SYS_INIT_L3_ADDR;
cmd/bdinfo.c:76:bdinfo_print_num("memstart", (ulong)bd-
>bi_memstart);
cmd/bedbug.c:351: top = gd->bd->bi_memstart + gd->bd->bi_memsize;
common/board_f.c:610: bd->bi_memstart =
CONFIG_SYS_SDRAM_BASE;/* start of memory */
common/image.c:693: start = gd->bd->bi_memstart;
drivers/video/cfb_console.c:1999: if ((ulong)video_fb_address >=
bd->bi_memstart &&
drivers/video/cfb_console.c:2000: (ulong)video_fb_address <
bd->bi_memstart + bd->bi_memsize)
include/asm-generic/u-boot.h:30:unsigned
long bi_memstart;/* start of DRAM memory */
lib/lmb.c:130: lmb_add(lmb, bd->bi_memstart, bd->bi_memsize);
$ git grep -n bi_memsize
api/api_platform-mips.c:28: gd->bd->bi_memsize,
MR_ATTR_DRAM);
api/api_platform-powerpc.c:45: platform_set_mr(si, gd->bd-
>bi_memstart, gd->bd->bi_memsize, MR_ATTR_DRAM);
arch/arc/lib/cpu.c:31: gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
arch/powerpc/cpu/mpc83xx/fdt.c:124: fdt_fixup_memory(blob, (u64)bd-
>bi_memstart, (u64)bd->bi_memsize);
arch/powerpc/cpu/mpc83xx/traps.c:26:#define END_OF_MEM (gd->bd-
>bi_memstart + gd->bd->bi_memsize)
arch/powerpc/cpu/mpc85xx/fdt.c:675: fdt_fixup_memory(blob, (u64)bd-
>bi_memstart, (u64)bd->bi_memsize);
arch/powerpc/cpu/mpc85xx/fdt.c:678: ft_fixup_cpu(blob, (u64)bd-
>bi_memstart + (u64)bd->bi_memsize);
arch/powerpc/cpu/mpc86xx/fdt.c:30: fdt_fixup_memory(blob, (u64)bd-
>bi_memstart, (u64)bd->bi_memsize);
arch/powerpc/cpu/mpc8xx/fdt.c:28: fdt_fixup_memory(blob, (u64)bd-
>bi_memstart, (u64)bd->bi_memsize);
arch/powerpc/lib/bootm.c:302: size = (u64)gd->bd->bi_memsize;
arch/xtensa/lib/bootm.c:52:
[PATCH 1/1] test: do not rely on => being the prompt
In our tests we should use the customized prompt for testing.
Reported-by: Tom Rini
Signed-off-by: Heinrich Schuchardt
---
test/py/tests/test_efi_loader.py | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/test/py/tests/test_efi_loader.py b/test/py/tests/test_efi_loader.py
index ca68626cec..fc8d6b8655 100644
--- a/test/py/tests/test_efi_loader.py
+++ b/test/py/tests/test_efi_loader.py
@@ -199,6 +199,6 @@ def test_efi_grub_net(u_boot_console):
# Then exit cleanly
u_boot_console.wait_for('grub>')
u_boot_console.run_command('exit', wait_for_prompt=False,
wait_for_echo=False)
-u_boot_console.wait_for('=>')
+u_boot_console.wait_for(u_boot_console.prompt)
# And give us our U-Boot prompt back
u_boot_console.run_command('')
--
2.27.0
Re: [PATCH] CONFIG_NR_DRAM_BANKS: Remove unreferenced code as its always defined
On Fri, Jul 24, 2020 at 5:54 PM Stefan Roese wrote:
>
> Since commit 86cf1c82850f ("configs: Migrate CONFIG_NR_DRAM_BANKS") &
> commit 999a772d9f24 ("Kconfig: Migrate CONFIG_NR_DRAM_BANKS"),
> CONFIG_NR_DRAM_BANKS is always defined with a value (4 is default).
> It makes no sense to still carry code that is guarded with
> "#ifndef CONFIG_NR_DRAM_BANKS" (and similar). This patch removes
> all these unreferenced code paths.
>
> Signed-off-by: Stefan Roese
> Cc: Tom Rini
> Cc: Ramon Fried
> Cc: Simon Glass
> Cc: Michal Simek
> ---
> arch/x86/cpu/broadwell/cpu_from_spl.c | 2 --
> board/xilinx/zynqmp/zynqmp.c | 2 --
> cmd/bdinfo.c | 2 --
> common/board_f.c | 6 +-
> common/image.c| 3 +--
> common/init/handoff.c | 4
> drivers/pci/pci-uclass.c | 17 +
> include/asm-generic/u-boot.h | 2 --
> include/handoff.h | 2 --
> lib/fdtdec.c | 5 -
> lib/lmb.c | 7 ---
> 11 files changed, 3 insertions(+), 49 deletions(-)
>
> diff --git a/arch/x86/cpu/broadwell/cpu_from_spl.c
> b/arch/x86/cpu/broadwell/cpu_from_spl.c
> index 6567d50653..4d4cdafa2b 100644
> --- a/arch/x86/cpu/broadwell/cpu_from_spl.c
> +++ b/arch/x86/cpu/broadwell/cpu_from_spl.c
> @@ -53,14 +53,12 @@ void board_debug_uart_init(void)
>
> int dram_init_banksize(void)
> {
> -#ifdef CONFIG_NR_DRAM_BANKS
> struct spl_handoff *ho;
>
> ho = bloblist_find(BLOBLISTT_SPL_HANDOFF, sizeof(*ho));
> if (!ho)
> return log_msg_ret("Missing SPL hand-off info", -ENOENT);
> handoff_load_dram_banks(ho);
> -#endif
>
> return 0;
> }
> diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c
> index ebb7172908..4cc5cb6fd7 100644
> --- a/board/xilinx/zynqmp/zynqmp.c
> +++ b/board/xilinx/zynqmp/zynqmp.c
> @@ -467,10 +467,8 @@ int dram_init(void)
> #else
> int dram_init_banksize(void)
> {
> -#if defined(CONFIG_NR_DRAM_BANKS)
> gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
> gd->bd->bi_dram[0].size = get_effective_memsize();
> -#endif
>
> mem_map_fill();
>
> diff --git a/cmd/bdinfo.c b/cmd/bdinfo.c
> index 8b2c105e77..61daef4214 100644
> --- a/cmd/bdinfo.c
> +++ b/cmd/bdinfo.c
> @@ -47,7 +47,6 @@ void bdinfo_print_mhz(const char *name, unsigned long hz)
>
> static void print_bi_dram(const struct bd_info *bd)
> {
> -#ifdef CONFIG_NR_DRAM_BANKS
> int i;
>
> for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) {
> @@ -57,7 +56,6 @@ static void print_bi_dram(const struct bd_info *bd)
> bdinfo_print_num("-> size", bd->bi_dram[i].size);
> }
> }
> -#endif
> }
>
> __weak void arch_print_bdinfo(void)
> diff --git a/common/board_f.c b/common/board_f.c
> index 88ff0424a7..d7c13f63c9 100644
> --- a/common/board_f.c
> +++ b/common/board_f.c
> @@ -216,7 +216,6 @@ static int show_dram_config(void)
> {
> unsigned long long size;
>
> -#ifdef CONFIG_NR_DRAM_BANKS
> int i;
>
> debug("\nRAM Configuration:\n");
> @@ -229,9 +228,6 @@ static int show_dram_config(void)
> #endif
> }
> debug("\nDRAM: ");
> -#else
> - size = gd->ram_size;
> -#endif
>
> print_size(size, "");
> board_add_ram_info(0);
> @@ -242,7 +238,7 @@ static int show_dram_config(void)
>
> __weak int dram_init_banksize(void)
> {
> -#if defined(CONFIG_NR_DRAM_BANKS) && defined(CONFIG_SYS_SDRAM_BASE)
> +#if defined(CONFIG_SYS_SDRAM_BASE)
> gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
> gd->bd->bi_dram[0].size = get_effective_memsize();
> #endif
> diff --git a/common/image.c b/common/image.c
> index 9d7d5c17d1..2ed46f7685 100644
> --- a/common/image.c
> +++ b/common/image.c
> @@ -685,8 +685,7 @@ phys_size_t env_get_bootm_size(void)
> return tmp;
> }
>
> -#if (defined(CONFIG_ARM) || defined(CONFIG_MICROBLAZE)) && \
> - defined(CONFIG_NR_DRAM_BANKS)
> +#if defined(CONFIG_ARM) || defined(CONFIG_MICROBLAZE)
> start = gd->bd->bi_dram[0].start;
> size = gd->bd->bi_dram[0].size;
> #else
> diff --git a/common/init/handoff.c b/common/init/handoff.c
> index e00b43e6a7..c20fbf78b8 100644
> --- a/common/init/handoff.c
> +++ b/common/init/handoff.c
> @@ -13,7 +13,6 @@ DECLARE_GLOBAL_DATA_PTR;
> void handoff_save_dram(struct spl_handoff *ho)
> {
> ho->ram_size = gd->ram_size;
> -#ifdef CONFIG_NR_DRAM_BANKS
> {
> struct bd_info *bd = gd->bd;
> int i;
> @@ -23,7 +22,6 @@ void handoff_save_dram(struct spl_handoff *ho)
> ho->ram_bank[i].size = bd->bi_dram[i].size;
> }
> }
> -#endif
> }
>
> void handoff_load_dram_size(struct spl_handoff *ho)
> @@ -33,7 +31,6 @@ void handoff_load_dram_size(struct spl_handoff *ho)
>
> void
[PATCH 1/1] dm: remove superfluous comment for union ofnode_union
"future live tree" does not make sense anymore as we have CONFIG_OF_LIVE.
Signed-off-by: Heinrich Schuchardt
---
include/dm/ofnode.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/dm/ofnode.h b/include/dm/ofnode.h
index a0d3df7786..8df2facf99 100644
--- a/include/dm/ofnode.h
+++ b/include/dm/ofnode.h
@@ -48,7 +48,7 @@ struct resource;
* is not a really a pointer to a node: it is an offset value. See above.
*/
typedef union ofnode_union {
- const struct device_node *np; /* will be used for future live tree */
+ const struct device_node *np;
long of_offset;
} ofnode;
--
2.27.0
[PATCH v2 1/1] mtd: cfi_flash: read device tree correctly
The size of #address-cells and #size-cells is not correctly determined if
CONFIG_OF_LIVE=n.
dev_read_size_cells() and dev_read_addr_cells() do not walk up the device
tree to find the number of cells. On error they return 1 and 2
respectively. On qemu_arm64_defconfig this leads to the incorrect detection
of the address of the second flash bank as 0x400 instead of
0x400.
When running
qemu-system-aarch64 -machine virt -bios u-boot.bin \
-cpu cortex-a53 -nographic \
-drive if=3Dpflash,format=3Draw,index=3D1,file=3Denvstore.img
the command 'saveenv' fails with
Saving Environment to Flash... Error: start and/or end address not on
sector boundary
Error: start and/or end address not on sector boundary
Failed (1)
due to this incorrect address.
Use function fdtdec_get_addr_size_auto_noparent() to read the array of
flash banks from the device tree if CONFIG_OF_LIVE=n.
Add debug statements for testing.
Signed-off-by: Heinrich Schuchardt
---
v2:
Do not change the existing logic for CONFIG_OF_LIVE=y.
---
drivers/mtd/cfi_flash.c | 36
1 file changed, 36 insertions(+)
diff --git a/drivers/mtd/cfi_flash.c b/drivers/mtd/cfi_flash.c
index b7289ba539..0030949779 100644
--- a/drivers/mtd/cfi_flash.c
+++ b/drivers/mtd/cfi_flash.c
@@ -2466,6 +2466,9 @@ unsigned long flash_init(void)
}
#ifdef CONFIG_CFI_FLASH /* for driver model */
+
+#ifdef CONFIG_OF_LIVE
+
static int cfi_flash_probe(struct udevice *dev)
{
const fdt32_t *cell;
@@ -2488,6 +2491,7 @@ static int cfi_flash_probe(struct udevice *dev)
flash_info[cfi_flash_num_flash_banks].dev = dev;
flash_info[cfi_flash_num_flash_banks].base = addr;
+ debug("CFI flash at 0x%llx\n", addr);
cfi_flash_num_flash_banks++;
idx += addrc + sizec;
@@ -2497,6 +2501,38 @@ static int cfi_flash_probe(struct udevice *dev)
return 0;
}
+#else
+
+static int cfi_flash_probe(struct udevice *dev)
+{
+ const fdt32_t *cell;
+ int len;
+
+ /* decode regs; there may be multiple reg tuples. */
+ cell = dev_read_prop(dev, "reg", );
+ if (!cell)
+ return -ENOENT;
+
+ for (cfi_flash_num_flash_banks = 0; ; ++cfi_flash_num_flash_banks) {
+ phys_addr_t addr;
+
+ addr = fdtdec_get_addr_size_auto_noparent(
+ gd->fdt_blob, dev_of_offset(dev), "reg",
+ cfi_flash_num_flash_banks, NULL, false);
+ if (addr == FDT_ADDR_T_NONE)
+ break;
+
+ flash_info[cfi_flash_num_flash_banks].dev = dev;
+ flash_info[cfi_flash_num_flash_banks].base = addr;
+ debug("CFI flash at 0x%llx\n", addr);
+ }
+ gd->bd->bi_flashstart = flash_info[0].base;
+
+ return 0;
+}
+
+#endif
+
static const struct udevice_id cfi_flash_ids[] = {
{ .compatible = "cfi-flash" },
{ .compatible = "jedec-flash" },
--
2.27.0
Re: [PATCH 1/1] mtd: cfi_flash: read device tree correctly
On 24.07.20 11:14, Rick Chen wrote:
> Hi Heinrich
>
>> From: U-Boot [mailto:u-boot-boun...@lists.denx.de] On Behalf Of Heinrich
>> Schuchardt
>> Sent: Tuesday, July 21, 2020 10:51 AM
>> To: Stefan Roese
>> Cc: Simon Glass; u-boot@lists.denx.de; Heinrich Schuchardt
>> Subject: [PATCH 1/1] mtd: cfi_flash: read device tree correctly
>>
>> dev_read_size_cells() and dev_read_addr_cells() do not walk up the device
>> tree to find the number of cells. On error they return 1 and 2 respectively.
>> On qemu_arm64_defconfig this leads to the incorrect detection of address of
>> the second flash bank as 0x400 instead of 0x400.
>>
>> When running
>>
>> qemu-system-aarch64 -machine virt -bios u-boot.bin \
>> -cpu cortex-a53 -nographic \
>> -drive if=pflash,format=raw,index=1,file=envstore.img
>>
>> the command 'saveenv' fails with
>>
>> Saving Environment to Flash... Error: start and/or end address not on
>> sector boundary
>> Error: start and/or end address not on sector boundary
>> Failed (1)
>>
>> due to this incorrect address.
>>
>> Use function fdtdec_get_addr_size_auto_noparent() to read the array of flash
>> banks from the device tree.
>>
>> Signed-off-by: Heinrich Schuchardt
>> ---
>> drivers/mtd/cfi_flash.c | 20
>> 1 file changed, 8 insertions(+), 12 deletions(-)
>>
>> diff --git a/drivers/mtd/cfi_flash.c b/drivers/mtd/cfi_flash.c index
>> b7289ba539..dfa104bcf0 100644
>> --- a/drivers/mtd/cfi_flash.c
>> +++ b/drivers/mtd/cfi_flash.c
>> @@ -2469,28 +2469,24 @@ unsigned long flash_init(void) static int
>> cfi_flash_probe(struct udevice *dev) {
>> const fdt32_t *cell;
>> - int addrc, sizec;
>> - int len, idx;
>> -
>> - addrc = dev_read_addr_cells(dev);
>> - sizec = dev_read_size_cells(dev);
>> + int len;
>>
>> /* decode regs; there may be multiple reg tuples. */
>> cell = dev_read_prop(dev, "reg", );
>> if (!cell)
>> return -ENOENT;
>> - idx = 0;
>> - len /= sizeof(fdt32_t);
>> - while (idx < len) {
>> +
>> + for (cfi_flash_num_flash_banks = 0; ; ++cfi_flash_num_flash_banks) {
>> phys_addr_t addr;
>>
>> - addr = dev_translate_address(dev, cell + idx);
>> + addr = fdtdec_get_addr_size_auto_noparent(
>> + gd->fdt_blob, dev_of_offset(dev), "reg",
>> + cfi_flash_num_flash_banks, NULL, false);
>> + if (addr == FDT_ADDR_T_NONE)
>> + break;
>>
>> flash_info[cfi_flash_num_flash_banks].dev = dev;
>> flash_info[cfi_flash_num_flash_banks].base = addr;
>> - cfi_flash_num_flash_banks++;
>> -
>> - idx += addrc + sizec;
>> }
>> gd->bd->bi_flashstart = flash_info[0].base;
>>
>> --
>> 2.27.0
>>
>
> This patch remind me that I have encounter flash bank detection
> problem on AE350 platform a period time ago.
> And have commit a patch to work around this problem as below:
>
> commit cca8b1e5b20cdab7299a5ee7139e70783f73ccdf
>
> riscv: dts: Add #address-cells and #size-cells in nor node
>
> Those are required for cfi-flash driver to get correct address
> information.
> Also modify size description correctly.
>
> With this patch, there is unnecessary to re-declaration address-cells
> and size-cells in nor node indeed.
>
> Tested-by: Rick Chen
>
> Thanks,
> Rick
>
Dear Stefan, dear Rick,
thanks for testing on different systems.
The reason for the different test results is the usage of CONFIG_OF_LIVE:
CONFIG_OF_LIVE=y
* octeon_ebb7304_defconfig
CONFIG_OF_LIVE=n
* ae350_rv32_defconfig
* qemu_arm64_defconfig
dev_translate_address() behaves differently depending on the usage of a
live tree.
I will send a revised patch that only changes the behavior only for the
CONFIG_OF_LIVE=n case after testing qemu_arm64_defconfig both with and
without live tree.
Best regards
Heinrich
Re: [PATCH v2 8/8] test: dm: add a test for class button
Hi Simon,
> Hi Philippe,
>
> On Mon, 20 Jul 2020 at 08:30, Philippe REYNES
> wrote:
>>
>> Hi Simon,
>>
>> > Hi Philippe,
>> >
>> > On Fri, 17 Jul 2020 at 06:22, Philippe Reynes
>> > wrote:
>> >>
>> >> Add a test to confirm that we can read button state
>> >> using the button-gpio driver.
>> >>
>> >> Signed-off-by: Philippe Reynes
>> >> ---
>> >> Changelog:
>> >> v2:
>> >> - new commit in the serie
>> >>
>> >> test/dm/Makefile | 1 +
>> >> test/dm/button.c | 74
>> >>
>> >> 2 files changed, 75 insertions(+)
>> >> create mode 100644 test/dm/button.c
>> >
>> > This seems to fail with 'make qcheck'. Can you please take a look?
>> > I've left it unapplied for now.
>>
>> I've tried to reproduce this issue, but make qcheck don't work for me.
>> I have some issues with test for binman, patman, and dtoc.
>>
>> Could you provide me the log of the issue with 'make qcheck' please ?
>
> See below. What sort of issues are you seeing? I wonder if we should
> have a script to set up for running these tests fully.
>
>
> === FAILURES
> ===
> __
> test_button_exit_statuses
> ___
>
> u_boot_console = 0x7fe1121eef60>
>
> @pytest.mark.boardspec('sandbox')
> @pytest.mark.buildconfigspec('cmd_button')
> def test_button_exit_statuses(u_boot_console):
> """Test that non-input button commands correctly return the command
> success/failure status."""
>
> expected_response = 'rc:0'
> response = u_boot_console.run_command('button list; echo rc:$?')
> assert(expected_response in response)
> response = u_boot_console.run_command('button summer; echo rc:$?')
>> assert(expected_response in response)
> E assert 'rc:0' in "Button 'summer' not found (err=-16)\r\r\nrc:1"
>
> test/py/tests/test_button.py:15: AssertionError
> - Captured stdout call
> -
> => button list; echo rc:$?
> summer
> christmas
> rc:0
> => => button summer; echo rc:$?
> Button 'summer' not found (err=-16)
> rc:1
> =>
> == 1 failed, 512 passed, 59 skipped, 105
> deselected in 43.38s ==
I think I have found the issue. This issue only appears after the commit
9ba84329dc45 ("sandbox, test: add test for GPIO_HOG function") that uses
gpio_a 0, 1, 2 and 3.
I've sent a patch do change the gpio used for hog on sandbox. With this
patch, I don't reproduce this issue.
> Regards,
> Simon
Regards,
Philippe
[PATCH v3 3/8] cmd: button: add a new 'button' command
Adds a command 'button' that provides the list of buttons
supported by the board, and the state of a button.
Reviewed-by: Simon Glass
Signed-off-by: Philippe Reynes
---
Changelog:
v3:
- no change
v2
- no change
cmd/Kconfig | 11
cmd/Makefile | 1 +
cmd/button.c | 86
3 files changed, 98 insertions(+)
create mode 100644 cmd/button.c
diff --git a/cmd/Kconfig b/cmd/Kconfig
index bfe6c16..8ef87dc 100644
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -1679,6 +1679,17 @@ config CMD_BLOCK_CACHE
during development, but also allows the cache to be disabled when
it might hurt performance (e.g. when using the ums command).
+config CMD_BUTTON
+ bool "button"
+ depends on BUTTON
+ default y if BUTTON
+ help
+ Enable the 'button' command which allows to get the status of
+ buttons supported by the board. The buttonss can be listed with
+ 'button list' and state can be known with 'button '.
+ Any button drivers can be controlled with this command, e.g.
+ button_gpio.
+
config CMD_CACHE
bool "icache or dcache"
help
diff --git a/cmd/Makefile b/cmd/Makefile
index 7952138..6e0086b 100644
--- a/cmd/Makefile
+++ b/cmd/Makefile
@@ -33,6 +33,7 @@ obj-$(CONFIG_CMD_BOOTSTAGE) += bootstage.o
obj-$(CONFIG_CMD_BOOTZ) += bootz.o
obj-$(CONFIG_CMD_BOOTI) += booti.o
obj-$(CONFIG_CMD_BTRFS) += btrfs.o
+obj-$(CONFIG_CMD_BUTTON) += button.o
obj-$(CONFIG_CMD_CACHE) += cache.o
obj-$(CONFIG_CMD_CBFS) += cbfs.o
obj-$(CONFIG_CMD_CLK) += clk.o
diff --git a/cmd/button.c b/cmd/button.c
new file mode 100644
index 000..84ad165
--- /dev/null
+++ b/cmd/button.c
@@ -0,0 +1,86 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 Philippe Reynes
+ *
+ * Based on led.c
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+static const char *const state_label[] = {
+ [BUTTON_OFF]= "off",
+ [BUTTON_ON] = "on",
+};
+
+static int show_button_state(struct udevice *dev)
+{
+ int ret;
+
+ ret = button_get_state(dev);
+ if (ret >= BUTTON_COUNT)
+ ret = -EINVAL;
+ if (ret >= 0)
+ printf("%s\n", state_label[ret]);
+
+ return ret;
+}
+
+static int list_buttons(void)
+{
+ struct udevice *dev;
+ int ret;
+
+ for (uclass_find_first_device(UCLASS_BUTTON, );
+dev;
+uclass_find_next_device()) {
+ struct button_uc_plat *plat = dev_get_uclass_platdata(dev);
+
+ if (!plat->label)
+ continue;
+ printf("%-15s ", plat->label);
+ if (device_active(dev)) {
+ ret = show_button_state(dev);
+ if (ret < 0)
+ printf("Error %d\n", ret);
+ } else {
+ printf("\n");
+ }
+ }
+
+ return 0;
+}
+
+int do_button(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
+{
+ const char *button_label;
+ struct udevice *dev;
+ int ret;
+
+ /* Validate arguments */
+ if (argc < 2)
+ return CMD_RET_USAGE;
+ button_label = argv[1];
+ if (strncmp(button_label, "list", 4) == 0)
+ return list_buttons();
+
+ ret = button_get_by_label(button_label, );
+ if (ret) {
+ printf("Button '%s' not found (err=%d)\n", button_label, ret);
+ return CMD_RET_FAILURE;
+ }
+
+ ret = show_button_state(dev);
+
+ return 0;
+}
+
+U_BOOT_CMD(
+ button, 4, 1, do_button,
+ "manage buttons",
+ " \tGet button state\n"
+ "button list\t\tShow a list of buttons"
+);
--
2.7.4
[PATCH v3 8/8] test: dm: add a test for class button
Add a test to confirm that we can read button state
using the button-gpio driver.
Signed-off-by: Philippe Reynes
---
Changelog:
v3:
- no change
v2:
- new commit in the serie
test/dm/Makefile | 1 +
test/dm/button.c | 74
2 files changed, 75 insertions(+)
create mode 100644 test/dm/button.c
diff --git a/test/dm/Makefile b/test/dm/Makefile
index b03c96d..42b46cc 100644
--- a/test/dm/Makefile
+++ b/test/dm/Makefile
@@ -19,6 +19,7 @@ obj-$(CONFIG_ACPIGEN) += acpi_dp.o
obj-$(CONFIG_SOUND) += audio.o
obj-$(CONFIG_BLK) += blk.o
obj-$(CONFIG_BOARD) += board.o
+obj-$(CONFIG_BUTTON) += button.o
obj-$(CONFIG_DM_BOOTCOUNT) += bootcount.o
obj-$(CONFIG_CLK) += clk.o clk_ccf.o
obj-$(CONFIG_DEVRES) += devres.o
diff --git a/test/dm/button.c b/test/dm/button.c
new file mode 100644
index 000..890f470
--- /dev/null
+++ b/test/dm/button.c
@@ -0,0 +1,74 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2020 Philippe Reynes
+ *
+ * Based on led.c
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+/* Base test of the button uclass */
+static int dm_test_button_base(struct unit_test_state *uts)
+{
+ struct udevice *dev;
+
+ /* Get the top-level device */
+ ut_assertok(uclass_get_device(UCLASS_BUTTON, 0, ));
+ ut_assertok(uclass_get_device(UCLASS_BUTTON, 1, ));
+ ut_assertok(uclass_get_device(UCLASS_BUTTON, 2, ));
+ ut_asserteq(-ENODEV, uclass_get_device(UCLASS_BUTTON, 3, ));
+
+ return 0;
+}
+DM_TEST(dm_test_button_base, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
+
+/* Test of the button uclass using the button_gpio driver */
+static int dm_test_button_gpio(struct unit_test_state *uts)
+{
+ const int offset = 3;
+ struct udevice *dev, *gpio;
+
+ /*
+* Check that we can manipulate an BUTTON. BUTTON 1 is connected to GPIO
+* bank gpio_a, offset 3.
+*/
+ ut_assertok(uclass_get_device(UCLASS_BUTTON, 1, ));
+ ut_assertok(uclass_get_device(UCLASS_GPIO, 1, ));
+
+ ut_asserteq(0, sandbox_gpio_set_value(gpio, offset, 0));
+ ut_asserteq(0, sandbox_gpio_get_value(gpio, offset));
+ ut_asserteq(BUTTON_OFF, button_get_state(dev));
+
+ ut_asserteq(0, sandbox_gpio_set_value(gpio, offset, 1));
+ ut_asserteq(1, sandbox_gpio_get_value(gpio, offset));
+ ut_asserteq(BUTTON_ON, button_get_state(dev));
+
+ return 0;
+}
+DM_TEST(dm_test_button_gpio, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
+
+/* Test obtaining an BUTTON by label */
+static int dm_test_button_label(struct unit_test_state *uts)
+{
+ struct udevice *dev, *cmp;
+
+ ut_assertok(button_get_by_label("summer", ));
+ ut_asserteq(1, device_active(dev));
+ ut_assertok(uclass_get_device(UCLASS_BUTTON, 1, ));
+ ut_asserteq_ptr(dev, cmp);
+
+ ut_assertok(button_get_by_label("christmas", ));
+ ut_asserteq(1, device_active(dev));
+ ut_assertok(uclass_get_device(UCLASS_BUTTON, 2, ));
+ ut_asserteq_ptr(dev, cmp);
+
+ ut_asserteq(-ENODEV, button_get_by_label("spring", ));
+
+ return 0;
+}
+DM_TEST(dm_test_button_label, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
--
2.7.4
[PATCH v3 6/8] sandbox: enable button
Enable the support of button (driver and command) on sandbox. Reviewed-by: Simon Glass Signed-off-by: Philippe Reynes --- Changelog: v3: - no change v2: - no change configs/sandbox_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig index 6059d66..18cecf5 100644 --- a/configs/sandbox_defconfig +++ b/configs/sandbox_defconfig @@ -106,6 +106,8 @@ CONFIG_AXI_SANDBOX=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_DM_BOOTCOUNT=y CONFIG_DM_BOOTCOUNT_RTC=y +CONFIG_BUTTON=y +CONFIG_BUTTON_GPIO=y CONFIG_CLK=y CONFIG_CLK_COMPOSITE_CCF=y CONFIG_SANDBOX_CLK_CCF=y -- 2.7.4
[PATCH v3 4/8] sandbox: dtsi: add buttons
Adds two buttons on sandbox so button framework may be tested.
Reviewed-by: Simon Glass
Signed-off-by: Philippe Reynes
---
Changelog:
v3:
- update comptatible to "gpio-keys"
v2:
- no change
arch/sandbox/dts/sandbox.dtsi | 14 ++
1 file changed, 14 insertions(+)
diff --git a/arch/sandbox/dts/sandbox.dtsi b/arch/sandbox/dts/sandbox.dtsi
index e1f68cd..c76ecc0 100644
--- a/arch/sandbox/dts/sandbox.dtsi
+++ b/arch/sandbox/dts/sandbox.dtsi
@@ -15,6 +15,20 @@
#sound-dai-cells = <1>;
};
+ buttons {
+ compatible = "gpio-keys";
+
+ summer {
+ gpios = <_a 3 0>;
+ label = "summer";
+ };
+
+ christmas {
+ gpios = <_a 4 0>;
+ label = "christmas";
+ };
+ };
+
gpio_a: gpios@0 {
u-boot,dm-pre-reloc;
gpio-controller;
--
2.7.4
[PATCH v3 2/8] dm: button: add a driver for button driven by gpio
Add a simple driver which allows use of buttons attached to GPIOs.
Reviewed-by: Simon Glass
Signed-off-by: Philippe Reynes
---
Changelog:
v3:
- change compatible to gpio-keys and gpio-keys-polled
(feedback from Neil Armstrong)
v2:
- remove useless default in Kconfig
- re-order include
- fix condition in button_gpio_remove
drivers/button/Kconfig | 9
drivers/button/Makefile | 1 +
drivers/button/button-gpio.c | 112 +++
3 files changed, 122 insertions(+)
create mode 100644 drivers/button/button-gpio.c
diff --git a/drivers/button/Kconfig b/drivers/button/Kconfig
index 8301858..6b3ec7e 100644
--- a/drivers/button/Kconfig
+++ b/drivers/button/Kconfig
@@ -9,4 +9,13 @@ config BUTTON
can provide access to board-specific buttons. Use of the device tree
for configuration is encouraged.
+config BUTTON_GPIO
+ bool "Button gpio"
+ depends on BUTTON
+ help
+ Enable support for buttons which are connected to GPIO lines. These
+ GPIOs may be on the SoC or some other device which provides GPIOs.
+ The GPIO driver must used driver model. Buttons are configured using
+ the device tree.
+
endmenu
diff --git a/drivers/button/Makefile b/drivers/button/Makefile
index 0b4c128..fcc10eb 100644
--- a/drivers/button/Makefile
+++ b/drivers/button/Makefile
@@ -3,3 +3,4 @@
# Copyright (C) 2020 Philippe Reynes
obj-$(CONFIG_BUTTON) += button-uclass.o
+obj-$(CONFIG_BUTTON_GPIO) += button-gpio.o
diff --git a/drivers/button/button-gpio.c b/drivers/button/button-gpio.c
new file mode 100644
index 000..985ae7f
--- /dev/null
+++ b/drivers/button/button-gpio.c
@@ -0,0 +1,112 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 Philippe Reynes
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+struct button_gpio_priv {
+ struct gpio_desc gpio;
+};
+
+static enum button_state_t button_gpio_get_state(struct udevice *dev)
+{
+ struct button_gpio_priv *priv = dev_get_priv(dev);
+ int ret;
+
+ if (!dm_gpio_is_valid(>gpio))
+ return -EREMOTEIO;
+ ret = dm_gpio_get_value(>gpio);
+ if (ret < 0)
+ return ret;
+
+ return ret ? BUTTON_ON : BUTTON_OFF;
+}
+
+static int button_gpio_probe(struct udevice *dev)
+{
+ struct button_uc_plat *uc_plat = dev_get_uclass_platdata(dev);
+ struct button_gpio_priv *priv = dev_get_priv(dev);
+ int ret;
+
+ /* Ignore the top-level button node */
+ if (!uc_plat->label)
+ return 0;
+
+ ret = gpio_request_by_name(dev, "gpios", 0, >gpio, GPIOD_IS_IN);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static int button_gpio_remove(struct udevice *dev)
+{
+ /*
+* The GPIO driver may have already been removed. We will need to
+* address this more generally.
+*/
+ if (!IS_ENABLED(CONFIG_SANDBOX)) {
+ struct button_gpio_priv *priv = dev_get_priv(dev);
+
+ if (dm_gpio_is_valid(>gpio))
+ dm_gpio_free(dev, >gpio);
+ }
+
+ return 0;
+}
+
+static int button_gpio_bind(struct udevice *parent)
+{
+ struct udevice *dev;
+ ofnode node;
+ int ret;
+
+ dev_for_each_subnode(node, parent) {
+ struct button_uc_plat *uc_plat;
+ const char *label;
+
+ label = ofnode_read_string(node, "label");
+ if (!label) {
+ debug("%s: node %s has no label\n", __func__,
+ ofnode_get_name(node));
+ return -EINVAL;
+ }
+ ret = device_bind_driver_to_node(parent, "button_gpio",
+ofnode_get_name(node),
+node, );
+ if (ret)
+ return ret;
+ uc_plat = dev_get_uclass_platdata(dev);
+ uc_plat->label = label;
+ }
+
+ return 0;
+}
+
+static const struct button_ops button_gpio_ops = {
+ .get_state = button_gpio_get_state,
+};
+
+static const struct udevice_id button_gpio_ids[] = {
+ { .compatible = "gpio-keys" },
+ { .compatible = "gpio-keys-polled" },
+ { }
+};
+
+U_BOOT_DRIVER(button_gpio) = {
+ .name = "button_gpio",
+ .id = UCLASS_BUTTON,
+ .of_match = button_gpio_ids,
+ .ops= _gpio_ops,
+ .priv_auto_alloc_size = sizeof(struct button_gpio_priv),
+ .bind = button_gpio_bind,
+ .probe = button_gpio_probe,
+ .remove = button_gpio_remove,
+};
--
2.7.4
[PATCH v3 1/8] dm: button: add an uclass for button
Add a new uclass for button that implements two functions:
- button_get_by_label
- button_get_status
Reviewed-by: Simon Glass
Signed-off-by: Philippe Reynes
---
Changelog:
v3:
- no change
v2:
- re-order include
- use uclass_id_foreach_dev
- add comments to enum button_state_t
drivers/Kconfig| 2 ++
drivers/Makefile | 1 +
drivers/button/Kconfig | 12 +
drivers/button/Makefile| 5
drivers/button/button-uclass.c | 43 ++
include/button.h | 59 ++
include/dm/uclass-id.h | 1 +
7 files changed, 123 insertions(+)
create mode 100644 drivers/button/Kconfig
create mode 100644 drivers/button/Makefile
create mode 100644 drivers/button/button-uclass.c
create mode 100644 include/button.h
diff --git a/drivers/Kconfig b/drivers/Kconfig
index 7a839fa..119e412 100644
--- a/drivers/Kconfig
+++ b/drivers/Kconfig
@@ -16,6 +16,8 @@ source "drivers/block/Kconfig"
source "drivers/bootcount/Kconfig"
+source "drivers/button/Kconfig"
+
source "drivers/cache/Kconfig"
source "drivers/clk/Kconfig"
diff --git a/drivers/Makefile b/drivers/Makefile
index afd159e..2178871 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -1,5 +1,6 @@
# SPDX-License-Identifier: GPL-2.0+
+obj-$(CONFIG_$(SPL_TPL_)BUTTON) += button/
obj-$(CONFIG_$(SPL_TPL_)CACHE) += cache/
obj-$(CONFIG_$(SPL_TPL_)CLK) += clk/
obj-$(CONFIG_$(SPL_TPL_)DM) += core/
diff --git a/drivers/button/Kconfig b/drivers/button/Kconfig
new file mode 100644
index 000..8301858
--- /dev/null
+++ b/drivers/button/Kconfig
@@ -0,0 +1,12 @@
+menu "Button Support"
+
+config BUTTON
+ bool "Enable button support"
+ depends on DM
+ help
+ Many boards have buttons which can be used to change behaviour
(reset, ...).
+ U-Boot provides a uclass API to implement this feature. Button drivers
+ can provide access to board-specific buttons. Use of the device tree
+ for configuration is encouraged.
+
+endmenu
diff --git a/drivers/button/Makefile b/drivers/button/Makefile
new file mode 100644
index 000..0b4c128
--- /dev/null
+++ b/drivers/button/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2020 Philippe Reynes
+
+obj-$(CONFIG_BUTTON) += button-uclass.o
diff --git a/drivers/button/button-uclass.c b/drivers/button/button-uclass.c
new file mode 100644
index 000..1c742c2
--- /dev/null
+++ b/drivers/button/button-uclass.c
@@ -0,0 +1,43 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2020 Philippe Reynes
+ *
+ * Based on led-uclass.c
+ */
+
+#include
+#include
+#include
+#include
+
+int button_get_by_label(const char *label, struct udevice **devp)
+{
+ struct udevice *dev;
+ struct uclass *uc;
+
+ uclass_id_foreach_dev(UCLASS_BUTTON, dev, uc) {
+ struct button_uc_plat *uc_plat = dev_get_uclass_platdata(dev);
+
+ /* Ignore the top-level button node */
+ if (uc_plat->label && !strcmp(label, uc_plat->label))
+ return uclass_get_device_tail(dev, 0, devp);
+ }
+
+ return -ENODEV;
+}
+
+enum button_state_t button_get_state(struct udevice *dev)
+{
+ struct button_ops *ops = button_get_ops(dev);
+
+ if (!ops->get_state)
+ return -ENOSYS;
+
+ return ops->get_state(dev);
+}
+
+UCLASS_DRIVER(button) = {
+ .id = UCLASS_BUTTON,
+ .name = "button",
+ .per_device_platdata_auto_alloc_size = sizeof(struct button_uc_plat),
+};
diff --git a/include/button.h b/include/button.h
new file mode 100644
index 000..688b63b
--- /dev/null
+++ b/include/button.h
@@ -0,0 +1,59 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2020 Philippe Reynes
+ */
+
+#ifndef __BUTTON_H
+#define __BUTTON_H
+
+/**
+ * struct button_uc_plat - Platform data the uclass stores about each device
+ *
+ * @label: Button label
+ */
+struct button_uc_plat {
+ const char *label;
+};
+
+/**
+ * enum button_state_t - State used for button
+ * - BUTTON_OFF - Button is not pressed
+ * - BUTTON_ON - Button is pressed
+ * - BUTTON_COUNT - Number of button state
+ */
+enum button_state_t {
+ BUTTON_OFF = 0,
+ BUTTON_ON = 1,
+ BUTTON_COUNT,
+};
+
+struct button_ops {
+ /**
+* get_state() - get the state of a button
+*
+* @dev:button device to change
+* @return button state button_state_t, or -ve on error
+*/
+ enum button_state_t (*get_state)(struct udevice *dev);
+};
+
+#define button_get_ops(dev)((struct button_ops *)(dev)->driver->ops)
+
+/**
+ * button_get_by_label() - Find a button device by label
+ *
+ * @label: button label to look up
+ * @devp: Returns the associated device, if found
+ * @return 0 if found, -ENODEV if not found, other -ve on error
+ */
+int button_get_by_label(const
[PATCH v3 7/8] test/py: add tests for the button commands
Adds tests for the button commands.
Reviewed-by: Simon Glass
Signed-off-by: Philippe Reynes
---
Changelog:
v3:
- update compatible to "gpio-keys"
v2:
- no change (button uclass test is added in another commit
arch/sandbox/dts/test.dts| 14 ++
test/py/tests/test_button.py | 19 +++
2 files changed, 33 insertions(+)
create mode 100644 test/py/tests/test_button.py
diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts
index c3404c0..db8fa54 100644
--- a/arch/sandbox/dts/test.dts
+++ b/arch/sandbox/dts/test.dts
@@ -51,6 +51,20 @@
#sound-dai-cells = <1>;
};
+ buttons {
+ compatible = "gpio-keys";
+
+ summer {
+ gpios = <_a 3 0>;
+ label = "summer";
+ };
+
+ christmas {
+ gpios = <_a 4 0>;
+ label = "christmas";
+ };
+ };
+
cros_ec: cros-ec {
reg = <0 0>;
compatible = "google,cros-ec-sandbox";
diff --git a/test/py/tests/test_button.py b/test/py/tests/test_button.py
new file mode 100644
index 000..98067a9
--- /dev/null
+++ b/test/py/tests/test_button.py
@@ -0,0 +1,19 @@
+# SPDX-License-Identifier: GPL-2.0+
+
+import pytest
+
+@pytest.mark.boardspec('sandbox')
+@pytest.mark.buildconfigspec('cmd_button')
+def test_button_exit_statuses(u_boot_console):
+"""Test that non-input button commands correctly return the command
+success/failure status."""
+
+expected_response = 'rc:0'
+response = u_boot_console.run_command('button list; echo rc:$?')
+assert(expected_response in response)
+response = u_boot_console.run_command('button summer; echo rc:$?')
+assert(expected_response in response)
+
+expected_response = 'rc:1'
+response = u_boot_console.run_command('button nonexistent-button; echo
rc:$?')
+assert(expected_response in response)
--
2.7.4
[PATCH v3 5/8] sandbox64: enable button
Enable the support of button (driver and command) on sandbox64. Reviewed-by: Simon Glass Signed-off-by: Philippe Reynes --- Changelog: v3: - no change v2: - no change configs/sandbox64_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/configs/sandbox64_defconfig b/configs/sandbox64_defconfig index dcf2f44..875a9dc 100644 --- a/configs/sandbox64_defconfig +++ b/configs/sandbox64_defconfig @@ -92,6 +92,8 @@ CONFIG_ADC=y CONFIG_ADC_SANDBOX=y CONFIG_AXI=y CONFIG_AXI_SANDBOX=y +CONFIG_BUTTON=y +CONFIG_BUTTON_GPIO=y CONFIG_CLK=y CONFIG_CPU=y CONFIG_DM_DEMO=y -- 2.7.4
Re: [PATCH V2 7/7] env: Add support for explicit write access list
On Tue, Jul 07, 2020 at 08:51:39PM +0200, Marek Vasut wrote: > This option marks any U-Boot variable which does not have explicit 'w' > writeable flag set as read-only. This way the environment can be locked > down and only variables explicitly configured to be writeable can ever > be changed by either 'env import', 'env set' or loading user environment > from environment storage. > > Signed-off-by: Marek Vasut Reviewed-by: Tom Rini -- Tom signature.asc Description: PGP signature
Re: [PATCH V2 6/7] env: Add option to only ever append environment
On Tue, Jul 07, 2020 at 08:51:38PM +0200, Marek Vasut wrote: > Add configuration option which prevents the environment hash table to be > ever cleared and reloaded with different content. This is useful in case > the first environment loaded into the hash table contains e.g. sensitive > content which must not be dropped or reloaded. > > Signed-off-by: Marek Vasut Reviewed-by: Tom Rini -- Tom signature.asc Description: PGP signature
Re: [PATCH V2 4/7] env: Fix invalid env handling in env_init()
On Tue, Jul 07, 2020 at 08:51:36PM +0200, Marek Vasut wrote:
> This fixes the case where there are multiple environment drivers, one of
> them is the default environment one, and it is followed by an environment
> driver which does not implement .init() callback. The default environment
> driver sets gd->env_valid to ENV_INVALID and returns 0 from its .init()
> callback implementation, which is valid behavior for default environment.
>
> Since the subsequent environment driver does not implement .init(), it
> also does not modify the $ret variable in the loop. Therefore, the loop
> is exited with gd->env_valid=ENV_INVALID and ret=0, which means that the
> code further down in env_init() will not reset the environment to the
> default one, which is incorrect.
>
> This patch sets the $ret variable back to -ENOENT in case the env_valid
> is set to ENV_INVALID by an environment driver, so that the environment
> would be correctly reset back to default one, unless a subsequent driver
> loads a valid environment.
>
> Signed-off-by: Marek Vasut
> ---
> V2: Reword commit message
> ---
> env/env.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/env/env.c b/env/env.c
> index dcc25c030b..024d36fdbe 100644
> --- a/env/env.c
> +++ b/env/env.c
> @@ -300,6 +300,9 @@ int env_init(void)
>
> debug("%s: Environment %s init done (ret=%d)\n", __func__,
> drv->name, ret);
> +
> + if (gd->env_valid == ENV_INVALID)
> + ret = -ENOENT;
> }
>
> if (!prio)
So, I am not sure about this change. Given the whole thread that ends
in https://lists.denx.de/pipermail/u-boot/2020-June/417433.html this
particular part of the function is being too clever. I think it's
intentionally not doing what you're adding right here for some use
cases. I think that to cleanly achieve the goals of your series we need
to stop letting drv->init be optional so that we then stop doing the
particular we're doing with "ENOENT means runs this common code path for
many envs". We may also need to make sure the link order in
env/Makefile has nowhere first in all cases, rather than just most cases
like it does now, with a big comment on why.
--
Tom
signature.asc
Description: PGP signature
Re: [PATCH V2 5/7] env: nowhere: Implement .load callback
On Tue, Jul 07, 2020 at 08:51:37PM +0200, Marek Vasut wrote: > Add .load callback for the 'nowhere' environment driver. This is useful > for when the 'nowhere' driver is used in combination with other drivers > and should be used to load the default environment. > > Signed-off-by: Marek Vasut Reviewed-by: Tom Rini -- Tom signature.asc Description: PGP signature
Re: [PATCH V2 2/7] env: Add H_DEFAULT flag
On Tue, Jul 07, 2020 at 08:51:34PM +0200, Marek Vasut wrote: > Add another internal environment flag which indicates that the operation > is resetting the environment to the default one. This allows the env code > to discern between import of external environment and reset to default. > > Signed-off-by: Marek Vasut Reviewed-by: Tom Rini -- Tom signature.asc Description: PGP signature
Re: [PATCH V2 1/7] env: Warn on force access if ENV_ACCESS_IGNORE_FORCE set
On Tue, Jul 07, 2020 at 08:51:33PM +0200, Marek Vasut wrote: > If the ENV_ACCESS_IGNORE_FORCE is set, inform user that the variable > cannot be force-set if such attempt happens. > > Signed-off-by: Marek Vasut Reviewed-by: Tom Rini -- Tom signature.asc Description: PGP signature
Re: [PATCH V2 3/7] env: Discern environment coming from external storage
On Tue, Jul 07, 2020 at 08:51:35PM +0200, Marek Vasut wrote: > Add another custom environment flag which discerns environment coming > from external storage from environment set by U-Boot itself. > > Signed-off-by: Marek Vasut Reviewed-by: Tom Rini -- Tom signature.asc Description: PGP signature
[PATCH] CONFIG_NR_DRAM_BANKS: Remove unreferenced code as its always defined
Since commit 86cf1c82850f ("configs: Migrate CONFIG_NR_DRAM_BANKS") &
commit 999a772d9f24 ("Kconfig: Migrate CONFIG_NR_DRAM_BANKS"),
CONFIG_NR_DRAM_BANKS is always defined with a value (4 is default).
It makes no sense to still carry code that is guarded with
"#ifndef CONFIG_NR_DRAM_BANKS" (and similar). This patch removes
all these unreferenced code paths.
Signed-off-by: Stefan Roese
Cc: Tom Rini
Cc: Ramon Fried
Cc: Simon Glass
Cc: Michal Simek
---
arch/x86/cpu/broadwell/cpu_from_spl.c | 2 --
board/xilinx/zynqmp/zynqmp.c | 2 --
cmd/bdinfo.c | 2 --
common/board_f.c | 6 +-
common/image.c| 3 +--
common/init/handoff.c | 4
drivers/pci/pci-uclass.c | 17 +
include/asm-generic/u-boot.h | 2 --
include/handoff.h | 2 --
lib/fdtdec.c | 5 -
lib/lmb.c | 7 ---
11 files changed, 3 insertions(+), 49 deletions(-)
diff --git a/arch/x86/cpu/broadwell/cpu_from_spl.c
b/arch/x86/cpu/broadwell/cpu_from_spl.c
index 6567d50653..4d4cdafa2b 100644
--- a/arch/x86/cpu/broadwell/cpu_from_spl.c
+++ b/arch/x86/cpu/broadwell/cpu_from_spl.c
@@ -53,14 +53,12 @@ void board_debug_uart_init(void)
int dram_init_banksize(void)
{
-#ifdef CONFIG_NR_DRAM_BANKS
struct spl_handoff *ho;
ho = bloblist_find(BLOBLISTT_SPL_HANDOFF, sizeof(*ho));
if (!ho)
return log_msg_ret("Missing SPL hand-off info", -ENOENT);
handoff_load_dram_banks(ho);
-#endif
return 0;
}
diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c
index ebb7172908..4cc5cb6fd7 100644
--- a/board/xilinx/zynqmp/zynqmp.c
+++ b/board/xilinx/zynqmp/zynqmp.c
@@ -467,10 +467,8 @@ int dram_init(void)
#else
int dram_init_banksize(void)
{
-#if defined(CONFIG_NR_DRAM_BANKS)
gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].size = get_effective_memsize();
-#endif
mem_map_fill();
diff --git a/cmd/bdinfo.c b/cmd/bdinfo.c
index 8b2c105e77..61daef4214 100644
--- a/cmd/bdinfo.c
+++ b/cmd/bdinfo.c
@@ -47,7 +47,6 @@ void bdinfo_print_mhz(const char *name, unsigned long hz)
static void print_bi_dram(const struct bd_info *bd)
{
-#ifdef CONFIG_NR_DRAM_BANKS
int i;
for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) {
@@ -57,7 +56,6 @@ static void print_bi_dram(const struct bd_info *bd)
bdinfo_print_num("-> size", bd->bi_dram[i].size);
}
}
-#endif
}
__weak void arch_print_bdinfo(void)
diff --git a/common/board_f.c b/common/board_f.c
index 88ff0424a7..d7c13f63c9 100644
--- a/common/board_f.c
+++ b/common/board_f.c
@@ -216,7 +216,6 @@ static int show_dram_config(void)
{
unsigned long long size;
-#ifdef CONFIG_NR_DRAM_BANKS
int i;
debug("\nRAM Configuration:\n");
@@ -229,9 +228,6 @@ static int show_dram_config(void)
#endif
}
debug("\nDRAM: ");
-#else
- size = gd->ram_size;
-#endif
print_size(size, "");
board_add_ram_info(0);
@@ -242,7 +238,7 @@ static int show_dram_config(void)
__weak int dram_init_banksize(void)
{
-#if defined(CONFIG_NR_DRAM_BANKS) && defined(CONFIG_SYS_SDRAM_BASE)
+#if defined(CONFIG_SYS_SDRAM_BASE)
gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].size = get_effective_memsize();
#endif
diff --git a/common/image.c b/common/image.c
index 9d7d5c17d1..2ed46f7685 100644
--- a/common/image.c
+++ b/common/image.c
@@ -685,8 +685,7 @@ phys_size_t env_get_bootm_size(void)
return tmp;
}
-#if (defined(CONFIG_ARM) || defined(CONFIG_MICROBLAZE)) && \
- defined(CONFIG_NR_DRAM_BANKS)
+#if defined(CONFIG_ARM) || defined(CONFIG_MICROBLAZE)
start = gd->bd->bi_dram[0].start;
size = gd->bd->bi_dram[0].size;
#else
diff --git a/common/init/handoff.c b/common/init/handoff.c
index e00b43e6a7..c20fbf78b8 100644
--- a/common/init/handoff.c
+++ b/common/init/handoff.c
@@ -13,7 +13,6 @@ DECLARE_GLOBAL_DATA_PTR;
void handoff_save_dram(struct spl_handoff *ho)
{
ho->ram_size = gd->ram_size;
-#ifdef CONFIG_NR_DRAM_BANKS
{
struct bd_info *bd = gd->bd;
int i;
@@ -23,7 +22,6 @@ void handoff_save_dram(struct spl_handoff *ho)
ho->ram_bank[i].size = bd->bi_dram[i].size;
}
}
-#endif
}
void handoff_load_dram_size(struct spl_handoff *ho)
@@ -33,7 +31,6 @@ void handoff_load_dram_size(struct spl_handoff *ho)
void handoff_load_dram_banks(struct spl_handoff *ho)
{
-#ifdef CONFIG_NR_DRAM_BANKS
{
struct bd_info *bd = gd->bd;
int i;
@@ -43,5 +40,4 @@ void handoff_load_dram_banks(struct spl_handoff *ho)
bd->bi_dram[i].size = ho->ram_bank[i].size;
}
}
Re: [PATCH v4 00/27] rockchip: x86: Support building ROM files automatically with binman
Hi Kever (and other Rockchip people), Are there any more comments on this series? I can pick it up via -dm but I would like to get more comments if possible. I'd also like to see if someone can take on removing the other ad-hoc Rockchip script. Regards, Simon On Sun, 19 Jul 2020 at 21:07, Simon Glass wrote: > > Hi Bin, > > On Sun, 19 Jul 2020 at 19:12, Bin Meng wrote: > > > > Hi Simon, > > > > On Mon, Jul 20, 2020 at 3:56 AM Simon Glass wrote: > > > > > > Rockchip-based Chromebooks support booting from SPI flash. It is annoying > > > to have to manually build the SPI image when the SD image is built > > > automatically. > > > > > > This feature is already available for x86 devices, so the existing > > > mechanism is reused. Briefly, this allows a BUILD_ROM environment variable > > > to be provided to indicate that any required binary blobs are present and > > > it is safe to build the ROM. > > > > > > A new 'mkimage' type is added to binman to support building binaries > > > containing mkimagem using a binman definition to configure it. This avoids > > > Makefile/shell/Python code to do the same thing. > > > > > > This series also migrates some rockchip boards to use binman to produce > > > their FIT as well, resulting in removing the fit_spl_optee.sh script. > > > > > > Other archs and the rest of rockchip could be migrated too. > > > > > > This series uses binman to produce a ROM image on two selected > > > Chromebooks, Bob (RK3399) and Jerry (RK3388). > > > > > > Changes in v4: > > > - Add a new CONFIG_ROCKCHIP_SPI_IMAGE to control SPI-image generation > > > - Use CONFIG_ROCKCHIP_SPI_IMAGE to select the image > > > - Update for changes to arch/arm/mach-k3/config.mk > > > - Move the .itb output to a separate rockchip-optee.dtsi file > > > - Add a check for CONFIG_FIT before building the .its > > > > > > Changes in v3: > > > - Add a comment about CONFIG_SPL_FRAMEWORK > > > - Drop rockchip changes which should not be in this patch > > > - Move in the rockchip changes mistakenly in the earlier x86 patch > > > - Drop use of rk322x.dtsi > > > - Add changes to rk3288-u-boot.dtsi instead > > > - Drop leftover debugging > > > > It looks you have applied part of the v3 in u-boot-dm, and sent the > > remaining patches as v4? > > > > I re-assigned this series to you in patchwork. > > Yes I applied the binman patches and those that were reviewed. > > I am not sure if this shold be an x86 or rockchip series, or perhaps > we just wait until people have had a look. > > Regards, > Simon
[PATCH] arm: imx6q: pcm058: Rework SPI NOR configuration
Enable CONFIG_SPL_DM_SPI_FLASH to be able to boot from SPI NOR,
modify the offset of U-boot proper in the SPI NOR, so the
difference in offset matches between SPL and U-boot matches that of
the SD Card, allowing u-boot-with-spl.imx to also be copied to SPI
NOR at an offset of 0x400. Update the README to reflect this
change.
Signed-off-by: Niel Fourie
Cc: Stefano Babic
---
board/phytec/pcm058/README | 20
configs/pcm058_defconfig | 3 ++-
2 files changed, 14 insertions(+), 9 deletions(-)
diff --git a/board/phytec/pcm058/README b/board/phytec/pcm058/README
index 02be0994fc..687366bffb 100644
--- a/board/phytec/pcm058/README
+++ b/board/phytec/pcm058/README
@@ -61,17 +61,21 @@ Then, clear the SPI flash:
=> sf probe
=> sf erase 0x0 0x100
-Load the SPL from raw MMC into memory and copy to the SPI. The SPL is maximum
-392*512-byte blocks in size therefore 0x188 blocks, totaling 0x31000 bytes:
+Load the equivalent of u-boot-with-spl.imx from the raw MMC into memory and
+copy to the SPI. The SPL is expected at an offset of 0x400, and its size is
+maximum 392*512-byte blocks in size, therefore 0x188 blocks, totaling 0x31000
+bytes. Assume U-boot should fit into 640KiB, therefore 0x500 512-byte blocks,
+totalling 0xA bytes. Adding these together:
-=> mmc read ${loadaddr} 0x2 0x188
-=> sf write ${loadaddr} 0x400 0x31000
+=> mmc read ${loadaddr} 0x2 0x688
+=> sf write ${loadaddr} 0x400 0xD1000
-Load the U-boot binary into memory and copy to the SPI. U-boot should fit into
-640KiB, so 0x500 512-byte blocks, totalling 0xA bytes:
+The SPL is located at offset 0x400, and U-boot at 0x31400 in SPI flash, as to
+match the SD Card layout. This would allow, instead of reading from the SD Card
+above, with networking and TFTP correctly configured, the equivalent of:
-=> mmc read ${loadaddr} 0x18a 0x500
-=> sf write ${loadaddr} 0x4 0xA
+=> tftp u-boot-with-spl.imx
+=> sf write ${fileaddr} 0x400 ${filesize}
The default NAND bootscripts expect a single MTD partition named "rootfs",
which in turn contains the UBI volumes "fit" (which contains the kernel fit-
diff --git a/configs/pcm058_defconfig b/configs/pcm058_defconfig
index c491cbf9a0..b085a7dd0c 100644
--- a/configs/pcm058_defconfig
+++ b/configs/pcm058_defconfig
@@ -7,7 +7,7 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_ENV_SIZE=0x4000
CONFIG_ENV_OFFSET=0x10
CONFIG_ENV_SECT_SIZE=0x1
-CONFIG_SYS_SPI_U_BOOT_OFFS=0x4
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x31400
CONFIG_MX6_OCRAM_256KB=y
CONFIG_TARGET_PCM058=y
CONFIG_SPL_TEXT_BASE=0x00908000
@@ -34,6 +34,7 @@ CONFIG_SPL_SEPARATE_BSS=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x18a
CONFIG_SPL_DMA=y
CONFIG_SPL_FS_EXT4=y
+CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_SPL_YMODEM_SUPPORT=y
--
2.26.2
Re: [U-Boot] Pull request: u-boot-riscv/master 20200724
On Fri, Jul 24, 2020 at 03:18:45PM +0800, ub...@andestech.com wrote: > Hi Tom, > > Please pull some riscv updates: > > - Fix SiFive HiFive Unleashed board booting failure problem. > - Enable SiFive fu540 PWM driver. > - Support SiFive fu540: SPI boot. > - Update OpenSBI used for RISC-V CI testing. > - Revert "riscv: Allow use of reset drivers". > - Revert "Revert "riscv: sifive: fu540: Add gpio-restart support"". > - sysreset: syscon: > - Don't assume default value for offset and mask property. > - Support value property. > - qemu: Add syscon reboot and poweroff support. > - Fix SIFIVE debug serial dependency. > - Fix linking error when building u-boot-spl with no SMP support. > - AE350 use fdtdec_get_addr_size_auto_noparent to parse smc reg. > - Make memory node available to SPL in hifive-unleashed-a00-u-boot.dtsi > - SiFive fu540 avoid using hardcoded ram base and size. > > Thanks > Rick > > https://travis-ci.org/github/rickchen36/u-boot-riscv/builds/710968496 > > The following changes since commit 5d3a21df6694ebd66d5c34c9d62a26edc7456fc7: > > Merge tag 'dm-pull-20jul20' of git://git.denx.de/u-boot-dm (2020-07-23 > 15:56:06 -0400) > > are available in the Git repository at: > > g...@gitlab.denx.de:u-boot/custodians/u-boot-riscv.git > > for you to fetch changes up to ecb70bdb9f12b694e3a50895a759119b3fc27507: > > ram: sifive: Avoid using hardcoded ram base and size (2020-07-24 14:56:29 > +0800) > Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH v2 06/10] drivers: spi: Add SPI controller driver for Octeon
On 24.07.20 15:56, Daniel Schwierzeck wrote:
Am Donnerstag, den 23.07.2020, 12:17 +0200 schrieb Stefan Roese:
From: Suneel Garapati
Adds support for SPI controllers found on Octeon II/III and Octeon TX
TX2 SoC platforms.
Signed-off-by: Aaron Williams
Signed-off-by: Suneel Garapati
Signed-off-by: Stefan Roese
Cc: Daniel Schwierzeck
Cc: Aaron Williams
Cc: Chandrakala Chavva
Cc: Jagan Teki
---
Changes in v2:
- Newly added to this series
- Removed inclusion of "common.h"
- Added "depends on DM_PCI" to Kconfig
- Tested on MIPS Octeon and ARM Octeon TX2
- Fixed issues with Octeon TX2 registration. Now only one driver is
registered and the "ops" is overwritten in the Octeon TX2 case.
- Use dev_get_driver_data() to get the driver data struct
- Removed "struct pci_device_id" definition and U_BOOT_PCI_DEVICE()
as its not needed for the PCI based probing on Octeon TX2
drivers/spi/Kconfig | 8 +
drivers/spi/Makefile | 1 +
drivers/spi/octeon_spi.c | 647 +++
3 files changed, 656 insertions(+)
create mode 100644 drivers/spi/octeon_spi.c
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 30d808d7bb..3fc2d0674a 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -240,6 +240,14 @@ config NXP_FSPI
Enable the NXP FlexSPI (FSPI) driver. This driver can be used to
access the SPI NOR flash on platforms embedding this NXP IP core.
+config OCTEON_SPI
+ bool "Octeon SPI driver"
+ depends on DM_PCI && (ARCH_OCTEON || ARCH_OCTEONTX || ARCH_OCTEONTX2)
+ help
+ Enable the Octeon SPI driver. This driver can be used to
+ access the SPI NOR flash on Octeon II/III and OcteonTX/TX2
+ SoC platforms.
+
config OMAP3_SPI
bool "McSPI driver for OMAP"
help
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 4e7461771f..b5c9ff1af8 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -43,6 +43,7 @@ obj-$(CONFIG_MXC_SPI) += mxc_spi.o
obj-$(CONFIG_MXS_SPI) += mxs_spi.o
obj-$(CONFIG_NXP_FSPI) += nxp_fspi.o
obj-$(CONFIG_ATCSPI200_SPI) += atcspi200_spi.o
+obj-$(CONFIG_OCTEON_SPI) += octeon_spi.o
obj-$(CONFIG_OMAP3_SPI) += omap3_spi.o
obj-$(CONFIG_PIC32_SPI) += pic32_spi.o
obj-$(CONFIG_PL022_SPI) += pl022_spi.o
diff --git a/drivers/spi/octeon_spi.c b/drivers/spi/octeon_spi.c
new file mode 100644
index 00..2fb39e444c
--- /dev/null
+++ b/drivers/spi/octeon_spi.c
@@ -0,0 +1,647 @@
+// SPDX-License-Identifier:GPL-2.0
+/*
+ * Copyright (C) 2018 Marvell International Ltd.
+ *
+ * https://spdx.org/licenses
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define OCTEON_SPI_MAX_BYTES 9
+#define OCTEON_SPI_MAX_CLOCK_HZ5000
+
+#define OCTEON_SPI_NUM_CS 4
+
+#define OCTEON_SPI_CS_VALID(cs)((cs) < OCTEON_SPI_NUM_CS)
+
+#define MPI_CFG0x
+#define MPI_STS0x0008
+#define MPI_TX 0x0010
+#define MPI_XMIT 0x0018
+#define MPI_WIDE_DAT 0x0040
+#define MPI_IO_CTL 0x0048
+#define MPI_DAT(X) (0x0080 + ((X) << 3))
+#define MPI_WIDE_BUF(X)(0x0800 + ((X) << 3))
+#define MPI_CYA_CFG0x1000
+#define MPI_CLKEN 0x1080
+
+#define MPI_CFG_ENABLE BIT_ULL(0)
+#define MPI_CFG_IDLELO BIT_ULL(1)
+#define MPI_CFG_CLK_CONT BIT_ULL(2)
+#define MPI_CFG_WIREOR BIT_ULL(3)
+#define MPI_CFG_LSBFIRST BIT_ULL(4)
+#define MPI_CFG_CS_STICKY BIT_ULL(5)
+#define MPI_CFG_CSHI BIT_ULL(7)
+#define MPI_CFG_IDLECLKS GENMASK_ULL(9, 8)
+#define MPI_CFG_TRITX BIT_ULL(10)
+#define MPI_CFG_CSLATE BIT_ULL(11)
+#define MPI_CFG_CSENA0 BIT_ULL(12)
+#define MPI_CFG_CSENA1 BIT_ULL(13)
+#define MPI_CFG_CSENA2 BIT_ULL(14)
+#define MPI_CFG_CSENA3 BIT_ULL(15)
+#define MPI_CFG_CLKDIV GENMASK_ULL(28, 16)
+#define MPI_CFG_LEGACY_DIS BIT_ULL(31)
+#define MPI_CFG_IOMODE GENMASK_ULL(35, 34)
+#define MPI_CFG_TB100_EN BIT_ULL(49)
+
+#define MPI_DAT_DATA GENMASK_ULL(7, 0)
+
+#define MPI_STS_BUSY BIT_ULL(0)
+#define MPI_STS_MPI_INTR BIT_ULL(1)
+#define MPI_STS_RXNUM GENMASK_ULL(12, 8)
+
+#define MPI_TX_TOTNUM GENMASK_ULL(4, 0)
+#define MPI_TX_TXNUM GENMASK_ULL(12, 8)
+#define MPI_TX_LEAVECS BIT_ULL(16)
+#define MPI_TX_CSIDGENMASK_ULL(21, 20)
+
+#define MPI_XMIT_TOTNUMGENMASK_ULL(10, 0)
+#define MPI_XMIT_TXNUM GENMASK_ULL(30, 20)
+#define MPI_XMIT_BUF_SEL BIT_ULL(59)
+#define MPI_XMIT_LEAVECS BIT_ULL(60)
+#define MPI_XMIT_CSID GENMASK_ULL(62, 61)
+
+enum {
+ PROBE_PCI = 0, /* PCI based probing */
+ PROBE_DT, /* DT based probing */
+};
+
+/* Used on Octeon TX2 */
Re: [PATCH v2 06/10] drivers: spi: Add SPI controller driver for Octeon
Am Donnerstag, den 23.07.2020, 12:17 +0200 schrieb Stefan Roese: > From: Suneel Garapati > > Adds support for SPI controllers found on Octeon II/III and Octeon TX > TX2 SoC platforms. > > Signed-off-by: Aaron Williams > Signed-off-by: Suneel Garapati > Signed-off-by: Stefan Roese > Cc: Daniel Schwierzeck > Cc: Aaron Williams > Cc: Chandrakala Chavva > Cc: Jagan Teki > > --- > > Changes in v2: > - Newly added to this series > - Removed inclusion of "common.h" > - Added "depends on DM_PCI" to Kconfig > - Tested on MIPS Octeon and ARM Octeon TX2 > - Fixed issues with Octeon TX2 registration. Now only one driver is > registered and the "ops" is overwritten in the Octeon TX2 case. > - Use dev_get_driver_data() to get the driver data struct > - Removed "struct pci_device_id" definition and U_BOOT_PCI_DEVICE() > as its not needed for the PCI based probing on Octeon TX2 > > drivers/spi/Kconfig | 8 + > drivers/spi/Makefile | 1 + > drivers/spi/octeon_spi.c | 647 +++ > 3 files changed, 656 insertions(+) > create mode 100644 drivers/spi/octeon_spi.c > > diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig > index 30d808d7bb..3fc2d0674a 100644 > --- a/drivers/spi/Kconfig > +++ b/drivers/spi/Kconfig > @@ -240,6 +240,14 @@ config NXP_FSPI > Enable the NXP FlexSPI (FSPI) driver. This driver can be used to > access the SPI NOR flash on platforms embedding this NXP IP core. > > +config OCTEON_SPI > + bool "Octeon SPI driver" > + depends on DM_PCI && (ARCH_OCTEON || ARCH_OCTEONTX || ARCH_OCTEONTX2) > + help > + Enable the Octeon SPI driver. This driver can be used to > + access the SPI NOR flash on Octeon II/III and OcteonTX/TX2 > + SoC platforms. > + > config OMAP3_SPI > bool "McSPI driver for OMAP" > help > diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile > index 4e7461771f..b5c9ff1af8 100644 > --- a/drivers/spi/Makefile > +++ b/drivers/spi/Makefile > @@ -43,6 +43,7 @@ obj-$(CONFIG_MXC_SPI) += mxc_spi.o > obj-$(CONFIG_MXS_SPI) += mxs_spi.o > obj-$(CONFIG_NXP_FSPI) += nxp_fspi.o > obj-$(CONFIG_ATCSPI200_SPI) += atcspi200_spi.o > +obj-$(CONFIG_OCTEON_SPI) += octeon_spi.o > obj-$(CONFIG_OMAP3_SPI) += omap3_spi.o > obj-$(CONFIG_PIC32_SPI) += pic32_spi.o > obj-$(CONFIG_PL022_SPI) += pl022_spi.o > diff --git a/drivers/spi/octeon_spi.c b/drivers/spi/octeon_spi.c > new file mode 100644 > index 00..2fb39e444c > --- /dev/null > +++ b/drivers/spi/octeon_spi.c > @@ -0,0 +1,647 @@ > +// SPDX-License-Identifier:GPL-2.0 > +/* > + * Copyright (C) 2018 Marvell International Ltd. > + * > + * https://spdx.org/licenses > + */ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +#define OCTEON_SPI_MAX_BYTES 9 > +#define OCTEON_SPI_MAX_CLOCK_HZ 5000 > + > +#define OCTEON_SPI_NUM_CS4 > + > +#define OCTEON_SPI_CS_VALID(cs) ((cs) < OCTEON_SPI_NUM_CS) > + > +#define MPI_CFG 0x > +#define MPI_STS 0x0008 > +#define MPI_TX 0x0010 > +#define MPI_XMIT 0x0018 > +#define MPI_WIDE_DAT 0x0040 > +#define MPI_IO_CTL 0x0048 > +#define MPI_DAT(X) (0x0080 + ((X) << 3)) > +#define MPI_WIDE_BUF(X) (0x0800 + ((X) << 3)) > +#define MPI_CYA_CFG 0x1000 > +#define MPI_CLKEN0x1080 > + > +#define MPI_CFG_ENABLE BIT_ULL(0) > +#define MPI_CFG_IDLELO BIT_ULL(1) > +#define MPI_CFG_CLK_CONT BIT_ULL(2) > +#define MPI_CFG_WIREOR BIT_ULL(3) > +#define MPI_CFG_LSBFIRST BIT_ULL(4) > +#define MPI_CFG_CS_STICKYBIT_ULL(5) > +#define MPI_CFG_CSHI BIT_ULL(7) > +#define MPI_CFG_IDLECLKS GENMASK_ULL(9, 8) > +#define MPI_CFG_TRITXBIT_ULL(10) > +#define MPI_CFG_CSLATE BIT_ULL(11) > +#define MPI_CFG_CSENA0 BIT_ULL(12) > +#define MPI_CFG_CSENA1 BIT_ULL(13) > +#define MPI_CFG_CSENA2 BIT_ULL(14) > +#define MPI_CFG_CSENA3 BIT_ULL(15) > +#define MPI_CFG_CLKDIV GENMASK_ULL(28, 16) > +#define MPI_CFG_LEGACY_DIS BIT_ULL(31) > +#define MPI_CFG_IOMODE GENMASK_ULL(35, 34) > +#define MPI_CFG_TB100_EN BIT_ULL(49) > + > +#define MPI_DAT_DATA GENMASK_ULL(7, 0) > + > +#define MPI_STS_BUSY BIT_ULL(0) > +#define MPI_STS_MPI_INTR BIT_ULL(1) > +#define MPI_STS_RXNUMGENMASK_ULL(12, 8) > + > +#define MPI_TX_TOTNUMGENMASK_ULL(4, 0) > +#define MPI_TX_TXNUM GENMASK_ULL(12, 8) > +#define MPI_TX_LEAVECS BIT_ULL(16) > +#define MPI_TX_CSID GENMASK_ULL(21, 20) > + > +#define MPI_XMIT_TOTNUM GENMASK_ULL(10, 0) > +#define MPI_XMIT_TXNUM GENMASK_ULL(30, 20) > +#define MPI_XMIT_BUF_SEL BIT_ULL(59) > +#define
[PATCH] sandbox, test: change hog gpio
Since commit 9ba84329dc45 ("sandbox, test: add test for GPIO_HOG
function"), the gpio_a 0,1,2 and 3 are used by hog in test.dts.
But 2 leds 'sandbox:red' and 'sandbox:green' are using gpio_a 0
and 1. As hog always request his gpios, the led command on both
led is broken:
=> led sandbox:red
LED 'sandbox:red' not found (err=-16)
The gpio is already requested by hog, so it can't be enabled
for led 'sandbox:red'.
This commit change the gpio used by hog to 10, 11, 12 and 13,
so the led command could be used again with 'sandbox:red' and
'sandbox:green'.
Signed-off-by: Philippe Reynes
---
arch/sandbox/dts/test.dts | 8
test/dm/gpio.c| 12 ++--
2 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts
index 2ae4239..2325ec6 100644
--- a/arch/sandbox/dts/test.dts
+++ b/arch/sandbox/dts/test.dts
@@ -355,22 +355,22 @@
hog_input_active_low {
gpio-hog;
input;
- gpios = <0 GPIO_ACTIVE_LOW>;
+ gpios = <10 GPIO_ACTIVE_LOW>;
};
hog_input_active_high {
gpio-hog;
input;
- gpios = <1 GPIO_ACTIVE_HIGH>;
+ gpios = <11 GPIO_ACTIVE_HIGH>;
};
hog_output_low {
gpio-hog;
output-low;
- gpios = <2 GPIO_ACTIVE_HIGH>;
+ gpios = <12 GPIO_ACTIVE_HIGH>;
};
hog_output_high {
gpio-hog;
output-high;
- gpios = <3 GPIO_ACTIVE_HIGH>;
+ gpios = <13 GPIO_ACTIVE_HIGH>;
};
};
diff --git a/test/dm/gpio.c b/test/dm/gpio.c
index 2970138..b7ee8fc 100644
--- a/test/dm/gpio.c
+++ b/test/dm/gpio.c
@@ -114,21 +114,21 @@ static int dm_test_gpio(struct unit_test_state *uts)
/* add gpio hog tests */
ut_assertok(gpio_hog_lookup_name("hog_input_active_low", ));
ut_asserteq(GPIOD_IS_IN | GPIOD_ACTIVE_LOW, desc->flags);
- ut_asserteq(0, desc->offset);
+ ut_asserteq(10, desc->offset);
ut_asserteq(1, dm_gpio_get_value(desc));
ut_assertok(gpio_hog_lookup_name("hog_input_active_high", ));
ut_asserteq(GPIOD_IS_IN, desc->flags);
- ut_asserteq(1, desc->offset);
+ ut_asserteq(11, desc->offset);
ut_asserteq(0, dm_gpio_get_value(desc));
ut_assertok(gpio_hog_lookup_name("hog_output_low", ));
ut_asserteq(GPIOD_IS_OUT, desc->flags);
- ut_asserteq(2, desc->offset);
+ ut_asserteq(12, desc->offset);
ut_asserteq(0, dm_gpio_get_value(desc));
ut_assertok(dm_gpio_set_value(desc, 1));
ut_asserteq(1, dm_gpio_get_value(desc));
ut_assertok(gpio_hog_lookup_name("hog_output_high", ));
ut_asserteq(GPIOD_IS_OUT, desc->flags);
- ut_asserteq(3, desc->offset);
+ ut_asserteq(13, desc->offset);
ut_asserteq(1, dm_gpio_get_value(desc));
ut_assertok(dm_gpio_set_value(desc, 0));
ut_asserteq(0, dm_gpio_get_value(desc));
@@ -137,8 +137,8 @@ static int dm_test_gpio(struct unit_test_state *uts)
ut_assertok(gpio_lookup_name("hog_input_active_low", , ,
));
ut_asserteq_str(dev->name, "base-gpios");
- ut_asserteq(0, offset);
- ut_asserteq(CONFIG_SANDBOX_GPIO_COUNT + 0, gpio);
+ ut_asserteq(10, offset);
+ ut_asserteq(CONFIG_SANDBOX_GPIO_COUNT + 10, gpio);
ut_assert(gpio_lookup_name("hog_not_exist", , ,
));
--
2.7.4
Re: Using gerrit or github for review?
Hi, I'm a bit late to this discussion, but I'll drop my $0.02 anyway. On 13/07/20 02:06PM, Simon Glass wrote: > Hi Heinrich, > > On Mon, 13 Jul 2020 at 13:36, Heinrich Schuchardt wrote: > > > > On 13.07.20 20:25, Simon Glass wrote: > > > Hi, > > > > > > At present U-Boot uses the mailing list for patch review. What do > > > > Currently we are using Patchwork to keep track of the review process: > > > > https://patchwork.ozlabs.org/project/uboot/list/ > > > > > people think about trying out geritt or github for this? I'd be > > > willing to do a trial with the -dm mailing list. > > > > > > My idea is that patman would email out the patches and also upload > > > them to one of these systems. With geritt, emails are sent every time > > > there is a review, but for github I'm not sure. > > > > Do we need an new tool? Managing reviews it supported by Gitlab. > > > > There is no need for patman in a process with any of the mentioned > > tools. Gitlab, Gerrit, and Github send out mails to reviewers. > > > > The work flow with Gitlab and Gerrit that I have seen relied on a role > > concept where only specific users of the system are reviewers. - Our > > current process allows anybody to review. This is what I would like to keep. > > > > Simon, could you, please, explain why you want to change the current > > process. > > I have used various tools and I'm wondering whether having another > option might have some benefits in terms of productivity, automation > and accessibility. Just as one example, if people pushed patches to > github / gitlab then we could 1) check out the branch and try it, 2) > have test automation attached, 3) use a UI for review. > > So that is the purpose of my email. You might want to look into GitGitGadget (GGG in short) [0][1]. GGG lets you open GitHub Pull Requests and it will convert them to patch form and send them to the Git mailing list. It works pretty well for the most part (though I haven't ever used personally. Just observed other people using it a lot). It automatically adds version number to patches, and even CCs the subsystem maintainers automatically (as of now there are only two, but it shouldn't be difficult to extend it to use get_maintainer.pl). It also watches for replies on the email thread and shows them in comments to the Pull Request. It also runs CI build and tests for each PR. One major limitation of the tool is that while you can read replies to the email thread, you can't send replies. You'd still need a plain text email client to do that. I attempted to solve this problem once but I didn't make much progress partly due to lack of time and partly due lack of TypeScript and Azure experience. But I think it can be done. I think it can help bridge the gap between the mailing list workflow and the GitHub workflow. If anyone is interested, they can try porting it to work with the U-Boot mailing list. [0] https://github.com/gitgitgadget/gitgitgadget [1] https://github.com/gitgitgadget/git -- Regards, Pratyush Yadav Texas Instruments India
Re: [PATCH 07/18] arm: mach-k3: j721e: Add detection for j721e
On 24/07/20 5:55 pm, Grygorii Strashko wrote:
>
>
> On 23/07/2020 11:47, Lokesh Vutla wrote:
>> Add an api soc_is_j721e(), and use it to enable certain functionality
>> that is available only on j721e.
>>
>> Signed-off-by: Lokesh Vutla
>> Signed-off-by: Suman Anna
>> ---
>> arch/arm/mach-k3/common.c | 10 ++
>> arch/arm/mach-k3/include/mach/sys_proto.h | 2 ++
>> arch/arm/mach-k3/j721e_init.c | 3 +++
>> 3 files changed, 15 insertions(+)
>>
>> diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c
>> index eb72451d06..aec6c600b9 100644
>> --- a/arch/arm/mach-k3/common.c
>> +++ b/arch/arm/mach-k3/common.c
>> @@ -355,6 +355,16 @@ int print_cpuinfo(void)
>> }
>> #endif
>> +bool soc_is_j721e(void)
>> +{
>> + u32 soc;
>> +
>> + soc = (readl(CTRLMMR_WKUP_JTAG_ID) &
>> + JTAG_ID_PARTNO_MASK) >> JTAG_ID_PARTNO_SHIFT;
>> +
>> + return soc == J721E;
>> +}
>
> Shouldn't it be done using UCLASS_SOC introduce by Dave Gerlach
>
>
> https://patchwork.ozlabs.org/project/uboot/cover/20200716044004.6014-1-d-gerl...@ti.com/
SoC differentiation is needed before DT is available. So I had to use these
apis.
Thanks and regards,
Lokesh
Re: Please pull u-boot-dm
On Thu, Jul 23, 2020 at 09:09:33PM -0400, Tom Rini wrote: > On Mon, Jul 20, 2020 at 02:19:02PM -0600, Simon Glass wrote: > > > Hi Tom, > > > > https://gitlab.denx.de/u-boot/custodians/u-boot-dm/pipelines/4139 > > > > The following changes since commit 7303ba10a4a39852b9ba356fae5656b43122eec6: > > > > Merge https://gitlab.denx.de/u-boot/custodians/u-boot-x86 > > (2020-07-20 09:25:32 -0400) > > > > are available in the Git repository at: > > > > git://git.denx.de/u-boot-dm.git tags/dm-pull-20jul20 > > > > for you to fetch changes up to 60e7fa8b3b8538aae1e644dac61d5e4076901edb: > > > > treewide: convert devfdt_get_addr() to dev_read_addr() (2020-07-20 > > 11:37:47 -0600) > > > > Applied to u-boot/master, thanks! I spoke too soon. This is reliably causing: https://travis-ci.org/github/trini/u-boot/jobs/711313649 and I don't see why it's different from: https://gitlab.denx.de/u-boot/u-boot/-/jobs/129107 But, I also don't see why in both cases we say that pyelftools isn't installed when it very much is. So I've reverted this for now, sorry. -- Tom signature.asc Description: PGP signature
[PATCH] clk: versal: Move pm_query_id out of clock driver
There is no reason to have firmware specific structure in clock driver.
Move it to generic location and also initialize enum values which is based
on https://lore.kernel.org/linux-arm-kernel/20200318125003.ga2727...@kroah.com/
recommended way to go to make sure that values guaranteed by compiler.
Signed-off-by: Michal Simek
---
drivers/clk/clk_versal.c | 17 -
include/zynqmp_firmware.h | 17 +
2 files changed, 17 insertions(+), 17 deletions(-)
diff --git a/drivers/clk/clk_versal.c b/drivers/clk/clk_versal.c
index 6f82b60f04db..d93b860aed35 100644
--- a/drivers/clk/clk_versal.c
+++ b/drivers/clk/clk_versal.c
@@ -68,23 +68,6 @@
#define CLOCK_NODE_TYPE_DIV4
#define CLOCK_NODE_TYPE_GATE 6
-enum pm_query_id {
- PM_QID_INVALID,
- PM_QID_CLOCK_GET_NAME,
- PM_QID_CLOCK_GET_TOPOLOGY,
- PM_QID_CLOCK_GET_FIXEDFACTOR_PARAMS,
- PM_QID_CLOCK_GET_PARENTS,
- PM_QID_CLOCK_GET_ATTRIBUTES,
- PM_QID_PINCTRL_GET_NUM_PINS,
- PM_QID_PINCTRL_GET_NUM_FUNCTIONS,
- PM_QID_PINCTRL_GET_NUM_FUNCTION_GROUPS,
- PM_QID_PINCTRL_GET_FUNCTION_NAME,
- PM_QID_PINCTRL_GET_FUNCTION_GROUPS,
- PM_QID_PINCTRL_GET_PIN_GROUPS,
- PM_QID_CLOCK_GET_NUM_CLOCKS,
- PM_QID_CLOCK_GET_MAX_DIVISOR,
-};
-
enum clk_type {
CLK_TYPE_OUTPUT,
CLK_TYPE_EXTERNAL,
diff --git a/include/zynqmp_firmware.h b/include/zynqmp_firmware.h
index 93d771ece26a..98e20a466e24 100644
--- a/include/zynqmp_firmware.h
+++ b/include/zynqmp_firmware.h
@@ -62,6 +62,23 @@ enum pm_api_id {
PM_API_MAX,
};
+enum pm_query_id {
+ PM_QID_INVALID = 0,
+ PM_QID_CLOCK_GET_NAME = 1,
+ PM_QID_CLOCK_GET_TOPOLOGY = 2,
+ PM_QID_CLOCK_GET_FIXEDFACTOR_PARAMS = 3,
+ PM_QID_CLOCK_GET_PARENTS = 4,
+ PM_QID_CLOCK_GET_ATTRIBUTES = 5,
+ PM_QID_PINCTRL_GET_NUM_PINS = 6,
+ PM_QID_PINCTRL_GET_NUM_FUNCTIONS = 7,
+ PM_QID_PINCTRL_GET_NUM_FUNCTION_GROUPS = 8,
+ PM_QID_PINCTRL_GET_FUNCTION_NAME = 9,
+ PM_QID_PINCTRL_GET_FUNCTION_GROUPS = 10,
+ PM_QID_PINCTRL_GET_PIN_GROUPS = 11,
+ PM_QID_CLOCK_GET_NUM_CLOCKS = 12,
+ PM_QID_CLOCK_GET_MAX_DIVISOR = 13,
+};
+
#define PM_SIP_SVC 0xc200
#define ZYNQMP_PM_VERSION_MAJOR 1
--
2.27.0
Re: [PATCH 07/18] arm: mach-k3: j721e: Add detection for j721e
On 23/07/2020 11:47, Lokesh Vutla wrote:
Add an api soc_is_j721e(), and use it to enable certain functionality
that is available only on j721e.
Signed-off-by: Lokesh Vutla
Signed-off-by: Suman Anna
---
arch/arm/mach-k3/common.c | 10 ++
arch/arm/mach-k3/include/mach/sys_proto.h | 2 ++
arch/arm/mach-k3/j721e_init.c | 3 +++
3 files changed, 15 insertions(+)
diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c
index eb72451d06..aec6c600b9 100644
--- a/arch/arm/mach-k3/common.c
+++ b/arch/arm/mach-k3/common.c
@@ -355,6 +355,16 @@ int print_cpuinfo(void)
}
#endif
+bool soc_is_j721e(void)
+{
+ u32 soc;
+
+ soc = (readl(CTRLMMR_WKUP_JTAG_ID) &
+ JTAG_ID_PARTNO_MASK) >> JTAG_ID_PARTNO_SHIFT;
+
+ return soc == J721E;
+}
Shouldn't it be done using UCLASS_SOC introduce by Dave Gerlach
https://patchwork.ozlabs.org/project/uboot/cover/20200716044004.6014-1-d-gerl...@ti.com/
+
#ifdef CONFIG_ARM64
void board_prep_linux(bootm_headers_t *images)
{
diff --git a/arch/arm/mach-k3/include/mach/sys_proto.h
b/arch/arm/mach-k3/include/mach/sys_proto.h
index 3c825aa3d1..48b11178c3 100644
--- a/arch/arm/mach-k3/include/mach/sys_proto.h
+++ b/arch/arm/mach-k3/include/mach/sys_proto.h
@@ -16,4 +16,6 @@ int do_board_detect(void);
void release_resources_for_core_shutdown(void);
int fdt_disable_node(void *blob, char *node_path);
+bool soc_is_j721e(void);
+
#endif
diff --git a/arch/arm/mach-k3/j721e_init.c b/arch/arm/mach-k3/j721e_init.c
index 461a9d7f8f..3b15da2d7c 100644
--- a/arch/arm/mach-k3/j721e_init.c
+++ b/arch/arm/mach-k3/j721e_init.c
@@ -361,6 +361,9 @@ void start_non_linux_remote_cores(void)
int size = 0, ret;
u32 loadaddr = 0;
+ if (!soc_is_j721e())
+ return;
+
size = load_firmware("name_mainr5f0_0fw", "addr_mainr5f0_0load",
);
if (size <= 0)
--
Best regards,
grygorii
Re: [PATCH 2/2] xilinx: zynqmp: Enable DFU tftp support
st 15. 7. 2020 v 15:51 odesílatel Michal Simek napsal:
>
> Enable DFU tftp support for firmware update. Fill dfu_ram_tftp variable to
> have command present for showing how to use it.
>
> boot FIT image has been created from below fragment. Key part is that type
> of image has to be firmware. Also based on experiment load property is
> completely ignored and base addresses are taken from dfu_alt_info variable.
>
> $ cat update_uboot.its
> /dts-v1/;
>
> / {
> description = "Automatic U-Boot update";
> #address-cells = <1>;
>
> images {
> Image {
> description = "Kernel";
> data = /incbin/("/tftpboot/Image");
> compression = "none";
> arch = "arm64";
> type = "firmware";
> os = "linux";
> load = <0x8>;
> entry = <0x8>;
> hash-1 {
> algo = "sha1";
> };
> };
> system.dtb {
> description = "DTB";
> data = /incbin/("/tftpboot/system.dtb");
> compression = "none";
> arch = "arm64";
> type = "firmware";
> load = <0>;
> hash-1 {
> algo = "sha1";
> };
> };
> };
> };
>
> $ mkimage -f update_uboot.its /tftpboot/boot
>
> When U-Boot starts get IP address and server IP.
> dhcp
> setenv serverip 192.168.0.105
>
> And then run prepared command.
> run dfu_ram_tftp
>
> Signed-off-by: Michal Simek
> ---
>
> configs/xilinx_zynqmp_virt_defconfig | 1 +
> include/configs/xilinx_zynqmp.h | 4 +++-
> 2 files changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/configs/xilinx_zynqmp_virt_defconfig
> b/configs/xilinx_zynqmp_virt_defconfig
> index d77ba051624e..2d84f0c04e12 100644
> --- a/configs/xilinx_zynqmp_virt_defconfig
> +++ b/configs/xilinx_zynqmp_virt_defconfig
> @@ -69,6 +69,7 @@ CONFIG_SPL_DM_SEQ_ALIAS=y
> CONFIG_SCSI_AHCI=y
> CONFIG_SATA_CEVA=y
> CONFIG_CLK_ZYNQMP=y
> +CONFIG_DFU_TFTP=y
> CONFIG_DFU_RAM=y
> CONFIG_USB_FUNCTION_FASTBOOT=y
> CONFIG_FASTBOOT_FLASH=y
> diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h
> index 86f292761b38..f45a1a2272d3 100644
> --- a/include/configs/xilinx_zynqmp.h
> +++ b/include/configs/xilinx_zynqmp.h
> @@ -61,7 +61,9 @@
> "Image ram 8 $kernel_size_r;" \
> "system.dtb ram $fdt_addr_r $fdt_size_r\0" \
> "dfu_ram=run dfu_ram_info && dfu 0 ram 0\0" \
> - "thor_ram=run dfu_ram_info && thordown 0 ram 0\0"
> + "thor_ram=run dfu_ram_info && thordown 0 ram 0\0" \
> + "dfu_ram_tftp=run dfu_ram_info && setenv updatefile boot && " \
> + "setenv loadaddr 1000 && dfu tftp ram 0\0"
>
> #define DFU_ALT_INFO \
> DFU_ALT_INFO_RAM
> --
> 2.27.0
>
Applied.
M
--
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Xilinx Microblaze
Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP ARM64 SoCs
U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP/Versal SoCs
Re: [PATCH 1/2] xilinx: Align dfu ram with booti command
st 15. 7. 2020 v 15:51 odesílatel Michal Simek napsal: > > Image should be loaded to 0x8 address and not to $kernel_addr_r. > Also kernel_addr, fdt_addr and fdt_size in zynqmp case are not defined > that's why define it to be aligned with Versal. > > Signed-off-by: Michal Simek > --- > > include/configs/xilinx_versal.h | 2 +- > include/configs/xilinx_zynqmp.h | 6 -- > 2 files changed, 5 insertions(+), 3 deletions(-) > > diff --git a/include/configs/xilinx_versal.h b/include/configs/xilinx_versal.h > index 804525dcad26..32cd5b21f7b7 100644 > --- a/include/configs/xilinx_versal.h > +++ b/include/configs/xilinx_versal.h > @@ -54,7 +54,7 @@ > #define DFU_ALT_INFO_RAM \ > "dfu_ram_info=" \ > "setenv dfu_alt_info " \ > - "Image ram $kernel_addr_r $kernel_size_r;" \ > + "Image ram 8 $kernel_size_r;" \ > "system.dtb ram $fdt_addr_r $fdt_size_r\0" \ > "dfu_ram=run dfu_ram_info && dfu 0 ram 0\0" \ > "thor_ram=run dfu_ram_info && thordown 0 ram 0\0" > diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h > index e7cfebee7c46..86f292761b38 100644 > --- a/include/configs/xilinx_zynqmp.h > +++ b/include/configs/xilinx_zynqmp.h > @@ -58,8 +58,8 @@ > #define DFU_ALT_INFO_RAM \ > "dfu_ram_info=" \ > "setenv dfu_alt_info " \ > - "Image ram $kernel_addr $kernel_size;" \ > - "system.dtb ram $fdt_addr $fdt_size\0" \ > + "Image ram 8 $kernel_size_r;" \ > + "system.dtb ram $fdt_addr_r $fdt_size_r\0" \ > "dfu_ram=run dfu_ram_info && dfu 0 ram 0\0" \ > "thor_ram=run dfu_ram_info && thordown 0 ram 0\0" > > @@ -101,8 +101,10 @@ > #define ENV_MEM_LAYOUT_SETTINGS \ > "fdt_high=1000\0" \ > "fdt_addr_r=0x4000\0" \ > + "fdt_size_r=0x40\0" \ > "pxefile_addr_r=0x1000\0" \ > "kernel_addr_r=0x1800\0" \ > + "kernel_size_r=0x1000\0" \ > "scriptaddr=0x2000\0" \ > "ramdisk_addr_r=0x0210\0" \ > "script_size_f=0x8\0" \ > -- > 2.27.0 > Applied. M -- Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91 w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel - Xilinx Microblaze Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP ARM64 SoCs U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP/Versal SoCs
Re: [PATCH] arm64: zynqmp: Reduce malloc memory for mini QSPI configuration
čt 16. 7. 2020 v 12:03 odesílatel Michal Simek napsal: > > From: Ashok Reddy Soma > > Mini U-boot runs on lower foot print of 256KB OCM. Hence 8K memory > for malloc may not be required. Reduce it by 1.5K. > > Signed-off-by: Ashok Reddy Soma > Signed-off-by: Michal Simek > --- > > include/configs/xilinx_zynqmp_mini_qspi.h | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/include/configs/xilinx_zynqmp_mini_qspi.h > b/include/configs/xilinx_zynqmp_mini_qspi.h > index 129af6e93294..205ddb4ae097 100644 > --- a/include/configs/xilinx_zynqmp_mini_qspi.h > +++ b/include/configs/xilinx_zynqmp_mini_qspi.h > @@ -13,6 +13,6 @@ > #include > > #define CONFIG_SYS_INIT_SP_ADDR(CONFIG_SYS_TEXT_BASE + 0x2) > -#define CONFIG_SYS_MALLOC_LEN 0x2000 > +#define CONFIG_SYS_MALLOC_LEN 0x1a00 > > #endif /* __CONFIG_ZYNQMP_MINI_QSPI_H */ > -- > 2.27.0 > Applied. M -- Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91 w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel - Xilinx Microblaze Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP ARM64 SoCs U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP/Versal SoCs
Re: [PATCH v2 0/3] xilinx: Enable Versal allocation from low memory
pá 10. 7. 2020 v 14:40 odesílatel Michal Simek napsal: > > Hi, > > Generated DTS files don't need to have memory nodes sorted out that's why > it can happen that the first memory node is not pointing to lowest DDR > which is normally used for system boot. That's why new function was > introduced which finds out the lowest memory available and use it for > u-boot and later can be also used for OS. > > The series is based on > https://lists.denx.de/pipermail/u-boot/2020-July/419656.html > which simplified conversion to livetree API which was asked by Simon. > > And also I keep conversion to livetree in separate patch on the top of v1 > which shouldn't be a problem. > > The series is still missing tests which Simon asked for but I would like to > get feedback about these patches. If they are fine I would like to have > discussion how/where to write little test for it. > > Thanks, > Michal > > Changes in v2: > - Separate Xilinx change from generic patch > - new patch asked by Simon > - split from generic patch sent in v1 > > Michal Simek (3): > lib: fdt: Introduce fdtdec_setup_mem_size_base_lowest() > lib: fdt: Convert fdtdes_setup_mem..() to livetree API > xilinx: versal: Use lowest memory for U-Boot > > board/xilinx/versal/board.c | 2 +- > include/fdtdec.h| 17 +++ > lib/fdtdec.c| 90 - > 3 files changed, 87 insertions(+), 22 deletions(-) > > -- > 2.27.0 > Applied all. M -- Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91 w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel - Xilinx Microblaze Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP ARM64 SoCs U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP/Versal SoCs
Re: [PATCH] versal: fix versal PM ret payload size
st 8. 7. 2020 v 14:54 odesílatel Michal Simek napsal:
>
> From: Ibai Erkiaga
>
> The PM return payload size is defined as 4 bytes for Versal arquitecture
> while the PM calls implemented both in the Versal clock driver and
> ZynqMP firmware driver expects 5 bytes length.
>
> Signed-off-by: Ibai Erkiaga
> Signed-off-by: Michal Simek
> ---
>
> ---
> arch/arm/mach-versal/include/mach/sys_proto.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm/mach-versal/include/mach/sys_proto.h
> b/arch/arm/mach-versal/include/mach/sys_proto.h
> index 31af049a21c9..cfd480bec17e 100644
> --- a/arch/arm/mach-versal/include/mach/sys_proto.h
> +++ b/arch/arm/mach-versal/include/mach/sys_proto.h
> @@ -8,7 +8,7 @@ enum {
> TCM_SPLIT,
> };
>
> -#define PAYLOAD_ARG_CNT4U
> +#define PAYLOAD_ARG_CNT5U
>
> void tcm_init(u8 mode);
> void mem_map_fill(void);
> --
> 2.27.0
>
Applied.
M
--
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Xilinx Microblaze
Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP ARM64 SoCs
U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP/Versal SoCs
Re: [PATCH v2] xilinx: versal: Add new versal loadpdi command
st 24. 6. 2020 v 14:49 odesílatel Michal Simek napsal:
>
> From: T Karthik Reddy
>
> Versal loadpdi command is used for loading secure & non-secure
> pdi images.
>
> Signed-off-by: T Karthik Reddy
> Signed-off-by: Michal Simek
> ---
>
> Changes in v2:
> - Fix failures for versal mini configuration and create Kconfig entry for
> versal specific commands. Dependency to firmware should ensure that it is
> not enabled for mini configurations.
>
> arch/arm/Kconfig | 1 +
> board/xilinx/versal/Kconfig | 14 +
> board/xilinx/versal/Makefile | 1 +
> board/xilinx/versal/cmds.c | 105 +++
> 4 files changed, 121 insertions(+)
> create mode 100644 board/xilinx/versal/Kconfig
> create mode 100644 board/xilinx/versal/cmds.c
>
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index 54d65f84889f..b1bd640b2d92 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -1920,6 +1920,7 @@ source "board/vscom/baltos/Kconfig"
> source "board/xilinx/Kconfig"
> source "board/xilinx/zynq/Kconfig"
> source "board/xilinx/zynqmp/Kconfig"
> +source "board/xilinx/versal/Kconfig"
> source "board/phytium/durian/Kconfig"
>
> source "arch/arm/Kconfig.debug"
> diff --git a/board/xilinx/versal/Kconfig b/board/xilinx/versal/Kconfig
> new file mode 100644
> index ..c02068b2
> --- /dev/null
> +++ b/board/xilinx/versal/Kconfig
> @@ -0,0 +1,14 @@
> +# Copyright (c) 2020, Xilinx, Inc.
> +#
> +# SPDX-License-Identifier: GPL-2.0
> +
> +if ARCH_VERSAL
> +
> +config CMD_VERSAL
> + bool "Enable Versal specific commands"
> + default y
> + depends on ZYNQMP_FIRMWARE
> + help
> + Enable Versal specific commands.
> +
> +endif
> diff --git a/board/xilinx/versal/Makefile b/board/xilinx/versal/Makefile
> index e9307d7fa690..90e034315406 100644
> --- a/board/xilinx/versal/Makefile
> +++ b/board/xilinx/versal/Makefile
> @@ -5,4 +5,5 @@
> #
>
> obj-y := board.o
> +obj-$(CONFIG_CMD_VERSAL) += cmds.o
> obj-y += ../common/board.o
> diff --git a/board/xilinx/versal/cmds.c b/board/xilinx/versal/cmds.c
> new file mode 100644
> index ..981c80ee4742
> --- /dev/null
> +++ b/board/xilinx/versal/cmds.c
> @@ -0,0 +1,105 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * (C) Copyright 2020 Xilinx, Inc.
> + * Michal Simek
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +static int do_versal_load_pdi(struct cmd_tbl *cmdtp, int flag, int argc,
> + char * const argv[])
> +{
> + u32 buf_lo, buf_hi;
> + u32 ret_payload[5];
> + ulong addr, *pdi_buf;
> + size_t len;
> + int ret;
> +
> + if (argc != cmdtp->maxargs) {
> + debug("pdi_load: incorrect parameters passed\n");
> + return CMD_RET_USAGE;
> + }
> +
> + addr = simple_strtol(argv[2], NULL, 16);
> + if (!addr) {
> + debug("pdi_load: zero pdi_data address\n");
> + return CMD_RET_USAGE;
> + }
> +
> + len = simple_strtoul(argv[3], NULL, 16);
> + if (!len) {
> + debug("pdi_load: zero size\n");
> + return CMD_RET_USAGE;
> + }
> +
> + pdi_buf = (ulong *)ALIGN((ulong)addr, ARCH_DMA_MINALIGN);
> + if ((ulong)addr != (ulong)pdi_buf) {
> + memcpy((void *)pdi_buf, (void *)addr, len);
> + debug("Pdi addr:0x%lx aligned to 0x%lx\n",
> + addr, (ulong)pdi_buf);
> + }
> +
> + flush_dcache_range((ulong)pdi_buf, (ulong)pdi_buf + len);
> +
> + buf_lo = lower_32_bits((ulong)pdi_buf);
> + buf_hi = upper_32_bits((ulong)pdi_buf);
> +
> + ret = xilinx_pm_request(VERSAL_PM_LOAD_PDI, VERSAL_PM_PDI_TYPE,
> buf_lo,
> + buf_hi, 0, ret_payload);
> + if (ret)
> + printf("PDI load failed with err: 0x%08x\n", ret);
> +
> + return ret;
> +}
> +
> +static struct cmd_tbl cmd_versal_sub[] = {
> + U_BOOT_CMD_MKENT(loadpdi, 4, 1, do_versal_load_pdi, "", ""),
> +};
> +
> +/**
> + * do_versal - Handle the "versal" command-line command
> + * @cmdtp: Command data struct pointer
> + * @flag: Command flag
> + * @argc: Command-line argument count
> + * @argv: Array of command-line arguments
> + *
> + * Processes the versal specific commands
> + *
> + * Return: return 0 on success, Error value if command fails.
> + * CMD_RET_USAGE incase of incorrect/missing parameters.
> + */
> +static int do_versal(struct cmd_tbl *cmdtp, int flag, int argc,
> +char *const argv[])
> +{
> + struct cmd_tbl *c;
> + int ret = CMD_RET_USAGE;
> +
> + if (argc < 2)
> + return CMD_RET_USAGE;
> +
> + c = find_cmd_tbl(argv[1], _versal_sub[0],
> +ARRAY_SIZE(cmd_versal_sub));
> + if (c)
> + ret = c->cmd(c, flag, argc, argv);
> +
> +
Re: [PATCH] arm64: zynqmp: Fix set_fdtfile() not to break u-boots DTB
st 24. 6. 2020 v 14:44 odesílatel Michal Simek napsal:
>
> Origin function was calling strsep which replaced delimiter ',' by a null
> byte ('\0'). Operation was done directly on FDT which ends up with the
> following behavior:
>
> ZynqMP> printenv fdtfile
> fdtfile=xilinx/zynqmp.dtb
> ZynqMP> fdt addr $fdtcontroladdr
> ZynqMP> fdt print / compatible
> compatible = "xlnx", "zynqmp"
>
> As is visible fdtfile was correctly composed but a null byte caused that
> xlnx was separated from zynqmp.
> This hasn't been spotted because in all Xilinx DTs there are at least 3
> compatible string and only the first one was affected by this issue.
> But for systems which only had one compatible string "xlnx,zynqmp" it was
> causing an issue when U-Boot's DT was used by Linux kernel.
>
> The patch removes strsep calling and strchr is called instead which just
> locate the first char after deliminator ',' (variable called "name").
> And using this pointer in fdtfile composing.
>
> Fixes: 91d7e0c47f51 ("arm64: zynqmp: Create fdtfile from compatible string")
> Signed-off-by: Michal Simek
> ---
>
> board/xilinx/zynqmp/zynqmp.c | 19 +--
> 1 file changed, 13 insertions(+), 6 deletions(-)
>
> diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c
> index ebb71729081d..8a4df6fc1ab6 100644
> --- a/board/xilinx/zynqmp/zynqmp.c
> +++ b/board/xilinx/zynqmp/zynqmp.c
> @@ -541,23 +541,30 @@ static int set_fdtfile(void)
> char *compatible, *fdtfile;
> const char *suffix = ".dtb";
> const char *vendor = "xilinx/";
> + int fdt_compat_len;
>
> if (env_get("fdtfile"))
> return 0;
>
> - compatible = (char *)fdt_getprop(gd->fdt_blob, 0, "compatible", NULL);
> - if (compatible) {
> + compatible = (char *)fdt_getprop(gd->fdt_blob, 0, "compatible",
> +_compat_len);
> + if (compatible && fdt_compat_len) {
> + char *name;
> +
> debug("Compatible: %s\n", compatible);
>
> - /* Discard vendor prefix */
> - strsep(, ",");
> + name = strchr(compatible, ',');
> + if (!name)
> + return -EINVAL;
> +
> + name++;
>
> - fdtfile = calloc(1, strlen(vendor) + strlen(compatible) +
> + fdtfile = calloc(1, strlen(vendor) + strlen(name) +
> strlen(suffix) + 1);
> if (!fdtfile)
> return -ENOMEM;
>
> - sprintf(fdtfile, "%s%s%s", vendor, compatible, suffix);
> + sprintf(fdtfile, "%s%s%s", vendor, name, suffix);
>
> env_set("fdtfile", fdtfile);
> free(fdtfile);
> --
> 2.27.0
>
Applied.
M
--
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Xilinx Microblaze
Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP ARM64 SoCs
U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP/Versal SoCs
Re: [PATCH v4 08/17] board_f: Factor out bdinfo bi_mem{start, size} to setup_bdinfo
Hi Ovidiu,
> Move all assignments to gd->bd->bi_mem{start,size} to generic code in
> setup_bdinfo.
>
> Xtensa architecture is special in this regard as it defines its own
> handling of gd->bd->bi_mem{start,size} fields. In order to avoid defining
> a weak SDRAM function, let arch_setup_bdinfo overwrite the generic flags.
>
> For ARC architecture, remove ARCH_EARLY_INIT_R from Kconfig since it is
> not needed anymore.
>
> Also, use gd->ram_base to populate bi_memstart to avoid an ifdef.
>
> Signed-off-by: Ovidiu Panait
> ---
>
> arch/Kconfig | 1 -
> arch/arc/lib/cpu.c| 7 ---
> arch/xtensa/lib/Makefile | 2 +-
> arch/xtensa/lib/bdinfo.c | 22 ++
> board/cadence/xtfpga/xtfpga.c | 3 ---
> common/board_f.c | 11 +--
> 6 files changed, 28 insertions(+), 18 deletions(-)
> create mode 100644 arch/xtensa/lib/bdinfo.c
>
> diff --git a/arch/Kconfig b/arch/Kconfig
> index 9be02d1319..4d9557959c 100644
> --- a/arch/Kconfig
> +++ b/arch/Kconfig
> @@ -10,7 +10,6 @@ choice
>
> config ARC
> bool "ARC architecture"
> - select ARCH_EARLY_INIT_R
> select ARC_TIMER
> select CLK
> select HAVE_PRIVATE_LIBGCC
> diff --git a/arch/arc/lib/cpu.c b/arch/arc/lib/cpu.c
> index 27b5832a0c..d66a8c867a 100644
> --- a/arch/arc/lib/cpu.c
> +++ b/arch/arc/lib/cpu.c
> @@ -25,13 +25,6 @@ int arch_cpu_init(void)
> return 0;
> }
>
> -int arch_early_init_r(void)
> -{
> - gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
> - gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
> - return 0;
> -}
> -
> /* This is a dummy function on arc */
> int dram_init(void)
> {
For ARC part...
Acked-by: Alexey Brodkin
Re: [PATCH] xilinx: Setup bootm variables
pá 10. 7. 2020 v 13:20 odesílatel Michal Simek napsal:
>
> On system with PL DDR which is placed before PS DDR in DT
> env_get_bootm_size() and env_get_bootm_low() without specifying bootm_low
> and bootm_size variables are taking by default gd->bd->bi_dram[0].start and
> gd->bd->bi_dram[0].size. As you see 0 means bank 0 which doesn't need to be
> PS ddr and even can be memory above 39bit VA which is what U-Boot supports
> now.
> That's why setup bootm variables based on ram_base/ram_size setting to make
> sure that boot images are placed to the same location as U-Boot is placed.
> This location should be by default location where OS can boot from.
>
> Signed-off-by: Michal Simek
> ---
>
> board/xilinx/common/board.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/board/xilinx/common/board.c b/board/xilinx/common/board.c
> index 0469e2e7ac9b..3bca3a25a97b 100644
> --- a/board/xilinx/common/board.c
> +++ b/board/xilinx/common/board.c
> @@ -86,5 +86,8 @@ int board_late_init_xilinx(void)
> initrd_hi = round_down(initrd_hi, SZ_16M);
> env_set_addr("initrd_high", (void *)initrd_hi);
>
> + env_set_addr("bootm_low", (void *)gd->ram_base);
> + env_set_addr("bootm_size", (void *)gd->ram_size);
> +
> return 0;
> }
> --
> 2.27.0
>
Applied.
M
--
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Xilinx Microblaze
Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP ARM64 SoCs
U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP/Versal SoCs
[PATCH v4 13/17] dm: blk: Use IS_ENABLED() instead of #ifdefs in blk_post_probe
Use IS_ENABLED() instead of #ifdef in blk_post_probe function.
No functional change intended.
Reviewed-by: Simon Glass
Signed-off-by: Ovidiu Panait
---
drivers/block/blk-uclass.c | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/drivers/block/blk-uclass.c b/drivers/block/blk-uclass.c
index b19375cbc8..b2738f5717 100644
--- a/drivers/block/blk-uclass.c
+++ b/drivers/block/blk-uclass.c
@@ -644,11 +644,12 @@ int blk_unbind_all(int if_type)
static int blk_post_probe(struct udevice *dev)
{
-#if defined(CONFIG_PARTITIONS) && defined(CONFIG_HAVE_BLOCK_DEVICE)
- struct blk_desc *desc = dev_get_uclass_platdata(dev);
+ if (IS_ENABLED(CONFIG_PARTITIONS) &&
+ IS_ENABLED(CONFIG_HAVE_BLOCK_DEV)) {
+ struct blk_desc *desc = dev_get_uclass_platdata(dev);
- part_init(desc);
-#endif
+ part_init(desc);
+ }
return 0;
}
--
2.17.1
[PATCH v4 17/17] common/board_r: Move blkcache_init call earlier in the boot sequence
blkcache_init manually relocates blkcache list pointers when
CONFIG_NEEDS_MANUAL_RELOC is enabled. However, it is called very late in
the boot sequence, which could be a problem if previous boot calls execute
blkcache operations with the non-relocated pointers. For example, mmc is
initialized earlier and might call blkcache_invalidate (in
mmc_select_hwpart()) when trying to load the environment from mmc via
env_load().
To fix this issue, move blkcache_init boot call earlier, before mmc gets
initialized.
Acked-by: Angelo Dureghello
Tested-by: Angelo Dureghello
Reviewed-by: Simon Glass
Signed-off-by: Ovidiu Panait
---
common/board_r.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/common/board_r.c b/common/board_r.c
index 63c53b7b96..1c307383d5 100644
--- a/common/board_r.c
+++ b/common/board_r.c
@@ -705,6 +705,9 @@ static init_fnc_t init_sequence_r[] = {
initr_watchdog,
#endif
INIT_FUNC_WATCHDOG_RESET
+#if defined(CONFIG_NEEDS_MANUAL_RELOC) && defined(CONFIG_BLOCK_CACHE)
+ blkcache_init,
+#endif
#ifdef CONFIG_NEEDS_MANUAL_RELOC
initr_manual_reloc_cmdtable,
#endif
@@ -835,9 +838,6 @@ static init_fnc_t init_sequence_r[] = {
#endif
#if defined(CONFIG_PRAM)
initr_mem,
-#endif
-#if defined(CONFIG_NEEDS_MANUAL_RELOC) && defined(CONFIG_BLOCK_CACHE)
- blkcache_init,
#endif
run_main_loop,
};
--
2.17.1
[PATCH v4 14/17] drivers: serial: Make serial_initialize return int
serial_initialize is called only during the common init sequence, after
relocation (in common/board_r.c). Because it has a void return value, it
has to wrapped in initr_serial. In order to be able to get rid of this
indirection, make serial_initialize return int.
Remove extern from prototype in order to silence the following checkpatch
warning:
check: extern prototypes should be avoided in .h files
Reviewed-by: Simon Glass
Signed-off-by: Ovidiu Panait
---
drivers/serial/serial-uclass.c | 4 ++--
drivers/serial/serial.c| 4 +++-
include/serial.h | 2 +-
3 files changed, 6 insertions(+), 4 deletions(-)
diff --git a/drivers/serial/serial-uclass.c b/drivers/serial/serial-uclass.c
index a0af0e6bfd..0027625ebf 100644
--- a/drivers/serial/serial-uclass.c
+++ b/drivers/serial/serial-uclass.c
@@ -170,9 +170,9 @@ int serial_init(void)
}
/* Called after relocation */
-void serial_initialize(void)
+int serial_initialize(void)
{
- serial_init();
+ return serial_init();
}
static void _serial_putc(struct udevice *dev, char ch)
diff --git a/drivers/serial/serial.c b/drivers/serial/serial.c
index da017dc5b3..53358acb81 100644
--- a/drivers/serial/serial.c
+++ b/drivers/serial/serial.c
@@ -170,7 +170,7 @@ void serial_register(struct serial_device *dev)
* serial port to the serial core. That serial port is then used as a
* default output.
*/
-void serial_initialize(void)
+int serial_initialize(void)
{
atmel_serial_initialize();
mcf_serial_initialize();
@@ -183,6 +183,8 @@ void serial_initialize(void)
mtk_serial_initialize();
serial_assign(default_serial_console()->name);
+
+ return 0;
}
static int serial_stub_start(struct stdio_dev *sdev)
diff --git a/include/serial.h b/include/serial.h
index c590637b1f..6d1e62c677 100644
--- a/include/serial.h
+++ b/include/serial.h
@@ -42,10 +42,10 @@ extern struct serial_device eserial5_device;
extern struct serial_device eserial6_device;
extern void serial_register(struct serial_device *);
-extern void serial_initialize(void);
extern void serial_stdio_init(void);
extern int serial_assign(const char *name);
extern void serial_reinit_all(void);
+int serial_initialize(void);
/* For usbtty */
#ifdef CONFIG_USB_TTY
--
2.17.1
[PATCH v4 16/17] blkcache: Extend blkcache_init to cover CONFIG_NEEDS_MANUAL_RELOC
Extend manual relocation of block_cache list pointers to all platforms that
enable CONFIG_NEEDS_MANUAL_RELOC. Remove m68k-specific checks and provide a
single implementation that adds gd->reloc_off to the pre-relocation
pointers.
Acked-by: Angelo Dureghello
Tested-by: Angelo Dureghello
Reviewed-by: Simon Glass
Reviewed-by: Eric Nelson
Signed-off-by: Ovidiu Panait
---
common/board_r.c | 2 +-
drivers/block/blkcache.c | 13 +++--
2 files changed, 8 insertions(+), 7 deletions(-)
diff --git a/common/board_r.c b/common/board_r.c
index 79772135a4..63c53b7b96 100644
--- a/common/board_r.c
+++ b/common/board_r.c
@@ -836,7 +836,7 @@ static init_fnc_t init_sequence_r[] = {
#if defined(CONFIG_PRAM)
initr_mem,
#endif
-#if defined(CONFIG_M68K) && defined(CONFIG_BLOCK_CACHE)
+#if defined(CONFIG_NEEDS_MANUAL_RELOC) && defined(CONFIG_BLOCK_CACHE)
blkcache_init,
#endif
run_main_loop,
diff --git a/drivers/block/blkcache.c b/drivers/block/blkcache.c
index b6fc72fe98..d97ee99cf4 100644
--- a/drivers/block/blkcache.c
+++ b/drivers/block/blkcache.c
@@ -12,6 +12,8 @@
#include
#include
+DECLARE_GLOBAL_DATA_PTR;
+
struct block_cache_node {
struct list_head lh;
int iftype;
@@ -22,21 +24,20 @@ struct block_cache_node {
char *cache;
};
-#ifndef CONFIG_M68K
static LIST_HEAD(block_cache);
-#else
-static struct list_head block_cache;
-#endif
static struct block_cache_stats _stats = {
.max_blocks_per_entry = 8,
.max_entries = 32
};
-#ifdef CONFIG_M68K
+#ifdef CONFIG_NEEDS_MANUAL_RELOC
int blkcache_init(void)
{
- INIT_LIST_HEAD(_cache);
+ struct list_head *head = _cache;
+
+ head->next = (uintptr_t)head->next + gd->reloc_off;
+ head->prev = (uintptr_t)head->prev + gd->reloc_off;
return 0;
}
--
2.17.1
[PATCH v4 03/17] Kconfig: Convert CONFIG_SYS_SRAM_SIZE to Kconfig
This converts ad-hoc CONFIG_SYS_SRAM_SIZE to Kconfig. Reviewed-by: Simon Glass Signed-off-by: Ovidiu Panait --- Kconfig | 7 +++ include/configs/devkit8000.h | 1 - include/configs/pic32mzdask.h | 2 -- include/configs/tricorder.h | 1 - scripts/config_whitelist.txt | 1 - 5 files changed, 7 insertions(+), 5 deletions(-) diff --git a/Kconfig b/Kconfig index 4ff1000848..d0f7ff80d1 100644 --- a/Kconfig +++ b/Kconfig @@ -366,6 +366,13 @@ config SYS_SRAM_BASE default 0x8000 if TARGET_PIC32MZDASK default 0x0 +config SYS_SRAM_SIZE + hex + default 0x0008 if TARGET_PIC32MZDASK + default 0x1 if TARGET_DEVKIT8000 + default 0x1 if TARGET_TRICORDER + default 0x0 + endmenu# General setup menu "Boot images" diff --git a/include/configs/devkit8000.h b/include/configs/devkit8000.h index f90c1c5a18..cdf7d7aa21 100644 --- a/include/configs/devkit8000.h +++ b/include/configs/devkit8000.h @@ -140,7 +140,6 @@ /* SRAM config */ #define CONFIG_SYS_SRAM_START 0x4020 -#define CONFIG_SYS_SRAM_SIZE 0x1 /* Defines for SPL */ diff --git a/include/configs/pic32mzdask.h b/include/configs/pic32mzdask.h index 25b898f2e6..d50edc7715 100644 --- a/include/configs/pic32mzdask.h +++ b/include/configs/pic32mzdask.h @@ -19,8 +19,6 @@ /*-- * Memory Layout */ -#define CONFIG_SYS_SRAM_SIZE 0x0008 /* 512K */ - /* Initial RAM for temporary stack, global data */ #define CONFIG_SYS_INIT_RAM_SIZE 0x1 #define CONFIG_SYS_INIT_RAM_ADDR \ diff --git a/include/configs/tricorder.h b/include/configs/tricorder.h index 83aa3cd468..d438a7e635 100644 --- a/include/configs/tricorder.h +++ b/include/configs/tricorder.h @@ -202,7 +202,6 @@ /* SRAM config */ #define CONFIG_SYS_SRAM_START 0x4020 -#define CONFIG_SYS_SRAM_SIZE 0x1 /* Defines for SPL */ diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 93233f066b..392b50875f 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -3788,7 +3788,6 @@ CONFIG_SYS_SPL_LEN CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_SPL_MALLOC_START CONFIG_SYS_SPR -CONFIG_SYS_SRAM_SIZE CONFIG_SYS_SRAM_START CONFIG_SYS_SRIO CONFIG_SYS_SRIO1_MEM_BASE -- 2.17.1
[PATCH v4 15/17] common/board_r: Remove initr_serial wrapper
Remove the initr_serial->serial_initialize indirection and call
serial_initialize directly.
Reviewed-by: Simon Glass
Signed-off-by: Ovidiu Panait
---
common/board_r.c | 8 +---
1 file changed, 1 insertion(+), 7 deletions(-)
diff --git a/common/board_r.c b/common/board_r.c
index 67dc25c7d2..79772135a4 100644
--- a/common/board_r.c
+++ b/common/board_r.c
@@ -187,12 +187,6 @@ static int initr_reloc_global_data(void)
return 0;
}
-static int initr_serial(void)
-{
- serial_initialize();
- return 0;
-}
-
#if defined(CONFIG_PPC) || defined(CONFIG_M68K) || defined(CONFIG_MIPS)
static int initr_trap(void)
{
@@ -705,7 +699,7 @@ static init_fnc_t init_sequence_r[] = {
#endif
initr_dm_devices,
stdio_init_tables,
- initr_serial,
+ serial_initialize,
initr_announce,
#if CONFIG_IS_ENABLED(WDT)
initr_watchdog,
--
2.17.1
[PATCH v4 10/17] board_f: m68k: Factor out m68k-specific bdinfo setup
Factor out m68k-specific bdinfo setup to arch_setup_bdinfo in
arch/m68k/lib/bdinfo.c. Also, use if(IS_ENABLED()) instead of #ifdef where
possible.
Reviewed-by: Simon Glass
Signed-off-by: Ovidiu Panait
---
arch/m68k/lib/bdinfo.c | 21 +
common/board_f.c | 19 ---
2 files changed, 25 insertions(+), 15 deletions(-)
diff --git a/arch/m68k/lib/bdinfo.c b/arch/m68k/lib/bdinfo.c
index b7bc6a3044..404e5f19ed 100644
--- a/arch/m68k/lib/bdinfo.c
+++ b/arch/m68k/lib/bdinfo.c
@@ -11,6 +11,27 @@
DECLARE_GLOBAL_DATA_PTR;
+int arch_setup_bdinfo(void)
+{
+ struct bd_info *bd = gd->bd;
+
+ bd->bi_mbar_base = CONFIG_SYS_MBAR; /* base of internal registers */
+
+ bd->bi_intfreq = gd->cpu_clk; /* Internal Freq, in Hz */
+ bd->bi_busfreq = gd->bus_clk; /* Bus Freq, in Hz */
+
+ if (IS_ENABLED(CONFIG_PCI))
+ bd->bi_pcifreq = gd->pci_clk;
+
+#if defined(CONFIG_EXTRA_CLOCK)
+ bd->bi_inpfreq = gd->arch.inp_clk; /* input Freq in Hz */
+ bd->bi_vcofreq = gd->arch.vco_clk; /* vco Freq in Hz */
+ bd->bi_flbfreq = gd->arch.flb_clk; /* flexbus Freq in Hz */
+#endif
+
+ return 0;
+}
+
void arch_print_bdinfo(void)
{
struct bd_info *bd = gd->bd;
diff --git a/common/board_f.c b/common/board_f.c
index e83bc2eb05..0c20f3fadf 100644
--- a/common/board_f.c
+++ b/common/board_f.c
@@ -618,7 +618,7 @@ int setup_bdinfo(void)
return arch_setup_bdinfo();
}
-#if defined(CONFIG_M68K) || defined(CONFIG_MIPS) || defined(CONFIG_PPC) || \
+#if defined(CONFIG_MIPS) || defined(CONFIG_PPC) || \
defined(CONFIG_SH)
static int setup_board_part1(void)
{
@@ -627,9 +627,6 @@ static int setup_board_part1(void)
#if defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
bd->bi_immr_base = CONFIG_SYS_IMMR; /* base of IMMR register */
#endif
-#if defined(CONFIG_M68K)
- bd->bi_mbar_base = CONFIG_SYS_MBAR; /* base of internal registers */
-#endif
#if defined(CONFIG_MPC83xx)
bd->bi_immrbar = CONFIG_SYS_IMMR;
#endif
@@ -638,7 +635,7 @@ static int setup_board_part1(void)
}
#endif
-#if defined(CONFIG_PPC) || defined(CONFIG_M68K)
+#if defined(CONFIG_PPC)
static int setup_board_part2(void)
{
struct bd_info *bd = gd->bd;
@@ -651,14 +648,6 @@ static int setup_board_part2(void)
bd->bi_sccfreq = gd->arch.scc_clk;
bd->bi_vco = gd->arch.vco_out;
#endif /* CONFIG_CPM2 */
-#if defined(CONFIG_M68K) && defined(CONFIG_PCI)
- bd->bi_pcifreq = gd->pci_clk;
-#endif
-#if defined(CONFIG_EXTRA_CLOCK)
- bd->bi_inpfreq = gd->arch.inp_clk; /* input Freq in Hz */
- bd->bi_vcofreq = gd->arch.vco_clk; /* vco Freq in Hz */
- bd->bi_flbfreq = gd->arch.flb_clk; /* flexbus Freq in Hz */
-#endif
return 0;
}
@@ -985,11 +974,11 @@ static const init_fnc_t init_sequence_f[] = {
dram_init_banksize,
show_dram_config,
setup_bdinfo,
-#if defined(CONFIG_M68K) || defined(CONFIG_MIPS) || defined(CONFIG_PPC) || \
+#if defined(CONFIG_MIPS) || defined(CONFIG_PPC) || \
defined(CONFIG_SH)
setup_board_part1,
#endif
-#if defined(CONFIG_PPC) || defined(CONFIG_M68K)
+#if defined(CONFIG_PPC)
INIT_FUNC_WATCHDOG_RESET
setup_board_part2,
#endif
--
2.17.1
[PATCH v4 11/17] board_f: ppc: Factor out ppc-specific bdinfo setup
Factor out ppc-specific bdinfo setup from generic init sequence to
arch_setup_bdinfo in arch/powerpc/lib/bdinfo.c.
Reviewed-by: Simon Glass
Signed-off-by: Ovidiu Panait
---
arch/powerpc/lib/bdinfo.c | 25 +
common/board_f.c | 36 ++--
2 files changed, 27 insertions(+), 34 deletions(-)
diff --git a/arch/powerpc/lib/bdinfo.c b/arch/powerpc/lib/bdinfo.c
index 07f823ee7a..36c9c99ee6 100644
--- a/arch/powerpc/lib/bdinfo.c
+++ b/arch/powerpc/lib/bdinfo.c
@@ -11,6 +11,31 @@
DECLARE_GLOBAL_DATA_PTR;
+int arch_setup_bdinfo(void)
+{
+ struct bd_info *bd = gd->bd;
+
+#if defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
+ bd->bi_immr_base = CONFIG_SYS_IMMR; /* base of IMMR register */
+#endif
+
+#if defined(CONFIG_MPC83xx)
+ bd->bi_immrbar = CONFIG_SYS_IMMR;
+#endif
+
+ bd->bi_intfreq = gd->cpu_clk; /* Internal Freq, in Hz */
+ bd->bi_busfreq = gd->bus_clk; /* Bus Freq, in Hz */
+
+#if defined(CONFIG_CPM2)
+ bd->bi_cpmfreq = gd->arch.cpm_clk;
+ bd->bi_brgfreq = gd->arch.brg_clk;
+ bd->bi_sccfreq = gd->arch.scc_clk;
+ bd->bi_vco = gd->arch.vco_out;
+#endif /* CONFIG_CPM2 */
+
+ return 0;
+}
+
void __weak board_detail(void)
{
/* Please define board_detail() for your PPC platform */
diff --git a/common/board_f.c b/common/board_f.c
index 0c20f3fadf..e670155417 100644
--- a/common/board_f.c
+++ b/common/board_f.c
@@ -618,37 +618,9 @@ int setup_bdinfo(void)
return arch_setup_bdinfo();
}
-#if defined(CONFIG_MIPS) || defined(CONFIG_PPC) || \
- defined(CONFIG_SH)
+#if defined(CONFIG_MIPS) || defined(CONFIG_SH)
static int setup_board_part1(void)
{
- struct bd_info *bd = gd->bd;
-
-#if defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
- bd->bi_immr_base = CONFIG_SYS_IMMR; /* base of IMMR register */
-#endif
-#if defined(CONFIG_MPC83xx)
- bd->bi_immrbar = CONFIG_SYS_IMMR;
-#endif
-
- return 0;
-}
-#endif
-
-#if defined(CONFIG_PPC)
-static int setup_board_part2(void)
-{
- struct bd_info *bd = gd->bd;
-
- bd->bi_intfreq = gd->cpu_clk; /* Internal Freq, in Hz */
- bd->bi_busfreq = gd->bus_clk; /* Bus Freq, in Hz */
-#if defined(CONFIG_CPM2)
- bd->bi_cpmfreq = gd->arch.cpm_clk;
- bd->bi_brgfreq = gd->arch.brg_clk;
- bd->bi_sccfreq = gd->arch.scc_clk;
- bd->bi_vco = gd->arch.vco_out;
-#endif /* CONFIG_CPM2 */
-
return 0;
}
#endif
@@ -974,14 +946,10 @@ static const init_fnc_t init_sequence_f[] = {
dram_init_banksize,
show_dram_config,
setup_bdinfo,
-#if defined(CONFIG_MIPS) || defined(CONFIG_PPC) || \
- defined(CONFIG_SH)
+#if defined(CONFIG_MIPS) || defined(CONFIG_SH)
setup_board_part1,
#endif
-#if defined(CONFIG_PPC)
INIT_FUNC_WATCHDOG_RESET
- setup_board_part2,
-#endif
display_new_sp,
#ifdef CONFIG_OF_BOARD_FIXUP
fix_fdt,
--
2.17.1
[PATCH v4 12/17] board_f: Remove setup_board_part1
Now that all arch specific code was converted to setup_bdinfo, we can
remove setup_board_part1.
Reviewed-by: Simon Glass
Signed-off-by: Ovidiu Panait
---
common/board_f.c | 12 +---
1 file changed, 1 insertion(+), 11 deletions(-)
diff --git a/common/board_f.c b/common/board_f.c
index e670155417..79532f4365 100644
--- a/common/board_f.c
+++ b/common/board_f.c
@@ -618,13 +618,6 @@ int setup_bdinfo(void)
return arch_setup_bdinfo();
}
-#if defined(CONFIG_MIPS) || defined(CONFIG_SH)
-static int setup_board_part1(void)
-{
- return 0;
-}
-#endif
-
#ifdef CONFIG_POST
static int init_post(void)
{
@@ -945,11 +938,8 @@ static const init_fnc_t init_sequence_f[] = {
reserve_stacks,
dram_init_banksize,
show_dram_config,
- setup_bdinfo,
-#if defined(CONFIG_MIPS) || defined(CONFIG_SH)
- setup_board_part1,
-#endif
INIT_FUNC_WATCHDOG_RESET
+ setup_bdinfo,
display_new_sp,
#ifdef CONFIG_OF_BOARD_FIXUP
fix_fdt,
--
2.17.1
[PATCH v4 06/17] board_f: Introduce setup_bdinfo initcall
Introduce setup_bdinfo initcall as a generic routine to populate bdinfo
fields.
Reviewed-by: Simon Glass
Signed-off-by: Ovidiu Panait
---
common/board_f.c | 6 ++
include/init.h | 10 ++
2 files changed, 16 insertions(+)
diff --git a/common/board_f.c b/common/board_f.c
index 88ff0424a7..72446f6da5 100644
--- a/common/board_f.c
+++ b/common/board_f.c
@@ -598,6 +598,11 @@ static int display_new_sp(void)
return 0;
}
+int setup_bdinfo(void)
+{
+ return 0;
+}
+
#if defined(CONFIG_M68K) || defined(CONFIG_MIPS) || defined(CONFIG_PPC) || \
defined(CONFIG_SH)
static int setup_board_part1(void)
@@ -975,6 +980,7 @@ static const init_fnc_t init_sequence_f[] = {
reserve_stacks,
dram_init_banksize,
show_dram_config,
+ setup_bdinfo,
#if defined(CONFIG_M68K) || defined(CONFIG_MIPS) || defined(CONFIG_PPC) || \
defined(CONFIG_SH)
setup_board_part1,
diff --git a/include/init.h b/include/init.h
index e727031514..2a8c910677 100644
--- a/include/init.h
+++ b/include/init.h
@@ -141,6 +141,16 @@ int arch_reserve_stacks(void);
*/
int arch_reserve_mmu(void);
+/**
+ * setup_bdinfo() - Generic boardinfo setup
+ *
+ * Routine for populating various generic boardinfo fields of
+ * gd->bd. It is called during the generic board init sequence.
+ *
+ * Return: 0 if OK
+ */
+int setup_bdinfo(void);
+
/**
* init_cache_f_r() - Turn on the cache in preparation for relocation
*
--
2.17.1
[PATCH v4 05/17] cmd: bdinfo: Move sram info prints to generic code
bi_sramstart and bi_sramsize are generic members of the bd_info structure,
so move the m68k/powerpc-specific prints to generic code. Also, print them
only if SRAM support is enabled via CONFIG_SYS_HAS_SRAM.
Reviewed-by: Simon Glass
Signed-off-by: Ovidiu Panait
---
arch/m68k/lib/bdinfo.c| 4
arch/powerpc/lib/bdinfo.c | 4
cmd/bdinfo.c | 4
3 files changed, 4 insertions(+), 8 deletions(-)
diff --git a/arch/m68k/lib/bdinfo.c b/arch/m68k/lib/bdinfo.c
index fb4d1a52fd..b7bc6a3044 100644
--- a/arch/m68k/lib/bdinfo.c
+++ b/arch/m68k/lib/bdinfo.c
@@ -15,10 +15,6 @@ void arch_print_bdinfo(void)
{
struct bd_info *bd = gd->bd;
-#if defined(CONFIG_SYS_INIT_RAM_ADDR)
- bdinfo_print_num("sramstart", (ulong)bd->bi_sramstart);
- bdinfo_print_num("sramsize", (ulong)bd->bi_sramsize);
-#endif
bdinfo_print_mhz("busfreq", bd->bi_busfreq);
#if defined(CONFIG_SYS_MBAR)
bdinfo_print_num("mbar", bd->bi_mbar_base);
diff --git a/arch/powerpc/lib/bdinfo.c b/arch/powerpc/lib/bdinfo.c
index 75611e2592..07f823ee7a 100644
--- a/arch/powerpc/lib/bdinfo.c
+++ b/arch/powerpc/lib/bdinfo.c
@@ -20,10 +20,6 @@ void arch_print_bdinfo(void)
{
struct bd_info *bd = gd->bd;
-#if defined(CONFIG_SYS_INIT_RAM_ADDR)
- bdinfo_print_num("sramstart", (ulong)bd->bi_sramstart);
- bdinfo_print_num("sramsize", (ulong)bd->bi_sramsize);
-#endif
bdinfo_print_mhz("busfreq", bd->bi_busfreq);
#if defined(CONFIG_MPC8xx) || defined(CONFIG_E500)
bdinfo_print_num("immr_base", bd->bi_immr_base);
diff --git a/cmd/bdinfo.c b/cmd/bdinfo.c
index 8b2c105e77..7da36f8096 100644
--- a/cmd/bdinfo.c
+++ b/cmd/bdinfo.c
@@ -75,6 +75,10 @@ int do_bdinfo(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
print_bi_dram(bd);
bdinfo_print_num("memstart", (ulong)bd->bi_memstart);
print_lnum("memsize", (u64)bd->bi_memsize);
+ if (IS_ENABLED(CONFIG_SYS_HAS_SRAM)) {
+ bdinfo_print_num("sramstart", (ulong)bd->bi_sramstart);
+ bdinfo_print_num("sramsize", (ulong)bd->bi_sramsize);
+ }
bdinfo_print_num("flashstart", (ulong)bd->bi_flashstart);
bdinfo_print_num("flashsize", (ulong)bd->bi_flashsize);
bdinfo_print_num("flashoffset", (ulong)bd->bi_flashoffset);
--
2.17.1
[PATCH v4 09/17] board_f: Move sram bdinfo assignments to generic code
Move sram related bdinfo from arch-specific setup_board_part1 to generic
code in setup_bdinfo. Also use "if (IS_ENABLED(CONFIG_SYS_HAS_SRAM))"
instead of "#ifdef CONFIG_SYS_SRAM_BASE".
Reviewed-by: Simon Glass
Signed-off-by: Ovidiu Panait
---
common/board_f.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/common/board_f.c b/common/board_f.c
index 3b11f08725..e83bc2eb05 100644
--- a/common/board_f.c
+++ b/common/board_f.c
@@ -610,6 +610,11 @@ int setup_bdinfo(void)
bd->bi_memstart = gd->ram_base; /* start of memory */
bd->bi_memsize = gd->ram_size; /* size in bytes */
+ if (IS_ENABLED(CONFIG_SYS_HAS_SRAM)) {
+ bd->bi_sramstart = CONFIG_SYS_SRAM_BASE; /* start of SRAM */
+ bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE; /* size of SRAM */
+ }
+
return arch_setup_bdinfo();
}
@@ -619,11 +624,6 @@ static int setup_board_part1(void)
{
struct bd_info *bd = gd->bd;
-#ifdef CONFIG_SYS_SRAM_BASE
- bd->bi_sramstart = CONFIG_SYS_SRAM_BASE;/* start of SRAM */
- bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE; /* size of SRAM */
-#endif
-
#if defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
bd->bi_immr_base = CONFIG_SYS_IMMR; /* base of IMMR register */
#endif
--
2.17.1
[PATCH v4 04/17] Kconfig: Remove CONFIG_SYS_SRAM_START
Remove ad-hoc CONFIG_SYS_SRAM_START and use CONFIG_SYS_SRAM_BASE instead. Reviewed-by: Simon Glass Signed-off-by: Ovidiu Panait --- Kconfig | 2 ++ include/configs/devkit8000.h | 3 --- include/configs/tricorder.h | 3 --- scripts/config_whitelist.txt | 1 - 4 files changed, 2 insertions(+), 7 deletions(-) diff --git a/Kconfig b/Kconfig index d0f7ff80d1..b16ee0f57d 100644 --- a/Kconfig +++ b/Kconfig @@ -364,6 +364,8 @@ config SYS_HAS_SRAM config SYS_SRAM_BASE hex default 0x8000 if TARGET_PIC32MZDASK + default 0x4020 if TARGET_DEVKIT8000 + default 0x4020 if TARGET_TRICORDER default 0x0 config SYS_SRAM_SIZE diff --git a/include/configs/devkit8000.h b/include/configs/devkit8000.h index cdf7d7aa21..b4f649a958 100644 --- a/include/configs/devkit8000.h +++ b/include/configs/devkit8000.h @@ -138,9 +138,6 @@ /* Boot Argument Buffer Size */ -/* SRAM config */ -#define CONFIG_SYS_SRAM_START 0x4020 - /* Defines for SPL */ /* NAND boot config */ diff --git a/include/configs/tricorder.h b/include/configs/tricorder.h index d438a7e635..8ffa39f92f 100644 --- a/include/configs/tricorder.h +++ b/include/configs/tricorder.h @@ -200,9 +200,6 @@ CONFIG_SYS_INIT_RAM_SIZE - \ GENERATED_GBL_DATA_SIZE) -/* SRAM config */ -#define CONFIG_SYS_SRAM_START 0x4020 - /* Defines for SPL */ #define CONFIG_SPL_NAND_BASE diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 392b50875f..f840a504b6 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -3788,7 +3788,6 @@ CONFIG_SYS_SPL_LEN CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_SPL_MALLOC_START CONFIG_SYS_SPR -CONFIG_SYS_SRAM_START CONFIG_SYS_SRIO CONFIG_SYS_SRIO1_MEM_BASE CONFIG_SYS_SRIO1_MEM_BUS -- 2.17.1
[PATCH v4 08/17] board_f: Factor out bdinfo bi_mem{start, size} to setup_bdinfo
Move all assignments to gd->bd->bi_mem{start,size} to generic code in
setup_bdinfo.
Xtensa architecture is special in this regard as it defines its own
handling of gd->bd->bi_mem{start,size} fields. In order to avoid defining
a weak SDRAM function, let arch_setup_bdinfo overwrite the generic flags.
For ARC architecture, remove ARCH_EARLY_INIT_R from Kconfig since it is
not needed anymore.
Also, use gd->ram_base to populate bi_memstart to avoid an ifdef.
Signed-off-by: Ovidiu Panait
---
arch/Kconfig | 1 -
arch/arc/lib/cpu.c| 7 ---
arch/xtensa/lib/Makefile | 2 +-
arch/xtensa/lib/bdinfo.c | 22 ++
board/cadence/xtfpga/xtfpga.c | 3 ---
common/board_f.c | 11 +--
6 files changed, 28 insertions(+), 18 deletions(-)
create mode 100644 arch/xtensa/lib/bdinfo.c
diff --git a/arch/Kconfig b/arch/Kconfig
index 9be02d1319..4d9557959c 100644
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -10,7 +10,6 @@ choice
config ARC
bool "ARC architecture"
- select ARCH_EARLY_INIT_R
select ARC_TIMER
select CLK
select HAVE_PRIVATE_LIBGCC
diff --git a/arch/arc/lib/cpu.c b/arch/arc/lib/cpu.c
index 27b5832a0c..d66a8c867a 100644
--- a/arch/arc/lib/cpu.c
+++ b/arch/arc/lib/cpu.c
@@ -25,13 +25,6 @@ int arch_cpu_init(void)
return 0;
}
-int arch_early_init_r(void)
-{
- gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
- gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
- return 0;
-}
-
/* This is a dummy function on arc */
int dram_init(void)
{
diff --git a/arch/xtensa/lib/Makefile b/arch/xtensa/lib/Makefile
index c59df7d372..ceee59b9bd 100644
--- a/arch/xtensa/lib/Makefile
+++ b/arch/xtensa/lib/Makefile
@@ -5,4 +5,4 @@
obj-$(CONFIG_CMD_BOOTM) += bootm.o
-obj-y += cache.o misc.o relocate.o time.o
+obj-y += cache.o misc.o relocate.o time.o bdinfo.o
diff --git a/arch/xtensa/lib/bdinfo.c b/arch/xtensa/lib/bdinfo.c
new file mode 100644
index 00..4ec8529521
--- /dev/null
+++ b/arch/xtensa/lib/bdinfo.c
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * XTENSA-specific information for the 'bd' command
+ *
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, w...@denx.de.
+ */
+
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int arch_setup_bdinfo(void)
+{
+ struct bd_info *bd = gd->bd;
+
+ bd->bi_memstart = PHYSADDR(CONFIG_SYS_SDRAM_BASE);
+ bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
+
+ return 0;
+}
diff --git a/board/cadence/xtfpga/xtfpga.c b/board/cadence/xtfpga/xtfpga.c
index 2869e5cf68..4b49b6e5c8 100644
--- a/board/cadence/xtfpga/xtfpga.c
+++ b/board/cadence/xtfpga/xtfpga.c
@@ -51,9 +51,6 @@ int checkboard(void)
int dram_init_banksize(void)
{
- gd->bd->bi_memstart = PHYSADDR(CONFIG_SYS_SDRAM_BASE);
- gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
-
return 0;
}
diff --git a/common/board_f.c b/common/board_f.c
index 4356431488..3b11f08725 100644
--- a/common/board_f.c
+++ b/common/board_f.c
@@ -605,6 +605,11 @@ __weak int arch_setup_bdinfo(void)
int setup_bdinfo(void)
{
+ struct bd_info *bd = gd->bd;
+
+ bd->bi_memstart = gd->ram_base; /* start of memory */
+ bd->bi_memsize = gd->ram_size; /* size in bytes */
+
return arch_setup_bdinfo();
}
@@ -614,12 +619,6 @@ static int setup_board_part1(void)
{
struct bd_info *bd = gd->bd;
- /*
-* Save local variables to board info struct
-*/
- bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;/* start of memory */
- bd->bi_memsize = gd->ram_size; /* size in bytes */
-
#ifdef CONFIG_SYS_SRAM_BASE
bd->bi_sramstart = CONFIG_SYS_SRAM_BASE;/* start of SRAM */
bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE; /* size of SRAM */
--
2.17.1
[PATCH v4 02/17] Kconfig: Convert CONFIG_SYS_SRAM_BASE to Kconfig
This converts ad-hoc CONFIG_SYS_SRAM_BASE to Kconfig. Reviewed-by: Simon Glass Signed-off-by: Ovidiu Panait --- Kconfig | 5 + include/configs/pic32mzdask.h | 1 - scripts/config_whitelist.txt | 1 - 3 files changed, 5 insertions(+), 2 deletions(-) diff --git a/Kconfig b/Kconfig index 934c020a2f..4ff1000848 100644 --- a/Kconfig +++ b/Kconfig @@ -361,6 +361,11 @@ config SYS_HAS_SRAM SRAM base address is controlled by CONFIG_SYS_SRAM_BASE. SRAM size is controlled by CONFIG_SYS_SRAM_SIZE. +config SYS_SRAM_BASE + hex + default 0x8000 if TARGET_PIC32MZDASK + default 0x0 + endmenu# General setup menu "Boot images" diff --git a/include/configs/pic32mzdask.h b/include/configs/pic32mzdask.h index 73edd28f1a..25b898f2e6 100644 --- a/include/configs/pic32mzdask.h +++ b/include/configs/pic32mzdask.h @@ -19,7 +19,6 @@ /*-- * Memory Layout */ -#define CONFIG_SYS_SRAM_BASE 0x8000 #define CONFIG_SYS_SRAM_SIZE 0x0008 /* 512K */ /* Initial RAM for temporary stack, global data */ diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 2ec7642583..93233f066b 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -3788,7 +3788,6 @@ CONFIG_SYS_SPL_LEN CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_SPL_MALLOC_START CONFIG_SYS_SPR -CONFIG_SYS_SRAM_BASE CONFIG_SYS_SRAM_SIZE CONFIG_SYS_SRAM_START CONFIG_SYS_SRIO -- 2.17.1
[PATCH v2 1/3] armv8: gpio: add gpio feature
From: "hui.song"
add one struct mpc8xxx_gpio_plat to enable gpio feature.
Signed-off-by: hui.song
---
.../include/asm/arch-fsl-layerscape/gpio.h| 22 +++
1 file changed, 22 insertions(+)
create mode 100644 arch/arm/include/asm/arch-fsl-layerscape/gpio.h
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/gpio.h
b/arch/arm/include/asm/arch-fsl-layerscape/gpio.h
new file mode 100644
index 00..7ae5eee8b6
--- /dev/null
+++ b/arch/arm/include/asm/arch-fsl-layerscape/gpio.h
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2020 NXP
+ */
+
+/*
+ * Dummy header file to enable CONFIG_OF_CONTROL.
+ * If CONFIG_OF_CONTROL is enabled, lib/fdtdec.c is compiled.
+ * It includes via , so those SoCs that enable
+ * OF_CONTROL must have arch/gpio.h.
+ */
+
+#ifndef __ASM_ARCH_MX85XX_GPIO_H
+#define __ASM_ARCH_MX85XX_GPIO_H
+
+struct mpc8xxx_gpio_plat {
+ ulong addr;
+ ulong size;
+ uint ngpios;
+};
+
+#endif
--
2.17.1
[PATCH v4 07/17] board_f: Introduce arch_setup_bdinfo initcall
Certain architectures (ppc, mips, sh, m68k) use setup board_part1 and
setup_board_part2 calls during pre-relocation init to populate gd->bd
boardinfo fields. This makes the generic init sequence cluttered with
arch-specific ifdefs.
In order to clean these arch-specific sequences from generic init,
introduce arch_setup_bdinfo weak initcall so that everyone can define their
own bdinfo setup routines.
Reviewed-by: Simon Glass
Signed-off-by: Ovidiu Panait
---
common/board_f.c | 7 ++-
include/init.h | 12
2 files changed, 18 insertions(+), 1 deletion(-)
diff --git a/common/board_f.c b/common/board_f.c
index 72446f6da5..4356431488 100644
--- a/common/board_f.c
+++ b/common/board_f.c
@@ -598,11 +598,16 @@ static int display_new_sp(void)
return 0;
}
-int setup_bdinfo(void)
+__weak int arch_setup_bdinfo(void)
{
return 0;
}
+int setup_bdinfo(void)
+{
+ return arch_setup_bdinfo();
+}
+
#if defined(CONFIG_M68K) || defined(CONFIG_MIPS) || defined(CONFIG_PPC) || \
defined(CONFIG_SH)
static int setup_board_part1(void)
diff --git a/include/init.h b/include/init.h
index 2a8c910677..e9354e8fca 100644
--- a/include/init.h
+++ b/include/init.h
@@ -141,6 +141,18 @@ int arch_reserve_stacks(void);
*/
int arch_reserve_mmu(void);
+/**
+ * arch_setup_bdinfo() - Architecture dependent boardinfo setup
+ *
+ * Architecture-specific routine for populating various boardinfo fields of
+ * gd->bd. It is called during the generic board init sequence.
+ *
+ * If an implementation is not provided, it will just be a nop stub.
+ *
+ * Return: 0 if OK
+ */
+int arch_setup_bdinfo(void);
+
/**
* setup_bdinfo() - Generic boardinfo setup
*
--
2.17.1
[PATCH v2 3/3] gpio: mpc8xxx: support fsl-layerscape platform.
From: "hui.song"
Make the MPC8XXX gpio driver to support the fsl-layerscape.
Signed-off-by: hui.song
---
drivers/gpio/mpc8xxx_gpio.c | 108 +---
1 file changed, 87 insertions(+), 21 deletions(-)
diff --git a/drivers/gpio/mpc8xxx_gpio.c b/drivers/gpio/mpc8xxx_gpio.c
index 1dfd22522c..27881a7322 100644
--- a/drivers/gpio/mpc8xxx_gpio.c
+++ b/drivers/gpio/mpc8xxx_gpio.c
@@ -6,12 +6,15 @@
* based on arch/powerpc/include/asm/mpc85xx_gpio.h, which is
*
* Copyright 2010 eXMeritus, A Boeing Company
+ * Copyright 2020 NXP
*/
#include
#include
#include
#include
+#include
+#include
struct ccsr_gpio {
u32 gpdir;
@@ -20,6 +23,7 @@ struct ccsr_gpio {
u32 gpier;
u32 gpimr;
u32 gpicr;
+ u32 gpibe;
};
struct mpc8xxx_gpio_data {
@@ -35,6 +39,7 @@ struct mpc8xxx_gpio_data {
*/
u32 dat_shadow;
ulong type;
+ bool little_endian;
};
enum {
@@ -47,33 +52,56 @@ inline u32 gpio_mask(uint gpio)
return (1U << (31 - (gpio)));
}
-static inline u32 mpc8xxx_gpio_get_val(struct ccsr_gpio *base, u32 mask)
+static inline u32 mpc8xxx_gpio_get_val(struct udevice *dev, u32 mask)
{
- return in_be32(>gpdat) & mask;
+ struct mpc8xxx_gpio_data *data = dev_get_priv(dev);
+
+ if (data->little_endian)
+ return in_le32(>base->gpdat) & mask;
+ else
+ return in_be32(>base->gpdat) & mask;
}
-static inline u32 mpc8xxx_gpio_get_dir(struct ccsr_gpio *base, u32 mask)
+static inline u32 mpc8xxx_gpio_get_dir(struct udevice *dev, u32 mask)
{
- return in_be32(>gpdir) & mask;
+ struct mpc8xxx_gpio_data *data = dev_get_priv(dev);
+
+ if (data->little_endian)
+ return in_le32(>base->gpdir) & mask;
+ else
+ return in_be32(>base->gpdir) & mask;
}
-static inline int mpc8xxx_gpio_open_drain_val(struct ccsr_gpio *base, u32 mask)
+static inline int mpc8xxx_gpio_open_drain_val(struct udevice *dev, u32 mask)
{
- return in_be32(>gpodr) & mask;
+ struct mpc8xxx_gpio_data *data = dev_get_priv(dev);
+
+ if (data->little_endian)
+ return in_le32(>base->gpodr) & mask;
+ else
+ return in_be32(>base->gpodr) & mask;
}
-static inline void mpc8xxx_gpio_open_drain_on(struct ccsr_gpio *base, u32
+static inline void mpc8xxx_gpio_open_drain_on(struct udevice *dev, u32
gpios)
{
+ struct mpc8xxx_gpio_data *data = dev_get_priv(dev);
/* GPODR register 1 -> open drain on */
- setbits_be32(>gpodr, gpios);
+ if (data->little_endian)
+ setbits_le32(>base->gpodr, gpios);
+ else
+ setbits_be32(>base->gpodr, gpios);
}
-static inline void mpc8xxx_gpio_open_drain_off(struct ccsr_gpio *base,
+static inline void mpc8xxx_gpio_open_drain_off(struct udevice *dev,
u32 gpios)
{
+ struct mpc8xxx_gpio_data *data = dev_get_priv(dev);
/* GPODR register 0 -> open drain off (actively driven) */
- clrbits_be32(>gpodr, gpios);
+ if (data->little_endian)
+ clrbits_le32(>base->gpodr, gpios);
+ else
+ clrbits_be32(>base->gpodr, gpios);
}
static int mpc8xxx_gpio_direction_input(struct udevice *dev, uint gpio)
@@ -82,7 +110,10 @@ static int mpc8xxx_gpio_direction_input(struct udevice
*dev, uint gpio)
u32 mask = gpio_mask(gpio);
/* GPDIR register 0 -> input */
- clrbits_be32(>base->gpdir, mask);
+ if (data->little_endian)
+ clrbits_le32(>base->gpdir, mask);
+ else
+ clrbits_be32(>base->gpdir, mask);
return 0;
}
@@ -100,10 +131,20 @@ static int mpc8xxx_gpio_set_value(struct udevice *dev,
uint gpio, int value)
data->dat_shadow &= ~mask;
}
- gpdir = in_be32(>gpdir);
+ if (data->little_endian)
+ gpdir = in_le32(>gpdir);
+ else
+ gpdir = in_be32(>gpdir);
+
gpdir |= gpio_mask(gpio);
- out_be32(>gpdat, gpdir & data->dat_shadow);
- out_be32(>gpdir, gpdir);
+
+ if (data->little_endian) {
+ out_le32(>gpdat, gpdir & data->dat_shadow);
+ out_le32(>gpdir, gpdir);
+ } else {
+ out_be32(>gpdat, gpdir & data->dat_shadow);
+ out_be32(>gpdir, gpdir);
+ }
return 0;
}
@@ -124,21 +165,20 @@ static int mpc8xxx_gpio_get_value(struct udevice *dev,
uint gpio)
{
struct mpc8xxx_gpio_data *data = dev_get_priv(dev);
- if (!!mpc8xxx_gpio_get_dir(data->base, gpio_mask(gpio))) {
+ if (!!mpc8xxx_gpio_get_dir(dev, gpio_mask(gpio))) {
/* Output -> use shadowed value */
return !!(data->dat_shadow & gpio_mask(gpio));
}
/* Input -> read value from GPDAT register */
- return
[PATCH v1 21/24] net: Add NIC controller driver for OcteonTX2
From: Suneel Garapati
Adds support for Network Interface controllers found on
OcteonTX2 SoC platforms.
Signed-off-by: Suneel Garapati
Cc: Joe Hershberger
Signed-off-by: Stefan Roese
---
Changes in v1:
- Change patch subject
- Rebased on latest TOT
- Removed inclusion of common.h
drivers/net/Kconfig| 17 +
drivers/net/Makefile |2 +
drivers/net/octeontx2/Makefile | 11 +
drivers/net/octeontx2/cgx.c| 298
drivers/net/octeontx2/cgx.h| 107 +++
drivers/net/octeontx2/cgx_intf.c | 717 ++
drivers/net/octeontx2/cgx_intf.h | 450
drivers/net/octeontx2/lmt.h| 51 ++
drivers/net/octeontx2/nix.c| 833 +
drivers/net/octeontx2/nix.h| 355 +
drivers/net/octeontx2/nix_af.c | 1104
drivers/net/octeontx2/npc.h| 92 +++
drivers/net/octeontx2/rvu.h| 121 +++
drivers/net/octeontx2/rvu_af.c | 173 +
drivers/net/octeontx2/rvu_common.c | 73 ++
drivers/net/octeontx2/rvu_pf.c | 118 +++
16 files changed, 4522 insertions(+)
create mode 100644 drivers/net/octeontx2/Makefile
create mode 100644 drivers/net/octeontx2/cgx.c
create mode 100644 drivers/net/octeontx2/cgx.h
create mode 100644 drivers/net/octeontx2/cgx_intf.c
create mode 100644 drivers/net/octeontx2/cgx_intf.h
create mode 100644 drivers/net/octeontx2/lmt.h
create mode 100644 drivers/net/octeontx2/nix.c
create mode 100644 drivers/net/octeontx2/nix.h
create mode 100644 drivers/net/octeontx2/nix_af.c
create mode 100644 drivers/net/octeontx2/npc.h
create mode 100644 drivers/net/octeontx2/rvu.h
create mode 100644 drivers/net/octeontx2/rvu_af.c
create mode 100644 drivers/net/octeontx2/rvu_common.c
create mode 100644 drivers/net/octeontx2/rvu_pf.c
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 4e746c8156..fdc94a50f0 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -393,6 +393,15 @@ config NET_OCTEONTX
help
You must select Y to enable network device support for
OcteonTX SoCs. If unsure, say n
+
+config NET_OCTEONTX2
+ bool "OcteonTX2 Ethernet support"
+ depends on ARCH_OCTEONTX2
+ select OCTEONTX2_CGX_INTF
+ help
+ You must select Y to enable network device support for
+ OcteonTX2 SoCs. If unsure, say n
+
config OCTEONTX_SMI
bool "OcteonTX SMI Device support"
depends on ARCH_OCTEONTX || ARCH_OCTEONTX2
@@ -400,6 +409,14 @@ config OCTEONTX_SMI
You must select Y to enable SMI controller support for
OcteonTX or OcteonTX2 SoCs. If unsure, say n
+config OCTEONTX2_CGX_INTF
+ bool "OcteonTX2 CGX ATF interface support"
+ depends on ARCH_OCTEONTX2
+ default y if ARCH_OCTEONTX2
+ help
+ You must select Y to enable CGX ATF interface support for
+ OcteonTX2 SoCs. If unsure, say n
+
config PCH_GBE
bool "Intel Platform Controller Hub EG20T GMAC driver"
depends on DM_ETH && DM_PCI
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index bee9680f76..c07b5ad698 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -66,7 +66,9 @@ obj-$(CONFIG_SMC9) += smc9.o
obj-$(CONFIG_SMC911X) += smc911x.o
obj-$(CONFIG_TSEC_ENET) += tsec.o fsl_mdio.o
obj-$(CONFIG_NET_OCTEONTX) += octeontx/
+obj-$(CONFIG_NET_OCTEONTX2) += octeontx2/
obj-$(CONFIG_OCTEONTX_SMI) += octeontx/smi.o
+obj-$(CONFIG_OCTEONTX2_CGX_INTF) += octeontx2/cgx_intf.o
obj-$(CONFIG_FMAN_ENET) += fsl_mdio.o
obj-$(CONFIG_ULI526X) += uli526x.o
obj-$(CONFIG_VSC7385_ENET) += vsc7385.o
diff --git a/drivers/net/octeontx2/Makefile b/drivers/net/octeontx2/Makefile
new file mode 100644
index 00..92183ffc3e
--- /dev/null
+++ b/drivers/net/octeontx2/Makefile
@@ -0,0 +1,11 @@
+#/*
+# * Copyright (C) 2018 Marvell International Ltd.
+# *
+# * SPDX-License-Identifier:GPL-2.0
+# * https://spdx.org/licenses
+# */
+
+
+obj-$(CONFIG_NET_OCTEONTX2) += cgx.o nix_af.o nix.o rvu_pf.o \
+ rvu_af.o rvu_common.o
+
diff --git a/drivers/net/octeontx2/cgx.c b/drivers/net/octeontx2/cgx.c
new file mode 100644
index 00..378b11503e
--- /dev/null
+++ b/drivers/net/octeontx2/cgx.c
@@ -0,0 +1,298 @@
+// SPDX-License-Identifier:GPL-2.0
+/*
+ * Copyright (C) 2018 Marvell International Ltd.
+ *
+ * https://spdx.org/licenses
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "cgx.h"
+
+char lmac_type_to_str[][8] = {
+ "SGMII",
+ "XAUI",
+ "RXAUI",
+ "10G_R",
+ "40G_R",
+ "RGMII",
+ "QSGMII",
+ "25G_R",
+ "50G_R",
+ "100G_R",
+ "USXGMII",
+};
+
+char lmac_speed_to_str[][8] = {
+ "0",
+ "10M",
+ "100M",
+ "1G",
+ "2.5G",
+ "5G",
+ "10G",
+ "20G",
+ "25G",
+ "40G",
+
[PATCH v2 2/3] dm: armv8: gpio: include for fsl-layerscape
From: "hui.song" Enable the gpio feature on fsl-layerscape platform. Signed-off-by: hui.song --- arch/arm/include/asm/gpio.h | 8 ++-- 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/arch/arm/include/asm/gpio.h b/arch/arm/include/asm/gpio.h index 333e407b66..7715a01706 100644 --- a/arch/arm/include/asm/gpio.h +++ b/arch/arm/include/asm/gpio.h @@ -1,12 +1,8 @@ #if !defined(CONFIG_ARCH_UNIPHIER) && !defined(CONFIG_ARCH_STI) && \ !defined(CONFIG_ARCH_K3) && !defined(CONFIG_ARCH_BCM68360) && \ !defined(CONFIG_ARCH_BCM6858) && !defined(CONFIG_ARCH_BCM63158) && \ - !defined(CONFIG_ARCH_ROCKCHIP) && !defined(CONFIG_ARCH_LX2160A) && \ - !defined(CONFIG_ARCH_LS1028A) && !defined(CONFIG_ARCH_LS2080A) && \ - !defined(CONFIG_ARCH_LS1088A) && !defined(CONFIG_ARCH_ASPEED) && \ - !defined(CONFIG_ARCH_LS1012A) && !defined(CONFIG_ARCH_LS1043A) && \ - !defined(CONFIG_ARCH_LS1046A) && !defined(CONFIG_ARCH_U8500) && \ - !defined(CONFIG_CORTINA_PLATFORM) + !defined(CONFIG_ARCH_ROCKCHIP) && !defined(CONFIG_ARCH_ASPEED) && \ + !defined(CONFIG_ARCH_U8500) && !defined(CONFIG_CORTINA_PLATFORM) #include #endif #include -- 2.17.1
[PATCH v1 18/24] mmc: Add MMC controller driver for OcteonTX / TX2
From: Suneel Garapati Adds support for MMC controllers found on OcteonTX or OcteonTX2 SoC platforms. Signed-off-by: Aaron Williams Signed-off-by: Suneel Garapati Cc: Peng Fan Signed-off-by: Stefan Roese --- Changes in v1: - Change patch subject - Rebased on latest TOT - Removed inclusion of common.h - Fix most checkpatch errors / warnings (use IS_ENABLED etc) drivers/mmc/Kconfig |9 + drivers/mmc/Makefile |1 + drivers/mmc/octeontx_hsmmc.c | 3904 ++ drivers/mmc/octeontx_hsmmc.h | 207 ++ 4 files changed, 4121 insertions(+) create mode 100644 drivers/mmc/octeontx_hsmmc.c create mode 100644 drivers/mmc/octeontx_hsmmc.h diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index ad86c232c4..ce68e68680 100644 --- a/drivers/mmc/Kconfig +++ b/drivers/mmc/Kconfig @@ -297,6 +297,15 @@ config MMC_PCI This selects PCI-based MMC controllers. If you have an MMC controller on a PCI bus, say Y here. +config MMC_OCTEONTX + bool "Marvell OcteonTX Multimedia Card Interface support" + depends on (ARCH_OCTEONTX || ARCH_OCTEONTX2) + depends on DM_MMC + help + This selects the OcteonTX Multimedia card Interface. + If you have an OcteonTX/TX2 board with a Multimedia Card slot, + say Y here. + If unsure, say N. config PXA_MMC_GENERIC diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile index e84c792999..e71297f725 100644 --- a/drivers/mmc/Makefile +++ b/drivers/mmc/Makefile @@ -36,6 +36,7 @@ obj-$(CONFIG_MVEBU_MMC) += mvebu_mmc.o obj-$(CONFIG_MMC_OMAP_HS) += omap_hsmmc.o obj-$(CONFIG_MMC_MXC) += mxcmmc.o obj-$(CONFIG_MMC_MXS) += mxsmmc.o +obj-$(CONFIG_MMC_OCTEONTX) += octeontx_hsmmc.o obj-$(CONFIG_MMC_PCI) += pci_mmc.o obj-$(CONFIG_PXA_MMC_GENERIC) += pxa_mmc_gen.o obj-$(CONFIG_$(SPL_TPL_)SUPPORT_EMMC_RPMB) += rpmb.o diff --git a/drivers/mmc/octeontx_hsmmc.c b/drivers/mmc/octeontx_hsmmc.c new file mode 100644 index 00..f8872b9739 --- /dev/null +++ b/drivers/mmc/octeontx_hsmmc.c @@ -0,0 +1,3904 @@ +// SPDX-License-Identifier:GPL-2.0 +/* + * Copyright (C) 2019 Marvell International Ltd. + * + * https://spdx.org/licenses + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include +#include +#include +#include + +#include + +#include "octeontx_hsmmc.h" + +#define MMC_TIMEOUT_SHORT 20 /* in ms */ +#define MMC_TIMEOUT_LONG 1000 +#define MMC_TIMEOUT_ERASE 1 + +#define MMC_DEFAULT_DATA_IN_TAP10 +#define MMC_DEFAULT_CMD_IN_TAP 10 +#define MMC_DEFAULT_CMD_OUT_TAP39 +#define MMC_DEFAULT_DATA_OUT_TAP 39 +#define MMC_DEFAULT_HS200_CMD_IN_TAP 24 +#define MMC_DEFAULT_HS200_DATA_IN_TAP 24 +#define MMC_DEFAULT_HS200_CMD_OUT_TAP (otx_is_soc(CN95XX) ? 10 : 5) +#define MMC_DEFAULT_HS200_DATA_OUT_TAP (otx_is_soc(CN95XX) ? 10 : 5) +#define MMC_DEFAULT_HS400_CMD_OUT_TAP (otx_is_soc(CN95XX) ? 10 : 5) +#define MMC_DEFAULT_HS400_DATA_OUT_TAP (otx_is_soc(CN95XX) ? 5 : 3) +#define MMC_DEFAULT_HS200_CMD_OUT_DLY 800 /* Delay in ps */ +#define MMC_DEFAULT_HS200_DATA_OUT_DLY 800 /* Delay in ps */ +#define MMC_DEFAULT_HS400_CMD_OUT_DLY 800 /* Delay in ps */ +#define MMC_DEFAULT_HS400_DATA_OUT_DLY 400 /* Delay in ps */ +#define MMC_DEFAULT_SD_UHS_SDR104_CMD_OUT_TAP MMC_DEFAULT_HS200_CMD_OUT_TAP +#define MMC_DEFAULT_SD_UHS_SDR104_DATA_OUT_TAP MMC_DEFAULT_HS200_DATA_OUT_TAP +#define MMC_LEGACY_DEFAULT_CMD_OUT_TAP 39 +#define MMC_LEGACY_DEFAULT_DATA_OUT_TAP39 +#define MMC_SD_LEGACY_DEFAULT_CMD_OUT_TAP 63 +#define MMC_SD_LEGACY_DEFAULT_DATA_OUT_TAP 63 +#define MMC_HS_CMD_OUT_TAP 32 +#define MMC_HS_DATA_OUT_TAP32 +#define MMC_SD_HS_CMD_OUT_TAP 26 +#define MMC_SD_HS_DATA_OUT_TAP 26 +#define MMC_SD_UHS_SDR25_CMD_OUT_TAP 26 +#define MMC_SD_UHS_SDR25_DATA_OUT_TAP 26 +#define MMC_SD_UHS_SDR50_CMD_OUT_TAP 26 +#define MMC_SD_UHS_SDR50_DATA_OUT_TAP 26 +#define MMC_DEFAULT_TAP_DELAY 4 +#define TOTAL_NO_OF_TAPS 512 +static void octeontx_mmc_switch_to(struct mmc *mmc); +static int octeontx_mmc_configure_delay(struct mmc *mmc); +static void octeontx_mmc_set_timing(struct mmc *mmc); +static void set_wdog(struct mmc *mmc, u64 us); +static void do_switch(struct mmc *mmc, union mio_emm_switch emm_switch); +static int octeontx_mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, +struct mmc_data *data); +static int octeontx2_mmc_calc_delay(struct mmc *mmc, int delay); +static int
[PATCH] Fix data abort caused by mis-aligning fit data in
Attempting to place device tree immediately after an image in memory can lead to mis-aligned data accesses if that image size is not divisible by the alignment requirements of the architecture. Data aborts caused by this were observed on a custom Marvel A388 based system, where the image was a uboot FIT file. The total size varies depending on the uboot device tree size, which does not always lead to correct alignment. Signed-off-by: Reuben Dowle --- common/spl/spl_fit.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c index 365104f..d221075 100644 --- a/common/spl/spl_fit.c +++ b/common/spl/spl_fit.c @@ -349,9 +349,9 @@ static int spl_fit_append_fdt(struct spl_image_info *spl_image, /* * Use the address following the image as target address for the -* device tree. +* device tree. Ensure that address is appropriately aligned. */ - image_info.load_addr = spl_image->load_addr + spl_image->size; + image_info.load_addr = ALIGN(spl_image->load_addr + spl_image->size, ARCH_DMA_MINALIGN); /* Figure out which device tree the board wants to use */ node = spl_fit_get_image_node(fit, images, FIT_FDT_PROP, index++); -- 2.7.4
[PATCH v4 01/17] Kconfig: Introduce CONFIG_SYS_HAS_SRAM
In order to be able to replace "#ifdef CONFIG_SYS_SRAM_BASE" sequences with the IS_ENABLED() equivalent, introduce a new boolean Kconfig option that signals whether the platform has SRAM support. Reviewed-by: Simon Glass Signed-off-by: Ovidiu Panait --- Kconfig | 11 +++ 1 file changed, 11 insertions(+) diff --git a/Kconfig b/Kconfig index 566ca72c92..934c020a2f 100644 --- a/Kconfig +++ b/Kconfig @@ -350,6 +350,17 @@ config PLATFORM_ELFENTRY default "__start" if MIPS default "_start" +config SYS_HAS_SRAM + bool + default y if TARGET_PIC32MZDASK + default y if TARGET_DEVKIT8000 + default y if TARGET_TRICORDER + default n + help + Enable this to allow support for the on board SRAM. + SRAM base address is controlled by CONFIG_SYS_SRAM_BASE. + SRAM size is controlled by CONFIG_SYS_SRAM_SIZE. + endmenu# General setup menu "Boot images" -- 2.17.1
[PATCH 4/7] rockchip: Add Engicam PX30.Core EDIMM2.2 Starter Kit
PX30.Core is an EDIMM SOM based on Rockchip PX30 from Engicam.
EDIMM2.2 Starter Kit is an EDIMM 2.2 Form Factor Capacitive
Evaluation Board from Engicam.
PX30.Core needs to mount on top of this Evaluation board for
creating complete PX30.Core EDIMM2.2 Starter Kit.
Add support for it.
Signed-off-by: Jagan Teki
---
Note:
- Linux ML link:
https://lkml.org/lkml/2020/7/23/520
arch/arm/dts/Makefile | 3 +-
arch/arm/dts/px30-px30-core-edimm2.2.dts | 21 +
arch/arm/mach-rockchip/px30/Kconfig | 6 ++
board/rockchip/evb_px30/MAINTAINERS | 6 ++
configs/px30-core-edimm2.2-px30_defconfig | 108 ++
5 files changed, 143 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/dts/px30-px30-core-edimm2.2.dts
create mode 100644 configs/px30-core-edimm2.2-px30_defconfig
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index cee10f533f..8198808ba5 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -71,7 +71,8 @@ dtb-$(CONFIG_MACH_S700) += \
dtb-$(CONFIG_ROCKCHIP_PX30) += \
px30-evb.dtb \
- px30-firefly.dtb
+ px30-firefly.dtb \
+ px30-px30-core-edimm2.2.dtb
dtb-$(CONFIG_ROCKCHIP_RK3036) += \
rk3036-sdk.dtb
diff --git a/arch/arm/dts/px30-px30-core-edimm2.2.dts
b/arch/arm/dts/px30-px30-core-edimm2.2.dts
new file mode 100644
index 00..c36280ce7f
--- /dev/null
+++ b/arch/arm/dts/px30-px30-core-edimm2.2.dts
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd
+ * Copyright (c) 2020 Engicam srl
+ * Copyright (c) 2020 Amarula Solutions(India)
+ */
+
+/dts-v1/;
+#include "px30.dtsi"
+#include "px30-engicam-edimm2.2.dtsi"
+#include "px30-px30-core.dtsi"
+
+/ {
+ model = "Engicam PX30.Core EDIMM2.2 Starter Kit";
+ compatible = "engicam,px30-core-edimm2.2", "engicam,px30-px30-core",
+"rockchip,px30";
+
+ chosen {
+ stdout-path = "serial2:115200n8";
+ };
+};
diff --git a/arch/arm/mach-rockchip/px30/Kconfig
b/arch/arm/mach-rockchip/px30/Kconfig
index 82bbc1c86f..f1fa225251 100644
--- a/arch/arm/mach-rockchip/px30/Kconfig
+++ b/arch/arm/mach-rockchip/px30/Kconfig
@@ -8,6 +8,12 @@ config TARGET_EVB_PX30
EVB_PX30:
* EVB_PX30 is an evaluation board for Rockchip PX30.
+ PX30.Core EDIMM2.2:
+ * PX30.Core is an EDIMM SOM based on Rockchip PX30 from Engicam.
+ * EDIMM2.2 is a Form Factor Capacitive Evaluation Board from Engicam.
+ * PX30.Core needs to mount on top of EDIMM2.2 for creating complete
+ PX30.Core EDIMM2.2 Starter Kit.
+
config ROCKCHIP_BOOT_MODE_REG
default 0xff010200
diff --git a/board/rockchip/evb_px30/MAINTAINERS
b/board/rockchip/evb_px30/MAINTAINERS
index 4dc060c501..48fba4e046 100644
--- a/board/rockchip/evb_px30/MAINTAINERS
+++ b/board/rockchip/evb_px30/MAINTAINERS
@@ -5,3 +5,9 @@ F: board/rockchip/evb_px30
F: include/configs/evb_px30.h
F: configs/evb-px30_defconfig
F: configs/firefly-px30_defconfig
+
+PX30-Core-EDIMM2.2
+M: Jagan Teki
+M: Suniel Mahesh
+S: Maintained
+F: configs/px30-core-edimm2.2-px30_defconfig
diff --git a/configs/px30-core-edimm2.2-px30_defconfig
b/configs/px30-core-edimm2.2-px30_defconfig
new file mode 100644
index 00..07205f0243
--- /dev/null
+++ b/configs/px30-core-edimm2.2-px30_defconfig
@@ -0,0 +1,108 @@
+CONFIG_ARM=y
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SYS_TEXT_BASE=0x0020
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SPL_TEXT_BASE=0x
+CONFIG_ROCKCHIP_PX30=y
+CONFIG_TARGET_EVB_PX30=y
+CONFIG_TPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_SPL_STACK_R_ADDR=0x60
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_DEBUG_UART_BASE=0xFF16
+CONFIG_DEBUG_UART_CLOCK=2400
+CONFIG_DEBUG_UART=y
+CONFIG_TPL_SYS_MALLOC_F_LEN=0x600
+# CONFIG_ANDROID_BOOT_IMAGE is not set
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_LOAD_FIT=y
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_DEFAULT_FDT_FILE="rockchip/px30-px30-core-edimm2.2.dtb"
+CONFIG_MISC_INIT_R=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_SPL_BOOTROM_SUPPORT=y
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_STACK_R=y
+# CONFIG_TPL_BANNER_PRINT is not set
+CONFIG_SPL_CRC32_SUPPORT=y
+CONFIG_SPL_ATF=y
+# CONFIG_TPL_FRAMEWORK is not set
+# CONFIG_CMD_BOOTD is not set
+# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_LZMADEC is not set
+# CONFIG_CMD_UNZIP is not set
+CONFIG_CMD_GPT=y
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+# CONFIG_CMD_ITEST is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_MISC is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_ISO_PARTITION is not set
[PATCH 7/7] doc: rockchip: Document Rockchip miniloader flashing
This would be useful and recommended boot flow for new boards
which has doesn't have the DDR support yet in mainline.
Sometimes it is very useful for debugging mainline DDR support.
Documen it for px30 boot flow.
Signed-off-by: Jagan Teki
---
doc/board/rockchip/rockchip.rst | 40 -
1 file changed, 39 insertions(+), 1 deletion(-)
diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst
index 8c92de0c92..ea061ad171 100644
--- a/doc/board/rockchip/rockchip.rst
+++ b/doc/board/rockchip/rockchip.rst
@@ -123,6 +123,9 @@ To build rk3399 boards::
Flashing
+1. Package the image with U-Boot TPL/SPL
+-
+
SD Card
^^^
@@ -187,6 +190,39 @@ Copy SPI boot images into SD card and boot from SD::
sf erase 0x6 +$filesize
sf write $kernel_addr_r 0x6 ${filesize}
+2. Package the image with Rockchip miniloader
+-
+
+Image package with Rockchip miniloader requires robin [1].
+
+Create idbloader.img
+
+.. code-block:: none
+
+ cd u-boot
+ ./tools/mkimage -n px30 -T rksd -d rkbin/bin/rk33/px30_ddr_333MHz_v1.15.bin
idbloader.img
+ cat rkbin/bin/rk33/px30_miniloader_v1.22.bin >> idbloader.img
+ sudo dd if=idbloader.img of=/dev/sda seek=64
+
+Create trust.img
+
+.. code-block:: none
+
+ cd rkbin
+ ./tools/trust_merger RKTRUST/PX30TRUST.ini
+ sudo dd if=trust.img of=/dev/sda seek=24576
+
+Create uboot.img
+
+.. code-block:: none
+
+ rbink/tools/loaderimage --pack --uboot u-boot-dtb.bin uboot.img 0x20
+ sudo dd if=uboot.img of=/dev/sda seek=16384
+
+Note:
+1. 0x20 is load address and it's an optional in some platforms.
+2. rkbin binaries are kept on updating, so would recommend to use the latest
versions.
+
TODO
@@ -195,5 +231,7 @@ TODO
- Document SPI flash boot
- Add missing SoC's with it boards list
+[1] https://github.com/rockchip-linux/rkbin
+
.. Jagan Teki
-.. Tuesday 02 June 2020 12:18:57 AM IST
+.. Thursday 23 July 2020 04:50:22 PM IST
--
2.25.1
[PATCH 5/7] arm: dts: rockchip: px30: Add Engicam C.TOUCH 2.0 10.1" OF
Engicam C.TOUCH 2.0 10.1" Open Frame is a Carrier board with Capacitive touch 10.1" open frame. Genaral features: - TFT 10.1" industrial, 1280x800 LVDS display - Ethernet 10/100 - Wifi/BT - USB Type A/OTG - Audio Out - CAN SOM's like PX30.Core needs to mount on top of this Carrier board for creating complete PX30.Core C.TOUCH 2.0 10.1" Open Frame. Add support for it. Signed-off-by: Jagan Teki --- Note: - Linux ML link: https://lkml.org/lkml/2020/7/23/522 arch/arm/dts/px30-engicam-ctouch2-of10.dtsi | 7 +++ 1 file changed, 7 insertions(+) create mode 100644 arch/arm/dts/px30-engicam-ctouch2-of10.dtsi diff --git a/arch/arm/dts/px30-engicam-ctouch2-of10.dtsi b/arch/arm/dts/px30-engicam-ctouch2-of10.dtsi new file mode 100644 index 00..cb00988953 --- /dev/null +++ b/arch/arm/dts/px30-engicam-ctouch2-of10.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Engicam srl + * Copyright (c) 2020 Amarula Solutions(India) + */ + +#include "px30-engicam-common.dtsi" -- 2.25.1
[PATCH 6/7] rockchip: Add Engicam PX30.Core C.TOUCH 2.0 10.1" OF
PX30.Core is an EDIMM SOM based on Rockchip PX30 from Engicam.
C.TOUCH 2.0 10.1" Open Frame is a Carrier board with Capacitive
touch 10.1" open frame from Engicam.
PX30.Core needs to mount on top of this Carrier board for creating
complete PX30.Core C.TOUCH 2.0 10.1" Open Frame.
Add support for it.
Signed-off-by: Jagan Teki
---
Note:
- Linux ML link:
https://lkml.org/lkml/2020/7/23/523
arch/arm/dts/Makefile | 1 +
arch/arm/dts/px30-px30-core-ctouch2-of10.dts | 21
arch/arm/mach-rockchip/px30/Kconfig | 7 ++
board/rockchip/evb_px30/MAINTAINERS | 6 +
configs/px30-core-ctouch2-of10-px30_defconfig | 108 ++
5 files changed, 143 insertions(+)
create mode 100644 arch/arm/dts/px30-px30-core-ctouch2-of10.dts
create mode 100644 configs/px30-core-ctouch2-of10-px30_defconfig
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 8198808ba5..270de39823 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -72,6 +72,7 @@ dtb-$(CONFIG_MACH_S700) += \
dtb-$(CONFIG_ROCKCHIP_PX30) += \
px30-evb.dtb \
px30-firefly.dtb \
+ px30-px30-core-ctouch2-of10.dtb \
px30-px30-core-edimm2.2.dtb
dtb-$(CONFIG_ROCKCHIP_RK3036) += \
diff --git a/arch/arm/dts/px30-px30-core-ctouch2-of10.dts
b/arch/arm/dts/px30-px30-core-ctouch2-of10.dts
new file mode 100644
index 00..9c957a21e3
--- /dev/null
+++ b/arch/arm/dts/px30-px30-core-ctouch2-of10.dts
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd
+ * Copyright (c) 2020 Engicam srl
+ * Copyright (c) 2020 Amarula Solutions(India)
+ */
+
+/dts-v1/;
+#include "px30.dtsi"
+#include "px30-engicam-ctouch2-of10.dtsi"
+#include "px30-px30-core.dtsi"
+
+/ {
+ model = "Engicam PX30.Core C.TOUCH 2.0 10.1\" Open Frame";
+ compatible = "engicam,px30-core-ctouch2-of10", "engicam,px30-px30-core",
+"rockchip,px30";
+
+ chosen {
+ stdout-path = "serial2:115200n8";
+ };
+};
diff --git a/arch/arm/mach-rockchip/px30/Kconfig
b/arch/arm/mach-rockchip/px30/Kconfig
index f1fa225251..21e7bbcd7f 100644
--- a/arch/arm/mach-rockchip/px30/Kconfig
+++ b/arch/arm/mach-rockchip/px30/Kconfig
@@ -14,6 +14,13 @@ config TARGET_EVB_PX30
* PX30.Core needs to mount on top of EDIMM2.2 for creating complete
PX30.Core EDIMM2.2 Starter Kit.
+ PX30.Core CTOUCH2 OF10:
+ * PX30.Core is an EDIMM SOM based on Rockchip PX30 from Engicam.
+ * CTOUCH2 OF 10 is a Carrier board with Capacitive touch 10.1"
+ Open frame from Engicam.
+ * PX30.Core needs to mount on top of CTOUCH2 OF10 for creating
complete
+ PX30.Core C.TOUCH 2.0 10.1\" Open Frame.
+
config ROCKCHIP_BOOT_MODE_REG
default 0xff010200
diff --git a/board/rockchip/evb_px30/MAINTAINERS
b/board/rockchip/evb_px30/MAINTAINERS
index 48fba4e046..459626e679 100644
--- a/board/rockchip/evb_px30/MAINTAINERS
+++ b/board/rockchip/evb_px30/MAINTAINERS
@@ -11,3 +11,9 @@ M:Jagan Teki
M: Suniel Mahesh
S: Maintained
F: configs/px30-core-edimm2.2-px30_defconfig
+
+PX30-Core-CTOUCH2-OF10
+M: Jagan Teki
+M: Suniel Mahesh
+S: Maintained
+F: configs/px30-core-ctouch2-of10-px30_defconfig
diff --git a/configs/px30-core-ctouch2-of10-px30_defconfig
b/configs/px30-core-ctouch2-of10-px30_defconfig
new file mode 100644
index 00..b87b61f740
--- /dev/null
+++ b/configs/px30-core-ctouch2-of10-px30_defconfig
@@ -0,0 +1,108 @@
+CONFIG_ARM=y
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SYS_TEXT_BASE=0x0020
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SPL_TEXT_BASE=0x
+CONFIG_ROCKCHIP_PX30=y
+CONFIG_TARGET_EVB_PX30=y
+CONFIG_TPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_SPL_STACK_R_ADDR=0x60
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_DEBUG_UART_BASE=0xFF16
+CONFIG_DEBUG_UART_CLOCK=2400
+CONFIG_DEBUG_UART=y
+CONFIG_TPL_SYS_MALLOC_F_LEN=0x600
+# CONFIG_ANDROID_BOOT_IMAGE is not set
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_LOAD_FIT=y
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_DEFAULT_FDT_FILE="rockchip/px30-px30-core-ctouch2-of10.dtb"
+CONFIG_MISC_INIT_R=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_SPL_BOOTROM_SUPPORT=y
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_STACK_R=y
+# CONFIG_TPL_BANNER_PRINT is not set
+CONFIG_SPL_CRC32_SUPPORT=y
+CONFIG_SPL_ATF=y
+# CONFIG_TPL_FRAMEWORK is not set
+# CONFIG_CMD_BOOTD is not set
+# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_LZMADEC is not set
+# CONFIG_CMD_UNZIP is not set
+CONFIG_CMD_GPT=y
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+# CONFIG_CMD_ITEST is not set
+# CONFIG_CMD_SETEXPR is not set
+#
[PATCH 3/7] rockchip: px30: Add EVB_PX30 Kconfig help
TARGET_EVB_PX30 can be possible to use other px30 boards. Add the help text for existing EVB, so-that the new boards which are resuing this config option can mention their board help text. This would help to track which boards are using EVB_PX30 config. Signed-off-by: Jagan Teki --- arch/arm/mach-rockchip/px30/Kconfig | 5 + 1 file changed, 5 insertions(+) diff --git a/arch/arm/mach-rockchip/px30/Kconfig b/arch/arm/mach-rockchip/px30/Kconfig index 9f3ad4f623..82bbc1c86f 100644 --- a/arch/arm/mach-rockchip/px30/Kconfig +++ b/arch/arm/mach-rockchip/px30/Kconfig @@ -2,6 +2,11 @@ if ROCKCHIP_PX30 config TARGET_EVB_PX30 bool "EVB_PX30" + help + This target config option used for below listed px30 boards. + + EVB_PX30: + * EVB_PX30 is an evaluation board for Rockchip PX30. config ROCKCHIP_BOOT_MODE_REG default 0xff010200 -- 2.25.1
[PATCH 2/7] arm: dts: rockchip: Add Engicam PX30.Core SOM
PX30.Core is an EDIMM SOM based on Rockchip PX30 from Engicam.
General features:
- Rockchip PX30
- Up to 2GB DDR4
- eMMC 4 GB expandible
- rest of PX30 features
PX30.Core needs to mount on top of Engicam baseboards for creating
complete platform boards.
Possible baseboards are,
- EDIMM2.2
- C.TOUCH 2.0 10.1" Open Frame
Add support for it.
Signed-off-by: Jagan Teki
---
Note:
- Linux ML link:
https://lkml.org/lkml/2020/7/23/519
arch/arm/dts/px30-px30-core.dtsi | 250 +++
1 file changed, 250 insertions(+)
create mode 100644 arch/arm/dts/px30-px30-core.dtsi
diff --git a/arch/arm/dts/px30-px30-core.dtsi b/arch/arm/dts/px30-px30-core.dtsi
new file mode 100644
index 00..26f81dbeab
--- /dev/null
+++ b/arch/arm/dts/px30-px30-core.dtsi
@@ -0,0 +1,250 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd
+ * Copyright (c) 2020 Engicam srl
+ * Copyright (c) 2020 Amarula Solutions(India)
+ */
+
+#include
+#include
+
+/ {
+ compatible = "engicam,px30-px30-core", "rockchip,px30";
+};
+
+ {
+ cpu-supply = <_arm>;
+};
+
+ {
+ cpu-supply = <_arm>;
+};
+
+ {
+ cpu-supply = <_arm>;
+};
+
+ {
+ cpu-supply = <_arm>;
+};
+
+ {
+ cap-mmc-highspeed;
+ mmc-hs200-1_8v;
+ non-removable;
+ status = "okay";
+};
+
+ {
+ clock_in_out = "output";
+ phy-supply = <_3v3>;/* +3V3_SOM */
+ snps,reset-active-low;
+ snps,reset-delays-us = <0 5 5>;
+ snps,reset-gpio = < RK_PB5 GPIO_ACTIVE_HIGH>;
+};
+
+ {
+ status = "okay";
+
+ rk809: pmic@20 {
+ compatible = "rockchip,rk809";
+ reg = <0x20>;
+ interrupt-parent = <>;
+ interrupts = ;
+ pinctrl-names = "default";
+ pinctrl-0 = <_int>;
+ rockchip,system-power-controller;
+ wakeup-source;
+ #clock-cells = <1>;
+ clock-output-names = "rk808-clkout1", "rk808-clkout2";
+
+ vcc1-supply = <_sys>;
+ vcc2-supply = <_sys>;
+ vcc3-supply = <_sys>;
+ vcc4-supply = <_sys>;
+ vcc5-supply = <_sys>;
+ vcc6-supply = <_sys>;
+ vcc7-supply = <_sys>;
+ vcc8-supply = <_sys>;
+ vcc9-supply = <_sys>;
+
+ regulators {
+ vdd_log: DCDC_REG1 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <135>;
+ regulator-min-microvolt = <95>;
+ regulator-name = "vdd_log";
+ regulator-ramp-delay = <6001>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <95>;
+ };
+ };
+
+ vdd_arm: DCDC_REG2 {
+ regulator-max-microvolt = <135>;
+ regulator-min-microvolt = <95>;
+ regulator-name = "vdd_arm";
+ regulator-ramp-delay = <6001>;
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <95>;
+ };
+ };
+
+ vcc_ddr: DCDC_REG3 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-name = "vcc_ddr";
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vcc_3v3: DCDC_REG4 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <330>;
+ regulator-min-microvolt = <330>;
+ regulator-name = "vcc_3v3";
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <330>;
+ };
+ };
+
+ vcc3v3_sys: DCDC_REG5 {
+ regulator-always-on;
+ regulator-boot-on;
+
[PATCH 1/7] arm: dts: rockchip: px30: Add Engicam EDIMM2.2 Starter Kit
Engicam EDIMM2.2 Starter Kit is an EDIMM 2.2 Form Factor Capacitive
Evaluation Board.
Genaral features:
- LCD 7" C.Touch
- microSD slot
- Ethernet 1Gb
- Wifi/BT
- 2x LVDS Full HD interfaces
- 3x USB 2.0
- 1x USB 3.0
- HDMI Out
- Mini PCIe
- MIPI CSI
- 2x CAN
- Audio Out
SOM's like PX30.Core needs to mount on top of this Evaluation board
for creating complete PX30.Core EDIMM2.2 Starter Kit.
Add support for it.
Signed-off-by: Jagan Teki
---
Note:
- Linux ML link:
https://lkml.org/lkml/2020/7/23/518
arch/arm/dts/px30-engicam-common.dtsi | 31 +
arch/arm/dts/px30-engicam-edimm2.2.dtsi | 7 ++
2 files changed, 38 insertions(+)
create mode 100644 arch/arm/dts/px30-engicam-common.dtsi
create mode 100644 arch/arm/dts/px30-engicam-edimm2.2.dtsi
diff --git a/arch/arm/dts/px30-engicam-common.dtsi
b/arch/arm/dts/px30-engicam-common.dtsi
new file mode 100644
index 00..fa0645231b
--- /dev/null
+++ b/arch/arm/dts/px30-engicam-common.dtsi
@@ -0,0 +1,31 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2020 Engicam srl
+ * Copyright (c) 2020 Amarula Solutions(India)
+ */
+
+/ {
+ vcc5v0_sys: vcc5v0-sys {
+ compatible = "regulator-fixed";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <500>;
+ regulator-max-microvolt = <500>;
+ regulator-name = "vcc5v0_sys"; /* +5V */
+ };
+};
+
+ {
+ phy-supply = <_3v3>;/* +3V3_SOM */
+ status = "okay";
+};
+
+ {
+ vmmc-supply = <_3v3>; /* +3V3_SOM */
+ status = "okay";
+};
+
+ {
+ pinctrl-0 = <_xfer>;
+ status = "okay";
+};
diff --git a/arch/arm/dts/px30-engicam-edimm2.2.dtsi
b/arch/arm/dts/px30-engicam-edimm2.2.dtsi
new file mode 100644
index 00..cb00988953
--- /dev/null
+++ b/arch/arm/dts/px30-engicam-edimm2.2.dtsi
@@ -0,0 +1,7 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2020 Engicam srl
+ * Copyright (c) 2020 Amarula Solutions(India)
+ */
+
+#include "px30-engicam-common.dtsi"
--
2.25.1
[PATCH 0/7] rockchip: Add Engicam PX30.Core support
PX30.Core is an EDIMM SOM based on Rockchip PX30 from Engicam. PX30.Core needs to mount on top of Engicam baseboards for creating complete platform boards. Possible baseboards are, - EDIMM2.2 Starter Kit - C.TOUCH 2.0 10.1" Open Frame Right now boot support is working via Rockchip miniloader, will update to U-Boot TPL once the ddr supported. Note: dts patches are in Linux mailing-list. Any inputs? Jagan. Jagan Teki (7): arm: dts: rockchip: px30: Add Engicam EDIMM2.2 Starter Kit arm: dts: rockchip: Add Engicam PX30.Core SOM rockchip: px30: Add EVB_PX30 Kconfig help rockchip: Add Engicam PX30.Core EDIMM2.2 Starter Kit arm: dts: rockchip: px30: Add Engicam C.TOUCH 2.0 10.1" OF rockchip: Add Engicam PX30.Core C.TOUCH 2.0 10.1" OF doc: rockchip: Document Rockchip miniloader flashing arch/arm/dts/Makefile | 4 +- arch/arm/dts/px30-engicam-common.dtsi | 31 +++ arch/arm/dts/px30-engicam-ctouch2-of10.dtsi | 7 + arch/arm/dts/px30-engicam-edimm2.2.dtsi | 7 + arch/arm/dts/px30-px30-core-ctouch2-of10.dts | 21 ++ arch/arm/dts/px30-px30-core-edimm2.2.dts | 21 ++ arch/arm/dts/px30-px30-core.dtsi | 250 ++ arch/arm/mach-rockchip/px30/Kconfig | 18 ++ board/rockchip/evb_px30/MAINTAINERS | 12 + configs/px30-core-ctouch2-of10-px30_defconfig | 108 configs/px30-core-edimm2.2-px30_defconfig | 108 doc/board/rockchip/rockchip.rst | 40 ++- 12 files changed, 625 insertions(+), 2 deletions(-) create mode 100644 arch/arm/dts/px30-engicam-common.dtsi create mode 100644 arch/arm/dts/px30-engicam-ctouch2-of10.dtsi create mode 100644 arch/arm/dts/px30-engicam-edimm2.2.dtsi create mode 100644 arch/arm/dts/px30-px30-core-ctouch2-of10.dts create mode 100644 arch/arm/dts/px30-px30-core-edimm2.2.dts create mode 100644 arch/arm/dts/px30-px30-core.dtsi create mode 100644 configs/px30-core-ctouch2-of10-px30_defconfig create mode 100644 configs/px30-core-edimm2.2-px30_defconfig -- 2.25.1
RE: [PATCH v4 2/6] drivers: net: add a DSA sandbox driver
>-Original Message- >From: Priyanka Jain (OSS) [...] > >Kindly fix build error for target >BUILDMAN="sandbox x86" TOOLCHAIN="i386" > >https://travis-ci.org/github/p-priyanka-jain/u-boot/jobs/711090082 > > Hi Priyanka, I will look into rebasing the patches and addressing these new found issues, unfortunately I'll be out of office for the next week. Also note that the patches are based on top of the -net tree (git.denx.de/u-boot-net.git), since they introduce networking features. But -net didn't change for a long time. Should I base the patches on another upstream tree instead? Thanks. Claudiu
Re: [PATCH 15/18] arm: dts: k3-j7200: Add dts support
On 23/07/20 3:20 pm, Faiz Abbas wrote:
> Hi Lokesh,
>
> Hi Lokesh,
>
> On 23/07/20 2:17 pm, Lokesh Vutla wrote:
>> Add the basic r5 and a72 basic dts for j7200. Following nodes were
>> supported:
>> - UART
>> - MMC SD
>> - I2C
>> - TISCI communication
>>
>> Signed-off-by: Lokesh Vutla
>> Signed-off-by: Vignesh Raghavendra
>> Signed-off-by: Vishal Mahaveer
>> Signed-off-by: Faiz Abbas
>> ---
>> arch/arm/dts/Makefile | 4 +-
>> .../k3-j7200-common-proc-board-u-boot.dtsi| 92 +
>> arch/arm/dts/k3-j7200-common-proc-board.dts | 94 ++
>> arch/arm/dts/k3-j7200-main.dtsi | 313 ++
>> arch/arm/dts/k3-j7200-mcu-wakeup.dtsi | 117 +++
>> .../arm/dts/k3-j7200-r5-common-proc-board.dts | 191 +++
>> arch/arm/dts/k3-j7200-som-p0.dtsi | 29 ++
>> arch/arm/dts/k3-j7200.dtsi| 175 ++
>> 8 files changed, 1014 insertions(+), 1 deletion(-)
>> create mode 100644 arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi
>> create mode 100644 arch/arm/dts/k3-j7200-common-proc-board.dts
>> create mode 100644 arch/arm/dts/k3-j7200-main.dtsi
>> create mode 100644 arch/arm/dts/k3-j7200-mcu-wakeup.dtsi
>> create mode 100644 arch/arm/dts/k3-j7200-r5-common-proc-board.dts
>> create mode 100644 arch/arm/dts/k3-j7200-som-p0.dtsi
>> create mode 100644 arch/arm/dts/k3-j7200.dtsi
>>
>> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
>> index cee10f533f..cdca20206f 100644
>> --- a/arch/arm/dts/Makefile
>> +++ b/arch/arm/dts/Makefile
>> @@ -938,7 +938,9 @@ dtb-$(CONFIG_STM32MP15x) += \
>>
> ...
>> +
>> +main_sdhci0: sdhci@4f8000 {
> /s/4f8000/4f8
Good catch. Will fix in v2.
>> +compatible = "ti,j7200-sdhci-8bit";
> Replace with compatible = "ti,j7200-sdhci-8bit", ti,j721e-sdhci-8bit";
No point adding just the j7200 compatible. Will use j721e for now and please
update it as in when needed.
Thanks and regards,
Lokesh
[PATCH v1 24/24] arm: octeontx2: Add support for OcteonTX2 SoC platforms
From: Suneel Garapati This patch adds support for all OcteonTX2 96xx/95xx boards from Marvell. For 96xx boards, use octeontx_96xx_defconfig and for 95xx boards, use octeontx_95xx_defconfig. Signed-off-by: Suneel Garapati Signed-off-by: Stefan Roese --- Changes in v1: - Changed patch subject - Rebased on latest TOT - Removed inclusion of common.h - Moved MEMTEST defines to Kconfig - *.c files checkpatch cleanup - Add go_uboot cmd for U-Boot starting from RAM arch/arm/Kconfig| 13 ++ arch/arm/Makefile | 1 + arch/arm/mach-octeontx2/Kconfig | 23 +++ arch/arm/mach-octeontx2/Makefile| 9 + arch/arm/mach-octeontx2/clock.c | 35 arch/arm/mach-octeontx2/config.mk | 4 + arch/arm/mach-octeontx2/cpu.c | 72 +++ arch/arm/mach-octeontx2/lowlevel_init.S | 33 board/Marvell/octeontx2/Kconfig | 14 ++ board/Marvell/octeontx2/MAINTAINERS | 8 + board/Marvell/octeontx2/Makefile| 9 + board/Marvell/octeontx2/board-fdt.c | 221 + board/Marvell/octeontx2/board.c | 247 board/Marvell/octeontx2/smc.c | 58 ++ board/Marvell/octeontx2/soc-utils.c | 49 + configs/octeontx2_95xx_defconfig| 105 ++ configs/octeontx2_96xx_defconfig| 131 + include/configs/octeontx2_common.h | 72 +++ 18 files changed, 1104 insertions(+) create mode 100644 arch/arm/mach-octeontx2/Kconfig create mode 100644 arch/arm/mach-octeontx2/Makefile create mode 100644 arch/arm/mach-octeontx2/clock.c create mode 100644 arch/arm/mach-octeontx2/config.mk create mode 100644 arch/arm/mach-octeontx2/cpu.c create mode 100644 arch/arm/mach-octeontx2/lowlevel_init.S create mode 100644 board/Marvell/octeontx2/Kconfig create mode 100644 board/Marvell/octeontx2/MAINTAINERS create mode 100644 board/Marvell/octeontx2/Makefile create mode 100644 board/Marvell/octeontx2/board-fdt.c create mode 100644 board/Marvell/octeontx2/board.c create mode 100644 board/Marvell/octeontx2/smc.c create mode 100644 board/Marvell/octeontx2/soc-utils.c create mode 100644 configs/octeontx2_95xx_defconfig create mode 100644 configs/octeontx2_96xx_defconfig create mode 100644 include/configs/octeontx2_common.h diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 886c387ac5..869d1c462b 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1722,6 +1722,15 @@ config ARCH_OCTEONTX select OF_CONTROL select BOARD_LATE_INIT select SYS_CACHE_SHIFT_7 + +config ARCH_OCTEONTX2 + bool "Support OcteonTX2 SoCs" + select DM + select ARM64 + select OF_CONTROL + select BOARD_LATE_INIT + select SYS_CACHE_SHIFT_7 + config TARGET_THUNDERX_88XX bool "Support ThunderX 88xx" select ARM64 @@ -1811,6 +1820,9 @@ source "arch/arm/mach-lpc32xx/Kconfig" source "arch/arm/mach-mvebu/Kconfig" source "arch/arm/mach-octeontx/Kconfig" + +source "arch/arm/mach-octeontx2/Kconfig" + source "arch/arm/cpu/armv7/ls102xa/Kconfig" source "arch/arm/mach-imx/mx2/Kconfig" @@ -1893,6 +1905,7 @@ source "board/CarMediaLab/flea3/Kconfig" source "board/Marvell/aspenite/Kconfig" source "board/Marvell/gplugd/Kconfig" source "board/Marvell/octeontx/Kconfig" +source "board/Marvell/octeontx2/Kconfig" source "board/armadeus/apf27/Kconfig" source "board/armltd/vexpress/Kconfig" source "board/armltd/vexpress64/Kconfig" diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 2976a3920b..5e910e12cb 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -79,6 +79,7 @@ machine-$(CONFIG_ARCH_SUNXI) += sunxi machine-$(CONFIG_ARCH_TEGRA) += tegra machine-$(CONFIG_ARCH_U8500) += u8500 machine-$(CONFIG_ARCH_OCTEONTX)+= octeontx +machine-$(CONFIG_ARCH_OCTEONTX2) += octeontx2 machine-$(CONFIG_ARCH_UNIPHIER)+= uniphier machine-$(CONFIG_ARCH_VERSAL) += versal machine-$(CONFIG_ARCH_ZYNQ)+= zynq diff --git a/arch/arm/mach-octeontx2/Kconfig b/arch/arm/mach-octeontx2/Kconfig new file mode 100644 index 00..8e5cb0f638 --- /dev/null +++ b/arch/arm/mach-octeontx2/Kconfig @@ -0,0 +1,23 @@ +if ARCH_OCTEONTX2 + +choice + prompt "OcteonTX2 board select" + optional + +config TARGET_OCTEONTX2_95XX + bool "Marvell OcteonTX2 CN95XX" + +config TARGET_OCTEONTX2_96XX + bool "Marvell OcteonTX2 CN96XX" + +endchoice + +config SYS_SOC + string + default "octeontx2" + +config SYS_PCI_64BIT + bool + default y + +endif diff --git a/arch/arm/mach-octeontx2/Makefile b/arch/arm/mach-octeontx2/Makefile new file mode 100644 index 00..c3192343dd --- /dev/null +++ b/arch/arm/mach-octeontx2/Makefile @@ -0,0 +1,9 @@ +#/* +# * Copyright (C) 2018 Marvell International Ltd. +# * +# * SPDX-License-Identifier:GPL-2.0 +# * https://spdx.org/licenses +# */ + +obj-y +=
[PATCH v1 13/24] arm: octeontx: Add headers for OcteonTX
From: Suneel Garapati
Signed-off-by: Suneel Garapati
Signed-off-by: Stefan Roese
---
Changes in v1:
- Change patch subject
arch/arm/include/asm/arch-octeontx/board.h| 123 ++
arch/arm/include/asm/arch-octeontx/clock.h| 25 +
.../asm/arch-octeontx/csrs/csrs-mio_emm.h | 1193 +
.../include/asm/arch-octeontx/csrs/csrs-xcv.h | 428 ++
arch/arm/include/asm/arch-octeontx/gpio.h |6 +
arch/arm/include/asm/arch-octeontx/smc.h | 20 +
arch/arm/include/asm/arch-octeontx/soc.h | 33 +
7 files changed, 1828 insertions(+)
create mode 100644 arch/arm/include/asm/arch-octeontx/board.h
create mode 100644 arch/arm/include/asm/arch-octeontx/clock.h
create mode 100644 arch/arm/include/asm/arch-octeontx/csrs/csrs-mio_emm.h
create mode 100644 arch/arm/include/asm/arch-octeontx/csrs/csrs-xcv.h
create mode 100644 arch/arm/include/asm/arch-octeontx/gpio.h
create mode 100644 arch/arm/include/asm/arch-octeontx/smc.h
create mode 100644 arch/arm/include/asm/arch-octeontx/soc.h
diff --git a/arch/arm/include/asm/arch-octeontx/board.h
b/arch/arm/include/asm/arch-octeontx/board.h
new file mode 100644
index 00..c9fc3993f8
--- /dev/null
+++ b/arch/arm/include/asm/arch-octeontx/board.h
@@ -0,0 +1,123 @@
+/* SPDX-License-Identifier:GPL-2.0
+ *
+ * Copyright (C) 2018 Marvell International Ltd.
+ *
+ * https://spdx.org/licenses
+ */
+
+#ifndef __BOARD_H__
+#define __BOARD_H__
+
+#include
+
+#define MAX_LMAC_PER_BGX 4
+#define LMAC_CNT MAX_LMAC_PER_BGX
+
+#if defined(CONFIG_TARGET_OCTEONTX_81XX)
+
+/** Maximum number of BGX interfaces per CPU node */
+#define MAX_BGX_PER_NODE 3
+#define OCTEONTX_XCV /* RGMII Interface */
+
+#elif defined(CONFIG_TARGET_OCTEONTX_83XX)
+
+/** Maximum number of BGX interfaces per CPU node */
+#define MAX_BGX_PER_NODE 4
+
+#endif
+
+/** Reg offsets */
+#define RST_BOOT 0x87E006001600ULL
+
+/** Structure definitions */
+
+/**
+ * Register (RSL) rst_boot
+ *
+ * RST Boot Register This register is not accessible through ROM scripts;
+ * see SCR_WRITE32_S[ADDR].
+ */
+union rst_boot {
+ u64 u;
+ struct rst_boot_s {
+ u64 rboot_pin: 1;
+ u64 rboot: 1;
+ u64 reserved_2_32: 31;
+ u64 pnr_mul : 6;
+ u64 reserved_39 : 1;
+ u64 c_mul: 7;
+ u64 reserved_47_52 : 6;
+ u64 gpio_ejtag : 1;
+ u64 mcp_jtagdis : 1;
+ u64 dis_scan : 1;
+ u64 dis_huk : 1;
+ u64 vrm_err : 1;
+ u64 jt_tstmode : 1;
+ u64 ckill_ppdis : 1;
+ u64 trusted_mode : 1;
+ u64 reserved_61_62 : 2;
+ u64 chipkill : 1;
+ } s;
+ struct rst_boot_cn81xx {
+ u64 rboot_pin: 1;
+ u64 rboot: 1;
+ u64 lboot: 10;
+ u64 lboot_ext23 : 6;
+ u64 lboot_ext45 : 6;
+ u64 lboot_jtg: 1;
+ u64 lboot_ckill : 1;
+ u64 reserved_26_29 : 4;
+ u64 lboot_oci: 3;
+ u64 pnr_mul : 6;
+ u64 reserved_39 : 1;
+ u64 c_mul: 7;
+ u64 reserved_47_54 : 8;
+ u64 dis_scan : 1;
+ u64 dis_huk : 1;
+ u64 vrm_err : 1;
+ u64 jt_tstmode : 1;
+ u64 ckill_ppdis : 1;
+ u64 trusted_mode : 1;
+ u64 ejtagdis : 1;
+ u64 jtcsrdis : 1;
+ u64 chipkill : 1;
+ } cn81xx;
+ struct rst_boot_cn83xx {
+ u64 rboot_pin: 1;
+ u64 rboot: 1;
+ u64 lboot: 10;
+ u64 lboot_ext23 : 6;
+ u64 lboot_ext45 : 6;
+ u64 lboot_jtg: 1;
+ u64 lboot_ckill : 1;
+ u64 lboot_pf_flr : 4;
+
[PATCH v1 19/24] mtd: nand: Add NAND controller driver for OcteonTX
From: Suneel Garapati
Adds support for NAND controllers found on OcteonTX or
OcteonTX2 SoC platforms. Also includes driver to support
Hardware ECC using BCH HW engine found on these platforms.
Signed-off-by: Aaron Williams
Signed-off-by: Suneel Garapati
Signed-off-by: Stefan Roese
---
Changes in v1:
- Change patch subject
drivers/mtd/nand/raw/Kconfig | 16 +
drivers/mtd/nand/raw/Makefile|2 +
drivers/mtd/nand/raw/octeontx_bch.c | 425
drivers/mtd/nand/raw/octeontx_bch.h | 133 ++
drivers/mtd/nand/raw/octeontx_bch_regs.h | 169 ++
drivers/mtd/nand/raw/octeontx_nand.c | 2263 ++
6 files changed, 3008 insertions(+)
create mode 100644 drivers/mtd/nand/raw/octeontx_bch.c
create mode 100644 drivers/mtd/nand/raw/octeontx_bch.h
create mode 100644 drivers/mtd/nand/raw/octeontx_bch_regs.h
create mode 100644 drivers/mtd/nand/raw/octeontx_nand.c
diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig
index 06b2ff972c..5d86fe470d 100644
--- a/drivers/mtd/nand/raw/Kconfig
+++ b/drivers/mtd/nand/raw/Kconfig
@@ -291,6 +291,22 @@ config NAND_ZYNQ_USE_BOOTLOADER1_TIMINGS
This flag prevent U-boot reconfigure NAND flash controller and reuse
the NAND timing from 1st stage bootloader.
+config NAND_OCTEONTX
+ bool "Support for OcteonTX NAND controller"
+ select SYS_NAND_SELF_INIT
+ imply CMD_NAND
+ help
+This enables Nand flash controller hardware found on the OcteonTX
+processors.
+
+config NAND_OCTEONTX_HW_ECC
+ bool "Support Hardware ECC for OcteonTX NAND controller"
+ depends on NAND_OCTEONTX
+ default y
+ help
+This enables Hardware BCH engine found on the OcteonTX processors to
+support ECC for NAND flash controller.
+
config NAND_STM32_FMC2
bool "Support for NAND controller on STM32MP SoCs"
depends on ARCH_STM32MP
diff --git a/drivers/mtd/nand/raw/Makefile b/drivers/mtd/nand/raw/Makefile
index 9337f6482e..24c51b6924 100644
--- a/drivers/mtd/nand/raw/Makefile
+++ b/drivers/mtd/nand/raw/Makefile
@@ -58,6 +58,8 @@ obj-$(CONFIG_NAND_VF610_NFC) += vf610_nfc.o
obj-$(CONFIG_NAND_MXC) += mxc_nand.o
obj-$(CONFIG_NAND_MXS) += mxs_nand.o
obj-$(CONFIG_NAND_MXS_DT) += mxs_nand_dt.o
+obj-$(CONFIG_NAND_OCTEONTX) += octeontx_nand.o
+obj-$(CONFIG_NAND_OCTEONTX_HW_ECC) += octeontx_bch.o
obj-$(CONFIG_NAND_PXA3XX) += pxa3xx_nand.o
obj-$(CONFIG_NAND_SPEAR) += spr_nand.o
obj-$(CONFIG_TEGRA_NAND) += tegra_nand.o
diff --git a/drivers/mtd/nand/raw/octeontx_bch.c
b/drivers/mtd/nand/raw/octeontx_bch.c
new file mode 100644
index 00..c38cbb9526
--- /dev/null
+++ b/drivers/mtd/nand/raw/octeontx_bch.c
@@ -0,0 +1,425 @@
+// SPDX-License-Identifier:GPL-2.0
+/*
+ * Copyright (C) 2018 Marvell International Ltd.
+ *
+ * https://spdx.org/licenses
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include "octeontx_bch.h"
+
+#ifdef DEBUG
+# undef CONFIG_LOGLEVEL
+# define CONFIG_LOGLEVEL 8
+#endif
+
+LIST_HEAD(octeontx_bch_devices);
+static unsigned int num_vfs = BCH_NR_VF;
+static void *bch_pf;
+static void *bch_vf;
+static void *token;
+static bool bch_pf_initialized;
+static bool bch_vf_initialized;
+
+static int pci_enable_sriov(struct udevice *dev, int nr_virtfn)
+{
+ int ret;
+
+ ret = pci_sriov_init(dev, nr_virtfn);
+ if (ret)
+ printf("%s(%s): pci_sriov_init returned %d\n", __func__,
+ dev->name, ret);
+ return ret;
+}
+
+void *octeontx_bch_getv(void)
+{
+ if (!bch_vf)
+ return NULL;
+ if (bch_vf_initialized && bch_pf_initialized)
+ return bch_vf;
+ else
+ return NULL;
+}
+
+void octeontx_bch_putv(void *token)
+{
+ bch_vf_initialized = !!token;
+ bch_vf = token;
+}
+
+void *octeontx_bch_getp(void)
+{
+ return token;
+}
+
+void octeontx_bch_putp(void *token)
+{
+ bch_pf = token;
+ bch_pf_initialized = !!token;
+}
+
+static int do_bch_init(struct bch_device *bch)
+{
+ return 0;
+}
+
+static void bch_reset(struct bch_device *bch)
+{
+ writeq(1, bch->reg_base + BCH_CTL);
+ mdelay(2);
+}
+
+static void bch_disable(struct bch_device *bch)
+{
+ writeq(~0ull, bch->reg_base + BCH_ERR_INT_ENA_W1C);
+ writeq(~0ull, bch->reg_base + BCH_ERR_INT);
+ bch_reset(bch);
+}
+
+static u32 bch_check_bist_status(struct bch_device *bch)
+{
+ return readq(bch->reg_base + BCH_BIST_RESULT);
+}
+
+static int bch_device_init(struct bch_device *bch)
+{
+ u64 bist;
+ int rc;
+
+ debug("%s: Resetting...\n", __func__);
+ /* Reset the PF when probed first */
+ bch_reset(bch);
+
+ debug("%s: Checking BIST...\n", __func__);
+ /* Check
[PATCH v1 22/24] watchdog: Add reset support for OcteonTX / TX2
From: Suneel Garapati
Adds support for Core 0 watchdog poke on OcteonTX and OcteonTX2
platforms.
Signed-off-by: Suneel Garapati
Signed-off-by: Stefan Roese
---
Changes in v1:
- Change patch subject
- Remove inclusion of common.h
- Remove global wdt_dev as its unused
- Remove #ifdef's
- Remove optional fixed register access - only use address passed via
DT while probing
- Use dev_remap_addr() instead of dev_read_addr_index()
drivers/watchdog/Kconfig| 10 ++
drivers/watchdog/Makefile | 1 +
drivers/watchdog/octeontx_wdt.c | 57 +
3 files changed, 68 insertions(+)
create mode 100644 drivers/watchdog/octeontx_wdt.c
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index bf06180cdd..981b33355d 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -139,6 +139,16 @@ config WDT_MTK
The watchdog timer is stopped when initialized.
It performs full SoC reset.
+config WDT_OCTEONTX
+ bool "OcteonTX core watchdog support"
+ depends on WDT && (ARCH_OCTEONTX || ARCH_OCTEONTX2)
+ default y if WDT && ARCH_OCTEONTX || ARCH_OCTEONTX2
+ imply WATCHDOG
+ help
+ This enables OcteonTX watchdog driver, which can be
+ found on OcteonTX/TX2 chipsets and inline with driver model.
+ Only supports watchdog reset.
+
config WDT_OMAP3
bool "TI OMAP watchdog timer support"
depends on WDT && ARCH_OMAP2PLUS
diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile
index 519bbd3a40..fbba0ca386 100644
--- a/drivers/watchdog/Makefile
+++ b/drivers/watchdog/Makefile
@@ -26,6 +26,7 @@ obj-$(CONFIG_WDT_CDNS) += cdns_wdt.o
obj-$(CONFIG_WDT_MPC8xx) += mpc8xx_wdt.o
obj-$(CONFIG_WDT_MT7621) += mt7621_wdt.o
obj-$(CONFIG_WDT_MTK) += mtk_wdt.o
+obj-$(CONFIG_WDT_OCTEONTX) += octeontx_wdt.o
obj-$(CONFIG_WDT_OMAP3) += omap_wdt.o
obj-$(CONFIG_WDT_SP805) += sp805_wdt.o
obj-$(CONFIG_WDT_STM32MP) += stm32mp_wdt.o
diff --git a/drivers/watchdog/octeontx_wdt.c b/drivers/watchdog/octeontx_wdt.c
new file mode 100644
index 00..a9c29ef26a
--- /dev/null
+++ b/drivers/watchdog/octeontx_wdt.c
@@ -0,0 +1,57 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Marvell International Ltd.
+ *
+ * https://spdx.org/licenses
+ */
+
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define CORE0_POKE_OFFSET 0x5
+
+struct octeontx_wdt {
+ void __iomem *reg;
+};
+
+static int octeontx_wdt_reset(struct udevice *dev)
+{
+ struct octeontx_wdt *priv = dev_get_priv(dev);
+
+ writeq(~0ULL, ((u64)priv->reg & ~0xfULL) | CORE0_POKE_OFFSET);
+
+ return 0;
+}
+
+static int octeontx_wdt_probe(struct udevice *dev)
+{
+ struct octeontx_wdt *priv = dev_get_priv(dev);
+
+ priv->reg = dev_remap_addr(dev);
+ if (!priv->reg)
+ return -EINVAL;
+
+ return 0;
+}
+
+static const struct wdt_ops octeontx_wdt_ops = {
+ .reset = octeontx_wdt_reset,
+};
+
+static const struct udevice_id octeontx_wdt_ids[] = {
+ { .compatible = "arm,sbsa-gwdt" },
+ {}
+};
+
+U_BOOT_DRIVER(wdt_octeontx) = {
+ .name = "wdt_octeontx",
+ .id = UCLASS_WDT,
+ .of_match = octeontx_wdt_ids,
+ .ops = _wdt_ops,
+ .priv_auto_alloc_size = sizeof(struct octeontx_wdt),
+ .probe = octeontx_wdt_probe,
+};
--
2.27.0
[PATCH v1 16/24] pci: Add PCI controller driver for OcteonTX / TX2
From: Suneel Garapati
Adds support for PCI ECAM/PEM controllers found on OcteonTX
or OcteonTX2 SoC platforms.
Signed-off-by: Suneel Garapati
Cc: Simon Glass
Cc: Bin Meng
Signed-off-by: Stefan Roese
---
Changes in v1:
- Change patch subject
- Remove inclusion of common.h
- Remove #ifdef's and use driver specific data instead
- Add comments to struct
- Add some helper functions to reduce code size
- Misc coding style changes (blank lines etc)
- Use debug() instead of printf() in some cases
drivers/pci/Kconfig| 8 +
drivers/pci/Makefile | 1 +
drivers/pci/pci_octeontx.c | 344 +
3 files changed, 353 insertions(+)
create mode 100644 drivers/pci/pci_octeontx.c
diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
index bc77c23f89..89cca6ffb3 100644
--- a/drivers/pci/Kconfig
+++ b/drivers/pci/Kconfig
@@ -149,6 +149,14 @@ config PCI_TEGRA
with a total of 5 lanes. Some boards require this for Ethernet
support to work (e.g. beaver, jetson-tk1).
+config PCI_OCTEONTX
+ bool "OcteonTX PCI support"
+ depends on (ARCH_OCTEONTX || ARCH_OCTEONTX2)
+ help
+ Enable support for the OcteonTX/TX2 SoC family ECAM/PEM controllers.
+ These controllers provide PCI configuration access to all on-board
+ peripherals so it should only be disabled for testing purposes
+
config PCI_XILINX
bool "Xilinx AXI Bridge for PCI Express"
depends on DM_PCI
diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
index 6378821aaf..0529cceee7 100644
--- a/drivers/pci/Makefile
+++ b/drivers/pci/Makefile
@@ -45,3 +45,4 @@ obj-$(CONFIG_PCI_KEYSTONE) += pcie_dw_ti.o
obj-$(CONFIG_PCIE_MEDIATEK) += pcie_mediatek.o
obj-$(CONFIG_PCIE_ROCKCHIP) += pcie_rockchip.o
obj-$(CONFIG_PCI_BRCMSTB) += pcie_brcmstb.o
+obj-$(CONFIG_PCI_OCTEONTX) += pci_octeontx.o
diff --git a/drivers/pci/pci_octeontx.c b/drivers/pci/pci_octeontx.c
new file mode 100644
index 00..5c6a6f05f2
--- /dev/null
+++ b/drivers/pci/pci_octeontx.c
@@ -0,0 +1,344 @@
+// SPDX-License-Identifier:GPL-2.0
+/*
+ * Copyright (C) 2018 Marvell International Ltd.
+ *
+ * https://spdx.org/licenses
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+enum {
+ OTX_ECAM,
+ OTX_PEM,
+ OTX2_PEM,
+};
+
+/**
+ * struct octeontx_pci - Driver private data
+ * @type: Device type matched via compatible
+ * @cfg: Config resource
+ * @bus: Bus resource
+ */
+struct octeontx_pci {
+ unsigned int type;
+
+ struct fdt_resource cfg;
+ struct fdt_resource bus;
+};
+
+static uintptr_t octeontx_cfg_addr(struct octeontx_pci *pcie,
+ int bus_offs, int shift_offs,
+ pci_dev_t bdf, uint offset)
+{
+ u32 bus, dev, func;
+ uintptr_t address;
+
+ bus = PCI_BUS(bdf) + bus_offs;
+ dev = PCI_DEV(bdf);
+ func = PCI_FUNC(bdf);
+
+ address = (bus << (20 + shift_offs)) |
+ (dev << (15 + shift_offs)) |
+ (func << (12 + shift_offs)) | offset;
+ address += pcie->cfg.start;
+
+ return address;
+}
+
+static ulong readl_size(uintptr_t addr, enum pci_size_t size)
+{
+ ulong val;
+
+ switch (size) {
+ case PCI_SIZE_8:
+ val = readb(addr);
+ break;
+ case PCI_SIZE_16:
+ val = readw(addr);
+ break;
+ case PCI_SIZE_32:
+ val = readl(addr);
+ break;
+ default:
+ printf("Invalid size\n");
+ };
+
+ return val;
+}
+
+static void writel_size(uintptr_t addr, enum pci_size_t size, ulong valuep)
+{
+ switch (size) {
+ case PCI_SIZE_8:
+ writeb(valuep, addr);
+ break;
+ case PCI_SIZE_16:
+ writew(valuep, addr);
+ break;
+ case PCI_SIZE_32:
+ writel(valuep, addr);
+ break;
+ default:
+ printf("Invalid size\n");
+ };
+}
+
+static int octeontx_ecam_read_config(const struct udevice *bus, pci_dev_t bdf,
+uint offset, ulong *valuep,
+enum pci_size_t size)
+{
+ struct octeontx_pci *pcie = (struct octeontx_pci *)dev_get_priv(bus);
+ struct pci_controller *hose = dev_get_uclass_priv(bus);
+ uintptr_t address;
+
+ address = octeontx_cfg_addr(pcie, pcie->bus.start - hose->first_busno,
+ 0, bdf, offset);
+ *valuep = readl_size(address, size);
+
+ debug("%02x.%02x.%02x: u%d %x -> %lx\n",
+ PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf), size, offset, *valuep);
+
+ return 0;
+}
+
+static int octeontx_ecam_write_config(struct udevice *bus, pci_dev_t bdf,
+ uint offset, ulong value,
+
[PATCH v1 23/24] arm: octeontx: Add support for OcteonTX SoC platforms
From: Suneel Garapati This patch adds support for all OcteonTX 81xx/83xx boards from Marvell. For 81xx boards, use octeontx_81xx_defconfig and for 83xx boards, use octeontx_83xx_defconfig. Signed-off-by: Suneel Garapati Signed-off-by: Stefan Roese --- Changes in v1: - Changed patch subject - Rebased on latest TOT - Removed inclusion of common.h - Moved MEMTEST defines to Kconfig - *.c files checkpatch cleanup arch/arm/Kconfig | 9 + arch/arm/Makefile | 1 + arch/arm/mach-octeontx/Kconfig | 23 ++ arch/arm/mach-octeontx/Makefile| 9 + arch/arm/mach-octeontx/clock.c | 35 +++ arch/arm/mach-octeontx/cpu.c | 76 ++ arch/arm/mach-octeontx/lowlevel_init.S | 33 +++ board/Marvell/octeontx/Kconfig | 14 ++ board/Marvell/octeontx/MAINTAINERS | 8 + board/Marvell/octeontx/Makefile| 9 + board/Marvell/octeontx/board-fdt.c | 311 + board/Marvell/octeontx/board.c | 152 board/Marvell/octeontx/smc.c | 25 ++ board/Marvell/octeontx/soc-utils.c | 50 configs/octeontx_81xx_defconfig| 134 +++ configs/octeontx_83xx_defconfig| 129 ++ drivers/mtd/nand/raw/octeontx_bch.c| 7 +- drivers/mtd/nand/raw/octeontx_nand.c | 11 +- drivers/net/octeontx/bgx.c | 2 +- drivers/net/octeontx/nic_main.c| 2 +- drivers/net/octeontx/nicvf_main.c | 2 +- drivers/net/octeontx/nicvf_queues.c| 2 +- drivers/net/octeontx/smi.c | 2 +- drivers/net/octeontx/xcv.c | 2 +- include/configs/octeontx_common.h | 89 +++ 25 files changed, 1123 insertions(+), 14 deletions(-) create mode 100644 arch/arm/mach-octeontx/Kconfig create mode 100644 arch/arm/mach-octeontx/Makefile create mode 100644 arch/arm/mach-octeontx/clock.c create mode 100644 arch/arm/mach-octeontx/cpu.c create mode 100644 arch/arm/mach-octeontx/lowlevel_init.S create mode 100644 board/Marvell/octeontx/Kconfig create mode 100644 board/Marvell/octeontx/MAINTAINERS create mode 100644 board/Marvell/octeontx/Makefile create mode 100644 board/Marvell/octeontx/board-fdt.c create mode 100644 board/Marvell/octeontx/board.c create mode 100644 board/Marvell/octeontx/smc.c create mode 100644 board/Marvell/octeontx/soc-utils.c create mode 100644 configs/octeontx_81xx_defconfig create mode 100644 configs/octeontx_83xx_defconfig create mode 100644 include/configs/octeontx_common.h diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index e16fe03887..886c387ac5 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1715,6 +1715,13 @@ config ARCH_ROCKCHIP imply TPL_SYSRESET imply USB_FUNCTION_FASTBOOT +config ARCH_OCTEONTX + bool "Support OcteonTX SoCs" + select DM + select ARM64 + select OF_CONTROL + select BOARD_LATE_INIT + select SYS_CACHE_SHIFT_7 config TARGET_THUNDERX_88XX bool "Support ThunderX 88xx" select ARM64 @@ -1803,6 +1810,7 @@ source "arch/arm/mach-lpc32xx/Kconfig" source "arch/arm/mach-mvebu/Kconfig" +source "arch/arm/mach-octeontx/Kconfig" source "arch/arm/cpu/armv7/ls102xa/Kconfig" source "arch/arm/mach-imx/mx2/Kconfig" @@ -1884,6 +1892,7 @@ source "board/bosch/guardian/Kconfig" source "board/CarMediaLab/flea3/Kconfig" source "board/Marvell/aspenite/Kconfig" source "board/Marvell/gplugd/Kconfig" +source "board/Marvell/octeontx/Kconfig" source "board/armadeus/apf27/Kconfig" source "board/armltd/vexpress/Kconfig" source "board/armltd/vexpress64/Kconfig" diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 94eb50bf72..2976a3920b 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -78,6 +78,7 @@ machine-$(CONFIG_ARCH_STM32MP)+= stm32mp machine-$(CONFIG_ARCH_SUNXI) += sunxi machine-$(CONFIG_ARCH_TEGRA) += tegra machine-$(CONFIG_ARCH_U8500) += u8500 +machine-$(CONFIG_ARCH_OCTEONTX)+= octeontx machine-$(CONFIG_ARCH_UNIPHIER)+= uniphier machine-$(CONFIG_ARCH_VERSAL) += versal machine-$(CONFIG_ARCH_ZYNQ)+= zynq diff --git a/arch/arm/mach-octeontx/Kconfig b/arch/arm/mach-octeontx/Kconfig new file mode 100644 index 00..28ecf9821f --- /dev/null +++ b/arch/arm/mach-octeontx/Kconfig @@ -0,0 +1,23 @@ +if ARCH_OCTEONTX + +choice + prompt "OcteonTX board select" + optional + +config TARGET_OCTEONTX_81XX + bool "Marvell OcteonTX CN81XX" + +config TARGET_OCTEONTX_83XX + bool "Marvell OcteonTX CN83XX" + +endchoice + +config SYS_SOC + string + default "octeontx" + +config SYS_PCI_64BIT + bool + default y + +endif diff --git a/arch/arm/mach-octeontx/Makefile b/arch/arm/mach-octeontx/Makefile new file mode 100644 index 00..20cb48ad92 --- /dev/null +++ b/arch/arm/mach-octeontx/Makefile @@ -0,0 +1,9 @@ +#/* SPDX-License-Identifier:
[PATCH v1 17/24] mmc: Remove static qualifier on mmc_power_init
From: Suneel Garapati
For platforms with multiple slot support like OcteonTX,
this is invoked per slot.
Signed-off-by: Suneel Garapati
Cc: Peng Fan
Signed-off-by: Stefan Roese
---
Changes in v1:
- Change patch subject
drivers/mmc/mmc.c | 2 +-
include/mmc.h | 1 +
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index f36d11ddc8..b26df59b91 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -2683,7 +2683,7 @@ __weak void board_mmc_power_init(void)
}
#endif
-static int mmc_power_init(struct mmc *mmc)
+int mmc_power_init(struct mmc *mmc)
{
#if CONFIG_IS_ENABLED(DM_MMC)
#if CONFIG_IS_ENABLED(DM_REGULATOR)
diff --git a/include/mmc.h b/include/mmc.h
index 82562193cc..e05c59713c 100644
--- a/include/mmc.h
+++ b/include/mmc.h
@@ -747,6 +747,7 @@ int mmc_unbind(struct udevice *dev);
int mmc_initialize(struct bd_info *bis);
int mmc_init_device(int num);
int mmc_init(struct mmc *mmc);
+int mmc_power_init(struct mmc *mmc);
int mmc_send_tuning(struct mmc *mmc, u32 opcode, int *cmd_error);
#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
--
2.27.0
[PATCH v1 12/24] arm: include/asm/io.h: Add 64bit clrbits and setbits helpers
From: Suneel Garapati Add 64bit API for clrbits and setbits. Signed-off-by: Suneel Garapati Reviewed-by: Simon Glass Signed-off-by: Stefan Roese --- Changes in v1: - Change patch subject - Add small commit text - Also add clr/setbits_64 (without endianess extension), which is needed for the updated Octeon device drivers arch/arm/include/asm/io.h | 16 1 file changed, 16 insertions(+) diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h index 8959749ad6..1969851c7d 100644 --- a/arch/arm/include/asm/io.h +++ b/arch/arm/include/asm/io.h @@ -176,16 +176,20 @@ static inline void __raw_readsl(unsigned long addr, void *data, int longlen) #define in_le32(a) in_arch(l,le32,a) #define in_le16(a) in_arch(w,le16,a) +#define out_be64(a,v) out_arch(l,be64,a,v) #define out_be32(a,v) out_arch(l,be32,a,v) #define out_be16(a,v) out_arch(w,be16,a,v) +#define in_be64(a) in_arch(l,be64,a) #define in_be32(a) in_arch(l,be32,a) #define in_be16(a) in_arch(w,be16,a) +#define out_64(a,v)__raw_writeq(v,a) #define out_32(a,v)__raw_writel(v,a) #define out_16(a,v)__raw_writew(v,a) #define out_8(a,v) __raw_writeb(v,a) +#define in_64(a) __raw_readq(a) #define in_32(a) __raw_readl(a) #define in_16(a) __raw_readw(a) #define in_8(a)__raw_readb(a) @@ -227,6 +231,18 @@ static inline void __raw_readsl(unsigned long addr, void *data, int longlen) #define setbits_8(addr, set) setbits(8, addr, set) #define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set) +#define clrbits_be64(addr, clear) clrbits(be64, addr, clear) +#define setbits_be64(addr, set) setbits(be64, addr, set) +#define clrsetbits_be64(addr, clear, set) clrsetbits(be64, addr, clear, set) + +#define clrbits_le64(addr, clear) clrbits(le64, addr, clear) +#define setbits_le64(addr, set) setbits(le64, addr, set) +#define clrsetbits_le64(addr, clear, set) clrsetbits(le64, addr, clear, set) + +#define clrbits_64(addr, clear) clrbits(64, addr, clear) +#define setbits_64(addr, set) setbits(64, addr, set) +#define clrsetbits_64(addr, clear, set) clrsetbits(64, addr, clear, set) + /* * Now, pick up the machine-defined IO definitions */ -- 2.27.0
[PATCH v1 15/24] ata: ahci: Add BAR index quirk for Cavium PCI SATA device
From: Suneel Garapati
For SATA controller found on OcteonTX SoC's, use non-standard PCI BAR0
instead of BAR5.
Signed-off-by: Suneel Garapati
Cc: Simon Glass
Signed-off-by: Stefan Roese
---
Changes in v1:
- Change patch subject
- Use constants from pci_ids.h instead of hardcoded values
drivers/ata/ahci.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c
index 47cdea1f58..28161b5e62 100644
--- a/drivers/ata/ahci.c
+++ b/drivers/ata/ahci.c
@@ -1198,10 +1198,18 @@ int ahci_probe_scsi(struct udevice *ahci_dev, ulong
base)
int ahci_probe_scsi_pci(struct udevice *ahci_dev)
{
ulong base;
+ u16 vendor, device;
base = (ulong)dm_pci_map_bar(ahci_dev, PCI_BASE_ADDRESS_5,
PCI_REGION_MEM);
+ dm_pci_read_config16(ahci_dev, PCI_VENDOR_ID, );
+ dm_pci_read_config16(ahci_dev, PCI_DEVICE_ID, );
+
+ if (vendor == PCI_VENDOR_ID_CAVIUM &&
+ device == PCI_DEVICE_ID_CAVIUM_SATA)
+ base = (uintptr_t)dm_pci_map_bar(ahci_dev, PCI_BASE_ADDRESS_0,
+PCI_REGION_MEM);
return ahci_probe_scsi(ahci_dev, base);
}
#endif
--
2.27.0
