[PATCH v2 8/8] mips: octeon: octeon_ebb7304_defconfig: Enable USB support
This patch enables USB support with some helpful commands, like fs support. Signed-off-by: Stefan Roese --- (no changes since v1) configs/octeon_ebb7304_defconfig | 17 + 1 file changed, 17 insertions(+) diff --git a/configs/octeon_ebb7304_defconfig b/configs/octeon_ebb7304_defconfig index 105fe5b00a..a98d73a268 100644 --- a/configs/octeon_ebb7304_defconfig +++ b/configs/octeon_ebb7304_defconfig @@ -15,12 +15,19 @@ CONFIG_HUSH_PARSER=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MTD=y +CONFIG_CMD_PART=y CONFIG_CMD_PCI=y +CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_CMD_PING=y CONFIG_CMD_TIME=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +# CONFIG_DOS_PARTITION is not set CONFIG_ENV_IS_IN_FLASH=y CONFIG_ENV_ADDR=0x1FBFE000 +CONFIG_BLK=y CONFIG_CLK=y # CONFIG_INPUT is not set CONFIG_MTD=y @@ -48,4 +55,14 @@ CONFIG_SPI=y CONFIG_OCTEON_SPI=y CONFIG_SYSRESET=y CONFIG_SYSRESET_OCTEON=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_ASIX88179=y +CONFIG_USB_ETHER_MCS7830=y +CONFIG_USB_ETHER_RTL8152=y +CONFIG_USB_ETHER_SMSC95XX=y CONFIG_HEXDUMP=y -- 2.28.0
[PATCH v2 3/8] usb: xhci: octeon: Add DWC3 glue layer for Octeon
This patch adds the glue layer for the MIPS Octeon SoCs. Its ported
mainly from the Linux code.
Signed-off-by: Stefan Roese
Cc: Bin Meng
Cc: Marek Vasut
---
(no changes since v1)
drivers/usb/host/Kconfig| 9 +
drivers/usb/host/Makefile | 1 +
drivers/usb/host/dwc3-octeon-glue.c | 396
3 files changed, 406 insertions(+)
create mode 100644 drivers/usb/host/dwc3-octeon-glue.c
diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index 1c374a7bd8..d71c12d888 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -46,6 +46,15 @@ config USB_XHCI_MVEBU
SoCs, which includes Armada8K, Armada3700 and other Armada
family SoCs.
+config USB_XHCI_OCTEON
+ bool "Support for Marvell Octeon family on-chip xHCI USB controller"
+ depends on ARCH_OCTEON
+ default y
+ help
+ Enables support for the on-chip xHCI controller on Marvell Octeon
+ family SoCs. This is a driver for the dwc3 to provide the glue logic
+ to configure the controller.
+
config USB_XHCI_PCI
bool "Support for PCI-based xHCI USB controller"
depends on DM_USB
diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
index 29d4f87e38..a12e8f2702 100644
--- a/drivers/usb/host/Makefile
+++ b/drivers/usb/host/Makefile
@@ -56,6 +56,7 @@ obj-$(CONFIG_USB_XHCI_OMAP) += xhci-omap.o
obj-$(CONFIG_USB_XHCI_PCI) += xhci-pci.o
obj-$(CONFIG_USB_XHCI_RCAR) += xhci-rcar.o
obj-$(CONFIG_USB_XHCI_STI) += dwc3-sti-glue.o
+obj-$(CONFIG_USB_XHCI_OCTEON) += dwc3-octeon-glue.o
# designware
obj-$(CONFIG_USB_DWC2) += dwc2.o
diff --git a/drivers/usb/host/dwc3-octeon-glue.c
b/drivers/usb/host/dwc3-octeon-glue.c
new file mode 100644
index 00..7b1ca7ee33
--- /dev/null
+++ b/drivers/usb/host/dwc3-octeon-glue.c
@@ -0,0 +1,396 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Octeon family DWC3 specific glue layer
+ *
+ * Copyright (C) 2020 Stefan Roese
+ *
+ * The lowlevel init code is based on the Linux driver octeon-usb.c by
+ * David Daney , which is:
+ * Copyright (C) 2010-2017 Cavium Networks
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define CVMX_GPIO_BIT_CFGX(i) (0x000107000900ull + ((i) * 8))
+#define CVMX_GPIO_XBIT_CFGX(i) (0x000107000900ull + \
+((i) & 31) * 8 - 8 * 16)
+
+#define GPIO_BIT_CFG_TX_OE BIT_ULL(0)
+#define GPIO_BIT_CFG_OUTPUT_SELGENMASK_ULL(20, 16)
+
+#define UCTL_CTL_UCTL_RST BIT_ULL(0)
+#define UCTL_CTL_UAHC_RST BIT_ULL(1)
+#define UCTL_CTL_UPHY_RST BIT_ULL(2)
+#define UCTL_CTL_DRD_MODE BIT_ULL(3)
+#define UCTL_CTL_SCLK_EN BIT_ULL(4)
+#define UCTL_CTL_HS_POWER_EN BIT_ULL(12)
+#define UCTL_CTL_SS_POWER_EN BIT_ULL(14)
+#define UCTL_CTL_H_CLKDIV_SEL GENMASK_ULL(26, 24)
+#define UCTL_CTL_H_CLKDIV_RST BIT_ULL(28)
+#define UCTL_CTL_H_CLK_EN BIT_ULL(30)
+#define UCTL_CTL_REF_CLK_FSEL GENMASK_ULL(37, 32)
+#define UCTL_CTL_REF_CLK_DIV2 BIT_ULL(38)
+#define UCTL_CTL_REF_SSP_ENBIT_ULL(39)
+#define UCTL_CTL_MPLL_MULTIPLIER GENMASK_ULL(46, 40)
+#define UCTL_CTL_SSC_ENBIT_ULL(59)
+#define UCTL_CTL_REF_CLK_SEL GENMASK_ULL(61, 60)
+
+#define UCTL_HOST_CFG 0xe0
+#define UCTL_HOST_CFG_PPC_ACTIVE_HIGH_EN BIT_ULL(24)
+#define UCTL_HOST_CFG_PPC_EN BIT_ULL(25)
+
+#define UCTL_SHIM_CFG 0xe8
+#define UCTL_SHIM_CFG_CSR_ENDIAN_MODE GENMASK_ULL(1, 0)
+#define UCTL_SHIM_CFG_DMA_ENDIAN_MODE GENMASK_ULL(9, 8)
+
+#define OCTEON_H_CLKDIV_SEL8
+#define OCTEON_MIN_H_CLK_RATE 15000
+#define OCTEON_MAX_H_CLK_RATE 3
+
+static u8 clk_div[OCTEON_H_CLKDIV_SEL] = {1, 2, 4, 6, 8, 16, 24, 32};
+
+static int dwc3_octeon_config_power(struct udevice *dev, void __iomem *base)
+{
+ u64 uctl_host_cfg;
+ u64 gpio_bit;
+ u32 gpio_pwr[3];
+ int gpio, len, power_active_low;
+ const struct device_node *node = dev_np(dev);
+ int index = ((u64)base >> 24) & 1;
+ void __iomem *gpio_bit_cfg;
+
+ if (of_find_property(node, "power", )) {
+ if (len == 12) {
+ dev_read_u32_array(dev, "power", gpio_pwr, 3);
+ power_active_low = gpio_pwr[2] & 0x01;
+ gpio = gpio_pwr[1];
+ } else if (len == 8) {
+ dev_read_u32_array(dev, "power", gpio_pwr, 2);
+ power_active_low = 0;
+ gpio = gpio_pwr[1];
+ } else {
+ printf("dwc3 controller clock init failure\n");
+ return -EINVAL;
+ }
+
+
[PATCH v2 6/8] mips: octeon: cache.c: Flush all pending writes in flush_dcache_range()
As noticed while working on the USB xHCI support, Octeon needs to flush
all pending writes so that the values are present in the memory. Add
this "syncw" instruction (twice) to flush_dcache_range().
Signed-off-by: Stefan Roese
---
(no changes since v1)
arch/mips/mach-octeon/cache.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/arch/mips/mach-octeon/cache.c b/arch/mips/mach-octeon/cache.c
index 9a88bb97c7..f293d65dae 100644
--- a/arch/mips/mach-octeon/cache.c
+++ b/arch/mips/mach-octeon/cache.c
@@ -5,14 +5,13 @@
#include
-/*
- * The Octeon platform is cache coherent and cache flushes and invalidates
- * are not needed. Define some platform specific empty flush_foo()
- * functions here to overwrite the _weak common function as a no-op.
- * This effectively disables all cache operations.
- */
+/* Octeon memory write barrier */
+#define CVMX_SYNCW asm volatile ("syncw\nsyncw\n" : : : "memory")
+
void flush_dcache_range(ulong start_addr, ulong stop)
{
+ /* Flush all pending writes */
+ CVMX_SYNCW;
}
void flush_cache(ulong start_addr, ulong size)
@@ -21,4 +20,5 @@ void flush_cache(ulong start_addr, ulong size)
void invalidate_dcache_range(ulong start_addr, ulong stop)
{
+ /* Don't need to do anything for OCTEON */
}
--
2.28.0
[PATCH v2 7/8] mips: octeon: Add USB DT nodes
Add the USB device tree nodes to the Octeon dts/dtsi files.
Signed-off-by: Stefan Roese
---
(no changes since v1)
arch/mips/dts/mrvl,cn73xx.dtsi| 58 +++
arch/mips/dts/mrvl,octeon-ebb7304.dts | 22 ++
2 files changed, 80 insertions(+)
diff --git a/arch/mips/dts/mrvl,cn73xx.dtsi b/arch/mips/dts/mrvl,cn73xx.dtsi
index 44a5a03014..1865849fe8 100644
--- a/arch/mips/dts/mrvl,cn73xx.dtsi
+++ b/arch/mips/dts/mrvl,cn73xx.dtsi
@@ -143,5 +143,63 @@
spi-max-frequency = <2500>;
clocks = < OCTEON_CLK_IO>;
};
+
+ /* USB 0 */
+ usb0: uctl@118006800 {
+ compatible = "cavium,octeon-7130-usb-uctl";
+ reg = <0x11800 0x6800 0x0 0x100>;
+ ranges; /* Direct mapping */
+ #address-cells = <2>;
+ #size-cells = <2>;
+ /* Only 100MHz allowed */
+ refclk-frequency = <1>;
+ /* Only "dlmc_ref_clk0" is supported for 73xx */
+ refclk-type-ss = "dlmc_ref_clk0";
+ /* Only "dlmc_ref_clk0" is supported for 73xx */
+ refclk-type-hs = "dlmc_ref_clk0";
+
+ /* Power is specified by three parts:
+* 1) GPIO handle (must be )
+* 2) GPIO pin number
+* 3) Active high (0) or active low (1)
+*/
+ xhci@16800 {
+ compatible =
"cavium,octeon-7130-xhci","synopsys,dwc3","snps,dwc3";
+ reg = <0x16800 0x 0x10 0x0>;
+ interrupts = <0x68080 4>; /* UAHC_IMAN, level */
+ maximum-speed = "super-speed";
+ dr_mode = "host";
+ snps,dis_u3_susphy_quirk;
+ snps,dis_u2_susphy_quirk;
+ snps,dis_enblslpm_quirk;
+ };
+ };
+
+ /* USB 1 */
+ usb1: uctl@118006900 {
+ compatible = "cavium,octeon-7130-usb-uctl";
+ reg = <0x11800 0x6900 0x0 0x100>;
+ ranges; /* Direct mapping */
+ #address-cells = <2>;
+ #size-cells = <2>;
+ /* 50MHz, 100MHz and 125MHz allowed */
+ refclk-frequency = <1>;
+ /* Either "dlmc_ref_clk0" or "dlmc_ref_clk0" */
+ refclk-type-ss = "dlmc_ref_clk0";
+ /* Either "dlmc_ref_clk0" "dlmc_ref_clk1" or
"pll_ref_clk" */
+ refclk-type-hs = "dlmc_ref_clk0";
+
+ /* Power is specified by three parts:
+* 1) GPIO handle (must be )
+* 2) GPIO pin number
+* 3) Active high (0) or active low (1)
+*/
+ xhci@16900 {
+ compatible =
"cavium,octeon-7130-xhci","synopsys,dwc3","snps,dwc3";
+ reg = <0x16900 0x 0x10 0x0>;
+ interrupts = <0x69080 4>; /* UAHC_IMAN, level */
+ dr_mode = "host";
+ };
+ };
};
};
diff --git a/arch/mips/dts/mrvl,octeon-ebb7304.dts
b/arch/mips/dts/mrvl,octeon-ebb7304.dts
index 6b2e5e84bc..cd576db478 100644
--- a/arch/mips/dts/mrvl,octeon-ebb7304.dts
+++ b/arch/mips/dts/mrvl,octeon-ebb7304.dts
@@ -113,3 +113,25 @@
reg = <0>;
};
};
+
+/* USB 0 */
+ {
+ status = "okay";
+ /* Power is specified by three parts:
+* 1) GPIO handle (must be )
+* 2) GPIO pin number
+* 3) Active high (0) or active low (1)
+*/
+ power = < 20 0>;
+};
+
+/* USB 1 */
+ {
+ status = "okay";
+ /* Power is specified by three parts:
+* 1) GPIO handle (must be )
+* 2) GPIO pin number
+* 3) Active high (0) or active low (1)
+*/
+ power = < 21 0>;
+};
--
2.28.0
[PATCH v2 2/8] usb: xhci: xhci_bulk_tx: Don't "BUG" when comparing addresses
Octeon uses mapped addresses for virtual and physical memory. Its not that easy to calculate the resulting addresses here. So lets remove this BUG_ON() completely, as its not really helpful. Please also note, that BUG_ON() is not recommended any more in the Linux kernel. Signed-off-by: Stefan Roese Cc: Bin Meng Cc: Marek Vasut --- Changes in v2: - Completely remove BUG_ON() for this trans_event.buffer check - Reword commit text drivers/usb/host/xhci-ring.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/usb/host/xhci-ring.c b/drivers/usb/host/xhci-ring.c index 092ed6eaf1..fd15f39906 100644 --- a/drivers/usb/host/xhci-ring.c +++ b/drivers/usb/host/xhci-ring.c @@ -726,8 +726,6 @@ int xhci_bulk_tx(struct usb_device *udev, unsigned long pipe, BUG_ON(TRB_TO_SLOT_ID(field) != slot_id); BUG_ON(TRB_TO_EP_INDEX(field) != ep_index); - BUG_ON(*(void **)(uintptr_t)le64_to_cpu(event->trans_event.buffer) - - buffer > (size_t)length); record_transfer_result(udev, event, length); xhci_acknowledge_event(ctrl); -- 2.28.0
[PATCH v2 4/8] mips: octeon: cpu.c: Add table for selective swapping
Import octeon_should_swizzle_table[] which is needed for the area
specific swapping. It will be used by the platform specific
mangle-port.h header.
Imported from Linux v5.7.
Signed-off-by: Stefan Roese
---
(no changes since v1)
arch/mips/mach-octeon/cpu.c | 21 +
1 file changed, 21 insertions(+)
diff --git a/arch/mips/mach-octeon/cpu.c b/arch/mips/mach-octeon/cpu.c
index 2680a2e6ed..6f87a4ef8c 100644
--- a/arch/mips/mach-octeon/cpu.c
+++ b/arch/mips/mach-octeon/cpu.c
@@ -13,6 +13,27 @@
DECLARE_GLOBAL_DATA_PTR;
+/*
+ * TRUE for devices having registers with little-endian byte
+ * order, FALSE for registers with native-endian byte order.
+ * PCI mandates little-endian, USB and SATA are configurable,
+ * but we chose little-endian for these.
+ *
+ * This table will be referened in the Octeon platform specific
+ * mangle-port.h header.
+ */
+const bool octeon_should_swizzle_table[256] = {
+ [0x00] = true, /* bootbus/CF */
+ [0x1b] = true, /* PCI mmio window */
+ [0x1c] = true, /* PCI mmio window */
+ [0x1d] = true, /* PCI mmio window */
+ [0x1e] = true, /* PCI mmio window */
+ [0x68] = true, /* OCTEON III USB */
+ [0x69] = true, /* OCTEON III USB */
+ [0x6c] = true, /* OCTEON III SATA */
+ [0x6f] = true, /* OCTEON II USB */
+};
+
static int get_clocks(void)
{
const u64 ref_clock = PLL_REF_CLK;
--
2.28.0
[PATCH v2 5/8] mips: octeon: Add mangle-port.h
Import platform specific mangle-port.h header, allowing a area specific
swapping, which is needed on Octeon for USB & PCI areas.
Imported from Linux v5.7.
Signed-off-by: Stefan Roese
---
Changes in v2:
- Only use SPDX format for license info
arch/mips/mach-octeon/include/mangle-port.h | 56 +
1 file changed, 56 insertions(+)
create mode 100644 arch/mips/mach-octeon/include/mangle-port.h
diff --git a/arch/mips/mach-octeon/include/mangle-port.h
b/arch/mips/mach-octeon/include/mangle-port.h
new file mode 100644
index 00..7e95dcef5a
--- /dev/null
+++ b/arch/mips/mach-octeon/include/mangle-port.h
@@ -0,0 +1,56 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2003, 2004 Ralf Baechle
+ */
+
+#ifndef __ASM_MACH_GENERIC_MANGLE_PORT_H
+#define __ASM_MACH_GENERIC_MANGLE_PORT_H
+
+#include
+
+#ifdef __BIG_ENDIAN
+
+static inline bool __should_swizzle_bits(volatile void *a)
+{
+ extern const bool octeon_should_swizzle_table[];
+ u64 did = ((u64)(uintptr_t)a >> 40) & 0xff;
+
+ return octeon_should_swizzle_table[did];
+}
+
+# define __swizzle_addr_b(port)(port)
+# define __swizzle_addr_w(port)(port)
+# define __swizzle_addr_l(port)(port)
+# define __swizzle_addr_q(port)(port)
+
+#else /* __LITTLE_ENDIAN */
+
+#define __should_swizzle_bits(a) false
+
+static inline bool __should_swizzle_addr(u64 p)
+{
+ /* boot bus? */
+ return ((p >> 40) & 0xff) == 0;
+}
+
+# define __swizzle_addr_b(port)\
+ (__should_swizzle_addr(port) ? (port) ^ 7 : (port))
+# define __swizzle_addr_w(port)\
+ (__should_swizzle_addr(port) ? (port) ^ 6 : (port))
+# define __swizzle_addr_l(port)\
+ (__should_swizzle_addr(port) ? (port) ^ 4 : (port))
+# define __swizzle_addr_q(port)(port)
+
+#endif /* __BIG_ENDIAN */
+
+
+# define ioswabb(a, x) (x)
+# define __mem_ioswabb(a, x) (x)
+# define ioswabw(a, x) (__should_swizzle_bits(a) ? le16_to_cpu(x) : x)
+# define __mem_ioswabw(a, x) (x)
+# define ioswabl(a, x) (__should_swizzle_bits(a) ? le32_to_cpu(x) : x)
+# define __mem_ioswabl(a, x) (x)
+# define ioswabq(a, x) (__should_swizzle_bits(a) ? le64_to_cpu(x) : x)
+# define __mem_ioswabq(a, x) (x)
+
+#endif /* __ASM_MACH_GENERIC_MANGLE_PORT_H */
--
2.28.0
[PATCH v2 0/8] mips/usb: Add Octeon xHCI USB support
This patchset adds xHCI USB support for MIPS Octeon. After the xHCI code has been fixed to support mapped addresses (virt != phys), this patchset now adds the missing code pieces to enable USB support on Octeon. This is mainly the USB glue code for Octeon and the MIPS platform specific changes (cache fixes, platform specific swapping based on address areas, DT & defcopnfig changes). Thanks, Stefan Changes in v2: - Completely remove BUG_ON() for this trans_event.buffer check - Reword commit text - Only use SPDX format for license info Stefan Roese (8): usb: xhci: xhci-dwc3.c: Use dev_remap_addr() instead of dev_get_addr() usb: xhci: xhci_bulk_tx: Don't "BUG" when comparing addresses usb: xhci: octeon: Add DWC3 glue layer for Octeon mips: octeon: cpu.c: Add table for selective swapping mips: octeon: Add mangle-port.h mips: octeon: cache.c: Flush all pending writes in flush_dcache_range() mips: octeon: Add USB DT nodes mips: octeon: octeon_ebb7304_defconfig: Enable USB support arch/mips/dts/mrvl,cn73xx.dtsi | 58 +++ arch/mips/dts/mrvl,octeon-ebb7304.dts | 22 ++ arch/mips/mach-octeon/cache.c | 12 +- arch/mips/mach-octeon/cpu.c | 21 ++ arch/mips/mach-octeon/include/mangle-port.h | 56 +++ configs/octeon_ebb7304_defconfig| 17 + drivers/usb/host/Kconfig| 9 + drivers/usb/host/Makefile | 1 + drivers/usb/host/dwc3-octeon-glue.c | 396 drivers/usb/host/xhci-dwc3.c| 2 +- drivers/usb/host/xhci-ring.c| 2 - 11 files changed, 587 insertions(+), 9 deletions(-) create mode 100644 arch/mips/mach-octeon/include/mangle-port.h create mode 100644 drivers/usb/host/dwc3-octeon-glue.c -- 2.28.0
[PATCH v2 1/8] usb: xhci: xhci-dwc3.c: Use dev_remap_addr() instead of dev_get_addr()
On MIPS platforms, mapping of the base address is needed. This patch switches from dev_get_addr() to dev_remap_addr() to get the mapped base address of the xHCI controller. Signed-off-by: Stefan Roese Cc: Bin Meng Cc: Marek Vasut --- (no changes since v1) drivers/usb/host/xhci-dwc3.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/usb/host/xhci-dwc3.c b/drivers/usb/host/xhci-dwc3.c index 27f84102db..045de2ffde 100644 --- a/drivers/usb/host/xhci-dwc3.c +++ b/drivers/usb/host/xhci-dwc3.c @@ -122,7 +122,7 @@ static int xhci_dwc3_probe(struct udevice *dev) u32 reg; int ret; - hccr = (struct xhci_hccr *)((uintptr_t)dev_read_addr(dev)); + hccr = (struct xhci_hccr *)((uintptr_t)dev_remap_addr(dev)); hcor = (struct xhci_hcor *)((uintptr_t)hccr + HC_LENGTH(xhci_readl(&(hccr)->cr_capbase))); -- 2.28.0
[PATCH v1 08/10] mips: octeon: Add bootmem support
From: Aaron Williams This is needed for Linux booting, as the memory infos need to be passed in this bootmem format to the Linux kernel. Signed-off-by: Aaron Williams Signed-off-by: Stefan Roese --- arch/mips/mach-octeon/Makefile|1 + arch/mips/mach-octeon/cvmx-bootmem.c | 1460 + .../mach-octeon/include/mach/cvmx-bootmem.h | 533 ++ 3 files changed, 1994 insertions(+) create mode 100644 arch/mips/mach-octeon/cvmx-bootmem.c create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-bootmem.h diff --git a/arch/mips/mach-octeon/Makefile b/arch/mips/mach-octeon/Makefile index 5155f89a1e..e96f0deb1b 100644 --- a/arch/mips/mach-octeon/Makefile +++ b/arch/mips/mach-octeon/Makefile @@ -9,3 +9,4 @@ obj-y += clock.o obj-y += cpu.o obj-y += dram.o obj-y += cvmx-coremask.o +obj-y += cvmx-bootmem.o diff --git a/arch/mips/mach-octeon/cvmx-bootmem.c b/arch/mips/mach-octeon/cvmx-bootmem.c new file mode 100644 index 00..80bb7ac6c8 --- /dev/null +++ b/arch/mips/mach-octeon/cvmx-bootmem.c @@ -0,0 +1,1460 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2018-2020 Marvell International Ltd. + */ + +/* + * Simple allocate only memory allocator. Used to allocate memory at + * application start time. + */ + +#include + +#include +#include +#include + +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define CVMX_MIPS32_SPACE_KSEG01L +#define CVMX_MIPS_SPACE_XKPHYS 2LL + +#define CVMX_ADD_SEG(seg, add) u64)(seg)) << 62) | (add)) +#define CVMX_ADD_SEG32(seg, add) (((u32)(seg) << 31) | (u32)(add)) + +/** + * This is the physical location of a struct cvmx_bootmem_desc + * structure in Octeon's memory. Note that dues to addressing + * limits or runtime environment it might not be possible to + * create a C pointer to this structure. + */ +static u64 cvmx_bootmem_desc_addr; + +/** + * This macro returns the size of a member of a structure. + * Logically it is the same as "sizeof(s::field)" in C++, but + * C lacks the "::" operator. + */ +#define SIZEOF_FIELD(s, field) sizeof(((s *)NULL)->field) + +/** + * This macro returns a member of the struct cvmx_bootmem_desc + * structure. These members can't be directly addressed as + * they might be in memory not directly reachable. In the case + * where bootmem is compiled with LINUX_HOST, the structure + * itself might be located on a remote Octeon. The argument + * "field" is the member name of the struct cvmx_bootmem_desc to read. + * Regardless of the type of the field, the return type is always + * a u64. + */ +#define CVMX_BOOTMEM_DESC_GET_FIELD(field) \ + __cvmx_bootmem_desc_get(cvmx_bootmem_desc_addr, \ + offsetof(struct cvmx_bootmem_desc, field), \ + SIZEOF_FIELD(struct cvmx_bootmem_desc, field)) + +/** + * This macro writes a member of the struct cvmx_bootmem_desc + * structure. These members can't be directly addressed as + * they might be in memory not directly reachable. In the case + * where bootmem is compiled with LINUX_HOST, the structure + * itself might be located on a remote Octeon. The argument + * "field" is the member name of the struct cvmx_bootmem_desc to write. + */ +#define CVMX_BOOTMEM_DESC_SET_FIELD(field, value) \ + __cvmx_bootmem_desc_set(cvmx_bootmem_desc_addr, \ + offsetof(struct cvmx_bootmem_desc, field), \ + SIZEOF_FIELD(struct cvmx_bootmem_desc, field), \ + value) + +/** + * This macro returns a member of the + * struct cvmx_bootmem_named_block_desc structure. These members can't + * be directly addressed as they might be in memory not directly + * reachable. In the case where bootmem is compiled with + * LINUX_HOST, the structure itself might be located on a remote + * Octeon. The argument "field" is the member name of the + * struct cvmx_bootmem_named_block_desc to read. Regardless of the type + * of the field, the return type is always a u64. The "addr" + * parameter is the physical address of the structure. + */ +#define CVMX_BOOTMEM_NAMED_GET_FIELD(addr, field) \ + __cvmx_bootmem_desc_get(addr, \ + offsetof(struct cvmx_bootmem_named_block_desc, field), \ + SIZEOF_FIELD(struct cvmx_bootmem_named_block_desc, field)) + +/** + * This macro writes a member of the struct cvmx_bootmem_named_block_desc + * structure. These members can't be directly addressed as + * they might be in memory not directly reachable. In the case + * where bootmem is compiled with LINUX_HOST, the structure + * itself might be located on a remote Octeon. The argument + * "field" is the member name of the + * struct cvmx_bootmem_named_block_desc to write. The "addr" parameter + * is the physical
[PATCH v1 07/10] mips: octeon: Add coremask support
From: Aaron Williams
This patch adds the coremask handling functions.
Signed-off-by: Aaron Williams
Signed-off-by: Stefan Roese
---
arch/mips/mach-octeon/Makefile| 1 +
arch/mips/mach-octeon/cvmx-coremask.c | 366 +
.../mach-octeon/include/mach/cvmx-coremask.h | 752 ++
3 files changed, 1119 insertions(+)
create mode 100644 arch/mips/mach-octeon/cvmx-coremask.c
create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-coremask.h
diff --git a/arch/mips/mach-octeon/Makefile b/arch/mips/mach-octeon/Makefile
index 2e37ca572c..5155f89a1e 100644
--- a/arch/mips/mach-octeon/Makefile
+++ b/arch/mips/mach-octeon/Makefile
@@ -8,3 +8,4 @@ obj-y += cache.o
obj-y += clock.o
obj-y += cpu.o
obj-y += dram.o
+obj-y += cvmx-coremask.o
diff --git a/arch/mips/mach-octeon/cvmx-coremask.c
b/arch/mips/mach-octeon/cvmx-coremask.c
new file mode 100644
index 00..cff8c08b97
--- /dev/null
+++ b/arch/mips/mach-octeon/cvmx-coremask.c
@@ -0,0 +1,366 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018-2020 Marvell International Ltd.
+ */
+
+#include
+#include
+
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+
+struct cvmx_coremask *get_coremask_override(struct cvmx_coremask *pcm)
+{
+ struct cvmx_coremask pcm_override = CVMX_COREMASK_MAX;
+ char *cptr;
+
+ /* The old code sets the number of cores to be to 16 in this case. */
+ cvmx_coremask_set_cores(pcm, 0, 16);
+
+ if (OCTEON_IS_OCTEON2() || OCTEON_IS_OCTEON3())
+ cvmx_coremask_copy(pcm, _override);
+
+ cptr = env_get("coremask_override");
+ if (cptr) {
+ if (cvmx_coremask_str2bmp(pcm, cptr) < 0)
+ return NULL;
+ }
+
+ return pcm;
+}
+
+/* Validate the coremask that is passed to a boot* function. */
+int validate_coremask(struct cvmx_coremask *pcm)
+{
+ struct cvmx_coremask coremask_override;
+ struct cvmx_coremask fuse_coremask;
+
+ if (!get_coremask_override(_override))
+ return -1;
+
+ octeon_get_available_coremask(_coremask);
+
+ if (!cvmx_coremask_is_subset(_coremask, pcm)) {
+ puts("ERROR: Can't boot cores that don't exist!\n");
+ puts("Available coremask:\n");
+ cvmx_coremask_print(_coremask);
+ return -1;
+ }
+
+ if (!cvmx_coremask_is_subset(_override, pcm)) {
+ struct cvmx_coremask print_cm;
+
+ puts("Notice: coremask changed from:\n");
+ cvmx_coremask_print(pcm);
+ puts("based on coremask_override of:\n");
+ cvmx_coremask_print(_override);
+ cvmx_coremask_and(_cm, pcm, _override);
+ puts("to:\n");
+ cvmx_coremask_print(_cm);
+ }
+
+ return 0;
+}
+
+/**
+ * In CIU_FUSE for the 78XX, odd and even cores are separated out.
+ * For example, a CIU_FUSE value of 0xfefe indicates that bits 0 and 1
+ * are set.
+ * This function converts the bit number in the CIU_FUSE register to a
+ * physical core number.
+ */
+static int convert_ciu_fuse_to_physical_core(int core, int max_cores)
+{
+ if (!octeon_has_feature(OCTEON_FEATURE_CIU3))
+ return core;
+ else if (!OCTEON_IS_MODEL(OCTEON_CN78XX))
+ return core;
+ else if (core < (max_cores / 2))
+ return core * 2;
+ else
+ return ((core - (max_cores / 2)) * 2) + 1;
+}
+
+/**
+ * Get the total number of fuses blown as well as the number blown per tad.
+ *
+ * @param coremaskfuse coremask
+ * @param[out] tad_blown_count number of cores blown for each tad
+ * @param num_tadsnumber of tads
+ * @param max_cores maximum number of cores
+ *
+ * @return void
+ */
+void fill_tad_corecount(u64 coremask, int tad_blown_count[], int num_tads,
+ int max_cores)
+{
+ int core, physical_core;
+
+ for (core = 0; core < max_cores; core++) {
+ if (!(coremask & (1ULL << core))) {
+ int tad;
+
+ physical_core =
+ convert_ciu_fuse_to_physical_core(core,
+ max_cores);
+ tad = physical_core % num_tads;
+ tad_blown_count[tad]++;
+ }
+ }
+}
+
+u64 get_core_pattern(int num_tads, int max_cores)
+{
+ u64 pattern = 1ULL;
+ int cnt;
+
+ for (cnt = 1; cnt < (max_cores / num_tads); cnt++)
+ pattern |= pattern << num_tads;
+
+ return pattern;
+}
+
+/**
+ * For CN78XX and CN68XX this function returns the logical coremask from the
+ * CIU_FUSE register value. For other models there is no difference.
+ *
+ * @param ciu_fuse_value fuse value from CIU_FUSE register
+ * @return logical coremask of CIU_FUSE
[PATCH v1 04/10] mips: octeon: Add header octeon-feature.h
From: Aaron Williams
This header includes the Octeon feature detection used in many Octeon
drivers.
Signed-off-by: Aaron Williams
Signed-off-by: Stefan Roese
---
.../mach-octeon/include/mach/octeon-feature.h | 442 ++
1 file changed, 442 insertions(+)
create mode 100644 arch/mips/mach-octeon/include/mach/octeon-feature.h
diff --git a/arch/mips/mach-octeon/include/mach/octeon-feature.h
b/arch/mips/mach-octeon/include/mach/octeon-feature.h
new file mode 100644
index 00..1202716ba5
--- /dev/null
+++ b/arch/mips/mach-octeon/include/mach/octeon-feature.h
@@ -0,0 +1,442 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2020 Marvell International Ltd.
+ */
+
+#ifndef __OCTEON_FEATURE_H__
+#define __OCTEON_FEATURE_H__
+
+/*
+ * Octeon models are declared after the macros in octeon-model.h with the
+ * suffix _FEATURE. The individual features are declared with the
+ * _FEATURE_ infix.
+ */
+enum octeon_feature {
+ /*
+* Checks on the critical path are moved to the top (8 positions)
+* so that the compiler generates one less insn than for the rest
+* of the checks.
+*/
+ OCTEON_FEATURE_PKND, /* CN68XX uses port kinds for packet interface */
+ /* CN68XX has different fields in word0 - word2 */
+ OCTEON_FEATURE_CN68XX_WQE,
+
+ /*
+* Features
+*/
+ /*
+* Octeon models in the CN5XXX family and higher support atomic
+* add instructions to memory (saa/saad)
+*/
+ OCTEON_FEATURE_SAAD,
+ /* Does this Octeon support the ZIP offload engine? */
+ OCTEON_FEATURE_ZIP,
+ /* Does this Octeon support crypto acceleration using COP2? */
+ OCTEON_FEATURE_CRYPTO,
+ /* Can crypto be enabled by calling cvmx_crypto_dormant_enable()? */
+ OCTEON_FEATURE_DORM_CRYPTO,
+ OCTEON_FEATURE_PCIE,/* Does this Octeon support PCI express? */
+ OCTEON_FEATURE_SRIO,/* Does this Octeon support SRIO */
+ OCTEON_FEATURE_ILK, /* Does this Octeon support Interlaken */
+ /*
+* Some Octeon models support internal memory for storing
+* cryptographic keys
+*/
+ OCTEON_FEATURE_KEY_MEMORY,
+ /* Octeon has a LED controller for banks of external LEDs */
+ OCTEON_FEATURE_LED_CONTROLLER,
+ OCTEON_FEATURE_TRA, /* Octeon has a trace buffer */
+ OCTEON_FEATURE_MGMT_PORT, /* Octeon has a management port */
+ OCTEON_FEATURE_RAID,/* Octeon has a raid unit */
+ OCTEON_FEATURE_USB, /* Octeon has a builtin USB */
+ /* Octeon IPD can run without using work queue entries */
+ OCTEON_FEATURE_NO_WPTR,
+ OCTEON_FEATURE_DFA, /* Octeon has DFA state machines */
+ /*
+* Octeon MDIO block supports clause 45 transactions for
+* 10 Gig support
+*/
+ OCTEON_FEATURE_MDIO_CLAUSE_45,
+ /*
+* CN52XX and CN56XX used a block named NPEI for PCIe access.
+* Newer chips replaced this with SLI+DPI
+*/
+ OCTEON_FEATURE_NPEI,
+ OCTEON_FEATURE_HFA, /* Octeon has DFA/HFA */
+ OCTEON_FEATURE_DFM, /* Octeon has DFM */
+ OCTEON_FEATURE_CIU2,/* Octeon has CIU2 */
+ /* Octeon has DMA Instruction Completion Interrupt mode */
+ OCTEON_FEATURE_DICI_MODE,
+ /* Octeon has Bit Select Extractor schedulor */
+ OCTEON_FEATURE_BIT_EXTRACTOR,
+ OCTEON_FEATURE_NAND,/* Octeon has NAND */
+ OCTEON_FEATURE_MMC, /* Octeon has built-in MMC support */
+ OCTEON_FEATURE_ROM, /* Octeon has built-in ROM support */
+ OCTEON_FEATURE_AUTHENTIK, /* Octeon has Authentik ROM support */
+ OCTEON_FEATURE_MULTICAST_TIMER, /* Octeon has multi_cast timer */
+ OCTEON_FEATURE_MULTINODE, /* Octeon has node support */
+ OCTEON_FEATURE_CIU3,/* Octeon has CIU3 */
+ OCTEON_FEATURE_FPA3,/* Octeon has FPA first seen on 78XX */
+ /* CN78XX has different fields in word0 - word2 */
+ OCTEON_FEATURE_CN78XX_WQE,
+ OCTEON_FEATURE_PKO3,/* Octeon has enhanced PKO block */
+ OCTEON_FEATURE_SPI, /* Octeon supports SPI interfaces */
+ OCTEON_FEATURE_ZIP3,/* Octeon has zip first seen on 78XX */
+ OCTEON_FEATURE_BCH, /* Octeon supports BCH ECC */
+ OCTEON_FEATURE_PKI, /* Octeon has PKI block */
+ OCTEON_FEATURE_OCLA,/* Octeon has OCLA */
+ OCTEON_FEATURE_FAU, /* Octeon has FAU */
+ OCTEON_FEATURE_BGX, /* Octeon has BGX */
+ OCTEON_FEATURE_BGX_MIX, /* On of the BGX is used for MIX */
+ OCTEON_FEATURE_HNA, /* Octeon has HNA */
+ OCTEON_FEATURE_BGX_XCV, /* Octeon has BGX XCV RGMII support */
+ OCTEON_FEATURE_TSO, /* Octeon has tcp segmentation offload */
+ OCTEON_FEATURE_TDM, /* Octeon has PCM/TDM support */
+ OCTEON_FEATURE_PTP, /* Octeon has PTP support */
+ OCTEON_MAX_FEATURE
+};
+
+static
[PATCH v1 09/10] mips: octeon: Add bootoctlinux command
From: Aaron Williams
Octeon needs a platform specific cmd to boot the Linux kernel, as
specific parameters need to be passed and special handling for the
multiple cores (SMP) is needed.
Co-developed-by: Stefan Roese
Signed-off-by: Aaron Williams
Signed-off-by: Stefan Roese
---
arch/mips/mach-octeon/Makefile| 1 +
arch/mips/mach-octeon/bootoctlinux.c | 661 ++
.../mach-octeon/include/mach/bootoct_cmd.h| 54 ++
3 files changed, 716 insertions(+)
create mode 100644 arch/mips/mach-octeon/bootoctlinux.c
create mode 100644 arch/mips/mach-octeon/include/mach/bootoct_cmd.h
diff --git a/arch/mips/mach-octeon/Makefile b/arch/mips/mach-octeon/Makefile
index e96f0deb1b..3486aa9d8b 100644
--- a/arch/mips/mach-octeon/Makefile
+++ b/arch/mips/mach-octeon/Makefile
@@ -10,3 +10,4 @@ obj-y += cpu.o
obj-y += dram.o
obj-y += cvmx-coremask.o
obj-y += cvmx-bootmem.o
+obj-y += bootoctlinux.o
diff --git a/arch/mips/mach-octeon/bootoctlinux.c
b/arch/mips/mach-octeon/bootoctlinux.c
new file mode 100644
index 00..af69808ce8
--- /dev/null
+++ b/arch/mips/mach-octeon/bootoctlinux.c
@@ -0,0 +1,661 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2020 Stefan Roese
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* ToDo: Revisit these settings */
+#define OCTEON_RESERVED_LOW_MEM_SIZE (512 * 1024)
+#define OCTEON_RESERVED_LOW_BOOT_MEM_SIZE (1024 * 1024)
+#define BOOTLOADER_BOOTMEM_DESC_SPACE (1024 * 1024)
+
+/* Default stack and heap sizes, in bytes */
+#define DEFAULT_STACK_SIZE (1 * 1024 * 1024)
+#define DEFAULT_HEAP_SIZE (3 * 1024 * 1024)
+
+/**
+ * NOTE: This must duplicate octeon_boot_descriptor_t in the toolchain
+ * octeon-app-init.h file.
+ */
+enum {
+ /* If set, core should do app-wide init, only one core per app will have
+* this flag set.
+*/
+ BOOT_FLAG_INIT_CORE = 1,
+ OCTEON_BL_FLAG_DEBUG= 1 << 1,
+ OCTEON_BL_FLAG_NO_MAGIC = 1 << 2,
+ /* If set, use uart1 for console */
+ OCTEON_BL_FLAG_CONSOLE_UART1 = 1 << 3,
+ OCTEON_BL_FLAG_CONSOLE_PCI = 1 << 4,/* If set, use PCI console */
+ /* Call exit on break on serial port */
+ OCTEON_BL_FLAG_BREAK= 1 << 5,
+ /*
+* Be sure to update OCTEON_APP_INIT_H_VERSION when new fields are added
+* and to conditionalize the new flag's usage based on the version.
+*/
+} octeon_boot_descriptor_flag;
+
+/**
+ * NOTE: This must duplicate octeon_boot_descriptor_t in the toolchain
+ * octeon-app-init.h file.
+ */
+#ifndef OCTEON_CURRENT_DESC_VERSION
+# define OCTEON_CURRENT_DESC_VERSION 7
+#endif
+/**
+ * NOTE: This must duplicate octeon_boot_descriptor_t in the toolchain
+ * octeon-app-init.h file.
+ */
+/* Version 7 changes: Change names of deprecated fields */
+#ifndef OCTEON_ARGV_MAX_ARGS
+# define OCTEON_ARGV_MAX_ARGS 64
+#endif
+
+/**
+ * NOTE: This must duplicate octeon_boot_descriptor_t in the toolchain
+ * octeon-app-init.h file.
+ */
+#ifndef OCTEON_SERIAL_LEN
+# define OCTEON_SERIAL_LEN 20
+#endif
+
+/**
+ * Bootloader structure used to pass info to Octeon executive startup code.
+ * NOTE: all fields are deprecated except for:
+ * * desc_version
+ * * desc_size,
+ * * heap_base
+ * * heap_end
+ * * eclock_hz
+ * * flags
+ * * argc
+ * * argv
+ * * cvmx_desc_vaddr
+ * * debugger_flags_base_addr
+ *
+ * All other fields have been moved to the cvmx_descriptor, and the new
+ * fields should be added there. They are left as placeholders in this
+ * structure for binary compatibility.
+ *
+ * NOTE: This structure must match what is in the toolchain octeon-app-init.h
+ * file.
+ */
+struct octeon_boot_descriptor {
+ /* Start of block referenced by assembly code - do not change! */
+ u32 desc_version;
+ u32 desc_size;
+ u64 stack_top;
+ u64 heap_base;
+ u64 heap_end;
+ u64 deprecated17;
+ u64 deprecated16;
+ /* End of block referenced by assembly code - do not change! */
+ u32 deprecated18;
+ u32 deprecated15;
+ u32 deprecated14;
+ u32 argc; /* argc for main() */
+ u32 argv[OCTEON_ARGV_MAX_ARGS]; /* argv for main() */
+ u32 flags; /* Flags for application */
+ u32 core_mask; /* Coremask running this image */
+ u32 dram_size; /* DEPRECATED, DRAM size in megabyes. Used up to SDK
1.8.1 */
+ u32 phy_mem_desc_addr;
+ u32 debugger_flags_base_addr; /* used to pass flags from app to
debugger. */
+ u32 eclock_hz; /* CPU clock speed, in hz. */
+ u32 deprecated10;
+ u32 deprecated9;
+ u16 deprecated8;
+ u8 deprecated7;
+ u8 deprecated6;
+
[PATCH v1 10/10] mips: octeon: octeon_common.h: Increase CONFIG_SYS_BOOTM_LEN
Increase CONFIG_SYS_BOOTM_LEN to 64MiB for Linux kernel booting. Signed-off-by: Stefan Roese --- include/configs/octeon_common.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/configs/octeon_common.h b/include/configs/octeon_common.h index 541b81801e..109ef4064d 100644 --- a/include/configs/octeon_common.h +++ b/include/configs/octeon_common.h @@ -21,4 +21,6 @@ #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + (1 << 20)) +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ + #endif /* __OCTEON_COMMON_H__ */ -- 2.28.0
[PATCH v1 06/10] mips: octeon: Add header cvmx-bootinfo.h
From: Aaron Williams
Add header to handle bootinfo support, needed for Octeon Linux kernel
booting.
Signed-off-by: Aaron Williams
Signed-off-by: Stefan Roese
---
.../mach-octeon/include/mach/cvmx-bootinfo.h | 350 ++
1 file changed, 350 insertions(+)
create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-bootinfo.h
diff --git a/arch/mips/mach-octeon/include/mach/cvmx-bootinfo.h
b/arch/mips/mach-octeon/include/mach/cvmx-bootinfo.h
new file mode 100644
index 00..337987178f
--- /dev/null
+++ b/arch/mips/mach-octeon/include/mach/cvmx-bootinfo.h
@@ -0,0 +1,350 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2020 Marvell International Ltd.
+ */
+
+/*
+ * Header file containing the ABI with the bootloader.
+ */
+
+#ifndef __CVMX_BOOTINFO_H__
+#define __CVMX_BOOTINFO_H__
+
+#include "cvmx-coremask.h"
+
+/*
+ * Current major and minor versions of the CVMX bootinfo block that is
+ * passed from the bootloader to the application. This is versioned
+ * so that applications can properly handle multiple bootloader
+ * versions.
+ */
+#define CVMX_BOOTINFO_MAJ_VER 1
+#define CVMX_BOOTINFO_MIN_VER 4
+
+#if (CVMX_BOOTINFO_MAJ_VER == 1)
+#define CVMX_BOOTINFO_OCTEON_SERIAL_LEN 20
+/*
+ * This structure is populated by the bootloader. For binary
+ * compatibility the only changes that should be made are
+ * adding members to the end of the structure, and the minor
+ * version should be incremented at that time.
+ * If an incompatible change is made, the major version
+ * must be incremented, and the minor version should be reset
+ * to 0.
+ */
+struct cvmx_bootinfo {
+ u32 major_version;
+ u32 minor_version;
+
+ u64 stack_top;
+ u64 heap_base;
+ u64 heap_end;
+ u64 desc_vaddr;
+
+ u32 exception_base_addr;
+ u32 stack_size;
+ u32 flags;
+ u32 core_mask;
+ /* DRAM size in megabytes */
+ u32 dram_size;
+ /* physical address of free memory descriptor block*/
+ u32 phy_mem_desc_addr;
+ /* used to pass flags from app to debugger */
+ u32 debugger_flags_base_addr;
+
+ /* CPU clock speed, in hz */
+ u32 eclock_hz;
+
+ /* DRAM clock speed, in hz */
+ u32 dclock_hz;
+
+ u32 reserved0;
+ u16 board_type;
+ u8 board_rev_major;
+ u8 board_rev_minor;
+ u16 reserved1;
+ u8 reserved2;
+ u8 reserved3;
+ char board_serial_number[CVMX_BOOTINFO_OCTEON_SERIAL_LEN];
+ u8 mac_addr_base[6];
+ u8 mac_addr_count;
+#if (CVMX_BOOTINFO_MIN_VER >= 1)
+ /*
+* Several boards support compact flash on the Octeon boot
+* bus. The CF memory spaces may be mapped to different
+* addresses on different boards. These are the physical
+* addresses, so care must be taken to use the correct
+* XKPHYS/KSEG0 addressing depending on the application's
+* ABI. These values will be 0 if CF is not present.
+*/
+ u64 compact_flash_common_base_addr;
+ u64 compact_flash_attribute_base_addr;
+ /*
+* Base address of the LED display (as on EBT3000 board)
+* This will be 0 if LED display not present.
+*/
+ u64 led_display_base_addr;
+#endif
+#if (CVMX_BOOTINFO_MIN_VER >= 2)
+ /* DFA reference clock in hz (if applicable)*/
+ u32 dfa_ref_clock_hz;
+
+ /*
+* flags indicating various configuration options. These
+* flags supercede the 'flags' variable and should be used
+* instead if available.
+*/
+ u32 config_flags;
+#endif
+#if (CVMX_BOOTINFO_MIN_VER >= 3)
+ /*
+* Address of the OF Flattened Device Tree structure
+* describing the board.
+*/
+ u64 fdt_addr;
+#endif
+#if (CVMX_BOOTINFO_MIN_VER >= 4)
+ /*
+* Coremask used for processors with more than 32 cores
+* or with OCI. This replaces core_mask.
+*/
+ struct cvmx_coremask ext_core_mask;
+#endif
+};
+
+#define CVMX_BOOTINFO_CFG_FLAG_PCI_HOST(1ull << 0)
+#define CVMX_BOOTINFO_CFG_FLAG_PCI_TARGET (1ull << 1)
+#define CVMX_BOOTINFO_CFG_FLAG_DEBUG (1ull << 2)
+#define CVMX_BOOTINFO_CFG_FLAG_NO_MAGIC(1ull << 3)
+/*
+ * This flag is set if the TLB mappings are not contained in the
+ * 0x1000 - 0x2000 boot bus region.
+ */
+#define CVMX_BOOTINFO_CFG_FLAG_OVERSIZE_TLB_MAPPING(1ull << 4)
+#define CVMX_BOOTINFO_CFG_FLAG_BREAK (1ull << 5)
+
+#endif /* (CVMX_BOOTINFO_MAJ_VER == 1) */
+
+/* Type defines for board and chip types */
+enum cvmx_board_types_enum {
+ CVMX_BOARD_TYPE_NULL = 0,
+ CVMX_BOARD_TYPE_SIM = 1,
+ CVMX_BOARD_TYPE_EBT3000 = 2,
+ CVMX_BOARD_TYPE_KODAMA = 3,
+ CVMX_BOARD_TYPE_NIAGARA = 4,
+ CVMX_BOARD_TYPE_NAC38 = 5, /* formerly NAO38 */
+ CVMX_BOARD_TYPE_THUNDER = 6,
+ CVMX_BOARD_TYPE_TRANTOR
[PATCH v1 02/10] mips: octeon: lowlevel_init.S: Add NMI handling code for SMP Linux booting
This patch adds the necessary lowlevel init code, to enable SMP Linux booting. This code will be used with the platform specific Octeon Linux boot command "bootoctlinux", which starts a configurable number of cores into Linux. Additionally some erratas and lowlevel register initializations are copied from the original Cavium / Marvell U-Boot source code, enabling booting into the Linux kernel. Signed-off-by: Stefan Roese --- arch/mips/mach-octeon/lowlevel_init.S | 76 +++ 1 file changed, 76 insertions(+) diff --git a/arch/mips/mach-octeon/lowlevel_init.S b/arch/mips/mach-octeon/lowlevel_init.S index fa87cb4e34..56d1d2261e 100644 --- a/arch/mips/mach-octeon/lowlevel_init.S +++ b/arch/mips/mach-octeon/lowlevel_init.S @@ -10,10 +10,36 @@ #include #include #include +#include + +#define COP0_CVMCTL_REG$9,7/* Cavium control */ +#define COP0_CVMMEMCTL_REG $11,7 /* Cavium memory control */ +#define COP0_PROC_ID_REG $15,0 .set noreorder LEAF(lowlevel_init) + + /* Set LMEMSZ in CVMMEMCTL register */ + dmfc0 a0, COP0_CVMMEMCTL_REG + dinsa0, zero, 0, 9 + mfc0a4, COP0_PROC_ID_REG + li a5, OCTEON_CN63XX_PASS1_0 /* Octeon cn63xx pass1 chip id */ + bgt a5, a4, 2f +ori a0, 0x104 /* setup 4 lines of scratch */ + ori a6, a5, 8 /* Octeon cn63xx pass2 chip id */ + bge a4, a6, 2f +nop + li a6, 4 + ins a0, a6, 11, 4 /* Set WBTHRESH=4 as per Core-14752 errata */ +2: + dmtc0 a0, COP0_CVMMEMCTL_REG + + /* Set REPUN bit in CVMCTL register */ + dmfc0 a0, COP0_CVMCTL_REG + ori a0, 1<<14 /* enable fixup of unaligned mem access */ + dmtc0 a0, COP0_CVMCTL_REG + jr ra nop END(lowlevel_init) @@ -67,3 +93,53 @@ __dummy: nop END(mips_mach_early_init) + +LEAF(nmi_bootvector) + + /* +* From Marvell original bootvector setup +*/ + mfc0k0, CP0_STATUS + /* Enable 64-bit addressing, set ERL (should already be set) */ + ori k0, 0x84 + mtc0k0, CP0_STATUS + /* Core-14345, clear L1 Dcache virtual tags if the core hit an NMI */ + cache 17, 0($0) + + /* +* Needed for Linux kernel booting, otherwise it hangs while +* zero'ing all of CVMSEG +*/ + dmfc0 a0, COP0_CVMMEMCTL_REG + dinsa0, zero, 0, 9 + ori a0, 0x104 /* setup 4 lines of scratch */ + dmtc0 a0, COP0_CVMMEMCTL_REG + + /* +* Load parameters and entry point +*/ + PTR_LA t9, nmi_handler_para + sync + + ld s0, 0x00(t9) + ld a0, 0x08(t9) + ld a1, 0x10(t9) + ld a2, 0x18(t9) + ld a3, 0x20(t9) + + /* Finally jump to entry point (start kernel etc) */ + j s0 +nop + + END(nmi_bootvector) + + /* +* Add here some space for the NMI parameters (entry point and args) +*/ + .globl nmi_handler_para +nmi_handler_para: + .dword 0 // entry-point + .dword 0 // arg0 + .dword 0 // arg1 + .dword 0 // arg2 + .dword 0 // arg3 -- 2.28.0
[PATCH v1 05/10] mips: octeon: Add header cvmx-fuse.h
From: Aaron Williams
Add header to handle Octeon fuse access.
Signed-off-by: Aaron Williams
Signed-off-by: Stefan Roese
---
.../mips/mach-octeon/include/mach/cvmx-fuse.h | 71 +++
1 file changed, 71 insertions(+)
create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-fuse.h
diff --git a/arch/mips/mach-octeon/include/mach/cvmx-fuse.h
b/arch/mips/mach-octeon/include/mach/cvmx-fuse.h
new file mode 100644
index 00..a06a1326cb
--- /dev/null
+++ b/arch/mips/mach-octeon/include/mach/cvmx-fuse.h
@@ -0,0 +1,71 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2020 Marvell International Ltd.
+ */
+
+#ifndef __CVMX_FUSE_H__
+#define __CVMX_FUSE_H__
+
+/**
+ * Read a byte of fuse data
+ * @param node node to read from
+ * @param byte_addraddress to read
+ *
+ * @return fuse value: 0 or 1
+ */
+static inline u8 cvmx_fuse_read_byte_node(u8 node, int byte_addr)
+{
+ u64 val;
+
+ val = FIELD_PREP(MIO_FUS_RCMD_ADDR, byte_addr) | MIO_FUS_RCMD_PEND;
+ csr_wr_node(node, CVMX_MIO_FUS_RCMD, val);
+
+ do {
+ val = csr_rd_node(node, CVMX_MIO_FUS_RCMD);
+ } while (val & MIO_FUS_RCMD_PEND);
+
+ return FIELD_GET(MIO_FUS_RCMD_DAT, val);
+}
+
+/**
+ * Read a byte of fuse data
+ * @param byte_addr address to read
+ *
+ * @return fuse value: 0 or 1
+ */
+static inline u8 cvmx_fuse_read_byte(int byte_addr)
+{
+ return cvmx_fuse_read_byte_node(0, byte_addr);
+}
+
+/**
+ * Read a single fuse bit
+ *
+ * @param node Node number
+ * @param fuse Fuse number (0-1024)
+ *
+ * @return fuse value: 0 or 1
+ */
+static inline int cvmx_fuse_read_node(u8 node, int fuse)
+{
+ return (cvmx_fuse_read_byte_node(node, fuse >> 3) >> (fuse & 0x7)) & 1;
+}
+
+/**
+ * Read a single fuse bit
+ *
+ * @param fuse Fuse number (0-1024)
+ *
+ * @return fuse value: 0 or 1
+ */
+static inline int cvmx_fuse_read(int fuse)
+{
+ return cvmx_fuse_read_node(0, fuse);
+}
+
+static inline int cvmx_octeon_fuse_locked(void)
+{
+ return cvmx_fuse_read(123);
+}
+
+#endif /* __CVMX_FUSE_H__ */
--
2.28.0
[PATCH v1 03/10] mips: octeon: Add header cvmx-regs.h
From: Aaron Williams
This header includes common register defines and accessor functions.
Signed-off-by: Aaron Williams
Signed-off-by: Stefan Roese
---
.../mips/mach-octeon/include/mach/cvmx-regs.h | 144 ++
1 file changed, 144 insertions(+)
create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-regs.h
diff --git a/arch/mips/mach-octeon/include/mach/cvmx-regs.h
b/arch/mips/mach-octeon/include/mach/cvmx-regs.h
new file mode 100644
index 00..b84fc9fd57
--- /dev/null
+++ b/arch/mips/mach-octeon/include/mach/cvmx-regs.h
@@ -0,0 +1,144 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2020 Stefan Roese
+ */
+
+#ifndef __CVMX_REGS_H__
+#define __CVMX_REGS_H__
+
+#include
+#include
+#include
+
+/* General defines */
+#define CVMX_MAX_CORES 48
+/* Maximum # of bits to define core in node */
+#define CVMX_NODE_NO_SHIFT 7
+#define CVMX_NODE_BITS 2 /* Number of bits to define a node */
+#define CVMX_MAX_NODES (1 << CVMX_NODE_BITS)
+#define CVMX_NODE_MASK (CVMX_MAX_NODES - 1)
+#define CVMX_NODE_IO_SHIFT 36
+#define CVMX_NODE_MEM_SHIFT40
+#define CVMX_NODE_IO_MASK ((u64)CVMX_NODE_MASK << CVMX_NODE_IO_SHIFT)
+
+#define CVMX_MIPS_MAX_CORE_BITS10 /* Maximum # of bits to define
cores */
+#define CVMX_MIPS_MAX_CORES(1 << CVMX_MIPS_MAX_CORE_BITS)
+
+#define MAX_CORE_TADS 8
+
+#define CAST_ULL(v)((unsigned long long)(v))
+#define CASTPTR(type, v) ((type *)(long)(v))
+
+/* Regs */
+#define CVMX_CIU_PP_RST0x000101000100ULL
+#define CVMX_CIU3_NMI 0x000101000160ULL
+#define CVMX_CIU_FUSE 0x0001010001a0ULL
+#define CVMX_CIU_NMI 0x000107000718ULL
+
+#define CVMX_MIO_BOOT_LOC_CFGX(x) (0x00011880ULL + ((x) & 1) * 8)
+#define MIO_BOOT_LOC_CFG_BASE GENMASK_ULL(27, 3)
+#define MIO_BOOT_LOC_CFG_ENBIT_ULL(31)
+
+#define CVMX_MIO_BOOT_LOC_ADR 0x00011890ULL
+#define MIO_BOOT_LOC_ADR_ADR GENMASK_ULL(7, 3)
+
+#define CVMX_MIO_BOOT_LOC_DAT 0x00011898ULL
+
+#define CVMX_MIO_FUS_DAT2 0x000118001410ULL
+#define MIO_FUS_DAT2_NOCRYPTO BIT_ULL(26)
+#define MIO_FUS_DAT2_NOMUL BIT_ULL(27)
+#define MIO_FUS_DAT2_DORM_CRYPTO BIT_ULL(34)
+
+#define CVMX_MIO_FUS_RCMD 0x000118001500ULL
+#define MIO_FUS_RCMD_ADDR GENMASK_ULL(7, 0)
+#define MIO_FUS_RCMD_PEND BIT_ULL(12)
+#define MIO_FUS_RCMD_DAT GENMASK_ULL(23, 16)
+
+#define CVMX_RNM_CTL_STATUS0x000118004000ULL
+#define RNM_CTL_STATUS_EER_VAL BIT_ULL(9)
+
+/* turn the variable name into a string */
+#define CVMX_TMP_STR(x)CVMX_TMP_STR2(x)
+#define CVMX_TMP_STR2(x) #x
+
+#define CVMX_RDHWRNV(result, regstr) \
+ asm volatile ("rdhwr %[rt],$" CVMX_TMP_STR(regstr) : [rt] "=d" (result))
+
+#define CVMX_SYNCW \
+ asm volatile ("syncw\nsyncw\n" : : : "memory")
+
+/* ToDo: Currently only node = 0 supported */
+static inline u64 csr_rd_node(int node, u64 addr)
+{
+ void __iomem *base;
+
+ base = ioremap_nocache(addr, 0x100);
+ return ioread64(base);
+}
+
+static inline u64 csr_rd(u64 addr)
+{
+ return csr_rd_node(0, addr);
+}
+
+static inline void csr_wr_node(int node, u64 addr, u64 val)
+{
+ void __iomem *base;
+
+ base = ioremap_nocache(addr, 0x100);
+ iowrite64(val, base);
+}
+
+static inline void csr_wr(u64 addr, u64 val)
+{
+ csr_wr_node(0, addr, val);
+}
+
+/*
+ * We need to use the volatile access here, otherwise the IO accessor
+ * functions might swap the bytes
+ */
+static inline u64 cvmx_read64_uint64(u64 addr)
+{
+ return *(volatile u64 *)addr;
+}
+
+static inline void cvmx_write64_uint64(u64 addr, u64 val)
+{
+ *(volatile u64 *)addr = val;
+}
+
+static inline u32 cvmx_read64_uint32(u64 addr)
+{
+ return *(volatile u32 *)addr;
+}
+
+static inline void cvmx_write64_uint32(u64 addr, u32 val)
+{
+ *(volatile u32 *)addr = val;
+}
+
+static inline void *cvmx_phys_to_ptr(u64 addr)
+{
+ return (void *)CKSEG0ADDR(addr);
+}
+
+static inline u64 cvmx_ptr_to_phys(void *ptr)
+{
+ return virt_to_phys(ptr);
+}
+
+/**
+ * Number of the Core on which the program is currently running.
+ *
+ * @return core number
+ */
+static inline unsigned int cvmx_get_core_num(void)
+{
+ unsigned int core_num;
+
+ CVMX_RDHWRNV(core_num, 0);
+ return core_num;
+}
+
+#endif /* __CVMX_REGS_H__ */
--
2.28.0
[PATCH v1 01/10] mips: octeon: octeon-model.h: Enable inclusion from assembler files
Add the #ifdef __ASSEMBLY__ checks to enable inclusion of this header from assembler files. Signed-off-by: Stefan Roese --- arch/mips/mach-octeon/include/mach/octeon-model.h | 4 1 file changed, 4 insertions(+) diff --git a/arch/mips/mach-octeon/include/mach/octeon-model.h b/arch/mips/mach-octeon/include/mach/octeon-model.h index 209e813a2f..c842f894bf 100644 --- a/arch/mips/mach-octeon/include/mach/octeon-model.h +++ b/arch/mips/mach-octeon/include/mach/octeon-model.h @@ -266,6 +266,8 @@ ))); \ }) +#ifndef __ASSEMBLY__ + #ifndef OCTEON_IS_MODEL static inline int __octeon_is_model_runtime_internal__(u32 model) @@ -314,4 +316,6 @@ static inline u32 cvmx_get_octeon_family(void) return (read_c0_prid() & OCTEON_FAMILY_MASK); } +#endif /* __ASSEMBLY__ */ + #endif /* __OCTEON_MODEL_H__ */ -- 2.28.0
[PATCH v1 00/10] mips: octeon: Add bootoctlinux command for Octeon Linux kernel booting
This patchset adds the platforms specific bootoctlinux command, which is used to boot the MIPS Octeon Linux kernel (4.9.x). A special command is necessary here, as very platform specific data is passed to the kernel via the bootinfo / bootmem format. This patchset also includes various required infrastructure code for this (octeon-feature, coremask, bootinfo). The code for booting the additional cores is also included in this patchset. Tested on Octeon 7304 EBB with all 16 cores. Thanks, Stefan Aaron Williams (7): mips: octeon: Add header cvmx-regs.h mips: octeon: Add header octeon-feature.h mips: octeon: Add header cvmx-fuse.h mips: octeon: Add header cvmx-bootinfo.h mips: octeon: Add coremask support mips: octeon: Add bootmem support mips: octeon: Add bootoctlinux command Stefan Roese (3): mips: octeon: octeon-model.h: Enable inclusion from assembler files mips: octeon: lowlevel_init.S: Add NMI handling code for SMP Linux booting mips: octeon: octeon_common.h: Increase CONFIG_SYS_BOOTM_LEN arch/mips/mach-octeon/Makefile|3 + arch/mips/mach-octeon/bootoctlinux.c | 661 arch/mips/mach-octeon/cvmx-bootmem.c | 1460 + arch/mips/mach-octeon/cvmx-coremask.c | 366 + .../mach-octeon/include/mach/bootoct_cmd.h| 54 + .../mach-octeon/include/mach/cvmx-bootinfo.h | 350 .../mach-octeon/include/mach/cvmx-bootmem.h | 533 ++ .../mach-octeon/include/mach/cvmx-coremask.h | 752 + .../mips/mach-octeon/include/mach/cvmx-fuse.h | 71 + .../mips/mach-octeon/include/mach/cvmx-regs.h | 144 ++ .../mach-octeon/include/mach/octeon-feature.h | 442 + .../mach-octeon/include/mach/octeon-model.h |4 + arch/mips/mach-octeon/lowlevel_init.S | 76 + include/configs/octeon_common.h |2 + 14 files changed, 4918 insertions(+) create mode 100644 arch/mips/mach-octeon/bootoctlinux.c create mode 100644 arch/mips/mach-octeon/cvmx-bootmem.c create mode 100644 arch/mips/mach-octeon/cvmx-coremask.c create mode 100644 arch/mips/mach-octeon/include/mach/bootoct_cmd.h create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-bootinfo.h create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-bootmem.h create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-coremask.h create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-fuse.h create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-regs.h create mode 100644 arch/mips/mach-octeon/include/mach/octeon-feature.h -- 2.28.0
Re: [EXT] [PATCH 1/2] arm64: a37xx: pci: Make PCIe Reset GPIO DT compatible with Linux kernel DT
Hi Kosta,
AFAICT, this mail does not contain any info from you. I can only
assume, that you wanted to send a Reviewed-by tag. If yes, then
please double-check which mails did not work and resend them with
the correct tags. As they are automatically collected by patchwork.
Thanks,
Stefan
On 19.08.20 19:28, Kostya Porotchkin wrote:
From: Pali Rohár
Sent: Wednesday, August 19, 2020 16:57
To: Stefan Roese; Kostya Porotchkin
Cc: u-boot@lists.denx.de
Subject: [EXT] [PATCH 1/2] arm64: a37xx: pci: Make PCIe Reset GPIO DT
compatible with Linux kernel DT
External Email
--
Change active-high to active-low and change DT property name from
reset-gpio to reset-gpios. This format of gpio reset is used by
pci-aardvark driver in Linux kernel.
Signed-off-by: Pali Rohár
Reviewed-by: Konstantin Porotchkin
---
arch/arm/dts/armada-3720-db.dts | 2 +-
arch/arm/dts/armada-3720-espressobin.dts | 2 +-
arch/arm/dts/armada-3720-turris-mox.dts | 2 +-
drivers/pci/pci-aardvark.c | 6 +++---
4 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/arch/arm/dts/armada-3720-db.dts b/arch/arm/dts/armada-3720-db.dts
index 1b219c423b..1b1b66b94d 100644
--- a/arch/arm/dts/armada-3720-db.dts
+++ b/arch/arm/dts/armada-3720-db.dts
@@ -159,6 +159,6 @@
{
pinctrl-names = "default";
pinctrl-0 = <_pins>;
- reset-gpio = < 3 GPIO_ACTIVE_HIGH>;
+ reset-gpios = < 3 GPIO_ACTIVE_LOW>;
status = "okay";
};
diff --git a/arch/arm/dts/armada-3720-espressobin.dts
b/arch/arm/dts/armada-3720-espressobin.dts
index 84e2c2adba..f10a953ec5 100644
--- a/arch/arm/dts/armada-3720-espressobin.dts
+++ b/arch/arm/dts/armada-3720-espressobin.dts
@@ -145,6 +145,6 @@
{
pinctrl-names = "default";
pinctrl-0 = <_pins>;
- reset-gpio = < 3 GPIO_ACTIVE_HIGH>;
+ reset-gpios = < 3 GPIO_ACTIVE_LOW>;
status = "okay";
};
diff --git a/arch/arm/dts/armada-3720-turris-mox.dts
b/arch/arm/dts/armada-3720-turris-mox.dts
index 0f0a6ce65d..974270cc8c 100644
--- a/arch/arm/dts/armada-3720-turris-mox.dts
+++ b/arch/arm/dts/armada-3720-turris-mox.dts
@@ -172,6 +172,6 @@
{
pinctrl-names = "default";
pinctrl-0 = <_pins>;
- reset-gpio = < 3 GPIO_ACTIVE_HIGH>;
+ reset-gpios = < 3 GPIO_ACTIVE_LOW>;
status = "disabled";
};
diff --git a/drivers/pci/pci-aardvark.c b/drivers/pci/pci-aardvark.c
index 711b930d0f..5b3f23c184 100644
--- a/drivers/pci/pci-aardvark.c
+++ b/drivers/pci/pci-aardvark.c
@@ -616,7 +616,7 @@ static int pcie_advk_probe(struct udevice *dev)
#if CONFIG_IS_ENABLED(DM_GPIO)
struct gpio_desc reset_gpio;
- gpio_request_by_name(dev, "reset-gpio", 0, _gpio,
+ gpio_request_by_name(dev, "reset-gpios", 0, _gpio,
GPIOD_IS_OUT);
/*
* Issue reset to add-in card through the dedicated GPIO.
@@ -633,9 +633,9 @@ static int pcie_advk_probe(struct udevice *dev)
*/
if (dm_gpio_is_valid(_gpio)) {
dev_dbg(pcie->dev, "Toggle PCIE Reset GPIO ...\n");
- dm_gpio_set_value(_gpio, 0);
- mdelay(200);
dm_gpio_set_value(_gpio, 1);
+ mdelay(200);
+ dm_gpio_set_value(_gpio, 0);
}
#else
dev_dbg(pcie->dev, "PCIE Reset on GPIO support is missing\n");
--
2.20.1
Viele Grüße,
Stefan
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-51 Fax: (+49)-8142-66989-80 Email: s...@denx.de
Re: [PATCH 2/2] arm64: a37xx: pci: Assert PERST# signal when unloading driver
On 19.08.20 15:57, Pali Rohár wrote:
This change ensures that PCIe card is put into reset state when U-Boot
stops using it.
DM_FLAG_OS_PREPARE ensures that U-Boot executes driver's remove callback
prior booting Linux kernel.
Linux kernel pci-aardvark driver needs to reset PCIe card via PERST# signal
prior initializing it. If it does not issue reset then some PCIe cards
(specially Compex WiFi cards) are not detected at all.
Putting PCIe card into reset state prior booting Linux kernel would ensure
that card would be properly reset at time when Linux kernel starts
initializing pci-aardvark driver.
Signed-off-by: Pali Rohár
---
drivers/pci/pci-aardvark.c | 27 +--
1 file changed, 21 insertions(+), 6 deletions(-)
diff --git a/drivers/pci/pci-aardvark.c b/drivers/pci/pci-aardvark.c
index 5b3f23c184..8996be5309 100644
--- a/drivers/pci/pci-aardvark.c
+++ b/drivers/pci/pci-aardvark.c
@@ -148,6 +148,9 @@ struct pcie_advk {
void *base;
intfirst_busno;
struct udevice *dev;
+#if CONFIG_IS_ENABLED(DM_GPIO)
+ struct gpio_desc reset_gpio;
+#endif
};
Adding more #ifdef's is not recommended. Can't you "depend" this driver
on DM_GPIO in Kconfig instead? Are there any used that don't support
DM_GPIO right now?
static inline void advk_writel(struct pcie_advk *pcie, uint val, uint reg)
@@ -614,9 +617,7 @@ static int pcie_advk_probe(struct udevice *dev)
struct pcie_advk *pcie = dev_get_priv(dev);
#if CONFIG_IS_ENABLED(DM_GPIO)
If you change the driver to rely on DM_GPIO, then please also remove all
other #ifdef's with DM_GPIO.
Thanks,
Stefan
- struct gpio_desc reset_gpio;
-
- gpio_request_by_name(dev, "reset-gpios", 0, _gpio,
+ gpio_request_by_name(dev, "reset-gpios", 0, >reset_gpio,
GPIOD_IS_OUT);
/*
* Issue reset to add-in card through the dedicated GPIO.
@@ -631,11 +632,11 @@ static int pcie_advk_probe(struct udevice *dev)
* possible before PCIe PHY initialization. Moreover, the PCIe
* clock should be gated as well.
*/
- if (dm_gpio_is_valid(_gpio)) {
+ if (dm_gpio_is_valid(>reset_gpio)) {
dev_dbg(pcie->dev, "Toggle PCIE Reset GPIO ...\n");
- dm_gpio_set_value(_gpio, 1);
+ dm_gpio_set_value(>reset_gpio, 1);
mdelay(200);
- dm_gpio_set_value(_gpio, 0);
+ dm_gpio_set_value(>reset_gpio, 0);
}
#else
dev_dbg(pcie->dev, "PCIE Reset on GPIO support is missing\n");
@@ -647,6 +648,18 @@ static int pcie_advk_probe(struct udevice *dev)
return pcie_advk_setup_hw(pcie);
}
+static int pcie_advk_remove(struct udevice *dev)
+{
+#if CONFIG_IS_ENABLED(DM_GPIO)
+ struct pcie_advk *pcie = dev_get_priv(dev);
+
+ if (dm_gpio_is_valid(>reset_gpio))
+ dm_gpio_set_value(>reset_gpio, 1);
+#endif /* DM_GPIO */
+
+ return 0;
+}
+
/**
* pcie_advk_ofdata_to_platdata() - Translate from DT to device state
*
@@ -687,5 +700,7 @@ U_BOOT_DRIVER(pcie_advk) = {
.ops= _advk_ops,
.ofdata_to_platdata = pcie_advk_ofdata_to_platdata,
.probe = pcie_advk_probe,
+ .remove = pcie_advk_remove,
+ .flags = DM_FLAG_OS_PREPARE,
.priv_auto_alloc_size = sizeof(struct pcie_advk),
};
Viele Grüße,
Stefan
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-51 Fax: (+49)-8142-66989-80 Email: s...@denx.de
Re: [PATCH 1/2] arm64: a37xx: pci: Make PCIe Reset GPIO DT compatible with Linux kernel DT
On 19.08.20 15:57, Pali Rohár wrote:
Change active-high to active-low and change DT property name from
reset-gpio to reset-gpios. This format of gpio reset is used by
pci-aardvark driver in Linux kernel.
Signed-off-by: Pali Rohár
Reviewed-by: Stefan Roese
Thanks,
Stefan
---
arch/arm/dts/armada-3720-db.dts | 2 +-
arch/arm/dts/armada-3720-espressobin.dts | 2 +-
arch/arm/dts/armada-3720-turris-mox.dts | 2 +-
drivers/pci/pci-aardvark.c | 6 +++---
4 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/arch/arm/dts/armada-3720-db.dts b/arch/arm/dts/armada-3720-db.dts
index 1b219c423b..1b1b66b94d 100644
--- a/arch/arm/dts/armada-3720-db.dts
+++ b/arch/arm/dts/armada-3720-db.dts
@@ -159,6 +159,6 @@
{
pinctrl-names = "default";
pinctrl-0 = <_pins>;
- reset-gpio = < 3 GPIO_ACTIVE_HIGH>;
+ reset-gpios = < 3 GPIO_ACTIVE_LOW>;
status = "okay";
};
diff --git a/arch/arm/dts/armada-3720-espressobin.dts
b/arch/arm/dts/armada-3720-espressobin.dts
index 84e2c2adba..f10a953ec5 100644
--- a/arch/arm/dts/armada-3720-espressobin.dts
+++ b/arch/arm/dts/armada-3720-espressobin.dts
@@ -145,6 +145,6 @@
{
pinctrl-names = "default";
pinctrl-0 = <_pins>;
- reset-gpio = < 3 GPIO_ACTIVE_HIGH>;
+ reset-gpios = < 3 GPIO_ACTIVE_LOW>;
status = "okay";
};
diff --git a/arch/arm/dts/armada-3720-turris-mox.dts
b/arch/arm/dts/armada-3720-turris-mox.dts
index 0f0a6ce65d..974270cc8c 100644
--- a/arch/arm/dts/armada-3720-turris-mox.dts
+++ b/arch/arm/dts/armada-3720-turris-mox.dts
@@ -172,6 +172,6 @@
{
pinctrl-names = "default";
pinctrl-0 = <_pins>;
- reset-gpio = < 3 GPIO_ACTIVE_HIGH>;
+ reset-gpios = < 3 GPIO_ACTIVE_LOW>;
status = "disabled";
};
diff --git a/drivers/pci/pci-aardvark.c b/drivers/pci/pci-aardvark.c
index 711b930d0f..5b3f23c184 100644
--- a/drivers/pci/pci-aardvark.c
+++ b/drivers/pci/pci-aardvark.c
@@ -616,7 +616,7 @@ static int pcie_advk_probe(struct udevice *dev)
#if CONFIG_IS_ENABLED(DM_GPIO)
struct gpio_desc reset_gpio;
- gpio_request_by_name(dev, "reset-gpio", 0, _gpio,
+ gpio_request_by_name(dev, "reset-gpios", 0, _gpio,
GPIOD_IS_OUT);
/*
* Issue reset to add-in card through the dedicated GPIO.
@@ -633,9 +633,9 @@ static int pcie_advk_probe(struct udevice *dev)
*/
if (dm_gpio_is_valid(_gpio)) {
dev_dbg(pcie->dev, "Toggle PCIE Reset GPIO ...\n");
- dm_gpio_set_value(_gpio, 0);
- mdelay(200);
dm_gpio_set_value(_gpio, 1);
+ mdelay(200);
+ dm_gpio_set_value(_gpio, 0);
}
#else
dev_dbg(pcie->dev, "PCIE Reset on GPIO support is missing\n");
Viele Grüße,
Stefan
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-51 Fax: (+49)-8142-66989-80 Email: s...@denx.de
Re: [PATCH 2/2] arm: mvebu: Espressobin: Setup MTD partitions when booting kernel
On 19.08.20 16:24, Pali Rohár wrote:
Due to different partition layouts in different U-Boot versions, DTS for
Espressobin in Linux does not contain any definition of MTD partitions.
See commit https://git.kernel.org/stable/c/00954566464a4 for more details.
This patch via ft_board_setup() hook fills current partition layout used by
U-Boot, so booted kernel would see correct MTD partitions layout.
U-Boot env partition is calculated from CONFIG_ENV_OFFSET option.
First partition contains secure firmware, ARM trusted firmware and U-Boot
with checksums. So it is not possible to replace just one image (e.g.
U-Boot) without updating other parts where is stored checksum of U-Boot.
Therefore there is no extra partition defined for U-Boot and first
partition is called just 'firmware'.
Signed-off-by: Pali Rohár
---
board/Marvell/mvebu_armada-37xx/board.c | 100
configs/mvebu_espressobin-88f3720_defconfig | 1 +
2 files changed, 101 insertions(+)
diff --git a/board/Marvell/mvebu_armada-37xx/board.c
b/board/Marvell/mvebu_armada-37xx/board.c
index 031de318c6..7b9c3223ed 100644
--- a/board/Marvell/mvebu_armada-37xx/board.c
+++ b/board/Marvell/mvebu_armada-37xx/board.c
@@ -243,3 +243,103 @@ int board_network_enable(struct mii_dev *bus)
return 0;
}
+
+#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_ENV_IS_IN_SPI_FLASH)
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+ int ret;
+ int spi_off;
+ int parts_off;
+ int part_off;
+
+ /* Fill SPI MTD partitions for Linux kernel on Espressobin */
+ if (!of_machine_is_compatible("marvell,armada-3720-espressobin"))
+ return 0;
+
+ spi_off = fdt_node_offset_by_compatible(blob, -1, "jedec,spi-nor");
+ if (spi_off < 0)
+ return 0;
+
+ /* Do not touch partitions if they are already defined */
+ if (fdt_subnode_offset(blob, spi_off, "partitions") >= 0)
+ return 0;
+
+ parts_off = fdt_add_subnode(blob, spi_off, "partitions");
+ if (parts_off < 0) {
+ printf("Can't add partitions node: %s\n",
fdt_strerror(parts_off));
+ return 0;
+ }
+
+ ret = fdt_setprop_string(blob, parts_off, "compatible",
"fixed-partitions");
+ if (ret < 0) {
+ printf("Can't set compatible property: %s\n",
fdt_strerror(ret));
+ return 0;
+ }
+
+ ret = fdt_setprop_u32(blob, parts_off, "#address-cells", 1);
+ if (ret < 0) {
+ printf("Can't set #address-cells property: %s\n",
fdt_strerror(ret));
+ return 0;
+ }
+
+ ret = fdt_setprop_u32(blob, parts_off, "#size-cells", 1);
+ if (ret < 0) {
+ printf("Can't set #size-cells property: %s\n",
fdt_strerror(ret));
+ return 0;
+ }
+
+ /* Add u-boot-env partition */
+
+ part_off = fdt_add_subnode(blob, parts_off, "partition@u-boot-env");
+ if (part_off < 0) {
+ printf("Can't add partition@u-boot-env node: %s\n",
fdt_strerror(part_off));
+ return 0;
+ }
+
+ ret = fdt_setprop_u32(blob, part_off, "reg", CONFIG_ENV_OFFSET);
+ if (ret < 0) {
+ printf("Can't set partition@u-boot-env reg property: %s\n",
fdt_strerror(ret));
+ return 0;
+ }
+
+ ret = fdt_appendprop_u32(blob, part_off, "reg", CONFIG_ENV_SIZE);
+ if (ret < 0) {
+ printf("Can't set partition@u-boot-env reg property: %s\n",
fdt_strerror(ret));
+ return 0;
+ }
+
+ ret = fdt_setprop_string(blob, part_off, "label", "u-boot-env");
+ if (ret < 0) {
+ printf("Can't set partition@u-boot-env label property: %s\n",
fdt_strerror(ret));
+ return 0;
+ }
+
+ /* Add firmware partition */
+
+ part_off = fdt_add_subnode(blob, parts_off, "partition@firmware");
+ if (part_off < 0) {
+ printf("Can't add partition@firmware node: %s\n",
fdt_strerror(part_off));
+ return 0;
+ }
+
+ ret = fdt_setprop_u32(blob, part_off, "reg", 0);
+ if (ret < 0) {
+ printf("Can't set partition@firmware reg property: %s\n",
fdt_strerror(ret));
+ return 0;
+ }
+
+ ret = fdt_appendprop_u32(blob, part_off, "reg", CONFIG_ENV_OFFSET);
+ if (ret < 0) {
+ printf("Can't set partition@firmware reg property: %s\n",
fdt_strerror(ret));
+ return 0;
+ }
+
+ ret = fdt_setprop_string(blob, part_off, "label", "firmware");
+ if (ret < 0) {
+ printf("Can't set partition@firmware label property: %s\n",
fdt_strerror(ret));
+ return 0;
+ }
+
+ return 0;
+}
+#endif
Can't you just use "mtdparts=" kernel cmdline parameter instead to pass
the MTD layout to the kernel?
Thanks,
Stefan
Re: [PATCH 1/2] arm: mvebu: Espressobin: Make SPI env offset compatible with Marvell's U-Boot
On 19.08.20 16:24, Pali Rohár wrote: Espressobin board comes with Marvell's U-Boot version where U-Boot env is stored in SPI at offset 0x3F. This patch changes env offset in Espressobin defconfig file to match Marvell's U-Boot version. Users who want to use previous or different env offset can still change it in .config file when compiling U-Boot. Signed-off-by: Pali Rohár Reviewed-by: Stefan Roese Thanks, Stefan --- configs/mvebu_espressobin-88f3720_defconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/configs/mvebu_espressobin-88f3720_defconfig b/configs/mvebu_espressobin-88f3720_defconfig index 933592af88..afcdd947c1 100644 --- a/configs/mvebu_espressobin-88f3720_defconfig +++ b/configs/mvebu_espressobin-88f3720_defconfig @@ -6,7 +6,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_NR_DRAM_BANKS=1 CONFIG_TARGET_MVEBU_ARMADA_37XX=y CONFIG_ENV_SIZE=0x1 -CONFIG_ENV_OFFSET=0x18 +CONFIG_ENV_OFFSET=0x3F CONFIG_ENV_SECT_SIZE=0x1 CONFIG_DM_GPIO=y CONFIG_DEBUG_UART_BASE=0xd0012000 Viele Grüße, Stefan -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-51 Fax: (+49)-8142-66989-80 Email: s...@denx.de
Re: [PATCH 2/2] arm: dts: a37x0: enable sd card support on espressobin
On 19.08.20 16:19, Pali Rohár wrote:
From: Wilson Ding
Enabled SDIO slot 0 (south bridge) for SD card on
Espressobin board.
Change-Id: I51a2debf9fba276b9c4a2bc6da91328d47f443e3
Signed-off-by: Wilson Ding
Signed-off-by: Konstantin Porotchkin
Reviewed-on: http://vgitil04.il.marvell.com:8080/60945
Tested-by: iSoC Platform CI
Reviewed-by: Igal Liberman
[pali: Define cd-gpios and enable CONFIG_DM_REGULATOR_GPIO]
Signed-off-by: Pali Rohár
Reviewed-by: Stefan Roese
Thanks,
Stefan
---
arch/arm/dts/armada-3720-espressobin.dts| 20
configs/mvebu_espressobin-88f3720_defconfig | 1 +
2 files changed, 21 insertions(+)
diff --git a/arch/arm/dts/armada-3720-espressobin.dts
b/arch/arm/dts/armada-3720-espressobin.dts
index f10a953ec5..92eddca6c0 100644
--- a/arch/arm/dts/armada-3720-espressobin.dts
+++ b/arch/arm/dts/armada-3720-espressobin.dts
@@ -67,6 +67,17 @@
device_type = "memory";
reg = <0x 0x 0x 0x2000>;
};
+
+ vcc_sd_reg0: regulator@0 {
+ compatible = "regulator-gpio";
+ regulator-name = "vcc_sd0";
+ regulator-min-microvolt = <180>;
+ regulator-max-microvolt = <330>;
+ regulator-type = "voltage";
+ states = <180 0x1
+ 330 0x0>;
+ gpios = < 4 GPIO_ACTIVE_HIGH>;
+ };
};
{
@@ -110,6 +121,15 @@
status = "okay";
};
+ {
+ pinctrl-names = "default";
+ pinctrl-0 = <_pins>;
+ bus-width = <4>;
+ cd-gpios = < 3 GPIO_ACTIVE_LOW>;
+ vqmmc-supply = <_sd_reg0>;
+ status = "okay";
+};
+
{
status = "okay";
pinctrl-names = "default";
diff --git a/configs/mvebu_espressobin-88f3720_defconfig
b/configs/mvebu_espressobin-88f3720_defconfig
index 495faf43a3..933592af88 100644
--- a/configs/mvebu_espressobin-88f3720_defconfig
+++ b/configs/mvebu_espressobin-88f3720_defconfig
@@ -81,3 +81,4 @@ CONFIG_USB_ETHER_SMSC95XX=y
CONFIG_SHA1=y
CONFIG_SHA256=y
CONFIG_MVNETA=y
+CONFIG_DM_REGULATOR_GPIO=y
Viele Grüße,
Stefan
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-51 Fax: (+49)-8142-66989-80 Email: s...@denx.de
Re: [PATCH 1/2] mmc: xenon: set signal voltage and max base clock
On 19.08.20 16:19, Pali Rohár wrote:
From: Evan Wang
- The SDIO signal voltage and max base clock frequency
setting are missing in driver, which causes SDIO
not working.
- The patch adds SDIO signal voltage switch support,
which is based on regulator-gpio of vqmmc-supply, and
sets the max base clock frequency.
- Fix the zero clock value in call to sdhci_setup_cfg()
function.
Change-Id: I79c8860c65b8db166f4f70db56ede4097f71f1fa
Signed-off-by: Evan Wang
Reviewed-on: http://vgitil04.il.marvell.com:8080/53589
Reviewed-by: Hua Jing
Tested-by: Hua Jing
[pali: Amended fixup patch]
Signed-off-by: Pali Rohár
Reviewed-by: Stefan Roese
Thanks,
Stefan
---
drivers/mmc/xenon_sdhci.c | 79 ++-
1 file changed, 78 insertions(+), 1 deletion(-)
diff --git a/drivers/mmc/xenon_sdhci.c b/drivers/mmc/xenon_sdhci.c
index 356dd9846d..7f9a579c83 100644
--- a/drivers/mmc/xenon_sdhci.c
+++ b/drivers/mmc/xenon_sdhci.c
@@ -22,6 +22,7 @@
#include
#include
#include
+#include
DECLARE_GLOBAL_DATA_PTR;
@@ -42,6 +43,14 @@ DECLARE_GLOBAL_DATA_PTR;
#define SDHC_SYS_EXT_OP_CTRL 0x010C
#define MASK_CMD_CONFLICT_ERROR BIT(8)
+#define SDHC_SLOT_EMMC_CTRL 0x0130
+#define ENABLE_DATA_STROBE_SHIFT 24
+#define SET_EMMC_RSTN_SHIFT16
+#define EMMC_VCCQ_MASK 0x3
+#define EMMC_VCCQ_1_8V 0x1
+#define EMMC_VCCQ_1_2V 0x2
+#defineEMMC_VCCQ_3_3V 0x3
+
#define SDHC_SLOT_RETUNING_REQ_CTRL 0x0144
/* retuning compatible */
#define RETUNING_COMPATIBLE 0x1
@@ -108,6 +117,8 @@ DECLARE_GLOBAL_DATA_PTR;
#define MMC_TIMING_MMC_HS400 10
#define XENON_MMC_MAX_CLK 4
+#define XENON_MMC_3V3_UV 330
+#define XENON_MMC_1V8_UV 180
enum soc_pad_ctrl_type {
SOC_PAD_SD,
@@ -128,6 +139,8 @@ struct xenon_sdhci_priv {
void *pad_ctrl_reg;
int pad_type;
+
+ struct udevice *vqmmc;
};
static int xenon_mmc_phy_init(struct sdhci_host *host)
@@ -208,6 +221,51 @@ static void armada_3700_soc_pad_voltage_set(struct
sdhci_host *host)
writel(ARMADA_3700_SOC_PAD_3_3V, priv->pad_ctrl_reg);
}
+static int xenon_mmc_start_signal_voltage_switch(struct sdhci_host *host)
+{
+ struct xenon_sdhci_priv *priv = host->mmc->priv;
+ u8 voltage;
+ u32 ctrl;
+ int ret = 0;
+
+ /* If there is no vqmmc regulator, return */
+ if (!priv->vqmmc)
+ return 0;
+
+ if (priv->pad_type == SOC_PAD_FIXED_1_8V) {
+ /* Switch to 1.8v */
+ ret = regulator_set_value(priv->vqmmc,
+ XENON_MMC_1V8_UV);
+ } else if (priv->pad_type == SOC_PAD_SD) {
+ /* Get voltage info */
+ voltage = sdhci_readb(host, SDHCI_POWER_CONTROL);
+ voltage &= ~SDHCI_POWER_ON;
+
+ if (voltage == SDHCI_POWER_330) {
+ /* Switch to 3.3v */
+ ret = regulator_set_value(priv->vqmmc,
+ XENON_MMC_3V3_UV);
+ } else {
+ /* Switch to 1.8v */
+ ret = regulator_set_value(priv->vqmmc,
+ XENON_MMC_1V8_UV);
+ }
+ }
+
+ /* Set VCCQ, eMMC mode: 1.8V; SD/SDIO mode: 3.3V */
+ ctrl = sdhci_readl(host, SDHC_SLOT_EMMC_CTRL);
+ if (IS_SD(host->mmc))
+ ctrl |= EMMC_VCCQ_3_3V;
+ else
+ ctrl |= EMMC_VCCQ_1_8V;
+ sdhci_writel(host, ctrl, SDHC_SLOT_EMMC_CTRL);
+
+ if (ret)
+ printf("Signal voltage switch fail\n");
+
+ return ret;
+}
+
static void xenon_mmc_phy_set(struct sdhci_host *host)
{
struct xenon_sdhci_priv *priv = host->mmc->priv;
@@ -334,6 +392,13 @@ static int xenon_sdhci_set_ios_post(struct sdhci_host
*host)
uint speed = host->mmc->tran_speed;
int pwr_18v = 0;
+ /*
+* Signal Voltage Switching is only applicable for Host Controllers
+* v3.00 and above.
+*/
+ if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
+ xenon_mmc_start_signal_voltage_switch(host);
+
if ((sdhci_readb(host, SDHCI_POWER_CONTROL) & ~SDHCI_POWER_ON) ==
SDHCI_POWER_180)
pwr_18v = 1;
@@ -394,6 +459,18 @@ static int xenon_sdhci_probe(struct udevice *dev)
/* Set default timing */
priv->timing = MMC_TIMING_LEGACY;
+ /* Get the vqmmc regulator if there is */
+ device_get_supply_regulator(dev, "vqmmc-supply", >vqmmc);
+ /* Set the initial voltage value to 3.3V if there is regulator */
+ if (priv->vqmmc) {
+ ret = regulator_set_value(priv->vqmmc,
+
[PATCH v7 08/10] powerpc: Remove bi_memstart & bi_memsize assignments in spl.c
Most likely these deprecated (removed) variables are not needed. Lets remove the assignments completely from all spl.c files. Signed-off-by: Stefan Roese Tested-by: Oleksandr Zhadan and Michael Durrant --- (no changes since v5) Changes in v5: - Add Tested-by tag from Oleksandr & Michael Changes in v4: - New patch board/Arcturus/ucp1020/spl.c | 2 -- board/freescale/p1010rdb/spl.c | 2 -- board/freescale/p1_p2_rdb_pc/spl.c | 2 -- board/freescale/t102xrdb/spl.c | 2 -- board/freescale/t104xrdb/spl.c | 2 -- board/freescale/t208xqds/spl.c | 2 -- board/freescale/t208xrdb/spl.c | 2 -- board/freescale/t4rdb/spl.c| 2 -- 8 files changed, 16 deletions(-) diff --git a/board/Arcturus/ucp1020/spl.c b/board/Arcturus/ucp1020/spl.c index 5416a5b663..0fd9532d74 100644 --- a/board/Arcturus/ucp1020/spl.c +++ b/board/Arcturus/ucp1020/spl.c @@ -83,8 +83,6 @@ void board_init_r(gd_t *gd, ulong dest_addr) bd = (struct bd_info *)(CONFIG_SPL_GD_ADDR + sizeof(gd_t)); memset(bd, 0, sizeof(struct bd_info)); gd->bd = bd; - bd->bi_memstart = CONFIG_SYS_INIT_L2_ADDR; - bd->bi_memsize = CONFIG_SYS_L2_SIZE; arch_cpu_init(); get_clocks(); diff --git a/board/freescale/p1010rdb/spl.c b/board/freescale/p1010rdb/spl.c index 4ee4573d2b..fbaa6a6514 100644 --- a/board/freescale/p1010rdb/spl.c +++ b/board/freescale/p1010rdb/spl.c @@ -69,8 +69,6 @@ void board_init_r(gd_t *gd, ulong dest_addr) bd = (struct bd_info *)(CONFIG_SPL_GD_ADDR + sizeof(gd_t)); memset(bd, 0, sizeof(struct bd_info)); gd->bd = bd; - bd->bi_memstart = CONFIG_SYS_INIT_L2_ADDR; - bd->bi_memsize = CONFIG_SYS_L2_SIZE; arch_cpu_init(); get_clocks(); diff --git a/board/freescale/p1_p2_rdb_pc/spl.c b/board/freescale/p1_p2_rdb_pc/spl.c index e76c3e82c3..8aceceb56a 100644 --- a/board/freescale/p1_p2_rdb_pc/spl.c +++ b/board/freescale/p1_p2_rdb_pc/spl.c @@ -75,8 +75,6 @@ void board_init_r(gd_t *gd, ulong dest_addr) bd = (struct bd_info *)(CONFIG_SPL_GD_ADDR + sizeof(gd_t)); memset(bd, 0, sizeof(struct bd_info)); gd->bd = bd; - bd->bi_memstart = CONFIG_SYS_INIT_L2_ADDR; - bd->bi_memsize = CONFIG_SYS_L2_SIZE; arch_cpu_init(); get_clocks(); diff --git a/board/freescale/t102xrdb/spl.c b/board/freescale/t102xrdb/spl.c index da442fcc18..09dd88ac4e 100644 --- a/board/freescale/t102xrdb/spl.c +++ b/board/freescale/t102xrdb/spl.c @@ -103,8 +103,6 @@ void board_init_r(gd_t *gd, ulong dest_addr) bd = (struct bd_info *)(gd + sizeof(gd_t)); memset(bd, 0, sizeof(struct bd_info)); gd->bd = bd; - bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR; - bd->bi_memsize = CONFIG_SYS_L3_SIZE; arch_cpu_init(); get_clocks(); diff --git a/board/freescale/t104xrdb/spl.c b/board/freescale/t104xrdb/spl.c index f83d69ba15..e7922954de 100644 --- a/board/freescale/t104xrdb/spl.c +++ b/board/freescale/t104xrdb/spl.c @@ -94,8 +94,6 @@ void board_init_r(gd_t *gd, ulong dest_addr) bd = (struct bd_info *)(gd + sizeof(gd_t)); memset(bd, 0, sizeof(struct bd_info)); gd->bd = bd; - bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR; - bd->bi_memsize = CONFIG_SYS_L3_SIZE; arch_cpu_init(); get_clocks(); diff --git a/board/freescale/t208xqds/spl.c b/board/freescale/t208xqds/spl.c index c197884421..d8c2bbe28d 100644 --- a/board/freescale/t208xqds/spl.c +++ b/board/freescale/t208xqds/spl.c @@ -102,8 +102,6 @@ void board_init_r(gd_t *gd, ulong dest_addr) bd = (struct bd_info *)(gd + sizeof(gd_t)); memset(bd, 0, sizeof(struct bd_info)); gd->bd = bd; - bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR; - bd->bi_memsize = CONFIG_SYS_L3_SIZE; arch_cpu_init(); get_clocks(); diff --git a/board/freescale/t208xrdb/spl.c b/board/freescale/t208xrdb/spl.c index 07aab6349c..c64bd87115 100644 --- a/board/freescale/t208xrdb/spl.c +++ b/board/freescale/t208xrdb/spl.c @@ -72,8 +72,6 @@ void board_init_r(gd_t *gd, ulong dest_addr) bd = (struct bd_info *)(gd + sizeof(gd_t)); memset(bd, 0, sizeof(struct bd_info)); gd->bd = bd; - bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR; - bd->bi_memsize = CONFIG_SYS_L3_SIZE; arch_cpu_init(); get_clocks(); diff --git a/board/freescale/t4rdb/spl.c b/board/freescale/t4rdb/spl.c index 64d2753da8..9aa0a9b052 100644 --- a/board/freescale/t4rdb/spl.c +++ b/board/freescale/t4rdb/spl.c @@ -75,8 +75,6 @@ void board_init_r(gd_t *gd, ulong dest_addr) bd = (struct bd_info *)(gd + sizeof(gd_t)); memset(bd, 0, sizeof(struct bd_info)); gd->bd = bd; - bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR; - bd->bi_memsize = CONFIG_SYS_L3_SIZE; arch_cpu_init(); get_clocks(); -- 2.28.0
[PATCH v7 09/10] cmd: bdinfo: Remove print of superseeded bi_memstart / bi_memsize values
Remove printing of the superseeded (by bi_dram[]) memory values from the
bdinfo command.
Signed-off-by: Stefan Roese
Reviewed-by: Ovidiu Panait
---
Changes in v7:
- Add Reviewe-by tag from Ovidiu
Changes in v4:
- New patch
cmd/bdinfo.c | 8
1 file changed, 8 deletions(-)
diff --git a/cmd/bdinfo.c b/cmd/bdinfo.c
index 9e230f23cb..0229846d3e 100644
--- a/cmd/bdinfo.c
+++ b/cmd/bdinfo.c
@@ -34,12 +34,6 @@ static void print_eth(int idx)
printf("%-12s= %s\n", name, val);
}
-static void print_phys_addr(const char *name, phys_addr_t value)
-{
- printf("%-12s= 0x%.*llx\n", name, 2 * (int)sizeof(ulong),
- (unsigned long long)value);
-}
-
void bdinfo_print_mhz(const char *name, unsigned long hz)
{
char buf[32];
@@ -73,8 +67,6 @@ int do_bdinfo(struct cmd_tbl *cmdtp, int flag, int argc, char
*const argv[])
#endif
bdinfo_print_num("boot_params", (ulong)bd->bi_boot_params);
print_bi_dram(bd);
- bdinfo_print_num("memstart", (ulong)bd->bi_memstart);
- print_phys_addr("memsize", bd->bi_memsize);
if (IS_ENABLED(CONFIG_SYS_HAS_SRAM)) {
bdinfo_print_num("sramstart", (ulong)bd->bi_sramstart);
bdinfo_print_num("sramsize", (ulong)bd->bi_sramsize);
--
2.28.0
[PATCH v7 10/10] asm-generic/u-boot.h: Remove bi_memstart & bi_memsize from bd_info
bi_memstart & bi_memsize are now not referenced any more. This patch
removes their definitions from the bd_info struct.
Signed-off-by: Stefan Roese
---
(no changes since v4)
Changes in v4:
- New patch
include/asm-generic/u-boot.h | 2 --
1 file changed, 2 deletions(-)
diff --git a/include/asm-generic/u-boot.h b/include/asm-generic/u-boot.h
index 99d3fe33ad..637de0c455 100644
--- a/include/asm-generic/u-boot.h
+++ b/include/asm-generic/u-boot.h
@@ -27,8 +27,6 @@
#include
struct bd_info {
- unsigned long bi_memstart;/* start of DRAM memory */
- phys_size_t bi_memsize; /* size of DRAM memory in bytes */
unsigned long bi_flashstart; /* start of FLASH memory */
unsigned long bi_flashsize; /* size of FLASH memory */
unsigned long bi_flashoffset; /* reserved area for startup monitor */
--
2.28.0
[PATCH v7 05/10] xtensa: Remove arch_setup_bdinfo()
arch_setup_bdinfo() only configures the deprecated bi_memstart &
bi_memsize values, which should not be needed any more. Lets remove
this file completely.
Signed-off-by: Stefan Roese
Reviewed-by: Ovidiu Panait
---
Changes in v7:
- Add Reviewe-by tag from Ovidiu
Changes in v4:
- New patch
arch/xtensa/lib/Makefile | 2 +-
arch/xtensa/lib/bdinfo.c | 22 --
2 files changed, 1 insertion(+), 23 deletions(-)
delete mode 100644 arch/xtensa/lib/bdinfo.c
diff --git a/arch/xtensa/lib/Makefile b/arch/xtensa/lib/Makefile
index ceee59b9bd..c59df7d372 100644
--- a/arch/xtensa/lib/Makefile
+++ b/arch/xtensa/lib/Makefile
@@ -5,4 +5,4 @@
obj-$(CONFIG_CMD_BOOTM) += bootm.o
-obj-y += cache.o misc.o relocate.o time.o bdinfo.o
+obj-y += cache.o misc.o relocate.o time.o
diff --git a/arch/xtensa/lib/bdinfo.c b/arch/xtensa/lib/bdinfo.c
deleted file mode 100644
index 4ec8529521..00
--- a/arch/xtensa/lib/bdinfo.c
+++ /dev/null
@@ -1,22 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * XTENSA-specific information for the 'bd' command
- *
- * (C) Copyright 2003
- * Wolfgang Denk, DENX Software Engineering, w...@denx.de.
- */
-
-#include
-#include
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int arch_setup_bdinfo(void)
-{
- struct bd_info *bd = gd->bd;
-
- bd->bi_memstart = PHYSADDR(CONFIG_SYS_SDRAM_BASE);
- bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
-
- return 0;
-}
--
2.28.0
[PATCH v7 07/10] video: cfb_console.c: Use bi_dram[] values on all platforms
All platforms support bi_dram[] since quite some time. Lets remove the
and bi_memsize values completely.
Signed-off-by: Stefan Roese
---
(no changes since v4)
Changes in v4:
- New patch
drivers/video/cfb_console.c | 8 +---
1 file changed, 1 insertion(+), 7 deletions(-)
diff --git a/drivers/video/cfb_console.c b/drivers/video/cfb_console.c
index badade353e..3f07f4eb29 100644
--- a/drivers/video/cfb_console.c
+++ b/drivers/video/cfb_console.c
@@ -1983,8 +1983,6 @@ static void *video_logo(void)
static int cfb_fb_is_in_dram(void)
{
struct bd_info *bd = gd->bd;
-#if defined(CONFIG_ARM) || defined(CONFIG_NDS32) || \
-defined(CONFIG_SANDBOX) || defined(CONFIG_X86)
ulong start, end;
int i;
@@ -1995,11 +1993,7 @@ defined(CONFIG_SANDBOX) || defined(CONFIG_X86)
(ulong)video_fb_address < end)
return 1;
}
-#else
- if ((ulong)video_fb_address >= bd->bi_memstart &&
- (ulong)video_fb_address < bd->bi_memstart + bd->bi_memsize)
- return 1;
-#endif
+
return 0;
}
--
2.28.0
[PATCH v7 04/10] global: Move from bi_memstart/memsize -> gd->ram_base/ram_size
With the planned removal of bi_memstart & bi_memsize, this patch now
moves the references to the better suiting gd->ram_base/ram_size
variables.
Signed-off-by: Stefan Roese
---
Changes in v7:
- Reword commit text as suggested by Wolfgang
Changes in v5:
- Use PHYSADDR() for xtensa, as the bi_memstart value was originally
defined this way
Changes in v4:
- New patch
api/api_platform-mips.c | 3 +--
api/api_platform-powerpc.c | 2 +-
arch/mips/lib/boot.c | 2 +-
arch/mips/lib/bootm.c| 2 +-
arch/powerpc/cpu/mpc83xx/fdt.c | 2 +-
arch/powerpc/cpu/mpc83xx/traps.c | 2 +-
arch/powerpc/cpu/mpc85xx/fdt.c | 4 ++--
arch/powerpc/cpu/mpc85xx/traps.c | 2 +-
arch/powerpc/cpu/mpc86xx/fdt.c | 4 +++-
arch/powerpc/cpu/mpc86xx/traps.c | 2 +-
arch/powerpc/cpu/mpc8xx/fdt.c| 2 +-
arch/powerpc/lib/bootm.c | 4 ++--
arch/xtensa/lib/bootm.c | 5 ++---
cmd/bedbug.c | 2 +-
14 files changed, 19 insertions(+), 19 deletions(-)
diff --git a/api/api_platform-mips.c b/api/api_platform-mips.c
index 51cd328b3d..e1509663af 100644
--- a/api/api_platform-mips.c
+++ b/api/api_platform-mips.c
@@ -24,8 +24,7 @@ DECLARE_GLOBAL_DATA_PTR;
int platform_sys_info(struct sys_info *si)
{
- platform_set_mr(si, gd->bd->bi_memstart,
- gd->bd->bi_memsize, MR_ATTR_DRAM);
+ platform_set_mr(si, gd->ram_base, gd->ram_size, MR_ATTR_DRAM);
return 1;
}
diff --git a/api/api_platform-powerpc.c b/api/api_platform-powerpc.c
index 15930cfdb6..847a4a3015 100644
--- a/api/api_platform-powerpc.c
+++ b/api/api_platform-powerpc.c
@@ -42,7 +42,7 @@ int platform_sys_info(struct sys_info *si)
si->bar = 0;
#endif
- platform_set_mr(si, gd->bd->bi_memstart, gd->bd->bi_memsize,
MR_ATTR_DRAM);
+ platform_set_mr(si, gd->ram_base, gd->ram_size, MR_ATTR_DRAM);
platform_set_mr(si, gd->bd->bi_flashstart, gd->bd->bi_flashsize,
MR_ATTR_FLASH);
platform_set_mr(si, gd->bd->bi_sramstart, gd->bd->bi_sramsize,
MR_ATTR_SRAM);
diff --git a/arch/mips/lib/boot.c b/arch/mips/lib/boot.c
index db862f6379..6ef9109022 100644
--- a/arch/mips/lib/boot.c
+++ b/arch/mips/lib/boot.c
@@ -17,7 +17,7 @@ unsigned long do_go_exec(ulong (*entry)(int, char * const []),
* whole SDRAM area, since we don't know the size of the image
* that was loaded.
*/
- flush_cache(gd->bd->bi_memstart, gd->ram_top - gd->bd->bi_memstart);
+ flush_cache(gd->ram_base, gd->ram_top - gd->ram_base);
return entry(argc, argv);
}
diff --git a/arch/mips/lib/bootm.c b/arch/mips/lib/bootm.c
index 0a13f6edb7..d5c99d891c 100644
--- a/arch/mips/lib/bootm.c
+++ b/arch/mips/lib/bootm.c
@@ -242,7 +242,7 @@ static int boot_reloc_fdt(bootm_headers_t *images)
#if CONFIG_IS_ENABLED(MIPS_BOOT_FDT) && CONFIG_IS_ENABLED(OF_LIBFDT)
int arch_fixup_fdt(void *blob)
{
- u64 mem_start = virt_to_phys((void *)gd->bd->bi_memstart);
+ u64 mem_start = virt_to_phys((void *)gd->ram_base);
u64 mem_size = gd->ram_size;
return fdt_fixup_memory_banks(blob, _start, _size, 1);
diff --git a/arch/powerpc/cpu/mpc83xx/fdt.c b/arch/powerpc/cpu/mpc83xx/fdt.c
index ebdedb2888..4ea7b27ef4 100644
--- a/arch/powerpc/cpu/mpc83xx/fdt.c
+++ b/arch/powerpc/cpu/mpc83xx/fdt.c
@@ -121,7 +121,7 @@ void ft_cpu_setup(void *blob, struct bd_info *bd)
"clock-frequency", get_serial_clock(), 1);
#endif
- fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
+ fdt_fixup_memory(blob, (u64)gd->ram_base, (u64)gd->ram_size);
#if defined(CONFIG_BOOTCOUNT_LIMIT) && \
(defined(CONFIG_QE) && !defined(CONFIG_ARCH_MPC831X))
diff --git a/arch/powerpc/cpu/mpc83xx/traps.c b/arch/powerpc/cpu/mpc83xx/traps.c
index c3cc119d65..ea8bc6c152 100644
--- a/arch/powerpc/cpu/mpc83xx/traps.c
+++ b/arch/powerpc/cpu/mpc83xx/traps.c
@@ -23,7 +23,7 @@ DECLARE_GLOBAL_DATA_PTR;
/* Returns 0 if exception not found and fixup otherwise. */
extern unsigned long search_exception_table(unsigned long);
-#define END_OF_MEM (gd->bd->bi_memstart + gd->bd->bi_memsize)
+#define END_OF_MEM (gd->ram_base + gd->ram_size)
/*
* Trap & Exception support
diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c
index 9569c1a64b..0d8353ceb2 100644
--- a/arch/powerpc/cpu/mpc85xx/fdt.c
+++ b/arch/powerpc/cpu/mpc85xx/fdt.c
@@ -672,10 +672,10 @@ void ft_cpu_setup(void *blob, struct bd_info *bd)
"clock-frequency", get_bus_freq(0), 1);
#endif
- fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
+ fdt_fixup_memory(blob, (u64)gd->ram_base, (u64)gd->ram_size);
#ifdef CONFIG_MP
- ft_fixup_cpu(blob, (u64)bd->bi_memstart + (u64)bd->bi_memsize);
+ ft_fixup_cpu(blob, (u64)gd->ram_base + (u64)gd->ram_size);
ft_fixup_num_cores(blob);
#endif
diff --git a/arch/powerpc/cpu/mpc85xx/traps.c b/arch/powerpc/cpu/mpc85xx/traps.c
index
[PATCH v7 06/10] xtensa: Remove local no-op dram_init_banksize()
When this no-op dram_init_banksize() is removed, the weak default will
be used instead, which correctly sets the bi_dram[] banksize values.
Signed-off-by: Stefan Roese
Reviewed-by: Ovidiu Panait
---
Changes in v7:
- Add Reviewe-by tag from Ovidiu
Changes in v5:
- New patch to fix the failing "test.py xtfpga" CI test
board/cadence/xtfpga/xtfpga.c | 5 -
1 file changed, 5 deletions(-)
diff --git a/board/cadence/xtfpga/xtfpga.c b/board/cadence/xtfpga/xtfpga.c
index 4b49b6e5c8..5811c43142 100644
--- a/board/cadence/xtfpga/xtfpga.c
+++ b/board/cadence/xtfpga/xtfpga.c
@@ -49,11 +49,6 @@ int checkboard(void)
return 0;
}
-int dram_init_banksize(void)
-{
- return 0;
-}
-
int board_postclk_init(void)
{
/*
--
2.28.0
[PATCH v7 01/10] CONFIG_NR_DRAM_BANKS: Remove unreferenced code as its always defined
Since commit 86cf1c82850f ("configs: Migrate CONFIG_NR_DRAM_BANKS") &
commit 999a772d9f24 ("Kconfig: Migrate CONFIG_NR_DRAM_BANKS"),
CONFIG_NR_DRAM_BANKS is always defined with a value (4 is default).
It makes no sense to still carry code that is guarded with
"#ifndef CONFIG_NR_DRAM_BANKS" (and similar). This patch removes
all these unreferenced code paths.
Signed-off-by: Stefan Roese
Reviewed-by: Pali Rohár
Reviewed-by: Andy Shevchenko
---
(no changes since v5)
Changes in v5:
- Add Reviewed-by tag from Pali & Andy
- Move "bd" assignment as suggested by Andy
Changes in v4:
- Only remove dead code with CONFIG_NR_DRAM_BANKS always defined
arch/x86/cpu/broadwell/cpu_from_spl.c | 2 --
board/xilinx/zynqmp/zynqmp.c | 2 --
cmd/bdinfo.c | 2 --
common/board_f.c | 7 +-
common/image.c| 3 +--
common/init/handoff.c | 33 +++
drivers/pci/pci-uclass.c | 18 ++-
include/asm-generic/u-boot.h | 2 --
include/handoff.h | 2 --
lib/fdtdec.c | 5
lib/lmb.c | 9 ++--
11 files changed, 19 insertions(+), 66 deletions(-)
diff --git a/arch/x86/cpu/broadwell/cpu_from_spl.c
b/arch/x86/cpu/broadwell/cpu_from_spl.c
index 6567d50653..4d4cdafa2b 100644
--- a/arch/x86/cpu/broadwell/cpu_from_spl.c
+++ b/arch/x86/cpu/broadwell/cpu_from_spl.c
@@ -53,14 +53,12 @@ void board_debug_uart_init(void)
int dram_init_banksize(void)
{
-#ifdef CONFIG_NR_DRAM_BANKS
struct spl_handoff *ho;
ho = bloblist_find(BLOBLISTT_SPL_HANDOFF, sizeof(*ho));
if (!ho)
return log_msg_ret("Missing SPL hand-off info", -ENOENT);
handoff_load_dram_banks(ho);
-#endif
return 0;
}
diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c
index ebb7172908..4cc5cb6fd7 100644
--- a/board/xilinx/zynqmp/zynqmp.c
+++ b/board/xilinx/zynqmp/zynqmp.c
@@ -467,10 +467,8 @@ int dram_init(void)
#else
int dram_init_banksize(void)
{
-#if defined(CONFIG_NR_DRAM_BANKS)
gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].size = get_effective_memsize();
-#endif
mem_map_fill();
diff --git a/cmd/bdinfo.c b/cmd/bdinfo.c
index 9593b345a3..9e230f23cb 100644
--- a/cmd/bdinfo.c
+++ b/cmd/bdinfo.c
@@ -49,7 +49,6 @@ void bdinfo_print_mhz(const char *name, unsigned long hz)
static void print_bi_dram(const struct bd_info *bd)
{
-#ifdef CONFIG_NR_DRAM_BANKS
int i;
for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) {
@@ -59,7 +58,6 @@ static void print_bi_dram(const struct bd_info *bd)
bdinfo_print_num("-> size", bd->bi_dram[i].size);
}
}
-#endif
}
__weak void arch_print_bdinfo(void)
diff --git a/common/board_f.c b/common/board_f.c
index 3932e0c69d..d1f0f9af08 100644
--- a/common/board_f.c
+++ b/common/board_f.c
@@ -215,8 +215,6 @@ static int announce_dram_init(void)
static int show_dram_config(void)
{
unsigned long long size;
-
-#ifdef CONFIG_NR_DRAM_BANKS
int i;
debug("\nRAM Configuration:\n");
@@ -229,9 +227,6 @@ static int show_dram_config(void)
#endif
}
debug("\nDRAM: ");
-#else
- size = gd->ram_size;
-#endif
print_size(size, "");
board_add_ram_info(0);
@@ -242,7 +237,7 @@ static int show_dram_config(void)
__weak int dram_init_banksize(void)
{
-#if defined(CONFIG_NR_DRAM_BANKS) && defined(CONFIG_SYS_SDRAM_BASE)
+#if defined(CONFIG_SYS_SDRAM_BASE)
gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].size = get_effective_memsize();
#endif
diff --git a/common/image.c b/common/image.c
index 9d7d5c17d1..2ed46f7685 100644
--- a/common/image.c
+++ b/common/image.c
@@ -685,8 +685,7 @@ phys_size_t env_get_bootm_size(void)
return tmp;
}
-#if (defined(CONFIG_ARM) || defined(CONFIG_MICROBLAZE)) && \
- defined(CONFIG_NR_DRAM_BANKS)
+#if defined(CONFIG_ARM) || defined(CONFIG_MICROBLAZE)
start = gd->bd->bi_dram[0].start;
size = gd->bd->bi_dram[0].size;
#else
diff --git a/common/init/handoff.c b/common/init/handoff.c
index e00b43e6a7..62071bd017 100644
--- a/common/init/handoff.c
+++ b/common/init/handoff.c
@@ -12,18 +12,15 @@ DECLARE_GLOBAL_DATA_PTR;
void handoff_save_dram(struct spl_handoff *ho)
{
+ struct bd_info *bd = gd->bd;
+ int i;
+
ho->ram_size = gd->ram_size;
-#ifdef CONFIG_NR_DRAM_BANKS
- {
- struct bd_info *bd = gd->bd;
- int i;
-
- for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
- ho->ram_bank[i].start = bd->bi_dram[i].start;
- ho->ram_bank[i].size = bd->bi_dram[i].size;
- }
+
+ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+ ho->ram_bank[i].start =
[PATCH v7 03/10] board_f: Add default values for bi_dram[] in dram_init_banksize()
Remove the bi_memstart / bi_memsize assignment in setup_bdinfo() and
make sure, that bd_dram[] is always configured in the weak default
implementation of dram_init_banksize(), when CONFIG_SYS_SDRAM_BASE is
not set.
Signed-off-by: Stefan Roese
Reviewed-by: Ovidiu Panait
---
Changes in v7:
- Add Reviewe-by tag from Ovidiu
Changes in v6:
- Simplify dram_init_banksize() even more as suggested by Daniel
Changes in v4:
- New patch
common/board_f.c | 7 +--
1 file changed, 1 insertion(+), 6 deletions(-)
diff --git a/common/board_f.c b/common/board_f.c
index d1f0f9af08..8a43df97e4 100644
--- a/common/board_f.c
+++ b/common/board_f.c
@@ -237,10 +237,8 @@ static int show_dram_config(void)
__weak int dram_init_banksize(void)
{
-#if defined(CONFIG_SYS_SDRAM_BASE)
- gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_dram[0].start = gd->ram_base;
gd->bd->bi_dram[0].size = get_effective_memsize();
-#endif
return 0;
}
@@ -602,9 +600,6 @@ int setup_bdinfo(void)
{
struct bd_info *bd = gd->bd;
- bd->bi_memstart = gd->ram_base; /* start of memory */
- bd->bi_memsize = gd->ram_size; /* size in bytes */
-
if (IS_ENABLED(CONFIG_SYS_HAS_SRAM)) {
bd->bi_sramstart = CONFIG_SYS_SRAM_BASE; /* start of SRAM */
bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE; /* size of SRAM */
--
2.28.0
[PATCH v7 02/10] image: Use gd->ram_base/_size in env_get_bootm_size()
Use only gd->ram_base/_size in env_get_bootm_size() instead of bi_dram[]
in some cases and bi_memstart in others.
Signed-off-by: Stefan Roese
---
(no changes since v4)
Changes in v4:
- New patch
common/image.c | 9 ++---
1 file changed, 2 insertions(+), 7 deletions(-)
diff --git a/common/image.c b/common/image.c
index 2ed46f7685..6f68b13fce 100644
--- a/common/image.c
+++ b/common/image.c
@@ -685,13 +685,8 @@ phys_size_t env_get_bootm_size(void)
return tmp;
}
-#if defined(CONFIG_ARM) || defined(CONFIG_MICROBLAZE)
- start = gd->bd->bi_dram[0].start;
- size = gd->bd->bi_dram[0].size;
-#else
- start = gd->bd->bi_memstart;
- size = gd->bd->bi_memsize;
-#endif
+ start = gd->ram_base;
+ size = gd->ram_size;
s = env_get("bootm_low");
if (s)
--
2.28.0
Re: Aw: Re: [PATCH v2 09/11] arm: dts: mt7622: add sata- and asm_sel nodes
On Wed, 2020-08-19 at 12:58 +0200, Frank Wunderlich wrote:
> Hi
>
> > Gesendet: Mittwoch, 19. August 2020 um 10:54 Uhr
> > Von: "Chunfeng Yun"
> > > + sata_phy: sata-phy@1a243000 {
> > > + compatible = "mediatek,generic-tphy-v1";
> > > + #address-cells = <1>;
> > > + #size-cells = <1>;
> > > + ranges;
> > we can use ranges with parameters if you send next version, otherwise no
> > change is also fine to me.
> >
> > ranges=<0 0x1a243000 0x100>;
>
> i took the dts-part from linux where ranges is also empty
>
> https://elixir.bootlin.com/linux/latest/source/arch/arm64/boot/dts/mediatek/mt7622.dtsi#L880
>
I think it follows the early dt-binding doc of tphy, I modify it later.
> why should ranges have a value when i recently removed the reg (after making
> it optional)?
Both are ok, but prefer to use translation way:)
Without shared registers, it's simple and clear to use address
translation from parent-bus-address to child-bus-address.
e.g. subnode: usb-phy@0, usb-phy@1000, they tell us the offset at the
same time.
>
> > For phy part,
> > Reviewed-by: Chunfeng Yun
>
> any issues in sata-node/gpio-hog?
Also looks good to me
>
> regards Frank
Re: [PATCH v3 1/1] cmd: provide command sbi
Hi Heinrich,
On Wed, Aug 19, 2020 at 6:29 PM Heinrich Schuchardt wrote:
>
> Provide a command to display information about the SBI implementation.
>
> The output might look like:
>
> => sbi
> SBI 0.2
> OpenSBI
> Extensions:
> sbi_set_timer
> sbi_console_putchar
> sbi_console_getchar
> sbi_clear_ipi
> sbi_send_ipi
> sbi_remote_fence_i
> sbi_remote_sfence_vma
> sbi_remote_sfence_vma_asid
> sbi_shutdown
> SBI Base Functionality
> Timer Extension
> IPI Extension
> RFENCE Extension
> Hart State Management Extension
>
> The command can be used to construct a unit test checking that the
> communication with the SEE is working.
>
> Signed-off-by: Heinrich Schuchardt
> ---
> v3:
> add dependency on CONFIG_SBI_V02
> use lower case for sbi in Kconfig
> v2:
> provide a non-blank long help text
> ---
> arch/riscv/include/asm/sbi.h | 2 +
> arch/riscv/lib/sbi.c | 36
> cmd/Kconfig | 6 +++
> cmd/riscv/Makefile | 1 +
> cmd/riscv/sbi.c | 82
> 5 files changed, 127 insertions(+)
> create mode 100644 cmd/riscv/sbi.c
>
> diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h
> index 08e1ac0c0e..53ca316180 100644
> --- a/arch/riscv/include/asm/sbi.h
> +++ b/arch/riscv/include/asm/sbi.h
> @@ -115,6 +115,8 @@ void sbi_remote_sfence_vma_asid(const unsigned long
> *hart_mask,
> unsigned long asid);
> #endif
> void sbi_set_timer(uint64_t stime_value);
> +long sbi_get_spec_version(void);
> +int sbi_get_impl_id(void);
> int sbi_probe_extension(int ext);
>
> #endif
> diff --git a/arch/riscv/lib/sbi.c b/arch/riscv/lib/sbi.c
> index 8fbc23839d..920889ed13 100644
> --- a/arch/riscv/lib/sbi.c
> +++ b/arch/riscv/lib/sbi.c
> @@ -53,6 +53,42 @@ void sbi_set_timer(uint64_t stime_value)
> #endif
> }
>
> +/**
> + * sbi_get_spec_version() - get current SBI specification version
> + *
> + * Return: version id
> + */
> +long sbi_get_spec_version(void)
> +{
> + struct sbiret ret;
> +
> + ret = sbi_ecall(SBI_EXT_BASE, SBI_EXT_BASE_GET_SPEC_VERSION,
> + 0, 0, 0, 0, 0, 0);
> + if (!ret.error)
> + if (ret.value)
> + return ret.value;
> +
> + return -ENOTSUPP;
> +}
> +
> +/**
> + * sbi_get_impl_id() - get SBI implemenation ID
> + *
> + * Return: implementation ID
> + */
> +int sbi_get_impl_id(void)
> +{
> + struct sbiret ret;
> +
> + ret = sbi_ecall(SBI_EXT_BASE, SBI_EXT_BASE_GET_IMP_ID,
> + 0, 0, 0, 0, 0, 0);
> + if (!ret.error)
> + if (ret.value)
> + return ret.value;
> +
> + return -ENOTSUPP;
> +}
> +
> /**
> * sbi_probe_extension() - Check if an SBI extension ID is supported or not.
> * @extid: The extension ID to be probed.
> diff --git a/cmd/Kconfig b/cmd/Kconfig
> index 9ad511aa17..8feeb0ddb0 100644
> --- a/cmd/Kconfig
> +++ b/cmd/Kconfig
> @@ -270,6 +270,12 @@ config SPL_CMD_TLV_EEPROM
> help
> Read system EEPROM data block in ONIE Tlvinfo format from SPL.
>
> +config CMD_SBI
> + bool "sbi information"
nits: what I actually pointed out is not the case, but the prompt
being the command name, so here is:
bool "sbi"
> + depends on RISCV_SMODE && SBI_V02
> + help
> + Display information about the SBI implementation.
> +
> endmenu
>
> menu "Boot commands"
> diff --git a/cmd/riscv/Makefile b/cmd/riscv/Makefile
> index 24df023ece..1e6ac364e3 100644
> --- a/cmd/riscv/Makefile
> +++ b/cmd/riscv/Makefile
> @@ -1,3 +1,4 @@
> # SPDX-License-Identifier: GPL-2.0+
>
> obj-$(CONFIG_CMD_EXCEPTION) += exception.o
> +obj-$(CONFIG_CMD_SBI) += sbi.o
> diff --git a/cmd/riscv/sbi.c b/cmd/riscv/sbi.c
> new file mode 100644
> index 00..7c9151f436
> --- /dev/null
> +++ b/cmd/riscv/sbi.c
> @@ -0,0 +1,82 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * The 'sbi' command displays information about the SBI implementation.
> + *
> + * Copyright (c) 2020, Heinrich Schuchardt
> + */
> +
> +#include
> +#include
> +#include
> +
> +struct sbi_ext {
> + const u32 id;
> + const char *name;
> +};
> +
> +static struct sbi_ext extensions[] = {
> + { 0x, "sbi_set_timer" },
> + { 0x0001, "sbi_console_putchar" },
> + { 0x0002, "sbi_console_getchar" },
> + { 0x0003, "sbi_clear_ipi" },
> + { 0x0004, "sbi_send_ipi" },
> + { 0x0005, "sbi_remote_fence_i" },
> + { 0x0006, "sbi_remote_sfence_vma" },
> + { 0x0007, "sbi_remote_sfence_vma_asid" },
> + { 0x0008, "sbi_shutdown" },
> + { 0x0010, "SBI Base Functionality" },
> + { 0x54494D45, "Timer Extension" },
> + { 0x00735049, "IPI Extension" },
> + { 0x52464E43, "RFENCE Extension" },
> + { 0x0048534D, "Hart State Management Extension" },
> +};
> +
> +static
Re: [PATCH] arm: dts: fix ast2500-evb inclusion for correct target
Adding Ryan and Chiawei to the list. On 8/17/2020 5:53 PM, Thirupathaiah Annapureddy wrote: > Include ast2500-evb.dtb for CONFIG_TARGET_EVB_AST2500 instead of > for all aspeed targets. > > Signed-off-by: Thirupathaiah Annapureddy --- > arch/arm/dts/Makefile | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile > index 7e29b9096b..d019f26983 100644 > --- a/arch/arm/dts/Makefile > +++ b/arch/arm/dts/Makefile > @@ -938,7 +938,7 @@ dtb-$(CONFIG_ARCH_BCM6858) += \ > > dtb-$(CONFIG_TARGET_BCMNS3) += ns3-board.dtb > > -dtb-$(CONFIG_ARCH_ASPEED) += ast2500-evb.dtb > +dtb-$(CONFIG_TARGET_EVB_AST2500) += ast2500-evb.dtb > > dtb-$(CONFIG_ARCH_STI) += stih410-b2260.dtb > >
Re: [v3, 00/11] mmc: fsl_esdhc: support eMMC HS200/HS400 modes
Hi Yangbo, On 8/18/20 1:35 PM, Y.b. Lu wrote: > Any commets on the v3 patch-set. > Thanks! Sorry for late. I will test with your patch on my target. Today, i will reply about your patch. Best Regards, Jaehoon Chung > > Best regards, > Yangbo Lu > >> -Original Message- >> From: Yangbo Lu >> Sent: Thursday, July 23, 2020 12:30 PM >> To: u-boot@lists.denx.de; Peng Fan ; Priyanka Jain >> ; 'Jaehoon Chung' >> Cc: Y.b. Lu >> Subject: [v3, 00/11] mmc: fsl_esdhc: support eMMC HS200/HS400 modes >> >> This patch-set is to support eMMC HS200 and HS400 speed modes for >> eSDHC, and enable them on LX2160ARDB board. >> >> CI build link >> https://protect2.fireeye.com/v1/url?k=035d63a4-5e936277-035ce8eb-000babff317b-31e05acd460d6c4f=1=0b204f55-99b2-446d-9800-90ff26476621=https%3A%2F%2Feur01.safelinks.protection.outlook.com%2F%3Furl%3Dhttps%253A%252F%252Ftravis-ci >> .org%2Fgithub%2Fyangbolu1991%2Fu-boot-test%2Fbuilds%2F710977092 >> mp;data=02%7C01%7Cyangbo.lu%40nxp.com%7Cad44ad82358841b1750d08 >> d82ec207a0%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C63731 >> 0758167126235sdata=u8fiHRayfKhk%2FiFGjXItjlHmyWWk9MMqbWHz >> WeId60c%3Dreserved=0 >> >> Changes for v2: >> - Added two patches to fix stability issue. >> Changes for v3: >> - Explained more in commit messages. >> - Added HS400 exit code for downgrade. >> >> Yangbo Lu (11): >> mmc: add a reinit() API >> mmc: fsl_esdhc: add a reinit() callback >> mmc: fsl_esdhc: support tuning for eMMC HS200 >> mmc: fsl_esdhc: clean TBCTL[TB_EN] manually during init >> mmc: add a hs400_tuning flag >> mmc: add a mmc_hs400_prepare_ddr() interface >> mmc: fsl_esdhc: support eMMC HS400 mode >> mmc: fsl_esdhc: fix mmc->clock with actual clock >> mmc: fsl_esdhc: fix eMMC HS400 stability issue >> arm: dts: lx2160ardb: support eMMC HS400 mode >> configs: lx2160ardb: enable eMMC HS400 mode support >> >> arch/arm/dts/fsl-lx2160a-rdb.dts | 2 + >> configs/lx2160ardb_tfa_SECURE_BOOT_defconfig | 1 + >> configs/lx2160ardb_tfa_defconfig | 1 + >> configs/lx2160ardb_tfa_stmm_defconfig| 1 + >> drivers/mmc/fsl_esdhc.c | 176 >> ++- >> drivers/mmc/mmc-uclass.c | 30 + >> drivers/mmc/mmc.c| 12 +- >> include/fsl_esdhc.h | 29 - >> include/mmc.h| 26 +++- >> 9 files changed, 268 insertions(+), 10 deletions(-) >> >> -- >> 2.7.4 > >
Re: [PATCH 2/3] arm: dts: k3-j7200-r5: Add fs_loader node
Hi Lokesh,
On 8/18/20 2:09 PM, Suman Anna wrote:
> Add a generic fs_loader node to the K3 J7200 R5 common board dts
> file and use it as the chosen firmware-loader so that it can be
> used for loading various firmwares from a boot media/filesystem
> in R5 SPL on K3 J7200 EVM.
>
> Signed-off-by: Suman Anna
> ---
> arch/arm/dts/k3-j7200-r5-common-proc-board.dts | 6 ++
> 1 file changed, 6 insertions(+)
>
> diff --git a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts
> b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts
> index f5e4166926dc..b8c8487f3afe 100644
> --- a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts
> +++ b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts
> @@ -18,6 +18,12 @@
> chosen {
> stdout-path = _uart0;
> tick-timer =
> + firmware-loader = _loader0;
> + };
> +
> + fs_loader0: fs_loader@0 {
I realized I used underscore in the node name. Can you fix up the node name
while applying, or do you want me to send a v2?
regards
Suman
> + u-boot,dm-pre-reloc;
> + compatible = "u-boot,fs-loader";
> };
>
> a72_0: a72@0 {
>
Re: [PATCH v3 1/1] cmd: provide command sbi
On Wed, Aug 19, 2020 at 3:29 AM Heinrich Schuchardt wrote:
>
> Provide a command to display information about the SBI implementation.
>
> The output might look like:
>
> => sbi
> SBI 0.2
> OpenSBI
> Extensions:
> sbi_set_timer
> sbi_console_putchar
> sbi_console_getchar
> sbi_clear_ipi
> sbi_send_ipi
> sbi_remote_fence_i
> sbi_remote_sfence_vma
> sbi_remote_sfence_vma_asid
> sbi_shutdown
> SBI Base Functionality
> Timer Extension
> IPI Extension
> RFENCE Extension
> Hart State Management Extension
>
> The command can be used to construct a unit test checking that the
> communication with the SEE is working.
>
> Signed-off-by: Heinrich Schuchardt
> ---
> v3:
> add dependency on CONFIG_SBI_V02
> use lower case for sbi in Kconfig
> v2:
> provide a non-blank long help text
> ---
> arch/riscv/include/asm/sbi.h | 2 +
> arch/riscv/lib/sbi.c | 36
> cmd/Kconfig | 6 +++
> cmd/riscv/Makefile | 1 +
> cmd/riscv/sbi.c | 82
> 5 files changed, 127 insertions(+)
> create mode 100644 cmd/riscv/sbi.c
>
> diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h
> index 08e1ac0c0e..53ca316180 100644
> --- a/arch/riscv/include/asm/sbi.h
> +++ b/arch/riscv/include/asm/sbi.h
> @@ -115,6 +115,8 @@ void sbi_remote_sfence_vma_asid(const unsigned long
> *hart_mask,
> unsigned long asid);
> #endif
> void sbi_set_timer(uint64_t stime_value);
> +long sbi_get_spec_version(void);
> +int sbi_get_impl_id(void);
> int sbi_probe_extension(int ext);
>
> #endif
> diff --git a/arch/riscv/lib/sbi.c b/arch/riscv/lib/sbi.c
> index 8fbc23839d..920889ed13 100644
> --- a/arch/riscv/lib/sbi.c
> +++ b/arch/riscv/lib/sbi.c
> @@ -53,6 +53,42 @@ void sbi_set_timer(uint64_t stime_value)
> #endif
> }
>
> +/**
> + * sbi_get_spec_version() - get current SBI specification version
> + *
> + * Return: version id
> + */
> +long sbi_get_spec_version(void)
> +{
> + struct sbiret ret;
> +
> + ret = sbi_ecall(SBI_EXT_BASE, SBI_EXT_BASE_GET_SPEC_VERSION,
> + 0, 0, 0, 0, 0, 0);
> + if (!ret.error)
> + if (ret.value)
> + return ret.value;
> +
> + return -ENOTSUPP;
> +}
> +
> +/**
> + * sbi_get_impl_id() - get SBI implemenation ID
> + *
> + * Return: implementation ID
> + */
> +int sbi_get_impl_id(void)
> +{
> + struct sbiret ret;
> +
> + ret = sbi_ecall(SBI_EXT_BASE, SBI_EXT_BASE_GET_IMP_ID,
> + 0, 0, 0, 0, 0, 0);
> + if (!ret.error)
> + if (ret.value)
> + return ret.value;
> +
> + return -ENOTSUPP;
> +}
> +
> /**
> * sbi_probe_extension() - Check if an SBI extension ID is supported or not.
> * @extid: The extension ID to be probed.
> diff --git a/cmd/Kconfig b/cmd/Kconfig
> index 9ad511aa17..8feeb0ddb0 100644
> --- a/cmd/Kconfig
> +++ b/cmd/Kconfig
> @@ -270,6 +270,12 @@ config SPL_CMD_TLV_EEPROM
> help
> Read system EEPROM data block in ONIE Tlvinfo format from SPL.
>
> +config CMD_SBI
> + bool "sbi information"
> + depends on RISCV_SMODE && SBI_V02
> + help
> + Display information about the SBI implementation.
> +
> endmenu
>
> menu "Boot commands"
> diff --git a/cmd/riscv/Makefile b/cmd/riscv/Makefile
> index 24df023ece..1e6ac364e3 100644
> --- a/cmd/riscv/Makefile
> +++ b/cmd/riscv/Makefile
> @@ -1,3 +1,4 @@
> # SPDX-License-Identifier: GPL-2.0+
>
> obj-$(CONFIG_CMD_EXCEPTION) += exception.o
> +obj-$(CONFIG_CMD_SBI) += sbi.o
> diff --git a/cmd/riscv/sbi.c b/cmd/riscv/sbi.c
> new file mode 100644
> index 00..7c9151f436
> --- /dev/null
> +++ b/cmd/riscv/sbi.c
> @@ -0,0 +1,82 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * The 'sbi' command displays information about the SBI implementation.
> + *
> + * Copyright (c) 2020, Heinrich Schuchardt
> + */
> +
> +#include
> +#include
> +#include
> +
> +struct sbi_ext {
> + const u32 id;
> + const char *name;
> +};
> +
> +static struct sbi_ext extensions[] = {
> + { 0x, "sbi_set_timer" },
> + { 0x0001, "sbi_console_putchar" },
> + { 0x0002, "sbi_console_getchar" },
> + { 0x0003, "sbi_clear_ipi" },
> + { 0x0004, "sbi_send_ipi" },
> + { 0x0005, "sbi_remote_fence_i" },
> + { 0x0006, "sbi_remote_sfence_vma" },
> + { 0x0007, "sbi_remote_sfence_vma_asid" },
> + { 0x0008, "sbi_shutdown" },
> + { 0x0010, "SBI Base Functionality" },
> + { 0x54494D45, "Timer Extension" },
> + { 0x00735049, "IPI Extension" },
> + { 0x52464E43, "RFENCE Extension" },
> + { 0x0048534D, "Hart State Management Extension" },
> +};
> +
> +static int do_sbi(struct cmd_tbl *cmdtp, int flag, int argc,
> + char *const argv[])
> +{
> + int i;
> + long
Re: Revert "ARM: socfpga: Remove socfpga_sdram_apply_static_cfg()
On Wed, Aug 19, 2020 at 09:28:39PM +0200, Marek Vasut wrote: Is the F2SDRAM port enabled in your case ? Is there a way I can check this via software? Unfortunately I do not have access to Quartus/Qsys files, nor the person who did the design. Ralph
Re: [PATCH] arm: imx6q_logic: Enable I2C PMIC
Hi Adam, On Wed, Aug 19, 2020 at 9:13 AM Adam Ford wrote: > The issue I am seeing is U-Boot specific, because Linux doesn't power > this rail down. I'd rather not keep this regulator-always-on in > Linux, and I want to keep the devices trees between U-Boot and Linux Yes, I also prefer to always keep them in sync. > the same. In the device tree, I have associated this rail to the SDHC > interface , but for some reason, U-Boot still powers it down, so when > it tries to go and read from the SD card, the system hangs. Interesting. Then this needs to be investigated, otherwise we will just paper over the real problem without understanding its root cause. Why is U-Boot powering the regulator down? The device tree representation of the regulators is agnostic to U-Boot or kernel, as it just represents the hardware, so I prefer that the correct regulator description is passed in the main device tree instead of hacking the specific U-Boot device tree.
Re: [PATCH 4/5] usb: xhci: Add Qualcomm DWC3 xHCI driver
On 8/19/20 8:22 PM, Tom Rini wrote:
[...]
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
Please keep the list sorted.
>> +/* Declare global data pointer */
>> +DECLARE_GLOBAL_DATA_PTR;
>> +
>> +struct ipq_xhci_platdata {
>> +fdt_addr_t hcd_base;
>> +unsigned int rst_ctrl;
>> +unsigned int hs_only;
bool ...
>> +};
>> +
>> +struct ipq_xhci {
>> +struct ipq_xhci_platdata usb_plat;
>> +struct xhci_ctrl ctrl;
>> +struct udevice* dev;
>> +struct xhci_hccr *hcd;
>> +struct dwc3 *dwc3_reg;
>> +};
>> +
>> +void ipq_reset_usb_phy(void *data)
>> +{
>> +unsigned int gcc_rst_ctrl;
>> +struct ipq_xhci_platdata *platdata;
>> +struct ipq_xhci *ipq = (struct ipq_xhci *)data;
Pass struct ipg_xhci pointer in instead of void *.
>> +platdata = dev_get_platdata(ipq->dev);
>> +if (platdata == NULL) {
>> +printf("Error: %s Failed\n", __func__);
dev_err() here.
>> +return;
>> +}
Shouldn't this be part of a PHY driver ?
>> +gcc_rst_ctrl = platdata->rst_ctrl;
>> +
>> +if (gcc_rst_ctrl) {
>> +/* assert HS PHY POR reset */
>> +setbits_le32(gcc_rst_ctrl, 0x10);
>> +mdelay(10);
Does it really need such lengthy delays here ?
>> +/* assert HS PHY SRIF reset */
>> +setbits_le32(gcc_rst_ctrl, 0x4);
>> +mdelay(10);
>> +
>> +/* deassert HS PHY SRIF reset and program HS PHY registers */
>> +clrbits_le32(gcc_rst_ctrl, 0x4);
>> +mdelay(10);
>> +
>> +/* de-assert USB3 HS PHY POR reset */
>> +clrbits_le32(gcc_rst_ctrl, 0x10);
This BIT(4) should likely be #define'd as a macro , same for the others.
>> +mdelay(10);
>> +
>> +if (!platdata->hs_only) {
>> +/* assert SS PHY POR reset */
>> +setbits_le32(gcc_rst_ctrl, 0x20);
>> +mdelay(10);
>> +
>> +/* deassert SS PHY POR reset */
>> +clrbits_le32(gcc_rst_ctrl, 0x20);
>> +}
>> +}
>> +}
>> +
>> +static int ipq_xhci_core_init(struct ipq_xhci *ipq)
>> +{
>> +int ret = 0;
>> +
>> +ipq_reset_usb_phy((void *)ipq);
>> +
>> +ret = dwc3_core_init(ipq->dwc3_reg);
>> +if (ret) {
>> +debug("%s:failed to initialize core\n", __func__);
dev_dbg()
>> +return ret;
>> +}
>> +
>> +/* We are hard-coding DWC3 core to Host Mode */
>> +dwc3_set_mode(ipq->dwc3_reg, DWC3_GCTL_PRTCAP_HOST);
>> +
>> +return ret;
>> +}
>> +
>> +static void ipq_xhci_core_exit(struct ipq_xhci *ipq)
>> +{
Is some code missing here ?
>> +}
>> +
>> +static int xhci_usb_remove(struct udevice *dev)
>> +{
>> +int ret;
>> +ret = xhci_deregister(dev);
>> +
>> +if (ret != 0) {
>> +debug("%s:xhci deregistration failed\n", __func__);
dev_dbg()
>> +return ret;
>> +}
>> +
>> +ipq_xhci_core_exit(dev_get_priv(dev));
>> +
>> +return 0;
return ipg_xhci_core_exit() to propagate the error value (if any).
>> +}
[...]
Re: Revert "ARM: socfpga: Remove socfpga_sdram_apply_static_cfg()
On 8/19/20 8:35 PM, Ralph Siemsen wrote: > Hi Wolfgang et al., > > On Fri, Aug 07, 2020 at 05:49:13PM +0200, Wolfgang Grandegger wrote: >> >> >> Am 07.08.20 um 17:05 schrieb Dinh Nguyen: >>> >>> On 8/6/20 7:36 AM, Wolfgang Grandegger wrote: Am 06.08.20 um 13:04 schrieb Marek Vasut: > On 8/6/20 12:53 PM, Wolfgang Grandegger wrote: >> This reverts commit c5f4b805755912a3d2fe20f014b6b6ab0473bd73. >> >> Conflicts: >> arch/arm/mach-socfpga/misc_gen5.c >> >> Without socfpga_sdram_apply_static_cfg(), the system hangs when Linux >> calls altvipfb2_start_hw() of the Intel Video and Image >> Processing(VIP) >> Frame Buffer II driver (drivers/video/fbdev/altvipfb2.c) > > There is no such driver in mainline U-Boot or Linux. It's a simple frame buffer driver from linux-socfpga for the IP core Intel Video and Image Processing(VIP) Frame Buffer II. > > Just a note that I am seeing the same problem, also on Cyclone V, but > with a different IP block in the FPGA. I'm using the Altera/Intel triple > speed Ethernet, which is supported by drivers/net/altera_tse.c driver. > > With earlier u-boot (tested 2018.03) it worked fine. But with 2020.04 > and 2020.07 the system hangs as soon as I do "ifconfig eth0 up". This > only happens on cold boot; on warm reboot the eth0 port works fine. > Reverting c5f4b805755912a3d2fe20 fixes the problem. Is the F2SDRAM port enabled in your case ?
[PATCH] ARM: imx6q_logic: Fix broken booting by moving fdt_addr_r address
The loading address is too close to the kernel address, so newer kernels may overlap memory space, so loading the device tree may corrupt zImage. This patch moves the fdt_addr_r to 0x1800 which is also consistent with some other i.MX6Q boards. Signed-off-by: Adam Ford diff --git a/include/configs/imx6_logic.h b/include/configs/imx6_logic.h index 63662dd18d..58862e4c49 100644 --- a/include/configs/imx6_logic.h +++ b/include/configs/imx6_logic.h @@ -34,7 +34,7 @@ "script=boot.scr\0" \ "image=zImage\0" \ "bootm_size=0x1000\0" \ - "fdt_addr_r=0x1300\0" \ + "fdt_addr_r=0x1800\0" \ "ramdisk_addr_r=0x1400\0" \ "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ "ramdisk_file=rootfs.cpio.uboot\0" \ -- 2.25.1
Re: Revert "ARM: socfpga: Remove socfpga_sdram_apply_static_cfg()
Hi Wolfgang et al., On Fri, Aug 07, 2020 at 05:49:13PM +0200, Wolfgang Grandegger wrote: Am 07.08.20 um 17:05 schrieb Dinh Nguyen: On 8/6/20 7:36 AM, Wolfgang Grandegger wrote: Am 06.08.20 um 13:04 schrieb Marek Vasut: On 8/6/20 12:53 PM, Wolfgang Grandegger wrote: This reverts commit c5f4b805755912a3d2fe20f014b6b6ab0473bd73. Conflicts: arch/arm/mach-socfpga/misc_gen5.c Without socfpga_sdram_apply_static_cfg(), the system hangs when Linux calls altvipfb2_start_hw() of the Intel Video and Image Processing(VIP) Frame Buffer II driver (drivers/video/fbdev/altvipfb2.c) There is no such driver in mainline U-Boot or Linux. It's a simple frame buffer driver from linux-socfpga for the IP core Intel Video and Image Processing(VIP) Frame Buffer II. Just a note that I am seeing the same problem, also on Cyclone V, but with a different IP block in the FPGA. I'm using the Altera/Intel triple speed Ethernet, which is supported by drivers/net/altera_tse.c driver. With earlier u-boot (tested 2018.03) it worked fine. But with 2020.04 and 2020.07 the system hangs as soon as I do "ifconfig eth0 up". This only happens on cold boot; on warm reboot the eth0 port works fine. Reverting c5f4b805755912a3d2fe20 fixes the problem. Regards, Ralph
Re: [PATCH 4/5] usb: xhci: Add Qualcomm DWC3 xHCI driver
On Mon, Aug 17, 2020 at 12:36:05PM +0200, Robert Marko wrote:
> Add driver for Qualcomm DWC3 based dual role xHCI USB controller.
> Currently tested on IPQ40xx, but should support other Qualcomm SoC families
> as well.
>
> Signed-off-by: Robert Marko
> ---
> MAINTAINERS | 2 +
> .../usb/qcom-dwc3-ipq.txt | 25 +++
> drivers/usb/host/Kconfig | 6 +
> drivers/usb/host/Makefile | 1 +
> drivers/usb/host/xhci-ipq.c | 193 ++
> 5 files changed, 227 insertions(+)
> create mode 100644 doc/device-tree-bindings/usb/qcom-dwc3-ipq.txt
> create mode 100644 drivers/usb/host/xhci-ipq.c
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 1a55327406..0e4e281d9b 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -239,6 +239,8 @@ S:Maintained
> F: arch/arm/mach-ipq40xx/
> F: include/dt-bindings/reset/qcom,ipq40xx-reset.h
> F: drivers/reset/reset-ipq40xx.c
> +F: doc/device-tree-bindings/usb/qcom-dwc3-ipq.txt
> +F: drivers/usb/host/xhci-ipq.c
>
> ARM MARVELL KIRKWOOD ARMADA-XP ARMADA-38X ARMADA-37XX ARMADA-7K/8K
> M: Stefan Roese
> diff --git a/doc/device-tree-bindings/usb/qcom-dwc3-ipq.txt
> b/doc/device-tree-bindings/usb/qcom-dwc3-ipq.txt
> new file mode 100644
> index 00..591683e520
> --- /dev/null
> +++ b/doc/device-tree-bindings/usb/qcom-dwc3-ipq.txt
> @@ -0,0 +1,25 @@
> +Qualcomm SuperSpeed DWC3 USB SoC controller
> +
> +This controller is integrated in IPQ40xx SoC-s.
> +It is a dual role USB3.0/USB2.0 controller.
> +
> +Required properties :
> + - compatible: must be "qcom,dwc3-ipq"
> + - reg: should contain address and length of the standard XHCI
> + register set for the device.
> +
> +Optional properties:
> + - rst-ctrl: Magic value used to reset PHY-s properly
> + (PHY-s may not function properly without it)
> + - hs-only : If present, specifies that board only has USB2.0(HS)
> + port
> +
> +Example:
> + xhci@8a0 {
> + compatible = "qcom,dwc3-ipq";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + reg = <0x8a0 0xcd00>;
> + rst-ctrl = <0x181E038 0x4>;
> + status = "disabled";
> + };
> diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
> index 1c374a7bd8..320c77ead5 100644
> --- a/drivers/usb/host/Kconfig
> +++ b/drivers/usb/host/Kconfig
> @@ -93,6 +93,12 @@ config USB_XHCI_BRCM
> USB controller based on the Broadcom USB3 IP Core.
> Supports USB2/3 functionality.
>
> +config USB_XHCI_IPQ
> + bool "Support for Qualcomm IPQ on-chip DWC3 xHCI USB controller"
> + depends on DM_USB && USB_XHCI_DWC3 && ARCH_IPQ40XX
> + help
> + Enables support for the on-chip xHCI DWC3 controller on Qualcomm IPQ
> SoCs.
> +
> endif # USB_XHCI_HCD
>
> config USB_EHCI_HCD
> diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
> index 29d4f87e38..0fa9c8f32a 100644
> --- a/drivers/usb/host/Makefile
> +++ b/drivers/usb/host/Makefile
> @@ -55,6 +55,7 @@ obj-$(CONFIG_USB_XHCI_MVEBU) += xhci-mvebu.o
> obj-$(CONFIG_USB_XHCI_OMAP) += xhci-omap.o
> obj-$(CONFIG_USB_XHCI_PCI) += xhci-pci.o
> obj-$(CONFIG_USB_XHCI_RCAR) += xhci-rcar.o
> +obj-$(CONFIG_USB_XHCI_IPQ) += xhci-ipq.o
> obj-$(CONFIG_USB_XHCI_STI) += dwc3-sti-glue.o
>
> # designware
> diff --git a/drivers/usb/host/xhci-ipq.c b/drivers/usb/host/xhci-ipq.c
> new file mode 100644
> index 00..b550cafac2
> --- /dev/null
> +++ b/drivers/usb/host/xhci-ipq.c
> @@ -0,0 +1,193 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright 2015 Freescale Semiconductor, Inc.
> + * Copyright (c) 2020 Sartura Ltd.
> + *
> + * DWC3 controller driver
> + *
> + * Author: Ramneek Mehresh
> + * Author: Robert Marko
> + *
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +/* Declare global data pointer */
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +struct ipq_xhci_platdata {
> + fdt_addr_t hcd_base;
> + unsigned int rst_ctrl;
> + unsigned int hs_only;
> +};
> +
> +struct ipq_xhci {
> + struct ipq_xhci_platdata usb_plat;
> + struct xhci_ctrl ctrl;
> + struct udevice* dev;
> + struct xhci_hccr *hcd;
> + struct dwc3 *dwc3_reg;
> +};
> +
> +void ipq_reset_usb_phy(void *data)
> +{
> + unsigned int gcc_rst_ctrl;
> + struct ipq_xhci_platdata *platdata;
> + struct ipq_xhci *ipq = (struct ipq_xhci *)data;
> +
> + platdata = dev_get_platdata(ipq->dev);
> + if (platdata == NULL) {
> + printf("Error: %s Failed\n", __func__);
> + return;
> + }
> +
> + gcc_rst_ctrl = platdata->rst_ctrl;
> +
> + if (gcc_rst_ctrl) {
> + /* assert HS PHY POR reset */
> + setbits_le32(gcc_rst_ctrl, 0x10);
> + mdelay(10);
> +
> + /* assert HS PHY SRIF reset */
RE: [EXT] [PATCH 2/2] arm: mvebu: Espressobin: Setup MTD partitions when booting kernel
> -Original Message-
> From: Pali Rohár
> Sent: Wednesday, August 19, 2020 17:24
> To: Stefan Roese ; Kostya Porotchkin
> Cc: u-boot@lists.denx.de
> Subject: [EXT] [PATCH 2/2] arm: mvebu: Espressobin: Setup MTD partitions
> when booting kernel
>
> External Email
>
> --
> Due to different partition layouts in different U-Boot versions, DTS for
> Espressobin in Linux does not contain any definition of MTD partitions.
> See commit https://urldefense.proofpoint.com/v2/url?u=https-
> 3A__git.kernel.org_stable_c_00954566464a4=DwIDaQ=nKjWec2b6R0m
> OyPaz7xtfQ=-
> N9sN4p5NSr0JGQoQ_2UCOgAqajG99W1EbSOww0WU8o=EH2hF8LOBbgZ
> NUxvBwhhmIe2uzWWEa_eJ3vAmWPxqmo=ei6YI15fI5FM73Z6537XKz_p9
> p3nx9nT7qiUvg2o_tU= for more details.
>
> This patch via ft_board_setup() hook fills current partition layout used by U-
> Boot, so booted kernel would see correct MTD partitions layout.
>
> U-Boot env partition is calculated from CONFIG_ENV_OFFSET option.
>
> First partition contains secure firmware, ARM trusted firmware and U-Boot
> with checksums. So it is not possible to replace just one image (e.g.
> U-Boot) without updating other parts where is stored checksum of U-Boot.
> Therefore there is no extra partition defined for U-Boot and first partition
> is
> called just 'firmware'.
>
> Signed-off-by: Pali Rohár
Reviewed-by: Konstantin Porotchkin
> ---
> board/Marvell/mvebu_armada-37xx/board.c | 100
>
> configs/mvebu_espressobin-88f3720_defconfig | 1 +
> 2 files changed, 101 insertions(+)
>
> diff --git a/board/Marvell/mvebu_armada-37xx/board.c
> b/board/Marvell/mvebu_armada-37xx/board.c
> index 031de318c6..7b9c3223ed 100644
> --- a/board/Marvell/mvebu_armada-37xx/board.c
> +++ b/board/Marvell/mvebu_armada-37xx/board.c
> @@ -243,3 +243,103 @@ int board_network_enable(struct mii_dev *bus)
>
> return 0;
> }
> +
> +#if defined(CONFIG_OF_BOARD_SETUP) &&
> +defined(CONFIG_ENV_IS_IN_SPI_FLASH)
> +int ft_board_setup(void *blob, struct bd_info *bd) {
> + int ret;
> + int spi_off;
> + int parts_off;
> + int part_off;
> +
> + /* Fill SPI MTD partitions for Linux kernel on Espressobin */
> + if (!of_machine_is_compatible("marvell,armada-3720-espressobin"))
> + return 0;
> +
> + spi_off = fdt_node_offset_by_compatible(blob, -1, "jedec,spi-nor");
> + if (spi_off < 0)
> + return 0;
> +
> + /* Do not touch partitions if they are already defined */
> + if (fdt_subnode_offset(blob, spi_off, "partitions") >= 0)
> + return 0;
> +
> + parts_off = fdt_add_subnode(blob, spi_off, "partitions");
> + if (parts_off < 0) {
> + printf("Can't add partitions node: %s\n",
> fdt_strerror(parts_off));
> + return 0;
> + }
> +
> + ret = fdt_setprop_string(blob, parts_off, "compatible", "fixed-
> partitions");
> + if (ret < 0) {
> + printf("Can't set compatible property: %s\n",
> fdt_strerror(ret));
> + return 0;
> + }
> +
> + ret = fdt_setprop_u32(blob, parts_off, "#address-cells", 1);
> + if (ret < 0) {
> + printf("Can't set #address-cells property: %s\n",
> fdt_strerror(ret));
> + return 0;
> + }
> +
> + ret = fdt_setprop_u32(blob, parts_off, "#size-cells", 1);
> + if (ret < 0) {
> + printf("Can't set #size-cells property: %s\n",
> fdt_strerror(ret));
> + return 0;
> + }
> +
> + /* Add u-boot-env partition */
> +
> + part_off = fdt_add_subnode(blob, parts_off, "partition@u-boot-
> env");
> + if (part_off < 0) {
> + printf("Can't add partition@u-boot-env node: %s\n",
> fdt_strerror(part_off));
> + return 0;
> + }
> +
> + ret = fdt_setprop_u32(blob, part_off, "reg", CONFIG_ENV_OFFSET);
> + if (ret < 0) {
> + printf("Can't set partition@u-boot-env reg property: %s\n",
> fdt_strerror(ret));
> + return 0;
> + }
> +
> + ret = fdt_appendprop_u32(blob, part_off, "reg",
> CONFIG_ENV_SIZE);
> + if (ret < 0) {
> + printf("Can't set partition@u-boot-env reg property: %s\n",
> fdt_strerror(ret));
> + return 0;
> + }
> +
> + ret = fdt_setprop_string(blob, part_off, "label", "u-boot-env");
> + if (ret < 0) {
> + printf("Can't set partition@u-boot-env label property: %s\n",
> fdt_strerror(ret));
> + return 0;
> + }
> +
> + /* Add firmware partition */
> +
> + part_off = fdt_add_subnode(blob, parts_off, "partition@firmware");
> + if (part_off < 0) {
> + printf("Can't add partition@firmware node: %s\n",
> fdt_strerror(part_off));
> + return 0;
> + }
> +
> + ret = fdt_setprop_u32(blob, part_off, "reg", 0);
> + if (ret < 0) {
> + printf("Can't set partition@firmware reg property: %s\n",
> fdt_strerror(ret));
> + return 0;
> +
RE: [EXT] [PATCH 1/2] arm: mvebu: Espressobin: Make SPI env offset compatible with Marvell's U-Boot
> -Original Message- > From: Pali Rohár > Sent: Wednesday, August 19, 2020 17:24 > To: Stefan Roese ; Kostya Porotchkin > Cc: u-boot@lists.denx.de > Subject: [EXT] [PATCH 1/2] arm: mvebu: Espressobin: Make SPI env offset > compatible with Marvell's U-Boot > > External Email > > -- > Espressobin board comes with Marvell's U-Boot version where U-Boot env is > stored in SPI at offset 0x3F. This patch changes env offset in Espressobin > defconfig file to match Marvell's U-Boot version. > > Users who want to use previous or different env offset can still change it in > .config file when compiling U-Boot. > > Signed-off-by: Pali Rohár Reviewed-by: Konstantin Porotchkin > --- > configs/mvebu_espressobin-88f3720_defconfig | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/configs/mvebu_espressobin-88f3720_defconfig > b/configs/mvebu_espressobin-88f3720_defconfig > index 933592af88..afcdd947c1 100644 > --- a/configs/mvebu_espressobin-88f3720_defconfig > +++ b/configs/mvebu_espressobin-88f3720_defconfig > @@ -6,7 +6,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000 > CONFIG_NR_DRAM_BANKS=1 > CONFIG_TARGET_MVEBU_ARMADA_37XX=y > CONFIG_ENV_SIZE=0x1 > -CONFIG_ENV_OFFSET=0x18 > +CONFIG_ENV_OFFSET=0x3F > CONFIG_ENV_SECT_SIZE=0x1 > CONFIG_DM_GPIO=y > CONFIG_DEBUG_UART_BASE=0xd0012000 > -- > 2.20.1
RE: [EXT] [PATCH 2/2] arm: dts: a37x0: enable sd card support on espressobin
> -Original Message-
> From: Pali Rohár
> Sent: Wednesday, August 19, 2020 17:20
> To: Peng Fan ; Kostya Porotchkin
> ; Stefan Roese
> Cc: u-boot@lists.denx.de
> Subject: [EXT] [PATCH 2/2] arm: dts: a37x0: enable sd card support on
> espressobin
>
> External Email
>
> --
> From: Wilson Ding
>
> Enabled SDIO slot 0 (south bridge) for SD card on Espressobin board.
>
> Change-Id: I51a2debf9fba276b9c4a2bc6da91328d47f443e3
> Signed-off-by: Wilson Ding
> Signed-off-by: Konstantin Porotchkin
> Reviewed-on: http://vgitil04.il.marvell.com:8080/60945
> Tested-by: iSoC Platform CI
> Reviewed-by: Igal Liberman
> [pali: Define cd-gpios and enable CONFIG_DM_REGULATOR_GPIO]
> Signed-off-by: Pali Rohár
Reviewed-by: Konstantin Porotchkin
> ---
> arch/arm/dts/armada-3720-espressobin.dts| 20
> configs/mvebu_espressobin-88f3720_defconfig | 1 +
> 2 files changed, 21 insertions(+)
>
> diff --git a/arch/arm/dts/armada-3720-espressobin.dts
> b/arch/arm/dts/armada-3720-espressobin.dts
> index f10a953ec5..92eddca6c0 100644
> --- a/arch/arm/dts/armada-3720-espressobin.dts
> +++ b/arch/arm/dts/armada-3720-espressobin.dts
> @@ -67,6 +67,17 @@
> device_type = "memory";
> reg = <0x 0x 0x 0x2000>;
> };
> +
> + vcc_sd_reg0: regulator@0 {
> + compatible = "regulator-gpio";
> + regulator-name = "vcc_sd0";
> + regulator-min-microvolt = <180>;
> + regulator-max-microvolt = <330>;
> + regulator-type = "voltage";
> + states = <180 0x1
> + 330 0x0>;
> + gpios = < 4 GPIO_ACTIVE_HIGH>;
> + };
> };
>
> {
> @@ -110,6 +121,15 @@
> status = "okay";
> };
>
> + {
> + pinctrl-names = "default";
> + pinctrl-0 = <_pins>;
> + bus-width = <4>;
> + cd-gpios = < 3 GPIO_ACTIVE_LOW>;
> + vqmmc-supply = <_sd_reg0>;
> + status = "okay";
> +};
> +
> {
> status = "okay";
> pinctrl-names = "default";
> diff --git a/configs/mvebu_espressobin-88f3720_defconfig
> b/configs/mvebu_espressobin-88f3720_defconfig
> index 495faf43a3..933592af88 100644
> --- a/configs/mvebu_espressobin-88f3720_defconfig
> +++ b/configs/mvebu_espressobin-88f3720_defconfig
> @@ -81,3 +81,4 @@ CONFIG_USB_ETHER_SMSC95XX=y CONFIG_SHA1=y
> CONFIG_SHA256=y CONFIG_MVNETA=y
> +CONFIG_DM_REGULATOR_GPIO=y
> --
> 2.20.1
RE: [EXT] [PATCH 1/2] mmc: xenon: set signal voltage and max base clock
> -Original Message-
> From: Pali Rohár
> Sent: Wednesday, August 19, 2020 17:20
> To: Peng Fan ; Kostya Porotchkin
> ; Stefan Roese
> Cc: u-boot@lists.denx.de
> Subject: [EXT] [PATCH 1/2] mmc: xenon: set signal voltage and max base
> clock
>
> External Email
>
> --
> From: Evan Wang
>
> - The SDIO signal voltage and max base clock frequency
> setting are missing in driver, which causes SDIO
> not working.
> - The patch adds SDIO signal voltage switch support,
> which is based on regulator-gpio of vqmmc-supply, and
> sets the max base clock frequency.
> - Fix the zero clock value in call to sdhci_setup_cfg()
> function.
>
> Change-Id: I79c8860c65b8db166f4f70db56ede4097f71f1fa
> Signed-off-by: Evan Wang
> Reviewed-on: http://vgitil04.il.marvell.com:8080/53589
> Reviewed-by: Hua Jing
> Tested-by: Hua Jing
> [pali: Amended fixup patch]
> Signed-off-by: Pali Rohár
Reviewed-by: Konstantin Porotchkin
> ---
> drivers/mmc/xenon_sdhci.c | 79
> ++-
> 1 file changed, 78 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/mmc/xenon_sdhci.c b/drivers/mmc/xenon_sdhci.c index
> 356dd9846d..7f9a579c83 100644
> --- a/drivers/mmc/xenon_sdhci.c
> +++ b/drivers/mmc/xenon_sdhci.c
> @@ -22,6 +22,7 @@
> #include
> #include
> #include
> +#include
>
> DECLARE_GLOBAL_DATA_PTR;
>
> @@ -42,6 +43,14 @@ DECLARE_GLOBAL_DATA_PTR;
> #define SDHC_SYS_EXT_OP_CTRL 0x010C
> #define MASK_CMD_CONFLICT_ERROR BIT(8)
>
> +#define SDHC_SLOT_EMMC_CTRL 0x0130
> +#define ENABLE_DATA_STROBE_SHIFT 24
> +#define SET_EMMC_RSTN_SHIFT 16
> +#define EMMC_VCCQ_MASK 0x3
> +#define EMMC_VCCQ_1_8V 0x1
> +#define EMMC_VCCQ_1_2V 0x2
> +#define EMMC_VCCQ_3_3V 0x3
> +
> #define SDHC_SLOT_RETUNING_REQ_CTRL 0x0144
> /* retuning compatible */
> #define RETUNING_COMPATIBLE 0x1
> @@ -108,6 +117,8 @@ DECLARE_GLOBAL_DATA_PTR;
> #define MMC_TIMING_MMC_HS400 10
>
> #define XENON_MMC_MAX_CLK4
> +#define XENON_MMC_3V3_UV 330
> +#define XENON_MMC_1V8_UV 180
>
> enum soc_pad_ctrl_type {
> SOC_PAD_SD,
> @@ -128,6 +139,8 @@ struct xenon_sdhci_priv {
>
> void *pad_ctrl_reg;
> int pad_type;
> +
> + struct udevice *vqmmc;
> };
>
> static int xenon_mmc_phy_init(struct sdhci_host *host) @@ -208,6 +221,51
> @@ static void armada_3700_soc_pad_voltage_set(struct sdhci_host *host)
> writel(ARMADA_3700_SOC_PAD_3_3V, priv->pad_ctrl_reg);
> }
>
> +static int xenon_mmc_start_signal_voltage_switch(struct sdhci_host
> +*host) {
> + struct xenon_sdhci_priv *priv = host->mmc->priv;
> + u8 voltage;
> + u32 ctrl;
> + int ret = 0;
> +
> + /* If there is no vqmmc regulator, return */
> + if (!priv->vqmmc)
> + return 0;
> +
> + if (priv->pad_type == SOC_PAD_FIXED_1_8V) {
> + /* Switch to 1.8v */
> + ret = regulator_set_value(priv->vqmmc,
> + XENON_MMC_1V8_UV);
> + } else if (priv->pad_type == SOC_PAD_SD) {
> + /* Get voltage info */
> + voltage = sdhci_readb(host, SDHCI_POWER_CONTROL);
> + voltage &= ~SDHCI_POWER_ON;
> +
> + if (voltage == SDHCI_POWER_330) {
> + /* Switch to 3.3v */
> + ret = regulator_set_value(priv->vqmmc,
> + XENON_MMC_3V3_UV);
> + } else {
> + /* Switch to 1.8v */
> + ret = regulator_set_value(priv->vqmmc,
> + XENON_MMC_1V8_UV);
> + }
> + }
> +
> + /* Set VCCQ, eMMC mode: 1.8V; SD/SDIO mode: 3.3V */
> + ctrl = sdhci_readl(host, SDHC_SLOT_EMMC_CTRL);
> + if (IS_SD(host->mmc))
> + ctrl |= EMMC_VCCQ_3_3V;
> + else
> + ctrl |= EMMC_VCCQ_1_8V;
> + sdhci_writel(host, ctrl, SDHC_SLOT_EMMC_CTRL);
> +
> + if (ret)
> + printf("Signal voltage switch fail\n");
> +
> + return ret;
> +}
> +
> static void xenon_mmc_phy_set(struct sdhci_host *host) {
> struct xenon_sdhci_priv *priv = host->mmc->priv; @@ -334,6
> +392,13 @@ static int xenon_sdhci_set_ios_post(struct sdhci_host *host)
> uint speed = host->mmc->tran_speed;
> int pwr_18v = 0;
>
> + /*
> + * Signal Voltage Switching is only applicable for Host Controllers
> + * v3.00 and above.
> + */
> + if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
> + xenon_mmc_start_signal_voltage_switch(host);
> +
> if ((sdhci_readb(host, SDHCI_POWER_CONTROL) &
> ~SDHCI_POWER_ON) ==
> SDHCI_POWER_180)
> pwr_18v = 1;
Re: [EXT] [PATCH 2/2] arm64: a37xx: pci: Assert PERST# signal when unloading driver
From: Pali Rohár
Sent: Wednesday, August 19, 2020 16:57
To: Stefan Roese; Kostya Porotchkin
Cc: u-boot@lists.denx.de
Subject: [EXT] [PATCH 2/2] arm64: a37xx: pci: Assert PERST# signal when
unloading driver
External Email
--
This change ensures that PCIe card is put into reset state when U-Boot
stops using it.
DM_FLAG_OS_PREPARE ensures that U-Boot executes driver's remove callback
prior booting Linux kernel.
Linux kernel pci-aardvark driver needs to reset PCIe card via PERST# signal
prior initializing it. If it does not issue reset then some PCIe cards
(specially Compex WiFi cards) are not detected at all.
Putting PCIe card into reset state prior booting Linux kernel would ensure
that card would be properly reset at time when Linux kernel starts
initializing pci-aardvark driver.
Signed-off-by: Pali Rohár
Reviewed-by: Konstantin Porotchkin
---
drivers/pci/pci-aardvark.c | 27 +--
1 file changed, 21 insertions(+), 6 deletions(-)
diff --git a/drivers/pci/pci-aardvark.c b/drivers/pci/pci-aardvark.c
index 5b3f23c184..8996be5309 100644
--- a/drivers/pci/pci-aardvark.c
+++ b/drivers/pci/pci-aardvark.c
@@ -148,6 +148,9 @@ struct pcie_advk {
void *base;
intfirst_busno;
struct udevice *dev;
+#if CONFIG_IS_ENABLED(DM_GPIO)
+ struct gpio_desc reset_gpio;
+#endif
};
static inline void advk_writel(struct pcie_advk *pcie, uint val, uint reg)
@@ -614,9 +617,7 @@ static int pcie_advk_probe(struct udevice *dev)
struct pcie_advk *pcie = dev_get_priv(dev);
#if CONFIG_IS_ENABLED(DM_GPIO)
- struct gpio_desc reset_gpio;
-
- gpio_request_by_name(dev, "reset-gpios", 0, _gpio,
+ gpio_request_by_name(dev, "reset-gpios", 0, >reset_gpio,
GPIOD_IS_OUT);
/*
* Issue reset to add-in card through the dedicated GPIO.
@@ -631,11 +632,11 @@ static int pcie_advk_probe(struct udevice *dev)
* possible before PCIe PHY initialization. Moreover, the PCIe
* clock should be gated as well.
*/
- if (dm_gpio_is_valid(_gpio)) {
+ if (dm_gpio_is_valid(>reset_gpio)) {
dev_dbg(pcie->dev, "Toggle PCIE Reset GPIO ...\n");
- dm_gpio_set_value(_gpio, 1);
+ dm_gpio_set_value(>reset_gpio, 1);
mdelay(200);
- dm_gpio_set_value(_gpio, 0);
+ dm_gpio_set_value(>reset_gpio, 0);
}
#else
dev_dbg(pcie->dev, "PCIE Reset on GPIO support is missing\n");
@@ -647,6 +648,18 @@ static int pcie_advk_probe(struct udevice *dev)
return pcie_advk_setup_hw(pcie);
}
+static int pcie_advk_remove(struct udevice *dev)
+{
+#if CONFIG_IS_ENABLED(DM_GPIO)
+ struct pcie_advk *pcie = dev_get_priv(dev);
+
+ if (dm_gpio_is_valid(>reset_gpio))
+ dm_gpio_set_value(>reset_gpio, 1);
+#endif /* DM_GPIO */
+
+ return 0;
+}
+
/**
* pcie_advk_ofdata_to_platdata() - Translate from DT to device state
*
@@ -687,5 +700,7 @@ U_BOOT_DRIVER(pcie_advk) = {
.ops= _advk_ops,
.ofdata_to_platdata = pcie_advk_ofdata_to_platdata,
.probe = pcie_advk_probe,
+ .remove = pcie_advk_remove,
+ .flags = DM_FLAG_OS_PREPARE,
.priv_auto_alloc_size = sizeof(struct pcie_advk),
};
--
2.20.1
Re: [EXT] [PATCH 1/2] arm64: a37xx: pci: Make PCIe Reset GPIO DT compatible with Linux kernel DT
From: Pali Rohár
Sent: Wednesday, August 19, 2020 16:57
To: Stefan Roese; Kostya Porotchkin
Cc: u-boot@lists.denx.de
Subject: [EXT] [PATCH 1/2] arm64: a37xx: pci: Make PCIe Reset GPIO DT
compatible with Linux kernel DT
External Email
--
Change active-high to active-low and change DT property name from
reset-gpio to reset-gpios. This format of gpio reset is used by
pci-aardvark driver in Linux kernel.
Signed-off-by: Pali Rohár
Reviewed-by: Konstantin Porotchkin
---
arch/arm/dts/armada-3720-db.dts | 2 +-
arch/arm/dts/armada-3720-espressobin.dts | 2 +-
arch/arm/dts/armada-3720-turris-mox.dts | 2 +-
drivers/pci/pci-aardvark.c | 6 +++---
4 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/arch/arm/dts/armada-3720-db.dts b/arch/arm/dts/armada-3720-db.dts
index 1b219c423b..1b1b66b94d 100644
--- a/arch/arm/dts/armada-3720-db.dts
+++ b/arch/arm/dts/armada-3720-db.dts
@@ -159,6 +159,6 @@
{
pinctrl-names = "default";
pinctrl-0 = <_pins>;
- reset-gpio = < 3 GPIO_ACTIVE_HIGH>;
+ reset-gpios = < 3 GPIO_ACTIVE_LOW>;
status = "okay";
};
diff --git a/arch/arm/dts/armada-3720-espressobin.dts
b/arch/arm/dts/armada-3720-espressobin.dts
index 84e2c2adba..f10a953ec5 100644
--- a/arch/arm/dts/armada-3720-espressobin.dts
+++ b/arch/arm/dts/armada-3720-espressobin.dts
@@ -145,6 +145,6 @@
{
pinctrl-names = "default";
pinctrl-0 = <_pins>;
- reset-gpio = < 3 GPIO_ACTIVE_HIGH>;
+ reset-gpios = < 3 GPIO_ACTIVE_LOW>;
status = "okay";
};
diff --git a/arch/arm/dts/armada-3720-turris-mox.dts
b/arch/arm/dts/armada-3720-turris-mox.dts
index 0f0a6ce65d..974270cc8c 100644
--- a/arch/arm/dts/armada-3720-turris-mox.dts
+++ b/arch/arm/dts/armada-3720-turris-mox.dts
@@ -172,6 +172,6 @@
{
pinctrl-names = "default";
pinctrl-0 = <_pins>;
- reset-gpio = < 3 GPIO_ACTIVE_HIGH>;
+ reset-gpios = < 3 GPIO_ACTIVE_LOW>;
status = "disabled";
};
diff --git a/drivers/pci/pci-aardvark.c b/drivers/pci/pci-aardvark.c
index 711b930d0f..5b3f23c184 100644
--- a/drivers/pci/pci-aardvark.c
+++ b/drivers/pci/pci-aardvark.c
@@ -616,7 +616,7 @@ static int pcie_advk_probe(struct udevice *dev)
#if CONFIG_IS_ENABLED(DM_GPIO)
struct gpio_desc reset_gpio;
- gpio_request_by_name(dev, "reset-gpio", 0, _gpio,
+ gpio_request_by_name(dev, "reset-gpios", 0, _gpio,
GPIOD_IS_OUT);
/*
* Issue reset to add-in card through the dedicated GPIO.
@@ -633,9 +633,9 @@ static int pcie_advk_probe(struct udevice *dev)
*/
if (dm_gpio_is_valid(_gpio)) {
dev_dbg(pcie->dev, "Toggle PCIE Reset GPIO ...\n");
- dm_gpio_set_value(_gpio, 0);
- mdelay(200);
dm_gpio_set_value(_gpio, 1);
+ mdelay(200);
+ dm_gpio_set_value(_gpio, 0);
}
#else
dev_dbg(pcie->dev, "PCIE Reset on GPIO support is missing\n");
--
2.20.1
[PATCH 1/1] fs/squashfs: Fix Coverity Scan defects
Fix defects such as uninitialized variables and untrusted pointer
operations. Most part of the tainted variables and the related defects
actually comes from Linux's macro get_unaligned_le**, extensively used
in SquashFS code. Add sanity checks for those variables.
Signed-off-by: Joao Marcos Costa
---
fs/squashfs/sqfs.c | 40 +---
fs/squashfs/sqfs_dir.c | 3 +++
fs/squashfs/sqfs_inode.c | 5 -
3 files changed, 36 insertions(+), 12 deletions(-)
diff --git a/fs/squashfs/sqfs.c b/fs/squashfs/sqfs.c
index 9bd7b98d88..f67f7c4a40 100644
--- a/fs/squashfs/sqfs.c
+++ b/fs/squashfs/sqfs.c
@@ -154,6 +154,11 @@ static int sqfs_frag_lookup(u32 inode_fragment_index,
header = get_unaligned_le16(metadata_buffer + table_offset);
metadata = metadata_buffer + table_offset + SQFS_HEADER_SIZE;
+ if (!metadata) {
+ ret = -ENOMEM;
+ goto free_buffer;
+ }
+
entries = malloc(SQFS_METADATA_BLOCK_SIZE);
if (!entries) {
ret = -ENOMEM;
@@ -272,8 +277,8 @@ static int sqfs_join(char **strings, char *dest, int start,
int end,
*/
static int sqfs_tokenize(char **tokens, int count, const char *str)
{
+ int i, j, ret = 0;
char *aux, *strc;
- int i, j;
strc = strdup(str);
if (!strc)
@@ -282,8 +287,8 @@ static int sqfs_tokenize(char **tokens, int count, const
char *str)
if (!strcmp(strc, "/")) {
tokens[0] = strdup(strc);
if (!tokens[0]) {
- free(strc);
- return -ENOMEM;
+ ret = -ENOMEM;
+ goto free_strc;
}
} else {
for (j = 0; j < count; j++) {
@@ -292,15 +297,16 @@ static int sqfs_tokenize(char **tokens, int count, const
char *str)
if (!tokens[j]) {
for (i = 0; i < j; i++)
free(tokens[i]);
- free(strc);
- return -ENOMEM;
+ ret = -ENOMEM;
+ goto free_strc;
}
}
}
+free_strc:
free(strc);
- return 0;
+ return ret;
}
/*
@@ -428,9 +434,9 @@ static int sqfs_search_dir(struct squashfs_dir_stream
*dirs, char **token_list,
{
struct squashfs_super_block *sblk = ctxt.sblk;
char *path, *target, **sym_tokens, *res, *rem;
+ struct squashfs_ldir_inode *ldir = NULL;
int j, ret, new_inode_number, offset;
struct squashfs_symlink_inode *sym;
- struct squashfs_ldir_inode *ldir;
struct squashfs_dir_inode *dir;
struct fs_dir_stream *dirsp;
struct fs_dirent *dent;
@@ -630,7 +636,7 @@ static int sqfs_read_inode_table(unsigned char
**inode_table)
int j, ret = 0, metablks_count;
unsigned char *src_table, *itb;
u32 src_len, dest_offset = 0;
- unsigned long dest_len;
+ unsigned long dest_len = 0;
bool compressed;
table_size = get_unaligned_le64(>directory_table_start) -
@@ -685,6 +691,7 @@ static int sqfs_read_inode_table(unsigned char
**inode_table)
goto free_itb;
}
+ dest_offset += dest_len;
} else {
memcpy(*inode_table + (j * SQFS_METADATA_BLOCK_SIZE),
src_table, src_len);
@@ -694,7 +701,7 @@ static int sqfs_read_inode_table(unsigned char
**inode_table)
* Offsets to the decompression destination, to the metadata
* buffer 'itb' and to the decompression source, respectively.
*/
- dest_offset += dest_len;
+
table_offset += src_len + SQFS_HEADER_SIZE;
src_table += src_len + SQFS_HEADER_SIZE;
}
@@ -712,7 +719,7 @@ static int sqfs_read_directory_table(unsigned char
**dir_table, u32 **pos_list)
int j, ret = 0, metablks_count = -1;
unsigned char *src_table, *dtb;
u32 src_len, dest_offset = 0;
- unsigned long dest_len;
+ unsigned long dest_len = 0;
bool compressed;
/* DIRECTORY TABLE */
@@ -781,6 +788,8 @@ static int sqfs_read_directory_table(unsigned char
**dir_table, u32 **pos_list)
dest_offset += dest_len;
break;
}
+
+ dest_offset += dest_len;
} else {
memcpy(*dir_table + (j * SQFS_METADATA_BLOCK_SIZE),
src_table, src_len);
@@ -790,7 +799,6 @@ static int sqfs_read_directory_table(unsigned char
**dir_table, u32 **pos_list)
* Offsets to the decompression destination, to the metadata
* buffer
[PATCH 0/1] fs/squashfs: Fix Coverity Scan defects
Hello, The following patch fixes most of the defects pointed by Coverity Scan. It depends on the previous patch series adding new decompression algorithms. Some of the defects may be out of SquashFS scope, because they come from a Linux's macro, but sanity checks were added as a possible solution for these tainted values. Please do not hesitate to report any remaining issues. Best regards, Joao Joao Marcos Costa (1): fs/squashfs: Fix Coverity Scan defects fs/squashfs/sqfs.c | 40 +--- fs/squashfs/sqfs_dir.c | 3 +++ fs/squashfs/sqfs_inode.c | 5 - 3 files changed, 36 insertions(+), 12 deletions(-) -- 2.17.1
Re: [PATCH v2 7/9] ram: octeon: Add MIPS Octeon3 DDR4 support (part 3/3)
Am Montag, den 17.08.2020, 14:12 +0200 schrieb Stefan Roese:
> From: Aaron Williams
>
> This Octeon 3 DDR driver is ported from the 2013 Cavium / Marvell U-Boot
> repository. It currently supports DDR4 on Octeon 3. It can be later
> extended to support also DDR3 and Octeon 2 platforms.
>
> Part 3 includes the DIMM SPD handling code and the Kconfig / Makefile
> integration.
>
> Signed-off-by: Aaron Williams
> Signed-off-by: Stefan Roese
> ---
>
> (no changes since v1)
>
> drivers/ram/Kconfig | 1 +
> drivers/ram/Makefile | 2 +
> drivers/ram/octeon/Kconfig | 17 ++
> drivers/ram/octeon/Makefile | 8 +
> drivers/ram/octeon/dimm_spd_eeprom.c | 410 +++
> 5 files changed, 438 insertions(+)
> create mode 100644 drivers/ram/octeon/Kconfig
> create mode 100644 drivers/ram/octeon/Makefile
> create mode 100644 drivers/ram/octeon/dimm_spd_eeprom.c
>
> diff --git a/drivers/ram/Kconfig b/drivers/ram/Kconfig
> index 7e6e981897..a0e859afd6 100644
> --- a/drivers/ram/Kconfig
> +++ b/drivers/ram/Kconfig
> @@ -76,3 +76,4 @@ config IMXRT_SDRAM
> source "drivers/ram/rockchip/Kconfig"
> source "drivers/ram/sifive/Kconfig"
> source "drivers/ram/stm32mp1/Kconfig"
> +source "drivers/ram/octeon/Kconfig"
> diff --git a/drivers/ram/Makefile b/drivers/ram/Makefile
> index 769c9d6218..d685a579a0 100644
> --- a/drivers/ram/Makefile
> +++ b/drivers/ram/Makefile
> @@ -19,3 +19,5 @@ obj-$(CONFIG_K3_J721E_DDRSS) += k3-j721e/
> obj-$(CONFIG_IMXRT_SDRAM) += imxrt_sdram.o
>
> obj-$(CONFIG_RAM_SIFIVE) += sifive/
> +
> +obj-$(CONFIG_ARCH_OCTEON) += octeon/
> diff --git a/drivers/ram/octeon/Kconfig b/drivers/ram/octeon/Kconfig
> new file mode 100644
> index 00..eb5a1208ed
> --- /dev/null
> +++ b/drivers/ram/octeon/Kconfig
> @@ -0,0 +1,17 @@
> +config RAM_OCTEON
> + bool "Ram drivers for Octeon SoCs"
> + depends on RAM && ARCH_OCTEON
> + default n
> + help
> + This enables support for RAM drivers for Octeon SoCs.
> +
> +if RAM_OCTEON
> +
> +config RAM_OCTEON_DDR4
> + bool "Octeon III DDR4 RAM support"
> + default n
> + help
> + This enables support for DDR4 RAM suppoort for Octeon III. This does
> + not include support for Octeon CN70XX.
> +
> +endif # RAM_OCTEON
> diff --git a/drivers/ram/octeon/Makefile b/drivers/ram/octeon/Makefile
> new file mode 100644
> index 00..27649d1e6f
> --- /dev/null
> +++ b/drivers/ram/octeon/Makefile
> @@ -0,0 +1,8 @@
> +# SPDX-License-Identifier: GPL-2.0
> +#
> +# Copyright (c) 2020 Marvell, Inc.
> +#
> +
> +obj-$(CONFIG_RAM_OCTEON_DDR4) += octeon_ddr.o
> +obj-$(CONFIG_RAM_OCTEON_DDR4) += octeon3_lmc.o
> +obj-y += dimm_spd_eeprom.o
> diff --git a/drivers/ram/octeon/dimm_spd_eeprom.c
> b/drivers/ram/octeon/dimm_spd_eeprom.c
> new file mode 100644
> index 00..efff3be71f
> --- /dev/null
> +++ b/drivers/ram/octeon/dimm_spd_eeprom.c
> @@ -0,0 +1,410 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2020 Marvell International Ltd.
> + *
> + * https://spdx.org/licenses
this line is superfluous
> + */
> +
> +#include
try to avoid common.h in new code
> +#include
> +#include
> +
> +#include
> +
> +#define DEVICE_TYPE DDR4_SPD_KEY_BYTE_DEVICE_TYPE // same for DDR3 and DDR4
> +#define MODULE_TYPE DDR4_SPD_KEY_BYTE_MODULE_TYPE // same for DDR3 and DDR4
> +#define BUS_WIDTH(t) (((t) == DDR4_DRAM) ? \
> + DDR4_SPD_MODULE_MEMORY_BUS_WIDTH : \
> + DDR3_SPD_MEMORY_BUS_WIDTH)
> +
> +/*
> + * Allow legacy code to encode bus number in the upper bits of the address
> + * These are only supported in read_spd()
> + */
> +#define OCTEON_TWSI_BUS_IN_ADDR_BIT 12
> +#define OCTEON_TWSI_BUS_IN_ADDR_MASK (15 << OCTEON_TWSI_BUS_IN_ADDR_BIT)
> +#define OCTEON_TWSI_GET_BUS(addr)\
> + (((addr) >> OCTEON_TWSI_BUS_IN_ADDR_BIT) & 0xf)
> +
> +const char *ddr3_dimm_types[] = {
> + /* */ "Undefined",
> + /* 0001 */ "RDIMM",
> + /* 0010 */ "UDIMM",
> + /* 0011 */ "SO-DIMM",
> + /* 0100 */ "Micro-DIMM",
> + /* 0101 */ "Mini-RDIMM",
> + /* 0110 */ "Mini-UDIMM",
> + /* 0111 */ "Mini-CDIMM",
> + /* 1000 */ "72b-SO-UDIMM",
> + /* 1001 */ "72b-SO-RDIMM",
> + /* 1010 */ "72b-SO-CDIMM"
> + /* 1011 */ "LRDIMM",
> + /* 1100 */ "16b-SO-DIMM",
> + /* 1101 */ "32b-SO-DIMM",
> + /* 1110 */ "Reserved",
> + /* */ "Reserved"
> +};
> +
> +const char *ddr4_dimm_types[] = {
> + /* */ "Extended",
> + /* 0001 */ "RDIMM",
> + /* 0010 */ "UDIMM",
> + /* 0011 */ "SO-DIMM",
> + /* 0100 */ "LRDIMM",
> + /* 0101 */ "Mini-RDIMM",
> + /* 0110 */ "Mini-UDIMM",
> + /* 0111 */ "Reserved",
> + /* 1000 */ "72b-SO-RDIMM",
> + /* 1001 */ "72b-SO-UDIMM",
> + /* 1010 */ "Reserved",
> + /* 1011 */ "Reserved",
> + /* 1100 */ "16b-SO-DIMM",
> + /* 1101 */ "32b-SO-DIMM",
> +
Re: [PATCH v2 5/9] ram: octeon: Add MIPS Octeon3 DDR4 support (part 1/3)
Am Montag, den 17.08.2020, 14:12 +0200 schrieb Stefan Roese:
> From: Aaron Williams
>
> This Octeon 3 DDR driver is ported from the 2013 Cavium / Marvell U-Boot
> repository. It currently supports DDR4 on Octeon 3. It can be later
> extended to support also DDR3 and Octeon 2 platforms.
>
> Part 1 adds the base U-Boot RAM driver, which will be instantiated by
> the DT based probing.
>
> Signed-off-by: Aaron Williams
> Signed-off-by: Stefan Roese
>
> ---
>
> Changes in v2:
> - Don't re-init after relocation
> - Some unsupported Octeon families removed (only Octeon 2 & 3 supported
> in general)
>
> drivers/ram/octeon/octeon_ddr.c | 2730 +++
> 1 file changed, 2730 insertions(+)
> create mode 100644 drivers/ram/octeon/octeon_ddr.c
some general notes:
- there are still some C++ style comments
- there are a lot of non-static functions, are them really used in
other source files and why? Of course you can split the code into
multiple files but this file is the driver entrypoint and shouldn't
export anything
>
> diff --git a/drivers/ram/octeon/octeon_ddr.c b/drivers/ram/octeon/octeon_ddr.c
> new file mode 100644
> index 00..0b347b61fd
> --- /dev/null
> +++ b/drivers/ram/octeon/octeon_ddr.c
> @@ -0,0 +1,2730 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2020 Marvell International Ltd.
> + *
> + * https://spdx.org/licenses
this line is superfluous
> + */
> +
> +#include
try to avoid common.h in new code
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +#include
> +#include
> +
> +#include
do Octeon ARM and MIPS share the same DDR3/4 memory controller? If yes,
would this driver support both archs and would ARM provide an own
version of octeon_ddr.h?
> +
> +#define CONFIG_REF_HERTZ 5000
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +/* Sign of an integer */
> +static s64 _sign(s64 v)
> +{
> + return (v < 0);
> +}
> +
> +#ifndef DDR_NO_DEBUG
> +char *lookup_env(struct ddr_priv *priv, const char *format, ...)
> +{
> + char *s;
> + unsigned long value;
> + va_list args;
> + char buffer[64];
> +
> + va_start(args, format);
> + vsnprintf(buffer, sizeof(buffer), format, args);
> + va_end(args);
> +
> + s = ddr_getenv_debug(priv, buffer);
> + if (s) {
> + value = simple_strtoul(s, NULL, 0);
> + printf("Parameter found in environment %s=\"%s\" 0x%lx (%ld)\n",
> +buffer, s, value, value);
> + }
> +
> + return s;
> +}
> +
> +char *lookup_env_ull(struct ddr_priv *priv, const char *format, ...)
> +{
> + char *s;
> + u64 value;
> + va_list args;
> + char buffer[64];
> +
> + va_start(args, format);
> + vsnprintf(buffer, sizeof(buffer), format, args);
> + va_end(args);
> +
> + s = ddr_getenv_debug(priv, buffer);
> + if (s) {
> + value = simple_strtoull(s, NULL, 0);
> + printf("Parameter found in environment. %s = 0x%016llx\n",
> +buffer, value);
> + }
> +
> + return s;
> +}
> +#else
> +char *lookup_env(struct ddr_priv *priv, const char *format, ...)
> +{
> + return NULL;
> +}
> +
> +char *lookup_env_ull(struct ddr_priv *priv, const char *format, ...)
> +{
> + return NULL;
> +}
> +#endif
> +
> +/* Number of L2C Tag-and-data sections (TADs) that are connected to LMC. */
> +#define CVMX_L2C_TADS ((OCTEON_IS_MODEL(OCTEON_CN68XX) || \
> + OCTEON_IS_MODEL(OCTEON_CN73XX) || \
> + OCTEON_IS_MODEL(OCTEON_CNF75XX)) ? 4 : \
> + (OCTEON_IS_MODEL(OCTEON_CN78XX)) ? 8 : 1)
> +
> +/* Number of L2C IOBs connected to LMC. */
> +#define CVMX_L2C_IOBS ((OCTEON_IS_MODEL(OCTEON_CN68XX) || \
> + OCTEON_IS_MODEL(OCTEON_CN78XX) || \
> + OCTEON_IS_MODEL(OCTEON_CN73XX) || \
> + OCTEON_IS_MODEL(OCTEON_CNF75XX)) ? 2 : 1)
> +
> +#define CVMX_L2C_MAX_MEMSZ_ALLOWED (OCTEON_IS_OCTEON2() ?\
> + (32 * CVMX_L2C_TADS) : \
> + (OCTEON_IS_MODEL(OCTEON_CN70XX) ? \
> + 512 : (OCTEON_IS_OCTEON3() ? 1024 : 0)))
> +
> +/**
> + * Initialize the BIG address in L2C+DRAM to generate proper error
> + * on reading/writing to an non-existent memory location.
> + *
> + * @param node OCX CPU node number
> + * @param mem_size Amount of DRAM configured in MB.
> + * @param mode Allow/Disallow reporting errors L2C_INT_SUM[BIGRD,BIGWR].
> + */
> +static void cvmx_l2c_set_big_size(struct ddr_priv *priv, u64 mem_size, int
> mode)
> +{
> + if ((OCTEON_IS_OCTEON2() || OCTEON_IS_OCTEON3()) &&
> + !OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X)) {
> + union cvmx_l2c_big_ctl big_ctl;
> + int bits = 0, zero_bits = 0;
> + u64 mem;
>
[PATCH 1/2] arm: mvebu: Espressobin: Make SPI env offset compatible with Marvell's U-Boot
Espressobin board comes with Marvell's U-Boot version where U-Boot env is stored in SPI at offset 0x3F. This patch changes env offset in Espressobin defconfig file to match Marvell's U-Boot version. Users who want to use previous or different env offset can still change it in .config file when compiling U-Boot. Signed-off-by: Pali Rohár --- configs/mvebu_espressobin-88f3720_defconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/configs/mvebu_espressobin-88f3720_defconfig b/configs/mvebu_espressobin-88f3720_defconfig index 933592af88..afcdd947c1 100644 --- a/configs/mvebu_espressobin-88f3720_defconfig +++ b/configs/mvebu_espressobin-88f3720_defconfig @@ -6,7 +6,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_NR_DRAM_BANKS=1 CONFIG_TARGET_MVEBU_ARMADA_37XX=y CONFIG_ENV_SIZE=0x1 -CONFIG_ENV_OFFSET=0x18 +CONFIG_ENV_OFFSET=0x3F CONFIG_ENV_SECT_SIZE=0x1 CONFIG_DM_GPIO=y CONFIG_DEBUG_UART_BASE=0xd0012000 -- 2.20.1
[PATCH 2/2] arm: mvebu: Espressobin: Setup MTD partitions when booting kernel
Due to different partition layouts in different U-Boot versions, DTS for
Espressobin in Linux does not contain any definition of MTD partitions.
See commit https://git.kernel.org/stable/c/00954566464a4 for more details.
This patch via ft_board_setup() hook fills current partition layout used by
U-Boot, so booted kernel would see correct MTD partitions layout.
U-Boot env partition is calculated from CONFIG_ENV_OFFSET option.
First partition contains secure firmware, ARM trusted firmware and U-Boot
with checksums. So it is not possible to replace just one image (e.g.
U-Boot) without updating other parts where is stored checksum of U-Boot.
Therefore there is no extra partition defined for U-Boot and first
partition is called just 'firmware'.
Signed-off-by: Pali Rohár
---
board/Marvell/mvebu_armada-37xx/board.c | 100
configs/mvebu_espressobin-88f3720_defconfig | 1 +
2 files changed, 101 insertions(+)
diff --git a/board/Marvell/mvebu_armada-37xx/board.c
b/board/Marvell/mvebu_armada-37xx/board.c
index 031de318c6..7b9c3223ed 100644
--- a/board/Marvell/mvebu_armada-37xx/board.c
+++ b/board/Marvell/mvebu_armada-37xx/board.c
@@ -243,3 +243,103 @@ int board_network_enable(struct mii_dev *bus)
return 0;
}
+
+#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_ENV_IS_IN_SPI_FLASH)
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+ int ret;
+ int spi_off;
+ int parts_off;
+ int part_off;
+
+ /* Fill SPI MTD partitions for Linux kernel on Espressobin */
+ if (!of_machine_is_compatible("marvell,armada-3720-espressobin"))
+ return 0;
+
+ spi_off = fdt_node_offset_by_compatible(blob, -1, "jedec,spi-nor");
+ if (spi_off < 0)
+ return 0;
+
+ /* Do not touch partitions if they are already defined */
+ if (fdt_subnode_offset(blob, spi_off, "partitions") >= 0)
+ return 0;
+
+ parts_off = fdt_add_subnode(blob, spi_off, "partitions");
+ if (parts_off < 0) {
+ printf("Can't add partitions node: %s\n",
fdt_strerror(parts_off));
+ return 0;
+ }
+
+ ret = fdt_setprop_string(blob, parts_off, "compatible",
"fixed-partitions");
+ if (ret < 0) {
+ printf("Can't set compatible property: %s\n",
fdt_strerror(ret));
+ return 0;
+ }
+
+ ret = fdt_setprop_u32(blob, parts_off, "#address-cells", 1);
+ if (ret < 0) {
+ printf("Can't set #address-cells property: %s\n",
fdt_strerror(ret));
+ return 0;
+ }
+
+ ret = fdt_setprop_u32(blob, parts_off, "#size-cells", 1);
+ if (ret < 0) {
+ printf("Can't set #size-cells property: %s\n",
fdt_strerror(ret));
+ return 0;
+ }
+
+ /* Add u-boot-env partition */
+
+ part_off = fdt_add_subnode(blob, parts_off, "partition@u-boot-env");
+ if (part_off < 0) {
+ printf("Can't add partition@u-boot-env node: %s\n",
fdt_strerror(part_off));
+ return 0;
+ }
+
+ ret = fdt_setprop_u32(blob, part_off, "reg", CONFIG_ENV_OFFSET);
+ if (ret < 0) {
+ printf("Can't set partition@u-boot-env reg property: %s\n",
fdt_strerror(ret));
+ return 0;
+ }
+
+ ret = fdt_appendprop_u32(blob, part_off, "reg", CONFIG_ENV_SIZE);
+ if (ret < 0) {
+ printf("Can't set partition@u-boot-env reg property: %s\n",
fdt_strerror(ret));
+ return 0;
+ }
+
+ ret = fdt_setprop_string(blob, part_off, "label", "u-boot-env");
+ if (ret < 0) {
+ printf("Can't set partition@u-boot-env label property: %s\n",
fdt_strerror(ret));
+ return 0;
+ }
+
+ /* Add firmware partition */
+
+ part_off = fdt_add_subnode(blob, parts_off, "partition@firmware");
+ if (part_off < 0) {
+ printf("Can't add partition@firmware node: %s\n",
fdt_strerror(part_off));
+ return 0;
+ }
+
+ ret = fdt_setprop_u32(blob, part_off, "reg", 0);
+ if (ret < 0) {
+ printf("Can't set partition@firmware reg property: %s\n",
fdt_strerror(ret));
+ return 0;
+ }
+
+ ret = fdt_appendprop_u32(blob, part_off, "reg", CONFIG_ENV_OFFSET);
+ if (ret < 0) {
+ printf("Can't set partition@firmware reg property: %s\n",
fdt_strerror(ret));
+ return 0;
+ }
+
+ ret = fdt_setprop_string(blob, part_off, "label", "firmware");
+ if (ret < 0) {
+ printf("Can't set partition@firmware label property: %s\n",
fdt_strerror(ret));
+ return 0;
+ }
+
+ return 0;
+}
+#endif
diff --git a/configs/mvebu_espressobin-88f3720_defconfig
b/configs/mvebu_espressobin-88f3720_defconfig
index afcdd947c1..0c1c92d4ff 100644
--- a/configs/mvebu_espressobin-88f3720_defconfig
+++
[PATCH 2/2] arm: dts: a37x0: enable sd card support on espressobin
From: Wilson Ding
Enabled SDIO slot 0 (south bridge) for SD card on
Espressobin board.
Change-Id: I51a2debf9fba276b9c4a2bc6da91328d47f443e3
Signed-off-by: Wilson Ding
Signed-off-by: Konstantin Porotchkin
Reviewed-on: http://vgitil04.il.marvell.com:8080/60945
Tested-by: iSoC Platform CI
Reviewed-by: Igal Liberman
[pali: Define cd-gpios and enable CONFIG_DM_REGULATOR_GPIO]
Signed-off-by: Pali Rohár
---
arch/arm/dts/armada-3720-espressobin.dts| 20
configs/mvebu_espressobin-88f3720_defconfig | 1 +
2 files changed, 21 insertions(+)
diff --git a/arch/arm/dts/armada-3720-espressobin.dts
b/arch/arm/dts/armada-3720-espressobin.dts
index f10a953ec5..92eddca6c0 100644
--- a/arch/arm/dts/armada-3720-espressobin.dts
+++ b/arch/arm/dts/armada-3720-espressobin.dts
@@ -67,6 +67,17 @@
device_type = "memory";
reg = <0x 0x 0x 0x2000>;
};
+
+ vcc_sd_reg0: regulator@0 {
+ compatible = "regulator-gpio";
+ regulator-name = "vcc_sd0";
+ regulator-min-microvolt = <180>;
+ regulator-max-microvolt = <330>;
+ regulator-type = "voltage";
+ states = <180 0x1
+ 330 0x0>;
+ gpios = < 4 GPIO_ACTIVE_HIGH>;
+ };
};
{
@@ -110,6 +121,15 @@
status = "okay";
};
+ {
+ pinctrl-names = "default";
+ pinctrl-0 = <_pins>;
+ bus-width = <4>;
+ cd-gpios = < 3 GPIO_ACTIVE_LOW>;
+ vqmmc-supply = <_sd_reg0>;
+ status = "okay";
+};
+
{
status = "okay";
pinctrl-names = "default";
diff --git a/configs/mvebu_espressobin-88f3720_defconfig
b/configs/mvebu_espressobin-88f3720_defconfig
index 495faf43a3..933592af88 100644
--- a/configs/mvebu_espressobin-88f3720_defconfig
+++ b/configs/mvebu_espressobin-88f3720_defconfig
@@ -81,3 +81,4 @@ CONFIG_USB_ETHER_SMSC95XX=y
CONFIG_SHA1=y
CONFIG_SHA256=y
CONFIG_MVNETA=y
+CONFIG_DM_REGULATOR_GPIO=y
--
2.20.1
[PATCH 1/2] mmc: xenon: set signal voltage and max base clock
From: Evan Wang
- The SDIO signal voltage and max base clock frequency
setting are missing in driver, which causes SDIO
not working.
- The patch adds SDIO signal voltage switch support,
which is based on regulator-gpio of vqmmc-supply, and
sets the max base clock frequency.
- Fix the zero clock value in call to sdhci_setup_cfg()
function.
Change-Id: I79c8860c65b8db166f4f70db56ede4097f71f1fa
Signed-off-by: Evan Wang
Reviewed-on: http://vgitil04.il.marvell.com:8080/53589
Reviewed-by: Hua Jing
Tested-by: Hua Jing
[pali: Amended fixup patch]
Signed-off-by: Pali Rohár
---
drivers/mmc/xenon_sdhci.c | 79 ++-
1 file changed, 78 insertions(+), 1 deletion(-)
diff --git a/drivers/mmc/xenon_sdhci.c b/drivers/mmc/xenon_sdhci.c
index 356dd9846d..7f9a579c83 100644
--- a/drivers/mmc/xenon_sdhci.c
+++ b/drivers/mmc/xenon_sdhci.c
@@ -22,6 +22,7 @@
#include
#include
#include
+#include
DECLARE_GLOBAL_DATA_PTR;
@@ -42,6 +43,14 @@ DECLARE_GLOBAL_DATA_PTR;
#define SDHC_SYS_EXT_OP_CTRL 0x010C
#define MASK_CMD_CONFLICT_ERRORBIT(8)
+#define SDHC_SLOT_EMMC_CTRL0x0130
+#define ENABLE_DATA_STROBE_SHIFT 24
+#define SET_EMMC_RSTN_SHIFT16
+#define EMMC_VCCQ_MASK 0x3
+#define EMMC_VCCQ_1_8V 0x1
+#define EMMC_VCCQ_1_2V 0x2
+#defineEMMC_VCCQ_3_3V 0x3
+
#define SDHC_SLOT_RETUNING_REQ_CTRL0x0144
/* retuning compatible */
#define RETUNING_COMPATIBLE0x1
@@ -108,6 +117,8 @@ DECLARE_GLOBAL_DATA_PTR;
#define MMC_TIMING_MMC_HS400 10
#define XENON_MMC_MAX_CLK 4
+#define XENON_MMC_3V3_UV 330
+#define XENON_MMC_1V8_UV 180
enum soc_pad_ctrl_type {
SOC_PAD_SD,
@@ -128,6 +139,8 @@ struct xenon_sdhci_priv {
void *pad_ctrl_reg;
int pad_type;
+
+ struct udevice *vqmmc;
};
static int xenon_mmc_phy_init(struct sdhci_host *host)
@@ -208,6 +221,51 @@ static void armada_3700_soc_pad_voltage_set(struct
sdhci_host *host)
writel(ARMADA_3700_SOC_PAD_3_3V, priv->pad_ctrl_reg);
}
+static int xenon_mmc_start_signal_voltage_switch(struct sdhci_host *host)
+{
+ struct xenon_sdhci_priv *priv = host->mmc->priv;
+ u8 voltage;
+ u32 ctrl;
+ int ret = 0;
+
+ /* If there is no vqmmc regulator, return */
+ if (!priv->vqmmc)
+ return 0;
+
+ if (priv->pad_type == SOC_PAD_FIXED_1_8V) {
+ /* Switch to 1.8v */
+ ret = regulator_set_value(priv->vqmmc,
+ XENON_MMC_1V8_UV);
+ } else if (priv->pad_type == SOC_PAD_SD) {
+ /* Get voltage info */
+ voltage = sdhci_readb(host, SDHCI_POWER_CONTROL);
+ voltage &= ~SDHCI_POWER_ON;
+
+ if (voltage == SDHCI_POWER_330) {
+ /* Switch to 3.3v */
+ ret = regulator_set_value(priv->vqmmc,
+ XENON_MMC_3V3_UV);
+ } else {
+ /* Switch to 1.8v */
+ ret = regulator_set_value(priv->vqmmc,
+ XENON_MMC_1V8_UV);
+ }
+ }
+
+ /* Set VCCQ, eMMC mode: 1.8V; SD/SDIO mode: 3.3V */
+ ctrl = sdhci_readl(host, SDHC_SLOT_EMMC_CTRL);
+ if (IS_SD(host->mmc))
+ ctrl |= EMMC_VCCQ_3_3V;
+ else
+ ctrl |= EMMC_VCCQ_1_8V;
+ sdhci_writel(host, ctrl, SDHC_SLOT_EMMC_CTRL);
+
+ if (ret)
+ printf("Signal voltage switch fail\n");
+
+ return ret;
+}
+
static void xenon_mmc_phy_set(struct sdhci_host *host)
{
struct xenon_sdhci_priv *priv = host->mmc->priv;
@@ -334,6 +392,13 @@ static int xenon_sdhci_set_ios_post(struct sdhci_host
*host)
uint speed = host->mmc->tran_speed;
int pwr_18v = 0;
+ /*
+* Signal Voltage Switching is only applicable for Host Controllers
+* v3.00 and above.
+*/
+ if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
+ xenon_mmc_start_signal_voltage_switch(host);
+
if ((sdhci_readb(host, SDHCI_POWER_CONTROL) & ~SDHCI_POWER_ON) ==
SDHCI_POWER_180)
pwr_18v = 1;
@@ -394,6 +459,18 @@ static int xenon_sdhci_probe(struct udevice *dev)
/* Set default timing */
priv->timing = MMC_TIMING_LEGACY;
+ /* Get the vqmmc regulator if there is */
+ device_get_supply_regulator(dev, "vqmmc-supply", >vqmmc);
+ /* Set the initial voltage value to 3.3V if there is regulator */
+ if (priv->vqmmc) {
+ ret = regulator_set_value(priv->vqmmc,
+ XENON_MMC_3V3_UV);
+ if (ret) {
+
[PATCH 0/2] arm: mvebu: Espressobin: Add support for SD card
This patch series contains two patches from Marvell's U-Boot repository https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/ which add support for SD card on Espressobin board. I slightly modified them for current mainline U-Boot version. It allows U-Boot to load and boot Linux kernel from uSD card. Evan Wang (1): mmc: xenon: set signal voltage and max base clock Wilson Ding (1): arm: dts: a37x0: enable sd card support on espressobin arch/arm/dts/armada-3720-espressobin.dts| 20 ++ configs/mvebu_espressobin-88f3720_defconfig | 1 + drivers/mmc/xenon_sdhci.c | 79 - 3 files changed, 99 insertions(+), 1 deletion(-) -- 2.20.1
Re: [PATCH v2 4/9] mips: octeon: Add octeon_ddr.h header
Am Montag, den 17.08.2020, 14:12 +0200 schrieb Stefan Roese:
> From: Aaron Williams
>
> This header will be used by the DDR driver (lmc). Its ported from the
> 2013 Cavium / Marvell U-Boot repository.
>
> Signed-off-by: Aaron Williams
> Signed-off-by: Stefan Roese
>
> ---
>
> Changes in v2:
> - Use readq/writeq in cvmx_read64_uint64/cvmx_write64_uint64 instead of
> readl/writel
>
> .../mach-octeon/include/mach/octeon_ddr.h | 988 ++
> 1 file changed, 988 insertions(+)
> create mode 100644 arch/mips/mach-octeon/include/mach/octeon_ddr.h
>
> diff --git a/arch/mips/mach-octeon/include/mach/octeon_ddr.h
> b/arch/mips/mach-octeon/include/mach/octeon_ddr.h
> new file mode 100644
> index 00..630231a191
> --- /dev/null
> +++ b/arch/mips/mach-octeon/include/mach/octeon_ddr.h
> @@ -0,0 +1,988 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Copyright (C) 2020 Marvell International Ltd.
> + *
> + * https://spdx.org/licenses
this line is superfluous
> + */
> +
> +#ifndef __OCTEON_DDR_H_
> +#define __OCTEON_DDR_H_
> +
> +#include
> +#include
> +#include
> +#include
> +#include
don't pull unneeded headers. Especially avoid common.h in new code.
> +#include
> +#include
> +
> +/* Mapping is done starting from 0x11800.8000 */
> +#define CVMX_L2C_CTL 0x0080
> +#define CVMX_L2C_BIG_CTL 0x00800030
> +#define CVMX_L2C_TADX_INT(i) (0x00a00028 + (((i) & 7) * 0x4))
> +#define CVMX_L2C_MCIX_INT(i) (0x00c00028 + (((i) & 3) * 0x4))
> +
> +/* Some "external" (non-LMC) registers */
> +#define CVMX_IPD_CLK_COUNT 0x00014F000338
> +#define CVMX_FPA_CLK_COUNT 0x000128F0
> +
> +#define CVMX_NODE_MEM_SHIFT 40
> +
> +#define DDR_INTERFACE_MAX4
> +
> +/* Private data struct */
> +struct ddr_priv {
> + void __iomem *lmc_base;
> + void __iomem *l2c_base;
> +
> + bool ddr_clock_initialized[DDR_INTERFACE_MAX];
> + bool ddr_memory_preserved;
> + u32 flags;
> +
> + struct ram_info info;
> +};
> +
> +/* Short cut to convert a number to megabytes */
> +#define MB(X)((u64)(X) * (u64)(1024 * 1024))
> +
> +#define octeon_is_cpuid(x) (__OCTEON_IS_MODEL_COMPILE__(x, read_c0_prid()))
> +
> +#define strtoull simple_strtoull
> +
> +/* Access LMC registers */
> +static inline u64 lmc_rd(struct ddr_priv *priv, u64 addr)
> +{
> + return ioread64(priv->lmc_base + addr);
> +}
> +
> +static inline void lmc_wr(struct ddr_priv *priv, u64 addr, u64 val)
> +{
> + iowrite64(val, priv->lmc_base + addr);
> +}
> +
> +/* Access L2C registers */
> +static inline u64 l2c_rd(struct ddr_priv *priv, u64 addr)
> +{
> + return ioread64(priv->l2c_base + addr);
> +}
> +
> +static inline void l2c_wr(struct ddr_priv *priv, u64 addr, u64 val)
> +{
> + iowrite64(val, priv->l2c_base + addr);
> +}
> +
> +/* Access other CSR registers not located inside the LMC address space */
> +static inline u64 csr_rd(u64 addr)
> +{
> + void __iomem *base;
> +
> + base = ioremap_nocache(addr, 0x100);
> + return ioread64(base);
> +}
> +
> +static inline void csr_wr(u64 addr, u64 val)
> +{
> + void __iomem *base;
> +
> + base = ioremap_nocache(addr, 0x100);
> + return iowrite64(val, base);
> +}
> +
> +/* "Normal" access, without any offsets and/or mapping */
> +static inline u64 cvmx_read64_uint64(u64 addr)
> +{
> + return readq((void *)addr);
> +}
> +
> +static inline void cvmx_write64_uint64(u64 addr, u64 val)
> +{
> + writeq(val, (void *)addr);
> +}
> +
> +/* Failsafe mode */
> +#define FLAG_FAILSAFE_MODE 0x01000
> +/* Note that the DDR clock initialized flags must be contiguous */
> +/* Clock for DDR 0 initialized */
> +#define FLAG_DDR0_CLK_INITIALIZED0x02000
> +/* Clock for DDR 1 initialized */
> +#define FLAG_DDR1_CLK_INITIALIZED0x04000
> +/* Clock for DDR 2 initialized */
> +#define FLAG_DDR2_CLK_INITIALIZED0x08000
> +/* Clock for DDR 3 initialized */
> +#define FLAG_DDR3_CLK_INITIALIZED0x1
> +/* Loaded into RAM externally */
> +#define FLAG_RAM_RESIDENT0x2
> +/* Verbose DDR information */
> +#define FLAG_DDR_VERBOSE 0x4
> +/* Check env. for DDR variables */
> +#define FLAG_DDR_DEBUG 0x8
> +#define FLAG_DDR_TRACE_INIT 0x10
> +#define FLAG_MEMORY_PRESERVED0x20
> +#define FLAG_DFM_VERBOSE 0x40
> +#define FLAG_DFM_TRACE_INIT 0x80
> +/* DFM memory clock initialized */
> +#define FLAG_DFM_CLK_INITIALIZED 0x100
> +/* EEPROM clock descr. missing */
> +#define FLAG_CLOCK_DESC_MISSING 0x200
> +/* EEPROM board descr. missing */
> +#define FLAG_BOARD_DESC_MISSING 0x400
> +#define FLAG_DDR_PROMPT 0x800
> +
> +#ifndef DDR_NO_DEBUG
> +static inline int ddr_verbose(struct ddr_priv *priv)
> +{
> + return !!(priv->flags & FLAG_DDR_VERBOSE);
> +}
> +
> +static
Re: [PATCH v2 3/9] mips: octeon Add cvmx/cvmx-lmcx-defs.h header
Am Montag, den 17.08.2020, 14:12 +0200 schrieb Stefan Roese: > From: Aaron Williams > > This header will be used by the DDR driver (lmc). Its ported from the > 2013 Cavium / Marvell U-Boot repository. > > Signed-off-by: Aaron Williams > Signed-off-by: Stefan Roese > > --- > > Changes in v2: > - Some unsupported Octeon families removed (only Octeon 2 & 3 supported > in general) > > .../include/mach/cvmx/cvmx-lmcx-defs.h| 4576 + > 1 file changed, 4576 insertions(+) > create mode 100644 arch/mips/mach-octeon/include/mach/cvmx/cvmx-lmcx-defs.h > > diff --git a/arch/mips/mach-octeon/include/mach/cvmx/cvmx-lmcx-defs.h > b/arch/mips/mach-octeon/include/mach/cvmx/cvmx-lmcx-defs.h > new file mode 100644 > index 00..5361aeecf8 > --- /dev/null > +++ b/arch/mips/mach-octeon/include/mach/cvmx/cvmx-lmcx-defs.h > @@ -0,0 +1,4576 @@ > +/* SPDX-License-Identifier: GPL-2.0 */ > +/* > + * Copyright (C) 2020 Marvell International Ltd. > + * > + * https://spdx.org/licenses this line is superfluous > + */ > + > +#ifndef __CVMX_LMCX_DEFS_H__ > +#define __CVMX_LMCX_DEFS_H__ > + > +#define CVMX_LMCX_BANK_CONFLICT1(offs) \ > + ((0x000360ull) + ((offs) & 3) * 0x100ull) > +#define CVMX_LMCX_BANK_CONFLICT2(offs) \ > + ((0x000368ull) + ((offs) & 3) * 0x100ull) > +#define CVMX_LMCX_BIST_RESULT(offs) \ > + ((0xF8ull) + ((offs) & 1) * 0x6000ull) > +#define CVMX_LMCX_CHAR_CTL(offs) \ > + ((0x000220ull) + ((offs) & 3) * 0x100ull) > +#define CVMX_LMCX_CHAR_DQ_ERR_COUNT(offs)\ > + ((0x40ull) + ((offs) & 3) * 0x100ull) > +#define CVMX_LMCX_CHAR_MASK0(offs) \ > + ((0x000228ull) + ((offs) & 3) * 0x100ull) > +#define CVMX_LMCX_CHAR_MASK1(offs) \ > + ((0x000230ull) + ((offs) & 3) * 0x100ull) > +#define CVMX_LMCX_CHAR_MASK2(offs) \ > + ((0x000238ull) + ((offs) & 3) * 0x100ull) > +#define CVMX_LMCX_CHAR_MASK3(offs) \ > + ((0x000240ull) + ((offs) & 3) * 0x100ull) > +#define CVMX_LMCX_CHAR_MASK4(offs) \ > + ((0x000318ull) + ((offs) & 3) * 0x100ull) > +#define CVMX_LMCX_COMP_CTL(offs) \ > + ((0x28ull) + ((offs) & 1) * 0x6000ull) > +#define CVMX_LMCX_COMP_CTL2(offs)\ > + ((0x0001B8ull) + ((offs) & 3) * 0x100ull) > +#define CVMX_LMCX_CONFIG(offs) \ > + ((0x000188ull) + ((offs) & 3) * 0x100ull) > +#define CVMX_LMCX_CONTROL(offs) \ > + ((0x000190ull) + ((offs) & 3) * 0x100ull) > +#define CVMX_LMCX_CTL(offs) \ > + ((0x10ull) + ((offs) & 1) * 0x6000ull) > +#define CVMX_LMCX_CTL1(offs) \ > + ((0x90ull) + ((offs) & 1) * 0x6000ull) > +#define CVMX_LMCX_DBTRAIN_CTL(offs) \ > + ((0x0003F8ull) + ((offs) & 3) * 0x100ull) > +#define CVMX_LMCX_DCLK_CNT(offs) \ > + ((0x0001E0ull) + ((offs) & 3) * 0x100ull) > +#define CVMX_LMCX_DCLK_CNT_HI(offs) \ > + ((0x70ull) + ((offs) & 1) * 0x6000ull) > +#define CVMX_LMCX_DCLK_CNT_LO(offs) \ > + ((0x68ull) + ((offs) & 1) * 0x6000ull) > +#define CVMX_LMCX_DCLK_CTL(offs) \ > + ((0xB8ull) + ((offs) & 1) * 0x6000ull) > +#define CVMX_LMCX_DDR2_CTL(offs) \ > + ((0x18ull) + ((offs) & 1) * 0x6000ull) > +#define CVMX_LMCX_DDR4_DIMM_CTL(offs)\ > + ((0x0003F0ull) + ((offs) & 3) * 0x100ull) > +#define CVMX_LMCX_DDR_PLL_CTL(offs) \ > + ((0x000258ull) + ((offs) & 3) * 0x100ull) > +#define CVMX_LMCX_DELAY_CFG(offs)\ > + ((0x88ull) + ((offs) & 1) * 0x6000ull) > +#define CVMX_LMCX_DIMMX_DDR4_PARAMS0(offs, id) > \ > + ((0xD0ull) + (((offs) & 1) + ((id) & 3) * 0x20ull) * 8) > +#define CVMX_LMCX_DIMMX_DDR4_PARAMS1(offs, id) > \ > + ((0x000140ull) + (((offs) & 1) + ((id) & 3) * 0x20ull) * 8) > +#define CVMX_LMCX_DIMMX_PARAMS(offs, id) \ > + ((0x000270ull) + (((offs) & 1) + ((id) & 3) * 0x20ull) * 8) > +#define CVMX_LMCX_DIMM_CTL(offs) \ > + ((0x000310ull) + ((offs) & 3) * 0x100ull) > +#define CVMX_LMCX_DLL_CTL(offs) \ > + ((0xC0ull) + ((offs) & 1) * 0x6000ull) > +#define CVMX_LMCX_DLL_CTL2(offs) \ > + ((0x0001C8ull) + ((offs) & 3) * 0x100ull) > +#define CVMX_LMCX_DLL_CTL3(offs) \ > + ((0x000218ull) + ((offs) & 3) * 0x100ull) > +#define CVMX_LMCX_ECC_PARITY_TEST(offs) \ > + ((0x000108ull) + ((offs) & 3) *
Re: [PATCH v2 2/9] mips: octeon: Add octeon-model.h header
Am Montag, den 17.08.2020, 14:12 +0200 schrieb Stefan Roese: > From: Aaron Williams > > This header is used by the upcoming DDR driver and potentially by other > drivers ported from the 2013 Cavium / Marvell U-Boot repository. > > Signed-off-by: Aaron Williams > Signed-off-by: Stefan Roese > > --- > > Changes in v2: > - Some unsupported Octeon families removed (only Octeon 2 & 3 supported > in general) > > .../mach-octeon/include/mach/octeon-model.h | 317 ++ > 1 file changed, 317 insertions(+) > create mode 100644 arch/mips/mach-octeon/include/mach/octeon-model.h > > diff --git a/arch/mips/mach-octeon/include/mach/octeon-model.h > b/arch/mips/mach-octeon/include/mach/octeon-model.h > new file mode 100644 > index 00..209e813a2f > --- /dev/null > +++ b/arch/mips/mach-octeon/include/mach/octeon-model.h > @@ -0,0 +1,317 @@ > +/* SPDX-License-Identifier: GPL-2.0 */ > +/* > + * Copyright (C) 2020 Marvell International Ltd. > + * > + * https://spdx.org/licenses this line is superfluous > + */ > + > +#ifndef __OCTEON_MODEL_H__ > +#define __OCTEON_MODEL_H__ > + > +/* NOTE: These must match what is checked in common-config.mk */ > +/* Defines to represent the different versions of Octeon. */ > + > +/* > + * IMPORTANT: When the default pass is updated for an Octeon Model, > + * the corresponding change must also be made in the oct-sim script. > + */ > + > +/* > + * The defines below should be used with the OCTEON_IS_MODEL() macro to > + * determine what model of chip the software is running on. Models ending > + * in 'XX' match multiple models (families), while specific models match only > + * that model. If a pass (revision) is specified, then only that revision > + * will be matched. Care should be taken when checking for both specific > + * models and families that the specific models are checked for first. > + * While these defines are similar to the processor ID, they are not intended > + * to be used by anything other that the OCTEON_IS_MODEL framework, and > + * the values are subject to change at anytime without notice. > + * > + * NOTE: only the OCTEON_IS_MODEL() macro/function and the OCTEON_CN* macros > + * should be used outside of this file. All other macros are for internal > + * use only, and may change without notice. > + */ should be just one multi-line comment block > + > +#define OCTEON_FAMILY_MASK 0x0000 > +#define OCTEON_PRID_MASK 0x00ff > + > +/* Flag bits in top byte */ > +/* Ignores revision in model checks */ > +#define OM_IGNORE_REVISION0x0100 > +/* Check submodels */ > +#define OM_CHECK_SUBMODEL 0x0200 > +/* Match all models previous than the one specified */ > +#define OM_MATCH_PREVIOUS_MODELS 0x0400 > +/* Ignores the minor revison on newer parts */ > +#define OM_IGNORE_MINOR_REVISION 0x0800 > +#define OM_FLAG_MASK 0xff00 > + > +/* Match all cn5XXX Octeon models. */ > +#define OM_MATCH_5XXX_FAMILY_MODELS 0x2000 > +/* Match all cn6XXX Octeon models. */ > +#define OM_MATCH_6XXX_FAMILY_MODELS 0x4000 > +/* Match all cnf7XXX Octeon models. */ > +#define OM_MATCH_F7XXX_FAMILY_MODELS0x8000 > +/* Match all cn7XXX Octeon models. */ > +#define OM_MATCH_7XXX_FAMILY_MODELS 0x1000 > +#define OM_MATCH_FAMILY_MODELS (OM_MATCH_5XXX_FAMILY_MODELS | \ > + OM_MATCH_6XXX_FAMILY_MODELS | \ > + OM_MATCH_F7XXX_FAMILY_MODELS | \ > + OM_MATCH_7XXX_FAMILY_MODELS) > + > +/* > + * CN7XXX models with new revision encoding > + */ > + > +#define OCTEON_CNF75XX_PASS1_0 0x000d9800 > +#define OCTEON_CNF75XX_PASS1_2 0x000d9802 > +#define OCTEON_CNF75XX_PASS1_3 0x000d9803 > +#define OCTEON_CNF75XX (OCTEON_CNF75XX_PASS1_0 | OM_IGNORE_REVISION) > +#define OCTEON_CNF75XX_PASS1_X \ > + (OCTEON_CNF75XX_PASS1_0 | OM_IGNORE_MINOR_REVISION) > + > +#define OCTEON_CN73XX_PASS1_0 0x000d9700 > +#define OCTEON_CN73XX_PASS1_1 0x000d9701 > +#define OCTEON_CN73XX_PASS1_2 0x000d9702 > +#define OCTEON_CN73XX_PASS1_3 0x000d9703 > +#define OCTEON_CN73XX (OCTEON_CN73XX_PASS1_0 | OM_IGNORE_REVISION) > +#define OCTEON_CN73XX_PASS1_X\ > + (OCTEON_CN73XX_PASS1_0 | OM_IGNORE_MINOR_REVISION) > + > +#define OCTEON_CN72XXOCTEON_CN73XX > + > +#define OCTEON_CN23XXOCTEON_CN73XX > +#define OCTEON_CN23XX_PASS1_2OCTEON_CN73XX_PASS1_2 > +#define OCTEON_CN23XX_PASS1_3OCTEON_CN73XX_PASS1_3 > + > +#define OCTEON_CN70XX_PASS1_0 0x000d9600 > +#define OCTEON_CN70XX_PASS1_1 0x000d9601 > +#define OCTEON_CN70XX_PASS1_2 0x000d9602 > + > +#define OCTEON_CN70XX_PASS2_0 0x000d9608 > + > +#define OCTEON_CN70XX (OCTEON_CN70XX_PASS1_0 | OM_IGNORE_REVISION) > +#define OCTEON_CN70XX_PASS1_X
Re: [PATCH v1 8/8] mips: octeon: octeon_ebb7304_defconfig: Enable USB support
On 19.08.20 15:54, Daniel Schwierzeck wrote: Am Montag, den 17.08.2020, 15:06 +0200 schrieb Stefan Roese: This patch enables USB support with some helpful commands, like fs support. Signed-off-by: Stefan Roese --- configs/octeon_ebb7304_defconfig | 17 + 1 file changed, 17 insertions(+) diff --git a/configs/octeon_ebb7304_defconfig b/configs/octeon_ebb7304_defconfig index 105fe5b00a..a98d73a268 100644 --- a/configs/octeon_ebb7304_defconfig +++ b/configs/octeon_ebb7304_defconfig @@ -15,12 +15,19 @@ CONFIG_HUSH_PARSER=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MTD=y +CONFIG_CMD_PART=y CONFIG_CMD_PCI=y +CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_CMD_PING=y CONFIG_CMD_TIME=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +# CONFIG_DOS_PARTITION is not set CONFIG_ENV_IS_IN_FLASH=y CONFIG_ENV_ADDR=0x1FBFE000 +CONFIG_BLK=y CONFIG_CLK=y # CONFIG_INPUT is not set CONFIG_MTD=y @@ -48,4 +55,14 @@ CONFIG_SPI=y CONFIG_OCTEON_SPI=y CONFIG_SYSRESET=y CONFIG_SYSRESET_OCTEON=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_ASIX88179=y +CONFIG_USB_ETHER_MCS7830=y +CONFIG_USB_ETHER_RTL8152=y +CONFIG_USB_ETHER_SMSC95XX=y is it intentional to enable all USB ethernet drivers? Yes. As we currently don't have support for the integrated ethernet controller(s), I wanted to give the user as many choices of supported USB ethernet adapters as possible. Thanks, Stefan
[PATCH 1/2] arm64: a37xx: pci: Make PCIe Reset GPIO DT compatible with Linux kernel DT
Change active-high to active-low and change DT property name from
reset-gpio to reset-gpios. This format of gpio reset is used by
pci-aardvark driver in Linux kernel.
Signed-off-by: Pali Rohár
---
arch/arm/dts/armada-3720-db.dts | 2 +-
arch/arm/dts/armada-3720-espressobin.dts | 2 +-
arch/arm/dts/armada-3720-turris-mox.dts | 2 +-
drivers/pci/pci-aardvark.c | 6 +++---
4 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/arch/arm/dts/armada-3720-db.dts b/arch/arm/dts/armada-3720-db.dts
index 1b219c423b..1b1b66b94d 100644
--- a/arch/arm/dts/armada-3720-db.dts
+++ b/arch/arm/dts/armada-3720-db.dts
@@ -159,6 +159,6 @@
{
pinctrl-names = "default";
pinctrl-0 = <_pins>;
- reset-gpio = < 3 GPIO_ACTIVE_HIGH>;
+ reset-gpios = < 3 GPIO_ACTIVE_LOW>;
status = "okay";
};
diff --git a/arch/arm/dts/armada-3720-espressobin.dts
b/arch/arm/dts/armada-3720-espressobin.dts
index 84e2c2adba..f10a953ec5 100644
--- a/arch/arm/dts/armada-3720-espressobin.dts
+++ b/arch/arm/dts/armada-3720-espressobin.dts
@@ -145,6 +145,6 @@
{
pinctrl-names = "default";
pinctrl-0 = <_pins>;
- reset-gpio = < 3 GPIO_ACTIVE_HIGH>;
+ reset-gpios = < 3 GPIO_ACTIVE_LOW>;
status = "okay";
};
diff --git a/arch/arm/dts/armada-3720-turris-mox.dts
b/arch/arm/dts/armada-3720-turris-mox.dts
index 0f0a6ce65d..974270cc8c 100644
--- a/arch/arm/dts/armada-3720-turris-mox.dts
+++ b/arch/arm/dts/armada-3720-turris-mox.dts
@@ -172,6 +172,6 @@
{
pinctrl-names = "default";
pinctrl-0 = <_pins>;
- reset-gpio = < 3 GPIO_ACTIVE_HIGH>;
+ reset-gpios = < 3 GPIO_ACTIVE_LOW>;
status = "disabled";
};
diff --git a/drivers/pci/pci-aardvark.c b/drivers/pci/pci-aardvark.c
index 711b930d0f..5b3f23c184 100644
--- a/drivers/pci/pci-aardvark.c
+++ b/drivers/pci/pci-aardvark.c
@@ -616,7 +616,7 @@ static int pcie_advk_probe(struct udevice *dev)
#if CONFIG_IS_ENABLED(DM_GPIO)
struct gpio_desc reset_gpio;
- gpio_request_by_name(dev, "reset-gpio", 0, _gpio,
+ gpio_request_by_name(dev, "reset-gpios", 0, _gpio,
GPIOD_IS_OUT);
/*
* Issue reset to add-in card through the dedicated GPIO.
@@ -633,9 +633,9 @@ static int pcie_advk_probe(struct udevice *dev)
*/
if (dm_gpio_is_valid(_gpio)) {
dev_dbg(pcie->dev, "Toggle PCIE Reset GPIO ...\n");
- dm_gpio_set_value(_gpio, 0);
- mdelay(200);
dm_gpio_set_value(_gpio, 1);
+ mdelay(200);
+ dm_gpio_set_value(_gpio, 0);
}
#else
dev_dbg(pcie->dev, "PCIE Reset on GPIO support is missing\n");
--
2.20.1
[PATCH 2/2] arm64: a37xx: pci: Assert PERST# signal when unloading driver
This change ensures that PCIe card is put into reset state when U-Boot
stops using it.
DM_FLAG_OS_PREPARE ensures that U-Boot executes driver's remove callback
prior booting Linux kernel.
Linux kernel pci-aardvark driver needs to reset PCIe card via PERST# signal
prior initializing it. If it does not issue reset then some PCIe cards
(specially Compex WiFi cards) are not detected at all.
Putting PCIe card into reset state prior booting Linux kernel would ensure
that card would be properly reset at time when Linux kernel starts
initializing pci-aardvark driver.
Signed-off-by: Pali Rohár
---
drivers/pci/pci-aardvark.c | 27 +--
1 file changed, 21 insertions(+), 6 deletions(-)
diff --git a/drivers/pci/pci-aardvark.c b/drivers/pci/pci-aardvark.c
index 5b3f23c184..8996be5309 100644
--- a/drivers/pci/pci-aardvark.c
+++ b/drivers/pci/pci-aardvark.c
@@ -148,6 +148,9 @@ struct pcie_advk {
void *base;
intfirst_busno;
struct udevice *dev;
+#if CONFIG_IS_ENABLED(DM_GPIO)
+ struct gpio_desc reset_gpio;
+#endif
};
static inline void advk_writel(struct pcie_advk *pcie, uint val, uint reg)
@@ -614,9 +617,7 @@ static int pcie_advk_probe(struct udevice *dev)
struct pcie_advk *pcie = dev_get_priv(dev);
#if CONFIG_IS_ENABLED(DM_GPIO)
- struct gpio_desc reset_gpio;
-
- gpio_request_by_name(dev, "reset-gpios", 0, _gpio,
+ gpio_request_by_name(dev, "reset-gpios", 0, >reset_gpio,
GPIOD_IS_OUT);
/*
* Issue reset to add-in card through the dedicated GPIO.
@@ -631,11 +632,11 @@ static int pcie_advk_probe(struct udevice *dev)
* possible before PCIe PHY initialization. Moreover, the PCIe
* clock should be gated as well.
*/
- if (dm_gpio_is_valid(_gpio)) {
+ if (dm_gpio_is_valid(>reset_gpio)) {
dev_dbg(pcie->dev, "Toggle PCIE Reset GPIO ...\n");
- dm_gpio_set_value(_gpio, 1);
+ dm_gpio_set_value(>reset_gpio, 1);
mdelay(200);
- dm_gpio_set_value(_gpio, 0);
+ dm_gpio_set_value(>reset_gpio, 0);
}
#else
dev_dbg(pcie->dev, "PCIE Reset on GPIO support is missing\n");
@@ -647,6 +648,18 @@ static int pcie_advk_probe(struct udevice *dev)
return pcie_advk_setup_hw(pcie);
}
+static int pcie_advk_remove(struct udevice *dev)
+{
+#if CONFIG_IS_ENABLED(DM_GPIO)
+ struct pcie_advk *pcie = dev_get_priv(dev);
+
+ if (dm_gpio_is_valid(>reset_gpio))
+ dm_gpio_set_value(>reset_gpio, 1);
+#endif /* DM_GPIO */
+
+ return 0;
+}
+
/**
* pcie_advk_ofdata_to_platdata() - Translate from DT to device state
*
@@ -687,5 +700,7 @@ U_BOOT_DRIVER(pcie_advk) = {
.ops= _advk_ops,
.ofdata_to_platdata = pcie_advk_ofdata_to_platdata,
.probe = pcie_advk_probe,
+ .remove = pcie_advk_remove,
+ .flags = DM_FLAG_OS_PREPARE,
.priv_auto_alloc_size = sizeof(struct pcie_advk),
};
--
2.20.1
Re: [PATCH v1 8/8] mips: octeon: octeon_ebb7304_defconfig: Enable USB support
Am Montag, den 17.08.2020, 15:06 +0200 schrieb Stefan Roese: > This patch enables USB support with some helpful commands, like fs > support. > > Signed-off-by: Stefan Roese > > --- > > configs/octeon_ebb7304_defconfig | 17 + > 1 file changed, 17 insertions(+) > > diff --git a/configs/octeon_ebb7304_defconfig > b/configs/octeon_ebb7304_defconfig > index 105fe5b00a..a98d73a268 100644 > --- a/configs/octeon_ebb7304_defconfig > +++ b/configs/octeon_ebb7304_defconfig > @@ -15,12 +15,19 @@ CONFIG_HUSH_PARSER=y > CONFIG_CMD_GPIO=y > CONFIG_CMD_I2C=y > CONFIG_CMD_MTD=y > +CONFIG_CMD_PART=y > CONFIG_CMD_PCI=y > +CONFIG_CMD_USB=y > CONFIG_CMD_DHCP=y > CONFIG_CMD_PING=y > CONFIG_CMD_TIME=y > +CONFIG_CMD_EXT4=y > +CONFIG_CMD_FAT=y > +CONFIG_CMD_FS_GENERIC=y > +# CONFIG_DOS_PARTITION is not set > CONFIG_ENV_IS_IN_FLASH=y > CONFIG_ENV_ADDR=0x1FBFE000 > +CONFIG_BLK=y > CONFIG_CLK=y > # CONFIG_INPUT is not set > CONFIG_MTD=y > @@ -48,4 +55,14 @@ CONFIG_SPI=y > CONFIG_OCTEON_SPI=y > CONFIG_SYSRESET=y > CONFIG_SYSRESET_OCTEON=y > +CONFIG_USB=y > +CONFIG_DM_USB=y > +CONFIG_USB_XHCI_HCD=y > +CONFIG_USB_XHCI_DWC3=y > +CONFIG_USB_HOST_ETHER=y > +CONFIG_USB_ETHER_ASIX=y > +CONFIG_USB_ETHER_ASIX88179=y > +CONFIG_USB_ETHER_MCS7830=y > +CONFIG_USB_ETHER_RTL8152=y > +CONFIG_USB_ETHER_SMSC95XX=y is it intentional to enable all USB ethernet drivers? > CONFIG_HEXDUMP=y -- - Daniel
Re: [PATCH v1 2/8] usb: xhci: xhci_bulk_tx: Don't "BUG" when comparing addresses on Octeon
On 19.08.20 15:49, Daniel Schwierzeck wrote:
Am Montag, den 17.08.2020, 15:06 +0200 schrieb Stefan Roese:
Octeon uses mapped addresses for virtual and physical memory. Its not
that easy to calculate the resulting addresses here. So lets remove
this BUG_ON() for Octeon in xhci_bulk_tx().
Signed-off-by: Stefan Roese
Cc: Bin Meng
Cc: Marek Vasut
---
drivers/usb/host/xhci-ring.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/usb/host/xhci-ring.c b/drivers/usb/host/xhci-ring.c
index 092ed6eaf1..a762177c57 100644
--- a/drivers/usb/host/xhci-ring.c
+++ b/drivers/usb/host/xhci-ring.c
@@ -726,8 +726,11 @@ int xhci_bulk_tx(struct usb_device *udev, unsigned long
pipe,
BUG_ON(TRB_TO_SLOT_ID(field) != slot_id);
BUG_ON(TRB_TO_EP_INDEX(field) != ep_index);
- BUG_ON(*(void **)(uintptr_t)le64_to_cpu(event->trans_event.buffer) -
- buffer > (size_t)length);
+ if (!IS_ENABLED(CONFIG_ARCH_OCTEON)) {
+ BUG_ON(*(void **)(uintptr_t)le64_to_cpu(
+ event->trans_event.buffer) - buffer >
+ (size_t)length);
+ }
why not remove the check? Or add at least a generic Kconfig option for
special handling on archs with memory remapping. Arch or SoC specific
config options in generic code are bad ;)
Yes, I agree. I was also thinking about removing this check completely.
I'm not 100% sure, but I think that some (most?) of these BUG_ON()
macros have been removed from the Linux kernel.
To not make too many changes, I'll change this patch in the next
version to just remove this one BUG_ON().
Thanks,
Stefan
Re: [PATCH v1 5/8] mips: octeon: Add mangle-port.h
On 19.08.20 15:43, Daniel Schwierzeck wrote:
Am Montag, den 17.08.2020, 15:06 +0200 schrieb Stefan Roese:
Import platform specific mangle-port.h header, allowing a area specific
swapping, which is needed on Octeon for USB & PCI areas.
Imported from Linux v5.7.
Signed-off-by: Stefan Roese
---
arch/mips/mach-octeon/include/mangle-port.h | 58 +
1 file changed, 58 insertions(+)
create mode 100644 arch/mips/mach-octeon/include/mangle-port.h
diff --git a/arch/mips/mach-octeon/include/mangle-port.h
b/arch/mips/mach-octeon/include/mangle-port.h
new file mode 100644
index 00..8ff2cbdf2c
--- /dev/null
+++ b/arch/mips/mach-octeon/include/mangle-port.h
@@ -0,0 +1,58 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2003, 2004 Ralf Baechle
+ */
when importing headers from Linux, please remove the license text and
just keep copyrights and optionally additonal info text. At the top
insert the SPDX identifier, e.g.
Okay. Will change in next version.
Thanks,
Stefan
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2003, 2004 Ralf Baechle
*/
+#ifndef __ASM_MACH_GENERIC_MANGLE_PORT_H
+#define __ASM_MACH_GENERIC_MANGLE_PORT_H
+
+#include
+
+#ifdef __BIG_ENDIAN
+
+static inline bool __should_swizzle_bits(volatile void *a)
+{
+ extern const bool octeon_should_swizzle_table[];
+ u64 did = ((u64)(uintptr_t)a >> 40) & 0xff;
+
+ return octeon_should_swizzle_table[did];
+}
+
+# define __swizzle_addr_b(port)(port)
+# define __swizzle_addr_w(port)(port)
+# define __swizzle_addr_l(port)(port)
+# define __swizzle_addr_q(port)(port)
+
+#else /* __LITTLE_ENDIAN */
+
+#define __should_swizzle_bits(a) false
+
+static inline bool __should_swizzle_addr(u64 p)
+{
+ /* boot bus? */
+ return ((p >> 40) & 0xff) == 0;
+}
+
+# define __swizzle_addr_b(port)\
+ (__should_swizzle_addr(port) ? (port) ^ 7 : (port))
+# define __swizzle_addr_w(port)\
+ (__should_swizzle_addr(port) ? (port) ^ 6 : (port))
+# define __swizzle_addr_l(port)\
+ (__should_swizzle_addr(port) ? (port) ^ 4 : (port))
+# define __swizzle_addr_q(port)(port)
+
+#endif /* __BIG_ENDIAN */
+
+
+# define ioswabb(a, x) (x)
+# define __mem_ioswabb(a, x) (x)
+# define ioswabw(a, x) (__should_swizzle_bits(a) ? le16_to_cpu(x) : x)
+# define __mem_ioswabw(a, x) (x)
+# define ioswabl(a, x) (__should_swizzle_bits(a) ? le32_to_cpu(x) : x)
+# define __mem_ioswabl(a, x) (x)
+# define ioswabq(a, x) (__should_swizzle_bits(a) ? le64_to_cpu(x) : x)
+# define __mem_ioswabq(a, x) (x)
+
+#endif /* __ASM_MACH_GENERIC_MANGLE_PORT_H */
Viele Grüße,
Stefan
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-51 Fax: (+49)-8142-66989-80 Email: s...@denx.de
Re: [PATCH v1 2/8] usb: xhci: xhci_bulk_tx: Don't "BUG" when comparing addresses on Octeon
Am Montag, den 17.08.2020, 15:06 +0200 schrieb Stefan Roese:
> Octeon uses mapped addresses for virtual and physical memory. Its not
> that easy to calculate the resulting addresses here. So lets remove
> this BUG_ON() for Octeon in xhci_bulk_tx().
>
> Signed-off-by: Stefan Roese
> Cc: Bin Meng
> Cc: Marek Vasut
> ---
>
> drivers/usb/host/xhci-ring.c | 7 +--
> 1 file changed, 5 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/usb/host/xhci-ring.c b/drivers/usb/host/xhci-ring.c
> index 092ed6eaf1..a762177c57 100644
> --- a/drivers/usb/host/xhci-ring.c
> +++ b/drivers/usb/host/xhci-ring.c
> @@ -726,8 +726,11 @@ int xhci_bulk_tx(struct usb_device *udev, unsigned long
> pipe,
>
> BUG_ON(TRB_TO_SLOT_ID(field) != slot_id);
> BUG_ON(TRB_TO_EP_INDEX(field) != ep_index);
> - BUG_ON(*(void **)(uintptr_t)le64_to_cpu(event->trans_event.buffer) -
> - buffer > (size_t)length);
> + if (!IS_ENABLED(CONFIG_ARCH_OCTEON)) {
> + BUG_ON(*(void **)(uintptr_t)le64_to_cpu(
> +event->trans_event.buffer) - buffer >
> +(size_t)length);
> + }
why not remove the check? Or add at least a generic Kconfig option for
special handling on archs with memory remapping. Arch or SoC specific
config options in generic code are bad ;)
>
> record_transfer_result(udev, event, length);
> xhci_acknowledge_event(ctrl);
--
- Daniel
Re: [PATCH v1 5/8] mips: octeon: Add mangle-port.h
Am Montag, den 17.08.2020, 15:06 +0200 schrieb Stefan Roese:
> Import platform specific mangle-port.h header, allowing a area specific
> swapping, which is needed on Octeon for USB & PCI areas.
>
> Imported from Linux v5.7.
>
> Signed-off-by: Stefan Roese
> ---
>
> arch/mips/mach-octeon/include/mangle-port.h | 58 +
> 1 file changed, 58 insertions(+)
> create mode 100644 arch/mips/mach-octeon/include/mangle-port.h
>
> diff --git a/arch/mips/mach-octeon/include/mangle-port.h
> b/arch/mips/mach-octeon/include/mangle-port.h
> new file mode 100644
> index 00..8ff2cbdf2c
> --- /dev/null
> +++ b/arch/mips/mach-octeon/include/mangle-port.h
> @@ -0,0 +1,58 @@
> +/*
> + * This file is subject to the terms and conditions of the GNU General Public
> + * License. See the file "COPYING" in the main directory of this archive
> + * for more details.
> + *
> + * Copyright (C) 2003, 2004 Ralf Baechle
> + */
when importing headers from Linux, please remove the license text and
just keep copyrights and optionally additonal info text. At the top
insert the SPDX identifier, e.g.
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2003, 2004 Ralf Baechle
*/
> +#ifndef __ASM_MACH_GENERIC_MANGLE_PORT_H
> +#define __ASM_MACH_GENERIC_MANGLE_PORT_H
> +
> +#include
> +
> +#ifdef __BIG_ENDIAN
> +
> +static inline bool __should_swizzle_bits(volatile void *a)
> +{
> + extern const bool octeon_should_swizzle_table[];
> + u64 did = ((u64)(uintptr_t)a >> 40) & 0xff;
> +
> + return octeon_should_swizzle_table[did];
> +}
> +
> +# define __swizzle_addr_b(port) (port)
> +# define __swizzle_addr_w(port) (port)
> +# define __swizzle_addr_l(port) (port)
> +# define __swizzle_addr_q(port) (port)
> +
> +#else /* __LITTLE_ENDIAN */
> +
> +#define __should_swizzle_bits(a) false
> +
> +static inline bool __should_swizzle_addr(u64 p)
> +{
> + /* boot bus? */
> + return ((p >> 40) & 0xff) == 0;
> +}
> +
> +# define __swizzle_addr_b(port) \
> + (__should_swizzle_addr(port) ? (port) ^ 7 : (port))
> +# define __swizzle_addr_w(port) \
> + (__should_swizzle_addr(port) ? (port) ^ 6 : (port))
> +# define __swizzle_addr_l(port) \
> + (__should_swizzle_addr(port) ? (port) ^ 4 : (port))
> +# define __swizzle_addr_q(port) (port)
> +
> +#endif /* __BIG_ENDIAN */
> +
> +
> +# define ioswabb(a, x) (x)
> +# define __mem_ioswabb(a, x) (x)
> +# define ioswabw(a, x) (__should_swizzle_bits(a) ?
> le16_to_cpu(x) : x)
> +# define __mem_ioswabw(a, x) (x)
> +# define ioswabl(a, x) (__should_swizzle_bits(a) ?
> le32_to_cpu(x) : x)
> +# define __mem_ioswabl(a, x) (x)
> +# define ioswabq(a, x) (__should_swizzle_bits(a) ?
> le64_to_cpu(x) : x)
> +# define __mem_ioswabq(a, x) (x)
> +
> +#endif /* __ASM_MACH_GENERIC_MANGLE_PORT_H */
--
- Daniel
Re: [PATCHv2] armv8: MMU: Mark code memory Executable, any other Non-Executable
On Wed, Aug 19, 2020 at 03:17:24PM +0200, Marek Bykowski wrote: > > I think this will have to wait for you to return from holidays and > > investigate more. All I know is that the QEMU models are working as > > expected prior to the patch and fail with it. > > > > -- > > Tom > > From the esr (Exception Syndrome Register) = 0x964F: > - EC (Exception Class) -> it is an exception from data abort > - from ISS (Instruction specific syndrome) -> WnR field set = Abort caused > by Write (not Read), Data Fault Status Code = Permission fault, third level > > It looks like it results as a Write attempted to a read-only region. > Are you sure the tests are devised/designed so that they are not trying to > write to a read-only region? > > @Tom > Probably I could send you a patch with debugging in that will print out all > the necessary information before reaching a prompt (or after a command). > Would you agree to apply and run it? > > What I'm really looking for is the address map with the attributes. Sth around > it: > EL2N:0x-0x3FD35FFF NP:0x-0x3FD35FFF Normal RW C S XN If I recall this failure correctly, it's that qemu fails to boot, with this applied, and that's where things blow up as far as the testing goes. Maybe there's something wrong in board/emulation/qemu-arm/qemu-arm.c ? -- Tom signature.asc Description: PGP signature
[RFCv2 03/16] common: Drop linux/printk.h from common header
From: Simon Glass Move this out of the common header and include it only where needed. Signed-off-by: Simon Glass --- arch/arm/lib/gic-v3-its.c | 1 + arch/arm/mach-imx/imx8/fdt.c | 1 + arch/arm/mach-k3/common.c | 1 + arch/arm/mach-meson/board-gx.c | 1 + arch/arm/mach-omap2/am33xx/board.c | 1 + arch/arm/mach-omap2/utils.c| 1 + arch/arm/mach-rockchip/boot_mode.c | 1 + arch/arm/mach-rockchip/rk3188/rk3188.c | 1 + arch/arm/mach-rockchip/rk3399/rk3399.c | 1 + arch/arm/mach-socfpga/misc.c | 1 + arch/arm/mach-stm32mp/bsec.c | 1 + arch/arm/mach-stm32mp/cmd_stm32key.c | 1 + arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c| 1 + arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c| 1 + arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.h| 2 ++ arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_serial.c | 1 + arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_usb.c| 1 + arch/arm/mach-stm32mp/cpu.c| 1 + arch/arm/mach-stm32mp/include/mach/stm32mp1_smc.h | 1 + arch/arm/mach-tegra/cboot.c| 1 + arch/arm/mach-tegra/ivc.c | 1 + arch/arm/mach-tegra/tegra124/xusb-padctl.c | 1 + arch/arm/mach-tegra/tegra20/clock.c| 1 + arch/arm/mach-tegra/tegra210/xusb-padctl.c | 1 + arch/arm/mach-tegra/tegra30/clock.c| 1 + arch/arm/mach-tegra/xusb-padctl-common.c | 1 + arch/arm/mach-uniphier/boot-device/boot-device.c | 1 + arch/arm/mach-uniphier/clk/dpll-ld4.c | 1 + arch/arm/mach-uniphier/clk/dpll-pro4.c | 1 + arch/arm/mach-uniphier/dram/umc-ld4.c | 1 + arch/arm/mach-uniphier/dram/umc-pro4.c | 1 + arch/arm/mach-uniphier/dram/umc-sld8.c | 1 + arch/arm/mach-uniphier/memconf.c | 1 + arch/arm/mach-uniphier/spl_board_init.c| 1 + arch/riscv/lib/smp.c | 1 + arch/x86/cpu/tangier/pinmux.c | 1 + arch/x86/cpu/tangier/sdram.c | 1 + board/dhelectronics/dh_stm32mp1/board.c| 1 + board/mediatek/mt8518/mt8518_ap1.c | 1 + board/mscc/ocelot/ocelot.c | 1 + board/nvidia/jetson-tk1/jetson-tk1.c | 1 + board/pine64/pinebook-pro-rk3399/pinebook-pro-rk3399.c | 1 + board/samsung/common/exynos5-dt.c | 1 + board/samsung/common/misc.c| 1 + board/samsung/goni/goni.c | 1 + board/samsung/odroid/odroid.c | 1 + board/st/common/stm32mp_dfu.c | 1 + board/st/common/stm32mp_mtdparts.c | 1 + board/st/stm32mp1/stm32mp1.c | 1 + board/sunxi/board.c| 1 + board/synopsys/hsdk/clk-lib.c | 1 + board/synopsys/hsdk/env-lib.c | 1 + board/ti/am65x/evm.c | 1 + board/ti/common/board_detect.c | 1 + board/ti/j721e/evm.c | 1 + board/toradex/apalis-tk1/apalis-tk1.c | 1 + cmd/adc.c | 1 + cmd/fastboot.c | 1 + cmd/nvedit.c | 1 + cmd/onenand.c | 1 + cmd/regulator.c| 1 + cmd/thordown.c | 1 + cmd/tpm_test.c | 1 + cmd/usb_gadget_sdp.c | 1 + cmd/usb_mass_storage.c | 1 + common/dfu.c | 1 + common/spl/spl_dfu.c | 1 + common/spl/spl_fit.c | 1 + common/spl/spl_opensbi.c | 1 + common/spl/spl_sdp.c | 1 + common/update.c| 1 + disk/part_efi.c| 1 + drivers/adc/adc-uclass.c | 1 + drivers/adc/exynos-adc.c | 1 + drivers/adc/meson-saradc.c | 1 + drivers/adc/rockchip-saradc.c | 1 + drivers/adc/sandbox.c | 1 + drivers/ata/dwc_ahci.c | 1 +
Re: [PATCH 4/9] nand: Kconfig: Change dependency for NAND_ARASAN
On 19. 08. 20 15:15, Tom Rini wrote: > On Wed, Aug 19, 2020 at 02:52:11PM +0200, Michal Simek wrote: >> >> >> On 19. 08. 20 14:43, Tom Rini wrote: >>> On Wed, Aug 19, 2020 at 02:36:20PM +0200, Michal Simek wrote: On 19. 08. 20 14:31, Tom Rini wrote: > On Wed, Aug 19, 2020 at 10:44:18AM +0200, Michal Simek wrote: > >> NAND_ARASAN selecting DM_MTD uunconditionally. Driver can be enabled with >> !DM that's why Kconfig it showing it as error: >> >> WARNING: unmet direct dependencies detected for DM_MTD >> Depends on [n]: DM [=n] >> Selected by [y]: >> - NAND_ARASAN [=y] && MTD_RAW_NAND [=y] >> >> Signed-off-by: Michal Simek >> --- >> >> drivers/mtd/nand/raw/Kconfig | 2 +- >> 1 file changed, 1 insertion(+), 1 deletion(-) >> >> diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig >> index 06b2ff972cad..df4cbd52cf5c 100644 >> --- a/drivers/mtd/nand/raw/Kconfig >> +++ b/drivers/mtd/nand/raw/Kconfig >> @@ -233,7 +233,7 @@ endif >> config NAND_ARASAN >> bool "Configure Arasan Nand" >> select SYS_NAND_SELF_INIT >> -select DM_MTD >> +depends on DM_MTD >> imply CMD_NAND >> help >>This enables Nand driver support for Arasan nand flash > > If we can use the driver without DM then we can't depend nor select > DM_MTD. Is someone using the driver still without DM_MTD? > Driver has been converted to DM already. It is used by ZynqMP platforms. And it can't be used without DM_MTD. commit b014b833bd627d27542b50e71df9cf0628f241e7 Author: Ashok Reddy Soma AuthorDate: Thu Dec 19 02:27:42 2019 -0700 Commit: Michal Simek CommitDate: Tue Jan 14 09:05:52 2020 +0100 mtd: nand: Move arasan nand driver to driver model Make changes to arasan nand driver to move it to driver model. Select DM_MTD if arasan nand driver is selected. Signed-off-by: Ashok Reddy Soma Signed-off-by: Michal Simek >>> >>> Ah, I misunderstood the comment, sorry. Yes, this is right then, >>> thanks. >>> >>> Reviewed-by: Tom Rini >>> >> >> ok. I just need to enable this symbol for zynqmp platforms. > > That is the hard part about all of these patches, when you go from > "select X" to "depends on X", you also need to run a script and make > sure that every config that enables the main symbol (NAND_ARASAN) also > enables the now depended on symbol (DM_MTD) and sync the configs after > the change. This one is easy but others can be problematic. But there is serious issue with these symbols. When you run make randconfig you see unfortunately a lot of issues reported. Do you use any tool/script for defconfig update when Kconfig layout has changed? Thanks, Michal signature.asc Description: OpenPGP digital signature
Re: [PATCH 5/5] xen: Code style conformity
On Wed, Aug 19, 2020 at 03:42:21PM +0300, Anastasiia Lukianenko wrote: > From: Anastasiia Lukianenko > > Signed-off-by: Anastasiia Lukianenko Checkpatch still notes: CHECK: Comparison to NULL could be written "err" And please add a commit message saying what you're cleaning up. Thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCHv2] armv8: MMU: Mark code memory Executable, any other Non-Executable
> I think this will have to wait for you to return from holidays and > investigate more. All I know is that the QEMU models are working as > expected prior to the patch and fail with it. > > -- > Tom >From the esr (Exception Syndrome Register) = 0x964F: - EC (Exception Class) -> it is an exception from data abort - from ISS (Instruction specific syndrome) -> WnR field set = Abort caused by Write (not Read), Data Fault Status Code = Permission fault, third level It looks like it results as a Write attempted to a read-only region. Are you sure the tests are devised/designed so that they are not trying to write to a read-only region? @Tom Probably I could send you a patch with debugging in that will print out all the necessary information before reaching a prompt (or after a command). Would you agree to apply and run it? What I'm really looking for is the address map with the attributes. Sth around it: EL2N:0x-0x3FD35FFF NP:0x-0x3FD35FFF Normal RW C S XN Marek
Re: [PATCH 2/5] MAINTAINERS: Add maintainers to XEN section
On Wed, Aug 19, 2020 at 03:42:18PM +0300, Anastasiia Lukianenko wrote: > From: Anastasiia Lukianenko > > Signed-off-by: Anastasiia Lukianenko > --- > MAINTAINERS | 20 > 1 file changed, 20 insertions(+) > > diff --git a/MAINTAINERS b/MAINTAINERS > index 2a281a9a0f..840c7625f1 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -1028,6 +1028,26 @@ T: git > https://gitlab.denx.de/u-boot/custodians/u-boot-x86.git > F: arch/x86/ > F: cmd/x86/ > > +XEN > +M: Anastasiia Lukianenko > +M: Oleksandr Andrushchenko > +S: Maintained > +F: arch/arm/cpu/armv8/xen/ > +F: arch/arm/include/asm/xen.h > +F: arch/arm/include/asm/xen/ > +F: board/xen/xenguest_arm64/ > +F: cmd/pvblock.c > +F: configs/xenguest_arm64_defconfig > +F: doc/board/xen/ > +F: drivers/serial/serial_xen.c > +F: drivers/xen/ > +F: include/configs/xenguest_arm64.h > +F: include/pvblock.h > +F: include/xen/ > +F: include/xen.h > +F: lib/sscanf.c > +F: test/lib/sscanf.c Note that this duplicates some of board/xen/xenguest_arm64/MAINTAINERS and it's probably best to keep the board-specific parts under there anyhow. -- Tom signature.asc Description: PGP signature
Re: [PATCH 1/5] board: xen: Remove unnecessary CONFIG_BOARD_EARLY_INIT_F define and board_early_init_f function
On Wed, Aug 19, 2020 at 03:42:17PM +0300, Anastasiia Lukianenko wrote: > From: Anastasiia Lukianenko > > Signed-off-by: Anastasiia Lukianenko Reviewed-by: Tom Rini -- Tom signature.asc Description: PGP signature
Re: [PATCH 4/9] nand: Kconfig: Change dependency for NAND_ARASAN
On Wed, Aug 19, 2020 at 02:52:11PM +0200, Michal Simek wrote: > > > On 19. 08. 20 14:43, Tom Rini wrote: > > On Wed, Aug 19, 2020 at 02:36:20PM +0200, Michal Simek wrote: > >> On 19. 08. 20 14:31, Tom Rini wrote: > >>> On Wed, Aug 19, 2020 at 10:44:18AM +0200, Michal Simek wrote: > >>> > NAND_ARASAN selecting DM_MTD uunconditionally. Driver can be enabled with > !DM that's why Kconfig it showing it as error: > > WARNING: unmet direct dependencies detected for DM_MTD > Depends on [n]: DM [=n] > Selected by [y]: > - NAND_ARASAN [=y] && MTD_RAW_NAND [=y] > > Signed-off-by: Michal Simek > --- > > drivers/mtd/nand/raw/Kconfig | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig > index 06b2ff972cad..df4cbd52cf5c 100644 > --- a/drivers/mtd/nand/raw/Kconfig > +++ b/drivers/mtd/nand/raw/Kconfig > @@ -233,7 +233,7 @@ endif > config NAND_ARASAN > bool "Configure Arasan Nand" > select SYS_NAND_SELF_INIT > -select DM_MTD > +depends on DM_MTD > imply CMD_NAND > help > This enables Nand driver support for Arasan nand flash > >>> > >>> If we can use the driver without DM then we can't depend nor select > >>> DM_MTD. Is someone using the driver still without DM_MTD? > >>> > >> > >> Driver has been converted to DM already. It is used by ZynqMP platforms. > >> And it can't be used without DM_MTD. > >> > >> commit b014b833bd627d27542b50e71df9cf0628f241e7 > >> Author: Ashok Reddy Soma > >> AuthorDate: Thu Dec 19 02:27:42 2019 -0700 > >> Commit: Michal Simek > >> CommitDate: Tue Jan 14 09:05:52 2020 +0100 > >> > >> mtd: nand: Move arasan nand driver to driver model > >> > >> Make changes to arasan nand driver to move it to driver model. > >> Select DM_MTD if arasan nand driver is selected. > >> > >> Signed-off-by: Ashok Reddy Soma > >> Signed-off-by: Michal Simek > > > > Ah, I misunderstood the comment, sorry. Yes, this is right then, > > thanks. > > > > Reviewed-by: Tom Rini > > > > ok. I just need to enable this symbol for zynqmp platforms. That is the hard part about all of these patches, when you go from "select X" to "depends on X", you also need to run a script and make sure that every config that enables the main symbol (NAND_ARASAN) also enables the now depended on symbol (DM_MTD) and sync the configs after the change. -- Tom signature.asc Description: PGP signature
[RFCv2 15/16] common: Add a comment about the current state of common.h
From: Simon Glass This file still includes the auto-generated config.h header. Add a comment as to why, to help guide further work. Signed-off-by: Simon Glass --- include/common.h | 8 scripts/Makefile.autoconf | 19 +++ 2 files changed, 23 insertions(+), 4 deletions(-) diff --git a/include/common.h b/include/common.h index 1a9a2ce0ea85..2669f93c978f 100644 --- a/include/common.h +++ b/include/common.h @@ -2,17 +2,17 @@ /* * Common header file for U-Boot * - * This file still includes quite a few headers that should be included - * individually as needed. Patches to remove things are welcome. + * This just includes the auto-generated config.h which is documented in + * Makefile.autoconf * * (C) Copyright 2000-2009 * Wolfgang Denk, DENX Software Engineering, w...@denx.de. */ #ifndef __COMMON_H_ -#define __COMMON_H_1 +#define __COMMON_H_ -#ifndef __ASSEMBLY__ /* put C only stuff in this section */ +#ifndef __ASSEMBLY__ #include #endif /* __ASSEMBLY__ */ diff --git a/scripts/Makefile.autoconf b/scripts/Makefile.autoconf index 89882e3c71a4..a0f6783bc7da 100644 --- a/scripts/Makefile.autoconf +++ b/scripts/Makefile.autoconf @@ -99,6 +99,25 @@ tpl/include/autoconf.mk: tpl/u-boot.cfg # include/config.h # Prior to Kconfig, it was generated by mkconfig. Now it is created here. +# This currently has the following contents: +# +# 1. #define CONFIG_BOARDDIR board/... +# 2. #include +# 3. #include +# 4. #include +# 5. #include +# 6. #include +# +# 1 should be able to move to Kconfig +# 2 should be removed by tidying up a few Kconfig items +# 3 uses CONFIG_SYS_CONFIG_NAME and will go away when Kconfig migration is +# completed and all files in include/configs are removed +# 4 should be removed when all CONFIG options in those files move to Kconfig +# 5 is automatically included by the build system (see UBOOTINCLUDE) so is +# already unnecessary +# 6 should be removed by tidying up a few Kconfig items +# +# So all of the above should eventually go away define filechk_config_h (echo "/* Automatically generated - do not edit */";\ for i in $$(echo $(CONFIG_SYS_EXTRA_OPTIONS) | sed 's/,/ /g'); do \ -- 2.17.1
[RFCv2 16/16] Makefile: Drop linux/kconfig.h from config.h
From: Simon Glass
This header always included by the build system (see UBOOTINCLUDE) except
when building tools, so is unnecessary. Drop it and update the
documentation in the common.h header.
Tools generally should not make use of the board config, but a few do.
Update the Atmel pmecc tool to cope with this.
Signed-off-by: Simon Glass
---
scripts/Makefile.autoconf | 8 ++--
tools/atmel_pmecc_params.c | 1 +
2 files changed, 3 insertions(+), 6 deletions(-)
diff --git a/scripts/Makefile.autoconf b/scripts/Makefile.autoconf
index a0f6783bc7da..0339cef1d917 100644
--- a/scripts/Makefile.autoconf
+++ b/scripts/Makefile.autoconf
@@ -105,17 +105,14 @@ tpl/include/autoconf.mk: tpl/u-boot.cfg
# 2. #include
# 3. #include
# 4. #include
-# 5. #include
-# 6. #include
+# 5. #include
#
# 1 should be able to move to Kconfig
# 2 should be removed by tidying up a few Kconfig items
# 3 uses CONFIG_SYS_CONFIG_NAME and will go away when Kconfig migration is
# completed and all files in include/configs are removed
# 4 should be removed when all CONFIG options in those files move to Kconfig
-# 5 is automatically included by the build system (see UBOOTINCLUDE) so is
-# already unnecessary
-# 6 should be removed by tidying up a few Kconfig items
+# 5 should be removed by tidying up a few Kconfig items
#
# So all of the above should eventually go away
define filechk_config_h
@@ -128,7 +125,6 @@ define filechk_config_h
echo \#include \; \
echo \#include \; \
echo \#include \;\
- echo \#include \; \
echo \#include \;)
endef
diff --git a/tools/atmel_pmecc_params.c b/tools/atmel_pmecc_params.c
index a4ae03f0fd42..bb203427aa03 100644
--- a/tools/atmel_pmecc_params.c
+++ b/tools/atmel_pmecc_params.c
@@ -14,6 +14,7 @@
#include
#include
+#include
static int pmecc_get_ecc_bytes(int cap, int sector_size)
{
--
2.17.1
[RFCv2 05/16] common: Drop time.h from common header
From: Simon Glass Move this out of the common header and include it only where needed. Signed-off-by: Simon Glass --- api/api.c| 1 + arch/arm/mach-at91/arm920t/clock.c | 1 + arch/arm/mach-at91/arm926ejs/clock.c | 1 + arch/arm/mach-at91/clock.c | 1 + arch/arm/mach-at91/phy.c | 1 + arch/arm/mach-bcm283x/mbox.c | 1 + arch/arm/mach-exynos/clock.c | 1 + arch/arm/mach-imx/i2c-mxv7.c | 1 + arch/arm/mach-imx/mx6/clock.c| 1 + arch/arm/mach-imx/mx7/clock.c| 1 + arch/arm/mach-omap2/omap3/am35x_musb.c | 1 + arch/arm/mach-stm32mp/pwr_regulator.c| 1 + arch/arm/mach-tegra/powergate.c | 1 + arch/arm/mach-tegra/tegra124/xusb-padctl.c | 1 + arch/arm/mach-tegra/tegra210/clock.c | 1 + arch/arm/mach-tegra/tegra210/xusb-padctl.c | 1 + arch/m68k/cpu/mcf547x_8x/slicetimer.c| 1 + arch/mips/mach-mtmips/mt7628/init.c | 1 + arch/mips/mach-octeon/clock.c| 1 + arch/powerpc/lib/interrupts.c| 1 + arch/x86/cpu/acpi_gpe.c | 1 + arch/x86/cpu/apollolake/punit.c | 1 + arch/x86/cpu/coreboot/timestamp.c| 1 + arch/x86/cpu/intel_common/mrc.c | 1 + arch/x86/cpu/mp_init.c | 1 + arch/x86/cpu/quark/mrc.c | 1 + arch/x86/cpu/quark/mrc_util.c| 1 + arch/x86/cpu/quark/smc.c | 1 + board/astro/mcf5373l/mcf5373l.c | 1 + board/cobra5272/flash.c | 1 + board/freescale/m5253demo/flash.c| 1 + board/gdsys/common/phy.c | 1 + board/nokia/rx51/rx51.c | 1 + board/sandbox/sandbox.c | 1 + board/theadorable/fpga.c | 1 + board/theadorable/theadorable.c | 1 + cmd/clone.c | 1 + cmd/gettime.c| 1 + cmd/mem.c| 1 + cmd/misc.c | 1 + cmd/sf.c | 1 + cmd/tpm_test.c | 1 + common/command.c | 1 + common/dfu.c | 1 + common/usb_hub.c | 1 + common/usb_kbd.c | 1 + common/xyzModem.c| 1 + drivers/ata/ahci.c | 1 + drivers/ata/sata_mv.c| 1 + drivers/ddr/altera/sdram_soc64.c | 1 + drivers/dma/lpc32xx_dma.c| 1 + drivers/fpga/ACEX1K.c| 1 + drivers/fpga/cyclon2.c | 1 + drivers/fpga/socfpga_arria10.c | 1 + drivers/fpga/spartan2.c | 1 + drivers/fpga/spartan3.c | 1 + drivers/fpga/stratix10.c | 1 + drivers/fpga/virtex2.c | 1 + drivers/fpga/zynqpl.c| 1 + drivers/hwspinlock/hwspinlock-uclass.c | 1 + drivers/i2c/at91_i2c.c | 1 + drivers/i2c/designware_i2c.c | 1 + drivers/i2c/i2c-cortina.c| 1 + drivers/i2c/imx_lpi2c.c | 1 + drivers/i2c/intel_i2c.c | 1 + drivers/i2c/meson_i2c.c | 1 + drivers/i2c/muxes/i2c-arb-gpio-challenge.c | 1 + drivers/i2c/mxc_i2c.c| 1 + drivers/i2c/nx_i2c.c | 1 + drivers/i2c/octeon_i2c.c | 1 + drivers/i2c/rk_i2c.c | 1 + drivers/i2c/s3c24x0_i2c.c| 1 + drivers/i2c/stm32f7_i2c.c| 1 + drivers/input/input.c| 1 + drivers/input/tegra-kbc.c| 1 + drivers/misc/cros_ec.c | 1 + drivers/misc/cros_ec_lpc.c | 1 + drivers/misc/cros_ec_sandbox.c | 1 + drivers/misc/cros_ec_spi.c | 1 + drivers/mmc/am654_sdhci.c| 1 + drivers/mmc/bcm2835_sdhost.c | 1 + drivers/mmc/dw_mmc.c | 1 + drivers/mmc/fsl_esdhc.c | 1 + drivers/mmc/fsl_esdhc_imx.c | 1 + drivers/mmc/ftsdc010_mci.c | 1 + drivers/mmc/meson_gx_mmc.c | 1 + drivers/mmc/mmc.c| 1 + drivers/mmc/mvebu_mmc.c | 1 + drivers/mmc/omap_hsmmc.c | 1 + drivers/mmc/sdhci.c | 1 + drivers/mmc/sunxi_mmc.c | 1 + drivers/mmc/tegra_mmc.c | 1 + drivers/mtd/cfi_flash.c | 1 +
[RFCv2 14/16] common: Move the build-system includes to a separate file
From: Simon Glass
At present common.h is used by the build system when calculating
dependencies. Move it out into a separate file so we can drop the
env_internal.h inclusion from common.
Signed-off-by: Simon Glass
---
arch/nds32/lib/asm-offsets.c | 1 +
include/common.h | 5 -
include/deps_internal.h | 18 ++
scripts/Makefile.autoconf| 8 +---
4 files changed, 24 insertions(+), 8 deletions(-)
create mode 100644 include/deps_internal.h
diff --git a/arch/nds32/lib/asm-offsets.c b/arch/nds32/lib/asm-offsets.c
index 39e3480bd52f..7412b788d793 100644
--- a/arch/nds32/lib/asm-offsets.c
+++ b/arch/nds32/lib/asm-offsets.c
@@ -10,6 +10,7 @@
* published by the Free Software Foundation.
*/
#include
+#include
#include
diff --git a/include/common.h b/include/common.h
index 2e95d0ebdf5d..1a9a2ce0ea85 100644
--- a/include/common.h
+++ b/include/common.h
@@ -16,9 +16,4 @@
#include
#endif /* __ASSEMBLY__ */
-/* Pull in stuff for the build system */
-#ifdef DO_DEPS_ONLY
-# include
-#endif
-
#endif /* __COMMON_H_ */
diff --git a/include/deps_internal.h b/include/deps_internal.h
new file mode 100644
index ..9c3b31cc5771
--- /dev/null
+++ b/include/deps_internal.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Internal header file used by the build system to calculate dependences
+ *
+ * (C) Copyright 2000-2009
+ * Wolfgang Denk, DENX Software Engineering, w...@denx.de.
+ */
+
+#ifndef __DEPS_INTERNAL
+#define __DEPS_INTERNAL
+
+#ifndef __ASSEMBLY__
+#include
+#endif
+
+#include
+
+#endif /* __DEPS_INTERNAL */
diff --git a/scripts/Makefile.autoconf b/scripts/Makefile.autoconf
index 0bfc1b2a6292..89882e3c71a4 100644
--- a/scripts/Makefile.autoconf
+++ b/scripts/Makefile.autoconf
@@ -41,8 +41,9 @@ c_flags := $(KBUILD_CFLAGS) $(KBUILD_CPPFLAGS)
$(PLATFORM_CPPFLAGS) \
quiet_cmd_autoconf_dep = GEN $@
cmd_autoconf_dep = $(CC) -x c -DDO_DEPS_ONLY -M -MP $(c_flags) \
- -MQ include/config/auto.conf $(srctree)/include/common.h > $@ || {
\
- rm $@; false;
\
+ -MQ include/config/auto.conf $(srctree)/include/deps_internal.h > $@ \
+ || {\
+ rm $@; false; \
}
include/autoconf.mk.dep: include/config.h FORCE
$(call cmd,autoconf_dep)
@@ -66,7 +67,8 @@ quiet_cmd_autoconf = GEN $@
quiet_cmd_u_boot_cfg = CFG $@
cmd_u_boot_cfg = \
- $(CPP) $(c_flags) $2 -DDO_DEPS_ONLY -dM $(srctree)/include/common.h >
$@.tmp && { \
+ $(CPP) $(c_flags) $2 -DDO_DEPS_ONLY -dM \
+ $(srctree)/include/deps_internal.h > $@.tmp && {\
grep 'define CONFIG_' $@.tmp > $@; \
rm $@.tmp; \
} || { \
--
2.17.1
[RFCv2 09/16] common: Drop stdarg.h from common header
From: Simon Glass Move this out of the common header and include it only where needed. Signed-off-by: Simon Glass --- api/api.c | 1 + board/CZ.NIC/turris_mox/turris_mox.c| 1 + common/lcd_console.c| 1 + common/log.c| 1 + common/log_syslog.c | 1 + drivers/core/util.c | 1 + drivers/fastboot/fb_common.c| 1 + drivers/gpio/gpio-uclass.c | 1 + drivers/mtd/nand/raw/brcmnand/brcmnand_compat.c | 1 + include/common.h| 1 - include/efi.h | 1 + include/exports.h | 1 + lib/efi_selftest/efi_selftest_console.c | 1 + lib/panic.c | 1 + lib/tpm-common.c| 1 + post/post.c | 1 + test/ut.c | 1 + 17 files changed, 16 insertions(+), 1 deletion(-) diff --git a/api/api.c b/api/api.c index d6b5b60c2255..748df20bebe4 100644 --- a/api/api.c +++ b/api/api.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include diff --git a/board/CZ.NIC/turris_mox/turris_mox.c b/board/CZ.NIC/turris_mox/turris_mox.c index f5fcb93262b7..7f2ed1350bf2 100644 --- a/board/CZ.NIC/turris_mox/turris_mox.c +++ b/board/CZ.NIC/turris_mox/turris_mox.c @@ -4,6 +4,7 @@ */ #include +#include #include #include #include diff --git a/common/lcd_console.c b/common/lcd_console.c index 7a10a20d7244..0ccb4a468802 100644 --- a/common/lcd_console.c +++ b/common/lcd_console.c @@ -11,6 +11,7 @@ #include #include #include +#include #include /* Get font data, width and height */ #if defined(CONFIG_LCD_LOGO) #include diff --git a/common/log.c b/common/log.c index 06a66b0a..493ee0ff0d9f 100644 --- a/common/log.c +++ b/common/log.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include diff --git a/common/log_syslog.c b/common/log_syslog.c index 2f3c93bf8393..6cb4ed18ca12 100644 --- a/common/log_syslog.c +++ b/common/log_syslog.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include diff --git a/drivers/core/util.c b/drivers/core/util.c index 7a2fe1f4394b..cd15768970cc 100644 --- a/drivers/core/util.c +++ b/drivers/core/util.c @@ -4,6 +4,7 @@ */ #include +#include #include #include #include diff --git a/drivers/fastboot/fb_common.c b/drivers/fastboot/fb_common.c index da467666cf4c..325ce4d283fe 100644 --- a/drivers/fastboot/fb_common.c +++ b/drivers/fastboot/fb_common.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/gpio/gpio-uclass.c b/drivers/gpio/gpio-uclass.c index 7d4e3354f173..2e371f3ad79c 100644 --- a/drivers/gpio/gpio-uclass.c +++ b/drivers/gpio/gpio-uclass.c @@ -6,6 +6,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/mtd/nand/raw/brcmnand/brcmnand_compat.c b/drivers/mtd/nand/raw/brcmnand/brcmnand_compat.c index a6acf556bcc7..1b05e2db9f6d 100644 --- a/drivers/mtd/nand/raw/brcmnand/brcmnand_compat.c +++ b/drivers/mtd/nand/raw/brcmnand/brcmnand_compat.c @@ -3,6 +3,7 @@ #include #include #include +#include #include #include "brcmnand_compat.h" diff --git a/include/common.h b/include/common.h index 33171360ddb0..31c3d462132f 100644 --- a/include/common.h +++ b/include/common.h @@ -16,7 +16,6 @@ #include #include #include -#include #include #include #endif /* __ASSEMBLY__ */ diff --git a/include/efi.h b/include/efi.h index f986aad8..818295642ddb 100644 --- a/include/efi.h +++ b/include/efi.h @@ -16,6 +16,7 @@ #ifndef _EFI_H #define _EFI_H +#include #include #include #include diff --git a/include/exports.h b/include/exports.h index 5e10fc3bce53..935cf594c3b4 100644 --- a/include/exports.h +++ b/include/exports.h @@ -2,6 +2,7 @@ #define __EXPORTS_H__ #include +#include #include #include #include diff --git a/lib/efi_selftest/efi_selftest_console.c b/lib/efi_selftest/efi_selftest_console.c index 13f3ee6bc19f..0462c196c16d 100644 --- a/lib/efi_selftest/efi_selftest_console.c +++ b/lib/efi_selftest/efi_selftest_console.c @@ -7,6 +7,7 @@ #include #include +#include #include struct efi_simple_text_output_protocol *con_out; diff --git a/lib/panic.c b/lib/panic.c index eba1d43b7551..2267a8d4fb91 100644 --- a/lib/panic.c +++ b/lib/panic.c @@ -14,6 +14,7 @@ #if !defined(CONFIG_PANIC_HANG) #include #endif +#include #include #include diff --git a/lib/tpm-common.c b/lib/tpm-common.c index adfe49190699..21fc4c7c865e 100644 --- a/lib/tpm-common.c +++ b/lib/tpm-common.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include diff
[RFCv2] common: Drop remaining includes in common.h
I've picked up Simon's v1 of this series and moved it to an RFC with this v2. I don't intend for this series to go in as-is but rather since I spent a good bit of time iterating over the problems of trying a conversion (in a few places) where we only selectively add back in the header being removed from common.h in the case of a fail to build, I didn't want the work lost. What I think needs to be done moving forward is even smaller series here where we focus on removing one or two headers, but then only re-add them where required. Also note that this series shows a few funny issues. The patch to remove and selectively re-add it shows: bcm958712k : all -4 text -4 u-boot: add: 1/0, grow: 0/-3 bytes: 24/-28 (-4) function old new delta blk_dread- 24 +24 part_test_efi 184 180 -4 is_gpt_valid 736 724 -12 fs_devread 600 588 -12 everywhere that code is used. I don't see why, but there's some underlying problem exposed in the move. I believe it's also that patch which shows, for every big-endian platform something like: T4160RDB : all -592 text -592 u-boot: add: 2/0, grow: 1/-14 bytes: 68/-656 (-588) function old new delta ___arch__swab32 - 48 +48 blk_dread- 12 +12 ext4fs_bg_get_inode_table_id76 84 +8 ehci_td_buffer 164 156 -8 _ehci_destroy_int_queue244 236 -8 static.ehci_update_endpt2_dev_n_port 116 104 -12 ext4fs_open200 188 -12 _ehci_poll_int_queue 236 224 -12 usb_lowlevel_init 916 892 -24 ext4fs_mount 332 304 -28 fs_devread 572 540 -32 ext4fs_find_file1 756 724 -32 ext4fs_iterate_dir 848 812 -36 ext4fs_read_inode 520 452 -68 static._ehci_create_int_queue 1000 908 -92 ehci_submit_async 16321520-112 read_allocated_block 25322352-180 and I lack hardware to see (and it looks like qemu-ppce500 can't be given a disk atm) if the problem is that ext2/4 is broken before and fixed now, or fixed now and broken with this patch, as that's my first concern on seeing ___arch__swab32 show up. But maybe it's a harmless "no, don't inline ..." decision the compiler is now able to make. But very non-obvious and needing a run-time sanity check to be sure.
[RFCv2 04/16] Fix code style for time functions
From: Simon Glass
Fix the code style used for some time functions.
Signed-off-by: Simon Glass
---
arch/arm/cpu/arm920t/imx/timer.c | 2 +-
arch/arm/cpu/sa1100/timer.c | 2 +-
arch/microblaze/cpu/timer.c | 2 +-
arch/powerpc/lib/interrupts.c| 2 +-
arch/powerpc/lib/time.c | 5 +++--
board/armltd/integrator/timer.c | 2 +-
drivers/fpga/ACEX1K.c| 4 ++--
drivers/fpga/spartan2.c | 24
drivers/fpga/spartan3.c | 24
drivers/net/lan91c96.c | 4 ++--
drivers/net/ne2000_base.c| 4 ++--
drivers/net/smc9.c | 4 ++--
post/drivers/rtc.c | 4 ++--
13 files changed, 42 insertions(+), 41 deletions(-)
diff --git a/arch/arm/cpu/arm920t/imx/timer.c b/arch/arm/cpu/arm920t/imx/timer.c
index e9d55779214b..b559db75f12c 100644
--- a/arch/arm/cpu/arm920t/imx/timer.c
+++ b/arch/arm/cpu/arm920t/imx/timer.c
@@ -44,7 +44,7 @@ static ulong get_timer_masked (void)
return TCN1;
}
-ulong get_timer (ulong base)
+ulong get_timer(ulong base)
{
return get_timer_masked() - base;
}
diff --git a/arch/arm/cpu/sa1100/timer.c b/arch/arm/cpu/sa1100/timer.c
index a5cdaf5a66c4..5d597dd1ab4c 100644
--- a/arch/arm/cpu/sa1100/timer.c
+++ b/arch/arm/cpu/sa1100/timer.c
@@ -19,7 +19,7 @@ static ulong get_timer_masked (void)
return OSCR;
}
-ulong get_timer (ulong base)
+ulong get_timer(ulong base)
{
return get_timer_masked ();
}
diff --git a/arch/microblaze/cpu/timer.c b/arch/microblaze/cpu/timer.c
index 647bdcd5ba52..05ab0e1b1570 100644
--- a/arch/microblaze/cpu/timer.c
+++ b/arch/microblaze/cpu/timer.c
@@ -20,7 +20,7 @@ DECLARE_GLOBAL_DATA_PTR;
volatile int timestamp = 0;
microblaze_timer_t *tmr;
-ulong get_timer (ulong base)
+ulong get_timer(ulong base)
{
if (tmr)
return timestamp - base;
diff --git a/arch/powerpc/lib/interrupts.c b/arch/powerpc/lib/interrupts.c
index 73f270002cfc..bda0999327d9 100644
--- a/arch/powerpc/lib/interrupts.c
+++ b/arch/powerpc/lib/interrupts.c
@@ -89,7 +89,7 @@ void timer_interrupt(struct pt_regs *regs)
#endif /* CONFIG_LED_STATUS */
}
-ulong get_timer (ulong base)
+ulong get_timer(ulong base)
{
return (timestamp - base);
}
diff --git a/arch/powerpc/lib/time.c b/arch/powerpc/lib/time.c
index 8d6babfb83d6..d27432c23af8 100644
--- a/arch/powerpc/lib/time.c
+++ b/arch/powerpc/lib/time.c
@@ -39,8 +39,9 @@ unsigned long usec2ticks(unsigned long usec)
*/
void __udelay(unsigned long usec)
{
- ulong ticks = usec2ticks (usec);
- wait_ticks (ticks);
+ ulong ticks = usec2ticks(usec);
+
+ wait_ticks(ticks);
}
/* - */
diff --git a/board/armltd/integrator/timer.c b/board/armltd/integrator/timer.c
index d220b877d661..53d1c0ec3038 100644
--- a/board/armltd/integrator/timer.c
+++ b/board/armltd/integrator/timer.c
@@ -119,7 +119,7 @@ static ulong get_timer_masked (void)
return timestamp;
}
-ulong get_timer (ulong base_ticks)
+ulong get_timer(ulong base_ticks)
{
return get_timer_masked () - base_ticks;
}
diff --git a/drivers/fpga/ACEX1K.c b/drivers/fpga/ACEX1K.c
index aca8049c56ac..30a3727433e7 100644
--- a/drivers/fpga/ACEX1K.c
+++ b/drivers/fpga/ACEX1K.c
@@ -140,10 +140,10 @@ static int ACEX1K_ps_load(Altera_desc *desc, const void
*buf, size_t bsize)
udelay(2); /* T_cf2st1 < 4us */
/* Wait for nSTATUS to be released (i.e. deasserted) */
- ts = get_timer (0); /* get current time */
+ ts = get_timer(0); /* get current time */
do {
CONFIG_FPGA_DELAY ();
- if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) {/*
check the time */
+ if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) { /*
check the time */
puts ("** Timeout waiting for STATUS to go
high.\n");
(*fn->abort) (cookie);
return FPGA_FAIL;
diff --git a/drivers/fpga/spartan2.c b/drivers/fpga/spartan2.c
index 3435400e58bd..fae94f9663ab 100644
--- a/drivers/fpga/spartan2.c
+++ b/drivers/fpga/spartan2.c
@@ -151,11 +151,11 @@ static int spartan2_sp_load(xilinx_desc *desc, const void
*buf, size_t bsize)
CONFIG_FPGA_DELAY ();
(*fn->pgm) (false, true, cookie); /* Deassert the
program, commit */
- ts = get_timer (0); /* get current time */
+ ts = get_timer(0); /* get current time */
/* Now wait for INIT and BUSY to go high */
do {
CONFIG_FPGA_DELAY ();
- if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) {/*
check the time */
+ if (get_timer(ts) >
[RFCv2 02/16] common: Drop display_options.h from common header
From: Simon Glass Move this out of the common header and include it only where needed. Signed-off-by: Simon Glass --- arch/arm/cpu/armv7/s5p-common/cpu_info.c | 1 + arch/arm/mach-at91/arm926ejs/eflash.c | 1 + arch/arm/mach-imx/hab.c | 1 + arch/powerpc/cpu/mpc85xx/cpu.c| 1 + arch/powerpc/cpu/mpc85xx/cpu_init.c | 1 + arch/powerpc/cpu/mpc85xx/tlb.c| 1 + arch/powerpc/cpu/mpc86xx/cpu.c| 1 + arch/powerpc/cpu/mpc8xx/cpu.c | 1 + arch/powerpc/cpu/mpc8xxx/law.c| 1 + arch/x86/cpu/broadwell/refcode.c | 1 + board/corscience/tricorder/tricorder-eeprom.c | 1 + board/freescale/ls1028a/ls1028a.c | 1 + board/freescale/ls1088a/ls1088a.c | 1 + board/freescale/ls2080a/ls2080a.c | 1 + board/freescale/ls2080aqds/ls2080aqds.c | 1 + board/freescale/ls2080ardb/ls2080ardb.c | 1 + board/freescale/lx2160a/lx2160a.c | 1 + board/freescale/mpc8541cds/mpc8541cds.c | 1 + board/freescale/mpc8548cds/mpc8548cds.c | 1 + board/freescale/mpc8555cds/mpc8555cds.c | 1 + board/freescale/mpc8568mds/mpc8568mds.c | 1 + board/gdsys/p1022/controlcenterd-id.c | 1 + board/kosagi/novena/novena.c | 1 + board/sbc8548/sbc8548.c | 1 + cmd/acpi.c| 1 + cmd/axi.c | 1 + cmd/bcb.c | 1 + cmd/cpu.c | 1 + cmd/fpgad.c | 1 + cmd/io.c | 1 + cmd/mem.c | 1 + cmd/mmc.c | 1 + cmd/rtc.c | 1 + cmd/sf.c | 1 + cmd/version.c | 1 + common/board_f.c | 1 + common/board_r.c | 1 + common/console.c | 1 + common/image.c| 1 + common/splash.c | 1 + drivers/core/acpi.c | 1 + drivers/cpu/bmips_cpu.c | 1 + drivers/ddr/fsl/main.c| 1 + drivers/mmc/gen_atmel_mci.c | 1 + drivers/mtd/onenand/onenand_uboot.c | 1 + drivers/mtd/spi/sf_dataflash.c| 1 + drivers/mtd/spi/spi-nor-core.c| 1 + drivers/net/xilinx_axi_emac.c | 1 + drivers/tpm/tpm_atmel_twi.c | 1 + drivers/tpm/tpm_tis_sandbox.c | 1 + drivers/usb/gadget/pxa27x_udc.c | 1 + fs/fs.c | 1 + include/common.h | 1 - include/display_options.h | 1 + lib/aes.c | 1 + lib/display_options.c | 1 + lib/fdtdec.c | 1 + net/nfs.c | 1 + net/tftp.c| 1 + 59 files changed, 58 insertions(+), 1 deletion(-) diff --git a/arch/arm/cpu/armv7/s5p-common/cpu_info.c b/arch/arm/cpu/armv7/s5p-common/cpu_info.c index d910282e2b29..fb2920950d42 100644 --- a/arch/arm/cpu/armv7/s5p-common/cpu_info.c +++ b/arch/arm/cpu/armv7/s5p-common/cpu_info.c @@ -4,6 +4,7 @@ * Minkyu Kang */ #include +#include #include #include #include diff --git a/arch/arm/mach-at91/arm926ejs/eflash.c b/arch/arm/mach-at91/arm926ejs/eflash.c index 23c24936edf0..ef579e6089ce 100644 --- a/arch/arm/mach-at91/arm926ejs/eflash.c +++ b/arch/arm/mach-at91/arm926ejs/eflash.c @@ -43,6 +43,7 @@ * do a read-modify-write for partially programmed pages */ #include +#include #include #include #include diff --git a/arch/arm/mach-imx/hab.c b/arch/arm/mach-imx/hab.c index d0757d8b66af..7510735bf463 100644 --- a/arch/arm/mach-imx/hab.c +++ b/arch/arm/mach-imx/hab.c @@ -6,6 +6,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c index 5170610f0413..d35c97801722 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu.c +++ b/arch/powerpc/cpu/mpc85xx/cpu.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index e0f0f7ecda60..fcc2c7be31a9 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -10,6 +10,7 @@ */ #include +#include #include #include #include diff --git a/arch/powerpc/cpu/mpc85xx/tlb.c b/arch/powerpc/cpu/mpc85xx/tlb.c index 973b6fbe4b74..927df4e5b660 100644 --- a/arch/powerpc/cpu/mpc85xx/tlb.c +++
Re: [PATCH 4/9] nand: Kconfig: Change dependency for NAND_ARASAN
On 19. 08. 20 14:43, Tom Rini wrote: > On Wed, Aug 19, 2020 at 02:36:20PM +0200, Michal Simek wrote: >> On 19. 08. 20 14:31, Tom Rini wrote: >>> On Wed, Aug 19, 2020 at 10:44:18AM +0200, Michal Simek wrote: >>> NAND_ARASAN selecting DM_MTD uunconditionally. Driver can be enabled with !DM that's why Kconfig it showing it as error: WARNING: unmet direct dependencies detected for DM_MTD Depends on [n]: DM [=n] Selected by [y]: - NAND_ARASAN [=y] && MTD_RAW_NAND [=y] Signed-off-by: Michal Simek --- drivers/mtd/nand/raw/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig index 06b2ff972cad..df4cbd52cf5c 100644 --- a/drivers/mtd/nand/raw/Kconfig +++ b/drivers/mtd/nand/raw/Kconfig @@ -233,7 +233,7 @@ endif config NAND_ARASAN bool "Configure Arasan Nand" select SYS_NAND_SELF_INIT - select DM_MTD + depends on DM_MTD imply CMD_NAND help This enables Nand driver support for Arasan nand flash >>> >>> If we can use the driver without DM then we can't depend nor select >>> DM_MTD. Is someone using the driver still without DM_MTD? >>> >> >> Driver has been converted to DM already. It is used by ZynqMP platforms. >> And it can't be used without DM_MTD. >> >> commit b014b833bd627d27542b50e71df9cf0628f241e7 >> Author: Ashok Reddy Soma >> AuthorDate: Thu Dec 19 02:27:42 2019 -0700 >> Commit: Michal Simek >> CommitDate: Tue Jan 14 09:05:52 2020 +0100 >> >> mtd: nand: Move arasan nand driver to driver model >> >> Make changes to arasan nand driver to move it to driver model. >> Select DM_MTD if arasan nand driver is selected. >> >> Signed-off-by: Ashok Reddy Soma >> Signed-off-by: Michal Simek > > Ah, I misunderstood the comment, sorry. Yes, this is right then, > thanks. > > Reviewed-by: Tom Rini > ok. I just need to enable this symbol for zynqmp platforms. Thanks, Michal signature.asc Description: OpenPGP digital signature
Re: [PATCH 4/9] nand: Kconfig: Change dependency for NAND_ARASAN
On Wed, Aug 19, 2020 at 02:36:20PM +0200, Michal Simek wrote: > On 19. 08. 20 14:31, Tom Rini wrote: > > On Wed, Aug 19, 2020 at 10:44:18AM +0200, Michal Simek wrote: > > > >> NAND_ARASAN selecting DM_MTD uunconditionally. Driver can be enabled with > >> !DM that's why Kconfig it showing it as error: > >> > >> WARNING: unmet direct dependencies detected for DM_MTD > >> Depends on [n]: DM [=n] > >> Selected by [y]: > >> - NAND_ARASAN [=y] && MTD_RAW_NAND [=y] > >> > >> Signed-off-by: Michal Simek > >> --- > >> > >> drivers/mtd/nand/raw/Kconfig | 2 +- > >> 1 file changed, 1 insertion(+), 1 deletion(-) > >> > >> diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig > >> index 06b2ff972cad..df4cbd52cf5c 100644 > >> --- a/drivers/mtd/nand/raw/Kconfig > >> +++ b/drivers/mtd/nand/raw/Kconfig > >> @@ -233,7 +233,7 @@ endif > >> config NAND_ARASAN > >>bool "Configure Arasan Nand" > >>select SYS_NAND_SELF_INIT > >> - select DM_MTD > >> + depends on DM_MTD > >>imply CMD_NAND > >>help > >> This enables Nand driver support for Arasan nand flash > > > > If we can use the driver without DM then we can't depend nor select > > DM_MTD. Is someone using the driver still without DM_MTD? > > > > Driver has been converted to DM already. It is used by ZynqMP platforms. > And it can't be used without DM_MTD. > > commit b014b833bd627d27542b50e71df9cf0628f241e7 > Author: Ashok Reddy Soma > AuthorDate: Thu Dec 19 02:27:42 2019 -0700 > Commit: Michal Simek > CommitDate: Tue Jan 14 09:05:52 2020 +0100 > > mtd: nand: Move arasan nand driver to driver model > > Make changes to arasan nand driver to move it to driver model. > Select DM_MTD if arasan nand driver is selected. > > Signed-off-by: Ashok Reddy Soma > Signed-off-by: Michal Simek Ah, I misunderstood the comment, sorry. Yes, this is right then, thanks. Reviewed-by: Tom Rini -- Tom signature.asc Description: PGP signature
[PATCH 3/5] board: xen: Remove CONFIG_CMD_RUN define as it is set on by default in Kconfig
From: Anastasiia Lukianenko Signed-off-by: Anastasiia Lukianenko --- configs/xenguest_arm64_defconfig | 1 - include/configs/xenguest_arm64.h | 2 -- 2 files changed, 3 deletions(-) diff --git a/configs/xenguest_arm64_defconfig b/configs/xenguest_arm64_defconfig index 46473c251d..1a85166ff5 100644 --- a/configs/xenguest_arm64_defconfig +++ b/configs/xenguest_arm64_defconfig @@ -17,7 +17,6 @@ CONFIG_CMD_ELF=n CONFIG_CMD_EXT4=y CONFIG_CMD_FAT=y CONFIG_CMD_GO=n -CONFIG_CMD_RUN=n CONFIG_CMD_IMI=n CONFIG_CMD_IMLS=n CONFIG_CMD_XIMG=n diff --git a/include/configs/xenguest_arm64.h b/include/configs/xenguest_arm64.h index e88ab87a1d..f3092cb2f8 100644 --- a/include/configs/xenguest_arm64.h +++ b/include/configs/xenguest_arm64.h @@ -39,8 +39,6 @@ #define CONFIG_CMDLINE_TAG1 #define CONFIG_INITRD_TAG 1 -#define CONFIG_CMD_RUN - #undef CONFIG_EXTRA_ENV_SETTINGS #define CONFIG_EXTRA_ENV_SETTINGS \ "loadimage=ext4load pvblock 0 0x9000 /boot/Image;\0" \ -- 2.17.1
[PATCH 2/5] MAINTAINERS: Add maintainers to XEN section
From: Anastasiia Lukianenko Signed-off-by: Anastasiia Lukianenko --- MAINTAINERS | 20 1 file changed, 20 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 2a281a9a0f..840c7625f1 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1028,6 +1028,26 @@ T: git https://gitlab.denx.de/u-boot/custodians/u-boot-x86.git F: arch/x86/ F: cmd/x86/ +XEN +M: Anastasiia Lukianenko +M: Oleksandr Andrushchenko +S: Maintained +F: arch/arm/cpu/armv8/xen/ +F: arch/arm/include/asm/xen.h +F: arch/arm/include/asm/xen/ +F: board/xen/xenguest_arm64/ +F: cmd/pvblock.c +F: configs/xenguest_arm64_defconfig +F: doc/board/xen/ +F: drivers/serial/serial_xen.c +F: drivers/xen/ +F: include/configs/xenguest_arm64.h +F: include/pvblock.h +F: include/xen/ +F: include/xen.h +F: lib/sscanf.c +F: test/lib/sscanf.c + XTENSA M: Max Filippov S: Maintained -- 2.17.1
[PATCH 4/5] board: xen: Remove unnecessary CONFIG_INITRD_TAG and CONFIG_CMDLINE_TAG
From: Anastasiia Lukianenko Signed-off-by: Anastasiia Lukianenko --- include/configs/xenguest_arm64.h | 3 --- 1 file changed, 3 deletions(-) diff --git a/include/configs/xenguest_arm64.h b/include/configs/xenguest_arm64.h index f3092cb2f8..c44381e966 100644 --- a/include/configs/xenguest_arm64.h +++ b/include/configs/xenguest_arm64.h @@ -36,9 +36,6 @@ #define CONFIG_OF_SYSTEM_SETUP -#define CONFIG_CMDLINE_TAG1 -#define CONFIG_INITRD_TAG 1 - #undef CONFIG_EXTRA_ENV_SETTINGS #define CONFIG_EXTRA_ENV_SETTINGS \ "loadimage=ext4load pvblock 0 0x9000 /boot/Image;\0" \ -- 2.17.1
[PATCH 5/5] xen: Code style conformity
From: Anastasiia Lukianenko
Signed-off-by: Anastasiia Lukianenko
---
drivers/xen/gnttab.c | 3 ++-
drivers/xen/pvblock.c | 12 ++--
include/xen/gnttab.h | 3 +--
lib/sscanf.c | 3 ++-
4 files changed, 11 insertions(+), 10 deletions(-)
diff --git a/drivers/xen/gnttab.c b/drivers/xen/gnttab.c
index becf7a79fb..9bf1091ab3 100644
--- a/drivers/xen/gnttab.c
+++ b/drivers/xen/gnttab.c
@@ -100,7 +100,8 @@ int gnttab_end_access(grant_ref_t ref)
nflags = gnttab_table[ref].flags;
do {
- if ((flags = nflags) & (GTF_reading | GTF_writing)) {
+ flags = nflags;
+ if ((flags) & (GTF_reading | GTF_writing)) {
printf("WARNING: g.e. still in use! (%x)\n", flags);
return 0;
}
diff --git a/drivers/xen/pvblock.c b/drivers/xen/pvblock.c
index 76e82fbf41..87e33afeb0 100644
--- a/drivers/xen/pvblock.c
+++ b/drivers/xen/pvblock.c
@@ -294,8 +294,8 @@ static void shutdown_blkfront(struct blkfront_dev *dev)
snprintf(path, sizeof(path), "%s/state", dev->backend);
snprintf(nodename, sizeof(nodename), "%s/state", dev->nodename);
- if ((err = xenbus_switch_state(XBT_NIL, nodename,
- XenbusStateClosing)) != NULL) {
+ err = xenbus_switch_state(XBT_NIL, nodename, XenbusStateClosing);
+ if (err != NULL) {
printf("%s: error changing state to %d: %s\n", __func__,
XenbusStateClosing, err);
goto close;
@@ -306,8 +306,8 @@ static void shutdown_blkfront(struct blkfront_dev *dev)
err = xenbus_wait_for_state_change(path, );
free(err);
- if ((err = xenbus_switch_state(XBT_NIL, nodename,
- XenbusStateClosed)) != NULL) {
+ err = xenbus_switch_state(XBT_NIL, nodename, XenbusStateClosed);
+ if (err != NULL) {
printf("%s: error changing state to %d: %s\n", __func__,
XenbusStateClosed, err);
goto close;
@@ -319,8 +319,8 @@ static void shutdown_blkfront(struct blkfront_dev *dev)
free(err);
}
- if ((err = xenbus_switch_state(XBT_NIL, nodename,
- XenbusStateInitialising)) != NULL) {
+ err = xenbus_switch_state(XBT_NIL, nodename, XenbusStateInitialising);
+ if (err != NULL) {
printf("%s: error changing state to %d: %s\n", __func__,
XenbusStateInitialising, err);
goto close;
diff --git a/include/xen/gnttab.h b/include/xen/gnttab.h
index db1d5361fe..db615004aa 100644
--- a/include/xen/gnttab.h
+++ b/include/xen/gnttab.h
@@ -1,5 +1,4 @@
-/*
- * SPDX-License-Identifier: GPL-2.0
+/* SPDX-License-Identifier: GPL-2.0
*
* (C) 2006, Steven Smith
* (C) 2006, Grzegorz Milos
diff --git a/lib/sscanf.c b/lib/sscanf.c
index d1e2dc272c..4c35c035fe 100644
--- a/lib/sscanf.c
+++ b/lib/sscanf.c
@@ -555,7 +555,8 @@ literal:
if (flags & SUPPRESS) {
size_t sum = 0;
- if ((n = inr) < width) {
+ n = inr;
+ if (n < width) {
sum += n;
width -= n;
inp += n;
--
2.17.1
[PATCH 0/5] Follow up to "Add new board: Xen guest for ARM64" series
From: Anastasiia Lukianenko Removed unnecessary defines, fixed code style errors and added maintainers to XEN section. Anastasiia Lukianenko (5): board: xen: Remove unnecessary CONFIG_BOARD_EARLY_INIT_F define and board_early_init_f function MAINTAINERS: Add maintainers to XEN section board: xen: Remove CONFIG_CMD_RUN define as it is set on by default in Kconfig board: xen: Remove unnecessary CONFIG_INITRD_TAG and CONFIG_CMDLINE_TAG xen: Code style conformity MAINTAINERS | 20 board/xen/xenguest_arm64/xenguest_arm64.c | 5 - configs/xenguest_arm64_defconfig | 1 - drivers/xen/gnttab.c | 3 ++- drivers/xen/pvblock.c | 12 ++-- include/configs/xenguest_arm64.h | 7 --- include/xen/gnttab.h | 3 +-- lib/sscanf.c | 3 ++- 8 files changed, 31 insertions(+), 23 deletions(-) -- 2.17.1
[PATCH 1/5] board: xen: Remove unnecessary CONFIG_BOARD_EARLY_INIT_F define and board_early_init_f function
From: Anastasiia Lukianenko
Signed-off-by: Anastasiia Lukianenko
---
board/xen/xenguest_arm64/xenguest_arm64.c | 5 -
include/configs/xenguest_arm64.h | 2 --
2 files changed, 7 deletions(-)
diff --git a/board/xen/xenguest_arm64/xenguest_arm64.c
b/board/xen/xenguest_arm64/xenguest_arm64.c
index 927d87ae37..ef9cbd5405 100644
--- a/board/xen/xenguest_arm64/xenguest_arm64.c
+++ b/board/xen/xenguest_arm64/xenguest_arm64.c
@@ -184,11 +184,6 @@ int ft_board_setup(void *blob, bd_t *bd)
return 0;
}
-int board_early_init_f(void)
-{
- return 0;
-}
-
int print_cpuinfo(void)
{
printf("Xen virtual CPU\n");
diff --git a/include/configs/xenguest_arm64.h b/include/configs/xenguest_arm64.h
index db3059a82c..e88ab87a1d 100644
--- a/include/configs/xenguest_arm64.h
+++ b/include/configs/xenguest_arm64.h
@@ -9,8 +9,6 @@
#include
#endif
-#define CONFIG_BOARD_EARLY_INIT_F
-
#define CONFIG_EXTRA_ENV_SETTINGS
#undef CONFIG_NR_DRAM_BANKS
--
2.17.1
