[PATCH v4 13/13] riscv: Add support for SPI on Kendryte K210
This enables configs necessary for using SPI. The environment is saved to the very end of SPI flash. This is unlikely to be overwritten unless the entire flash is reprogrammed. This also supplies a default bootcommand. It loads an image and device tree from the first partition of the MMC. This is a minimal/least effort bootcmd, so suggestions (especially in the form of patches) are welcome. I didn't set up distro boot because I think it is unlikely that any general-purpose linux distros will ever be ported to this board. Signed-off-by: Sean Anderson --- Changes in v4: - Enable booting from MMC - Place env in spi flash - Update documentation Changes in v3: - Rebase onto U-Boot master - Remove env and bootcmd configuration. I'm going to punt on those for now, since I haven't worked out the best way to boot with SPI yet. Those settings may be added back in a follow-up patch. Changes in v2: - Add Gigadevice SPI chips to dependencies board/sipeed/maix/Kconfig | 16 ++ configs/sipeed_maix_bitm_defconfig | 10 + doc/board/sipeed/maix.rst | 319 - include/configs/sipeed-maix.h | 7 +- 4 files changed, 300 insertions(+), 52 deletions(-) diff --git a/board/sipeed/maix/Kconfig b/board/sipeed/maix/Kconfig index 4c42dd2087..2cdea8ea81 100644 --- a/board/sipeed/maix/Kconfig +++ b/board/sipeed/maix/Kconfig @@ -53,4 +53,20 @@ config BOARD_SPECIFIC_OPTIONS imply CMD_GPIO imply LED imply LED_GPIO + imply SPI + imply DESIGNWARE_SPI + imply SPI_FLASH_GIGADEVICE + imply SPI_FLASH_WINBOND + imply DM_MTD + imply SPI_FLASH_MTD + imply CMD_MTD + imply ENV_IS_IN_SPI_FLASH + imply MMC + imply MMC_BROKEN_CD + imply MMC_SPI + imply CMD_MMC + imply DOS_PARTITION + imply EFI_PARTITION + imply CMD_PART + imply CMD_FS_GENERIC endif diff --git a/configs/sipeed_maix_bitm_defconfig b/configs/sipeed_maix_bitm_defconfig index 459bf0d530..cb9824e84e 100644 --- a/configs/sipeed_maix_bitm_defconfig +++ b/configs/sipeed_maix_bitm_defconfig @@ -1,8 +1,18 @@ CONFIG_RISCV=y +CONFIG_ENV_SIZE=0x1000 +CONFIG_ENV_OFFSET=0xfff000 +CONFIG_ENV_SECT_SIZE=0x1000 CONFIG_TARGET_SIPEED_MAIX=y CONFIG_ARCH_RV64I=y CONFIG_STACK_SIZE=0x10 +CONFIG_USE_BOOTCOMMAND=y +CONFIG_BOOTCOMMAND="run k210_bootcmd" +CONFIG_MTDIDS_DEFAULT="nor0=spi3:0" +CONFIG_MTDPARTS_DEFAULT="nor0:1M(u-boot),0x1000@0xfff000(env)" # CONFIG_NET is not set # CONFIG_INPUT is not set +CONFIG_SF_DEFAULT_BUS=3 # CONFIG_DM_ETH is not set +CONFIG_FS_EXT4=y +CONFIG_FS_FAT=y # CONFIG_EFI_LOADER is not set diff --git a/doc/board/sipeed/maix.rst b/doc/board/sipeed/maix.rst index 92f2d112a9..bf945b3458 100644 --- a/doc/board/sipeed/maix.rst +++ b/doc/board/sipeed/maix.rst @@ -70,6 +70,7 @@ console shall be opened immediately. Boot output should look like the following: U-Boot 2020.04-rc2-00087-g2221cc09c1-dirty (Feb 28 2020 - 13:53:09 -0500) DRAM: 8 MiB +MMC: spi@5300:slot@0: 0 In:serial@3800 Out: serial@3800 Err: serial@3800 @@ -118,14 +119,115 @@ The value of FW_PAYLOAD_OFFSET must match CONFIG_SYS_TEXT_BASE - 0x8000. The file to flash is build/platform/kendryte/k210/firmware/fw_payload.bin. -Loading Images -^^ +Booting +^^^ -To load a kernel, transfer it over serial. +The default boot process is to load and boot the files ``/uImage`` and +``/k210.dtb`` off of the first partition of the MMC. For Linux, this will result +in an output like .. code-block:: none -=> loady 8000 150 +U-Boot 2020.10-00691-gd1d651d988-dirty (Oct 16 2020 - 17:05:24 -0400) + +DRAM: 8 MiB +MMC: spi@5300:slot@0: 0 +Loading Environment from SPIFlash... SF: Detected w25q128fw with page size 256 Bytes, erase size 4 KiB, total 16 MiB +OK +In:serial@3800 +Out: serial@3800 +Err: serial@3800 +Hit any key to stop autoboot: 0 +1827380 bytes read in 1044 ms (1.7 MiB/s) +13428 bytes read in 10 ms (1.3 MiB/s) +## Booting kernel from Legacy Image at 8006 ... + Image Name: linux + Image Type: RISC-V Linux Kernel Image (uncompressed) + Data Size:1827316 Bytes = 1.7 MiB + Load Address: 8000 + Entry Point: 8000 + Verifying Checksum ... OK +## Flattened Device Tree blob at 8040 + Booting using the fdt blob at 0x8040 + Loading Kernel Image + Loading Device Tree to 803f9000, end 803ff473 ... OK + +Starting kernel ... + +[0.00] Linux version 5.9.0-00021-g6dcc2f0814c6-dirty (sean@godwin) (riscv64-linux-gnu-gcc (GCC) 10.2.0, GNU ld (GNU Binutils) 2.35) #34 SMP Fri Oct 16 14:40:57 EDT 2020 +[0.00] earlycon: sifive0 at MMIO 0x3800 (options '115200n8') +[0.00] printk: bootconsole [sifive0] enabled +[0.00] Zone
[PATCH v4 08/13] spi: dw: Add SoC-specific compatible strings
This adds SoC-specific compatible strings to all users of the designware
spi device. This will allow for the correct driver to be selected for each
device. Where it is publicly documented, a compatible string for the
specific device version has also been added. Devices without
publicly-documented device versions include MSCC SoCs, and Arc Socs. All
compatible strings except those for SoCFPGAs and some of the versioned
strings have been taken from Linux.
Since SSI_MAX_XFER_SIZE is determined at runtime, this is not strictly
necessary. However, it is a good cleanup and brings things closer to Linux.
Signed-off-by: Sean Anderson
Tested-by Eugeniy Paltsev
---
(no changes since v2)
Changes in v2:
- New
arch/arc/dts/axs10x_mb.dtsi | 2 +-
arch/arc/dts/hsdk-common.dtsi | 2 +-
arch/arm/dts/socfpga.dtsi | 6 --
arch/arm/dts/socfpga_agilex.dtsi| 6 --
arch/arm/dts/socfpga_arria10.dtsi | 6 --
arch/arm/dts/socfpga_stratix10.dtsi | 6 --
arch/mips/dts/mscc,jr2.dtsi | 2 +-
arch/mips/dts/mscc,ocelot.dtsi | 2 +-
arch/riscv/dts/k210.dtsi| 13 -
9 files changed, 28 insertions(+), 17 deletions(-)
diff --git a/arch/arc/dts/axs10x_mb.dtsi b/arch/arc/dts/axs10x_mb.dtsi
index daf7ca68fb..d4ff4f7039 100644
--- a/arch/arc/dts/axs10x_mb.dtsi
+++ b/arch/arc/dts/axs10x_mb.dtsi
@@ -90,7 +90,7 @@
};
spi0: spi@0 {
- compatible = "snps,dw-apb-ssi";
+ compatible = "snps,axs10x-spi", "snps,dw-apb-ssi";
reg = <0x0 0x100>;
#address-cells = <1>;
#size-cells = <0>;
diff --git a/arch/arc/dts/hsdk-common.dtsi b/arch/arc/dts/hsdk-common.dtsi
index a4b348b948..3fc82e57d7 100644
--- a/arch/arc/dts/hsdk-common.dtsi
+++ b/arch/arc/dts/hsdk-common.dtsi
@@ -128,7 +128,7 @@
};
spi0: spi@f002 {
- compatible = "snps,dw-apb-ssi";
+ compatible = "snps,hsdk-spi", "snps,dw-apb-ssi";
reg = <0xf002 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
diff --git a/arch/arm/dts/socfpga.dtsi b/arch/arm/dts/socfpga.dtsi
index eda558f2fe..ff79d335ac 100644
--- a/arch/arm/dts/socfpga.dtsi
+++ b/arch/arm/dts/socfpga.dtsi
@@ -804,7 +804,8 @@
};
spi0: spi@fff0 {
- compatible = "snps,dw-apb-ssi";
+ compatible = "altr,socfpga-spi", "snps,dw-apb-ssi-3.20",
+"snps,dw-apb-ssi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xfff0 0x1000>;
@@ -816,7 +817,8 @@
};
spi1: spi@fff01000 {
- compatible = "snps,dw-apb-ssi";
+ compatible = "altr,socfpga-spi", "snps,dw-apb-ssi-3.20",
+"snps,dw-apb-ssi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xfff01000 0x1000>;
diff --git a/arch/arm/dts/socfpga_agilex.dtsi b/arch/arm/dts/socfpga_agilex.dtsi
index 179b4d5591..c3ead2d72b 100644
--- a/arch/arm/dts/socfpga_agilex.dtsi
+++ b/arch/arm/dts/socfpga_agilex.dtsi
@@ -366,7 +366,8 @@
};
spi0: spi@ffda4000 {
- compatible = "snps,dw-apb-ssi";
+ compatible = "intel,agilex-spi",
+"snps,dw-apb-ssi-4.00a", "snps,dw-apb-ssi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xffda4000 0x1000>;
@@ -379,7 +380,8 @@
};
spi1: spi@ffda5000 {
- compatible = "snps,dw-apb-ssi";
+ compatible = "intel,agilex-spi",
+"snps,dw-apb-ssi-4.00a", "snps,dw-apb-ssi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xffda5000 0x1000>;
diff --git a/arch/arm/dts/socfpga_arria10.dtsi
b/arch/arm/dts/socfpga_arria10.dtsi
index a598c75542..bab34ab56c 100644
--- a/arch/arm/dts/socfpga_arria10.dtsi
+++ b/arch/arm/dts/socfpga_arria10.dtsi
@@ -604,7 +604,8 @@
};
spi0: spi@ffda4000 {
- compatible = "snps,dw-apb-ssi";
+ compatible = "altr,socfpga-arria10-spi",
+"snps,dw-apb-ssi-3.22a", "snps,dw-apb-ssi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xffda4000 0x100>;
@@ -617,7 +618,8 @@
};
spi1: spi@ffda5000 {
- compatible = "snps,dw-apb-ssi";
+ compatible =
[PATCH v4 10/13] spi: dw: Document devicetree binding
This documentation has been taken from Linux commit 3d7db0f11c7a ("spi: dw:
Refactor mid_spi_dma_setup() to separate DMA and IRQ config"), immediately
before the file was deleted and replaced with a yaml version. Additional
compatible strings from newer versions have been added, as well as a few
U-Boot-specific ones.
Signed-off-by: Sean Anderson
---
(no changes since v3)
Changes in v3:
- Synchronize compatible strings between docs and driver
Changes in v2:
- Document new compatible strings
- Split off from ctrlr0 commit
.../spi/snps,dw-apb-ssi.txt | 56 +++
1 file changed, 56 insertions(+)
create mode 100644 doc/device-tree-bindings/spi/snps,dw-apb-ssi.txt
diff --git a/doc/device-tree-bindings/spi/snps,dw-apb-ssi.txt
b/doc/device-tree-bindings/spi/snps,dw-apb-ssi.txt
new file mode 100644
index 00..8d2888fbe3
--- /dev/null
+++ b/doc/device-tree-bindings/spi/snps,dw-apb-ssi.txt
@@ -0,0 +1,56 @@
+Synopsys DesignWare AMBA 2.0 Synchronous Serial Interface
+and Synopsys DesignWare High Performance Synchronous Serial Interface
+
+Required properties:
+- compatible : One of
+ "altr,socfpga-spi",
+ "altr,socfpga-arria10-spi",
+ "canaan,kendryte-k210-spi",
+ "canaan,kendryte-k210-ssi",
+ "intel,stratix10-spi",
+ "intel,agilex-spi",
+ "mscc,ocelot-spi",
+ or "mscc,jaguar2-spi";
+ and one of
+ "snps,dw-apb-ssi-3.20a",
+ "snps,dw-apb-ssi-3.22a",
+ "snps,dw-apb-ssi-3.23",
+ "snps,dw-apb-ssi-4.00a",
+ "snps,dw-apb-ssi-4.01",
+ or "snps,dwc-ssi-1.01a".
+ "snps,dw-apb-ssi" may also be used, but is deprecated in favor of specific
+ version strings.
+- reg : The register base for the controller. For "mscc,-spi", a second
+ register set is required (named ICPU_CFG:SPI_MST)
+- #address-cells : <1>, as required by generic SPI binding.
+- #size-cells : <0>, also as required by generic SPI binding.
+- clocks : phandles for the clocks, see the description of clock-names below.
+ The phandle for the "ssi_clk" is required. The phandle for the "pclk" clock
+ is optional. If a single clock is specified but no clock-name, it is the
+ "ssi_clk" clock. If both clocks are listed, the "ssi_clk" must be first.
+
+Optional properties:
+- clock-names : Contains the names of the clocks:
+"ssi_clk", for the core clock used to generate the external SPI clock.
+"pclk", the interface clock, required for register access.
+- cs-gpios : Specifies the gpio pins to be used for chipselects.
+- num-cs : The number of chipselects. If omitted, this will default to 4.
+- reg-io-width : The I/O register width (in bytes) implemented by this
+ device. Supported values are 2 or 4 (the default).
+
+Child nodes as per the generic SPI binding.
+
+Example:
+
+ spi@fff0 {
+ compatible = "altr,socfpga-arria10-spi",
+"snps,dw-apb-ssi-4.00a", "snps,dw-apb-ssi";
+ reg = <0xfff0 0x1000>;
+ interrupts = <0 154 4>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <_m_clk>;
+ num-cs = <2>;
+ cs-gpios = < 13 0>,
+ < 14 0>;
+ };
--
2.28.0
[PATCH v4 11/13] spi: dw: Add mem_ops
The designware ssi device has "broken" chip select behaviour [1], and needs
specific manipulation to use the built-in chip select. The existing fix is
to use an external GPIO for chip select, but typically the K210 has SPI3
directly connected to a flash chip with dedicated pins. This makes it
impossible to use the spi_xfer function to use spi, since the CS is
de-asserted in between calls. This patch adds an implementation of
exec_op, which gives correct behaviour when reading/writing spi flash.
This patch also rearranges the headers to conform to U-Boot style.
[1] https://lkml.org/lkml/2015/12/23/132
Signed-off-by: Sean Anderson
Tested-by Eugeniy Paltsev
---
This patch was previously part of
https://patchwork.ozlabs.org/project/uboot/list/?series=161576
Changes in v4:
- Overcome my sloth
- Rearrange headers in designware_spi.c
Changes in v3:
- Use constant 0x1 instead of SZ_64K. The latter is not included on
some platforms and I'm too lazy to figure out what the correct header is.
Changes in v2:
- Add external gpio cs support
- Clean up exec_op
- Convert debug to log_*
- Limit data transfers to 64k
drivers/spi/designware_spi.c | 122 ---
1 file changed, 113 insertions(+), 9 deletions(-)
diff --git a/drivers/spi/designware_spi.c b/drivers/spi/designware_spi.c
index 9e02fce6c6..ce74ac0abc 100644
--- a/drivers/spi/designware_spi.c
+++ b/drivers/spi/designware_spi.c
@@ -12,21 +12,23 @@
#define LOG_CATEGORY UCLASS_SPI
#include
-#include
-#include
#include
#include
-#include
-#include
-#include
-#include
-#include
#include
-#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
#include
+#include
#include
#include
-#include
+#include
/* Register offsets */
#define DW_SPI_CTRLR0 0x00
@@ -560,6 +562,107 @@ static int dw_spi_xfer(struct udevice *dev, unsigned int
bitlen,
return ret;
}
+/*
+ * This function is necessary for reading SPI flash with the native CS
+ * c.f. https://lkml.org/lkml/2015/12/23/132
+ */
+static int dw_spi_exec_op(struct spi_slave *slave, const struct spi_mem_op *op)
+{
+ bool read = op->data.dir == SPI_MEM_DATA_IN;
+ int pos, i, ret = 0;
+ struct udevice *bus = slave->dev->parent;
+ struct dw_spi_priv *priv = dev_get_priv(bus);
+ u8 op_len = sizeof(op->cmd.opcode) + op->addr.nbytes + op->dummy.nbytes;
+ u8 op_buf[op_len];
+ u32 cr0;
+
+ if (read)
+ priv->tmode = CTRLR0_TMOD_EPROMREAD;
+ else
+ priv->tmode = CTRLR0_TMOD_TO;
+
+ cr0 = priv->update_cr0(priv);
+ dev_dbg(bus, "cr0=%08x buf=%p len=%u [bytes]\n", cr0, op->data.buf.in,
+ op->data.nbytes);
+
+ dw_write(priv, DW_SPI_SSIENR, 0);
+ dw_write(priv, DW_SPI_CTRLR0, cr0);
+ if (read)
+ dw_write(priv, DW_SPI_CTRLR1, op->data.nbytes - 1);
+ dw_write(priv, DW_SPI_SSIENR, 1);
+
+ /* From spi_mem_exec_op */
+ pos = 0;
+ op_buf[pos++] = op->cmd.opcode;
+ if (op->addr.nbytes) {
+ for (i = 0; i < op->addr.nbytes; i++)
+ op_buf[pos + i] = op->addr.val >>
+ (8 * (op->addr.nbytes - i - 1));
+
+ pos += op->addr.nbytes;
+ }
+ if (op->dummy.nbytes)
+ memset(op_buf + pos, 0xff, op->dummy.nbytes);
+
+ external_cs_manage(slave->dev, false);
+
+ priv->tx = _buf;
+ priv->tx_end = priv->tx + op_len;
+ priv->rx = NULL;
+ priv->rx_end = NULL;
+ while (priv->tx != priv->tx_end)
+ dw_writer(priv);
+
+ /*
+* XXX: The following are tight loops! Enabling debug messages may cause
+* them to fail because we are not reading/writing the fifo fast enough.
+*/
+ if (read) {
+ priv->rx = op->data.buf.in;
+ priv->rx_end = priv->rx + op->data.nbytes;
+
+ dw_write(priv, DW_SPI_SER, 1 << spi_chip_select(slave->dev));
+ while (priv->rx != priv->rx_end)
+ dw_reader(priv);
+ } else {
+ u32 val;
+
+ priv->tx = op->data.buf.out;
+ priv->tx_end = priv->tx + op->data.nbytes;
+
+ /* Fill up the write fifo before starting the transfer */
+ dw_writer(priv);
+ dw_write(priv, DW_SPI_SER, 1 << spi_chip_select(slave->dev));
+ while (priv->tx != priv->tx_end)
+ dw_writer(priv);
+
+ if (readl_poll_timeout(priv->regs + DW_SPI_SR, val,
+ (val & SR_TF_EMPT) && !(val & SR_BUSY),
+ RX_TIMEOUT * 1000)) {
+ ret = -ETIMEDOUT;
+ }
+ }
+
+ dw_write(priv, DW_SPI_SER, 0);
+ external_cs_manage(slave->dev, true);
+
+ dev_dbg(bus, "%u bytes
[PATCH v4 09/13] spi: dw: Add support for multiple CTRLR0 layouts
CTRLR0 can have several different layouts depending on the specific device (dw-apb-ssi vs dwc-ssi), and specific parameters set during synthesis. Update the driver to support three specific configurations: dw-apb-ssi with SSI_MAX_XFER_SIZE=16, dw-apb-ssi with SSI_MAX_XFER_SIZE=32, and dwc-ssi. dw-apb-ssi is the version of the device on Altera/Intel SoCFPGAs, MSCC SoCs, and Canaan Kendryte K210 SoCs. This is the only version this driver supported before this change. The register layout before version 3.23a is: | 31 .. 16 | | other stuff | | 15 .. 10 | 9 .. 8 | 7 .. 6 | 5 .. 4 | 3 .. 0 | | other stuff | TMOD | MODE | FRF | DFS | Note that DFS (Data Frame Size) is only 4 bits, limiting transfers to data frames of 16 bits or less. In version 3.23a, the SSI_MAX_XFER_SIZE parameter was introduced. This parameter defaults to 16 (resulting in the same layout as prior versions), but may also be set to 32. To allow setting longer data frame sizes, a new DFS_32 register was introduced: | 31 .. 21 | 20 .. 16 | | other stuff | DFS_32 | | 15 .. 10 | 9 .. 8 | 7 .. 6 | 5 .. 4 | 3 .. 0 | | other stuff | TMOD | MODE | FRF | all zeros | The old DFS field no longer controls the data frame size. To detect this layout, we try writing 0xF to DFS. If we read back 0x0, then this device has SSI_MAX_XFER_SIZE=32. dwc-ssi is the version of the device on Intel Keem Bay SoCs and Canaan Kendryte K210 SoCs. The layout of ctrlr0 is: | 31 .. 16 | | other stuff | | 15 .. 12 | 11 .. 10 | 9 .. 8 | 7 .. 6 | 4 .. 0 | | other stuff | TMOD | MODE | FRF | DFS_32 | The semantics of the fields have not changed since the previous version. However, SSI_MAX_XFER_SIZE is effectively always 32. To support these different layouts, we model our approach on the one which the Linux kernel has taken. During probe, the driver calls an init function stored in driver_data. This init function is responsible for determining the layout of CTRLR0, and supplying the update_cr0 function. The style of and information behind this commit is based on the Linux MMIO driver for these devices. Specific reference was made to the series adding support for Intel Keem Bay SoCs [1]. [1] https://lore.kernel.org/linux-spi/20200505130618.554-1-wan.ahmad.zainie.wan.moha...@intel.com/ Signed-off-by: Sean Anderson --- Changes in v4: - Auto-detect SSI_MAX_XFER_SIZE Changes in v3: - Prefix log messages with SPI@ Changes in v2: - Configure ctrlr0 register layout based on compatible string - Split documentation off into its own patch drivers/spi/designware_spi.c | 176 +-- 1 file changed, 145 insertions(+), 31 deletions(-) diff --git a/drivers/spi/designware_spi.c b/drivers/spi/designware_spi.c index 0ebd2cf3cb..9e02fce6c6 100644 --- a/drivers/spi/designware_spi.c +++ b/drivers/spi/designware_spi.c @@ -3,6 +3,7 @@ * Designware master SPI core controller driver * * Copyright (C) 2014 Stefan Roese + * Copyright (C) 2020 Sean Anderson * * Very loosely based on the Linux driver: * drivers/spi/spi-dw.c, which is: @@ -22,6 +23,7 @@ #include #include #include +#include #include #include #include @@ -54,28 +56,48 @@ #define DW_SPI_DR 0x60 /* Bit fields in CTRLR0 */ -#define SPI_DFS_OFFSET 0 +/* + * Only present when SSI_MAX_XFER_SIZE=16. This is the default, and the only + * option before version 3.23a. + */ +#define CTRLR0_DFS_MASKGENMASK(3, 0) -#define SPI_FRF_OFFSET 4 -#define SPI_FRF_SPI0x0 -#define SPI_FRF_SSP0x1 -#define SPI_FRF_MICROWIRE 0x2 -#define SPI_FRF_RESV 0x3 +#define CTRLR0_FRF_MASKGENMASK(5, 4) +#define CTRLR0_FRF_SPI 0x0 +#define CTRLR0_FRF_SSP 0x1 +#define CTRLR0_FRF_MICROWIRE 0x2 +#define CTRLR0_FRF_RESV0x3 -#define SPI_MODE_OFFSET6 -#define SPI_SCPH_OFFSET6 -#define SPI_SCOL_OFFSET7 +#define CTRLR0_MODE_MASK GENMASK(7, 6) +#define CTRLR0_MODE_SCPH 0x1 +#define CTRLR0_MODE_SCPOL 0x2 -#define SPI_TMOD_OFFSET8 -#define SPI_TMOD_MASK (0x3 << SPI_TMOD_OFFSET) -#defineSPI_TMOD_TR 0x0 /* xmit & recv */ -#define SPI_TMOD_TO0x1 /* xmit only */ -#define SPI_TMOD_RO0x2 /* recv only */ -#define SPI_TMOD_EPROMREAD 0x3 /* eeprom read mode */ +#define CTRLR0_TMOD_MASK GENMASK(9, 8) +#defineCTRLR0_TMOD_TR 0x0 /* xmit & recv */ +#define CTRLR0_TMOD_TO 0x1 /* xmit only */ +#define CTRLR0_TMOD_RO 0x2 /* recv only */ +#define
[PATCH v4 12/13] riscv: Add device tree bindings for SPI
This patch adds bindings for the MMC slot and SPI flash on the Sipeed Maix
Bit.
Signed-off-by: Sean Anderson
Acked-by: Rick Chen
---
This patch was previously part of
https://patchwork.ozlabs.org/project/uboot/list/?series=161576
(no changes since v2)
Changes in v2:
- Remove broken-wp property (implicit due to no wp gpio)
- Remove ctrl0 field offsets from device tree
- Switch to new compatible strings
- Switch to new pinmux binding style
arch/riscv/dts/k210-maix-bit.dts | 46 +++-
arch/riscv/dts/k210.dtsi | 2 ++
2 files changed, 47 insertions(+), 1 deletion(-)
diff --git a/arch/riscv/dts/k210-maix-bit.dts b/arch/riscv/dts/k210-maix-bit.dts
index c2beec602c..e4dea205b2 100644
--- a/arch/riscv/dts/k210-maix-bit.dts
+++ b/arch/riscv/dts/k210-maix-bit.dts
@@ -152,7 +152,7 @@
pinmux = ,
,
,
-;
+; /* cs */
};
};
@@ -160,3 +160,47 @@
pinctrl-0 = <_dvp>;
pinctrl-names = "default";
};
+
+ {
+ pinctrl-0 = <_spi0>;
+ pinctrl-names = "default";
+ num-cs = <1>;
+ cs-gpios = < 20 0>;
+
+ panel@0 {
+ compatible = "sitronix,st7789v";
+ reg = <0>;
+ reset-gpios = < 21 GPIO_ACTIVE_LOW>;
+ dc-gpios = < 22 0>;
+ spi-max-frequency = <1500>;
+ status = "disabled";
+ };
+};
+
+ {
+ pinctrl-0 = <_spi1>;
+ pinctrl-names = "default";
+ num-cs = <1>;
+ cs-gpios = < 13 0>;
+ status = "okay";
+
+ slot@0 {
+ compatible = "mmc-spi-slot";
+ reg = <0>;
+ spi-max-frequency = <2500>;
+ voltage-ranges = <3300 3300>;
+ broken-cd;
+ };
+};
+
+ {
+ status = "okay";
+
+ spi-flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <5000>;
+ m25p,fast-read;
+ broken-flash-reset;
+ };
+};
diff --git a/arch/riscv/dts/k210.dtsi b/arch/riscv/dts/k210.dtsi
index 1ae3bf9bdf..98411e63a4 100644
--- a/arch/riscv/dts/k210.dtsi
+++ b/arch/riscv/dts/k210.dtsi
@@ -496,6 +496,8 @@
interrupts = <24>;
clocks = < K210_CLK_DVP>;
resets = < K210_RST_DVP>;
+ kendryte,sysctl = <>;
+ kendryte,misc-offset = ;
status = "disabled";
};
--
2.28.0
[PATCH v4 03/13] spi: dw: Rename "cs-gpio" to "cs-gpios"
This property is named differently than other SPI drivers with the same
property, as well as the property as used in Linux.
Signed-off-by: Sean Anderson
Tested-by Eugeniy Paltsev
---
AFAIK these device trees are not synced with Linux. However, if they are,
they have not been synced since this property was renamed in Linux.
This patch was previously part of
https://patchwork.ozlabs.org/project/uboot/list/?series=161576
(no changes since v1)
arch/arc/dts/axs10x_mb.dtsi | 3 ++-
arch/arc/dts/hsdk-common.dtsi | 3 ++-
drivers/spi/designware_spi.c | 3 ++-
3 files changed, 6 insertions(+), 3 deletions(-)
diff --git a/arch/arc/dts/axs10x_mb.dtsi b/arch/arc/dts/axs10x_mb.dtsi
index 33b0593438..daf7ca68fb 100644
--- a/arch/arc/dts/axs10x_mb.dtsi
+++ b/arch/arc/dts/axs10x_mb.dtsi
@@ -97,7 +97,8 @@
spi-max-frequency = <400>;
clocks = <>;
clock-names = "spi_clk";
- cs-gpio = <_gpio 0>;
+ num-cs = <1>;
+ cs-gpios = <_gpio 0>;
spi_flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
diff --git a/arch/arc/dts/hsdk-common.dtsi b/arch/arc/dts/hsdk-common.dtsi
index 9aa10e4b25..a4b348b948 100644
--- a/arch/arc/dts/hsdk-common.dtsi
+++ b/arch/arc/dts/hsdk-common.dtsi
@@ -135,7 +135,8 @@
spi-max-frequency = <400>;
clocks = <_clk CLK_SYS_SPI_REF>;
clock-names = "spi_clk";
- cs-gpio = <_gpio 0>;
+ num-cs = <1>;
+ cs-gpios = <_gpio 0>;
spi_flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
diff --git a/drivers/spi/designware_spi.c b/drivers/spi/designware_spi.c
index b23655d4d9..32de33f695 100644
--- a/drivers/spi/designware_spi.c
+++ b/drivers/spi/designware_spi.c
@@ -135,7 +135,8 @@ static int request_gpio_cs(struct udevice *bus)
int ret;
/* External chip select gpio line is optional */
- ret = gpio_request_by_name(bus, "cs-gpio", 0, >cs_gpio, 0);
+ ret = gpio_request_by_name(bus, "cs-gpios", 0, >cs_gpio,
+ GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
if (ret == -ENOENT)
return 0;
--
2.28.0
[PATCH v4 07/13] spi: dw: Rearrange struct dw_spi_priv
This should reduce the size of the struct, and also groups more similar
fields together.
Signed-off-by: Sean Anderson
Tested-by Eugeniy Paltsev
---
(no changes since v2)
Changes in v2:
-New
drivers/spi/designware_spi.c | 27 +--
1 file changed, 13 insertions(+), 14 deletions(-)
diff --git a/drivers/spi/designware_spi.c b/drivers/spi/designware_spi.c
index 89a8266052..0ebd2cf3cb 100644
--- a/drivers/spi/designware_spi.c
+++ b/drivers/spi/designware_spi.c
@@ -95,27 +95,26 @@ struct dw_spi_platdata {
};
struct dw_spi_priv {
- void __iomem *regs;
- unsigned int freq; /* Default frequency */
- unsigned int mode;
struct clk clk;
- unsigned long bus_clk_rate;
-
+ struct reset_ctl_bulk resets;
struct gpio_desc cs_gpio; /* External chip-select gpio */
- int bits_per_word;
- u8 cs; /* chip select pin */
- u8 tmode; /* TR/TO/RO/EEPROM */
- u8 type;/* SPI/SSP/MicroWire */
- int len;
+ void __iomem *regs;
+ unsigned long bus_clk_rate;
+ unsigned int freq; /* Default frequency */
+ unsigned int mode;
- u32 fifo_len; /* depth of the FIFO buffer */
- void *tx;
- void *tx_end;
+ const void *tx;
+ const void *tx_end;
void *rx;
void *rx_end;
+ u32 fifo_len; /* depth of the FIFO buffer */
- struct reset_ctl_bulk resets;
+ int bits_per_word;
+ int len;
+ u8 cs; /* chip select pin */
+ u8 tmode; /* TR/TO/RO/EEPROM */
+ u8 type;/* SPI/SSP/MicroWire */
};
static inline u32 dw_read(struct dw_spi_priv *priv, u32 offset)
--
2.28.0
[PATCH v4 06/13] spi: dw: Remove spi_enable_chip
This function does nothing but wrap dw_write.
Signed-off-by: Sean Anderson
---
Changes in v4:
- New
drivers/spi/designware_spi.c | 17 ++---
1 file changed, 6 insertions(+), 11 deletions(-)
diff --git a/drivers/spi/designware_spi.c b/drivers/spi/designware_spi.c
index 8abcdde8a3..89a8266052 100644
--- a/drivers/spi/designware_spi.c
+++ b/drivers/spi/designware_spi.c
@@ -171,17 +171,12 @@ static int dw_spi_ofdata_to_platdata(struct udevice *bus)
return request_gpio_cs(bus);
}
-static inline void spi_enable_chip(struct dw_spi_priv *priv, int enable)
-{
- dw_write(priv, DW_SPI_SSIENR, (enable ? 1 : 0));
-}
-
/* Restart the controller, disable all interrupts, clean rx fifo */
static void spi_hw_init(struct udevice *bus, struct dw_spi_priv *priv)
{
- spi_enable_chip(priv, 0);
+ dw_write(priv, DW_SPI_SSIENR, 0);
dw_write(priv, DW_SPI_IMR, 0xff);
- spi_enable_chip(priv, 1);
+ dw_write(priv, DW_SPI_SSIENR, 1);
/*
* Try to detect the FIFO depth if not set by interface driver,
@@ -438,7 +433,7 @@ static int dw_spi_xfer(struct udevice *dev, unsigned int
bitlen,
priv->rx_end = priv->rx + priv->len;
/* Disable controller before writing control registers */
- spi_enable_chip(priv, 0);
+ dw_write(priv, DW_SPI_SSIENR, 0);
dev_dbg(dev, "cr0=%08x rx=%p tx=%p len=%d [bytes]\n", cr0, rx, tx,
priv->len);
@@ -455,7 +450,7 @@ static int dw_spi_xfer(struct udevice *dev, unsigned int
bitlen,
dw_write(priv, DW_SPI_SER, 1 << cs);
/* Enable controller after writing control registers */
- spi_enable_chip(priv, 1);
+ dw_write(priv, DW_SPI_SSIENR, 1);
/* Start transfer in a polling loop */
ret = poll_transfer(priv);
@@ -490,7 +485,7 @@ static int dw_spi_set_speed(struct udevice *bus, uint speed)
speed = plat->frequency;
/* Disable controller before writing control registers */
- spi_enable_chip(priv, 0);
+ dw_write(priv, DW_SPI_SSIENR, 0);
/* clk_div doesn't support odd number */
clk_div = priv->bus_clk_rate / speed;
@@ -498,7 +493,7 @@ static int dw_spi_set_speed(struct udevice *bus, uint speed)
dw_write(priv, DW_SPI_BAUDR, clk_div);
/* Enable controller after writing control registers */
- spi_enable_chip(priv, 1);
+ dw_write(priv, DW_SPI_SSIENR, 1);
priv->freq = speed;
dev_dbg(bus, "speed=%d clk_div=%d\n", priv->freq, clk_div);
--
2.28.0
[PATCH v4 05/13] spi: dw: Rename registers to match datasheet
A few registers had slightly different names from what is in the datasheet.
Signed-off-by: Sean Anderson
---
(no changes since v1)
drivers/spi/designware_spi.c | 18 +-
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/drivers/spi/designware_spi.c b/drivers/spi/designware_spi.c
index e8ba80ef41..8abcdde8a3 100644
--- a/drivers/spi/designware_spi.c
+++ b/drivers/spi/designware_spi.c
@@ -27,14 +27,14 @@
#include
/* Register offsets */
-#define DW_SPI_CTRL0 0x00
-#define DW_SPI_CTRL1 0x04
+#define DW_SPI_CTRLR0 0x00
+#define DW_SPI_CTRLR1 0x04
#define DW_SPI_SSIENR 0x08
#define DW_SPI_MWCR0x0c
#define DW_SPI_SER 0x10
#define DW_SPI_BAUDR 0x14
-#define DW_SPI_TXFLTR 0x18
-#define DW_SPI_RXFLTR 0x1c
+#define DW_SPI_TXFTLR 0x18
+#define DW_SPI_RXFTLR 0x1c
#define DW_SPI_TXFLR 0x20
#define DW_SPI_RXFLR 0x24
#define DW_SPI_SR 0x28
@@ -191,13 +191,13 @@ static void spi_hw_init(struct udevice *bus, struct
dw_spi_priv *priv)
u32 fifo;
for (fifo = 1; fifo < 256; fifo++) {
- dw_write(priv, DW_SPI_TXFLTR, fifo);
- if (fifo != dw_read(priv, DW_SPI_TXFLTR))
+ dw_write(priv, DW_SPI_TXFTLR, fifo);
+ if (fifo != dw_read(priv, DW_SPI_TXFTLR))
break;
}
priv->fifo_len = (fifo == 1) ? 0 : fifo;
- dw_write(priv, DW_SPI_TXFLTR, 0);
+ dw_write(priv, DW_SPI_TXFTLR, 0);
}
dev_dbg(bus, "fifo_len=%d\n", priv->fifo_len);
}
@@ -443,8 +443,8 @@ static int dw_spi_xfer(struct udevice *dev, unsigned int
bitlen,
dev_dbg(dev, "cr0=%08x rx=%p tx=%p len=%d [bytes]\n", cr0, rx, tx,
priv->len);
/* Reprogram cr0 only if changed */
- if (dw_read(priv, DW_SPI_CTRL0) != cr0)
- dw_write(priv, DW_SPI_CTRL0, cr0);
+ if (dw_read(priv, DW_SPI_CTRLR0) != cr0)
+ dw_write(priv, DW_SPI_CTRLR0, cr0);
/*
* Configure the desired SS (slave select 0...3) in the controller
--
2.28.0
[PATCH v4 04/13] spi: dw: Use generic function to read reg address
Using an fdt-specific function causes problems when compiled with a live tree. Signed-off-by: Sean Anderson Tested-by Eugeniy Paltsev --- This patch was previously part of https://patchwork.ozlabs.org/project/uboot/list/?series=161576 (no changes since v1) drivers/spi/designware_spi.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/spi/designware_spi.c b/drivers/spi/designware_spi.c index 32de33f695..e8ba80ef41 100644 --- a/drivers/spi/designware_spi.c +++ b/drivers/spi/designware_spi.c @@ -160,6 +160,8 @@ static int dw_spi_ofdata_to_platdata(struct udevice *bus) struct dw_spi_platdata *plat = bus->platdata; plat->regs = dev_read_addr_ptr(bus); + if (!plat->regs) + return -EINVAL; /* Use 500KHz as a suitable default */ plat->frequency = dev_read_u32_default(bus, "spi-max-frequency", -- 2.28.0
[PATCH v4 02/13] spi: dw: Convert calls to debug to dev_*
This allows different log levels to be enabled or disabled depending on the
desired level of verbosity. In particular, it allows for general debug
information to be printed while excluding more verbose logging which may
interfere with timing.
Signed-off-by: Sean Anderson
---
Changes in v4:
- Consolidate log messages in dw_spi_xfer. We don't need to print twice in such
short succession.
- Convert most log_xxx messages to dev_xxx. Since ceb70bb870 ("dm: Print device
name in dev_xxx like Linux"), dev_xxx can be controlled at runtime in the same
way as log_xxx. The log messages in dw_reader/dw_writer are not converted to
reduce the amount of instructions in those loops, even with logging enabled.
Changes in v3:
- Lower the log level of some messages
- Prefix user-facing logs with SPI@
- Reword error messages as "message (error %d)"
Changes in v2:
- New
drivers/spi/designware_spi.c | 38 ++--
1 file changed, 19 insertions(+), 19 deletions(-)
diff --git a/drivers/spi/designware_spi.c b/drivers/spi/designware_spi.c
index 74372171aa..b23655d4d9 100644
--- a/drivers/spi/designware_spi.c
+++ b/drivers/spi/designware_spi.c
@@ -9,6 +9,7 @@
* Copyright (c) 2009, Intel Corporation.
*/
+#define LOG_CATEGORY UCLASS_SPI
#include
#include
#include
@@ -139,7 +140,7 @@ static int request_gpio_cs(struct udevice *bus)
return 0;
if (ret < 0) {
- printf("Error: %d: Can't get %s gpio!\n", ret, bus->name);
+ dev_err(bus, "Couldn't request gpio! (error %d)\n", ret);
return ret;
}
@@ -148,7 +149,7 @@ static int request_gpio_cs(struct udevice *bus)
GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
}
- debug("%s: used external gpio for CS management\n", __func__);
+ dev_dbg(bus, "Using external gpio for CS management\n");
#endif
return 0;
}
@@ -162,8 +163,7 @@ static int dw_spi_ofdata_to_platdata(struct udevice *bus)
/* Use 500KHz as a suitable default */
plat->frequency = dev_read_u32_default(bus, "spi-max-frequency",
50);
- debug("%s: regs=%p max-frequency=%d\n", __func__, plat->regs,
- plat->frequency);
+ dev_info(bus, "max-frequency=%d\n", plat->frequency);
return request_gpio_cs(bus);
}
@@ -174,7 +174,7 @@ static inline void spi_enable_chip(struct dw_spi_priv
*priv, int enable)
}
/* Restart the controller, disable all interrupts, clean rx fifo */
-static void spi_hw_init(struct dw_spi_priv *priv)
+static void spi_hw_init(struct udevice *bus, struct dw_spi_priv *priv)
{
spi_enable_chip(priv, 0);
dw_write(priv, DW_SPI_IMR, 0xff);
@@ -196,7 +196,7 @@ static void spi_hw_init(struct dw_spi_priv *priv)
priv->fifo_len = (fifo == 1) ? 0 : fifo;
dw_write(priv, DW_SPI_TXFLTR, 0);
}
- debug("%s: fifo_len=%d\n", __func__, priv->fifo_len);
+ dev_dbg(bus, "fifo_len=%d\n", priv->fifo_len);
}
/*
@@ -221,8 +221,7 @@ __weak int dw_spi_get_clk(struct udevice *bus, ulong *rate)
if (!*rate)
goto err_rate;
- debug("%s: get spi controller clk via device tree: %lu Hz\n",
- __func__, *rate);
+ dev_dbg(bus, "Got clock via device tree: %lu Hz\n", *rate);
return 0;
@@ -247,14 +246,16 @@ static int dw_spi_reset(struct udevice *bus)
if (ret == -ENOENT || ret == -ENOTSUPP)
return 0;
- dev_warn(bus, "Can't get reset: %d\n", ret);
+ dev_warn(bus, "Couldn't find/assert reset device (error %d)\n",
+ret);
return ret;
}
ret = reset_deassert_bulk(>resets);
if (ret) {
reset_release_bulk(>resets);
- dev_err(bus, "Failed to reset: %d\n", ret);
+ dev_err(bus, "Failed to de-assert reset for SPI (error %d)\n",
+ ret);
return ret;
}
@@ -284,7 +285,7 @@ static int dw_spi_probe(struct udevice *bus)
priv->tmode = 0; /* Tx & Rx */
/* Basic HW init */
- spi_hw_init(priv);
+ spi_hw_init(bus, priv);
return 0;
}
@@ -333,7 +334,7 @@ static void dw_writer(struct dw_spi_priv *priv)
txw = *(u16 *)(priv->tx);
}
dw_write(priv, DW_SPI_DR, txw);
- debug("%s: tx=0x%02x\n", __func__, txw);
+ log_content("tx=0x%02x\n", txw);
priv->tx += priv->bits_per_word >> 3;
}
}
@@ -345,7 +346,7 @@ static void dw_reader(struct dw_spi_priv *priv)
while (max--) {
rxw = dw_read(priv, DW_SPI_DR);
- debug("%s: rx=0x%02x\n", __func__, rxw);
+ log_content("rx=0x%02x\n", rxw);
/* Care about rx if the transfer's original "rx" is not
[PATCH v4 01/13] spi: dw: Fix driving MOSI low while recieving
The resting state of MOSI is high when nothing is driving it. If we drive
it low while recieving, it looks like we are transmitting 0x00 instead of
transmitting nothing. This can confuse slaves (like SD cards) which allow
new commands to be sent over MOSI while they are returning data over MISO.
The return of MOSI from 0 to 1 at the end of recieving a byte can look like
a start bit and a transmission bit to an SD card. This will cause the card
to become out-of-sync with the SPI device, as it thinks the device has
already started transmitting two bytes of a new command. The mmc-spi driver
will not detect the R1 response from the SD card, since it is sent too
early, and offset by two bits. This patch fixes transfer errors when using
SD cards with dw spi.
Signed-off-by: Sean Anderson
---
Changes in v4:
- New
drivers/spi/designware_spi.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/spi/designware_spi.c b/drivers/spi/designware_spi.c
index 2559aac2e9..74372171aa 100644
--- a/drivers/spi/designware_spi.c
+++ b/drivers/spi/designware_spi.c
@@ -322,7 +322,7 @@ static inline u32 rx_max(struct dw_spi_priv *priv)
static void dw_writer(struct dw_spi_priv *priv)
{
u32 max = tx_max(priv);
- u16 txw = 0;
+ u16 txw = 0x;
while (max--) {
/* Set the tx word if the transfer's original "tx" is not null
*/
--
2.28.0
[PATCH v4 00/13] riscv: Add SPI support for Kendryte K210
This series adds support for SPI on the Kendryte K210. This covers the MMC
slot and SPI flash on the Sipeed Maix Bit.
This series makes significant changes to the designware SPI driver. I would
really appreciate if the maintainers I CC'd could test this series and ensure
that SPI still works on all their devices. I have tried my best not to affect
existing devices, but I'd rather find out if this breaks stuff now rather than
later. In particular, the method of detecting SSI_MAX_XFER_SIZE has changed
since the last revision, and will need to be re-tested.
This series was previously part of
https://patchwork.ozlabs.org/project/uboot/list/?series=161576
Changes in v4:
- Auto-detect SSI_MAX_XFER_SIZE
- Consolidate log messages in dw_spi_xfer. We don't need to print twice in such
short succession.
- Convert most log_xxx messages to dev_xxx. Since ceb70bb870 ("dm: Print device
name in dev_xxx like Linux"), dev_xxx can be controlled at runtime in the same
way as log_xxx. The log messages in dw_reader/dw_writer are not converted to
reduce the amount of instructions in those loops, even with logging enabled.
- Enable booting from MMC
- Fix MMC transfer errors
- Place env in spi flash
- Rearrange headers in designware_spi.c
- Remove spi_enable_chip
- Update documentation
Changes in v3:
- Lower the log level of some messages
- Prefix user-facing logs with SPI@
- Rebase onto U-Boot master
- Remove env and bootcmd configuration. I'm going to punt on those for now,
since I haven't worked out the best way to boot with SPI yet. Those
settings may be added back in a follow-up patch.
- Reword error messages as "message (error %d)"
- Synchronize compatible strings between docs and driver
- Use constant 0x1 instead of SZ_64K. The latter is not included on
some platforms and I'm too lazy to figure out what the correct header is.
Changes in v2:
- Add Gigadevice SPI chips to dependencies
- Add external gpio cs support
- Clean up exec_op
- Configure ctrlr0 register layout based on compatible string
- Convert debug calls to log_ instead of removing the ones which affect
timing
- Document new compatible strings
- Limit data transfers to 64k
- Remove broken-wp property (implicit due to no wp gpio)
- Remove ctrl0 field offsets from device tree
- Switch to new compatible strings
- Switch to new pinmux binding style
Sean Anderson (13):
spi: dw: Fix driving MOSI low while recieving
spi: dw: Convert calls to debug to dev_*
spi: dw: Rename "cs-gpio" to "cs-gpios"
spi: dw: Use generic function to read reg address
spi: dw: Rename registers to match datasheet
spi: dw: Remove spi_enable_chip
spi: dw: Rearrange struct dw_spi_priv
spi: dw: Add SoC-specific compatible strings
spi: dw: Add support for multiple CTRLR0 layouts
spi: dw: Document devicetree binding
spi: dw: Add mem_ops
riscv: Add device tree bindings for SPI
riscv: Add support for SPI on Kendryte K210
arch/arc/dts/axs10x_mb.dtsi | 5 +-
arch/arc/dts/hsdk-common.dtsi | 5 +-
arch/arm/dts/socfpga.dtsi | 6 +-
arch/arm/dts/socfpga_agilex.dtsi | 6 +-
arch/arm/dts/socfpga_arria10.dtsi | 6 +-
arch/arm/dts/socfpga_stratix10.dtsi | 6 +-
arch/mips/dts/mscc,jr2.dtsi | 2 +-
arch/mips/dts/mscc,ocelot.dtsi| 2 +-
arch/riscv/dts/k210-maix-bit.dts | 46 +-
arch/riscv/dts/k210.dtsi | 15 +-
board/sipeed/maix/Kconfig | 16 +
configs/sipeed_maix_bitm_defconfig| 10 +
doc/board/sipeed/maix.rst | 319 +++---
.../spi/snps,dw-apb-ssi.txt | 56 +++
drivers/spi/designware_spi.c | 401 ++
include/configs/sipeed-maix.h | 7 +-
16 files changed, 743 insertions(+), 165 deletions(-)
create mode 100644 doc/device-tree-bindings/spi/snps,dw-apb-ssi.txt
--
2.28.0
Re: Please pull u-boot-marvell/master
On Fri, Oct 16, 2020 at 03:40:46PM +0200, Stefan Roese wrote: > Hi Tom, > > please pull an update of Marvell Octeon TX/TX2 related patches. Here the > summary log: > Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH v3 00/27] Add DM support for omap PWM backlight
Hi Felix, > Il 16/10/2020 10:41 Felix Brack ha scritto: > > > Hello Dario, > > On 15.10.20 20:56, Dario Binacchi wrote: > > Hi Felix, > > > >> Il 15/10/2020 10:53 Felix Brack ha scritto: > >> > >> > >> Hello Dario, > >> > >> On 14.10.20 23:22, Dario Binacchi wrote: > >>> > Il 14/10/2020 10:22 Felix Brack ha scritto: > > > On 11.10.20 14:13, Dario Binacchi wrote: > > The series was born from the need to manage the PWM backlight of the > > display connected to my beaglebone board. To hit the target, I had to > > develop drivers for PWM management which in turn relied on drivers for > > managing timers and clocks, all developed according to the driver model. > > My intention was to use the SoC-specific API only at strictly necessary > > points in the code. My previous patches for migrating the AM335x display > > driver to the driver model had required the implementation of additional > > functions outside the concerns of the driver, (settings for dividing the > > pixel clock rate, configuring the display DPLL rate, ) not being > > able to use the API of the related clock drivers. This series shouldn't > > have repeated the same kind of mistake. Furthermore, I also wanted to > > fix > > that kind of forced choice. Almost everything should have been > > accessible > > via the driver model API. In the series there are also some patches that > > could be submitted separately, but which I have however inserted to > > avoid > > applying future patches to incorporate them. > > With this last consideration, I hope I have convincingly justified the > > large number of patches in the series. > > > > The patch enabling address translation into a CPU physical address from > > device-tree even in case of crossing levels with #size-cells = <0>, is > > crucial for the series. The previous implementation was unable to > > perform the address translation required by the am33xx device tree. > > I tried to apply in a conservative way as few changes as possible and > > to verify the execution of all the tests already developed, as well as > > the new ones I added for the new feature. > > > > As recommended by Grygorii Strashko I have removed some patches to > > upload them in new different series: > > - [v2,01/30] clk: remove a redundant header > > - [v2,03/30] arch: sandbox: fix typo in clk.h > > - [v2,20/30] video: backlight: fix pwm's duty cycle calculation > > - [v2,21/30] video: backlight: fix pwm data structure description > > - [v2,22/30] dm: core: improve uclass_get_device_by_phandle_id() > > description > > - [v2,23/30] gpio: fix gpio_request_by_name() description > > > > Grygorii suggested to remove also other patches that I have kept in the > > series to allow anyone who wants to be able to test it. Moreover after > > the addition of a patch that has largely changed the device tree. The > > patches removed are the one and only ones that do not affect the series > > in any way. I hope that the next version of this series will require > > only minimal changes allowing me to split it according to Grygorii's > > suggestions. > > > > >>> > I must be missing something as this patch series does not apply without > errors to U-Boot master: > > >>> > >>> Hi Felix, > >>> I applied the patch of the series downloaded from patchwork on master and > >>> I compiled it without errors. > >>> > >> Did you do that against a recently cloned master? > >> > error: drivers/clk/clk-ti-am3-dpll-x2.c: No such file or directory > error: drivers/clk/clk-ti-am3-dpll.c: No such file or directory > error: drivers/clk/clk-ti-ctrl.c: No such file or directory > error: drivers/clk/clk-ti-divider.c: No such file or directory > error: drivers/clk/clk-ti-gate.c: No such file or directory > error: drivers/clk/clk-ti-mux.c: No such file or directory > error: drivers/clk/clk-ti.c: No such file or directory > error: drivers/clk/clk-ti.h: No such file or directory > >>> > >>> After applying the patch you should find: > >>> ls drivers/clk/ti > >>> am3-prcm.c > >>> clk-am3-dpll.c > >>> clk-am3-dpll-x2.c > >>> clk.c > >>> clk-ctrl.c > >>> clk-divider.c > >>> clk-gate.c > >>> clk.h > >>> clk-mux.c > >>> clk-sci.c > >>> Kconfig > >>> Makefile > >>> omap4-cm.c > >>> > error: drivers/video/tilcdc-panel.c: No such file or directory > error: drivers/video/tilcdc-panel.h: No such file or directory > error: drivers/video/tilcdc.c: No such file or directory > error: drivers/video/tilcdc.h: No such file or directory > > >>> > >>> and > >>> ls drivers/video/ti > >>> am335x-fb.c > >>> am335x-fb.h > >>> Kconfig > >>> Makefile > >>> tilcdc.c > >>> tilcdc.h > >>> tilcdc-panel.c > >>> tilcdc-panel.h > >>> > >> As the patch series does not apply I don't see
[PATCH v1 8/8] doc: board: Add Microchip MPFS Icicle Kit doc
From: Padmarao Begari
This doc describes the procedure to build, flash and
boot Linux using U-boot on Microchip MPFS Icicle Kit.
Signed-off-by: Padmarao Begari
---
doc/board/index.rst | 1 +
doc/board/microchip/index.rst | 9 +
doc/board/microchip/mpfs_icicle.rst | 605
3 files changed, 615 insertions(+)
create mode 100644 doc/board/microchip/index.rst
create mode 100644 doc/board/microchip/mpfs_icicle.rst
diff --git a/doc/board/index.rst b/doc/board/index.rst
index 63935abcd7..e50a78d752 100644
--- a/doc/board/index.rst
+++ b/doc/board/index.rst
@@ -15,6 +15,7 @@ Board-specific doc
freescale/index
google/index
intel/index
+ microchip/index
renesas/index
rockchip/index
sifive/index
diff --git a/doc/board/microchip/index.rst b/doc/board/microchip/index.rst
new file mode 100644
index 00..b09e6788af
--- /dev/null
+++ b/doc/board/microchip/index.rst
@@ -0,0 +1,9 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+Microchip
+==
+
+.. toctree::
+ :maxdepth: 2
+
+ mpfs_icicle
diff --git a/doc/board/microchip/mpfs_icicle.rst
b/doc/board/microchip/mpfs_icicle.rst
new file mode 100644
index 00..d1e6bd2077
--- /dev/null
+++ b/doc/board/microchip/mpfs_icicle.rst
@@ -0,0 +1,605 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+Microchip PolarFire SoC Icicle Kit
+==
+
+RISC-V PolarFire SoC
+-
+The PolarFire SoC is the 4+1 64-bit RISC-V SoC from Microchip.
+
+The Icicle Kit development platform is based on PolarFire SoC and capable
+of running Linux.
+
+Mainline support
+
+The support for following drivers are already enabled:
+
+1. NS16550 UART Driver.
+2. Microchip Clock Driver.
+3. Cadence MACB ethernet driver for networking support.
+4. Cadence MMC Driver for eMMC/SD support.
+
+Booting from eMMC using HSS
+---
+
+Building
+
+
+1. Add the RISC-V toolchain to your PATH.
+2. Setup ARCH & cross compilation environment variable:
+
+.. code-block:: none
+
+ export CROSS_COMPILE=
+
+3. make microchip_mpfs_icicle_defconfig
+4. make
+
+Flashing
+
+
+The current U-Boot port is supported in S-mode only and loaded from DRAM.
+
+A prior stage M-mode firmware/bootloader (e.g HSS with OpenSBI) is required to
+boot the u-boot.bin in S-mode.
+
+Currently, the u-boot.bin is used as a payload of the HSS firmware.
+
+You will be creating a payload from `u-boot-dtb.bin`.
+Copy this file to the toplevel HSS (Hart Software Services) directory.
+
+Creating the HSS payload
+
+
+Please refer to HSS documenation to build the HSS firmware.
+(Note: HSS git repo is at
+https://github.com/polarfire-soc/hart-software-services/blob/master
+/tools/hss-payload-generator/README.md)
+
+Once the payload binary is generated, it should be copied to the eMMC.
+
+FPGA design with HSS programming file
+-
+https://github.com/polarfire-soc/polarfire-soc-documentation/blob/master/boards
+/mpfs-icicle-kit-es/updating-icicle-kit/updating-icicle-kit-design-and-linux.md
+
+The HSS firmware runs from the PolarFire SoC eNVM on reset.
+
+eMMC
+
+Program eMMC with payload binary is explained in the PolarFire SoC
documentation.
+
+(Note: PolarFire SoC Documentation git repo is at
+https://github.com/polarfire-soc/polarfire-soc-documentation/blob/master/boards
+/mpfs-icicle-kit-es/updating-icicle-kit/updating-icicle-kit-design-and-linux.md#eMMC
+
+Once the payload image is copied to the eMMC, press CTRL+C in the HSS command
+line interface, then type 'boot' and enter to boot the newly copied image.
+
+.. code-block:: none
+
+sudo dd if= of=/dev/sdX bs=512
+
+Booting
+---
+you should see the U-Boot prompt on UART1.
+
+Sample boot log from MPFS Icicle Kit
+---
+
+.. code-block:: none
+
+ U-Boot 2020.10-00544-g4f642dd804-dirty (Oct 16 2020 - 11:37:31 +0530)
+
+ CPU: rv64imafdc
+ Model: Microchip PolarFire-SoC
+ DRAM: 1 GiB
+ MMC: sdhc@20008000: 0
+ In:serial@2010
+ Out: serial@2010
+ Err: serial@2010
+ Net: eth0: ethernet@20112000
+ Hit any key to stop autoboot: 0
+
+Now you can configure your networking, tftp server and use tftp boot method to
+load uImage(with initramfs).
+
+.. code-block:: none
+
+ RISC-V # setenv kernel_addr_r 0x8020
+ RISC-V # setenv fdt_addr_r 0x8220
+
+ RISC-V # setenv ipaddr 192.168.1.5
+ RISC-V # setenv netmask 255.255.255.0
+ RISC-V # setenv serverip 192.168.1.3
+ RISC-V # setenv gateway 192.168.1.1
+
+ RISC-V # tftpboot ${kernel_addr_r} uImage
+ ethernet@20112000: PHY present at 9
+ ethernet@20112000: Starting autonegotiation...
+ ethernet@20112000: Autonegotiation complete
+ ethernet@20112000: link up, 1000Mbps full-duplex (lpa: 0x7800)
+ Using ethernet@20112000 device
+ TFTP from server 192.168.1.3; our IP address is 192.168.1.5
+ Filename
[PATCH v1 7/8] clk: Add Microchip PolarFire SoC clock driver
From: Padmarao Begari
Add clock driver code for the Microchip PolarFire SoC. This driver
handles reset and clock control of the Microchip PolarFire SoC device.
Signed-off-by: Padmarao Begari
---
drivers/clk/Kconfig | 1 +
drivers/clk/Makefile | 1 +
drivers/clk/microchip/Kconfig| 5 +
drivers/clk/microchip/Makefile | 1 +
drivers/clk/microchip/clk_pfsoc.c| 120
drivers/clk/microchip/clk_pfsoc.h| 19 +++
drivers/clk/microchip/clk_pfsoc_cfg.c| 135 ++
drivers/clk/microchip/clk_pfsoc_periph.c | 171 +++
8 files changed, 453 insertions(+)
create mode 100644 drivers/clk/microchip/Kconfig
create mode 100644 drivers/clk/microchip/Makefile
create mode 100644 drivers/clk/microchip/clk_pfsoc.c
create mode 100644 drivers/clk/microchip/clk_pfsoc.h
create mode 100644 drivers/clk/microchip/clk_pfsoc_cfg.c
create mode 100644 drivers/clk/microchip/clk_pfsoc_periph.c
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 4dfbad7986..1161fe7b5a 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -173,6 +173,7 @@ source "drivers/clk/exynos/Kconfig"
source "drivers/clk/imx/Kconfig"
source "drivers/clk/kendryte/Kconfig"
source "drivers/clk/meson/Kconfig"
+source "drivers/clk/microchip/Kconfig"
source "drivers/clk/mvebu/Kconfig"
source "drivers/clk/owl/Kconfig"
source "drivers/clk/renesas/Kconfig"
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index d1e295ac7c..bd8a6eed88 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -28,6 +28,7 @@ obj-$(CONFIG_CLK_EXYNOS) += exynos/
obj-$(CONFIG_$(SPL_TPL_)CLK_INTEL) += intel/
obj-$(CONFIG_CLK_HSDK) += clk-hsdk-cgu.o
obj-$(CONFIG_CLK_K210) += kendryte/
+obj-$(CONFIG_CLK_MPFS) += microchip/
obj-$(CONFIG_CLK_MPC83XX) += mpc83xx_clk.o
obj-$(CONFIG_CLK_OCTEON) += clk_octeon.o
obj-$(CONFIG_CLK_OWL) += owl/
diff --git a/drivers/clk/microchip/Kconfig b/drivers/clk/microchip/Kconfig
new file mode 100644
index 00..b70241559d
--- /dev/null
+++ b/drivers/clk/microchip/Kconfig
@@ -0,0 +1,5 @@
+config CLK_MPFS
+ bool "Clock support for Microchip PolarFire SoC"
+ depends on CLK && CLK_CCF
+ help
+ This enables support clock driver for Microchip PolarFire SoC
platform.
diff --git a/drivers/clk/microchip/Makefile b/drivers/clk/microchip/Makefile
new file mode 100644
index 00..c7f5ad21ae
--- /dev/null
+++ b/drivers/clk/microchip/Makefile
@@ -0,0 +1 @@
+obj-y += clk_pfsoc.o clk_pfsoc_cfg.o clk_pfsoc_periph.o
diff --git a/drivers/clk/microchip/clk_pfsoc.c
b/drivers/clk/microchip/clk_pfsoc.c
new file mode 100644
index 00..6c7f89f25c
--- /dev/null
+++ b/drivers/clk/microchip/clk_pfsoc.c
@@ -0,0 +1,120 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2020 Microchip Technology Inc.
+ * Padmarao Begari
+ */
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "clk_pfsoc.h"
+
+/* All methods are delegated to CCF clocks */
+
+static ulong pfsoc_clk_get_rate(struct clk *clk)
+{
+ struct clk *c;
+ int err = clk_get_by_id(clk->id, );
+
+ if (err)
+ return err;
+ return clk_get_rate(c);
+}
+
+static ulong pfsoc_clk_set_rate(struct clk *clk, unsigned long rate)
+{
+ struct clk *c;
+ int err = clk_get_by_id(clk->id, );
+
+ if (err)
+ return err;
+ return clk_set_rate(c, rate);
+}
+
+static int pfsoc_clk_set_parent(struct clk *clk, struct clk *parent)
+{
+ struct clk *c, *p;
+ int err = clk_get_by_id(clk->id, );
+
+ if (err)
+ return err;
+
+ err = clk_get_by_id(parent->id, );
+ if (err)
+ return err;
+
+ return clk_set_parent(c, p);
+}
+
+static int pfsoc_clk_endisable(struct clk *clk, bool enable)
+{
+ struct clk *c;
+ int err = clk_get_by_id(clk->id, );
+
+ if (err)
+ return err;
+ return enable ? clk_enable(c) : clk_disable(c);
+}
+
+static int pfsoc_clk_enable(struct clk *clk)
+{
+ return pfsoc_clk_endisable(clk, true);
+}
+
+static int pfsoc_clk_disable(struct clk *clk)
+{
+ return pfsoc_clk_endisable(clk, false);
+}
+
+static int pfsoc_clk_probe(struct udevice *dev)
+{
+ int ret;
+ void __iomem *base;
+ u32 clk_rate;
+ struct clk *clk;
+ const char *parent_clk_name;
+
+ base = dev_read_addr_ptr(dev);
+ if (!base)
+ return -ENODEV;
+ clk = kzalloc(sizeof(*clk), GFP_KERNEL);
+ if (!clk)
+ return -ENOMEM;
+
+ ret = clk_get_by_index(dev, 0, clk);
+ if (ret)
+ return ret;
+ dev_read_u32(clk->dev, "clock-frequency", _rate);
+ parent_clk_name = clk->dev->name;
+ ret = pfsoc_clk_register_cfgs(base, clk_rate, parent_clk_name);
+ ret = pfsoc_clk_register_periphs(base,
[PATCH v1 6/8] net: macb: Add phy address to read it from device tree
From: Padmarao Begari
Read phy address from device tree and use it to find the phy device
if not found then search in the range of 0 to 31.
Signed-off-by: Padmarao Begari
---
drivers/net/macb.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/drivers/net/macb.c b/drivers/net/macb.c
index e06d85d849..fda90f4e49 100644
--- a/drivers/net/macb.c
+++ b/drivers/net/macb.c
@@ -477,6 +477,12 @@ static int macb_phy_find(struct macb_device *macb, const
char *name)
int i;
u16 phy_id;
+ phy_id = macb_mdio_read(macb, macb->phy_addr, MII_PHYSID1);
+ if (phy_id != 0x) {
+ printf("%s: PHY present at %d\n", name, macb->phy_addr);
+ return 0;
+ }
+
/* Search for PHY... */
for (i = 0; i < 32; i++) {
macb->phy_addr = i;
@@ -1254,6 +1260,8 @@ static int macb_eth_probe(struct udevice *dev)
struct macb_device *macb = dev_get_priv(dev);
const char *phy_mode;
int ret;
+ u32 phy_addr;
+ ofnode node;
phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",
NULL);
@@ -1264,6 +1272,13 @@ static int macb_eth_probe(struct udevice *dev)
return -EINVAL;
}
+ /* Look for a PHY node under the Ethernet node */
+ node = dev_read_subnode(dev, "ethernet-phy");
+ if (ofnode_valid(node)) {
+ ofnode_read_u32(node, "reg", _addr);
+ macb->phy_addr = phy_addr;
+ }
+
macb->regs = (void *)pdata->iobase;
macb->is_big_endian = (cpu_to_be32(0x12345678) == 0x12345678);
--
2.17.1
[PATCH v1 4/8] riscv: Add DMA 64-bit address support
From: Padmarao Begari dma_addr_t holds any valid DMA address. If the DMA API only uses 32/64-bit addresses, dma_addr_t need only be 32/64 bits wide. Signed-off-by: Padmarao Begari --- arch/riscv/Kconfig | 5 + arch/riscv/include/asm/types.h | 4 2 files changed, 9 insertions(+) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index aaa3b833a5..7ab1ccff40 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -152,6 +152,11 @@ config 32BIT config 64BIT bool +config DMA_ADDR_T_64BIT + bool + depends on 64BIT + default n + config SIFIVE_CLINT bool depends on RISCV_MMODE || SPL_RISCV_MMODE diff --git a/arch/riscv/include/asm/types.h b/arch/riscv/include/asm/types.h index 403cf9a48f..b800b2d221 100644 --- a/arch/riscv/include/asm/types.h +++ b/arch/riscv/include/asm/types.h @@ -29,7 +29,11 @@ typedef unsigned short umode_t; #include +#ifdef CONFIG_DMA_ADDR_T_64BIT +typedef u64 dma_addr_t; +#else typedef u32 dma_addr_t; +#endif typedef unsigned long phys_addr_t; typedef unsigned long phys_size_t; -- 2.17.1
[PATCH v1 5/8] net: macb: Add DMA 64-bit address support for macb
From: Padmarao Begari
Enable 64-bit DMA support in the macb driver when CONFIG_DMA_ADDR_T_64BIT
is enabled. 32-bit DMA is enabled by default.
Signed-off-by: Padmarao Begari
---
drivers/net/macb.c | 42 +++---
drivers/net/macb.h | 6 ++
2 files changed, 41 insertions(+), 7 deletions(-)
diff --git a/drivers/net/macb.c b/drivers/net/macb.c
index b80a259ff7..e06d85d849 100644
--- a/drivers/net/macb.c
+++ b/drivers/net/macb.c
@@ -81,6 +81,10 @@ DECLARE_GLOBAL_DATA_PTR;
struct macb_dma_desc {
u32 addr;
u32 ctrl;
+#ifdef CONFIG_DMA_ADDR_T_64BIT
+ u32 addrh;
+ u32 unused;
+#endif
};
#define DMA_DESC_BYTES(n) (n * sizeof(struct macb_dma_desc))
@@ -327,6 +331,9 @@ static int _macb_send(struct macb_device *macb, const char
*name, void *packet,
macb->tx_ring[tx_head].ctrl = ctrl;
macb->tx_ring[tx_head].addr = paddr;
+#ifdef CONFIG_DMA_ADDR_T_64BIT
+ macb->tx_ring[tx_head].addrh = upper_32_bits((dma_addr_t)packet);
+#endif
barrier();
macb_flush_ring_desc(macb, TX);
macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE) | MACB_BIT(TSTART));
@@ -732,9 +739,18 @@ static int gmac_init_multi_queues(struct macb_device *macb)
flush_dcache_range(macb->dummy_desc_dma, macb->dummy_desc_dma +
ALIGN(MACB_TX_DUMMY_DMA_DESC_SIZE, PKTALIGN));
- for (i = 1; i < num_queues; i++)
+ for (i = 1; i < num_queues; i++) {
gem_writel_queue_TBQP(macb, macb->dummy_desc_dma, i - 1);
-
+#ifdef CONFIG_DMA_ADDR_T_64BIT
+ gem_writel_queue_TBQPH(macb,
+ upper_32_bits(macb->dummy_desc_dma), i - 1);
+#endif
+ gem_writel_queue_RBQP(macb, macb->dummy_desc_dma, i - 1);
+#ifdef CONFIG_DMA_ADDR_T_64BIT
+ gem_writel_queue_RBQPH(macb,
+ upper_32_bits(macb->dummy_desc_dma), i - 1);
+#endif
+ }
return 0;
}
@@ -760,6 +776,9 @@ static void gmac_configure_dma(struct macb_device *macb)
dmacfg &= ~GEM_BIT(ENDIA_DESC);
dmacfg &= ~GEM_BIT(ADDR64);
+#ifdef CONFIG_DMA_ADDR_T_64BIT
+ dmacfg |= GEM_BIT(ADDR64);
+#endif
gem_writel(macb, DMACFG, dmacfg);
}
@@ -772,7 +791,7 @@ static int _macb_init(struct macb_device *macb, const char
*name)
#ifdef CONFIG_DM_ETH
struct macb_device *macb = dev_get_priv(dev);
#endif
- unsigned long paddr;
+ dma_addr_t paddr;
int ret;
int i;
@@ -786,8 +805,11 @@ static int _macb_init(struct macb_device *macb, const char
*name)
for (i = 0; i < MACB_RX_RING_SIZE; i++) {
if (i == (MACB_RX_RING_SIZE - 1))
paddr |= MACB_BIT(RX_WRAP);
- macb->rx_ring[i].addr = paddr;
+ macb->rx_ring[i].addr = lower_32_bits(paddr);
macb->rx_ring[i].ctrl = 0;
+#ifdef CONFIG_DMA_ADDR_T_64BIT
+ macb->rx_ring[i].addrh = upper_32_bits(paddr);
+#endif
paddr += macb->rx_buffer_size;
}
macb_flush_ring_desc(macb, RX);
@@ -800,6 +822,9 @@ static int _macb_init(struct macb_device *macb, const char
*name)
MACB_BIT(TX_WRAP);
else
macb->tx_ring[i].ctrl = MACB_BIT(TX_USED);
+#ifdef CONFIG_DMA_ADDR_T_64BIT
+ macb->tx_ring[i].addrh = 0x0;
+#endif
}
macb_flush_ring_desc(macb, TX);
@@ -812,9 +837,12 @@ static int _macb_init(struct macb_device *macb, const char
*name)
gem_writel(macb, DMACFG, MACB_ZYNQ_GEM_DMACR_INIT);
#endif
- macb_writel(macb, RBQP, macb->rx_ring_dma);
- macb_writel(macb, TBQP, macb->tx_ring_dma);
-
+ macb_writel(macb, RBQP, lower_32_bits(macb->rx_ring_dma));
+ macb_writel(macb, TBQP, lower_32_bits(macb->tx_ring_dma));
+#ifdef CONFIG_DMA_ADDR_T_64BIT
+ macb_writel(macb, RBQPH, upper_32_bits(macb->rx_ring_dma));
+ macb_writel(macb, TBQPH, upper_32_bits(macb->tx_ring_dma));
+#endif
if (macb_is_gem(macb)) {
/* Initialize DMA properties */
gmac_configure_dma(macb);
diff --git a/drivers/net/macb.h b/drivers/net/macb.h
index 9b16383eba..72b84ae96e 100644
--- a/drivers/net/macb.h
+++ b/drivers/net/macb.h
@@ -768,5 +768,11 @@
#define GEM_RX_CSUM_CHECKED_MASK 2
#define gem_writel_queue_TBQP(port, value, queue_num) \
writel((value), (port)->regs + GEM_TBQP(queue_num))
+#define gem_writel_queue_TBQPH(port, value, queue_num) \
+ writel((value), (port)->regs + GEM_TBQPH(queue_num))
+#define gem_writel_queue_RBQP(port, value, queue_num) \
+ writel((value), (port)->regs + GEM_RBQP(queue_num))
+#define gem_writel_queue_RBQPH(port, value, queue_num) \
+ writel((value), (port)->regs + GEM_RBQPH(queue_num))
#endif /* __DRIVERS_MACB_H__ */
--
2.17.1
[PATCH v1 3/8] dt-bindings: clock: Add indexes for reset signals
From: Padmarao Begari Add indexes for reset and clock control signals within the system register module of the Microchip PolarFire SoC. Signed-off-by: Padmarao Begari --- .../dt-bindings/clock/microchip,pfsoc-clock.h | 45 +++ 1 file changed, 45 insertions(+) create mode 100644 include/dt-bindings/clock/microchip,pfsoc-clock.h diff --git a/include/dt-bindings/clock/microchip,pfsoc-clock.h b/include/dt-bindings/clock/microchip,pfsoc-clock.h new file mode 100644 index 00..527cff1a28 --- /dev/null +++ b/include/dt-bindings/clock/microchip,pfsoc-clock.h @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2020 Microchip Technology Inc. + * Padmarao Begari + */ + +#ifndef _DT_BINDINGS_CLK_MICROCHIP_PFSOC_H_ +#define _DT_BINDINGS_CLK_MICROCHIP_PFSOC_H_ + +#define CLK_CPU0 +#define CLK_AXI1 +#define CLK_AHB2 + +#define CLK_ENVM 3 +#define CLK_MAC0 4 +#define CLK_MAC1 5 +#define CLK_MMC6 +#define CLK_TIMER 7 +#define CLK_MMUART08 +#define CLK_MMUART19 +#define CLK_MMUART210 +#define CLK_MMUART311 +#define CLK_MMUART412 +#define CLK_SPI0 13 +#define CLK_SPI1 14 +#define CLK_I2C0 15 +#define CLK_I2C1 16 +#define CLK_CAN0 17 +#define CLK_CAN1 18 +#define CLK_USB19 +#define CLK_RESERVED 20 +#define CLK_RTC21 +#define CLK_QSPI 22 +#define CLK_GPIO0 23 +#define CLK_GPIO1 24 +#define CLK_GPIO2 25 +#define CLK_DDRC 26 +#define CLK_FIC0 27 +#define CLK_FIC1 28 +#define CLK_FIC2 29 +#define CLK_FIC3 30 +#define CLK_ATHENA 31 +#define CLK_CFM32 + +#endif /* _DT_BINDINGS_CLK_MICROCHIP_PFSOC_H_ */ -- 2.17.1
[PATCH v1 2/8] riscv: dts: Add device tree for Microchip Icicle Kit
From: Padmarao Begari
Add device tree for Microchip PolarFire SoC Icicle Kit.
Signed-off-by: Padmarao Begari
---
arch/riscv/dts/Makefile | 1 +
arch/riscv/dts/microchip-icicle-kit-a000.dts | 419 +++
2 files changed, 420 insertions(+)
create mode 100644 arch/riscv/dts/microchip-icicle-kit-a000.dts
diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile
index 3a6f96c67d..48c43bd122 100644
--- a/arch/riscv/dts/Makefile
+++ b/arch/riscv/dts/Makefile
@@ -3,6 +3,7 @@
dtb-$(CONFIG_TARGET_AX25_AE350) += ae350_32.dtb ae350_64.dtb
dtb-$(CONFIG_TARGET_SIFIVE_FU540) += hifive-unleashed-a00.dtb
dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb
+dtb-$(CONFIG_TARGET_MICROCHIP_ICICLE) += microchip-icicle-kit-a000.dtb
targets += $(dtb-y)
diff --git a/arch/riscv/dts/microchip-icicle-kit-a000.dts
b/arch/riscv/dts/microchip-icicle-kit-a000.dts
new file mode 100644
index 00..e7f0ec6926
--- /dev/null
+++ b/arch/riscv/dts/microchip-icicle-kit-a000.dts
@@ -0,0 +1,419 @@
+// SPDX-License-Identifier: GPL-2.0+
+/* Copyright (c) 2020 Microchip Technology Inc */
+
+/dts-v1/;
+#include "dt-bindings/clock/microchip,pfsoc-clock.h"
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ model = "Microchip PolarFire-SoC";
+ compatible = "microchip,polarfire-soc";
+
+ aliases {
+ serial0 =
+ ethernet0 =
+ };
+
+ chosen {
+ stdout-path = "serial0";
+ };
+
+ cpucomplex: cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ timebase-frequency = <100>;
+ cpu0: cpu@0 {
+ clocks = < CLK_CPU>;
+ compatible = "sifive,e51", "sifive,rocket0", "riscv";
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-cache-sets = <128>;
+ i-cache-size = <16384>;
+ reg = <0>;
+ riscv,isa = "rv64imac";
+ status = "disabled";
+ operating-points = <
+ /* kHz uV */
+ 60 110
+ 30 95
+ 15 75
+ >;
+ cpu0intc: interrupt-controller {
+ #interrupt-cells = <1>;
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ };
+ };
+ cpu1: cpu@1 {
+ clocks = < CLK_CPU>;
+ compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
+ d-cache-block-size = <64>;
+ d-cache-sets = <64>;
+ d-cache-size = <32768>;
+ d-tlb-sets = <1>;
+ d-tlb-size = <32>;
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-cache-sets = <64>;
+ i-cache-size = <32768>;
+ i-tlb-sets = <1>;
+ i-tlb-size = <32>;
+ mmu-type = "riscv,sv39";
+ reg = <1>;
+ riscv,isa = "rv64imafdc";
+ tlb-split;
+ status = "okay";
+ operating-points = <
+ /* kHz uV */
+ 60 110
+ 30 95
+ 15 75
+ >;
+ cpu1intc: interrupt-controller {
+ #interrupt-cells = <1>;
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ };
+ };
+ cpu2: cpu@2 {
+ clocks = < CLK_CPU>;
+ compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
+ d-cache-block-size = <64>;
+ d-cache-sets = <64>;
+ d-cache-size = <32768>;
+ d-tlb-sets = <1>;
+ d-tlb-size = <32>;
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-cache-sets = <64>;
+ i-cache-size = <32768>;
+ i-tlb-sets = <1>;
+ i-tlb-size = <32>;
+ mmu-type = "riscv,sv39";
+ reg = <2>;
+ riscv,isa = "rv64imafdc";
+ tlb-split;
+ status = "okay";
+ operating-points = <
+
[PATCH v1 0/8] Microchip PolarFire SoC support
From: Padmarao Begari This patch set adds Microchip PolarFire SoC Icicle Kit support to RISC-V U-Boot. The patches are based upon latest U-Boot tree (https://gitlab.denx.de/u-boot/u-boot.git) at commit id 9dc6aef8c963ae17e1263b89c692792fce0c7198 All drivers namely: NS16550 Serial, Microchip clock, Cadence eMMC and Cadence MACB Ethernet work fine on actual Microchip PolarFire SoC Icicle Kit. Padmarao Begari (8): riscv: Add Microchip MPFS Icicle Kit support riscv: dts: Add device tree for Microchip Icicle Kit dt-bindings: clock: Add indexes for reset signals riscv: Add DMA 64-bit address support net: macb: Add DMA 64-bit address support for macb net: macb: Add phy address to read it from device tree clk: Add Microchip PolarFire SoC clock driver doc: board: Add Microchip MPFS Icicle Kit doc arch/riscv/Kconfig| 5 + arch/riscv/dts/Makefile | 1 + arch/riscv/dts/microchip-icicle-kit-a000.dts | 419 arch/riscv/include/asm/types.h| 4 + board/microchip/mpfs_icicle/Kconfig | 26 + board/microchip/mpfs_icicle/mpfs_icicle.c | 96 ++- configs/microchip_mpfs_icicle_defconfig | 9 +- doc/board/index.rst | 1 + doc/board/microchip/index.rst | 9 + doc/board/microchip/mpfs_icicle.rst | 605 ++ drivers/clk/Kconfig | 1 + drivers/clk/Makefile | 1 + drivers/clk/microchip/Kconfig | 5 + drivers/clk/microchip/Makefile| 1 + drivers/clk/microchip/clk_pfsoc.c | 120 drivers/clk/microchip/clk_pfsoc.h | 19 + drivers/clk/microchip/clk_pfsoc_cfg.c | 135 drivers/clk/microchip/clk_pfsoc_periph.c | 171 + drivers/net/macb.c| 57 +- drivers/net/macb.h| 6 + include/configs/microchip_mpfs_icicle.h | 60 +- .../dt-bindings/clock/microchip,pfsoc-clock.h | 45 ++ 22 files changed, 1744 insertions(+), 52 deletions(-) create mode 100644 arch/riscv/dts/microchip-icicle-kit-a000.dts create mode 100644 doc/board/microchip/index.rst create mode 100644 doc/board/microchip/mpfs_icicle.rst create mode 100644 drivers/clk/microchip/Kconfig create mode 100644 drivers/clk/microchip/Makefile create mode 100644 drivers/clk/microchip/clk_pfsoc.c create mode 100644 drivers/clk/microchip/clk_pfsoc.h create mode 100644 drivers/clk/microchip/clk_pfsoc_cfg.c create mode 100644 drivers/clk/microchip/clk_pfsoc_periph.c create mode 100644 include/dt-bindings/clock/microchip,pfsoc-clock.h -- 2.17.1
[PATCH v1 1/8] riscv: Add Microchip MPFS Icicle Kit support
From: Padmarao Begari
This patch adds Microchip MPFS Icicle Kit support. For now, only
NS16550 Serial, Microchip clock, Cadence eMMC and MACB drivers are
only enabled. The Microchip MPFS Icicle defconfig by default builds
U-Boot for S-Mode because U-Boot on Microchip PolarFire SoC will run
in S-Mode as payload of HSS + OpenSBI.
Signed-off-by: Padmarao Begari
---
board/microchip/mpfs_icicle/Kconfig | 26 ++
board/microchip/mpfs_icicle/mpfs_icicle.c | 96 ++-
configs/microchip_mpfs_icicle_defconfig | 9 ++-
include/configs/microchip_mpfs_icicle.h | 60 +-
4 files changed, 146 insertions(+), 45 deletions(-)
diff --git a/board/microchip/mpfs_icicle/Kconfig
b/board/microchip/mpfs_icicle/Kconfig
index bf8e1a13ec..4406d1a13f 100644
--- a/board/microchip/mpfs_icicle/Kconfig
+++ b/board/microchip/mpfs_icicle/Kconfig
@@ -20,7 +20,33 @@ config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select GENERIC_RISCV
select BOARD_EARLY_INIT_F
+ select BOARD_LATE_INIT
imply SMP
+ imply CLK
+ imply CLK_CCF
+ imply CLK_MPFS
imply SYS_NS16550
+ imply CMD_DHCP
+ imply CMD_EXT2
+ imply CMD_EXT4
+ imply CMD_FAT
+ imply CMD_FS_GENERIC
+ imply CMD_NET
+ imply CMD_PING
+ imply CMD_MMC
+ imply DOS_PARTITION
+ imply EFI_PARTITION
+ imply IP_DYN
+ imply ISO_PARTITION
+ imply MACB
+ imply MII
+ imply NET_RANDOM_ETHADDR
+ imply PHY_LIB
+ imply PHY_VITESSE
+ imply DMA_ADDR_T_64BIT
+ imply MMC
+ imply MMC_WRITE
+ imply MMC_SDHCI
+ imply MMC_SDHCI_CADENCE
endif
diff --git a/board/microchip/mpfs_icicle/mpfs_icicle.c
b/board/microchip/mpfs_icicle/mpfs_icicle.c
index 8381361ec3..64133aee59 100644
--- a/board/microchip/mpfs_icicle/mpfs_icicle.c
+++ b/board/microchip/mpfs_icicle/mpfs_icicle.c
@@ -5,11 +5,47 @@
*/
#include
+#include
#include
#include
#include
-#define MPFS_SYSREG_SOFT_RESET ((unsigned int *)0x20002088)
+#define MPFS_SYSREG_SOFT_RESET ((unsigned int *)0x20002088)
+#define MPFS_SYS_SERVICE_CR((unsigned int *)0x37020050)
+#define MPFS_SYS_SERVICE_SR((unsigned int *)0x37020054)
+#define MPFS_SYS_SERVICE_MAILBOX ((unsigned char *)0x37020800)
+
+#define PERIPH_RESET_VALUE 0x1e8u
+#define SERVICE_CR_REQ 0x1u
+#define SERVICE_SR_BUSY0x2u
+
+static void read_device_serial_number(u8 *response, u8 response_size)
+{
+ u8 idx;
+ u8 *response_buf;
+ unsigned int val;
+
+ response_buf = (u8 *)response;
+
+ writel(SERVICE_CR_REQ, MPFS_SYS_SERVICE_CR);
+
+ /* REQ bit will remain set till the system controller starts
+* processing.
+*/
+ do {
+ val = readl(MPFS_SYS_SERVICE_CR);
+ } while (SERVICE_CR_REQ == (val & SERVICE_CR_REQ));
+
+ /* Once system controller starts processing the busy bit will
+* go high and service is completed when busy bit is gone low
+*/
+ do {
+ val = readl(MPFS_SYS_SERVICE_SR);
+ } while (SERVICE_SR_BUSY == (val & SERVICE_SR_BUSY));
+
+ for (idx = 0; idx < response_size; idx++)
+ response_buf[idx] = readb(MPFS_SYS_SERVICE_MAILBOX + idx);
+}
int board_init(void)
{
@@ -22,10 +58,64 @@ int board_early_init_f(void)
{
unsigned int val;
- /* Reset uart peripheral */
+ /* Reset uart, mmc peripheral */
val = readl(MPFS_SYSREG_SOFT_RESET);
- val = (val & ~(1u << 5u));
+ val = (val & ~(PERIPH_RESET_VALUE));
writel(val, MPFS_SYSREG_SOFT_RESET);
return 0;
}
+
+int board_late_init(void)
+{
+ u32 ret;
+ u32 node;
+ u8 idx;
+ u8 device_serial_number[16] = { 0 };
+ unsigned char mac_addr[6];
+ char icicle_mac_addr[20];
+ void *blob = (void *)gd->fdt_blob;
+
+ node = fdt_path_offset(blob, "ethernet0");
+ if (node < 0) {
+ printf("No ethernet0 path offset\n");
+ return -ENODEV;
+ }
+
+ ret = fdtdec_get_byte_array(blob, node, "mac-address", mac_addr, 6);
+ if (ret) {
+ printf("No mac-address property\n");
+ return -EINVAL;
+ }
+
+ read_device_serial_number(device_serial_number, 16);
+
+ /* Update MAC address with device serial number */
+ mac_addr[0] = 0x00;
+ mac_addr[1] = 0x04;
+ mac_addr[2] = 0xA3;
+ mac_addr[3] = device_serial_number[2];
+ mac_addr[4] = device_serial_number[1];
+ mac_addr[5] = device_serial_number[0];
+
+ ret = fdt_setprop(blob, node, "mac-address", mac_addr, 6);
+ if (ret) {
+ printf("Error setting mac-address property\n");
+ return -ENODEV;
+ }
+
+ icicle_mac_addr[0] = '[';
+
+ sprintf(_mac_addr[1], "%pM", mac_addr);
+
+
[PATCH] tools: mtk_image: add support for booting ARM64 images
mkimage is only able to package aarch32 binaries. Add support for
AArch64 images.
One can create a ARM64 image using the following command line:
mkimage -T mtk_image -a 0x201000 -e 0x201000 -n "media=emmc;arm64=1"
-d bl2.bin bl2.img
Signed-off-by: Fabien Parent
---
tools/mtk_image.c | 28
tools/mtk_image.h | 6 +-
2 files changed, 29 insertions(+), 5 deletions(-)
diff --git a/tools/mtk_image.c b/tools/mtk_image.c
index 2ca519483d33..bde1e5da4bec 100644
--- a/tools/mtk_image.c
+++ b/tools/mtk_image.c
@@ -246,6 +246,7 @@ static const struct brom_img_type {
/* Image type selected by user */
static enum brlyt_img_type hdr_media;
static int use_lk_hdr;
+static bool is_arm64_image;
/* LK image name */
static char lk_name[32] = "U-Boot";
@@ -276,6 +277,7 @@ static int mtk_brom_parse_imagename(const char *imagename)
static const char *media = "";
static const char *nandinfo = "";
static const char *lk = "";
+ static const char *arm64_param = "";
key = buf;
while (key) {
@@ -323,6 +325,9 @@ static int mtk_brom_parse_imagename(const char *imagename)
if (!strcmp(key, "lkname"))
snprintf(lk_name, sizeof(lk_name), "%s", val);
+
+ if (!strcmp(key, "arm64"))
+ arm64_param = val;
}
if (next)
@@ -354,6 +359,9 @@ static int mtk_brom_parse_imagename(const char *imagename)
}
}
+ if (arm64_param && arm64_param[0] == '1')
+ is_arm64_image = true;
+
free(buf);
if (hdr_media == BRLYT_TYPE_INVALID) {
@@ -458,6 +466,9 @@ static int mtk_image_verify_gen_header(const uint8_t *ptr,
int print)
le32_to_cpu(gfh->file_info.load_addr) +
le32_to_cpu(gfh->file_info.jump_offset));
+ if (print)
+ printf("Architecture: %s\n", is_arm64_image ? "ARM64" : "ARM");
+
return 0;
}
@@ -523,6 +534,9 @@ static int mtk_image_verify_nand_header(const uint8_t *ptr,
int print)
le32_to_cpu(gfh->file_info.load_addr) +
le32_to_cpu(gfh->file_info.jump_offset));
+ if (print)
+ printf("Architecture: %s\n", is_arm64_image ? "ARM64" : "ARM");
+
return 0;
}
@@ -581,6 +595,8 @@ static void put_ghf_common_header(struct gfh_common_header
*gfh, int size,
static void put_ghf_header(struct gfh_header *gfh, int file_size,
int dev_hdr_size, int load_addr, int flash_type)
{
+ uint32_t cfg_bits;
+
memset(gfh, 0, sizeof(struct gfh_header));
/* GFH_FILE_INFO header */
@@ -608,11 +624,15 @@ static void put_ghf_header(struct gfh_header *gfh, int
file_size,
/* GFH_BROM_CFG header */
put_ghf_common_header(>brom_cfg.gfh, sizeof(gfh->brom_cfg),
GFH_TYPE_BROM_CFG, 3);
- gfh->brom_cfg.cfg_bits = cpu_to_le32(
- GFH_BROM_CFG_USBDL_AUTO_DETECT_DIS |
- GFH_BROM_CFG_USBDL_BY_KCOL0_TIMEOUT_EN |
- GFH_BROM_CFG_USBDL_BY_FLAG_TIMEOUT_EN);
+ cfg_bits = GFH_BROM_CFG_USBDL_AUTO_DETECT_DIS |
+ GFH_BROM_CFG_USBDL_BY_KCOL0_TIMEOUT_EN |
+ GFH_BROM_CFG_USBDL_BY_FLAG_TIMEOUT_EN;
gfh->brom_cfg.usbdl_by_kcol0_timeout_ms = cpu_to_le32(5000);
+ if (is_arm64_image) {
+ gfh->brom_cfg.jump_bl_arm64 = GFH_BROM_CFG_JUMP_BL_ARM64;
+ cfg_bits |= GFH_BROM_CFG_JUMP_BL_ARM64_EN;
+ }
+ gfh->brom_cfg.cfg_bits = cpu_to_le32(cfg_bits);
/* GFH_BL_SEC_KEY header */
put_ghf_common_header(>bl_sec_key.gfh, sizeof(gfh->bl_sec_key),
diff --git a/tools/mtk_image.h b/tools/mtk_image.h
index 4e78b3d0ff0b..7dda71ce88a5 100644
--- a/tools/mtk_image.h
+++ b/tools/mtk_image.h
@@ -136,7 +136,9 @@ struct gfh_brom_cfg {
struct gfh_common_header gfh;
uint32_t cfg_bits;
uint32_t usbdl_by_auto_detect_timeout_ms;
- uint8_t unused[0x48];
+ uint8_t unused[0x45];
+ uint8_t jump_bl_arm64;
+ uint8_t unused2[2];
uint32_t usbdl_by_kcol0_timeout_ms;
uint32_t usbdl_by_flag_timeout_ms;
uint32_t pad;
@@ -146,6 +148,8 @@ struct gfh_brom_cfg {
#define GFH_BROM_CFG_USBDL_AUTO_DETECT_DIS 0x10
#define GFH_BROM_CFG_USBDL_BY_KCOL0_TIMEOUT_EN 0x80
#define GFH_BROM_CFG_USBDL_BY_FLAG_TIMEOUT_EN 0x100
+#define GFH_BROM_CFG_JUMP_BL_ARM64_EN 0x1000
+#define GFH_BROM_CFG_JUMP_BL_ARM64 0x64
struct gfh_bl_sec_key {
struct gfh_common_header gfh;
--
2.28.0
[PATCH v3] armv8: layerscape: don't remove crypto node if just partially disabled
On all newer Layerscape SoCs, only the export-controlled ciphers of the
crypto module are disabled on non-E parts. Thus it doesn't make sense to
completely remove the node. Linux will figure out what is there and what
is not.
Just remove it for older SoCs, where the module is indeed completely
disabled on non-E parts.
Signed-off-by: Michael Walle
---
Changes since v2:
- clearified "partially disabled"
- fixed typos
- added LS2080A to the "completely disabled list"
Changes since v1:
- properly filter on SoC. Thanks to Horia's mail. See
https://patchwork.ozlabs.org/project/uboot/patch/20200602150904.1997-1-mich...@walle.cc/#2457448
arch/arm/cpu/armv8/fsl-layerscape/fdt.c | 41 -
1 file changed, 40 insertions(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
index 7400b2cf29..6d3391db3b 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
@@ -437,13 +437,52 @@ __weak void fdt_fixup_ecam(void *blob)
}
#endif
+/*
+ * If it is a non-E part the crypto is disabled on the following SoCs:
+ * - LS1043A
+ * - LS1088A
+ * - LS2080A
+ * - LS2088A
+ * and their personalities.
+ *
+ * On all other SoCs just the export-controlled ciphers are disabled, that
+ * means that the following is still working:
+ * - hashing (using MDHA - message digest hash accelerator)
+ * - random number generation (using RNG4)
+ * - cyclic redundancy checking (using CRCA)
+ * - runtime integrity checker (RTIC)
+ *
+ * The linux driver will figure out what is available and what is not.
+ * Therefore, we just remove the crypto node on the SoCs which have no crypto
+ * support at all.
+ */
+static bool crypto_is_disabled(unsigned int svr)
+{
+ if (IS_E_PROCESSOR(svr))
+ return false;
+
+ if (IS_SVR_DEV(svr, SVR_DEV(SVR_LS1043A)))
+ return true;
+
+ if (IS_SVR_DEV(svr, SVR_DEV(SVR_LS1088A)))
+ return true;
+
+ if (IS_SVR_DEV(svr, SVR_DEV(SVR_LS2080A)))
+ return true;
+
+ if (IS_SVR_DEV(svr, SVR_DEV(SVR_LS2088A)))
+ return true;
+
+ return false;
+}
+
void ft_cpu_setup(void *blob, struct bd_info *bd)
{
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
unsigned int svr = gur_in32(>svr);
/* delete crypto node if not on an E-processor */
- if (!IS_E_PROCESSOR(svr))
+ if (crypto_is_disabled(svr))
fdt_fixup_crypto_node(blob, 0);
#if CONFIG_SYS_FSL_SEC_COMPAT >= 4
else {
--
2.20.1
[PATCH v2 4/5] sunxi: video: v3s: Enable LCD support
Enable support for V3s LCD display with following changes:
V3s has 2x VI and 1x UI channels (use UI channel).
V3s uses PLL3 (PLL_VIDEO) for both DE2 and TCON0 pixelclock.
V3s does not support doubleclock for PLL3.
V3s supports resolution upto 1024x1024.
V3s does not support HDMI.
Signed-off-by: Martin Cerveny
---
arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 5 ++--
arch/arm/include/asm/arch-sunxi/gpio.h| 1 +
arch/arm/mach-sunxi/Kconfig | 1 +
drivers/video/sunxi/lcdc.c| 5 ++--
drivers/video/sunxi/sunxi_de2.c | 25 ---
drivers/video/sunxi/sunxi_dw_hdmi.c | 2 ++
drivers/video/sunxi/sunxi_lcd.c | 9 ++-
7 files changed, 40 insertions(+), 8 deletions(-)
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
index ee387127f3..9efe05d103 100644
--- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
@@ -329,7 +329,7 @@ struct sunxi_ccm_reg {
#define AHB_GATE_OFFSET_DE 12
#define AHB_GATE_OFFSET_HDMI 11
#define AHB_GATE_OFFSET_TVE9
-#ifndef CONFIG_SUNXI_DE2
+#if !defined(CONFIG_SUNXI_DE2) || defined(CONFIG_MACH_SUN8I_V3S)
#define AHB_GATE_OFFSET_LCD1 5
#define AHB_GATE_OFFSET_LCD0 4
#else
@@ -476,7 +476,7 @@ struct sunxi_ccm_reg {
#define AHB_RESET_OFFSET_HDMI 11
#define AHB_RESET_OFFSET_HDMI2 10
#define AHB_RESET_OFFSET_TVE 9
-#ifndef CONFIG_SUNXI_DE2
+#if !defined(CONFIG_SUNXI_DE2) || defined(CONFIG_MACH_SUN8I_V3S)
#define AHB_RESET_OFFSET_LCD1 5
#define AHB_RESET_OFFSET_LCD0 4
#else
@@ -510,6 +510,7 @@ struct sunxi_ccm_reg {
#define CCM_DE2_CTRL_PLL_MASK (3 << 24)
#define CCM_DE2_CTRL_PLL6_2X (0 << 24)
#define CCM_DE2_CTRL_PLL10 (1 << 24)
+#define CCM_DE2_CTRL_PLL3_V3S (0 << 24)
#define CCM_DE2_CTRL_GATE (0x1 << 31)
/* CCU security switch, H3 only */
diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h
b/arch/arm/include/asm/arch-sunxi/gpio.h
index d83dfdf605..9b580fbe26 100644
--- a/arch/arm/include/asm/arch-sunxi/gpio.h
+++ b/arch/arm/include/asm/arch-sunxi/gpio.h
@@ -181,6 +181,7 @@ enum sunxi_gpio_number {
#define SUN5I_GPE_SDC2 3
#define SUN8I_GPE_TWI2 3
#define SUN50I_GPE_TWI23
+#define SUN8I_V3S_GPE_LCD0 3
#define SUNXI_GPF_SDC0 2
#define SUNXI_GPF_UART04
diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
index be0822bfb7..dc0ee2cdef 100644
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -258,6 +258,7 @@ config MACH_SUN8I_V3S
select CPU_V7_HAS_NONSEC
select CPU_V7_HAS_VIRT
select ARCH_SUPPORT_PSCI
+ select SUNXI_DE2
select SUNXI_GEN_SUN6I
select SUNXI_DRAM_DW
select SUNXI_DRAM_DW_16BIT
diff --git a/drivers/video/sunxi/lcdc.c b/drivers/video/sunxi/lcdc.c
index 73033c3b85..3d50f9d567 100644
--- a/drivers/video/sunxi/lcdc.c
+++ b/drivers/video/sunxi/lcdc.c
@@ -244,7 +244,7 @@ void lcdc_pll_set(struct sunxi_ccm_reg *ccm, int tcon, int
dotclock,
* not sync to higher frequencies.
*/
for (m = min_m; m <= max_m; m++) {
-#ifndef CONFIG_SUNXI_DE2
+#if !defined(CONFIG_SUNXI_DE2) || defined(CONFIG_MACH_SUN8I_V3S)
n = (m * dotclock) / step;
if ((n >= 9) && (n <= 127)) {
@@ -262,7 +262,7 @@ void lcdc_pll_set(struct sunxi_ccm_reg *ccm, int tcon, int
dotclock,
if (!(m & 1))
continue;
#endif
-
+#ifndef CONFIG_MACH_SUN8I_V3S
/* No double clock on DE2 */
n = (m * dotclock) / (step * 2);
if ((n >= 9) && (n <= 127)) {
@@ -275,6 +275,7 @@ void lcdc_pll_set(struct sunxi_ccm_reg *ccm, int tcon, int
dotclock,
best_double = 1;
}
}
+#endif
}
#ifdef CONFIG_MACH_SUN6I
diff --git a/drivers/video/sunxi/sunxi_de2.c b/drivers/video/sunxi/sunxi_de2.c
index b657e163f0..49d41eb243 100644
--- a/drivers/video/sunxi/sunxi_de2.c
+++ b/drivers/video/sunxi/sunxi_de2.c
@@ -26,12 +26,21 @@
DECLARE_GLOBAL_DATA_PTR;
+#ifdef CONFIG_MACH_SUN8I_V3S
+enum {
+ /* Maximum LCD size we support */
+ LCD_MAX_WIDTH = 1024,
+ LCD_MAX_HEIGHT = 1024,
+ LCD_MAX_LOG2_BPP= VIDEO_BPP32,
+};
+#else
enum {
/* Maximum LCD size we support */
LCD_MAX_WIDTH = 3840,
LCD_MAX_HEIGHT = 2160,
LCD_MAX_LOG2_BPP= VIDEO_BPP32,
};
+#endif
static void sunxi_de2_composer_init(void)
{
@@ -47,11 +56,19 @@ static void sunxi_de2_composer_init(void)
writel(reg_value, SUNXI_SRAMC_BASE + 0x04);
#endif
+#ifdef CONFIG_MACH_SUN8I_V3S
+ clock_set_pll3(5000);
+ /* pll3 is
[PATCH v2 2/5] ARM: dts: sun8i: v3s: Add simple-framebuffer
Add support for "allwinner,simple-framebuffer" with "mixer0-lcd0" pipeline.
Signed-off-by: Martin Cerveny
---
arch/arm/dts/sun8i-v3s.dtsi | 16
1 file changed, 16 insertions(+)
diff --git a/arch/arm/dts/sun8i-v3s.dtsi b/arch/arm/dts/sun8i-v3s.dtsi
index e5312869c0..b93dd69bf3 100644
--- a/arch/arm/dts/sun8i-v3s.dtsi
+++ b/arch/arm/dts/sun8i-v3s.dtsi
@@ -43,12 +43,28 @@
#include
#include
#include
+#include
/ {
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <>;
+ chosen {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ framebuffer-lcd {
+ compatible = "allwinner,simple-framebuffer",
+"simple-framebuffer";
+ allwinner,pipeline = "mixer0-lcd0";
+ clocks = <_clocks CLK_MIXER0>,
+< CLK_TCON0>;
+ status = "disabled";
+ };
+ };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
--
2.25.1
[PATCH v2 1/5] ARM: dts: sun8i: Update V3s dts(i) files from Linux-v5.9
Update all V3s devicetree dts and dtsi files from Linux-v5.9.
Signed-off-by: Martin Cerveny
---
arch/arm/dts/sun8i-v3s-licheepi-zero.dts | 26 ++-
arch/arm/dts/sun8i-v3s.dtsi | 200 ---
2 files changed, 196 insertions(+), 30 deletions(-)
diff --git a/arch/arm/dts/sun8i-v3s-licheepi-zero.dts
b/arch/arm/dts/sun8i-v3s-licheepi-zero.dts
index 3d9168cbae..2e4587d26c 100644
--- a/arch/arm/dts/sun8i-v3s-licheepi-zero.dts
+++ b/arch/arm/dts/sun8i-v3s-licheepi-zero.dts
@@ -55,11 +55,29 @@
chosen {
stdout-path = "serial0:115200n8";
};
+
+ leds {
+ compatible = "gpio-leds";
+
+ blue_led {
+ label = "licheepi:blue:usr";
+ gpios = < 6 1 GPIO_ACTIVE_LOW>; /* PG1 */
+ };
+
+ green_led {
+ label = "licheepi:green:usr";
+ gpios = < 6 0 GPIO_ACTIVE_LOW>; /* PG0 */
+ default-state = "on";
+ };
+
+ red_led {
+ label = "licheepi:red:usr";
+ gpios = < 6 2 GPIO_ACTIVE_LOW>; /* PG2 */
+ };
+ };
};
{
- pinctrl-0 = <_pins_a>;
- pinctrl-names = "default";
broken-cd;
bus-width = <4>;
vmmc-supply = <_vcc3v3>;
@@ -67,7 +85,7 @@
};
{
- pinctrl-0 = <_pins_a>;
+ pinctrl-0 = <_pb_pins>;
pinctrl-names = "default";
status = "okay";
};
@@ -78,6 +96,6 @@
};
{
- usb0_id_det-gpio = < 5 6 GPIO_ACTIVE_HIGH>;
+ usb0_id_det-gpios = < 5 6 GPIO_ACTIVE_HIGH>;
status = "okay";
};
diff --git a/arch/arm/dts/sun8i-v3s.dtsi b/arch/arm/dts/sun8i-v3s.dtsi
index ebefc0fefe..e5312869c0 100644
--- a/arch/arm/dts/sun8i-v3s.dtsi
+++ b/arch/arm/dts/sun8i-v3s.dtsi
@@ -40,10 +40,9 @@
* OTHER DEALINGS IN THE SOFTWARE.
*/
+#include
#include
#include
-#include
-#include
/ {
#address-cells = <1>;
@@ -62,6 +61,12 @@
};
};
+ de: display-engine {
+ compatible = "allwinner,sun8i-v3s-display-engine";
+ allwinner,pipelines = <>;
+ status = "disabled";
+ };
+
timer {
compatible = "arm,armv7-timer";
interrupts = ,
@@ -79,6 +84,7 @@
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <2400>;
+ clock-accuracy = <5>;
clock-output-names = "osc24M";
};
@@ -86,7 +92,8 @@
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <32768>;
- clock-output-names = "osc32k";
+ clock-accuracy = <5>;
+ clock-output-names = "ext-osc32k";
};
};
@@ -96,7 +103,77 @@
#size-cells = <1>;
ranges;
- mmc0: mmc@01c0f000 {
+ display_clocks: clock@100 {
+ compatible = "allwinner,sun8i-v3s-de2-clk";
+ reg = <0x0100 0x1>;
+ clocks = < CLK_BUS_DE>,
+< CLK_DE>;
+ clock-names = "bus",
+ "mod";
+ resets = < RST_BUS_DE>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ mixer0: mixer@110 {
+ compatible = "allwinner,sun8i-v3s-de2-mixer";
+ reg = <0x0110 0x10>;
+ clocks = <_clocks 0>,
+<_clocks 6>;
+ clock-names = "bus",
+ "mod";
+ resets = <_clocks 0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mixer0_out: port@1 {
+ reg = <1>;
+
+ mixer0_out_tcon0: endpoint {
+ remote-endpoint =
<_in_mixer0>;
+ };
+ };
+ };
+ };
+
+ tcon0: lcd-controller@1c0c000 {
+ compatible = "allwinner,sun8i-v3s-tcon";
+ reg = <0x01c0c000 0x1000>;
+ interrupts = ;
+ clocks = < CLK_BUS_TCON0>,
+< CLK_TCON0>;
+ clock-names = "ahb",
+ "tcon-ch0";
+ clock-output-names =
[PATCH v2 5/5] sunxi: add drivers and configs needed for LCD display
Add PWM and dummy power regulator support. Modify phase of data signal for LCD display. Signed-off-by: Martin Cerveny --- configs/LicheePi_Zero_defconfig | 4 1 file changed, 4 insertions(+) diff --git a/configs/LicheePi_Zero_defconfig b/configs/LicheePi_Zero_defconfig index 04d7b64504..ba1c085ec3 100644 --- a/configs/LicheePi_Zero_defconfig +++ b/configs/LicheePi_Zero_defconfig @@ -3,5 +3,9 @@ CONFIG_ARCH_SUNXI=y CONFIG_SPL=y CONFIG_MACH_SUN8I_V3S=y CONFIG_DRAM_CLK=360 +CONFIG_VIDEO_LCD_DCLK_PHASE=0 CONFIG_DEFAULT_DEVICE_TREE="sun8i-v3s-licheepi-zero" # CONFIG_NETDEVICES is not set +CONFIG_DM_REGULATOR=y +CONFIG_DM_PWM=y +CONFIG_PWM_SUNXI=y -- 2.25.1
[PATCH v2 0/5] sunxi: video: Add V3S simple-framebuffer
There are patches to enable "allwinner,simple-framebuffer" with "mixer0-lcd0" pipeline for V3s. First patch updates V3s dts(i) from Linux-v5.9. Second patch enable simple-framebuffer in V3s dtsi (planed merge in Linux-v5.11) Third patch enable PWM0 (for backlight support). Fourth patch is the main extension to code and build: - V3s has 2x VI and 1x UI channels (use UI channel), so use third channel. - V3s uses PLL3 (PLL_VIDEO) for both DE2 and TCON0 pixelclock. PLL10 is used for DDR2. PLL3 does not support doubleclock. - V3s supports resolution upto 1024x1024. Also scale down memory requirements for V3s (64MB embedded DDR2) - V3s does not support HDMI. Fifth patch enable PWM drivers and corrects CONFIG_VIDEO_LCD_DCLK_PHASE. Tested with "Lichee Zero" V3s and 800x600 LCD (not configured DRM DE2/TCON0/panel in linux DTS). To enable functionality see TESTING patch at - https://github.com/mcerveny/u-boot/tree/simplefb_v3s_v2 Changes since v1: - problematic patch for generic DE2 suppress of doubleclock search was redesigned for V3s only - changes dts(i) was synced from Linux-v5.9 and additional patch to enable simple-framebuffer Martin Cerveny (5): ARM: dts: sun8i: Update V3s dts(i) files from Linux-v5.9 ARM: dts: sun8i: v3s: Add simple-framebuffer pwm: sunxi: v3s: Enable PWM0 sunxi: video: v3s: Enable LCD support sunxi: add drivers and configs needed for LCD display arch/arm/dts/sun8i-v3s-licheepi-zero.dts | 26 ++- arch/arm/dts/sun8i-v3s.dtsi | 216 +++--- arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 5 +- arch/arm/include/asm/arch-sunxi/gpio.h| 2 + arch/arm/mach-sunxi/Kconfig | 1 + configs/LicheePi_Zero_defconfig | 4 + drivers/pwm/sunxi_pwm.c | 3 + drivers/video/sunxi/lcdc.c| 5 +- drivers/video/sunxi/sunxi_de2.c | 25 +- drivers/video/sunxi/sunxi_dw_hdmi.c | 2 + drivers/video/sunxi/sunxi_lcd.c | 9 +- 11 files changed, 260 insertions(+), 38 deletions(-) -- 2.25.1
[PATCH v2 3/5] pwm: sunxi: v3s: Enable PWM0
Enable PWM0 for V3S (for backlight LCD support).
Signed-off-by: Martin Cerveny
---
arch/arm/include/asm/arch-sunxi/gpio.h | 1 +
drivers/pwm/sunxi_pwm.c| 3 +++
2 files changed, 4 insertions(+)
diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h
b/arch/arm/include/asm/arch-sunxi/gpio.h
index a646ea6a3c..d83dfdf605 100644
--- a/arch/arm/include/asm/arch-sunxi/gpio.h
+++ b/arch/arm/include/asm/arch-sunxi/gpio.h
@@ -164,6 +164,7 @@ enum sunxi_gpio_number {
#define SUN8I_A33_GPB_UART03
#define SUN8I_A83T_GPB_UART0 2
#define SUN8I_V3S_GPB_UART03
+#define SUN8I_V3S_GPB_PWM0 2
#define SUN50I_GPB_UART0 4
#define SUNXI_GPC_NAND 2
diff --git a/drivers/pwm/sunxi_pwm.c b/drivers/pwm/sunxi_pwm.c
index e2ae1a8009..136e7c63d3 100644
--- a/drivers/pwm/sunxi_pwm.c
+++ b/drivers/pwm/sunxi_pwm.c
@@ -48,6 +48,8 @@ static int sunxi_pwm_config_pinmux(void)
{
#ifdef CONFIG_MACH_SUN50I
sunxi_gpio_set_cfgpin(SUNXI_GPD(22), SUNXI_GPD_PWM);
+#elif defined CONFIG_MACH_SUN8I_V3S
+ sunxi_gpio_set_cfgpin(SUNXI_GPB(4), SUN8I_V3S_GPB_PWM0);
#endif
return 0;
}
@@ -171,6 +173,7 @@ static const struct pwm_ops sunxi_pwm_ops = {
static const struct udevice_id sunxi_pwm_ids[] = {
{ .compatible = "allwinner,sun5i-a13-pwm" },
{ .compatible = "allwinner,sun50i-a64-pwm" },
+ { .compatible = "allwinner,sun7i-a20-pwm" },
{ }
};
--
2.25.1
Re: i.MX RT1050 toolchain
Hi Andy, On 10/16/20 9:05 AM, Andy Pont wrote: Hi Giulio, Is there a preferred / recommended toolchain for building U-Boot for the i.MX RT10xx platforms or should any recent ARM cross compiler work? It should compile fine with any recent ARM cross-compiler. Please let me know if it builds correctly Best regards -- Giulio Benetti Benetti Engineering sas
RE: [PATCH] usb: dwc2: add "u-boot,force-vbus-detection" for stm32
Hi Marek,
> From: Marek Vasut
> Sent: jeudi 15 octobre 2020 19:39
>
> On 10/15/20 6:52 PM, Patrick DELAUNAY wrote:
>
> Hi,
>
> [...]
>
> >> On 10/15/20 2:49 PM, Patrick Delaunay wrote:
> >>> On some board, the ID pin is not connected so the B session must be
> >>> overridden with "u-boot,force_b_session_valid" but the VBus sensing
> >>> must continue to be handle.
> >>>
> >>> To managed it, this patch adds a new DT field
> >>> "u-boot,force-vbus-detection" to use with "u-boot,force_b_session_valid"
> >>
> >> How is this solved in Linux ?
> >
> > It is managed by Linux DWC2 driver: it is a real OTG driver, with dual
> > mode support and by usb framework
> >
> > Throught the properties
> > _hs {
> > usb-role-switch;
> > };
> >
> > a glue treat the session and the sensing management see
> > linux/drivers/usb/dwc2/drd.c in linux-next
> >
> > PS: activate_stm_id_vb_detection is also used in driver = hsotg->params.
> >
> > As ID pin / vbus is completly managed by the USB TYPE driver C
> > (STUSB1600 for STMicroelectronics board) and DWC2 driver with dual
> > role stack (host/gadget).
> >
> > I don't found a better solution than device tree property for this
> > task in U-Boot as DWC2 driver don't support dual role and U-Boot don't have
> framework for USB type C controller.
> >
> >>
> >> btw can you do something about that huge change in indent ? Is it
> >> necessary ?
> >
> > I move all this code under activate_stm_id_vb_detection (linked to
> > compatible "st,stm32mp1-hsotg") to avoid impact on other platform as
> > this "sensing" properties are only support for STM32MP15X (it is
> > linked to USB block detection integrated in SOC)
> >
> > And after I need to check the
> > 1/ The usb33d-supply is required of vbus or IDPIN sensing 2/ manage
> > Vbus sensing or override (according dt) 3/ manage IDPIN or override
> > (according dt)
> >
> > I add a new property to be backward compatible (even it the
> > combinaison is less clear) I protect regulator function call to avoid
> > compilation
> issue for other platform.
> >
> > PS: after reading the refmanual, I also split VALOEN and VALOVAL bit update
> as it is required.
> >
> > So yes I think it is needed but I can split the patch to simplify the
> > review.
>
> I presume you don't feel like implementing proper OTG support, right ?
Yes, I am afraid of this task.
Patrick
Re: [PATCH v2] armv8: layerscape: don't remove crypto node if just partially disabled
On 8/10/2020 5:54 PM, Michael Walle wrote:
> On all newer Layerscape SoCs, the crypto module is just partially
> disabled on non-E parts. Thus it doesn't make sense to completely remove
> the node. Linux will figure out what is there and what is not.
>
Could add a clarification here, saying "partially disabled" means that
only export-controlled ciphers are disabled.
> Just remove it for older SoCs, where the module is indeed completely
> disabled on non-E parts.
>
> Signed-off-by: Michael Walle
> ---
> Changes since v1:
> - properly filter on SoC. Thanks to Horia's mail. See
>
> https://patchwork.ozlabs.org/project/uboot/patch/20200602150904.1997-1-mich...@walle.cc/#2457448
>
> arch/arm/cpu/armv8/fsl-layerscape/fdt.c | 37 -
> 1 file changed, 36 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
> b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
> index 3b43afb25c..acd25d4825 100644
> --- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
> +++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
> @@ -437,13 +437,48 @@ __weak void fdt_fixup_ecam(void *blob)
> }
> #endif
>
> +/*
> + * If it is a non-E part the crypto is disabled on the following SoCs:
> + * - LS1043A
> + * - LS1088A
> + * - LS2088A
I've missed LS2080A.
> + * and their personalities.
> + *
> + * On all other SoC they are just partially disabled, that means that the
^ it is (assuming "crypto" is the subject)
> + * following is still working:
> + * - hashing (using MDHA - message digest hash accelerator)
> + * - random number generation (using RNG4)
> + * - cyclic redundancy checking (using CRCA)
> + * - runtime integrity checker (RTIC)
> + *
> + * The linux driver will figure out what is available and what is not.
> + * Therefore, we just remove the crypto node on the SoCs which has no crypto
^ have
> + * support at all.
> + */
> +static bool crypto_is_disabled(unsigned int svr)
> +{
> + if (IS_E_PROCESSOR(svr))
> + return false;
> +
> + if (IS_SVR_DEV(svr, SVR_DEV(SVR_LS1043A)))
> + return true;
> +
> + if (IS_SVR_DEV(svr, SVR_DEV(SVR_LS1088A)))
> + return true;
> +
> + if (IS_SVR_DEV(svr, SVR_DEV(SVR_LS2088A)))
> + return true;
> +
> + return false;
> +}
> +
> void ft_cpu_setup(void *blob, struct bd_info *bd)
> {
> struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
> unsigned int svr = gur_in32(>svr);
>
> /* delete crypto node if not on an E-processor */
> - if (!IS_E_PROCESSOR(svr))
> + if (crypto_is_disabled(svr))
> fdt_fixup_crypto_node(blob, 0);
> #if CONFIG_SYS_FSL_SEC_COMPAT >= 4
> else {
>
[PATCH 3/5] board: mediatek: pumpkin: initialize usb device
Initialize USB device on pumpkin if it is enabled in the config.
Signed-off-by: Fabien Parent
---
board/mediatek/pumpkin/pumpkin.c | 17 +
1 file changed, 17 insertions(+)
diff --git a/board/mediatek/pumpkin/pumpkin.c b/board/mediatek/pumpkin/pumpkin.c
index 666e4d6a26fe..37daf1c51b92 100644
--- a/board/mediatek/pumpkin/pumpkin.c
+++ b/board/mediatek/pumpkin/pumpkin.c
@@ -4,8 +4,25 @@
*/
#include
+#include
int board_init(void)
{
return 0;
}
+
+int board_late_init(void)
+{
+ struct udevice *dev;
+ int ret;
+
+ if (CONFIG_IS_ENABLED(USB_GADGET)) {
+ ret = uclass_get_device(UCLASS_USB_GADGET_GENERIC, 0, );
+ if (ret) {
+ pr_err("%s: Cannot find USB device\n", __func__);
+ return ret;
+ }
+ }
+
+ return 0;
+}
--
2.28.0
[PATCH 2/5] arm: dts: mt8516-pumpkin: enable usb port
Enable the USB port for MT8516 Pumpkin Board.
Signed-off-by: Fabien Parent
---
arch/arm/dts/mt8516-pumpkin.dts | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/dts/mt8516-pumpkin.dts b/arch/arm/dts/mt8516-pumpkin.dts
index cd43c1f5e32c..292b00f0ffb1 100644
--- a/arch/arm/dts/mt8516-pumpkin.dts
+++ b/arch/arm/dts/mt8516-pumpkin.dts
@@ -108,3 +108,13 @@
{
status = "okay";
};
+
+ {
+ status = "okay";
+ dr_mode = "peripheral";
+
+ usb_con_c: connector {
+ compatible = "usb-c-connector";
+ label = "USB-C";
+ };
+};
--
2.28.0
[PATCH 5/5] configs: pumpkin: enable fastboot
Enable fastboot commands for mt8516 pumpkin board. Signed-off-by: Fabien Parent --- configs/pumpkin_defconfig | 7 ++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/configs/pumpkin_defconfig b/configs/pumpkin_defconfig index 94831adfa354..3f2cc6d023c1 100644 --- a/configs/pumpkin_defconfig +++ b/configs/pumpkin_defconfig @@ -46,8 +46,13 @@ CONFIG_CMD_PART=y # CONFIG_CMD_MISC is not set CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y -# CONFIG_NET is not set CONFIG_CLK=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x4d00 +CONFIG_FASTBOOT_BUF_SIZE=0x400 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 +CONFIG_FASTBOOT_MMC_BOOT1_SUPPORT=y # CONFIG_INPUT is not set CONFIG_DM_MMC=y # CONFIG_MMC_QUIRKS is not set -- 2.28.0
[PATCH 4/5] configs: pumpkin: enable USB gadget
Enable USB gadget on pumpkin. This requires to also enable BOARD_LATE_INIT since the init is done in board_late_init function. Signed-off-by: Fabien Parent --- configs/pumpkin_defconfig | 8 1 file changed, 8 insertions(+) diff --git a/configs/pumpkin_defconfig b/configs/pumpkin_defconfig index 3d6af03d2209..94831adfa354 100644 --- a/configs/pumpkin_defconfig +++ b/configs/pumpkin_defconfig @@ -17,6 +17,7 @@ CONFIG_FIT=y # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set CONFIG_DEFAULT_FDT_FILE="mt8516-pumpkin" # CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_BOARD_LATE_INIT=y CONFIG_HUSH_PARSER=y # CONFIG_CMD_BDI is not set # CONFIG_CMD_CONSOLE is not set @@ -59,6 +60,13 @@ CONFIG_BAUDRATE=921600 CONFIG_DM_SERIAL=y CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_MTK_SERIAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_MUSB_GADGET=y +CONFIG_USB_MUSB_MT85XX=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_VENDOR_NUM=0x0e8d +CONFIG_USB_GADGET_PRODUCT_NUM=0x201c CONFIG_WDT=y CONFIG_WDT_MTK=y # CONFIG_EFI_LOADER is not set -- 2.28.0
[PATCH 0/5] board: mediatek: pumpkin: add fastboot support
This series adds USB/Fastboot support on MT8516 Pumpkin board. Fabien Parent (5): arm: dts: mt8516: add support for USB arm: dts: mt8516-pumpkin: enable usb port board: mediatek: pumpkin: initialize usb device configs: pumpkin: enable USB gadget configs: pumpkin: enable fastboot arch/arm/dts/mt8516-pumpkin.dts | 10 ++ arch/arm/dts/mt8516.dtsi | 14 ++ board/mediatek/pumpkin/pumpkin.c | 17 + configs/pumpkin_defconfig| 15 ++- 4 files changed, 55 insertions(+), 1 deletion(-) -- 2.28.0
[PATCH 1/5] arm: dts: mt8516: add support for USB
Add support for USB on mt8516 based SoC.
Signed-off-by: Fabien Parent
---
arch/arm/dts/mt8516.dtsi | 14 ++
1 file changed, 14 insertions(+)
diff --git a/arch/arm/dts/mt8516.dtsi b/arch/arm/dts/mt8516.dtsi
index 1c3358208614..c4577ceea386 100644
--- a/arch/arm/dts/mt8516.dtsi
+++ b/arch/arm/dts/mt8516.dtsi
@@ -123,6 +123,20 @@
status = "disabled";
};
+ usb0: usb@1110 {
+ compatible = "mediatek,mt8516-musb",
+"mediatek,mt8518-musb";
+ reg = <0x1110 0x1000>;
+ interrupts = ;
+ interrupt-names = "mc";
+ clocks = < CLK_TOP_USB_PHY48M>,
+<_cg CLK_TOP_USBIF>,
+<_cg CLK_TOP_USB>,
+<_cg CLK_TOP_USB_1P>;
+ clock-names = "usbpll", "usbmcu", "usb", "icusb";
+ status = "disabled";
+ };
+
uart0: serial@11005000 {
compatible = "mediatek,hsuart";
reg = <0x11005000 0x1000>;
--
2.28.0
Re: [PATCH] libfdt: Fix signedness comparison warnings
On Fri, Oct 16, 2020 at 10:57:19AM -0400, Tom Rini wrote: > On Fri, Oct 16, 2020 at 03:42:50PM +0100, Andre Przywara wrote: > > > This is a combination of upstream libfdt commits to fix warnings about > > comparing signed and unsigned integers: > > == > > scripts/dtc/libfdt/fdt.c: In function ‘fdt_offset_ptr’: > > scripts/dtc/libfdt/fdt.c:137:18: warning: comparison between signed and > > unsigned integer expressions [-Wsign-compare] > >if ((absoffset < offset) > > ... > > == > > > > For a detailed description of the fixes, see the dtc repo: > > https://git.kernel.org/pub/scm/utils/dtc/dtc.git/log/?id=73e0f143b73d808 > > > > For this patch the commits between 73e0f143b73d8088 and ca19c3db2bf62000 > > have been combined and adjusted for the slight differences in U-Boot's > > libfdt code base. > > > > Signed-off-by: Andre Przywara > > So, the scripts that the Linux kernel uses to re-sync with dtc also work > for U-Boot. Has the kernel re-synced yet? If so, can we just re-sync > with that same commit again? That's typically how we do this. Thanks! I see that it has. So I'll give a re-sync a try and see what comes up. Thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH] libfdt: Fix signedness comparison warnings
On Fri, Oct 16, 2020 at 03:42:50PM +0100, Andre Przywara wrote: > This is a combination of upstream libfdt commits to fix warnings about > comparing signed and unsigned integers: > == > scripts/dtc/libfdt/fdt.c: In function ‘fdt_offset_ptr’: > scripts/dtc/libfdt/fdt.c:137:18: warning: comparison between signed and > unsigned integer expressions [-Wsign-compare] >if ((absoffset < offset) > ... > == > > For a detailed description of the fixes, see the dtc repo: > https://git.kernel.org/pub/scm/utils/dtc/dtc.git/log/?id=73e0f143b73d808 > > For this patch the commits between 73e0f143b73d8088 and ca19c3db2bf62000 > have been combined and adjusted for the slight differences in U-Boot's > libfdt code base. > > Signed-off-by: Andre Przywara So, the scripts that the Linux kernel uses to re-sync with dtc also work for U-Boot. Has the kernel re-synced yet? If so, can we just re-sync with that same commit again? That's typically how we do this. Thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH 15/17] fs/squashfs: sqfs_read: fix memory leak
Le 14/10/2020 à 10:06, Richard Genoud a écrit : sqfs_closedir() should be called to free memory allocated by sqfs_opendir() Signed-off-by: Richard Genoud --- fs/squashfs/sqfs.c | 1 + 1 file changed, 1 insertion(+) diff --git a/fs/squashfs/sqfs.c b/fs/squashfs/sqfs.c index 79d68dddb28..6cd3ba9ce10 100644 --- a/fs/squashfs/sqfs.c +++ b/fs/squashfs/sqfs.c @@ -1531,6 +1531,7 @@ free_datablk: free_paths: free(file); free(dir); + sqfs_closedir(dirsp); I forgot to remove a sqfs_closedir(dirsp); at the begining of the sqfs_read() function. So this could lead to a double free. I'll add it in next version. return ret; }
[PATCH] libfdt: Fix signedness comparison warnings
This is a combination of upstream libfdt commits to fix warnings about
comparing signed and unsigned integers:
==
scripts/dtc/libfdt/fdt.c: In function ‘fdt_offset_ptr’:
scripts/dtc/libfdt/fdt.c:137:18: warning: comparison between signed and
unsigned integer expressions [-Wsign-compare]
if ((absoffset < offset)
...
==
For a detailed description of the fixes, see the dtc repo:
https://git.kernel.org/pub/scm/utils/dtc/dtc.git/log/?id=73e0f143b73d808
For this patch the commits between 73e0f143b73d8088 and ca19c3db2bf62000
have been combined and adjusted for the slight differences in U-Boot's
libfdt code base.
Signed-off-by: Andre Przywara
---
scripts/dtc/libfdt/fdt.c | 15 +++
scripts/dtc/libfdt/fdt_overlay.c | 3 ++-
scripts/dtc/libfdt/fdt_ro.c | 20 +++-
scripts/dtc/libfdt/fdt_strerror.c | 4 ++--
scripts/dtc/libfdt/fdt_sw.c | 27 +++
scripts/dtc/libfdt/fdt_wip.c | 2 +-
6 files changed, 42 insertions(+), 29 deletions(-)
diff --git a/scripts/dtc/libfdt/fdt.c b/scripts/dtc/libfdt/fdt.c
index 8e4cce3b9be..28f4e1a5f15 100644
--- a/scripts/dtc/libfdt/fdt.c
+++ b/scripts/dtc/libfdt/fdt.c
@@ -131,16 +131,20 @@ int fdt_check_header(const void *fdt)
const void *fdt_offset_ptr(const void *fdt, int offset, unsigned int len)
{
- unsigned absoffset = offset + fdt_off_dt_struct(fdt);
+ unsigned int uoffset = offset;
+ unsigned int absoffset = offset + fdt_off_dt_struct(fdt);
+
+ if (offset < 0)
+ return NULL;
if (fdt_chk_basic())
- if ((absoffset < offset)
+ if ((absoffset < uoffset)
|| ((absoffset + len) < absoffset)
|| (absoffset + len) > fdt_totalsize(fdt))
return NULL;
if (!fdt_chk_version() || fdt_version(fdt) >= 0x11)
- if (((offset + len) < offset)
+ if (((uoffset + len) < uoffset)
|| ((offset + len) > fdt_size_dt_struct(fdt)))
return NULL;
@@ -302,9 +306,12 @@ const char *fdt_find_string_(const char *strtab, int
tabsize, const char *s)
int fdt_move(const void *fdt, void *buf, int bufsize)
{
+ if (fdt_chk_basic() && bufsize < 0)
+ return -FDT_ERR_NOSPACE;
+
FDT_RO_PROBE(fdt);
- if (fdt_totalsize(fdt) > bufsize)
+ if (fdt_totalsize(fdt) > (unsigned int)bufsize)
return -FDT_ERR_NOSPACE;
memmove(buf, fdt, fdt_totalsize(fdt));
diff --git a/scripts/dtc/libfdt/fdt_overlay.c b/scripts/dtc/libfdt/fdt_overlay.c
index bd75e3dd786..7a65c35af6f 100644
--- a/scripts/dtc/libfdt/fdt_overlay.c
+++ b/scripts/dtc/libfdt/fdt_overlay.c
@@ -241,6 +241,7 @@ static int overlay_update_local_node_references(void *fdto,
if (fixup_len % sizeof(uint32_t))
return -FDT_ERR_BADOVERLAY;
+ fixup_len /= sizeof(uint32_t);
tree_val = fdt_getprop(fdto, tree_node, name, _len);
if (!tree_val) {
@@ -250,7 +251,7 @@ static int overlay_update_local_node_references(void *fdto,
return tree_len;
}
- for (i = 0; i < (fixup_len / sizeof(uint32_t)); i++) {
+ for (i = 0; i < fixup_len; i++) {
fdt32_t adj_val;
uint32_t poffset;
diff --git a/scripts/dtc/libfdt/fdt_ro.c b/scripts/dtc/libfdt/fdt_ro.c
index d9d52e0d56e..d984bab036b 100644
--- a/scripts/dtc/libfdt/fdt_ro.c
+++ b/scripts/dtc/libfdt/fdt_ro.c
@@ -53,7 +53,7 @@ const char *fdt_get_string(const void *fdt, int stroffset,
int *lenp)
err = -FDT_ERR_BADOFFSET;
absoffset = stroffset + fdt_off_dt_strings(fdt);
- if (absoffset >= totalsize)
+ if (absoffset >= (unsigned)totalsize)
goto fail;
len = totalsize - absoffset;
@@ -61,17 +61,19 @@ const char *fdt_get_string(const void *fdt, int stroffset,
int *lenp)
if (stroffset < 0)
goto fail;
if (!fdt_chk_version() || fdt_version(fdt) >= 17) {
- if (stroffset >= fdt_size_dt_strings(fdt))
+ if ((unsigned)stroffset >= fdt_size_dt_strings(fdt))
goto fail;
if ((fdt_size_dt_strings(fdt) - stroffset) < len)
len = fdt_size_dt_strings(fdt) - stroffset;
}
} else if (fdt_magic(fdt) == FDT_SW_MAGIC) {
- if ((stroffset >= 0)
- || (stroffset < -fdt_size_dt_strings(fdt)))
+ unsigned int sw_stroffset = -stroffset;
+
+ if ((stroffset >= 0) ||
+ (sw_stroffset > fdt_size_dt_strings(fdt)))
goto fail;
- if ((-stroffset) < len)
- len = -stroffset;
+ if
Re: [PATCH 30/32] x86: acpi: Don't show the UART address by default
On Mon, Sep 28, 2020 at 12:26 PM Simon Glass wrote: > > This is useful when using Linux's earlycon since the MMIO address must be > provided on some platforms, e.g.: > >earlycon=uart8250,mmio32,0xddffc000,115200n8 > > However this is only for debugging, so don't show it by default. > > Signed-off-by: Simon Glass > --- > > arch/x86/lib/acpi_table.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > Reviewed-by: Bin Meng
Re: [PATCH 32/32] x86: fsp: Adjust calculations for MTRR range and DRAM top
On Mon, Sep 28, 2020 at 12:26 PM Simon Glass wrote: > > At present the top of available DRAM is the same as the top of the range > of the low-memory MTRR. > > In fact, U-Boot is allowed to use memory up until the start of the FSP > reserved memory. Use that value for low_end, since it makes more memory > available. > > Keep the same calculation as before for mtrr_top, i.e. the top of > reserved memory. > > A side-effect of this change is that the E820 tables have a single entry > that extends from the bottom of the memory used by U-Boot to the bottom > of the FSP reserved memory. This includes the bloblist, if ACPI tables > are placed there. > > Signed-off-by: Simon Glass > --- > > arch/x86/lib/fsp/fsp_dram.c | 35 ++- > 1 file changed, 22 insertions(+), 13 deletions(-) > Reviewed-by: Bin Meng
Re: [PATCH 31/32] x86: pinctrl: Silence the warning when a pin is not found
On Mon, Sep 28, 2020 at 12:26 PM Simon Glass wrote: > > This does not necessarily indicate a problem, since some pins are > optional. Let the caller show an error if necessary. > > Signed-off-by: Simon Glass > --- > > drivers/pinctrl/intel/pinctrl.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > Reviewed-by: Bin Meng
Re: [PATCH 29/32] x86: acpi: Include the TPMv1 table only if needed
On Mon, Sep 28, 2020 at 12:26 PM Simon Glass wrote: > > This table is not needed if a v2 TPM is in use. Add a condition to avoid > adding it when not needed. > > Signed-off-by: Simon Glass > --- > > arch/x86/lib/acpi_table.c | 19 +++ > 1 file changed, 11 insertions(+), 8 deletions(-) > Reviewed-by: Bin Meng
Re: [PATCH 26/32] x86: Boot coral into Chrome OS by default
On Mon, Sep 28, 2020 at 12:26 PM Simon Glass wrote: > > Add a script to boot Chrome OS from the internal MMC. This involved adding > a few commands and options. > > Signed-off-by: Simon Glass > --- > > configs/chromebook_coral_defconfig | 10 +++--- > include/configs/chromebook_coral.h | 9 - > 2 files changed, 15 insertions(+), 4 deletions(-) > Reviewed-by: Bin Meng
Re: [PATCH 28/32] x86: Silence some logging statements
On Mon, Sep 28, 2020 at 12:26 PM Simon Glass wrote: > > Quite a few log_info() calls are included in the x86 code which should use > log_debug() instead. Convert them to reduce unwanted output. > > Signed-off-by: Simon Glass > --- > > arch/x86/cpu/apollolake/fsp_s.c| 8 > arch/x86/cpu/intel_common/intel_opregion.c | 2 +- > arch/x86/cpu/intel_common/itss.c | 8 > arch/x86/lib/acpi_nhlt.c | 2 +- > arch/x86/lib/fsp/fsp_graphics.c| 2 +- > 5 files changed, 11 insertions(+), 11 deletions(-) > Reviewed-by: Bin Meng
Re: [PATCH 27/32] x86: fsp: Convert fsp_dram to use log_debug()
On Mon, Sep 28, 2020 at 12:26 PM Simon Glass wrote: > > Use log_debug() instead of debug() in this file, to enable the extra > features. > > Signed-off-by: Simon Glass > --- > > arch/x86/lib/fsp2/fsp_dram.c | 8 ++-- > 1 file changed, 6 insertions(+), 2 deletions(-) > Reviewed-by: Bin Meng
Re: [PATCH 23/32] x86: Define the Chrome OS GNVS region
Hi Simon,
On Mon, Sep 28, 2020 at 12:26 PM Simon Glass wrote:
>
> It is not possible to boot Chrome OS properly without passing some basic
> information from U-Boot. This applies even if verified boot is not being
> used. Add a structure definition for this.
>
> Signed-off-by: Simon Glass
> ---
>
> arch/x86/include/asm/intel_gnvs.h | 49 +++
> 1 file changed, 49 insertions(+)
>
> diff --git a/arch/x86/include/asm/intel_gnvs.h
> b/arch/x86/include/asm/intel_gnvs.h
> index c1e9d65779f..a2c17bf646f 100644
> --- a/arch/x86/include/asm/intel_gnvs.h
> +++ b/arch/x86/include/asm/intel_gnvs.h
> @@ -9,6 +9,55 @@
> #ifndef _INTEL_GNVS_H_
> #define _INTEL_GNVS_H_
>
> +/*
> + * The chromeos_acpi portion of ACPI GNVS is assumed to live from offset
> + * 0x100 - 0x1000. When defining acpi_global_nvs, use check_member
> + * to ensure that it is properly aligned:
> + *
> + * check_member(acpi_global_nvs, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
> + */
> +#define GNVS_CHROMEOS_ACPI_OFFSET 0x100
> +
> +enum {
> + CHSW_RECOVERY_X86 = BIT(1),
> + CHSW_RECOVERY_EC = BIT(2),
> + CHSW_DEVELOPER_SWITCH = BIT(5),
> + CHSW_FIRMWARE_WP = BIT(9),
> +};
> +
> +enum {
> + FIRMWARE_TYPE_AUTO_DETECT = -1,
> + FIRMWARE_TYPE_RECOVERY = 0,
> + FIRMWARE_TYPE_NORMAL = 1,
> + FIRMWARE_TYPE_DEVELOPER = 2,
> + FIRMWARE_TYPE_NETBOOT = 3,
> + FIRMWARE_TYPE_LEGACY = 4,
> +};
> +
> +struct __packed chromeos_acpi {
Should this be renamed as `choromeos_acpi_gnvs`?
> + /* ChromeOS-specific */
> + u32 boot_reason;// 00 boot reason
nits: please use /* */ instead of //
> + u32 active_main_fw; // 04 (0=recovery, 1=A, 2=B)
> + u32 activeec_fw;// 08 (0=RO, 1=RW)
> + u16 switches; // 0c CHSW
> + u8 vbt4[256]; // 0e HWID
> + u8 vbt5[64]; // 10e FWID
> + u8 vbt6[64]; // 14e FRID - 275
> + u32 main_fw_type; // 18e (2 = developer mode)
> + u32 vbt8; // 192 recovery reason
> + u32 vbt9; // 196 fmap base address
> + u8 vdat[3072]; // 19a VDAT space filled by verified boot
> + u32 vbt10; // d9a smbios bios version
> + u32 mehh[8];// d9e management engine hash
> + u32 ramoops_base; // dbe ramoops base address
> + u32 ramoops_len;// dc2 ramoops length
> + u32 vpd_ro_base;// dc6 pointer to RO_VPD
> + u32 vpd_ro_size;// dca size of RO_VPD
> + u32 vpd_rw_base;// dce pointer to RW_VPD
> + u32 vpd_rw_size;// dd2 size of RW_VPD
> + u8 pad[298]; // dd6-eff
> +};
> +
> struct __packed acpi_global_nvs {
> /* Miscellaneous */
> u8 pcnt; /* 0x00 - Processor Count */
> --
Regards,
Bin
Re: [PATCH 24/32] x86: Use CONFIG_CHROMEOS_VBOOT for verified boot
Hi Simon, On Mon, Sep 28, 2020 at 12:26 PM Simon Glass wrote: > > At present CONFIG_CHROMEOS is used to determine whether verified boot is > in use. The code to implement that is not in U-Boot mainline. > > However, it is useful to be able to boot a Chromebook in developer mode > in U-Boot mainline without needing the verified boot code. > > To allow this, use CONFIG_CHROMEOS_VBOOT to indicate that verified boot > should be used, and CONFIG_CHROMEOS to indicate that the board supports > Chrome OS. That allows us to define CONFIG_CHROMEOS on coral. > > Signed-off-by: Simon Glass > --- > > Kconfig| 8 > arch/x86/dts/chromebook_coral.dts | 2 +- > arch/x86/dts/chromebook_samus.dts | 2 +- > arch/x86/include/asm/intel_gnvs.h | 3 --- > arch/x86/lib/tpl.c | 2 +- > configs/chromebook_coral_defconfig | 3 ++- > 6 files changed, 13 insertions(+), 7 deletions(-) > > diff --git a/Kconfig b/Kconfig > index 837b2f517ae..bd3bcb0d6f1 100644 > --- a/Kconfig > +++ b/Kconfig > @@ -759,6 +759,14 @@ config ARCH_FIXUP_FDT_MEMORY > used for booting OS with different memory setup where the part of > the memory location should be used for different purpose. > > +config CHROMEOS > + bool "Support booting Chrome OS" > + help > + Chrome OS requires U-Boot to set up a table indicating the boot mode > + (e.g. Developer mode) and a few other things. Enable this if you are > + booting on a Chromebook to avoid getting an error about an invalid > + firmware ID. > + > endmenu# Boot images > > source "api/Kconfig" > diff --git a/arch/x86/dts/chromebook_coral.dts > b/arch/x86/dts/chromebook_coral.dts > index 92f70b13dd7..43f4b33da1b 100644 > --- a/arch/x86/dts/chromebook_coral.dts > +++ b/arch/x86/dts/chromebook_coral.dts > @@ -9,7 +9,7 @@ > /include/ "rtc.dtsi" > /include/ "tsc_timer.dtsi" > > -#ifdef CONFIG_CHROMEOS > +#ifdef CONFIG_CHROMEOS_VBOOT I don't see this being defined as a Kconfig option. Am I missing anything? > #include "chromeos-x86.dtsi" > #include "flashmap-x86-ro.dtsi" > #include "flashmap-16mb-rw.dtsi" [snip] Regards, Bin
Re: [PATCH 22/32] acpi: Don't reset the tables with every new generation
On Mon, Sep 28, 2020 at 12:26 PM Simon Glass wrote: > > At present if SSDT and DSDT code is created, only the latter is retained > for examination by the 'acpi items' command. Fix this by only resetting > the list when explicitly requested. > > Signed-off-by: Simon Glass > --- > > arch/x86/lib/acpi_table.c | 1 + > drivers/core/acpi.c | 10 ++ > include/dm/acpi.h | 9 + > test/dm/acpi.c| 4 > 4 files changed, 20 insertions(+), 4 deletions(-) > Reviewed-by: Bin Meng
Re: [PATCH 25/32] x86: Set up Chrome OS to boot into developer mode
On Mon, Sep 28, 2020 at 12:26 PM Simon Glass wrote: > > Set up a few fields necessarily to make Chrome OS boot without showing a > firmware error. > > Signed-off-by: Simon Glass > --- > > arch/x86/cpu/apollolake/acpi.c | 25 - > 1 file changed, 20 insertions(+), 5 deletions(-) > Reviewed-by: Bin Meng
Re: [PATCH 21/32] x86: acpi: Put the generated code first in DSDT
On Mon, Sep 28, 2020 at 12:26 PM Simon Glass wrote: > > The current implementation for DSDT tables is not correct for the case > where there is generated code, as the length ends up being incorrect. > Also, we want the generated code to go first in the table. > > Rewrite this piece to correct these problems. > > Signed-off-by: Simon Glass > --- > > arch/x86/lib/acpi_table.c | 27 ++- > 1 file changed, 18 insertions(+), 9 deletions(-) > Reviewed-by: Bin Meng
Re: [PATCH 10/16] tee: optee: Include device_compat.h
Hi Sean, On Mon, Oct 5, 2020 at 4:42 AM Sean Anderson wrote: > > Necessary for dev_xxx. > > Signed-off-by: Sean Anderson > --- > > drivers/tee/optee/core.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/drivers/tee/optee/core.c b/drivers/tee/optee/core.c > index 5260dab3ac..66ade37cd4 100644 > --- a/drivers/tee/optee/core.c > +++ b/drivers/tee/optee/core.c > @@ -5,6 +5,7 @@ > > #include > #include > +#include > #include > #include > #include > -- > 2.28.0 > Reviewed-by: Igor Opaniuk -- Best regards - Freundliche Grüsse - Meilleures salutations Igor Opaniuk mailto: igor.opan...@gmail.com skype: igor.opanyuk +380 (93) 836 40 67 http://ua.linkedin.com/in/iopaniuk
Re: [PATCH 16/16] dm: Don't undefine dev_xxx macros
On Sun, Oct 04, 2020 at 09:39:57PM -0400, Sean Anderson wrote: > Now that linux/compat.h does not define these macros, we do not need to > undefine them. > > Signed-off-by: Sean Anderson > Reviewed-by: Simon Glass Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH 15/16] linux/compat.h: Remove redefinition of dev_xxx macros
On Sun, Oct 04, 2020 at 09:39:56PM -0400, Sean Anderson wrote: > All users of these functions now include dm/device_compat.h directly. > > Signed-off-by: Sean Anderson > Reviewed-by: Simon Glass Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH 3/3] usb: dwc3: Include device_compat.h in dwc3-octeon-glue.c
On Fri, Oct 16, 2020 at 08:42:46AM -0400, Tom Rini wrote: > Necessary for dev_xxx. > > Signed-off-by: Tom Rini Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH 2/3] clk: at91: Include device_compat.h in compat.c
On Fri, Oct 16, 2020 at 08:42:45AM -0400, Tom Rini wrote: > Necessary for dev_xxx. > > Signed-off-by: Tom Rini Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH 11/16] timer: Include device_compat.h
On Sun, Oct 04, 2020 at 09:39:52PM -0400, Sean Anderson wrote: > Necessary for dev_xxx. > > Signed-off-by: Sean Anderson > Reviewed-by: Simon Glass Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH 1/3] arm: fsl-layerscape: Include device_compat.h in soc.c
On Fri, Oct 16, 2020 at 08:42:44AM -0400, Tom Rini wrote: > Necessary for dev_xxx. > > Signed-off-by: Tom Rini Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH 13/16] usb: musb-new: Include device_compat.h
On Sun, Oct 04, 2020 at 09:39:54PM -0400, Sean Anderson wrote: > This was included, but was ifdef'd out. We also need dm.h for struct > udevice. > > Signed-off-by: Sean Anderson Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH 10/16] tee: optee: Include device_compat.h
On Sun, Oct 04, 2020 at 09:39:51PM -0400, Sean Anderson wrote: > Necessary for dev_xxx. > > Signed-off-by: Sean Anderson > Reviewed-by: Simon Glass Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH 12/16] usb: xhci: Include device_compat.h
On Sun, Oct 04, 2020 at 09:39:53PM -0400, Sean Anderson wrote: > This header is necessary for the dev_xxx macros. > > Signed-off-by: Sean Anderson Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH 14/16] usb: musb-new: mt85xx: Fix not calling dev_err with a device
On Sun, Oct 04, 2020 at 09:39:55PM -0400, Sean Anderson wrote: > This driver doesn't use DM (in the correct places), so we use a device and > not a udevice. We also need to include device_compat.h > > Signed-off-by: Sean Anderson Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH 08/16] spi: nxp_fspi: Include device_compat.h
On Sun, Oct 04, 2020 at 09:39:49PM -0400, Sean Anderson wrote: > Necessary for dev_xxx. > > Signed-off-by: Sean Anderson Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH 07/16] ram: imxrt: Include device_compat.h
On Sun, Oct 04, 2020 at 09:39:48PM -0400, Sean Anderson wrote: > Necessary for dev_xxx. > > Signed-off-by: Sean Anderson Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH 06/16] phy: Include device_compat.h
On Sun, Oct 04, 2020 at 09:39:47PM -0400, Sean Anderson wrote: > Necessary for dev_xxx. > > Signed-off-by: Sean Anderson Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH 09/16] spi: fsl_qspi: Include device_compat.h
On Sun, Oct 04, 2020 at 09:39:50PM -0400, Sean Anderson wrote: > Necessary for dev_xxx. > > Signed-off-by: Sean Anderson Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH 03/16] firmware: scmi: Include device_compat.h
On Sun, Oct 04, 2020 at 09:39:44PM -0400, Sean Anderson wrote: > This header is necessary for the dev_xxx macros. > > Signed-off-by: Sean Anderson > Reviewed-by: Simon Glass Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH 02/16] dm: syscon: Set LOG_CATEGORY
On Sun, Oct 04, 2020 at 09:39:43PM -0400, Sean Anderson wrote: > We call log_debug, but do not have a category set. > > Signed-off-by: Sean Anderson > Reviewed-by: Simon Glass Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH 01/16] clk: sifive: Include device_compat.h
On Sun, Oct 04, 2020 at 09:39:42PM -0400, Sean Anderson wrote: > Necessary for dev_xxx. > > Signed-off-by: Sean Anderson Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH 04/16] mtd: mxs_nand: Fix not calling dev_xxx with a device
On Sun, Oct 04, 2020 at 09:39:45PM -0400, Sean Anderson wrote: > This includes device_compat.h, and fixes several calls to dev_xxx. > > Signed-off-by: Sean Anderson Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH 05/16] net: ldpaa_eth: Include device_compat.h
On Sun, Oct 04, 2020 at 09:39:46PM -0400, Sean Anderson wrote: > Necessary for dev_xxx. > > Signed-off-by: Sean Anderson Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH] sunxi: make V3s DRAM initialization more proper
On 16/10/2020 10:33, Icenowy Zheng wrote:
Hi,
> Previously, because we have no source code about the DRAM initialization
> of V3s and missing some configurations (delays and MBUS QoS info), our
> V3s DRAM initialization sequence is hacked from the H3 one.
>
> As the SDK shipped with PineCube contains source code for V3s libdram,
> we can retrieve these information from it and tweak some other magic
> bits.
Nice! Thanks for taking care.
> Signed-off-by: Icenowy Zheng
I couldn't be asked to check the specific bits in the new V3s libdram,
nor do I have any hardware to test this, but I checked the integration
into the driver, and compile tested for the LicheePi and H3 boards.
The code size for H3 stayed the same, for the LicheePi it actually
decreased.
So from this perspective:
Reviewed-by: Andre Przywara
Cheers,
Andre
> ---
> arch/arm/include/asm/arch-sunxi/cpu.h | 1 +
> arch/arm/mach-sunxi/dram_sunxi_dw.c | 91 +--
> 2 files changed, 87 insertions(+), 5 deletions(-)
>
> diff --git a/arch/arm/include/asm/arch-sunxi/cpu.h
> b/arch/arm/include/asm/arch-sunxi/cpu.h
> index 4c399b0a15..8b57d24e2f 100644
> --- a/arch/arm/include/asm/arch-sunxi/cpu.h
> +++ b/arch/arm/include/asm/arch-sunxi/cpu.h
> @@ -16,6 +16,7 @@
>
> #define SOCID_A640x1689
> #define SOCID_H3 0x1680
> +#define SOCID_V3S0x1681
> #define SOCID_H5 0x1718
> #define SOCID_R400x1701
>
> diff --git a/arch/arm/mach-sunxi/dram_sunxi_dw.c
> b/arch/arm/mach-sunxi/dram_sunxi_dw.c
> index a462538521..d0600011ff 100644
> --- a/arch/arm/mach-sunxi/dram_sunxi_dw.c
> +++ b/arch/arm/mach-sunxi/dram_sunxi_dw.c
> @@ -63,6 +63,8 @@ enum {
> MBUS_PORT_CSI = 5,
> MBUS_PORT_NAND = 6,
> MBUS_PORT_SS= 7,
> + MBUS_PORT_DE_V3S= 8,
> + MBUS_PORT_DE_CFD_V3S= 9,
> MBUS_PORT_TS= 8,
> MBUS_PORT_DI= 9,
> MBUS_PORT_DE= 10,
> @@ -134,6 +136,29 @@ static void mctl_set_master_priority_h3(void)
> MBUS_CONF(DE_CFD, true,HIGH, 0, 1024, 288, 64);
> }
>
> +static void mctl_set_master_priority_v3s(void)
> +{
> + struct sunxi_mctl_com_reg * const mctl_com =
> + (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
> +
> + /* enable bandwidth limit windows and set windows size 1us */
> + writel((1 << 16) | (400 << 0), _com->bwcr);
> +
> + /* set cpu high priority */
> + writel(0x0001, _com->mapr);
> +
> + MBUS_CONF( CPU, true, HIGHEST, 0, 160, 100, 80);
> + MBUS_CONF( GPU, true,HIGH, 0, 1792, 1536,0);
> + MBUS_CONF(UNUSED, true, HIGHEST, 0, 256, 128, 80);
> + MBUS_CONF( DMA, true,HIGH, 0, 256, 100,0);
> + MBUS_CONF(VE, true,HIGH, 0, 2048, 1600,0);
> + MBUS_CONF( CSI, true, HIGHEST, 0, 384, 256,0);
> + MBUS_CONF( NAND, true,HIGH, 0, 100, 50,0);
> + MBUS_CONF(SS, true,HIGH, 0, 384, 256,0);
> + MBUS_CONF(DE_V3S, false,HIGH, 0, 8192, 4096,0);
> + MBUS_CONF(DE_CFD_V3S, true,HIGH, 0, 640, 256,0);
> +}
> +
> static void mctl_set_master_priority_a64(void)
> {
> struct sunxi_mctl_com_reg * const mctl_com =
> @@ -231,6 +256,9 @@ static void mctl_set_master_priority(uint16_t socid)
> case SOCID_H3:
> mctl_set_master_priority_h3();
> return;
> + case SOCID_V3S:
> + mctl_set_master_priority_v3s();
> + return;
> case SOCID_A64:
> mctl_set_master_priority_a64();
> return;
> @@ -334,6 +362,28 @@ static void mctl_h3_zq_calibration_quirk(struct
> dram_para *para)
> }
> }
>
> +static void mctl_v3s_zq_calibration_quirk(struct dram_para *para)
> +{
> + struct sunxi_mctl_ctl_reg * const mctl_ctl =
> + (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
> +
> + u32 reg_val;
> +
> + clrsetbits_le32(_ctl->zqcr, 0xff,
> + CONFIG_DRAM_ZQ & 0xff);
> + mctl_phy_init(PIR_ZCAL);
> +
> + reg_val = readl(_ctl->zqdr[0]);
> + reg_val &= (0x1f << 16) | (0x1f << 0);
> + reg_val |= reg_val << 8;
> + writel(reg_val, _ctl->zqdr[0]);
> +
> + reg_val = readl(_ctl->zqdr[1]);
> + reg_val &= (0x1f << 16) | (0x1f << 0);
> + reg_val |= reg_val << 8;
> + writel(reg_val, _ctl->zqdr[1]);
> +}
> +
> static void mctl_set_cr(uint16_t socid, struct dram_para *para)
> {
> struct sunxi_mctl_com_reg * const mctl_com =
> @@ -391,7 +441,7 @@ static void mctl_sys_init(uint16_t socid, struct
> dram_para *para)
> CCM_DRAMCLK_CFG_DIV(1) |
> CCM_DRAMCLK_CFG_SRC_PLL11 |
> CCM_DRAMCLK_CFG_UPD);
> - } else if (socid == SOCID_H3 || socid == SOCID_H5) {
> + } else if (socid == SOCID_H3 || socid == SOCID_H5 || socid ==
>
Please pull u-boot-marvell/master
Hi Tom, please pull an update of Marvell Octeon TX/TX2 related patches. Here the summary log: - Fix Octeon SPI driver for Octeon TX2 - Fix and enhance Octeon watchdog driver - Misc minor enhancements to Octeon TX/TX2 Here the Azure build, without any issues: https://dev.azure.com/sr0718/u-boot/_build/results?buildId=57=results Thanks, Stefan The following changes since commit 9dc6aef8c963ae17e1263b89c692792fce0c7198: Merge tag 'mmc-2020-10-14' of https://gitlab.denx.de/u-boot/custodians/u-boot-mmc (2020-10-15 08:20:42 -0400) are available in the Git repository at: g...@gitlab.denx.de:u-boot/custodians/u-boot-marvell.git for you to fetch changes up to b666714c30c6d6501fbb91d1774065a204a88b8e: arm: octeontx: Add CMD_WDT (2020-10-16 13:55:04 +0200) Stefan Roese (4): spi: octeon_spi: Use a fixed 100MHz input clock on Octeon TX2 mmc: octeontx_hsmmc.c: Remove test debug message arm: octeontx: Select CLK arm: octeontx: Add CMD_WDT Suneel Garapati (1): watchdog: octeontx_wdt: Add support for start and stop arch/arm/Kconfig | 2 + configs/octeontx2_95xx_defconfig | 1 + configs/octeontx2_96xx_defconfig | 1 + configs/octeontx_81xx_defconfig | 1 + configs/octeontx_83xx_defconfig | 1 + drivers/mmc/octeontx_hsmmc.c | 1 - drivers/spi/octeon_spi.c | 5 ++- drivers/watchdog/octeontx_wdt.c | 88 +--- 8 files changed, 93 insertions(+), 7 deletions(-)
Re: [PATCH] spi: octeon_spi: Use a fixed 100MHz input clock on Octeon TX2
On 05.08.20 15:07, Stefan Roese wrote: Octeon TX2 sets the TB100_EN bit in the config register. We need to use a fixed 100MHz clock for this as well to work properly. Signed-off-by: Stefan Roese Cc: Aaron Williams Cc: Suneel Garapati Cc: Chandrakala Chavva Cc: Jagan Teki Applied to u-boot-marvell/master Thanks, Stefan --- drivers/spi/octeon_spi.c | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/spi/octeon_spi.c b/drivers/spi/octeon_spi.c index 83fe6330a1..7e88e5580f 100644 --- a/drivers/spi/octeon_spi.c +++ b/drivers/spi/octeon_spi.c @@ -519,7 +519,10 @@ static int octeon_spi_set_speed(struct udevice *bus, uint max_hz) if (max_hz > OCTEON_SPI_MAX_CLOCK_HZ) max_hz = OCTEON_SPI_MAX_CLOCK_HZ; - clk_rate = clk_get_rate(>clk); + if (device_is_compatible(bus, "cavium,thunderx-spi")) + clk_rate = 1; + else + clk_rate = clk_get_rate(>clk); if (IS_ERR_VALUE(clk_rate)) return -EINVAL; Viele Grüße, Stefan -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-51 Fax: (+49)-8142-66989-80 Email: s...@denx.de
Re: [PATCH 3/4] watchdog: octeontx_wdt: Add support for start and stop
On 23.09.20 11:01, Stefan Roese wrote:
From: Suneel Garapati
This patch enhances the Octeon TX/TX2 watchdog driver to fully enable
the WDT. With this changes, the "wdt" command is now also supported
on these platforms.
Signed-off-by: Suneel Garapati
Signed-off-by: Stefan Roese
Cc: Aaron Williams
Cc: Suneel Garapati
Cc: Chandrakala Chavva
Applied to u-boot-marvell/master
Thanks,
Stefan
---
drivers/watchdog/octeontx_wdt.c | 88 +++--
1 file changed, 83 insertions(+), 5 deletions(-)
diff --git a/drivers/watchdog/octeontx_wdt.c b/drivers/watchdog/octeontx_wdt.c
index 1e0670e0c5..88708dc5e1 100644
--- a/drivers/watchdog/octeontx_wdt.c
+++ b/drivers/watchdog/octeontx_wdt.c
@@ -5,25 +5,90 @@
* https://spdx.org/licenses
*/
+#include
#include
#include
#include
#include
+#include
DECLARE_GLOBAL_DATA_PTR;
+#define CORE0_WDOG_OFFSET 0x4
#define CORE0_POKE_OFFSET 0x5
#define CORE0_POKE_OFFSET_MASK0xfULL
+#define WDOG_MODE GENMASK_ULL(1, 0)
+#define WDOG_LEN GENMASK_ULL(19, 4)
+#define WDOG_CNT GENMASK_ULL(43, 20)
+
struct octeontx_wdt {
void __iomem *reg;
+ struct clk clk;
};
+static int octeontx_wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags)
+{
+ struct octeontx_wdt *priv = dev_get_priv(dev);
+ u64 clk_rate, val;
+ u64 tout_wdog;
+
+ clk_rate = clk_get_rate(>clk);
+ if (IS_ERR_VALUE(clk_rate))
+ return -EINVAL;
+
+ /* Watchdog counts in 1024 cycle steps */
+ tout_wdog = (clk_rate * timeout_ms / 1000) >> 10;
+
+ /*
+* We can only specify the upper 16 bits of a 24 bit value.
+* Round up
+*/
+ tout_wdog = (tout_wdog + 0xff) >> 8;
+
+ /* If the timeout overflows the hardware limit, set max */
+ if (tout_wdog >= 0x1)
+ tout_wdog = 0x;
+
+ val = FIELD_PREP(WDOG_MODE, 0x3) |
+ FIELD_PREP(WDOG_LEN, tout_wdog) |
+ FIELD_PREP(WDOG_CNT, tout_wdog << 8);
+ writeq(val, priv->reg + CORE0_WDOG_OFFSET);
+
+ return 0;
+}
+
+static int octeontx_wdt_stop(struct udevice *dev)
+{
+ struct octeontx_wdt *priv = dev_get_priv(dev);
+
+ writeq(0, priv->reg + CORE0_WDOG_OFFSET);
+
+ return 0;
+}
+
+static int octeontx_wdt_expire_now(struct udevice *dev, ulong flags)
+{
+ octeontx_wdt_stop(dev);
+
+ /* Start with 100ms timeout to expire immediately */
+ octeontx_wdt_start(dev, 100, flags);
+
+ return 0;
+}
+
static int octeontx_wdt_reset(struct udevice *dev)
{
struct octeontx_wdt *priv = dev_get_priv(dev);
- writeq(~0ULL, priv->reg);
+ writeq(~0ULL, priv->reg + CORE0_POKE_OFFSET);
+
+ return 0;
+}
+
+static int octeontx_wdt_remove(struct udevice *dev)
+{
+ octeontx_wdt_stop(dev);
return 0;
}
@@ -31,24 +96,35 @@ static int octeontx_wdt_reset(struct udevice *dev)
static int octeontx_wdt_probe(struct udevice *dev)
{
struct octeontx_wdt *priv = dev_get_priv(dev);
+ int ret;
priv->reg = dev_remap_addr(dev);
if (!priv->reg)
return -EINVAL;
/*
-* Save core poke register address in reg (its not 0xa as
-* extracted from the DT but 0x5 instead)
+* Save base register address in reg masking lower 20 bits
+* as 0xa appears when extracted from the DT
*/
priv->reg = (void __iomem *)(((u64)priv->reg &
- ~CORE0_POKE_OFFSET_MASK) |
-CORE0_POKE_OFFSET);
+ ~CORE0_POKE_OFFSET_MASK));
+
+ ret = clk_get_by_index(dev, 0, >clk);
+ if (ret < 0)
+ return ret;
+
+ ret = clk_enable(>clk);
+ if (ret)
+ return ret;
return 0;
}
static const struct wdt_ops octeontx_wdt_ops = {
.reset = octeontx_wdt_reset,
+ .start = octeontx_wdt_start,
+ .stop = octeontx_wdt_stop,
+ .expire_now = octeontx_wdt_expire_now,
};
static const struct udevice_id octeontx_wdt_ids[] = {
@@ -63,4 +139,6 @@ U_BOOT_DRIVER(wdt_octeontx) = {
.ops = _wdt_ops,
.priv_auto_alloc_size = sizeof(struct octeontx_wdt),
.probe = octeontx_wdt_probe,
+ .remove = octeontx_wdt_remove,
+ .flags = DM_FLAG_OS_PREPARE,
};
Viele Grüße,
Stefan
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-51 Fax: (+49)-8142-66989-80 Email: s...@denx.de
Re: [PATCH 1/4] mmc: octeontx_hsmmc.c: Remove test debug message
On 23.09.20 11:01, Stefan Roese wrote:
Remove a left-over debug test message from the Octeon TX / TX2
MMC driver.
Signed-off-by: Stefan Roese
Cc: Aaron Williams
Cc: Suneel Garapati
Cc: Chandrakala Chavva
Applied to u-boot-marvell/master
Thanks,
Stefan
---
drivers/mmc/octeontx_hsmmc.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/mmc/octeontx_hsmmc.c b/drivers/mmc/octeontx_hsmmc.c
index ddc36694e1..38ca373684 100644
--- a/drivers/mmc/octeontx_hsmmc.c
+++ b/drivers/mmc/octeontx_hsmmc.c
@@ -3638,7 +3638,6 @@ static int octeontx_mmc_slot_probe(struct udevice *dev)
struct mmc *mmc;
int err;
- printk("%s (%d)\n", __func__, __LINE__); // test-only
debug("%s(%s)\n", __func__, dev->name);
if (!host_probed) {
pr_err("%s(%s): Error: host not probed yet\n",
Viele Grüße,
Stefan
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-51 Fax: (+49)-8142-66989-80 Email: s...@denx.de
Re: [PATCH 4/4] arm: octeontx: Add CMD_WDT
On 23.09.20 11:01, Stefan Roese wrote: Enable WDT command for Octeon TX/TX2 boards. Signed-off-by: Stefan Roese Cc: Aaron Williams Cc: Suneel Garapati Cc: Chandrakala Chavva Applied to u-boot-marvell/master Thanks, Stefan --- configs/octeontx2_95xx_defconfig | 1 + configs/octeontx2_96xx_defconfig | 1 + configs/octeontx_81xx_defconfig | 1 + configs/octeontx_83xx_defconfig | 1 + 4 files changed, 4 insertions(+) diff --git a/configs/octeontx2_95xx_defconfig b/configs/octeontx2_95xx_defconfig index 047cb45a21..a17e5521d9 100644 --- a/configs/octeontx2_95xx_defconfig +++ b/configs/octeontx2_95xx_defconfig @@ -41,6 +41,7 @@ CONFIG_CMD_BKOPS_ENABLE=y CONFIG_CMD_PART=y CONFIG_CMD_PCI=y CONFIG_CMD_SF_TEST=y +CONFIG_CMD_WDT=y CONFIG_CMD_DHCP=y CONFIG_CMD_TFTPPUT=y CONFIG_CMD_TFTPSRV=y diff --git a/configs/octeontx2_96xx_defconfig b/configs/octeontx2_96xx_defconfig index 7b5a1243a7..2e6cef0684 100644 --- a/configs/octeontx2_96xx_defconfig +++ b/configs/octeontx2_96xx_defconfig @@ -42,6 +42,7 @@ CONFIG_CMD_PART=y CONFIG_CMD_PCI=y CONFIG_CMD_SF_TEST=y CONFIG_CMD_USB=y +CONFIG_CMD_WDT=y CONFIG_CMD_DHCP=y CONFIG_CMD_TFTPPUT=y CONFIG_CMD_TFTPSRV=y diff --git a/configs/octeontx_81xx_defconfig b/configs/octeontx_81xx_defconfig index ca3286b901..ff24e6e1e8 100644 --- a/configs/octeontx_81xx_defconfig +++ b/configs/octeontx_81xx_defconfig @@ -43,6 +43,7 @@ CONFIG_CMD_PART=y CONFIG_CMD_PCI=y CONFIG_CMD_SF_TEST=y CONFIG_CMD_USB=y +CONFIG_CMD_WDT=y CONFIG_CMD_DHCP=y CONFIG_CMD_TFTPPUT=y CONFIG_CMD_TFTPSRV=y diff --git a/configs/octeontx_83xx_defconfig b/configs/octeontx_83xx_defconfig index e7dd3f6b73..ab38d007ea 100644 --- a/configs/octeontx_83xx_defconfig +++ b/configs/octeontx_83xx_defconfig @@ -41,6 +41,7 @@ CONFIG_CMD_PART=y CONFIG_CMD_PCI=y CONFIG_CMD_SF_TEST=y CONFIG_CMD_USB=y +CONFIG_CMD_WDT=y CONFIG_CMD_DHCP=y CONFIG_CMD_TFTPPUT=y CONFIG_CMD_TFTPSRV=y Viele Grüße, Stefan -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-51 Fax: (+49)-8142-66989-80 Email: s...@denx.de
Re: [PATCH 2/4] arm: octeontx: Select CLK
On 23.09.20 11:01, Stefan Roese wrote: Clock support is needed for all Octeon TX/TX2 boards. This patch selects CONFIG_CLK so that it is available. Signed-off-by: Stefan Roese Cc: Aaron Williams Cc: Suneel Garapati Cc: Chandrakala Chavva Applied to u-boot-marvell/master Thanks, Stefan --- arch/arm/Kconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 80702c23d3..c8362b8a56 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1739,6 +1739,7 @@ config ARCH_ROCKCHIP config ARCH_OCTEONTX bool "Support OcteonTX SoCs" + select CLK select DM select ARM64 select OF_CONTROL @@ -1748,6 +1749,7 @@ config ARCH_OCTEONTX config ARCH_OCTEONTX2 bool "Support OcteonTX2 SoCs" + select CLK select DM select ARM64 select OF_CONTROL Viele Grüße, Stefan -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-51 Fax: (+49)-8142-66989-80 Email: s...@denx.de
Re: [PATCH 19/32] acpi: Correct reset handling in acpi_device_add_power_res()
On Mon, Sep 28, 2020 at 12:26 PM Simon Glass wrote: > > If there is no reset line, this still emits ACPI code for the reset GPIO. > Fix it by updating the check. > > Signed-off-by: Simon Glass > --- > > lib/acpi/acpi_device.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > Reviewed-by: Bin Meng
Re: [PATCH 17/32] x86: Show the interrupt pointer with 'irqinfo'
On Mon, Sep 28, 2020 at 12:26 PM Simon Glass wrote: > > It is useful for this command to show the address of the interrupt table. > Add support for this. > > Signed-off-by: Simon Glass > --- > > arch/x86/cpu/i386/interrupt.c| 14 +++--- > arch/x86/include/asm/interrupt.h | 17 + > arch/x86/lib/interrupts.c| 3 +++ > 3 files changed, 27 insertions(+), 7 deletions(-) > Reviewed-by: Bin Meng
Re: [PATCH 20/32] x86: acpi: Allow the SSDT to be empty
On Mon, Sep 28, 2020 at 12:26 PM Simon Glass wrote: > > If there is nothing in the SSDT we should not include it in the tables. > Update the implementation to check this. > > Signed-off-by: Simon Glass > --- > > arch/x86/lib/acpi_table.c | 22 +++--- > 1 file changed, 15 insertions(+), 7 deletions(-) > Reviewed-by: Bin Meng
Re: [PATCH 18/32] x86: sound: Correct error handling
On Mon, Sep 28, 2020 at 12:26 PM Simon Glass wrote: > > A few functions have changed to return pin numbers or I2C addresses. The > error checking for some of the callers is therefore wrong. Fix them. > > Signed-off-by: Simon Glass > --- > > drivers/sound/da7219.c| 4 ++-- > drivers/sound/max98357a.c | 2 +- > 2 files changed, 3 insertions(+), 3 deletions(-) > Reviewed-by: Bin Meng
Re: [PATCH 13/32] x86: Use if instead of #ifdef in write_tables()
On Mon, Sep 28, 2020 at 12:26 PM Simon Glass wrote: > > Use if() to remove the extra build path in this code. > > Signed-off-by: Simon Glass > --- > > arch/x86/lib/tables.c | 38 +++--- > 1 file changed, 19 insertions(+), 19 deletions(-) > Reviewed-by: Bin Meng
Re: [PATCH 16/32] x86: nhlt: Fix a few bugs in the table generation
On Mon, Sep 28, 2020 at 12:26 PM Simon Glass wrote: > > At present these tables do not have the correct header, and there is an > occasional incorrect value due to uninited data. Fix these bugs. > > Signed-off-by: Simon Glass > --- > > arch/x86/lib/acpi_nhlt.c | 4 +++- > 1 file changed, 3 insertions(+), 1 deletion(-) > Reviewed-by: Bin Meng
Re: [PATCH 14/32] x86: Allow putting some tables in the bloblist
On Mon, Sep 28, 2020 at 12:26 PM Simon Glass wrote: > > At present all tables are placed starting at address f in memory, and > can be up to 64KB in size. If the tables are very large, this may not > provide enough space. > > Also if the tables point to other tables (such as console log or a ramoops > area) then we must allocate other memory anyway. > > The bloblist is a nice place to put these tables since it is contiguous, > which makes it easy to reserve this memory for linux using the 820 tables. > > Add an option to put some of the tables in the bloblist. For SMBIOS and > ACPI, create suitable pointers from the f region to the new location > of the tables. > > Signed-off-by: Simon Glass > --- > > arch/x86/lib/tables.c | 46 --- > include/acpi/acpi_table.h | 10 + > lib/Kconfig | 9 > lib/acpi/acpi_table.c | 4 ++-- > 4 files changed, 64 insertions(+), 5 deletions(-) > Reviewed-by: Bin Meng
Re: [PATCH 15/32] x86: nhlt: Correct output of bytes and 16-bit data
On Mon, Sep 28, 2020 at 12:26 PM Simon Glass wrote: > > At present these functions are incorrect. Fix them and add some logging > and checking to avoid future problems. > > Signed-off-by: Simon Glass > --- > > arch/x86/lib/acpi_nhlt.c | 13 ++--- > 1 file changed, 10 insertions(+), 3 deletions(-) > Reviewed-by: Bin Meng
Re: [PATCH 12/32] x86: Move ROM_TABLE_ADDR into the C file
Hi Simon, On Mon, Sep 28, 2020 at 12:26 PM Simon Glass wrote: > > At present this is defined in the header file, along with a few related > defines. The code that used to need this has been removed. Move it into > the C file instead. > > Signed-off-by: Simon Glass > --- > > arch/x86/include/asm/tables.h | 8 > arch/x86/lib/tables.c | 8 > 2 files changed, 8 insertions(+), 8 deletions(-) > > diff --git a/arch/x86/include/asm/tables.h b/arch/x86/include/asm/tables.h > index bf66e79018e..ff15949bd47 100644 > --- a/arch/x86/include/asm/tables.h > +++ b/arch/x86/include/asm/tables.h > @@ -8,14 +8,6 @@ > > #include > > -#define ROM_TABLE_ADDR CONFIG_ROM_TABLE_ADDR > -#define ROM_TABLE_END (CONFIG_ROM_TABLE_ADDR + CONFIG_ROM_TABLE_SIZE - 1) > - > -#define ROM_TABLE_ALIGN1024 These macros are still referenced by arch/x86/lib/acpi.c. Am I missing something? > - > -/* SeaBIOS expects coreboot tables at address range 0x-0x1000 */ > -#define CB_TABLE_ADDR 0x800 > - > /** > * table_compute_checksum() - Compute a table checksum > * > diff --git a/arch/x86/lib/tables.c b/arch/x86/lib/tables.c > index 7099866a78a..43b61a7aeac 100644 > --- a/arch/x86/lib/tables.c > +++ b/arch/x86/lib/tables.c > @@ -13,6 +13,14 @@ > #include > #include > > +#define ROM_TABLE_ADDR CONFIG_ROM_TABLE_ADDR > +#define ROM_TABLE_END (CONFIG_ROM_TABLE_ADDR + CONFIG_ROM_TABLE_SIZE - 1) > + > +#define ROM_TABLE_ALIGN1024 > + > +/* SeaBIOS expects coreboot tables at address range 0x-0x1000 */ > +#define CB_TABLE_ADDR 0x800 > + > /** > * Function prototype to write a specific configuration table > * > -- Regards, Bin
Re: [PATCH 11/32] x86: coral: Correct max98357 file
Hi Simon,
On Mon, Sep 28, 2020 at 12:26 PM Simon Glass wrote:
>
> This somehow ended up as an empty file. Fix it.
>
> Signed-off-by: Simon Glass
> ---
>
> .../max98357-render-2ch-48khz-24b.dat | Bin 0 -> 116 bytes
> 1 file changed, 0 insertions(+), 0 deletions(-)
>
> diff --git a/board/google/chromebook_coral/max98357-render-2ch-48khz-24b.dat
> b/board/google/chromebook_coral/max98357-render-2ch-48khz-24b.dat
> index
> e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..b0b5b9ba648c4546f98e15e42356a5fc4af6bb27
> 100644
> GIT binary patch
> literal 116
> zcmZQzU|?WnWOx?=qy_%}|BnyXGahJUU??~MR0;$VT+Bccgqa+G1PJi6vnv28CMf>T
> R&%gk}Aix2{5
> literal 0
> HcmV?d1
>
> --
This patch seems not to be arriving on patchwork. Could you please
check what's wrong?
Regards,
Bin
Re: [PATCH 1/5] mips: start.S: Add Octeon boot header compatibility
> From: Stefan Roese > Date: Fri, 16 Oct 2020 15:08:46 +0200 > > Octeon has a specific boot header, when booted via SPI NOR, NAND or MMC. > Here the only 2 instructions are allowed in the first few bytes of the > image. And these instructions need to be one branch and a nop. This > patch adds the necessary nop after the nop, to that the common MIPS > image is compatible with this Octeon header. > > The tool to patch the Octeon boot header into the image will be send in > a follow-up patch. Since the moved instruction is no longer in a delay slot, you should probably remove the extra space before the instruction. Cheers, Mark > Signed-off-by: Stefan Roese > Cc: Aaron Williams > Cc: Chandrakala Chavva > Cc: Daniel Schwierzeck > --- > arch/mips/cpu/start.S | 8 +++- > 1 file changed, 7 insertions(+), 1 deletion(-) > > diff --git a/arch/mips/cpu/start.S b/arch/mips/cpu/start.S > index d0c412236d..6de2470cc2 100644 > --- a/arch/mips/cpu/start.S > +++ b/arch/mips/cpu/start.S > @@ -75,8 +75,13 @@ > > ENTRY(_start) > /* U-Boot entry point */ > + /* > + * Octeon needs special handling here, as the binary might be > + * patched to add a boot header for SPI, NAND or MMC booting. Only > + * one branch plus nop is allowed here. > + */ > b reset > - mtc0 zero, CP0_COUNT # clear cp0 count for most accurate boot timing > + nop > > #if defined(CONFIG_MIPS_INSERT_BOOT_CONFIG) > /* > @@ -123,6 +128,7 @@ ENTRY(_start) > #endif > > reset: > + mtc0 zero, CP0_COUNT # clear cp0 count for most accurate boot timing > #if __mips_isa_rev >= 6 > mfc0t0, CP0_CONFIG, 5 > and t0, t0, MIPS_CONF5_VP > -- > 2.28.0 > >
[PATCH 4/5] mips: octeon: bootoctlinux: Use gd->ram_size instead of ram_get_info()
Using ram_get_info() is complicated and does not work after relocation.
Now that gd->ram_size holds the full RAM size, let's use it instead and
remove the ram_get_size logic completely.
Signed-off-by: Stefan Roese
Cc: Aaron Williams
Cc: Chandrakala Chavva
Cc: Daniel Schwierzeck
---
arch/mips/mach-octeon/bootoctlinux.c | 21 +++--
1 file changed, 3 insertions(+), 18 deletions(-)
diff --git a/arch/mips/mach-octeon/bootoctlinux.c
b/arch/mips/mach-octeon/bootoctlinux.c
index 75d7e83bd7..26136902f3 100644
--- a/arch/mips/mach-octeon/bootoctlinux.c
+++ b/arch/mips/mach-octeon/bootoctlinux.c
@@ -9,7 +9,6 @@
#include
#include
#include
-#include
#include
#include
@@ -370,8 +369,6 @@ int do_bootoctlinux(struct cmd_tbl *cmdtp, int flag, int
argc,
struct cvmx_coremask avail_coremask;
int first_core;
int core;
- struct ram_info ram;
- struct udevice *dev;
const u64 *nmi_code;
int num_dwords;
u8 node_mask = 0x01;
@@ -470,19 +467,6 @@ int do_bootoctlinux(struct cmd_tbl *cmdtp, int flag, int
argc,
*/
cvmx_coremask_or(_to_run, _to_run, _mask);
- /* Get RAM size */
- ret = uclass_get_device(UCLASS_RAM, 0, );
- if (ret) {
- debug("DRAM init failed: %d\n", ret);
- return ret;
- }
-
- ret = ram_get_info(dev, );
- if (ret) {
- debug("Cannot get DRAM size: %d\n", ret);
- return ret;
- }
-
/*
* Load kernel ELF image, or try binary if ELF is not detected.
* This way the much smaller vmlinux.bin can also be started but
@@ -498,7 +482,7 @@ int do_bootoctlinux(struct cmd_tbl *cmdtp, int flag, int
argc,
/* Init bootmem list for Linux kernel booting */
if (!cvmx_bootmem_phy_mem_list_init(
- ram.size, OCTEON_RESERVED_LOW_MEM_SIZE,
+ gd->ram_size, OCTEON_RESERVED_LOW_MEM_SIZE,
(void *)CKSEG0ADDR(BOOTLOADER_BOOTMEM_DESC_SPACE))) {
printf("FATAL: Error initializing free memory list\n");
return 0;
@@ -517,7 +501,8 @@ int do_bootoctlinux(struct cmd_tbl *cmdtp, int flag, int
argc,
if (core == first_core)
cvmx_bootinfo_array[core].flags |= BOOT_FLAG_INIT_CORE;
- cvmx_bootinfo_array[core].dram_size = ram.size / (1024 * 1024);
+ cvmx_bootinfo_array[core].dram_size = gd->ram_size /
+ (1024 * 1024);
cvmx_bootinfo_array[core].dclock_hz = gd->mem_clk * 100;
cvmx_bootinfo_array[core].eclock_hz = gd->cpu_clk;
--
2.28.0
[PATCH 5/5] mips: octeon: tools: Add update_octeon_header tool
Add a tool to update or insert an Octeon specific header into the U-Boot
image. This is needed e.g. for booting via SPI NOR, eMMC and NAND.
While working on this, move enum cvmx_board_types_enum and
cvmx_board_type_to_string() to cvmx-bootloader.h and remove the
unreferenced (unsupported) board definition.
Signed-off-by: Stefan Roese
Cc: Aaron Williams
Cc: Chandrakala Chavva
Cc: Daniel Schwierzeck
---
.../mach-octeon/include/mach/cvmx-bootinfo.h | 222 -
.../include/mach/cvmx-bootloader.h| 172 +++
tools/Makefile| 3 +
tools/update_octeon_header.c | 450 ++
4 files changed, 625 insertions(+), 222 deletions(-)
create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-bootloader.h
create mode 100644 tools/update_octeon_header.c
diff --git a/arch/mips/mach-octeon/include/mach/cvmx-bootinfo.h
b/arch/mips/mach-octeon/include/mach/cvmx-bootinfo.h
index 337987178f..97438ff787 100644
--- a/arch/mips/mach-octeon/include/mach/cvmx-bootinfo.h
+++ b/arch/mips/mach-octeon/include/mach/cvmx-bootinfo.h
@@ -125,226 +125,4 @@ struct cvmx_bootinfo {
#endif /* (CVMX_BOOTINFO_MAJ_VER == 1) */
-/* Type defines for board and chip types */
-enum cvmx_board_types_enum {
- CVMX_BOARD_TYPE_NULL = 0,
- CVMX_BOARD_TYPE_SIM = 1,
- CVMX_BOARD_TYPE_EBT3000 = 2,
- CVMX_BOARD_TYPE_KODAMA = 3,
- CVMX_BOARD_TYPE_NIAGARA = 4,
- CVMX_BOARD_TYPE_NAC38 = 5, /* formerly NAO38 */
- CVMX_BOARD_TYPE_THUNDER = 6,
- CVMX_BOARD_TYPE_TRANTOR = 7,
- CVMX_BOARD_TYPE_EBH3000 = 8,
- CVMX_BOARD_TYPE_EBH3100 = 9,
- CVMX_BOARD_TYPE_HIKARI = 10,
- CVMX_BOARD_TYPE_CN3010_EVB_HS5 = 11,
- CVMX_BOARD_TYPE_CN3005_EVB_HS5 = 12,
- CVMX_BOARD_TYPE_KBP = 13,
- /* Deprecated, CVMX_BOARD_TYPE_CN3010_EVB_HS5 supports the CN3020 */
- CVMX_BOARD_TYPE_CN3020_EVB_HS5 = 14,
- CVMX_BOARD_TYPE_EBT5800 = 15,
- CVMX_BOARD_TYPE_NICPRO2 = 16,
- CVMX_BOARD_TYPE_EBH5600 = 17,
- CVMX_BOARD_TYPE_EBH5601 = 18,
- CVMX_BOARD_TYPE_EBH5200 = 19,
- CVMX_BOARD_TYPE_BBGW_REF = 20,
- CVMX_BOARD_TYPE_NIC_XLE_4G = 21,
- CVMX_BOARD_TYPE_EBT5600 = 22,
- CVMX_BOARD_TYPE_EBH5201 = 23,
- CVMX_BOARD_TYPE_EBT5200 = 24,
- CVMX_BOARD_TYPE_CB5600 = 25,
- CVMX_BOARD_TYPE_CB5601 = 26,
- CVMX_BOARD_TYPE_CB5200 = 27,
- /* Special 'generic' board type, supports many boards */
- CVMX_BOARD_TYPE_GENERIC = 28,
- CVMX_BOARD_TYPE_EBH5610 = 29,
- CVMX_BOARD_TYPE_LANAI2_A = 30,
- CVMX_BOARD_TYPE_LANAI2_U = 31,
- CVMX_BOARD_TYPE_EBB5600 = 32,
- CVMX_BOARD_TYPE_EBB6300 = 33,
- CVMX_BOARD_TYPE_NIC_XLE_10G = 34,
- CVMX_BOARD_TYPE_LANAI2_G = 35,
- CVMX_BOARD_TYPE_EBT5810 = 36,
- CVMX_BOARD_TYPE_NIC10E = 37,
- CVMX_BOARD_TYPE_EP6300C = 38,
- CVMX_BOARD_TYPE_EBB6800 = 39,
- CVMX_BOARD_TYPE_NIC4E = 40,
- CVMX_BOARD_TYPE_NIC2E = 41,
- CVMX_BOARD_TYPE_EBB6600 = 42,
- CVMX_BOARD_TYPE_REDWING = 43,
- CVMX_BOARD_TYPE_NIC68_4 = 44,
- CVMX_BOARD_TYPE_NIC10E_66 = 45,
- CVMX_BOARD_TYPE_MAX,
-
- /*
-* The range from CVMX_BOARD_TYPE_MAX to
-* CVMX_BOARD_TYPE_CUST_DEFINED_MIN is reserved for future
-* SDK use.
-*/
-
- /*
-* Set aside a range for customer boards. These numbers are managed
-* by Cavium.
-*/
- CVMX_BOARD_TYPE_CUST_DEFINED_MIN = 1,
- CVMX_BOARD_TYPE_CUST_WSX16 = 10001,
- CVMX_BOARD_TYPE_CUST_NS0216 = 10002,
- CVMX_BOARD_TYPE_CUST_NB5 = 10003,
- CVMX_BOARD_TYPE_CUST_WMR500 = 10004,
- CVMX_BOARD_TYPE_CUST_ITB101 = 10005,
- CVMX_BOARD_TYPE_CUST_NTE102 = 10006,
- CVMX_BOARD_TYPE_CUST_AGS103 = 10007,
- CVMX_BOARD_TYPE_CUST_GST104 = 10008,
- CVMX_BOARD_TYPE_CUST_GCT105 = 10009,
- CVMX_BOARD_TYPE_CUST_AGS106 = 10010,
- CVMX_BOARD_TYPE_CUST_SGM107 = 10011,
- CVMX_BOARD_TYPE_CUST_GCT108 = 10012,
- CVMX_BOARD_TYPE_CUST_AGS109 = 10013,
- CVMX_BOARD_TYPE_CUST_GCT110 = 10014,
- CVMX_BOARD_TYPE_CUST_L2_AIR_SENDER = 10015,
- CVMX_BOARD_TYPE_CUST_L2_AIR_RECEIVER = 10016,
- CVMX_BOARD_TYPE_CUST_L2_ACCTON2_TX = 10017,
- CVMX_BOARD_TYPE_CUST_L2_ACCTON2_RX = 10018,
- CVMX_BOARD_TYPE_CUST_L2_WSTRNSNIC_TX = 10019,
- CVMX_BOARD_TYPE_CUST_L2_WSTRNSNIC_RX = 10020,
- CVMX_BOARD_TYPE_CUST_L2_ZINWELL = 10021,
- CVMX_BOARD_TYPE_CUST_DEFINED_MAX = 2,
-
- /*
-* Set aside a range for customer private use. The SDK won't
-* use any numbers in this range.
-*/
- CVMX_BOARD_TYPE_CUST_PRIVATE_MIN = 20001,
- CVMX_BOARD_TYPE_UBNT_E100 = 20002,
- CVMX_BOARD_TYPE_CUST_DSR1000N = 20006,
- CVMX_BOARD_TYPE_KONTRON_S1901 = 21901,
- CVMX_BOARD_TYPE_CUST_PRIVATE_MAX = 3,
-
- /* The
[PATCH 3/5] mips: octeon: Report full DDR size in dram_init() to gd->ram_size
With this patch, gd->ram_size now holds to full RAM size detected by the
DDR init code. It introduces the get_effective_memsize() function to
report the maximum usable RAM size in U-Boot to the system instead.
Signed-off-by: Stefan Roese
Cc: Aaron Williams
Cc: Chandrakala Chavva
Cc: Daniel Schwierzeck
---
arch/mips/mach-octeon/dram.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/arch/mips/mach-octeon/dram.c b/arch/mips/mach-octeon/dram.c
index 6dc08e19da..4679260f17 100644
--- a/arch/mips/mach-octeon/dram.c
+++ b/arch/mips/mach-octeon/dram.c
@@ -33,7 +33,7 @@ int dram_init(void)
return ret;
}
- gd->ram_size = min_t(size_t, ram.size, UBOOT_RAM_SIZE_MAX);
+ gd->ram_size = ram.size;
debug("SDRAM base=%lx, size=%lx\n",
(unsigned long)ram.base, (unsigned long)ram.size);
} else {
@@ -72,6 +72,11 @@ void board_add_ram_info(int use_default)
}
}
+phys_size_t get_effective_memsize(void)
+{
+ return UBOOT_RAM_SIZE_MAX;
+}
+
ulong board_get_usable_ram_top(ulong total_size)
{
if (IS_ENABLED(CONFIG_RAM_OCTEON)) {
--
2.28.0
[PATCH 2/5] mips: octeon: Fix Octeon DDR driver to use the correct struct
Don't use "platdata_auto_alloc_size" but "priv_auto_alloc_size" instead
to auto allocate the private data struct, which is referenced via
dev_get_priv() in this driver. This fixes an ugly bug detected while
trying to boot via SPI NOR.
Signed-off-by: Stefan Roese
Cc: Aaron Williams
Cc: Chandrakala Chavva
Cc: Daniel Schwierzeck
---
drivers/ram/octeon/octeon_ddr.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/ram/octeon/octeon_ddr.c b/drivers/ram/octeon/octeon_ddr.c
index 757436b9d3..aaff9c3687 100644
--- a/drivers/ram/octeon/octeon_ddr.c
+++ b/drivers/ram/octeon/octeon_ddr.c
@@ -2724,5 +2724,5 @@ U_BOOT_DRIVER(octeon_ddr) = {
.of_match = octeon_ids,
.ops = _ops,
.probe = octeon_ddr_probe,
- .platdata_auto_alloc_size = sizeof(struct ddr_priv),
+ .priv_auto_alloc_size = sizeof(struct ddr_priv),
};
--
2.28.0
