On Sat, Nov 14, 2020 at 04:45:18AM +0100, Heinrich Schuchardt wrote:
> Provide a minimal test for the EFI_TCG2_PROTOCOL.
>
> Signed-off-by: Heinrich Schuchardt
> ---
> lib/efi_selftest/Makefile| 1 +
> lib/efi_selftest/efi_selftest_tcg2.c | 75
> 2 files
On 09.11.20 18:08, Mark Kettenis wrote:
>> From: Heinrich Schuchardt
>> Date: Mon, 9 Nov 2020 15:36:33 +0100
>>
>> On 09.11.20 14:51, Mark Kettenis wrote:
From: Paulo Alcantara
Date: Mon, 09 Nov 2020 10:24:08 -0300
Heinrich Schuchardt writes:
> On 09.11.20 00:58, Pau
On 11/13/20 3:52 PM, Daniel Kiper wrote:
> Hey,
>
>
> Here is the description (pseudocode) of the structures which will be
> used to store the log data.
>
> Anyway, I am aware that this is not specification per se.
Yes, you have caveats here. I'm sure that you either already know
or would lear
Provide a minimal test for the EFI_TCG2_PROTOCOL.
Signed-off-by: Heinrich Schuchardt
---
lib/efi_selftest/Makefile| 1 +
lib/efi_selftest/efi_selftest_tcg2.c | 75
2 files changed, 76 insertions(+)
create mode 100644 lib/efi_selftest/efi_selftest_tcg2.c
When setting up the EFI_RNG_PROTOCOL warning messages may be issued.
The messages should end with a newline.
Signed-off-by: Heinrich Schuchardt
---
lib/efi_loader/efi_rng.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/lib/efi_loader/efi_rng.c b/lib/efi_loader/efi_rng.c
In v2021.01-rc2 enabling CONFIG_FS_BTRFS=y produces:
x86_64-poky-linux-ld.bfd: fs/built-in.o: in function `hash_sha256':
u-boot/1_2021.01-rc2-r0/git/fs/btrfs/crypto/hash.c:25: undefined
reference to `sha256_starts'
x86_64-poky-linux-ld.bfd:
u-boot/1_2021.01-rc2-r0/git/fs/btrfs/crypto/hash.c
Hey,
This is next attempt to create firmware and bootloader log specification.
Due to high interest among industry it is an extension to the initial
bootloader log only specification. It takes into the account most of the
comments which I got up until now.
The goal is to pass all logs produced by
On 12/11/2020, 08:15, "Atish Patra" wrote:
On Tue, Nov 10, 2020 at 5:40 AM Bin Meng wrote:
>
> On Tue, Nov 10, 2020 at 6:46 PM Padmarao Begari
> wrote:
> >
> > Add device tree for Microchip PolarFire SoC Icicle Kit.
> >
> > Signed-off-by: Padmarao Begari
Since commit 690079767803 ("cros_ec: Support keyboard scanning with
EC_CMD_GET_NEXT_EVENT") the cros-ec-keyb driver has started using this
command, but the sandbox EC emulator does not recognize it and
continuously prints:
** Unknown EC command 0x67
This patch makes the sandbox driver send ba
The Microchip KSZ9477/KSZ9897/KSZ9567 7-Port Gigabit Ethernet Switches
support SGMII/RGMII/MII/RMII with register access via SPI or I2C.
This driver currently supports I2C register access but SPI register
access can be easily added at a later time.
This was tested with a KSZ9897S switch with an I
This patch series adds a driver for the Microchip 7-port
KSZ9477/KSZ9897/KSZ9567 GbE Switch.
This was tested on an IMX8MM board that has its FEC MAC RGMII connected
to the CPU uplink port of a KSZ9897 and I2C controlling the KSZ9897 registers.
I found that the UCLASS_ETH_PHY class appears appropr
commit 5fe419ef2a61 ("net: Add eth phy generic driver for shared MDIO")
added a UCLASS_ETH_PHY for Ethernet PHY devices to aid in connecting eth
devices to mii bus drivers. However the binding was only allowed for a phy
that was a child of the ethernet device which is fairly restrictive.
For a dev
According to the manpage of rand, it is recommended
to use random instead of rand. This commit updates
the function get_random_data to use random.
Reported-by: Coverity (CID: 312953)
Signed-off-by: Philippe Reynes
---
tools/image-host.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
You can disregard this patch, unless you think this is a good idea in general.
The patch caused the same problem on another 83xx of very similar design.
ATM, it looks like disabling the icache while executing in flash(turn of once
in RAM)
works for all boards.
Seems like something goes terribly w
In the function get_random_data, strerrno is called with
the variable ret (which is the return of the function
clock_gettime). It should be called with errnor. This
commit fixes this mistake.
Reported-by: Coverity (CID: 312956)
Signed-off-by: Philippe Reynes
---
tools/image-host.c | 2 +-
1 file
On 11/13/20 2:19 AM, Rick Chen wrote:
> Hi Sean
>
>>> I2C and SCCB previously shared defaults. However, SCCB needs OE_INV and
>>> IE_INV set, but I2C cannot have those bits set. This adds a separate
>>> default for SCCB.
>>>
>>> Signed-off-by: Sean Anderson
>>> Reported-by: Damien Le Moal
>>> --
I2C and SCCB previously shared defaults. However, SCCB needs OE_INV and
IE_INV set, but I2C cannot have those bits set. This adds a separate
default for SCCB.
Signed-off-by: Sean Anderson
Reported-by: Damien Le Moal
---
Changes in v2:
- Fix build error
drivers/pinctrl/pinctrl-kendryte.c | 11
This renames power domains to match the names on the k210 datasheet.
Signed-off-by: Sean Anderson
Reported-by: Damien Le Moal
Reviewed-by: Rick Chen
---
(no changes since v1)
.../pinctrl/kendryte,k210-fpioa.txt| 2 +-
drivers/pinctrl/pinctrl-kendryte.c
On Fri, 2020-11-13 at 20:47 +0900, Brad Kim wrote:
> Not s2 register, t1 register is correct
> Fortunately, it works because t1 register has a garbage value
>
> Signed-off-by: Brad Kim
> ---
> arch/riscv/cpu/start.S | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
Thanks for catching
Not s2 register, t1 register is correct
Fortunately, it works because t1 register has a garbage value
Signed-off-by: Brad Kim
---
arch/riscv/cpu/start.S | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
index bbc737ed9a..8589509e0
On 2020/10/31 上午2:20, Arnaud Patard (Rtp) wrote:
Kever Yang writes:
Hi Arnaud,
Thanks for your patch.
Please use module name as subject prefix instead of a file name,
eg. "rockchip: video: vop".
ok. will fix.
On 2020/10/27 下午9:21, Arnaud Patard (Rtp) wrote:
The current code
On 2020/11/10 下午6:09, Peter Robinson wrote:
Improve USB config so keyboard and USB-A ports work.
Signed-off-by: Peter Robinson
Reviewed-by: Kever Yang
Thanks,
- Kever
---
configs/pinebook-pro-rk3399_defconfig | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/config
On 2020/10/23 上午3:43, Alper Nebi Yasak wrote:
These files have a lot of code in common with their counterparts in
coreboot, especially in their earlier revisions:
U-Boot | coreboot
--|---
On 2020/10/28 上午5:15, Alper Nebi Yasak wrote:
Commit fe974716326c ("rockchip: rk3288: Allow setting up clocks in
U-Boot proper") fixes some clock issues when chainloading U-Boot on
rk3288 chromebooks. Part of that change is still available in veyron's
board_early_init_r() function. Since chain-
On 2020/10/28 上午5:15, Alper Nebi Yasak wrote:
It's possible to chainload U-Boot proper from the vendor firmware in
rk3399 chromebooks, but the way the vendor firmware sets up clocks is
somehow different than what U-Boot expects. This causes the display to
stay devoid of content even though vidc
Le 29/10/2020 à 18:27, Steven Lawrance a écrit :
This change sets the output (hardware) polarity register instead of the
input (software) polarity register for the bcm6858 LED controller. The
logic was inverted (a LED configued active high behaved as active low).
Signed-off-by: Steven Lawrance
Hi Pragnesh
> From: Pragnesh Patel [mailto:pragnesh.pa...@sifive.com]
> Sent: Wednesday, November 11, 2020 6:15 PM
> To: u-boot@lists.denx.de
> Cc: atish.pa...@wdc.com; palmerdabb...@google.com; bmeng...@gmail.com;
> paul.walms...@sifive.com; anup.pa...@wdc.com; sagar.ka...@sifive.com; Rick
> Ji
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