Re: [PATCH] doc: qemu-riscv: Fix opensbi build instructions
> From: U-Boot [mailto:u-boot-boun...@lists.denx.de] On Behalf Of Atish Patra > Sent: Wednesday, December 23, 2020 3:50 AM > To: U-Boot Mailing List > Cc: Atish Patra; Anup Patel; Bin Meng; Heinrich Schuchardt; Jagan Teki; Marek > Vasut; Simon Goldschmidt; David Abdurachmanov; Tom Rini > Subject: [PATCH] doc: qemu-riscv: Fix opensbi build instructions > > Latest opensbi uses generic platform for Qemu. Update the build > instructions. > > Signed-off-by: Atish Patra > --- > doc/board/emulation/qemu-riscv.rst | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) Reviewed-by: Rick Chen
Re: [PATCH v2 2/2] riscv: timer: Add support for an early timer
> From: Pragnesh Patel [mailto:pragnesh.pa...@sifive.com] > Sent: Tuesday, December 22, 2020 2:23 PM > To: u-boot@lists.denx.de > Cc: atish.pa...@wdc.com; palmerdabb...@google.com; bmeng...@gmail.com; > paul.walms...@sifive.com; anup.pa...@wdc.com; sagar.ka...@sifive.com; Rick > Jian-Zhi Chen(陳建志); pragnesh.pa...@openfive.com; Pragnesh Patel; Palmer > Dabbelt; Sean Anderson; Claudiu Beznea; Simon Glass > Subject: [PATCH v2 2/2] riscv: timer: Add support for an early timer > > Added support for timer_early_get_count() and timer_early_get_rate() > This is mostly useful in tracing. > > Signed-off-by: Pragnesh Patel > --- > > Changes in v2: > - make u-boot compile for qemu (include/configs/qemu-riscv.h) > > drivers/timer/andes_plmt_timer.c | 21 - > drivers/timer/riscv_timer.c| 21 - > drivers/timer/sifive_clint_timer.c | 21 - > include/configs/ax25-ae350.h | 5 + > include/configs/qemu-riscv.h | 5 + > include/configs/sifive-fu540.h | 5 + > 6 files changed, 75 insertions(+), 3 deletions(-) Reviewed-by: Rick Chen
Re: [PATCH v2 1/2] trace: select TIMER_EARLY to avoid infinite recursion
> From: Pragnesh Patel [mailto:pragnesh.pa...@sifive.com] > Sent: Tuesday, December 22, 2020 2:23 PM > To: u-boot@lists.denx.de > Cc: atish.pa...@wdc.com; palmerdabb...@google.com; bmeng...@gmail.com; > paul.walms...@sifive.com; anup.pa...@wdc.com; sagar.ka...@sifive.com; Rick > Jian-Zhi Chen(陳建志); pragnesh.pa...@openfive.com; Pragnesh Patel; Simon Glass; > Stefan Roese; Joao Marcos Costa; Reuben Dowle; Weijie Gao; Marcin > Juszkiewicz; Michael Walle; Marek Szyprowski; Keerthy > Subject: [PATCH v2 1/2] trace: select TIMER_EARLY to avoid infinite recursion > > When tracing functions is enabled this adds calls to > __cyg_profile_func_enter() and __cyg_profile_func_exit() to the traced > functions. > > __cyg_profile_func_enter() and __cyg_profile_func_exit() invoke > timer_get_us() to record the entry and exit time. > > initr_dm() will make gd->dm_root = NULL and gd->timer = NULL, so > timer_get_us() -> get_ticks() -> dm_timer_init() will lead to an > indefinite recursion. > > So select TIMER_EARLY when tracing got enabled. > > Signed-off-by: Pragnesh Patel > --- > > Changes in v2: > - new patch > > lib/Kconfig | 1 + > 1 file changed, 1 insertion(+) Reviewed-by: Rick Chen
Re: [PATCH v2] riscv: Add support for SPI on Kendryte K210
> This enables configs necessary for using SPI. The environment is saved to > the very end of SPI flash. This is unlikely to be overwritten unless the > entire flash is reprogrammed. > > This also supplies a default bootcommand. It loads an image and device tree > from the first partition of the MMC. This is a minimal/least effort > bootcmd, so suggestions (especially in the form of patches) are welcome. I > didn't set up distro boot because I think it is unlikely that any > general-purpose linux distros will ever be ported to this board. > > Signed-off-by: Sean Anderson > --- > Sorry for the late follow-up Jagen. > > This patch was previously part of > https://patchwork.ozlabs.org/project/uboot/list/?series=208443 > > Changes in v2: > - Add CONFIG_HUSH_PARSER to run the bootcmd > (In my haste I forgot to commit my changes) > > board/sipeed/maix/Kconfig | 16 ++ > configs/sipeed_maix_bitm_defconfig | 11 + > doc/board/sipeed/maix.rst | 319 - > include/configs/sipeed-maix.h | 7 +- > 4 files changed, 301 insertions(+), 52 deletions(-) Reviewed-by: Rick Chen
Re: [PATCH 2/2] video: remove unused include/mb862xx.h
On Tue, 29 Dec 2020 at 04:53, Heinrich Schuchardt wrote: > > CONFIG_VIDEO_MB862xx cannot be selected by any configuration. > So we can eliminate include/mb862xx.h. > > Signed-off-by: Heinrich Schuchardt > --- > board/socrates/socrates.c | 12 - > include/mb862xx.h | 101 -- > 2 files changed, 113 deletions(-) > delete mode 100644 include/mb862xx.h Reviewed-by: Simon Glass
Re: [PATCH 1/2] video: eliminate unused drivers/video/mb862xx.c
On Tue, 29 Dec 2020 at 04:53, Heinrich Schuchardt wrote: > > The mb862xx driver does not conform to the driver model and is unused. > Eliminate it. > > Signed-off-by: Heinrich Schuchardt > --- > drivers/video/Makefile | 1 - > drivers/video/mb862xx.c | 486 --- > scripts/config_whitelist.txt | 2 - > 3 files changed, 489 deletions(-) > delete mode 100644 drivers/video/mb862xx.c Reviewed-by: Simon Glass
Re: [PATCH] usb: xhci: Use only 32-bit accesses in nvme_writeq/nvme_readq
Hi Stefan,
On Wed, Dec 30, 2020 at 3:37 AM Stefan Agner wrote:
The tag is wrong. Should be nvme:
>
> There might be hardware configurations where 64-bit data accesses
> to NVMe registers are not supported properly. This patch removes
> the readq/writeq so always two 32-bit accesses are used to read/write
> 64-bit NVMe registers, similarly as it is done in Linux kernel.
>
> This patch fixes operation of NVMe devices on RPi4 Broadcom
> BCM2711 SoC based board, where the VL805 USB XHCI controller is
> connected to the PCIe Root Complex, which is attached to the system
> through the SCB bridge.
>
> Even though the architecture is 64-bit the PCIe BAR is 32-bit and likely
> the 64-bit wide register accesses initiated by the CPU are not properly
> translated to a sequence of 32-bit PCIe accesses.
> nvme_readq(), for example, always returns same value in upper and lower
> 32-bits, e.g. 0x3c033fff3c033fff which lead to NVMe devices to fail
> probing.
>
> This fix is analogous to commit 8e2ab05000ab ("usb: xhci: Use only
> 32-bit accesses in xhci_writeq/xhci_readq").
>
> Cc: Sylwester Nawrocki
> Cc: Zhikang Zhang
> Cc: Nicolas Saenz Julienne
> Cc: Matthias Brugger
> Signed-off-by: Stefan Agner
> ---
>
> drivers/nvme/nvme.h | 8
> 1 file changed, 8 deletions(-)
>
Otherwise, LGTM:
Reviewed-by: Bin Meng
RE: [PATCH 05/13] imx: imx8mn_evk: correct stack/malloc adress
> Subject: Re: [PATCH 05/13] imx: imx8mn_evk: correct stack/malloc adress
>
> On Mon, Dec 28, 2020 at 7:28 AM Peng Fan (OSS)
> wrote:
> >
> > From: Peng Fan
> >
> > Move SP to end of OCRAM space. Drop MALLOC_F to make it alloc from
> > stack space.
> >
> > Signed-off-by: Peng Fan
> > ---
> > drivers/power/power_i2c.c| 8
> > include/configs/imx8mn_evk.h | 9 +++--
> > 2 files changed, 7 insertions(+), 10 deletions(-)
> >
> > diff --git a/drivers/power/power_i2c.c b/drivers/power/power_i2c.c
> > index 5a0455e119..b67ac2f027 100644
> > --- a/drivers/power/power_i2c.c
> > +++ b/drivers/power/power_i2c.c
> > @@ -23,7 +23,7 @@ int pmic_reg_write(struct pmic *p, u32 reg, u32 val)
> >
> > if (check_reg(p, reg))
> > return -EINVAL;
> > -#if defined(CONFIG_DM_I2C)
> > +#if CONFIG_IS_ENABLED(DM_I2C)
> > struct udevice *dev;
> > int ret;
> >
> > @@ -67,7 +67,7 @@ int pmic_reg_write(struct pmic *p, u32 reg, u32 val)
> > return -EINVAL;
> > }
> >
> > -#if defined(CONFIG_DM_I2C)
> > +#if CONFIG_IS_ENABLED(DM_I2C)
> > return dm_i2c_write(dev, reg, buf, pmic_i2c_tx_num); #else
> > return i2c_write(pmic_i2c_addr, reg, 1, buf, pmic_i2c_tx_num);
> > @@ -83,7 +83,7 @@ int pmic_reg_read(struct pmic *p, u32 reg, u32 *val)
> > if (check_reg(p, reg))
> > return -EINVAL;
> >
> > -#if defined(CONFIG_DM_I2C)
> > +#if CONFIG_IS_ENABLED(DM_I2C)
> > struct udevice *dev;
> >
> > ret = i2c_get_chip_for_busnum(p->bus, pmic_i2c_addr, @@
> -131,7
> > +131,7 @@ int pmic_reg_read(struct pmic *p, u32 reg, u32 *val) int
> > pmic_probe(struct pmic *p) {
> > debug("Bus: %d PMIC:%s probed!\n", p->bus, p->name); -#if
> > defined(CONFIG_DM_I2C)
> > +#if CONFIG_IS_ENABLED(DM_I2C)
> > struct udevice *dev;
> > int ret;
> >
> > diff --git a/include/configs/imx8mn_evk.h
> > b/include/configs/imx8mn_evk.h index a6333085fe..61db244e98 100644
> > --- a/include/configs/imx8mn_evk.h
> > +++ b/include/configs/imx8mn_evk.h
> > @@ -20,17 +20,14 @@
> > (QSPI0_AMBA_BASE +
> CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR *
> > 512)
> >
> > #ifdef CONFIG_SPL_BUILD
> > -#define CONFIG_SPL_STACK 0x95fff0
> > -#define CONFIG_SPL_BSS_START_ADDR 0x0095
> > -#define CONFIG_SPL_BSS_MAX_SIZESZ_8K /* 8 KB
> */
> > +#define CONFIG_SPL_STACK 0x98
> > +#define CONFIG_SPL_BSS_START_ADDR 0x95
> > +#define CONFIG_SPL_BSS_MAX_SIZESZ_4K /* 8 KB
> */
>
> If ATF sits at 96 and CONFIG_SPL_BSS_START_ADDR starts at 0x95,
> 8K should fit with extra space. I think it should be able to go even larger.
>
> I took your patch and applied it to the Beacon 8mn kit and, I was able to set
> the max size to SZ_64K with CONFIG_SPL_BSS_START_ADDR set to
> 0x95
No need so large BSS area.
>
> The reference manual states that OCRAM starts at 91. What is located
> in the space between 91 and 95?
As you see, it is SPL, nothing else. But spl + ddr firmware is very large.
Regards,
Peng.
>
> > #define CONFIG_SYS_SPL_MALLOC_START0x4220
> > #define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K /* 512 KB */
> > #define CONFIG_SYS_ICACHE_OFF
> > #define CONFIG_SYS_DCACHE_OFF
> >
> > -/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
> > -#define CONFIG_MALLOC_F_ADDR 0x0094
> > -
> > /* For RAW image gives a error info not panic */ #define
> > CONFIG_SPL_ABORT_ON_RAW_IMAGE
> >
> > --
> > 2.28.0
> >
[PATCH v8 00/28] Add DM support for omap PWM backlight
The series was born from the need to manage the PWM backlight of the display connected to my beaglebone board. To hit the target, I had to develop drivers for PWM management which in turn relied on drivers for managing timers and clocks, all developed according to the driver model. My intention was to use the SoC-specific API only at strictly necessary points in the code. My previous patches for migrating the AM335x display driver to the driver model had required the implementation of additional functions outside the concerns of the driver, (settings for dividing the pixel clock rate, configuring the display DPLL rate, ) not being able to use the API of the related clock drivers. This series shouldn't have repeated the same kind of mistake. Furthermore, I also wanted to fix that kind of forced choice. Almost everything should have been accessible via the driver model API. In the series there are also some patches that could be submitted separately, but which I have however inserted to avoid applying future patches to incorporate them. With this last consideration, I hope I have convincingly justified the large number of patches in the series. The patch enabling address translation into a CPU physical address from device-tree even in case of crossing levels with #size-cells = <0>, is crucial for the series. The previous implementation was unable to perform the address translation required by the am33xx device tree. I tried to apply in a conservative way as few changes as possible and to verify the execution of all the tests already developed, as well as the new ones I added for the new feature. The patch series can be cleanly applied to the HEAD of the master which at the time of release points to ab865a8ee5c1a069f72a171270c02c99ccda7bfa commit (Merge tag 'u-boot-imx-20201227' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx). Changes in v8: - Imply CONFIG_TI_SYSC only if CONFIG_DM and CONFIG_OF_CONTROL are enabled. - Revert change on cm_t335_defconfig added on version 7 of the series. - Revert change on da850-evm-u-boot.dtsi. It was wrong and generated building errors. Changes in v7: - Not all OMAP2 platform need CONFIG_TI_SYSC. Set CONFIG_TI_SYSC as imply and disable it to fix building errors in: nokia_rx51_defconfig cm_t335_defconfig - Add gd_size_cells_0 macro to fix building errors for boards that do not use CONFIG_DM. - Add dm8168-evm-u-boot.dtsi to fix building errors for ti816x_evm_defconfig. - Add linux/err.h header in am335x-fb.c to fix building errors for brxre1_defconfig. - Fix building errors for: brppt1_mmc_defconfig brppt1_nand_defconfig brppt1_spi_defconfig brxre1_defconfig brsmarc1_defconfig Changes in v6: - Remove the 'am3-prcm' driver. - Add the 'simple-bus' compatible string to the prcm_clocks node. - Remove the 'am3-scm' driver. - Add the 'simple-bus' compatible string to the scm_clocks node. Changes in v5: - Create drivers/clk/ti directory. - Move the clk-ti-mux.c file to drivers/clk/ti and rename it clk-mux.c - Move the clk-ti-am3-dpll.c file to drivers/clk/ti with the name clk-am3-dpll.c. - Move the clk-ti-am3-dpll-x2.c file to drivers/clk/ti with the name clk-am3-dpll-x2.c. - Move the clk-ti.c file to drivers/clk/ti with the name clk.c. - Move the clk-ti.h file to drivers/clk/ti with the name clk.h. - Move the clk-ti-divider.c file to drivers/clk/ti with the name clk-divider.c. - Move the clk-ti-gate.c file to drivers/clk/ti with the name clk-gate.c. - Move the clk-ti-ctrl.c file to drivers/clk/ti with the name clk-ctrl.c. Changes in v4: - Include device_compat.h header for dev_xxx macros. - Remove a blank line at end of file arch/arm/dts/am33xx-l4.dtsi. - Update clk_round_rate description. - Add Sean Anderson review. - Include device_compat.h header for dev_xxx macros. - Include device_compat.h header for dev_xxx macros. - Fix compilation errors on the dev parameter of the dev_xx macros. - Include device_compat.h header for dev_xxx macros. - Fix compilation errors on the dev parameter of the dev_xx macros. - Include device_compat.h header for dev_xxx macros. - Include device_compat.h header for dev_xxx macros. - Fix compilation errors on the dev parameter of the dev_xx macros. - Include device_compat.h header for dev_xxx macros. - Add Sphinx documentation for dm_flags. - Convert GD_DM_FLG_* to enum. - Include device_compat.h header in test/dm/test-fdt.c for dev_xxx macros. - Include device_compat.h header for dev_xxx macros. - Include device_compat.h header for dev_xxx macros. - Include device_compat.h header for dev_xxx macros. - Add Simon Glass review. - Include device_compat.h header for dev_xxx macros. Changes in v3: - Remove doc/device-tree-bindings/clock/clock-bindings.txt. - Remove doc/device-tree-bindings/clock/ti,mux.txt. - Add to commit message the references to linux kernel dt binding documentation. - Remove doc/device-tree-bindings/clock/ti,dpll.txt. - Add to commit message the references to linux kernel
Re: [PATCH 2/8] spl: fit: Factor out FIT parsing and use a context struct
On 12/28/20 9:33 PM, Simon Glass wrote:
Hi Alex,
On Mon, 21 Dec 2020 at 15:24, Alex G. wrote:
On 12/21/20 2:23 PM, Simon Glass wrote:
Hi Alex,
On Mon, 21 Dec 2020 at 12:28, Alex G. wrote:
On 12/18/20 8:28 PM, Simon Glass wrote:
Hi Alexandru,
On Tue, 15 Dec 2020 at 17:09, Alexandru Gagniuc wrote:
The logical steps in spl_load_simple_fit() are difficult to follow.
I think the long comments, ifdefs, and ungodly number of variables
seriously affect the readability. In particular, it violates section 6
of the coding style, paragraphs (3), and (4).
The purpose of this patch is to improve the situation by
- Factoring out initialization and parsing to separate functions
- Reduce the number of variables by using a context structure
This change introduces no functional changes.
Signed-off-by: Alexandru Gagniuc
---
common/spl/spl_fit.c | 87 ++--
1 file changed, 60 insertions(+), 27 deletions(-)
This certainly looks a lot better although your email address does not
inspire confidence...
Don't worry. It doesn't bite.
Do you think you could look at creating a sandbox SPL test for this?
It should be possible to write it in C, set up a bit of data, call
your function and check the results.
I can look at it. I can't promise anything though, since this is the
first time I heard of the sandbox. Maybe doc knows more.
Yes, see doc/arch/sandbox.rst
test/dm/Makefile shows that only one test file is enabled for SPL, but
you can add more. Let me know if you need pointers.
These aliases might help, if you build into /tmp/b/ :
# Run a pytest on sandbox
# $1: Name of test to run (optional, else run all)
function pyt {
test/py/test.py -B sandbox --build-dir /tmp/b/sandbox ${1:+"-k $1"}
}
# Run a pytest on sandbox_spl
# $1: Name of test to run (optional, else run all SPL tests)
function pytspl {
local run=$1
[[ -z "$run" ]] && run=spl
test/py/test.py -B sandbox_spl --build-dir /tmp/b/sandbox_spl -k $run
}
You're thinking way ahead of where I am. I know how to build a board,
but I've never used the test infrastructure. After some fumbling, I
figured I'd try sandbox_spl:
$ test/py/test.py -B sandbox_spl --bd sandbox_spl --build
As you can imagine, it kept complaining about SDL. I've never used
environment variables with Kbuild, so using NO_SPL=1 seems unnatural.
But then why would we need SDL for testing an SPL build anyway? 'swig'
was missing too, but that was an easy fix.
Second try:
$ NO_SDL=1 test/py/test.py -B sandbox_spl --bd sandbox_spl \
--build
Went a bit better, but " 29 failed, 502 passed, 212 skipped". Is this
normal?
What I seem to be missing is how to connect this python to calling
spl_load_simple_fit(). In the real world, I'd build u-boot and feed it a
FIT image -- boots, okay.
Here's a suggestoin
- Write a function that calls the function to load a fit and does some
checks that it worked correct, e.g. by looking in memory
- put a call to that function in an SPL C test (as mentioned ealler)
I suppose you could also boot it, perhaps by switching sandbox to use
FIT to boot?
Hi Simon,
There seems to be a lot more to wrapping around spl_load_simple_fit().
We need populated spl_image_info spl_load_info structure. I'm not even
sure if the test code runs in SPL, or how to run it in SPL.
There are examples, and unfocused documentation on how to connect this
into u-boot proper. The current documentation and exampples are not
helping with what I was trying to accomplish. Unfortunately, I've spent
a week on this, and wasn't able to make any progress. I'm one guy who's
getting paid to ship a product. This test infrastructure is more tedious
than I anticipated, and I need to move on.
ALex
Re: [PATCH] common: board_f: fix to display wrong memory information
On 12/30/20 8:48 AM, Sean Anderson wrote:
> On 12/29/20 6:24 PM, Jaehoon Chung wrote:
>> When run meminfo command, it's displayed wrong memory information.
>> Because it's using gd->ram_size what didn't configure ram size.
>
> what -> which?
Will update
>
>>
>> On 4G RPI4 target
>> - Before
>> U-Boot> meminfo
>> DRAM: 948MiB
>> - After
>> U-Boot> meminfo
>> DRAM: 3.9GiB
>>
>> Signed-off-by: Jaehoon Chung
>> ---
>> common/board_f.c | 1 +
>> 1 file changed, 1 insertion(+)
>>
>> diff --git a/common/board_f.c b/common/board_f.c
>> index 9f441c44f176..96c675ea28e4 100644
>> --- a/common/board_f.c
>> +++ b/common/board_f.c
>> @@ -228,6 +228,7 @@ static int show_dram_config(void)
>> }
>> debug("\nDRAM: ");
>> + gd->ram_size = size;
>
> Shouldn't this be set by dram_init?
Yes, it's set by dram_init(), I didn't think about only rpi's problem.
I will check other target. (I have checked only RPI..) Thanks for pointing out.
Best Regards,
Jaehoon Chung
>
> --Sean
>
>> print_size(size, "");
>> board_add_ram_info(0);
>> putc('\n');
>>
>
>
Re: IMX8MM SD UHS support
On Tue, Dec 29, 2020 at 3:43 PM Jaehoon Chung wrote:
>
> Hi,
>
> On 12/30/20 8:21 AM, Tim Harvey wrote:
> > Greetings,
> >
> > In 50b1a69cee0d ("ARM: dts: imx8m: add UHS or HS400/HS400ES
> > properties") u-boot dt props were added to enable UHS and HS400 on a
> > couple of IMX8MM boards including the imx8mm-evk and in the subsequent
> > patch enabled the config items.
> >
> > While I see this making a huge difference for eMMC performance in
> > U-Boot I find it doesn't do anything for microSD performance.
> >
> > The issue appears to be that sd_get_capabilities() is not
> > appropriately detecting UHS speeds on cards that appropriately detect
> > as SDR104/DDR50 in Linux:
> >
> > u-boot=> mmc info
> > Device: FSL_SDHC
> > Manufacturer ID: 1b
> > OEM: 534d
> > Name: 0
> > Bus Speed: 5000
> > Mode: SD High Speed (50MHz)
> > card capabilities: widths [4, 1] modes [MMC legacy, SD High Speed (50MHz)]
> > no SDR104 detected for this card
>
> Did you enable MMC_UHS_SUPPORT?
yes, I'm using master so I also have your patch that enables that:
e601f0f9c966 ("configs: imx8m: enable eMMC HS400ES and SD UHS mode on EVK")
>
> > host capabilities: widths [4, 1] modes [MMC legacy, MMC High Speed
> > (26MHz), SD High Speed (50MHz), MMC High Speed (52MHz), UHS DDR50
> > (50MHz), UHS SDR104 (208MHz)]
> > Rd Block Len: 512
> > SD version 3.0
> > High Capacity: Yes
> > Capacity: 14.9 GiB
> > Bus Width: 4-bit
> > Erase Group Size: 512 Bytes
> >
> > The same card in Linux shows the following upon insertion and
> > performance tests show that it is operating at SDR104 speeds:
> > mmc1: new ultra high speed SDR104 SDHC card at address 0001
> >
> > I haven't found very good documentation on the SD switch settings to
> > understand if something is wrong in the U-Boot implementation of of
> > sd_get_capabilities() and I suppose it also could be an issue in
> > sdhci-esdhc-imx.c.
> >
> > Any ideas where to look?
> >
> > Anyone see SDR104 cards being detected properly for other platforms?
>
> I remembered that SDR104 was working fine before.
> Will check whether it's working or not with my other targets.
>
The way to check is simply do an 'mmc info' and see if the card
capabilities show SDR104 or DDR50 (depending on the capabilities of
your card)
Let me know what you find. Again, I'm seeing this with master on an
imx8mm-evk and the host shows those capabilities, its the card that
does not. The code in sd_get_capabilities() is ancient so I'm guessing
it may be out of date.
Thanks,
Tim
Re: [PATCH] common: board_f: fix to display wrong memory information
On 12/29/20 6:24 PM, Jaehoon Chung wrote:
When run meminfo command, it's displayed wrong memory information.
Because it's using gd->ram_size what didn't configure ram size.
what -> which?
On 4G RPI4 target
- Before
U-Boot> meminfo
DRAM: 948MiB
- After
U-Boot> meminfo
DRAM: 3.9GiB
Signed-off-by: Jaehoon Chung
---
common/board_f.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/common/board_f.c b/common/board_f.c
index 9f441c44f176..96c675ea28e4 100644
--- a/common/board_f.c
+++ b/common/board_f.c
@@ -228,6 +228,7 @@ static int show_dram_config(void)
}
debug("\nDRAM: ");
+ gd->ram_size = size;
Shouldn't this be set by dram_init?
--Sean
print_size(size, "");
board_add_ram_info(0);
putc('\n');
Re: IMX8MM SD UHS support
Hi,
On 12/30/20 8:21 AM, Tim Harvey wrote:
> Greetings,
>
> In 50b1a69cee0d ("ARM: dts: imx8m: add UHS or HS400/HS400ES
> properties") u-boot dt props were added to enable UHS and HS400 on a
> couple of IMX8MM boards including the imx8mm-evk and in the subsequent
> patch enabled the config items.
>
> While I see this making a huge difference for eMMC performance in
> U-Boot I find it doesn't do anything for microSD performance.
>
> The issue appears to be that sd_get_capabilities() is not
> appropriately detecting UHS speeds on cards that appropriately detect
> as SDR104/DDR50 in Linux:
>
> u-boot=> mmc info
> Device: FSL_SDHC
> Manufacturer ID: 1b
> OEM: 534d
> Name: 0
> Bus Speed: 5000
> Mode: SD High Speed (50MHz)
> card capabilities: widths [4, 1] modes [MMC legacy, SD High Speed (50MHz)]
> no SDR104 detected for this card
Did you enable MMC_UHS_SUPPORT?
> host capabilities: widths [4, 1] modes [MMC legacy, MMC High Speed
> (26MHz), SD High Speed (50MHz), MMC High Speed (52MHz), UHS DDR50
> (50MHz), UHS SDR104 (208MHz)]
> Rd Block Len: 512
> SD version 3.0
> High Capacity: Yes
> Capacity: 14.9 GiB
> Bus Width: 4-bit
> Erase Group Size: 512 Bytes
>
> The same card in Linux shows the following upon insertion and
> performance tests show that it is operating at SDR104 speeds:
> mmc1: new ultra high speed SDR104 SDHC card at address 0001
>
> I haven't found very good documentation on the SD switch settings to
> understand if something is wrong in the U-Boot implementation of of
> sd_get_capabilities() and I suppose it also could be an issue in
> sdhci-esdhc-imx.c.
>
> Any ideas where to look?
>
> Anyone see SDR104 cards being detected properly for other platforms?
I remembered that SDR104 was working fine before.
Will check whether it's working or not with my other targets.
Best Regards,
Jaehoon Chung
>
> Best regards,
>
> Tim
>
[PATCH] common: board_f: fix to display wrong memory information
When run meminfo command, it's displayed wrong memory information.
Because it's using gd->ram_size what didn't configure ram size.
On 4G RPI4 target
- Before
U-Boot> meminfo
DRAM: 948MiB
- After
U-Boot> meminfo
DRAM: 3.9GiB
Signed-off-by: Jaehoon Chung
---
common/board_f.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/common/board_f.c b/common/board_f.c
index 9f441c44f176..96c675ea28e4 100644
--- a/common/board_f.c
+++ b/common/board_f.c
@@ -228,6 +228,7 @@ static int show_dram_config(void)
}
debug("\nDRAM: ");
+ gd->ram_size = size;
print_size(size, "");
board_add_ram_info(0);
putc('\n');
--
2.29.0
IMX8MM SD UHS support
Greetings,
In 50b1a69cee0d ("ARM: dts: imx8m: add UHS or HS400/HS400ES
properties") u-boot dt props were added to enable UHS and HS400 on a
couple of IMX8MM boards including the imx8mm-evk and in the subsequent
patch enabled the config items.
While I see this making a huge difference for eMMC performance in
U-Boot I find it doesn't do anything for microSD performance.
The issue appears to be that sd_get_capabilities() is not
appropriately detecting UHS speeds on cards that appropriately detect
as SDR104/DDR50 in Linux:
u-boot=> mmc info
Device: FSL_SDHC
Manufacturer ID: 1b
OEM: 534d
Name: 0
Bus Speed: 5000
Mode: SD High Speed (50MHz)
card capabilities: widths [4, 1] modes [MMC legacy, SD High Speed (50MHz)]
no SDR104 detected for this card
host capabilities: widths [4, 1] modes [MMC legacy, MMC High Speed
(26MHz), SD High Speed (50MHz), MMC High Speed (52MHz), UHS DDR50
(50MHz), UHS SDR104 (208MHz)]
Rd Block Len: 512
SD version 3.0
High Capacity: Yes
Capacity: 14.9 GiB
Bus Width: 4-bit
Erase Group Size: 512 Bytes
The same card in Linux shows the following upon insertion and
performance tests show that it is operating at SDR104 speeds:
mmc1: new ultra high speed SDR104 SDHC card at address 0001
I haven't found very good documentation on the SD switch settings to
understand if something is wrong in the U-Boot implementation of of
sd_get_capabilities() and I suppose it also could be an issue in
sdhci-esdhc-imx.c.
Any ideas where to look?
Anyone see SDR104 cards being detected properly for other platforms?
Best regards,
Tim
[PATCH v8 28/28] board: ti: am335x-ice: get CDCE913 clock device
With support for other clock drivers, the potentially supported CDCE913 device can no longer be probed without specifying its DT node name. Signed-off-by: Dario Binacchi --- (no changes since v1) board/ti/am335x/board.c | 2 +- board/ti/am43xx/board.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c index 984cc5e3ba..e1f64859cf 100644 --- a/board/ti/am335x/board.c +++ b/board/ti/am335x/board.c @@ -879,7 +879,7 @@ int board_late_init(void) } /* Just probe the potentially supported cdce913 device */ - uclass_get_device(UCLASS_CLK, 0, ); + uclass_get_device_by_name(UCLASS_CLK, "cdce913@65", ); return 0; } diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c index de49590031..62ed37cb48 100644 --- a/board/ti/am43xx/board.c +++ b/board/ti/am43xx/board.c @@ -744,7 +744,7 @@ int board_late_init(void) #endif /* Just probe the potentially supported cdce913 device */ - uclass_get_device(UCLASS_CLK, 0, ); + uclass_get_device_by_name(UCLASS_CLK, "cdce913@65", ); return 0; } -- 2.17.1
[PATCH v8 27/28] video: omap: move drivers to 'ti' directory
Add drivers/video/ti/ folder and move all TI's code in this folder for
better maintenance.
Signed-off-by: Dario Binacchi
---
(no changes since v7)
Changes in v7:
- Fix building errors for:
brppt1_mmc_defconfig
brppt1_nand_defconfig
brppt1_spi_defconfig
brxre1_defconfig
brsmarc1_defconfig
board/BuR/common/bur_common.h | 2 +-
board/BuR/common/common.c | 2 +-
drivers/video/Kconfig | 5 +
drivers/video/Makefile| 4 +---
drivers/video/ti/Kconfig | 8
drivers/video/ti/Makefile | 10 ++
drivers/video/{ => ti}/am335x-fb.c| 0
drivers/video/{ => ti}/am335x-fb.h| 0
drivers/video/{ => ti}/tilcdc-panel.c | 0
drivers/video/{ => ti}/tilcdc-panel.h | 0
drivers/video/{ => ti}/tilcdc.c | 0
drivers/video/{ => ti}/tilcdc.h | 0
12 files changed, 22 insertions(+), 9 deletions(-)
create mode 100644 drivers/video/ti/Kconfig
create mode 100644 drivers/video/ti/Makefile
rename drivers/video/{ => ti}/am335x-fb.c (100%)
rename drivers/video/{ => ti}/am335x-fb.h (100%)
rename drivers/video/{ => ti}/tilcdc-panel.c (100%)
rename drivers/video/{ => ti}/tilcdc-panel.h (100%)
rename drivers/video/{ => ti}/tilcdc.c (100%)
rename drivers/video/{ => ti}/tilcdc.h (100%)
diff --git a/board/BuR/common/bur_common.h b/board/BuR/common/bur_common.h
index c64ebe93b0..79c9af1466 100644
--- a/board/BuR/common/bur_common.h
+++ b/board/BuR/common/bur_common.h
@@ -12,7 +12,7 @@
#define _BUR_COMMON_H_
#if !CONFIG_IS_ENABLED(DM_VIDEO)
-#include <../../../drivers/video/am335x-fb.h>
+#include <../../../drivers/video/ti/am335x-fb.h>
int load_lcdtiming(struct am335x_lcdpanel *panel);
#endif
diff --git a/board/BuR/common/common.c b/board/BuR/common/common.c
index 0a5104a48f..f676d7baa6 100644
--- a/board/BuR/common/common.c
+++ b/board/BuR/common/common.c
@@ -27,7 +27,7 @@ DECLARE_GLOBAL_DATA_PTR;
#include
#include
#include
-#include "../../../drivers/video/am335x-fb.h"
+#include "../../../drivers/video/ti/am335x-fb.h"
void lcdbacklight(int on)
{
diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index 998271b9b6..758aab37e0 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -546,10 +546,7 @@ config ATMEL_HLCD
help
HLCDC supports video output to an attached LCD panel.
-config AM335X_LCD
- bool "Enable AM335x video support"
- help
- Supports video output to an attached LCD panel.
+source "drivers/video/ti/Kconfig"
config LOGICORE_DP_TX
bool "Enable Logicore DP TX driver"
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index 29f3434f7c..51b545ed83 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -16,15 +16,13 @@ obj-$(CONFIG_DM_VIDEO) += video-uclass.o vidconsole-uclass.o
obj-$(CONFIG_DM_VIDEO) += video_bmp.o
obj-$(CONFIG_PANEL) += panel-uclass.o
obj-$(CONFIG_SIMPLE_PANEL) += simple_panel.o
-obj-$(CONFIG_AM335X_LCD) += tilcdc.o tilcdc-panel.o
-else
-obj-$(CONFIG_AM335X_LCD) += am335x-fb.o
endif
obj-${CONFIG_EXYNOS_FB} += exynos/
obj-${CONFIG_VIDEO_ROCKCHIP} += rockchip/
obj-${CONFIG_VIDEO_STM32} += stm32/
obj-${CONFIG_VIDEO_TEGRA124} += tegra124/
+obj-y += ti/
obj-$(CONFIG_ATI_RADEON_FB) += ati_radeon_fb.o videomodes.o
obj-$(CONFIG_ATMEL_HLCD) += atmel_hlcdfb.o
diff --git a/drivers/video/ti/Kconfig b/drivers/video/ti/Kconfig
new file mode 100644
index 00..3081e9e8c0
--- /dev/null
+++ b/drivers/video/ti/Kconfig
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2020 Dario Binacchi
+#
+config AM335X_LCD
+ bool "Enable AM335x video support"
+ help
+ Supports video output to an attached LCD panel.
diff --git a/drivers/video/ti/Makefile b/drivers/video/ti/Makefile
new file mode 100644
index 00..d59216
--- /dev/null
+++ b/drivers/video/ti/Makefile
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2020 Dario Binacchi
+#
+
+ifdef CONFIG_DM_VIDEO
+obj-$(CONFIG_AM335X_LCD) += tilcdc.o tilcdc-panel.o
+else
+obj-$(CONFIG_AM335X_LCD) += am335x-fb.o
+endif
diff --git a/drivers/video/am335x-fb.c b/drivers/video/ti/am335x-fb.c
similarity index 100%
rename from drivers/video/am335x-fb.c
rename to drivers/video/ti/am335x-fb.c
diff --git a/drivers/video/am335x-fb.h b/drivers/video/ti/am335x-fb.h
similarity index 100%
rename from drivers/video/am335x-fb.h
rename to drivers/video/ti/am335x-fb.h
diff --git a/drivers/video/tilcdc-panel.c b/drivers/video/ti/tilcdc-panel.c
similarity index 100%
rename from drivers/video/tilcdc-panel.c
rename to drivers/video/ti/tilcdc-panel.c
diff --git a/drivers/video/tilcdc-panel.h b/drivers/video/ti/tilcdc-panel.h
similarity index 100%
rename from drivers/video/tilcdc-panel.h
rename to drivers/video/ti/tilcdc-panel.h
diff --git a/drivers/video/tilcdc.c b/drivers/video/ti/tilcdc.c
similarity index 100%
rename from drivers/video/tilcdc.c
rename to
[PATCH v8 25/28] video: omap: set LCD clock rate through DM API
The patch configures the display DPLL using the functions provided by
the driver model API for the clock. The device tree contains everything
needed to get the DPLL clock. The round rate function developed for
calculating the DPLL multiplier and divisor and the platform routines
for accessing the DPLL registers are removed from the LCD driver code
because they are implemented inside the DPLL clock driver.
Signed-off-by: Dario Binacchi
---
(no changes since v3)
Changes in v3:
- Add clk.h header.
- Fix an error code returned by the probe function.
drivers/video/am335x-fb.c | 129 ++
1 file changed, 103 insertions(+), 26 deletions(-)
diff --git a/drivers/video/am335x-fb.c b/drivers/video/am335x-fb.c
index dc959baa27..a0a635cc29 100644
--- a/drivers/video/am335x-fb.c
+++ b/drivers/video/am335x-fb.c
@@ -12,6 +12,7 @@
* - starts output DMA from gd->fb_base buffer
*/
#include
+#include
#include
#include
#include
@@ -112,6 +113,27 @@ struct am335x_lcdhw {
unsigned intclkc_reset; /* 0x70 */
};
+DECLARE_GLOBAL_DATA_PTR;
+
+#if !CONFIG_IS_ENABLED(DM_VIDEO)
+
+#if !defined(LCD_CNTL_BASE)
+#error "hw-base address of LCD-Controller (LCD_CNTL_BASE) not defined!"
+#endif
+
+/* Macro definitions */
+#define FBSIZE(x) (((x)->hactive * (x)->vactive * (x)->bpp) >> 3)
+
+#define LCDC_RASTER_TIMING_2_INVMASK(x)((x) & GENMASK(25, 20))
+
+static struct am335x_lcdhw *lcdhw = (void *)LCD_CNTL_BASE;
+
+int lcd_get_size(int *line_length)
+{
+ *line_length = (panel_info.vl_col * NBITS(panel_info.vl_bpix)) / 8;
+ return *line_length * panel_info.vl_row + 0x20;
+}
+
struct dpll_data {
unsigned long rounded_rate;
u16 rounded_m;
@@ -119,8 +141,6 @@ struct dpll_data {
u8 rounded_div;
};
-DECLARE_GLOBAL_DATA_PTR;
-
/**
* am335x_dpll_round_rate() - Round a target rate for an OMAP DPLL
*
@@ -199,25 +219,6 @@ static ulong am335x_fb_set_pixel_clk_rate(struct
am335x_lcdhw *regs, ulong rate)
return round_rate;
}
-#if !CONFIG_IS_ENABLED(DM_VIDEO)
-
-#if !defined(LCD_CNTL_BASE)
-#error "hw-base address of LCD-Controller (LCD_CNTL_BASE) not defined!"
-#endif
-
-/* Macro definitions */
-#define FBSIZE(x) (((x)->hactive * (x)->vactive * (x)->bpp) >> 3)
-
-#define LCDC_RASTER_TIMING_2_INVMASK(x)((x) & GENMASK(25, 20))
-
-static struct am335x_lcdhw *lcdhw = (void *)LCD_CNTL_BASE;
-
-int lcd_get_size(int *line_length)
-{
- *line_length = (panel_info.vl_col * NBITS(panel_info.vl_bpix)) / 8;
- return *line_length * panel_info.vl_row + 0x20;
-}
-
int am335xfb_init(struct am335x_lcdpanel *panel)
{
u32 raster_ctrl = 0;
@@ -335,14 +336,58 @@ enum {
struct am335x_fb_priv {
struct am335x_lcdhw *regs;
+ struct clk gclk;
+ struct clk dpll_m2_clk;
};
+static ulong tilcdc_set_pixel_clk_rate(struct udevice *dev, ulong rate)
+{
+ struct am335x_fb_priv *priv = dev_get_priv(dev);
+ struct am335x_lcdhw *regs = priv->regs;
+ ulong mult_rate, mult_round_rate, best_err, err;
+ u32 v;
+ int div, i;
+
+ best_err = rate;
+ div = 0;
+ for (i = 2; i <= 255; i++) {
+ mult_rate = rate * i;
+ mult_round_rate = clk_round_rate(>gclk, mult_rate);
+ if (IS_ERR_VALUE(mult_round_rate))
+ return mult_round_rate;
+
+ err = mult_rate - mult_round_rate;
+ if (err < best_err) {
+ best_err = err;
+ div = i;
+ if (err == 0)
+ break;
+ }
+ }
+
+ if (div == 0) {
+ dev_err(dev, "failed to find a divisor\n");
+ return -EFAULT;
+ }
+
+ mult_rate = clk_set_rate(>gclk, rate * div);
+ v = readl(>ctrl) & ~LCDC_CTRL_CLK_DIVISOR_MASK;
+ v |= LCDC_CTRL_CLK_DIVISOR(div);
+ writel(v, >ctrl);
+ rate = mult_rate / div;
+ dev_dbg(dev, "rate=%ld, div=%d, err=%ld\n", rate, div, err);
+ return rate;
+}
+
static int am335x_fb_remove(struct udevice *dev)
{
struct video_uc_platdata *uc_plat = dev_get_uclass_platdata(dev);
+ struct am335x_fb_priv *priv = dev_get_priv(dev);
uc_plat->base -= 0x20;
uc_plat->size += 0x20;
+ clk_release_all(>gclk, 1);
+ clk_release_all(>dpll_m2_clk, 1);
return 0;
}
@@ -352,10 +397,10 @@ static int am335x_fb_probe(struct udevice *dev)
struct video_priv *uc_priv = dev_get_uclass_priv(dev);
struct am335x_fb_priv *priv = dev_get_priv(dev);
struct am335x_lcdhw *regs = priv->regs;
- struct udevice *panel;
+ struct udevice *panel, *clk_dev;
struct tilcdc_panel_info info;
struct display_timing timing;
- struct cm_dpll *const cmdpll = (struct cm_dpll *)CM_DPLL;
+ ulong rate;
u32 reg;
int err;
@@
[PATCH v8 26/28] video: omap: split the legacy code from the DM code
The schedule for deprecating the features of the pre-driver-model puts
2019.17 as the deadline for the video subsystem. Furthermore, the latest
patches applied to the am335x-fb.c module have decreased the amount of
code shared with the pre-driver-model implementation. Splitting the two
implementations into two modules improves the readability of the code
and will make it easier to drop the pre-driver-model code.
I have not created a header file with the data structures and the
constants for accessing the LCD controller registers, but I preferred to
keep them inside the two c modules. This is a code replication until the
pre-driver-model version is dropped.
Signed-off-by: Dario Binacchi
---
(no changes since v7)
Changes in v7:
- Add linux/err.h header in am335x-fb.c to fix building errors for
brxre1_defconfig.
Changes in v4:
- Include device_compat.h header for dev_xxx macros.
drivers/video/Makefile | 5 +-
drivers/video/am335x-fb.c| 335 ---
drivers/video/am335x-fb.h| 35 ---
drivers/video/tilcdc-panel.c | 2 +-
drivers/video/tilcdc-panel.h | 2 +-
drivers/video/tilcdc.c | 425 +++
drivers/video/tilcdc.h | 38
7 files changed, 468 insertions(+), 374 deletions(-)
create mode 100644 drivers/video/tilcdc.c
create mode 100644 drivers/video/tilcdc.h
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index 132a63ecea..29f3434f7c 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -16,7 +16,9 @@ obj-$(CONFIG_DM_VIDEO) += video-uclass.o vidconsole-uclass.o
obj-$(CONFIG_DM_VIDEO) += video_bmp.o
obj-$(CONFIG_PANEL) += panel-uclass.o
obj-$(CONFIG_SIMPLE_PANEL) += simple_panel.o
-obj-$(CONFIG_AM335X_LCD) += tilcdc-panel.o
+obj-$(CONFIG_AM335X_LCD) += tilcdc.o tilcdc-panel.o
+else
+obj-$(CONFIG_AM335X_LCD) += am335x-fb.o
endif
obj-${CONFIG_EXYNOS_FB} += exynos/
@@ -24,7 +26,6 @@ obj-${CONFIG_VIDEO_ROCKCHIP} += rockchip/
obj-${CONFIG_VIDEO_STM32} += stm32/
obj-${CONFIG_VIDEO_TEGRA124} += tegra124/
-obj-$(CONFIG_AM335X_LCD) += am335x-fb.o
obj-$(CONFIG_ATI_RADEON_FB) += ati_radeon_fb.o videomodes.o
obj-$(CONFIG_ATMEL_HLCD) += atmel_hlcdfb.o
obj-$(CONFIG_ATMEL_LCD) += atmel_lcdfb.o
diff --git a/drivers/video/am335x-fb.c b/drivers/video/am335x-fb.c
index a0a635cc29..5fa6f794ec 100644
--- a/drivers/video/am335x-fb.c
+++ b/drivers/video/am335x-fb.c
@@ -12,22 +12,16 @@
* - starts output DMA from gd->fb_base buffer
*/
#include
-#include
-#include
#include
#include
-#include
-#include
#include
#include
#include
#include
#include
-#include
#include
#include
#include "am335x-fb.h"
-#include "tilcdc-panel.h"
#define LCDC_FMAX 2
@@ -115,8 +109,6 @@ struct am335x_lcdhw {
DECLARE_GLOBAL_DATA_PTR;
-#if !CONFIG_IS_ENABLED(DM_VIDEO)
-
#if !defined(LCD_CNTL_BASE)
#error "hw-base address of LCD-Controller (LCD_CNTL_BASE) not defined!"
#endif
@@ -323,330 +315,3 @@ int am335xfb_init(struct am335x_lcdpanel *panel)
return 0;
}
-
-#else /* CONFIG_DM_VIDEO */
-
-#define FBSIZE(t, p) (((t).hactive.typ * (t).vactive.typ * (p).bpp) >> 3)
-
-enum {
- LCD_MAX_WIDTH = 2048,
- LCD_MAX_HEIGHT = 2048,
- LCD_MAX_LOG2_BPP= VIDEO_BPP32,
-};
-
-struct am335x_fb_priv {
- struct am335x_lcdhw *regs;
- struct clk gclk;
- struct clk dpll_m2_clk;
-};
-
-static ulong tilcdc_set_pixel_clk_rate(struct udevice *dev, ulong rate)
-{
- struct am335x_fb_priv *priv = dev_get_priv(dev);
- struct am335x_lcdhw *regs = priv->regs;
- ulong mult_rate, mult_round_rate, best_err, err;
- u32 v;
- int div, i;
-
- best_err = rate;
- div = 0;
- for (i = 2; i <= 255; i++) {
- mult_rate = rate * i;
- mult_round_rate = clk_round_rate(>gclk, mult_rate);
- if (IS_ERR_VALUE(mult_round_rate))
- return mult_round_rate;
-
- err = mult_rate - mult_round_rate;
- if (err < best_err) {
- best_err = err;
- div = i;
- if (err == 0)
- break;
- }
- }
-
- if (div == 0) {
- dev_err(dev, "failed to find a divisor\n");
- return -EFAULT;
- }
-
- mult_rate = clk_set_rate(>gclk, rate * div);
- v = readl(>ctrl) & ~LCDC_CTRL_CLK_DIVISOR_MASK;
- v |= LCDC_CTRL_CLK_DIVISOR(div);
- writel(v, >ctrl);
- rate = mult_rate / div;
- dev_dbg(dev, "rate=%ld, div=%d, err=%ld\n", rate, div, err);
- return rate;
-}
-
-static int am335x_fb_remove(struct udevice *dev)
-{
- struct video_uc_platdata *uc_plat = dev_get_uclass_platdata(dev);
- struct am335x_fb_priv *priv = dev_get_priv(dev);
-
- uc_plat->base -= 0x20;
- uc_plat->size += 0x20;
- clk_release_all(>gclk,
[PATCH v8 23/28] video: omap: add panel driver
The previous version of am335x-fb.c contained the functionalities of two
drivers that this patch has split. It was a video type driver that used
the same registration compatible string that now registers a panel type
driver. The proof of this is that two compatible strings were referred
to within the same driver.
There are now two drivers, each with its own compatible string,
functions and API.
Furthermore, the panel driver, in addition to decoding the display
timings, is now also able to manage the backlight.
Signed-off-by: Dario Binacchi
Reviewed-by: Simon Glass
---
Changes in v8:
- Revert change on da850-evm-u-boot.dtsi. It was wrong and generated building
errors.
Changes in v4:
- Include device_compat.h header for dev_xxx macros.
- Add Simon Glass review.
Changes in v3:
- Update the DTS lcdc node of the am335x boards because of the
am33xx.dtsi resynced with Linux 5.9-rc7.
arch/arm/dts/am335x-brppt1-mmc.dts | 17 +-
arch/arm/dts/am335x-brppt1-nand.dts | 17 +-
arch/arm/dts/am335x-brppt1-spi.dts | 17 +-
arch/arm/dts/am335x-brsmarc1.dts | 20 +-
arch/arm/dts/am335x-brxre1.dts | 21 +-
arch/arm/dts/am335x-evm-u-boot.dtsi | 15 +-
arch/arm/dts/am335x-evmsk-u-boot.dtsi| 14 +-
arch/arm/dts/am335x-guardian-u-boot.dtsi | 18 +-
arch/arm/dts/am335x-pdu001-u-boot.dtsi | 18 +-
arch/arm/dts/am335x-pxm50-u-boot.dtsi| 14 +-
arch/arm/dts/am335x-rut-u-boot.dtsi | 14 +-
drivers/video/Makefile | 1 +
drivers/video/am335x-fb.c| 255 ++-
drivers/video/am335x-fb.h| 31 +++
drivers/video/tilcdc-panel.c | 172 +++
drivers/video/tilcdc-panel.h | 14 ++
16 files changed, 464 insertions(+), 194 deletions(-)
create mode 100644 drivers/video/tilcdc-panel.c
create mode 100644 drivers/video/tilcdc-panel.h
diff --git a/arch/arm/dts/am335x-brppt1-mmc.dts
b/arch/arm/dts/am335x-brppt1-mmc.dts
index 6f919711f0..bd2f6c2e3e 100644
--- a/arch/arm/dts/am335x-brppt1-mmc.dts
+++ b/arch/arm/dts/am335x-brppt1-mmc.dts
@@ -53,8 +53,6 @@
bkl-pwm = <>;
bkl-tps = <_bl>;
- u-boot,dm-pre-reloc;
-
panel-info {
ac-bias = <255>;
ac-bias-intrpt = <0>;
@@ -238,8 +236,19 @@
status = "okay";
};
- {
- status = "disabled";
+_per {
+
+ segment@30 {
+
+ target-module@e000 {
+ u-boot,dm-pre-reloc;
+
+ lcdc: lcdc@0 {
+ u-boot,dm-pre-reloc;
+ status = "disabled";
+ };
+ };
+ };
};
{
diff --git a/arch/arm/dts/am335x-brppt1-nand.dts
b/arch/arm/dts/am335x-brppt1-nand.dts
index 9d4340f591..67c609739f 100644
--- a/arch/arm/dts/am335x-brppt1-nand.dts
+++ b/arch/arm/dts/am335x-brppt1-nand.dts
@@ -53,8 +53,6 @@
bkl-pwm = <>;
bkl-tps = <_bl>;
- u-boot,dm-pre-reloc;
-
panel-info {
ac-bias = <255>;
ac-bias-intrpt = <0>;
@@ -228,8 +226,19 @@
status = "disabled";
};
- {
- status = "disabled";
+_per {
+
+ segment@30 {
+
+ target-module@e000 {
+ u-boot,dm-pre-reloc;
+
+ lcdc: lcdc@0 {
+ u-boot,dm-pre-reloc;
+ status = "disabled";
+ };
+ };
+ };
};
{
diff --git a/arch/arm/dts/am335x-brppt1-spi.dts
b/arch/arm/dts/am335x-brppt1-spi.dts
index c078af8fba..ce3dce204d 100644
--- a/arch/arm/dts/am335x-brppt1-spi.dts
+++ b/arch/arm/dts/am335x-brppt1-spi.dts
@@ -54,8 +54,6 @@
bkl-pwm = <>;
bkl-tps = <_bl>;
- u-boot,dm-pre-reloc;
-
panel-info {
ac-bias = <255>;
ac-bias-intrpt = <0>;
@@ -259,8 +257,19 @@
status = "okay";
};
- {
- status = "disabled";
+_per {
+
+ segment@30 {
+
+ target-module@e000 {
+ u-boot,dm-pre-reloc;
+
+ lcdc: lcdc@0 {
+ u-boot,dm-pre-reloc;
+ status = "disabled";
+ };
+ };
+ };
};
{
diff --git a/arch/arm/dts/am335x-brsmarc1.dts b/arch/arm/dts/am335x-brsmarc1.dts
index 7e9516e8f8..25cdb11164 100644
--- a/arch/arm/dts/am335x-brsmarc1.dts
+++ b/arch/arm/dts/am335x-brsmarc1.dts
@@ -59,7 +59,6 @@
/*backlight = <_bl>; */
compatible = "ti,tilcdc,panel";
status = "okay";
- u-boot,dm-pre-reloc;
panel-info {
ac-bias = <255>;
@@ -298,10 +297,21 @@
[PATCH v8 15/28] arm: dts: am335x: enable prcm_clocks auto binding
Adding the 'simple-bus' compatible string to the prcm_clocks node will
allow its automatic binding.
Signed-off-by: Dario Binacchi
---
(no changes since v6)
Changes in v6:
- Remove the 'am3-prcm' driver.
- Add the 'simple-bus' compatible string to the prcm_clocks node.
Changes in v4:
- Include device_compat.h header for dev_xxx macros.
Changes in v3:
- Add to commit message the references to linux kernel dt binding
documentation.
Changes in v2:
- Remove the 'ti_am3_prcm_clocks' driver. Handle 'prcm_clocks' node in
the 'ti_am3_prcm' driver.
- Update the commit message.
arch/arm/dts/am33xx-u-boot.dtsi | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/dts/am33xx-u-boot.dtsi b/arch/arm/dts/am33xx-u-boot.dtsi
index 78f5e2c4d3..2426ece680 100644
--- a/arch/arm/dts/am33xx-u-boot.dtsi
+++ b/arch/arm/dts/am33xx-u-boot.dtsi
@@ -9,3 +9,7 @@
u-boot,dm-pre-reloc;
};
};
+
+_clocks {
+ compatible = "simple-bus";
+};
--
2.17.1
[PATCH v8 24/28] video: omap: drop domain clock enabling by SOC api
Enabling the domain clock is performed by the sysc interconnect target module driver during the video device probing. Signed-off-by: Dario Binacchi --- (no changes since v3) Changes in v3: - Remove clock domain enabling/disabling. - Update the commit message. arch/arm/mach-omap2/am33xx/clock_am33xx.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-omap2/am33xx/clock_am33xx.c b/arch/arm/mach-omap2/am33xx/clock_am33xx.c index 2427933c8b..cf71192360 100644 --- a/arch/arm/mach-omap2/am33xx/clock_am33xx.c +++ b/arch/arm/mach-omap2/am33xx/clock_am33xx.c @@ -226,7 +226,7 @@ void enable_basic_clocks(void) >usb0clkctrl, >emiffwclkctrl, >emifclkctrl, -#if CONFIG_IS_ENABLED(AM335X_LCD) +#if CONFIG_IS_ENABLED(AM335X_LCD) && !CONFIG_IS_ENABLED(DM_VIDEO) >lcdclkctrl, >lcdcclkstctrl, #endif -- 2.17.1
[PATCH v8 17/28] fdt: translate address if #size-cells = <0>
The __of_translate_address routine translates an address from the
device tree into a CPU physical address. A note in the description of
the routine explains that the crossing of any level with
#size-cells = <0> is to be considered an error not by specification but
since inherited from IBM. This does not happen for Texas Instruments, or
at least for the beaglebone device tree. Without this patch, in fact,
the translation into physical addresses of the registers contained in the
am33xx-clocks.dtsi nodes would not be possible. They all have a parent
with #size-cells = <0>.
The CONFIG_OF_TRANSLATE_ZERO_SIZE_CELLS symbol makes translation
possible even in the case of crossing levels with #size-cells = <0>.
The patch acts conservatively on address translation, except for
removing a check within the of_translate_one function in the
drivers/core/of_addr.c file:
+
ranges = of_get_property(parent, rprop, );
- if (ranges == NULL && !of_empty_ranges_quirk(parent)) {
- debug("no ranges; cannot translate\n");
- return 1;
- }
if (ranges == NULL || rlen == 0) {
offset = of_read_number(addr, na);
memset(addr, 0, pna * 4);
debug("empty ranges; 1:1 translation\n");
There are two reasons:
1 The function of_empty_ranges_quirk always returns false, invalidating
the following if statement in case of null ranges. Therefore one of
the two checks is useless.
2 The implementation of the of_translate_one function found in the
common/fdt_support.c file has removed this check while keeping the one
about the 1:1 translation.
The patch adds a test and modifies a check for the correctness of an
address in the case of enabling translation also for zero size cells.
The added test checks translations of addresses generated by nodes of
a device tree similar to those you can find in the files am33xx.dtsi
and am33xx-clocks.dtsi for which the patch was created.
The patch was also tested on a beaglebone black board. The addresses
generated for the registers of the loaded drivers are those specified
by the AM335x reference manual.
Signed-off-by: Dario Binacchi
Tested-by: Dario Binacchi
Reviewed-by: Simon Glass
---
(no changes since v7)
Changes in v7:
- Add gd_size_cells_0 macro to fix building errors for boards that do
not use CONFIG_DM.
Changes in v4:
- Add Sphinx documentation for dm_flags.
- Convert GD_DM_FLG_* to enum.
- Include device_compat.h header in test/dm/test-fdt.c for dev_xxx macros.
Changes in v3:
- Comment dm_flags field in the global_data structure.
Changes in v2:
- Fix a missing line in the commit message.
- Add dm_flags to global_data structure and GD_DM_FLG_SIZE_CELLS_0 macro
to test without recompiling.
- Update the OF_CHECK_COUNTS macro in order to have just one
#define by bringing the GD_DM_FLG_SIZE_CELLS_0 into the expression.
- Lower-case the 0xC019 hex number.
arch/sandbox/dts/test.dts | 21 ++
common/fdt_support.c | 6 ++-
drivers/core/Kconfig | 12 ++
drivers/core/fdtaddr.c| 2 +-
drivers/core/of_addr.c| 13 ++
drivers/core/ofnode.c | 7 +++-
drivers/core/root.c | 3 ++
include/asm-generic/global_data.h | 24 +++
test/dm/test-fdt.c| 69 ++-
9 files changed, 141 insertions(+), 16 deletions(-)
diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts
index f3b766271d..637d79caf7 100644
--- a/arch/sandbox/dts/test.dts
+++ b/arch/sandbox/dts/test.dts
@@ -41,6 +41,7 @@
fdt-dummy1 = "/translation-test@8000/dev@1,100";
fdt-dummy2 = "/translation-test@8000/dev@2,200";
fdt-dummy3 = "/translation-test@8000/noxlatebus@3,300/dev@42";
+ fdt-dummy4 =
"/translation-test@8000/xlatebus@4,400/devs/dev@19";
usb0 = _0;
usb1 = _1;
usb2 = _2;
@@ -1061,6 +1062,7 @@
1 0x100 0x9000 0x1000
2 0x200 0xA000 0x1000
3 0x300 0xB000 0x1000
+ 4 0x400 0xC000 0x1000
>;
dma-ranges = <0 0x000 0x1000 0x1000
@@ -1097,6 +1099,25 @@
reg = <0x42>;
};
};
+
+ xlatebus@4,400 {
+ compatible = "sandbox,zero-size-cells-bus";
+ reg = <4 0x400 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 4 0x400 0x1000>;
+
+ devs {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ dev@19 {
+ compatible = "denx,u-boot-fdt-dummy";
+ reg =
[PATCH v8 21/28] bus: ti: am33xx: add pwm subsystem driver
The TI PWMSS driver is a simple bus driver for providing clock and power
management for the PWM peripherals on TI AM33xx SoCs, namely eCAP,
eHRPWM and eQEP.
For DT binding details see Linux doc:
- Documentation/devicetree/bindings/pwm/pwm-tipwmss.txt
Signed-off-by: Dario Binacchi
---
(no changes since v3)
Changes in v3:
- Move Kconfig symbol from drivers/pwm to drivers/bus.
- Remove the domain clock reference from the pwmss nodes of the device
tree in am33xx.dtsi. The resync of am33xx.dtsi with Linux 5.9-rc7
already contains such references.
- Remove domain clock enabling/disabling. Enabling the domain clock is
performed by the sysc interconnect target module driver during the pwm
device probing.
- Remove doc/device-tree-bindings/pwm/ti,pwmss.txt.
- Add to commit message the references to linux kernel dt binding
documentation.
drivers/bus/Kconfig| 6 ++
drivers/bus/Makefile | 1 +
drivers/bus/ti-pwmss.c | 21 +
3 files changed, 28 insertions(+)
create mode 100644 drivers/bus/ti-pwmss.c
diff --git a/drivers/bus/Kconfig b/drivers/bus/Kconfig
index 733bec5a56..d742ed333b 100644
--- a/drivers/bus/Kconfig
+++ b/drivers/bus/Kconfig
@@ -5,6 +5,12 @@
menu "Bus devices"
+config TI_PWMSS
+ bool
+ default y if ARCH_OMAP2PLUS && PWM_TI_EHRPWM
+ help
+ PWM Subsystem driver support for AM33xx SOC.
+
config TI_SYSC
bool "TI sysc interconnect target module driver"
depends on ARCH_OMAP2PLUS
diff --git a/drivers/bus/Makefile b/drivers/bus/Makefile
index 875bb4ed42..a2e71c7b3b 100644
--- a/drivers/bus/Makefile
+++ b/drivers/bus/Makefile
@@ -3,5 +3,6 @@
# Makefile for the bus drivers.
#
+obj-$(CONFIG_TI_PWMSS) += ti-pwmss.o
obj-$(CONFIG_TI_SYSC) += ti-sysc.o
obj-$(CONFIG_UNIPHIER_SYSTEM_BUS) += uniphier-system-bus.o
diff --git a/drivers/bus/ti-pwmss.c b/drivers/bus/ti-pwmss.c
new file mode 100644
index 00..265b4cf83b
--- /dev/null
+++ b/drivers/bus/ti-pwmss.c
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Pulse-Width Modulation Subsystem (pwmss)
+ *
+ * Copyright (C) 2020 Dario Binacchi
+ */
+
+#include
+#include
+
+static const struct udevice_id ti_pwmss_ids[] = {
+ {.compatible = "ti,am33xx-pwmss"},
+ {}
+};
+
+U_BOOT_DRIVER(ti_pwmss) = {
+ .name = "ti_pwmss",
+ .id = UCLASS_SIMPLE_BUS,
+ .of_match = ti_pwmss_ids,
+ .bind = dm_scan_fdt_dev,
+};
--
2.17.1
[PATCH v8 20/28] pwm: ti: am33xx: add enhanced pwm driver
Enhanced high resolution PWM module (EHRPWM) hardware can be used to generate PWM output over 2 channels. This commit adds PWM driver support for EHRPWM device present on AM33XX SOC. The code is based on the drivers/pwm/pwm-tiehrpwm.c driver of the Linux kernel version 5.9-rc7. For DT binding details see: - Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.txt Signed-off-by: Dario Binacchi --- (no changes since v4) Changes in v4: - Include device_compat.h header for dev_xxx macros. Changes in v3: - Adds PWM_TI_EHRPWM dependency on ARCH_OMAP2PLUS in Kconfig. - Add error message in case of invalid address. - Remove doc/device-tree-bindings/pwm/ti,ehrpwm.txt. - Add to commit message the references to linux kernel dt binding documentation. drivers/pwm/Kconfig | 7 + drivers/pwm/Makefile| 1 + drivers/pwm/pwm-ti-ehrpwm.c | 468 3 files changed, 476 insertions(+) create mode 100644 drivers/pwm/pwm-ti-ehrpwm.c diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index b3bd5c6bb7..ccf81abbe9 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -75,3 +75,10 @@ config PWM_SUNXI help This PWM is found on H3, A64 and other Allwinner SoCs. It supports a programmable period and duty cycle. A 16-bit counter is used. + +config PWM_TI_EHRPWM + bool "Enable support for EHRPWM PWM" + depends on DM_PWM && ARCH_OMAP2PLUS + default y + help + PWM driver support for the EHRPWM controller found on TI SOCs. diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile index f21ae7d76e..0b9d2698a3 100644 --- a/drivers/pwm/Makefile +++ b/drivers/pwm/Makefile @@ -19,3 +19,4 @@ obj-$(CONFIG_PWM_SANDBOX) += sandbox_pwm.o obj-$(CONFIG_PWM_SIFIVE) += pwm-sifive.o obj-$(CONFIG_PWM_TEGRA)+= tegra_pwm.o obj-$(CONFIG_PWM_SUNXI)+= sunxi_pwm.o +obj-$(CONFIG_PWM_TI_EHRPWM)+= pwm-ti-ehrpwm.o diff --git a/drivers/pwm/pwm-ti-ehrpwm.c b/drivers/pwm/pwm-ti-ehrpwm.c new file mode 100644 index 00..df995c8865 --- /dev/null +++ b/drivers/pwm/pwm-ti-ehrpwm.c @@ -0,0 +1,468 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * EHRPWM PWM driver + * + * Copyright (C) 2020 Dario Binacchi + * + * Based on Linux kernel drivers/pwm/pwm-tiehrpwm.c + */ + +#include +#include +#include +#include +#include +#include +#include + +#define NSEC_PER_SEC 10L + +/* Time base module registers */ +#define TI_EHRPWM_TBCTL0x00 +#define TI_EHRPWM_TBPRD0x0A + +#define TI_EHRPWM_TBCTL_PRDLD_MASK BIT(3) +#define TI_EHRPWM_TBCTL_PRDLD_SHDW 0 +#define TI_EHRPWM_TBCTL_PRDLD_IMDT BIT(3) +#define TI_EHRPWM_TBCTL_CLKDIV_MASKGENMASK(12, 7) +#define TI_EHRPWM_TBCTL_CTRMODE_MASK GENMASK(1, 0) +#define TI_EHRPWM_TBCTL_CTRMODE_UP 0 +#define TI_EHRPWM_TBCTL_CTRMODE_DOWN BIT(0) +#define TI_EHRPWM_TBCTL_CTRMODE_UPDOWN BIT(1) +#define TI_EHRPWM_TBCTL_CTRMODE_FREEZE GENMASK(1, 0) + +#define TI_EHRPWM_TBCTL_HSPCLKDIV_SHIFT7 +#define TI_EHRPWM_TBCTL_CLKDIV_SHIFT 10 + +#define TI_EHRPWM_CLKDIV_MAX 7 +#define TI_EHRPWM_HSPCLKDIV_MAX7 +#define TI_EHRPWM_PERIOD_MAX 0x + +/* Counter compare module registers */ +#define TI_EHRPWM_CMPA 0x12 +#define TI_EHRPWM_CMPB 0x14 + +/* Action qualifier module registers */ +#define TI_EHRPWM_AQCTLA 0x16 +#define TI_EHRPWM_AQCTLB 0x18 +#define TI_EHRPWM_AQSFRC 0x1A +#define TI_EHRPWM_AQCSFRC 0x1C + +#define TI_EHRPWM_AQCTL_CBU_MASK GENMASK(9, 8) +#define TI_EHRPWM_AQCTL_CBU_FRCLOW BIT(8) +#define TI_EHRPWM_AQCTL_CBU_FRCHIGHBIT(9) +#define TI_EHRPWM_AQCTL_CBU_FRCTOGGLE GENMASK(9, 8) +#define TI_EHRPWM_AQCTL_CAU_MASK GENMASK(5, 4) +#define TI_EHRPWM_AQCTL_CAU_FRCLOW BIT(4) +#define TI_EHRPWM_AQCTL_CAU_FRCHIGHBIT(5) +#define TI_EHRPWM_AQCTL_CAU_FRCTOGGLE GENMASK(5, 4) +#define TI_EHRPWM_AQCTL_PRD_MASK GENMASK(3, 2) +#define TI_EHRPWM_AQCTL_PRD_FRCLOW BIT(2) +#define TI_EHRPWM_AQCTL_PRD_FRCHIGHBIT(3) +#define TI_EHRPWM_AQCTL_PRD_FRCTOGGLE GENMASK(3, 2) +#define TI_EHRPWM_AQCTL_ZRO_MASK GENMASK(1, 0) +#define TI_EHRPWM_AQCTL_ZRO_FRCLOW BIT(0) +#define TI_EHRPWM_AQCTL_ZRO_FRCHIGHBIT(1) +#define TI_EHRPWM_AQCTL_ZRO_FRCTOGGLE GENMASK(1, 0) + +#define TI_EHRPWM_AQCTL_CHANA_POLNORMAL (TI_EHRPWM_AQCTL_CAU_FRCLOW | \ +TI_EHRPWM_AQCTL_PRD_FRCHIGH | \ +
[PATCH v8 22/28] dm: core: add a function to decode display timings
The patch adds a function to get display timings from the device tree
node attached to the device.
Signed-off-by: Dario Binacchi
Reviewed-by: Simon Glass
---
(no changes since v1)
arch/sandbox/dts/test.dts | 46 ++
drivers/core/read.c | 6 +++
include/dm/read.h | 24
test/dm/test-fdt.c| 80 +++
4 files changed, 156 insertions(+)
diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts
index 637d79caf7..6e095de180 100644
--- a/arch/sandbox/dts/test.dts
+++ b/arch/sandbox/dts/test.dts
@@ -141,6 +141,52 @@
<>;
mux-control-names = "mux0", "mux1", "mux2", "mux3", "mux4";
mux-syscon = <>;
+ display-timings {
+ timing0: 240x320 {
+ clock-frequency = <650>;
+ hactive = <240>;
+ vactive = <320>;
+ hfront-porch = <6>;
+ hback-porch = <7>;
+ hsync-len = <1>;
+ vback-porch = <5>;
+ vfront-porch = <8>;
+ vsync-len = <2>;
+ hsync-active = <1>;
+ vsync-active = <0>;
+ de-active = <1>;
+ pixelclk-active = <1>;
+ interlaced;
+ doublescan;
+ doubleclk;
+ };
+ timing1: 480x800 {
+ clock-frequency = <900>;
+ hactive = <480>;
+ vactive = <800>;
+ hfront-porch = <10>;
+ hback-porch = <59>;
+ hsync-len = <12>;
+ vback-porch = <15>;
+ vfront-porch = <17>;
+ vsync-len = <16>;
+ hsync-active = <0>;
+ vsync-active = <1>;
+ de-active = <0>;
+ pixelclk-active = <0>;
+ };
+ timing2: 800x480 {
+ clock-frequency = <3350>;
+ hactive = <800>;
+ vactive = <480>;
+ hback-porch = <89>;
+ hfront-porch = <164>;
+ vback-porch = <23>;
+ vfront-porch = <10>;
+ hsync-len = <11>;
+ vsync-len = <13>;
+ };
+ };
};
junk {
diff --git a/drivers/core/read.c b/drivers/core/read.c
index 076125824c..7925c09f60 100644
--- a/drivers/core/read.c
+++ b/drivers/core/read.c
@@ -377,3 +377,9 @@ int dev_read_pci_bus_range(const struct udevice *dev,
return 0;
}
+
+int dev_decode_display_timing(const struct udevice *dev, int index,
+ struct display_timing *config)
+{
+ return ofnode_decode_display_timing(dev_ofnode(dev), index, config);
+}
diff --git a/include/dm/read.h b/include/dm/read.h
index 0585eb1228..0ac26d9f1d 100644
--- a/include/dm/read.h
+++ b/include/dm/read.h
@@ -694,6 +694,23 @@ int dev_get_child_count(const struct udevice *dev);
*/
int dev_read_pci_bus_range(const struct udevice *dev, struct resource *res);
+/**
+ * dev_decode_display_timing() - decode display timings
+ *
+ * Decode display timings from the supplied 'display-timings' node.
+ * See doc/device-tree-bindings/video/display-timing.txt for binding
+ * information.
+ *
+ * @dev: device to read DT display timings from. The node linked to the device
+ * contains a child node called 'display-timings' which in turn contains
+ * one or more display timing nodes.
+ * @index: index number to read (0=first timing subnode)
+ * @config: place to put timings
+ * @return 0 if OK, -FDT_ERR_NOTFOUND if not found
+ */
+int dev_decode_display_timing(const struct udevice *dev, int index,
+ struct display_timing *config);
+
#else /* CONFIG_DM_DEV_READ_INLINE is enabled */
static inline int dev_read_u32(const struct udevice *dev,
@@ -1016,6 +1033,13 @@ static inline int dev_get_child_count(const struct
udevice *dev)
return ofnode_get_child_count(dev_ofnode(dev));
}
+static inline int dev_decode_display_timing(const struct udevice *dev,
+ int index,
+ struct display_timing *config)
+{
+ return ofnode_decode_display_timing(dev_ofnode(dev), index,
[PATCH v8 19/28] arm: dts: am335x: enable scm_clocks auto binding
Adding the 'simple-bus' compatible string to the scm_clocks node will
allow its automatic binding.
Signed-off-by: Dario Binacchi
---
(no changes since v7)
Changes in v7:
- Add dm8168-evm-u-boot.dtsi to fix building errors for
ti816x_evm_defconfig.
Changes in v6:
- Remove the 'am3-scm' driver.
- Add the 'simple-bus' compatible string to the scm_clocks node.
Changes in v4:
- Include device_compat.h header for dev_xxx macros.
Changes in v3:
- Remove doc/device-tree-bindings/arm/omap,ctrl.txt.
- Remove doc/device-tree-bindings/pinctrl/pinctrl-single.txt.
- Add to commit message the references to linux kernel dt binding
documentation.
Changes in v2:
- Remove the 'ti_am3_scm_clocks' driver. Handle 'scm_clocks' node in
the 'ti_am3_scm' driver.
- Update the commit message.
arch/arm/dts/am33xx-u-boot.dtsi | 4
arch/arm/dts/dm8168-evm-u-boot.dtsi | 12
2 files changed, 16 insertions(+)
create mode 100644 arch/arm/dts/dm8168-evm-u-boot.dtsi
diff --git a/arch/arm/dts/am33xx-u-boot.dtsi b/arch/arm/dts/am33xx-u-boot.dtsi
index 2426ece680..61d10b841b 100644
--- a/arch/arm/dts/am33xx-u-boot.dtsi
+++ b/arch/arm/dts/am33xx-u-boot.dtsi
@@ -13,3 +13,7 @@
_clocks {
compatible = "simple-bus";
};
+
+_clocks {
+ compatible = "simple-bus";
+};
diff --git a/arch/arm/dts/dm8168-evm-u-boot.dtsi
b/arch/arm/dts/dm8168-evm-u-boot.dtsi
new file mode 100644
index 00..de0bb9bc81
--- /dev/null
+++ b/arch/arm/dts/dm8168-evm-u-boot.dtsi
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * dm8168-evm U-Boot Additions
+ *
+ * Copyright (C) 2020 Dario Binacchi
+ */
+
+/ {
+ ocp {
+ u-boot,dm-pre-reloc;
+ };
+};
--
2.17.1
[PATCH v8 18/28] omap: timer: fix the rate setting
The prescaler (PTV) setting must be taken into account even when the
timer input clock frequency has been set.
Signed-off-by: Dario Binacchi
---
(no changes since v1)
drivers/timer/omap-timer.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/timer/omap-timer.c b/drivers/timer/omap-timer.c
index 4eecb3e64d..c08cb5ad2e 100644
--- a/drivers/timer/omap-timer.c
+++ b/drivers/timer/omap-timer.c
@@ -19,8 +19,6 @@
#define TCLR_PRE_ENBIT(5) /* Pre-scaler enable */
#define TCLR_PTV_SHIFT (2) /* Pre-scaler shift value */
-#define TIMER_CLOCK (V_SCLK / (2 << CONFIG_SYS_PTV))
-
struct omap_gptimer_regs {
unsigned int tidr; /* offset 0x00 */
unsigned char res1[12];
@@ -61,7 +59,9 @@ static int omap_timer_probe(struct udevice *dev)
struct omap_timer_priv *priv = dev_get_priv(dev);
if (!uc_priv->clock_rate)
- uc_priv->clock_rate = TIMER_CLOCK;
+ uc_priv->clock_rate = V_SCLK;
+
+ uc_priv->clock_rate /= (2 << CONFIG_SYS_PTV);
/* start the counter ticking up, reload value on overflow */
writel(0, >regs->tldr);
--
2.17.1
[PATCH v8 16/28] clk: move clk-ti-sci driver to 'ti' directory
The patch moves the clk-ti-sci.c file to the 'ti' directory along with
all the other TI's drivers, and renames it clk-sci.c.
Signed-off-by: Dario Binacchi
---
(no changes since v1)
drivers/clk/Kconfig| 8
drivers/clk/Makefile | 1 -
drivers/clk/ti/Kconfig | 8
drivers/clk/ti/Makefile| 1 +
drivers/clk/{clk-ti-sci.c => ti/clk-sci.c} | 0
5 files changed, 9 insertions(+), 9 deletions(-)
rename drivers/clk/{clk-ti-sci.c => ti/clk-sci.c} (100%)
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 9e54929039..db06f276ec 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -98,14 +98,6 @@ config CLK_STM32F
This clock driver adds support for RCC clock management
for STM32F4 and STM32F7 SoCs.
-config CLK_TI_SCI
- bool "TI System Control Interface (TI SCI) clock driver"
- depends on CLK && TI_SCI_PROTOCOL && OF_CONTROL
- help
- This enables the clock driver support over TI System Control Interface
- available on some new TI's SoCs. If you wish to use clock resources
- managed by the TI System Controller, say Y here. Otherwise, say N.
-
config CLK_HSDK
bool "Enable cgu clock driver for HSDK boards"
depends on CLK && TARGET_HSDK
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 2581fe0a19..f8383e523d 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -48,6 +48,5 @@ obj-$(CONFIG_SANDBOX) += clk_sandbox.o
obj-$(CONFIG_SANDBOX) += clk_sandbox_test.o
obj-$(CONFIG_SANDBOX_CLK_CCF) += clk_sandbox_ccf.o
obj-$(CONFIG_STM32H7) += clk_stm32h7.o
-obj-$(CONFIG_CLK_TI_SCI) += clk-ti-sci.o
obj-$(CONFIG_CLK_VERSAL) += clk_versal.o
obj-$(CONFIG_CLK_CDCE9XX) += clk-cdce9xx.o
diff --git a/drivers/clk/ti/Kconfig b/drivers/clk/ti/Kconfig
index 9e257a2eb7..2dc86d44a9 100644
--- a/drivers/clk/ti/Kconfig
+++ b/drivers/clk/ti/Kconfig
@@ -33,3 +33,11 @@ config CLK_TI_MUX
depends on CLK && OF_CONTROL && CLK_CCF
help
This enables the mux clock driver support on TI's SoCs.
+
+config CLK_TI_SCI
+ bool "TI System Control Interface (TI SCI) clock driver"
+ depends on CLK && TI_SCI_PROTOCOL && OF_CONTROL
+ help
+ This enables the clock driver support over TI System Control Interface
+ available on some new TI's SoCs. If you wish to use clock resources
+ managed by the TI System Controller, say Y here. Otherwise, say N.
diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile
index dbd343069c..9f56b47736 100644
--- a/drivers/clk/ti/Makefile
+++ b/drivers/clk/ti/Makefile
@@ -10,3 +10,4 @@ obj-$(CONFIG_CLK_TI_CTRL) += clk-ctrl.o
obj-$(CONFIG_CLK_TI_DIVIDER) += clk-divider.o
obj-$(CONFIG_CLK_TI_GATE) += clk-gate.o
obj-$(CONFIG_CLK_TI_MUX) += clk-mux.o
+obj-$(CONFIG_CLK_TI_SCI) += clk-sci.o
diff --git a/drivers/clk/clk-ti-sci.c b/drivers/clk/ti/clk-sci.c
similarity index 100%
rename from drivers/clk/clk-ti-sci.c
rename to drivers/clk/ti/clk-sci.c
--
2.17.1
[PATCH v8 14/28] clk: ti: omap4: add clock manager driver
This minimal driver is only used to bind child devices.
For DT binding details see Linux doc:
- Documentation/devicetree/bindings/arm/omap/prcm.txt
Signed-off-by: Dario Binacchi
---
(no changes since v3)
Changes in v3:
- doc/device-tree-bindings/arm/omap,prcm.txt.
- Add to commit message the references to linux kernel dt binding
documentation.
drivers/clk/ti/Makefile | 2 +-
drivers/clk/ti/omap4-cm.c | 22 ++
2 files changed, 23 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/ti/omap4-cm.c
diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile
index ed45f18311..dbd343069c 100644
--- a/drivers/clk/ti/Makefile
+++ b/drivers/clk/ti/Makefile
@@ -3,7 +3,7 @@
# Copyright (C) 2020 Dario Binacchi
#
-obj-$(CONFIG_ARCH_OMAP2PLUS) += clk.o
+obj-$(CONFIG_ARCH_OMAP2PLUS) += clk.o omap4-cm.o
obj-$(CONFIG_CLK_TI_AM3_DPLL) += clk-am3-dpll.o clk-am3-dpll-x2.o
obj-$(CONFIG_CLK_TI_CTRL) += clk-ctrl.o
diff --git a/drivers/clk/ti/omap4-cm.c b/drivers/clk/ti/omap4-cm.c
new file mode 100644
index 00..3cdc9b2888
--- /dev/null
+++ b/drivers/clk/ti/omap4-cm.c
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * OMAP4 clock manager (cm)
+ *
+ * Copyright (C) 2020 Dario Binacchi
+ */
+
+#include
+#include
+#include
+
+static const struct udevice_id ti_omap4_cm_ids[] = {
+ {.compatible = "ti,omap4-cm"},
+ {}
+};
+
+U_BOOT_DRIVER(ti_omap4_cm) = {
+ .name = "ti_omap4_cm",
+ .id = UCLASS_SIMPLE_BUS,
+ .of_match = ti_omap4_cm_ids,
+ .bind = dm_scan_fdt_dev,
+};
--
2.17.1
[PATCH v8 13/28] clk: ti: add support for clkctrl clocks
Until now the clkctrl clocks have been enabled/disabled through platform
routines. Thanks to this patch they can be enabled and configured directly
by the probed devices that need to use them.
For DT binding details see Linux doc:
- Documentation/devicetree/bindings/clock/ti-clkctrl.txt
Signed-off-by: Dario Binacchi
---
(no changes since v5)
Changes in v5:
- Move the clk-ti-ctrl.c file to drivers/clk/ti with the name
clk-ctrl.c.
Changes in v4:
- Include device_compat.h header for dev_xxx macros.
- Fix compilation errors on the dev parameter of the dev_xx macros.
Changes in v3:
- Fix access to registers listed by device tree following resync of
am33xx-clock.dtsi with Linux 5.9-rc7.
- Remove doc/device-tree-bindings/clock/ti,clkctrl.txt.
- Add to commit message the references to linux kernel dt binding
documentation.
drivers/clk/ti/Kconfig| 6 ++
drivers/clk/ti/Makefile | 1 +
drivers/clk/ti/clk-ctrl.c | 154 ++
3 files changed, 161 insertions(+)
create mode 100644 drivers/clk/ti/clk-ctrl.c
diff --git a/drivers/clk/ti/Kconfig b/drivers/clk/ti/Kconfig
index 30959a316a..9e257a2eb7 100644
--- a/drivers/clk/ti/Kconfig
+++ b/drivers/clk/ti/Kconfig
@@ -10,6 +10,12 @@ config CLK_TI_AM3_DPLL
This enables the DPLL clock drivers support on AM33XX SoCs. The DPLL
provides all interface clocks and functional clocks to the processor.
+config CLK_TI_CTRL
+ bool "TI OMAP4 clock controller"
+ depends on CLK && OF_CONTROL
+ help
+ This enables the clock controller driver support on TI's SoCs.
+
config CLK_TI_DIVIDER
bool "TI divider clock driver"
depends on CLK && OF_CONTROL && CLK_CCF
diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile
index f8aa735c83..ed45f18311 100644
--- a/drivers/clk/ti/Makefile
+++ b/drivers/clk/ti/Makefile
@@ -6,6 +6,7 @@
obj-$(CONFIG_ARCH_OMAP2PLUS) += clk.o
obj-$(CONFIG_CLK_TI_AM3_DPLL) += clk-am3-dpll.o clk-am3-dpll-x2.o
+obj-$(CONFIG_CLK_TI_CTRL) += clk-ctrl.o
obj-$(CONFIG_CLK_TI_DIVIDER) += clk-divider.o
obj-$(CONFIG_CLK_TI_GATE) += clk-gate.o
obj-$(CONFIG_CLK_TI_MUX) += clk-mux.o
diff --git a/drivers/clk/ti/clk-ctrl.c b/drivers/clk/ti/clk-ctrl.c
new file mode 100644
index 00..74271aaf56
--- /dev/null
+++ b/drivers/clk/ti/clk-ctrl.c
@@ -0,0 +1,154 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * OMAP clock controller support
+ *
+ * Copyright (C) 2020 Dario Binacchi
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+struct clk_ti_ctrl_offs {
+ fdt_addr_t start;
+ fdt_size_t end;
+};
+
+struct clk_ti_ctrl_priv {
+ int offs_num;
+ struct clk_ti_ctrl_offs *offs;
+};
+
+static int clk_ti_ctrl_check_offs(struct clk *clk, fdt_addr_t offs)
+{
+ struct clk_ti_ctrl_priv *priv = dev_get_priv(clk->dev);
+ int i;
+
+ for (i = 0; i < priv->offs_num; i++) {
+ if (offs >= priv->offs[i].start && offs <= priv->offs[i].end)
+ return 0;
+ }
+
+ return -EFAULT;
+}
+
+static int clk_ti_ctrl_disable(struct clk *clk)
+{
+ struct clk_ti_ctrl_priv *priv = dev_get_priv(clk->dev);
+ u32 *clk_modules[2] = { };
+ fdt_addr_t offs;
+ int err;
+
+ offs = priv->offs[0].start + clk->id;
+ err = clk_ti_ctrl_check_offs(clk, offs);
+ if (err) {
+ dev_err(clk->dev, "invalid offset: 0x%lx\n", offs);
+ return err;
+ }
+
+ clk_modules[0] = (u32 *)(offs);
+ dev_dbg(clk->dev, "module address=%p\n", clk_modules[0]);
+ do_disable_clocks(NULL, clk_modules, 1);
+ return 0;
+}
+
+static int clk_ti_ctrl_enable(struct clk *clk)
+{
+ struct clk_ti_ctrl_priv *priv = dev_get_priv(clk->dev);
+ u32 *clk_modules[2] = { };
+ fdt_addr_t offs;
+ int err;
+
+ offs = priv->offs[0].start + clk->id;
+ err = clk_ti_ctrl_check_offs(clk, offs);
+ if (err) {
+ dev_err(clk->dev, "invalid offset: 0x%lx\n", offs);
+ return err;
+ }
+
+ clk_modules[0] = (u32 *)(offs);
+ dev_dbg(clk->dev, "module address=%p\n", clk_modules[0]);
+ do_enable_clocks(NULL, clk_modules, 1);
+ return 0;
+}
+
+static ulong clk_ti_ctrl_get_rate(struct clk *clk)
+{
+ return 0;
+}
+
+static int clk_ti_ctrl_of_xlate(struct clk *clk,
+ struct ofnode_phandle_args *args)
+{
+ if (args->args_count != 2) {
+ dev_err(clk->dev, "invaild args_count: %d\n", args->args_count);
+ return -EINVAL;
+ }
+
+ if (args->args_count)
+ clk->id = args->args[0];
+ else
+ clk->id = 0;
+
+ dev_dbg(clk->dev, "name=%s, id=%ld\n", clk->dev->name, clk->id);
+ return 0;
+}
+
+static int clk_ti_ctrl_ofdata_to_platdata(struct udevice *dev)
+{
+ struct clk_ti_ctrl_priv *priv = dev_get_priv(dev);
+ fdt_size_t fdt_size;
+ int i,
[PATCH v8 12/28] ti: am33xx: fix do_enable_clocks() to accept NULL parameters
Up till this commit passing NULL as input parameter was allowed, but not
handled properly. When a NULL parameter was passed to the function a data
abort was raised.
Signed-off-by: Dario Binacchi
Reviewed-by: Simon Glass
---
(no changes since v1)
arch/arm/mach-omap2/am33xx/clock.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-omap2/am33xx/clock.c
b/arch/arm/mach-omap2/am33xx/clock.c
index 8819062aaa..130ee6c6e3 100644
--- a/arch/arm/mach-omap2/am33xx/clock.c
+++ b/arch/arm/mach-omap2/am33xx/clock.c
@@ -194,13 +194,14 @@ void do_enable_clocks(u32 *const *clk_domains,
u32 i, max = 100;
/* Put the clock domains in SW_WKUP mode */
- for (i = 0; (i < max) && clk_domains[i]; i++) {
+ for (i = 0; (i < max) && clk_domains && clk_domains[i]; i++) {
enable_clock_domain(clk_domains[i],
CD_CLKCTRL_CLKTRCTRL_SW_WKUP);
}
/* Clock modules that need to be put in SW_EXPLICIT_EN mode */
- for (i = 0; (i < max) && clk_modules_explicit_en[i]; i++) {
+ for (i = 0; (i < max) && clk_modules_explicit_en &&
+clk_modules_explicit_en[i]; i++) {
enable_clock_module(clk_modules_explicit_en[i],
MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN,
wait_for_enable);
@@ -215,12 +216,13 @@ void do_disable_clocks(u32 *const *clk_domains,
/* Clock modules that need to be put in SW_DISABLE */
- for (i = 0; (i < max) && clk_modules_disable[i]; i++)
+ for (i = 0; (i < max) && clk_modules_disable && clk_modules_disable[i];
+i++)
disable_clock_module(clk_modules_disable[i],
wait_for_disable);
/* Put the clock domains in SW_SLEEP mode */
- for (i = 0; (i < max) && clk_domains[i]; i++)
+ for (i = 0; (i < max) && clk_domains && clk_domains[i]; i++)
disable_clock_domain(clk_domains[i]);
}
--
2.17.1
[PATCH v8 04/28] arm: dts: sync am33xx with Linux 5.9-rc7
There have been several changes to the am33xx.dtsi, so this patch
re-syncs it with Linux.
Let's add proper interconnect hierarchy for l4 interconnect instances
with the related ti-sysc interconnect module data as documented in
Documentation/devicetree/bindings/bus/ti-sysc.txt of the Linux kernel.
With l4 interconnect hierarchy and ti-sysc interconnect target module
data in place, we can simply move all the related child devices to their
proper location and enable probing using ti-sysc.
The am33xx-clock.dtsi file is the same as that of the Linux kernel,
except for the reg property of the node l4-wkup-clkctrl@0.
As for the am33xx.dtsi file, all the devices with drivers not yet
implemented and those I was able to test with this patch have been moved
to am33xx-l4.dtsi. In case of any regressions, problem devices can be
reverted by moving them back and removing the related interconnect
target module node.
Signed-off-by: Dario Binacchi
---
(no changes since v4)
Changes in v4:
- Remove a blank line at end of file arch/arm/dts/am33xx-l4.dtsi.
arch/arm/dts/am335x-draco.dtsi | 11 +-
arch/arm/dts/am335x-evm.dts |2 +-
arch/arm/dts/am335x-evmsk.dts|2 +-
arch/arm/dts/am335x-guardian-u-boot.dtsi |5 -
arch/arm/dts/am335x-pxm2.dtsi|2 +-
arch/arm/dts/am335x-rut.dts |2 +-
arch/arm/dts/am335x-shc.dts |2 +-
arch/arm/dts/am33xx-clocks.dtsi | 106 +-
arch/arm/dts/am33xx-l4.dtsi | 1962 ++
arch/arm/dts/am33xx.dtsi | 721 +++-
10 files changed, 2273 insertions(+), 542 deletions(-)
create mode 100644 arch/arm/dts/am33xx-l4.dtsi
diff --git a/arch/arm/dts/am335x-draco.dtsi b/arch/arm/dts/am335x-draco.dtsi
index b38ff55e1d..2c125fcec9 100644
--- a/arch/arm/dts/am335x-draco.dtsi
+++ b/arch/arm/dts/am335x-draco.dtsi
@@ -20,11 +20,6 @@
};
ocp {
- uart0: serial@44e09000 {
- pinctrl-names = "default";
- pinctrl-0 = <_pins>;
- status = "okay";
- };
i2c0: i2c@44e0b000 {
pinctrl-names = "default";
@@ -112,6 +107,12 @@
status = "disabled";
};
+ {
+ pinctrl-names = "default";
+ pinctrl-0 = <_pins>;
+ status = "okay";
+};
+
{
status = "disabled";
};
diff --git a/arch/arm/dts/am335x-evm.dts b/arch/arm/dts/am335x-evm.dts
index 0bda4d4429..07288fb188 100644
--- a/arch/arm/dts/am335x-evm.dts
+++ b/arch/arm/dts/am335x-evm.dts
@@ -486,7 +486,7 @@
{
status = "okay";
- ecap0: ecap@48300100 {
+ ecap0: ecap@100 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <_pins>;
diff --git a/arch/arm/dts/am335x-evmsk.dts b/arch/arm/dts/am335x-evmsk.dts
index 5762967cf7..c94c33b595 100644
--- a/arch/arm/dts/am335x-evmsk.dts
+++ b/arch/arm/dts/am335x-evmsk.dts
@@ -531,7 +531,7 @@
{
status = "okay";
- ecap2: ecap@48304100 {
+ ecap2: ecap@100 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <_pins>;
diff --git a/arch/arm/dts/am335x-guardian-u-boot.dtsi
b/arch/arm/dts/am335x-guardian-u-boot.dtsi
index 705ef335bf..eae027c541 100644
--- a/arch/arm/dts/am335x-guardian-u-boot.dtsi
+++ b/arch/arm/dts/am335x-guardian-u-boot.dtsi
@@ -26,11 +26,6 @@
u-boot,dm-pre-reloc;
};
- {
- clocks = <_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
- clock-names = "int-clk";
-};
-
{
u-boot,dm-pre-reloc;
};
diff --git a/arch/arm/dts/am335x-pxm2.dtsi b/arch/arm/dts/am335x-pxm2.dtsi
index 19bd7e2420..645d221507 100644
--- a/arch/arm/dts/am335x-pxm2.dtsi
+++ b/arch/arm/dts/am335x-pxm2.dtsi
@@ -148,7 +148,7 @@
{
status = "okay";
- ecap0: ecap@48300100 {
+ ecap0: ecap@100 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <_pins>;
diff --git a/arch/arm/dts/am335x-rut.dts b/arch/arm/dts/am335x-rut.dts
index 145247344f..cc06f5d23a 100644
--- a/arch/arm/dts/am335x-rut.dts
+++ b/arch/arm/dts/am335x-rut.dts
@@ -174,7 +174,7 @@
{
status = "okay";
- ecap0: ecap@48300100 {
+ ecap0: ecap@100 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <_pins>;
diff --git a/arch/arm/dts/am335x-shc.dts b/arch/arm/dts/am335x-shc.dts
index 8e35c439e5..a41a0606b1 100644
--- a/arch/arm/dts/am335x-shc.dts
+++ b/arch/arm/dts/am335x-shc.dts
@@ -136,7 +136,7 @@
{
status = "okay";
- ehrpwm1: pwm@48302200 {
+ ehrpwm1: pwm@200 {
pinctrl-names = "default";
pinctrl-0 = <_pins>;
status = "okay";
diff --git a/arch/arm/dts/am33xx-clocks.dtsi b/arch/arm/dts/am33xx-clocks.dtsi
index 95d5c9d136..87c4410ee2 100644
--- a/arch/arm/dts/am33xx-clocks.dtsi
+++
[PATCH v8 11/28] arm: dts: am335x: include am33xx-u-boot.dtsi
Include the SoC U-boot DTS in each am335x--u-boot.dtsi.
Signed-off-by: Dario Binacchi
---
(no changes since v1)
arch/arm/dts/am335x-chiliboard-u-boot.dtsi | 2 ++
arch/arm/dts/am335x-evm-u-boot.dtsi| 2 ++
arch/arm/dts/am335x-evmsk-u-boot.dtsi | 2 ++
arch/arm/dts/am335x-guardian-u-boot.dtsi | 2 ++
arch/arm/dts/am335x-icev2-u-boot.dtsi | 3 +++
arch/arm/dts/am335x-pdu001-u-boot.dtsi | 2 ++
arch/arm/dts/am335x-pxm50-u-boot.dtsi | 2 ++
arch/arm/dts/am335x-regor-rdk-u-boot.dtsi | 2 ++
arch/arm/dts/am335x-rut-u-boot.dtsi| 2 ++
arch/arm/dts/am335x-shc-u-boot.dtsi| 2 ++
arch/arm/dts/am335x-wega-rdk-u-boot.dtsi | 2 ++
11 files changed, 23 insertions(+)
diff --git a/arch/arm/dts/am335x-chiliboard-u-boot.dtsi
b/arch/arm/dts/am335x-chiliboard-u-boot.dtsi
index 4f9d308039..06a13872ee 100644
--- a/arch/arm/dts/am335x-chiliboard-u-boot.dtsi
+++ b/arch/arm/dts/am335x-chiliboard-u-boot.dtsi
@@ -4,6 +4,8 @@
* Author: Marcin Niestroj
*/
+#include "am33xx-u-boot.dtsi"
+
/ {
chosen {
stdout-path =
diff --git a/arch/arm/dts/am335x-evm-u-boot.dtsi
b/arch/arm/dts/am335x-evm-u-boot.dtsi
index d7b049ef20..400a1d2cec 100644
--- a/arch/arm/dts/am335x-evm-u-boot.dtsi
+++ b/arch/arm/dts/am335x-evm-u-boot.dtsi
@@ -3,6 +3,8 @@
* Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
*/
+#include "am33xx-u-boot.dtsi"
+
/ {
panel {
u-boot,dm-pre-reloc;
diff --git a/arch/arm/dts/am335x-evmsk-u-boot.dtsi
b/arch/arm/dts/am335x-evmsk-u-boot.dtsi
index 599fb377e6..96798330b1 100644
--- a/arch/arm/dts/am335x-evmsk-u-boot.dtsi
+++ b/arch/arm/dts/am335x-evmsk-u-boot.dtsi
@@ -5,6 +5,8 @@
* Copyright (C) 2020 Dario Binacchi
*/
+#include "am33xx-u-boot.dtsi"
+
/ {
panel {
u-boot,dm-pre-reloc;
diff --git a/arch/arm/dts/am335x-guardian-u-boot.dtsi
b/arch/arm/dts/am335x-guardian-u-boot.dtsi
index eae027c541..c866ce83f3 100644
--- a/arch/arm/dts/am335x-guardian-u-boot.dtsi
+++ b/arch/arm/dts/am335x-guardian-u-boot.dtsi
@@ -4,6 +4,8 @@
* Copyright (C) 2018 Robert Bosch Power Tools GmbH
*/
+#include "am33xx-u-boot.dtsi"
+
/ {
ocp {
u-boot,dm-pre-reloc;
diff --git a/arch/arm/dts/am335x-icev2-u-boot.dtsi
b/arch/arm/dts/am335x-icev2-u-boot.dtsi
index cc9569af03..67bfac916e 100644
--- a/arch/arm/dts/am335x-icev2-u-boot.dtsi
+++ b/arch/arm/dts/am335x-icev2-u-boot.dtsi
@@ -2,6 +2,9 @@
/*
* Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
*/
+
+#include "am33xx-u-boot.dtsi"
+
/ {
xtal25mhz: xtal25mhz {
compatible = "fixed-clock";
diff --git a/arch/arm/dts/am335x-pdu001-u-boot.dtsi
b/arch/arm/dts/am335x-pdu001-u-boot.dtsi
index a799fe9bc3..4f4fc411f9 100644
--- a/arch/arm/dts/am335x-pdu001-u-boot.dtsi
+++ b/arch/arm/dts/am335x-pdu001-u-boot.dtsi
@@ -3,6 +3,8 @@
* Copyright (C) 2018 EETS GmbH - https://www.eets.ch/
*/
+#include "am33xx-u-boot.dtsi"
+
/ {
ocp {
u-boot,dm-pre-reloc;
diff --git a/arch/arm/dts/am335x-pxm50-u-boot.dtsi
b/arch/arm/dts/am335x-pxm50-u-boot.dtsi
index 77dfe6e262..65ed948c58 100644
--- a/arch/arm/dts/am335x-pxm50-u-boot.dtsi
+++ b/arch/arm/dts/am335x-pxm50-u-boot.dtsi
@@ -5,6 +5,8 @@
* Copyright (C) 2020 Dario Binacchi
*/
+#include "am33xx-u-boot.dtsi"
+
/ {
panel {
u-boot,dm-pre-reloc;
diff --git a/arch/arm/dts/am335x-regor-rdk-u-boot.dtsi
b/arch/arm/dts/am335x-regor-rdk-u-boot.dtsi
index 1ddd715875..4052d0ee21 100644
--- a/arch/arm/dts/am335x-regor-rdk-u-boot.dtsi
+++ b/arch/arm/dts/am335x-regor-rdk-u-boot.dtsi
@@ -3,6 +3,8 @@
* Copyright (C) 2020 Linumiz
*/
+#include "am33xx-u-boot.dtsi"
+
/ {
chosen {
#address-cells = <1>;
diff --git a/arch/arm/dts/am335x-rut-u-boot.dtsi
b/arch/arm/dts/am335x-rut-u-boot.dtsi
index b2b4aa596a..b16f75a764 100644
--- a/arch/arm/dts/am335x-rut-u-boot.dtsi
+++ b/arch/arm/dts/am335x-rut-u-boot.dtsi
@@ -5,6 +5,8 @@
* Copyright (C) 2020 Dario Binacchi
*/
+#include "am33xx-u-boot.dtsi"
+
/ {
panel {
u-boot,dm-pre-reloc;
diff --git a/arch/arm/dts/am335x-shc-u-boot.dtsi
b/arch/arm/dts/am335x-shc-u-boot.dtsi
index 2975839ea7..359ae05209 100644
--- a/arch/arm/dts/am335x-shc-u-boot.dtsi
+++ b/arch/arm/dts/am335x-shc-u-boot.dtsi
@@ -3,6 +3,8 @@
* Copyright (C) 2019 Heiko Schocher
*/
+#include "am33xx-u-boot.dtsi"
+
/ {
ocp {
u-boot,dm-pre-reloc;
diff --git a/arch/arm/dts/am335x-wega-rdk-u-boot.dtsi
b/arch/arm/dts/am335x-wega-rdk-u-boot.dtsi
index 634f1b0712..28fd62e231 100644
--- a/arch/arm/dts/am335x-wega-rdk-u-boot.dtsi
+++ b/arch/arm/dts/am335x-wega-rdk-u-boot.dtsi
@@ -3,6 +3,8 @@
* Copyright (C) 2019 DENX Software Engineering GmbH
*/
+#include "am33xx-u-boot.dtsi"
+
/ {
chosen {
#address-cells = <1>;
--
2.17.1
[PATCH v8 09/28] clk: ti: add divider clock driver
The patch adds support for TI divider clock binding. The driver uses
routines provided by the common clock framework (ccf).
The code is based on the drivers/clk/ti/divider.c driver of the Linux
kernel version 5.9-rc7.
For DT binding details see:
- Documentation/devicetree/bindings/clock/ti/divider.txt
Signed-off-by: Dario Binacchi
---
(no changes since v5)
Changes in v5:
- Move the clk-ti.c file to drivers/clk/ti with the name clk.c.
- Move the clk-ti.h file to drivers/clk/ti with the name clk.h.
- Move the clk-ti-divider.c file to drivers/clk/ti with the name
clk-divider.c.
Changes in v4:
- Include device_compat.h header for dev_xxx macros.
- Fix compilation errors on the dev parameter of the dev_xx macros.
Changes in v3:
- Remove doc/device-tree-bindings/clock/ti,autoidle.txt.
- Remove doc/device-tree-bindings/clock/ti,divider.txt.
- Add to commit message the references to linux kernel dt binding
documentation.
Changes in v2:
- Merged to patch [09/31] clk: ti: refactor mux and divider clock
drivers.
drivers/clk/ti/Kconfig | 6 +
drivers/clk/ti/Makefile | 3 +
drivers/clk/ti/clk-divider.c | 381 +++
drivers/clk/ti/clk-mux.c | 27 +--
drivers/clk/ti/clk.c | 34
drivers/clk/ti/clk.h | 13 ++
6 files changed, 439 insertions(+), 25 deletions(-)
create mode 100644 drivers/clk/ti/clk-divider.c
create mode 100644 drivers/clk/ti/clk.c
create mode 100644 drivers/clk/ti/clk.h
diff --git a/drivers/clk/ti/Kconfig b/drivers/clk/ti/Kconfig
index c430dd9b8a..87eea86c6f 100644
--- a/drivers/clk/ti/Kconfig
+++ b/drivers/clk/ti/Kconfig
@@ -10,6 +10,12 @@ config CLK_TI_AM3_DPLL
This enables the DPLL clock drivers support on AM33XX SoCs. The DPLL
provides all interface clocks and functional clocks to the processor.
+config CLK_TI_DIVIDER
+ bool "TI divider clock driver"
+ depends on CLK && OF_CONTROL && CLK_CCF
+ help
+ This enables the divider clock driver support on TI's SoCs.
+
config CLK_TI_MUX
bool "TI mux clock driver"
depends on CLK && OF_CONTROL && CLK_CCF
diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile
index 9e14b83cfe..fd7094cff0 100644
--- a/drivers/clk/ti/Makefile
+++ b/drivers/clk/ti/Makefile
@@ -3,5 +3,8 @@
# Copyright (C) 2020 Dario Binacchi
#
+obj-$(CONFIG_ARCH_OMAP2PLUS) += clk.o
+
obj-$(CONFIG_CLK_TI_AM3_DPLL) += clk-am3-dpll.o clk-am3-dpll-x2.o
+obj-$(CONFIG_CLK_TI_DIVIDER) += clk-divider.o
obj-$(CONFIG_CLK_TI_MUX) += clk-mux.o
diff --git a/drivers/clk/ti/clk-divider.c b/drivers/clk/ti/clk-divider.c
new file mode 100644
index 00..d448197b1f
--- /dev/null
+++ b/drivers/clk/ti/clk-divider.c
@@ -0,0 +1,381 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * TI divider clock support
+ *
+ * Copyright (C) 2020 Dario Binacchi
+ *
+ * Loosely based on Linux kernel drivers/clk/ti/divider.c
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include "clk.h"
+
+/*
+ * The reverse of DIV_ROUND_UP: The maximum number which
+ * divided by m is r
+ */
+#define MULT_ROUND_UP(r, m) ((r) * (m) + (m) - 1)
+
+struct clk_ti_divider_priv {
+ struct clk parent;
+ fdt_addr_t reg;
+ const struct clk_div_table *table;
+ u8 shift;
+ u8 flags;
+ u8 div_flags;
+ s8 latch;
+ u16 min;
+ u16 max;
+ u16 mask;
+};
+
+static unsigned int _get_div(const struct clk_div_table *table, ulong flags,
+unsigned int val)
+{
+ if (flags & CLK_DIVIDER_ONE_BASED)
+ return val;
+
+ if (flags & CLK_DIVIDER_POWER_OF_TWO)
+ return 1 << val;
+
+ if (table)
+ return clk_divider_get_table_div(table, val);
+
+ return val + 1;
+}
+
+static unsigned int _get_val(const struct clk_div_table *table, ulong flags,
+unsigned int div)
+{
+ if (flags & CLK_DIVIDER_ONE_BASED)
+ return div;
+
+ if (flags & CLK_DIVIDER_POWER_OF_TWO)
+ return __ffs(div);
+
+ if (table)
+ return clk_divider_get_table_val(table, div);
+
+ return div - 1;
+}
+
+static int _div_round_up(const struct clk_div_table *table, ulong parent_rate,
+ulong rate)
+{
+ const struct clk_div_table *clkt;
+ int up = INT_MAX;
+ int div = DIV_ROUND_UP_ULL((u64)parent_rate, rate);
+
+ for (clkt = table; clkt->div; clkt++) {
+ if (clkt->div == div)
+ return clkt->div;
+ else if (clkt->div < div)
+ continue;
+
+ if ((clkt->div - div) < (up - div))
+ up = clkt->div;
+ }
+
+ return up;
+}
+
+static int _div_round(const struct clk_div_table *table, ulong parent_rate,
+ ulong rate)
+{
+ if (table)
+ return
[PATCH v8 10/28] clk: ti: add gate clock driver
The patch adds support for TI gate clock binding. The code is based on
the drivers/clk/ti/gate.c driver of the Linux kernel version 5.9-rc7.
For DT binding details see:
- Documentation/devicetree/bindings/clock/ti/gate.txt
Signed-off-by: Dario Binacchi
---
(no changes since v5)
Changes in v5:
- Move the clk-ti-gate.c file to drivers/clk/ti with the name
clk-gate.c.
Changes in v4:
- Include device_compat.h header for dev_xxx macros.
Changes in v3:
- Remove doc/device-tree-bindings/clock/gpio-gate-clock.txt.
- Remove doc/device-tree-bindings/clock/ti,clockdomain.txt.
- Remove doc/device-tree-bindings/clock/ti,gate.txt.
- Add to commit message the references to linux kernel dt binding
documentation.
drivers/clk/ti/Kconfig| 6 +++
drivers/clk/ti/Makefile | 1 +
drivers/clk/ti/clk-gate.c | 93 +++
3 files changed, 100 insertions(+)
create mode 100644 drivers/clk/ti/clk-gate.c
diff --git a/drivers/clk/ti/Kconfig b/drivers/clk/ti/Kconfig
index 87eea86c6f..30959a316a 100644
--- a/drivers/clk/ti/Kconfig
+++ b/drivers/clk/ti/Kconfig
@@ -16,6 +16,12 @@ config CLK_TI_DIVIDER
help
This enables the divider clock driver support on TI's SoCs.
+config CLK_TI_GATE
+ bool "TI gate clock driver"
+ depends on CLK && OF_CONTROL
+ help
+ This enables the gate clock driver support on TI's SoCs.
+
config CLK_TI_MUX
bool "TI mux clock driver"
depends on CLK && OF_CONTROL && CLK_CCF
diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile
index fd7094cff0..f8aa735c83 100644
--- a/drivers/clk/ti/Makefile
+++ b/drivers/clk/ti/Makefile
@@ -7,4 +7,5 @@ obj-$(CONFIG_ARCH_OMAP2PLUS) += clk.o
obj-$(CONFIG_CLK_TI_AM3_DPLL) += clk-am3-dpll.o clk-am3-dpll-x2.o
obj-$(CONFIG_CLK_TI_DIVIDER) += clk-divider.o
+obj-$(CONFIG_CLK_TI_GATE) += clk-gate.o
obj-$(CONFIG_CLK_TI_MUX) += clk-mux.o
diff --git a/drivers/clk/ti/clk-gate.c b/drivers/clk/ti/clk-gate.c
new file mode 100644
index 00..6c5432c823
--- /dev/null
+++ b/drivers/clk/ti/clk-gate.c
@@ -0,0 +1,93 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * TI gate clock support
+ *
+ * Copyright (C) 2020 Dario Binacchi
+ *
+ * Loosely based on Linux kernel drivers/clk/ti/gate.c
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+struct clk_ti_gate_priv {
+ fdt_addr_t reg;
+ u8 enable_bit;
+ u32 flags;
+ bool invert_enable;
+};
+
+static int clk_ti_gate_disable(struct clk *clk)
+{
+ struct clk_ti_gate_priv *priv = dev_get_priv(clk->dev);
+ u32 v;
+
+ v = readl(priv->reg);
+ if (priv->invert_enable)
+ v |= (1 << priv->enable_bit);
+ else
+ v &= ~(1 << priv->enable_bit);
+
+ writel(v, priv->reg);
+ /* No OCP barrier needed here since it is a disable operation */
+ return 0;
+}
+
+static int clk_ti_gate_enable(struct clk *clk)
+{
+ struct clk_ti_gate_priv *priv = dev_get_priv(clk->dev);
+ u32 v;
+
+ v = readl(priv->reg);
+ if (priv->invert_enable)
+ v &= ~(1 << priv->enable_bit);
+ else
+ v |= (1 << priv->enable_bit);
+
+ writel(v, priv->reg);
+ /* OCP barrier */
+ v = readl(priv->reg);
+ return 0;
+}
+
+static int clk_ti_gate_ofdata_to_platdata(struct udevice *dev)
+{
+ struct clk_ti_gate_priv *priv = dev_get_priv(dev);
+
+ priv->reg = dev_read_addr(dev);
+ if (priv->reg == FDT_ADDR_T_NONE) {
+ dev_err(dev, "failed to get control register\n");
+ return -EINVAL;
+ }
+
+ dev_dbg(dev, "reg=0x%08lx\n", priv->reg);
+ priv->enable_bit = dev_read_u32_default(dev, "ti,bit-shift", 0);
+ if (dev_read_bool(dev, "ti,set-rate-parent"))
+ priv->flags |= CLK_SET_RATE_PARENT;
+
+ priv->invert_enable = dev_read_bool(dev, "ti,set-bit-to-disable");
+ return 0;
+}
+
+static struct clk_ops clk_ti_gate_ops = {
+ .enable = clk_ti_gate_enable,
+ .disable = clk_ti_gate_disable,
+};
+
+static const struct udevice_id clk_ti_gate_of_match[] = {
+ { .compatible = "ti,gate-clock" },
+ { },
+};
+
+U_BOOT_DRIVER(clk_ti_gate) = {
+ .name = "ti_gate_clock",
+ .id = UCLASS_CLK,
+ .of_match = clk_ti_gate_of_match,
+ .ofdata_to_platdata = clk_ti_gate_ofdata_to_platdata,
+ .priv_auto_alloc_size = sizeof(struct clk_ti_gate_priv),
+ .ops = _ti_gate_ops,
+};
--
2.17.1
[PATCH v8 08/28] clk: ti: am33xx: add DPLL clock drivers
The digital phase-locked loop (DPLL) provides all interface clocks and
functional clocks to the processor of the AM33xx device. The AM33xx
device integrates five different DPLLs:
* Core DPLL
* Per DPLL
* LCD DPLL
* DDR DPLL
* MPU DPLL
The patch adds support for the compatible strings:
* "ti,am3-dpll-core-clock"
* "ti,am3-dpll-no-gate-clock"
* "ti,am3-dpll-no-gate-j-type-clock"
* "ti,am3-dpll-x2-clock"
The code is loosely based on the drivers/clk/ti/dpll.c drivers of the
Linux kernel version 5.9-rc7.
For DT binding details see:
- Documentation/devicetree/bindings/clock/ti/dpll.txt
Signed-off-by: Dario Binacchi
---
(no changes since v5)
Changes in v5:
- Move the clk-ti-am3-dpll.c file to drivers/clk/ti with the name
clk-am3-dpll.c.
- Move the clk-ti-am3-dpll-x2.c file to drivers/clk/ti with the name
clk-am3-dpll-x2.c.
Changes in v4:
- Include device_compat.h header for dev_xxx macros.
- Fix compilation errors on the dev parameter of the dev_xx macros.
Changes in v3:
- Remove doc/device-tree-bindings/clock/ti,dpll.txt.
- Add to commit message the references to linux kernel dt binding
documentation.
drivers/clk/ti/Kconfig | 7 +
drivers/clk/ti/Makefile | 1 +
drivers/clk/ti/clk-am3-dpll-x2.c | 79 +
drivers/clk/ti/clk-am3-dpll.c| 268 +++
4 files changed, 355 insertions(+)
create mode 100644 drivers/clk/ti/clk-am3-dpll-x2.c
create mode 100644 drivers/clk/ti/clk-am3-dpll.c
diff --git a/drivers/clk/ti/Kconfig b/drivers/clk/ti/Kconfig
index be4f26817f..c430dd9b8a 100644
--- a/drivers/clk/ti/Kconfig
+++ b/drivers/clk/ti/Kconfig
@@ -3,6 +3,13 @@
# Copyright (C) 2020 Dario Binacchi
#
+config CLK_TI_AM3_DPLL
+ bool "TI AM33XX Digital Phase-Locked Loop (DPLL) clock drivers"
+ depends on CLK && OF_CONTROL
+ help
+ This enables the DPLL clock drivers support on AM33XX SoCs. The DPLL
+ provides all interface clocks and functional clocks to the processor.
+
config CLK_TI_MUX
bool "TI mux clock driver"
depends on CLK && OF_CONTROL && CLK_CCF
diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile
index 5faf68d30e..9e14b83cfe 100644
--- a/drivers/clk/ti/Makefile
+++ b/drivers/clk/ti/Makefile
@@ -3,4 +3,5 @@
# Copyright (C) 2020 Dario Binacchi
#
+obj-$(CONFIG_CLK_TI_AM3_DPLL) += clk-am3-dpll.o clk-am3-dpll-x2.o
obj-$(CONFIG_CLK_TI_MUX) += clk-mux.o
diff --git a/drivers/clk/ti/clk-am3-dpll-x2.c b/drivers/clk/ti/clk-am3-dpll-x2.c
new file mode 100644
index 00..3aa35f0e6c
--- /dev/null
+++ b/drivers/clk/ti/clk-am3-dpll-x2.c
@@ -0,0 +1,79 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * TI DPLL x2 clock support
+ *
+ * Copyright (C) 2020 Dario Binacchi
+ *
+ * Loosely based on Linux kernel drivers/clk/ti/dpll.c
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+struct clk_ti_am3_dpll_x2_priv {
+ struct clk parent;
+};
+
+static ulong clk_ti_am3_dpll_x2_get_rate(struct clk *clk)
+{
+ struct clk_ti_am3_dpll_x2_priv *priv = dev_get_priv(clk->dev);
+ unsigned long rate;
+
+ rate = clk_get_rate(>parent);
+ if (IS_ERR_VALUE(rate))
+ return rate;
+
+ rate *= 2;
+ dev_dbg(clk->dev, "rate=%ld\n", rate);
+ return rate;
+}
+
+const struct clk_ops clk_ti_am3_dpll_x2_ops = {
+ .get_rate = clk_ti_am3_dpll_x2_get_rate,
+};
+
+static int clk_ti_am3_dpll_x2_remove(struct udevice *dev)
+{
+ struct clk_ti_am3_dpll_x2_priv *priv = dev_get_priv(dev);
+ int err;
+
+ err = clk_release_all(>parent, 1);
+ if (err) {
+ dev_err(dev, "failed to release parent clock\n");
+ return err;
+ }
+
+ return 0;
+}
+
+static int clk_ti_am3_dpll_x2_probe(struct udevice *dev)
+{
+ struct clk_ti_am3_dpll_x2_priv *priv = dev_get_priv(dev);
+ int err;
+
+ err = clk_get_by_index(dev, 0, >parent);
+ if (err) {
+ dev_err(dev, "%s: failed to get parent clock\n", __func__);
+ return err;
+ }
+
+ return 0;
+}
+
+static const struct udevice_id clk_ti_am3_dpll_x2_of_match[] = {
+ {.compatible = "ti,am3-dpll-x2-clock"},
+ {}
+};
+
+U_BOOT_DRIVER(clk_ti_am3_dpll_x2) = {
+ .name = "ti_am3_dpll_x2_clock",
+ .id = UCLASS_CLK,
+ .of_match = clk_ti_am3_dpll_x2_of_match,
+ .probe = clk_ti_am3_dpll_x2_probe,
+ .remove = clk_ti_am3_dpll_x2_remove,
+ .priv_auto_alloc_size = sizeof(struct clk_ti_am3_dpll_x2_priv),
+ .ops = _ti_am3_dpll_x2_ops,
+};
diff --git a/drivers/clk/ti/clk-am3-dpll.c b/drivers/clk/ti/clk-am3-dpll.c
new file mode 100644
index 00..d50660aae2
--- /dev/null
+++ b/drivers/clk/ti/clk-am3-dpll.c
@@ -0,0 +1,268 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * TI DPLL clock support
+ *
+ * Copyright (C) 2020 Dario Binacchi
+ *
+ * Loosely based on Linux kernel drivers/clk/ti/dpll.c
+ */
+
+#include
+#include
+#include
+#include
+#include
[PATCH v8 07/28] arm: ti: am33xx: add DPLL_EN_FAST_RELOCK_BYPASS macro
Add missing DPLL_EN_FAST_RELOCK_BYPASS macro. Used to put the DPLL in idle bypass fast relock mode. Signed-off-by: Dario Binacchi --- (no changes since v1) arch/arm/include/asm/arch-am33xx/clock.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/include/asm/arch-am33xx/clock.h b/arch/arm/include/asm/arch-am33xx/clock.h index dc7a9b188d..5d775902bb 100644 --- a/arch/arm/include/asm/arch-am33xx/clock.h +++ b/arch/arm/include/asm/arch-am33xx/clock.h @@ -66,6 +66,7 @@ #define DPLL_EN_STOP 1 #define DPLL_EN_MN_BYPASS 4 #define DPLL_EN_LOW_POWER_BYPASS 5 +#define DPLL_EN_FAST_RELOCK_BYPASS 6 #define DPLL_EN_LOCK 7 /* CM_IDLEST_DPLL fields */ -- 2.17.1
[PATCH v8 06/28] clk: ti: add mux clock driver
The driver manages a register-mapped multiplexer with multiple input
clock signals or parents, one of which can be selected as output. It
uses routines provided by the common clock framework (ccf).
The code is based on the drivers/clk/ti/mux.c driver of the Linux
kernel version 5.9-rc7.
For DT binding details see:
- Documentation/devicetree/bindings/clock/ti/mux.txt
Signed-off-by: Dario Binacchi
---
(no changes since v5)
Changes in v5:
- Create drivers/clk/ti directory.
- Move the clk-ti-mux.c file to drivers/clk/ti and rename it clk-mux.c
Changes in v4:
- Include device_compat.h header for dev_xxx macros.
Changes in v3:
- Remove doc/device-tree-bindings/clock/clock-bindings.txt.
- Remove doc/device-tree-bindings/clock/ti,mux.txt.
- Add to commit message the references to linux kernel dt binding
documentation.
drivers/clk/Kconfig | 1 +
drivers/clk/Makefile | 1 +
drivers/clk/ti/Kconfig | 10 ++
drivers/clk/ti/Makefile | 6 +
drivers/clk/ti/clk-mux.c | 276 +++
5 files changed, 294 insertions(+)
create mode 100644 drivers/clk/ti/Kconfig
create mode 100644 drivers/clk/ti/Makefile
create mode 100644 drivers/clk/ti/clk-mux.c
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 4dfbad7986..9e54929039 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -179,6 +179,7 @@ source "drivers/clk/renesas/Kconfig"
source "drivers/clk/sunxi/Kconfig"
source "drivers/clk/sifive/Kconfig"
source "drivers/clk/tegra/Kconfig"
+source "drivers/clk/ti/Kconfig"
source "drivers/clk/uniphier/Kconfig"
config ICS8N3QV01
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index d1e295ac7c..2581fe0a19 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -14,6 +14,7 @@ obj-$(CONFIG_$(SPL_TPL_)CLK_COMPOSITE_CCF) += clk-composite.o
obj-y += analogbits/
obj-y += imx/
obj-y += tegra/
+obj-y += ti/
obj-$(CONFIG_ARCH_ASPEED) += aspeed/
obj-$(CONFIG_ARCH_MEDIATEK) += mediatek/
obj-$(CONFIG_ARCH_MTMIPS) += mtmips/
diff --git a/drivers/clk/ti/Kconfig b/drivers/clk/ti/Kconfig
new file mode 100644
index 00..be4f26817f
--- /dev/null
+++ b/drivers/clk/ti/Kconfig
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2020 Dario Binacchi
+#
+
+config CLK_TI_MUX
+ bool "TI mux clock driver"
+ depends on CLK && OF_CONTROL && CLK_CCF
+ help
+ This enables the mux clock driver support on TI's SoCs.
diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile
new file mode 100644
index 00..5faf68d30e
--- /dev/null
+++ b/drivers/clk/ti/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2020 Dario Binacchi
+#
+
+obj-$(CONFIG_CLK_TI_MUX) += clk-mux.o
diff --git a/drivers/clk/ti/clk-mux.c b/drivers/clk/ti/clk-mux.c
new file mode 100644
index 00..9720c84513
--- /dev/null
+++ b/drivers/clk/ti/clk-mux.c
@@ -0,0 +1,276 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * TI multiplexer clock support
+ *
+ * Copyright (C) 2020 Dario Binacchi
+ *
+ * Based on Linux kernel drivers/clk/ti/mux.c
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+struct clk_ti_mux_priv {
+ struct clk_bulk parents;
+ fdt_addr_t reg;
+ u32 flags;
+ u32 mux_flags;
+ u32 mask;
+ u32 shift;
+ s32 latch;
+};
+
+static void clk_ti_mux_rmw(u32 val, u32 mask, fdt_addr_t reg)
+{
+ u32 v;
+
+ v = readl(reg);
+ v &= ~mask;
+ v |= val;
+ writel(v, reg);
+}
+
+static void clk_ti_mux_latch(fdt_addr_t reg, s8 shift)
+{
+ u32 latch;
+
+ if (shift < 0)
+ return;
+
+ latch = 1 << shift;
+
+ clk_ti_mux_rmw(latch, latch, reg);
+ clk_ti_mux_rmw(0, latch, reg);
+ readl(reg); /* OCP barrier */
+}
+
+static struct clk *clk_ti_mux_get_parent_by_index(struct clk_bulk *parents,
+ int index)
+{
+ if (index < 0 || !parents)
+ return ERR_PTR(-EINVAL);
+
+ if (index >= parents->count)
+ return ERR_PTR(-ENODEV);
+
+ return >clks[index];
+}
+
+static int clk_ti_mux_get_parent_index(struct clk_bulk *parents,
+ struct clk *parent)
+{
+ int i;
+
+ if (!parents || !parent)
+ return -EINVAL;
+
+ for (i = 0; i < parents->count; i++) {
+ if (parents->clks[i].dev == parent->dev)
+ return i;
+ }
+
+ return -ENODEV;
+}
+
+static int clk_ti_mux_get_index(struct clk *clk)
+{
+ struct clk_ti_mux_priv *priv = dev_get_priv(clk->dev);
+ u32 val;
+
+ val = readl(priv->reg);
+ val >>= priv->shift;
+ val &= priv->mask;
+
+ if (val && (priv->flags & CLK_MUX_INDEX_BIT))
+ val = ffs(val) - 1;
+
+ if (val && (priv->flags & CLK_MUX_INDEX_ONE))
+ val--;
+
+ if (val >= priv->parents.count)
+
[PATCH v8 03/28] bus: ti: add minimal sysc interconnect target driver
We can handle the sysc interconnect target module in a generic way for
many TI SoCs. Initially let's just enable domain clocks before the
children are probed.
The code is loosely based on the drivers/bus/ti-sysc.c of the Linux
kernel version 5.9-rc7.
For DT binding details see:
- Documentation/devicetree/bindings/bus/ti-sysc.txt
Signed-off-by: Dario Binacchi
---
Changes in v8:
- Imply CONFIG_TI_SYSC only if CONFIG_DM and CONFIG_OF_CONTROL are enabled.
- Revert change on cm_t335_defconfig added on version 7 of the series.
Changes in v7:
- Not all OMAP2 platform need CONFIG_TI_SYSC.
Set CONFIG_TI_SYSC as imply and disable it to fix building errors in:
nokia_rx51_defconfig
cm_t335_defconfig
Changes in v4:
- Include device_compat.h header for dev_xxx macros.
arch/arm/Kconfig | 1 +
configs/nokia_rx51_defconfig | 1 +
drivers/bus/Kconfig | 7 ++
drivers/bus/Makefile | 1 +
drivers/bus/ti-sysc.c| 166 +++
5 files changed, 176 insertions(+)
create mode 100644 drivers/bus/ti-sysc.c
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index fbe90875ae..6b5235e740 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -799,6 +799,7 @@ config ARCH_OMAP2PLUS
select SPL_BOARD_INIT if SPL
select SPL_STACK_R if SPL
select SUPPORT_SPL
+ imply TI_SYSC if DM && OF_CONTROL
imply FIT
config ARCH_MESON
diff --git a/configs/nokia_rx51_defconfig b/configs/nokia_rx51_defconfig
index d0c8929525..30a02e2bc3 100644
--- a/configs/nokia_rx51_defconfig
+++ b/configs/nokia_rx51_defconfig
@@ -4,6 +4,7 @@ CONFIG_ARCH_OMAP2PLUS=y
CONFIG_SYS_TEXT_BASE=0x80008000
CONFIG_NR_DRAM_BANKS=2
CONFIG_TARGET_NOKIA_RX51=y
+# CONFIG_TI_SYSC is not set
# CONFIG_FIT is not set
CONFIG_BOOTDELAY=30
CONFIG_AUTOBOOT_KEYED=y
diff --git a/drivers/bus/Kconfig b/drivers/bus/Kconfig
index 07a33c6287..733bec5a56 100644
--- a/drivers/bus/Kconfig
+++ b/drivers/bus/Kconfig
@@ -5,6 +5,13 @@
menu "Bus devices"
+config TI_SYSC
+ bool "TI sysc interconnect target module driver"
+ depends on ARCH_OMAP2PLUS
+ help
+ Generic driver for Texas Instruments interconnect target module
+ found on many TI SoCs.
+
config UNIPHIER_SYSTEM_BUS
bool "UniPhier System Bus driver"
depends on ARCH_UNIPHIER
diff --git a/drivers/bus/Makefile b/drivers/bus/Makefile
index 0b97fc1f8b..875bb4ed42 100644
--- a/drivers/bus/Makefile
+++ b/drivers/bus/Makefile
@@ -3,4 +3,5 @@
# Makefile for the bus drivers.
#
+obj-$(CONFIG_TI_SYSC) += ti-sysc.o
obj-$(CONFIG_UNIPHIER_SYSTEM_BUS) += uniphier-system-bus.o
diff --git a/drivers/bus/ti-sysc.c b/drivers/bus/ti-sysc.c
new file mode 100644
index 00..65974a70a6
--- /dev/null
+++ b/drivers/bus/ti-sysc.c
@@ -0,0 +1,166 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Texas Instruments sysc interconnect target driver
+ *
+ * Copyright (C) 2020 Dario Binacchi
+ */
+
+#include
+#include
+#include
+#include
+
+enum ti_sysc_clocks {
+ TI_SYSC_FCK,
+ TI_SYSC_ICK,
+ TI_SYSC_MAX_CLOCKS,
+};
+
+static const char *const clock_names[] = {"fck", "ick"};
+
+struct ti_sysc_priv {
+ int clocks_count;
+ struct clk clocks[TI_SYSC_MAX_CLOCKS];
+};
+
+static const struct udevice_id ti_sysc_ids[] = {
+ {.compatible = "ti,sysc-omap2"},
+ {.compatible = "ti,sysc-omap4"},
+ {.compatible = "ti,sysc-omap4-simple"},
+ {.compatible = "ti,sysc-omap3430-sr"},
+ {.compatible = "ti,sysc-omap3630-sr"},
+ {.compatible = "ti,sysc-omap4-sr"},
+ {.compatible = "ti,sysc-omap3-sham"},
+ {.compatible = "ti,sysc-omap-aes"},
+ {.compatible = "ti,sysc-mcasp"},
+ {.compatible = "ti,sysc-usb-host-fs"},
+ {}
+};
+
+static int ti_sysc_get_one_clock(struct udevice *dev, enum ti_sysc_clocks
index)
+{
+ struct ti_sysc_priv *priv = dev_get_priv(dev);
+ const char *name;
+ int err;
+
+ switch (index) {
+ case TI_SYSC_FCK:
+ break;
+ case TI_SYSC_ICK:
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ name = clock_names[index];
+
+ err = clk_get_by_name(dev, name, >clocks[index]);
+ if (err) {
+ if (err == -ENODATA)
+ return 0;
+
+ dev_err(dev, "failed to get %s clock\n", name);
+ return err;
+ }
+
+ return 0;
+}
+
+static int ti_sysc_put_clocks(struct udevice *dev)
+{
+ struct ti_sysc_priv *priv = dev_get_priv(dev);
+ int err;
+
+ err = clk_release_all(priv->clocks, priv->clocks_count);
+ if (err)
+ dev_err(dev, "failed to release all clocks\n");
+
+ return err;
+}
+
+static int ti_sysc_get_clocks(struct udevice *dev)
+{
+ struct ti_sysc_priv *priv = dev_get_priv(dev);
+ int i, err;
+
+ for (i = 0; i < TI_SYSC_MAX_CLOCKS; i++) {
+ err =
[PATCH v8 05/28] clk: add clk_round_rate()
It returns the rate which will be set if you ask clk_set_rate() to set
that rate. It provides a way to query exactly what rate you'll get if
you call clk_set_rate() with that same argument.
So essentially, clk_round_rate() and clk_set_rate() are equivalent
except the former does not modify the clock hardware in any way.
Signed-off-by: Dario Binacchi
Reviewed-by: Simon Glass
Reviewed-by: Sean Anderson
---
(no changes since v4)
Changes in v4:
- Update clk_round_rate description.
- Add Sean Anderson review.
arch/sandbox/include/asm/clk.h | 9 +
drivers/clk/clk-uclass.c | 15 +++
drivers/clk/clk_sandbox.c | 17 +
drivers/clk/clk_sandbox_test.c | 10 ++
include/clk-uclass.h | 8
include/clk.h | 28
test/dm/clk.c | 22 ++
7 files changed, 109 insertions(+)
diff --git a/arch/sandbox/include/asm/clk.h b/arch/sandbox/include/asm/clk.h
index c184c4bffc..0294baee27 100644
--- a/arch/sandbox/include/asm/clk.h
+++ b/arch/sandbox/include/asm/clk.h
@@ -105,6 +105,15 @@ int sandbox_clk_test_get_bulk(struct udevice *dev);
* @return:The rate of the clock.
*/
ulong sandbox_clk_test_get_rate(struct udevice *dev, int id);
+/**
+ * sandbox_clk_test_round_rate - Ask the sandbox clock test device to round a
+ * clock's rate.
+ *
+ * @dev: The sandbox clock test (client) device.
+ * @id:The test device's clock ID to configure.
+ * @return:The rounded rate of the clock.
+ */
+ulong sandbox_clk_test_round_rate(struct udevice *dev, int id, ulong rate);
/**
* sandbox_clk_test_set_rate - Ask the sandbox clock test device to set a
* clock's rate.
diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c
index ac954a34d2..3b8e27e4a5 100644
--- a/drivers/clk/clk-uclass.c
+++ b/drivers/clk/clk-uclass.c
@@ -523,6 +523,21 @@ long long clk_get_parent_rate(struct clk *clk)
return pclk->rate;
}
+ulong clk_round_rate(struct clk *clk, ulong rate)
+{
+ const struct clk_ops *ops;
+
+ debug("%s(clk=%p, rate=%lu)\n", __func__, clk, rate);
+ if (!clk_valid(clk))
+ return 0;
+
+ ops = clk_dev_ops(clk->dev);
+ if (!ops->round_rate)
+ return -ENOSYS;
+
+ return ops->round_rate(clk, rate);
+}
+
ulong clk_set_rate(struct clk *clk, ulong rate)
{
const struct clk_ops *ops;
diff --git a/drivers/clk/clk_sandbox.c b/drivers/clk/clk_sandbox.c
index 0ff1b49633..0751e923e7 100644
--- a/drivers/clk/clk_sandbox.c
+++ b/drivers/clk/clk_sandbox.c
@@ -30,6 +30,22 @@ static ulong sandbox_clk_get_rate(struct clk *clk)
return priv->rate[clk->id];
}
+static ulong sandbox_clk_round_rate(struct clk *clk, ulong rate)
+{
+ struct sandbox_clk_priv *priv = dev_get_priv(clk->dev);
+
+ if (!priv->probed)
+ return -ENODEV;
+
+ if (clk->id >= SANDBOX_CLK_ID_COUNT)
+ return -EINVAL;
+
+ if (!rate)
+ return -EINVAL;
+
+ return rate;
+}
+
static ulong sandbox_clk_set_rate(struct clk *clk, ulong rate)
{
struct sandbox_clk_priv *priv = dev_get_priv(clk->dev);
@@ -103,6 +119,7 @@ static int sandbox_clk_free(struct clk *clk)
}
static struct clk_ops sandbox_clk_ops = {
+ .round_rate = sandbox_clk_round_rate,
.get_rate = sandbox_clk_get_rate,
.set_rate = sandbox_clk_set_rate,
.enable = sandbox_clk_enable,
diff --git a/drivers/clk/clk_sandbox_test.c b/drivers/clk/clk_sandbox_test.c
index 873383856f..f7b77aa674 100644
--- a/drivers/clk/clk_sandbox_test.c
+++ b/drivers/clk/clk_sandbox_test.c
@@ -86,6 +86,16 @@ ulong sandbox_clk_test_get_rate(struct udevice *dev, int id)
return clk_get_rate(sbct->clkps[id]);
}
+ulong sandbox_clk_test_round_rate(struct udevice *dev, int id, ulong rate)
+{
+ struct sandbox_clk_test *sbct = dev_get_priv(dev);
+
+ if (id < 0 || id >= SANDBOX_CLK_TEST_ID_COUNT)
+ return -EINVAL;
+
+ return clk_round_rate(sbct->clkps[id], rate);
+}
+
ulong sandbox_clk_test_set_rate(struct udevice *dev, int id, ulong rate)
{
struct sandbox_clk_test *sbct = dev_get_priv(dev);
diff --git a/include/clk-uclass.h b/include/clk-uclass.h
index dac42dab36..50e8681b55 100644
--- a/include/clk-uclass.h
+++ b/include/clk-uclass.h
@@ -61,6 +61,14 @@ struct clk_ops {
* @return 0 if OK, or a negative error code.
*/
int (*rfree)(struct clk *clock);
+ /**
+* round_rate() - Adjust a rate to the exact rate a clock can provide.
+*
+* @clk:The clock to manipulate.
+* @rate: Desidered clock rate in Hz.
+* @return rounded rate in Hz, or -ve error code.
+*/
+ ulong (*round_rate)(struct clk *clk, ulong rate);
/**
* get_rate() - Get current clock rate.
*
diff --git a/include/clk.h
[PATCH v8 02/28] dt-bindings: bus: ti-sysc: resync with Linux 5.9-rc7
Add support for PRUSS SYSC type: The PRUSS module has a SYSCFG which is unique. The SYSCFG has two additional unique fields called STANDBY_INIT and SUB_MWAIT in addition to regular IDLE_MODE and STANDBY_MODE fields. Add the bindings for this new sysc type. Add support for MCAN on dra76x: The dra76x MCAN generic interconnect module has a its own format for the bits in the control registers. Signed-off-by: Dario Binacchi --- (no changes since v1) include/dt-bindings/bus/ti-sysc.h | 6 ++ 1 file changed, 6 insertions(+) diff --git a/include/dt-bindings/bus/ti-sysc.h b/include/dt-bindings/bus/ti-sysc.h index 2c005376ac..eae4274543 100644 --- a/include/dt-bindings/bus/ti-sysc.h +++ b/include/dt-bindings/bus/ti-sysc.h @@ -15,6 +15,12 @@ /* SmartReflex sysc found on 36xx and later */ #define SYSC_OMAP3_SR_ENAWAKEUP(1 << 26) +#define SYSC_DRA7_MCAN_ENAWAKEUP (1 << 4) + +/* PRUSS sysc found on AM33xx/AM43xx/AM57xx */ +#define SYSC_PRUSS_SUB_MWAIT (1 << 5) +#define SYSC_PRUSS_STANDBY_INIT(1 << 4) + /* SYSCONFIG STANDBYMODE/MIDLEMODE/SIDLEMODE supported by hardware */ #define SYSC_IDLE_FORCE0 #define SYSC_IDLE_NO 1 -- 2.17.1
[PATCH v8 01/28] clk: export generic routines
Export routines that can be used by other drivers avoiding duplicating
code.
Signed-off-by: Dario Binacchi
Reviewed-by: Simon Glass
---
(no changes since v2)
Changes in v2:
- Add the clk_ prefix to the divider functions.
- Add kernel-doc comments to the exported functions.
drivers/clk/clk-divider.c| 24 +++
include/linux/clk-provider.h | 57
2 files changed, 69 insertions(+), 12 deletions(-)
diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
index 8f59d7fb72..9df50a5e72 100644
--- a/drivers/clk/clk-divider.c
+++ b/drivers/clk/clk-divider.c
@@ -28,8 +28,8 @@
#define UBOOT_DM_CLK_CCF_DIVIDER "ccf_clk_divider"
-static unsigned int _get_table_div(const struct clk_div_table *table,
- unsigned int val)
+unsigned int clk_divider_get_table_div(const struct clk_div_table *table,
+ unsigned int val)
{
const struct clk_div_table *clkt;
@@ -49,7 +49,7 @@ static unsigned int _get_div(const struct clk_div_table
*table,
if (flags & CLK_DIVIDER_MAX_AT_ZERO)
return val ? val : clk_div_mask(width) + 1;
if (table)
- return _get_table_div(table, val);
+ return clk_divider_get_table_div(table, val);
return val + 1;
}
@@ -89,8 +89,8 @@ static ulong clk_divider_recalc_rate(struct clk *clk)
divider->flags, divider->width);
}
-static bool _is_valid_table_div(const struct clk_div_table *table,
- unsigned int div)
+bool clk_divider_is_valid_table_div(const struct clk_div_table *table,
+ unsigned int div)
{
const struct clk_div_table *clkt;
@@ -100,18 +100,18 @@ static bool _is_valid_table_div(const struct
clk_div_table *table,
return false;
}
-static bool _is_valid_div(const struct clk_div_table *table, unsigned int div,
- unsigned long flags)
+bool clk_divider_is_valid_div(const struct clk_div_table *table,
+ unsigned int div, unsigned long flags)
{
if (flags & CLK_DIVIDER_POWER_OF_TWO)
return is_power_of_2(div);
if (table)
- return _is_valid_table_div(table, div);
+ return clk_divider_is_valid_table_div(table, div);
return true;
}
-static unsigned int _get_table_val(const struct clk_div_table *table,
- unsigned int div)
+unsigned int clk_divider_get_table_val(const struct clk_div_table *table,
+ unsigned int div)
{
const struct clk_div_table *clkt;
@@ -131,7 +131,7 @@ static unsigned int _get_val(const struct clk_div_table
*table,
if (flags & CLK_DIVIDER_MAX_AT_ZERO)
return (div == clk_div_mask(width) + 1) ? 0 : div;
if (table)
- return _get_table_val(table, div);
+ return clk_divider_get_table_val(table, div);
return div - 1;
}
int divider_get_val(unsigned long rate, unsigned long parent_rate,
@@ -142,7 +142,7 @@ int divider_get_val(unsigned long rate, unsigned long
parent_rate,
div = DIV_ROUND_UP_ULL((u64)parent_rate, rate);
- if (!_is_valid_div(table, div, flags))
+ if (!clk_divider_is_valid_div(table, div, flags))
return -EINVAL;
value = _get_val(table, div, flags, width);
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 79dce8f0ad..a94539037a 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -76,6 +76,19 @@ struct clk_mux {
extern const struct clk_ops clk_mux_ops;
u8 clk_mux_get_parent(struct clk *clk);
+/**
+ * clk_mux_index_to_val() - Convert the parent index to the register value
+ *
+ * It returns the value to write in the hardware register to output the
selected
+ * input clock parent.
+ *
+ * @table: array of register values corresponding to the parent index
(optional)
+ * @flags: hardware-specific flags
+ * @index: parent clock index
+ * @return the register value
+ */
+unsigned int clk_mux_index_to_val(u32 *table, unsigned int flags, u8 index);
+
struct clk_gate {
struct clk clk;
void __iomem*reg;
@@ -125,6 +138,50 @@ struct clk_divider {
#define CLK_DIVIDER_READ_ONLY BIT(5)
#define CLK_DIVIDER_MAX_AT_ZEROBIT(6)
extern const struct clk_ops clk_divider_ops;
+
+/**
+ * clk_divider_get_table_div() - convert the register value to the divider
+ *
+ * @table: array of register values corresponding to valid dividers
+ * @val: value to convert
+ * @return the divider
+ */
+unsigned int clk_divider_get_table_div(const struct clk_div_table *table,
+ unsigned int val);
+
+/**
+ * clk_divider_get_table_val() - convert the divider to the register value
+ *
+ * It returns the value to write in the
[PATCH] usb: xhci: Use only 32-bit accesses in nvme_writeq/nvme_readq
There might be hardware configurations where 64-bit data accesses
to NVMe registers are not supported properly. This patch removes
the readq/writeq so always two 32-bit accesses are used to read/write
64-bit NVMe registers, similarly as it is done in Linux kernel.
This patch fixes operation of NVMe devices on RPi4 Broadcom
BCM2711 SoC based board, where the VL805 USB XHCI controller is
connected to the PCIe Root Complex, which is attached to the system
through the SCB bridge.
Even though the architecture is 64-bit the PCIe BAR is 32-bit and likely
the 64-bit wide register accesses initiated by the CPU are not properly
translated to a sequence of 32-bit PCIe accesses.
nvme_readq(), for example, always returns same value in upper and lower
32-bits, e.g. 0x3c033fff3c033fff which lead to NVMe devices to fail
probing.
This fix is analogous to commit 8e2ab05000ab ("usb: xhci: Use only
32-bit accesses in xhci_writeq/xhci_readq").
Cc: Sylwester Nawrocki
Cc: Zhikang Zhang
Cc: Nicolas Saenz Julienne
Cc: Matthias Brugger
Signed-off-by: Stefan Agner
---
drivers/nvme/nvme.h | 8
1 file changed, 8 deletions(-)
diff --git a/drivers/nvme/nvme.h b/drivers/nvme/nvme.h
index 0e8cb221a7..aa4b3bac67 100644
--- a/drivers/nvme/nvme.h
+++ b/drivers/nvme/nvme.h
@@ -535,28 +535,20 @@ struct nvme_completion {
*/
static inline u64 nvme_readq(__le64 volatile *regs)
{
-#if BITS_PER_LONG == 64
- return readq(regs);
-#else
__u32 *ptr = (__u32 *)regs;
u64 val_lo = readl(ptr);
u64 val_hi = readl(ptr + 1);
return val_lo + (val_hi << 32);
-#endif
}
static inline void nvme_writeq(const u64 val, __le64 volatile *regs)
{
-#if BITS_PER_LONG == 64
- writeq(val, regs);
-#else
__u32 *ptr = (__u32 *)regs;
u32 val_lo = lower_32_bits(val);
u32 val_hi = upper_32_bits(val);
writel(val_lo, ptr);
writel(val_hi, ptr + 1);
-#endif
}
struct nvme_bar {
--
2.29.2
Re: [PATCH] drivers: tee: i2c trampoline driver
Hi Jorge,
On Mon, 21 Dec 2020 at 11:15, Jorge Ramirez-Ortiz wrote:
>
> This commit gives the secure world access to the I2C bus so it can
> communicate with I2C slaves (tipically those would be secure elements
> like the NXP SE050).
>
Since this code is ported from linux it might be worth adding a link
to the linux commit or patch.
> Tested on imx8mmevk.
>
> Signed-off-by: Jorge Ramirez-Ortiz
> ---
> drivers/tee/optee/Makefile | 1 +
> drivers/tee/optee/i2c.c | 88
> drivers/tee/optee/optee_msg.h| 22 ++
> drivers/tee/optee/optee_msg_supplicant.h | 5 ++
> drivers/tee/optee/optee_private.h| 12
> drivers/tee/optee/supplicant.c | 3 +
> 6 files changed, 131 insertions(+)
> create mode 100644 drivers/tee/optee/i2c.c
>
> diff --git a/drivers/tee/optee/Makefile b/drivers/tee/optee/Makefile
> index 928d3f8002..068c6e7aa1 100644
> --- a/drivers/tee/optee/Makefile
> +++ b/drivers/tee/optee/Makefile
> @@ -2,4 +2,5 @@
>
> obj-y += core.o
> obj-y += supplicant.o
> +obj-$(CONFIG_DM_I2C) += i2c.o
> obj-$(CONFIG_SUPPORT_EMMC_RPMB) += rpmb.o
> diff --git a/drivers/tee/optee/i2c.c b/drivers/tee/optee/i2c.c
> new file mode 100644
> index 00..2ebbf1ff7c
> --- /dev/null
> +++ b/drivers/tee/optee/i2c.c
> @@ -0,0 +1,88 @@
> +// SPDX-License-Identifier: BSD-2-Clause
> +/*
> + * Copyright (c) 2020 Foundries.io Ltd
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include "optee_msg.h"
> +#include "optee_private.h"
> +
> +static struct {
comments on members, but see below
> + struct udevice *dev;
> + int chip;
> + int bus;
> +} xfer;
How come this is not a local variable? Is it an optimisation? Does it
make any difference in execution time? If so I think it would be
better to drop it as state should be kept in driver rmodel. If you
really want it, then perhaps just keep the dev, since you can use:
dev_seq(dev_get_parent(dev) - to get the bus number the device is on
struct dm_i2c_chip *chip = dev_get_parent_platdata(dev);
then use chip->chip_addr to get the chip address
then store 'dev' in priv data in your dev (I think this is struct
optee_private), the one passed to the function below:
> +
> +void optee_suppl_cmd_i2c_transfer(struct udevice *dev,
> + struct optee_msg_arg *arg)
> +{
> + const uint64_t attr[] = {
> + OPTEE_MSG_ATTR_TYPE_VALUE_INPUT,
> + OPTEE_MSG_ATTR_TYPE_VALUE_INPUT,
> + OPTEE_MSG_ATTR_TYPE_RMEM_INOUT,
> + OPTEE_MSG_ATTR_TYPE_VALUE_OUTPUT,
> + };
> + struct udevice *chip_dev = NULL;
> + struct tee_shm *shm = NULL;
> + uint8_t *buf = NULL;
Shouldn't init vars that don't need to be
> + size_t len = 0;
> + int chip = -1;
> + int bus = -1;
> + int ret = -1;
> +
> + if (arg->num_params != ARRAY_SIZE(attr) ||
> + arg->params[0].attr != attr[0] ||
> + arg->params[1].attr != attr[1] ||
> + arg->params[2].attr != attr[2] ||
> + arg->params[3].attr != attr[3]) {
> + arg->ret = TEE_ERROR_BAD_PARAMETERS;
> + return;
> + }
> +
> + len = arg->params[2].u.tmem.size;
> + shm = (struct tee_shm *)(unsigned long)arg->params[2].u.tmem.shm_ref;
> + buf = shm->addr;
> + if (!buf || !len)
> + goto bad;
> +
> + bus = (int)arg->params[0].u.value.b;
> + chip = (int)arg->params[0].u.value.c;
> +
> + if (!xfer.dev || xfer.chip != chip || xfer.bus != bus) {
> + if (i2c_get_chip_for_busnum(bus, chip, 0, _dev))
> + goto bad;
> +
> + xfer.dev = chip_dev;
> + xfer.chip = chip;
> + xfer.bus = bus;
> + }
> +
> + if (arg->params[1].u.value.a & OPTEE_MSG_RPC_CMD_I2C_FLAGS_TEN_BIT)
> + if (i2c_set_chip_flags(xfer.dev, DM_I2C_CHIP_10BIT))
> + goto bad;
Is this flag defined in the devicetree? If so we could read it in
i2c_chip_ofdata_to_platdata() (which will be i2c_chip_of_to_plat()
when the next merge window opens - see upstream/next).
It just seems odd that optee is controlling this, since presumably
U-Boot knows about it?
> +
> + switch (arg->params[0].u.value.a) {
> + case OPTEE_MSG_RPC_CMD_I2C_TRANSFER_RD:
> + ret = dm_i2c_read(xfer.dev, 0, buf, len);
> + break;
> + case OPTEE_MSG_RPC_CMD_I2C_TRANSFER_WR:
> + ret = dm_i2c_write(xfer.dev, 0, buf, len);
This code should run on sandbox and you can use a suitable i2c
emulator (UCLASS_I2C_EMUL), only three at present) or write a new one.
Then your test can arrange for sandbox to send an RPC (e.g. by calling
a function directly in that driver to tell it to do that next time it
has a chance), and your test can check that the i2c read/write
happened.
> + break;
> +
Pull request for UEFI sub-system for efi-2021-01-rc5 (2)
Dear Tom, unfortunately I found two bugs that can lead to a crash. The following changes since commit ab865a8ee5c1a069f72a171270c02c99ccda7bfa: Merge tag 'u-boot-imx-20201227' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx (2020-12-28 07:44:03 -0500) are available in the Git repository at: https://gitlab.denx.de/u-boot/custodians/u-boot-efi.git tags/efi-2021-01-rc5-2 for you to fetch changes up to be48b0f453a3903e924a4f1790f134b9b36e5fa8: efi_loader: use after free in efi_exit() (2020-12-29 02:09:04 +0100) Gitlab CI found no problems: https://gitlab.denx.de/u-boot/custodians/u-boot-efi/-/pipelines/5698 Pull request for UEFI sub-system for efi-2021-01-rc5 (2) The following errors in the UEFI sub-system are fixed: * use after free in efi_exit() * invalid free when using the boot manager * pressing escape key once not recognized Heinrich Schuchardt (6): efi_loader: missing parentheses after if efi_loader: escape key handling efi_loader: avoid invalid free efi_loader: efi_signal_event() fix comment typos efi_loader: describe struct efi_loaded_image_obj efi_loader: use after free in efi_exit() include/efi_loader.h | 8 +--- lib/efi_loader/efi_bootmgr.c | 2 +- lib/efi_loader/efi_boottime.c | 23 +++ lib/efi_loader/efi_console.c | 12 4 files changed, 33 insertions(+), 12 deletions(-)
Re: [PATCH] drivers: tee: i2c trampoline driver
Hi Jorge, On Tue, 29 Dec 2020 at 01:30, Jorge Ramirez-Ortiz, Foundries wrote: > > On 28/12/20, Simon Glass wrote: > > Hi Jorge, > > > > On Mon, 21 Dec 2020 at 11:15, Jorge Ramirez-Ortiz > > wrote: > > > > > > This commit gives the secure world access to the I2C bus so it can > > > communicate with I2C slaves (tipically those would be secure elements > > > > typically > > ok > > > > > > like the NXP SE050). > > > > > > Tested on imx8mmevk. > > > > We don't seem to have any optee tests in U-Boot at present. I vaguely > > recall they were coming at some point. I think we need: > > > > - a sandbox fake drive for optee, that understands and responds to the > > 6 uclass calls at a basic level > > - an update to get_invoke_func() that provides a sandbox function too > > > > Then we should be able to run optee tests in CI. > > > > It is not a lot of work, but I don't think we should add to optee > > until this is resolved. > > um, ok but shouldnt this infrastructure better rest on a maintainer's > roadmap rather than on an off-the-blue request? I mean, had I known I > could have done it in parallel but now I'll need to find the time to > do this. We always need tests in U-Boot, so if you are not writing a test it would be a good question to ask as to how you can do that. Actually patman sometimes warns about that, but perhaps only in certain situations. Actually I see that there is a test - it is hidden under the generic unit tests so I didn't see it. See dm/test/tee.c I'll make some comments on the patch. > > also notice that Linux's equivalent patchset was merged back in the > summer (ie, this is not untested code). > > https://lkml.org/lkml/2020/8/12/276 I don't see any tests in that patch though...are they somewhere else? Or do you justmean people have been running similar code? If so, that's fair enough but it doesn't really help us much. Lots of people test code manually before submitting patches, at least for their use case, but this is an open-source project. Over time people want to change and expand the code, and it is very hard for them to do that if there are no automated tests. Regards, Simon
[PATCH 3/4] phy: Add Amlogic AXG MIPI D-PHY driver
The Amlogic AXG SoCs embeds a MIPI D-PHY used to communicate with DSI panels. This D-PHY depends on a separate analog PHY. Signed-off-by:Neil Armstrong Signed-off-by: Neil Armstrong --- drivers/phy/Kconfig | 9 + drivers/phy/Makefile | 1 + drivers/phy/meson-axg-mipi-dphy.c | 393 ++ 3 files changed, 403 insertions(+) create mode 100644 drivers/phy/meson-axg-mipi-dphy.c diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index 8d9da17b53..00d77eef08 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -196,6 +196,15 @@ config MESON_G12A_USB_PHY This is the generic phy driver for the Amlogic Meson G12A USB2 and USB3 PHYS. +config MESON_AXG_MIPI_DPHY + bool "Amlogic Meson AXG MIPI D-PHY" + depends on PHY && ARCH_MESON && MESON_AXG + select MIPI_DPHY_HELPERS + imply REGMAP + help + This is the generic phy driver for the Amlogic Meson AXG + MIPI D-PHY. + config MSM8916_USB_PHY bool "Qualcomm MSM8916 USB PHY support" depends on PHY diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile index 9024002822..b2fd2d06f6 100644 --- a/drivers/phy/Makefile +++ b/drivers/phy/Makefile @@ -22,6 +22,7 @@ obj-$(CONFIG_PHY_STM32_USBPHYC) += phy-stm32-usbphyc.o obj-$(CONFIG_MESON_GXBB_USB_PHY) += meson-gxbb-usb2.o obj-$(CONFIG_MESON_GXL_USB_PHY) += meson-gxl-usb2.o obj-$(CONFIG_MESON_G12A_USB_PHY) += meson-g12a-usb2.o meson-g12a-usb3-pcie.o +obj-$(CONFIG_MESON_AXG_MIPI_DPHY) += meson-axg-mipi-dphy.o obj-$(CONFIG_MSM8916_USB_PHY) += msm8916-usbh-phy.o obj-$(CONFIG_OMAP_USB2_PHY) += omap-usb2-phy.o obj-$(CONFIG_KEYSTONE_USB_PHY) += keystone-usb-phy.o diff --git a/drivers/phy/meson-axg-mipi-dphy.c b/drivers/phy/meson-axg-mipi-dphy.c new file mode 100644 index 00..8b2469793d --- /dev/null +++ b/drivers/phy/meson-axg-mipi-dphy.c @@ -0,0 +1,393 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Meson AXG MIPI DPHY driver + * + * Copyright (C) 2018 Amlogic, Inc. All rights reserved + * Copyright (C) 2020 BayLibre, SAS + * Author: Neil Armstrong + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +/* [31] soft reset for the phy. + * 1: reset. 0: dessert the reset. + * [30] clock lane soft reset. + * [29] data byte lane 3 soft reset. + * [28] data byte lane 2 soft reset. + * [27] data byte lane 1 soft reset. + * [26] data byte lane 0 soft reset. + * [25] mipi dsi pll clock selection. + * 1: clock from fixed 850Mhz clock source. 0: from VID2 PLL. + * [12] mipi HSbyteclk enable. + * [11] mipi divider clk selection. + * 1: select the mipi DDRCLKHS from clock divider. + * 0: from PLL clock. + * [10] mipi clock divider control. + * 1: /4. 0: /2. + * [9] mipi divider output enable. + * [8] mipi divider counter enable. + * [7] PLL clock enable. + * [5] LPDT data endian. + * 1 = transfer the high bit first. 0 : transfer the low bit first. + * [4] HS data endian. + * [3] force data byte lane in stop mode. + * [2] force data byte lane 0 in receiver mode. + * [1] write 1 to sync the txclkesc input. the internal logic have to + * use txclkesc to decide Txvalid and Txready. + * [0] enalbe the MIPI DPHY TxDDRClk. + */ +#define MIPI_DSI_PHY_CTRL 0x0 + +/* [31] clk lane tx_hs_en control selection. + * 1: from register. 0: use clk lane state machine. + * [30] register bit for clock lane tx_hs_en. + * [29] clk lane tx_lp_en contrl selection. + * 1: from register. 0: from clk lane state machine. + * [28] register bit for clock lane tx_lp_en. + * [27] chan0 tx_hs_en control selection. + * 1: from register. 0: from chan0 state machine. + * [26] register bit for chan0 tx_hs_en. + * [25] chan0 tx_lp_en control selection. + * 1: from register. 0: from chan0 state machine. + * [24] register bit from chan0 tx_lp_en. + * [23] chan0 rx_lp_en control selection. + * 1: from register. 0: from chan0 state machine. + * [22] register bit from chan0 rx_lp_en. + * [21] chan0 contention detection enable control selection. + * 1: from register. 0: from chan0 state machine. + * [20] register bit from chan0 contention dectection enable. + * [19] chan1 tx_hs_en control selection. + * 1: from register. 0: from chan0 state machine. + * [18] register bit for chan1 tx_hs_en. + * [17] chan1 tx_lp_en control selection. + * 1: from register. 0: from chan0 state machine. + * [16] register bit from chan1 tx_lp_en. + * [15] chan2 tx_hs_en control selection. + * 1: from register. 0: from chan0 state machine. + * [14] register bit for chan2 tx_hs_en. + * [13] chan2 tx_lp_en control selection. + * 1: from register. 0: from chan0 state
[PATCH 4/4] phy: Add Amlogic AXG MIPI PCIe Analog PHY driver
The Amlogic AXG MIPI + PCIe Analog PHY provides function for both PCIe and
MIPI DSI at the same time, and provides the Analog part of MIPI DSI transmission
and Analog part of the PCIe lines.
Signed-off-by: Neil Armstrong
---
drivers/phy/Kconfig | 9 +
drivers/phy/Makefile | 1 +
drivers/phy/meson-axg-mipi-pcie-analog.c | 233 +++
3 files changed, 243 insertions(+)
create mode 100644 drivers/phy/meson-axg-mipi-pcie-analog.c
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 00d77eef08..e64802e8f3 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -205,6 +205,15 @@ config MESON_AXG_MIPI_DPHY
This is the generic phy driver for the Amlogic Meson AXG
MIPI D-PHY.
+config MESON_AXG_MIPI_PCIE_ANALOG_PHY
+ bool "Amlogic Meson AXG MIPI PCIe Analog PHY"
+ depends on PHY && ARCH_MESON && MESON_AXG
+ select MIPI_DPHY_HELPERS
+ imply REGMAP
+ help
+ This is the generic phy driver for the Amlogic Meson AXG
+ MIPI PCIe Analog PHY.
+
config MSM8916_USB_PHY
bool "Qualcomm MSM8916 USB PHY support"
depends on PHY
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index b2fd2d06f6..8daf9f6089 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -23,6 +23,7 @@ obj-$(CONFIG_MESON_GXBB_USB_PHY) += meson-gxbb-usb2.o
obj-$(CONFIG_MESON_GXL_USB_PHY) += meson-gxl-usb2.o
obj-$(CONFIG_MESON_G12A_USB_PHY) += meson-g12a-usb2.o meson-g12a-usb3-pcie.o
obj-$(CONFIG_MESON_AXG_MIPI_DPHY) += meson-axg-mipi-dphy.o
+obj-$(CONFIG_MESON_AXG_MIPI_PCIE_ANALOG_PHY) += meson-axg-mipi-pcie-analog.o
obj-$(CONFIG_MSM8916_USB_PHY) += msm8916-usbh-phy.o
obj-$(CONFIG_OMAP_USB2_PHY) += omap-usb2-phy.o
obj-$(CONFIG_KEYSTONE_USB_PHY) += keystone-usb-phy.o
diff --git a/drivers/phy/meson-axg-mipi-pcie-analog.c
b/drivers/phy/meson-axg-mipi-pcie-analog.c
new file mode 100644
index 00..276e6004e5
--- /dev/null
+++ b/drivers/phy/meson-axg-mipi-pcie-analog.c
@@ -0,0 +1,233 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Amlogic AXG MIPI + PCIE analog PHY driver
+ *
+ * Copyright (C) 2019 Remi Pommarel
+ * Copyright (C) 2020 BayLibre, SAS
+ * Author: Neil Armstrong
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+
+#define HHI_MIPI_CNTL0 0x00
+#defineHHI_MIPI_CNTL0_COMMON_BLOCK GENMASK(31, 28)
+#defineHHI_MIPI_CNTL0_ENABLE BIT(29)
+#defineHHI_MIPI_CNTL0_BANDGAP BIT(26)
+#defineHHI_MIPI_CNTL0_DIF_REF_CTL1 GENMASK(25, 16)
+#defineHHI_MIPI_CNTL0_DIF_REF_CTL0 GENMASK(15, 0)
+
+#define HHI_MIPI_CNTL1 0x04
+#defineHHI_MIPI_CNTL1_CH0_CML_PDR_EN BIT(12)
+#defineHHI_MIPI_CNTL1_LP_ABILITY GENMASK(5, 4)
+#defineHHI_MIPI_CNTL1_LP_RESISTER BIT(3)
+#defineHHI_MIPI_CNTL1_INPUT_SETTINGBIT(2)
+#defineHHI_MIPI_CNTL1_INPUT_SELBIT(1)
+#defineHHI_MIPI_CNTL1_PRBS7_EN BIT(0)
+
+#define HHI_MIPI_CNTL2 0x08
+#defineHHI_MIPI_CNTL2_CH_PUGENMASK(31, 25)
+#defineHHI_MIPI_CNTL2_CH_CTL GENMASK(24, 19)
+#defineHHI_MIPI_CNTL2_CH0_DIGDR_EN BIT(18)
+#defineHHI_MIPI_CNTL2_CH_DIGDR_EN BIT(17)
+#defineHHI_MIPI_CNTL2_LPULPS_ENBIT(16)
+#defineHHI_MIPI_CNTL2_CH_ENGENMASK(15, 11)
+#defineHHI_MIPI_CNTL2_CH0_LP_CTL GENMASK(10, 1)
+
+#define DSI_LANE_0 (1 << 4)
+#define DSI_LANE_1 (1 << 3)
+#define DSI_LANE_CLK(1 << 2)
+#define DSI_LANE_2 (1 << 1)
+#define DSI_LANE_3 (1 << 0)
+#define DSI_LANE_MASK (0x1F)
+
+struct phy_meson_axg_mipi_pcie_analog_priv {
+ struct regmap *regmap;
+ struct phy_configure_opts_mipi_dphy config;
+ bool dsi_configured;
+ bool dsi_enabled;
+ bool powered;
+};
+
+static void phy_bandgap_enable(struct phy_meson_axg_mipi_pcie_analog_priv
*priv)
+{
+ regmap_update_bits(priv->regmap, HHI_MIPI_CNTL0,
+ HHI_MIPI_CNTL0_BANDGAP, HHI_MIPI_CNTL0_BANDGAP);
+
+ regmap_update_bits(priv->regmap, HHI_MIPI_CNTL0,
+ HHI_MIPI_CNTL0_ENABLE, HHI_MIPI_CNTL0_ENABLE);
+}
+
+static void phy_bandgap_disable(struct phy_meson_axg_mipi_pcie_analog_priv
*priv)
+{
+ regmap_update_bits(priv->regmap, HHI_MIPI_CNTL0,
+ HHI_MIPI_CNTL0_BANDGAP, 0);
+ regmap_update_bits(priv->regmap, HHI_MIPI_CNTL0,
+ HHI_MIPI_CNTL0_ENABLE, 0);
+}
+
+static void phy_dsi_analog_enable(struct phy_meson_axg_mipi_pcie_analog_priv
*priv)
+{
+ u32 reg;
+
+
[PATCH 2/4] generic-phy: add configure op
Add the PHY configure op callback to the generic PHY uclass to permit
configuring the PHY.
It's useful for MIPI DSI PHYs to setup the link timings.
Signed-off-by:Neil Armstrong
Signed-off-by: Neil Armstrong
---
drivers/phy/phy-uclass.c | 11 +++
include/generic-phy.h| 23 +++
2 files changed, 34 insertions(+)
diff --git a/drivers/phy/phy-uclass.c b/drivers/phy/phy-uclass.c
index ef03e3a502..43ffbcee0f 100644
--- a/drivers/phy/phy-uclass.c
+++ b/drivers/phy/phy-uclass.c
@@ -204,6 +204,17 @@ int generic_phy_power_off(struct phy *phy)
return ret;
}
+int generic_phy_configure(struct phy *phy, void *params)
+{
+ struct phy_ops const *ops;
+
+ if (!generic_phy_valid(phy))
+ return 0;
+ ops = phy_dev_ops(phy->dev);
+
+ return ops->configure ? ops->configure(phy, params) : 0;
+}
+
int generic_phy_get_bulk(struct udevice *dev, struct phy_bulk *bulk)
{
int i, ret, count;
diff --git a/include/generic-phy.h b/include/generic-phy.h
index 5ab34cda03..a17d900e4b 100644
--- a/include/generic-phy.h
+++ b/include/generic-phy.h
@@ -122,6 +122,20 @@ struct phy_ops {
* @return 0 if OK, or a negative error code
*/
int (*power_off)(struct phy *phy);
+
+ /**
+ * configure - configure a PHY device
+ *
+ * @phy: PHY port to be configured
+ * @params: PHY Parameters, underlying data is specific to the PHY
function
+ *
+ * During runtime, the PHY may need to be configured for it's main
function.
+ * This function configures the PHY for it's main function following
+ * power_on/off() after beeing initialized.
+ *
+ * @return 0 if OK, or a negative error code
+ */
+ int (*configure)(struct phy *phy, void *params);
};
/**
@@ -183,6 +197,15 @@ int generic_phy_power_on(struct phy *phy);
*/
int generic_phy_power_off(struct phy *phy);
+/**
+ * generic_phy_configure() - configure a PHY device
+ *
+ * @phy: PHY port to be configured
+ * @params:PHY Parameters, underlying data is specific to the PHY function
+ * @return 0 if OK, or a negative error code
+ */
+int generic_phy_configure(struct phy *phy, void *params);
+
/**
* generic_phy_get_by_index() - Get a PHY device by integer index.
--
2.25.1
[PATCH 1/4] phy: dphy: Add configuration helpers
The MIPI D-PHY spec defines default values and boundaries for most of the
parameters it defines. Introduce helpers to help drivers get meaningful
values based on their current parameters, and validate the boundaries of
these parameters if needed.
These helpers and header are taken from Linux commit 9123e3a74ec7 ("Linux
5.9-rc1").
Signed-off-by: Neil Armstrong
---
drivers/phy/Kconfig | 5 +
drivers/phy/Makefile | 1 +
drivers/phy/phy-core-mipi-dphy.c | 161 ++
include/phy-mipi-dphy.h | 284 +++
4 files changed, 451 insertions(+)
create mode 100644 drivers/phy/phy-core-mipi-dphy.c
create mode 100644 include/phy-mipi-dphy.h
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index d12a6b02ad..8d9da17b53 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -59,6 +59,11 @@ config SPL_NOP_PHY
This is useful when a driver uses the PHY framework but no real PHY
hardware exists.
+config MIPI_DPHY_HELPERS
+ bool "MIPI D-PHY support helpers"
+ help
+ Provides a number of helpers a core functions for MIPI D-PHY drivers.
+
config BCM6318_USBH_PHY
bool "BCM6318 USBH PHY support"
depends on PHY && ARCH_BMIPS
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index 45a7fe5b56..9024002822 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -5,6 +5,7 @@
obj-$(CONFIG_$(SPL_)PHY) += phy-uclass.o
obj-$(CONFIG_$(SPL_)NOP_PHY) += nop-phy.o
+obj-$(CONFIG_MIPI_DPHY_HELPERS) += phy-core-mipi-dphy.o
obj-$(CONFIG_BCM6318_USBH_PHY) += bcm6318-usbh-phy.o
obj-$(CONFIG_BCM6348_USBH_PHY) += bcm6348-usbh-phy.o
obj-$(CONFIG_BCM6358_USBH_PHY) += bcm6358-usbh-phy.o
diff --git a/drivers/phy/phy-core-mipi-dphy.c b/drivers/phy/phy-core-mipi-dphy.c
new file mode 100644
index 00..ba5f648612
--- /dev/null
+++ b/drivers/phy/phy-core-mipi-dphy.c
@@ -0,0 +1,161 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2013 NVIDIA Corporation
+ * Copyright (C) 2018 Cadence Design Systems Inc.
+ */
+
+#include
+#include
+
+#include
+
+#define PSEC_PER_SEC 1LL
+
+/*
+ * Minimum D-PHY timings based on MIPI D-PHY specification. Derived
+ * from the valid ranges specified in Section 6.9, Table 14, Page 41
+ * of the D-PHY specification (v2.1).
+ */
+int phy_mipi_dphy_get_default_config(unsigned long pixel_clock,
+unsigned int bpp,
+unsigned int lanes,
+struct phy_configure_opts_mipi_dphy *cfg)
+{
+ unsigned long long hs_clk_rate;
+ unsigned long long ui;
+
+ if (!cfg)
+ return -EINVAL;
+
+ hs_clk_rate = pixel_clock * bpp;
+ do_div(hs_clk_rate, lanes);
+
+ ui = ALIGN(PSEC_PER_SEC, hs_clk_rate);
+ do_div(ui, hs_clk_rate);
+
+ cfg->clk_miss = 0;
+ cfg->clk_post = 6 + 52 * ui;
+ cfg->clk_pre = 8000;
+ cfg->clk_prepare = 38000;
+ cfg->clk_settle = 95000;
+ cfg->clk_term_en = 0;
+ cfg->clk_trail = 6;
+ cfg->clk_zero = 262000;
+ cfg->d_term_en = 0;
+ cfg->eot = 0;
+ cfg->hs_exit = 10;
+ cfg->hs_prepare = 4 + 4 * ui;
+ cfg->hs_zero = 105000 + 6 * ui;
+ cfg->hs_settle = 85000 + 6 * ui;
+ cfg->hs_skip = 4;
+
+ /*
+* The MIPI D-PHY specification (Section 6.9, v1.2, Table 14, Page 40)
+* contains this formula as:
+*
+* T_HS-TRAIL = max(n * 8 * ui, 60 + n * 4 * ui)
+*
+* where n = 1 for forward-direction HS mode and n = 4 for reverse-
+* direction HS mode. There's only one setting and this function does
+* not parameterize on anything other that ui, so this code will
+* assumes that reverse-direction HS mode is supported and uses n = 4.
+*/
+ cfg->hs_trail = max(4 * 8 * ui, 6 + 4 * 4 * ui);
+
+ cfg->init = 100;
+ cfg->lpx = 6;
+ cfg->ta_get = 5 * cfg->lpx;
+ cfg->ta_go = 4 * cfg->lpx;
+ cfg->ta_sure = 2 * cfg->lpx;
+ cfg->wakeup = 1000;
+
+ cfg->hs_clk_rate = hs_clk_rate;
+ cfg->lanes = lanes;
+
+ return 0;
+}
+
+/*
+ * Validate D-PHY configuration according to MIPI D-PHY specification
+ * (v1.2, Section Section 6.9 "Global Operation Timing Parameters").
+ */
+int phy_mipi_dphy_config_validate(struct phy_configure_opts_mipi_dphy *cfg)
+{
+ unsigned long long ui;
+
+ if (!cfg)
+ return -EINVAL;
+
+ ui = ALIGN(PSEC_PER_SEC, cfg->hs_clk_rate);
+ do_div(ui, cfg->hs_clk_rate);
+
+ if (cfg->clk_miss > 6)
+ return -EINVAL;
+
+ if (cfg->clk_post < (6 + 52 * ui))
+ return -EINVAL;
+
+ if (cfg->clk_pre < 8000)
+ return -EINVAL;
+
+ if (cfg->clk_prepare < 38000 || cfg->clk_prepare > 95000)
+ return -EINVAL;
+
+
[PATCH 0/4] phy: add support for Amlogic Meson AXG MIPI-DSI PHY function
The Amlogic AXg SoCs embeds a MIPI D-PHY to communicate with DSI panels, this adds the bindings. This D-PHY depends on a separate analog PHY. The Amlogic AXG MIPI + PCIe Analog PHY provides function for both PCIe and MIPI DSI at the same time. In order to configure the DSI PHY timings, a new "configure" PHY op is added to permit dynamic (re)configuration of the PHY function. Finally, the Linux MIPI D-PHY configuration helpers are imported to provide a standard set of default D-PHY timings, timings struct and correct calculations. Neil Armstrong (4): phy: dphy: Add configuration helpers generic-phy: add configure op phy: Add Amlogic AXG MIPI D-PHY driver phy: Add Amlogic AXG MIPI PCIe Analog PHY driver drivers/phy/Kconfig | 23 ++ drivers/phy/Makefile | 3 + drivers/phy/meson-axg-mipi-dphy.c| 393 +++ drivers/phy/meson-axg-mipi-pcie-analog.c | 233 ++ drivers/phy/phy-core-mipi-dphy.c | 161 ++ drivers/phy/phy-uclass.c | 11 + include/generic-phy.h| 23 ++ include/phy-mipi-dphy.h | 284 8 files changed, 1131 insertions(+) create mode 100644 drivers/phy/meson-axg-mipi-dphy.c create mode 100644 drivers/phy/meson-axg-mipi-pcie-analog.c create mode 100644 drivers/phy/phy-core-mipi-dphy.c create mode 100644 include/phy-mipi-dphy.h -- 2.25.1
Re: u-boot: rk3308 added support rock pi s
Hi Mara Can you please send it inline and provide proper SoB and description in the patch? Michael On Tue, Dec 29, 2020 at 1:32 PM wrote: > > Hi, > I added support for rock pi s. > Patch adds dts and sonfile for this board. > > board https://wiki.radxa.com/RockpiS > -- Michael Nazzareno Trimarchi Amarula Solutions BV COO Co-Founder Cruquiuskade 47 Amsterdam 1018 AM NL T. +31(0)851119172 M. +39(0)3479132170 [`as] https://www.amarulasolutions.com
u-boot: rk3308 added support rock pi s
Hi,
I added support for rock pi s.
Patch adds dts and sonfile for this board.
board https://wiki.radxa.com/RockpiS
--- a/arch/arm/dts/Makefile 2020-12-25 15:14:09.980329455 +0200
+++ b/arch/arm/dts/Makefile 2020-12-25 15:14:47.952271432 +0200
@@ -106,7 +106,8 @@
dtb-$(CONFIG_ROCKCHIP_RK3308) += \
rk3308-evb.dtb \
- rk3308-roc-cc.dtb
+ rk3308-roc-cc.dtb \
+ rk3308-rock-pi-s.dtb
dtb-$(CONFIG_ROCKCHIP_RK3328) += \
rk3328-evb.dtb \
--- /dev/null 2020-12-23 11:47:50.04430 +0200
+++ b/arch/arm/dts/rk3308-rock-pi-s-u-boot.dtsi 2020-12-25 15:00:18.561552517
+0200
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2018-2019 Rockchip Electronics Co., Ltd
+ */
+#include "rk3308-u-boot.dtsi"
+
+/ {
+ chosen {
+ u-boot,spl-boot-order = "same-as-spl", ,
+ };
+};
+
+ {
+ u-boot,dm-pre-reloc;
+ clock-frequency = <2400>;
+ status = "okay";
+};
--- /dev/null 2020-12-23 11:47:50.04430 +0200
+++ b/arch/arm/dts/rk3308-rock-pi-s.dts 2020-12-25 15:53:15.775897762 +0200
@@ -0,0 +1,215 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Akash Gajjar
+ * Copyright (c) 2019 Jagan Teki
+ */
+
+/dts-v1/;
+#include "rk3308.dtsi"
+
+/ {
+ model = "Radxa ROCK Pi S";
+ compatible = "radxa,rockpis", "rockchip,rk3308";
+
+ chosen {
+ stdout-path = "serial2:150n8";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <_led_gio>, <_led_gpio>;
+
+ green-led {
+ label = "rockpis:green:power";
+ gpios = < RK_PA6 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "default-on";
+ default-state = "on";
+ };
+
+ blue-led {
+ label = "rockpis:blue:user";
+ gpios = < RK_PA5 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ linux,default-trigger = "heartbeat";
+ };
+ };
+
+ vcc5v0_sys: vcc5v0-sys {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <500>;
+ regulator-max-microvolt = <500>;
+ };
+
+ vdd_core: vdd-core {
+ compatible = "pwm-regulator";
+ pwms = < 0 5000 1>;
+ regulator-name = "vdd_core";
+ regulator-min-microvolt = <827000>;
+ regulator-max-microvolt = <134>;
+ regulator-init-microvolt = <1015000>;
+ regulator-settling-time-up-us = <250>;
+ regulator-always-on;
+ regulator-boot-on;
+ pwm-supply = <_sys>;
+ };
+
+ vdd_log: vdd-log {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_log";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <105>;
+ regulator-max-microvolt = <105>;
+ vin-supply = <_sys>;
+ };
+
+ vcc_ddr: vcc-ddr {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_ddr";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <150>;
+ regulator-max-microvolt = <150>;
+ vin-supply = <_sys>;
+ };
+
+ vcc_1v8: vcc-1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_1v8";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <180>;
+ regulator-max-microvolt = <180>;
+ vin-supply = <_io>;
+ };
+
+ vcc_io: vcc-io {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_io";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ vin-supply = <_sys>;
+ };
+
+ vcc_phy: vcc-phy-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_phy";
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vcc5v0_otg: vcc5v0-otg {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_otg";
+ regulator-always-on;
+ gpio = < RK_PC5 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ pinctrl-names = "default";
+ pinctrl-0 = <_vbus_drv>;
+ vin-supply = <_sys>;
+ };
+};
+
+ {
+ cpu-supply =
Re: [PATCH 05/13] imx: imx8mn_evk: correct stack/malloc adress
On Mon, Dec 28, 2020 at 7:28 AM Peng Fan (OSS) wrote:
>
> From: Peng Fan
>
> Move SP to end of OCRAM space. Drop MALLOC_F to make it alloc from
> stack space.
>
> Signed-off-by: Peng Fan
> ---
> drivers/power/power_i2c.c| 8
> include/configs/imx8mn_evk.h | 9 +++--
> 2 files changed, 7 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/power/power_i2c.c b/drivers/power/power_i2c.c
> index 5a0455e119..b67ac2f027 100644
> --- a/drivers/power/power_i2c.c
> +++ b/drivers/power/power_i2c.c
> @@ -23,7 +23,7 @@ int pmic_reg_write(struct pmic *p, u32 reg, u32 val)
>
> if (check_reg(p, reg))
> return -EINVAL;
> -#if defined(CONFIG_DM_I2C)
> +#if CONFIG_IS_ENABLED(DM_I2C)
> struct udevice *dev;
> int ret;
>
> @@ -67,7 +67,7 @@ int pmic_reg_write(struct pmic *p, u32 reg, u32 val)
> return -EINVAL;
> }
>
> -#if defined(CONFIG_DM_I2C)
> +#if CONFIG_IS_ENABLED(DM_I2C)
> return dm_i2c_write(dev, reg, buf, pmic_i2c_tx_num);
> #else
> return i2c_write(pmic_i2c_addr, reg, 1, buf, pmic_i2c_tx_num);
> @@ -83,7 +83,7 @@ int pmic_reg_read(struct pmic *p, u32 reg, u32 *val)
> if (check_reg(p, reg))
> return -EINVAL;
>
> -#if defined(CONFIG_DM_I2C)
> +#if CONFIG_IS_ENABLED(DM_I2C)
> struct udevice *dev;
>
> ret = i2c_get_chip_for_busnum(p->bus, pmic_i2c_addr,
> @@ -131,7 +131,7 @@ int pmic_reg_read(struct pmic *p, u32 reg, u32 *val)
> int pmic_probe(struct pmic *p)
> {
> debug("Bus: %d PMIC:%s probed!\n", p->bus, p->name);
> -#if defined(CONFIG_DM_I2C)
> +#if CONFIG_IS_ENABLED(DM_I2C)
> struct udevice *dev;
> int ret;
>
> diff --git a/include/configs/imx8mn_evk.h b/include/configs/imx8mn_evk.h
> index a6333085fe..61db244e98 100644
> --- a/include/configs/imx8mn_evk.h
> +++ b/include/configs/imx8mn_evk.h
> @@ -20,17 +20,14 @@
> (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
>
> #ifdef CONFIG_SPL_BUILD
> -#define CONFIG_SPL_STACK 0x95fff0
> -#define CONFIG_SPL_BSS_START_ADDR 0x0095
> -#define CONFIG_SPL_BSS_MAX_SIZESZ_8K /* 8 KB */
> +#define CONFIG_SPL_STACK 0x98
> +#define CONFIG_SPL_BSS_START_ADDR 0x95
> +#define CONFIG_SPL_BSS_MAX_SIZESZ_4K /* 8 KB */
If ATF sits at 96 and CONFIG_SPL_BSS_START_ADDR starts at
0x95, 8K should fit with extra space. I think it should be able
to go even larger.
I took your patch and applied it to the Beacon 8mn kit and, I was able
to set the max size to SZ_64K with CONFIG_SPL_BSS_START_ADDR set to
0x95
The reference manual states that OCRAM starts at 91. What is
located in the space between 91 and 95?
> #define CONFIG_SYS_SPL_MALLOC_START0x4220
> #define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K /* 512 KB */
> #define CONFIG_SYS_ICACHE_OFF
> #define CONFIG_SYS_DCACHE_OFF
>
> -/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
> -#define CONFIG_MALLOC_F_ADDR 0x0094
> -
> /* For RAW image gives a error info not panic */
> #define CONFIG_SPL_ABORT_ON_RAW_IMAGE
>
> --
> 2.28.0
>
[PATCH 1/2] video: eliminate unused drivers/video/mb862xx.c
The mb862xx driver does not conform to the driver model and is unused.
Eliminate it.
Signed-off-by: Heinrich Schuchardt
---
drivers/video/Makefile | 1 -
drivers/video/mb862xx.c | 486 ---
scripts/config_whitelist.txt | 2 -
3 files changed, 489 deletions(-)
delete mode 100644 drivers/video/mb862xx.c
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index 67a492a2d6..32113a20ab 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -56,7 +56,6 @@ obj-$(CONFIG_VIDEO_LCD_HITACHI_TX18D42VM) +=
hitachi_tx18d42vm_lcd.o
obj-$(CONFIG_VIDEO_LCD_ORISETECH_OTM8009A) += orisetech_otm8009a.o
obj-$(CONFIG_VIDEO_LCD_RAYDIUM_RM68200) += raydium-rm68200.o
obj-$(CONFIG_VIDEO_LCD_SSD2828) += ssd2828.o
-obj-$(CONFIG_VIDEO_MB862xx) += mb862xx.o videomodes.o
obj-${CONFIG_VIDEO_MESON} += meson/
obj-${CONFIG_VIDEO_MIPI_DSI} += mipi_dsi.o
obj-$(CONFIG_VIDEO_MVEBU) += mvebu_lcd.o
diff --git a/drivers/video/mb862xx.c b/drivers/video/mb862xx.c
deleted file mode 100644
index 04e435f913..00
--- a/drivers/video/mb862xx.c
+++ /dev/null
@@ -1,486 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2007
- * DENX Software Engineering, Anatolij Gustschin, ag...@denx.de
- */
-
-/*
- * mb862xx.c - Graphic interface for Fujitsu CoralP/Lime
- * PCI and video mode code was derived from smiLynxEM driver.
- */
-
-#include
-#include
-
-#include
-#include
-#include
-#include
-#include "videomodes.h"
-#include
-
-#if defined(CONFIG_POST)
-#include
-#endif
-
-/*
- * Graphic Device
- */
-GraphicDevice mb862xx;
-
-/*
- * 32MB external RAM - 256K Chip MMIO = 0x1FC ;
- */
-#define VIDEO_MEM_SIZE 0x01FC
-
-#if defined(CONFIG_PCI)
-#if defined(CONFIG_VIDEO_CORALP)
-
-static struct pci_device_id supported[] = {
- { PCI_VENDOR_ID_FUJITSU, PCI_DEVICE_ID_CORAL_P },
- { PCI_VENDOR_ID_FUJITSU, PCI_DEVICE_ID_CORAL_PA },
- { }
-};
-
-/* Internal clock frequency divider table, index is mode number */
-unsigned int fr_div[] = { 0x0f00, 0x0900, 0x0500 };
-#endif
-#endif
-
-#if defined(CONFIG_VIDEO_CORALP)
-#definerd_io in32r
-#definewr_io out32r
-#else
-#definerd_io(addr) in_be32((volatile unsigned *)(addr))
-#definewr_io(addr, val)out_be32((volatile unsigned *)(addr),
(val))
-#endif
-
-#define HOST_RD_REG(off) rd_io((dev->frameAdrs + GC_HOST_BASE + (off)))
-#define HOST_WR_REG(off, val) wr_io((dev->frameAdrs + GC_HOST_BASE + (off)), \
- (val))
-#define DISP_RD_REG(off) rd_io((dev->frameAdrs + GC_DISP_BASE + (off)))
-#define DISP_WR_REG(off, val) wr_io((dev->frameAdrs + GC_DISP_BASE + (off)), \
- (val))
-#define DE_RD_REG(off) rd_io((dev->dprBase + (off)))
-#define DE_WR_REG(off, val)wr_io((dev->dprBase + (off)), (val))
-
-#if defined(CONFIG_VIDEO_CORALP)
-#define DE_WR_FIFO(val)wr_io((dev->dprBase + (GC_GEO_FIFO)),
(val))
-#else
-#define DE_WR_FIFO(val)wr_io((dev->dprBase + (GC_FIFO)), (val))
-#endif
-
-#define L0PAL_WR_REG(idx, val) wr_io((dev->frameAdrs + \
- (GC_DISP_BASE | GC_L0PAL0) + \
- ((idx) << 2)), (val))
-
-#if defined(CONFIG_VIDEO_MB862xx_ACCEL)
-static void gdc_sw_reset (void)
-{
- GraphicDevice *dev =
-
- HOST_WR_REG (GC_SRST, 0x1);
- udelay(500);
- video_hw_init ();
-}
-
-
-static void de_wait (void)
-{
- GraphicDevice *dev =
- int lc = 0x1;
-
- /*
-* Sync with software writes to framebuffer,
-* try to reset if engine locked
-*/
- while (DE_RD_REG (GC_CTR) & 0x0131)
- if (lc-- < 0) {
- gdc_sw_reset ();
- puts ("gdc reset done after drawing engine lock.\n");
- break;
- }
-}
-
-static void de_wait_slots (int slots)
-{
- GraphicDevice *dev =
- int lc = 0x1;
-
- /* Wait for free fifo slots */
- while (DE_RD_REG (GC_IFCNT) < slots)
- if (lc-- < 0) {
- gdc_sw_reset ();
- puts ("gdc reset done after drawing engine lock.\n");
- break;
- }
-}
-#endif
-
-#if !defined(CONFIG_VIDEO_CORALP)
-static void board_disp_init (void)
-{
- GraphicDevice *dev =
- const gdc_regs *regs = board_get_regs ();
-
- while (regs->index) {
- DISP_WR_REG (regs->index, regs->value);
- regs++;
- }
-}
-#endif
-
-/*
- * Init drawing engine if accel enabled.
- * Also clears visible framebuffer.
- */
-static void de_init (void)
-{
- GraphicDevice *dev =
-#if defined(CONFIG_VIDEO_MB862xx_ACCEL)
- int cf = (dev->gdfBytesPP == 1) ? 0x : 0x8000;
-
- dev->dprBase = dev->frameAdrs + GC_DRAW_BASE;
-
- /*
[PATCH 2/2] video: remove unused include/mb862xx.h
CONFIG_VIDEO_MB862xx cannot be selected by any configuration.
So we can eliminate include/mb862xx.h.
Signed-off-by: Heinrich Schuchardt
---
board/socrates/socrates.c | 12 -
include/mb862xx.h | 101 --
2 files changed, 113 deletions(-)
delete mode 100644 include/mb862xx.h
diff --git a/board/socrates/socrates.c b/board/socrates/socrates.c
index 25bc664328..60b7122673 100644
--- a/board/socrates/socrates.c
+++ b/board/socrates/socrates.c
@@ -25,14 +25,12 @@
#include
#include
#include
-#include
#include
#include "upm_table.h"
DECLARE_GLOBAL_DATA_PTR;
extern flash_info_t flash_info[]; /* FLASH chips info */
-extern GraphicDevice mb862xx;
void local_bus_init (void);
ulong flash_get_size (ulong base, int banknum);
@@ -206,16 +204,6 @@ int ft_board_setup(void *blob, struct bd_info *bd)
val[i++] = gd->bd->bi_flashstart;
val[i++] = gd->bd->bi_flashsize;
-#if defined(CONFIG_VIDEO_MB862xx)
- if (mb862xx.frameAdrs == CONFIG_SYS_LIME_BASE) {
- /* Fixup LIME mapping */
- val[i++] = 2; /* chip select number */
- val[i++] = 0; /* always 0 */
- val[i++] = CONFIG_SYS_LIME_BASE;
- val[i++] = CONFIG_SYS_LIME_SIZE;
- }
-#endif
-
/* Fixup FPGA mapping */
val[i++] = 3; /* chip select number */
val[i++] = 0; /* always 0 */
diff --git a/include/mb862xx.h b/include/mb862xx.h
deleted file mode 100644
index 54c8c757c0..00
--- a/include/mb862xx.h
+++ /dev/null
@@ -1,101 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2007
- * DENX Software Engineering, Anatolij Gustschin, ag...@denx.de
- */
-
-/*
- * mb862xx.h - Graphic interface for Fujitsu CoralP/Lime
- */
-
-#ifndef _MB862XX_H_
-#define _MB862XX_H_
-
-#define PCI_VENDOR_ID_FUJITSU 0x10CF
-#define PCI_DEVICE_ID_CORAL_P 0x2019
-#define PCI_DEVICE_ID_CORAL_PA 0x201E
-
-#define MB862XX_TYPE_LIME 0x1
-
-#define GC_HOST_BASE 0x01fc
-#define GC_DISP_BASE 0x01fd
-#define GC_DRAW_BASE 0x01ff
-
-/* Host interface registers */
-#define GC_SRST0x002c
-#define GC_CCF 0x0038
-#define GC_CID 0x00f0
-#define GC_MMR 0xfffc
-
-/*
- * Display Controller registers
- * _A means the offset is aligned, we use these for boards
- * with 8-/16-bit GDC access not working or buggy.
- */
-#define GC_DCM00x
-#define GC_HTP_A 0x0004
-#define GC_HTP 0x0006
-#define GC_HDB_HDP_A 0x0008
-#define GC_HDP 0x0008
-#define GC_HDB 0x000a
-#define GC_VSW_HSW_HSP_A 0x000c
-#define GC_HSP 0x000c
-#define GC_HSW 0x000e
-#define GC_VSW 0x000f
-#define GC_VTR_A 0x0010
-#define GC_VTR 0x0012
-#define GC_VDP_VSP_A 0x0014
-#define GC_VSP 0x0014
-#define GC_VDP 0x0016
-#define GC_WY_WX 0x0018
-#define GC_WH_WW 0x001c
-#define GC_L0M 0x0020
-#define GC_L0OA0 0x0024
-#define GC_L0DA0 0x0028
-#define GC_L0DY_L0DX 0x002c
-#define GC_L2M 0x0040
-#define GC_L2OA0 0x0044
-#define GC_L2DA0 0x0048
-#define GC_L2OA1 0x004c
-#define GC_L2DA1 0x0050
-#define GC_L2DX0x0054
-#define GC_L2DY0x0056
-#define GC_DCM10x0100
-#define GC_DCM20x0104
-#define GC_DCM30x0108
-#define GC_L0EM0x0110
-#define GC_L0WY_L0WX 0x0114
-#define GC_L0WH_L0WW 0x0118
-#define GC_L2EM0x0130
-#define GC_L2WX0x0134
-#define GC_L2WY0x0136
-#define GC_L2WW0x0138
-#define GC_L2WH0x013a
-#define GC_L0PAL0 0x0400
-
-/* Drawing registers */
-#define GC_CTR 0x0400
-#define GC_IFCNT 0x0408
-#define GC_FBR 0x0440
-#define GC_XRES0x0444
-#define GC_CXMIN 0x0454
-#define GC_CXMAX 0x0458
-#define GC_CYMIN 0x045c
-#define GC_CYMAX 0x0460
-#define GC_FC 0x0480
-#define GC_BC 0x0484
-#define GC_FIFO0x04a0
-#define GC_REV 0x8084
-#define GC_GEO_FIFO0x8400
-
Re: [PATCH] bootmenu: Select CFB_CONSOLE_ANSI if CFB_CONSOLE
On Tuesday 29 December 2020 11:42:56 Heinrich Schuchardt wrote: > On 12/29/20 4:32 AM, Simon Glass wrote: > > Hi Paul, > > > > On Sat, 26 Dec 2020 at 14:04, Pali Rohár wrote: > > > > > > CMD_BOOTMENU uses ANSI terminal. Therefore if U-Boot has enabled > > > CFB_CONSOLE then bootmenu needs also CFB_CONSOLE_ANSI to work. > > > > > > Define this dependency in Kconfig and remove information about this > > > requirement from documentation file. > > > > > > Signed-off-by: Pali Rohár > > > --- > > > cmd/Kconfig| 1 + > > > doc/usage/bootmenu.rst | 5 - > > > 2 files changed, 1 insertion(+), 5 deletions(-) > > > > This driver is past the driver model migration deadline so we > > shouldn't accept patches, except perhaps to migrate or remove it. > > All boards selecting CONFIG_CFB_CONSOLE also select > CONFIG_CFB_CONSOLE_ANSI. So this change probably is not needed for > existing boards. CONFIG_CFB_CONSOLE_ANSI=y is mentioned in > doc/usage/bootmenu.rst. That is because I added this "hint" into Kconfig. So it does not have to be specified in documentation rst file. > Why does CMD_BOOTMENU not select CONFIG_VIDEO_ANSI which is the setting > used by all driver model video drivers? Shouldn't that setting be > mentioned in doc/usage/bootmenu.rst? Because I did not know about this option. It was not mentioned in documentation rst file.
Re: [PATCH v5 00/13] Raspberry Pi 400/Compute Module 4 support
Hi Nicolas, With the xhci patch snippet the pci/xhci crash I was seeing is now gone. I am seeing an error which I need to test a bit more around mmc voltage select which I didn't see previously: Card did not respond to voltage select! : -110 I'm going to do some wider testing. Overall this looks good Series Tested-by: Peter Robinson > This series could be split into at least two or even three parts, but I > kept it as is for now as it contains all the changes needed in order to > have u-boot working on the new Raspberry Pi 400 and Raspberry Pi Compute > Module 4. > > There are core changes, specifically with regard to cpu to bus address > space translations. So far we had relied on hard-coded values but RPi > needs per device translations as it has at least three distinct bus > address spaces with different offsets. So it's a good opportunity to > implement bus translations the right way by parsing DT's dma-ranges. > > Here's a more concrete example of what we're dealing with: > > - On a RPi4, SoC version BCM2711C0 with 8GB of memory > > [0x0 0x2] [0x2 0x4] [0xc000 > 0x1] [0x 0x1] > phys/cpu address PCIe bus address Legacy peripheral > emmc2 address > space space address space > space > > - On a RPi4, SoC version BCM2711C0 with 4GB of memory > > [0x0 0x1] [0x1 0x2] [0xc000 > 0x1] [0x 0x1] > phys/cpu address PCIe bus address Legacy peripheral > emmc2 address > space spaceaddress space >space > > - On a RPi4, SoC version BCM2711B0 with 8GB of memory (bus can only access the > lower 3GB of memory because of a SoC routing bug) > > [0x0 0x2] [0x 0xC000] [0xc000 0x1] > phys/cpu address PCIe bus address Legacy peripheral > space space address space > > --- > > Changes since v4: > - Get rid of #ifs all over the place > > Changes since v3: > - Add commit "video: arm: rpi: Add brcm,bcm2711-hdmi0 compatible", it's >pretty harmless > - Get rid of non-device based phys2bus call in xhci & mmc > - Simon's review changes in tests > - Comment some of the APIs > > Changes since v2: > - Test builds not broken with buildman > - Add tests to all DM changes > - Make code conditional with config option > - Correct OF refcount > - Add config changes > - Address small changes as per reviews > > Changes since v1: > - Fix some issues in 'dm: Introduce xxx_get_dma_range()' > - Fix some typos in commit messages > - Change DTB file name for RPi400 > - Address Matthias' comments > > Nicolas Saenz Julienne (13): > rpi: Add identifier for the new RPi400 > rpi: Add identifier for the new CM4 > pci: pcie-brcmstb: Fix inbound window configurations > dm: Introduce xxx_get_dma_range() > dm: test: Add test case for dev_get_dma_ranges() > dm: Introduce DMA constraints into the core device model > dm: test: Add test case for dev->dma_offset > dm: Introduce dev_phys_to_bus()/dev_bus_to_phys() > dm: test: Add test case for dev_phys_to_bus()/dev_bus_to_phys() > xhci: translate virtual addresses into the bus's address space > mmc: Introduce mmc_phys_to_bus()/mmc_bus_to_phys() > configs: rpi4: Enable DM_DMA across all RPi4 configurations > video: arm: rpi: Add brcm,bcm2711-hdmi0 compatible > > arch/sandbox/dts/test.dts | 21 > board/raspberrypi/rpi/rpi.c| 10 > common/fdt_support.c | 73 > configs/rpi_4_32b_defconfig| 1 + > configs/rpi_4_defconfig| 1 + > configs/rpi_arm64_defconfig| 1 + > configs/sandbox64_defconfig| 1 + > configs/sandbox_defconfig | 1 + > configs/sandbox_flattree_defconfig | 1 + > configs/sandbox_spl_defconfig | 1 + > drivers/core/Kconfig | 10 > drivers/core/device.c | 41 > drivers/core/of_addr.c | 78 ++ > drivers/core/ofnode.c | 9 > drivers/core/read.c| 6 +++ > drivers/mmc/sdhci.c| 12 +++-- > drivers/pci/pcie_brcmstb.c | 12 ++--- > drivers/usb/host/xhci-mem.c| 45 + > drivers/usb/host/xhci-ring.c | 11 +++-- > drivers/usb/host/xhci.c| 4 +- > drivers/video/bcm2835.c| 1 + > include/dm/device.h| 13 + > include/dm/of_addr.h | 17 +++ > include/dm/ofnode.h| 16 ++ > include/dm/read.h | 21 > include/fdt_support.h | 14 ++ > include/mmc.h | 6 +++ > include/phys2bus.h
Re: [PATCH] bootmenu: Select CFB_CONSOLE_ANSI if CFB_CONSOLE
On 12/29/20 4:32 AM, Simon Glass wrote: Hi Paul, On Sat, 26 Dec 2020 at 14:04, Pali Rohár wrote: CMD_BOOTMENU uses ANSI terminal. Therefore if U-Boot has enabled CFB_CONSOLE then bootmenu needs also CFB_CONSOLE_ANSI to work. Define this dependency in Kconfig and remove information about this requirement from documentation file. Signed-off-by: Pali Rohár --- cmd/Kconfig| 1 + doc/usage/bootmenu.rst | 5 - 2 files changed, 1 insertion(+), 5 deletions(-) This driver is past the driver model migration deadline so we shouldn't accept patches, except perhaps to migrate or remove it. All boards selecting CONFIG_CFB_CONSOLE also select CONFIG_CFB_CONSOLE_ANSI. So this change probably is not needed for existing boards. CONFIG_CFB_CONSOLE_ANSI=y is mentioned in doc/usage/bootmenu.rst. Why does CMD_BOOTMENU not select CONFIG_VIDEO_ANSI which is the setting used by all driver model video drivers? Shouldn't that setting be mentioned in doc/usage/bootmenu.rst? Best regards Heinrich
Re: U-Boot statistics update
Dear Adam, In message you wrote: > > The stats on the U-Boot 2020.10 release haven't been updated yet. Is > there any chance you could post them? Sorry this took so long busy times... Here they are: Changes since v2020.07: * Processed 2048 csets from 227 developers * 30 employers found * A total of 166886 lines added, 60806 removed (delta 106080) Developers with the most changesets Simon Glass352 (17.2%) Heinrich Schuchardt153 (7.5%) Marek Vasut112 (5.5%) Patrick Delaunay 103 (5.0%) Tom Rini80 (3.9%) Jagan Teki 74 (3.6%) Michal Simek48 (2.3%) Masahiro Yamada 39 (1.9%) AKASHI Takahiro 36 (1.8%) Stefan Roese34 (1.7%) ... Developers with the most changed lines Suneel Garapati 36718 (17.7%) Jagan Teki34103 (16.4%) Stefan Bosch 17981 (8.7%) Simon Glass 16554 (8.0%) Tero Kristo 12230 (5.9%) Tom Rini 8307 (4.0%) Adam Ford 5638 (2.7%) Oleksandr Andrushchenko 4905 (2.4%) Heinrich Schuchardt 4360 (2.1%) Marek Vasut 4331 (2.1%) ... Developers with the most lines removed Jagan Teki30007 (49.3%) Tom Rini 2437 (4.0%) Andy Shevchenko114 (0.2%) Bhargav Shah 111 (0.2%) Wig Cheng 47 (0.1%) Derald D. Woods 33 (0.1%) Ibai Erkiaga24 (0.0%) Sébastien Szymanski20 (0.0%) Mian Yousaf Kaukab 14 (0.0%) Lad Prabhakar 13 (0.0%) ... Developers with the most signoffs (total 252) Michal Simek30 (11.9%) Peng Fan19 (7.5%) Matthias Brugger16 (6.3%) Tom Rini15 (6.0%) Hou Zhiqiang13 (5.2%) Bin Meng11 (4.4%) Anastasiia Lukianenko 11 (4.4%) Priyanka Jain 10 (4.0%) Oleksandr Andrushchenko 9 (3.6%) Rayagonda Kokatanur 8 (3.2%) ... Developers with the most reviews (total 1268) Bin Meng 276 (21.8%) Simon Glass262 (20.7%) Wolfgang Wallner92 (7.3%) Patrice Chotard 85 (6.7%) Priyanka Jain 80 (6.3%) Stefan Roese63 (5.0%) Kever Yang 54 (4.3%) Tom Rini32 (2.5%) Heiko Schocher 28 (2.2%) Pragnesh Patel 25 (2.0%) ... Developers with the most test credits (total 130) Bin Meng36 (27.7%) Andre Heider13 (10.0%) Stefan Roese 8 (6.2%) Pragnesh Patel 8 (6.2%) Wolfgang Wallner 4 (3.1%) Angelo Dureghello4 (3.1%) Anand Moon 4 (3.1%) Heinrich Schuchardt 3 (2.3%) Soeren Moch 3 (2.3%) Masahiro Yamada 3 (2.3%) ... Developers who gave the most tested-by credits (total 130) Simon Glass 26 (20.0%) Pali Rohár 10 (7.7%) Heinrich Schuchardt 9 (6.9%) Daniel Schwierzeck 8 (6.2%) Bin Meng 7 (5.4%) Pragnesh Patel 6 (4.6%) Jagan Teki 6 (4.6%) Stefan Roese 4 (3.1%) Michael Walle4 (3.1%) Tom Rini 3 (2.3%) ... Developers with the most report credits (total 25) Stefan Bosch 5 (20.0%) Tom Rini 4 (16.0%) Heinrich Schuchardt 2 (8.0%) Scott K Logan2 (8.0%) Pali Rohár 1 (4.0%) Andre Heider 1 (4.0%) Soeren Moch 1 (4.0%) Sean Anderson1 (4.0%) Dmitry N. Kolesnikov 1 (4.0%) Matt Porter 1 (4.0%) ... Developers who gave the most report credits (total 25) Simon Glass 5 (20.0%) Heinrich Schuchardt 4 (16.0%) Fabio Estevam3 (12.0%) Tom Rini 2 (8.0%) Andre Heider 2 (8.0%) Igor Lantsman1 (4.0%) Anatolij Gustschin 1 (4.0%) Neil Armstrong 1 (4.0%) Volodymyr Babchuk1 (4.0%) AKASHI Takahiro 1 (4.0%) ... Top changeset contributors by employer (Unknown) 685 (33.4%) Google, Inc. 352 (17.2%) ST Microelectronics122 (6.0%) NXP116 (5.7%) Texas Instruments 103 (5.0%) DENX Software Engineering 95 (4.6%) Konsulko Group 80 (3.9%) Amarula Solutions 78 (3.8%) Xilinx 72 (3.5%) Linaro 48 (2.3%) ... Top lines changed by employer (Unknown) 60618 (29.2%) Marvell 37156 (17.9%) Amarula Solutions 34151 (16.5%) Texas Instruments 20589 (9.9%) Google, Inc. 16554 (8.0%) Konsulko Group8307 (4.0%) NXP
Re: [PATCH] drivers: tee: i2c trampoline driver
On 28/12/20, Simon Glass wrote: > Hi Jorge, > > On Mon, 21 Dec 2020 at 11:15, Jorge Ramirez-Ortiz wrote: > > > > This commit gives the secure world access to the I2C bus so it can > > communicate with I2C slaves (tipically those would be secure elements > > typically ok > > > like the NXP SE050). > > > > Tested on imx8mmevk. > > We don't seem to have any optee tests in U-Boot at present. I vaguely > recall they were coming at some point. I think we need: > > - a sandbox fake drive for optee, that understands and responds to the > 6 uclass calls at a basic level > - an update to get_invoke_func() that provides a sandbox function too > > Then we should be able to run optee tests in CI. > > It is not a lot of work, but I don't think we should add to optee > until this is resolved. um, ok but shouldnt this infrastructure better rest on a maintainer's roadmap rather than on an off-the-blue request? I mean, had I known I could have done it in parallel but now I'll need to find the time to do this. also notice that Linux's equivalent patchset was merged back in the summer (ie, this is not untested code). https://lkml.org/lkml/2020/8/12/276 > > Regards, > Simon > [.]
Re: [PATCH] board: amlogic: add MMC boot device detection for environment load
On 18/12/2020 15:26, Marek Szyprowski wrote:
> Detect eMMC or SD card boot on Odroid-C4/N2 and Khadas VIM3(l) boards and
> report proper MMC device for the environment loading code. This allows to
> automatically load and store environment variables on the FAT partition
> or RAW offset of the MMC device without the need to use different
> configurations on eMMC and SD card.
>
> To use this feature with environment stored on FAT partition, one has to
> specify an empty device part (i.e. ":1" for the first partition) in
> CONFIG_ENV_FAT_DEVICE_AND_PART to let the code to set the device to the
> value returned by mmc_get_env_dev() function.
>
> Signed-off-by: Marek Szyprowski
> ---
> board/amlogic/odroid-n2/odroid-n2.c | 8
> board/amlogic/vim3/vim3.c | 8
> 2 files changed, 16 insertions(+)
>
> diff --git a/board/amlogic/odroid-n2/odroid-n2.c
> b/board/amlogic/odroid-n2/odroid-n2.c
> index caf7fd6810..12ee5d3abc 100644
> --- a/board/amlogic/odroid-n2/odroid-n2.c
> +++ b/board/amlogic/odroid-n2/odroid-n2.c
> @@ -10,6 +10,7 @@
> #include
> #include
> #include
> +#include
> #include
> #include
>
> @@ -17,6 +18,13 @@
> #define EFUSE_MAC_SIZE 12
> #define MAC_ADDR_LEN 6
>
> +int mmc_get_env_dev(void)
> +{
> + if (meson_get_boot_device() == BOOT_DEVICE_EMMC)
> + return 1;
> + return 0;
> +}
> +
> int misc_init_r(void)
> {
> u8 mac_addr[MAC_ADDR_LEN];
> diff --git a/board/amlogic/vim3/vim3.c b/board/amlogic/vim3/vim3.c
> index 09ef39ff30..f9049e0172 100644
> --- a/board/amlogic/vim3/vim3.c
> +++ b/board/amlogic/vim3/vim3.c
> @@ -10,10 +10,18 @@
> #include
> #include
> #include
> +#include
> #include
> #include
> #include "khadas-mcu.h"
>
> +int mmc_get_env_dev(void)
> +{
> + if (meson_get_boot_device() == BOOT_DEVICE_EMMC)
> + return 2;
> + return 1;
> +}
> +
> /*
> * The VIM3 on-board MCU can mux the PCIe/USB3.0 shared differential
> * lines using a FUSB340TMX USB 3.1 SuperSpeed Data Switch between
>
Thanks,
I would have hoped to have something more generic... but for now it's ok !
Applying to u-boot-amlogic-next
Neil
Re: [PATCH] adc: meson-saradc: use correct printf code
On 27/12/2020 09:46, Heinrich Schuchardt wrote:
> For printing unsigned int we have to use %u not %d.
>
> Signed-off-by: Heinrich Schuchardt
> ---
> drivers/adc/meson-saradc.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/adc/meson-saradc.c b/drivers/adc/meson-saradc.c
> index 13a8f49dc5..406583e474 100644
> --- a/drivers/adc/meson-saradc.c
> +++ b/drivers/adc/meson-saradc.c
> @@ -282,7 +282,7 @@ static int meson_saradc_read_raw_sample(struct
> meson_saradc_priv *priv,
> regmap_read(priv->regmap, MESON_SAR_ADC_FIFO_RD, );
> fifo_chan = FIELD_GET(MESON_SAR_ADC_FIFO_RD_CHAN_ID_MASK, regval);
> if (fifo_chan != channel) {
> - printf("ADC FIFO entry belongs to channel %d instead of %d\n",
> + printf("ADC FIFO entry belongs to channel %u instead of %u\n",
> fifo_chan, channel);
> return -EINVAL;
> }
> --
> 2.29.2
>
Acked-by: Neil Armstrong
