Re: [PATCH RFT v2 0/4] pci: add common Designware PCIe functions and support Amlogic Meson PCIe controller

[Bin Meng]

Hi Neil,

On Tue, Apr 6, 2021 at 8:22 PM Neil Armstrong  wrote:
>
> Hi Bin,
>
> On 25/03/2021 15:49, Neil Armstrong wrote:
> > With the introduction of pcie_dw_rockchip, and need to support the DW PCIe 
> > in the
> > Amlogic AXG & G12 SoCs, most of the DW PCIe helpers would be duplicated.
> >
> > This introduce a "common" DW PCIe helpers file with common code merged from 
> > the
> > dw_ti and dw_rockchip drivers and adapted to fit with the upcoming dw_meson.
> >
> > The following changes will switch the dw_ti and dw_rockchip, and introduce 
> > a new
> > driver to support the Amlogic AXG & G12 SoCs using these new common helpers.
> >
> > The dw_meson has been validated, but the dw_ti and dw_rockchip would need 
> > testing
> > on hardware to validate nothing has been broken.
>
> How should be proceed ? I can't possibly test patches 2 & 3, but Green has 
> tested it
> on Sifive, should patch 1 & 4 be merged then we should wait feedback from the 
> Ti & Rockchip
> owners ?

This series is not assigned to me in patchwork so I cannot decide anything :)

But my opinion was that let's wait for some more time, and if nobody
jumps out let's merge this series.

Regards,
Bin

Re: [PATCH v4 0/7] Add FU740 chip and HiFive Unmatched board support

[Leo Liang]

Hi Green,

There seems to be some compilation failure when running CI test.
CI trest result: 
(https://dev.azure.com/ycliang-tw/u-boot-riscv/_build/results?buildId=24=logs=24a4c78b-f197-51e6-cd79-c14cda102aad=6a1228d0-d58c-5c15-8977-c1c59ea93a2c=280)

Could you please also check and fix those errors, thanks!

Best regards,
Leo

On Fri, Mar 26, 2021 at 11:54:02PM +0800, Green Wan wrote:
> This patch set is to add SiFive fu740 chip and HiFive Unmatched board
> support. Patches are split into several parts:
> 
>   - [PATCH 1/7] dts for fu740
>   - [PATCH 2/7] support for fu740 cpu
>   - [PATCH 3/7- 4/7] support for fu740 clk and ram
>   - [PATCH 5/7] add pcie driver
>   - [PATCH 6/7] add unmatched board
>   - [PATCH 7/7] add fu740 support to macb driver
> 
> Description
> 
>   - For fu740 cpu support, reuse most of fu540 cpu.
>   - For prci driver, add one abstract layer to separate fu540 and
> fu740. Move orignal fu540 code to separate files.
>   - For pcie driver, it depends on gpio, prci, clk and reset drivers
> to do init works.
>   - Align with Linux DT file.
> 
> Tests and patch checks
> 
>   - Able to boot both unmatched and unleashed boards.
>   - PCIe tests
> . M.2 NVMe SSD
> . e1000 compatibale ethernet adapter (ping)
> . pci-to-usb adapter(usb mass storage)
>   - checkpatch is performed. To keep code derived from other boards
> the same, ignore some warnings/errors in [PATCH 7/8].
> 
> Changlogs
>   - V4
> . fixed incorrect file name in ./board/sifive/unmatched/Makefile
> . fixed link in doc/board/sifive/index.rst, passed 'make htmldocs'
>   - V3
> . Rebase to unleashed rename v2 patch
> . Rename
>   doc/board/sifive/unmatched.rst
>   board/sifive/unmatched/unmatched.c
> . Fix tail whitespace
> . Add 'git mv' info to ram driver and merge patch back to one
> . Add comment to macb driver for PLL hardware quirk
> . Add reviewed-by to patch [6/7] 
> . Add 'gpio-poweroff' node for upcoming opensbi integration
>   - V2
> . Rebase to unleashed rename patch
> . remove unnessaary fu540 changes
> . split ram driver patch into 2 to keep 'git mv' info
> . use a shorter name for unmatched support
> . Remove redundant temperature-sensor in DT
> . Remove unnecessary USB EHCI & OHCI from defconfig
> . Revised fu740 doc
> . Fixed year of copyright
> . Add reviewed-by received in v1 patch
> 
> David Abdurachmanov (1):
>   drivers: net: macb: add fu740 support
> 
> Green Wan (6):
>   riscv: dts: add fu740 support
>   riscv: cpu: fu740: Add support for cpu fu740
>   drivers: clk: add fu740 support
>   drivers: ram: sifive: rename fu540_ddr and add fu740 support
>   drivers: pci: add pcie support for fu740
>   board: sifive: add HiFive Unmatched board support
> 
>  arch/riscv/Kconfig|5 +
>  arch/riscv/cpu/fu740/Kconfig  |   37 +
>  arch/riscv/cpu/fu740/Makefile |   12 +
>  arch/riscv/cpu/fu740/cache.c  |   55 +
>  arch/riscv/cpu/fu740/cpu.c|   22 +
>  arch/riscv/cpu/fu740/dram.c   |   38 +
>  arch/riscv/cpu/fu740/spl.c|   23 +
>  arch/riscv/dts/Makefile   |1 +
>  arch/riscv/dts/fu740-c000-u-boot.dtsi |  105 ++
>  arch/riscv/dts/fu740-c000.dtsi|  329 
>  .../dts/fu740-hifive-unmatched-a00-ddr.dtsi   | 1489 +
>  .../dts/hifive-unmatched-a00-u-boot.dtsi  |   40 +
>  arch/riscv/dts/hifive-unmatched-a00.dts   |  259 +++
>  arch/riscv/include/asm/arch-fu740/cache.h |   14 +
>  arch/riscv/include/asm/arch-fu740/clk.h   |   14 +
>  arch/riscv/include/asm/arch-fu740/gpio.h  |   38 +
>  arch/riscv/include/asm/arch-fu740/reset.h |   13 +
>  arch/riscv/include/asm/arch-fu740/spl.h   |   14 +
>  arch/riscv/lib/sifive_clint.c |1 -
>  board/sifive/unmatched/Kconfig|   50 +
>  board/sifive/unmatched/MAINTAINERS|9 +
>  board/sifive/unmatched/Makefile   |9 +
>  board/sifive/unmatched/spl.c  |   85 +
>  board/sifive/unmatched/unmatched.c|   24 +
>  common/spl/Kconfig|4 +-
>  configs/sifive_unmatched_defconfig|   53 +
>  doc/board/sifive/index.rst|1 +
>  doc/board/sifive/unmatched.rst|  536 ++
>  drivers/clk/sifive/Kconfig|8 +-
>  drivers/clk/sifive/Makefile   |4 +-
>  drivers/clk/sifive/fu540-prci.c   |  769 +
>  drivers/clk/sifive/fu540-prci.h   |   22 +
>  drivers/clk/sifive/fu740-prci.c   |  158 ++
>  drivers/clk/sifive/fu740-prci.h   |   22 +
>  drivers/clk/sifive/sifive-prci.c  |  733 
>  drivers/clk/sifive/sifive-prci.h  |  323 
>  drivers/net/macb.c|   13 +-

Re: [PATCH 02/16] timer: imx-gpt: Add timer support for i.MX SoCs family

[Giulio Benetti]

Hi Jesse,

please use plain-text e-mail instead of html,

On 4/8/21 3:06 AM, Jesse T wrote:

> +     if (rate == 2400UL) {
> +             /* Set timer frequency if using 24M clock source */
> +             if (prescaler > GPT_PR_PRESCALER24M_MAX)
> +                     return -EINVAL;
> +

In the datasheet for the imxrt1050 the 24Mhz scaler output goes into the 
normal prescaler.The width of the 24Mhz prescaler is only 4 bits it 
seems to be meant to divide the 24Mhz to something more reasonable for 
the other prescaler.


You're right, I've missed RM Figure 51-2 against 51-1, I was sure that 
Prescaler 24M was directly feeding the Timer Counter. Anyway I was 
trying to follow what they do in Linux kernel:

https://elixir.bootlin.com/linux/latest/source/drivers/clocksource/timer-imx-gpt.c#L314

What they try to do as I understand is to avoid using PLL if 3Mhz is the 
wished rate and the same I'm trying to do here. Then yes, you're right 
that main prescaler can divide again.



I would do something like this...

+     if (rate == 2400UL) {
+             /* Set timer frequency if using 24M clock source */
+             if (prescaler > (GPT_PR_PRESCALER24M_MAX  <<  12) | 
GPT_PR_PRESCALER_MAX)


I can't understand this check ^^^


+                     return -EINVAL;
+
+               /* Set 24M prescaler */
+               writel(( (prescaler >> 12) << 
GPT_PR_PRESCALER24M_SHIFT), >pr);
+               writel(( (prescaler & GPT_PR_PRESCALER_MASK) << 
GPT_PR_PRESCALER_SHIFT), >pr);


This way ^^^ you set the 2 in-series prescalers with the same value if 
it's what you mean.




Ideally we would have the lengths in bits for GPT_PR_PRESCALER_MASK to 
replace the 12, but we can also do...


+     if (rate == 2400UL) {
+             /* Set timer frequency if using 24M clock source */
+             if (prescaler > (GPT_PR_PRESCALER24M_MASK | 
GPT_PR_PRESCALER_MAX))


Still don't understand this ^^^ with the 2 or'ed macros.

That gets expanded like:
```
if (prescaler > (GPT_PR_PRESCALER24M_MASK | ((GPT_PR_PRESCALER24M_MASK 
>> GPT_PR_PRESCALER24M_SHIFT)))

```
and to:
```
if (prescaler > (0xF000 | (0xF000 >> 12)))
```
that results in:
```
if (prescaler > (0xF000 | 0xF))
```

so it doesn't make sense to me, maybe did you mean something different 
or I'm wrong while expanding?



+                     return -EINVAL;
+
+               /* Set 24M prescaler */
+               writel(prescaler , >pr);

Side note while debugging this i added `KCFLAGS=-DDEBUG` and the boot 
would hang with it but without it would boot normally. The cause for the 
hang is this loop will never exit, not this only happens while booting 
u-boot and not during the spl stage.

  /drivers/serial/serial_lpuart.c
@@ -356,7 +356,9 @@ static void _lpuart32_serial_putc(struct 
lpuart_serial_plat *plat,


   while (true) {
   lpuart_read32(plat->flags, >stat, );

   if ((stat & STAT_TDRE))
   break;


Thanks for recalling me this, I still didn't check it, so I'm going 
through this and fix it.



Sorry if im being dumb


You're not being dumb

im new to this stuff and thanks for every one for

walking me through this.


You're welcome :-) and thank you for helping me with this driver and 
reviewing! Reviewing is a very important part of the process of 
upstreaming patches.


Kind regards
--
Giulio Benetti
Benetti Engineering sas



On Wed, Apr 7, 2021 at 3:20 PM Giulio Benetti 
> wrote:


On 4/7/21 9:02 PM, Giulio Benetti wrote:
 > This timer driver is using GPT Timer (General Purpose Timer)
available
 > on almost all i.MX SoCs family. Since this driver is only meant to
 > provide u-boot's timer and counter, and most of the i.MX* SoCs use a
 > 24Mhz crystal, let's only deal with that specific source.

Sorry, it's not true we deal 24Mhz only, also peripheral clock is dealt.
So commit log should be:
```
This timer driver is using GPT Timer (General Purpose Timer) available
on almost all i.MX SoCs family. This driver deals with both 24Mhz
oscillator as well as peripheral clock.
```

Let me know if I need to re-send.

Best regards
-- 
Giulio Benetti

Benetti Engineering sas

 > Signed-off-by: Giulio Benetti
mailto:giulio.bene...@benettiengineering.com>>
 > [Giulio: added the driver's stub and handled peripheral clock
prescaler
 > setting]
 > Signed-off-by: Jesse Taube mailto:mr.bossman...@gmail.com>>
 > [Jesse: added init, setting prescaler for 24Mhz support and enabling
 > timer]
 > ---
 >   drivers/timer/Kconfig         |   7 ++
 >   drivers/timer/Makefile        |   1 +
 >   drivers/timer/imx-gpt-timer.c | 162
++
 >   3 files changed, 170 insertions(+)
 >   create mode 100644 drivers/timer/imx-gpt-timer.c
 >
 > diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig
 > index 

Re: [PATCH 17/17] doc: Update documentation for cros-2021.04 release

[Bin Meng]

Hi Simon,

On Wed, Apr 7, 2021 at 12:33 PM Simon Glass  wrote:
>
> With the new 2021.04 we have a new version of Chromium OS boot, which
> supports sandbox, coral and coral-on-coreboot. Add documentation for

Chrominum OS can run on Sandbox?

> this.
>
> Signed-off-by: Simon Glass 
> ---
>
>  doc/chromium/run_vboot.rst | 15 +++
>  1 file changed, 7 insertions(+), 8 deletions(-)
>

Reviewed-by: Bin Meng 

Regards,
Bin

Re: [PATCH 15/17] x86: Check ROM exists before building vboot

[Bin Meng]

Hi Simon,

On Wed, Apr 7, 2021 at 12:33 PM Simon Glass  wrote:
>
> All the x86 devicetree files are built at once, whichever board is
> actually being built. If coreboot is the target build, CONFIG_ROM_SIZE
> is not defined and samus cannot build Chromium OS verified boot. Add
> this condition to avoid errors about CONFIG_ROM_SIZE being missing.

The commit title should use "x86: chromebook" as the tags, since it's
not x86 generic thing.

>
> Signed-off-by: Simon Glass 
> ---
>
>  arch/x86/dts/chromebook_coral.dts | 2 +-
>  arch/x86/dts/chromebook_samus.dts | 2 +-
>  2 files changed, 2 insertions(+), 2 deletions(-)
>

Otherwise,
Reviewed-by: Bin Meng 

Regards,
Bin

Re: [PATCH 14/17] x86: coreboot: Document the memory map

[Bin Meng]

Hi Simon,

On Wed, Apr 7, 2021 at 12:33 PM Simon Glass  wrote:
>
> Add information about memory usage when U-Boot is started from coreboot.
> This is useful when debugging. Also, since coreboot takes a chunk of
> memory in the middle of SDRAM for use by PCI devices, it can help avoid
> overwriting this with a loaded kernel by accident.
>
> Signed-off-by: Simon Glass 
> ---
>
>  doc/board/coreboot/coreboot.rst | 19 +++
>  1 file changed, 19 insertions(+)
>
> diff --git a/doc/board/coreboot/coreboot.rst b/doc/board/coreboot/coreboot.rst
> index 9c44c025a48..e791b7e39f0 100644
> --- a/doc/board/coreboot/coreboot.rst
> +++ b/doc/board/coreboot/coreboot.rst
> @@ -50,3 +50,22 @@ works by using a 32-bit SPL binary to switch to 64-bit for 
> running U-Boot. It
>  can be useful for running UEFI applications, for example.
>
>  This has only been lightly tested.
> +
> +
> +Memory map
> +--
> +
> +::

Can we use the reST table syntax for the following table?

> +
> +  Top of ROM (and last byte of 32-bit address space)
> +7a9fd000  Typical top of memory available to U-Boot
> +  (use cbsysinfo to see where memory range 'table' starts)
> +1000  Memory reserved by coreboot for mapping PCI devices
> +  (typical size 2151000, includes framebuffer)
> + 192  CONFIG_SYS_CAR_ADDR, fake Cache-as-RAM memory, used during 
> startup
> + 111  CONFIG_SYS_TEXT_BASE (start address of U-Boot code, before 
> reloc)
> +  11  CONFIG_BLOBLIST_ADDR (before being relocated)
> +  10  CONFIG_PRE_CON_BUF_ADDR
> +   f  ACPI tables set up by U-Boot
> +  (typically redirects to 7ab10030 or similar)
> + 500  Location of coreboot sysinfo table, used during startup
> --

Regards,
Bin

Re: [PATCH 13/17] x86: coreboot: Enable the cbsysinfo command

[Bin Meng]

Hi Simon,

On Wed, Apr 7, 2021 at 12:33 PM Simon Glass  wrote:
>
> Enable this by default on coreboot, since it is quite useful there.
>
> Signed-off-by: Simon Glass 
> ---
>
>  arch/x86/cpu/coreboot/Kconfig | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/arch/x86/cpu/coreboot/Kconfig b/arch/x86/cpu/coreboot/Kconfig
> index b97c2779041..11385918d83 100644
> --- a/arch/x86/cpu/coreboot/Kconfig
> +++ b/arch/x86/cpu/coreboot/Kconfig
> @@ -26,5 +26,6 @@ config SYS_COREBOOT
> imply CBMEM_CONSOLE
> imply X86_TSC_READ_BASE
> select BINMAN if X86_64
> +   imply CMD_CBSYSINFO

This is not needed as in cmd/Kconfig, we have:

config CMD_CBSYSINFO
default y if SYS_COREBOOT

Regards,
Bin

Re: [PATCH 12/17] x86: coreboot: Use vendor in the Kconfig

[Bin Meng]

Hi Simon,

On Wed, Apr 7, 2021 at 12:33 PM Simon Glass  wrote:
>
> Use VENDOR_COREBOOT instead of TARGET_COREBOOT so we can have multiple
> coreboot boards, sharing options. Only SYS_CONFIG_NAME needs to be
> defined TARGET_COREBOOT.
>

I am not sure what use case this is? This change makes no difference
when U-Boot is built as a coreboot payload.

> Signed-off-by: Simon Glass 
> ---
>
>  arch/x86/cpu/coreboot/Kconfig   |  2 +-
>  board/coreboot/coreboot/Kconfig | 12 
>  2 files changed, 9 insertions(+), 5 deletions(-)
>

Regards,
Bin

Re: [PATCH 11/17] x86: Add function comments to cb_sysinfo.h

[Bin Meng]

On Wed, Apr 7, 2021 at 12:33 PM Simon Glass  wrote:
>
> Add a function comment for get_coreboot_info() and a declaration for
> cb_get_sysinfo(), since this may be called from elsewhere.
>
> Signed-off-by: Simon Glass 
> ---
>
>  arch/x86/include/asm/cb_sysinfo.h | 16 
>  1 file changed, 16 insertions(+)
>

Reviewed-by: Bin Meng 

Re: [PATCH] atcspi200: Add timeout mechanism in spi_xfer()

[Leo Liang]

On Thu, Apr 01, 2021 at 04:48:51PM +0800, Dylan Dai-Rong Jhong(??) wrote:
> Adding timeout mechanism to avoid spi driver from stucking
> in the while loop in __atcspi200_spi_xfer().
> 
> Signed-off-by: Dylan Jhong 
> ---
>  drivers/spi/atcspi200_spi.c | 10 --
>  1 file changed, 8 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/spi/atcspi200_spi.c b/drivers/spi/atcspi200_spi.c
> index 634cd56561..775b9ffc25 100644
> --- a/drivers/spi/atcspi200_spi.c
> +++ b/drivers/spi/atcspi200_spi.c
> @@ -201,7 +201,7 @@ static int __atcspi200_spi_xfer(struct nds_spi_slave *ns,
>   size_t cmd_len = ns->cmd_len;
>   unsigned long data_len = bitlen / 8;
>   int rf_cnt;
> - int ret = 0;
> + int ret = 0, timeout = 0;
>  
>   max_tran_len = ns->max_transfer_length;
>   switch (flags) {
> @@ -243,11 +243,12 @@ static int __atcspi200_spi_xfer(struct nds_spi_slave 
> *ns,
>   ns->tran_len = tran_len;
>   num_blks = DIV_ROUND_UP(tran_len , CHUNK_SIZE);
>   num_bytes = (tran_len) % CHUNK_SIZE;
> + timeout = SPI_TIMEOUT;
>   if(num_bytes == 0)
>   num_bytes = CHUNK_SIZE;
>   __atcspi200_spi_start(ns);
>  
> - while (num_blks) {
> + while (num_blks && (timeout--)) {
>   event = in_le32(>regs->status);
>   if ((event & TXEPTY) && (data_out)) {
>   __nspi_espi_tx(ns, dout);
> @@ -269,6 +270,11 @@ static int __atcspi200_spi_xfer(struct nds_spi_slave *ns,
>   din = (unsigned char *)din + 
> rx_bytes;
>   }
>   }
> +
> + if (!timeout) {
> + debug("spi_xfer: %s() timeout\n", 
> __func__);
> + break;
> + }
>   }
>  
>   data_len -= tran_len;
> -- 
> 2.17.0
>

Reviewed-by: Leo Yu-Chi Liang 

Re: [PATCH 10/17] x86: coral: Allow booting from coreboot

[Bin Meng]

Hi Simon,

On Wed, Apr 7, 2021 at 12:33 PM Simon Glass  wrote:
>
> Set up coral so that it can boot from coreboot, even though it is a
> bare-metal build. This helps with testing since the same image can be used
> in both cases.
>
> Signed-off-by: Simon Glass 
> ---
>
>  board/google/chromebook_coral/coral.c | 28 +++
>  1 file changed, 28 insertions(+)
>
> diff --git a/board/google/chromebook_coral/coral.c 
> b/board/google/chromebook_coral/coral.c
> index 3f9235c903b..b16252d2a8b 100644
> --- a/board/google/chromebook_coral/coral.c
> +++ b/board/google/chromebook_coral/coral.c
> @@ -10,17 +10,21 @@
>  #include 
>  #include 
>  #include 
> +#include 
>  #include 
>  #include 
>  #include 
>  #include 
>  #include 
> +#include 
>  #include 
>  #include 
>  #include 
>  #include 
>  #include "variant_gpio.h"
>
> +DECLARE_GLOBAL_DATA_PTR;
> +
>  struct cros_gpio_info {
> const char *linux_name;
> enum cros_gpio_t type;
> @@ -28,6 +32,30 @@ struct cros_gpio_info {
> int flags;
>  };
>
> +int misc_init_f(void)
> +{
> +   if (!ll_boot_init()) {
> +   printf("Running as secondary loader");
> +   if (gd->arch.coreboot_table) {
> +   int ret;
> +
> +   printf(" (found coreboot table at %lx)",
> +  gd->arch.coreboot_table);

Missing an ending '\n', if the following get_coreboot_info() fails

> +
> +   ret = get_coreboot_info(_sysinfo);
> +   if (ret != 0) {
> +   printf("Failed to parse coreboot tables 
> (err=%d)\n",
> +  ret);
> +   return ret;
> +   }
> +   }
> +
> +   printf("\n");
> +   }
> +
> +   return 0;
> +}
> +
>  int arch_misc_init(void)
>  {
> return 0;
> --

Otherwise,
Reviewed-by: Bin Meng 

Regards,
Bin

Re: [PATCH 09/17] x86: coreboot: Show the BIOS date

[Bin Meng]

Hi Simon,

On Wed, Apr 7, 2021 at 12:33 PM Simon Glass  wrote:
>
> The BIOS version may not be present, e.g. on a Chrome OS build. Add the
> BIOS date as well, so we get some sort of indication of coreboot's
> vintage.
>
> Signed-off-by: Simon Glass 
> ---
>
>  board/coreboot/coreboot/coreboot.c | 3 +++
>  1 file changed, 3 insertions(+)
>
> diff --git a/board/coreboot/coreboot/coreboot.c 
> b/board/coreboot/coreboot/coreboot.c
> index 175d3ce691a..93f897893eb 100644
> --- a/board/coreboot/coreboot/coreboot.c
> +++ b/board/coreboot/coreboot/coreboot.c
> @@ -39,6 +39,7 @@ int show_board_info(void)
> const char *bios_ver = smbios_string(bios, t0->bios_ver);

I would insert the line here and name the variable as bios_date:

   const char *bios_date = smbios_string(bios, t0->bios_release_date);

> const char *model = smbios_string(system, t1->product_name);
> const char *manufacturer = smbios_string(system, t1->manufacturer);
> +   const char *date = smbios_string(bios, t0->bios_release_date);
>
> if (!model || !manufacturer || !bios_ver)
> goto fallback;
> @@ -46,6 +47,8 @@ int show_board_info(void)
> printf("Vendor: %s\n", manufacturer);
> printf("Model: %s\n", model);
> printf("BIOS Version: %s\n", bios_ver);
> +   if (date)
> +   printf("BIOS date: %s\n", date);
>
> return 0;

Regards,
Bin

Re: [PATCH 08/17] x86: Do cache set-up by default when booting from coreboot

[Bin Meng]

Hi Simon,

On Wed, Apr 7, 2021 at 12:33 PM Simon Glass  wrote:
>
> A recent change to disable cache setup when booting from coreboot
> assumed that this has been done by SPL. The result is that for the
> coreboot board, the cache is disabled (in start.S) and never
> re-enabled.
>
> If the cache was turned off, as it is on boards without SPL, we should
> turn it back on. Add this new condition.
>
> Signed-off-by: Simon Glass 
> ---
>
>  arch/x86/lib/init_helpers.c | 5 +
>  1 file changed, 1 insertion(+), 4 deletions(-)
>
> diff --git a/arch/x86/lib/init_helpers.c b/arch/x86/lib/init_helpers.c
> index 67401b9ba79..0c55544a670 100644
> --- a/arch/x86/lib/init_helpers.c
> +++ b/arch/x86/lib/init_helpers.c
> @@ -18,10 +18,7 @@ int init_cache_f_r(void)
>  IS_ENABLED(CONFIG_FSP_VERSION2);
> int ret;
>
> -   if (!ll_boot_init())
> -   return 0;
> -
> -   do_mtrr &= !IS_ENABLED(CONFIG_FSP_VERSION1) &&

Can we add a comment block here for every configuration we support?

> +   do_mtrr &= !IS_ENABLED(CONFIG_SPL) && 
> !IS_ENABLED(CONFIG_FSP_VERSION1) &&
> !IS_ENABLED(CONFIG_SYS_SLIMBOOTLOADER);
>
> if (do_mtrr) {
> --

Otherwise,
Reviewed-by: Bin Meng 

Regards,
Bin

Re: [PATCH 07/17] x86: Update the MP constants to avoid conflicts

[Bin Meng]

On Wed, Apr 7, 2021 at 12:33 PM Simon Glass  wrote:
>
> These constants conflict with error codes returned by the MP
> implementation when something is wrong. In particular, mp_first_cpu()
> returns MP_SELECT_BSP when running without multiprocessing enabled.
> Since this is -2, it is interpreted as an error by callers, which
> expect a positive CPU number for the first CPU.
>
> Correct this by using a different range for the pre-defined CPU
> numbers, above zero and out of the range of possible CPU values. For
> now it is safe to assume there are no more than 64K CPUs.
>
> This fixes the 'mtrr' command when CONFIG_SMP is not enabled.
>
> Signed-off-by: Simon Glass 
> ---
>
>  arch/x86/include/asm/mp.h | 12 
>  1 file changed, 8 insertions(+), 4 deletions(-)
>

Reviewed-by: Bin Meng 

Re: [PATCH 06/17] x86: Don't set up MTRRs if previously done

[Bin Meng]

On Wed, Apr 7, 2021 at 12:33 PM Simon Glass  wrote:
>
> When starting U-Boot from a previous-stage bootloader we presumably don't
> need to set up the variable MTRRs. In fact this could be harmful if the
> existing settings are not what U-Boot uses.
>
> Skip that step in this case.
>
> Signed-off-by: Simon Glass 
> ---
>
>  arch/x86/cpu/i386/cpu.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>

Reviewed-by: Bin Meng 

Re: [PATCH 01/17] pci: Use const for pci_find_device_id() etc.

[Bin Meng]

On Wed, Apr 7, 2021 at 12:32 PM Simon Glass  wrote:
>
> These functions don't modify the device-ID struct that is passed in, so
> mark the argument as const, so the data structure can be declared that
> way. This allows it to be placed in the rodata section.
>
> Signed-off-by: Simon Glass 
> ---
>
>  drivers/pci/pci-uclass.c | 6 +++---
>  include/pci.h| 4 ++--
>  2 files changed, 5 insertions(+), 5 deletions(-)
>

Reviewed-by: Bin Meng 

Re: [PATCH 05/17] tpm: cr50: Drop unnecessary coral headers

[Bin Meng]

On Wed, Apr 7, 2021 at 12:33 PM Simon Glass  wrote:
>
> These headers are not actually used. Drop them so that this driver can
> be used by other boards, e.g. coreboot.
>
> Signed-off-by: Simon Glass 
> ---
>
>  drivers/tpm/cr50_i2c.c | 2 --
>  1 file changed, 2 deletions(-)
>

Reviewed-by: Bin Meng 

Re: [PATCH 04/17] spi: ich: Don't require the PCH

[Bin Meng]

On Wed, Apr 7, 2021 at 12:34 PM Simon Glass  wrote:
>
> When booting from coreboot we may not have a PCH driver available. The
> SPI driver can operate without the PCH but currently complains in this
> case. Update it to continue to work normally. The only missing feature
> is memory-mapping of SPI-flash contents, which is not essential.
>
> Signed-off-by: Simon Glass 
> ---
>
>  drivers/spi/ich.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>

Reviewed-by: Bin Meng 

But I feel this driver is slightly becoming unmaintainable as there
are many combinations we need to consider ...

Regards,
Bin

Re: [PATCH 03/17] x86: Allow coreboot serial driver to guess the UART

[Bin Meng]

Hi Simon,

On Wed, Apr 7, 2021 at 12:32 PM Simon Glass  wrote:
>
> At present this driver relies on coreboot to provide information about
> the console UART. However if coreboot is not compiled with the UART
> enabled, the information is left out. This configuration is quite
> common, e.g. with shipping x86-based Chrome OS Chromebooks.
>
> Add a way to determine the UART settings in this case, using a
> hard-coded list of PCI IDs.
>
> Signed-off-by: Simon Glass 
> ---
>
>  drivers/serial/serial_coreboot.c | 68 
>  include/pci_ids.h|  1 +
>  2 files changed, 61 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/serial/serial_coreboot.c 
> b/drivers/serial/serial_coreboot.c
> index de09c8681f5..4b4619432d8 100644
> --- a/drivers/serial/serial_coreboot.c
> +++ b/drivers/serial/serial_coreboot.c
> @@ -11,19 +11,71 @@
>  #include 
>  #include 
>
> +static const struct pci_device_id ids[] = {
> +   { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_APL_UART2) },
> +   {},
> +};
> +
> +/*
> + * Coreboot only sets up the UART if it uses it and doesn't bother to put the
> + * details in sysinfo if it doesn't. Try to guess in that case, using devices
> + * we know about
> + *
> + * @plat: Platform data to fill in
> + * @return 0 if found, -ve if no UART was found
> + */
> +static int guess_uart(struct ns16550_plat *plat)

This is really not a guess, but use a pre-configured platform data.
Also this only work for Apollo Lake board, and will break other boards
if they don't have cbinfo available.

Why not just simply put a serial node in the device tree and we are all done?

> +{
> +   struct udevice *bus, *dev;
> +   ulong addr;
> +   int index;
> +   int ret;
> +
> +   ret = uclass_first_device_err(UCLASS_PCI, );
> +   if (ret)
> +   return ret;
> +   index = 0;
> +   ret = pci_bus_find_devices(bus, ids, , );
> +   if (ret)
> +   return ret;
> +   addr = dm_pci_read_bar32(dev, 0);
> +   plat->base = addr;
> +   plat->reg_shift = 2;
> +   plat->reg_width = 4;
> +   plat->clock = 1843200;
> +   plat->fcr = UART_FCR_DEFVAL;
> +   plat->flags = 0;
> +
> +   return 0;
> +}
> +
>  static int coreboot_of_to_plat(struct udevice *dev)
>  {
> struct ns16550_plat *plat = dev_get_plat(dev);
> struct cb_serial *cb_info = lib_sysinfo.serial;
>
> -   plat->base = cb_info->baseaddr;
> -   plat->reg_shift = cb_info->regwidth == 4 ? 2 : 0;
> -   plat->reg_width = cb_info->regwidth;
> -   plat->clock = cb_info->input_hertz;
> -   plat->fcr = UART_FCR_DEFVAL;
> -   plat->flags = 0;
> -   if (cb_info->type == CB_SERIAL_TYPE_IO_MAPPED)
> -   plat->flags |= NS16550_FLAG_IO;
> +   if (cb_info) {
> +   plat->base = cb_info->baseaddr;
> +   plat->reg_shift = cb_info->regwidth == 4 ? 2 : 0;
> +   plat->reg_width = cb_info->regwidth;
> +   plat->clock = cb_info->input_hertz;
> +   plat->fcr = UART_FCR_DEFVAL;
> +   plat->flags = 0;
> +   if (cb_info->type == CB_SERIAL_TYPE_IO_MAPPED)
> +   plat->flags |= NS16550_FLAG_IO;
> +   } else if (CONFIG_IS_ENABLED(PCI)) {
> +   int ret;
> +
> +   ret = guess_uart(plat);
> +   if (ret) {
> +   /*
> +* Returning an error will cause U-Boot to complain 
> that
> +* there is no UART, which may panic. So stay silent 
> and
> +* pray that the video console will work.
> +*/
> +   log_debug("Cannot detect UART\n");
> +   }
> +   }
>
> return 0;
>  }
> diff --git a/include/pci_ids.h b/include/pci_ids.h
> index 7ecedc7f04c..d91c1d08f1a 100644
> --- a/include/pci_ids.h
> +++ b/include/pci_ids.h
> @@ -2987,6 +2987,7 @@
>  #define PCI_DEVICE_ID_INTEL_UNC_R3QPI1 0x3c45
>  #define PCI_DEVICE_ID_INTEL_JAKETOWN_UBOX  0x3ce0
>  #define PCI_DEVICE_ID_INTEL_IOAT_SNB   0x402f
> +#define PCI_DEVICE_ID_INTEL_APL_UART2  0x5ac0
>  #define PCI_DEVICE_ID_INTEL_5100_160x65f0
>  #define PCI_DEVICE_ID_INTEL_5100_190x65f3
>  #define PCI_DEVICE_ID_INTEL_5100_210x65f5
> --

Regards,
Bin

Re: [PATCH 02/17] x86: pci: Allow binding of some devices before relocation

[Bin Meng]

Hi Simon,

On Wed, Apr 7, 2021 at 12:32 PM Simon Glass  wrote:
>
> At present only bridge devices are bound before relocation, to save space
> in pre-relocation memory. In some cases we do actually want to bind a
> device, e.g. because it provides the console UART. Add a devicetree
> binding to support this.
>
> Use the PCI_VENDEV() macro to encode the cell value. This is present in
> U-Boot but not used, so move it to the binding header-file.
>
> Signed-off-by: Simon Glass 
> ---
>
>  doc/device-tree-bindings/pci/x86-pci.txt |  7 -
>  drivers/pci/pci-uclass.c | 33 +++-
>  include/dt-bindings/pci/pci.h| 12 +
>  include/pci.h|  1 -
>  4 files changed, 50 insertions(+), 3 deletions(-)
>  create mode 100644 include/dt-bindings/pci/pci.h
>
> diff --git a/doc/device-tree-bindings/pci/x86-pci.txt 
> b/doc/device-tree-bindings/pci/x86-pci.txt
> index 95e370b3e72..cf4e5ed595a 100644
> --- a/doc/device-tree-bindings/pci/x86-pci.txt
> +++ b/doc/device-tree-bindings/pci/x86-pci.txt
> @@ -20,6 +20,10 @@ For PCI devices the following optional property is 
> available:
> output to be lost. This should not generally be used in production 
> code,
> although it is often harmless.
>
> +- u-boot,pci-pre-reloc : List of vendor/device IDs to bind before 
> relocation, even
> +   if they are not bridges. This is useful if the device is needed (e.g. 
> a
> +   UART). The format is 0x where d is the device ID and v is the
> +   vendor ID.

Can we reuse "u-boot,dm-pre-reloc" to do such thing?

The following is an example from arch/x86/dts/crownbay.dts

pciuart0: uart@a,1 {
compatible = "pci8086,8811.00",
"pci8086,8811",
"pciclass,070002",
"pciclass,0700",
"ns16550";
u-boot,dm-pre-reloc;
reg = <0x00025100 0x0 0x0 0x0 0x0
   0x01025110 0x0 0x0 0x0 0x0>;
reg-shift = <0>;
clock-frequency = <1843200>;
current-speed = <115200>;
};

Regards,
Bin

Re: [PATCH v2 1/5] arm64: dts: imx8mm: Add common -u-boot.dtsi

[Peng Fan (OSS)]

On 2021/3/16 1:45, Jagan Teki wrote:

/soc@0
aips1
aips2
aips3
clk
iomuxc
osc_24m

are common node enablements across imx8mm platform for
dm-spi, dm-pre-reloc stages.

Move them into common dtsi, imx8mm-u-boot.dtsi


This may conflict with 
https://patchwork.ozlabs.org/project/uboot/patch/20210406035904.26598-1-peng@oss.nxp.com/


Thanks,
Peng.



Cc: Tim Harvey 
Cc: Adam Ford 
Cc: Peng Fan 
Cc: Teresa Remmet 
Cc: Igor Opaniuk 
Signed-off-by: Jagan Teki 
---
Changes for v2:
- add venice changes

  arch/arm/dts/imx8mm-beacon-kit-u-boot.dtsi| 37 +-
  arch/arm/dts/imx8mm-evk-u-boot.dtsi   | 37 +-
  arch/arm/dts/imx8mm-u-boot.dtsi   | 39 +++
  arch/arm/dts/imx8mm-venice-gw700x-u-boot.dtsi | 35 +
  arch/arm/dts/imx8mm-venice-u-boot.dtsi| 37 +-
  arch/arm/dts/imx8mm-verdin-u-boot.dtsi| 38 ++
  arch/arm/dts/phycore-imx8mm-u-boot.dtsi   | 37 +-
  7 files changed, 51 insertions(+), 209 deletions(-)
  create mode 100644 arch/arm/dts/imx8mm-u-boot.dtsi

diff --git a/arch/arm/dts/imx8mm-beacon-kit-u-boot.dtsi 
b/arch/arm/dts/imx8mm-beacon-kit-u-boot.dtsi
index 6d80a529ae..73ddfdade6 100644
--- a/arch/arm/dts/imx8mm-beacon-kit-u-boot.dtsi
+++ b/arch/arm/dts/imx8mm-beacon-kit-u-boot.dtsi
@@ -3,6 +3,8 @@
   * Copyright 2020 Compass Electronics Group, LLC
   */
  
+#include "imx8mm-u-boot.dtsi"

+
  / {
wdt-reboot {
compatible = "wdt-reboot";
@@ -11,32 +13,6 @@
};
  };
  
-&{/soc@0} {

-   u-boot,dm-pre-reloc;
-   u-boot,dm-spl;
-};
-
- {
-   u-boot,dm-spl;
-   u-boot,dm-pre-reloc;
-};
-
- {
-   u-boot,dm-spl;
-};
-
- {
-   u-boot,dm-spl;
-};
-
- {
-   u-boot,dm-spl;
-   u-boot,dm-pre-reloc;
-   /delete-property/ assigned-clocks;
-   /delete-property/ assigned-clock-parents;
-   /delete-property/ assigned-clock-rates;
-};
-
  _usdhc2_vmmc {
u-boot,off-on-delay-us = <2>;
  };
@@ -65,15 +41,6 @@
u-boot,dm-spl;
  };
  
- {

-   u-boot,dm-spl;
-};
-
-_24m {
-   u-boot,dm-spl;
-   u-boot,dm-pre-reloc;
-};
-
  _0 {
compatible = "ti,tca6416";
  };
diff --git a/arch/arm/dts/imx8mm-evk-u-boot.dtsi 
b/arch/arm/dts/imx8mm-evk-u-boot.dtsi
index e843a5648e..79dffe7ccd 100644
--- a/arch/arm/dts/imx8mm-evk-u-boot.dtsi
+++ b/arch/arm/dts/imx8mm-evk-u-boot.dtsi
@@ -3,6 +3,8 @@
   * Copyright 2019 NXP
   */
  
+#include "imx8mm-u-boot.dtsi"

+
  / {
wdt-reboot {
compatible = "wdt-reboot";
@@ -11,41 +13,6 @@
};
  };
  
-&{/soc@0} {

-   u-boot,dm-pre-reloc;
-   u-boot,dm-spl;
-};
-
- {
-   u-boot,dm-spl;
-   u-boot,dm-pre-reloc;
-   /delete-property/ assigned-clocks;
-   /delete-property/ assigned-clock-parents;
-   /delete-property/ assigned-clock-rates;
-};
-
-_24m {
-   u-boot,dm-spl;
-   u-boot,dm-pre-reloc;
-};
-
- {
-   u-boot,dm-spl;
-   u-boot,dm-pre-reloc;
-};
-
- {
-   u-boot,dm-spl;
-};
-
- {
-   u-boot,dm-spl;
-};
-
- {
-   u-boot,dm-spl;
-};
-
  _usdhc2_vmmc {
u-boot,off-on-delay-us = <2>;
  };
diff --git a/arch/arm/dts/imx8mm-u-boot.dtsi b/arch/arm/dts/imx8mm-u-boot.dtsi
new file mode 100644
index 00..f833d9df59
--- /dev/null
+++ b/arch/arm/dts/imx8mm-u-boot.dtsi
@@ -0,0 +1,39 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2020 Jagan Teki 
+ */
+
+&{/soc@0} {
+   u-boot,dm-pre-reloc;
+   u-boot,dm-spl;
+};
+
+ {
+   u-boot,dm-spl;
+   u-boot,dm-pre-reloc;
+};
+
+ {
+   u-boot,dm-spl;
+};
+
+ {
+   u-boot,dm-spl;
+};
+
+ {
+   u-boot,dm-spl;
+   u-boot,dm-pre-reloc;
+   /delete-property/ assigned-clocks;
+   /delete-property/ assigned-clock-parents;
+   /delete-property/ assigned-clock-rates;
+};
+
+ {
+   u-boot,dm-spl;
+};
+
+_24m {
+   u-boot,dm-spl;
+   u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/imx8mm-venice-gw700x-u-boot.dtsi 
b/arch/arm/dts/imx8mm-venice-gw700x-u-boot.dtsi
index a4487e20c3..1a15d6a2ad 100644
--- a/arch/arm/dts/imx8mm-venice-gw700x-u-boot.dtsi
+++ b/arch/arm/dts/imx8mm-venice-gw700x-u-boot.dtsi
@@ -3,40 +3,7 @@
   * Copyright 2021 Gateworks Corporation
   */
  
-&{/soc@0} {

-   u-boot,dm-pre-reloc;
-   u-boot,dm-spl;
-};
-
- {
-   u-boot,dm-spl;
-   u-boot,dm-pre-reloc;
-   /delete-property/ assigned-clocks;
-   /delete-property/ assigned-clock-parents;
-   /delete-property/ assigned-clock-rates;
-};
-
-_24m {
-   u-boot,dm-spl;
-   u-boot,dm-pre-reloc;
-};
-
- {
-   u-boot,dm-spl;
-   u-boot,dm-pre-reloc;
-};
-
- {
-   u-boot,dm-spl;
-};
-
- {
-   u-boot,dm-spl;
-};
-
- {
-   u-boot,dm-spl;
-};
+#include "imx8mm-u-boot.dtsi"
  
   {

u-boot,dm-spl;
diff --git a/arch/arm/dts/imx8mm-venice-u-boot.dtsi 
b/arch/arm/dts/imx8mm-venice-u-boot.dtsi
index 5b06d872c6..42b2903f04 100644
--- 

Re: [PATCH] x86: mtrr: Fix function descriptions

[Bin Meng]

On Thu, Apr 8, 2021 at 9:57 AM Bin Meng  wrote:
>
> On Tue, Mar 23, 2021 at 5:39 PM Wolfgang Wallner
>  wrote:
> >
> > Fix copy/paste errors in the descriptions of mtrr_close () and mtrr_set().
> >
> > Signed-off-by: Wolfgang Wallner 
> >
> > ---
> >
> >  arch/x86/include/asm/mtrr.h | 4 ++--
> >  1 file changed, 2 insertions(+), 2 deletions(-)
> >
>
> Reviewed-by: Bin Meng 

applied to u-boot-x86, thanks!

Re: [PATCH] dt-bindings: fsp: Fix Apollo Lake FSP-S devicetree bindings

[Bin Meng]

On Thu, Apr 8, 2021 at 9:56 AM Bin Meng  wrote:
>
> On Tue, Mar 23, 2021 at 4:55 PM Wolfgang Wallner
>  wrote:
> >
> > An entry is missing in the FSP-S devicetree bindings, and as a result
> > the description for the next few following entries is off by one line.
> >
> > Signed-off-by: Wolfgang Wallner 
> >
> > ---
> >
> >  .../fsp/fsp2/apollolake/fsp-s.txt | 19 ++-
> >  1 file changed, 10 insertions(+), 9 deletions(-)
> >
>
> Reviewed-by: Bin Meng 

applied to u-boot-x86, thanks!

Re: [PATCH] x86: mtrr: Fix function descriptions

[Bin Meng]

On Tue, Mar 23, 2021 at 5:39 PM Wolfgang Wallner
 wrote:
>
> Fix copy/paste errors in the descriptions of mtrr_close () and mtrr_set().
>
> Signed-off-by: Wolfgang Wallner 
>
> ---
>
>  arch/x86/include/asm/mtrr.h | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>

Reviewed-by: Bin Meng 

Re: [PATCH] dt-bindings: fsp: Fix Apollo Lake FSP-S devicetree bindings

[Bin Meng]

On Tue, Mar 23, 2021 at 4:55 PM Wolfgang Wallner
 wrote:
>
> An entry is missing in the FSP-S devicetree bindings, and as a result
> the description for the next few following entries is off by one line.
>
> Signed-off-by: Wolfgang Wallner 
>
> ---
>
>  .../fsp/fsp2/apollolake/fsp-s.txt | 19 ++-
>  1 file changed, 10 insertions(+), 9 deletions(-)
>

Reviewed-by: Bin Meng 

Re: [PATCH 02/16] timer: imx-gpt: Add timer support for i.MX SoCs family

[Sean Anderson]

On 4/7/21 3:02 PM, Giulio Benetti wrote:

This timer driver is using GPT Timer (General Purpose Timer) available
on almost all i.MX SoCs family. Since this driver is only meant to
provide u-boot's timer and counter, and most of the i.MX* SoCs use a
24Mhz crystal, let's only deal with that specific source.

Signed-off-by: Giulio Benetti 
[Giulio: added the driver's stub and handled peripheral clock prescaler
setting]
Signed-off-by: Jesse Taube 
[Jesse: added init, setting prescaler for 24Mhz support and enabling
timer]
---
  drivers/timer/Kconfig |   7 ++
  drivers/timer/Makefile|   1 +
  drivers/timer/imx-gpt-timer.c | 162 ++
  3 files changed, 170 insertions(+)
  create mode 100644 drivers/timer/imx-gpt-timer.c

diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig
index 80743a2551..ee81dfa776 100644
--- a/drivers/timer/Kconfig
+++ b/drivers/timer/Kconfig
@@ -227,4 +227,11 @@ config MCHP_PIT64B_TIMER
  Select this to enable support for Microchip 64-bit periodic
  interval timer.
  
+config IMX_GPT_TIMER

+   bool "NXP i.MX GPT timer support"
+   depends on TIMER
+   help
+ Select this to enable support for the timer found on
+ NXP i.MX devices.
+
  endmenu
diff --git a/drivers/timer/Makefile b/drivers/timer/Makefile
index eb5c48cc6c..e214ba7268 100644
--- a/drivers/timer/Makefile
+++ b/drivers/timer/Makefile
@@ -25,3 +25,4 @@ obj-$(CONFIG_STM32_TIMER) += stm32_timer.o
  obj-$(CONFIG_X86_TSC_TIMER)   += tsc_timer.o
  obj-$(CONFIG_MTK_TIMER)   += mtk_timer.o
  obj-$(CONFIG_MCHP_PIT64B_TIMER)   += mchp-pit64b-timer.o
+obj-$(CONFIG_IMX_GPT_TIMER)+= imx-gpt-timer.o
diff --git a/drivers/timer/imx-gpt-timer.c b/drivers/timer/imx-gpt-timer.c
new file mode 100644
index 00..a498f2e21c
--- /dev/null
+++ b/drivers/timer/imx-gpt-timer.c
@@ -0,0 +1,162 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2021
+ * Author(s): Giulio Benetti 
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+
+#define GPT_CR_EN  BIT(0)
+#define GPT_CR_FRR BIT(9)
+#define GPT_CR_EN_24M  BIT(10)
+#define GPT_CR_SWR BIT(15)
+
+#define GPT_PR_PRESCALER24M_MASK   0xF000
+#define GPT_PR_PRESCALER24M_SHIFT  12
+#define GPT_PR_PRESCALER24M_MAX(GPT_PR_PRESCALER24M_MASK >> 
GPT_PR_PRESCALER24M_SHIFT)
+#define GPT_PR_PRESCALER_MASK  0x0FFF
+#define GPT_PR_PRESCALER_SHIFT 0
+#define GPT_PR_PRESCALER_MAX   (GPT_PR_PRESCALER_MASK >> 
GPT_PR_PRESCALER_SHIFT)
+
+#define GPT_CLKSRC_IPG_CLK (1 << 6)
+#define GPT_CLKSRC_IPG_CLK_24M (5 << 6)
+
+/* If CONFIG_SYS_HZ_CLOCK not specified et's default to 3Mhz */
+#ifndef CONFIG_SYS_HZ_CLOCK
+#define CONFIG_SYS_HZ_CLOCK300
+#endif
+
+struct imx_gpt_timer_regs {
+   u32 cr;
+   u32 pr;
+   u32 sr;
+   u32 ir;
+   u32 ocr1;
+   u32 ocr2;
+   u32 ocr3;
+   u32 icr1;
+   u32 icr2;
+   u32 cnt;
+};
+
+struct imx_gpt_timer_priv {
+   struct imx_gpt_timer_regs *base;
+};
+
+static u64 imx_gpt_timer_get_count(struct udevice *dev)
+{
+   struct imx_gpt_timer_priv *priv = dev_get_priv(dev);
+   struct imx_gpt_timer_regs *regs = priv->base;
+
+   return readl(>cnt);


This should use timer_conv_64 since it is a 32-bit timer.

--Sean


+}
+
+static int imx_gpt_setup(struct imx_gpt_timer_regs *regs, u32 rate)
+{
+   u32 prescaler = (rate / CONFIG_SYS_HZ_CLOCK) - 1;
+
+   /* Reset the timer */
+   setbits_le32(>cr, GPT_CR_SWR);
+
+   /* Wait for timer to finish reset */
+   while (readl(>cr) & GPT_CR_SWR)
+   ;
+
+   if (rate == 2400UL) {
+   /* Set timer frequency if using 24M clock source */
+   if (prescaler > GPT_PR_PRESCALER24M_MAX)
+   return -EINVAL;
+
+   /* Set 24M prescaler */
+   writel((prescaler << GPT_PR_PRESCALER24M_SHIFT), >pr);
+   /* Set Oscillator as clock source, enable 24M input and set gpt
+* in free-running mode
+*/
+   writel(GPT_CLKSRC_IPG_CLK_24M | GPT_CR_EN_24M | GPT_CR_FRR, 
>cr);
+   } else {
+   if (prescaler > GPT_PR_PRESCALER_MAX)
+   return -EINVAL;
+
+   /* Set prescaler */
+   writel((prescaler << GPT_PR_PRESCALER_SHIFT), >pr);
+   /* Set Peripheral as clock source and set gpt in free-running
+* mode
+*/
+   writel(GPT_CLKSRC_IPG_CLK | GPT_CR_FRR, >cr);
+   }
+
+   /* Start timer */
+   setbits_le32(>cr, GPT_CR_EN);
+
+   return 0;
+}
+
+static int imx_gpt_timer_probe(struct udevice *dev)
+{
+   struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+   struct imx_gpt_timer_priv *priv = dev_get_priv(dev);

Re: [NXP-IMX V2] please pull nxp-imx-2021-4-6

[Sean Anderson]

On 4/7/21 1:30 AM, Peng Fan (OSS) wrote:

Hi Stefano,


Hi Peng,

Did you address the following comments for "imx: hab/caam new feature
and update" from Horia Geantă?

On 3/31/21 8:32 AM, Horia Geantă wrote:

I don't think adding yet another caam driver (drivers/crypto/fsl_caam.c)
is a good idea.
Instead existing driver (drivers/crypto/fsl/*) should be extended / modified.

... snip ...

There are several patches fixing newly added code.
Internal development history is of little value, fixes should be squashed.


I think these are good comments for that series, but I did not see what
your response was.

--Sean


Please pull nxp-imx-2021-4-6.
This PR is based on Tom's master branch.
If you need me rebase on imx/master, I could redo this PR.
This is quite a large PR, since lots stuff in downstream tree.

CI: https://source.denx.de/u-boot/custodians/u-boot-mmc/-/pipelines/7046
--
convert to use binman for i.MX8MN/M/P EVK board
i.MX8M caam/dek support
hab update/fix for i.MX8M/7ULP
env/distro cleanup for i.MX8M
i.MX8M ddr script/driver update
--

Thanks,
Peng.

The following changes since commit 90eba245a66aa20589404ba537215faf2012c1a3:

   Merge branch 'next' (2021-04-05 11:29:57 -0400)

are available in the Git repository at:

   https://github.com/MrVan/u-boot.git tags/nxp-imx-2021-4-6

for you to fetch changes up to cf0202c231815ed41e580f0b81e3abc7493671fc:

   doc: imx8mp-evk: update after using binman (2021-04-07 10:51:49 +0800)


Aymen Sghaier (6):
   crypto: caam: Add CAAM support to i.MX8M platforms
   crypto: caam: Fix build warnings pointer casting
   crypto: Add blob command support for i.MX8M platforms
   crypto: caam: Fix pointer size to 32bit for i.MX8M
   crypto: caam: Add secure memory vid 3 support
   crypto: caam: RNG4 TRNG errata

Breno Lima (13):
   imx: imx7 Support for Manufacturing Protection
   imx: Avoid hardcoded output ring size register offset (ORSR)
   imx: Ensure CAAM clock is enabled prior getting out_jr_size
   imx: Avoid hardcoded Job Ring Max size
   imx: hab: Enable hab.c to authenticate additional images in open 
configuration
   imx: hab: Check if IVT header is HABv4
   mx7ulp: hab: Add hab_status command for HABv4 M4 boot
   imx: hab: Fix build warnings in 32-bit targets
   crypto: fsl: blob: Flush dcache range for destination address
   mx6dq: hab: Fix chip version in hab.h code
   cmd: blob: Add IMX_HAB and CAAM supported SoCs as dependency
   cmd: blob: Instantiate RNG before running CMD_BLOB
   fsl_mfgprot: Fix typo in sign_mppubk()

Clement Faure (2):
   imx8m: Add DEK blob encapsulation for imx8m
   imx8: Add DEK blob encapsulation

Clement Le Marquis (1):
   imx: caam: new u-boot command to set PRIBLOB bitfield from CAAM SCFGR 
register to 0x3

Franck LENORMAND (3):
   crypto: caam: change JR running loop
   caam: enable support for iMX7ULP
   imx7ulp: Enable support for cmd blob

Jacky Bai (1):
   imx8mn: Update the DDR4 timing script on imx8mn ddr4 evk

Peng (1):
   imx8mn: evk: update MAINTAINERS

Peng Fan (20):
   tools: imx image: fix write warning
   imx8mm/p: remove boot.cmd
   imx8mm_evk: add/cleanup variable for distro
   imx8mp_evk: add/cleanup variable for distro
   imx8mp_evk: spl: clean up including headers
   imx8mp_evk: Increase VDD_ARM to 0.95v Overdrive voltage
   power: pca9450: add a new parameter for power_pca9450_init
   imx8mn_evk: drop duplicated code
   imx8mn: Add LPDDR4 EVK board support
   imx8m: soc: update fuse path
   arch: mach-imx: imx8m: fix unique_id read error for imx8mp
   imx8m: add regs used by CAAM
   imx: HAB: Update hab codes to support ARM64 and i.MX8M
   imx8mm_evk: switch to use binman to pack images
   doc: imx8mm_evk: update doc after using binman
   imx8mn-ddr4-evk: switch to use binman
   imx8mn-evk: switch to use binman
   doc: imx8mn_evk: update doc after using binman
   imx8mp-evk: switch to use binman
   doc: imx8mp-evk: update after using binman

Sherry Sun (1):
   imx8mp: ddr: Add inline ECC feature support

Utkarsh Gupta (2):
   imx: HAB: Validate IVT before authenticating image
   imx: hab: Display All HAB events via hab_status command

Ye Li (18):
   imx8mm_evk: Update to latest LPDDR4 script
   imx8mm_evk: Switch to new imx8mm evk board
   imx8mp_evk: Update LPDDR4 timing for new FW 202006
   imx8mp_evk: Update LPDDR4 refresh time
   imx8mn: Add low drive mode support for DDR4/LPDDR4 EVK
   imx8mn: Add support for 11x11 UltraLite part number
   imx8m: Update thermal and PMU kernel nodes for dual/single cores
   imx8m: ddr: Disable CA VREF Training for LPDDR4
   iMX8MQ: Recognize the B2 revision
   misc: ocotp: Update OCOTP driver 

Re: [NXP-IMX] please pull nxp-imx-2021-4-6

[Peng Fan (OSS)]

Hi Stefano,

On 2021/4/6 17:45, Stefano Babic wrote:

Hi Peng,

On 06.04.21 11:34, Peng Fan (OSS) wrote:

Hi Stefano,

Please pull nxp-imx-2021-4-6. This PR is based on Tom's master branch. 
If you need
me rebase on imx/master, I could redo this PR. This is quite a large 
PR, since lots

stuff in downstream tree.

I ran local buildman test for all boards, no issue found.
--
convert to use binman for i.MX8MN/M/P EVK board
i.MX8M caam/dek support
hab update/fix for i.MX8M/7ULP
env/distro cleanup for i.MX8M
i.MX8M ddr script/driver update
--



Can you help me to sync myself with then patches in patchwork ? IMHO you 
have two big series, I name them as "update on imx8m" (26 patches) and 
"imx: hab/caam new features and update" (37 patches). In PR there should 
be something more as the count of patches does not match ;-)


Sorry for this. I have a V2 PR
https://patchwork.ozlabs.org/project/uboot/patch/db6pr0402mb276fc5d80300aa73058e88...@db6pr0402mb2760.eurprd04.prod.outlook.com/

The last PR was wrongly did direclty from my local tree.
V2 PR is done from downloading patches on patchwork.

I have updated the patches with awaiting upstream status.

Thanks,
Peng.



Regards,
Stefano


Thanks,
Peng.

The following changes since commit 
90eba245a66aa20589404ba537215faf2012c1a3:


   Merge branch 'next' (2021-04-05 11:29:57 -0400)

are available in the Git repository at:

   https://github.com/MrVan/u-boot.git tags/nxp-imx-2021-4-6

for you to fetch changes up to 95dfcc086b419aece6835fd7aaad704de661e246:

   doc: imx8mp-evk: update after using binman (2021-04-06 17:19:45 +0800)


Aymen Sghaier (6):
   crypto: caam: Add CAAM support to i.MX8M platforms
   crypto: caam: Fix build warnings pointer casting
   crypto: Add blob command support for i.MX8M platforms
   crypto: caam: Fix pointer size to 32bit for i.MX8M
   crypto: caam: Add secure memory vid 3 support
   crypto: caam: RNG4 TRNG errata

Breno Lima (13):
   imx: imx7 Support for Manufacturing Protection
   imx: Avoid hardcoded output ring size register offset (ORSR)
   imx: Ensure CAAM clock is enabled prior getting out_jr_size
   imx: Avoid hardcoded Job Ring Max size
   imx: hab: Enable hab.c to authenticate additional images in 
open configuration

   imx: hab: Check if IVT header is HABv4
   mx7ulp: hab: Add hab_status command for HABv4 M4 boot
   imx: hab: Fix build warnings in 32-bit targets
   crypto: fsl: blob: Flush dcache range for destination address
   mx6dq: hab: Fix chip version in hab.h code
   cmd: blob: Add IMX_HAB and CAAM supported SoCs as dependency
   cmd: blob: Instantiate RNG before running CMD_BLOB
   fsl_mfgprot: Fix typo in sign_mppubk()

Clement Faure (2):
   imx8m: Add DEK blob encapsulation for imx8m
   imx8: Add DEK blob encapsulation

Clement Le Marquis (1):
   imx: caam: new u-boot command to set PRIBLOB bitfield from CAAM 
SCFGR register to 0x3


Franck LENORMAND (3):
   crypto: caam: change JR running loop
   caam: enable support for iMX7ULP
   imx7ulp: Enable support for cmd blob

Jacky Bai (1):
   imx8mn: Update the DDR4 timing script on imx8mn ddr4 evk

Peng Fan (21):
   tools: imx image: fix write warning
   imx8mm/p: remove boot.cmd
   imx8mm_evk: add/cleanup variable for distro
   imx8mp_evk: add/cleanup variable for distro
   imx8mp_evk: spl: clean up including headers
   imx8mp_evk: Increase VDD_ARM to 0.95v Overdrive voltage
   power: pca9450: add a new parameter for power_pca9450_init
   imx8mn_evk: drop duplicated code
   imx8mn: Add LPDDR4 EVK board support
   imx: logos: use NXP logo
   imx8m: soc: update fuse path
   arch: mach-imx: imx8m: fix unique_id read error for imx8mp
   imx: HAB: Update hab codes to support ARM64 and i.MX8M
   imx8m: add regs used by CAAM
   imx8mm_evk: switch to use binman to pack images
   doc: imx8mm_evk: update doc after using binman
   imx8mn-ddr4-evk: switch to use binman
   imx8mn-evk: switch to use binman
   doc: imx8mn_evk: update doc after using binman
   imx8mp-evk: switch to use binman
   doc: imx8mp-evk: update after using binman

Sherry Sun (1):
   imx8mp: ddr: Add inline ECC feature support

Utkarsh Gupta (2):
   imx: HAB: Validate IVT before authenticating image
   imx: hab: Display All HAB events via hab_status command

Ye Li (18):
   imx8mm_evk: Update to latest LPDDR4 script
   imx8mm_evk: Switch to new imx8mm evk board
   imx8mp_evk: Update LPDDR4 timing for new FW 202006
   imx8mp_evk: Update LPDDR4 refresh time
   imx8mn: Add low drive mode support for DDR4/LPDDR4 EVK
   imx8mn: Add support for 11x11 UltraLite part number
   imx8m: Update thermal and PMU kernel nodes for dual/single cores
   

Re: [PATCH 02/16] timer: imx-gpt: Add timer support for i.MX SoCs family

[Jesse T]

>
> > + if (rate == 2400UL) {
> > + /* Set timer frequency if using 24M clock source */
> > + if (prescaler > GPT_PR_PRESCALER24M_MAX)
> > + return -EINVAL;
> > +
>

In the datasheet for the imxrt1050 the 24Mhz scaler output goes into the
normal prescaler.The width of the 24Mhz prescaler is only 4 bits it seems
to be meant to divide the 24Mhz to something more reasonable for the other
prescaler.
I would do something like this...

+ if (rate == 2400UL) {
+ /* Set timer frequency if using 24M clock source */
+ if (prescaler > (GPT_PR_PRESCALER24M_MAX  <<  12) |
GPT_PR_PRESCALER_MAX)
+ return -EINVAL;
+
+   /* Set 24M prescaler */
+   writel(( (prescaler >> 12) << GPT_PR_PRESCALER24M_SHIFT),
>pr);
+   writel(( (prescaler & GPT_PR_PRESCALER_MASK) <<
GPT_PR_PRESCALER_SHIFT), >pr);

Ideally we would have the lengths in bits for GPT_PR_PRESCALER_MASK to
replace the 12, but we can also do...

+ if (rate == 2400UL) {
+ /* Set timer frequency if using 24M clock source */
+ if (prescaler > (GPT_PR_PRESCALER24M_MASK |
GPT_PR_PRESCALER_MAX))
+ return -EINVAL;
+
+   /* Set 24M prescaler */
+   writel(prescaler , >pr);

Side note while debugging this i added `KCFLAGS=-DDEBUG` and the boot would
hang with it but without it would boot normally. The cause for the hang is
this loop will never exit, not this only happens while booting u-boot and
not during the spl stage.
 /drivers/serial/serial_lpuart.c
@@ -356,7 +356,9 @@ static void _lpuart32_serial_putc(struct
lpuart_serial_plat *plat,

  while (true) {
  lpuart_read32(plat->flags, >stat, );

  if ((stat & STAT_TDRE))
  break;

Sorry if im being dumb im new to this stuff and thanks for every one for
walking me through this.


On Wed, Apr 7, 2021 at 3:20 PM Giulio Benetti <
giulio.bene...@benettiengineering.com> wrote:

> On 4/7/21 9:02 PM, Giulio Benetti wrote:
> > This timer driver is using GPT Timer (General Purpose Timer) available
> > on almost all i.MX SoCs family. Since this driver is only meant to
> > provide u-boot's timer and counter, and most of the i.MX* SoCs use a
> > 24Mhz crystal, let's only deal with that specific source.
>
> Sorry, it's not true we deal 24Mhz only, also peripheral clock is dealt.
> So commit log should be:
> ```
> This timer driver is using GPT Timer (General Purpose Timer) available
> on almost all i.MX SoCs family. This driver deals with both 24Mhz
> oscillator as well as peripheral clock.
> ```
>
> Let me know if I need to re-send.
>
> Best regards
> --
> Giulio Benetti
> Benetti Engineering sas
>
> > Signed-off-by: Giulio Benetti 
> > [Giulio: added the driver's stub and handled peripheral clock prescaler
> > setting]
> > Signed-off-by: Jesse Taube 
> > [Jesse: added init, setting prescaler for 24Mhz support and enabling
> > timer]
> > ---
> >   drivers/timer/Kconfig |   7 ++
> >   drivers/timer/Makefile|   1 +
> >   drivers/timer/imx-gpt-timer.c | 162 ++
> >   3 files changed, 170 insertions(+)
> >   create mode 100644 drivers/timer/imx-gpt-timer.c
> >
> > diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig
> > index 80743a2551..ee81dfa776 100644
> > --- a/drivers/timer/Kconfig
> > +++ b/drivers/timer/Kconfig
> > @@ -227,4 +227,11 @@ config MCHP_PIT64B_TIMER
> > Select this to enable support for Microchip 64-bit periodic
> > interval timer.
> >
> > +config IMX_GPT_TIMER
> > + bool "NXP i.MX GPT timer support"
> > + depends on TIMER
> > + help
> > +   Select this to enable support for the timer found on
> > +   NXP i.MX devices.
> > +
> >   endmenu
> > diff --git a/drivers/timer/Makefile b/drivers/timer/Makefile
> > index eb5c48cc6c..e214ba7268 100644
> > --- a/drivers/timer/Makefile
> > +++ b/drivers/timer/Makefile
> > @@ -25,3 +25,4 @@ obj-$(CONFIG_STM32_TIMER)   += stm32_timer.o
> >   obj-$(CONFIG_X86_TSC_TIMER) += tsc_timer.o
> >   obj-$(CONFIG_MTK_TIMER) += mtk_timer.o
> >   obj-$(CONFIG_MCHP_PIT64B_TIMER) += mchp-pit64b-timer.o
> > +obj-$(CONFIG_IMX_GPT_TIMER)  += imx-gpt-timer.o
> > diff --git a/drivers/timer/imx-gpt-timer.c
> b/drivers/timer/imx-gpt-timer.c
> > new file mode 100644
> > index 00..a498f2e21c
> > --- /dev/null
> > +++ b/drivers/timer/imx-gpt-timer.c
> > @@ -0,0 +1,162 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * Copyright (C) 2021
> > + * Author(s): Giulio Benetti 
> > + */
> > +
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +
> > +#include 
> > +
> > +#define GPT_CR_ENBIT(0)
> > +#define GPT_CR_FRR   BIT(9)
> > +#define GPT_CR_EN_24MBIT(10)
> > +#define GPT_CR_SWR   BIT(15)
> > +
> > +#define GPT_PR_PRESCALER24M_MASK 0xF000
> > +#define 

Re: [PATCH 1/1] Azure/GitLab: bump OpenSBI version to 0.9

[Tom Rini]

On Fri, Apr 02, 2021 at 11:42:01AM +0200, Heinrich Schuchardt wrote:

> Version 0.9 of OpenSBI provides the system reset extension which allows us
> to reset and power off boards without board specific code.
> 
> Signed-off-by: Heinrich Schuchardt 
> Reviewed-by: Bin Meng 

Applied to u-boot/master, thanks!

-- 
Tom


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Re: [PATCH] Azure: Rework SH / Renesas job

[Tom Rini]

On Mon, Feb 15, 2021 at 10:52:19AM -0500, Tom Rini wrote:

> Now that there is a single SuperH platform, rework the Azure job
> slightly.  Azure build time limits mean that we need to split the world
> build up still.  Make a single build job for the single Renesas SuperH
> platform as well as all of the ARM platforms from Renesas.
> 
> Cc: Marek Vasut 
> Signed-off-by: Tom Rini 

Applied to u-boot/master, thanks!

-- 
Tom


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Re: [PATCH 2/5] pytest: Lower pygit2 requirement

[Tom Rini]

On Fri, Feb 26, 2021 at 07:52:28AM -0500, Tom Rini wrote:

> The latest versions of pygit2 are not available in practically any
> distribution at this time.  Furthermore, we don't need the latest in
> order to run all of our testsuites.  Reduce this version requirement to
> something older that meets our needs while still supporting running our
> tests on older hosts (and so, test labs).
> 
> Reported-by: Tom Warren 
> Signed-off-by: Tom Rini 

Applied to u-boot/master, thanks!

-- 
Tom


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Re: [PATCH 1/5] GitLab: Remove "tags" stanzas

[Tom Rini]

On Fri, Feb 26, 2021 at 07:52:27AM -0500, Tom Rini wrote:

> Given the structure of our current GitLab tests, we don't make real use
> of the tags.  Furthermore, these tags prevent the automatic usage of the
> default GitLab runners.  Remove these tags.
> 
> Reported-by: Roger Meier 
> Signed-off-by: Tom Rini 

Applied to u-boot/master, thanks!

-- 
Tom


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Re: [PATCH] JFFS2: fix jffs2 summary datacrc status uninitialized

[Tom Rini]

On Tue, Feb 23, 2021 at 12:49:00AM -0300, Wagner Popov dos Santos wrote:

> The function jffs2_1pass_read_inode() was discarding the summary
> inodes and dirent because the value in datacrc flag wasn't
> initialized in function jffs2_sum_process_sum_data().
> 
> This fix initializes the status of all summary records to indicate
> that the CRC needs to be verified when they are loaded.
> 
> Before this fix, the behaviors produced by the undefined value of
> datacrc was:
> - Summary's registries were discarded when 'b->datacrc' is equal
>   as 'CRC_BAD'.
> - Summary's registries were not checked when b->datacrc differs of
>   'CRC_BAD' and 'CRC_UNKNOWN'
> 
> So, almost all of the time the crc just isn't checked, and in some
> cases the registries are discarded.
> 
> Signed-off-by: Wagner Popov dos Santos 

Applied to u-boot/master, thanks!

-- 
Tom


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Re: [PATCH] JFFS2: fix the reading address over nand's limit

[Tom Rini]

On Mon, Feb 22, 2021 at 11:30:58PM -0300, Wagner Popov dos Santos wrote:

> Fixes address violation in functions read_nand_cached() and
> read_onenand_cached(). This happens because these functions
> try to read a fixed amount
> of data even when the offset+length
> is above the nand's limit.
> 
> Signed-off-by: Wagner Popov dos Santos 

Applied to u-boot/master, thanks!

-- 
Tom


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Re: [PATCH] tools: Integrate the Dockerfile used for CI

[Tom Rini]

On Mon, Mar 15, 2021 at 01:19:01PM -0400, Tom Rini wrote:

> Integrate the Dockerfile from
> https://source.denx.de/u-boot/gitlab-ci-runner.git as of
> commit bc6130d572f1 ("Dockerfile: Remove high UID/GID") and introduce a
> short rST on how to build the container.
> 
> Cc: Heinrich Schuchardt 
> Signed-off-by: Tom Rini 

Applied to u-boot/master, thanks!

-- 
Tom


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Re: [PATCH v2] ARM: dts: at91: sama5d3: add u-boot properties to sama5d3 pit timer

[Derald Woods]

On Wed, Apr 7, 2021 at 1:32 AM  wrote:

> On 4/7/21 1:16 AM, Derald Woods wrote:
> > On Tue, Apr 6, 2021 at 4:40 AM Manuel Reis  > > wrote:
> >
> > in the early SPL boot stage whenever there is a call to udelay,
> > dm_timer_init fails to find the pit timer whenever it traverses
> > the device tree, if this property is not present
> >
> > Signed-off-by: Manuel Reis  > >
> > CC: Eugen Hristev  > >
> > ---
> >   arch/arm/dts/sama5d3.dtsi | 1 +
> >   1 file changed, 1 insertion(+)
> >
> > diff --git a/arch/arm/dts/sama5d3.dtsi b/arch/arm/dts/sama5d3.dtsi
> > index 6ed218eaad..42c30e9f30 100644
> > --- a/arch/arm/dts/sama5d3.dtsi
> > +++ b/arch/arm/dts/sama5d3.dtsi
> > @@ -1320,6 +1320,7 @@
> >  reg = <0xfe30 0xf>;
> >  interrupts = <3 IRQ_TYPE_LEVEL_HIGH
> 5>;
> >  clocks = <>;
> > +   u-boot,dm-pre-reloc;
> >  };
> >
> >  watchdog@fe40 {
> > --
> > 2.27.0
> >
> >
> > This patch, on top of v2021.04, allows my SAMA5D3 Xplained board to boot
> > normally again.
> >
> > Tested-by: Derald D. Woods  > >
> >
>
> Hi Derald,
>
> Could I ask, you are using the SPL to boot your board ?
> Did you have to remove any udelay from the ddr2_init code , or it booted
> out of the box by applying this patch only ?
>

With just this patch on top of v2021.04, the board booted as expected. It
did not work with v2021.01. So this patch works for "v2021.04" onward. I
did not touch ddr2_init code.

Derald



>
> Thanks,
> Eugen
>

Re: [EXTERNAL] Re: [PATCH v2 6/6] test: dm: Add test for ECDSA UCLASS support

[Alex G.]

On 4/7/21 12:29 PM, Tim Romanski wrote:

Question for Alex, I see your repo has a few branches related to ECDSA 
(patch-ecdsa-v[1-5], patch-mkimage-keyfile-v{1,2}). You sent me a link 
to 'patch-ecdsa-v1' in a previous email, is that the one that's being 
upstreamed? Should I be working off a different branch or is that one ok?


I'm up to v6 on the patch submission. The differences are not that big, 
but I recommend sticking to the latest.


Alex

[PATCH v2] apalis-imx8x: update build instructions

[Oleksandr Suvorov]

Improve and update u-boot image build instructions to support
the module Apalis iMX8X V1.1B.

Signed-off-by: Oleksandr Suvorov 
---

Changes in v2:
- Update instructions to support the latest Apalis iMX8X V1.1B
- Change the commit message

 doc/board/toradex/apalix-imx8x.rst | 33 --
 1 file changed, 18 insertions(+), 15 deletions(-)

diff --git a/doc/board/toradex/apalix-imx8x.rst 
b/doc/board/toradex/apalix-imx8x.rst
index ce7dde8d00..b070a21d1b 100644
--- a/doc/board/toradex/apalix-imx8x.rst
+++ b/doc/board/toradex/apalix-imx8x.rst
@@ -1,43 +1,46 @@
 .. SPDX-License-Identifier: GPL-2.0+
 
-Apalis iMX8X V1.1A Module
+Apalis iMX8X V1.1B Module (SoC NXP i.MX8QXP RevC)
 ==
 
 Quick Start
 ---
 
-- Build the ARM trusted firmware binary
-- Get scfw_tcm.bin and ahab-container.img
+- Get and Build the ARM trusted firmware
+- Get System Controller firmware
+- Get SECO container
 - Build U-Boot
 - Load U-Boot binary using uuu
 - Flash U-Boot binary into the eMMC
 - Boot
 
+Note: builddir is U-Boot build directory (source directory for in-tree builds)
+
 Get and Build the ARM Trusted Firmware
 --
 
 .. code-block:: bash
 
-$ git clone -b toradex_imx_5.4.24_2.1.0 
http://git.toradex.com/cgit/imx-atf.git
-$ cd imx-atf/
-$ make PLAT=imx8qx bl31
+$ cd $(builddir)
+$ git clone -b toradex_imx_5.4.70_2.3.0 
http://git.toradex.com/cgit/imx-atf.git
+$ make PLAT=imx8qx bl31 -C imx-atf
+$ cp imx-atf/build/imx8qx/release/bl31.bin $(builddir)
 
-Get scfw_tcm.bin and ahab-container.img
+Get System Controller firmware
 ---
 
 .. code-block:: bash
 
-$ wget 
https://github.com/toradex/i.MX-System-Controller-Firmware/blob/master/src/scfw_export_mx8qx_b0/build_mx8qx_b0/mx8qx-apalis-scfw-tcm.bin
-$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/imx-seco-3.6.3.bin
-$ chmod +x imx-seco-3.6.3.bin
-$ ./imx-seco-3.6.3.bin
+$ wget 
https://github.com/toradex/i.MX-System-Controller-Firmware/raw/master/src/scfw_export_mx8qx_b0/build_mx8qx_b0/mx8qx-apalis-scfw-tcm.bin
 
-Copy the following binaries to the U-Boot folder:
+Get SECO container
+---
 
 .. code-block:: bash
 
-$ cp imx-atf/build/imx8qx/release/bl31.bin .
-$ cp imx-seco-3.6.3/firmware/seco/mx8qxb0-ahab-container.img 
mx8qx-ahab-container.imx8_defconfig
+$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/imx-seco-3.7.4.bin
+$ sh imx-seco-3.7.4.bin
+$ cp imx-seco-3.7.4/firmware/seco/mx8qxc0-ahab-container.img 
$(builddir)/mx8qx-ahab-container.img
 
 Build U-Boot
 
@@ -58,7 +61,7 @@ to your host and execute uuu:
 
 .. code-block:: bash
 
-sudo ./uuu u-boot/u-boot-dtb.imx
+sudo ./uuu $(builddir)/u-boot-dtb.imx
 
 Flash the U-Boot Binary into the eMMC
 -
-- 
2.31.1

Re: [EXTERNAL] Re: [PATCH v2 6/6] test: dm: Add test for ECDSA UCLASS support

[Tim Romanski]

Update on current progress on U-Boot ECDSA verification: I've isolated 
the OpenSSL code required to verify a signature signed with the 
nistp256v1 curve, and I've written a small test program to show that the 
code works without any external dependencies [1]. Currently fitting the 
code into Alex's fork of U-Boot.


Question for Alex, I see your repo has a few branches related to ECDSA 
(patch-ecdsa-v[1-5], patch-mkimage-keyfile-v{1,2}). You sent me a link 
to 'patch-ecdsa-v1' in a previous email, is that the one that's being 
upstreamed? Should I be working off a different branch or is that one ok?


Tim

[1] https://github.com/timr11/openssl-ecdsa-verify

On 2021-03-30 2:27 p.m., Tim Romanski wrote:

On 3/30/21 2:17PM, Alexandru Gagniuc  wrote:

I don't have any updates from Tim that you don't. I assume he's still silently 
hacking at it.

Yep, I'm working on a software implementation of ECDSA. Currently have the 
OpenSSL implementation for the nistp256 curve isolated, debugging a test 
program that verifies a signature on data that was randomly generated, then 
will need to clean up unnecessary code and fit it into U-Boot.

CC'd my @linux.microsoft.com email, I prefer to use that one from now on.

All the best,
Tim

-Original Message-
From: Alex G. 
Sent: March 29, 2021 2:43 PM
To: Simon Glass 
Cc: U-Boot Mailing List ; Tom Rini ; Tim 
Romanski 
Subject: [EXTERNAL] Re: [PATCH v2 6/6] test: dm: Add test for ECDSA UCLASS 
support

+ Tim

On 3/29/21 2:43 AM, Simon Glass wrote:

Hi Alexandru,

On Tue, 16 Mar 2021 at 13:24, Alexandru Gagniuc  wrote:

This test verifies that ECDSA_UCLASS is implemented, and that
ecdsa_verify() works as expected. The definition of "expected" is
"does not find a device, and returns -ENODEV".

The lack of a hardware-independent ECDSA implementation prevents us
from having one in the sandbox, for now.

Yes we do need a software impl at some point. Any update on that?

I don't have any updates from Tim that you don't. I assume he's still silently 
hacking at it.

Alex

[RESEND PATCH] apalis/colibri_imx6: remove video= settings

[Oleksandr Suvorov]

Since Toradex provides the full set of overlays for Linux kernel
for display interfaces for both Apalis iMX6Q and Colibri iMX6DL
modules, the video= settings are obsolete. Remove them.

Signed-off-by: Oleksandr Suvorov 
---

 include/configs/apalis_imx6.h  | 5 +
 include/configs/colibri_imx6.h | 3 +--
 2 files changed, 2 insertions(+), 6 deletions(-)

diff --git a/include/configs/apalis_imx6.h b/include/configs/apalis_imx6.h
index 0e81ef94d3..12de0105c6 100644
--- a/include/configs/apalis_imx6.h
+++ b/include/configs/apalis_imx6.h
@@ -163,10 +163,7 @@
"source ${loadaddr}\0" \
"splashpos=m,m\0" \
"splashimage=" __stringify(CONFIG_LOADADDR) "\0" \
-   "vidargs=mxc_hdmi.only_cea=1 " \
-   "video=mxcfb0:dev=hdmi,1920x1080M@60,if=RGB24 " \
-   "video=mxcfb1:off video=mxcfb2:off video=mxcfb3:off " \
-   "fbmem=32M\0 "
+   "vidargs=mxc_hdmi.only_cea=1 fbmem=32M\0"
 
 /* Miscellaneous configurable options */
 #undef CONFIG_SYS_CBSIZE
diff --git a/include/configs/colibri_imx6.h b/include/configs/colibri_imx6.h
index c014d6b2d5..0c99ab0741 100644
--- a/include/configs/colibri_imx6.h
+++ b/include/configs/colibri_imx6.h
@@ -144,8 +144,7 @@
"source ${loadaddr}\0" \
"splashpos=m,m\0" \
"splashimage=" __stringify(CONFIG_LOADADDR) "\0" \
-   "vidargs=video=mxcfb0:dev=lcd,640x480M@60,if=RGB666 " \
-   "video=mxcfb1:off fbmem=8M\0 "
+   "vidargs=fbmem=8M\0"
 
 /* Miscellaneous configurable options */
 #undef CONFIG_SYS_CBSIZE
-- 
2.31.1

[RESEND PATCH] colibri_imx6ull/imx7: add missing tdxargs variable

[Oleksandr Suvorov]

From: Philippe Schenker 

All the other boards have tdxargs specified for setting manual kernel
command-line arguments. Add them also to NAND-based boards.

Signed-off-by: Philippe Schenker 
Signed-off-by: Oleksandr Suvorov 
---

 include/configs/colibri-imx6ull.h | 2 +-
 include/configs/colibri_imx7.h| 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/include/configs/colibri-imx6ull.h 
b/include/configs/colibri-imx6ull.h
index 2827c171c9..22ee2ba03e 100644
--- a/include/configs/colibri-imx6ull.h
+++ b/include/configs/colibri-imx6ull.h
@@ -63,7 +63,7 @@
"ubi.fm_autoconvert=1\0" \
"ubiboot=run setup; " \
"setenv bootargs ${defargs} ${ubiargs} " \
-   "${setupargs} ${vidargs}; echo Booting from NAND...; " \
+   "${setupargs} ${vidargs} ${tdxargs}; echo Booting from NAND...; 
" \
"ubi part ubi &&" \
"ubi read ${kernel_addr_r} kernel && " \
"ubi read ${fdt_addr_r} dtb && " \
diff --git a/include/configs/colibri_imx7.h b/include/configs/colibri_imx7.h
index 85dd891055..2fffaa39c0 100644
--- a/include/configs/colibri_imx7.h
+++ b/include/configs/colibri_imx7.h
@@ -110,7 +110,7 @@
"ubi.fm_autoconvert=1\0" \
"ubiboot=run setup; " \
"setenv bootargs ${defargs} ${ubiargs} " \
-   "${setupargs} ${vidargs}; echo Booting from NAND...; " \
+   "${setupargs} ${vidargs} ${tdxargs}; echo Booting from NAND...; 
" \
"ubi part ubi && run m4boot && " \
"ubi read ${kernel_addr_r} kernel && " \
"ubi read ${fdt_addr_r} dtb && " \
-- 
2.31.1

[RESEND PATCH] colibri_imx6: adjust boot order

[Oleksandr Suvorov]

From: Igor Opaniuk 

Remove duplicate of mmc0, set this boot order:
1) SD
2) eMMC
3) USB
4) DHCP boot

Fixes: 0e15165bc4e0 ("colibri_imx6: boot env configuration updates")
Signed-off-by: Igor Opaniuk 
---

 include/configs/colibri_imx6.h | 1 -
 1 file changed, 1 deletion(-)

diff --git a/include/configs/colibri_imx6.h b/include/configs/colibri_imx6.h
index c014d6b2d5..5f5e201b4c 100644
--- a/include/configs/colibri_imx6.h
+++ b/include/configs/colibri_imx6.h
@@ -72,7 +72,6 @@
 
 #ifndef CONFIG_SPL_BUILD
 #define BOOT_TARGET_DEVICES(func) \
-   func(MMC, mmc, 0) \
func(MMC, mmc, 1) \
func(MMC, mmc, 0) \
func(USB, usb, 0) \
-- 
2.31.1

Re: [PATCH 02/16] timer: imx-gpt: Add timer support for i.MX SoCs family

[Giulio Benetti]

On 4/7/21 9:02 PM, Giulio Benetti wrote:

This timer driver is using GPT Timer (General Purpose Timer) available
on almost all i.MX SoCs family. Since this driver is only meant to
provide u-boot's timer and counter, and most of the i.MX* SoCs use a
24Mhz crystal, let's only deal with that specific source.


Sorry, it's not true we deal 24Mhz only, also peripheral clock is dealt.
So commit log should be:
```
This timer driver is using GPT Timer (General Purpose Timer) available
on almost all i.MX SoCs family. This driver deals with both 24Mhz
oscillator as well as peripheral clock.
```

Let me know if I need to re-send.

Best regards
--
Giulio Benetti
Benetti Engineering sas


Signed-off-by: Giulio Benetti 
[Giulio: added the driver's stub and handled peripheral clock prescaler
setting]
Signed-off-by: Jesse Taube 
[Jesse: added init, setting prescaler for 24Mhz support and enabling
timer]
---
  drivers/timer/Kconfig |   7 ++
  drivers/timer/Makefile|   1 +
  drivers/timer/imx-gpt-timer.c | 162 ++
  3 files changed, 170 insertions(+)
  create mode 100644 drivers/timer/imx-gpt-timer.c

diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig
index 80743a2551..ee81dfa776 100644
--- a/drivers/timer/Kconfig
+++ b/drivers/timer/Kconfig
@@ -227,4 +227,11 @@ config MCHP_PIT64B_TIMER
  Select this to enable support for Microchip 64-bit periodic
  interval timer.
  
+config IMX_GPT_TIMER

+   bool "NXP i.MX GPT timer support"
+   depends on TIMER
+   help
+ Select this to enable support for the timer found on
+ NXP i.MX devices.
+
  endmenu
diff --git a/drivers/timer/Makefile b/drivers/timer/Makefile
index eb5c48cc6c..e214ba7268 100644
--- a/drivers/timer/Makefile
+++ b/drivers/timer/Makefile
@@ -25,3 +25,4 @@ obj-$(CONFIG_STM32_TIMER) += stm32_timer.o
  obj-$(CONFIG_X86_TSC_TIMER)   += tsc_timer.o
  obj-$(CONFIG_MTK_TIMER)   += mtk_timer.o
  obj-$(CONFIG_MCHP_PIT64B_TIMER)   += mchp-pit64b-timer.o
+obj-$(CONFIG_IMX_GPT_TIMER)+= imx-gpt-timer.o
diff --git a/drivers/timer/imx-gpt-timer.c b/drivers/timer/imx-gpt-timer.c
new file mode 100644
index 00..a498f2e21c
--- /dev/null
+++ b/drivers/timer/imx-gpt-timer.c
@@ -0,0 +1,162 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2021
+ * Author(s): Giulio Benetti 
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+
+#define GPT_CR_EN  BIT(0)
+#define GPT_CR_FRR BIT(9)
+#define GPT_CR_EN_24M  BIT(10)
+#define GPT_CR_SWR BIT(15)
+
+#define GPT_PR_PRESCALER24M_MASK   0xF000
+#define GPT_PR_PRESCALER24M_SHIFT  12
+#define GPT_PR_PRESCALER24M_MAX(GPT_PR_PRESCALER24M_MASK >> 
GPT_PR_PRESCALER24M_SHIFT)
+#define GPT_PR_PRESCALER_MASK  0x0FFF
+#define GPT_PR_PRESCALER_SHIFT 0
+#define GPT_PR_PRESCALER_MAX   (GPT_PR_PRESCALER_MASK >> 
GPT_PR_PRESCALER_SHIFT)
+
+#define GPT_CLKSRC_IPG_CLK (1 << 6)
+#define GPT_CLKSRC_IPG_CLK_24M (5 << 6)
+
+/* If CONFIG_SYS_HZ_CLOCK not specified et's default to 3Mhz */
+#ifndef CONFIG_SYS_HZ_CLOCK
+#define CONFIG_SYS_HZ_CLOCK300
+#endif
+
+struct imx_gpt_timer_regs {
+   u32 cr;
+   u32 pr;
+   u32 sr;
+   u32 ir;
+   u32 ocr1;
+   u32 ocr2;
+   u32 ocr3;
+   u32 icr1;
+   u32 icr2;
+   u32 cnt;
+};
+
+struct imx_gpt_timer_priv {
+   struct imx_gpt_timer_regs *base;
+};
+
+static u64 imx_gpt_timer_get_count(struct udevice *dev)
+{
+   struct imx_gpt_timer_priv *priv = dev_get_priv(dev);
+   struct imx_gpt_timer_regs *regs = priv->base;
+
+   return readl(>cnt);
+}
+
+static int imx_gpt_setup(struct imx_gpt_timer_regs *regs, u32 rate)
+{
+   u32 prescaler = (rate / CONFIG_SYS_HZ_CLOCK) - 1;
+
+   /* Reset the timer */
+   setbits_le32(>cr, GPT_CR_SWR);
+
+   /* Wait for timer to finish reset */
+   while (readl(>cr) & GPT_CR_SWR)
+   ;
+
+   if (rate == 2400UL) {
+   /* Set timer frequency if using 24M clock source */
+   if (prescaler > GPT_PR_PRESCALER24M_MAX)
+   return -EINVAL;
+
+   /* Set 24M prescaler */
+   writel((prescaler << GPT_PR_PRESCALER24M_SHIFT), >pr);
+   /* Set Oscillator as clock source, enable 24M input and set gpt
+* in free-running mode
+*/
+   writel(GPT_CLKSRC_IPG_CLK_24M | GPT_CR_EN_24M | GPT_CR_FRR, 
>cr);
+   } else {
+   if (prescaler > GPT_PR_PRESCALER_MAX)
+   return -EINVAL;
+
+   /* Set prescaler */
+   writel((prescaler << GPT_PR_PRESCALER_SHIFT), >pr);
+   /* Set Peripheral as clock source and set gpt in free-running
+* mode
+*/
+   

Re: imxrt1020 EVK u-boot doesn't run.

[Giulio Benetti]

Hi Nicolas,

This patchset includes the fix for i.MXRT1020:
https://patchwork.ozlabs.org/project/uboot/list/?series=237909

Best regards
--
Giulio Benetti
Benetti Engineering sas

On 4/5/21 5:07 PM, Giulio Benetti wrote:

Hi Nicolas,


Il giorno 5 apr 2021, alle ore 16:34, Nicolás Muratore 
 ha scritto:


Hi Giulio, hope this email finds you well, many thanks for your support.

After the modification that you proposed, the result was the following:


yes it's the same message.


Ok, well,



Please let me know when you have finished the timer driver.



I need some time, I’ve created other patches but
there is still something to be fixed. I’m close but
I need some other time. I’m going to send patches
soon.


Many thanks.


You’re welcome

Best regards
Giulio




El dom, 4 abr 2021 a las 15:51, Giulio Benetti 
() escribió:
Hi Nicolas,

On 4/4/21 7:56 PM, Giulio Benetti wrote:

Would you have any idea what is going on?


I've just entered debugging and two things came out:
1) in board/freescale/imxrt-1020-evk/imxrt1020-evk.c when calling
spl_dram_init() there is some printf() inside that gets called, but that
happens before calling preloader_console_init() that set serial up, so
this is the reason why there is no output at all.


Can you please try to apply this patch [1] to check if uart starts to
work and giving you this message [2]?

[1]:
https://patchwork.ozlabs.org/project/uboot/patch/20210404182135.1243077-1-giulio.bene...@benettiengineering.com/
[2]: ```
U-Boot SPL 2021.04-rc5-00518-ga0da06d2f8-dirty (Apr 04 2021 - 19:49:47
+0200)
Could not initialize timer (err -19)
   ```

Thank you
--
Giulio Benetti
Benetti Engineering sas


2) I've completely ignored(wrongly) having a timer and at that time
u-boot allowed it getting a tick-count always at 0, so every delay
called return immediatly with 0. This is not possible anymore and I need
to finish writing gpt-timer driver I was writing.

So please let me finish that gpt-driver timer and I'll send patches to
fix imxrt1020/50-evk.


I really appreciate your help, sorry to bother you, but I'm breaking my
mind thinking why this doesn't run on my EVK.

Many thanks.


Best regards
and happy easter! :-)

[PATCH 05/16] ARM: dts: imxrt1020-evk: enable gpt1 timer

[Giulio Benetti]

Signed-off-by: Giulio Benetti 
---
 arch/arm/dts/imxrt1020-evk.dts | 4 
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/dts/imxrt1020-evk.dts b/arch/arm/dts/imxrt1020-evk.dts
index ece13601bd..a471ff3838 100644
--- a/arch/arm/dts/imxrt1020-evk.dts
+++ b/arch/arm/dts/imxrt1020-evk.dts
@@ -186,6 +186,10 @@
};
 };
 
+ {
+   status = "okay";
+};
+
  {
pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
pinctrl-0 = <_usdhc0>;
-- 
2.25.1

[PATCH 15/16] ARM: dts: imxrt1050-evk: add device_type = "memory" to memory node

[Giulio Benetti]

Now device_type = "memory" is mandatory to allow u-boot to read memory
node, so let's add it to memory node.

Signed-off-by: Giulio Benetti 
---
 arch/arm/dts/imxrt1050-evk.dts | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/dts/imxrt1050-evk.dts b/arch/arm/dts/imxrt1050-evk.dts
index 6d21f2b738..2052d4eb4e 100644
--- a/arch/arm/dts/imxrt1050-evk.dts
+++ b/arch/arm/dts/imxrt1050-evk.dts
@@ -20,6 +20,7 @@
};
 
memory {
+   device_type = "memory";
reg = <0x8000 0x200>;
};
 };
-- 
2.25.1

[PATCH 13/16] ARM: dts: imxrt1050-evk: set gpt1 as tick-timer for u-boot

[Giulio Benetti]

Signed-off-by: Giulio Benetti 
---
 arch/arm/dts/imxrt1050-evk.dts | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/dts/imxrt1050-evk.dts b/arch/arm/dts/imxrt1050-evk.dts
index e592330332..6d21f2b738 100644
--- a/arch/arm/dts/imxrt1050-evk.dts
+++ b/arch/arm/dts/imxrt1050-evk.dts
@@ -16,6 +16,7 @@
chosen {
bootargs = "root=/dev/ram";
stdout-path = "serial0:115200n8";
+   tick-timer = 
};
 
memory {
-- 
2.25.1

[PATCH 09/16] configs: imxrt1020-evk: enable imx gpt timer as tick-timer

[Giulio Benetti]

Signed-off-by: Giulio Benetti 
---
 configs/imxrt1020-evk_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/configs/imxrt1020-evk_defconfig b/configs/imxrt1020-evk_defconfig
index 9bddb69cd4..51ff702bc6 100644
--- a/configs/imxrt1020-evk_defconfig
+++ b/configs/imxrt1020-evk_defconfig
@@ -62,6 +62,7 @@ CONFIG_IMXRT_SDRAM=y
 CONFIG_FSL_LPUART=y
 CONFIG_TIMER=y
 CONFIG_SPL_TIMER=y
+CONFIG_IMX_GPT_TIMER=y
 CONFIG_SHA1=y
 CONFIG_SHA256=y
 CONFIG_HEXDUMP=y
-- 
2.25.1

[PATCH 12/16] ARM: dts: imxrt1050-evk: enable gpt1 timer

[Giulio Benetti]

Signed-off-by: Giulio Benetti 
---
 arch/arm/dts/imxrt1050-evk.dts | 4 
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/dts/imxrt1050-evk.dts b/arch/arm/dts/imxrt1050-evk.dts
index b5e781275e..e592330332 100644
--- a/arch/arm/dts/imxrt1050-evk.dts
+++ b/arch/arm/dts/imxrt1050-evk.dts
@@ -215,6 +215,10 @@
};
 };
 
+ {
+   status = "okay";
+};
+
  {
pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
pinctrl-0 = <_usdhc0>;
-- 
2.25.1

[PATCH 16/16] configs: imxrt1050-evk: enable imx gpt timer as tick-timer

[Giulio Benetti]

Signed-off-by: Giulio Benetti 
---
 configs/imxrt1050-evk_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/configs/imxrt1050-evk_defconfig b/configs/imxrt1050-evk_defconfig
index f639ea7623..e74473511d 100644
--- a/configs/imxrt1050-evk_defconfig
+++ b/configs/imxrt1050-evk_defconfig
@@ -65,6 +65,7 @@ CONFIG_IMXRT_SDRAM=y
 CONFIG_FSL_LPUART=y
 CONFIG_TIMER=y
 CONFIG_SPL_TIMER=y
+CONFIG_IMX_GPT_TIMER=y
 CONFIG_DM_VIDEO=y
 CONFIG_BACKLIGHT_GPIO=y
 CONFIG_SYS_WHITE_ON_BLACK=y
-- 
2.25.1

[PATCH 01/16] arm: imxrt: soc: make mpu regions generic

[Giulio Benetti]

This mpu handling works for every i.MXRT SoC that we have, so let's
generalize imxrt1050_region_config to imxrt_region_config.

Signed-off-by: Giulio Benetti 
---
 arch/arm/mach-imx/imxrt/soc.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-imx/imxrt/soc.c b/arch/arm/mach-imx/imxrt/soc.c
index 8e7d15160d..c533f3554a 100644
--- a/arch/arm/mach-imx/imxrt/soc.c
+++ b/arch/arm/mach-imx/imxrt/soc.c
@@ -14,7 +14,7 @@ int arch_cpu_init(void)
 {
int i;
 
-   struct mpu_region_config imxrt1050_region_config[] = {
+   struct mpu_region_config imxrt_region_config[] = {
{ 0x, REGION_0, XN_DIS, PRIV_RW_USR_RW,
  STRONG_ORDER, REGION_4GB },
{ PHYS_SDRAM, REGION_1, XN_DIS, PRIV_RW_USR_RW,
@@ -29,8 +29,8 @@ int arch_cpu_init(void)
 * the whole 4GB address space.
 */
disable_mpu();
-   for (i = 0; i < ARRAY_SIZE(imxrt1050_region_config); i++)
-   mpu_config(_region_config[i]);
+   for (i = 0; i < ARRAY_SIZE(imxrt_region_config); i++)
+   mpu_config(_region_config[i]);
enable_mpu();
 
return 0;
-- 
2.25.1

[PATCH 14/16] ARM: dts: imxrt1050-evk-u-boot: make gpt1 present for SPL

[Giulio Benetti]

Signed-off-by: Giulio Benetti 
---
 arch/arm/dts/imxrt1050-evk-u-boot.dtsi | 4 
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/dts/imxrt1050-evk-u-boot.dtsi 
b/arch/arm/dts/imxrt1050-evk-u-boot.dtsi
index fb4f7f6f9d..a4b50f0bb2 100644
--- a/arch/arm/dts/imxrt1050-evk-u-boot.dtsi
+++ b/arch/arm/dts/imxrt1050-evk-u-boot.dtsi
@@ -10,6 +10,10 @@
};
 };
 
+ {
+   u-boot,dm-spl;
+};
+
  { /* console */
u-boot,dm-spl;
 };
-- 
2.25.1

[PATCH 10/16] ARM: dts: imxrt1050: add alias to osc

[Giulio Benetti]

Signed-off-by: Giulio Benetti 
---
 arch/arm/dts/imxrt1050.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/dts/imxrt1050.dtsi b/arch/arm/dts/imxrt1050.dtsi
index a9281001e5..b7cc3fbc2a 100644
--- a/arch/arm/dts/imxrt1050.dtsi
+++ b/arch/arm/dts/imxrt1050.dtsi
@@ -28,7 +28,7 @@
clocks {
u-boot,dm-spl;
 
-   osc {
+   osc: osc {
u-boot,dm-spl;
compatible = "fsl,imx-osc", "fixed-clock";
#clock-cells = <0>;
-- 
2.25.1

[PATCH 11/16] ARM: dts: imxrt1050: add gpt1 node

[Giulio Benetti]

Signed-off-by: Giulio Benetti 
---
 arch/arm/dts/imxrt1050.dtsi | 8 
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/dts/imxrt1050.dtsi b/arch/arm/dts/imxrt1050.dtsi
index b7cc3fbc2a..6f9da3fe8a 100644
--- a/arch/arm/dts/imxrt1050.dtsi
+++ b/arch/arm/dts/imxrt1050.dtsi
@@ -154,5 +154,13 @@
clock-names = "per";
status = "disabled";
};
+
+   gpt1: gpt1@401ec000 {
+   compatible = "fsl,imxrt-gpt";
+   reg = <0x401ec000 0x4000>;
+   interrupts = <100>;
+   clocks = <>;
+   status = "disabled";
+   };
};
 };
-- 
2.25.1

[PATCH 07/16] ARM: dts: imxrt1020-evk-u-boot: make gpt1 present for SPL

[Giulio Benetti]

Signed-off-by: Giulio Benetti 
---
 arch/arm/dts/imxrt1020-evk-u-boot.dtsi | 4 
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/dts/imxrt1020-evk-u-boot.dtsi 
b/arch/arm/dts/imxrt1020-evk-u-boot.dtsi
index d32c98de9c..34d19e06c5 100644
--- a/arch/arm/dts/imxrt1020-evk-u-boot.dtsi
+++ b/arch/arm/dts/imxrt1020-evk-u-boot.dtsi
@@ -10,6 +10,10 @@
};
 };
 
+ {
+   u-boot,dm-spl;
+};
+
  { /* console */
u-boot,dm-spl;
 };
-- 
2.25.1

[PATCH 06/16] ARM: dts: imxrt1020-evk: set gpt1 as tick-timer for u-boot

[Giulio Benetti]

Signed-off-by: Giulio Benetti 
---
 arch/arm/dts/imxrt1020-evk.dts | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/dts/imxrt1020-evk.dts b/arch/arm/dts/imxrt1020-evk.dts
index a471ff3838..b527206fcf 100644
--- a/arch/arm/dts/imxrt1020-evk.dts
+++ b/arch/arm/dts/imxrt1020-evk.dts
@@ -16,6 +16,7 @@
chosen {
bootargs = "root=/dev/ram";
stdout-path = "serial0:115200n8";
+   tick-timer = 
};
 
memory {
-- 
2.25.1

[PATCH 08/16] ARM: dts: imxrt1020-evk: add device_type = "memory" to memory node

[Giulio Benetti]

Now device_type = "memory" is mandatory to allow u-boot to read memory
node, so let's add it to memory node.

Signed-off-by: Giulio Benetti 
---
 arch/arm/dts/imxrt1020-evk.dts | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/dts/imxrt1020-evk.dts b/arch/arm/dts/imxrt1020-evk.dts
index b527206fcf..2da79e5c20 100644
--- a/arch/arm/dts/imxrt1020-evk.dts
+++ b/arch/arm/dts/imxrt1020-evk.dts
@@ -20,6 +20,7 @@
};
 
memory {
+   device_type = "memory";
reg = <0x8000 0x200>;
};
 };
-- 
2.25.1

[PATCH 04/16] ARM: dts: imxrt1020: add gpt1 node

[Giulio Benetti]

Signed-off-by: Giulio Benetti 
---
 arch/arm/dts/imxrt1020.dtsi | 8 
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/dts/imxrt1020.dtsi b/arch/arm/dts/imxrt1020.dtsi
index 0a3a3b451a..cab608c644 100644
--- a/arch/arm/dts/imxrt1020.dtsi
+++ b/arch/arm/dts/imxrt1020.dtsi
@@ -129,5 +129,13 @@
interrupt-controller;
#interrupt-cells = <2>;
};
+
+   gpt1: gpt1@401ec000 {
+   compatible = "fsl,imxrt-gpt";
+   reg = <0x401ec000 0x4000>;
+   interrupts = <100>;
+   clocks = <>;
+   status = "disabled";
+   };
};
 };
-- 
2.25.1

[PATCH 03/16] ARM: dts: imxrt1020: add alias to osc

[Giulio Benetti]

Signed-off-by: Giulio Benetti 
---
 arch/arm/dts/imxrt1020.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/dts/imxrt1020.dtsi b/arch/arm/dts/imxrt1020.dtsi
index 97f3cec9f3..0a3a3b451a 100644
--- a/arch/arm/dts/imxrt1020.dtsi
+++ b/arch/arm/dts/imxrt1020.dtsi
@@ -36,7 +36,7 @@
clock-frequency = <0>;
};
 
-   osc {
+   osc: osc {
u-boot,dm-spl;
compatible = "fsl,imx-osc", "fixed-clock";
#clock-cells = <0>;
-- 
2.25.1

[PATCH 02/16] timer: imx-gpt: Add timer support for i.MX SoCs family

[Giulio Benetti]

This timer driver is using GPT Timer (General Purpose Timer) available
on almost all i.MX SoCs family. Since this driver is only meant to
provide u-boot's timer and counter, and most of the i.MX* SoCs use a
24Mhz crystal, let's only deal with that specific source.

Signed-off-by: Giulio Benetti 
[Giulio: added the driver's stub and handled peripheral clock prescaler
setting]
Signed-off-by: Jesse Taube 
[Jesse: added init, setting prescaler for 24Mhz support and enabling
timer]
---
 drivers/timer/Kconfig |   7 ++
 drivers/timer/Makefile|   1 +
 drivers/timer/imx-gpt-timer.c | 162 ++
 3 files changed, 170 insertions(+)
 create mode 100644 drivers/timer/imx-gpt-timer.c

diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig
index 80743a2551..ee81dfa776 100644
--- a/drivers/timer/Kconfig
+++ b/drivers/timer/Kconfig
@@ -227,4 +227,11 @@ config MCHP_PIT64B_TIMER
  Select this to enable support for Microchip 64-bit periodic
  interval timer.
 
+config IMX_GPT_TIMER
+   bool "NXP i.MX GPT timer support"
+   depends on TIMER
+   help
+ Select this to enable support for the timer found on
+ NXP i.MX devices.
+
 endmenu
diff --git a/drivers/timer/Makefile b/drivers/timer/Makefile
index eb5c48cc6c..e214ba7268 100644
--- a/drivers/timer/Makefile
+++ b/drivers/timer/Makefile
@@ -25,3 +25,4 @@ obj-$(CONFIG_STM32_TIMER) += stm32_timer.o
 obj-$(CONFIG_X86_TSC_TIMER)+= tsc_timer.o
 obj-$(CONFIG_MTK_TIMER)+= mtk_timer.o
 obj-$(CONFIG_MCHP_PIT64B_TIMER)+= mchp-pit64b-timer.o
+obj-$(CONFIG_IMX_GPT_TIMER)+= imx-gpt-timer.o
diff --git a/drivers/timer/imx-gpt-timer.c b/drivers/timer/imx-gpt-timer.c
new file mode 100644
index 00..a498f2e21c
--- /dev/null
+++ b/drivers/timer/imx-gpt-timer.c
@@ -0,0 +1,162 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2021
+ * Author(s): Giulio Benetti 
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+
+#define GPT_CR_EN  BIT(0)
+#define GPT_CR_FRR BIT(9)
+#define GPT_CR_EN_24M  BIT(10)
+#define GPT_CR_SWR BIT(15)
+
+#define GPT_PR_PRESCALER24M_MASK   0xF000
+#define GPT_PR_PRESCALER24M_SHIFT  12
+#define GPT_PR_PRESCALER24M_MAX(GPT_PR_PRESCALER24M_MASK >> 
GPT_PR_PRESCALER24M_SHIFT)
+#define GPT_PR_PRESCALER_MASK  0x0FFF
+#define GPT_PR_PRESCALER_SHIFT 0
+#define GPT_PR_PRESCALER_MAX   (GPT_PR_PRESCALER_MASK >> 
GPT_PR_PRESCALER_SHIFT)
+
+#define GPT_CLKSRC_IPG_CLK (1 << 6)
+#define GPT_CLKSRC_IPG_CLK_24M (5 << 6)
+
+/* If CONFIG_SYS_HZ_CLOCK not specified et's default to 3Mhz */
+#ifndef CONFIG_SYS_HZ_CLOCK
+#define CONFIG_SYS_HZ_CLOCK300
+#endif
+
+struct imx_gpt_timer_regs {
+   u32 cr;
+   u32 pr;
+   u32 sr;
+   u32 ir;
+   u32 ocr1;
+   u32 ocr2;
+   u32 ocr3;
+   u32 icr1;
+   u32 icr2;
+   u32 cnt;
+};
+
+struct imx_gpt_timer_priv {
+   struct imx_gpt_timer_regs *base;
+};
+
+static u64 imx_gpt_timer_get_count(struct udevice *dev)
+{
+   struct imx_gpt_timer_priv *priv = dev_get_priv(dev);
+   struct imx_gpt_timer_regs *regs = priv->base;
+
+   return readl(>cnt);
+}
+
+static int imx_gpt_setup(struct imx_gpt_timer_regs *regs, u32 rate)
+{
+   u32 prescaler = (rate / CONFIG_SYS_HZ_CLOCK) - 1;
+
+   /* Reset the timer */
+   setbits_le32(>cr, GPT_CR_SWR);
+
+   /* Wait for timer to finish reset */
+   while (readl(>cr) & GPT_CR_SWR)
+   ;
+
+   if (rate == 2400UL) {
+   /* Set timer frequency if using 24M clock source */
+   if (prescaler > GPT_PR_PRESCALER24M_MAX)
+   return -EINVAL;
+
+   /* Set 24M prescaler */
+   writel((prescaler << GPT_PR_PRESCALER24M_SHIFT), >pr);
+   /* Set Oscillator as clock source, enable 24M input and set gpt
+* in free-running mode
+*/
+   writel(GPT_CLKSRC_IPG_CLK_24M | GPT_CR_EN_24M | GPT_CR_FRR, 
>cr);
+   } else {
+   if (prescaler > GPT_PR_PRESCALER_MAX)
+   return -EINVAL;
+
+   /* Set prescaler */
+   writel((prescaler << GPT_PR_PRESCALER_SHIFT), >pr);
+   /* Set Peripheral as clock source and set gpt in free-running
+* mode
+*/
+   writel(GPT_CLKSRC_IPG_CLK | GPT_CR_FRR, >cr);
+   }
+
+   /* Start timer */
+   setbits_le32(>cr, GPT_CR_EN);
+
+   return 0;
+}
+
+static int imx_gpt_timer_probe(struct udevice *dev)
+{
+   struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+   struct imx_gpt_timer_priv *priv = dev_get_priv(dev);
+   struct imx_gpt_timer_regs *regs;
+   struct clk clk;
+   fdt_addr_t addr;
+   u32 clk_rate;
+   

[PATCH 00/16] Fix i.MXRT1020/50

[Giulio Benetti]

This patchset adds imx-gpt-timer driver that is supported by i.MXRT and also
a lot of other i.MX* SoCs. This driver is needed for i.MXRT SoC family that is
lacking at the moment the timer at all and that makes u-boot to fail running on
i.MXRT.
There are also some fixes in imxrt10*0-evk.dts and other minor fixed and
improvements.

Giulio Benetti (16):
  arm: imxrt: soc: make mpu regions generic
  timer: imx-gpt: Add timer support for i.MX SoCs family
  ARM: dts: imxrt1020: add alias to osc
  ARM: dts: imxrt1020: add gpt1 node
  ARM: dts: imxrt1020-evk: enable gpt1 timer
  ARM: dts: imxrt1020-evk: set gpt1 as tick-timer for u-boot
  ARM: dts: imxrt1020-evk-u-boot: make gpt1 present for SPL
  ARM: dts: imxrt1020-evk: add device_type = "memory" to memory node
  configs: imxrt1020-evk: enable imx gpt timer as tick-timer
  ARM: dts: imxrt1050: add alias to osc
  ARM: dts: imxrt1050: add gpt1 node
  ARM: dts: imxrt1050-evk: enable gpt1 timer
  ARM: dts: imxrt1050-evk: set gpt1 as tick-timer for u-boot
  ARM: dts: imxrt1050-evk-u-boot: make gpt1 present for SPL
  ARM: dts: imxrt1050-evk: add device_type = "memory" to memory node
  configs: imxrt1050-evk: enable imx gpt timer as tick-timer

 arch/arm/dts/imxrt1020-evk-u-boot.dtsi |   4 +
 arch/arm/dts/imxrt1020-evk.dts |   6 +
 arch/arm/dts/imxrt1020.dtsi|  10 +-
 arch/arm/dts/imxrt1050-evk-u-boot.dtsi |   4 +
 arch/arm/dts/imxrt1050-evk.dts |   6 +
 arch/arm/dts/imxrt1050.dtsi|  10 +-
 arch/arm/mach-imx/imxrt/soc.c  |   6 +-
 configs/imxrt1020-evk_defconfig|   1 +
 configs/imxrt1050-evk_defconfig|   1 +
 drivers/timer/Kconfig  |   7 ++
 drivers/timer/Makefile |   1 +
 drivers/timer/imx-gpt-timer.c  | 162 +
 12 files changed, 213 insertions(+), 5 deletions(-)
 create mode 100644 drivers/timer/imx-gpt-timer.c

-- 
2.25.1

Re: [PATCH 1/2] of: addr: Abort address translation for parent nodes missing 'ranges'

[Tom Rini]

On Thu, Apr 08, 2021 at 04:14:07AM +1200, Simon Glass wrote:
> Hi,
> 
> On Thu, 8 Apr 2021 at 02:42, Rob Herring  wrote:
> >
> > On Tue, Apr 6, 2021 at 4:53 PM Dario Binacchi  wrote:
> > >
> > >
> > > > Il 06/04/2021 16:26 Rob Herring  ha scritto:
> > > >
> > > >
> > > > On Tue, Mar 16, 2021 at 8:26 PM Bin Meng  wrote:
> > > > >
> > > > > Hi Dario,
> > > > >
> > > > > On Wed, Mar 17, 2021 at 4:57 AM Dario Binacchi  
> > > > > wrote:
> > > > > >
> > > > > > Hi Bin,
> > > > > >
> > > > > > > Il 16/03/2021 02:28 Bin Meng  ha scritto:
> > > > > > >
> > > > > > >
> > > > > > > Hi Dario,
> > > > > > >
> > > > > > > On Tue, Mar 16, 2021 at 6:49 AM Dario Binacchi 
> > > > > > >  wrote:
> > > > > > > >
> > > > > > > >
> > > > > > > > > Il 15/03/2021 19:23 Simon Glass  ha 
> > > > > > > > > scritto:
> > > > > > > > >
> > > > > > > > >
> > > > > > > > > +Tom Rini too
> > > > > > > > >
> > > > > > > > >
> > > > > > > > > On Tue, 16 Mar 2021 at 03:48, Bin Meng  
> > > > > > > > > wrote:
> > > > > > > > > >
> > > > > > > > > > +Dario Binacchi
> > > > > > > > > >
> > > > > > > > > > On Mon, Mar 15, 2021 at 3:11 PM Simon Glass 
> > > > > > > > > >  wrote:
> > > > > > > > > > >
> > > > > > > > > > > Hi Bin,
> > > > > > > > > > >
> > > > > > > > > > > On Wed, 3 Mar 2021 at 14:54, Simon Glass 
> > > > > > > > > > >  wrote:
> > > > > > > > > > > >
> > > > > > > > > > > > On Fri, 26 Feb 2021 at 00:36, Bin Meng 
> > > > > > > > > > > >  wrote:
> > > > > > > > > > > > >
> > > > > > > > > > > > > The implementation of of_translate_one() was taken 
> > > > > > > > > > > > > from the one in
> > > > > > > > > > > > > Linux kernel drivers/of/address.c, and the Linux one 
> > > > > > > > > > > > > added a quirk
> > > > > > > > > > > > > for Apple Macs that don't have the  property 
> > > > > > > > > > > > > in the parent
> > > > > > > > > > > > > node. Since U-Boot does not support Apple Macs, 
> > > > > > > > > > > > > remove the comment
> > > > > > > > > > > > > block and adhere to the spec to abort the translation.
> > > > > > > > > > > > >
> > > > > > > > > > > > > Signed-off-by: Bin Meng 
> > > > > > > > > > > > > ---
> > > > > > > > > > > > >
> > > > > > > > > > > > >  drivers/core/of_addr.c | 24 ++--
> > > > > > > > > > > > >  1 file changed, 6 insertions(+), 18 deletions(-)
> > > > > > > > > > > >
> > > > > > > > > > > > Reviewed-by: Simon Glass 
> > > > > > > > > > >
> > > > > > > > > > > Unfortunately this seems to cause a test failure for
> > > > > > > > > > > ut_dm_fdt_translation. Can you please take a look?
> > > > > > > > > >
> > > > > > > > > > It seems the no "ranges" property was intentionally removed 
> > > > > > > > > > by the
> > > > > > > > > > following commit:
> > > > > > > > > >
> > > > > > > > > > commit d64b9cdcd475eb7f07b49741ded87e24dae4a5fc
> > > > > > > > > > Author: Dario Binacchi 
> > > > > > > > > > Date:   Wed Dec 30 00:16:21 2020 +0100
> > > > > > > > > >
> > > > > > > > > > fdt: translate address if #size-cells = <0>
> > > > > > > > > >
> > > > > > > > > > The __of_translate_address routine translates an 
> > > > > > > > > > address from the
> > > > > > > > > > device tree into a CPU physical address. A note in the 
> > > > > > > > > > description of
> > > > > > > > > > the routine explains that the crossing of any level with
> > > > > > > > > > since inherited from IBM. This does not happen for 
> > > > > > > > > > Texas Instruments, or
> > > > > > > > > > at least for the beaglebone device tree. Without this 
> > > > > > > > > > patch, in fact,
> > > > > > > > > > the translation into physical addresses of the 
> > > > > > > > > > registers contained in the
> > > > > > > > > > am33xx-clocks.dtsi nodes would not be possible. They 
> > > > > > > > > > all have a parent
> > > > > > > > > > with #size-cells = <0>.
> > > > > > > > > >
> > > > > > > > > > It looks the commit was needed for beaglebone board.
> > > > > > > > > >
> > > > > > > > > > Dario, could you please comment on why U-Boot needs to done 
> > > > > > > > > > like this,
> > > > > > > > > > while Linux kernel has this check? Is the beaglebone board 
> > > > > > > > > > not working
> > > > > > > > > > in Linux?
> > > > > > > > > >
> > > > > > > >
> > > > > > > > Beaglebone is working in Linux, but I think Linux walks the 
> > > > > > > > device tree less
> > > > > > > > fully than u-boot.
> > > > > > > > I was surprised by the address translation error when 
> > > > > > > > traversing nodes with
> > > > > > > > size cells 0. And for this reason I added the 
> > > > > > > > CONFIG_OF_TRANSLATE_ZERO_SIZE_CELLS
> > > > > > > > symbol to fix the issue, not enabled by default, thus making 
> > > > > > > > the change backwards
> > > > > > > > compatible.
> > > > > > >
> > > > > > > Could you please prepare a patch against upstream Linux kernel, so
> > > > > > > that U-Boot can be in sync with it?
> > > >
> > > > I've replied on that patch...
> > > >
> > > > > >
> > > > > > With pleasure. 

Re: [PATCH 1/2] moveconfig.py: add try…except

[Trevor Woerner]

It looks like Simon beat me to this one with 
7570d9bb47be24d9d73518742703f32126af8113
but I'm hoping 2/2 can still make it in.

On Mon 2021-03-15 @ 12:01:32 PM, Trevor Woerner wrote:
> I keep getting a UnicodeDecodeError from one of the header files while
> modifying the headers:
> 
>Traceback (most recent call last):
> File "tools/moveconfig.py", line 1953, in 
>   main()
> File "tools/moveconfig.py", line 1927, in main
>   cleanup_headers(configs, options)
> File "tools/moveconfig.py", line 675, in cleanup_headers
>   cleanup_one_header(header_path, patterns, options)
> File "tools/moveconfig.py", line 599, in cleanup_one_header
>   lines = f.readlines()
> File "/usr/lib64/python3.6/codecs.py", line 321, in decode
>   (result, consumed) = self._buffer_decode(data, self.errors, final)
>   UnicodeDecodeError: 'utf-8' codec can't decode byte 0x83 in position 9: 
> invalid start byte
> 
> I'm curious to know which header file is causing the problem.
> 
> Signed-off-by: Trevor Woerner 
> ---
>  tools/moveconfig.py | 7 ++-
>  1 file changed, 6 insertions(+), 1 deletion(-)
> 
> diff --git a/tools/moveconfig.py b/tools/moveconfig.py
> index 9514d9a00c..dd92c00bb7 100755
> --- a/tools/moveconfig.py
> +++ b/tools/moveconfig.py
> @@ -596,7 +596,12 @@ def cleanup_one_header(header_path, patterns, options):
>options: option flags.
>  """
>  with open(header_path) as f:
> -lines = f.readlines()
> +try:
> +lines = f.readlines()
> +except:
> +print("caught exception: ", sys.exc_info()[0])
> +print("header_path: ", header_path)
> +lines = ""
>  
>  matched = []
>  for i, line in enumerate(lines):
> -- 
> 2.30.0.rc0
> 

Re: [PATCH v2] smbios: Fix table when no string is present

[Simon Glass]

Hi Matthias,

On Tue, 6 Apr 2021 at 21:04,  wrote:
>
> From: Matthias Brugger 
>
> When no string is present in a table, next_ptr points to the same
> location as eos. When calculating the string table length, we would only
> reserve one \0. By spec a SMBIOS table has to end with two \0\0 when no
> strings a present.
>
> Signed-off-by: Matthias Brugger 
>
> ---
>
> Changes in v2:
> - check in smbios_string_table_len if no string present and return value
>   accordingly

This looks like a better idea to me. But where are the \0 bytes
actually written? Perhaps that should be in smbios_set_eos()?

>
>  lib/smbios.c | 4 
>  1 file changed, 4 insertions(+)
>
> diff --git a/lib/smbios.c b/lib/smbios.c
> index 9eb226ec9f..fd57d8694f 100644
> --- a/lib/smbios.c
> +++ b/lib/smbios.c
> @@ -191,6 +191,10 @@ int smbios_update_version(const char *version)
>   */
>  static int smbios_string_table_len(const struct smbios_ctx *ctx)
>  {
> +   /* In case no string is defined we have to return two \0 */
> +   if (ctx->next_ptr == ctx->eos)
> +   return 2;
> +
> /* Allow for the final \0 after all strings */
> return (ctx->next_ptr + 1) - ctx->eos;
>  }
> --
> 2.30.2
>

Regards,
Simon

Re: [RESEND PATCH v1 1/5] efi_loader: Kconfig: Select IMAGE_SIGN_INFO when capsule authentication is enabled

[Simon Glass]

On Thu, 8 Apr 2021 at 02:42, Sughosh Ganu  wrote:
>
> Enable building of the crypto helper functions used during capsule
> authentication by selecting IMAGE_SIGN_INFO.
>
> Signed-off-by: Sughosh Ganu 
> ---
>
> This was not detected when support for capsule auth was added to the
> qemu arm64 platform. This is because the platform includes
> CONFIG_FIT_SIGNATURE which selects IMAGE_SIGN_INFO.
>
>
>  lib/efi_loader/Kconfig | 1 +
>  1 file changed, 1 insertion(+)

Reviewed-by: Simon Glass 

Re: [PATCH 1/2] of: addr: Abort address translation for parent nodes missing 'ranges'

[Simon Glass]

Hi,

On Thu, 8 Apr 2021 at 02:42, Rob Herring  wrote:
>
> On Tue, Apr 6, 2021 at 4:53 PM Dario Binacchi  wrote:
> >
> >
> > > Il 06/04/2021 16:26 Rob Herring  ha scritto:
> > >
> > >
> > > On Tue, Mar 16, 2021 at 8:26 PM Bin Meng  wrote:
> > > >
> > > > Hi Dario,
> > > >
> > > > On Wed, Mar 17, 2021 at 4:57 AM Dario Binacchi  
> > > > wrote:
> > > > >
> > > > > Hi Bin,
> > > > >
> > > > > > Il 16/03/2021 02:28 Bin Meng  ha scritto:
> > > > > >
> > > > > >
> > > > > > Hi Dario,
> > > > > >
> > > > > > On Tue, Mar 16, 2021 at 6:49 AM Dario Binacchi  
> > > > > > wrote:
> > > > > > >
> > > > > > >
> > > > > > > > Il 15/03/2021 19:23 Simon Glass  ha scritto:
> > > > > > > >
> > > > > > > >
> > > > > > > > +Tom Rini too
> > > > > > > >
> > > > > > > >
> > > > > > > > On Tue, 16 Mar 2021 at 03:48, Bin Meng  
> > > > > > > > wrote:
> > > > > > > > >
> > > > > > > > > +Dario Binacchi
> > > > > > > > >
> > > > > > > > > On Mon, Mar 15, 2021 at 3:11 PM Simon Glass 
> > > > > > > > >  wrote:
> > > > > > > > > >
> > > > > > > > > > Hi Bin,
> > > > > > > > > >
> > > > > > > > > > On Wed, 3 Mar 2021 at 14:54, Simon Glass 
> > > > > > > > > >  wrote:
> > > > > > > > > > >
> > > > > > > > > > > On Fri, 26 Feb 2021 at 00:36, Bin Meng 
> > > > > > > > > > >  wrote:
> > > > > > > > > > > >
> > > > > > > > > > > > The implementation of of_translate_one() was taken from 
> > > > > > > > > > > > the one in
> > > > > > > > > > > > Linux kernel drivers/of/address.c, and the Linux one 
> > > > > > > > > > > > added a quirk
> > > > > > > > > > > > for Apple Macs that don't have the  property in 
> > > > > > > > > > > > the parent
> > > > > > > > > > > > node. Since U-Boot does not support Apple Macs, remove 
> > > > > > > > > > > > the comment
> > > > > > > > > > > > block and adhere to the spec to abort the translation.
> > > > > > > > > > > >
> > > > > > > > > > > > Signed-off-by: Bin Meng 
> > > > > > > > > > > > ---
> > > > > > > > > > > >
> > > > > > > > > > > >  drivers/core/of_addr.c | 24 ++--
> > > > > > > > > > > >  1 file changed, 6 insertions(+), 18 deletions(-)
> > > > > > > > > > >
> > > > > > > > > > > Reviewed-by: Simon Glass 
> > > > > > > > > >
> > > > > > > > > > Unfortunately this seems to cause a test failure for
> > > > > > > > > > ut_dm_fdt_translation. Can you please take a look?
> > > > > > > > >
> > > > > > > > > It seems the no "ranges" property was intentionally removed 
> > > > > > > > > by the
> > > > > > > > > following commit:
> > > > > > > > >
> > > > > > > > > commit d64b9cdcd475eb7f07b49741ded87e24dae4a5fc
> > > > > > > > > Author: Dario Binacchi 
> > > > > > > > > Date:   Wed Dec 30 00:16:21 2020 +0100
> > > > > > > > >
> > > > > > > > > fdt: translate address if #size-cells = <0>
> > > > > > > > >
> > > > > > > > > The __of_translate_address routine translates an address 
> > > > > > > > > from the
> > > > > > > > > device tree into a CPU physical address. A note in the 
> > > > > > > > > description of
> > > > > > > > > the routine explains that the crossing of any level with
> > > > > > > > > since inherited from IBM. This does not happen for Texas 
> > > > > > > > > Instruments, or
> > > > > > > > > at least for the beaglebone device tree. Without this 
> > > > > > > > > patch, in fact,
> > > > > > > > > the translation into physical addresses of the registers 
> > > > > > > > > contained in the
> > > > > > > > > am33xx-clocks.dtsi nodes would not be possible. They all 
> > > > > > > > > have a parent
> > > > > > > > > with #size-cells = <0>.
> > > > > > > > >
> > > > > > > > > It looks the commit was needed for beaglebone board.
> > > > > > > > >
> > > > > > > > > Dario, could you please comment on why U-Boot needs to done 
> > > > > > > > > like this,
> > > > > > > > > while Linux kernel has this check? Is the beaglebone board 
> > > > > > > > > not working
> > > > > > > > > in Linux?
> > > > > > > > >
> > > > > > >
> > > > > > > Beaglebone is working in Linux, but I think Linux walks the 
> > > > > > > device tree less
> > > > > > > fully than u-boot.
> > > > > > > I was surprised by the address translation error when traversing 
> > > > > > > nodes with
> > > > > > > size cells 0. And for this reason I added the 
> > > > > > > CONFIG_OF_TRANSLATE_ZERO_SIZE_CELLS
> > > > > > > symbol to fix the issue, not enabled by default, thus making the 
> > > > > > > change backwards
> > > > > > > compatible.
> > > > > >
> > > > > > Could you please prepare a patch against upstream Linux kernel, so
> > > > > > that U-Boot can be in sync with it?
> > >
> > > I've replied on that patch...
> > >
> > > > >
> > > > > With pleasure. But how do I justify the patch since it doesn't fix 
> > > > > any bugs?
> > > > > Can I refer to the patches developed for U-boot?
> > > >
> > > > Good question :)
> > > >
> > > > If Linux does not have any issue, maybe U-Boot's fix is questionable?
> > >
> > > IMO, yes it is. Simply put, 'ranges' must be present to be
> > 

Re: [PATCH 0/5] Add support for embedding public key in platform's dtb

[Simon Glass]

Hi,

On Wed, 7 Apr 2021 at 23:54, Sughosh Ganu  wrote:
>
> Patch 1 fixes an issue of selection of IMAGE_SIGN_INFO config option
> when capsule authentication is enabled.
>
> Patch 2 add two config symbols, EFI_PKEY_DTB_EMBED and EFI_PKEY_FILE
> which are used for enabling embedding of the public key in the dtb,
> and specifying the esl file name.
>
> Patch 3 moves efi_capsule_auth_enabled as a weak function, which can
> be used as a default mechanism for checking if capsule authentication
> has been enabled.
>
> Patch 4 adds a default weak function for retrieving the public key
> from the platform's dtb.
>
> Patch 5 adds the functionality to embed the esl file into the
> platform's dtb during the platform build.
>
> I have tested this functionality on the STM32MP157C DK2 board.
>
> [1] - https://lists.denx.de/pipermail/u-boot/2021-March/442867.html
>
> Sughosh Ganu (5):
>   efi_loader: Kconfig: Select IMAGE_SIGN_INFO when capsule
> authentication is enabled
>   efi_loader: Kconfig: Add symbols for embedding the public key into the
> platform's dtb
>   efi_capsule: Add a weak function to check whether capsule
> authentication is enabled
>   efi_capsule: Add a weak function to get the public key needed for
> capsule authentication
>   Makefile: Add provision for embedding public key in platform's dtb
>
>  Makefile  | 10 ++
>  board/emulation/common/qemu_capsule.c |  6 
>  lib/efi_loader/Kconfig| 16 ++
>  lib/efi_loader/efi_capsule.c  | 44 ---
>  4 files changed, 66 insertions(+), 10 deletions(-)
>
> --
> 2.17.1
>

We need to rethink the use of weak functions for this sort of thing,
or we will end up with an unnavigable mess at some point. If we need
to adjust the flow of boot, let's adjust the flow rather than adding
hooks everywhere.

Regards,
Simon

Re: [PATCH] arm64: dts: meson: odroidc2: readd PHY reset properties

[Neil Armstrong]

On 07/04/2021 16:49, Stefan Agner wrote:
> The sync of the device tree and dt-bindings from Linux v5.6-rc2
> 11a48a5a18c6 ("Linux 5.6-rc2") causes Ethernet to break on some
> ODROID-C2. The PHY seems to need proper reset timing to be functional
> in U-Boot and Linux afterwards. Readd the old PHY reset bindings for
> dwmac until we support the new bindings in the PHY node.
> 
> Fixes: dd5f2351e99a ("arm64: dts: meson: sync dt and bindings from v5.6-rc2")
> Signed-off-by: Stefan Agner 
> ---
>  arch/arm/dts/meson-gxbb-odroidc2.dts | 4 
>  1 file changed, 4 insertions(+)
> 
> diff --git a/arch/arm/dts/meson-gxbb-odroidc2.dts 
> b/arch/arm/dts/meson-gxbb-odroidc2.dts
> index 70fcfb7b06..8b80bbc90b 100644
> --- a/arch/arm/dts/meson-gxbb-odroidc2.dts
> +++ b/arch/arm/dts/meson-gxbb-odroidc2.dts
> @@ -188,6 +188,10 @@
>   phy-handle = <_phy0>;
>   phy-mode = "rgmii";
>  
> + snps,reset-gpio = < GPIOZ_14 0>;
> + snps,reset-delays-us = <0 1 100>;
> + snps,reset-active-low;
> +
>   amlogic,tx-delay-ns = <2>;
>  
>   mdio {
> 

Thanks, it's ok but please add the changes to 
arch/arm/dts/meson-gxbb-odroidc2-u-boot.dtsi
instead, we want to keep the DT files in sync with Linux, local u-boot changes 
must go into
the -u-boot.dtsi files.

Neil

[PATCH] arm64: dts: meson: odroidc2: readd PHY reset properties

[Stefan Agner]

The sync of the device tree and dt-bindings from Linux v5.6-rc2
11a48a5a18c6 ("Linux 5.6-rc2") causes Ethernet to break on some
ODROID-C2. The PHY seems to need proper reset timing to be functional
in U-Boot and Linux afterwards. Readd the old PHY reset bindings for
dwmac until we support the new bindings in the PHY node.

Fixes: dd5f2351e99a ("arm64: dts: meson: sync dt and bindings from v5.6-rc2")
Signed-off-by: Stefan Agner 
---
 arch/arm/dts/meson-gxbb-odroidc2.dts | 4 
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/dts/meson-gxbb-odroidc2.dts 
b/arch/arm/dts/meson-gxbb-odroidc2.dts
index 70fcfb7b06..8b80bbc90b 100644
--- a/arch/arm/dts/meson-gxbb-odroidc2.dts
+++ b/arch/arm/dts/meson-gxbb-odroidc2.dts
@@ -188,6 +188,10 @@
phy-handle = <_phy0>;
phy-mode = "rgmii";
 
+   snps,reset-gpio = < GPIOZ_14 0>;
+   snps,reset-delays-us = <0 1 100>;
+   snps,reset-active-low;
+
amlogic,tx-delay-ns = <2>;
 
mdio {
-- 
2.31.1

Re: [PATCH 1/2] of: addr: Abort address translation for parent nodes missing 'ranges'

[Rob Herring]

On Tue, Apr 6, 2021 at 4:53 PM Dario Binacchi  wrote:
>
>
> > Il 06/04/2021 16:26 Rob Herring  ha scritto:
> >
> >
> > On Tue, Mar 16, 2021 at 8:26 PM Bin Meng  wrote:
> > >
> > > Hi Dario,
> > >
> > > On Wed, Mar 17, 2021 at 4:57 AM Dario Binacchi  wrote:
> > > >
> > > > Hi Bin,
> > > >
> > > > > Il 16/03/2021 02:28 Bin Meng  ha scritto:
> > > > >
> > > > >
> > > > > Hi Dario,
> > > > >
> > > > > On Tue, Mar 16, 2021 at 6:49 AM Dario Binacchi  
> > > > > wrote:
> > > > > >
> > > > > >
> > > > > > > Il 15/03/2021 19:23 Simon Glass  ha scritto:
> > > > > > >
> > > > > > >
> > > > > > > +Tom Rini too
> > > > > > >
> > > > > > >
> > > > > > > On Tue, 16 Mar 2021 at 03:48, Bin Meng  wrote:
> > > > > > > >
> > > > > > > > +Dario Binacchi
> > > > > > > >
> > > > > > > > On Mon, Mar 15, 2021 at 3:11 PM Simon Glass  
> > > > > > > > wrote:
> > > > > > > > >
> > > > > > > > > Hi Bin,
> > > > > > > > >
> > > > > > > > > On Wed, 3 Mar 2021 at 14:54, Simon Glass  
> > > > > > > > > wrote:
> > > > > > > > > >
> > > > > > > > > > On Fri, 26 Feb 2021 at 00:36, Bin Meng  
> > > > > > > > > > wrote:
> > > > > > > > > > >
> > > > > > > > > > > The implementation of of_translate_one() was taken from 
> > > > > > > > > > > the one in
> > > > > > > > > > > Linux kernel drivers/of/address.c, and the Linux one 
> > > > > > > > > > > added a quirk
> > > > > > > > > > > for Apple Macs that don't have the  property in 
> > > > > > > > > > > the parent
> > > > > > > > > > > node. Since U-Boot does not support Apple Macs, remove 
> > > > > > > > > > > the comment
> > > > > > > > > > > block and adhere to the spec to abort the translation.
> > > > > > > > > > >
> > > > > > > > > > > Signed-off-by: Bin Meng 
> > > > > > > > > > > ---
> > > > > > > > > > >
> > > > > > > > > > >  drivers/core/of_addr.c | 24 ++--
> > > > > > > > > > >  1 file changed, 6 insertions(+), 18 deletions(-)
> > > > > > > > > >
> > > > > > > > > > Reviewed-by: Simon Glass 
> > > > > > > > >
> > > > > > > > > Unfortunately this seems to cause a test failure for
> > > > > > > > > ut_dm_fdt_translation. Can you please take a look?
> > > > > > > >
> > > > > > > > It seems the no "ranges" property was intentionally removed by 
> > > > > > > > the
> > > > > > > > following commit:
> > > > > > > >
> > > > > > > > commit d64b9cdcd475eb7f07b49741ded87e24dae4a5fc
> > > > > > > > Author: Dario Binacchi 
> > > > > > > > Date:   Wed Dec 30 00:16:21 2020 +0100
> > > > > > > >
> > > > > > > > fdt: translate address if #size-cells = <0>
> > > > > > > >
> > > > > > > > The __of_translate_address routine translates an address 
> > > > > > > > from the
> > > > > > > > device tree into a CPU physical address. A note in the 
> > > > > > > > description of
> > > > > > > > the routine explains that the crossing of any level with
> > > > > > > > since inherited from IBM. This does not happen for Texas 
> > > > > > > > Instruments, or
> > > > > > > > at least for the beaglebone device tree. Without this 
> > > > > > > > patch, in fact,
> > > > > > > > the translation into physical addresses of the registers 
> > > > > > > > contained in the
> > > > > > > > am33xx-clocks.dtsi nodes would not be possible. They all 
> > > > > > > > have a parent
> > > > > > > > with #size-cells = <0>.
> > > > > > > >
> > > > > > > > It looks the commit was needed for beaglebone board.
> > > > > > > >
> > > > > > > > Dario, could you please comment on why U-Boot needs to done 
> > > > > > > > like this,
> > > > > > > > while Linux kernel has this check? Is the beaglebone board not 
> > > > > > > > working
> > > > > > > > in Linux?
> > > > > > > >
> > > > > >
> > > > > > Beaglebone is working in Linux, but I think Linux walks the device 
> > > > > > tree less
> > > > > > fully than u-boot.
> > > > > > I was surprised by the address translation error when traversing 
> > > > > > nodes with
> > > > > > size cells 0. And for this reason I added the 
> > > > > > CONFIG_OF_TRANSLATE_ZERO_SIZE_CELLS
> > > > > > symbol to fix the issue, not enabled by default, thus making the 
> > > > > > change backwards
> > > > > > compatible.
> > > > >
> > > > > Could you please prepare a patch against upstream Linux kernel, so
> > > > > that U-Boot can be in sync with it?
> >
> > I've replied on that patch...
> >
> > > >
> > > > With pleasure. But how do I justify the patch since it doesn't fix any 
> > > > bugs?
> > > > Can I refer to the patches developed for U-boot?
> > >
> > > Good question :)
> > >
> > > If Linux does not have any issue, maybe U-Boot's fix is questionable?
> >
> > IMO, yes it is. Simply put, 'ranges' must be present to be
> > translatable. Using '#size-cells == 0' is at least questionable, but
> > could maybe be supported (depends what happens with non-empty
> > 'ranges').
> >
> > The 'fix' makes every 'reg' translatable. Give the function an I2C
> > address 'reg' and you'll get back 'I2C controller address + I2C
> > address'.
>
> IMHO this could mean 

[RESEND PATCH v1 5/5] Makefile: Add provision for embedding public key in platform's dtb

[Sughosh Ganu]

Add provision for embedding the public key used for capsule
authentication in the platform's dtb. This is done by invoking the
mkeficapsule utility which puts the public key in the efi signature
list(esl) format into the dtb.

Signed-off-by: Sughosh Ganu 
---
 Makefile | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/Makefile b/Makefile
index 193aa4d1c9..0d50c6a805 100644
--- a/Makefile
+++ b/Makefile
@@ -1010,6 +1010,10 @@ cmd_pad_cat = $(cmd_objcopy) && $(append) || { rm -f $@; 
false; }
 quiet_cmd_lzma = LZMA$@
 cmd_lzma = lzma -c -z -k -9 $< > $@
 
+quiet_cmd_mkeficapsule = MKEFICAPSULE $@
+cmd_mkeficapsule = $(objtree)/tools/mkeficapsule -K $(CONFIG_EFI_PKEY_FILE) \
+   -D $@
+
 cfg: u-boot.cfg
 
 quiet_cmd_cfgcheck = CFGCHK  $2
@@ -1104,8 +1108,14 @@ endif
 PHONY += dtbs
 dtbs: dts/dt.dtb
@:
+ifeq ($(CONFIG_EFI_CAPSULE_AUTHENTICATE)$(CONFIG_EFI_PKEY_DTB_EMBED),yy)
+dts/dt.dtb: u-boot tools
+   $(Q)$(MAKE) $(build)=dts dtbs
+   $(call cmd,mkeficapsule)
+else
 dts/dt.dtb: u-boot
$(Q)$(MAKE) $(build)=dts dtbs
+endif
 
 quiet_cmd_copy = COPY$@
   cmd_copy = cp $< $@
-- 
2.17.1

[RESEND PATCH v1 4/5] efi_capsule: Add a weak function to get the public key needed for capsule authentication

[Sughosh Ganu]

Define a weak function which would be used in the scenario where the
public key is stored on the platform's dtb. This dtb is concatenated
with the u-boot binary during the build process. Platforms which have
a different mechanism for getting the public key would define their
own platform specific function.

Signed-off-by: Sughosh Ganu 
---
 lib/efi_loader/efi_capsule.c | 38 
 1 file changed, 34 insertions(+), 4 deletions(-)

diff --git a/lib/efi_loader/efi_capsule.c b/lib/efi_loader/efi_capsule.c
index 1423b675c8..fc5e1c0856 100644
--- a/lib/efi_loader/efi_capsule.c
+++ b/lib/efi_loader/efi_capsule.c
@@ -14,10 +14,13 @@
 #include 
 #include 
 
+#include 
 #include 
 #include 
 #include 
 
+DECLARE_GLOBAL_DATA_PTR;
+
 const efi_guid_t efi_guid_capsule_report = EFI_CAPSULE_REPORT_GUID;
 static const efi_guid_t efi_guid_firmware_management_capsule_id =
EFI_FIRMWARE_MANAGEMENT_CAPSULE_ID_GUID;
@@ -210,11 +213,38 @@ const efi_guid_t efi_guid_capsule_root_cert_guid =
 
 __weak int efi_get_public_key_data(void **pkey, efi_uintn_t *pkey_len)
 {
-   /* The platform is supposed to provide
-* a method for getting the public key
-* stored in the form of efi signature
-* list
+   /*
+* This is a function for retrieving the public key from the
+* platform's device tree. The platform's device tree has been
+* concatenated with the u-boot binary.
+* If a platform has a different mechanism to get the public
+* key, it can define it's own function.
 */
+   const void *fdt_blob = gd->fdt_blob;
+   const void *blob;
+   const char *cnode_name = "capsule-key";
+   const char *snode_name = "signature";
+   int sig_node;
+   int len;
+
+   sig_node = fdt_subnode_offset(fdt_blob, 0, snode_name);
+   if (sig_node < 0) {
+   EFI_PRINT("Unable to get signature node offset\n");
+   return -FDT_ERR_NOTFOUND;
+   }
+
+   blob = fdt_getprop(fdt_blob, sig_node, cnode_name, );
+
+   if (!blob || len < 0) {
+   EFI_PRINT("Unable to get capsule-key value\n");
+   *pkey = NULL;
+   *pkey_len = 0;
+   return -FDT_ERR_NOTFOUND;
+   }
+
+   *pkey = (void *)blob;
+   *pkey_len = len;
+
return 0;
 }
 
-- 
2.17.1

[RESEND PATCH v1 3/5] efi_capsule: Add a weak function to check whether capsule authentication is enabled

[Sughosh Ganu]

Define a weak function which checks if the environment variable
capsule_authentication_enabled has been set, for enabling capsule
authentication. Other platforms might have a different mechanism to
determine this, and would then define their own platform specific
function.

Signed-off-by: Sughosh Ganu 
---
 board/emulation/common/qemu_capsule.c | 6 --
 lib/efi_loader/efi_capsule.c  | 6 ++
 2 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/board/emulation/common/qemu_capsule.c 
b/board/emulation/common/qemu_capsule.c
index 5cb461d52b..6b8a87022a 100644
--- a/board/emulation/common/qemu_capsule.c
+++ b/board/emulation/common/qemu_capsule.c
@@ -41,9 +41,3 @@ int efi_get_public_key_data(void **pkey, efi_uintn_t 
*pkey_len)
 
return 0;
 }
-
-bool efi_capsule_auth_enabled(void)
-{
-   return env_get("capsule_authentication_enabled") != NULL ?
-   true : false;
-}
diff --git a/lib/efi_loader/efi_capsule.c b/lib/efi_loader/efi_capsule.c
index 0cfff0daf7..1423b675c8 100644
--- a/lib/efi_loader/efi_capsule.c
+++ b/lib/efi_loader/efi_capsule.c
@@ -218,6 +218,12 @@ __weak int efi_get_public_key_data(void **pkey, 
efi_uintn_t *pkey_len)
return 0;
 }
 
+__weak bool efi_capsule_auth_enabled(void)
+{
+   return env_get("capsule_authentication_enabled") ?
+   true : false;
+}
+
 efi_status_t efi_capsule_authenticate(const void *capsule, efi_uintn_t 
capsule_size,
  void **image, efi_uintn_t *image_size)
 {
-- 
2.17.1

[RESEND PATCH v1 2/5] efi_loader: Kconfig: Add symbols for embedding the public key into the platform's dtb

[Sughosh Ganu]

Add config options EFI_PKEY_DTB_EMBED and EFI_PKEY_FILE which are to
be used for embedding the public key to be used for capsule
authentication into the platform's device tree.

The embedding of the public key would take place during the platform
build process.

Signed-off-by: Sughosh Ganu 
---
 lib/efi_loader/Kconfig | 15 +++
 1 file changed, 15 insertions(+)

diff --git a/lib/efi_loader/Kconfig b/lib/efi_loader/Kconfig
index 0b99d7c774..de3083a979 100644
--- a/lib/efi_loader/Kconfig
+++ b/lib/efi_loader/Kconfig
@@ -179,6 +179,21 @@ config EFI_CAPSULE_AUTHENTICATE
  Select this option if you want to enable capsule
  authentication
 
+config EFI_PKEY_DTB_EMBED
+   bool "Embed the public key in the Device Tree"
+   default n
+   depends on EFI_CAPSULE_AUTHENTICATE
+   help
+ Select this option if the public key used for capsule
+ authentication is to be embedded into the platform's
+ device tree.
+
+config EFI_PKEY_FILE
+   string "Public Key esl file to be embedded into the Device Tree"
+   help
+ Specify the absolute path of the public key esl file that is
+ to be embedded in the platform's device tree.
+
 config EFI_CAPSULE_FIRMWARE_FIT
bool "FMP driver for FIT image"
depends on EFI_CAPSULE_FIRMWARE_MANAGEMENT
-- 
2.17.1

[RESEND PATCH v1 1/5] efi_loader: Kconfig: Select IMAGE_SIGN_INFO when capsule authentication is enabled

[Sughosh Ganu]

Enable building of the crypto helper functions used during capsule
authentication by selecting IMAGE_SIGN_INFO.

Signed-off-by: Sughosh Ganu 
---

This was not detected when support for capsule auth was added to the
qemu arm64 platform. This is because the platform includes
CONFIG_FIT_SIGNATURE which selects IMAGE_SIGN_INFO.


 lib/efi_loader/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/lib/efi_loader/Kconfig b/lib/efi_loader/Kconfig
index e44f004f3f..0b99d7c774 100644
--- a/lib/efi_loader/Kconfig
+++ b/lib/efi_loader/Kconfig
@@ -173,6 +173,7 @@ config EFI_CAPSULE_AUTHENTICATE
select X509_CERTIFICATE_PARSER
select PKCS7_MESSAGE_PARSER
select PKCS7_VERIFY
+   select IMAGE_SIGN_INFO
default n
help
  Select this option if you want to enable capsule
-- 
2.17.1

[RESEND PATCH v1 0/5] Add support for embedding public key in platform's dtb

[Sughosh Ganu]

Resending the same set of patches. For some reason, the first
paragraph of the cover letter got deleted in the original
set. Hopefully this will go through fine.

These patches add support for embedding the public key efi signature
list(esl) file into the platform's device tree. The current solution
for the Qemu arm64 platform has the public key as part of an overlay,
and stored on the Efi System Partition(ESP). Having the provision to
embed the public key into the platform's dtb which is then
concatenated with the u-boot binary is a better approach, recommended
by Heinrich[1].

Patch 1 fixes an issue of selection of IMAGE_SIGN_INFO config option
when capsule authentication is enabled.

Patch 2 add two config symbols, EFI_PKEY_DTB_EMBED and EFI_PKEY_FILE
which are used for enabling embedding of the public key in the dtb,
and specifying the esl file name.

Patch 3 moves efi_capsule_auth_enabled as a weak function, which can
be used as a default mechanism for checking if capsule authentication
has been enabled.

Patch 4 adds a default weak function for retrieving the public key
from the platform's dtb.

Patch 5 adds the functionality to embed the esl file into the
platform's dtb during the platform build.

I have tested this functionality on the STM32MP157C DK2 board, and it
works as expected.

[1] - https://lists.denx.de/pipermail/u-boot/2021-March/442867.html 

Sughosh Ganu (5):
  efi_loader: Kconfig: Select IMAGE_SIGN_INFO when capsule
authentication is enabled
  efi_loader: Kconfig: Add symbols for embedding the public key into the
platform's dtb
  efi_capsule: Add a weak function to check whether capsule
authentication is enabled
  efi_capsule: Add a weak function to get the public key needed for
capsule authentication
  Makefile: Add provision for embedding public key in platform's dtb

 Makefile  | 10 ++
 board/emulation/common/qemu_capsule.c |  6 
 lib/efi_loader/Kconfig| 16 ++
 lib/efi_loader/efi_capsule.c  | 44 ---
 4 files changed, 66 insertions(+), 10 deletions(-)

-- 
2.17.1

Re: [PATCH] arm64: dts: meson: fix PHY deassert timing requirements

[Stefan Agner]

On 2021-04-07 16:29, Neil Armstrong wrote:
> On 07/04/2021 16:21, Stefan Agner wrote:
>> On 2021-04-07 15:31, Neil Armstrong wrote:
>>> Hi,
>>>
>>> On 06/04/2021 19:47, Stefan Agner wrote:
 The sync of the device tree and dt-bindings from Linux v5.6-rc2
 11a48a5a18c6 ("Linux 5.6-rc2") causes Ethernet to break on some
 ODROID-C2.

 Meanwhile a fix to increase the reset timing has been added to Linux.
 Instead of reverting the offending commit, use the new reset timing
 from upstream Linux commit c183c406c432 ("arm64: dts: meson: fix PHY
 deassert timing requirements").

 Fixes: dd5f2351e99a ("arm64: dts: meson: sync dt and bindings from 
 v5.6-rc2")
 Signed-off-by: Stefan Agner 
 ---
  arch/arm/dts/meson-g12b-odroid-n2.dtsi | 2 +-
  arch/arm/dts/meson-gxbb-nanopi-k2.dts  | 2 +-
  arch/arm/dts/meson-gxbb-odroidc2.dts   | 2 +-
  arch/arm/dts/meson-gxm-khadas-vim2.dts | 2 +-
  4 files changed, 4 insertions(+), 4 deletions(-)

 diff --git a/arch/arm/dts/meson-g12b-odroid-n2.dtsi 
 b/arch/arm/dts/meson-g12b-odroid-n2.dtsi
 index 6982632ae6..39a09661c5 100644
 --- a/arch/arm/dts/meson-g12b-odroid-n2.dtsi
 +++ b/arch/arm/dts/meson-g12b-odroid-n2.dtsi
 @@ -413,7 +413,7 @@
max-speed = <1000>;

reset-assert-us = <1>;
 -  reset-deassert-us = <3>;
 +  reset-deassert-us = <8>;
>>>
>>> In fact, these are not used by current U-boot, support for
>>> reset/deassert in PHY node
>>> is not yet supported in U-Boot. This first step was to switch to
>>> DM_MDIO and use the
>>> proper Designware glue, the second step is to find how to make use of
>>> these properties.
>>
>> Hm, that is strange, I have users reporting that this patch fixes the
>> issue on their devices. I guess it might be that the problem does not
>> always appear and it was just (bad) luck.
>>
>>>
>>> Concerning the patch, I'll prefer you sync the DT with v5.11 instead.
>>
>> We have multiple reports of non-working ODROID-C2 which worked in
>> previous U-Boot releases:
>> https://github.com/home-assistant/operating-system/issues/1202
>>
>> Similar reports exist in Armbian Forums as well.
>>
>> Until we have proper PHY reset/deassert support, I'd suggest to revert
>> dd5f2351e99a ("arm64: dts: meson: sync dt and bindings from v5.6-rc2")
>> partially then...
> 
> Reverting this is clearly not a solution, the intermediate solution is to
> put back the previous reset properties like it was done for multiple boards
> like in arch/arm/dts/meson-sm1-odroid-c4-u-boot.dtsi :

Yes, that is what I meant with revert ... partially. :)

I'll send a patch.

--
Stefan

> 
> ==
> diff --git a/arch/arm/dts/meson-gxbb-odroidc2-u-boot.dtsi
> b/arch/arm/dts/meson-gxbb-odroidc2-u-boot.dtsi
> index 90087b00db..f1e6914351 100644
> --- a/arch/arm/dts/meson-gxbb-odroidc2-u-boot.dtsi
> +++ b/arch/arm/dts/meson-gxbb-odroidc2-u-boot.dtsi
> @@ -29,6 +29,12 @@
> };
>  };
> 
> + {
> +snps,reset-gpio = < GPIOZ_14 0>;
> +snps,reset-delays-us = <0 1 100>;
> +snps,reset-active-low;
> +};
> +
>   {
> status = "disabled";
>  };
> ==
> 
> Neil
>>
>> --
>> Stefan
>>
>>
>>>
>>> Neil
>>>
reset-gpios = < GPIOZ_15 (GPIO_ACTIVE_LOW | 
 GPIO_OPEN_DRAIN)>;

interrupt-parent = <_intc>;
 diff --git a/arch/arm/dts/meson-gxbb-nanopi-k2.dts 
 b/arch/arm/dts/meson-gxbb-nanopi-k2.dts
 index 7be3e35409..de27beafe9 100644
 --- a/arch/arm/dts/meson-gxbb-nanopi-k2.dts
 +++ b/arch/arm/dts/meson-gxbb-nanopi-k2.dts
 @@ -165,7 +165,7 @@
reg = <0>;

reset-assert-us = <1>;
 -  reset-deassert-us = <3>;
 +  reset-deassert-us = <8>;
reset-gpios = < GPIOZ_14 GPIO_ACTIVE_LOW>;

interrupt-parent = <_intc>;
 diff --git a/arch/arm/dts/meson-gxbb-odroidc2.dts 
 b/arch/arm/dts/meson-gxbb-odroidc2.dts
 index 70fcfb7b06..50de1d01e5 100644
 --- a/arch/arm/dts/meson-gxbb-odroidc2.dts
 +++ b/arch/arm/dts/meson-gxbb-odroidc2.dts
 @@ -200,7 +200,7 @@
reg = <0>;

reset-assert-us = <1>;
 -  reset-deassert-us = <3>;
 +  reset-deassert-us = <8>;
reset-gpios = < GPIOZ_14 GPIO_ACTIVE_LOW>;

interrupt-parent = <_intc>;
 diff --git a/arch/arm/dts/meson-gxm-khadas-vim2.dts 
 b/arch/arm/dts/meson-gxm-khadas-vim2.dts
 index bff8ec2c1c..e38d9e50ca 100644
 --- a/arch/arm/dts/meson-gxm-khadas-vim2.dts
 +++ b/arch/arm/dts/meson-gxm-khadas-vim2.dts
 @@ -194,7 +194,7 @@
   

Re: [PATCH] arm64: dts: meson: fix PHY deassert timing requirements

[Neil Armstrong]

On 07/04/2021 16:21, Stefan Agner wrote:
> On 2021-04-07 15:31, Neil Armstrong wrote:
>> Hi,
>>
>> On 06/04/2021 19:47, Stefan Agner wrote:
>>> The sync of the device tree and dt-bindings from Linux v5.6-rc2
>>> 11a48a5a18c6 ("Linux 5.6-rc2") causes Ethernet to break on some
>>> ODROID-C2.
>>>
>>> Meanwhile a fix to increase the reset timing has been added to Linux.
>>> Instead of reverting the offending commit, use the new reset timing
>>> from upstream Linux commit c183c406c432 ("arm64: dts: meson: fix PHY
>>> deassert timing requirements").
>>>
>>> Fixes: dd5f2351e99a ("arm64: dts: meson: sync dt and bindings from 
>>> v5.6-rc2")
>>> Signed-off-by: Stefan Agner 
>>> ---
>>>  arch/arm/dts/meson-g12b-odroid-n2.dtsi | 2 +-
>>>  arch/arm/dts/meson-gxbb-nanopi-k2.dts  | 2 +-
>>>  arch/arm/dts/meson-gxbb-odroidc2.dts   | 2 +-
>>>  arch/arm/dts/meson-gxm-khadas-vim2.dts | 2 +-
>>>  4 files changed, 4 insertions(+), 4 deletions(-)
>>>
>>> diff --git a/arch/arm/dts/meson-g12b-odroid-n2.dtsi 
>>> b/arch/arm/dts/meson-g12b-odroid-n2.dtsi
>>> index 6982632ae6..39a09661c5 100644
>>> --- a/arch/arm/dts/meson-g12b-odroid-n2.dtsi
>>> +++ b/arch/arm/dts/meson-g12b-odroid-n2.dtsi
>>> @@ -413,7 +413,7 @@
>>> max-speed = <1000>;
>>>
>>> reset-assert-us = <1>;
>>> -   reset-deassert-us = <3>;
>>> +   reset-deassert-us = <8>;
>>
>> In fact, these are not used by current U-boot, support for
>> reset/deassert in PHY node
>> is not yet supported in U-Boot. This first step was to switch to
>> DM_MDIO and use the
>> proper Designware glue, the second step is to find how to make use of
>> these properties.
> 
> Hm, that is strange, I have users reporting that this patch fixes the
> issue on their devices. I guess it might be that the problem does not
> always appear and it was just (bad) luck.
> 
>>
>> Concerning the patch, I'll prefer you sync the DT with v5.11 instead.
> 
> We have multiple reports of non-working ODROID-C2 which worked in
> previous U-Boot releases:
> https://github.com/home-assistant/operating-system/issues/1202
> 
> Similar reports exist in Armbian Forums as well.
> 
> Until we have proper PHY reset/deassert support, I'd suggest to revert
> dd5f2351e99a ("arm64: dts: meson: sync dt and bindings from v5.6-rc2")
> partially then...

Reverting this is clearly not a solution, the intermediate solution is to
put back the previous reset properties like it was done for multiple boards
like in arch/arm/dts/meson-sm1-odroid-c4-u-boot.dtsi :

==
diff --git a/arch/arm/dts/meson-gxbb-odroidc2-u-boot.dtsi 
b/arch/arm/dts/meson-gxbb-odroidc2-u-boot.dtsi
index 90087b00db..f1e6914351 100644
--- a/arch/arm/dts/meson-gxbb-odroidc2-u-boot.dtsi
+++ b/arch/arm/dts/meson-gxbb-odroidc2-u-boot.dtsi
@@ -29,6 +29,12 @@
};
 };

+ {
+snps,reset-gpio = < GPIOZ_14 0>;
+snps,reset-delays-us = <0 1 100>;
+snps,reset-active-low;
+};
+
  {
status = "disabled";
 };
==

Neil
> 
> --
> Stefan
> 
> 
>>
>> Neil
>>
>>> reset-gpios = < GPIOZ_15 (GPIO_ACTIVE_LOW | 
>>> GPIO_OPEN_DRAIN)>;
>>>
>>> interrupt-parent = <_intc>;
>>> diff --git a/arch/arm/dts/meson-gxbb-nanopi-k2.dts 
>>> b/arch/arm/dts/meson-gxbb-nanopi-k2.dts
>>> index 7be3e35409..de27beafe9 100644
>>> --- a/arch/arm/dts/meson-gxbb-nanopi-k2.dts
>>> +++ b/arch/arm/dts/meson-gxbb-nanopi-k2.dts
>>> @@ -165,7 +165,7 @@
>>> reg = <0>;
>>>
>>> reset-assert-us = <1>;
>>> -   reset-deassert-us = <3>;
>>> +   reset-deassert-us = <8>;
>>> reset-gpios = < GPIOZ_14 GPIO_ACTIVE_LOW>;
>>>
>>> interrupt-parent = <_intc>;
>>> diff --git a/arch/arm/dts/meson-gxbb-odroidc2.dts 
>>> b/arch/arm/dts/meson-gxbb-odroidc2.dts
>>> index 70fcfb7b06..50de1d01e5 100644
>>> --- a/arch/arm/dts/meson-gxbb-odroidc2.dts
>>> +++ b/arch/arm/dts/meson-gxbb-odroidc2.dts
>>> @@ -200,7 +200,7 @@
>>> reg = <0>;
>>>
>>> reset-assert-us = <1>;
>>> -   reset-deassert-us = <3>;
>>> +   reset-deassert-us = <8>;
>>> reset-gpios = < GPIOZ_14 GPIO_ACTIVE_LOW>;
>>>
>>> interrupt-parent = <_intc>;
>>> diff --git a/arch/arm/dts/meson-gxm-khadas-vim2.dts 
>>> b/arch/arm/dts/meson-gxm-khadas-vim2.dts
>>> index bff8ec2c1c..e38d9e50ca 100644
>>> --- a/arch/arm/dts/meson-gxm-khadas-vim2.dts
>>> +++ b/arch/arm/dts/meson-gxm-khadas-vim2.dts
>>> @@ -194,7 +194,7 @@
>>> reg = <0>;
>>>
>>> reset-assert-us = <1>;
>>> -   reset-deassert-us = <3>;
>>> +   reset-deassert-us = <8>;
>>> reset-gpios = < GPIOZ_14 GPIO_ACTIVE_LOW>;
>>>
>>> interrupt-parent = <_intc>;
>>>

Re: [PATCH] toradex: configblock: fix module revision in config block

[Oleksandr Suvorov]

On Wed, Apr 7, 2021 at 3:31 PM  wrote:
>
> From: Denys Drozdov 
>
> U-boot might display wrong module revision information
> for modules with an assembly version 'K'. "cfgblock create"
> does not takes into account all revision digits from PID8.
>
> This fix takes into account all digits of PID8
> to store module revision.
>
> Signed-off-by: Denys Drozdov 

Reviewed-by: Oleksandr Suvorov 

> ---
>  board/toradex/common/tdx-cfg-block.c | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/board/toradex/common/tdx-cfg-block.c 
> b/board/toradex/common/tdx-cfg-block.c
> index adab0a0802..9be58d538b 100644
> --- a/board/toradex/common/tdx-cfg-block.c
> +++ b/board/toradex/common/tdx-cfg-block.c
> @@ -555,6 +555,8 @@ static int get_cfgblock_interactive(void)
>  static int get_cfgblock_barcode(char *barcode, struct toradex_hw *tag,
> u32 *serial)
>  {
> +   char revision[3] = {barcode[6], barcode[7], '\0'};
> +
> if (strlen(barcode) < 16) {
> printf("Argument too short, barcode is 16 chars long\n");
> return -1;
> @@ -563,7 +565,7 @@ static int get_cfgblock_barcode(char *barcode, struct 
> toradex_hw *tag,
> /* Get hardware information from the first 8 digits */
> tag->ver_major = barcode[4] - '0';
> tag->ver_minor = barcode[5] - '0';
> -   tag->ver_assembly = barcode[7] - '0';
> +   tag->ver_assembly = simple_strtoul(revision, NULL, 10);
>
> barcode[4] = '\0';
> tag->prodid = simple_strtoul(barcode, NULL, 10);
> --
> 2.17.1
>


-- 
Best regards
Oleksandr Suvorov

Toradex AG
Ebenaustrasse 10 | 6048 Horw | Switzerland | T: +41 41 500 48 00

Re: [PATCH] arm64: dts: meson: fix PHY deassert timing requirements

[Stefan Agner]

On 2021-04-07 15:31, Neil Armstrong wrote:
> Hi,
> 
> On 06/04/2021 19:47, Stefan Agner wrote:
>> The sync of the device tree and dt-bindings from Linux v5.6-rc2
>> 11a48a5a18c6 ("Linux 5.6-rc2") causes Ethernet to break on some
>> ODROID-C2.
>>
>> Meanwhile a fix to increase the reset timing has been added to Linux.
>> Instead of reverting the offending commit, use the new reset timing
>> from upstream Linux commit c183c406c432 ("arm64: dts: meson: fix PHY
>> deassert timing requirements").
>>
>> Fixes: dd5f2351e99a ("arm64: dts: meson: sync dt and bindings from v5.6-rc2")
>> Signed-off-by: Stefan Agner 
>> ---
>>  arch/arm/dts/meson-g12b-odroid-n2.dtsi | 2 +-
>>  arch/arm/dts/meson-gxbb-nanopi-k2.dts  | 2 +-
>>  arch/arm/dts/meson-gxbb-odroidc2.dts   | 2 +-
>>  arch/arm/dts/meson-gxm-khadas-vim2.dts | 2 +-
>>  4 files changed, 4 insertions(+), 4 deletions(-)
>>
>> diff --git a/arch/arm/dts/meson-g12b-odroid-n2.dtsi 
>> b/arch/arm/dts/meson-g12b-odroid-n2.dtsi
>> index 6982632ae6..39a09661c5 100644
>> --- a/arch/arm/dts/meson-g12b-odroid-n2.dtsi
>> +++ b/arch/arm/dts/meson-g12b-odroid-n2.dtsi
>> @@ -413,7 +413,7 @@
>>  max-speed = <1000>;
>>
>>  reset-assert-us = <1>;
>> -reset-deassert-us = <3>;
>> +reset-deassert-us = <8>;
> 
> In fact, these are not used by current U-boot, support for
> reset/deassert in PHY node
> is not yet supported in U-Boot. This first step was to switch to
> DM_MDIO and use the
> proper Designware glue, the second step is to find how to make use of
> these properties.

Hm, that is strange, I have users reporting that this patch fixes the
issue on their devices. I guess it might be that the problem does not
always appear and it was just (bad) luck.

> 
> Concerning the patch, I'll prefer you sync the DT with v5.11 instead.

We have multiple reports of non-working ODROID-C2 which worked in
previous U-Boot releases:
https://github.com/home-assistant/operating-system/issues/1202

Similar reports exist in Armbian Forums as well.

Until we have proper PHY reset/deassert support, I'd suggest to revert
dd5f2351e99a ("arm64: dts: meson: sync dt and bindings from v5.6-rc2")
partially then...

--
Stefan


> 
> Neil
> 
>>  reset-gpios = < GPIOZ_15 (GPIO_ACTIVE_LOW | 
>> GPIO_OPEN_DRAIN)>;
>>
>>  interrupt-parent = <_intc>;
>> diff --git a/arch/arm/dts/meson-gxbb-nanopi-k2.dts 
>> b/arch/arm/dts/meson-gxbb-nanopi-k2.dts
>> index 7be3e35409..de27beafe9 100644
>> --- a/arch/arm/dts/meson-gxbb-nanopi-k2.dts
>> +++ b/arch/arm/dts/meson-gxbb-nanopi-k2.dts
>> @@ -165,7 +165,7 @@
>>  reg = <0>;
>>
>>  reset-assert-us = <1>;
>> -reset-deassert-us = <3>;
>> +reset-deassert-us = <8>;
>>  reset-gpios = < GPIOZ_14 GPIO_ACTIVE_LOW>;
>>
>>  interrupt-parent = <_intc>;
>> diff --git a/arch/arm/dts/meson-gxbb-odroidc2.dts 
>> b/arch/arm/dts/meson-gxbb-odroidc2.dts
>> index 70fcfb7b06..50de1d01e5 100644
>> --- a/arch/arm/dts/meson-gxbb-odroidc2.dts
>> +++ b/arch/arm/dts/meson-gxbb-odroidc2.dts
>> @@ -200,7 +200,7 @@
>>  reg = <0>;
>>
>>  reset-assert-us = <1>;
>> -reset-deassert-us = <3>;
>> +reset-deassert-us = <8>;
>>  reset-gpios = < GPIOZ_14 GPIO_ACTIVE_LOW>;
>>
>>  interrupt-parent = <_intc>;
>> diff --git a/arch/arm/dts/meson-gxm-khadas-vim2.dts 
>> b/arch/arm/dts/meson-gxm-khadas-vim2.dts
>> index bff8ec2c1c..e38d9e50ca 100644
>> --- a/arch/arm/dts/meson-gxm-khadas-vim2.dts
>> +++ b/arch/arm/dts/meson-gxm-khadas-vim2.dts
>> @@ -194,7 +194,7 @@
>>  reg = <0>;
>>
>>  reset-assert-us = <1>;
>> -reset-deassert-us = <3>;
>> +reset-deassert-us = <8>;
>>  reset-gpios = < GPIOZ_14 GPIO_ACTIVE_LOW>;
>>
>>  interrupt-parent = <_intc>;
>>

Re: [PATCH] fs: ext4: Add metadata checksums support

[Tom Rini]

On Fri, Feb 12, 2021 at 05:57:47PM +0100, Fredrik Hallenberg wrote:

> Support crc32c checksums in ext4 filesystems with metadata_csum flag
> active. This includes superblock, inodes, inode and block group tables,
> directory blocks and journal.
> 
> Signed-off-by: Fredrik Hallenberg 

This fails broadly with an error like:
   aarch64:  +   ls1046ardb_qspi
+(ls1046ardb_qspi) In file included from ../include/linux/bitops.h:22,
+(ls1046ardb_qspi)  from include/asm/arch/config.h:14,
+(ls1046ardb_qspi)  from ../include/configs/ls1046a_common.h:32,
+(ls1046ardb_qspi)  from ../include/configs/ls1046ardb.h:10,
+(ls1046ardb_qspi)  from include/config.h:4,
+(ls1046ardb_qspi)  from ../include/common.h:16,
+(ls1046ardb_qspi)  from ../fs/ext4/ext4_common.c:21:
+(ls1046ardb_qspi) ../fs/ext4/ext4_common.c: In function 'ext4fs_read_inode':
+(ls1046ardb_qspi) ../include/linux/kernel.h:184:17: error: comparison of 
distinct pointer types lacks a cast [-Werror]
+(ls1046ardb_qspi)   184 |  (void) (&_min1 == &_min2);  \
+(ls1046ardb_qspi)   | ^~
+(ls1046ardb_qspi) ../fs/ext4/ext4_common.c:1655:9: note: in expansion of macro 
'min'
+(ls1046ardb_qspi)  1655 |  size = min(sizeof(struct ext2_inode), fs->inodesz);
+(ls1046ardb_qspi)   | ^~~
+(ls1046ardb_qspi) cc1: all warnings being treated as errors
+(ls1046ardb_qspi) make[3]: *** [fs/ext4/ext4_common.o] Error 1
+(ls1046ardb_qspi) make[2]: *** [fs/ext4] Error 2
+(ls1046ardb_qspi) make[1]: *** [fs] Error 2
+(ls1046ardb_qspi) make: *** [sub-make] Error 2

-- 
Tom


signature.asc
Description: PGP signature

Re: [PATCH v2] ARM: dts: at91: sama5d3: add u-boot properties to sama5d3 pit timer

[Eugen.Hristev]

On 4/7/21 12:16 PM, Manuel Luís Reis wrote:
> Hi,
> 
> @Derald: Thanks for trying this out.
> 
> @Eugen: For what is worth, I can also confirm that I also tried with
> the latest version v2021.04 and the board boots OK out of the box with
> this patch only.
> 

Ok, great news ! Thanks.

Until this patch can reach the master of u-boot, if anyone needs a tree, 
you can have my testing branch in u-boot-atmel custodian tree at denx:

https://source.denx.de/u-boot/custodians/u-boot-atmel/-/tree/testing

Eugen

> 
> RomBOOT
> 
> U-Boot SPL 2021.04-00372-g90eba245a6-dirty (Apr 07 2021 - 10:05:18 +0100)
> Trying to boot from MMC1
> 
> U-Boot 2021.04-00372-g90eba245a6-dirty (Apr 07 2021 - 10:05:18 +0100)
> CPU: SAMA5D36
> Crystal frequency:   12 MHz
> .
> 
> 
> Thanks,
> Manuel
> 
> On Wed, 7 Apr 2021 at 07:32,  wrote:
>>
>> On 4/7/21 1:16 AM, Derald Woods wrote:
>>> On Tue, Apr 6, 2021 at 4:40 AM Manuel Reis >> > wrote:
>>>
>>>  in the early SPL boot stage whenever there is a call to udelay,
>>>  dm_timer_init fails to find the pit timer whenever it traverses
>>>  the device tree, if this property is not present
>>>
>>>  Signed-off-by: Manuel Reis >>  >
>>>  CC: Eugen Hristev >>  >
>>>  ---
>>>arch/arm/dts/sama5d3.dtsi | 1 +
>>>1 file changed, 1 insertion(+)
>>>
>>>  diff --git a/arch/arm/dts/sama5d3.dtsi b/arch/arm/dts/sama5d3.dtsi
>>>  index 6ed218eaad..42c30e9f30 100644
>>>  --- a/arch/arm/dts/sama5d3.dtsi
>>>  +++ b/arch/arm/dts/sama5d3.dtsi
>>>  @@ -1320,6 +1320,7 @@
>>>   reg = <0xfe30 0xf>;
>>>   interrupts = <3 IRQ_TYPE_LEVEL_HIGH 
>>> 5>;
>>>   clocks = <>;
>>>  +   u-boot,dm-pre-reloc;
>>>   };
>>>
>>>   watchdog@fe40 {
>>>  --
>>>  2.27.0
>>>
>>>
>>> This patch, on top of v2021.04, allows my SAMA5D3 Xplained board to boot
>>> normally again.
>>>
>>> Tested-by: Derald D. Woods >> >
>>>
>>
>> Hi Derald,
>>
>> Could I ask, you are using the SPL to boot your board ?
>> Did you have to remove any udelay from the ddr2_init code , or it booted
>> out of the box by applying this patch only ?
>>
>> Thanks,
>> Eugen

Re: [PATCH] arm64: dts: meson: fix PHY deassert timing requirements

[Neil Armstrong]

Hi,

On 06/04/2021 19:47, Stefan Agner wrote:
> The sync of the device tree and dt-bindings from Linux v5.6-rc2
> 11a48a5a18c6 ("Linux 5.6-rc2") causes Ethernet to break on some
> ODROID-C2.
> 
> Meanwhile a fix to increase the reset timing has been added to Linux.
> Instead of reverting the offending commit, use the new reset timing
> from upstream Linux commit c183c406c432 ("arm64: dts: meson: fix PHY
> deassert timing requirements").
> 
> Fixes: dd5f2351e99a ("arm64: dts: meson: sync dt and bindings from v5.6-rc2")
> Signed-off-by: Stefan Agner 
> ---
>  arch/arm/dts/meson-g12b-odroid-n2.dtsi | 2 +-
>  arch/arm/dts/meson-gxbb-nanopi-k2.dts  | 2 +-
>  arch/arm/dts/meson-gxbb-odroidc2.dts   | 2 +-
>  arch/arm/dts/meson-gxm-khadas-vim2.dts | 2 +-
>  4 files changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/arm/dts/meson-g12b-odroid-n2.dtsi 
> b/arch/arm/dts/meson-g12b-odroid-n2.dtsi
> index 6982632ae6..39a09661c5 100644
> --- a/arch/arm/dts/meson-g12b-odroid-n2.dtsi
> +++ b/arch/arm/dts/meson-g12b-odroid-n2.dtsi
> @@ -413,7 +413,7 @@
>   max-speed = <1000>;
>  
>   reset-assert-us = <1>;
> - reset-deassert-us = <3>;
> + reset-deassert-us = <8>;

In fact, these are not used by current U-boot, support for reset/deassert in 
PHY node
is not yet supported in U-Boot. This first step was to switch to DM_MDIO and 
use the
proper Designware glue, the second step is to find how to make use of these 
properties.

Concerning the patch, I'll prefer you sync the DT with v5.11 instead.

Neil

>   reset-gpios = < GPIOZ_15 (GPIO_ACTIVE_LOW | 
> GPIO_OPEN_DRAIN)>;
>  
>   interrupt-parent = <_intc>;
> diff --git a/arch/arm/dts/meson-gxbb-nanopi-k2.dts 
> b/arch/arm/dts/meson-gxbb-nanopi-k2.dts
> index 7be3e35409..de27beafe9 100644
> --- a/arch/arm/dts/meson-gxbb-nanopi-k2.dts
> +++ b/arch/arm/dts/meson-gxbb-nanopi-k2.dts
> @@ -165,7 +165,7 @@
>   reg = <0>;
>  
>   reset-assert-us = <1>;
> - reset-deassert-us = <3>;
> + reset-deassert-us = <8>;
>   reset-gpios = < GPIOZ_14 GPIO_ACTIVE_LOW>;
>  
>   interrupt-parent = <_intc>;
> diff --git a/arch/arm/dts/meson-gxbb-odroidc2.dts 
> b/arch/arm/dts/meson-gxbb-odroidc2.dts
> index 70fcfb7b06..50de1d01e5 100644
> --- a/arch/arm/dts/meson-gxbb-odroidc2.dts
> +++ b/arch/arm/dts/meson-gxbb-odroidc2.dts
> @@ -200,7 +200,7 @@
>   reg = <0>;
>  
>   reset-assert-us = <1>;
> - reset-deassert-us = <3>;
> + reset-deassert-us = <8>;
>   reset-gpios = < GPIOZ_14 GPIO_ACTIVE_LOW>;
>  
>   interrupt-parent = <_intc>;
> diff --git a/arch/arm/dts/meson-gxm-khadas-vim2.dts 
> b/arch/arm/dts/meson-gxm-khadas-vim2.dts
> index bff8ec2c1c..e38d9e50ca 100644
> --- a/arch/arm/dts/meson-gxm-khadas-vim2.dts
> +++ b/arch/arm/dts/meson-gxm-khadas-vim2.dts
> @@ -194,7 +194,7 @@
>   reg = <0>;
>  
>   reset-assert-us = <1>;
> - reset-deassert-us = <3>;
> + reset-deassert-us = <8>;
>   reset-gpios = < GPIOZ_14 GPIO_ACTIVE_LOW>;
>  
>   interrupt-parent = <_intc>;
> 

Re: [PATCH 1/2] clk: zynq: Add clock wizard driver

[Michal Simek]

On 4/7/21 11:05 AM, zhengxunli wrote:
> The Clocking Wizard IP supports clock circuits customized
> to your clocking requirements. The wizard support for
> dynamically reconfiguring the clocking primitives for
> Multiply, Divide, Phase Shift/Offset, or Duty Cycle.
> 
> Limited by uboot clk uclass without set_phase API, this
> patch only provides set_rate to modify the frequency and
> set 50% duty cycle by default.
> 
> Signed-off-by: zhengxunli 

Please use full name.

> ---
>  drivers/clk/Kconfig  |   7 ++
>  drivers/clk/Makefile |   1 +
>  drivers/clk/clk_wizard.c | 180 
> +++
>  3 files changed, 188 insertions(+)
>  create mode 100644 drivers/clk/clk_wizard.c
> 
> diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
> index 4aeaa0c..4ebeccc 100644
> --- a/drivers/clk/Kconfig
> +++ b/drivers/clk/Kconfig
> @@ -136,6 +136,13 @@ config CLK_ZYNQMP
> This clock driver adds support for clock realted settings for
> ZynqMP platform.
>  
> +config CLK_WIZARD

https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/staging/clocking-wizard/Kconfig?h=v5.12-rc6

Small alignment with kernel would be useful.
At least CLK_XLNX_CLKWZRD.


> + bool "Enable clock wizard driver support for zynq"
> + depends on CLK && ARCH_ZYNQ

Clocking wizard is standard PL based IP not just related to Zynq. It can
be used by Microblaze, ARM cores, etc. It means no need to have
dependency on ZYNQ here.

> + help
> +   This clock driver adds support for clock wizard setting for
> +   Zynq platform.

ditto

> +
>  config CLK_STM32MP1
>   bool "Enable RCC clock driver for STM32MP1"
>   depends on ARCH_STM32MP && CLK
> diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
> index 645709b..d8b878c 100644
> --- a/drivers/clk/Makefile
> +++ b/drivers/clk/Makefile
> @@ -43,6 +43,7 @@ obj-$(CONFIG_CLK_UNIPHIER) += uniphier/
>  obj-$(CONFIG_CLK_VEXPRESS_OSC) += clk_vexpress_osc.o
>  obj-$(CONFIG_CLK_ZYNQ) += clk_zynq.o
>  obj-$(CONFIG_CLK_ZYNQMP) += clk_zynqmp.o
> +obj-$(CONFIG_CLK_WIZARD) += clk_wizard.o
>  obj-$(CONFIG_ICS8N3QV01) += ics8n3qv01.o
>  obj-$(CONFIG_MACH_PIC32) += clk_pic32.o
>  obj-$(CONFIG_SANDBOX) += clk_sandbox.o
> diff --git a/drivers/clk/clk_wizard.c b/drivers/clk/clk_wizard.c
> new file mode 100644
> index 000..f5c2387
> --- /dev/null
> +++ b/drivers/clk/clk_wizard.c

name could be also aligned with kernel to have easier match with the kernel.

> @@ -0,0 +1,180 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Xilinx 'Clocking Wizard' driver
> + *
> + * Copyright (c) 2021 Macronix Inc.
> + *
> + * Author: Zhengxun Li 
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +#define SRR  0x0
> +
> +#define SR   0x4
> +#define SR_LOCKEDBIT(0)
> +
> +#define CCR(x)   (0x200 + ((x) * 4))
> +
> +#define FBOUT_CFGCCR(0)
> +#define FBOUT_DIV(x) (x)
> +#define FBOUT_GET_DIV(x) ((x) & GENMASK(7, 0))
> +#define FBOUT_MUL(x) ((x) << 8)
> +#define FBOUT_GET_MUL(x) (((x) & GENMASK(15, 8)) >> 8)
> +#define FBOUT_FRAC(x)((x) << 16)
> +#define FBOUT_GET_FRAC(x)(((x) & GENMASK(25, 16)) >> 16)
> +#define FBOUT_FRAC_ENBIT(26)
> +
> +#define FBOUT_PHASE  CCR(1)
> +
> +#define OUT_CFG(x)   CCR(2 + ((x) * 3))
> +#define OUT_DIV(x)   (x)
> +#define OUT_GET_DIV(x)   ((x) & GENMASK(7, 0))
> +#define OUT_FRAC(x)  ((x) << 8)
> +#define OUT_GET_FRAC(x)  (((x) & GENMASK(17, 8)) >> 8)
> +#define OUT_FRAC_EN  BIT(18)
> +
> +#define OUT_PHASE(x) CCR(3 + ((x) * 3))
> +#define OUT_DUTY(x)  CCR(4 + ((x) * 3))
> +
> +#define CTRL CCR(23)
> +#define CTRL_SEN BIT(2)
> +#define CTRL_SADDR   BIT(1)
> +#define CTRL_LOADBIT(0)
> +
> +/*

/** for kernel-doc as noted below.

> + *  MMCM Block Diagram
> + *
> + *  ++  +-+
> + * input ->| vco_clk_div_hw |->| vco_clk_mul_hw  |--+
> + * rate| (int divide)   |  | (frac multiply) |  |
> + *  ++  +-+  |
> + *   |
> + *   +VCO-rate---+
> + *   |
> + *   |  ++
> + *   +->| clkout[0]  |-> output0 rate
> + *   |  | (frac divide)  |
> + *   |  ++
> + *   |
> + *   |  ++
> + *   +->| clkout[1]  |-> output1 rate
> + *   |  | (int divide)   |
> + *   |  ++
> + *   |
> + * ...
> + *   |
> + *   |  ++
> + *   +->| clkout[1]  |-> output6 rate
> + *  | (int divide)   |
> + *  ++
> + *
> + * struct clkwzrd - Clock wizard private data structure
> + *
> + * @lock Lock pointer
> + * @base Memory base
> + * @vco_clk  

[PATCH 2/2] ARM: dts: at91: sama7g5: change pinctrl compatible to sama7g5

[Eugen Hristev]

Change the pinctrl compatible to sama7g5, the right one for this product.

Signed-off-by: Eugen Hristev 
---
 arch/arm/dts/sama7g5.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/dts/sama7g5.dtsi b/arch/arm/dts/sama7g5.dtsi
index 0cb6eaf5d0..b951aff43e 100644
--- a/arch/arm/dts/sama7g5.dtsi
+++ b/arch/arm/dts/sama7g5.dtsi
@@ -63,7 +63,7 @@
#size-cells = <1>;
 
pioA: pinctrl@e0014000 {
-   compatible = "atmel,sama5d2-gpio";
+   compatible = "microchip,sama7g5-gpio";
reg = <0xe0014000 0x800>;
gpio-controller;
#gpio-cells = <2>;
-- 
2.25.1

[PATCH 1/2] gpio: atmel_pio4: add support for sama7g5 pio4 version with 5 banks

[Eugen Hristev]

Add support for sama7g5 pinctrl variant, with 5 banks with a degraded
8 line only 5th bank.
Based on Linux Kernel implementation.

Signed-off-by: Eugen Hristev 
---
 drivers/gpio/atmel_pio4.c | 22 ++
 1 file changed, 22 insertions(+)

diff --git a/drivers/gpio/atmel_pio4.c b/drivers/gpio/atmel_pio4.c
index f615fce32e..bea609db9d 100644
--- a/drivers/gpio/atmel_pio4.c
+++ b/drivers/gpio/atmel_pio4.c
@@ -173,8 +173,15 @@ int atmel_pio4_get_pio_input(u32 port, u32 pin)
 
 #if CONFIG_IS_ENABLED(DM_GPIO)
 
+/**
+ * struct atmel_pioctrl_data - Atmel PIO controller (pinmux + gpio) data struct
+ * @nbanks: number of PIO banks
+ * @last_bank_count: number of lines in the last bank (can be less than
+ * the rest of the banks).
+ */
 struct atmel_pioctrl_data {
u32 nbanks;
+   u32 last_bank_count;
 };
 
 struct atmel_pio4_plat {
@@ -313,6 +320,12 @@ static int atmel_pio4_probe(struct udevice *dev)
  NULL);
uc_priv->gpio_count = nbanks * ATMEL_PIO_NPINS_PER_BANK;
 
+   /* if last bank has limited number of pins, adjust accordingly */
+   if (pioctrl_data->last_bank_count != ATMEL_PIO_NPINS_PER_BANK) {
+   uc_priv->gpio_count -= ATMEL_PIO_NPINS_PER_BANK;
+   uc_priv->gpio_count += pioctrl_data->last_bank_count;
+   }
+
return 0;
 }
 
@@ -322,12 +335,21 @@ static int atmel_pio4_probe(struct udevice *dev)
  */
 static const struct atmel_pioctrl_data atmel_sama5d2_pioctrl_data = {
.nbanks = 4,
+   .last_bank_count = ATMEL_PIO_NPINS_PER_BANK,
+};
+
+static const struct atmel_pioctrl_data microchip_sama7g5_pioctrl_data = {
+   .nbanks = 5,
+   .last_bank_count = 8, /* 5th bank has only 8 lines on sama7g5 */
 };
 
 static const struct udevice_id atmel_pio4_ids[] = {
{
.compatible = "atmel,sama5d2-gpio",
.data = (ulong)_sama5d2_pioctrl_data,
+   }, {
+   .compatible = "microchip,sama7g5-gpio",
+   .data = (ulong)_sama7g5_pioctrl_data,
},
{}
 };
-- 
2.25.1

[PATCH] clk: Fix typo in Zynq Kconfig symbol description

[Michal Simek]

Trivial typo fix.

Signed-off-by: Michal Simek 
---

 drivers/clk/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 4aeaa0cd589d..40a5a5dd8835 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -125,7 +125,7 @@ config CLK_ZYNQ
depends on CLK && ARCH_ZYNQ
default y
help
- This clock driver adds support for clock realted settings for
+ This clock driver adds support for clock related settings for
  Zynq platform.
 
 config CLK_ZYNQMP
-- 
2.31.0

Re: [PATCH 2/2] board: Add Zynq Mxic picozed development board support

[Michal Simek]

Hi,

On 4/7/21 11:05 AM, zhengxunli wrote:
> Add the Zynq Mxic picozed development board support.
> 
> Signed-off-by: zhengxunli 
> ---
>  arch/arm/dts/Makefile  |  3 +-
>  arch/arm/dts/zynq-mxic-picozed.dts | 66 
> ++
>  2 files changed, 68 insertions(+), 1 deletion(-)
>  create mode 100644 arch/arm/dts/zynq-mxic-picozed.dts
> 
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> index 9a8de46..059bb3b 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -286,7 +286,8 @@ dtb-$(CONFIG_ARCH_ZYNQ) += \
>   zynq-zturn.dtb \
>   zynq-zturn-v5.dtb \
>   zynq-zybo.dtb \
> - zynq-zybo-z7.dtb
> + zynq-zybo-z7.dtb \
> + zynq-mxic-picozed.dtb
>  dtb-$(CONFIG_ARCH_ZYNQMP) += \
>   avnet-ultra96-rev1.dtb  \
>   avnet-ultrazedev-cc-v1.0-ultrazedev-som-v1.0.dtb\
> diff --git a/arch/arm/dts/zynq-mxic-picozed.dts 
> b/arch/arm/dts/zynq-mxic-picozed.dts
> new file mode 100644
> index 000..d2ff358
> --- /dev/null
> +++ b/arch/arm/dts/zynq-mxic-picozed.dts
> @@ -0,0 +1,66 @@
> +/dts-v1/;
> +/include/ "zynq-7000.dtsi"
> +
> +/ {
> + model = "Zynq MXIC PicoZed Development Board";
> + compatible = "mxicy,zynq-mxic-picozed", "xlnx,zynq-7000";
> +
> + aliases {
> + ethernet0 = 
> + serial0 = 
> + spi0 = _controller;
> + };
> +
> + memory@0 {
> + device_type = "memory";
> + reg = <0x0 0x3000>;
> + };
> +
> + chosen {
> + bootargs = "";
> + stdout-path = "serial0:115200n8";
> + };
> +};
> +
> + {
> + clkwizard: clkwizard@43c2 {
> + compatible = "xlnx,clk-wizard-5.1";
> + reg = <0x43c2 0x1>;
> + clocks = < 18>, < 18>;
> + clock-names = "aclk", "clk_in1";
> + #clock-cells = <1>;
> + clock-frequency = <13330>;
> + xlnx,clk-wizard-num-outputs = <2>;
> + };

This is definitely PL IP.

> +
> + spi_controller: spi@43c3 {
> + compatible = "mxicy,mx25f0a-spi";


And I expect this is also PL based IP.
And we have agreement that for upstream project we won't be accepting
any description for PL.
But there is not a problem with accepting driver for clocking wizard or
this IP.

And picozed board is already supported in u-boot.

Thanks,
Michal

[PATCH] toradex: configblock: fix module revision in config block

[denys . drozdov]

From: Denys Drozdov 

U-boot might display wrong module revision information
for modules with an assembly version 'K'. "cfgblock create"
does not takes into account all revision digits from PID8.

This fix takes into account all digits of PID8
to store module revision.

Signed-off-by: Denys Drozdov 
---
 board/toradex/common/tdx-cfg-block.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/board/toradex/common/tdx-cfg-block.c 
b/board/toradex/common/tdx-cfg-block.c
index adab0a0802..9be58d538b 100644
--- a/board/toradex/common/tdx-cfg-block.c
+++ b/board/toradex/common/tdx-cfg-block.c
@@ -555,6 +555,8 @@ static int get_cfgblock_interactive(void)
 static int get_cfgblock_barcode(char *barcode, struct toradex_hw *tag,
u32 *serial)
 {
+   char revision[3] = {barcode[6], barcode[7], '\0'};
+
if (strlen(barcode) < 16) {
printf("Argument too short, barcode is 16 chars long\n");
return -1;
@@ -563,7 +565,7 @@ static int get_cfgblock_barcode(char *barcode, struct 
toradex_hw *tag,
/* Get hardware information from the first 8 digits */
tag->ver_major = barcode[4] - '0';
tag->ver_minor = barcode[5] - '0';
-   tag->ver_assembly = barcode[7] - '0';
+   tag->ver_assembly = simple_strtoul(revision, NULL, 10);
 
barcode[4] = '\0';
tag->prodid = simple_strtoul(barcode, NULL, 10);
-- 
2.17.1

Re: [PULL] please pull mmc-2021-4-6

[Tom Rini]

On Wed, Apr 07, 2021 at 01:31:32AM +, Peng Fan wrote:

> Hi Tom,
> 
> Please pull mmc-2021-4-6
> 
> CI: https://source.denx.de/u-boot/custodians/u-boot-mmc/-/pipelines/7022
> 

Applied to u-boot/master, thanks!

-- 
Tom


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Description: PGP signature

Re: [PULL] u-boot-usb/master

[Tom Rini]

On Tue, Apr 06, 2021 at 08:09:01PM +0200, Marek Vasut wrote:

> The following changes since commit 472fd5a35af3308f97de0376a6c25f5368035557:
> 
>   Merge tag 'rockchip-for-v2021.07' of
> https://source.denx.de/u-boot/custodians/u-boot-rockchip (2021-04-05
> 22:39:10 -0400)
> 
> are available in the Git repository at:
> 
>   git://source.denx.de/u-boot-usb.git master
> 
> for you to fetch changes up to 82e4e198ed7afd5103f728dd21bff80ecfe8dd72:
> 
>   usb: xhci: Make debug output better readable and checkpatch clean
> (2021-04-06 16:38:58 +0200)
> 

Applied to u-boot/master, thanks!

-- 
Tom


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Re: [PATCH v2 0/5] board: imx8mm: Add Engicam i.Core MX8M Mini SoM

[Jagan Teki]

Hi Stefano,

On Mon, Mar 15, 2021 at 11:16 PM Jagan Teki  wrote:
>
> Patch series for Engicam i.Core MX8M Mini SOM and it's associated
> carrier board dts(i) support.
>
> patch 1-2: add imx8mm-u-boot.dtsi, header improvement code
>
> patch 3: Engicam i.Core MX8M Mini SoM dts
>
> patch 4-5: EDIMM2.2, C.TOUCH 2.0 Carrier boards
>
> Changes for v2:
> - add Linux commit sha1 in commit messages.
>
> Any inputs?
> Jagan.
>
> Jagan Teki (5):
>   arm64: dts: imx8mm: Add common -u-boot.dtsi
>   configs: Add imx8mm-common header
>   arm64: dts: imx8mm: Add Engicam i.Core MX8M Mini SoM
>   board: imx8mm: Add Engicam i.Core MX8M Mini EDIMM2.2 Starter Kit
>   board: imx8mm: Add Engicam i.Core MX8M Mini C.TOUCH 2.0

Any comments?

Jagan.

[PATCH 4/5] efi_capsule: Add a weak function to get the public key needed for capsule authentication

[Sughosh Ganu]

Define a weak function which would be used in the scenario where the
public key is stored on the platform's dtb. This dtb is concatenated
with the u-boot binary during the build process. Platforms which have
a different mechanism for getting the public key would define their
own platform specific function.

Signed-off-by: Sughosh Ganu 
---
 lib/efi_loader/efi_capsule.c | 38 
 1 file changed, 34 insertions(+), 4 deletions(-)

diff --git a/lib/efi_loader/efi_capsule.c b/lib/efi_loader/efi_capsule.c
index 1423b675c8..fc5e1c0856 100644
--- a/lib/efi_loader/efi_capsule.c
+++ b/lib/efi_loader/efi_capsule.c
@@ -14,10 +14,13 @@
 #include 
 #include 
 
+#include 
 #include 
 #include 
 #include 
 
+DECLARE_GLOBAL_DATA_PTR;
+
 const efi_guid_t efi_guid_capsule_report = EFI_CAPSULE_REPORT_GUID;
 static const efi_guid_t efi_guid_firmware_management_capsule_id =
EFI_FIRMWARE_MANAGEMENT_CAPSULE_ID_GUID;
@@ -210,11 +213,38 @@ const efi_guid_t efi_guid_capsule_root_cert_guid =
 
 __weak int efi_get_public_key_data(void **pkey, efi_uintn_t *pkey_len)
 {
-   /* The platform is supposed to provide
-* a method for getting the public key
-* stored in the form of efi signature
-* list
+   /*
+* This is a function for retrieving the public key from the
+* platform's device tree. The platform's device tree has been
+* concatenated with the u-boot binary.
+* If a platform has a different mechanism to get the public
+* key, it can define it's own function.
 */
+   const void *fdt_blob = gd->fdt_blob;
+   const void *blob;
+   const char *cnode_name = "capsule-key";
+   const char *snode_name = "signature";
+   int sig_node;
+   int len;
+
+   sig_node = fdt_subnode_offset(fdt_blob, 0, snode_name);
+   if (sig_node < 0) {
+   EFI_PRINT("Unable to get signature node offset\n");
+   return -FDT_ERR_NOTFOUND;
+   }
+
+   blob = fdt_getprop(fdt_blob, sig_node, cnode_name, );
+
+   if (!blob || len < 0) {
+   EFI_PRINT("Unable to get capsule-key value\n");
+   *pkey = NULL;
+   *pkey_len = 0;
+   return -FDT_ERR_NOTFOUND;
+   }
+
+   *pkey = (void *)blob;
+   *pkey_len = len;
+
return 0;
 }
 
-- 
2.17.1

[PATCH 5/5] Makefile: Add provision for embedding public key in platform's dtb

[Sughosh Ganu]

Add provision for embedding the public key used for capsule
authentication in the platform's dtb. This is done by invoking the
mkeficapsule utility which puts the public key in the efi signature
list(esl) format into the dtb.

Signed-off-by: Sughosh Ganu 
---
 Makefile | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/Makefile b/Makefile
index 193aa4d1c9..0d50c6a805 100644
--- a/Makefile
+++ b/Makefile
@@ -1010,6 +1010,10 @@ cmd_pad_cat = $(cmd_objcopy) && $(append) || { rm -f $@; 
false; }
 quiet_cmd_lzma = LZMA$@
 cmd_lzma = lzma -c -z -k -9 $< > $@
 
+quiet_cmd_mkeficapsule = MKEFICAPSULE $@
+cmd_mkeficapsule = $(objtree)/tools/mkeficapsule -K $(CONFIG_EFI_PKEY_FILE) \
+   -D $@
+
 cfg: u-boot.cfg
 
 quiet_cmd_cfgcheck = CFGCHK  $2
@@ -1104,8 +1108,14 @@ endif
 PHONY += dtbs
 dtbs: dts/dt.dtb
@:
+ifeq ($(CONFIG_EFI_CAPSULE_AUTHENTICATE)$(CONFIG_EFI_PKEY_DTB_EMBED),yy)
+dts/dt.dtb: u-boot tools
+   $(Q)$(MAKE) $(build)=dts dtbs
+   $(call cmd,mkeficapsule)
+else
 dts/dt.dtb: u-boot
$(Q)$(MAKE) $(build)=dts dtbs
+endif
 
 quiet_cmd_copy = COPY$@
   cmd_copy = cp $< $@
-- 
2.17.1

[PATCH 3/5] efi_capsule: Add a weak function to check whether capsule authentication is enabled

[Sughosh Ganu]

Define a weak function which checks if the environment variable
capsule_authentication_enabled has been set, for enabling capsule
authentication. Other platforms might have a different mechanism to
determine this, and would then define their own platform specific
function.

Signed-off-by: Sughosh Ganu 
---
 board/emulation/common/qemu_capsule.c | 6 --
 lib/efi_loader/efi_capsule.c  | 6 ++
 2 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/board/emulation/common/qemu_capsule.c 
b/board/emulation/common/qemu_capsule.c
index 5cb461d52b..6b8a87022a 100644
--- a/board/emulation/common/qemu_capsule.c
+++ b/board/emulation/common/qemu_capsule.c
@@ -41,9 +41,3 @@ int efi_get_public_key_data(void **pkey, efi_uintn_t 
*pkey_len)
 
return 0;
 }
-
-bool efi_capsule_auth_enabled(void)
-{
-   return env_get("capsule_authentication_enabled") != NULL ?
-   true : false;
-}
diff --git a/lib/efi_loader/efi_capsule.c b/lib/efi_loader/efi_capsule.c
index 0cfff0daf7..1423b675c8 100644
--- a/lib/efi_loader/efi_capsule.c
+++ b/lib/efi_loader/efi_capsule.c
@@ -218,6 +218,12 @@ __weak int efi_get_public_key_data(void **pkey, 
efi_uintn_t *pkey_len)
return 0;
 }
 
+__weak bool efi_capsule_auth_enabled(void)
+{
+   return env_get("capsule_authentication_enabled") ?
+   true : false;
+}
+
 efi_status_t efi_capsule_authenticate(const void *capsule, efi_uintn_t 
capsule_size,
  void **image, efi_uintn_t *image_size)
 {
-- 
2.17.1

[PATCH 2/5] efi_loader: Kconfig: Add symbols for embedding the public key into the platform's dtb

[Sughosh Ganu]

Add config options EFI_PKEY_DTB_EMBED and EFI_PKEY_FILE which are to
be used for embedding the public key to be used for capsule
authentication into the platform's device tree.

The embedding of the public key would take place during the platform
build process.

Signed-off-by: Sughosh Ganu 
---
 lib/efi_loader/Kconfig | 15 +++
 1 file changed, 15 insertions(+)

diff --git a/lib/efi_loader/Kconfig b/lib/efi_loader/Kconfig
index 0b99d7c774..de3083a979 100644
--- a/lib/efi_loader/Kconfig
+++ b/lib/efi_loader/Kconfig
@@ -179,6 +179,21 @@ config EFI_CAPSULE_AUTHENTICATE
  Select this option if you want to enable capsule
  authentication
 
+config EFI_PKEY_DTB_EMBED
+   bool "Embed the public key in the Device Tree"
+   default n
+   depends on EFI_CAPSULE_AUTHENTICATE
+   help
+ Select this option if the public key used for capsule
+ authentication is to be embedded into the platform's
+ device tree.
+
+config EFI_PKEY_FILE
+   string "Public Key esl file to be embedded into the Device Tree"
+   help
+ Specify the absolute path of the public key esl file that is
+ to be embedded in the platform's device tree.
+
 config EFI_CAPSULE_FIRMWARE_FIT
bool "FMP driver for FIT image"
depends on EFI_CAPSULE_FIRMWARE_MANAGEMENT
-- 
2.17.1

[PATCH 1/5] efi_loader: Kconfig: Select IMAGE_SIGN_INFO when capsule authentication is enabled

[Sughosh Ganu]

Enable building of the crypto helper functions used during capsule
authentication by selecting IMAGE_SIGN_INFO.

Signed-off-by: Sughosh Ganu 
---

This was not detected when support for capsule auth was added to the
qemu arm64 platform. This is because the platform includes
CONFIG_FIT_SIGNATURE which selects IMAGE_SIGN_INFO.


 lib/efi_loader/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/lib/efi_loader/Kconfig b/lib/efi_loader/Kconfig
index e44f004f3f..0b99d7c774 100644
--- a/lib/efi_loader/Kconfig
+++ b/lib/efi_loader/Kconfig
@@ -173,6 +173,7 @@ config EFI_CAPSULE_AUTHENTICATE
select X509_CERTIFICATE_PARSER
select PKCS7_MESSAGE_PARSER
select PKCS7_VERIFY
+   select IMAGE_SIGN_INFO
default n
help
  Select this option if you want to enable capsule
-- 
2.17.1

[PATCH 0/5] Add support for embedding public key in platform's dtb

[Sughosh Ganu]

Patch 1 fixes an issue of selection of IMAGE_SIGN_INFO config option
when capsule authentication is enabled.

Patch 2 add two config symbols, EFI_PKEY_DTB_EMBED and EFI_PKEY_FILE
which are used for enabling embedding of the public key in the dtb,
and specifying the esl file name.

Patch 3 moves efi_capsule_auth_enabled as a weak function, which can
be used as a default mechanism for checking if capsule authentication
has been enabled.

Patch 4 adds a default weak function for retrieving the public key
from the platform's dtb.

Patch 5 adds the functionality to embed the esl file into the
platform's dtb during the platform build.

I have tested this functionality on the STM32MP157C DK2 board.

[1] - https://lists.denx.de/pipermail/u-boot/2021-March/442867.html 

Sughosh Ganu (5):
  efi_loader: Kconfig: Select IMAGE_SIGN_INFO when capsule
authentication is enabled
  efi_loader: Kconfig: Add symbols for embedding the public key into the
platform's dtb
  efi_capsule: Add a weak function to check whether capsule
authentication is enabled
  efi_capsule: Add a weak function to get the public key needed for
capsule authentication
  Makefile: Add provision for embedding public key in platform's dtb

 Makefile  | 10 ++
 board/emulation/common/qemu_capsule.c |  6 
 lib/efi_loader/Kconfig| 16 ++
 lib/efi_loader/efi_capsule.c  | 44 ---
 4 files changed, 66 insertions(+), 10 deletions(-)

-- 
2.17.1

[PATCH 2/2] board: Add Zynq Mxic picozed development board support

[zhengxunli]

Add the Zynq Mxic picozed development board support.

Signed-off-by: zhengxunli 
---
 arch/arm/dts/Makefile  |  3 +-
 arch/arm/dts/zynq-mxic-picozed.dts | 66 ++
 2 files changed, 68 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/dts/zynq-mxic-picozed.dts

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 9a8de46..059bb3b 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -286,7 +286,8 @@ dtb-$(CONFIG_ARCH_ZYNQ) += \
zynq-zturn.dtb \
zynq-zturn-v5.dtb \
zynq-zybo.dtb \
-   zynq-zybo-z7.dtb
+   zynq-zybo-z7.dtb \
+   zynq-mxic-picozed.dtb
 dtb-$(CONFIG_ARCH_ZYNQMP) += \
avnet-ultra96-rev1.dtb  \
avnet-ultrazedev-cc-v1.0-ultrazedev-som-v1.0.dtb\
diff --git a/arch/arm/dts/zynq-mxic-picozed.dts 
b/arch/arm/dts/zynq-mxic-picozed.dts
new file mode 100644
index 000..d2ff358
--- /dev/null
+++ b/arch/arm/dts/zynq-mxic-picozed.dts
@@ -0,0 +1,66 @@
+/dts-v1/;
+/include/ "zynq-7000.dtsi"
+
+/ {
+   model = "Zynq MXIC PicoZed Development Board";
+   compatible = "mxicy,zynq-mxic-picozed", "xlnx,zynq-7000";
+
+   aliases {
+   ethernet0 = 
+   serial0 = 
+   spi0 = _controller;
+   };
+
+   memory@0 {
+   device_type = "memory";
+   reg = <0x0 0x3000>;
+   };
+
+   chosen {
+   bootargs = "";
+   stdout-path = "serial0:115200n8";
+   };
+};
+
+ {
+   clkwizard: clkwizard@43c2 {
+   compatible = "xlnx,clk-wizard-5.1";
+   reg = <0x43c2 0x1>;
+   clocks = < 18>, < 18>;
+   clock-names = "aclk", "clk_in1";
+   #clock-cells = <1>;
+   clock-frequency = <13330>;
+   xlnx,clk-wizard-num-outputs = <2>;
+   };
+
+   spi_controller: spi@43c3 {
+   compatible = "mxicy,mx25f0a-spi";
+   reg = <0x43c3 0x1>;
+   reg-names = "regs";
+   clocks = < 0>, < 1>, < 18>;
+   clock-names = "send_clk", "send_dly_clk", "ps_clk";
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   flash@0 {
+   compatible = "jedec,spi-nor";
+   reg = <0>;
+   spi-max-frequency = <2500>;
+   spi-tx-bus-width = <1>;
+   spi-rx-bus-width = <1>;
+   };
+   };
+};
+
+ {
+   ps-clk-frequency = <>;
+};
+
+ {
+   status = "okay";
+   phy-mode = "rgmii-id";
+};
+
+ {
+   status = "okay";
+};
-- 
1.9.1