Re: [PATCH v3 1/2] efi_loader: expose efi_image_parse() even if UEFI Secure Boot is disabled
Hi Heinrich,
I'm about to send v4 patch series.
> 1) keep if (!IS_ENABLED(CONFIG_EFI_SECURE_BOOT)) condition
I chose this option, but I reverted #ifdef statement instead of using
"if (IS_ENABLED)" because I think it is better not to rely on compiler
optimization.
> 2) remove if (!IS_ENABLED(CONFIG_EFI_SECURE_BOOT)) condition and
> always include efi_signature.c as compilation target.
In this option, CONFIG_PKCS7_VERIFY is required for EFI_TCG2_PROTOCOL
just for successful build.
To minimize dependency, I did not proceed with 2).
Please kindly review v4.
Thanks,
Masahisa
On Tue, 11 May 2021 at 07:06, Masahisa Kojima
wrote:
>
> On Mon, 10 May 2021 at 11:07, Takahiro Akashi
> wrote:
> >
> > On Mon, May 10, 2021 at 09:49:03AM +0900, Masahisa Kojima wrote:
> > > Hi Heinrich,
> > >
> > > Sorry for the late reply.
> > >
> > > On Sat, 8 May 2021 at 23:08, Heinrich Schuchardt
> > > wrote:
> > > >
> > > > On 4/28/21 3:16 PM, Heinrich Schuchardt wrote:
> > > > > On 28.04.21 14:19, Masahisa Kojima wrote:
> > > >
> > > > >> /**
> > > > >>* cmp_pe_section() - compare virtual addresses of two PE image
> > > > >> sections
> > > > >>* @arg1: pointer to pointer to first section header
> > > > >> @@ -504,6 +565,9 @@ static bool efi_image_authenticate(void *efi,
> > > > >> size_t efi_size)
> > > > >>
> > > > >> EFI_PRINT("%s: Enter, %d\n", __func__, ret);
> > > > >>
> > > > >> +if (!IS_ENABLED(CONFIG_EFI_SECURE_BOOT))
> > > > >> +return true;
> > > > >> +
> > > > >
> > > > > Why is this needed? Doesn't efi_secure_boot_enabled() return false in
> > > > > this case?
> > >
> > > The original code is as follows.
> >
> > Heinrich's concern was, I guess, that
> >
> > > > >> +if (!IS_ENABLED(CONFIG_EFI_SECURE_BOOT))
> > > > >> +return true;
> >
> > and the succeeding check,
> >
> > if (!efi_secure_boot_enabled())
> > return true;
> >
> > are somehow redundant.
> > But in the latter case, I'm afraid that a compiler cannot optimize out
> > the rest of the logic in efi_image_authenticate().
>
> Hi Heinrich, Takahiro,
>
> Sorry for the late reply.
> I now understand Takahiro's concern.
> If I remove following check,
>
> > +if (!IS_ENABLED(CONFIG_EFI_SECURE_BOOT))
> > +return true;
>
> compiler optimization does not work and link error occurs.
>
> lib/built-in.o: In function `efi_image_authenticate':
> /home/ubuntu/SynQuacer/ledge/u-boot/lib/efi_loader/efi_image_loader.c:601:
> undefined reference to `efi_sigstore_parse_sigdb'
> /home/ubuntu/SynQuacer/ledge/u-boot/lib/efi_loader/efi_image_loader.c:607:
> undefined reference to `efi_sigstore_parse_sigdb'
> /home/ubuntu/SynQuacer/ledge/u-boot/lib/efi_loader/efi_image_loader.c:613:
> undefined reference to `efi_signature_lookup_digest'
>
> I would like to propose two resolution.
>
> 1) keep if (!IS_ENABLED(CONFIG_EFI_SECURE_BOOT)) condition
> 2) remove if (!IS_ENABLED(CONFIG_EFI_SECURE_BOOT)) condition and
> always include efi_signature.c as compilation target.
>
> Please advise.
>
> Thanks,
> Masahisa
>
>
> >
> > -Takahiro Akashi
> >
> >
> > > #ifdef CONFIG_EFI_SECURE_BOOT
> > > static bool efi_image_authenticate(void *efi, size_t efi_size) {
> > >
> > > < snip >
> > >
> > > }
> > > #else
> > > static bool efi_image_authenticate(void *efi, size_t efi_size)
> > > {
> > >return true;
> > > }
> > > #endif /* CONFIG_EFI_SECURE_BOOT */
> > >
> > > The purpose of this commit is removing #if compilation switch,
> > > so I keep the original implementation, always return true
> > > if CONFIG_EFI_SECURE_BOOT is disabled.
> > >
> > > Thanks,
> > > Masahisa
> > >
> > > >
> > > > Hello Masahisa,
> > > >
> > > > I did not see any reply yet. Was a mail lost?
> > > >
> > > > Best regards
> > > >
> > > > Heinrich
Re: [PATCH] Revert "riscv: cpu: fu740: clear feature disable CSR"
On Mon, May 10, 2021 at 05:08:16PM +0800, Bin Meng wrote:
> This reverts commit bc8bbb77f74f21582b3bfd790334397757f88575.
>
> This commit breaks U-Boot booting on SiFive Unleashed board, as
> there is no such CSR on U54 core.
>
> Signed-off-by: Bin Meng
> ---
>
> arch/riscv/cpu/fu540/spl.c | 15 ---
> 1 file changed, 15 deletions(-)
>
> diff --git a/arch/riscv/cpu/fu540/spl.c b/arch/riscv/cpu/fu540/spl.c
> index 1740ef98b6..45657b7909 100644
> --- a/arch/riscv/cpu/fu540/spl.c
> +++ b/arch/riscv/cpu/fu540/spl.c
> @@ -6,9 +6,6 @@
>
> #include
> #include
> -#include
> -
> -#define CSR_U74_FEATURE_DISABLE 0x7c1
>
> int spl_soc_init(void)
> {
> @@ -24,15 +21,3 @@ int spl_soc_init(void)
>
> return 0;
> }
> -
> -void harts_early_init(void)
> -{
> - /*
> - * Feature Disable CSR
> - *
> - * Clear feature disable CSR to '0' to turn on all features for
> - * each core. This operation must be in M-mode.
> - */
> - if (CONFIG_IS_ENABLED(RISCV_MMODE))
> - csr_write(CSR_U74_FEATURE_DISABLE, 0);
> -}
> --
> 2.25.1
>
Reviewed-by: Leo Yu-Chi Liang
Re: [PATCH 5/7] ARM: dts: k3: Add cfg register space for ringacc and udmap
On 12/05/21 11:50 am, Vignesh Raghavendra wrote: > > > On 5/12/21 11:40 AM, Lokesh Vutla wrote: >> >> >> On 11/05/21 11:34 am, Vignesh Raghavendra wrote: >>> >>> >>> On 5/11/21 10:21 AM, Lokesh Vutla wrote: On 10/05/21 10:54 pm, Vignesh Raghavendra wrote: > R5 SPL needs access to cfg space of Rings and UDMAP, therefore add RING > CFG, TCHAN CFG and RCHAN CFG address ranges. > > Signed-off-by: Vignesh Raghavendra > --- > arch/arm/dts/k3-am654-base-board-u-boot.dtsi | 14 ++ > .../k3-j7200-common-proc-board-u-boot.dtsi| 26 +++ > .../k3-j721e-common-proc-board-u-boot.dtsi| 14 ++ If these are specific to R5, then it should be moved to R5 dts no? -u-boot.dtsi will be applied to A53 dts as well. >>> >>> Not really.. There registers are present within respective IPs. A53/A72 >>> use DM APIs to configure these registers whereas R5 does direct >>> programming. I intend to add these ranges to kernel DT as well. Until >>> then, will be in -u-boot.dtsi. >>> >> >> You intend to add mcu-navss ringacc to kernel dts as well. I am fine with >> this. > > MCU RINGACC node itself is present in kernel dts, its just cfg register > ranges that are not populated. okay, please mention this intention in commit description. It says needed only for R5 but code is in u-boot.dtsi with the intention of being added in kernel dts. It is confusing. Thanks and regards, Lokesh
Re: [PATCH 5/7] ARM: dts: k3: Add cfg register space for ringacc and udmap
On 5/12/21 11:40 AM, Lokesh Vutla wrote:
>
>
> On 11/05/21 11:34 am, Vignesh Raghavendra wrote:
>>
>>
>> On 5/11/21 10:21 AM, Lokesh Vutla wrote:
>>>
>>>
>>> On 10/05/21 10:54 pm, Vignesh Raghavendra wrote:
R5 SPL needs access to cfg space of Rings and UDMAP, therefore add RING
CFG, TCHAN CFG and RCHAN CFG address ranges.
Signed-off-by: Vignesh Raghavendra
---
arch/arm/dts/k3-am654-base-board-u-boot.dtsi | 14 ++
.../k3-j7200-common-proc-board-u-boot.dtsi| 26 +++
.../k3-j721e-common-proc-board-u-boot.dtsi| 14 ++
>>>
>>> If these are specific to R5, then it should be moved to R5 dts no?
>>> -u-boot.dtsi
>>> will be applied to A53 dts as well.
>>>
>>
>> Not really.. There registers are present within respective IPs. A53/A72
>> use DM APIs to configure these registers whereas R5 does direct
>> programming. I intend to add these ranges to kernel DT as well. Until
>> then, will be in -u-boot.dtsi.
>>
>
> You intend to add mcu-navss ringacc to kernel dts as well. I am fine with
> this.
MCU RINGACC node itself is present in kernel dts, its just cfg register
ranges that are not populated.
> But please remember to update u-boot dts once you update kernel dts
>
Sure will do...
Regards
Vignesh
> Thanks and regards,
> Lokesh
>
>>> Thanks and regards,
>>> Lokesh
>>>
3 files changed, 54 insertions(+)
diff --git a/arch/arm/dts/k3-am654-base-board-u-boot.dtsi
b/arch/arm/dts/k3-am654-base-board-u-boot.dtsi
index b0602d1dad..2840258518 100644
--- a/arch/arm/dts/k3-am654-base-board-u-boot.dtsi
+++ b/arch/arm/dts/k3-am654-base-board-u-boot.dtsi
@@ -35,11 +35,25 @@
u-boot,dm-spl;
ringacc@2b80 {
+ reg = <0x0 0x2b80 0x0 0x40>,
+ <0x0 0x2b00 0x0 0x40>,
+ <0x0 0x2859 0x0 0x100>,
+ <0x0 0x2a50 0x0 0x4>,
+ <0x0 0x2844 0x0 0x4>;
+ reg-names = "rt", "fifos", "proxy_gcfg",
"proxy_target", "cfg";
u-boot,dm-spl;
ti,dma-ring-reset-quirk;
};
dma-controller@285c {
+ reg = <0x0 0x285c 0x0 0x100>,
+ <0x0 0x284c 0x0 0x4000>,
+ <0x0 0x2a80 0x0 0x4>,
+ <0x0 0x284a 0x0 0x4000>,
+ <0x0 0x2aa0 0x0 0x4>,
+ <0x0 0x2840 0x0 0x2000>;
+ reg-names = "gcfg", "rchan", "rchanrt", "tchan",
+ "tchanrt", "rflow";
u-boot,dm-spl;
};
};
diff --git a/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi
b/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi
index c3aae65b39..41ce9fcb59 100644
--- a/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi
+++ b/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi
@@ -40,6 +40,32 @@
chipid@4314 {
u-boot,dm-spl;
};
+
+ mcu-navss{
+ u-boot,dm-spl;
+
+ ringacc@2b80 {
+ reg = <0x0 0x2b80 0x0 0x40>,
+ <0x0 0x2b00 0x0 0x40>,
+ <0x0 0x2859 0x0 0x100>,
+ <0x0 0x2a50 0x0 0x4>,
+ <0x0 0x2844 0x0 0x4>;
+ reg-names = "rt", "fifos", "proxy_gcfg",
"proxy_target", "cfg";
+ u-boot,dm-spl;
+ };
+
+ dma-controller@285c {
+ reg = <0x0 0x285c 0x0 0x100>,
+ <0x0 0x284c 0x0 0x4000>,
+ <0x0 0x2a80 0x0 0x4>,
+ <0x0 0x284a 0x0 0x4000>,
+ <0x0 0x2aa0 0x0 0x4>,
+ <0x0 0x2840 0x0 0x2000>;
+ reg-names = "gcfg", "rchan", "rchanrt", "tchan",
+ "tchanrt", "rflow";
+ u-boot,dm-spl;
+ };
+ };
};
&secure_proxy_main {
diff --git a/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi
b/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi
index 1135de5a92..ed64f2720d 100644
--- a/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi
+++ b/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi
@@ -54,10 +54,24 @@
u-boot,dm-spl;
ringacc@2b80 {
+ reg = <0x0 0x2b80 0x0 0x40>,
+
Re: [PATCH v8 1/7] riscv: cpu: fu740: Add support for cpu fu740
Hi Green, This patch series seems to have failed CI test. Could you please check the CI result ? Thanks! https://dev.azure.com/ycliang-tw/u-boot-riscv/_build/results?buildId=28&view=results Best regards, Leo On Fri, May 07, 2021 at 10:36:47AM -0700, Green Wan wrote: > Add SiFive fu740 cpu to support RISC-V arch > > Signed-off-by: Green Wan > Reviewed-by: Bin Meng > --- > arch/riscv/Kconfig| 1 + > arch/riscv/cpu/fu740/Kconfig | 37 +++ > arch/riscv/cpu/fu740/Makefile | 12 + > arch/riscv/cpu/fu740/cache.c | 55 +++ > arch/riscv/cpu/fu740/cpu.c| 22 + > arch/riscv/cpu/fu740/dram.c | 38 > arch/riscv/cpu/fu740/spl.c| 23 ++ > arch/riscv/include/asm/arch-fu740/cache.h | 14 ++ > arch/riscv/include/asm/arch-fu740/clk.h | 14 ++ > arch/riscv/include/asm/arch-fu740/gpio.h | 38 > arch/riscv/include/asm/arch-fu740/reset.h | 13 ++ > arch/riscv/include/asm/arch-fu740/spl.h | 14 ++ > 12 files changed, 281 insertions(+) > create mode 100644 arch/riscv/cpu/fu740/Kconfig > create mode 100644 arch/riscv/cpu/fu740/Makefile > create mode 100644 arch/riscv/cpu/fu740/cache.c > create mode 100644 arch/riscv/cpu/fu740/cpu.c > create mode 100644 arch/riscv/cpu/fu740/dram.c > create mode 100644 arch/riscv/cpu/fu740/spl.c > create mode 100644 arch/riscv/include/asm/arch-fu740/cache.h > create mode 100644 arch/riscv/include/asm/arch-fu740/clk.h > create mode 100644 arch/riscv/include/asm/arch-fu740/gpio.h > create mode 100644 arch/riscv/include/asm/arch-fu740/reset.h > create mode 100644 arch/riscv/include/asm/arch-fu740/spl.h
Re: [PATCH 5/7] ARM: dts: k3: Add cfg register space for ringacc and udmap
On 11/05/21 11:34 am, Vignesh Raghavendra wrote:
>
>
> On 5/11/21 10:21 AM, Lokesh Vutla wrote:
>>
>>
>> On 10/05/21 10:54 pm, Vignesh Raghavendra wrote:
>>> R5 SPL needs access to cfg space of Rings and UDMAP, therefore add RING
>>> CFG, TCHAN CFG and RCHAN CFG address ranges.
>>>
>>> Signed-off-by: Vignesh Raghavendra
>>> ---
>>> arch/arm/dts/k3-am654-base-board-u-boot.dtsi | 14 ++
>>> .../k3-j7200-common-proc-board-u-boot.dtsi| 26 +++
>>> .../k3-j721e-common-proc-board-u-boot.dtsi| 14 ++
>>
>> If these are specific to R5, then it should be moved to R5 dts no?
>> -u-boot.dtsi
>> will be applied to A53 dts as well.
>>
>
> Not really.. There registers are present within respective IPs. A53/A72
> use DM APIs to configure these registers whereas R5 does direct
> programming. I intend to add these ranges to kernel DT as well. Until
> then, will be in -u-boot.dtsi.
>
You intend to add mcu-navss ringacc to kernel dts as well. I am fine with this.
But please remember to update u-boot dts once you update kernel dts
Thanks and regards,
Lokesh
>> Thanks and regards,
>> Lokesh
>>
>>> 3 files changed, 54 insertions(+)
>>>
>>> diff --git a/arch/arm/dts/k3-am654-base-board-u-boot.dtsi
>>> b/arch/arm/dts/k3-am654-base-board-u-boot.dtsi
>>> index b0602d1dad..2840258518 100644
>>> --- a/arch/arm/dts/k3-am654-base-board-u-boot.dtsi
>>> +++ b/arch/arm/dts/k3-am654-base-board-u-boot.dtsi
>>> @@ -35,11 +35,25 @@
>>> u-boot,dm-spl;
>>>
>>> ringacc@2b80 {
>>> + reg = <0x0 0x2b80 0x0 0x40>,
>>> + <0x0 0x2b00 0x0 0x40>,
>>> + <0x0 0x2859 0x0 0x100>,
>>> + <0x0 0x2a50 0x0 0x4>,
>>> + <0x0 0x2844 0x0 0x4>;
>>> + reg-names = "rt", "fifos", "proxy_gcfg",
>>> "proxy_target", "cfg";
>>> u-boot,dm-spl;
>>> ti,dma-ring-reset-quirk;
>>> };
>>>
>>> dma-controller@285c {
>>> + reg = <0x0 0x285c 0x0 0x100>,
>>> + <0x0 0x284c 0x0 0x4000>,
>>> + <0x0 0x2a80 0x0 0x4>,
>>> + <0x0 0x284a 0x0 0x4000>,
>>> + <0x0 0x2aa0 0x0 0x4>,
>>> + <0x0 0x2840 0x0 0x2000>;
>>> + reg-names = "gcfg", "rchan", "rchanrt", "tchan",
>>> + "tchanrt", "rflow";
>>> u-boot,dm-spl;
>>> };
>>> };
>>> diff --git a/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi
>>> b/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi
>>> index c3aae65b39..41ce9fcb59 100644
>>> --- a/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi
>>> +++ b/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi
>>> @@ -40,6 +40,32 @@
>>> chipid@4314 {
>>> u-boot,dm-spl;
>>> };
>>> +
>>> + mcu-navss{
>>> + u-boot,dm-spl;
>>> +
>>> + ringacc@2b80 {
>>> + reg = <0x0 0x2b80 0x0 0x40>,
>>> + <0x0 0x2b00 0x0 0x40>,
>>> + <0x0 0x2859 0x0 0x100>,
>>> + <0x0 0x2a50 0x0 0x4>,
>>> + <0x0 0x2844 0x0 0x4>;
>>> + reg-names = "rt", "fifos", "proxy_gcfg",
>>> "proxy_target", "cfg";
>>> + u-boot,dm-spl;
>>> + };
>>> +
>>> + dma-controller@285c {
>>> + reg = <0x0 0x285c 0x0 0x100>,
>>> + <0x0 0x284c 0x0 0x4000>,
>>> + <0x0 0x2a80 0x0 0x4>,
>>> + <0x0 0x284a 0x0 0x4000>,
>>> + <0x0 0x2aa0 0x0 0x4>,
>>> + <0x0 0x2840 0x0 0x2000>;
>>> + reg-names = "gcfg", "rchan", "rchanrt", "tchan",
>>> + "tchanrt", "rflow";
>>> + u-boot,dm-spl;
>>> + };
>>> + };
>>> };
>>>
>>> &secure_proxy_main {
>>> diff --git a/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi
>>> b/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi
>>> index 1135de5a92..ed64f2720d 100644
>>> --- a/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi
>>> +++ b/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi
>>> @@ -54,10 +54,24 @@
>>> u-boot,dm-spl;
>>>
>>> ringacc@2b80 {
>>> + reg = <0x0 0x2b80 0x0 0x40>,
>>> + <0x0 0x2b00 0x0 0x40>,
>>> + <0x0 0x2859 0x0 0x100>,
>>> + <0x0 0x2a50 0x0 0x4>,
>>> + <0x0 0x2844 0x0 0x4>;
>>> +
Re: [PATCH 0/4] efi_loader: capsule: improve capsule authentication support
Am 12. Mai 2021 06:57:49 MESZ schrieb AKASHI Takahiro : >As I discussed in [1], I have made a couple of improvements on >the current implemenation of capsule update. > >Among others, this patch series >1. add signing feature to mkeficapsule >2. remove dtb operation from mkeficapsule >3. add pytest for capsule authentication (on sandbox) > >NOTE: >I temporarily include Patch#3 in order to show that it is not worth >implementing in C as we can do the same thing with a very small >shell script. > >My intent is *NOT* to merge Patch#3 in upstream. > Should you need to resend the series, please, put "DO NOT MERGE" into the title of patch 3. Best regards Heinrich >Prerequisite patches > >See Sughosh's [2] and my [3]. > >Test > >* passed the pytest which is included in this patch series > on sandbox built locally. > >Todo > >* review and update the document for capsule update >doc/board/emulation/qemu_capsule_update.rst > (but not in this patch series) > >[1] https://lists.denx.de/pipermail/u-boot/2021-April/447918.html >[2] https://lists.denx.de/pipermail/u-boot/2021-April/447183.html >[3] https://lists.denx.de/pipermail/u-boot/2021-May/449347.html >https://lists.denx.de/pipermail/u-boot/2021-May/449348.html >https://lists.denx.de/pipermail/u-boot/2021-May/449349.html >https://lists.denx.de/pipermail/u-boot/2021-May/449350.html >https://lists.denx.de/pipermail/u-boot/2021-May/449351.html > >Changes >=== >Initial release (May 12, 2021) >* based on v2021.07-rc2 > >AKASHI Takahiro (4): > tools: mkeficapsule: add firmwware image signing > tools: mkeficapsule: remove device-tree related operation > tools: add fdtsig command > test/py: efi_capsule: add image authentication test > > Makefile | 7 +- > .../py/tests/test_efi_capsule/capsule_defs.py | 5 + > test/py/tests/test_efi_capsule/conftest.py| 35 +- > test/py/tests/test_efi_capsule/signature.dts | 8 + > .../test_capsule_firmware_signed.py | 234 + > tools/Makefile| 7 +- > tools/fdtsig.c| 274 +++ > tools/fdtsig.sh | 40 ++ > tools/mkeficapsule.c | 455 ++ > 9 files changed, 856 insertions(+), 209 deletions(-) > create mode 100644 test/py/tests/test_efi_capsule/signature.dts >create mode 100644 >test/py/tests/test_efi_capsule/test_capsule_firmware_signed.py > create mode 100644 tools/fdtsig.c > create mode 100755 tools/fdtsig.sh
[PATCH 4/4] test/py: efi_capsule: add image authentication test
Add a couple of test cases against dealing with a signed capsule file.
Signed-off-by: AKASHI Takahiro
---
.../py/tests/test_efi_capsule/capsule_defs.py | 5 +
test/py/tests/test_efi_capsule/conftest.py| 35 ++-
test/py/tests/test_efi_capsule/signature.dts | 8 +
.../test_capsule_firmware_signed.py | 234 ++
4 files changed, 279 insertions(+), 3 deletions(-)
create mode 100644 test/py/tests/test_efi_capsule/signature.dts
create mode 100644
test/py/tests/test_efi_capsule/test_capsule_firmware_signed.py
diff --git a/test/py/tests/test_efi_capsule/capsule_defs.py
b/test/py/tests/test_efi_capsule/capsule_defs.py
index 4fd6353c2040..aa9bf5eee3aa 100644
--- a/test/py/tests/test_efi_capsule/capsule_defs.py
+++ b/test/py/tests/test_efi_capsule/capsule_defs.py
@@ -3,3 +3,8 @@
# Directories
CAPSULE_DATA_DIR = '/EFI/CapsuleTestData'
CAPSULE_INSTALL_DIR = '/EFI/UpdateCapsule'
+
+# v1.5.1 or earlier of efitools has a bug in sha256 calculation, and
+# you need build a newer version on your own.
+# The path must terminate with '/'.
+EFITOOLS_PATH = ''
diff --git a/test/py/tests/test_efi_capsule/conftest.py
b/test/py/tests/test_efi_capsule/conftest.py
index 6ad5608cd71c..bd9544bc056f 100644
--- a/test/py/tests/test_efi_capsule/conftest.py
+++ b/test/py/tests/test_efi_capsule/conftest.py
@@ -10,13 +10,13 @@ import pytest
from capsule_defs import *
#
-# Fixture for UEFI secure boot test
+# Fixture for UEFI capsule test
#
-
@pytest.fixture(scope='session')
def efi_capsule_data(request, u_boot_config):
-"""Set up a file system to be used in UEFI capsule test.
+"""Set up a file system to be used in UEFI capsule and
+ authenticaion test.
Args:
request: Pytest request object.
@@ -40,6 +40,26 @@ def efi_capsule_data(request, u_boot_config):
check_call('mkdir -p %s' % data_dir, shell=True)
check_call('mkdir -p %s' % install_dir, shell=True)
+capsule_auth_enabled = u_boot_config.buildconfig.get(
+'config_efi_capsule_authenticate')
+if capsule_auth_enabled:
+# Create private key (SIGNER.key) and certificate (SIGNER.crt)
+check_call('cd %s; openssl req -x509 -sha256 -newkey rsa:2048
-subj /CN=TEST_SIGNER/ -keyout SIGNER.key -out SIGNER.crt -nodes -days 365'
+ % data_dir, shell=True)
+check_call('cd %s; %scert-to-efi-sig-list SIGNER.crt SIGNER.esl'
+ % (data_dir, EFITOOLS_PATH), shell=True)
+
+# Update dtb adding capsule certificate
+check_call('cd %s; cp
%s/test/py/tests/test_efi_capsule/signature.dts .'
+ % (data_dir, u_boot_config.source_dir), shell=True)
+check_call('cd %s; dtc -@ -I dts -O dtb -o signature.dtbo
signature.dts; fdtoverlay -i %s/arch/sandbox/dts/test.dtb -o test_sig.dtb
signature.dtbo'
+ % (data_dir, u_boot_config.build_dir), shell=True)
+
+# Create *malicious* private key (SIGNER2.key) and certificate
+# (SIGNER2.crt)
+check_call('cd %s; openssl req -x509 -sha256 -newkey rsa:2048
-subj /CN=TEST_SIGNER/ -keyout SIGNER2.key -out SIGNER2.crt -nodes -days 365'
+ % data_dir, shell=True)
+
# Create capsule files
# two regions: one for u-boot.bin and the other for u-boot.env
check_call('cd %s; echo -n u-boot:Old > u-boot.bin.old; echo -n
u-boot:New > u-boot.bin.new; echo -n u-boot-env:Old -> u-boot.env.old; echo -n
u-boot-env:New > u-boot.env.new' % data_dir,
@@ -56,6 +76,15 @@ def efi_capsule_data(request, u_boot_config):
check_call('cd %s; %s/tools/mkeficapsule --raw u-boot.bin.new --index
1 Test02' %
(data_dir, u_boot_config.build_dir),
shell=True)
+if capsule_auth_enabled:
+# firmware signed with proper key
+check_call('cd %s; %s/tools/mkeficapsule --raw u-boot.bin.new
--index 1 --monotonic-count 1 --private-key SIGNER.key --certificate SIGNER.crt
Test03' %
+ (data_dir, u_boot_config.build_dir),
+ shell=True)
+# firmware signed with *mal* key
+check_call('cd %s; %s/tools/mkeficapsule --raw u-boot.bin.new
--index 1 --monotonic-count 1 --private-key SIGNER2.key --certificate
SIGNER2.crt Test04' %
+ (data_dir, u_boot_config.build_dir),
+ shell=True)
# Create a disk image with EFI system partition
check_call('virt-make-fs --partition=gpt --size=+1M --type=vfat %s %s'
%
diff --git a/test/py/tests/test_efi_capsule/signature.dts
b/test/py/tests/test_efi_capsule/signature.dts
new file mode 100644
index ..55c15432979a
--- /dev/null
+++ b/test/py/tests/test_efi_capsule/signature.dts
@@ -0,0 +1,8 @@
+/dts-v1/;
+/plugin/;
+
+&{/} {
+ signature {
+ capsule-key = /incbin/("SIGNER.esl");
+ };
[PATCH 3/4] tools: add fdtsig command
This command allows us to add a certificate (or public key) to dtb blob:
{
signature {
capsule-key = "...";
};
}
The value is actually a signature list in terms of UEFI specificaion,
and used in verifying UEFI capsules.
The code was originally developed by Sughosh and derived from
mkeficapsule.c.
Signed-off-by: AKASHI Takahiro
---
Makefile | 2 +-
tools/Makefile | 2 +
tools/fdtsig.c | 274 +
3 files changed, 277 insertions(+), 1 deletion(-)
create mode 100644 tools/fdtsig.c
diff --git a/Makefile b/Makefile
index 9806464357e0..8b40987234a0 100644
--- a/Makefile
+++ b/Makefile
@@ -1016,7 +1016,7 @@ quiet_cmd_lzma = LZMA$@
cmd_lzma = lzma -c -z -k -9 $< > $@
quiet_cmd_fdtsig = FDTSIG $@
-cmd_fdtsig = $(srctree)/tools/fdtsig.sh $(CONFIG_EFI_PKEY_FILE) $@
+cmd_fdtsig = $(objtree)/tools/fdtsig -K $(CONFIG_EFI_PKEY_FILE) -D $@
cfg: u-boot.cfg
diff --git a/tools/Makefile b/tools/Makefile
index 71a52719620c..e6fd1dbade19 100644
--- a/tools/Makefile
+++ b/tools/Makefile
@@ -234,6 +234,8 @@ HOSTCFLAGS_asn1_compiler.o = -idirafter $(srctree)/include
ifneq ($(CONFIG_EFI_CAPSULE_AUTHENTICATE),)
HOSTLDLIBS_mkeficapsule += \
$(shell pkg-config --libs libssl libcrypto 2> /dev/null || echo "-lssl
-lcrypto")
+ fdtsig-objs := fdtsig.o $(LIBFDT_OBJS)
+ hostprogs-y += fdtsig
endif
hostprogs-$(CONFIG_EFI_HAVE_CAPSULE_SUPPORT) += mkeficapsule
diff --git a/tools/fdtsig.c b/tools/fdtsig.c
new file mode 100644
index ..daa1e63c3b33
--- /dev/null
+++ b/tools/fdtsig.c
@@ -0,0 +1,274 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2021 Linaro Limited
+ * The code in this file was extracted from mkeficapsule.c
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+
+#include
+
+#define SIGNATURE_NODENAME "signature"
+#define OVERLAY_NODENAME "__overlay__"
+
+static const char *tool_name = "fdtsig";
+
+static const char *opts_short = "D:K:Oh";
+
+static struct option options[] = {
+ {"dtb", required_argument, NULL, 'D'},
+ {"public key", required_argument, NULL, 'K'},
+ {"overlay", no_argument, NULL, 'O'},
+ {"help", no_argument, NULL, 'h'},
+ {NULL, 0, NULL, 0},
+};
+
+static void print_usage(void)
+{
+ printf("Usage: %s [options]\n"
+ "Options:\n"
+
+ "\t-K, --public-key public key esl file\n"
+ "\t-D, --dtb dtb file\n"
+ "\t-O, --overlay the dtb file is an overlay\n"
+ "\t-h, --help print a help message\n",
+ tool_name);
+}
+
+static int fdt_add_pub_key_data(void *sptr, void *dptr, size_t key_size,
+ bool overlay)
+{
+ int parent;
+ int ov_node;
+ int frag_node;
+ int ret = 0;
+
+ if (overlay) {
+ /*
+* The signature would be stored in the
+* first fragment node of the overlay
+*/
+ frag_node = fdt_first_subnode(dptr, 0);
+ if (frag_node == -FDT_ERR_NOTFOUND) {
+ fprintf(stderr,
+ "Couldn't find the fragment node: %s\n",
+ fdt_strerror(frag_node));
+ goto done;
+ }
+
+ ov_node = fdt_subnode_offset(dptr, frag_node, OVERLAY_NODENAME);
+ if (ov_node == -FDT_ERR_NOTFOUND) {
+ fprintf(stderr,
+ "Couldn't find the __overlay__ node: %s\n",
+ fdt_strerror(ov_node));
+ goto done;
+ }
+ } else {
+ ov_node = 0;
+ }
+
+ parent = fdt_subnode_offset(dptr, ov_node, SIGNATURE_NODENAME);
+ if (parent == -FDT_ERR_NOTFOUND) {
+ parent = fdt_add_subnode(dptr, ov_node, SIGNATURE_NODENAME);
+ if (parent < 0) {
+ ret = parent;
+ if (ret != -FDT_ERR_NOSPACE) {
+ fprintf(stderr,
+ "Couldn't create signature node: %s\n",
+ fdt_strerror(parent));
+ }
+ }
+ }
+ if (ret)
+ goto done;
+
+ /* Write the key to the FDT node */
+ ret = fdt_setprop(dptr, parent, "capsule-key",
+ sptr, key_size);
+
+done:
+ if (ret)
+ ret = ret == -FDT_ERR_NOSPACE ? -ENOSPC : -EIO;
+
+ return ret;
+}
+
+static int add_public_key(const char *pkey_file, const char *dtb_file,
+ bool overlay)
+{
+ int ret;
+ int srcfd = -1;
+ int destfd = -1;
+ void *sptr = NULL;
+ void *dptr = NULL;
+ off_t src_size;
+ struct
[PATCH 2/4] tools: mkeficapsule: remove device-tree related operation
As we discussed, "-K" and "-D" options have nothing to do with
creating a capsule file. The same result can be obtained by
using standard commands like:
=== signature.dts ===
/dts-v1/;
/plugin/;
&{/} {
signature {
capsule-key = /incbin/("SIGNER.esl");
};
};
===
$ dtc -@ -I dts -O dtb -o signature.dtbo signature.dts
$ fdtoverlay -i test.dtb -o test_sig.dtb -v signature.dtbo
So just remove this feature.
(Effectively revert the commit 322c813f4bec ("mkeficapsule: Add support
for embedding public key in a dtb").)
The same feature is implemented by a shell script (tools/fdtsig.sh).
Signed-off-by: AKASHI Takahiro
---
Makefile | 7 +-
tools/Makefile | 1 -
tools/fdtsig.sh | 40
tools/mkeficapsule.c | 235 ++-
4 files changed, 50 insertions(+), 233 deletions(-)
create mode 100755 tools/fdtsig.sh
diff --git a/Makefile b/Makefile
index 63b1f0143220..9806464357e0 100644
--- a/Makefile
+++ b/Makefile
@@ -1015,9 +1015,8 @@ cmd_pad_cat = $(cmd_objcopy) && $(append) || { rm -f $@;
false; }
quiet_cmd_lzma = LZMA$@
cmd_lzma = lzma -c -z -k -9 $< > $@
-quiet_cmd_mkeficapsule = MKEFICAPSULE $@
-cmd_mkeficapsule = $(objtree)/tools/mkeficapsule -K $(CONFIG_EFI_PKEY_FILE) \
- -D $@
+quiet_cmd_fdtsig = FDTSIG $@
+cmd_fdtsig = $(srctree)/tools/fdtsig.sh $(CONFIG_EFI_PKEY_FILE) $@
cfg: u-boot.cfg
@@ -1114,7 +1113,7 @@ dtbs: dts/dt.dtb
ifeq ($(CONFIG_EFI_CAPSULE_AUTHENTICATE)$(CONFIG_EFI_PKEY_DTB_EMBED),yy)
dts/dt.dtb: u-boot tools
$(Q)$(MAKE) $(build)=dts dtbs
- $(call cmd,mkeficapsule)
+ $(call cmd,fdtsig)
else
dts/dt.dtb: u-boot
$(Q)$(MAKE) $(build)=dts dtbs
diff --git a/tools/Makefile b/tools/Makefile
index 02eae0286e20..71a52719620c 100644
--- a/tools/Makefile
+++ b/tools/Makefile
@@ -235,7 +235,6 @@ ifneq ($(CONFIG_EFI_CAPSULE_AUTHENTICATE),)
HOSTLDLIBS_mkeficapsule += \
$(shell pkg-config --libs libssl libcrypto 2> /dev/null || echo "-lssl
-lcrypto")
endif
-mkeficapsule-objs := mkeficapsule.o $(LIBFDT_OBJS)
hostprogs-$(CONFIG_EFI_HAVE_CAPSULE_SUPPORT) += mkeficapsule
# We build some files with extra pedantic flags to try to minimize things
diff --git a/tools/fdtsig.sh b/tools/fdtsig.sh
new file mode 100755
index ..aaa0a9190845
--- /dev/null
+++ b/tools/fdtsig.sh
@@ -0,0 +1,40 @@
+#!/bin/sh
+# SPDX-License-Identifier: GPL-2.0+
+#
+# script to add a certificate (efi-signature-list) to dtb blob
+
+usage() {
+ if [ -n "$*" ]; then
+ echo "ERROR: $*"
+ fi
+ echo "Usage: "$(basename $0) " "
+}
+
+if [ "$#" -ne 2 ]; then
+ usage "Arguments missing"
+ exit 1
+fi
+
+ESL=$1
+DTB=$2
+NEW_DTB=$(basename $DTB)_tmp
+SIG=signature
+
+cat << 'EOF' > $SIG.dts
+/dts-v1/;
+/plugin/;
+
+&{/} {
+signature {
+ capsule-key = /incbin/("ESL");
+};
+};
+EOF
+
+sed -in "s/ESL/$ESL/" $SIG.dts
+
+dtc -@ -I dts -O dtb -o $SIG.dtbo $SIG.dts
+fdtoverlay -i $DTB -o $NEW_DTB -v $SIG.dtbo
+mv $NEW_DTB $DTB
+
+rm $SIG.dts $SIG.dtbo $NEW_DTB
diff --git a/tools/mkeficapsule.c b/tools/mkeficapsule.c
index 34ff1bdd82eb..97ce68ec83ee 100644
--- a/tools/mkeficapsule.c
+++ b/tools/mkeficapsule.c
@@ -4,17 +4,13 @@
* Author: AKASHI Takahiro
*/
-#include
#include
#include
#include
#include
#include
#include
-#include
#include
-
-#include
#include
#include
@@ -28,8 +24,6 @@
#include
#endif
-#include
-
typedef __u8 u8;
typedef __u16 u16;
typedef __u32 u32;
@@ -39,9 +33,6 @@ typedef __s32 s32;
#define aligned_u64 __aligned_u64
-#define SIGNATURE_NODENAME "signature"
-#define OVERLAY_NODENAME "__overlay__"
-
#ifndef __packed
#define __packed __attribute__((packed))
#endif
@@ -59,9 +50,9 @@ efi_guid_t efi_guid_image_type_uboot_raw =
efi_guid_t efi_guid_cert_type_pkcs7 = EFI_CERT_TYPE_PKCS7_GUID;
#if IS_ENABLED(CONFIG_EFI_CAPSULE_AUTHENTICATE)
-static const char *opts_short = "f:r:i:I:v:D:K:P:C:m:dOh";
+static const char *opts_short = "f:r:i:I:v:P:C:m:dh";
#else
-static const char *opts_short = "f:r:i:I:v:D:K:Oh";
+static const char *opts_short = "f:r:i:I:v:h";
#endif
static struct option options[] = {
@@ -69,15 +60,12 @@ static struct option options[] = {
{"raw", required_argument, NULL, 'r'},
{"index", required_argument, NULL, 'i'},
{"instance", required_argument, NULL, 'I'},
- {"dtb", required_argument, NULL, 'D'},
- {"public key", required_argument, NULL, 'K'},
#if IS_ENABLED(CONFIG_EFI_CAPSULE_AUTHENTICATE)
{"private-key", required_argument, NULL, 'P'},
{"certificate", required_argument, NULL, 'C'},
{"monotonic-count", required_argument, NULL, 'm'},
{"dump-sig", no_argument, NULL, 'd'},
#endif
- {"overlay", no_argument, NULL, 'O'},
{"help", no_argument, NULL, 'h'},
{NULL, 0, NULL, 0},
};
@@ -104,180 +92,6 @@ static void prin
[PATCH 1/4] tools: mkeficapsule: add firmwware image signing
With this enhancement, mkeficapsule will be able to create a capsule
file with a signature which will be verified later by FMP's SetImage().
We will have to specify addtional command parameters:
-monotonic-cout : monotonic count
-private-key : private key file
-certificate : certificate file
Only when those parameters are given, a signature will be added
to a capsule file.
Users are expected to maintain the monotonic count for each firmware
image.
Signed-off-by: AKASHI Takahiro
---
tools/Makefile | 4 +
tools/mkeficapsule.c | 324 +++
2 files changed, 303 insertions(+), 25 deletions(-)
diff --git a/tools/Makefile b/tools/Makefile
index d020c55d6644..02eae0286e20 100644
--- a/tools/Makefile
+++ b/tools/Makefile
@@ -231,6 +231,10 @@ hostprogs-$(CONFIG_MIPS) += mips-relocs
hostprogs-$(CONFIG_ASN1_COMPILER) += asn1_compiler
HOSTCFLAGS_asn1_compiler.o = -idirafter $(srctree)/include
+ifneq ($(CONFIG_EFI_CAPSULE_AUTHENTICATE),)
+HOSTLDLIBS_mkeficapsule += \
+ $(shell pkg-config --libs libssl libcrypto 2> /dev/null || echo "-lssl
-lcrypto")
+endif
mkeficapsule-objs := mkeficapsule.o $(LIBFDT_OBJS)
hostprogs-$(CONFIG_EFI_HAVE_CAPSULE_SUPPORT) += mkeficapsule
diff --git a/tools/mkeficapsule.c b/tools/mkeficapsule.c
index de0a62898886..34ff1bdd82eb 100644
--- a/tools/mkeficapsule.c
+++ b/tools/mkeficapsule.c
@@ -18,7 +18,17 @@
#include
#include
-#include "fdt_host.h"
+#include
+#if IS_ENABLED(CONFIG_EFI_CAPSULE_AUTHENTICATE)
+#include
+#include
+#include
+#include
+#include
+#include
+#endif
+
+#include
typedef __u8 u8;
typedef __u16 u16;
@@ -46,6 +56,13 @@ efi_guid_t efi_guid_image_type_uboot_fit =
EFI_FIRMWARE_IMAGE_TYPE_UBOOT_FIT_GUID;
efi_guid_t efi_guid_image_type_uboot_raw =
EFI_FIRMWARE_IMAGE_TYPE_UBOOT_RAW_GUID;
+efi_guid_t efi_guid_cert_type_pkcs7 = EFI_CERT_TYPE_PKCS7_GUID;
+
+#if IS_ENABLED(CONFIG_EFI_CAPSULE_AUTHENTICATE)
+static const char *opts_short = "f:r:i:I:v:D:K:P:C:m:dOh";
+#else
+static const char *opts_short = "f:r:i:I:v:D:K:Oh";
+#endif
static struct option options[] = {
{"fit", required_argument, NULL, 'f'},
@@ -54,6 +71,12 @@ static struct option options[] = {
{"instance", required_argument, NULL, 'I'},
{"dtb", required_argument, NULL, 'D'},
{"public key", required_argument, NULL, 'K'},
+#if IS_ENABLED(CONFIG_EFI_CAPSULE_AUTHENTICATE)
+ {"private-key", required_argument, NULL, 'P'},
+ {"certificate", required_argument, NULL, 'C'},
+ {"monotonic-count", required_argument, NULL, 'm'},
+ {"dump-sig", no_argument, NULL, 'd'},
+#endif
{"overlay", no_argument, NULL, 'O'},
{"help", no_argument, NULL, 'h'},
{NULL, 0, NULL, 0},
@@ -70,6 +93,12 @@ static void print_usage(void)
"\t-I, --instanceupdate hardware instance\n"
"\t-K, --public-key public key esl file\n"
"\t-D, --dtb dtb file\n"
+#if IS_ENABLED(CONFIG_EFI_CAPSULE_AUTHENTICATE)
+ "\t-P, --private-key private key file\n"
+ "\t-C, --certificate signer's certificate file\n"
+ "\t-m, --monotonic-count monotonic count\n"
+ "\t-d, --dump_sig dump signature (*.p7)\n"
+#endif
"\t-O, --overlay the dtb file is an overlay\n"
"\t-h, --help print a help message\n",
tool_name);
@@ -249,12 +278,167 @@ err:
return ret;
}
+struct auth_context {
+ char *key_file;
+ char *cert_file;
+ u8 *image_data;
+ size_t image_size;
+ struct efi_firmware_image_authentication auth;
+ u8 *sig_data;
+ size_t sig_size;
+};
+
+static int dump_sig;
+
+#if IS_ENABLED(CONFIG_EFI_CAPSULE_AUTHENTICATE)
+static EVP_PKEY *fileio_read_pkey(const char *filename)
+{
+ EVP_PKEY *key = NULL;
+ BIO *bio;
+
+ bio = BIO_new_file(filename, "r");
+ if (!bio)
+ goto out;
+
+ key = PEM_read_bio_PrivateKey(bio, NULL, NULL, NULL);
+
+out:
+ BIO_free_all(bio);
+ if (!key) {
+ printf("Can't load key from file '%s'\n", filename);
+ ERR_print_errors_fp(stderr);
+ }
+
+ return key;
+}
+
+static X509 *fileio_read_cert(const char *filename)
+{
+ X509 *cert = NULL;
+ BIO *bio;
+
+ bio = BIO_new_file(filename, "r");
+ if (!bio)
+ goto out;
+
+ cert = PEM_read_bio_X509(bio, NULL, NULL, NULL);
+
+out:
+ BIO_free_all(bio);
+ if (!cert) {
+ printf("Can't load certificate from file '%s'\n", filename);
+ ERR_print_errors_fp(stderr);
+ }
+
+ return cert;
+}
+
+static int create_auth_data(struct auth_context *ctx)
+{
+ EVP_PKEY *key = NULL;
+ X509 *cert = NULL;
+ BIO *data_bio = NULL;
+ const EVP_MD *md;
+ PKCS7 *p7;
+
[PATCH 0/4] efi_loader: capsule: improve capsule authentication support
As I discussed in [1], I have made a couple of improvements on the current implemenation of capsule update. Among others, this patch series 1. add signing feature to mkeficapsule 2. remove dtb operation from mkeficapsule 3. add pytest for capsule authentication (on sandbox) NOTE: I temporarily include Patch#3 in order to show that it is not worth implementing in C as we can do the same thing with a very small shell script. My intent is *NOT* to merge Patch#3 in upstream. Prerequisite patches See Sughosh's [2] and my [3]. Test * passed the pytest which is included in this patch series on sandbox built locally. Todo * review and update the document for capsule update doc/board/emulation/qemu_capsule_update.rst (but not in this patch series) [1] https://lists.denx.de/pipermail/u-boot/2021-April/447918.html [2] https://lists.denx.de/pipermail/u-boot/2021-April/447183.html [3] https://lists.denx.de/pipermail/u-boot/2021-May/449347.html https://lists.denx.de/pipermail/u-boot/2021-May/449348.html https://lists.denx.de/pipermail/u-boot/2021-May/449349.html https://lists.denx.de/pipermail/u-boot/2021-May/449350.html https://lists.denx.de/pipermail/u-boot/2021-May/449351.html Changes === Initial release (May 12, 2021) * based on v2021.07-rc2 AKASHI Takahiro (4): tools: mkeficapsule: add firmwware image signing tools: mkeficapsule: remove device-tree related operation tools: add fdtsig command test/py: efi_capsule: add image authentication test Makefile | 7 +- .../py/tests/test_efi_capsule/capsule_defs.py | 5 + test/py/tests/test_efi_capsule/conftest.py| 35 +- test/py/tests/test_efi_capsule/signature.dts | 8 + .../test_capsule_firmware_signed.py | 234 + tools/Makefile| 7 +- tools/fdtsig.c| 274 +++ tools/fdtsig.sh | 40 ++ tools/mkeficapsule.c | 455 ++ 9 files changed, 856 insertions(+), 209 deletions(-) create mode 100644 test/py/tests/test_efi_capsule/signature.dts create mode 100644 test/py/tests/test_efi_capsule/test_capsule_firmware_signed.py create mode 100644 tools/fdtsig.c create mode 100755 tools/fdtsig.sh -- 2.31.0
Re: [PATCH] pwm: sifive: make set_config() and set_enable() work properly
Hello Vincent,
On 03.05.21 09:26, Vincent Chen wrote:
> The pwm_sifive_set_config() and pwm_sifive_set_enable() cannot work
> properly due to the wrong implementations. It will cause the u-boot
> PWM command to not work as expected. The bugs will be resolved in this
> patch.
>
> Signed-off-by: Vincent Chen
> ---
> drivers/pwm/pwm-sifive.c | 21 +++--
> 1 file changed, 11 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/pwm/pwm-sifive.c b/drivers/pwm/pwm-sifive.c
> index 01212d6..b9813a3 100644
> --- a/drivers/pwm/pwm-sifive.c
> +++ b/drivers/pwm/pwm-sifive.c
> @@ -38,6 +38,9 @@
> #define PWM_SIFIVE_SIZE_PWMCMP 4
> #define PWM_SIFIVE_CMPWIDTH 16
>
> +#define PWM_SIFIVE_CHANNEL_ENABLE_VAL 0
> +#define PWM_SIFIVE_CHANNEL_DISABLE_VAL 0x
> +
> DECLARE_GLOBAL_DATA_PTR;
>
> struct pwm_sifive_regs {
> @@ -77,7 +80,7 @@ static int pwm_sifive_set_config(struct udevice *dev, uint
> channel,
>*/
> scale_pow = lldiv((uint64_t)priv->freq * period_ns, 10);
> scale = clamp(ilog2(scale_pow) - PWM_SIFIVE_CMPWIDTH, 0, 0xf);
> - val |= FIELD_PREP(PWM_SIFIVE_PWMCFG_SCALE, scale);
> + val |= (FIELD_PREP(PWM_SIFIVE_PWMCFG_SCALE, scale) |
> PWM_SIFIVE_PWMCFG_EN_ALWAYS);
Ok, for this as it seems the same as in linux:
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/pwm/pwm-sifive.c#n96
> /*
>* The problem of output producing mixed setting as mentioned at top,
> @@ -88,6 +91,7 @@ static int pwm_sifive_set_config(struct udevice *dev, uint
> channel,
> num = (u64)duty_ns * (1U << PWM_SIFIVE_CMPWIDTH);
> frac = DIV_ROUND_CLOSEST_ULL(num, period_ns);
> frac = min(frac, (1U << PWM_SIFIVE_CMPWIDTH) - 1);
> + frac = (1U << PWM_SIFIVE_CMPWIDTH) - 1 - frac;
I just looked into linux code, and current code is the same as in linux, see:
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/pwm/pwm-sifive.c#n186
May you can describe what problem you exactly fix? May this part
is not needed?
I wonder, why this is not also a problem than in linux?
Thanks!
bye,
Heiko
>
> writel(val, priv->base + regs->cfg);
> writel(frac, priv->base + regs->cmp0 + channel *
> @@ -100,18 +104,15 @@ static int pwm_sifive_set_enable(struct udevice *dev,
> uint channel, bool enable)
> {
> struct pwm_sifive_priv *priv = dev_get_priv(dev);
> const struct pwm_sifive_regs *regs = &priv->data->regs;
> - u32 val;
>
> debug("%s: Enable '%s'\n", __func__, dev->name);
>
> - if (enable) {
> - val = readl(priv->base + regs->cfg);
> - val |= PWM_SIFIVE_PWMCFG_EN_ALWAYS;
> - writel(val, priv->base + regs->cfg);
> - } else {
> - writel(0, priv->base + regs->cmp0 + channel *
> -PWM_SIFIVE_SIZE_PWMCMP);
> - }
> + if (enable)
> + writel(PWM_SIFIVE_CHANNEL_ENABLE_VAL, priv->base +
> +regs->cmp0 + channel * PWM_SIFIVE_SIZE_PWMCMP);
> + else
> + writel(PWM_SIFIVE_CHANNEL_DISABLE_VAL, priv->base +
> +regs->cmp0 + channel * PWM_SIFIVE_SIZE_PWMCMP);
>
> return 0;
> }
>
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-52 Fax: +49-8142-66989-80 Email: h...@denx.de
Re: [PATCH v5 05/13] binman: Add support for RISC-V OpenSBI fw_dynamic blob
> From: Bin Meng > Sent: Monday, May 10, 2021 8:24 PM > To: Simon Glass ; Rick Jian-Zhi Chen(陳建志) > ; u-boot@lists.denx.de > Cc: Bin Meng > Subject: [PATCH v5 05/13] binman: Add support for RISC-V OpenSBI fw_dynamic > blob > > Add an entry for RISC-V OpenSBI's 'fw_dynamic' firmware payload. > > Signed-off-by: Bin Meng > Reviewed-by: Simon Glass > > --- > > (no changes since v2) > > Changes in v2: > - drop "size = <16>" in the binman node > > tools/binman/entries.rst | 13 + > tools/binman/etype/opensbi.py | 23 +++ > tools/binman/ftest.py | 7 +++ > tools/binman/test/201_opensbi.dts | 14 ++ > 4 files changed, 57 insertions(+) Reviewed-by: Rick Chen
Re: [PATCH v5 02/13] binman: Correct '-a' description in the doc
> From: Bin Meng > Sent: Monday, May 10, 2021 8:24 PM > To: Simon Glass ; Rick Jian-Zhi Chen(陳建志) > ; u-boot@lists.denx.de > Cc: Bin Meng > Subject: [PATCH v5 02/13] binman: Correct '-a' description in the doc > > It needs a space around '-a'. > > Signed-off-by: Bin Meng > Reviewed-by: Simon Glass > --- > > (no changes since v1) > > tools/binman/binman.rst | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) Reviewed-by: Rick Chen
Re: [PATCH v5 01/13] common: kconfig: Correct a typo in SPL_LOAD_FIT
> From: Bin Meng > Sent: Monday, May 10, 2021 8:23 PM > To: Simon Glass ; Rick Jian-Zhi Chen(陳建志) > ; u-boot@lists.denx.de > Cc: Bin Meng > Subject: [PATCH v5 01/13] common: kconfig: Correct a typo in SPL_LOAD_FIT > > It should be FDT, not FTD. > > Signed-off-by: Bin Meng > Reviewed-by: Simon Glass > --- > > (no changes since v1) > > common/Kconfig.boot | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) Reviewed-by: Rick Chen
Re: [PATCH v5 12/13] riscv: ae350: Switch to use binman to generate u-boot.itb
> From: Bin Meng > Sent: Monday, May 10, 2021 8:24 PM > To: Simon Glass ; Rick Jian-Zhi Chen(陳建志) > ; u-boot@lists.denx.de > Cc: Bin Meng > Subject: [PATCH v5 12/13] riscv: ae350: Switch to use binman to generate > u-boot.itb > > Use the new BINMAN_STANDALONE_FDT option for AE350 based SPL defconfigs, so > that binman is now used to generate u-boot.itb. > > Signed-off-by: Bin Meng > > --- > > (no changes since v3) > > Changes in v3: > - new patch: "riscv: ae350: Switch to use binman to generate u-boot.itb" > > arch/riscv/dts/ae350_32.dts | 2 ++ > arch/riscv/dts/ae350_64.dts | 2 ++ > board/AndesTech/ax25-ae350/Kconfig | 1 + > configs/ae350_rv32_spl_defconfig | 2 ++ > configs/ae350_rv32_spl_xip_defconfig | 2 ++ > configs/ae350_rv64_spl_defconfig | 2 ++ > configs/ae350_rv64_spl_xip_defconfig | 2 ++ > 7 files changed, 13 insertions(+) Reviewed-by: Rick Chen
Re: FW: [PATCH v4 00/13] riscv: Switch to use binman to generate u-boot.itb
Hi Rick,
On Wed, May 12, 2021 at 11:25 AM Rick Chen wrote:
>
> HI Bin,
>
> >
> > > Hi Rick,
> > >
> > > On Tue, May 11, 2021 at 8:49 AM Rick Chen wrote:
> > > >
> > > > Hi Bin,
> > > >
> > > > > Hi Rick,
> > > > >
> > > > > On Mon, May 10, 2021 at 3:22 PM Rick Chen
> > > > > wrote:
> > > > > >
> > > > > > Hi Bin
> > > > > >
> > > > > > > Hi Bin,
> > > > > > >
> > > > > > > > From: Bin Meng
> > > > > > > > Sent: Monday, May 10, 2021 2:58 PM
> > > > > > > > To: Simon Glass ; Rick Jian-Zhi Chen(陳建志)
> > > > > > > > ; u-boot@lists.denx.de
> > > > > > > > Subject: [PATCH v4 00/13] riscv: Switch to use binman to
> > > > > > > > generate u-boot.itb
> > > > > > > >
> > > > > > > > This series updates binman to handle creation of u-boot.itb
> > > > > > > > image for RISC-V boards.
> > > > > > > >
> > > > > > > > Azure results: PASS
> > > > > > > > https://dev.azure.com/bmeng/GitHub/_build/results?buildId=363&view=results
> > > > > > > >
> > > > > > > > The following tests were performed:
> > > > > > > > * booting qemu-riscv{32|64}_spl_defconfig on QEMU virt
> > > > > > > > * booting sifive_unleashed_defconfig on QEMU sifive_u
> > > > > > > >
> > > > > > > > AE350 SPL defconfigs are not tested. @Rick, could you please
> > > > > > > > test and report?
> > > > > > >
> > > > > > > OK. I will verify it on AE350.
> > > > > >
> > > > > > It fail as below messages:
> > > > > >
> > > > > > U-Boot SPL 2021.07-rc1-00218-g468b3b3 (May 10 2021 - 15:13:03 +0800)
> > > > > > Trying to boot from RAM
> > > > > > alloc space exhausted
> > > > >
> > > > > Looks it is running out of memory.
> > > > >
> > > > > > Could not get FIT buffer of 499076 bytes
> > > > > > check CONFIG_SYS_SPL_MALLOC_SIZE
> > > > >
> > > > > Could you please try increasing CONFIG_SYS_SPL_MALLOC_SIZE?
> > > >
> > > > I increased CONFIG_SYS_SPL_MALLOC_SIZE, but it is useless.
> > > > But it boots successfully after increase CONFIG_SPL_SYS_MALLOC_F_LEN
> > > > larger.
> > >
> > > Thanks for testing. I am not sure why AE350 fails to boot because this
> > > series only changes the way to assemble the bits.
> > >
> > > Could you please confirm if without this patch series, AE350 can boot?
> >
> > OK.
>
>
> I have verified AE350 without your patch, it works as below:
>
> U-Boot SPL 2021.07-rc1-00194-g07b5310 (May 12 2021 - 10:59:48 +0800)
> Trying to boot from RAM
>
> U-Boot 2021.07-rc1-00194-g07b5310 (May 12 2021 - 10:59:48 +0800)
>
> DRAM: 1 GiB
> Flash: 64 MiB
> MMC: mmc@f0e0: 0
> Loading Environment from SPIFlash... SF: Detected mx25u1635e with page
> size 256 Bytes, erase size 4 KiB, total 2 MiB
> OK
> In:serial@f030
> Out: serial@f030
> Err: serial@f030
> Net: no alias for ethernet0
>
> Warning: mac@e010 (eth0) using random MAC address - 26:00:fa:12:76:ad
> eth0: mac@e010
> Hit any key to stop autoboot: 0
> RISC-V #
>
> =
> With your patch, it fail as below:
> =
>
> U-Boot SPL 2021.07-rc1-00207-g28a2d21 (May 12 2021 - 11:09:11 +0800)
> Trying to boot from RAM
> alloc space exhausted
> Could not get FIT buffer of 499076 bytes
> check CONFIG_SYS_SPL_MALLOC_SIZE
> No device tree specified in SPL image
>
> ===
> After increase CONFIG_SPL_SYS_MALLOC_F_LEN, it works as below
> ===
> U-Boot SPL 2021.07-rc1-00207-g28a2d21 (May 12 2021 - 11:11:00 +0800)
> Trying to boot from RAM
>
>
> U-Boot 2021.07-rc1-00207-g28a2d21 (May 12 2021 - 11:11:00 +0800)
>
> DRAM: 1 GiB
> Flash: 64 MiB
> MMC: mmc@f0e0: 0
> Loading Environment from SPIFlash... SF: Detected mx25u1635e with page
> size 256 Bytes, erase size 4 KiB, total 2 MiB
> OK
> In:serial@f030
> Out: serial@f030
> Err: serial@f030
> Net: no alias for ethernet0
>
> Warning: mac@e010 (eth0) using random MAC address - e6:58:7e:7c:5f:49
> eth0: mac@e010
> Hit any key to stop autoboot: 0
> RISC-V #
>
>
> I found that it need larger heap size when spl try to get fit image
> with using binman to generate u-boot.itb instead of
> USE_SPL_FIT_GENERATOR.
> But it is OK. I will send a patch for AE350 later.
Thank you very much for your testing. Good to know we have a solution.
Regards,
Bin
Re: FW: [PATCH v4 00/13] riscv: Switch to use binman to generate u-boot.itb
HI Bin,
>
> > Hi Rick,
> >
> > On Tue, May 11, 2021 at 8:49 AM Rick Chen wrote:
> > >
> > > Hi Bin,
> > >
> > > > Hi Rick,
> > > >
> > > > On Mon, May 10, 2021 at 3:22 PM Rick Chen wrote:
> > > > >
> > > > > Hi Bin
> > > > >
> > > > > > Hi Bin,
> > > > > >
> > > > > > > From: Bin Meng
> > > > > > > Sent: Monday, May 10, 2021 2:58 PM
> > > > > > > To: Simon Glass ; Rick Jian-Zhi Chen(陳建志)
> > > > > > > ; u-boot@lists.denx.de
> > > > > > > Subject: [PATCH v4 00/13] riscv: Switch to use binman to generate
> > > > > > > u-boot.itb
> > > > > > >
> > > > > > > This series updates binman to handle creation of u-boot.itb image
> > > > > > > for RISC-V boards.
> > > > > > >
> > > > > > > Azure results: PASS
> > > > > > > https://dev.azure.com/bmeng/GitHub/_build/results?buildId=363&view=results
> > > > > > >
> > > > > > > The following tests were performed:
> > > > > > > * booting qemu-riscv{32|64}_spl_defconfig on QEMU virt
> > > > > > > * booting sifive_unleashed_defconfig on QEMU sifive_u
> > > > > > >
> > > > > > > AE350 SPL defconfigs are not tested. @Rick, could you please test
> > > > > > > and report?
> > > > > >
> > > > > > OK. I will verify it on AE350.
> > > > >
> > > > > It fail as below messages:
> > > > >
> > > > > U-Boot SPL 2021.07-rc1-00218-g468b3b3 (May 10 2021 - 15:13:03 +0800)
> > > > > Trying to boot from RAM
> > > > > alloc space exhausted
> > > >
> > > > Looks it is running out of memory.
> > > >
> > > > > Could not get FIT buffer of 499076 bytes
> > > > > check CONFIG_SYS_SPL_MALLOC_SIZE
> > > >
> > > > Could you please try increasing CONFIG_SYS_SPL_MALLOC_SIZE?
> > >
> > > I increased CONFIG_SYS_SPL_MALLOC_SIZE, but it is useless.
> > > But it boots successfully after increase CONFIG_SPL_SYS_MALLOC_F_LEN
> > > larger.
> >
> > Thanks for testing. I am not sure why AE350 fails to boot because this
> > series only changes the way to assemble the bits.
> >
> > Could you please confirm if without this patch series, AE350 can boot?
>
> OK.
I have verified AE350 without your patch, it works as below:
U-Boot SPL 2021.07-rc1-00194-g07b5310 (May 12 2021 - 10:59:48 +0800)
Trying to boot from RAM
U-Boot 2021.07-rc1-00194-g07b5310 (May 12 2021 - 10:59:48 +0800)
DRAM: 1 GiB
Flash: 64 MiB
MMC: mmc@f0e0: 0
Loading Environment from SPIFlash... SF: Detected mx25u1635e with page
size 256 Bytes, erase size 4 KiB, total 2 MiB
OK
In:serial@f030
Out: serial@f030
Err: serial@f030
Net: no alias for ethernet0
Warning: mac@e010 (eth0) using random MAC address - 26:00:fa:12:76:ad
eth0: mac@e010
Hit any key to stop autoboot: 0
RISC-V #
=
With your patch, it fail as below:
=
U-Boot SPL 2021.07-rc1-00207-g28a2d21 (May 12 2021 - 11:09:11 +0800)
Trying to boot from RAM
alloc space exhausted
Could not get FIT buffer of 499076 bytes
check CONFIG_SYS_SPL_MALLOC_SIZE
No device tree specified in SPL image
===
After increase CONFIG_SPL_SYS_MALLOC_F_LEN, it works as below
===
U-Boot SPL 2021.07-rc1-00207-g28a2d21 (May 12 2021 - 11:11:00 +0800)
Trying to boot from RAM
U-Boot 2021.07-rc1-00207-g28a2d21 (May 12 2021 - 11:11:00 +0800)
DRAM: 1 GiB
Flash: 64 MiB
MMC: mmc@f0e0: 0
Loading Environment from SPIFlash... SF: Detected mx25u1635e with page
size 256 Bytes, erase size 4 KiB, total 2 MiB
OK
In:serial@f030
Out: serial@f030
Err: serial@f030
Net: no alias for ethernet0
Warning: mac@e010 (eth0) using random MAC address - e6:58:7e:7c:5f:49
eth0: mac@e010
Hit any key to stop autoboot: 0
RISC-V #
I found that it need larger heap size when spl try to get fit image
with using binman to generate u-boot.itb instead of
USE_SPL_FIT_GENERATOR.
But it is OK. I will send a patch for AE350 later.
Thanks,
Rick
>
> >
> > Regards,
> > Bin
Re: [PATCH v2 16/50] image: Add Kconfig options for FIT in the host build
On Tue, May 11, 2021 at 07:50:38PM -0500, Alex G. wrote: > On 5/11/21 5:34 PM, Tom Rini wrote: > > On Tue, May 11, 2021 at 02:57:03PM -0500, Alex G. wrote: > > > On 5/6/21 9:24 AM, Simon Glass wrote: > > > > In preparation for enabling CONFIG_IS_ENABLED() on the host build, add > > > > some options to enable the various FIT options expected in these tools. > > > > This will ensure that the code builds correctly when CONFIG_HOST_xxx > > > > is distinct from CONFIG_xxx. > > > > > > > > Signed-off-by: Simon Glass > > > > > > Reviewed-by: Alexandru Gagniuc > > > > > > This makes me wonder whether we should just always enable host features. > > > Right now, each defconfig can have a different mkimage config. So we > > > should > > > really have mkimage-imx8, mkimage-stm32mp, etc, which support different > > > feature sets. This doesn't make much sense. > > > > > > The alternative is to get rid of all these configs and always enable > > > mkimage > > > features. The disadvantage is that we'd require openssl for building > > > target > > > code. > > > > > > A second alternative is to have a mkimage-nossl that gets built and used > > > when openssl isn't available. It's really just openssl that causes such a > > > schism. > > > > It would probably be best to have a single mkimage for everyone, with > > everything on. But before then we really need to move from openssl to > > gnutls or some other library that's compatible as it's been raised > > before that linking with openssl like we do is a license violation I > > believe. > > How about the former alternative for now? i.e. compile mkimage with or > without openssl, and have that be the only host side switch. That would be a step in the right direction, yeah. -- Tom signature.asc Description: PGP signature
Re: [PATCH v2 16/50] image: Add Kconfig options for FIT in the host build
On 5/11/21 5:34 PM, Tom Rini wrote: On Tue, May 11, 2021 at 02:57:03PM -0500, Alex G. wrote: On 5/6/21 9:24 AM, Simon Glass wrote: In preparation for enabling CONFIG_IS_ENABLED() on the host build, add some options to enable the various FIT options expected in these tools. This will ensure that the code builds correctly when CONFIG_HOST_xxx is distinct from CONFIG_xxx. Signed-off-by: Simon Glass Reviewed-by: Alexandru Gagniuc This makes me wonder whether we should just always enable host features. Right now, each defconfig can have a different mkimage config. So we should really have mkimage-imx8, mkimage-stm32mp, etc, which support different feature sets. This doesn't make much sense. The alternative is to get rid of all these configs and always enable mkimage features. The disadvantage is that we'd require openssl for building target code. A second alternative is to have a mkimage-nossl that gets built and used when openssl isn't available. It's really just openssl that causes such a schism. It would probably be best to have a single mkimage for everyone, with everything on. But before then we really need to move from openssl to gnutls or some other library that's compatible as it's been raised before that linking with openssl like we do is a license violation I believe. How about the former alternative for now? i.e. compile mkimage with or without openssl, and have that be the only host side switch. Alex
Re: Pull request: u-boot-imx u-boot-imx-20210502
On Tue, May 11, 2021 at 04:46:14PM +0200, Stefano Babic wrote: > Hi Tom, > > please pull from u-boot-imx, thanks ! > > CI : https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/7368 > > > The following changes since commit 8ddaf943589756442bba21e5be645cd47526d82b: > > Merge tag 'dm-pull-29apr21' of > https://source.denx.de/u-boot/custodians/u-boot-dm (2021-04-29 21:03:38 > -0400) > > are available in the Git repository at: > > https://gitlab.denx.de/u-boot/custodians/u-boot-imx.git > tags/u-boot-imx-20210502 > > for you to fetch changes up to 7666cccf4f24dd500a9279741a0b64a3f89a7331: > > ARM:imx:imx8mq-cm: Add support for Ronetix iMX8MQ-CM (2021-05-02 12:46:54 > +0200) > Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: FW: [PATCH] pwm: sifive: make set_config() and set_enable() work properly
> From: U-Boot On Behalf Of Vincent Chen > Sent: Monday, May 03, 2021 3:27 PM > To: s...@chromium.org; h...@denx.de > Cc: u-boot@lists.denx.de; Vincent Chen > Subject: [PATCH] pwm: sifive: make set_config() and set_enable() work properly > > The pwm_sifive_set_config() and pwm_sifive_set_enable() cannot work properly > due to the wrong implementations. It will cause the u-boot PWM command to not > work as expected. The bugs will be resolved in this patch. > > Signed-off-by: Vincent Chen > --- > drivers/pwm/pwm-sifive.c | 21 +++-- > 1 file changed, 11 insertions(+), 10 deletions(-) Reviewed-by: Rick Chen
Re: [PATCH] Revert "mmc: sdhci: set to INT_DATA_END when there are data"
Dear Andy On 5/11/21 4:39 PM, andy...@sony.com wrote: > Hi Jaehoon > >> If you're ok, I will test after reverted the patch on tomorrow, and I will >> share >> result. >> Or I will try to reproduce timeout issue on 410c board. > > Sorry, but is there any update for this comments? Sorry for replying too late. I had been doing other things. So if you're ok, i will test on my own boards with your patch until this weekend. (If possible, i will also check 410c board.) Best Regards, Jaehoon Chung > > Best Regards > Andy Wu > >> -Original Message- >> From: U-Boot On Behalf Of Jaehoon Chung >> Sent: Tuesday, April 6, 2021 7:13 PM >> To: Peng Fan ; jh80.ch...@gmail.com; >> u-boot@lists.denx.de >> Subject: Re: [PATCH] Revert "mmc: sdhci: set to INT_DATA_END when there are >> data" >> >> Hi Peng, >> >> On 4/6/21 7:02 PM, Peng Fan wrote: Subject: RE: [PATCH] Revert "mmc: sdhci: set to INT_DATA_END when there are data" Hi Jaehoon > Did you test on latest u-boot? v2018.01 was too old version. > Yes, we tested on v2020.04, although there is no such issue, but I think it just depends on call sequence timing. > And if my understanding is right, INT_DATA_END needs to set when > there is a data. If there is no data, it doesn't need to set to it. > Logically, there is no problem, isn't? > If there is no data, but current command is RESPONSE-WITH-BUSY (like CMD6) type, the INT_DATA_END needs set also, refer sdhci spec explanation for INT_DATA_END bit: Transfer Complete This bit indicates stop of transaction on three cases: ... (2) Completion of a command pairing with response-with-busy (R1b, R5b) So, our modification just within if (cmd->resp_type & MMC_RSP_BUSY) judgment. >>> >>> Jaehoon, >>> >>> Do you see any issue if revert the patch? >> >> If you're ok, I will test after reverted the patch on tomorrow, and I will >> share >> result. >> Or I will try to reproduce timeout issue on 410c board. >> >> Best Regards, >> Jaehoon Chung >>> >>> Thanks, >>> Peng. >>> Best Regards Andy Wu > -Original Message- > From: Jaehoon Chung > Sent: Monday, March 22, 2021 6:03 PM > To: Wu, Andy ; jh80.ch...@samsung.com; Mo, Yuezhang > ; u-boot@lists.denx.de > Cc: peng@nxp.com; c...@samsung.com > Subject: Re: [PATCH] Revert "mmc: sdhci: set to INT_DATA_END when > there are data" > > Hi Andy, > > On 3/18/21 10:59 AM, andy...@sony.com wrote: >> Hi >> >>> I don't want to revert this commit. Is there any issue without this? >> Without revert commit 17ea3c86, Some board, like Dragonboard 410c >> will meet transfer data timeout error (we used v2018.01): >> >> U-Boot 2018.01 (Nov 26 2020 - 03:31:09 +) Qualcomm-DragonBoard >> 410C >> >> DRAM: 986 MiB >> MMC: sdhci@07824000: 0, sdhci@07864000: 1 >> sdhci_transfer_data: Transfer data timeout >> mmc_init: -70, time 10645 >> *** Warning - No block device, using default environment >> >> And it seems the 17ea3c86 not followed the sdhci specification as >> transfer complete bit should be wait for the BUSY status de-assert. >> >> Kernel side code also wait the transfer complete bit for >> response-with-busy command. > > Did you test on latest u-boot? v2018.01 was too old version. > > And if my understanding is right, INT_DATA_END needs to set when > there is a data. > > If there is no data, it doesn't need to set to it. Logically, there > is no problem, isn't? > > I will check with QC 410C board for clarifying this problem. > >> >>> Without this patch, some SoCs have timeout error with stop command. >> Sorry, we didn't meet this stop command timeout issue, but I guess >> it maybe another issue, and can be fixed with modification limited >> to stop command, not for all response-with-busy command. >> >> Does the SDHCI_QUIRK_BROKEN_R1B can be used for this case? > > Well, it can be used. > > Best Regards, > > Jaehoon Chung > >> >> Best Regards >> Andy Wu >> >>> -Original Message- >>> From: U-Boot On Behalf Of Jaehoon >>> Chung >>> Sent: Thursday, March 18, 2021 6:44 AM >>> To: Mo, Yuezhang ; u-boot@lists.denx.de >>> Cc: peng@nxp.com; c...@samsung.com >>> Subject: Re: [PATCH] Revert "mmc: sdhci: set to INT_DATA_END when >>> there are data" >>> >>> Hi >>> >>> On 3/17/21 3:44 PM, yuezhang...@sony.com wrote: This reverts commit 17ea3c862865c0d704646f67dbf8412f9ff54f59. In eMMC specification, for the response-with-busy(R1b, R5b) command, the DAT0 will driven to LOW as BUSY status, and in sdhci specification, the transfer complete bit should be wait for BUSY status de-as
Re: [PATCHv4 15/26] cmd: ti: pd: Add debug command for K3 power domains
On 5/11/21 5:30 PM, Tero Kristo wrote:
> From: Tero Kristo
>
> Add support command for debugging K3 power domains. This is useful with
> the HSM rearch setup, where power domains are directly controlled by SPL
> instead of going through the TI SCI layer. The debugging support is only
> available in the u-boot codebase though, so the raw register access
> power domain layer must be enabled on u-boot side for this to work. By
> default, u-boot side uses the TI SCI layer, and R5 SPL only uses the
> direct access methods.
>
> Signed-off-by: Tero Kristo
> Signed-off-by: Tero Kristo
Reviewed-by: Jaehoon Chung
Best Regards,
Jaehoon Chung
> ---
> cmd/ti/Kconfig | 8 ++
> cmd/ti/Makefile| 1 +
> cmd/ti/pd.c| 185 +
> drivers/power/domain/ti-power-domain.c | 6 +-
> include/k3-dev.h | 9 ++
> 5 files changed, 206 insertions(+), 3 deletions(-)
> create mode 100644 cmd/ti/pd.c
>
> diff --git a/cmd/ti/Kconfig b/cmd/ti/Kconfig
> index efeff0d482..db557445a8 100644
> --- a/cmd/ti/Kconfig
> +++ b/cmd/ti/Kconfig
> @@ -7,4 +7,12 @@ config CMD_DDR3
> supports memory verification, memory comapre and ecc
> verification if supported.
>
> +config CMD_PD
> + bool "command for verifying power domains"
> + depends on TI_POWER_DOMAIN
> + help
> +Debug command for K3 power domains. For this to work, the
> +K3 power domain driver must be enabled for the u-boot; by
> +default it is only enabled for SPL.
> +
> endmenu
> diff --git a/cmd/ti/Makefile b/cmd/ti/Makefile
> index 16fbade9ed..045593396b 100644
> --- a/cmd/ti/Makefile
> +++ b/cmd/ti/Makefile
> @@ -5,4 +5,5 @@ obj- += dummy.o
>
> ifndef CONFIG_SPL_BUILD
> obj-$(CONFIG_CMD_DDR3) += ddr3.o
> +obj-$(CONFIG_CMD_PD) += pd.o
> endif
> diff --git a/cmd/ti/pd.c b/cmd/ti/pd.c
> new file mode 100644
> index 00..a53ccdcc40
> --- /dev/null
> +++ b/cmd/ti/pd.c
> @@ -0,0 +1,185 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Power Domain test commands
> + *
> + * Copyright (C) 2020 Texas Instruments Incorporated,
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +
> +static const struct udevice_id ti_pd_of_match[] = {
> + { .compatible = "ti,sci-pm-domain" },
> + { /* sentinel */ }
> +};
> +
> +static struct ti_k3_pd_platdata *ti_pd_find_data(void)
> +{
> + struct udevice *dev;
> + int i = 0;
> +
> + while (1) {
> + uclass_get_device(UCLASS_POWER_DOMAIN, i++, &dev);
> + if (!dev)
> + return NULL;
> +
> + if (device_is_compatible(dev,
> + ti_pd_of_match[0].compatible))
> + return dev_get_priv(dev);
> + }
> +
> + return NULL;
> +}
> +
> +static void dump_lpsc(struct ti_k3_pd_platdata *data, struct ti_pd *pd)
> +{
> + int i;
> + struct ti_lpsc *lpsc;
> + u8 state;
> + static const char * const lpsc_states[] = {
> + "swrstdis", "syncrst", "disable", "enable", "autosleep",
> + "autowake", "unknown",
> + };
> +
> + for (i = 0; i < data->num_lpsc; i++) {
> + lpsc = &data->lpsc[i];
> + if (lpsc->pd != pd)
> + continue;
> + state = lpsc_get_state(lpsc);
> + if (state > ARRAY_SIZE(lpsc_states))
> + state = ARRAY_SIZE(lpsc_states) - 1;
> + printf("LPSC%d: state=%s, usecount=%d\n",
> +lpsc->id, lpsc_states[state], lpsc->usecount);
> + }
> +}
> +
> +static void dump_pd(struct ti_k3_pd_platdata *data, struct ti_psc *psc)
> +{
> + int i;
> + struct ti_pd *pd;
> + u8 state;
> + static const char * const pd_states[] = {
> + "off", "on", "unknown"
> + };
> +
> + for (i = 0; i < data->num_pd; i++) {
> + pd = &data->pd[i];
> + if (pd->psc != psc)
> + continue;
> + state = ti_pd_state(pd);
> + if (state > ARRAY_SIZE(pd_states))
> + state = ARRAY_SIZE(pd_states) - 1;
> + printf(" PD%d: state=%s, usecount=%d:\n",
> +pd->id, pd_states[state], pd->usecount);
> + dump_lpsc(data, pd);
> + }
> +}
> +
> +static void dump_psc(struct ti_k3_pd_platdata *data)
> +{
> + int i;
> + struct ti_psc *psc;
> +
> + for (i = 0; i < data->num_psc; i++) {
> + psc = &data->psc[i];
> + printf("PSC%d [%p]:\n", psc->id, psc->base);
> + dump_pd(data, psc);
> + }
> +}
> +
> +static int do_pd_dump(struct cmd_tbl *cmdtp, int flag, int argc,
> + char *const argv[])
> +{
> + struct ti_k3_pd_platdata *data;
> +
> + data = ti_pd_find_data();
> + if (!data)
> + return CMD_RET_FAILURE;
> +
> + dump_psc(data);
> +
> + return 0;
> +}
> +
>
Re: [PATCHv4 14/26] power: domain: Introduce driver for raw TI K3 PDs
On 5/11/21 5:30 PM, Tero Kristo wrote:
> From: Tero Kristo
>
> Normally, power domains are handled via TI-SCI in K3 SoCs. However,
> SPL is not going to have access to sysfw resources, so it must control
> them directly. Add driver for supporting this.
>
> Signed-off-by: Tero Kristo
> Signed-off-by: Tero Kristo
Reviewed-by: Jaehoon Chung
Best Regards,
Jaehoon Chung
> ---
> drivers/power/domain/Kconfig | 7 +
> drivers/power/domain/Makefile | 1 +
> drivers/power/domain/ti-power-domain.c | 368 +
> include/k3-dev.h | 76 +
> 4 files changed, 452 insertions(+)
> create mode 100644 drivers/power/domain/ti-power-domain.c
> create mode 100644 include/k3-dev.h
>
> diff --git a/drivers/power/domain/Kconfig b/drivers/power/domain/Kconfig
> index a0fd980752..99b3f9ae71 100644
> --- a/drivers/power/domain/Kconfig
> +++ b/drivers/power/domain/Kconfig
> @@ -72,4 +72,11 @@ config TI_SCI_POWER_DOMAIN
> help
> Generic power domain implementation for TI devices implementing the
> TI SCI protocol.
> +
> +config TI_POWER_DOMAIN
> + bool "Enable the TI K3 Power domain driver"
> + depends on POWER_DOMAIN && ARCH_K3
> + help
> + Generic power domain implementation for TI K3 devices.
> +
> endmenu
> diff --git a/drivers/power/domain/Makefile b/drivers/power/domain/Makefile
> index 45bf9f6383..3d1e5f073c 100644
> --- a/drivers/power/domain/Makefile
> +++ b/drivers/power/domain/Makefile
> @@ -14,3 +14,4 @@ obj-$(CONFIG_SANDBOX_POWER_DOMAIN) += sandbox-power-domain.o
> obj-$(CONFIG_SANDBOX_POWER_DOMAIN) += sandbox-power-domain-test.o
> obj-$(CONFIG_TEGRA186_POWER_DOMAIN) += tegra186-power-domain.o
> obj-$(CONFIG_TI_SCI_POWER_DOMAIN) += ti-sci-power-domain.o
> +obj-$(CONFIG_TI_POWER_DOMAIN) += ti-power-domain.o
> diff --git a/drivers/power/domain/ti-power-domain.c
> b/drivers/power/domain/ti-power-domain.c
> new file mode 100644
> index 00..e418a7b996
> --- /dev/null
> +++ b/drivers/power/domain/ti-power-domain.c
> @@ -0,0 +1,368 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Texas Instruments power domain driver
> + *
> + * Copyright (C) 2020-2021 Texas Instruments Incorporated -
> http://www.ti.com/
> + * Tero Kristo
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +#define PSC_PTCMD0x120
> +#define PSC_PTSTAT 0x128
> +#define PSC_PDSTAT 0x200
> +#define PSC_PDCTL0x300
> +#define PSC_MDSTAT 0x800
> +#define PSC_MDCTL0xa00
> +
> +#define PDCTL_STATE_MASK 0x1
> +#define PDCTL_STATE_OFF 0x0
> +#define PDCTL_STATE_ON 0x1
> +
> +#define MDSTAT_STATE_MASK0x3f
> +#define MDSTAT_BUSY_MASK 0x30
> +#define MDSTAT_STATE_SWRSTDISABLE0x0
> +#define MDSTAT_STATE_ENABLE 0x3
> +
> +#define LPSC_TIMEOUT 1000
> +#define PD_TIMEOUT 1000
> +
> +static u32 psc_read(struct ti_psc *psc, u32 reg)
> +{
> + u32 val;
> +
> + val = readl(psc->base + reg);
> + debug("%s: 0x%x from %p\n", __func__, val, psc->base + reg);
> + return val;
> +}
> +
> +static void psc_write(u32 val, struct ti_psc *psc, u32 reg)
> +{
> + debug("%s: 0x%x to %p\n", __func__, val, psc->base + reg);
> + writel(val, psc->base + reg);
> +}
> +
> +static u32 pd_read(struct ti_pd *pd, u32 reg)
> +{
> + return psc_read(pd->psc, reg + 4 * pd->id);
> +}
> +
> +static void pd_write(u32 val, struct ti_pd *pd, u32 reg)
> +{
> + psc_write(val, pd->psc, reg + 4 * pd->id);
> +}
> +
> +static u32 lpsc_read(struct ti_lpsc *lpsc, u32 reg)
> +{
> + return psc_read(lpsc->psc, reg + 4 * lpsc->id);
> +}
> +
> +static void lpsc_write(u32 val, struct ti_lpsc *lpsc, u32 reg)
> +{
> + psc_write(val, lpsc->psc, reg + 4 * lpsc->id);
> +}
> +
> +static const struct soc_attr ti_k3_soc_pd_data[] = {
> +#ifdef CONFIG_SOC_K3_J721E
> + {
> + .family = "J721E",
> + .data = &j721e_pd_platdata,
> + },
> + {
> + .family = "J7200",
> + .data = &j7200_pd_platdata,
> + },
> +#endif
> + { /* sentinel */ }
> +};
> +
> +static int ti_power_domain_probe(struct udevice *dev)
> +{
> + struct ti_k3_pd_platdata *data = dev_get_priv(dev);
> + const struct soc_attr *soc_match_data;
> + const struct ti_k3_pd_platdata *pdata;
> +
> + printf("%s(dev=%p)\n", __func__, dev);
> +
> + if (!data)
> + return -ENOMEM;
> +
> + soc_match_data = soc_device_match(ti_k3_soc_pd_data);
> + if (!soc_match_data)
> + return -ENODEV;
> +
> + pdata = (const struct ti_k3_pd_platdata *)soc_match_data->data;
> +
> + data->psc = pdata->psc;
> + data->pd = pdata->pd;
> + data->lpsc = pdata->lpsc;
> + data->devs = pdata->devs;
> + data->num_psc = pdata->num_psc;
> + data->num_pd = pd
Re: [PATCH v2 16/50] image: Add Kconfig options for FIT in the host build
On Tue, May 11, 2021 at 02:57:03PM -0500, Alex G. wrote: > On 5/6/21 9:24 AM, Simon Glass wrote: > > In preparation for enabling CONFIG_IS_ENABLED() on the host build, add > > some options to enable the various FIT options expected in these tools. > > This will ensure that the code builds correctly when CONFIG_HOST_xxx > > is distinct from CONFIG_xxx. > > > > Signed-off-by: Simon Glass > > Reviewed-by: Alexandru Gagniuc > > This makes me wonder whether we should just always enable host features. > Right now, each defconfig can have a different mkimage config. So we should > really have mkimage-imx8, mkimage-stm32mp, etc, which support different > feature sets. This doesn't make much sense. > > The alternative is to get rid of all these configs and always enable mkimage > features. The disadvantage is that we'd require openssl for building target > code. > > A second alternative is to have a mkimage-nossl that gets built and used > when openssl isn't available. It's really just openssl that causes such a > schism. It would probably be best to have a single mkimage for everyone, with everything on. But before then we really need to move from openssl to gnutls or some other library that's compatible as it's been raised before that linking with openssl like we do is a license violation I believe. -- Tom signature.asc Description: PGP signature
[PATCH v2] efi_loader: Don't stop EFI subsystem init if installing TCG2 fails
Up to now we are stopping the EFI subsystem if a TPMv2 exists but the
protocol fails to install. Now that we've switched the config to 'default
y' the sandbox TPM fails, since it doesn't support all the required
capabilities of the protocol.
Not installing the protocol is not catastrophic. If the protocol fails
to install the PCRs will never be extended to the expected values, so
some other entity later in the boot flow will eventually figure it out
and take the necessary actions.
While at it fix a corner case were the user can see an invalid error
message when the protocol failed to install. We do have a tcg2_uninit()
which we call when the protocol installation fails. There are cases though
that this might be called before the configuration table is installed (e.g
probing the TPM for capabilities failed). In that case the user will see
"Failed to delete final events config table". So stop printing it since it's
not an actual failure , simply because the config table was never installed
in the first place.
In order to stop printing it make efi_init_event_log() and create_final_event()
cleanup themselves and only call tcg2_uninit() when the protocol installation
fails.
Signed-off-by: Ilias Apalodimas
---
changes since v1:
- stop printing a warning when tcg2_uninit was called before installing
the final events config table
lib/efi_loader/efi_tcg2.c | 33 -
1 file changed, 28 insertions(+), 5 deletions(-)
diff --git a/lib/efi_loader/efi_tcg2.c b/lib/efi_loader/efi_tcg2.c
index 8f8a26e7b7ae..31343e47678f 100644
--- a/lib/efi_loader/efi_tcg2.c
+++ b/lib/efi_loader/efi_tcg2.c
@@ -999,6 +999,11 @@ static efi_status_t create_final_event(void)
event_log.final_pos = sizeof(*final_event);
ret = efi_install_configuration_table(&efi_guid_final_events,
final_event);
+ if (ret != EFI_SUCCESS) {
+ efi_free_pool(event_log.final_buffer);
+ event_log.final_buffer = NULL;
+ }
+
out:
return ret;
}
@@ -1047,15 +1052,22 @@ static efi_status_t efi_init_event_log(void)
ret = create_specid_event(dev, (void *)((uintptr_t)event_log.buffer +
sizeof(*event_header)),
&spec_event_size);
if (ret != EFI_SUCCESS)
- goto out;
+ goto free_pool;
put_unaligned_le32(spec_event_size, &event_header->event_size);
event_log.pos = spec_event_size + sizeof(*event_header);
event_log.last_event_size = event_log.pos;
ret = create_final_event();
+ if (ret != EFI_SUCCESS)
+ goto free_pool;
out:
return ret;
+
+free_pool:
+ efi_free_pool(event_log.buffer);
+ event_log.buffer = NULL;
+ return ret;
}
/**
@@ -1112,19 +1124,30 @@ efi_status_t efi_tcg2_register(void)
goto fail;
ret = efi_append_scrtm_version(dev);
- if (ret != EFI_SUCCESS)
+ if (ret != EFI_SUCCESS) {
+ tcg2_uninit();
goto fail;
+ }
ret = efi_add_protocol(efi_root, &efi_guid_tcg2_protocol,
(void *)&efi_tcg2_protocol);
if (ret != EFI_SUCCESS) {
- log_err("Cannot install EFI_TCG2_PROTOCOL\n");
+ tcg2_uninit();
goto fail;
}
out:
return ret;
fail:
- tcg2_uninit();
- return ret;
+ log_err("Cannot install EFI_TCG2_PROTOCOL\n");
+ /*
+* Return EFI_SUCCESS and don't stop the EFI subsystem.
+* That's done for 2 reasons
+* - If the protocol is not installed the PCRs won't be extended. So
+* someone later in the boot flow will notice that and take the
+* necessary actions.
+* - The TPM sandbox is limited and we won't be able to run any efi
+* related tests with TCG2 enabled
+*/
+ return EFI_SUCCESS;
}
--
2.31.0
Re: [PATCH v2 16/50] image: Add Kconfig options for FIT in the host build
On 5/6/21 9:24 AM, Simon Glass wrote:
In preparation for enabling CONFIG_IS_ENABLED() on the host build, add
some options to enable the various FIT options expected in these tools.
This will ensure that the code builds correctly when CONFIG_HOST_xxx
is distinct from CONFIG_xxx.
Signed-off-by: Simon Glass
Reviewed-by: Alexandru Gagniuc
This makes me wonder whether we should just always enable host features.
Right now, each defconfig can have a different mkimage config. So we
should really have mkimage-imx8, mkimage-stm32mp, etc, which support
different feature sets. This doesn't make much sense.
The alternative is to get rid of all these configs and always enable
mkimage features. The disadvantage is that we'd require openssl for
building target code.
A second alternative is to have a mkimage-nossl that gets built and used
when openssl isn't available. It's really just openssl that causes such
a schism.
Alex
---
(no changes since v1)
common/image-fit-sig.c | 3 ++-
common/image-fit.c | 4 ++--
tools/Kconfig | 25 +
tools/Makefile | 18 +-
4 files changed, 38 insertions(+), 12 deletions(-)
diff --git a/common/image-fit-sig.c b/common/image-fit-sig.c
index 55ddf1879ed..12a6745c642 100644
--- a/common/image-fit-sig.c
+++ b/common/image-fit-sig.c
@@ -72,11 +72,12 @@ static int fit_image_setup_verify(struct image_sign_info
*info,
char *algo_name;
const char *padding_name;
+#ifndef USE_HOSTCC
if (fdt_totalsize(fit) > CONFIG_FIT_SIGNATURE_MAX_SIZE) {
*err_msgp = "Total size too large";
return 1;
}
-
+#endif
if (fit_image_hash_get_algo(fit, noffset, &algo_name)) {
*err_msgp = "Can't get hash algo property";
return -1;
diff --git a/common/image-fit.c b/common/image-fit.c
index e614643fe39..a16e2dd54a5 100644
--- a/common/image-fit.c
+++ b/common/image-fit.c
@@ -165,7 +165,7 @@ int fit_get_subimage_count(const void *fit, int
images_noffset)
return count;
}
-#if CONFIG_IS_ENABLED(FIT_PRINT) || CONFIG_IS_ENABLED(SPL_FIT_PRINT)
+#if CONFIG_IS_ENABLED(FIT_PRINT)
/**
* fit_image_print_data() - prints out the hash node details
* @fit: pointer to the FIT format image header
@@ -573,7 +573,7 @@ void fit_image_print(const void *fit, int image_noffset,
const char *p)
#else
void fit_print_contents(const void *fit) { }
void fit_image_print(const void *fit, int image_noffset, const char *p) { }
-#endif /* CONFIG_IS_ENABLED(FIR_PRINT) || CONFIG_IS_ENABLED(SPL_FIT_PRINT) */
+#endif /* CONFIG_IS_ENABLED(FIT_PRINT) */
/**
* fit_get_desc - get node description property
diff --git a/tools/Kconfig b/tools/Kconfig
index b2f5012240c..f00ab661135 100644
--- a/tools/Kconfig
+++ b/tools/Kconfig
@@ -9,4 +9,29 @@ config MKIMAGE_DTC_PATH
some cases the system dtc may not support all required features
and the path to a different version should be given here.
+config HOST_FIT
+ def_bool y
+ help
+ Enable FIT support in the host build.
Don't we always want to enable this for mkimage?
+
+config HOST_FIT_FULL_CHECK
+ def_bool y
+ help
+ Do a full check of the FIT before using it in the host build
How would this be used? FIT vs FIT_FULL is mostly an SPL distinction. I
don't think we should have it in host tools.
+
+config HOST_FIT_PRINT
+ def_bool y
+ help
+ Print the content of the FIT verbosely in the host build
This option also doesn't make sense.This seems to do what 'mkimage -l'
already supports.
+
+config HOST_FIT_SIGNATURE
+ def_bool y
+ help
+ Enable signature verification of FIT uImages in the host build
s/verification/signing and verification/
+
+config HOST_FIT_SIGNATURE_MAX_SIZE
+ hex
+ depends on HOST_FIT_SIGNATURE
+ default 0x1000
+
The only use of FIT_SIGNATURE_MAX_SIZE is under "#ifndef USE_HOSTCC". So
this wouldn't make any sense for the host.
endmenu
diff --git a/tools/Makefile b/tools/Makefile
index 2b4bc547abd..d143198f7c9 100644
--- a/tools/Makefile
+++ b/tools/Makefile
@@ -53,12 +53,12 @@ hostprogs-y += mkenvimage
mkenvimage-objs := mkenvimage.o os_support.o lib/crc32.o
hostprogs-y += dumpimage mkimage
-hostprogs-$(CONFIG_FIT_SIGNATURE) += fit_info fit_check_sign
+hostprogs-$(CONFIG_HOST_FIT_SIGNATURE) += fit_info fit_check_sign
hostprogs-$(CONFIG_CMD_BOOTEFI_SELFTEST) += file2include
-FIT_OBJS-$(CONFIG_FIT) := fit_common.o fit_image.o image-host.o common/image-fit.o
-FIT_SIG_OBJS-$(CONFIG_FIT_SIGNATURE) := common/image-sig.o
common/image-fit-sig.o
+FIT_OBJS-$(CONFIG_HOST_FIT) := fit_common.o fit_image.o image-host.o
common/image-fit.o
+FIT_SIG_OBJS-$(CONFIG_HOST_FIT_SIGNATURE) := common/image-sig.o
common/image-fit-sig.o
FIT_CIPHER_OBJS-$(CONFIG_FIT_CIPHER) := common/image-cipher.o
# The following files are sync
[PATCH 1/1] sandbox: ensure that state->ram_buf is in low memory
Addresses in state->ram_buf must be in the low 4 GiB of the address space. Otherwise we cannot correctly fill SMBIOS tables. This shows up in warnings like: WARNING: SMBIOS table_address overflow 7f752735e020 Ensure that state->ram_buf is initialized by the first invocation of os_malloc(). Signed-off-by: Heinrich Schuchardt --- arch/sandbox/cpu/start.c | 12 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/arch/sandbox/cpu/start.c b/arch/sandbox/cpu/start.c index e87365e800..1388dba895 100644 --- a/arch/sandbox/cpu/start.c +++ b/arch/sandbox/cpu/start.c @@ -439,6 +439,14 @@ int main(int argc, char *argv[]) int size; int ret; + /* +* This must be the first invocation of os_malloc() to have +* state->ram_buf in the low 4 GiB. +*/ + ret = state_init(); + if (ret) + goto err; + /* * Copy argv[] so that we can pass the arguments in the original * sequence when resetting the sandbox. @@ -453,10 +461,6 @@ int main(int argc, char *argv[]) gd = &data; gd->arch.text_base = os_find_text_base(); - ret = state_init(); - if (ret) - goto err; - state = state_get_current(); if (os_parse_args(state, argc, argv)) return 1; -- 2.30.2
[PATCH] efi_loader: Don't stop EFI subsystem init if installing TCG2 fails
Up to now we are stopping the EFI subsystem if a TPMv2 exists but the
protocol fails to install. Now that we've switched the config to 'default
y' the sandbox TPM fails, since it doesn't support all the required
capabilities of the protocol.
Not installing the protocol is not catastrophic. If the protocol fails
to install the PCRs will never be extended to the expected values, so
some other entity later in the boot flow will eventually figure it out
and take the necessary actions.
Signed-off-by: Ilias Apalodimas
---
lib/efi_loader/efi_tcg2.c | 16
1 file changed, 12 insertions(+), 4 deletions(-)
diff --git a/lib/efi_loader/efi_tcg2.c b/lib/efi_loader/efi_tcg2.c
index 8f8a26e7b7ae..23b9c3839740 100644
--- a/lib/efi_loader/efi_tcg2.c
+++ b/lib/efi_loader/efi_tcg2.c
@@ -1117,14 +1117,22 @@ efi_status_t efi_tcg2_register(void)
ret = efi_add_protocol(efi_root, &efi_guid_tcg2_protocol,
(void *)&efi_tcg2_protocol);
- if (ret != EFI_SUCCESS) {
- log_err("Cannot install EFI_TCG2_PROTOCOL\n");
+ if (ret != EFI_SUCCESS)
goto fail;
- }
out:
return ret;
fail:
+ log_err("Cannot install EFI_TCG2_PROTOCOL\n");
tcg2_uninit();
- return ret;
+ /*
+* Return EFI_SUCCESS and don't stop the EFI subsystem.
+* That's done for 2 reasons
+* - If the protocol is not installed the PCRs won't be extended. So
+* someone later in the boot flow will notice that and take the
+* necessary actions.
+* - The TPM sandbox is limited and we won't be able to run any efi
+* related tests with TCG2 enabled
+*/
+ return EFI_SUCCESS;
}
--
2.31.0
[BUG] WARNING: SMBIOS table_address overflow 7f752735e020
Hello Simon,
with sandbox_defconfig and 'bootefi hello' I see a message
WARNING: SMBIOS table_address overflow 7f752735e020
The problem is caused by mmap() being passed the same value 0x1000
on each call. Only the first call will give you a low address.
It is this call where we need a low address:
state->ram_buf = os_malloc(state->ram_size);
But before that we call
arch/sandbox/cpu/start.c:447
os_argv = os_malloc(size);
due to your patch b308d9fd18fa ("sandbox: Avoid using malloc() for
system state").
I suggest to move state_init() to the top of the function main().
Why are we using both 'return 1' and 'os_exit(1)' in main?
Can't we just use on of them?
--- a/arch/sandbox/cpu/start.c
+++ b/arch/sandbox/cpu/start.c
@@ -439,6 +439,10 @@ int main(int argc, char *argv[])
int size;
int ret;
+ ret = state_init();
+ if (ret)
+ goto err;
+
/*
* Copy argv[] so that we can pass the arguments in the original
* sequence when resetting the sandbox.
@@ -453,10 +457,6 @@ int main(int argc, char *argv[])
gd = &data;
gd->arch.text_base = os_find_text_base();
- ret = state_init();
- if (ret)
- goto err;
-
state = state_get_current();
if (os_parse_args(state, argc, argv))
return 1;
Best regards
Heinrich
Re: [PATCH v2 3/7] common: integrate crypt-based passwords
Hi Simon,
On 5/11/21 5:27 PM, Simon Glass wrote:
>>
>> [snip]
>>
diff --git a/common/autoboot.c b/common/autoboot.c
index 50ab9281e7..6f55abe388 100644
--- a/common/autoboot.c
+++ b/common/autoboot.c
@@ -316,3 +316,4 @@ static int abortboot_key_sequence(int bootdelay)
if (IS_ENABLED(CONFIG_AUTOBOOT_ENCRYPTION)) {
- if (IS_ENABLED(CONFIG_CRYPT_PW))
+ if (IS_ENABLED(CONFIG_CRYPT_PW) &&
+ env_get_yesno("bootstopusesha256") != 1)
abort = passwd_abort_crypt(etime);
>>>
>>> Yes, and then you can enable both in sandbox and potentially have a
>>> test for your code within the standard sandbox build.
>>
>> What kind of tests do you want to have added? Python based or C based ones?
>>
>> TBH I don't see an easy way (yet) to add more tests than the ones I
>> already added, as enabling AUTOBOOT_KEYED (which is required for both,
>> crypt and sha256) would change the startup behavior of the sandbox...
>
> Here is my idea...we have console monitoring, like this:
>
> console_record_reset();
> run_command("acpi dump rdst", 0);
> ut_assert_nextline("Table 'RDST' not found");
> ut_assert_console_end();
>
> What is needed is the ability to inject console input. We have
> gd->console_in (in console.c) but there is currently no function to
> add input to it. Something similar to console_record_puts() is needed,
> perhaps called console_write_in(), which does a
> membuff_put(&gd->console_in, ...) with some input data (the hash).
> That way the input can be read by sandbox.
>
> Then I think you could write a test like this:
>
> console_record_reset();
> console_write_in(hash_string, strlen(hash_string));
> ut_assertok(autoboot_command(""));
> ut_assert_nextline("whatever indicates success");
> ut_assert_console_end();
OK, that sounds fine, with the only problem that there's no way to
enable the necessary features without also having them enabled in the
autoboot flow!?
i.e. instead of having a single keypress to enable the console of the
sandbox, one would always have to enter the password, or am I missing
something?
Cheers
Steffen
[PATCH] mpc8379erdb: enable DM_USB DM_PCI DM_ETH
From: Sinan Akman
Signed-off-by: Sinan Akman
---
arch/powerpc/cpu/mpc83xx/pci.c| 2 ++
arch/powerpc/dts/mpc8379erdb.dts | 52 +++
board/freescale/mpc837xerdb/mpc837xerdb.c | 11 ++-
configs/MPC837XERDB_defconfig | 18 +--
4 files changed, 73 insertions(+), 10 deletions(-)
diff --git a/arch/powerpc/cpu/mpc83xx/pci.c b/arch/powerpc/cpu/mpc83xx/pci.c
index 5c289d0022..507ab3417b 100644
--- a/arch/powerpc/cpu/mpc83xx/pci.c
+++ b/arch/powerpc/cpu/mpc83xx/pci.c
@@ -27,6 +27,7 @@ DECLARE_GLOBAL_DATA_PTR;
static struct pci_controller pci_hose[MAX_BUSES];
static int pci_num_buses;
+#if !defined(CONFIG_DM_PCI)
static void pci_init_bus(int bus, struct pci_region *reg)
{
volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
@@ -184,6 +185,7 @@ void mpc83xx_pcislave_unlock(int bus)
hose->last_busno = pci_hose_scan(hose);
}
#endif
+#endif /* CONFIG_DM_PCI */
#if defined(CONFIG_OF_LIBFDT)
void ft_pci_setup(void *blob, struct bd_info *bd)
diff --git a/arch/powerpc/dts/mpc8379erdb.dts b/arch/powerpc/dts/mpc8379erdb.dts
index b1881b161c..2e7c8f103c 100644
--- a/arch/powerpc/dts/mpc8379erdb.dts
+++ b/arch/powerpc/dts/mpc8379erdb.dts
@@ -69,6 +69,58 @@
device_type = "ipic";
};
+ usb@23000 {
+ compatible = "fsl-usb2-dr";
+ reg = <0x23000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupt-parent = <&ipic>;
+ interrupts = <38 0x8>;
+ phy_type = "ulpi";
+ };
+
+ enet0: ethernet@24000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ cell-index = <0>;
+ device_type = "network";
+ model = "eTSEC";
+ compatible = "fsl,etsec2";
+ reg = <0x24000 0x1000>;
+ ranges = <0x0 0x24000 0x1000>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupts = <32 0x8 33 0x8 34 0x8>;
+ phy-connection-type = "mii";
+ interrupt-parent = <&ipic>;
+ fixed-link = <1 0 1000 0 0>;
+ phy-handle = <&phy>;
+ fsl,magic-packet;
+
+ mdio@520 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,etsec2-mdio";
+ reg = <0x520 0x20>;
+
+ phy: ethernet-phy@2 {
+ interrupt-parent = <&ipic>;
+ interrupts = <17 0x8>;
+ reg = <0x2>;
+ device_type = "ethernet-phy";
+ };
+ };
+ };
+
+ pci0: pci@e0008300 {
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ device_type = "pci";
+ reg = <0x0 0xe0008300 0x0 0x0fff>;
+ compatible = "fsl,mpc837x-pci";
+ clock-frequency = <0>;
+ };
+
};
};
diff --git a/board/freescale/mpc837xerdb/mpc837xerdb.c
b/board/freescale/mpc837xerdb/mpc837xerdb.c
index 624e92ef9c..66b3d9a465 100644
--- a/board/freescale/mpc837xerdb/mpc837xerdb.c
+++ b/board/freescale/mpc837xerdb/mpc837xerdb.c
@@ -176,7 +176,7 @@ int board_early_init_f(void)
}
#ifdef CONFIG_FSL_ESDHC
-#if !(CONFIG_IS_ENABLED(DM_MMC))
+#if !(CONFIG_IS_ENABLED(DM_MMC) || CONFIG_IS_ENABLED(DM_USB))
int board_mmc_init(struct bd_info *bd)
{
struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR;
@@ -217,6 +217,15 @@ int misc_init_r(void)
return rc;
}
+int board_late_init(void)
+{
+ volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+#ifdef CONFIG_USB
+ clrsetbits_be32(&immap->sysconf.sicrl, SICRL_USB_A, 0x4000);
+#endif
+ return 0;
+}
+
#if defined(CONFIG_OF_BOARD_SETUP)
int ft_board_setup(void *blob, struct bd_info *bd)
diff --git a/configs/MPC837XERDB_defconfig b/configs/MPC837XERDB_defconfig
index 63ce36d533..b6161ca072 100644
--- a/configs/MPC837XERDB_defconfig
+++ b/configs/MPC837XERDB_defconfig
@@ -147,7 +147,9 @@ CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="PCIE"
CONFIG_BOOTDELAY=6
+CONFIG_BOARD_LATE_INIT=y
CONFIG_MISC_INIT_R=y
+CONFIG_PCI_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_I2C=y
@@ -173,16 +175,14 @@ CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_
Re: [PATCH 1/2] reset: Do not return NULL on error for devm_reset_control_get_optional()
Hi Kishon,
On Tue, 11 May 2021 at 00:26, Kishon Vijay Abraham I wrote:
>
> Hi Simon,
>
> On 07/05/21 10:04 pm, Simon Glass wrote:
> > Hi Kishon,
> >
> > On Fri, 7 May 2021 at 05:02, Kishon Vijay Abraham I wrote:
> >>
> >> In order for client to know whether it was able to successfully get a
> >> reset controller or not, do not return NULL on error for
> >> devm_reset_control_get_optional() and
> >> devm_reset_bulk_get_optional_by_node().
> >>
> >> Signed-off-by: Kishon Vijay Abraham I
> >> ---
> >> drivers/reset/reset-uclass.c | 16 ++--
> >> drivers/reset/sandbox-reset-test.c | 2 +-
> >> 2 files changed, 3 insertions(+), 15 deletions(-)
> >>
> >> diff --git a/drivers/reset/reset-uclass.c b/drivers/reset/reset-uclass.c
> >> index ac89eaf098..906f58ce3d 100644
> >> --- a/drivers/reset/reset-uclass.c
> >> +++ b/drivers/reset/reset-uclass.c
> >> @@ -299,12 +299,7 @@ struct reset_ctl *devm_reset_control_get(struct
> >> udevice *dev, const char *id)
> >> struct reset_ctl *devm_reset_control_get_optional(struct udevice *dev,
> >> const char *id)
> >> {
> >> - struct reset_ctl *r = devm_reset_control_get(dev, id);
> >> -
> >> - if (IS_ERR(r))
> >> - return NULL;
> >> -
> >> - return r;
> >> + return devm_reset_control_get(dev, id);
> >> }
> >
> > We need to get some updates to the API (function comments in the
> > header) here. I'm not sure what the intent is.
>
> right, that has to be fixed.
> >
> > I thought these functions were going to return a valid (but possibly
> > empty) reset_ctl always?
>
> I thought about it again and felt it might not be correct to return
> reset_ctl always. The reset control is optional only if the consumer
> node doesn't have populated reset properties.
>
> If we always return valid reset_ctl possibly with it's dev member
> initialized or not initialized, it would not be possible to tell it's
> not initialized because of the absence of reset property or due to some
> other valid error.
reset_valid() should check if dev is NULL or not, like with clock and
GPIO. Is that enough?
Regards,
Simon
Re: [PATCH 3/3] DM: DM_MMC migration is now mandatory for non-SPL
On Wed, Apr 21, 2021 at 03:32:27PM -0400, Tom Rini wrote: > As it has been now two years past the migration deadline, it is required > to have migrated. Remove the check from the Makefile and rework some of > the Kconfig logic slightly to get the functional dependencies of DM_MMC > / BLK right in both the SPL and non-SPL case. > > Signed-off-by: Tom Rini Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH 2/3] ata: Make LIBATA means AHCI is enabled mandatory.
On Wed, Apr 21, 2021 at 03:32:26PM -0400, Tom Rini wrote: > The migration deadline for having LIBATA mean that AHCI is also enabled > was v2019.07. As that has long since passed, adjust the Kconfig > dependencies. > > Signed-off-by: Tom Rini Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH 1/3] boards: Disable CMD_SATA on platforms that no longer have a SATA driver enabled
On Wed, Apr 21, 2021 at 03:32:25PM -0400, Tom Rini wrote: > There are a number of platforms that depend on a SATA driver that has > been converted to require AHCI but the platforms themselves are behind > on other migrations that would make it trivial to enable AHCI. Disable > SATA in these cases. > > Signed-off-by: Tom Rini Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH 0/7] J72xx: R5 SPL DMA support post HSM Rearch
On Mon, May 10, 2021 at 10:54:35PM +0530, Vignesh Raghavendra wrote: > This series add DMA support for R5 SPL on J721e/J7200 SoCs post HSM > Rearch. > > Depends on Tero's base HSM rearch support series. > > Vignesh Raghavendra (7): > mailbox: k3-sec-proxy: Add DM to DMSC communication thread > firmware: ti_sci: Implement GET_RANGE with static data > firmware: ti_sci: Add support for Resoure Management at R5 SPL stage. > ARM: dts: j72xx-r5-common-proc-board: Add DM firmware node > ARM: dts: k3: Add cfg register space for ringacc and udmap > soc: ti: k3-navss-ringacc: Add support for native configuration of > rings > dma: ti: k3-udma: Add support for native configuration of chan/flow > > arch/arm/dts/k3-am654-base-board-u-boot.dtsi | 14 ++ > .../k3-j7200-common-proc-board-u-boot.dtsi| 26 +++ > .../arm/dts/k3-j7200-r5-common-proc-board.dts | 17 ++ > .../k3-j721e-common-proc-board-u-boot.dtsi| 14 ++ > .../arm/dts/k3-j721e-r5-common-proc-board.dts | 18 ++ > .../firmware/ti,j721e-dm-sci.txt | 32 > drivers/dma/ti/k3-udma-u-boot.c | 177 ++ > drivers/dma/ti/k3-udma.c | 42 - > drivers/firmware/ti_sci.c | 107 +++ > drivers/firmware/ti_sci_static_data.h | 92 + > drivers/mailbox/k3-sec-proxy.c| 2 +- > drivers/soc/ti/k3-navss-ringacc-u-boot.c | 61 ++ > drivers/soc/ti/k3-navss-ringacc.c | 36 +++- > 13 files changed, 630 insertions(+), 8 deletions(-) > create mode 100644 doc/device-tree-bindings/firmware/ti,j721e-dm-sci.txt > create mode 100644 drivers/dma/ti/k3-udma-u-boot.c > create mode 100644 drivers/firmware/ti_sci_static_data.h > create mode 100644 drivers/soc/ti/k3-navss-ringacc-u-boot.c Seems fine to me, thanks. -- Tom signature.asc Description: PGP signature
Re: [PATCH] ppc: Remove some SECURE_BOOT defconfigs
On Wed, Apr 21, 2021 at 12:32:46PM -0400, Tom Rini wrote: > These specific configs are missing a number of migrations. In addition, > they are blocking completion of the now-expired DM_MMC migration as it > requires enabling BLK. > > Cc: Priyanka Jain > Cc: Ruchika Gupta > Cc: Sumit Garg > Signed-off-by: Tom Rini Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH v2 3/7] common: integrate crypt-based passwords
Hi Steffen,
On Tue, 11 May 2021 at 09:02, Steffen Jaeckel
wrote:
>
> Hi Simon,
>
> On 5/10/21 10:45 PM, Simon Glass wrote:
> > On Mon, 10 May 2021 at 13:37, Steffen Jaeckel
> > wrote:
>
> [snip]
>
> >> diff --git a/common/autoboot.c b/common/autoboot.c
> >> index 50ab9281e7..6f55abe388 100644
> >> --- a/common/autoboot.c
> >> +++ b/common/autoboot.c
> >> @@ -316,3 +316,4 @@ static int abortboot_key_sequence(int bootdelay)
> >> if (IS_ENABLED(CONFIG_AUTOBOOT_ENCRYPTION)) {
> >> - if (IS_ENABLED(CONFIG_CRYPT_PW))
> >> + if (IS_ENABLED(CONFIG_CRYPT_PW) &&
> >> + env_get_yesno("bootstopusesha256") != 1)
> >> abort = passwd_abort_crypt(etime);
> >
> > Yes, and then you can enable both in sandbox and potentially have a
> > test for your code within the standard sandbox build.
>
> What kind of tests do you want to have added? Python based or C based ones?
>
> TBH I don't see an easy way (yet) to add more tests than the ones I
> already added, as enabling AUTOBOOT_KEYED (which is required for both,
> crypt and sha256) would change the startup behavior of the sandbox...
Here is my idea...we have console monitoring, like this:
console_record_reset();
run_command("acpi dump rdst", 0);
ut_assert_nextline("Table 'RDST' not found");
ut_assert_console_end();
What is needed is the ability to inject console input. We have
gd->console_in (in console.c) but there is currently no function to
add input to it. Something similar to console_record_puts() is needed,
perhaps called console_write_in(), which does a
membuff_put(&gd->console_in, ...) with some input data (the hash).
That way the input can be read by sandbox.
Then I think you could write a test like this:
console_record_reset();
console_write_in(hash_string, strlen(hash_string));
ut_assertok(autoboot_command(""));
ut_assert_nextline("whatever indicates success");
ut_assert_console_end();
Regards,
SImon
[PATCH v2 10/15] ram: k3-j721e: lpddr4_ctl_regs: Fix checkpatch issue for types
Use Linux style u32 instead of uint32_t.
Signed-off-by: Dave Gerlach
---
drivers/ram/k3-j721e/lpddr4_ctl_regs.h | 3028
1 file changed, 1514 insertions(+), 1514 deletions(-)
diff --git a/drivers/ram/k3-j721e/lpddr4_ctl_regs.h
b/drivers/ram/k3-j721e/lpddr4_ctl_regs.h
index 213e56948870..34e6698906ff 100644
--- a/drivers/ram/k3-j721e/lpddr4_ctl_regs.h
+++ b/drivers/ram/k3-j721e/lpddr4_ctl_regs.h
@@ -20,1527 +20,1527 @@
#include "lpddr4_phy_core_macros.h"
typedef struct __attribute__((packed)) lpddr4_ctlregs_s {
- volatile uint32_t DENALI_CTL_0;
- volatile uint32_t DENALI_CTL_1;
- volatile uint32_t DENALI_CTL_2;
- volatile uint32_t DENALI_CTL_3;
- volatile uint32_t DENALI_CTL_4;
- volatile uint32_t DENALI_CTL_5;
- volatile uint32_t DENALI_CTL_6;
- volatile uint32_t DENALI_CTL_7;
- volatile uint32_t DENALI_CTL_8;
- volatile uint32_t DENALI_CTL_9;
- volatile uint32_t DENALI_CTL_10;
- volatile uint32_t DENALI_CTL_11;
- volatile uint32_t DENALI_CTL_12;
- volatile uint32_t DENALI_CTL_13;
- volatile uint32_t DENALI_CTL_14;
- volatile uint32_t DENALI_CTL_15;
- volatile uint32_t DENALI_CTL_16;
- volatile uint32_t DENALI_CTL_17;
- volatile uint32_t DENALI_CTL_18;
- volatile uint32_t DENALI_CTL_19;
- volatile uint32_t DENALI_CTL_20;
- volatile uint32_t DENALI_CTL_21;
- volatile uint32_t DENALI_CTL_22;
- volatile uint32_t DENALI_CTL_23;
- volatile uint32_t DENALI_CTL_24;
- volatile uint32_t DENALI_CTL_25;
- volatile uint32_t DENALI_CTL_26;
- volatile uint32_t DENALI_CTL_27;
- volatile uint32_t DENALI_CTL_28;
- volatile uint32_t DENALI_CTL_29;
- volatile uint32_t DENALI_CTL_30;
- volatile uint32_t DENALI_CTL_31;
- volatile uint32_t DENALI_CTL_32;
- volatile uint32_t DENALI_CTL_33;
- volatile uint32_t DENALI_CTL_34;
- volatile uint32_t DENALI_CTL_35;
- volatile uint32_t DENALI_CTL_36;
- volatile uint32_t DENALI_CTL_37;
- volatile uint32_t DENALI_CTL_38;
- volatile uint32_t DENALI_CTL_39;
- volatile uint32_t DENALI_CTL_40;
- volatile uint32_t DENALI_CTL_41;
- volatile uint32_t DENALI_CTL_42;
- volatile uint32_t DENALI_CTL_43;
- volatile uint32_t DENALI_CTL_44;
- volatile uint32_t DENALI_CTL_45;
- volatile uint32_t DENALI_CTL_46;
- volatile uint32_t DENALI_CTL_47;
- volatile uint32_t DENALI_CTL_48;
- volatile uint32_t DENALI_CTL_49;
- volatile uint32_t DENALI_CTL_50;
- volatile uint32_t DENALI_CTL_51;
- volatile uint32_t DENALI_CTL_52;
- volatile uint32_t DENALI_CTL_53;
- volatile uint32_t DENALI_CTL_54;
- volatile uint32_t DENALI_CTL_55;
- volatile uint32_t DENALI_CTL_56;
- volatile uint32_t DENALI_CTL_57;
- volatile uint32_t DENALI_CTL_58;
- volatile uint32_t DENALI_CTL_59;
- volatile uint32_t DENALI_CTL_60;
- volatile uint32_t DENALI_CTL_61;
- volatile uint32_t DENALI_CTL_62;
- volatile uint32_t DENALI_CTL_63;
- volatile uint32_t DENALI_CTL_64;
- volatile uint32_t DENALI_CTL_65;
- volatile uint32_t DENALI_CTL_66;
- volatile uint32_t DENALI_CTL_67;
- volatile uint32_t DENALI_CTL_68;
- volatile uint32_t DENALI_CTL_69;
- volatile uint32_t DENALI_CTL_70;
- volatile uint32_t DENALI_CTL_71;
- volatile uint32_t DENALI_CTL_72;
- volatile uint32_t DENALI_CTL_73;
- volatile uint32_t DENALI_CTL_74;
- volatile uint32_t DENALI_CTL_75;
- volatile uint32_t DENALI_CTL_76;
- volatile uint32_t DENALI_CTL_77;
- volatile uint32_t DENALI_CTL_78;
- volatile uint32_t DENALI_CTL_79;
- volatile uint32_t DENALI_CTL_80;
- volatile uint32_t DENALI_CTL_81;
- volatile uint32_t DENALI_CTL_82;
- volatile uint32_t DENALI_CTL_83;
- volatile uint32_t DENALI_CTL_84;
- volatile uint32_t DENALI_CTL_85;
- volatile uint32_t DENALI_CTL_86;
- volatile uint32_t DENALI_CTL_87;
- volatile uint32_t DENALI_CTL_88;
- volatile uint32_t DENALI_CTL_89;
- volatile uint32_t DENALI_CTL_90;
- volatile uint32_t DENALI_CTL_91;
- volatile uint32_t DENALI_CTL_92;
- volatile uint32_t DENALI_CTL_93;
- volatile uint32_t DENALI_CTL_94;
- volatile uint32_t DENALI_CTL_95;
- volatile uint32_t DENALI_CTL_96;
- volatile uint32_t DENALI_CTL_97;
- volatile uint32_t DENALI_CTL_98;
- volatile uint32_t DENALI_CTL_99;
- volatile uint32_t DENALI_CTL_100;
- volatile uint32_t DENALI_CTL_101;
- volatile uint32_t DENALI_CTL_102;
- volatile uint32_t DENALI_CTL_103;
- volatile uint32_t DENALI_CTL_104;
- volatile uint32_t DENALI_CTL_105;
- volatile uint32_t DENALI_CTL_106;
- volatile uint32_t DENALI_CTL_107;
- volatile uint32_
[PATCH v2 11/15] ram: k3-j721e: Rename to k3-ddrss
Rename the k3-j721e folder under drivers/ram to k3-ddrss in preparation
of introducing additional support for other platforms to the same
driver.
Signed-off-by: Dave Gerlach
---
drivers/ram/Makefile| 2 +-
drivers/ram/{k3-j721e => k3-ddrss}/Makefile | 0
drivers/ram/{k3-j721e => k3-ddrss}/cps_drv_lpddr4.h | 0
drivers/ram/{k3-j721e => k3-ddrss}/k3-j721e-ddrss.c | 0
drivers/ram/{k3-j721e => k3-ddrss}/lpddr4.c | 0
.../ram/{k3-j721e => k3-ddrss}/lpddr4_address_slice_0_macros.h | 0
drivers/ram/{k3-j721e => k3-ddrss}/lpddr4_ctl_regs.h| 0
drivers/ram/{k3-j721e => k3-ddrss}/lpddr4_data_slice_0_macros.h | 0
drivers/ram/{k3-j721e => k3-ddrss}/lpddr4_data_slice_1_macros.h | 0
drivers/ram/{k3-j721e => k3-ddrss}/lpddr4_data_slice_2_macros.h | 0
drivers/ram/{k3-j721e => k3-ddrss}/lpddr4_data_slice_3_macros.h | 0
.../ram/{k3-j721e => k3-ddrss}/lpddr4_ddr_controller_macros.h | 0
drivers/ram/{k3-j721e => k3-ddrss}/lpddr4_if.h | 0
drivers/ram/{k3-j721e => k3-ddrss}/lpddr4_obj_if.c | 0
drivers/ram/{k3-j721e => k3-ddrss}/lpddr4_obj_if.h | 0
drivers/ram/{k3-j721e => k3-ddrss}/lpddr4_phy_core_macros.h | 0
drivers/ram/{k3-j721e => k3-ddrss}/lpddr4_pi_macros.h | 0
drivers/ram/{k3-j721e => k3-ddrss}/lpddr4_private.h | 0
drivers/ram/{k3-j721e => k3-ddrss}/lpddr4_sanity.h | 0
drivers/ram/{k3-j721e => k3-ddrss}/lpddr4_structs_if.h | 0
20 files changed, 1 insertion(+), 1 deletion(-)
rename drivers/ram/{k3-j721e => k3-ddrss}/Makefile (100%)
rename drivers/ram/{k3-j721e => k3-ddrss}/cps_drv_lpddr4.h (100%)
rename drivers/ram/{k3-j721e => k3-ddrss}/k3-j721e-ddrss.c (100%)
rename drivers/ram/{k3-j721e => k3-ddrss}/lpddr4.c (100%)
rename drivers/ram/{k3-j721e => k3-ddrss}/lpddr4_address_slice_0_macros.h
(100%)
rename drivers/ram/{k3-j721e => k3-ddrss}/lpddr4_ctl_regs.h (100%)
rename drivers/ram/{k3-j721e => k3-ddrss}/lpddr4_data_slice_0_macros.h (100%)
rename drivers/ram/{k3-j721e => k3-ddrss}/lpddr4_data_slice_1_macros.h (100%)
rename drivers/ram/{k3-j721e => k3-ddrss}/lpddr4_data_slice_2_macros.h (100%)
rename drivers/ram/{k3-j721e => k3-ddrss}/lpddr4_data_slice_3_macros.h (100%)
rename drivers/ram/{k3-j721e => k3-ddrss}/lpddr4_ddr_controller_macros.h (100%)
rename drivers/ram/{k3-j721e => k3-ddrss}/lpddr4_if.h (100%)
rename drivers/ram/{k3-j721e => k3-ddrss}/lpddr4_obj_if.c (100%)
rename drivers/ram/{k3-j721e => k3-ddrss}/lpddr4_obj_if.h (100%)
rename drivers/ram/{k3-j721e => k3-ddrss}/lpddr4_phy_core_macros.h (100%)
rename drivers/ram/{k3-j721e => k3-ddrss}/lpddr4_pi_macros.h (100%)
rename drivers/ram/{k3-j721e => k3-ddrss}/lpddr4_private.h (100%)
rename drivers/ram/{k3-j721e => k3-ddrss}/lpddr4_sanity.h (100%)
rename drivers/ram/{k3-j721e => k3-ddrss}/lpddr4_structs_if.h (100%)
diff --git a/drivers/ram/Makefile b/drivers/ram/Makefile
index 209a78c06f52..1806a160f51c 100644
--- a/drivers/ram/Makefile
+++ b/drivers/ram/Makefile
@@ -15,7 +15,7 @@ obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
obj-$(CONFIG_K3_AM654_DDRSS) += k3-am654-ddrss.o
obj-$(CONFIG_ARCH_MEDIATEK) += mediatek/
obj-$(CONFIG_ARCH_ASPEED) += aspeed/
-obj-$(CONFIG_K3_J721E_DDRSS) += k3-j721e/
+obj-$(CONFIG_K3_J721E_DDRSS) += k3-ddrss/
obj-$(CONFIG_IMXRT_SDRAM) += imxrt_sdram.o
diff --git a/drivers/ram/k3-j721e/Makefile b/drivers/ram/k3-ddrss/Makefile
similarity index 100%
rename from drivers/ram/k3-j721e/Makefile
rename to drivers/ram/k3-ddrss/Makefile
diff --git a/drivers/ram/k3-j721e/cps_drv_lpddr4.h
b/drivers/ram/k3-ddrss/cps_drv_lpddr4.h
similarity index 100%
rename from drivers/ram/k3-j721e/cps_drv_lpddr4.h
rename to drivers/ram/k3-ddrss/cps_drv_lpddr4.h
diff --git a/drivers/ram/k3-j721e/k3-j721e-ddrss.c
b/drivers/ram/k3-ddrss/k3-j721e-ddrss.c
similarity index 100%
rename from drivers/ram/k3-j721e/k3-j721e-ddrss.c
rename to drivers/ram/k3-ddrss/k3-j721e-ddrss.c
diff --git a/drivers/ram/k3-j721e/lpddr4.c b/drivers/ram/k3-ddrss/lpddr4.c
similarity index 100%
rename from drivers/ram/k3-j721e/lpddr4.c
rename to drivers/ram/k3-ddrss/lpddr4.c
diff --git a/drivers/ram/k3-j721e/lpddr4_address_slice_0_macros.h
b/drivers/ram/k3-ddrss/lpddr4_address_slice_0_macros.h
similarity index 100%
rename from drivers/ram/k3-j721e/lpddr4_address_slice_0_macros.h
rename to drivers/ram/k3-ddrss/lpddr4_address_slice_0_macros.h
diff --git a/drivers/ram/k3-j721e/lpddr4_ctl_regs.h
b/drivers/ram/k3-ddrss/lpddr4_ctl_regs.h
similarity index 100%
rename from drivers/ram/k3-j721e/lpddr4_ctl_regs.h
rename to drivers/ram/k3-ddrss/lpddr4_ctl_regs.h
diff --git a/drivers/ram/k3-j721e/lpddr4_data_slice_0_macros.h
b/drivers/ram/k3-ddrss/lpddr4_data_slice_0_macros.h
similarity index 100%
rename from drivers/ram/k3-j721e/lpddr4_data_slice_0_macros.h
rename to drivers/ram/k3-ddrss/lpddr4_data_slice_0_macros.h
diff --git a/drivers/ram/k3-j721e/lpddr4_
[PATCH v2 02/15] ram: k3-j721e: lpddr4_address_slice_0_macros: Fix indentation issues
Fix the indentation for certain macros to be consistent with the other macros in the file, as the existing indentation does not make sense in many places. Signed-off-by: Dave Gerlach --- .../k3-j721e/lpddr4_address_slice_0_macros.h | 334 +- 1 file changed, 167 insertions(+), 167 deletions(-) diff --git a/drivers/ram/k3-j721e/lpddr4_address_slice_0_macros.h b/drivers/ram/k3-j721e/lpddr4_address_slice_0_macros.h index bc8059efd15c..6fc9b0f74a84 100644 --- a/drivers/ram/k3-j721e/lpddr4_address_slice_0_macros.h +++ b/drivers/ram/k3-j721e/lpddr4_address_slice_0_macros.h @@ -10,8 +10,8 @@ #ifndef REG_LPDDR4_ADDRESS_SLICE_0_MACROS_H_ #define REG_LPDDR4_ADDRESS_SLICE_0_MACROS_H_ -#define LPDDR4__DENALI_PHY_1024_READ_MASK 0x000107FFU -#define LPDDR4__DENALI_PHY_1024_WRITE_MASK 0x000107FFU +#define LPDDR4__DENALI_PHY_1024_READ_MASK 0x000107FFU +#define LPDDR4__DENALI_PHY_1024_WRITE_MASK 0x000107FFU #define LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_0_MASK 0x07FFU #define LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_0_SHIFT 0U #define LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_0_WIDTH 11U @@ -32,16 +32,16 @@ #define LPDDR4__SC_PHY_ADR_MANUAL_CLEAR_0__REG DENALI_PHY_1024 #define LPDDR4__SC_PHY_ADR_MANUAL_CLEAR_0__FLD LPDDR4__DENALI_PHY_1024__SC_PHY_ADR_MANUAL_CLEAR_0 -#define LPDDR4__DENALI_PHY_1025_READ_MASK 0xU -#define LPDDR4__DENALI_PHY_1025_WRITE_MASK 0xU +#define LPDDR4__DENALI_PHY_1025_READ_MASK 0xU +#define LPDDR4__DENALI_PHY_1025_WRITE_MASK 0xU #define LPDDR4__DENALI_PHY_1025__PHY_ADR_LPBK_RESULT_OBS_0_MASK 0xU #define LPDDR4__DENALI_PHY_1025__PHY_ADR_LPBK_RESULT_OBS_0_SHIFT 0U #define LPDDR4__DENALI_PHY_1025__PHY_ADR_LPBK_RESULT_OBS_0_WIDTH 32U #define LPDDR4__PHY_ADR_LPBK_RESULT_OBS_0__REG DENALI_PHY_1025 #define LPDDR4__PHY_ADR_LPBK_RESULT_OBS_0__FLD LPDDR4__DENALI_PHY_1025__PHY_ADR_LPBK_RESULT_OBS_0 -#define LPDDR4__DENALI_PHY_1026_READ_MASK 0x0FFFU -#define LPDDR4__DENALI_PHY_1026_WRITE_MASK 0x0FFFU +#define LPDDR4__DENALI_PHY_1026_READ_MASK 0x0FFFU +#define LPDDR4__DENALI_PHY_1026_WRITE_MASK 0x0FFFU #define LPDDR4__DENALI_PHY_1026__PHY_ADR_LPBK_ERROR_COUNT_OBS_0_MASK 0xU #define LPDDR4__DENALI_PHY_1026__PHY_ADR_LPBK_ERROR_COUNT_OBS_0_SHIFT 0U #define LPDDR4__DENALI_PHY_1026__PHY_ADR_LPBK_ERROR_COUNT_OBS_0_WIDTH 16U @@ -60,8 +60,8 @@ #define LPDDR4__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_0__REG DENALI_PHY_1026 #define LPDDR4__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_1026__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_0 -#define LPDDR4__DENALI_PHY_1027_READ_MASK 0xFF7F07FFU -#define LPDDR4__DENALI_PHY_1027_WRITE_MASK 0xFF7F07FFU +#define LPDDR4__DENALI_PHY_1027_READ_MASK 0xFF7F07FFU +#define LPDDR4__DENALI_PHY_1027_WRITE_MASK 0xFF7F07FFU #define LPDDR4__DENALI_PHY_1027__PHY_ADR_MASTER_DLY_LOCK_OBS_0_MASK 0x07FFU #define LPDDR4__DENALI_PHY_1027__PHY_ADR_MASTER_DLY_LOCK_OBS_0_SHIFT 0U #define LPDDR4__DENALI_PHY_1027__PHY_ADR_MASTER_DLY_LOCK_OBS_0_WIDTH 11U @@ -80,8 +80,8 @@ #define LPDDR4__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_0__REG DENALI_PHY_1027 #define LPDDR4__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_1027__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_0 -#define LPDDR4__DENALI_PHY_1028_READ_MASK 0x01000707U -#define LPDDR4__DENALI_PHY_1028_WRITE_MASK 0x01000707U +#define LPDDR4__DENALI_PHY_1028_READ_MASK 0x01000707U +#define LPDDR4__DENALI_PHY_1028_WRITE_MASK 0x01000707U #define LPDDR4__DENALI_PHY_1028__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_0_MASK 0x0007U #define LPDDR4__DENALI_PHY_1028__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_0_SHIFT 0U #define LPDDR4__DENALI_PHY_1028__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_0_WIDTH 3U @@ -103,18 +103,18 @@ #define LPDDR4__SC_PHY_ADR_SNAP_OBS_REGS_0__FLD LPDDR4__DENALI_PHY_1028__SC_PHY_ADR_SNAP_OBS_REGS_0 #define LPDDR4__DENALI_PHY_1028__PHY_ADR_TSEL_ENABLE_0_MASK 0x0100U -#define LPDDR4__DENALI_PHY_1028__PHY_ADR_TSEL_ENABLE_0_SHIFT 24U -#define LPDDR4__DENALI_PHY_1028__PHY_ADR_TSEL_ENABLE_0_WIDTH 1U -#define LPDDR4__DENALI_PHY_1028__PHY_ADR_TSEL_ENABLE_0_WOCLR
[PATCH v2 12/15] ram: k3-ddrss: Introduce top-level CONFIG_K3_DDRSS
Create a new CONFIG_K3_DDRSS option to select the common parts of the k3-ddrss driver. Also introduce a choice that depends on the top level option to select CONFIG_K3_J721E_DDRSS for j721e support, and update corresponding Kconfig as required. Signed-off-by: Dave Gerlach --- board/ti/j721e/Kconfig | 4 ++-- drivers/ram/Kconfig| 11 ++- drivers/ram/Makefile | 2 +- 3 files changed, 13 insertions(+), 4 deletions(-) diff --git a/board/ti/j721e/Kconfig b/board/ti/j721e/Kconfig index 2cbe2b2481ac..c28752a658b3 100644 --- a/board/ti/j721e/Kconfig +++ b/board/ti/j721e/Kconfig @@ -23,7 +23,7 @@ config TARGET_J721E_R5_EVM select K3_LOAD_SYSFW select RAM select SPL_RAM - select K3_J721E_DDRSS + select K3_DDRSS imply SYS_K3_SPL_ATF imply TI_I2C_BOARD_DETECT @@ -43,7 +43,7 @@ config TARGET_J7200_R5_EVM select K3_LOAD_SYSFW select RAM select SPL_RAM - select K3_J721E_DDRSS + select K3_DDRSS imply SYS_K3_SPL_ATF imply TI_I2C_BOARD_DETECT diff --git a/drivers/ram/Kconfig b/drivers/ram/Kconfig index a270e13b2651..4e4e7a9632a6 100644 --- a/drivers/ram/Kconfig +++ b/drivers/ram/Kconfig @@ -54,9 +54,16 @@ config K3_AM654_DDRSS config add support for the initialization of the external SDRAM devices connected to DDR subsystem. +config K3_DDRSS + bool "Enable K3 DDRSS support" + depends on RAM + +choice + depends on K3_DDRSS + prompt "K3 DDRSS Arch Support" + config K3_J721E_DDRSS bool "Enable J721E DDRSS support" - depends on RAM help The J721E DDR subsystem comprises DDR controller, DDR PHY and wrapper logic to integrate these blocks in the device. The DDR @@ -65,6 +72,8 @@ config K3_J721E_DDRSS Enabling this config adds support for the DDR memory controller on J721E family of SoCs. +endchoice + config IMXRT_SDRAM bool "Enable i.MXRT SDRAM support" depends on RAM diff --git a/drivers/ram/Makefile b/drivers/ram/Makefile index 1806a160f51c..5a39611349d2 100644 --- a/drivers/ram/Makefile +++ b/drivers/ram/Makefile @@ -15,7 +15,7 @@ obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/ obj-$(CONFIG_K3_AM654_DDRSS) += k3-am654-ddrss.o obj-$(CONFIG_ARCH_MEDIATEK) += mediatek/ obj-$(CONFIG_ARCH_ASPEED) += aspeed/ -obj-$(CONFIG_K3_J721E_DDRSS) += k3-ddrss/ +obj-$(CONFIG_K3_DDRSS) += k3-ddrss/ obj-$(CONFIG_IMXRT_SDRAM) += imxrt_sdram.o -- 2.28.0
[PATCH v2 15/15] ram: k3-ddrss: Enable vtt regulator if present
From: Lokesh Vutla
Attempt to get and enable a vtt regulator if one is provided from the
dts. If we do not find one, continue as not all platforms have this.
Signed-off-by: Nishanth Menon
Signed-off-by: Lokesh Vutla
Signed-off-by: Dave Gerlach
---
drivers/ram/k3-ddrss/k3-ddrss.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/drivers/ram/k3-ddrss/k3-ddrss.c b/drivers/ram/k3-ddrss/k3-ddrss.c
index 8d9e7d2adba0..cb8edcbc154c 100644
--- a/drivers/ram/k3-ddrss/k3-ddrss.c
+++ b/drivers/ram/k3-ddrss/k3-ddrss.c
@@ -15,6 +15,7 @@
#include
#include
#include
+#include
#include "lpddr4_obj_if.h"
#include "lpddr4_if.h"
@@ -40,6 +41,7 @@ struct k3_ddrss_desc {
u32 ddr_freq1;
u32 ddr_freq2;
u32 ddr_fhs_cnt;
+ struct udevice *vtt_supply;
};
static lpddr4_obj *driverdt;
@@ -215,6 +217,18 @@ static int k3_ddrss_power_on(struct k3_ddrss_desc *ddrss)
return ret;
}
+ ret = device_get_supply_regulator(ddrss->dev, "vtt-supply",
+ &ddrss->vtt_supply);
+ if (ret) {
+ dev_dbg(ddrss->dev, "vtt-supply not found.\n");
+ } else {
+ ret = regulator_set_value(ddrss->vtt_supply, 330);
+ if (ret)
+ return ret;
+ dev_dbg(ddrss->dev, "VTT regulator enabled, volt = %d\n",
+ regulator_get_value(ddrss->vtt_supply));
+ }
+
return 0;
}
--
2.28.0
[PATCH v2 00/15] ram: k3-ddrss: Convert k3-j721e to common driver with k3-am64 support
This is v2 of the series to update the existing k3-j721e driver to a
common driver to support both j721e and the new am642 SoC. It renames
drivers/ram/k3-j721e to drivers/ram/k3-ddrss and then introduces a
refactored common driver with the existing j721e support moved to files
named with 32bit and am64 support introduced in files named with 16bit.
Changes since v1:
* Drop unnecessary error macro re-definitions and use normal errno header
* Drop other unnecessary headers that wrap standard kernel headers
* Fixed a few camelCase functions that slipped through
* Fixed clock initialization sequence based on comment from Vignesh
v1: https://lists.denx.de/pipermail/u-boot/2021-May/448716.html
Regards,
Dave
Dave Gerlach (14):
dt-bindings: memory-controller: Add K3 AM64 DDRSS compatible
ram: k3-j721e: lpddr4_address_slice_0_macros: Fix indentation issues
ram: k3-j721e: lpddr4_data_slice_0_macros: Fix indentation issues
ram: k3-j721e: lpddr4_data_slice_1_macros: Fix indentation issues
ram: k3-j721e: lpddr4_data_slice_2_macros: Fix indentation issues
ram: k3-j721e: lpddr4_data_slice_3_macros: Fix indentation issues
ram: k3-j721e: lpddr4_ddr_controller_macros: Fix indentation issues
ram: k3-j721e: lpddr4_phy_core_macros: Fix indentation issues
ram: k3-j721e: lpddr4_pi_macros: Fix indentation issues
ram: k3-j721e: lpddr4_ctl_regs: Fix checkpatch issue for types
ram: k3-j721e: Rename to k3-ddrss
ram: k3-ddrss: Introduce top-level CONFIG_K3_DDRSS
ram: k3-ddrss: Introduce common driver with J7 SoC support
ram: k3-ddrss: Introduce support for AM642 SoCs
Lokesh Vutla (1):
ram: k3-ddrss: Enable vtt regulator if present
board/ti/j721e/Kconfig|4 +-
.../memory-controller/k3-j721e-ddrss.txt |3 +-
drivers/ram/Kconfig | 24 +-
drivers/ram/Makefile |2 +-
drivers/ram/k3-ddrss/16bit/lpddr4_16bit_if.h | 108 +
.../ram/k3-ddrss/16bit/lpddr4_16bit_obj_if.h | 14 +
.../k3-ddrss/16bit/lpddr4_16bit_structs_if.h | 15 +
.../16bit/lpddr4_address_slice_0_macros.h | 624 ++
.../16bit/lpddr4_address_slice_1_macros.h | 624 ++
.../16bit/lpddr4_address_slice_2_macros.h | 624 ++
drivers/ram/k3-ddrss/16bit/lpddr4_ctl_regs.h | 1306 +++
.../k3-ddrss/16bit/lpddr4_ctl_regs_rw_masks.h | 23 +
.../16bit/lpddr4_data_slice_0_macros.h| 2036 +
.../16bit/lpddr4_data_slice_1_macros.h| 2036 +
.../16bit/lpddr4_ddr_controller_macros.h | 6436 ++
.../k3-ddrss/16bit/lpddr4_phy_core_macros.h | 1838
drivers/ram/k3-ddrss/16bit/lpddr4_pi_macros.h | 5784
drivers/ram/k3-ddrss/32bit/lpddr4_32bit_if.h | 91 +
.../ram/k3-ddrss/32bit/lpddr4_32bit_obj_if.h | 14 +
.../k3-ddrss/32bit/lpddr4_32bit_structs_if.h | 15 +
.../32bit}/lpddr4_address_slice_0_macros.h| 343 +-
drivers/ram/k3-ddrss/32bit/lpddr4_ctl_regs.h | 1545
.../k3-ddrss/32bit/lpddr4_ctl_regs_rw_masks.h | 23 +
.../32bit}/lpddr4_data_slice_0_macros.h | 1443 ++-
.../32bit}/lpddr4_data_slice_1_macros.h | 1363 ++-
.../32bit}/lpddr4_data_slice_2_macros.h | 1363 ++-
.../32bit}/lpddr4_data_slice_3_macros.h | 1363 ++-
.../32bit/lpddr4_ddr_controller_macros.h | 7792
.../32bit}/lpddr4_phy_core_macros.h | 1397 ++-
drivers/ram/k3-ddrss/32bit/lpddr4_pi_macros.h | 5396
drivers/ram/k3-ddrss/Makefile | 17 +
drivers/ram/k3-ddrss/cps_drv_lpddr4.h | 102 +
.../k3-j721e-ddrss.c => k3-ddrss/k3-ddrss.c} | 289 +-
drivers/ram/k3-ddrss/lpddr4.c | 1079 +++
drivers/ram/k3-ddrss/lpddr4.h | 73 +
drivers/ram/k3-ddrss/lpddr4_16bit.c | 396 +
drivers/ram/k3-ddrss/lpddr4_16bit.h | 33 +
.../k3-ddrss/lpddr4_16bit_ctl_regs_rw_masks.c | 1309 +++
drivers/ram/k3-ddrss/lpddr4_16bit_sanity.h| 257 +
drivers/ram/k3-ddrss/lpddr4_32bit.c | 302 +
drivers/ram/k3-ddrss/lpddr4_32bit.h | 30 +
.../k3-ddrss/lpddr4_32bit_ctl_regs_rw_masks.c | 1548
drivers/ram/k3-ddrss/lpddr4_32bit_sanity.h| 223 +
drivers/ram/k3-ddrss/lpddr4_if.h | 144 +
drivers/ram/k3-ddrss/lpddr4_obj_if.c | 51 +
drivers/ram/k3-ddrss/lpddr4_obj_if.h | 86 +
.../{k3-j721e => k3-ddrss}/lpddr4_private.h |0
drivers/ram/k3-ddrss/lpddr4_sanity.h | 445 +
drivers/ram/k3-ddrss/lpddr4_structs_if.h | 51 +
drivers/ram/k3-j721e/Makefile |8 -
drivers/ram/k3-j721e/cps_drv_lpddr4.h | 119 -
drivers/ram/k3-j721e/lpddr4.c | 2105 -
drivers/ram/k3-j721e/lpddr4_ctl_regs.h| 1546
.../k3-j721e/lpddr4_ddr_controller_macros.h | 7793 -
drivers/ram/k3-j721e/lpddr4_if.h | 578 --
drivers/ram/k3-j721e/lpddr4_obj_if.c | 55 -
drivers/ram/k3-j721e/lpddr4_obj_if.h | 383 -
drivers/ram/k3-j721e/lpddr4
[PATCH v2 01/15] dt-bindings: memory-controller: Add K3 AM64 DDRSS compatible
Update the k3-ddrss DT binding document to include compatible for k3,am64-ddrss. Signed-off-by: Dave Gerlach --- doc/device-tree-bindings/memory-controller/k3-j721e-ddrss.txt | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/doc/device-tree-bindings/memory-controller/k3-j721e-ddrss.txt b/doc/device-tree-bindings/memory-controller/k3-j721e-ddrss.txt index 873a0e7ae7c8..c4cf26eaa4cf 100644 --- a/doc/device-tree-bindings/memory-controller/k3-j721e-ddrss.txt +++ b/doc/device-tree-bindings/memory-controller/k3-j721e-ddrss.txt @@ -9,7 +9,8 @@ DDRSS device node: == Required properties: -- compatible: Shall be: "ti,j721e-ddrss" +- compatible: Shall be: "ti,j721e-ddrss" for j721e, j7200 + "ti,am64-ddrss" for am642 - reg-namescfg - Map the controller configuration region ctrl_mmr_lp4 - Map LP4 register region in ctrl mmr - reg: Contains the register map per reg-names. -- 2.28.0
Re: [PATCH v2 3/7] common: integrate crypt-based passwords
Hi Simon,
On 5/10/21 10:45 PM, Simon Glass wrote:
> On Mon, 10 May 2021 at 13:37, Steffen Jaeckel
> wrote:
[snip]
>> diff --git a/common/autoboot.c b/common/autoboot.c
>> index 50ab9281e7..6f55abe388 100644
>> --- a/common/autoboot.c
>> +++ b/common/autoboot.c
>> @@ -316,3 +316,4 @@ static int abortboot_key_sequence(int bootdelay)
>> if (IS_ENABLED(CONFIG_AUTOBOOT_ENCRYPTION)) {
>> - if (IS_ENABLED(CONFIG_CRYPT_PW))
>> + if (IS_ENABLED(CONFIG_CRYPT_PW) &&
>> + env_get_yesno("bootstopusesha256") != 1)
>> abort = passwd_abort_crypt(etime);
>
> Yes, and then you can enable both in sandbox and potentially have a
> test for your code within the standard sandbox build.
What kind of tests do you want to have added? Python based or C based ones?
TBH I don't see an easy way (yet) to add more tests than the ones I
already added, as enabling AUTOBOOT_KEYED (which is required for both,
crypt and sha256) would change the startup behavior of the sandbox...
Cheers
Steffen
Pull request: u-boot-imx u-boot-imx-20210502
Hi Tom, please pull from u-boot-imx, thanks ! CI : https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/7368 The following changes since commit 8ddaf943589756442bba21e5be645cd47526d82b: Merge tag 'dm-pull-29apr21' of https://source.denx.de/u-boot/custodians/u-boot-dm (2021-04-29 21:03:38 -0400) are available in the Git repository at: https://gitlab.denx.de/u-boot/custodians/u-boot-imx.git tags/u-boot-imx-20210502 for you to fetch changes up to 7666cccf4f24dd500a9279741a0b64a3f89a7331: ARM:imx:imx8mq-cm: Add support for Ronetix iMX8MQ-CM (2021-05-02 12:46:54 +0200) u-boot-imx-20210502 --- - mx6: fixes for Ventana -local fixes from maintainer - imx7d: Ronetix's iMX7-CM - imx8: Ronetix iMX8MQ-CM Engicam i.Core MX8M Compulab iot-gate-imx8 - Fixes i.MX8 documentation - Fixes phy usage with fec Ian Ray (5): configs: ge: bx50v3: adjust watchdog period configs: ge: use non-persistent environment include: configs: ge: bx50v3: drop USB boot include: configs: ge: simplify default boot command include: configs: ge: avoid shell on boot failure Ilko Iliev (2): imx: Add support for Ronetix's iMX7-CM board ARM:imx:imx8mq-cm: Add support for Ronetix iMX8MQ-CM Jagan Teki (4): arm64: dts: imx8mm: Add common -u-boot.dtsi arm64: dts: imx8mm: Add Engicam i.Core MX8M Mini SoM board: imx8mm: Add Engicam i.Core MX8M Mini EDIMM2.2 Starter Kit board: imx8mm: Add Engicam i.Core MX8M Mini C.TOUCH 2.0 Marek Vasut (1): Makefile: Fix generation of flash.bin u-boot.itb with binman Masami Hiramatsu (1): pci: Update the highest subordinate bus number for bridge setup Priit Laes (1): imx: imx8: Update README with somewhat correct firmware versions Sean Anderson (2): net: fec: Don't use disabled phys net: fec: Only unregister MII bus if we registered it Sebastian Reichel (2): board: ge: bx50v3: fix crystal bit board: ge: bx50v3: add phy reset GPIO Tim Harvey (5): imx: ventana: add delay before reading EEPROM arm: dts: imx6qdl-gw552x.dtsi: fix VBUS supply pci: pci-uclass: Add board_pci_fixup_dev for DM_PCI imx: mkimage_fit_atf: fix file size reporting pci: imx: disable imx6sdl LTSSM upon driver remove Ying-Chun Liu (PaulLiu) (2): arm: dts: add imx8mm-cl-iot-gate dts file arm: imx8m: add support for Compulab iot-gate-imx8 (imx8mm-cl-iot-gate) Makefile | 6 + arch/arm/dts/Makefile | 6 + arch/arm/dts/imx6q-bx50v3-uboot.dtsi | 12 + arch/arm/dts/imx6qdl-gw552x.dtsi | 1 - arch/arm/dts/imx7-cm-u-boot.dtsi | 17 ++ arch/arm/dts/imx7-cm.dts | 432 ++ arch/arm/dts/imx8mm-beacon-kit-u-boot.dtsi | 37 +-- arch/arm/dts/imx8mm-cl-iot-gate-u-boot.dtsi| 255 arch/arm/dts/imx8mm-cl-iot-gate.dts| 553 arch/arm/dts/imx8mm-evk-u-boot.dtsi| 37 +-- arch/arm/dts/imx8mm-icore-mx8mm-ctouch2-u-boot.dtsi| 31 +++ arch/arm/dts/imx8mm-icore-mx8mm-ctouch2.dts| 97 arch/arm/dts/imx8mm-icore-mx8mm-edimm2.2-u-boot.dtsi | 31 +++ arch/arm/dts/imx8mm-icore-mx8mm-edimm2.2.dts | 97 arch/arm/dts/imx8mm-icore-mx8mm-u-boot.dtsi| 27 +++ arch/arm/dts/imx8mm-icore-mx8mm.dtsi | 232 +++ arch/arm/dts/imx8mm-u-boot.dtsi| 39 arch/arm/dts/imx8mm-venice-gw700x-u-boot.dtsi | 35 +-- arch/arm/dts/imx8mm-venice-u-boot.dtsi | 37 +-- arch/arm/dts/imx8mm-verdin-u-boot.dtsi | 38 +-- arch/arm/dts/imx8mq-cm-u-boot.dtsi | 111 + arch/arm/dts/imx8mq-cm.dts | 535 ++ arch/arm/dts/phycore-imx8mm-u-boot.dtsi| 37 +-- arch/arm/mach-imx/imx8m/Kconfig| 42 +++- arch/arm/mach-imx/mkimage_fit_atf.sh | 8 +- arch/arm/mach-imx/mx7/Kconfig | 10 + board/compulab/imx8mm-cl-iot-gate/Kconfig | 12 + board/compulab/imx8mm-cl-iot-gate/MAINTAINERS | 6 + board/compulab/imx8mm-
Re: [PATCH v3 19/20] env: ti: j721e-evm: Add env variable to power on & reset QSGMII PHY in J7200 EVM
On Tue, May 11, 2021 at 07:28:10PM +0530, Kishon Vijay Abraham I wrote:
> Hi Tom,
>
> On 07/05/21 10:44 pm, Tom Rini wrote:
> > On Tue, May 04, 2021 at 04:11:54PM +0530, Kishon Vijay Abraham I wrote:
> >
> >> MAIN CPSW0 requires the PHY to be powered on and reset for QSGMII
> >> operation. Add a env variable to configure driving "0" on ENET_EXP_PWRDN
> >> controlled by GPIO EXPANDER2 (I2C Addr: 0x22), PIN: 17 and driving "1"
> >> on ENET_EXP_RESETZ controlled by GPIO EXPANDER2 (I2C Addr: 0x22),
> >> PIN: 18.
> >>
> >> Signed-off-by: Kishon Vijay Abraham I
> >> Reviewed-by: Suman Anna
> >> ---
> >> include/configs/j721e_evm.h | 16 +++-
> >> 1 file changed, 15 insertions(+), 1 deletion(-)
> >>
> >> diff --git a/include/configs/j721e_evm.h b/include/configs/j721e_evm.h
> >> index b707fc4e89..00d0a18a68 100644
> >> --- a/include/configs/j721e_evm.h
> >> +++ b/include/configs/j721e_evm.h
> >> @@ -139,11 +139,24 @@
> >> #endif /* CONFIG_TARGET_J721E_A72_EVM */
> >>
> >> #ifdef CONFIG_TARGET_J7200_A72_EVM
> >> +#define EXTRA_ENV_CONFIG_MAIN_CPSW0_QSGMII_PHY
> >> \
> >> + "do_main_cpsw0_qsgmii_phyinit=1\0" \
> >
> > When would this be not true?
>
> If the user don't want to use QSGMII, this could be set to false. For
> instance the SERDES in J7200 can be used such that it can be used with
> two protocols at a time. So it can be either PCIe + QSGMII or PCIe +
> USB. So for use cases which require PCIe + USB, this could be set to false.
Then we need to create doc/board/ti/j721e_evm.rst with some general
content and then document the above in there.
> >> + "init_main_cpsw0_qsgmii_phy=gpio set gpio@22_17;" \
> >> + "gpio clear gpio@22_16\0" \
> >> + "main_cpsw0_qsgmii_phyinit="\
> >> + "if test ${do_main_cpsw0_qsgmii_phyinit} -eq 1 && test ${dorprocboot}
> >> -eq 1 && " \
> >> + "test ${boot} = mmc; then " \
> >
> > And why only on mmc?
>
> The current J7200 u-boot code loads firmwares for remote cores only from
> MMC. So if it's not mmc, it's not going to load ethernet firmware and
> hence not required to configure the PHY.
OK. Please make sure this is also part of the documentation. Thanks.
--
Tom
signature.asc
Description: PGP signature
Re: [PATCH v3 19/20] env: ti: j721e-evm: Add env variable to power on & reset QSGMII PHY in J7200 EVM
Hi Tom,
On 07/05/21 10:44 pm, Tom Rini wrote:
> On Tue, May 04, 2021 at 04:11:54PM +0530, Kishon Vijay Abraham I wrote:
>
>> MAIN CPSW0 requires the PHY to be powered on and reset for QSGMII
>> operation. Add a env variable to configure driving "0" on ENET_EXP_PWRDN
>> controlled by GPIO EXPANDER2 (I2C Addr: 0x22), PIN: 17 and driving "1"
>> on ENET_EXP_RESETZ controlled by GPIO EXPANDER2 (I2C Addr: 0x22),
>> PIN: 18.
>>
>> Signed-off-by: Kishon Vijay Abraham I
>> Reviewed-by: Suman Anna
>> ---
>> include/configs/j721e_evm.h | 16 +++-
>> 1 file changed, 15 insertions(+), 1 deletion(-)
>>
>> diff --git a/include/configs/j721e_evm.h b/include/configs/j721e_evm.h
>> index b707fc4e89..00d0a18a68 100644
>> --- a/include/configs/j721e_evm.h
>> +++ b/include/configs/j721e_evm.h
>> @@ -139,11 +139,24 @@
>> #endif /* CONFIG_TARGET_J721E_A72_EVM */
>>
>> #ifdef CONFIG_TARGET_J7200_A72_EVM
>> +#define EXTRA_ENV_CONFIG_MAIN_CPSW0_QSGMII_PHY
>> \
>> +"do_main_cpsw0_qsgmii_phyinit=1\0" \
>
> When would this be not true?
If the user don't want to use QSGMII, this could be set to false. For
instance the SERDES in J7200 can be used such that it can be used with
two protocols at a time. So it can be either PCIe + QSGMII or PCIe +
USB. So for use cases which require PCIe + USB, this could be set to false.
>
>> +"init_main_cpsw0_qsgmii_phy=gpio set gpio@22_17;" \
>> + "gpio clear gpio@22_16\0" \
>> +"main_cpsw0_qsgmii_phyinit="\
>> +"if test ${do_main_cpsw0_qsgmii_phyinit} -eq 1 && test ${dorprocboot}
>> -eq 1 && " \
>> +"test ${boot} = mmc; then " \
>
> And why only on mmc?
The current J7200 u-boot code loads firmwares for remote cores only from
MMC. So if it's not mmc, it's not going to load ethernet firmware and
hence not required to configure the PHY.
>
>> +"run init_main_cpsw0_qsgmii_phy;" \
>> +"fi;\0"
>
> Finally, this feels like something we should be doing in CONFIG_PREBOOT,
> so it's always done, rather than part of seemingly the bootcmd.
>
I'll check on this.
Thanks for reviewing!
Regards
Kishon
Re: Porting u boot for a Qualcomm IPQ4019 based router.
On Tue, May 11, 2021 at 1:18 PM Florence Riker <1460...@gmail.com> wrote:> > Hi, I want to port u boot for a custom-made Qualcomm IPQ4019 based router, > I've finished the dts part but had problems with these files: > > > board/.c > include/configs/.h > > > Since there is no similar board to take reference, I have absolutely no The dragonboard410c and dragonboard820c are both QCom based boards so they would probably be a reasonable starting point. > idea what code should I write to these files. > I've read some of these files for other boards, it seems contains code that > is very device specific > and that leaves me even more confused because I don't know what words; > functions; definitions my device uses. > So, what should I do? > > Thanks for your help.
Re: [PATCH v2 27/28] fs/squashfs: sqfs_read: fragmented files are not supported
Hi all,
Le 08/05/2021 à 23:51, Simon Glass a écrit :
Hi,
On Thu, 4 Feb 2021 at 15:32, João Marcos Costa wrote:
Em qua., 27 de jan. de 2021 às 12:15, Simon Glass escreveu:
Hi Joao,
Hello!
This test works the first time I run it but fails the second time,
since the directory already exists. This makes it necessary to disable
the test for development.
It also uses the wrong quoting style - we have settled on a single
quote by default in U-Boot.
Finally, the tests and some functions need comments about what they do
and what the arguments are.
Please can you take a look?
Absolutely. Excuse me for such a late reply.
Any word on this please? Have you been able to repeat this?
Yes, for me, reading fragmented files doesn't work.
The test "test_sqfs_load" is OK because it only tests the file length not its
content.
I've written a patch to check if the file is corrupted or not, and it fails :
./test/py/test.py --bd sandbox --build -k test_sqfs_load -v
[...]
AssertionError: assert not 'ERROR' in 'crc32 for 0100 ... 010013eb ==>
df8e6fe2 != d1522690 ** ERROR **'
[...]
Here's the patch onto v2021.07-rc2 :
--8<
Subject: [PATCH] test/py: SquashFS: Check if loaded file is corrupted
After loading the file in memory, its content should be checked for
errors.
Signed-off-by: Richard Genoud
---
test/py/tests/test_fs/test_squashfs/sqfs_common.py| 5 -
test/py/tests/test_fs/test_squashfs/test_sqfs_load.py | 6 +-
2 files changed, 9 insertions(+), 2 deletions(-)
diff --git a/test/py/tests/test_fs/test_squashfs/sqfs_common.py
b/test/py/tests/test_fs/test_squashfs/sqfs_common.py
index c96f92c1d8f..a7673c73762 100644
--- a/test/py/tests/test_fs/test_squashfs/sqfs_common.py
+++ b/test/py/tests/test_fs/test_squashfs/sqfs_common.py
@@ -6,6 +6,7 @@ import os
import random
import string
import subprocess
+import zlib
def sqfs_get_random_letters(size):
letters = []
@@ -19,12 +20,14 @@ def sqfs_generate_file(path, size):
file = open(path, "w")
file.write(content)
file.close()
+return zlib.crc32(content.encode())
class Compression:
def __init__(self, name, files, sizes, block_size = 4096):
self.name = name
self.files = files
self.sizes = sizes
+self.crc = []
self.mksquashfs_opts = " -b " + str(block_size) + " -comp " + self.name
def add_opt(self, opt):
@@ -34,7 +37,7 @@ class Compression:
src = os.path.join(build_dir, "sqfs_src/")
os.mkdir(src)
for (f, s) in zip(self.files, self.sizes):
-sqfs_generate_file(src + f, s)
+self.crc.append(sqfs_generate_file(src + f, s))
# the symbolic link always targets the first file
os.symlink(self.files[0], src + "sym")
diff --git a/test/py/tests/test_fs/test_squashfs/test_sqfs_load.py
b/test/py/tests/test_fs/test_squashfs/test_sqfs_load.py
index 9e900623846..2ab4660036e 100644
--- a/test/py/tests/test_fs/test_squashfs/test_sqfs_load.py
+++ b/test/py/tests/test_fs/test_squashfs/test_sqfs_load.py
@@ -4,6 +4,7 @@
import os
import pytest
+import zlib
from sqfs_common import *
@pytest.mark.boardspec('sandbox')
@@ -14,6 +15,7 @@ from sqfs_common import *
def test_sqfs_load(u_boot_console):
build_dir = u_boot_console.config.build_dir
command = "sqfsload host 0 $kernel_addr_r "
+sum_command = "crc32 -v $kernel_addr_r $filesize "
for opt in comp_opts:
# generate and load the squashfs image
@@ -30,10 +32,12 @@ def test_sqfs_load(u_boot_console):
output = u_boot_console.run_command(command + "xxx")
assert "File not found." in output
-for (f, s) in zip(opt.files, opt.sizes):
+for (f, s, c) in zip(opt.files, opt.sizes, opt.crc):
try:
output = u_boot_console.run_command(command + f)
assert str(s) in output
+output = u_boot_console.run_command(sum_command + format(c,
'08x'))
+assert not 'ERROR' in output
except:
assert False
opt.cleanup(build_dir)
--
2.20.1
Re: [PATCH] riscv: Split SiFive CLINT support between SPL and U-Boot proper
On 5/11/21 8:04 AM, Bin Meng wrote:
At present there is only one Kconfig option CONFIG_SIFIVE_CLINT to
control the enabling of SiFive CLINT support in both SPL (M-mode)
and U-Boot proper (S-mode). So for a typical SPL config that the
SiFive CLINT driver is enabled in both SPL and U-Boot proper, that
means the S-mode U-Boot tries to access the memory-mapped CLINT
registers directly, instead of the normal 'rdtime' instruction.
This was not a problem before, as the hardware does not forbid the
access from S-mode. However this becomes an issue now with OpenSBI
commit 8b569803475e ("lib: utils/sys: Add CLINT memregion in the root domain")
that the SiFive CLINT register space is protected by PMP for M-mode
access only. U-Boot proper does not boot any more with the latest
OpenSBI, that access exceptions are fired forever from U-Boot when
trying to read the timer value via the SiFive CLINT driver in U-Boot.
To solve this, we need to split current SiFive CLINT support between
SPL and U-Boot proper, using 2 separate Kconfig options.
Signed-off-by: Bin Meng
---
arch/riscv/Kconfig | 9 -
arch/riscv/cpu/fu540/Kconfig | 2 +-
arch/riscv/cpu/generic/Kconfig | 3 ++-
arch/riscv/include/asm/global_data.h | 2 +-
arch/riscv/lib/Makefile | 2 +-
drivers/timer/Makefile | 2 +-
6 files changed, 14 insertions(+), 6 deletions(-)
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 3f221dccdb..82e10da11e 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -158,7 +158,14 @@ config DMA_ADDR_T_64BIT
config SIFIVE_CLINT
bool
- depends on RISCV_MMODE || SPL_RISCV_MMODE
+ depends on RISCV_MMODE
+ help
+ The SiFive CLINT block holds memory-mapped control and status
registers
+ associated with software and timer interrupts.
+
+config SPL_SIFIVE_CLINT
+ bool
+ depends on SPL_RISCV_MMODE
help
The SiFive CLINT block holds memory-mapped control and status
registers
associated with software and timer interrupts.
diff --git a/arch/riscv/cpu/fu540/Kconfig b/arch/riscv/cpu/fu540/Kconfig
index 616b25650f..dcf099447b 100644
--- a/arch/riscv/cpu/fu540/Kconfig
+++ b/arch/riscv/cpu/fu540/Kconfig
@@ -11,7 +11,7 @@ config SIFIVE_FU540
imply CPU
imply CPU_RISCV
imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE)
- imply SIFIVE_CLINT if (RISCV_MMODE || SPL_RISCV_MMODE)
+ imply SPL_SIFIVE_CLINT
imply CMD_CPU
imply SPL_CPU
imply SPL_OPENSBI
diff --git a/arch/riscv/cpu/generic/Kconfig b/arch/riscv/cpu/generic/Kconfig
index a4934bb957..e025134b23 100644
--- a/arch/riscv/cpu/generic/Kconfig
+++ b/arch/riscv/cpu/generic/Kconfig
@@ -9,7 +9,8 @@ config GENERIC_RISCV
imply CPU
imply CPU_RISCV
imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE)
- imply SIFIVE_CLINT if (RISCV_MMODE || SPL_RISCV_MMODE)
+ imply SIFIVE_CLINT if RISCV_MMODE
+ imply SPL_SIFIVE_CLINT if SPL_RISCV_MMODE
imply CMD_CPU
imply SPL_CPU
imply SPL_OPENSBI
diff --git a/arch/riscv/include/asm/global_data.h
b/arch/riscv/include/asm/global_data.h
index d3a0b1d221..095484a635 100644
--- a/arch/riscv/include/asm/global_data.h
+++ b/arch/riscv/include/asm/global_data.h
@@ -18,7 +18,7 @@
struct arch_global_data {
long boot_hart; /* boot hart id */
phys_addr_t firmware_fdt_addr;
-#ifdef CONFIG_SIFIVE_CLINT
+#if CONFIG_IS_ENABLED(SIFIVE_CLINT)
void __iomem *clint;/* clint base address */
#endif
#ifdef CONFIG_ANDES_PLIC
diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile
index d08cbe9b79..c4cc41434b 100644
--- a/arch/riscv/lib/Makefile
+++ b/arch/riscv/lib/Makefile
@@ -11,7 +11,7 @@ obj-$(CONFIG_CMD_BOOTI) += bootm.o image.o
obj-$(CONFIG_CMD_GO) += boot.o
obj-y += cache.o
ifeq ($(CONFIG_$(SPL_)RISCV_MMODE),y)
-obj-$(CONFIG_SIFIVE_CLINT) += sifive_clint.o
+obj-$(CONFIG_$(SPL_)SIFIVE_CLINT) += sifive_clint.o
obj-$(CONFIG_ANDES_PLIC) += andes_plic.o
else
obj-$(CONFIG_SBI) += sbi.o
diff --git a/drivers/timer/Makefile b/drivers/timer/Makefile
index eb5c48cc6c..2ebdeab0ce 100644
--- a/drivers/timer/Makefile
+++ b/drivers/timer/Makefile
@@ -19,7 +19,7 @@ obj-$(CONFIG_RENESAS_OSTM_TIMER) += ostm_timer.o
obj-$(CONFIG_RISCV_TIMER) += riscv_timer.o
obj-$(CONFIG_ROCKCHIP_TIMER) += rockchip_timer.o
obj-$(CONFIG_SANDBOX_TIMER) += sandbox_timer.o
-obj-$(CONFIG_SIFIVE_CLINT) += sifive_clint_timer.o
+obj-$(CONFIG_$(SPL_)SIFIVE_CLINT) += sifive_clint_timer.o
obj-$(CONFIG_STI_TIMER) += sti-timer.o
obj-$(CONFIG_STM32_TIMER) += stm32_timer.o
obj-$(CONFIG_X86_TSC_TIMER) += tsc_timer.o
Reviewed-by: Sean Anderson
Re: BeagleBone Green Wireless - serial debug port hangs after sending u-boot-spl.bin (since v2021.01)
On Tue, May 11, 2021 at 04:04:34PM +0800, Darren Ng wrote:
> On Sat, May 8, 2021 at 1:40 AM Tom Rini wrote:
>
> > On Sat, May 08, 2021 at 12:02:21AM +0800, Darren Ng wrote:
> >
> > > (Hello, from a U-Boot NOOB.)
> > >
> > > Issue
> > > -
> > > After sending u-boot-spl.bin with xmodem, the serial debug port seems to
> > > hang.
> > > Neither "...U-Boot SPL...\n...\nTrying to boot from UART..."
> > > nor "CCC..." shows up in minicom.
> > > Always 0% if I try sending u-boot.img with xmodem anyway.
> > >
> > > Target Device
> > > -
> > > Seeed Studio BeagleBone® Green Wireless
> > > https://seeeddoc.github.io/Beaglebone_green_wireless/
> > >
> > https://wiki.seeedstudio.com/BeagleBone_Green_Wireless/#hardware-overview
> > >
> > https://source.denx.de/u-boot/u-boot/-/commits/master/configs/am335x_boneblack_vboot_defconfig
> > >
> > > Matrix
> > > --
> > > This issue applies to tags ever since v2021.01. In the following table:
> > > (x) - This issue applies.
> > > (O) - I can send both u-boot-spl.bin and u-boot.img
> > > then execute u-boot commands without trouble.
> > > --
> > > tag result
> > > --
> > > v2021.07-rc1 (x) hangs
> > > v2021.04 (x) hangs
> > > v2021.01 (x) hangs
> > > v2020.10 (O) success
> >
> > It looks like something broke between v2020.10 and v2021.01 then. Since
> > you have a testcase, using "git bisect" should help figure out which
> > exact commit broke things.
> >
> > --
> > Tom
> >
>
> ("reply all" instead of "reply")
>
> v2021.04 running successfully with am335x_evm_defconfig(AED) now
OK, that's good.
> > commit 8fa7f65dd02c176ee6021eaf40114560b8954ba2
> > Author: Faiz Abbas
> > Date: Thu Jan 17 15:44:06 2019 +0530
> >
> > configs: Remove am335x_boneblack_defconfig
> >
> > The am335x_evm_defconfig supports all am335x_boneblack variants.
> Remove
> > the redundant am335x_boneblack_defconfig.
> >
> > Signed-off-by: Faiz Abbas
> > Reviewed-by: Tom Rini
> >
> > D configs/am335x_boneblack_defconfig
>
> According to the commit log above, a previous
> am335x_boneblack_defconfig(ABD)
> is removed in favor of am335x_evm_defconfig(AED)
Yes, am335x_evm_defconfig supports a wide range of am335x-based
platforms, that have an i2c EEPROM on them to identify which board it is
at run-time.
> However there is a am335x_boneblack_vboot_defconfig(ABVD) in the tree,
> which is what I have failed with.
>
> What does am335x_boneblack_vboot_defconfig(ABVD) do?
> What is the meaning of "_vboot_"?
> Is that "Verified Boot" as of
> <
> https://source.denx.de/u-boot/u-boot/-/blob/master/test/py/tests/test_vboot.py
> >?
> If so, do I need it?
Correct, it's an example of using that verified boot and you likely do
not need to use it.
--
Tom
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Description: PGP signature
Re: [PATCH] configs: ti: enable TFTP_SIZE
On 11/05/2021 15:07, Tom Rini wrote:
On Tue, May 11, 2021 at 10:40:15AM +0300, Tero Kristo wrote:
This fits the TFTP progress bar on single line based on the size of the
file being downloaded, reducing unnecessary spam and also making it
easier to track the download progress.
Signed-off-by: Tero Kristo
---
include/configs/ti_armv7_common.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/configs/ti_armv7_common.h
b/include/configs/ti_armv7_common.h
index f13e9e5264..f40089a3fd 100644
--- a/include/configs/ti_armv7_common.h
+++ b/include/configs/ti_armv7_common.h
@@ -205,6 +205,8 @@
"run netloadfdt; " \
"run netargs; " \
"bootz ${loadaddr} - ${fdtaddr}\0"
+
+#define CONFIG_TFTP_TSIZE
#else
#define NETARGS ""
#endif
That's pretty handy. Can you please convert it to Kconfig (it should go
in net/Kconfig) and default y if ARCH_OMAP2PLUS should be fine. Thanks.
Yea, I can take a shot at that.
-Tero
Re: [ANN] U-Boot v2021.07-rc2 released
On Tue, May 11, 2021 at 08:28:32AM -0400, Trevor Woerner wrote: > On Mon, May 10, 2021 at 5:06 PM Tom Rini wrote: > > > and shortly after this I will pull in the patches > > needed to enforce the DM migrations that are now 2 years past their > > warning dates. > > > > Could you please be more specific with respect to which DM subsystem(s) > migrations are targeted next? Sure. The deadline of v2019.07 was given for migration of CONFIG_DM_USB, CONFIG_AHCI, CONFIG_DM_PCI, CONFIG_DM_VIDEO and CONFIG_DM_SPI_FLASH. Of those, I think I actually do have AHCI done as USB, MMC and AHCI all also require enabling BLK, iirc. All of these (as well as the v2021.10 one of WDT and v2023.01 of DM itself) have been generating build warnings for a long long time. -- Tom signature.asc Description: PGP signature
Re: [ANN] U-Boot v2021.07-rc2 released
On Mon, May 10, 2021 at 5:06 PM Tom Rini wrote: > and shortly after this I will pull in the patches > needed to enforce the DM migrations that are now 2 years past their > warning dates. > Could you please be more specific with respect to which DM subsystem(s) migrations are targeted next?
Porting u boot for a Qualcomm IPQ4019 based router.
Hi, I want to port u boot for a custom-made Qualcomm IPQ4019 based router, I've finished the dts part but had problems with these files: board/.c include/configs/.h Since there is no similar board to take reference, I have absolutely no idea what code should I write to these files. I've read some of these files for other boards, it seems contains code that is very device specific and that leaves me even more confused because I don't know what words; functions; definitions my device uses. So, what should I do? Thanks for your help.
Re: [PATCH] configs: ti: enable TFTP_SIZE
On Tue, May 11, 2021 at 10:40:15AM +0300, Tero Kristo wrote:
> This fits the TFTP progress bar on single line based on the size of the
> file being downloaded, reducing unnecessary spam and also making it
> easier to track the download progress.
>
> Signed-off-by: Tero Kristo
> ---
> include/configs/ti_armv7_common.h | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/include/configs/ti_armv7_common.h
> b/include/configs/ti_armv7_common.h
> index f13e9e5264..f40089a3fd 100644
> --- a/include/configs/ti_armv7_common.h
> +++ b/include/configs/ti_armv7_common.h
> @@ -205,6 +205,8 @@
> "run netloadfdt; " \
> "run netargs; " \
> "bootz ${loadaddr} - ${fdtaddr}\0"
> +
> +#define CONFIG_TFTP_TSIZE
> #else
> #define NETARGS ""
> #endif
That's pretty handy. Can you please convert it to Kconfig (it should go
in net/Kconfig) and default y if ARCH_OMAP2PLUS should be fine. Thanks.
--
Tom
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Description: PGP signature
[PATCH] riscv: Split SiFive CLINT support between SPL and U-Boot proper
At present there is only one Kconfig option CONFIG_SIFIVE_CLINT to
control the enabling of SiFive CLINT support in both SPL (M-mode)
and U-Boot proper (S-mode). So for a typical SPL config that the
SiFive CLINT driver is enabled in both SPL and U-Boot proper, that
means the S-mode U-Boot tries to access the memory-mapped CLINT
registers directly, instead of the normal 'rdtime' instruction.
This was not a problem before, as the hardware does not forbid the
access from S-mode. However this becomes an issue now with OpenSBI
commit 8b569803475e ("lib: utils/sys: Add CLINT memregion in the root domain")
that the SiFive CLINT register space is protected by PMP for M-mode
access only. U-Boot proper does not boot any more with the latest
OpenSBI, that access exceptions are fired forever from U-Boot when
trying to read the timer value via the SiFive CLINT driver in U-Boot.
To solve this, we need to split current SiFive CLINT support between
SPL and U-Boot proper, using 2 separate Kconfig options.
Signed-off-by: Bin Meng
---
arch/riscv/Kconfig | 9 -
arch/riscv/cpu/fu540/Kconfig | 2 +-
arch/riscv/cpu/generic/Kconfig | 3 ++-
arch/riscv/include/asm/global_data.h | 2 +-
arch/riscv/lib/Makefile | 2 +-
drivers/timer/Makefile | 2 +-
6 files changed, 14 insertions(+), 6 deletions(-)
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 3f221dccdb..82e10da11e 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -158,7 +158,14 @@ config DMA_ADDR_T_64BIT
config SIFIVE_CLINT
bool
- depends on RISCV_MMODE || SPL_RISCV_MMODE
+ depends on RISCV_MMODE
+ help
+ The SiFive CLINT block holds memory-mapped control and status
registers
+ associated with software and timer interrupts.
+
+config SPL_SIFIVE_CLINT
+ bool
+ depends on SPL_RISCV_MMODE
help
The SiFive CLINT block holds memory-mapped control and status
registers
associated with software and timer interrupts.
diff --git a/arch/riscv/cpu/fu540/Kconfig b/arch/riscv/cpu/fu540/Kconfig
index 616b25650f..dcf099447b 100644
--- a/arch/riscv/cpu/fu540/Kconfig
+++ b/arch/riscv/cpu/fu540/Kconfig
@@ -11,7 +11,7 @@ config SIFIVE_FU540
imply CPU
imply CPU_RISCV
imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE)
- imply SIFIVE_CLINT if (RISCV_MMODE || SPL_RISCV_MMODE)
+ imply SPL_SIFIVE_CLINT
imply CMD_CPU
imply SPL_CPU
imply SPL_OPENSBI
diff --git a/arch/riscv/cpu/generic/Kconfig b/arch/riscv/cpu/generic/Kconfig
index a4934bb957..e025134b23 100644
--- a/arch/riscv/cpu/generic/Kconfig
+++ b/arch/riscv/cpu/generic/Kconfig
@@ -9,7 +9,8 @@ config GENERIC_RISCV
imply CPU
imply CPU_RISCV
imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE)
- imply SIFIVE_CLINT if (RISCV_MMODE || SPL_RISCV_MMODE)
+ imply SIFIVE_CLINT if RISCV_MMODE
+ imply SPL_SIFIVE_CLINT if SPL_RISCV_MMODE
imply CMD_CPU
imply SPL_CPU
imply SPL_OPENSBI
diff --git a/arch/riscv/include/asm/global_data.h
b/arch/riscv/include/asm/global_data.h
index d3a0b1d221..095484a635 100644
--- a/arch/riscv/include/asm/global_data.h
+++ b/arch/riscv/include/asm/global_data.h
@@ -18,7 +18,7 @@
struct arch_global_data {
long boot_hart; /* boot hart id */
phys_addr_t firmware_fdt_addr;
-#ifdef CONFIG_SIFIVE_CLINT
+#if CONFIG_IS_ENABLED(SIFIVE_CLINT)
void __iomem *clint;/* clint base address */
#endif
#ifdef CONFIG_ANDES_PLIC
diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile
index d08cbe9b79..c4cc41434b 100644
--- a/arch/riscv/lib/Makefile
+++ b/arch/riscv/lib/Makefile
@@ -11,7 +11,7 @@ obj-$(CONFIG_CMD_BOOTI) += bootm.o image.o
obj-$(CONFIG_CMD_GO) += boot.o
obj-y += cache.o
ifeq ($(CONFIG_$(SPL_)RISCV_MMODE),y)
-obj-$(CONFIG_SIFIVE_CLINT) += sifive_clint.o
+obj-$(CONFIG_$(SPL_)SIFIVE_CLINT) += sifive_clint.o
obj-$(CONFIG_ANDES_PLIC) += andes_plic.o
else
obj-$(CONFIG_SBI) += sbi.o
diff --git a/drivers/timer/Makefile b/drivers/timer/Makefile
index eb5c48cc6c..2ebdeab0ce 100644
--- a/drivers/timer/Makefile
+++ b/drivers/timer/Makefile
@@ -19,7 +19,7 @@ obj-$(CONFIG_RENESAS_OSTM_TIMER) += ostm_timer.o
obj-$(CONFIG_RISCV_TIMER) += riscv_timer.o
obj-$(CONFIG_ROCKCHIP_TIMER) += rockchip_timer.o
obj-$(CONFIG_SANDBOX_TIMER)+= sandbox_timer.o
-obj-$(CONFIG_SIFIVE_CLINT) += sifive_clint_timer.o
+obj-$(CONFIG_$(SPL_)SIFIVE_CLINT) += sifive_clint_timer.o
obj-$(CONFIG_STI_TIMER)+= sti-timer.o
obj-$(CONFIG_STM32_TIMER) += stm32_timer.o
obj-$(CONFIG_X86_TSC_TIMER)+= tsc_timer.o
--
2.25.1
Re: [PATCH v4] efi_loader: Fix Kconfig for EFI_TCG2 protocol
On 11.05.21 13:40, Ilias Apalodimas wrote: > EFI_TCG2 depends not only on TPMv2 but also on the underlying algorithms. > So select the missing SHA1, SHA256, SHA384 and SHA512 we currently support > > Reported-by: Michal Simek > Signed-off-by: Ilias Apalodimas I will add the default=y when merging as discussed online. Reviewed-by: Heinrich Schuchardt > --- > changes since v3: > - add multiple select lines > changes since v2: > - remove 'on' after select > changes since v1: > - use 'select' instead of 'depend' > lib/efi_loader/Kconfig | 4 > 1 file changed, 4 insertions(+) > > diff --git a/lib/efi_loader/Kconfig b/lib/efi_loader/Kconfig > index 0b99d7c7749b..9a5a0334ad45 100644 > --- a/lib/efi_loader/Kconfig > +++ b/lib/efi_loader/Kconfig > @@ -301,6 +301,10 @@ config EFI_RNG_PROTOCOL > config EFI_TCG2_PROTOCOL > bool "EFI_TCG2_PROTOCOL support" > depends on TPM_V2 > + select SHA1 > + select SHA256 > + select SHA384 > + select SHA512 > help > Provide a EFI_TCG2_PROTOCOL implementation using the TPM hardware > of the platform. >
[PATCH v4] efi_loader: Fix Kconfig for EFI_TCG2 protocol
EFI_TCG2 depends not only on TPMv2 but also on the underlying algorithms. So select the missing SHA1, SHA256, SHA384 and SHA512 we currently support Reported-by: Michal Simek Signed-off-by: Ilias Apalodimas --- changes since v3: - add multiple select lines changes since v2: - remove 'on' after select changes since v1: - use 'select' instead of 'depend' lib/efi_loader/Kconfig | 4 1 file changed, 4 insertions(+) diff --git a/lib/efi_loader/Kconfig b/lib/efi_loader/Kconfig index 0b99d7c7749b..9a5a0334ad45 100644 --- a/lib/efi_loader/Kconfig +++ b/lib/efi_loader/Kconfig @@ -301,6 +301,10 @@ config EFI_RNG_PROTOCOL config EFI_TCG2_PROTOCOL bool "EFI_TCG2_PROTOCOL support" depends on TPM_V2 + select SHA1 + select SHA256 + select SHA384 + select SHA512 help Provide a EFI_TCG2_PROTOCOL implementation using the TPM hardware of the platform. -- 2.31.0
[PATCH v3] efi_loader: Fix Kconfig for EFI_TCG2 protocol
EFI_TCG2 depends not only on TPMv2 but also on the underlying algorithms. So select the missing SHA1, SHA256, SHA384 and SHA512 we currently support Reported-by: Michal Simek Signed-off-by: Ilias Apalodimas --- changes since v1: - use 'select' instead of 'depend' changes since v2: - remove 'on' after select lib/efi_loader/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/lib/efi_loader/Kconfig b/lib/efi_loader/Kconfig index 0b99d7c7749b..4acc0d14e4cc 100644 --- a/lib/efi_loader/Kconfig +++ b/lib/efi_loader/Kconfig @@ -301,6 +301,7 @@ config EFI_RNG_PROTOCOL config EFI_TCG2_PROTOCOL bool "EFI_TCG2_PROTOCOL support" depends on TPM_V2 + select SHA1 && SHA256 && SHA384 && SHA512 help Provide a EFI_TCG2_PROTOCOL implementation using the TPM hardware of the platform. -- 2.31.0
Re: [PATCH v2] efi_loader: Fix Kconfig for EFI_TCG2 protocol
doh yea, forgot to delete the 'on' from depends. Let me send a v3 On Tue, 11 May 2021 at 14:03, Michal Simek wrote: > > > > On 5/11/21 12:57 PM, Ilias Apalodimas wrote: > > EFI_TCG2 depends not only on TPMv2 but also on the underlying algorithms. > > So select the missing SHA1, SHA256, SHA384 and SHA512 we currently support > > > > Reported-by: Michal Simek > > Signed-off-by: Ilias Apalodimas > > --- > > Changes since v1: > > - use 'select' instead of 'depends' > > lib/efi_loader/Kconfig | 1 + > > 1 file changed, 1 insertion(+) > > > > diff --git a/lib/efi_loader/Kconfig b/lib/efi_loader/Kconfig > > index 0b99d7c7749b..660236c1fc20 100644 > > --- a/lib/efi_loader/Kconfig > > +++ b/lib/efi_loader/Kconfig > > @@ -301,6 +301,7 @@ config EFI_RNG_PROTOCOL > > config EFI_TCG2_PROTOCOL > > bool "EFI_TCG2_PROTOCOL support" > > depends on TPM_V2 > > + select on SHA1 && SHA256 && SHA384 && SHA512 > > it should be just select. > > M > > > help > > Provide a EFI_TCG2_PROTOCOL implementation using the TPM hardware > > of the platform. > >
Re: [PATCH v2] efi_loader: Fix Kconfig for EFI_TCG2 protocol
On 5/11/21 12:57 PM, Ilias Apalodimas wrote: > EFI_TCG2 depends not only on TPMv2 but also on the underlying algorithms. > So select the missing SHA1, SHA256, SHA384 and SHA512 we currently support > > Reported-by: Michal Simek > Signed-off-by: Ilias Apalodimas > --- > Changes since v1: > - use 'select' instead of 'depends' > lib/efi_loader/Kconfig | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/lib/efi_loader/Kconfig b/lib/efi_loader/Kconfig > index 0b99d7c7749b..660236c1fc20 100644 > --- a/lib/efi_loader/Kconfig > +++ b/lib/efi_loader/Kconfig > @@ -301,6 +301,7 @@ config EFI_RNG_PROTOCOL > config EFI_TCG2_PROTOCOL > bool "EFI_TCG2_PROTOCOL support" > depends on TPM_V2 > + select on SHA1 && SHA256 && SHA384 && SHA512 it should be just select. M > help > Provide a EFI_TCG2_PROTOCOL implementation using the TPM hardware > of the platform. >
[PATCH v2] efi_loader: Fix Kconfig for EFI_TCG2 protocol
EFI_TCG2 depends not only on TPMv2 but also on the underlying algorithms. So select the missing SHA1, SHA256, SHA384 and SHA512 we currently support Reported-by: Michal Simek Signed-off-by: Ilias Apalodimas --- Changes since v1: - use 'select' instead of 'depends' lib/efi_loader/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/lib/efi_loader/Kconfig b/lib/efi_loader/Kconfig index 0b99d7c7749b..660236c1fc20 100644 --- a/lib/efi_loader/Kconfig +++ b/lib/efi_loader/Kconfig @@ -301,6 +301,7 @@ config EFI_RNG_PROTOCOL config EFI_TCG2_PROTOCOL bool "EFI_TCG2_PROTOCOL support" depends on TPM_V2 + select on SHA1 && SHA256 && SHA384 && SHA512 help Provide a EFI_TCG2_PROTOCOL implementation using the TPM hardware of the platform. -- 2.31.0
[PATCHv4 24/26] configs: j7200_evm_r5: Enable raw access power management features
From: Dave Gerlach Sysfw is not going to provide access to power management features in the new architecture, so SPL must implement these itself. Enable all the raw register access based clock + power domain drivers. Signed-off-by: Dave Gerlach Signed-off-by: Tero Kristo --- configs/j7200_evm_r5_defconfig | 14 -- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/configs/j7200_evm_r5_defconfig b/configs/j7200_evm_r5_defconfig index b20698fd0e..97eb1b3c9a 100644 --- a/configs/j7200_evm_r5_defconfig +++ b/configs/j7200_evm_r5_defconfig @@ -75,7 +75,7 @@ CONFIG_SPL_SYSCON=y CONFIG_SPL_OF_TRANSLATE=y CONFIG_CLK=y CONFIG_SPL_CLK=y -CONFIG_CLK_TI_SCI=y +# CONFIG_CLK_TI_SCI is not set CONFIG_DMA_CHANNELS=y CONFIG_TI_K3_NAVSS_UDMA=y CONFIG_TI_SCI_PROTOCOL=y @@ -111,7 +111,7 @@ CONFIG_SPL_PINCTRL=y # CONFIG_SPL_PINCTRL_GENERIC is not set CONFIG_PINCTRL_SINGLE=y CONFIG_POWER_DOMAIN=y -CONFIG_TI_SCI_POWER_DOMAIN=y +# CONFIG_TI_SCI_POWER_DOMAIN is not set CONFIG_K3_SYSTEM_CONTROLLER=y CONFIG_REMOTEPROC_TI_K3_ARM64=y CONFIG_DM_RESET=y @@ -143,3 +143,13 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0x6164 CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_FS_EXT4=y CONFIG_FS_FAT_MAX_CLUSTSIZE=16384 +CONFIG_SOC_DEVICE=y +CONFIG_SOC_DEVICE_TI_K3=y +CONFIG_TI_POWER_DOMAIN=y +CONFIG_SPL_CLK_CCF=y +CONFIG_LIB_RATIONAL=y +CONFIG_SPL_LIB_RATIONAL=y +CONFIG_SPL_CLK_K3_PLL=y +CONFIG_SPL_CLK_K3=y +CONFIG_K3_DM_FW=y +CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y -- 2.17.1
[PATCHv4 26/26] arm: dts: k3-j72xx: correct MCU timer1 frequency
MCU timer1 is used as the tick timer for MCU R5 SPL, and the clock-frequency defined in DT appears to be incorrect at the moment. Actual clock source for the timer is MCU_SYSCLK0 / 4 which is 250MHz. Earlier setup of 25MHz went unnoticed, as there was a separate issue with omap-timer, which caused an error to the clock by a factor of 8 with j7 devices. This problem surfaced once the omap-timer was fixed. Signed-off-by: Tero Kristo --- arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi | 2 +- arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi b/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi index bd037be350..c3aae65b39 100644 --- a/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi +++ b/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi @@ -33,7 +33,7 @@ compatible = "ti,omap5430-timer"; reg = <0x0 0x4040 0x0 0x80>; ti,timer-alwon; - clock-frequency = <2500>; + clock-frequency = <25000>; u-boot,dm-spl; }; diff --git a/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi b/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi index 3384ed9f3a..1135de5a92 100644 --- a/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi +++ b/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi @@ -46,7 +46,7 @@ compatible = "ti,omap5430-timer"; reg = <0x0 0x4040 0x0 0x80>; ti,timer-alwon; - clock-frequency = <2500>; + clock-frequency = <25000>; u-boot,dm-spl; }; -- 2.17.1
[PATCHv4 25/26] board: ti: j72xx: README: update build instructions and image formats
From: Tero Kristo Update build instructions and image formats based on HSM rearch. A new DM image is added into the build, which gets executed right after R5 SPL finishes its job. Signed-off-by: Tero Kristo Signed-off-by: Tero Kristo --- board/ti/j721e/README | 9 ++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/board/ti/j721e/README b/board/ti/j721e/README index c33afa496e..b1c9145c92 100644 --- a/board/ti/j721e/README +++ b/board/ti/j721e/README @@ -73,12 +73,12 @@ support. Below is the pictorial representation of boot flow: || | | +-+ | | | || |<|---| Start A72 | | | | || | | | and jump to | | | | -|| | | | next image | | | | +|| | | | DM fw image | | | | || | | +-+ | | | || | | | +---+ | | || |-|---|>| Reset rls | | | || | | | +---+ | | -|| DMSC | | | :| | +|| TIFS | | | :| | ||Services | | | +---+ | | || |<|---|>|*ATF/OPTEE*| | | || | | | +---+ | | @@ -154,7 +154,7 @@ $ make CROSS_COMPILE=arm-linux-gnueabihf- O=/tmp/r5 4.2. A72: $ make CROSS_COMPILE=aarch64-linux-gnu- j721e_evm_a72_defconfig O=/tmp/a72 -$ make CROSS_COMPILE=aarch64-linux-gnu- ATF=/build/k3/generic/release/bl31.bin TEE=/out/arm-plat-k3/core/tee-pager_v2.bin O=/tmp/a72 +$ make CROSS_COMPILE=aarch64-linux-gnu- ATF=/build/k3/generic/release/bl31.bin TEE=/out/arm-plat-k3/core/tee-pager_v2.bin DM= O=/tmp/a72 Target Images -- @@ -197,6 +197,9 @@ Image formats: | | A72 OPTEE | | | +---+ | | | | | +| | R5 DM FW | | +| +---+ | +| | | | | | A72 SPL | | | +---+ | | | | | -- 2.17.1
[PATCHv4 22/26] arm: mach-k3: j721e_init: Force early probe of clk-k3 driver
From: Dave Gerlach
Force the clk-k3 driver to probe early during R5 SPL boot to ensure the
default system clock configuration is completed. Many other drivers
assume a default state of the clock tree and it is currently possible
for them to probe before clk-k3 depending on the exact system
configuration.
Signed-off-by: Dave Gerlach
Reported-by: Keerthy
Tested-by: Keerthy
Signed-off-by: Tero Kristo
---
arch/arm/mach-k3/j721e_init.c | 12
1 file changed, 12 insertions(+)
diff --git a/arch/arm/mach-k3/j721e_init.c b/arch/arm/mach-k3/j721e_init.c
index 1a4f796e5e..b5268372dd 100644
--- a/arch/arm/mach-k3/j721e_init.c
+++ b/arch/arm/mach-k3/j721e_init.c
@@ -180,6 +180,18 @@ void board_init_f(ulong dummy)
k3_sysfw_loader(is_rom_loaded_sysfw(&bootdata),
k3_mmc_stop_clock, k3_mmc_restart_clock);
+#ifdef CONFIG_SPL_CLK_K3
+ /*
+* Force probe of clk_k3 driver here to ensure basic default clock
+* configuration is always done.
+*/
+ ret = uclass_get_device_by_driver(UCLASS_CLK,
+ DM_DRIVER_GET(ti_clk),
+ &dev);
+ if (ret)
+ panic("Failed to initialize clk-k3!\n");
+#endif
+
/* Prepare console output */
preloader_console_init();
--
2.17.1
[PATCHv4 21/26] arm: mach-k3: sysfw-loader: pass boardcfg to sciserver
From: Tero Kristo
Copy the contents of the board config loaded from sysfw.itb into an
EXTBOOT shared memory buffer that gets passed to sciserver. This only
needs to be done if EXTBOOT area has not been populated by ROM code yet.
Signed-off-by: Tero Kristo
Signed-off-by: Tero Kristo
---
arch/arm/mach-k3/sysfw-loader.c | 103
1 file changed, 103 insertions(+)
diff --git a/arch/arm/mach-k3/sysfw-loader.c b/arch/arm/mach-k3/sysfw-loader.c
index c6af205163..ac719cd46f 100644
--- a/arch/arm/mach-k3/sysfw-loader.c
+++ b/arch/arm/mach-k3/sysfw-loader.c
@@ -40,6 +40,46 @@ DECLARE_GLOBAL_DATA_PTR;
*/
#define K3_SYSTEM_CONTROLLER_RPROC_ID 0
+#define COMMON_HEADER_ADDRESS 0x41cffb00
+#define BOARDCFG_ADDRESS 0x41c8
+
+#define COMP_TYPE_SBL_DATA 0x11
+#define DESC_TYPE_BOARDCFG_PM_INDEX0x2
+#define DESC_TYPE_BOARDCFG_RM_INDEX0x3
+
+#define BOARD_CONFIG_RM_DESC_TYPE 0x000c
+#define BOARD_CONFIG_PM_DESC_TYPE 0x000e
+
+struct extboot_comp {
+ u32 comp_type;
+ u32 boot_core;
+ u32 comp_opts;
+ u64 dest_addr;
+ u32 comp_size;
+};
+
+struct extboot_header {
+ u8 magic[8];
+ u32 num_comps;
+ struct extboot_comp comps[5];
+ u32 reserved;
+};
+
+struct bcfg_desc {
+ u16 type;
+ u16 offset;
+ u16 size;
+ u8 devgrp;
+ u8 reserved;
+} __packed;
+
+struct bcfg_header {
+ u8 num_elems;
+ u8 sw_rev;
+ struct bcfg_desc descs[4];
+ u16 reserved;
+} __packed;
+
static bool sysfw_loaded;
static void *sysfw_load_address;
@@ -131,6 +171,15 @@ static void k3_sysfw_configure_using_fit(void *fit,
const void *cfg_fragment_addr;
size_t cfg_fragment_size;
int ret;
+#ifdef CONFIG_K3_DM_FW
+ u8 *buf;
+ struct extboot_header *common_header;
+ struct bcfg_header *bcfg_header;
+ struct extboot_comp *comp;
+ struct bcfg_desc *desc;
+ u32 addr;
+ bool copy_bcfg = false;
+#endif
/* Find the node holding the images information */
images = fdt_path_offset(fit, FIT_IMAGES_PATH);
@@ -165,6 +214,46 @@ static void k3_sysfw_configure_using_fit(void *fit,
(u32)cfg_fragment_size);
if (ret)
panic("Failed to set board PM configuration (%d)\n", ret);
+#else
+ /* Initialize shared memory boardconfig buffer */
+ buf = (u8 *)COMMON_HEADER_ADDRESS;
+ common_header = (struct extboot_header *)buf;
+
+ /* Check if we have a struct populated by ROM in memory already */
+ if (strcmp((char *)common_header->magic, "EXTBOOT"))
+ copy_bcfg = true;
+
+ if (copy_bcfg) {
+ strcpy((char *)common_header->magic, "EXTBOOT");
+ common_header->num_comps = 1;
+
+ comp = &common_header->comps[0];
+
+ comp->comp_type = COMP_TYPE_SBL_DATA;
+ comp->boot_core = 0x10;
+ comp->comp_opts = 0;
+ addr = (u32)BOARDCFG_ADDRESS;
+ comp->dest_addr = addr;
+ comp->comp_size = sizeof(*bcfg_header);
+
+ bcfg_header = (struct bcfg_header *)addr;
+
+ bcfg_header->num_elems = 2;
+ bcfg_header->sw_rev = 0;
+
+ desc = &bcfg_header->descs[0];
+
+ desc->type = BOARD_CONFIG_PM_DESC_TYPE;
+ desc->offset = sizeof(*bcfg_header);
+ desc->size = cfg_fragment_size;
+ comp->comp_size += desc->size;
+ desc->devgrp = 0;
+ desc->reserved = 0;
+ memcpy((u8 *)bcfg_header + desc->offset, cfg_fragment_addr,
+ cfg_fragment_size);
+
+ bcfg_header->descs[1].offset = desc->offset + desc->size;
+ }
#endif
/* Extract resource management (RM) specific configuration from FIT */
@@ -174,6 +263,20 @@ static void k3_sysfw_configure_using_fit(void *fit,
panic("Error accessing %s node in FIT (%d)\n", SYSFW_CFG_RM,
ret);
+#ifdef CONFIG_K3_DM_FW
+ if (copy_bcfg) {
+ desc = &bcfg_header->descs[1];
+
+ desc->type = BOARD_CONFIG_RM_DESC_TYPE;
+ desc->size = cfg_fragment_size;
+ comp->comp_size += desc->size;
+ desc->devgrp = 0;
+ desc->reserved = 0;
+ memcpy((u8 *)bcfg_header + desc->offset, cfg_fragment_addr,
+ cfg_fragment_size);
+ }
+#endif
+
/* Apply resource management (RM) configuration to SYSFW */
ret = board_ops->board_config_rm(ti_sci,
(u64)(u32)cfg_fragment_addr,
--
2.17.1
[PATCHv4 23/26] configs: j721e_evm_r5: Enable raw access power management features
From: Tero Kristo Sysfw is not going to provide access to power management features in the new architecture, so SPL must implement these itself. Enable all the raw register access based clock + power domain drivers. Signed-off-by: Tero Kristo Signed-off-by: Tero Kristo --- configs/j721e_evm_r5_defconfig | 12 ++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/configs/j721e_evm_r5_defconfig b/configs/j721e_evm_r5_defconfig index 7b4f0afce6..0d21904a00 100644 --- a/configs/j721e_evm_r5_defconfig +++ b/configs/j721e_evm_r5_defconfig @@ -72,7 +72,7 @@ CONFIG_SPL_REGMAP=y CONFIG_SPL_OF_TRANSLATE=y CONFIG_CLK=y CONFIG_SPL_CLK=y -CONFIG_CLK_TI_SCI=y +# CONFIG_CLK_TI_SCI is not set CONFIG_DMA_CHANNELS=y CONFIG_TI_K3_NAVSS_UDMA=y CONFIG_TI_SCI_PROTOCOL=y @@ -103,7 +103,7 @@ CONFIG_SPL_PINCTRL=y # CONFIG_SPL_PINCTRL_GENERIC is not set CONFIG_PINCTRL_SINGLE=y CONFIG_POWER_DOMAIN=y -CONFIG_TI_SCI_POWER_DOMAIN=y +# CONFIG_TI_SCI_POWER_DOMAIN is not set CONFIG_DM_PMIC=y CONFIG_PMIC_TPS65941=y CONFIG_DM_REGULATOR=y @@ -141,3 +141,11 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0x6163 CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_FS_EXT4=y CONFIG_FS_FAT_MAX_CLUSTSIZE=16384 +CONFIG_TI_POWER_DOMAIN=y +CONFIG_SPL_CLK_CCF=y +CONFIG_LIB_RATIONAL=y +CONFIG_SPL_LIB_RATIONAL=y +CONFIG_SPL_CLK_K3_PLL=y +CONFIG_SPL_CLK_K3=y +CONFIG_K3_DM_FW=y +CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y -- 2.17.1
[PATCHv4 17/26] arm: mach-k3: Add platform data for j721e and j7200
From: Dave Gerlach
Add platform clock and powerdomain data for J721e and J7200. This data
is used by the corresponding drivers to register all the required device
clocks and powerdomains.
Signed-off-by: Dave Gerlach
Signed-off-by: Tero Kristo
---
arch/arm/mach-k3/Makefile | 2 +-
arch/arm/mach-k3/j7200/Makefile | 5 +
arch/arm/mach-k3/j7200/clk-data.c | 547 +
arch/arm/mach-k3/j7200/dev-data.c | 77 +++
arch/arm/mach-k3/j721e/Makefile | 5 +
arch/arm/mach-k3/j721e/clk-data.c | 781 ++
arch/arm/mach-k3/j721e/dev-data.c | 75 +++
7 files changed, 1491 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/mach-k3/j7200/Makefile
create mode 100644 arch/arm/mach-k3/j7200/clk-data.c
create mode 100644 arch/arm/mach-k3/j7200/dev-data.c
create mode 100644 arch/arm/mach-k3/j721e/Makefile
create mode 100644 arch/arm/mach-k3/j721e/clk-data.c
create mode 100644 arch/arm/mach-k3/j721e/dev-data.c
diff --git a/arch/arm/mach-k3/Makefile b/arch/arm/mach-k3/Makefile
index 7572f56925..534ddfcd49 100644
--- a/arch/arm/mach-k3/Makefile
+++ b/arch/arm/mach-k3/Makefile
@@ -4,7 +4,7 @@
# Lokesh Vutla
obj-$(CONFIG_SOC_K3_AM6) += am6_init.o
-obj-$(CONFIG_SOC_K3_J721E) += j721e_init.o
+obj-$(CONFIG_SOC_K3_J721E) += j721e_init.o j721e/ j7200/
obj-$(CONFIG_ARM64) += arm64-mmu.o
obj-$(CONFIG_CPU_V7R) += r5_mpu.o lowlevel_init.o
obj-$(CONFIG_TI_SECURE_DEVICE) += security.o
diff --git a/arch/arm/mach-k3/j7200/Makefile b/arch/arm/mach-k3/j7200/Makefile
new file mode 100644
index 00..ff9abd78ea
--- /dev/null
+++ b/arch/arm/mach-k3/j7200/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
+obj-y += clk-data.o
+obj-y += dev-data.o
diff --git a/arch/arm/mach-k3/j7200/clk-data.c
b/arch/arm/mach-k3/j7200/clk-data.c
new file mode 100644
index 00..93c067079a
--- /dev/null
+++ b/arch/arm/mach-k3/j7200/clk-data.c
@@ -0,0 +1,547 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * J7200 specific clock platform data
+ *
+ * Copyright (C) 2020-2021 Texas Instruments Incorporated - http://www.ti.com/
+ */
+#include "k3-clk.h"
+
+static const char * const gluelogic_hfosc0_clkout_parents[] = {
+ "osc_19_2_mhz",
+ "osc_20_mhz",
+ "osc_24_mhz",
+ "osc_25_mhz",
+ "osc_26_mhz",
+ "osc_27_mhz",
+};
+
+static const char * const mcu_ospi0_iclk_sel_out0_parents[] = {
+ "board_0_mcu_ospi0_dqs_out",
+ "fss_mcu_0_ospi_0_ospi_oclk_clk",
+};
+
+static const char * const wkup_fref_clksel_out0_parents[] = {
+ "gluelogic_hfosc0_clkout",
+ "j7vc_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk",
+};
+
+static const char * const main_pll_hfosc_sel_out1_parents[] = {
+ "gluelogic_hfosc0_clkout",
+ "board_0_hfosc1_clk_out",
+};
+
+static const char * const k3_pll_ctrl_wrap_wkup_0_sysclkout_clk_parents[] = {
+ "wkup_fref_clksel_out0",
+ "hsdiv1_16fft_mcu_0_hsdivout0_clk",
+};
+
+static const char * const mcu_ospi_ref_clk_sel_out0_parents[] = {
+ "hsdiv4_16fft_mcu_1_hsdivout4_clk",
+ "hsdiv4_16fft_mcu_2_hsdivout4_clk",
+};
+
+static const char * const mcuusart_clk_sel_out0_parents[] = {
+ "hsdiv4_16fft_mcu_1_hsdivout3_clk",
+ "postdiv2_16fft_main_1_hsdivout5_clk",
+};
+
+static const char * const wkup_gpio0_clksel_out0_parents[] = {
+ "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk",
+ "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk",
+ "j7vc_wakeup_16ff_wkup_0_wkup_rcosc_32k_clk",
+ "j7vc_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk",
+};
+
+static const char * const wkup_i2c0_mcupll_bypass_clksel_out0_parents[] = {
+ "hsdiv4_16fft_mcu_1_hsdivout3_clk",
+ "gluelogic_hfosc0_clkout",
+};
+
+static const char * const main_pll_hfosc_sel_out0_parents[] = {
+ "gluelogic_hfosc0_clkout",
+ "board_0_hfosc1_clk_out",
+};
+
+static const char * const main_pll_hfosc_sel_out12_parents[] = {
+ "gluelogic_hfosc0_clkout",
+ "board_0_hfosc1_clk_out",
+};
+
+static const char * const main_pll_hfosc_sel_out14_parents[] = {
+ "gluelogic_hfosc0_clkout",
+ "board_0_hfosc1_clk_out",
+};
+
+static const char * const main_pll_hfosc_sel_out2_parents[] = {
+ "gluelogic_hfosc0_clkout",
+ "board_0_hfosc1_clk_out",
+};
+
+static const char * const main_pll_hfosc_sel_out3_parents[] = {
+ "gluelogic_hfosc0_clkout",
+ "board_0_hfosc1_clk_out",
+};
+
+static const char * const main_pll_hfosc_sel_out4_parents[] = {
+ "gluelogic_hfosc0_clkout",
+ "board_0_hfosc1_clk_out",
+};
+
+static const char * const main_pll_hfosc_sel_out7_parents[] = {
+ "gluelogic_hfosc0_clkout",
+ "board_0_hfosc1_clk_out",
+};
+
+static const char * const main_pll_hfosc_sel_out8_parents[] = {
+ "gluelogic_hfosc0_clkout",
+ "board_0_hfosc1_clk_out",
+};
+
+static const char * const usb0_refclk_sel_out0_parents[] = {
+ "gl
[PATCHv4 20/26] arm: mach-k3: common: Drop main r5 start
From: Dave Gerlach
Only start-up the non-linux remote cores if we are running in legacy
boot mode. HSM rearch is not yet supporting this.
Signed-off-by: Dave Gerlach
Signed-off-by: Tero Kristo
Signed-off-by: Tero Kristo
---
arch/arm/mach-k3/common.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c
index a5d6a10dc7..2b8c09a650 100644
--- a/arch/arm/mach-k3/common.c
+++ b/arch/arm/mach-k3/common.c
@@ -212,11 +212,12 @@ void __noreturn jump_to_image_no_args(struct
spl_image_info *spl_image)
panic("rproc failed to be initialized (%d)\n", ret);
init_env();
- start_non_linux_remote_cores();
- if (!fit_image_info[IMAGE_ID_DM_FW].image_start)
+
+ if (!fit_image_info[IMAGE_ID_DM_FW].image_start) {
+ start_non_linux_remote_cores();
size = load_firmware("name_mcur5f0_0fw", "addr_mcur5f0_0load",
&loadaddr);
-
+ }
/*
* It is assumed that remoteproc device 1 is the corresponding
--
2.17.1
[PATCHv4 19/26] arm: mach-k3: do board config for PM only if supported
From: Tero Kristo
If the raw PM support is built in, we are operating in the split
firmware approach mode where PM support is not available. In this
case, skip the board config for this.
Signed-off-by: Tero Kristo
Signed-off-by: Tero Kristo
---
arch/arm/mach-k3/sysfw-loader.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/mach-k3/sysfw-loader.c b/arch/arm/mach-k3/sysfw-loader.c
index 0bacfc4d07..c6af205163 100644
--- a/arch/arm/mach-k3/sysfw-loader.c
+++ b/arch/arm/mach-k3/sysfw-loader.c
@@ -159,11 +159,13 @@ static void k3_sysfw_configure_using_fit(void *fit,
ret);
/* Apply power/clock (PM) specific configuration to SYSFW */
+#ifndef CONFIG_K3_DM_FW
ret = board_ops->board_config_pm(ti_sci,
(u64)(u32)cfg_fragment_addr,
(u32)cfg_fragment_size);
if (ret)
panic("Failed to set board PM configuration (%d)\n", ret);
+#endif
/* Extract resource management (RM) specific configuration from FIT */
ret = fit_get_data_by_name(fit, images, SYSFW_CFG_RM,
--
2.17.1
[PATCHv4 16/26] tools: k3_fit_atf: add DM binary to the FIT image
From: Tero Kristo
Add DM (device manager) firmware image to the fit image that is loaded by
R5 SPL. This is needed with the HSM rearch where the firmware allocation
has been changed slightly.
Signed-off-by: Tero Kristo
Signed-off-by: Tero Kristo
---
arch/arm/mach-k3/config.mk | 4
tools/k3_fit_atf.sh| 19 ++-
2 files changed, 22 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-k3/config.mk b/arch/arm/mach-k3/config.mk
index 41fee2b5a1..503ece4520 100644
--- a/arch/arm/mach-k3/config.mk
+++ b/arch/arm/mach-k3/config.mk
@@ -49,6 +49,10 @@ endif
ifdef CONFIG_ARM64
+ifeq ($(CONFIG_SOC_K3_J721E),)
+export DM := /dev/null
+endif
+
ifeq ($(CONFIG_TI_SECURE_DEVICE),y)
SPL_ITS := u-boot-spl-k3_HS.its
$(SPL_ITS): export IS_HS=1
diff --git a/tools/k3_fit_atf.sh b/tools/k3_fit_atf.sh
index 4e9f69c087..c0940a2fcc 100755
--- a/tools/k3_fit_atf.sh
+++ b/tools/k3_fit_atf.sh
@@ -21,6 +21,13 @@ if [ ! -f $TEE ]; then
TEE=/dev/null
fi
+[ -z "$DM" ] && DM="dm.bin"
+
+if [ ! -e $DM ]; then
+ echo "WARNING DM file $DM NOT found, resulting might be non-functional"
>&2
+ DM=/dev/null
+fi
+
if [ ! -z "$IS_HS" ]; then
HS_APPEND=_HS
fi
@@ -53,6 +60,16 @@ cat << __HEADER_EOF
load = <0x9e80>;
entry = <0x9e80>;
};
+ dm {
+ description = "DM binary";
+ data = /incbin/("$DM");
+ type = "firmware";
+ arch = "arm32";
+ compression = "none";
+ os = "DM";
+ load = <0xa000>;
+ entry = <0xa000>;
+ };
spl {
description = "SPL (64-bit)";
data = /incbin/("spl/u-boot-spl-nodtb.bin$HS_APPEND");
@@ -91,7 +108,7 @@ do
$(basename $dtname) {
description = "$(basename $dtname .dtb)";
firmware = "atf";
- loadables = "tee", "spl";
+ loadables = "tee", "dm", "spl";
fdt = "$(basename $dtname)";
};
__CONF_SECTION_EOF
--
2.17.1
[PATCHv4 18/26] arm: mach-k3: add support for detecting firmware images from FIT
From: Tero Kristo
Add callback routines for parsing the firmware info from FIT image, and
use the data to boot up ATF and the MCU R5 firmware.
Signed-off-by: Tero Kristo
Signed-off-by: Tero Kristo
---
arch/arm/mach-k3/common.c | 80 +
arch/arm/mach-k3/common.h | 1 +
arch/arm/mach-k3/security.c | 3 +-
3 files changed, 75 insertions(+), 9 deletions(-)
diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c
index 9191f686f0..a5d6a10dc7 100644
--- a/arch/arm/mach-k3/common.c
+++ b/arch/arm/mach-k3/common.c
@@ -28,6 +28,27 @@
#include
#include
+#ifdef CONFIG_SYS_K3_SPL_ATF
+enum {
+ IMAGE_ID_ATF,
+ IMAGE_ID_OPTEE,
+ IMAGE_ID_SPL,
+ IMAGE_ID_DM_FW,
+ IMAGE_AMT,
+};
+
+#ifdef CONFIG_SPL_FIT_IMAGE_POST_PROCESS
+static const char *image_os_match[IMAGE_AMT] = {
+ "arm-trusted-firmware",
+ "tee",
+ "U-Boot",
+ "DM",
+};
+#endif
+
+static struct image_info fit_image_info[IMAGE_AMT];
+#endif
+
struct ti_sci_handle *get_ti_sci_handle(void)
{
struct udevice *dev;
@@ -181,7 +202,7 @@ void __noreturn jump_to_image_no_args(struct spl_image_info
*spl_image)
typedef void __noreturn (*image_entry_noargs_t)(void);
struct ti_sci_handle *ti_sci = get_ti_sci_handle();
u32 loadaddr = 0;
- int ret, size;
+ int ret, size = 0;
/* Release all the exclusive devices held by SPL before starting ATF */
ti_sci->ops.dev_ops.release_exclusive_devices(ti_sci);
@@ -192,15 +213,20 @@ void __noreturn jump_to_image_no_args(struct
spl_image_info *spl_image)
init_env();
start_non_linux_remote_cores();
- size = load_firmware("name_mcur5f0_0fw", "addr_mcur5f0_0load",
-&loadaddr);
+ if (!fit_image_info[IMAGE_ID_DM_FW].image_start)
+ size = load_firmware("name_mcur5f0_0fw", "addr_mcur5f0_0load",
+&loadaddr);
/*
* It is assumed that remoteproc device 1 is the corresponding
* Cortex-A core which runs ATF. Make sure DT reflects the same.
*/
- ret = rproc_load(1, spl_image->entry_point, 0x200);
+ if (!fit_image_info[IMAGE_ID_ATF].image_start)
+ fit_image_info[IMAGE_ID_ATF].image_start =
+ spl_image->entry_point;
+
+ ret = rproc_load(1, fit_image_info[IMAGE_ID_ATF].image_start, 0x200);
if (ret)
panic("%s: ATF failed to load on rproc (%d)\n", __func__, ret);
@@ -210,7 +236,8 @@ void __noreturn jump_to_image_no_args(struct spl_image_info
*spl_image)
ret = rproc_start(1);
if (ret)
panic("%s: ATF failed to start on rproc (%d)\n", __func__, ret);
- if (!(size > 0 && valid_elf_image(loadaddr))) {
+ if (!fit_image_info[IMAGE_ID_DM_FW].image_len &&
+ !(size > 0 && valid_elf_image(loadaddr))) {
debug("Shutting down...\n");
release_resources_for_core_shutdown();
@@ -218,13 +245,52 @@ void __noreturn jump_to_image_no_args(struct
spl_image_info *spl_image)
asm volatile("wfe");
}
- image_entry_noargs_t image_entry =
- (image_entry_noargs_t)load_elf_image_phdr(loadaddr);
+ if (!fit_image_info[IMAGE_ID_DM_FW].image_start) {
+ loadaddr = load_elf_image_phdr(loadaddr);
+ } else {
+ loadaddr = fit_image_info[IMAGE_ID_DM_FW].image_start;
+ if (valid_elf_image(loadaddr))
+ loadaddr = load_elf_image_phdr(loadaddr);
+ }
+
+ debug("%s: jumping to address %x\n", __func__, loadaddr);
+
+ image_entry_noargs_t image_entry = (image_entry_noargs_t)loadaddr;
image_entry();
}
#endif
+#ifdef CONFIG_SPL_FIT_IMAGE_POST_PROCESS
+void board_fit_image_post_process(const void *fit, int node, void **p_image,
+ size_t *p_size)
+{
+ int len;
+ int i;
+ const char *os;
+ u32 addr;
+
+ os = fdt_getprop(fit, node, "os", &len);
+ addr = fdt_getprop_u32_default_node(fit, node, 0, "entry", -1);
+
+ debug("%s: processing image: addr=%x, size=%d, os=%s\n", __func__,
+ addr, *p_size, os);
+
+ for (i = 0; i < IMAGE_AMT; i++) {
+ if (!strcmp(os, image_os_match[i])) {
+ fit_image_info[i].image_start = addr;
+ fit_image_info[i].image_len = *p_size;
+ debug("%s: matched image for ID %d\n", __func__, i);
+ break;
+ }
+ }
+
+#ifdef CONFIG_TI_SECURE_DEVICE
+ ti_secure_image_post_process(p_image, p_size);
+#endif
+}
+#endif
+
#if defined(CONFIG_OF_LIBFDT)
int fdt_fixup_msmc_ram(void *blob, char *parent_path, char *node_name)
{
diff --git a/arch/arm/mach-k3/common.h b/arch/arm/mach-k3/common.h
index a6dbc7808b..f421ed1bb1 100644
--- a/arch/arm/
[PATCHv4 13/26] clk: add support for TI K3 SoC clocks
From: Tero Kristo
Add driver to support TI K3 generation SoC clocks. This driver registers
the clocks provided via platform data, and adds support for controlling
the clocks via DT handles.
Signed-off-by: Tero Kristo
Signed-off-by: Tero Kristo
---
drivers/clk/ti/Kconfig | 12 ++
drivers/clk/ti/Makefile | 1 +
drivers/clk/ti/clk-k3.c | 374
include/k3-clk.h| 162 +
4 files changed, 549 insertions(+)
create mode 100644 drivers/clk/ti/clk-k3.c
diff --git a/drivers/clk/ti/Kconfig b/drivers/clk/ti/Kconfig
index a8ec4f541a..fbcdefd889 100644
--- a/drivers/clk/ti/Kconfig
+++ b/drivers/clk/ti/Kconfig
@@ -53,3 +53,15 @@ config SPL_CLK_K3_PLL
depends on CLK && LIB_RATIONAL && SPL
help
Enables PLL clock support for K3 SoC family of devices.
+
+config CLK_K3
+ bool "Clock support for K3 SoC family of devices"
+ depends on CLK
+ help
+ Enables the clock translation layer from DT to device clocks.
+
+config SPL_CLK_K3
+ bool "Clock support for K3 SoC family of devices"
+ depends on CLK && SPL
+ help
+ Enables the clock translation layer from DT to device clocks.
diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile
index 47839213e5..07aa9a53e0 100644
--- a/drivers/clk/ti/Makefile
+++ b/drivers/clk/ti/Makefile
@@ -12,3 +12,4 @@ obj-$(CONFIG_CLK_TI_GATE) += clk-gate.o
obj-$(CONFIG_CLK_TI_MUX) += clk-mux.o
obj-$(CONFIG_CLK_TI_SCI) += clk-sci.o
obj-$(CONFIG_$(SPL_TPL_)CLK_K3_PLL) += clk-k3-pll.o
+obj-$(CONFIG_$(SPL_TPL_)CLK_K3) += clk-k3.o
diff --git a/drivers/clk/ti/clk-k3.c b/drivers/clk/ti/clk-k3.c
new file mode 100644
index 00..ec262d5c21
--- /dev/null
+++ b/drivers/clk/ti/clk-k3.c
@@ -0,0 +1,374 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Texas Instruments K3 clock driver
+ *
+ * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
+ * Tero Kristo
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include "k3-clk.h"
+
+#define PLL_MIN_FREQ 8
+#define PLL_MAX_FREQ 32UL
+#define PLL_MAX_DIV127
+
+/**
+ * struct clk_map - mapping from dev/clk id tuples towards physical clocks
+ * @dev_id: device ID for the clock
+ * @clk_id: clock ID for the clock
+ * @clk: pointer to the registered clock entry for the mapping
+ */
+struct clk_map {
+ u16 dev_id;
+ u32 clk_id;
+ struct clk *clk;
+};
+
+/**
+ * struct ti_clk_data - clock controller information structure
+ * @map: mapping from dev/clk id tuples to physical clock entries
+ * @size: number of entries in the map
+ */
+struct ti_clk_data {
+ struct clk_map *map;
+ int size;
+};
+
+static ulong osc_freq;
+
+static void clk_add_map(struct ti_clk_data *data, struct clk *clk,
+ u32 dev_id, u32 clk_id)
+{
+ struct clk_map *map;
+
+ debug("%s: added clk=%p, data=%p, dev=%d, clk=%d\n", __func__,
+ clk, data, dev_id, clk_id);
+ if (!clk)
+ return;
+
+ map = data->map + data->size++;
+
+ map->dev_id = dev_id;
+ map->clk_id = clk_id;
+ map->clk = clk;
+}
+
+static const struct soc_attr ti_k3_soc_clk_data[] = {
+#ifdef CONFIG_SOC_K3_J721E
+ {
+ .family = "J721E",
+ .data = &j721e_clk_platdata,
+ },
+ {
+ .family = "J7200",
+ .data = &j7200_clk_platdata,
+ },
+#endif
+ { /* sentinel */ }
+};
+
+static int ti_clk_probe(struct udevice *dev)
+{
+ struct ti_clk_data *data = dev_get_priv(dev);
+ struct clk *clk;
+ const char *name;
+ const struct clk_data *ti_clk_data;
+ int i, j;
+ const struct soc_attr *soc_match_data;
+ const struct ti_k3_clk_platdata *pdata;
+
+ debug("%s(dev=%p)\n", __func__, dev);
+
+ soc_match_data = soc_device_match(ti_k3_soc_clk_data);
+ if (!soc_match_data)
+ return -ENODEV;
+
+ pdata = (const struct ti_k3_clk_platdata *)soc_match_data->data;
+
+ data->map = kcalloc(pdata->soc_dev_clk_data_cnt, sizeof(*data->map),
+ GFP_KERNEL);
+ data->size = 0;
+
+ for (i = 0; i < pdata->clk_list_cnt; i++) {
+ ti_clk_data = &pdata->clk_list[i];
+
+ switch (ti_clk_data->type) {
+ case CLK_TYPE_FIXED_RATE:
+ name = ti_clk_data->clk.fixed_rate.name;
+ clk = clk_register_fixed_rate(NULL,
+ name,
+
ti_clk_data->clk.fixed_rate.rate);
+ break;
+ case CLK_TYPE_DIV:
+ name = ti_clk_data->clk.div.name;
+ clk = clk_register_divider(NULL, name,
+ ti_clk_data->clk.div.parent,
+
[PATCHv4 15/26] cmd: ti: pd: Add debug command for K3 power domains
From: Tero Kristo
Add support command for debugging K3 power domains. This is useful with
the HSM rearch setup, where power domains are directly controlled by SPL
instead of going through the TI SCI layer. The debugging support is only
available in the u-boot codebase though, so the raw register access
power domain layer must be enabled on u-boot side for this to work. By
default, u-boot side uses the TI SCI layer, and R5 SPL only uses the
direct access methods.
Signed-off-by: Tero Kristo
Signed-off-by: Tero Kristo
---
cmd/ti/Kconfig | 8 ++
cmd/ti/Makefile| 1 +
cmd/ti/pd.c| 185 +
drivers/power/domain/ti-power-domain.c | 6 +-
include/k3-dev.h | 9 ++
5 files changed, 206 insertions(+), 3 deletions(-)
create mode 100644 cmd/ti/pd.c
diff --git a/cmd/ti/Kconfig b/cmd/ti/Kconfig
index efeff0d482..db557445a8 100644
--- a/cmd/ti/Kconfig
+++ b/cmd/ti/Kconfig
@@ -7,4 +7,12 @@ config CMD_DDR3
supports memory verification, memory comapre and ecc
verification if supported.
+config CMD_PD
+ bool "command for verifying power domains"
+ depends on TI_POWER_DOMAIN
+ help
+ Debug command for K3 power domains. For this to work, the
+ K3 power domain driver must be enabled for the u-boot; by
+ default it is only enabled for SPL.
+
endmenu
diff --git a/cmd/ti/Makefile b/cmd/ti/Makefile
index 16fbade9ed..045593396b 100644
--- a/cmd/ti/Makefile
+++ b/cmd/ti/Makefile
@@ -5,4 +5,5 @@ obj- += dummy.o
ifndef CONFIG_SPL_BUILD
obj-$(CONFIG_CMD_DDR3) += ddr3.o
+obj-$(CONFIG_CMD_PD) += pd.o
endif
diff --git a/cmd/ti/pd.c b/cmd/ti/pd.c
new file mode 100644
index 00..a53ccdcc40
--- /dev/null
+++ b/cmd/ti/pd.c
@@ -0,0 +1,185 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Power Domain test commands
+ *
+ * Copyright (C) 2020 Texas Instruments Incorporated,
+ */
+
+#include
+#include
+#include
+#include
+
+static const struct udevice_id ti_pd_of_match[] = {
+ { .compatible = "ti,sci-pm-domain" },
+ { /* sentinel */ }
+};
+
+static struct ti_k3_pd_platdata *ti_pd_find_data(void)
+{
+ struct udevice *dev;
+ int i = 0;
+
+ while (1) {
+ uclass_get_device(UCLASS_POWER_DOMAIN, i++, &dev);
+ if (!dev)
+ return NULL;
+
+ if (device_is_compatible(dev,
+ti_pd_of_match[0].compatible))
+ return dev_get_priv(dev);
+ }
+
+ return NULL;
+}
+
+static void dump_lpsc(struct ti_k3_pd_platdata *data, struct ti_pd *pd)
+{
+ int i;
+ struct ti_lpsc *lpsc;
+ u8 state;
+ static const char * const lpsc_states[] = {
+ "swrstdis", "syncrst", "disable", "enable", "autosleep",
+ "autowake", "unknown",
+ };
+
+ for (i = 0; i < data->num_lpsc; i++) {
+ lpsc = &data->lpsc[i];
+ if (lpsc->pd != pd)
+ continue;
+ state = lpsc_get_state(lpsc);
+ if (state > ARRAY_SIZE(lpsc_states))
+ state = ARRAY_SIZE(lpsc_states) - 1;
+ printf("LPSC%d: state=%s, usecount=%d\n",
+ lpsc->id, lpsc_states[state], lpsc->usecount);
+ }
+}
+
+static void dump_pd(struct ti_k3_pd_platdata *data, struct ti_psc *psc)
+{
+ int i;
+ struct ti_pd *pd;
+ u8 state;
+ static const char * const pd_states[] = {
+ "off", "on", "unknown"
+ };
+
+ for (i = 0; i < data->num_pd; i++) {
+ pd = &data->pd[i];
+ if (pd->psc != psc)
+ continue;
+ state = ti_pd_state(pd);
+ if (state > ARRAY_SIZE(pd_states))
+ state = ARRAY_SIZE(pd_states) - 1;
+ printf(" PD%d: state=%s, usecount=%d:\n",
+ pd->id, pd_states[state], pd->usecount);
+ dump_lpsc(data, pd);
+ }
+}
+
+static void dump_psc(struct ti_k3_pd_platdata *data)
+{
+ int i;
+ struct ti_psc *psc;
+
+ for (i = 0; i < data->num_psc; i++) {
+ psc = &data->psc[i];
+ printf("PSC%d [%p]:\n", psc->id, psc->base);
+ dump_pd(data, psc);
+ }
+}
+
+static int do_pd_dump(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ struct ti_k3_pd_platdata *data;
+
+ data = ti_pd_find_data();
+ if (!data)
+ return CMD_RET_FAILURE;
+
+ dump_psc(data);
+
+ return 0;
+}
+
+static int do_pd_endis(int argc, char *const argv[], u8 state)
+{
+ u32 psc_id;
+ u32 lpsc_id;
+ int i;
+ struct ti_k3_pd_platdata *data;
+ struct ti_lpsc *lpsc;
+ int ret;
+
+ if (argc < 3)
+ return CMD_RET_FAILURE;
+
+
[PATCHv4 14/26] power: domain: Introduce driver for raw TI K3 PDs
From: Tero Kristo
Normally, power domains are handled via TI-SCI in K3 SoCs. However,
SPL is not going to have access to sysfw resources, so it must control
them directly. Add driver for supporting this.
Signed-off-by: Tero Kristo
Signed-off-by: Tero Kristo
---
drivers/power/domain/Kconfig | 7 +
drivers/power/domain/Makefile | 1 +
drivers/power/domain/ti-power-domain.c | 368 +
include/k3-dev.h | 76 +
4 files changed, 452 insertions(+)
create mode 100644 drivers/power/domain/ti-power-domain.c
create mode 100644 include/k3-dev.h
diff --git a/drivers/power/domain/Kconfig b/drivers/power/domain/Kconfig
index a0fd980752..99b3f9ae71 100644
--- a/drivers/power/domain/Kconfig
+++ b/drivers/power/domain/Kconfig
@@ -72,4 +72,11 @@ config TI_SCI_POWER_DOMAIN
help
Generic power domain implementation for TI devices implementing the
TI SCI protocol.
+
+config TI_POWER_DOMAIN
+ bool "Enable the TI K3 Power domain driver"
+ depends on POWER_DOMAIN && ARCH_K3
+ help
+ Generic power domain implementation for TI K3 devices.
+
endmenu
diff --git a/drivers/power/domain/Makefile b/drivers/power/domain/Makefile
index 45bf9f6383..3d1e5f073c 100644
--- a/drivers/power/domain/Makefile
+++ b/drivers/power/domain/Makefile
@@ -14,3 +14,4 @@ obj-$(CONFIG_SANDBOX_POWER_DOMAIN) += sandbox-power-domain.o
obj-$(CONFIG_SANDBOX_POWER_DOMAIN) += sandbox-power-domain-test.o
obj-$(CONFIG_TEGRA186_POWER_DOMAIN) += tegra186-power-domain.o
obj-$(CONFIG_TI_SCI_POWER_DOMAIN) += ti-sci-power-domain.o
+obj-$(CONFIG_TI_POWER_DOMAIN) += ti-power-domain.o
diff --git a/drivers/power/domain/ti-power-domain.c
b/drivers/power/domain/ti-power-domain.c
new file mode 100644
index 00..e418a7b996
--- /dev/null
+++ b/drivers/power/domain/ti-power-domain.c
@@ -0,0 +1,368 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Texas Instruments power domain driver
+ *
+ * Copyright (C) 2020-2021 Texas Instruments Incorporated - http://www.ti.com/
+ * Tero Kristo
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define PSC_PTCMD 0x120
+#define PSC_PTSTAT 0x128
+#define PSC_PDSTAT 0x200
+#define PSC_PDCTL 0x300
+#define PSC_MDSTAT 0x800
+#define PSC_MDCTL 0xa00
+
+#define PDCTL_STATE_MASK 0x1
+#define PDCTL_STATE_OFF0x0
+#define PDCTL_STATE_ON 0x1
+
+#define MDSTAT_STATE_MASK 0x3f
+#define MDSTAT_BUSY_MASK 0x30
+#define MDSTAT_STATE_SWRSTDISABLE 0x0
+#define MDSTAT_STATE_ENABLE0x3
+
+#define LPSC_TIMEOUT 1000
+#define PD_TIMEOUT 1000
+
+static u32 psc_read(struct ti_psc *psc, u32 reg)
+{
+ u32 val;
+
+ val = readl(psc->base + reg);
+ debug("%s: 0x%x from %p\n", __func__, val, psc->base + reg);
+ return val;
+}
+
+static void psc_write(u32 val, struct ti_psc *psc, u32 reg)
+{
+ debug("%s: 0x%x to %p\n", __func__, val, psc->base + reg);
+ writel(val, psc->base + reg);
+}
+
+static u32 pd_read(struct ti_pd *pd, u32 reg)
+{
+ return psc_read(pd->psc, reg + 4 * pd->id);
+}
+
+static void pd_write(u32 val, struct ti_pd *pd, u32 reg)
+{
+ psc_write(val, pd->psc, reg + 4 * pd->id);
+}
+
+static u32 lpsc_read(struct ti_lpsc *lpsc, u32 reg)
+{
+ return psc_read(lpsc->psc, reg + 4 * lpsc->id);
+}
+
+static void lpsc_write(u32 val, struct ti_lpsc *lpsc, u32 reg)
+{
+ psc_write(val, lpsc->psc, reg + 4 * lpsc->id);
+}
+
+static const struct soc_attr ti_k3_soc_pd_data[] = {
+#ifdef CONFIG_SOC_K3_J721E
+ {
+ .family = "J721E",
+ .data = &j721e_pd_platdata,
+ },
+ {
+ .family = "J7200",
+ .data = &j7200_pd_platdata,
+ },
+#endif
+ { /* sentinel */ }
+};
+
+static int ti_power_domain_probe(struct udevice *dev)
+{
+ struct ti_k3_pd_platdata *data = dev_get_priv(dev);
+ const struct soc_attr *soc_match_data;
+ const struct ti_k3_pd_platdata *pdata;
+
+ printf("%s(dev=%p)\n", __func__, dev);
+
+ if (!data)
+ return -ENOMEM;
+
+ soc_match_data = soc_device_match(ti_k3_soc_pd_data);
+ if (!soc_match_data)
+ return -ENODEV;
+
+ pdata = (const struct ti_k3_pd_platdata *)soc_match_data->data;
+
+ data->psc = pdata->psc;
+ data->pd = pdata->pd;
+ data->lpsc = pdata->lpsc;
+ data->devs = pdata->devs;
+ data->num_psc = pdata->num_psc;
+ data->num_pd = pdata->num_pd;
+ data->num_lpsc = pdata->num_lpsc;
+ data->num_devs = pdata->num_devs;
+
+ return 0;
+}
+
+static int ti_pd_wait(struct ti_pd *pd)
+{
+ u32 ptstat;
+ int ret;
+
+ ret = readl_poll_timeout(pd->psc->base + PSC_PTSTAT, ptstat,
+
[PATCHv4 12/26] clk: add support for TI K3 SoC PLL
From: Tero Kristo
Add support for TI K3 SoC PLLs. This clock type supports
enabling/disabling/setting and querying the clock rate for the PLL. The
euclidean library routine is used to calculate divider/multiplier rates
for the PLLs.
Signed-off-by: Tero Kristo
Signed-off-by: Tero Kristo
---
drivers/clk/ti/Kconfig | 12 ++
drivers/clk/ti/Makefile | 1 +
drivers/clk/ti/clk-k3-pll.c | 283
include/k3-clk.h| 15 ++
4 files changed, 311 insertions(+)
create mode 100644 drivers/clk/ti/clk-k3-pll.c
create mode 100644 include/k3-clk.h
diff --git a/drivers/clk/ti/Kconfig b/drivers/clk/ti/Kconfig
index 2dc86d44a9..a8ec4f541a 100644
--- a/drivers/clk/ti/Kconfig
+++ b/drivers/clk/ti/Kconfig
@@ -41,3 +41,15 @@ config CLK_TI_SCI
This enables the clock driver support over TI System Control Interface
available on some new TI's SoCs. If you wish to use clock resources
managed by the TI System Controller, say Y here. Otherwise, say N.
+
+config CLK_K3_PLL
+ bool "PLL clock support for K3 SoC family of devices"
+ depends on CLK && LIB_RATIONAL
+ help
+ Enables PLL clock support for K3 SoC family of devices.
+
+config SPL_CLK_K3_PLL
+ bool "PLL clock support for K3 SoC family of devices"
+ depends on CLK && LIB_RATIONAL && SPL
+ help
+ Enables PLL clock support for K3 SoC family of devices.
diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile
index 9f56b47736..47839213e5 100644
--- a/drivers/clk/ti/Makefile
+++ b/drivers/clk/ti/Makefile
@@ -11,3 +11,4 @@ obj-$(CONFIG_CLK_TI_DIVIDER) += clk-divider.o
obj-$(CONFIG_CLK_TI_GATE) += clk-gate.o
obj-$(CONFIG_CLK_TI_MUX) += clk-mux.o
obj-$(CONFIG_CLK_TI_SCI) += clk-sci.o
+obj-$(CONFIG_$(SPL_TPL_)CLK_K3_PLL) += clk-k3-pll.o
diff --git a/drivers/clk/ti/clk-k3-pll.c b/drivers/clk/ti/clk-k3-pll.c
new file mode 100644
index 00..bf2407a020
--- /dev/null
+++ b/drivers/clk/ti/clk-k3-pll.c
@@ -0,0 +1,283 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Texas Instruments K3 SoC PLL clock driver
+ *
+ * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
+ * Tero Kristo
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include "k3-clk.h"
+#include
+
+/* 16FFT register offsets */
+#define PLL_16FFT_CFG 0x08
+#define PLL_KICK0 0x10
+#define PLL_KICK1 0x14
+#define PLL_16FFT_CTRL 0x20
+#define PLL_16FFT_STAT 0x24
+#define PLL_16FFT_FREQ_CTRL0 0x30
+#define PLL_16FFT_FREQ_CTRL1 0x34
+#define PLL_16FFT_DIV_CTRL 0x38
+
+/* CTRL register bits */
+#define PLL_16FFT_CTRL_BYPASS_EN BIT(31)
+#define PLL_16FFT_CTRL_PLL_EN BIT(15)
+#define PLL_16FFT_CTRL_DSM_EN BIT(1)
+
+/* STAT register bits */
+#define PLL_16FFT_STAT_LOCKBIT(0)
+
+/* FREQ_CTRL0 bits */
+#define PLL_16FFT_FREQ_CTRL0_FB_DIV_INT_MASK 0xfff
+
+/* DIV CTRL register bits */
+#define PLL_16FFT_DIV_CTRL_REF_DIV_MASK0x3f
+
+#define PLL_16FFT_FREQ_CTRL1_FB_DIV_FRAC_BITS 24
+#define PLL_16FFT_HSDIV_CTRL_CLKOUT_EN BIT(15)
+
+/* KICK register magic values */
+#define PLL_KICK0_VALUE0x68ef3490
+#define PLL_KICK1_VALUE0xd172bc5a
+
+/**
+ * struct ti_pll_clk - TI PLL clock data info structure
+ * @clk: core clock structure
+ * @reg: memory address of the PLL controller
+ */
+struct ti_pll_clk {
+ struct clk clk;
+ void __iomem*reg;
+};
+
+#define to_clk_pll(_clk) container_of(_clk, struct ti_pll_clk, clk)
+
+static int ti_pll_wait_for_lock(struct clk *clk)
+{
+ struct ti_pll_clk *pll = to_clk_pll(clk);
+ u32 stat;
+ int i;
+
+ for (i = 0; i < 10; i++) {
+ stat = readl(pll->reg + PLL_16FFT_STAT);
+ if (stat & PLL_16FFT_STAT_LOCK)
+ return 0;
+ }
+
+ printf("%s: pll (%s) failed to lock\n", __func__,
+ clk->dev->name);
+
+ return -EBUSY;
+}
+
+static ulong ti_pll_clk_get_rate(struct clk *clk)
+{
+ struct ti_pll_clk *pll = to_clk_pll(clk);
+ u64 current_freq;
+ u64 parent_freq = clk_get_parent_rate(clk);
+ u32 pllm;
+ u32 plld;
+ u32 pllfm;
+ u32 ctrl;
+
+ /* Check if we are in bypass */
+ ctrl = readl(pll->reg + PLL_16FFT_CTRL);
+ if (ctrl & PLL_16FFT_CTRL_BYPASS_EN)
+ return parent_freq;
+
+ pllm = readl(pll->reg + PLL_16FFT_FREQ_CTRL0);
+ pllfm = readl(pll->reg + PLL_16FFT_FREQ_CTRL1);
+
+ plld = readl(pll->reg + PLL_16FFT_DIV_CTRL) &
+ PLL_16FFT_DIV_CTRL_REF_DIV_MASK;
+
+ current_freq = parent_freq * pllm / plld;
+
+ if (pllfm) {
+ u64 tmp;
+
+ tmp = parent_freq * pllfm;
+ do_div(tmp, plld);
+
[PATCHv4 11/26] clk: fix set_rate to clean up cached rates for the hierarchy
From: Tero Kristo
Clock rates are cached within the individual clock nodes, and right now
if one changes a clock rate somewhere in the middle of the tree, none
of its child clocks notice the change. To fix this, clear up all the
cached rates for us and our child clocks.
Signed-off-by: Tero Kristo
Signed-off-by: Tero Kristo
---
drivers/clk/clk-uclass.c | 19 +++
1 file changed, 19 insertions(+)
diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c
index 5ebf7a33cb..0e495a6a2e 100644
--- a/drivers/clk/clk-uclass.c
+++ b/drivers/clk/clk-uclass.c
@@ -565,6 +565,22 @@ ulong clk_round_rate(struct clk *clk, ulong rate)
return ops->round_rate(clk, rate);
}
+static void clk_clean_rate_cache(struct clk *clk)
+{
+ struct udevice *child_dev;
+ struct clk *clkp;
+
+ if (!clk)
+ return;
+
+ clk->rate = 0;
+
+ list_for_each_entry(child_dev, &clk->dev->child_head, sibling_node) {
+ clkp = dev_get_clk_ptr(child_dev);
+ clk_clean_rate_cache(clkp);
+ }
+}
+
ulong clk_set_rate(struct clk *clk, ulong rate)
{
const struct clk_ops *ops;
@@ -577,6 +593,9 @@ ulong clk_set_rate(struct clk *clk, ulong rate)
if (!ops->set_rate)
return -ENOSYS;
+ /* Clean up cached rates for us and all child clocks */
+ clk_clean_rate_cache(clk);
+
return ops->set_rate(clk, rate);
}
--
2.17.1
[PATCHv4 09/26] clk: sci-clk: fix return value of set_rate
From: Tero Kristo
Set rate should return the new clock rate on success, and negative error
value on failure. Fix this, as currently set_rate returns 0 on success.
Signed-off-by: Tero Kristo
Signed-off-by: Tero Kristo
---
drivers/clk/ti/clk-sci.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/ti/clk-sci.c b/drivers/clk/ti/clk-sci.c
index 6f0fdaa111..acb9eadf03 100644
--- a/drivers/clk/ti/clk-sci.c
+++ b/drivers/clk/ti/clk-sci.c
@@ -111,10 +111,12 @@ static ulong ti_sci_clk_set_rate(struct clk *clk, ulong
rate)
#endif
ret = cops->set_freq(sci, clk->id, clk->data, 0, rate, ULONG_MAX);
- if (ret)
+ if (ret) {
dev_err(clk->dev, "%s: set_freq failed (%d)\n", __func__, ret);
+ return ret;
+ }
- return ret;
+ return rate;
}
static int ti_sci_clk_set_parent(struct clk *clk, struct clk *parent)
--
2.17.1
[PATCHv4 10/26] clk: fix assigned-clocks to pass with deferring provider
From: Tero Kristo
If a clock provider is not ready for assigning default rates/parents
during its probe, it may return -EPROBE_DEFER directly from xlate.
Handle this special case properly by skipping the entry and adjusting the
return value to pass. The defaults will be handled properly in post probe
phase then.
Signed-off-by: Tero Kristo
Signed-off-by: Tero Kristo
---
drivers/clk/clk-uclass.c | 18 ++
1 file changed, 18 insertions(+)
diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c
index ac2b7ae84e..5ebf7a33cb 100644
--- a/drivers/clk/clk-uclass.c
+++ b/drivers/clk/clk-uclass.c
@@ -240,6 +240,15 @@ static int clk_set_default_parents(struct udevice *dev,
int stage)
ret = clk_get_by_indexed_prop(dev, "assigned-clocks",
index, &clk);
+ /*
+* If the clock provider is not ready yet, let it handle
+* the re-programming later.
+*/
+ if (ret == -EPROBE_DEFER) {
+ ret = 0;
+ continue;
+ }
+
if (ret) {
debug("%s: could not get assigned clock %d for %s\n",
__func__, index, dev_read_name(dev));
@@ -308,6 +317,15 @@ static int clk_set_default_rates(struct udevice *dev, int
stage)
ret = clk_get_by_indexed_prop(dev, "assigned-clocks",
index, &clk);
+ /*
+* If the clock provider is not ready yet, let it handle
+* the re-programming later.
+*/
+ if (ret == -EPROBE_DEFER) {
+ ret = 0;
+ continue;
+ }
+
if (ret) {
debug("%s: could not get assigned clock %d for %s\n",
__func__, index, dev_read_name(dev));
--
2.17.1
[PATCHv4 08/26] clk: add support for setting clk rate from cmdline
From: Tero Kristo
Add new clk subcommand "clk setfreq", for setting up a clock rate
directly from u-boot cmdline. This is handy for any debugging purposes
towards clocks.
Acked-by: Lukasz Majewski
Signed-off-by: Tero Kristo
Signed-off-by: Tero Kristo
---
cmd/clk.c | 49 +++--
1 file changed, 47 insertions(+), 2 deletions(-)
diff --git a/cmd/clk.c b/cmd/clk.c
index 0245b97136..fd7944c02e 100644
--- a/cmd/clk.c
+++ b/cmd/clk.c
@@ -98,8 +98,52 @@ static int do_clk_dump(struct cmd_tbl *cmdtp, int flag, int
argc,
return ret;
}
+struct udevice *clk_lookup(const char *name)
+{
+ int i = 0;
+ struct udevice *dev;
+
+ do {
+ uclass_get_device(UCLASS_CLK, i++, &dev);
+ if (!strcmp(name, dev->name))
+ return dev;
+ } while (dev);
+
+ return NULL;
+}
+
+static int do_clk_setfreq(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ struct clk *clk = NULL;
+ s32 freq;
+ struct udevice *dev;
+
+ freq = simple_strtoul(argv[2], NULL, 10);
+
+ dev = clk_lookup(argv[1]);
+
+ if (dev)
+ clk = dev_get_clk_ptr(dev);
+
+ if (!clk) {
+ printf("clock '%s' not found.\n", argv[1]);
+ return -EINVAL;
+ }
+
+ freq = clk_set_rate(clk, freq);
+ if (freq < 0) {
+ printf("set_rate failed: %d\n", freq);
+ return CMD_RET_FAILURE;
+ }
+
+ printf("set_rate returns %u\n", freq);
+ return 0;
+}
+
static struct cmd_tbl cmd_clk_sub[] = {
U_BOOT_CMD_MKENT(dump, 1, 1, do_clk_dump, "", ""),
+ U_BOOT_CMD_MKENT(setfreq, 3, 1, do_clk_setfreq, "", ""),
};
static int do_clk(struct cmd_tbl *cmdtp, int flag, int argc,
@@ -124,7 +168,8 @@ static int do_clk(struct cmd_tbl *cmdtp, int flag, int argc,
#ifdef CONFIG_SYS_LONGHELP
static char clk_help_text[] =
- "dump - Print clock frequencies";
+ "dump - Print clock frequencies\n"
+ "setfreq [clk] [freq] - Set clock frequency";
#endif
-U_BOOT_CMD(clk, 2, 1, do_clk, "CLK sub-system", clk_help_text);
+U_BOOT_CMD(clk, 4, 1, do_clk, "CLK sub-system", clk_help_text);
--
2.17.1
[PATCHv4 06/26] clk: fix clock tree dump to properly dump out every registered clock
From: Tero Kristo
Some clocks are not associated to a DM node, so just parsing the DM is not
enough. This is especially true for root clocks, which typically don't have
any parents. Instead, fetch every registered UCLASS_CLK instance, and dump
these out.
Signed-off-by: Tero Kristo
Signed-off-by: Tero Kristo
---
cmd/clk.c | 27 +++
1 file changed, 19 insertions(+), 8 deletions(-)
diff --git a/cmd/clk.c b/cmd/clk.c
index e3c3d2f9bb..0245b97136 100644
--- a/cmd/clk.c
+++ b/cmd/clk.c
@@ -18,11 +18,14 @@ static void show_clks(struct udevice *dev, int depth, int
last_flag)
{
int i, is_last;
struct udevice *child;
- struct clk *clkp;
+ struct clk *clkp, *parent;
u32 rate;
clkp = dev_get_clk_ptr(dev);
if (device_get_uclass_id(dev) == UCLASS_CLK && clkp) {
+ parent = clk_get_parent(clkp);
+ if (!IS_ERR(parent) && depth == -1)
+ return;
depth++;
rate = clk_get_rate(clkp);
@@ -47,6 +50,9 @@ static void show_clks(struct udevice *dev, int depth, int
last_flag)
}
list_for_each_entry(child, &dev->child_head, sibling_node) {
+ if (child == dev)
+ continue;
+
is_last = list_is_last(&child->sibling_node, &dev->child_head);
show_clks(child, depth, (last_flag << 1) | is_last);
}
@@ -54,14 +60,19 @@ static void show_clks(struct udevice *dev, int depth, int
last_flag)
int __weak soc_clk_dump(void)
{
- struct udevice *root;
+ struct udevice *dev;
+ struct uclass *uc;
+ int ret;
- root = dm_root();
- if (root) {
- printf(" Rate Usecnt Name\n");
- printf("--\n");
- show_clks(root, -1, 0);
- }
+ ret = uclass_get(UCLASS_CLK, &uc);
+ if (ret)
+ return ret;
+
+ printf(" Rate Usecnt Name\n");
+ printf("--\n");
+
+ uclass_foreach_dev(dev, uc)
+ show_clks(dev, -1, 0);
return 0;
}
--
2.17.1
[PATCHv4 07/26] clk: do not attempt to fetch clock pointer with null device
From: Tero Kristo Bail out early if device returned for the parent clock is null. This avoids warning prints like this when doing clk dump: dev_get_uclass_priv: null device Signed-off-by: Tero Kristo Signed-off-by: Tero Kristo --- drivers/clk/clk-uclass.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c index 4ab3c402ed..ac2b7ae84e 100644 --- a/drivers/clk/clk-uclass.c +++ b/drivers/clk/clk-uclass.c @@ -499,6 +499,8 @@ struct clk *clk_get_parent(struct clk *clk) return NULL; pdev = dev_get_parent(clk->dev); + if (!pdev) + return ERR_PTR(-ENODEV); pclk = dev_get_clk_ptr(pdev); if (!pclk) return ERR_PTR(-ENODEV); -- 2.17.1
[PATCHv4 04/26] common: fit: Update board_fit_image_post_process() to pass fit and node_offset
From: Lokesh Vutla
board_fit_image_post_process() passes only start and size of the image,
but type of the image is not passed. So pass fit and node_offset, to
derive information about image to be processed.
Signed-off-by: Lokesh Vutla
Reviewed-by: Tom Rini
Signed-off-by: Tero Kristo
---
arch/arm/mach-k3/security.c | 3 ++-
arch/arm/mach-keystone/mon.c | 3 ++-
board/ti/am335x/board.c | 3 ++-
board/ti/am43xx/board.c | 3 ++-
board/ti/am57xx/board.c | 3 ++-
board/ti/dra7xx/evm.c| 3 ++-
common/image-fit.c | 2 +-
common/spl/spl_fit.c | 2 +-
include/image.h | 5 -
9 files changed, 18 insertions(+), 9 deletions(-)
diff --git a/arch/arm/mach-k3/security.c b/arch/arm/mach-k3/security.c
index 66f90a5a34..5b5ff9ba7b 100644
--- a/arch/arm/mach-k3/security.c
+++ b/arch/arm/mach-k3/security.c
@@ -18,7 +18,8 @@
#include
#include
-void board_fit_image_post_process(void **p_image, size_t *p_size)
+void board_fit_image_post_process(const void *fit, int node, void **p_image,
+ size_t *p_size)
{
struct ti_sci_handle *ti_sci = get_ti_sci_handle();
struct ti_sci_proc_ops *proc_ops = &ti_sci->ops.proc_ops;
diff --git a/arch/arm/mach-keystone/mon.c b/arch/arm/mach-keystone/mon.c
index 58995d73ac..b863bab196 100644
--- a/arch/arm/mach-keystone/mon.c
+++ b/arch/arm/mach-keystone/mon.c
@@ -103,7 +103,8 @@ static int k2_hs_bm_auth(int cmd, void *arg1)
return result;
}
-void board_fit_image_post_process(void **p_image, size_t *p_size)
+void board_fit_image_post_process(const void *fit, int node, void **p_image,
+ size_t *p_size)
{
int result = 0;
void *image = *p_image;
diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c
index bc1657e88f..6952484d01 100644
--- a/board/ti/am335x/board.c
+++ b/board/ti/am335x/board.c
@@ -957,7 +957,8 @@ int board_fit_config_name_match(const char *name)
#endif
#ifdef CONFIG_TI_SECURE_DEVICE
-void board_fit_image_post_process(void **p_image, size_t *p_size)
+void board_fit_image_post_process(const void *fit, int node, void **p_image,
+ size_t *p_size)
{
secure_boot_verify_image(p_image, p_size);
}
diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c
index e9febb9592..a71b588efc 100644
--- a/board/ti/am43xx/board.c
+++ b/board/ti/am43xx/board.c
@@ -896,7 +896,8 @@ int embedded_dtb_select(void)
#endif
#ifdef CONFIG_TI_SECURE_DEVICE
-void board_fit_image_post_process(void **p_image, size_t *p_size)
+void board_fit_image_post_process(const void *fit, int node, void **p_image,
+ size_t *p_size)
{
secure_boot_verify_image(p_image, p_size);
}
diff --git a/board/ti/am57xx/board.c b/board/ti/am57xx/board.c
index 73063faee6..99d1ad3215 100644
--- a/board/ti/am57xx/board.c
+++ b/board/ti/am57xx/board.c
@@ -1198,7 +1198,8 @@ static int board_bootmode_has_emmc(void)
#endif
#ifdef CONFIG_TI_SECURE_DEVICE
-void board_fit_image_post_process(void **p_image, size_t *p_size)
+void board_fit_image_post_process(const void *fit, int node, void **p_image,
+ size_t *p_size)
{
secure_boot_verify_image(p_image, p_size);
}
diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c
index 05f251f778..23e8005991 100644
--- a/board/ti/dra7xx/evm.c
+++ b/board/ti/dra7xx/evm.c
@@ -1065,7 +1065,8 @@ int fastboot_set_reboot_flag(enum fastboot_reboot_reason
reason)
#endif
#ifdef CONFIG_TI_SECURE_DEVICE
-void board_fit_image_post_process(void **p_image, size_t *p_size)
+void board_fit_image_post_process(const void *fit, int node, void **p_image,
+ size_t *p_size)
{
secure_boot_verify_image(p_image, p_size);
}
diff --git a/common/image-fit.c b/common/image-fit.c
index e614643fe3..0c5a05948d 100644
--- a/common/image-fit.c
+++ b/common/image-fit.c
@@ -2143,7 +2143,7 @@ int fit_image_load(bootm_headers_t *images, ulong addr,
/* perform any post-processing on the image data */
if (!host_build() && IS_ENABLED(CONFIG_FIT_IMAGE_POST_PROCESS))
- board_fit_image_post_process(&buf, &size);
+ board_fit_image_post_process(fit, noffset, &buf, &size);
len = (ulong)size;
diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c
index 4288f571fc..9f17146f78 100644
--- a/common/spl/spl_fit.c
+++ b/common/spl/spl_fit.c
@@ -316,7 +316,7 @@ static int spl_load_fit_image(struct spl_load_info *info,
ulong sector,
}
if (CONFIG_IS_ENABLED(FIT_IMAGE_POST_PROCESS))
- board_fit_image_post_process(&src, &length);
+ board_fit_image_post_process(fit, node, &src, &length);
load_ptr = map_sysmem(load_addr, length);
if (IS_ENABLED(CONFIG_SPL_GZIP) && image_comp == IH_COMP_GZIP) {
diff --git a/include/image.h b/include/image.h
index 459685d4d4..0c24bf6f35 100644
---
[PATCHv4 05/26] clk: fixed_rate: add API for directly registering fixed rate clocks
From: Tero Kristo
Current driver only supports registering fixed rate clocks from DT. Add
new API which makes it possible to register fixed rate clocks directly
from e.g. platform specific clock drivers.
Reviewed-by: Peng Fan
Signed-off-by: Tero Kristo
Signed-off-by: Tero Kristo
---
drivers/clk/clk_fixed_rate.c | 43
include/linux/clk-provider.h | 3 +++
2 files changed, 46 insertions(+)
diff --git a/drivers/clk/clk_fixed_rate.c b/drivers/clk/clk_fixed_rate.c
index 09f9ef26a4..c591abf685 100644
--- a/drivers/clk/clk_fixed_rate.c
+++ b/drivers/clk/clk_fixed_rate.c
@@ -9,6 +9,9 @@
#include
#include
+#define UBOOT_DM_CLK_FIXED_RATE "fixed_rate_clock"
+#define UBOOT_DM_CLK_FIXED_RATE_RAW "fixed_rate_raw_clock"
+
static ulong clk_fixed_rate_get_rate(struct clk *clk)
{
return to_clk_fixed_rate(clk->dev)->fixed_rate;
@@ -40,6 +43,15 @@ void clk_fixed_rate_ofdata_to_plat_(struct udevice *dev,
clk->enable_count = 0;
}
+static ulong clk_fixed_rate_raw_get_rate(struct clk *clk)
+{
+ return container_of(clk, struct clk_fixed_rate, clk)->fixed_rate;
+}
+
+const struct clk_ops clk_fixed_rate_raw_ops = {
+ .get_rate = clk_fixed_rate_raw_get_rate,
+};
+
static int clk_fixed_rate_of_to_plat(struct udevice *dev)
{
clk_fixed_rate_ofdata_to_plat_(dev, to_clk_fixed_rate(dev));
@@ -47,6 +59,30 @@ static int clk_fixed_rate_of_to_plat(struct udevice *dev)
return 0;
}
+struct clk *clk_register_fixed_rate(struct device *dev, const char *name,
+ ulong rate)
+{
+ struct clk *clk;
+ struct clk_fixed_rate *fixed;
+ int ret;
+
+ fixed = kzalloc(sizeof(*fixed), GFP_KERNEL);
+ if (!fixed)
+ return ERR_PTR(-ENOMEM);
+
+ fixed->fixed_rate = rate;
+
+ clk = &fixed->clk;
+
+ ret = clk_register(clk, UBOOT_DM_CLK_FIXED_RATE_RAW, name, NULL);
+ if (ret) {
+ kfree(fixed);
+ return ERR_PTR(ret);
+ }
+
+ return clk;
+}
+
static const struct udevice_id clk_fixed_rate_match[] = {
{
.compatible = "fixed-clock",
@@ -63,3 +99,10 @@ U_BOOT_DRIVER(fixed_clock) = {
.ops = &clk_fixed_rate_ops,
.flags = DM_FLAG_PRE_RELOC,
};
+
+U_BOOT_DRIVER(clk_fixed_rate_raw) = {
+ .name = UBOOT_DM_CLK_FIXED_RATE_RAW,
+ .id = UCLASS_CLK,
+ .ops = &clk_fixed_rate_raw_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 6fda14f5fe..9d296f240a 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -247,6 +247,9 @@ struct clk *clk_register_mux(struct device *dev, const char
*name,
void __iomem *reg, u8 shift, u8 width,
u8 clk_mux_flags);
+struct clk *clk_register_fixed_rate(struct device *dev, const char *name,
+ ulong rate);
+
const char *clk_hw_get_name(const struct clk *hw);
ulong clk_generic_get_rate(struct clk *clk);
--
2.17.1
[PATCHv4 03/26] remoteproc: k3-r5: remove sysfw PM calls if not supported
From: Tero Kristo
With the sysfw rearch, sysfw PM calls are no longer available from SPL
level. To properly support this, remove the is_on checks and the reset
assertion from the R5 remoteproc driver as these are not supported.
Attempting to access unavailable services will cause the device to hang.
Signed-off-by: Tero Kristo
Signed-off-by: Tero Kristo
---
drivers/remoteproc/ti_k3_r5f_rproc.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/remoteproc/ti_k3_r5f_rproc.c
b/drivers/remoteproc/ti_k3_r5f_rproc.c
index 3c569a3b7b..c8c30b9020 100644
--- a/drivers/remoteproc/ti_k3_r5f_rproc.c
+++ b/drivers/remoteproc/ti_k3_r5f_rproc.c
@@ -781,7 +781,9 @@ static int k3_r5f_probe(struct udevice *dev)
{
struct k3_r5f_cluster *cluster = dev_get_priv(dev->parent);
struct k3_r5f_core *core = dev_get_priv(dev);
+#ifndef CONFIG_K3_DM_FW
bool r_state;
+#endif
int ret;
dev_dbg(dev, "%s\n", __func__);
@@ -804,6 +806,12 @@ static int k3_r5f_probe(struct udevice *dev)
return ret;
}
+ /*
+* The PM functionality is not supported by the firmware during
+* SPL execution with the separated DM firmware image. The following
+* piece of code is not compiled in that case.
+*/
+#ifndef CONFIG_K3_DM_FW
ret = core->tsp.sci->ops.dev_ops.is_on(core->tsp.sci, core->tsp.dev_id,
&r_state, &core->in_use);
if (ret)
@@ -817,6 +825,7 @@ static int k3_r5f_probe(struct udevice *dev)
/* Make sure Local reset is asserted. Redundant? */
reset_assert(&core->reset);
+#endif
ret = k3_r5f_rproc_configure(core);
if (ret) {
--
2.17.1
[PATCHv4 02/26] arm: mach-k3: introduce new config option for sysfw split
From: Tero Kristo On J7 family of SoCs (J721E and J7200), sysfw is being split to be run under two cores, TIFS portion on DMSC core, and DM firmware under MCU R5. As MCU R5 is also used to run one phase of the bootloader, we must prevent access from here towards sysfw services. To support this, add new config option which can be used to detect presence of RM/PM sysfw services. Signed-off-by: Tero Kristo Signed-off-by: Tero Kristo --- arch/arm/mach-k3/Kconfig | 11 +++ 1 file changed, 11 insertions(+) diff --git a/arch/arm/mach-k3/Kconfig b/arch/arm/mach-k3/Kconfig index c7d186149b..c92722eab6 100644 --- a/arch/arm/mach-k3/Kconfig +++ b/arch/arm/mach-k3/Kconfig @@ -141,6 +141,17 @@ config SYS_K3_SPL_ATF Enabling this will try to start Cortex-A (typically with ATF) after SPL from R5. +config K3_DM_FW + bool "Separate DM firmware image" + depends on SPL && CPU_V7R && SOC_K3_J721E && !CLK_TI_SCI && !TI_SCI_POWER_DOMAIN + default y + help + Enabling this will indicate that the system has separate DM + and TIFS firmware images in place, instead of a single SYSFW + firmware. Due to DM being executed on the same core as R5 SPL + bootloader, it makes RM and PM services not being available + during R5 SPL execution time. + source "board/ti/am65x/Kconfig" source "board/ti/j721e/Kconfig" endif -- 2.17.1
[PATCHv4 00/26] J72xx: HSM rearch support series
Hello, Couple of small changes in v4: - re-worked patch #14 to include review comments from Jaehoon Chung * changed code to use iopoll version instead of hand crafted loops for timeout handling * other mostly cosmetic changes - patch #19/#21 changed to allow RM init to happen based on comment from Vignesh -Tero
[PATCHv4 01/26] lib: rational: copy the rational fraction lib routines from Linux
From: Tero Kristo
Copy the best rational approximation calculation routines from Linux.
Typical usecase for these routines is to calculate the M/N divider
values for PLLs to reach a specific clock rate.
This is based on linux kernel commit:
"lib/math/rational.c: fix possible incorrect result from rational
fractions helper"
(sha1: 323dd2c3ed0641f49e89b4e420f9eef5d3d5a881)
Signed-off-by: Tero Kristo
Reviewed-by: Tom Rini
Signed-off-by: Tero Kristo
---
include/linux/rational.h | 20
lib/Kconfig | 7 +++
lib/Makefile | 2 +
lib/rational.c | 99
4 files changed, 128 insertions(+)
create mode 100644 include/linux/rational.h
create mode 100644 lib/rational.c
diff --git a/include/linux/rational.h b/include/linux/rational.h
new file mode 100644
index 00..33f5f5fc3e
--- /dev/null
+++ b/include/linux/rational.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * rational fractions
+ *
+ * Copyright (C) 2009 emlix GmbH, Oskar Schirmer
+ *
+ * helper functions when coping with rational numbers,
+ * e.g. when calculating optimum numerator/denominator pairs for
+ * pll configuration taking into account restricted register size
+ */
+
+#ifndef _LINUX_RATIONAL_H
+#define _LINUX_RATIONAL_H
+
+void rational_best_approximation(
+ unsigned long given_numerator, unsigned long given_denominator,
+ unsigned long max_numerator, unsigned long max_denominator,
+ unsigned long *best_numerator, unsigned long *best_denominator);
+
+#endif /* _LINUX_RATIONAL_H */
diff --git a/lib/Kconfig b/lib/Kconfig
index 6d2d41de30..68d58aa90d 100644
--- a/lib/Kconfig
+++ b/lib/Kconfig
@@ -663,6 +663,13 @@ config GENERATE_SMBIOS_TABLE
See also SMBIOS_SYSINFO which allows SMBIOS values to be provided in
the devicetree.
+config LIB_RATIONAL
+ bool "enable continued fraction calculation routines"
+
+config SPL_LIB_RATIONAL
+ bool "enable continued fraction calculation routines for SPL"
+ depends on SPL
+
endmenu
config ASN1_COMPILER
diff --git a/lib/Makefile b/lib/Makefile
index 6825671955..ea6bd0cb55 100644
--- a/lib/Makefile
+++ b/lib/Makefile
@@ -73,6 +73,8 @@ obj-$(CONFIG_$(SPL_)LZO) += lzo/
obj-$(CONFIG_$(SPL_)LZMA) += lzma/
obj-$(CONFIG_$(SPL_)LZ4) += lz4_wrapper.o
+obj-$(CONFIG_$(SPL_)LIB_RATIONAL) += rational.o
+
obj-$(CONFIG_LIBAVB) += libavb/
obj-$(CONFIG_$(SPL_TPL_)OF_LIBFDT) += libfdt/
diff --git a/lib/rational.c b/lib/rational.c
new file mode 100644
index 00..316db3b590
--- /dev/null
+++ b/lib/rational.c
@@ -0,0 +1,99 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * rational fractions
+ *
+ * Copyright (C) 2009 emlix GmbH, Oskar Schirmer
+ * Copyright (C) 2019 Trent Piepho
+ *
+ * helper functions when coping with rational numbers
+ */
+
+#include
+#include
+#include
+
+/*
+ * calculate best rational approximation for a given fraction
+ * taking into account restricted register size, e.g. to find
+ * appropriate values for a pll with 5 bit denominator and
+ * 8 bit numerator register fields, trying to set up with a
+ * frequency ratio of 3.1415, one would say:
+ *
+ * rational_best_approximation(31415, 1,
+ * (1 << 8) - 1, (1 << 5) - 1, &n, &d);
+ *
+ * you may look at given_numerator as a fixed point number,
+ * with the fractional part size described in given_denominator.
+ *
+ * for theoretical background, see:
+ * http://en.wikipedia.org/wiki/Continued_fraction
+ */
+
+void rational_best_approximation(
+ unsigned long given_numerator, unsigned long given_denominator,
+ unsigned long max_numerator, unsigned long max_denominator,
+ unsigned long *best_numerator, unsigned long *best_denominator)
+{
+ /* n/d is the starting rational, which is continually
+* decreased each iteration using the Euclidean algorithm.
+*
+* dp is the value of d from the prior iteration.
+*
+* n2/d2, n1/d1, and n0/d0 are our successively more accurate
+* approximations of the rational. They are, respectively,
+* the current, previous, and two prior iterations of it.
+*
+* a is current term of the continued fraction.
+*/
+ unsigned long n, d, n0, d0, n1, d1, n2, d2;
+ n = given_numerator;
+ d = given_denominator;
+ n0 = d1 = 0;
+ n1 = d0 = 1;
+
+ for (;;) {
+ unsigned long dp, a;
+
+ if (d == 0)
+ break;
+ /* Find next term in continued fraction, 'a', via
+* Euclidean algorithm.
+*/
+ dp = d;
+ a = n / d;
+ d = n % d;
+ n = dp;
+
+ /* Calculate the current rational approximation (aka
+* convergent), n2/d2, using the term just found and
+* the two prior approximations.
+*/
+ n2 = n0 + a * n
Re: BeagleBone Green Wireless - serial debug port hangs after sending u-boot-spl.bin (since v2021.01)
On Sat, May 8, 2021 at 1:40 AM Tom Rini wrote:
> On Sat, May 08, 2021 at 12:02:21AM +0800, Darren Ng wrote:
>
> > (Hello, from a U-Boot NOOB.)
> >
> > Issue
> > -
> > After sending u-boot-spl.bin with xmodem, the serial debug port seems to
> > hang.
> > Neither "...U-Boot SPL...\n...\nTrying to boot from UART..."
> > nor "CCC..." shows up in minicom.
> > Always 0% if I try sending u-boot.img with xmodem anyway.
> >
> > Target Device
> > -
> > Seeed Studio BeagleBone® Green Wireless
> > https://seeeddoc.github.io/Beaglebone_green_wireless/
> >
> https://wiki.seeedstudio.com/BeagleBone_Green_Wireless/#hardware-overview
> >
> https://source.denx.de/u-boot/u-boot/-/commits/master/configs/am335x_boneblack_vboot_defconfig
> >
> > Matrix
> > --
> > This issue applies to tags ever since v2021.01. In the following table:
> > (x) - This issue applies.
> > (O) - I can send both u-boot-spl.bin and u-boot.img
> > then execute u-boot commands without trouble.
> > --
> > tag result
> > --
> > v2021.07-rc1 (x) hangs
> > v2021.04 (x) hangs
> > v2021.01 (x) hangs
> > v2020.10 (O) success
>
> It looks like something broke between v2020.10 and v2021.01 then. Since
> you have a testcase, using "git bisect" should help figure out which
> exact commit broke things.
>
> --
> Tom
>
("reply all" instead of "reply")
v2021.04 running successfully with am335x_evm_defconfig(AED) now
> commit 8fa7f65dd02c176ee6021eaf40114560b8954ba2
> Author: Faiz Abbas
> Date: Thu Jan 17 15:44:06 2019 +0530
>
> configs: Remove am335x_boneblack_defconfig
>
> The am335x_evm_defconfig supports all am335x_boneblack variants.
Remove
> the redundant am335x_boneblack_defconfig.
>
> Signed-off-by: Faiz Abbas
> Reviewed-by: Tom Rini
>
> D configs/am335x_boneblack_defconfig
According to the commit log above, a previous
am335x_boneblack_defconfig(ABD)
is removed in favor of am335x_evm_defconfig(AED)
However there is a am335x_boneblack_vboot_defconfig(ABVD) in the tree,
which is what I have failed with.
What does am335x_boneblack_vboot_defconfig(ABVD) do?
What is the meaning of "_vboot_"?
Is that "Verified Boot" as of
<
https://source.denx.de/u-boot/u-boot/-/blob/master/test/py/tests/test_vboot.py
>?
If so, do I need it?
[PATCH] configs: ti: enable TFTP_SIZE
This fits the TFTP progress bar on single line based on the size of the
file being downloaded, reducing unnecessary spam and also making it
easier to track the download progress.
Signed-off-by: Tero Kristo
---
include/configs/ti_armv7_common.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/configs/ti_armv7_common.h
b/include/configs/ti_armv7_common.h
index f13e9e5264..f40089a3fd 100644
--- a/include/configs/ti_armv7_common.h
+++ b/include/configs/ti_armv7_common.h
@@ -205,6 +205,8 @@
"run netloadfdt; " \
"run netargs; " \
"bootz ${loadaddr} - ${fdtaddr}\0"
+
+#define CONFIG_TFTP_TSIZE
#else
#define NETARGS ""
#endif
--
2.17.1
RE: [PATCH] Revert "mmc: sdhci: set to INT_DATA_END when there are data"
Hi Jaehoon > If you're ok, I will test after reverted the patch on tomorrow, and I will > share > result. > Or I will try to reproduce timeout issue on 410c board. Sorry, but is there any update for this comments? Best Regards Andy Wu > -Original Message- > From: U-Boot On Behalf Of Jaehoon Chung > Sent: Tuesday, April 6, 2021 7:13 PM > To: Peng Fan ; jh80.ch...@gmail.com; > u-boot@lists.denx.de > Subject: Re: [PATCH] Revert "mmc: sdhci: set to INT_DATA_END when there are > data" > > Hi Peng, > > On 4/6/21 7:02 PM, Peng Fan wrote: > >> Subject: RE: [PATCH] Revert "mmc: sdhci: set to INT_DATA_END when > >> there are data" > >> > >> Hi Jaehoon > >> > >>> Did you test on latest u-boot? v2018.01 was too old version. > >>> > >> Yes, we tested on v2020.04, although there is no such issue, but I > >> think it just depends on call sequence timing. > >> > >>> And if my understanding is right, INT_DATA_END needs to set when > >>> there is a data. If there is no data, it doesn't need to set to it. > >>> Logically, there is no > >> problem, isn't? > >>> > >> If there is no data, but current command is RESPONSE-WITH-BUSY (like > >> CMD6) type, the INT_DATA_END needs set also, refer sdhci spec > >> explanation for INT_DATA_END bit: > >> > >> Transfer Complete > >> This bit indicates stop of transaction on three cases: > >> ... > >> (2) Completion of a command pairing with response-with-busy (R1b, > >> R5b) > >> > >> So, our modification just within if (cmd->resp_type & MMC_RSP_BUSY) > >> judgment. > > > > Jaehoon, > > > > Do you see any issue if revert the patch? > > If you're ok, I will test after reverted the patch on tomorrow, and I will > share > result. > Or I will try to reproduce timeout issue on 410c board. > > Best Regards, > Jaehoon Chung > > > > Thanks, > > Peng. > > > >> > >> Best Regards > >> Andy Wu > >> > >>> -Original Message- > >>> From: Jaehoon Chung > >>> Sent: Monday, March 22, 2021 6:03 PM > >>> To: Wu, Andy ; jh80.ch...@samsung.com; Mo, > >> Yuezhang > >>> ; u-boot@lists.denx.de > >>> Cc: peng@nxp.com; c...@samsung.com > >>> Subject: Re: [PATCH] Revert "mmc: sdhci: set to INT_DATA_END when > >>> there are data" > >>> > >>> Hi Andy, > >>> > >>> On 3/18/21 10:59 AM, andy...@sony.com wrote: > Hi > > > I don't want to revert this commit. Is there any issue without this? > Without revert commit 17ea3c86, Some board, like Dragonboard 410c > will meet transfer data timeout error (we used v2018.01): > > U-Boot 2018.01 (Nov 26 2020 - 03:31:09 +) Qualcomm-DragonBoard > 410C > > DRAM: 986 MiB > MMC: sdhci@07824000: 0, sdhci@07864000: 1 > sdhci_transfer_data: Transfer data timeout > mmc_init: -70, time 10645 > *** Warning - No block device, using default environment > > And it seems the 17ea3c86 not followed the sdhci specification as > transfer complete bit should be wait for the BUSY status de-assert. > > Kernel side code also wait the transfer complete bit for > response-with-busy command. > >>> > >>> Did you test on latest u-boot? v2018.01 was too old version. > >>> > >>> And if my understanding is right, INT_DATA_END needs to set when > >>> there is a data. > >>> > >>> If there is no data, it doesn't need to set to it. Logically, there > >>> is no problem, > >> isn't? > >>> > >>> I will check with QC 410C board for clarifying this problem. > >>> > > > Without this patch, some SoCs have timeout error with stop command. > Sorry, we didn't meet this stop command timeout issue, but I guess > it maybe another issue, and can be fixed with modification limited > to stop command, not for all response-with-busy command. > > Does the SDHCI_QUIRK_BROKEN_R1B can be used for this case? > >>> > >>> Well, it can be used. > >>> > >>> Best Regards, > >>> > >>> Jaehoon Chung > >>> > > Best Regards > Andy Wu > > > -Original Message- > > From: U-Boot On Behalf Of Jaehoon > > Chung > > Sent: Thursday, March 18, 2021 6:44 AM > > To: Mo, Yuezhang ; u-boot@lists.denx.de > > Cc: peng@nxp.com; c...@samsung.com > > Subject: Re: [PATCH] Revert "mmc: sdhci: set to INT_DATA_END when > > there are data" > > > > Hi > > > > On 3/17/21 3:44 PM, yuezhang...@sony.com wrote: > >> This reverts commit 17ea3c862865c0d704646f67dbf8412f9ff54f59. > >> > >> In eMMC specification, for the response-with-busy(R1b, R5b) > >> command, the DAT0 will driven to LOW as BUSY status, and in sdhci > >> specification, the transfer complete bit should be wait for BUSY > >> status de-assert. > >> > >> All response-with-busy commands don't contain data, the data > >> judgement is no need. > > > > I don't want to revert this commit. Is there any issue without this? > > Without this patch, some SoCs have timeout error with stop command. > > > > To prevent it, i
Re: [PATCH] efi_loader: Fix Kconfig for EFI_TCG2 protocol
On Tue, May 11, 2021 at 09:25:04AM +0200, Heinrich Schuchardt wrote: > On 10.05.21 20:26, Ilias Apalodimas wrote: > > EFI_TCG2 depends not only on TPMv2 but also on the underlying algorithms. > > So add the missing SHA1, SHA256, SHA384 and SHA512 we currently support > > as depenmdencies > > Thanks for looking into the dependencies. > > %s/depenmdencies/dependencies/ > > > > > Signed-off-by: Ilias Apalodimas > > --- > > lib/efi_loader/Kconfig | 1 + > > 1 file changed, 1 insertion(+) > > > > diff --git a/lib/efi_loader/Kconfig b/lib/efi_loader/Kconfig > > index 0b99d7c7749b..6decdee6aa3e 100644 > > --- a/lib/efi_loader/Kconfig > > +++ b/lib/efi_loader/Kconfig > > @@ -301,6 +301,7 @@ config EFI_RNG_PROTOCOL > > config EFI_TCG2_PROTOCOL > > bool "EFI_TCG2_PROTOCOL support" > > depends on TPM_V2 > > Should we add default y? We could, the memory 'wasted' for the eventlog is 4kb so I don't think that's too much > > > + depends on SHA1 && SHA256 && SHA384 && SHA512 > > Would select make sense here? > > select SHA1 > select SHA256 > select SHA512_ALGO > select SHA384 > select SHA512 Yea ti would, I can change it if you prefer it. Cheers /Ilias > > Best regards > > Heinrich > > > help > > Provide a EFI_TCG2_PROTOCOL implementation using the TPM hardware > > of the platform. > > >
[PATCH v4,2/2] driver: watchdog: enable wdt command by default
From: MengLi In latest u-boot code, watchdog feature is implemented, so enable wdt command by default. Signed-off-by: Meng Li --- configs/socfpga_stratix10_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/socfpga_stratix10_defconfig b/configs/socfpga_stratix10_defconfig index 02d4ac0dae..0256afe511 100644 --- a/configs/socfpga_stratix10_defconfig +++ b/configs/socfpga_stratix10_defconfig @@ -40,6 +40,7 @@ CONFIG_CMD_CACHE=y CONFIG_CMD_EXT4=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y +CONFIG_CMD_WDT=y CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y -- 2.17.1
