Re: [PULL] u-boot-sh/next
On Fri, Jun 25, 2021 at 03:25:41AM +0200, Marek Vasut wrote: > On 6/25/21 3:22 AM, Tom Rini wrote: > > On Fri, Jun 25, 2021 at 03:14:51AM +0200, Marek Vasut wrote: > > > > > V3U Falcon board support, for next release. > > > > > > The following changes since commit > > > fcf3981161140d265b873a5b609b8867328dc9dc: > > > > > >Merge https://source.denx.de/u-boot/custodians/u-boot-x86 (2021-06-23 > > > 08:46:26 -0400) > > > > > > are available in the Git repository at: > > > > > >git://source.denx.de/u-boot-sh.git next > > > > > > for you to fetch changes up to 0beaae223dd55b3f727f07f38b799a1c58612b1b: > > > > > >ARM: rmobile: Add basic PSCI support for R8A779A0 V3U Falcon > > > (2021-06-24 > > > 20:22:18 +0200) > > > > This isn't against next but master. I see I did forget, sigh, to do > > -rc5 on this past Monday and should just do it this coming Monday, and > > then merge that to next and then grab this. I assume you need some of > > the changes already in master for this? Thanks. > > I don't think so, I just noticed master was newer. > > So just pull this once next catches up? OK, will do. -- Tom signature.asc Description: PGP signature
Re: [PULL] u-boot-sh/next
On 6/25/21 3:22 AM, Tom Rini wrote: On Fri, Jun 25, 2021 at 03:14:51AM +0200, Marek Vasut wrote: V3U Falcon board support, for next release. The following changes since commit fcf3981161140d265b873a5b609b8867328dc9dc: Merge https://source.denx.de/u-boot/custodians/u-boot-x86 (2021-06-23 08:46:26 -0400) are available in the Git repository at: git://source.denx.de/u-boot-sh.git next for you to fetch changes up to 0beaae223dd55b3f727f07f38b799a1c58612b1b: ARM: rmobile: Add basic PSCI support for R8A779A0 V3U Falcon (2021-06-24 20:22:18 +0200) This isn't against next but master. I see I did forget, sigh, to do -rc5 on this past Monday and should just do it this coming Monday, and then merge that to next and then grab this. I assume you need some of the changes already in master for this? Thanks. I don't think so, I just noticed master was newer. So just pull this once next catches up?
Re: [PULL] u-boot-sh/next
On Fri, Jun 25, 2021 at 03:14:51AM +0200, Marek Vasut wrote: > V3U Falcon board support, for next release. > > The following changes since commit fcf3981161140d265b873a5b609b8867328dc9dc: > > Merge https://source.denx.de/u-boot/custodians/u-boot-x86 (2021-06-23 > 08:46:26 -0400) > > are available in the Git repository at: > > git://source.denx.de/u-boot-sh.git next > > for you to fetch changes up to 0beaae223dd55b3f727f07f38b799a1c58612b1b: > > ARM: rmobile: Add basic PSCI support for R8A779A0 V3U Falcon (2021-06-24 > 20:22:18 +0200) This isn't against next but master. I see I did forget, sigh, to do -rc5 on this past Monday and should just do it this coming Monday, and then merge that to next and then grab this. I assume you need some of the changes already in master for this? Thanks. -- Tom signature.asc Description: PGP signature
[PULL] u-boot-sh/next
V3U Falcon board support, for next release. The following changes since commit fcf3981161140d265b873a5b609b8867328dc9dc: Merge https://source.denx.de/u-boot/custodians/u-boot-x86 (2021-06-23 08:46:26 -0400) are available in the Git repository at: git://source.denx.de/u-boot-sh.git next for you to fetch changes up to 0beaae223dd55b3f727f07f38b799a1c58612b1b: ARM: rmobile: Add basic PSCI support for R8A779A0 V3U Falcon (2021-06-24 20:22:18 +0200) Hai Pham (5): clk: renesas: Add R8A779A0 clock tables ARM: dts: renesas: Add R8A779A0 V3U DT extras ARM: renesas: Add R8A779A0 V3U platform code ARM: renesas: Add R8A779A0 V3U Falcon board code ARM: rmobile: Add basic PSCI support for R8A779A0 V3U Falcon Koji Matsuoka (2): ARM: renesas: Add generic timer initialization for V3U Falcon ARM: renesas: Add GICv3 initialization for V3U Falcon Marek Vasut (6): clk: renesas: Handle R8A779A0 V3U clock types in Gen3 clock code gpio: renesas: Handle R8A779A0 V3U INEN register pinctrl: renesas: Import R8A779A0 V3U PFC tables ARM: dts: renesas: Add R8A779A0 V3U DTs and headers ARM: dts: renesas: Add R8A779A0 V3U Falcon DTs ARM: dts: renesas: Add RPC node to R8A779A0 V3U arch/arm/dts/Makefile |3 +- arch/arm/dts/r8a779a0-falcon-cpu.dtsi | 184 arch/arm/dts/r8a779a0-falcon-u-boot.dts | 32 + arch/arm/dts/r8a779a0-falcon.dts | 28 + arch/arm/dts/r8a779a0-u-boot.dtsi | 25 + arch/arm/dts/r8a779a0.dtsi| 970 +++ arch/arm/mach-rmobile/Kconfig.64 | 12 + arch/arm/mach-rmobile/Makefile|4 + arch/arm/mach-rmobile/cpu_info.c |1 + arch/arm/mach-rmobile/include/mach/rmobile.h |1 + arch/arm/mach-rmobile/psci-r8a779a0.c | 49 + board/renesas/falcon/Kconfig | 15 + board/renesas/falcon/MAINTAINERS |6 + board/renesas/falcon/Makefile | 13 + board/renesas/falcon/falcon.c | 101 ++ configs/r8a779a0_falcon_defconfig | 65 ++ drivers/clk/renesas/Kconfig |6 + drivers/clk/renesas/Makefile |1 + drivers/clk/renesas/clk-rcar-gen3.c | 29 + drivers/clk/renesas/r8a779a0-cpg-mssr.c | 300 ++ drivers/clk/renesas/rcar-gen3-cpg.h | 10 + drivers/clk/renesas/renesas-cpg-mssr.c|4 + drivers/clk/renesas/renesas-cpg-mssr.h| 21 + drivers/gpio/gpio-rcar.c | 14 + drivers/pinctrl/renesas/Kconfig |6 + drivers/pinctrl/renesas/Makefile |1 + drivers/pinctrl/renesas/pfc-r8a779a0.c| 4503 ++ drivers/pinctrl/renesas/pfc.c | 12 + drivers/pinctrl/renesas/sh_pfc.h |1 + include/configs/falcon.h | 36 + include/dt-bindings/clock/r8a779a0-cpg-mssr.h | 55 ++ include/dt-bindings/power/r8a779a0-sysc.h | 59 ++ 32 files changed, 6566 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/r8a779a0-falcon-cpu.dtsi create mode 100644 arch/arm/dts/r8a779a0-falcon-u-boot.dts create mode 100644 arch/arm/dts/r8a779a0-falcon.dts create mode 100644 arch/arm/dts/r8a779a0-u-boot.dtsi create mode 100644 arch/arm/dts/r8a779a0.dtsi create mode 100644 arch/arm/mach-rmobile/psci-r8a779a0.c create mode 100644 board/renesas/falcon/Kconfig create mode 100644 board/renesas/falcon/MAINTAINERS create mode 100644 board/renesas/falcon/Makefile create mode 100644 board/renesas/falcon/falcon.c create mode 100644 configs/r8a779a0_falcon_defconfig create mode 100644 drivers/clk/renesas/r8a779a0-cpg-mssr.c create mode 100644 drivers/pinctrl/renesas/pfc-r8a779a0.c create mode 100644 include/configs/falcon.h create mode 100644 include/dt-bindings/clock/r8a779a0-cpg-mssr.h create mode 100644 include/dt-bindings/power/r8a779a0-sysc.h
[PULL] u-boot-sh/master
Beacon board fix, for this release. The following changes since commit fcf3981161140d265b873a5b609b8867328dc9dc: Merge https://source.denx.de/u-boot/custodians/u-boot-x86 (2021-06-23 08:46:26 -0400) are available in the Git repository at: git://source.denx.de/u-boot-sh.git master for you to fetch changes up to 12ef8016736a50feb744b14ac42c7d849dab2f97: ARM: rmobile: beacon: Set CONFIG_RZ_G2 on Beacon boards (2021-06-24 20:22:31 +0200) Adam Ford (1): ARM: rmobile: beacon: Set CONFIG_RZ_G2 on Beacon boards arch/arm/mach-rmobile/Kconfig.64 | 3 +++ 1 file changed, 3 insertions(+)
[PULL] u-boot-usb/master
A few easy MX7 EHCI USB fixes, for this release. The following changes since commit fcf3981161140d265b873a5b609b8867328dc9dc: Merge https://source.denx.de/u-boot/custodians/u-boot-x86 (2021-06-23 08:46:26 -0400) are available in the Git repository at: git://source.denx.de/u-boot-usb.git master for you to fetch changes up to 4822114f4fb4328114da8ab199672656591a150d: usb: ehci-mx6: Do not fail when 'reg' is not found (2021-06-24 20:23:23 +0200) Fabio Estevam (2): usb: ehci-mx6: Move fdtdec_get_alias_seq() inside the CONFIG_MX6 usb: ehci-mx6: Do not fail when 'reg' is not found drivers/usb/host/ehci-mx6.c | 17 - 1 file changed, 8 insertions(+), 9 deletions(-)
Re: Pull request: u-boot-spi/master for next
On Thu, Jun 24, 2021 at 07:12:08PM +0530, Jagan Teki wrote: > Hi Tom, > > Please pull this PR for next. > > Summary: > - SPI NOT OF partitions (Marek Behún) > - Macronic SPI NAND (Jaime Liao) > - Macronix MX66UW2G345G SPI NOR (zhengxun) > > CI: > https://source.denx.de/u-boot/custodians/u-boot-spi/-/pipelines/7922 > > thanks, > Jagan. > > The following changes since commit 28afb716463919c261cffc6fddd594fac87557bb: > > Merge tag 'u-boot-rockchip-20210618' of > https://source.denx.de/u-boot/custodians/u-boot-rockchip into next > (2021-06-19 08:20:12 -0400) > > are available in the Git repository at: > > https://source.denx.de/u-boot/custodians/u-boot-spi master > > for you to fetch changes up to e41a2bc6b87397ef0aeda4132a8227d164cd592b: > > cmd: mtd: expand argument definition in command help (2021-06-24 > 11:55:13 +0530) > A good start to the SPI queue, applied to u-boot/next, thanks! -- Tom signature.asc Description: PGP signature
[PATCH] sunxi: h3: add console support for uart1-3
Add uart1-3 console support for the Allwinner H3 SOC
Signed-off-by: Manuel Dipolt
---
arch/arm/include/asm/arch-sunxi/gpio.h | 3 +++
arch/arm/mach-sunxi/board.c | 14 ++
include/configs/sunxi-common.h | 5 -
3 files changed, 21 insertions(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h
b/arch/arm/include/asm/arch-sunxi/gpio.h
index 40a3f845d0..50010071ae 100644
--- a/arch/arm/include/asm/arch-sunxi/gpio.h
+++ b/arch/arm/include/asm/arch-sunxi/gpio.h
@@ -148,6 +148,9 @@ enum sunxi_gpio_number {
#define SUN6I_GPA_SDC2 5
#define SUN6I_GPA_SDC3 4
#define SUN8I_H3_GPA_UART0 2
+#define SUN8I_H3_GPG_UART1 2
+#define SUN8I_H3_GPA_UART2 2
+#define SUN8I_H3_GPA_UART3 3
#define SUN4I_GPB_PWM 2
#define SUN4I_GPB_TWI0 2
diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c
index 8e9bb63d9d..31f780d1b5 100644
--- a/arch/arm/mach-sunxi/board.c
+++ b/arch/arm/mach-sunxi/board.c
@@ -127,10 +127,24 @@ static int gpio_init(void)
sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG_UART1);
sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG_UART1);
sunxi_gpio_set_pull(SUNXI_GPG(4), SUNXI_GPIO_PULL_UP);
+#elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUN8I_H3)
+ sunxi_gpio_set_cfgpin(SUNXI_GPG(7), SUN8I_H3_GPG_UART1);
+ sunxi_gpio_set_cfgpin(SUNXI_GPG(6), SUN8I_H3_GPG_UART1);
+ sunxi_gpio_set_pull(SUNXI_GPG(6), SUNXI_GPIO_PULL_UP);
#elif CONFIG_CONS_INDEX == 3 && defined(CONFIG_MACH_SUN8I)
+#if defined(CONFIG_MACH_SUN8I_H3)
+ sunxi_gpio_set_cfgpin(SUNXI_GPA(1), SUN8I_H3_GPA_UART2);
+ sunxi_gpio_set_cfgpin(SUNXI_GPA(0), SUN8I_H3_GPA_UART2);
+ sunxi_gpio_set_pull(SUNXI_GPA(0), SUNXI_GPIO_PULL_UP);
+#else
sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_GPB_UART2);
sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_GPB_UART2);
sunxi_gpio_set_pull(SUNXI_GPB(1), SUNXI_GPIO_PULL_UP);
+#endif
+#elif CONFIG_CONS_INDEX == 4 && defined(CONFIG_MACH_SUN8I_H3)
+ sunxi_gpio_set_cfgpin(SUNXI_GPA(14), SUN8I_H3_GPA_UART3);
+ sunxi_gpio_set_cfgpin(SUNXI_GPA(13), SUN8I_H3_GPA_UART3);
+ sunxi_gpio_set_pull(SUNXI_GPA(13), SUNXI_GPIO_PULL_UP);
#elif CONFIG_CONS_INDEX == 5 && defined(CONFIG_MACH_SUN8I)
sunxi_gpio_set_cfgpin(SUNXI_GPL(2), SUN8I_GPL_R_UART);
sunxi_gpio_set_cfgpin(SUNXI_GPL(3), SUN8I_GPL_R_UART);
diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h
index fceb812448..5b7c310fde 100644
--- a/include/configs/sunxi-common.h
+++ b/include/configs/sunxi-common.h
@@ -246,10 +246,13 @@ extern int soft_i2c_gpio_scl;
#else
#define OF_STDOUT_PATH "/soc@01c0/serial@01c28000:115200"
#endif
-#elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUN5I)
+#elif CONFIG_CONS_INDEX == 2 && \
+ (defined(CONFIG_MACH_SUN5I) || \defined(CONFIG_MACH_SUN8I_H3))
#define OF_STDOUT_PATH "/soc@01c0/serial@01c28400:115200"
#elif CONFIG_CONS_INDEX == 3 && defined(CONFIG_MACH_SUN8I)
#define OF_STDOUT_PATH "/soc@01c0/serial@01c28800:115200"
+#elif CONFIG_CONS_INDEX == 4 && defined(CONFIG_MACH_SUN8I_H3)
+#define OF_STDOUT_PATH "/soc@01c0/serial@01c28C00:115200"
#elif CONFIG_CONS_INDEX == 5 && defined(CONFIG_MACH_SUN8I)
#define OF_STDOUT_PATH "/soc@01c0/serial@01f02800:115200"
#else
--
2.20.1
[PATCH v2 14/14] board: freescale: ls2088ardb: Update I2C mux config
Updates the board configuration to enable use of the PCA9547 I2C mux. Signed-off-by: Stephen Carlson --- configs/ls2088ardb_qspi_SECURE_BOOT_defconfig | 1 + configs/ls2088ardb_qspi_defconfig | 1 + configs/ls2088ardb_tfa_SECURE_BOOT_defconfig | 1 + configs/ls2088ardb_tfa_defconfig | 1 + 4 files changed, 4 insertions(+) diff --git a/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig b/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig index 10c139c98e..fb77c8942e 100644 --- a/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig +++ b/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig @@ -67,3 +67,4 @@ CONFIG_USB_XHCI_DWC3=y CONFIG_RSA=y CONFIG_RSA_SOFTWARE_EXP=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_FSL_USE_PCA9547_MUX=y diff --git a/configs/ls2088ardb_qspi_defconfig b/configs/ls2088ardb_qspi_defconfig index 58fc6b2384..c09568b52a 100644 --- a/configs/ls2088ardb_qspi_defconfig +++ b/configs/ls2088ardb_qspi_defconfig @@ -72,3 +72,4 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_FSL_USE_PCA9547_MUX=y diff --git a/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig b/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig index eed26fa898..032d6125f2 100644 --- a/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig @@ -83,3 +83,4 @@ CONFIG_RSA=y CONFIG_SPL_RSA=y CONFIG_RSA_SOFTWARE_EXP=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_FSL_USE_PCA9547_MUX=y diff --git a/configs/ls2088ardb_tfa_defconfig b/configs/ls2088ardb_tfa_defconfig index 56cd02418c..522b381bb7 100644 --- a/configs/ls2088ardb_tfa_defconfig +++ b/configs/ls2088ardb_tfa_defconfig @@ -88,3 +88,4 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_FSL_USE_PCA9547_MUX=y -- 2.17.1
[PATCH v2 13/14] board: freescale: ls2088aqds: Update I2C mux config
Updates the board configuration to enable use of the PCA9547 I2C mux. Signed-off-by: Stephen Carlson --- configs/ls2088aqds_tfa_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/ls2088aqds_tfa_defconfig b/configs/ls2088aqds_tfa_defconfig index 5d14b55e6b..41a58359e6 100644 --- a/configs/ls2088aqds_tfa_defconfig +++ b/configs/ls2088aqds_tfa_defconfig @@ -90,3 +90,4 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_FSL_USE_PCA9547_MUX=y -- 2.17.1
[PATCH v2 12/14] board: freescale: lx2162aqds: Update I2C mux config
Updates the board configuration to enable use of the PCA9547 I2C mux. Signed-off-by: Stephen Carlson --- configs/lx2162aqds_tfa_SECURE_BOOT_defconfig | 1 + configs/lx2162aqds_tfa_defconfig | 1 + configs/lx2162aqds_tfa_verified_boot_defconfig | 1 + 3 files changed, 3 insertions(+) diff --git a/configs/lx2162aqds_tfa_SECURE_BOOT_defconfig b/configs/lx2162aqds_tfa_SECURE_BOOT_defconfig index fcc78c6fe5..8dc601ff2c 100644 --- a/configs/lx2162aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/lx2162aqds_tfa_SECURE_BOOT_defconfig @@ -89,3 +89,4 @@ CONFIG_RSA=y CONFIG_SPL_RSA=y CONFIG_RSA_SOFTWARE_EXP=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_FSL_USE_PCA9547_MUX=y diff --git a/configs/lx2162aqds_tfa_defconfig b/configs/lx2162aqds_tfa_defconfig index 42a3a3af44..d493bc1e7f 100644 --- a/configs/lx2162aqds_tfa_defconfig +++ b/configs/lx2162aqds_tfa_defconfig @@ -96,3 +96,4 @@ CONFIG_USB_XHCI_DWC3=y CONFIG_WDT=y CONFIG_WDT_SBSA=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_FSL_USE_PCA9547_MUX=y diff --git a/configs/lx2162aqds_tfa_verified_boot_defconfig b/configs/lx2162aqds_tfa_verified_boot_defconfig index bf0ac38ff2..8ff6f8113e 100644 --- a/configs/lx2162aqds_tfa_verified_boot_defconfig +++ b/configs/lx2162aqds_tfa_verified_boot_defconfig @@ -97,3 +97,4 @@ CONFIG_USB_XHCI_DWC3=y CONFIG_WDT=y CONFIG_WDT_SBSA=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_FSL_USE_PCA9547_MUX=y -- 2.17.1
[PATCH v2 11/14] board: freescale: ls2081ardb: Update I2C mux config
Updates the board configuration to enable use of the PCA9547 I2C mux. Signed-off-by: Stephen Carlson --- configs/ls2081ardb_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/ls2081ardb_defconfig b/configs/ls2081ardb_defconfig index ab1a9e22e0..d9134d6a01 100644 --- a/configs/ls2081ardb_defconfig +++ b/configs/ls2081ardb_defconfig @@ -65,3 +65,4 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_FSL_USE_PCA9547_MUX=y -- 2.17.1
[PATCH v2 10/14] board: freescale: t2080qds: Update I2C mux config
Updates the board configuration to enable use of the PCA9547 I2C mux.
Signed-off-by: Stephen Carlson
---
board/freescale/t208xqds/t208xqds.c | 26 +--
configs/T2080QDS_NAND_defconfig | 1 +
configs/T2080QDS_SDCARD_defconfig | 1 +
configs/T2080QDS_SECURE_BOOT_defconfig| 1 +
configs/T2080QDS_SPIFLASH_defconfig | 1 +
configs/T2080QDS_SRIO_PCIE_BOOT_defconfig | 1 +
configs/T2080QDS_defconfig| 1 +
7 files changed, 7 insertions(+), 25 deletions(-)
diff --git a/board/freescale/t208xqds/t208xqds.c
b/board/freescale/t208xqds/t208xqds.c
index fd3217f24d..715de106d6 100644
--- a/board/freescale/t208xqds/t208xqds.c
+++ b/board/freescale/t208xqds/t208xqds.c
@@ -22,6 +22,7 @@
#include
#include
#include
+#include "../common/i2c_mux.h"
#include "../common/qixis.h"
#include "../common/vsc3316_3308.h"
@@ -79,31 +80,6 @@ int checkboard(void)
return 0;
}
-int select_i2c_ch_pca9547(u8 ch, int bus_num)
-{
- int ret;
-
-#if CONFIG_IS_ENABLED(DM_I2C)
- struct udevice *dev;
-
- ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_PRI, 1, );
- if (ret) {
- printf("%s: Cannot find udev for a bus %d\n", __func__,
- bus_num);
- return ret;
- }
- ret = dm_i2c_write(dev, 0, , 1);
-#else
- ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, , 1);
-#endif
- if (ret) {
- puts("PCA: failed to select proper channel\n");
- return ret;
- }
-
- return 0;
-}
-
int i2c_multiplexer_select_vid_channel(u8 channel)
{
return select_i2c_ch_pca9547(channel, 0);
diff --git a/configs/T2080QDS_NAND_defconfig b/configs/T2080QDS_NAND_defconfig
index ffd23fab6b..62ce9eeecd 100644
--- a/configs/T2080QDS_NAND_defconfig
+++ b/configs/T2080QDS_NAND_defconfig
@@ -83,3 +83,4 @@ CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
CONFIG_ADDR_MAP=y
CONFIG_SYS_NUM_ADDR_MAP=64
+CONFIG_FSL_USE_PCA9547_MUX=y
diff --git a/configs/T2080QDS_SDCARD_defconfig
b/configs/T2080QDS_SDCARD_defconfig
index cb5d7ff233..c7987fa3bf 100644
--- a/configs/T2080QDS_SDCARD_defconfig
+++ b/configs/T2080QDS_SDCARD_defconfig
@@ -80,3 +80,4 @@ CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
CONFIG_ADDR_MAP=y
CONFIG_SYS_NUM_ADDR_MAP=64
+CONFIG_FSL_USE_PCA9547_MUX=y
diff --git a/configs/T2080QDS_SECURE_BOOT_defconfig
b/configs/T2080QDS_SECURE_BOOT_defconfig
index 4d33dc6a3a..f8f031f778 100644
--- a/configs/T2080QDS_SECURE_BOOT_defconfig
+++ b/configs/T2080QDS_SECURE_BOOT_defconfig
@@ -70,3 +70,4 @@ CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_RSA=y
CONFIG_SPL_RSA=y
CONFIG_RSA_SOFTWARE_EXP=y
+CONFIG_FSL_USE_PCA9547_MUX=y
diff --git a/configs/T2080QDS_SPIFLASH_defconfig
b/configs/T2080QDS_SPIFLASH_defconfig
index 1029a8ec34..cdcbf37edc 100644
--- a/configs/T2080QDS_SPIFLASH_defconfig
+++ b/configs/T2080QDS_SPIFLASH_defconfig
@@ -82,3 +82,4 @@ CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
CONFIG_ADDR_MAP=y
CONFIG_SYS_NUM_ADDR_MAP=64
+CONFIG_FSL_USE_PCA9547_MUX=y
diff --git a/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig
b/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig
index 0677053e21..9ab1cdfe8c 100644
--- a/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig
+++ b/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig
@@ -60,3 +60,4 @@ CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
CONFIG_ADDR_MAP=y
CONFIG_SYS_NUM_ADDR_MAP=64
+CONFIG_FSL_USE_PCA9547_MUX=y
diff --git a/configs/T2080QDS_defconfig b/configs/T2080QDS_defconfig
index c9d1fec300..1cbc947454 100644
--- a/configs/T2080QDS_defconfig
+++ b/configs/T2080QDS_defconfig
@@ -68,3 +68,4 @@ CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
CONFIG_ADDR_MAP=y
CONFIG_SYS_NUM_ADDR_MAP=64
+CONFIG_FSL_USE_PCA9547_MUX=y
--
2.17.1
[PATCH v2 09/14] board: freescale: lx2160a: Update I2C mux config
Updates the board configuration to enable use of the PCA9547 I2C mux.
Signed-off-by: Stephen Carlson
---
board/freescale/lx2160a/lx2160a.c| 31
configs/lx2160aqds_tfa_SECURE_BOOT_defconfig | 1 +
configs/lx2160aqds_tfa_defconfig | 1 +
configs/lx2160ardb_tfa_SECURE_BOOT_defconfig | 1 +
configs/lx2160ardb_tfa_defconfig | 1 +
configs/lx2160ardb_tfa_stmm_defconfig| 1 +
6 files changed, 11 insertions(+), 25 deletions(-)
diff --git a/board/freescale/lx2160a/lx2160a.c
b/board/freescale/lx2160a/lx2160a.c
index 47a7024f33..04a6296a36 100644
--- a/board/freescale/lx2160a/lx2160a.c
+++ b/board/freescale/lx2160a/lx2160a.c
@@ -29,6 +29,8 @@
#include
#include
#include
+#include "../common/i2c_mux.h"
+
#include "../common/qixis.h"
#include "../common/vid.h"
#include
@@ -79,27 +81,6 @@ U_BOOT_DRVINFO(nxp_serial1) = {
.plat = ,
};
-int select_i2c_ch_pca9547(u8 ch)
-{
- int ret;
-
-#if !CONFIG_IS_ENABLED(DM_I2C)
- ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, , 1);
-#else
- struct udevice *dev;
-
- ret = i2c_get_chip_for_busnum(0, I2C_MUX_PCA_ADDR_PRI, 1, );
- if (!ret)
- ret = dm_i2c_write(dev, 0, , 1);
-#endif
- if (ret) {
- puts("PCA: failed to select proper channel\n");
- return ret;
- }
-
- return 0;
-}
-
static void uart_get_clock(void)
{
serial0.clock = get_serial_clock();
@@ -115,10 +96,10 @@ int board_early_init_f(void)
uart_get_clock();
#ifdef CONFIG_EMC2305
- select_i2c_ch_pca9547(I2C_MUX_CH_EMC2305);
+ select_i2c_ch_pca9547(I2C_MUX_CH_EMC2305, 0);
emc2305_init(I2C_EMC2305_ADDR);
set_fan_speed(I2C_EMC2305_PWM, I2C_EMC2305_ADDR);
- select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
+ select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
#endif
fsl_lsch3_early_init_f();
@@ -275,7 +256,7 @@ int esdhc_status_fixup(void *blob, const char *compat)
#if defined(CONFIG_VID)
int i2c_multiplexer_select_vid_channel(u8 channel)
{
- return select_i2c_ch_pca9547(channel);
+ return select_i2c_ch_pca9547(channel, 0);
}
int init_func_vid(void)
@@ -611,7 +592,7 @@ int board_init(void)
gd->env_addr = (ulong)_environment[0];
#endif
- select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
+ select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
#if defined(CONFIG_FSL_MC_ENET) && defined(CONFIG_TARGET_LX2160ARDB)
/* invert AQR107 IRQ pins polarity */
diff --git a/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig
b/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig
index 54d88c88d5..75a6bdd19a 100644
--- a/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig
+++ b/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig
@@ -86,3 +86,4 @@ CONFIG_RSA=y
CONFIG_SPL_RSA=y
CONFIG_RSA_SOFTWARE_EXP=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_FSL_USE_PCA9547_MUX=y
diff --git a/configs/lx2160aqds_tfa_defconfig b/configs/lx2160aqds_tfa_defconfig
index d25d3e8b98..fafe42c559 100644
--- a/configs/lx2160aqds_tfa_defconfig
+++ b/configs/lx2160aqds_tfa_defconfig
@@ -92,3 +92,4 @@ CONFIG_USB_XHCI_DWC3=y
CONFIG_WDT=y
CONFIG_WDT_SBSA=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_FSL_USE_PCA9547_MUX=y
diff --git a/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig
b/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig
index 1d61807c11..501e9ae44a 100644
--- a/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig
+++ b/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig
@@ -77,3 +77,4 @@ CONFIG_RSA=y
CONFIG_SPL_RSA=y
CONFIG_RSA_SOFTWARE_EXP=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_FSL_USE_PCA9547_MUX=y
diff --git a/configs/lx2160ardb_tfa_defconfig b/configs/lx2160ardb_tfa_defconfig
index a160cfe21e..4b8e7edf94 100644
--- a/configs/lx2160ardb_tfa_defconfig
+++ b/configs/lx2160ardb_tfa_defconfig
@@ -87,3 +87,4 @@ CONFIG_USB_XHCI_DWC3=y
CONFIG_WDT=y
CONFIG_WDT_SBSA=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_FSL_USE_PCA9547_MUX=y
diff --git a/configs/lx2160ardb_tfa_stmm_defconfig
b/configs/lx2160ardb_tfa_stmm_defconfig
index 8b69a36dd9..06cfacab6d 100644
--- a/configs/lx2160ardb_tfa_stmm_defconfig
+++ b/configs/lx2160ardb_tfa_stmm_defconfig
@@ -86,3 +86,4 @@ CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_EFI_MM_COMM_TEE=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_FSL_USE_PCA9547_MUX=y
--
2.17.1
[PATCH v2 08/14] board: freescale: ls2080ardb: Update I2C mux config
Updates the board configuration to enable use of the PCA9547 I2C mux.
Signed-off-by: Stephen Carlson
---
board/freescale/ls2080ardb/ls2080ardb.c | 27 +++-
configs/ls2080ardb_SECURE_BOOT_defconfig | 1 +
configs/ls2080ardb_defconfig | 1 +
configs/ls2080ardb_nand_defconfig| 1 +
4 files changed, 6 insertions(+), 24 deletions(-)
diff --git a/board/freescale/ls2080ardb/ls2080ardb.c
b/board/freescale/ls2080ardb/ls2080ardb.c
index 3a026b0827..6504cf768f 100644
--- a/board/freescale/ls2080ardb/ls2080ardb.c
+++ b/board/freescale/ls2080ardb/ls2080ardb.c
@@ -25,6 +25,7 @@
#include
#include
#include
+#include "../common/i2c_mux.h"
#ifdef CONFIG_FSL_QIXIS
#include "../common/qixis.h"
@@ -205,31 +206,9 @@ unsigned long get_board_sys_clk(void)
return 1;
}
-int select_i2c_ch_pca9547(u8 ch)
-{
- int ret;
-
-#if !CONFIG_IS_ENABLED(DM_I2C)
- ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, , 1);
-#else
- struct udevice *dev;
-
- ret = i2c_get_chip_for_busnum(0, I2C_MUX_PCA_ADDR_PRI, 1, );
- if (!ret)
- ret = dm_i2c_write(dev, 0, , 1);
-#endif
-
- if (ret) {
- puts("PCA: failed to select proper channel\n");
- return ret;
- }
-
- return 0;
-}
-
int i2c_multiplexer_select_vid_channel(u8 channel)
{
- return select_i2c_ch_pca9547(channel);
+ return select_i2c_ch_pca9547(channel, 0);
}
int config_board_mux(int ctrl_type)
@@ -267,7 +246,7 @@ int board_init(void)
#ifdef CONFIG_ENV_IS_NOWHERE
gd->env_addr = (ulong)_environment[0];
#endif
- select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
+ select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
#ifdef CONFIG_FSL_QIXIS
QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET_EN);
diff --git a/configs/ls2080ardb_SECURE_BOOT_defconfig
b/configs/ls2080ardb_SECURE_BOOT_defconfig
index 1175aafadb..b3cc52ba03 100644
--- a/configs/ls2080ardb_SECURE_BOOT_defconfig
+++ b/configs/ls2080ardb_SECURE_BOOT_defconfig
@@ -66,3 +66,4 @@ CONFIG_USB_XHCI_DWC3=y
CONFIG_RSA=y
CONFIG_RSA_SOFTWARE_EXP=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_FSL_USE_PCA9547_MUX=y
diff --git a/configs/ls2080ardb_defconfig b/configs/ls2080ardb_defconfig
index 53abd06ec6..b3c5001c50 100644
--- a/configs/ls2080ardb_defconfig
+++ b/configs/ls2080ardb_defconfig
@@ -67,3 +67,4 @@ CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_FSL_USE_PCA9547_MUX=y
diff --git a/configs/ls2080ardb_nand_defconfig
b/configs/ls2080ardb_nand_defconfig
index 93032edc0c..63fadc5255 100644
--- a/configs/ls2080ardb_nand_defconfig
+++ b/configs/ls2080ardb_nand_defconfig
@@ -72,3 +72,4 @@ CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_FSL_USE_PCA9547_MUX=y
--
2.17.1
[PATCH v2 07/14] board: freescale: ls2080aqds: Update I2C mux config
Updates the board configuration to enable use of the PCA9547 I2C mux.
Signed-off-by: Stephen Carlson
---
board/freescale/ls2080aqds/ls2080aqds.c | 25 ++--
configs/ls2080aqds_SECURE_BOOT_defconfig | 1 +
configs/ls2080aqds_defconfig | 1 +
configs/ls2080aqds_nand_defconfig| 1 +
configs/ls2080aqds_qspi_defconfig| 1 +
configs/ls2080aqds_sdcard_defconfig | 1 +
6 files changed, 7 insertions(+), 23 deletions(-)
diff --git a/board/freescale/ls2080aqds/ls2080aqds.c
b/board/freescale/ls2080aqds/ls2080aqds.c
index 9572319234..c48b01f7d7 100644
--- a/board/freescale/ls2080aqds/ls2080aqds.c
+++ b/board/freescale/ls2080aqds/ls2080aqds.c
@@ -23,7 +23,7 @@
#include
#include
#include
-
+#include "../common/i2c_mux.h"
#include "../common/qixis.h"
#include "ls2080aqds_qixis.h"
@@ -161,27 +161,6 @@ unsigned long get_board_ddr_clk(void)
return ;
}
-int select_i2c_ch_pca9547(u8 ch)
-{
- int ret;
-#if CONFIG_IS_ENABLED(DM_I2C)
- struct udevice *dev;
-
- ret = i2c_get_chip_for_busnum(0, I2C_MUX_PCA_ADDR_PRI, 1, );
- if (!ret)
- ret = dm_i2c_write(dev, 0, , 1);
-
-#else
- ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, , 1);
-#endif
- if (ret) {
- puts("PCA: failed to select proper channel\n");
- return ret;
- }
-
- return 0;
-}
-
int config_board_mux(int ctrl_type)
{
u8 reg5;
@@ -235,7 +214,7 @@ int board_init(void)
#ifdef CONFIG_ENV_IS_NOWHERE
gd->env_addr = (ulong)_environment[0];
#endif
- select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
+ select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
#ifdef CONFIG_RTC_ENABLE_32KHZ_OUTPUT
#if CONFIG_IS_ENABLED(DM_I2C)
diff --git a/configs/ls2080aqds_SECURE_BOOT_defconfig
b/configs/ls2080aqds_SECURE_BOOT_defconfig
index bfa697c9ef..9e687f8066 100644
--- a/configs/ls2080aqds_SECURE_BOOT_defconfig
+++ b/configs/ls2080aqds_SECURE_BOOT_defconfig
@@ -68,3 +68,4 @@ CONFIG_USB_XHCI_DWC3=y
CONFIG_RSA=y
CONFIG_RSA_SOFTWARE_EXP=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_FSL_USE_PCA9547_MUX=y
diff --git a/configs/ls2080aqds_defconfig b/configs/ls2080aqds_defconfig
index 6f9cce5b25..a13e471a68 100644
--- a/configs/ls2080aqds_defconfig
+++ b/configs/ls2080aqds_defconfig
@@ -69,3 +69,4 @@ CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_FSL_USE_PCA9547_MUX=y
diff --git a/configs/ls2080aqds_nand_defconfig
b/configs/ls2080aqds_nand_defconfig
index cc0f2b16aa..808140f10b 100644
--- a/configs/ls2080aqds_nand_defconfig
+++ b/configs/ls2080aqds_nand_defconfig
@@ -76,3 +76,4 @@ CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_FSL_USE_PCA9547_MUX=y
diff --git a/configs/ls2080aqds_qspi_defconfig
b/configs/ls2080aqds_qspi_defconfig
index cbdf733456..51ab47a583 100644
--- a/configs/ls2080aqds_qspi_defconfig
+++ b/configs/ls2080aqds_qspi_defconfig
@@ -68,3 +68,4 @@ CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_FSL_USE_PCA9547_MUX=y
diff --git a/configs/ls2080aqds_sdcard_defconfig
b/configs/ls2080aqds_sdcard_defconfig
index 71174de458..79fa0e179f 100644
--- a/configs/ls2080aqds_sdcard_defconfig
+++ b/configs/ls2080aqds_sdcard_defconfig
@@ -75,3 +75,4 @@ CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_FSL_USE_PCA9547_MUX=y
--
2.17.1
[PATCH v2 06/14] board: freescale: ls1088a: Update I2C mux config
Updates the board configuration to enable use of the PCA9547 I2C mux.
Signed-off-by: Stephen Carlson
---
board/freescale/ls1088a/ls1088a.c | 32 ---
configs/ls1088aqds_defconfig | 1 +
configs/ls1088aqds_qspi_SECURE_BOOT_defconfig | 1 +
configs/ls1088aqds_qspi_defconfig | 1 +
configs/ls1088aqds_sdcard_ifc_defconfig | 1 +
configs/ls1088aqds_sdcard_qspi_defconfig | 1 +
configs/ls1088aqds_tfa_defconfig | 1 +
configs/ls1088ardb_qspi_SECURE_BOOT_defconfig | 1 +
configs/ls1088ardb_qspi_defconfig | 1 +
...1088ardb_sdcard_qspi_SECURE_BOOT_defconfig | 1 +
configs/ls1088ardb_sdcard_qspi_defconfig | 1 +
configs/ls1088ardb_tfa_SECURE_BOOT_defconfig | 1 +
configs/ls1088ardb_tfa_defconfig | 1 +
13 files changed, 18 insertions(+), 26 deletions(-)
diff --git a/board/freescale/ls1088a/ls1088a.c
b/board/freescale/ls1088a/ls1088a.c
index f5dc449d89..2f422634d5 100644
--- a/board/freescale/ls1088a/ls1088a.c
+++ b/board/freescale/ls1088a/ls1088a.c
@@ -26,6 +26,7 @@
#include
#include
#include
+#include "../common/i2c_mux.h"
#include "../common/qixis.h"
#include "ls1088a_qixis.h"
@@ -415,34 +416,13 @@ unsigned long get_board_ddr_clk(void)
return ;
}
-int select_i2c_ch_pca9547(u8 ch)
-{
- int ret;
-
-#if !CONFIG_IS_ENABLED(DM_I2C)
- ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, , 1);
-#else
- struct udevice *dev;
-
- ret = i2c_get_chip_for_busnum(0, I2C_MUX_PCA_ADDR_PRI, 1, );
- if (!ret)
- ret = dm_i2c_write(dev, 0, , 1);
-#endif
- if (ret) {
- puts("PCA: failed to select proper channel\n");
- return ret;
- }
-
- return 0;
-}
-
#if !defined(CONFIG_SPL_BUILD)
void board_retimer_init(void)
{
u8 reg;
/* Retimer is connected to I2C1_CH5 */
- select_i2c_ch_pca9547(I2C_MUX_CH5);
+ select_i2c_ch_pca9547(I2C_MUX_CH5, 0);
/* Access to Control/Shared register */
reg = 0x0;
@@ -532,7 +512,7 @@ void board_retimer_init(void)
#ifdef CONFIG_TARGET_LS1088AQDS
/* Retimer is connected to I2C1_CH5 */
- select_i2c_ch_pca9547(I2C_MUX_CH5);
+ select_i2c_ch_pca9547(I2C_MUX_CH5, 0);
/* Access to Control/Shared register */
reg = 0x0;
@@ -620,7 +600,7 @@ void board_retimer_init(void)
#endif
/*return the default channel*/
- select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
+ select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
}
#ifdef CONFIG_MISC_INIT_R
@@ -669,7 +649,7 @@ int misc_init_r(void)
int i2c_multiplexer_select_vid_channel(u8 channel)
{
- return select_i2c_ch_pca9547(channel);
+ return select_i2c_ch_pca9547(channel, 0);
}
#ifdef CONFIG_TARGET_LS1088AQDS
@@ -827,7 +807,7 @@ int board_init(void)
u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE;
#endif
- select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
+ select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
board_retimer_init();
#ifdef CONFIG_ENV_IS_NOWHERE
diff --git a/configs/ls1088aqds_defconfig b/configs/ls1088aqds_defconfig
index c0fb4c9872..d9b8c9a18d 100644
--- a/configs/ls1088aqds_defconfig
+++ b/configs/ls1088aqds_defconfig
@@ -74,3 +74,4 @@ CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_DWC3=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
+CONFIG_FSL_USE_PCA9547_MUX=y
diff --git a/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig
b/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig
index 57c91c1ad8..518a3ce6b9 100644
--- a/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig
+++ b/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig
@@ -75,3 +75,4 @@ CONFIG_USB_GADGET=y
CONFIG_RSA=y
CONFIG_RSA_SOFTWARE_EXP=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_FSL_USE_PCA9547_MUX=y
diff --git a/configs/ls1088aqds_qspi_defconfig
b/configs/ls1088aqds_qspi_defconfig
index 9abaead1c8..641efd982e 100644
--- a/configs/ls1088aqds_qspi_defconfig
+++ b/configs/ls1088aqds_qspi_defconfig
@@ -76,3 +76,4 @@ CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_DWC3=y
CONFIG_USB_GADGET=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_FSL_USE_PCA9547_MUX=y
diff --git a/configs/ls1088aqds_sdcard_ifc_defconfig
b/configs/ls1088aqds_sdcard_ifc_defconfig
index 44d4c13632..b70720c1d7 100644
--- a/configs/ls1088aqds_sdcard_ifc_defconfig
+++ b/configs/ls1088aqds_sdcard_ifc_defconfig
@@ -82,3 +82,4 @@ CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_DWC3=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
+CONFIG_FSL_USE_PCA9547_MUX=y
diff --git a/configs/ls1088aqds_sdcard_qspi_defconfig
b/configs/ls1088aqds_sdcard_qspi_defconfig
index dadea57078..764df3b698 100644
--- a/configs/ls1088aqds_sdcard_qspi_defconfig
+++ b/configs/ls1088aqds_sdcard_qspi_defconfig
@@ -85,3 +85,4 @@ CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_DWC3=y
CONFIG_USB_GADGET=y
+CONFIG_FSL_USE_PCA9547_MUX=y
diff --git a/configs/ls1088aqds_tfa_defconfig b/configs/ls1088aqds_tfa_defconfig
index ea308cafef..0b724c1350 100644
---
[PATCH v2 05/14] board: freescale: ls1046aqds: Update I2C mux config
Updates the board configuration to enable use of the PCA9547 I2C mux.
Signed-off-by: Stephen Carlson
---
board/freescale/ls1046aqds/ls1046aqds.c | 26 +---
configs/ls1046aqds_SECURE_BOOT_defconfig | 1 +
configs/ls1046aqds_defconfig | 1 +
configs/ls1046aqds_lpuart_defconfig | 1 +
configs/ls1046aqds_nand_defconfig| 1 +
configs/ls1046aqds_qspi_defconfig| 1 +
configs/ls1046aqds_sdcard_ifc_defconfig | 1 +
configs/ls1046aqds_sdcard_qspi_defconfig | 1 +
configs/ls1046aqds_tfa_SECURE_BOOT_defconfig | 1 +
configs/ls1046aqds_tfa_defconfig | 1 +
10 files changed, 10 insertions(+), 25 deletions(-)
diff --git a/board/freescale/ls1046aqds/ls1046aqds.c
b/board/freescale/ls1046aqds/ls1046aqds.c
index 20694426af..2b0786ac30 100644
--- a/board/freescale/ls1046aqds/ls1046aqds.c
+++ b/board/freescale/ls1046aqds/ls1046aqds.c
@@ -29,6 +29,7 @@
#include
#include
#include
+#include "../common/i2c_mux.h"
#include "../common/vid.h"
#include "../common/qixis.h"
@@ -276,31 +277,6 @@ u32 get_lpuart_clk(void)
}
#endif
-int select_i2c_ch_pca9547(u8 ch, int bus_num)
-{
- int ret;
-#if CONFIG_IS_ENABLED(DM_I2C)
- struct udevice *dev;
-
- ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_PRI,
- 1, );
- if (ret) {
- printf("%s: Cannot find udev for a bus %d\n", __func__,
- bus_num);
- return ret;
- }
- ret = dm_i2c_write(dev, 0, , 1);
-#else
- ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, , 1);
-#endif
- if (ret) {
- puts("PCA: failed to select proper channel\n");
- return ret;
- }
-
- return 0;
-}
-
int dram_init(void)
{
/*
diff --git a/configs/ls1046aqds_SECURE_BOOT_defconfig
b/configs/ls1046aqds_SECURE_BOOT_defconfig
index 7e7ae34226..5d58cc40a2 100644
--- a/configs/ls1046aqds_SECURE_BOOT_defconfig
+++ b/configs/ls1046aqds_SECURE_BOOT_defconfig
@@ -70,3 +70,4 @@ CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_RSA=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_FSL_USE_PCA9547_MUX=y
diff --git a/configs/ls1046aqds_defconfig b/configs/ls1046aqds_defconfig
index 8905d450da..205a129bce 100644
--- a/configs/ls1046aqds_defconfig
+++ b/configs/ls1046aqds_defconfig
@@ -72,3 +72,4 @@ CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_FSL_USE_PCA9547_MUX=y
diff --git a/configs/ls1046aqds_lpuart_defconfig
b/configs/ls1046aqds_lpuart_defconfig
index 6627ac2bb0..0001b55aee 100644
--- a/configs/ls1046aqds_lpuart_defconfig
+++ b/configs/ls1046aqds_lpuart_defconfig
@@ -74,3 +74,4 @@ CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_FSL_USE_PCA9547_MUX=y
diff --git a/configs/ls1046aqds_nand_defconfig
b/configs/ls1046aqds_nand_defconfig
index 9da564a788..d71e13df99 100644
--- a/configs/ls1046aqds_nand_defconfig
+++ b/configs/ls1046aqds_nand_defconfig
@@ -80,3 +80,4 @@ CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_FSL_USE_PCA9547_MUX=y
diff --git a/configs/ls1046aqds_qspi_defconfig
b/configs/ls1046aqds_qspi_defconfig
index 6cf46ff2c9..3eb204fd07 100644
--- a/configs/ls1046aqds_qspi_defconfig
+++ b/configs/ls1046aqds_qspi_defconfig
@@ -70,3 +70,4 @@ CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_FSL_USE_PCA9547_MUX=y
diff --git a/configs/ls1046aqds_sdcard_ifc_defconfig
b/configs/ls1046aqds_sdcard_ifc_defconfig
index 165c272c41..91fde75c9e 100644
--- a/configs/ls1046aqds_sdcard_ifc_defconfig
+++ b/configs/ls1046aqds_sdcard_ifc_defconfig
@@ -90,3 +90,4 @@ CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_FSL_USE_PCA9547_MUX=y
diff --git a/configs/ls1046aqds_sdcard_qspi_defconfig
b/configs/ls1046aqds_sdcard_qspi_defconfig
index 8e60a35858..e81096fc2b 100644
--- a/configs/ls1046aqds_sdcard_qspi_defconfig
+++ b/configs/ls1046aqds_sdcard_qspi_defconfig
@@ -85,3 +85,4 @@ CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_FSL_USE_PCA9547_MUX=y
diff --git a/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig
b/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig
index 7e57b53a1f..f78bbcf695 100644
--- a/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig
@@ -72,3 +72,4 @@ CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_RSA=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_FSL_USE_PCA9547_MUX=y
diff --git a/configs/ls1046aqds_tfa_defconfig b/configs/ls1046aqds_tfa_defconfig
index 9366bc1d32..919c407618 100644
--- a/configs/ls1046aqds_tfa_defconfig
+++ b/configs/ls1046aqds_tfa_defconfig
@@ -82,3 +82,4 @@ CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
[PATCH v2 04/14] board: freescale: ls1046afrwy: Update I2C mux config
Updates the board configuration to enable use of the PCA9547 I2C mux.
Signed-off-by: Stephen Carlson
---
board/freescale/ls1046afrwy/ls1046afrwy.c | 27 +--
configs/ls1046afrwy_tfa_SECURE_BOOT_defconfig | 1 +
configs/ls1046afrwy_tfa_defconfig | 1 +
3 files changed, 3 insertions(+), 26 deletions(-)
diff --git a/board/freescale/ls1046afrwy/ls1046afrwy.c
b/board/freescale/ls1046afrwy/ls1046afrwy.c
index f1709dcd1c..f1c08a13f7 100644
--- a/board/freescale/ls1046afrwy/ls1046afrwy.c
+++ b/board/freescale/ls1046afrwy/ls1046afrwy.c
@@ -22,6 +22,7 @@
#include
#include
#include
+#include "../common/i2c_mux.h"
#define LS1046A_PORSR1_REG 0x1EE
#define BOOT_SRC_SD0x2000
@@ -38,32 +39,6 @@
DECLARE_GLOBAL_DATA_PTR;
-int select_i2c_ch_pca9547(u8 ch, int bus_num)
-{
- int ret;
-
-#if CONFIG_IS_ENABLED(DM_I2C)
- struct udevice *dev;
-
- ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_PRI,
- 1, );
- if (ret) {
- printf("%s: Cannot find udev for a bus %d\n", __func__,
- bus_num);
- return ret;
- }
- ret = dm_i2c_write(dev, 0, , 1);
-#else
- ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, , 1);
-#endif
- if (ret) {
- puts("PCA: failed to select proper channel\n");
- return ret;
- }
-
- return 0;
-}
-
static inline void demux_select_usb2(void)
{
u32 val;
diff --git a/configs/ls1046afrwy_tfa_SECURE_BOOT_defconfig
b/configs/ls1046afrwy_tfa_SECURE_BOOT_defconfig
index 33308aa0e3..4fb54f161a 100644
--- a/configs/ls1046afrwy_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls1046afrwy_tfa_SECURE_BOOT_defconfig
@@ -61,3 +61,4 @@ CONFIG_USB_ETHER_ASIX88179=y
CONFIG_USB_ETHER_RTL8152=y
CONFIG_RSA=y
CONFIG_NXP_ESBC=y
+CONFIG_FSL_USE_PCA9547_MUX=y
diff --git a/configs/ls1046afrwy_tfa_defconfig
b/configs/ls1046afrwy_tfa_defconfig
index ea62d7fa7e..6861d22193 100644
--- a/configs/ls1046afrwy_tfa_defconfig
+++ b/configs/ls1046afrwy_tfa_defconfig
@@ -68,3 +68,4 @@ CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
CONFIG_USB_ETHER_ASIX88179=y
CONFIG_USB_ETHER_RTL8152=y
+CONFIG_FSL_USE_PCA9547_MUX=y
--
2.17.1
[PATCH v2 03/14] board: freescale: ls1043aqds: Update I2C mux config
Updates the board configuration to enable use of the PCA9547 I2C mux.
Signed-off-by: Stephen Carlson
---
board/freescale/ls1043aqds/ls1043aqds.c | 27 +---
configs/ls1043aqds_defconfig | 1 +
configs/ls1043aqds_lpuart_defconfig | 1 +
configs/ls1043aqds_nand_defconfig| 1 +
configs/ls1043aqds_nor_ddr3_defconfig| 1 +
configs/ls1043aqds_qspi_defconfig| 1 +
configs/ls1043aqds_sdcard_ifc_defconfig | 1 +
configs/ls1043aqds_sdcard_qspi_defconfig | 1 +
configs/ls1043aqds_tfa_SECURE_BOOT_defconfig | 1 +
configs/ls1043aqds_tfa_defconfig | 1 +
10 files changed, 10 insertions(+), 26 deletions(-)
diff --git a/board/freescale/ls1043aqds/ls1043aqds.c
b/board/freescale/ls1043aqds/ls1043aqds.c
index 5b131d1d67..76bbb6087a 100644
--- a/board/freescale/ls1043aqds/ls1043aqds.c
+++ b/board/freescale/ls1043aqds/ls1043aqds.c
@@ -28,6 +28,7 @@
#include
#include
#include
+#include "../common/i2c_mux.h"
#include "../common/qixis.h"
#include "ls1043aqds_qixis.h"
@@ -279,32 +280,6 @@ unsigned long get_board_ddr_clk(void)
return ;
}
-int select_i2c_ch_pca9547(u8 ch, int bus_num)
-{
- int ret;
-
-#if CONFIG_IS_ENABLED(DM_I2C)
- struct udevice *dev;
-
- ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_PRI,
- 1, );
- if (ret) {
- printf("%s: Cannot find udev for a bus %d\n", __func__,
- bus_num);
- return ret;
- }
- ret = dm_i2c_write(dev, 0, , 1);
-#else
- ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, , 1);
-#endif
- if (ret) {
- puts("PCA: failed to select proper channel\n");
- return ret;
- }
-
- return 0;
-}
-
int dram_init(void)
{
/*
diff --git a/configs/ls1043aqds_defconfig b/configs/ls1043aqds_defconfig
index 42fd350075..2f1da44884 100644
--- a/configs/ls1043aqds_defconfig
+++ b/configs/ls1043aqds_defconfig
@@ -69,3 +69,4 @@ CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_FSL_USE_PCA9547_MUX=y
diff --git a/configs/ls1043aqds_lpuart_defconfig
b/configs/ls1043aqds_lpuart_defconfig
index 1bafc2bb03..41b304cee8 100644
--- a/configs/ls1043aqds_lpuart_defconfig
+++ b/configs/ls1043aqds_lpuart_defconfig
@@ -71,3 +71,4 @@ CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_FSL_USE_PCA9547_MUX=y
diff --git a/configs/ls1043aqds_nand_defconfig
b/configs/ls1043aqds_nand_defconfig
index 8fb23acd88..25c5d93fcb 100644
--- a/configs/ls1043aqds_nand_defconfig
+++ b/configs/ls1043aqds_nand_defconfig
@@ -85,3 +85,4 @@ CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_FSL_USE_PCA9547_MUX=y
diff --git a/configs/ls1043aqds_nor_ddr3_defconfig
b/configs/ls1043aqds_nor_ddr3_defconfig
index f87c9a7cbf..a324291824 100644
--- a/configs/ls1043aqds_nor_ddr3_defconfig
+++ b/configs/ls1043aqds_nor_ddr3_defconfig
@@ -70,3 +70,4 @@ CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_FSL_USE_PCA9547_MUX=y
diff --git a/configs/ls1043aqds_qspi_defconfig
b/configs/ls1043aqds_qspi_defconfig
index 5de4e07457..3724d392bc 100644
--- a/configs/ls1043aqds_qspi_defconfig
+++ b/configs/ls1043aqds_qspi_defconfig
@@ -66,3 +66,4 @@ CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_FSL_USE_PCA9547_MUX=y
diff --git a/configs/ls1043aqds_sdcard_ifc_defconfig
b/configs/ls1043aqds_sdcard_ifc_defconfig
index 6e3318b1ed..eedabdbc6b 100644
--- a/configs/ls1043aqds_sdcard_ifc_defconfig
+++ b/configs/ls1043aqds_sdcard_ifc_defconfig
@@ -86,3 +86,4 @@ CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_FSL_USE_PCA9547_MUX=y
diff --git a/configs/ls1043aqds_sdcard_qspi_defconfig
b/configs/ls1043aqds_sdcard_qspi_defconfig
index cd20980c98..3058442cdd 100644
--- a/configs/ls1043aqds_sdcard_qspi_defconfig
+++ b/configs/ls1043aqds_sdcard_qspi_defconfig
@@ -80,3 +80,4 @@ CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_FSL_USE_PCA9547_MUX=y
diff --git a/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig
b/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig
index 4caabcadb8..ee92209d63 100644
--- a/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig
@@ -72,3 +72,4 @@ CONFIG_RSA=y
CONFIG_SPL_RSA=y
CONFIG_RSA_SOFTWARE_EXP=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_FSL_USE_PCA9547_MUX=y
diff --git a/configs/ls1043aqds_tfa_defconfig b/configs/ls1043aqds_tfa_defconfig
index fb28072638..c15f956b0a 100644
--- a/configs/ls1043aqds_tfa_defconfig
+++ b/configs/ls1043aqds_tfa_defconfig
@@ -79,3 +79,4 @@ CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
[PATCH v2 02/14] board: freescale: ls1021aqds: Update I2C mux config
Updates the board configuration to enable use of the PCA9547 I2C mux.
Signed-off-by: Stephen Carlson
---
board/freescale/ls1021aqds/dcu.c | 26 +---
board/freescale/ls1021aqds/ls1021aqds.c | 26 +---
configs/ls1021aqds_ddr4_nor_defconfig| 1 +
configs/ls1021aqds_ddr4_nor_lpuart_defconfig | 1 +
configs/ls1021aqds_nand_defconfig| 1 +
configs/ls1021aqds_nor_SECURE_BOOT_defconfig | 1 +
configs/ls1021aqds_nor_defconfig | 1 +
configs/ls1021aqds_nor_lpuart_defconfig | 1 +
configs/ls1021aqds_qspi_defconfig| 1 +
configs/ls1021aqds_sdcard_ifc_defconfig | 1 +
configs/ls1021aqds_sdcard_qspi_defconfig | 1 +
11 files changed, 11 insertions(+), 50 deletions(-)
diff --git a/board/freescale/ls1021aqds/dcu.c b/board/freescale/ls1021aqds/dcu.c
index 7532f7c0b2..b5fee06b5b 100644
--- a/board/freescale/ls1021aqds/dcu.c
+++ b/board/freescale/ls1021aqds/dcu.c
@@ -11,37 +11,13 @@
#include
#include
#include
+#include "../common/i2c_mux.h"
#include "div64.h"
#include "../common/diu_ch7301.h"
#include "ls1021aqds_qixis.h"
DECLARE_GLOBAL_DATA_PTR;
-static int select_i2c_ch_pca9547(u8 ch, int bus_num)
-{
- int ret;
-#if CONFIG_IS_ENABLED(DM_I2C)
- struct udevice *dev;
-
- ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_PRI,
- 1, );
- if (ret) {
- printf("%s: Cannot find udev for a bus %d\n", __func__,
- bus_num);
- return ret;
- }
- ret = dm_i2c_write(dev, 0, , 1);
-#else
- ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, , 1);
-#endif
- if (ret) {
- puts("PCA: failed to select proper channel\n");
- return ret;
- }
-
- return 0;
-}
-
unsigned int dcu_set_pixel_clock(unsigned int pixclock)
{
unsigned long long div;
diff --git a/board/freescale/ls1021aqds/ls1021aqds.c
b/board/freescale/ls1021aqds/ls1021aqds.c
index aa1f6025c1..fcbde2ceb7 100644
--- a/board/freescale/ls1021aqds/ls1021aqds.c
+++ b/board/freescale/ls1021aqds/ls1021aqds.c
@@ -25,6 +25,7 @@
#include
#include
#include
+#include "../common/i2c_mux.h"
#include "../common/sleep.h"
#include "../common/qixis.h"
#include "ls1021aqds_qixis.h"
@@ -141,31 +142,6 @@ unsigned long get_board_ddr_clk(void)
return ;
}
-int select_i2c_ch_pca9547(u8 ch, int bus_num)
-{
- int ret;
-#if CONFIG_IS_ENABLED(DM_I2C)
- struct udevice *dev;
-
- ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_PRI,
- 1, );
- if (ret) {
- printf("%s: Cannot find udev for a bus %d\n", __func__,
- bus_num);
- return ret;
- }
- ret = dm_i2c_write(dev, 0, , 1);
-#else
- ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, , 1);
-#endif
- if (ret) {
- puts("PCA: failed to select proper channel\n");
- return ret;
- }
-
- return 0;
-}
-
int dram_init(void)
{
/*
diff --git a/configs/ls1021aqds_ddr4_nor_defconfig
b/configs/ls1021aqds_ddr4_nor_defconfig
index a02a9fd955..04ad866731 100644
--- a/configs/ls1021aqds_ddr4_nor_defconfig
+++ b/configs/ls1021aqds_ddr4_nor_defconfig
@@ -69,3 +69,4 @@ CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
+CONFIG_FSL_USE_PCA9547_MUX=y
diff --git a/configs/ls1021aqds_ddr4_nor_lpuart_defconfig
b/configs/ls1021aqds_ddr4_nor_lpuart_defconfig
index d42e351754..700768294d 100644
--- a/configs/ls1021aqds_ddr4_nor_lpuart_defconfig
+++ b/configs/ls1021aqds_ddr4_nor_lpuart_defconfig
@@ -69,3 +69,4 @@ CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
+CONFIG_FSL_USE_PCA9547_MUX=y
diff --git a/configs/ls1021aqds_nand_defconfig
b/configs/ls1021aqds_nand_defconfig
index 93cb6bfbf2..d36d957995 100644
--- a/configs/ls1021aqds_nand_defconfig
+++ b/configs/ls1021aqds_nand_defconfig
@@ -84,3 +84,4 @@ CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
+CONFIG_FSL_USE_PCA9547_MUX=y
diff --git a/configs/ls1021aqds_nor_SECURE_BOOT_defconfig
b/configs/ls1021aqds_nor_SECURE_BOOT_defconfig
index d3b68b9f95..43e77c95bc 100644
--- a/configs/ls1021aqds_nor_SECURE_BOOT_defconfig
+++ b/configs/ls1021aqds_nor_SECURE_BOOT_defconfig
@@ -68,3 +68,4 @@ CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
CONFIG_RSA=y
CONFIG_SPL_RSA=y
+CONFIG_FSL_USE_PCA9547_MUX=y
diff --git a/configs/ls1021aqds_nor_defconfig b/configs/ls1021aqds_nor_defconfig
index a67d040443..26d2e5e567 100644
--- a/configs/ls1021aqds_nor_defconfig
+++ b/configs/ls1021aqds_nor_defconfig
@@ -70,3 +70,4 @@ CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
+CONFIG_FSL_USE_PCA9547_MUX=y
diff --git a/configs/ls1021aqds_nor_lpuart_defconfig
b/configs/ls1021aqds_nor_lpuart_defconfig
index
[PATCH v2 01/14] board: freescale: Refactor NXP common mux code
Refactors similar mux code from multiple NXP boards into a common location,
and allows it to be disabled in config.
New config: CONFIG_FSL_USE_PCA9547_MUX to enable PCA9547 mux functionality.
Signed-off-by: Stephen Carlson
---
board/freescale/common/Kconfig | 6 +++
board/freescale/common/Makefile | 11 ++
board/freescale/common/i2c_common.c | 34 +
board/freescale/common/i2c_common.h | 30 +++
board/freescale/common/i2c_mux.c| 40
board/freescale/common/i2c_mux.h| 15
board/freescale/common/vid.c| 58 ++---
7 files changed, 148 insertions(+), 46 deletions(-)
create mode 100644 board/freescale/common/i2c_common.c
create mode 100644 board/freescale/common/i2c_common.h
create mode 100644 board/freescale/common/i2c_mux.c
create mode 100644 board/freescale/common/i2c_mux.h
diff --git a/board/freescale/common/Kconfig b/board/freescale/common/Kconfig
index 17db755951..ab9c14ae88 100644
--- a/board/freescale/common/Kconfig
+++ b/board/freescale/common/Kconfig
@@ -21,6 +21,12 @@ config CMD_ESBC_VALIDATE
esbc_validate - validate signature using RSA verification
esbc_halt - put the core in spin loop (Secure Boot Only)
+config FSL_USE_PCA9547_MUX
+ bool "Enable PCA9547 I2C Mux on Freescale boards"
+ default n
+ help
+This option enables the PCA9547 I2C mux on Freescale boards.
+
config VID
depends on DM_I2C
bool "Enable Freescale VID"
diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile
index 114b7ba8f9..45aaa16ca4 100644
--- a/board/freescale/common/Makefile
+++ b/board/freescale/common/Makefile
@@ -15,6 +15,15 @@ ifdef MINIMAL
# necessary to create built-in.o
obj- := __dummy__.o
else
+# include i2c_common.o once if either VID or FSL_USE_PCA9547_MUX
+I2C_COMMON=
+ifdef CONFIG_VID
+I2C_COMMON=y
+endif
+ifdef CONFIG_FSL_USE_PCA9547_MUX
+I2C_COMMON=y
+endif
+
obj-$(CONFIG_FSL_CADMUS) += cadmus.o
obj-$(CONFIG_FSL_VIA) += cds_via.o
obj-$(CONFIG_FMAN_ENET)+= fman.o
@@ -22,6 +31,8 @@ obj-$(CONFIG_FSL_PIXIS) += pixis.o
ifndef CONFIG_SPL_BUILD
obj-$(CONFIG_FSL_NGPIXIS) += ngpixis.o
endif
+obj-$(I2C_COMMON) += i2c_common.o
+obj-$(CONFIG_FSL_USE_PCA9547_MUX) += i2c_mux.o
obj-$(CONFIG_VID) += vid.o
obj-$(CONFIG_FSL_QIXIS)+= qixis.o
obj-$(CONFIG_PQ_MDS_PIB) += pq-mds-pib.o
diff --git a/board/freescale/common/i2c_common.c
b/board/freescale/common/i2c_common.c
new file mode 100644
index 00..0f09ed7d34
--- /dev/null
+++ b/board/freescale/common/i2c_common.c
@@ -0,0 +1,34 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ * Copyright 2020-21 NXP
+ * Copyright 2021 Microsoft Corporation
+ */
+
+#include
+#include
+#include "i2c_common.h"
+
+#ifdef CONFIG_DM_I2C
+
+/* If DM is in use, retrieve the chip for the specified bus number */
+int fsl_i2c_get_device(int address, int bus, DEVICE_HANDLE_T *dev)
+{
+ int ret = i2c_get_chip_for_busnum(bus, address, 1, dev);
+
+ if (ret)
+ printf("I2C: Bus %d has no device with address 0x%02X\n",
+ bus, address);
+ return ret;
+}
+
+#else
+
+/* Handle is passed directly */
+int fsl_i2c_get_device(int address, int bus, DEVICE_HANDLE_T *dev)
+{
+ *dev = address;
+ return 0;
+}
+
+#endif
diff --git a/board/freescale/common/i2c_common.h
b/board/freescale/common/i2c_common.h
new file mode 100644
index 00..840ad66183
--- /dev/null
+++ b/board/freescale/common/i2c_common.h
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ * Copyright 2020-21 NXP
+ * Copyright 2021 Microsoft Corporation
+ */
+
+#ifndef __NXP_I2C_COMMON_H__
+#define __NXP_I2C_COMMON_H__
+
+/* Common functionality shared by the I2C drivers for VID and the mux. */
+#ifdef CONFIG_DM_I2C
+#define DEVICE_HANDLE_T struct udevice *
+
+#define I2C_READ(dev, register, data, length) \
+ dm_i2c_read(dev, register, data, length)
+#define I2C_WRITE(dev, register, data, length) \
+ dm_i2c_write(dev, register, data, length)
+#else
+#define DEVICE_HANDLE_T int
+
+#define I2C_READ(dev, register, data, length) \
+ i2c_read(dev, register, 1, data, length)
+#define I2C_WRITE(dev, register, data, length) \
+ i2c_write(dev, register, 1, data, length)
+#endif
+
+int fsl_i2c_get_device(int address, int bus, DEVICE_HANDLE_T *dev);
+
+#endif
diff --git a/board/freescale/common/i2c_mux.c b/board/freescale/common/i2c_mux.c
new file mode 100644
index 00..54f89e2576
--- /dev/null
+++ b/board/freescale/common/i2c_mux.c
@@ -0,0 +1,40 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ * Copyright 2020-21 NXP
+ * Copyright 2021 Microsoft Corporation
+ */
+
+#include
+#include
+#include
[PATCH v2 00/14] board: freescale: common: Refactor I2C mux driver
This patch set unifies code from multiple Freescale boards for the PCA9547 I2C mux into one location, and adds a Kconfig to disable the mux for new Freescale boards which do not include it. This patch set has been tested on the following boards: LX2160ARDB LX2160AQDS LX2162AQDS LS1046AFRWY LS1046ARDB LS2088ARDB LS1043ARDB LS1043AQDS LS1088ARDB LS1088AQDS Signed-off-by: Stephen Carlson Signed-off-by: Wasim Khan Tested-by: Zhao Zheng --- board/freescale/common/Kconfig| 6 ++ board/freescale/common/Makefile | 11 board/freescale/common/i2c_common.c | 32 ++ board/freescale/common/i2c_common.h | 28 + board/freescale/common/i2c_mux.c | 38 board/freescale/common/i2c_mux.h | 13 + board/freescale/common/vid.c | 58 --- board/freescale/ls1021aqds/dcu.c | 26 + board/freescale/ls1021aqds/ls1021aqds.c | 26 + board/freescale/ls1043aqds/ls1043aqds.c | 27 + board/freescale/ls1046afrwy/ls1046afrwy.c | 27 + board/freescale/ls1046aqds/ls1046aqds.c | 26 + board/freescale/ls1088a/ls1088a.c | 32 ++ board/freescale/ls2080aqds/ls2080aqds.c | 25 +--- board/freescale/ls2080ardb/ls2080ardb.c | 27 + board/freescale/lx2160a/lx2160a.c | 31 ++ board/freescale/t208xqds/t208xqds.c | 26 + configs/T2080QDS_NAND_defconfig | 1 + configs/T2080QDS_SDCARD_defconfig | 1 + configs/T2080QDS_SECURE_BOOT_defconfig| 1 + configs/T2080QDS_SPIFLASH_defconfig | 1 + configs/T2080QDS_SRIO_PCIE_BOOT_defconfig | 1 + configs/T2080QDS_defconfig| 1 + configs/ls1021aqds_ddr4_nor_defconfig | 1 + configs/ls1021aqds_ddr4_nor_lpuart_defconfig | 1 + configs/ls1021aqds_nand_defconfig | 1 + configs/ls1021aqds_nor_SECURE_BOOT_defconfig | 1 + configs/ls1021aqds_nor_defconfig | 1 + configs/ls1021aqds_nor_lpuart_defconfig | 1 + configs/ls1021aqds_qspi_defconfig | 1 + configs/ls1021aqds_sdcard_ifc_defconfig | 1 + configs/ls1021aqds_sdcard_qspi_defconfig | 1 + configs/ls1043aqds_defconfig | 1 + configs/ls1043aqds_lpuart_defconfig | 1 + configs/ls1043aqds_nand_defconfig | 1 + configs/ls1043aqds_nor_ddr3_defconfig | 1 + configs/ls1043aqds_qspi_defconfig | 1 + configs/ls1043aqds_sdcard_ifc_defconfig | 1 + configs/ls1043aqds_sdcard_qspi_defconfig | 1 + configs/ls1043aqds_tfa_SECURE_BOOT_defconfig | 1 + configs/ls1043aqds_tfa_defconfig | 1 + configs/ls1046afrwy_tfa_SECURE_BOOT_defconfig | 1 + configs/ls1046afrwy_tfa_defconfig | 1 + configs/ls1046aqds_SECURE_BOOT_defconfig | 1 + configs/ls1046aqds_defconfig | 1 + configs/ls1046aqds_lpuart_defconfig | 1 + configs/ls1046aqds_nand_defconfig | 1 + configs/ls1046aqds_qspi_defconfig | 1 + configs/ls1046aqds_sdcard_ifc_defconfig | 1 + configs/ls1046aqds_sdcard_qspi_defconfig | 1 + configs/ls1046aqds_tfa_SECURE_BOOT_defconfig | 1 + configs/ls1046aqds_tfa_defconfig | 1 + configs/ls1088aqds_defconfig | 1 + configs/ls1088aqds_qspi_SECURE_BOOT_defconfig | 1 + configs/ls1088aqds_qspi_defconfig | 1 + configs/ls1088aqds_sdcard_ifc_defconfig | 1 + configs/ls1088aqds_sdcard_qspi_defconfig | 1 + configs/ls1088aqds_tfa_defconfig | 1 + configs/ls1088ardb_qspi_SECURE_BOOT_defconfig | 1 + configs/ls1088ardb_qspi_defconfig | 1 + ...1088ardb_sdcard_qspi_SECURE_BOOT_defconfig | 1 + configs/ls1088ardb_sdcard_qspi_defconfig | 1 + configs/ls1088ardb_tfa_SECURE_BOOT_defconfig | 1 + configs/ls1088ardb_tfa_defconfig | 1 + configs/ls2080aqds_SECURE_BOOT_defconfig | 1 + configs/ls2080aqds_defconfig | 1 + configs/ls2080aqds_nand_defconfig | 1 + configs/ls2080aqds_qspi_defconfig | 1 + configs/ls2080aqds_sdcard_defconfig | 1 + configs/ls2080ardb_SECURE_BOOT_defconfig | 1 + configs/ls2080ardb_defconfig | 1 + configs/ls2080ardb_nand_defconfig | 1 + configs/ls2081ardb_defconfig | 1 + configs/ls2088aqds_tfa_defconfig | 1 + configs/ls2088ardb_qspi_SECURE_BOOT_defconfig | 1 + configs/ls2088ardb_qspi_defconfig | 1 + configs/ls2088ardb_tfa_SECURE_BOOT_defconfig | 1 + configs/ls2088ardb_tfa_defconfig | 1 + configs/lx2160aqds_tfa_SECURE_BOOT_defconfig | 1 + configs/lx2160aqds_tfa_defconfig | 1 + configs/lx2160ardb_tfa_SECURE_BOOT_defconfig | 1 + configs/lx2160ardb_tfa_defconfig
Re: U-Boot DSA driver for microchip KSZ9477 suggestions needed
On Wed, Jun 23, 2021 at 7:05 PM Vladimir Oltean wrote: > > On Wed, Jun 23, 2021 at 05:28:42PM -0700, Tim Harvey wrote: > > On Wed, Jun 23, 2021 at 3:37 AM Vladimir Oltean > > wrote: > > > > > > On Tue, Jun 22, 2021 at 09:38:52AM -0700, Tim Harvey wrote: > > > > On Mon, Jun 21, 2021 at 4:49 PM Vladimir Oltean > > > > wrote: > > > > > > > > > > On Mon, Jun 21, 2021 at 04:10:51PM -0700, Tim Harvey wrote: > > > > > > Greetings, > > > > > > > > > > > > I've written a U-Boot phy driver for a Microchip KSZ9477 ethernet > > > > > > switch that I submitted some time ago as an RFC [1] which simply > > > > > > enables the ports in the dt and puts them in forwarding mode with > > > > > > link > > > > > > detect. However I think this would be much better suited as a DSA > > > > > > driver now that UCLASS_DSA exists. > > > > > > > > > > Define 'link detect'. I don't know how the switch-as-PHY drivers work. > > > > > I suppose the DSA master is made to connect to a PHY device which is > > > > > implemented by the switch driver, but whose port's link status is > > > > > being > > > > > reported? > > > > > > > > Yes, each downward port's link status can be detected. Each port has > > > > standard GbE PHY registers which can be indirectly read. > > > > > > What do you mean by 'each port'? > > > With the switch-as-PHY driver, how many UCLASS_ETH devices are being > > > registered? One for the FEC and one for each front-facing switch port > > > (same as DSA would)? Only one, and that for the FEC? If the latter, how > > > does U-Boot know which of the front-facing switch ports to use as the > > > link status reporting for the FEC device? > > > > With my ksz9477 'switch-as-phy' driver > > (https://www.mail-archive.com/u-boot@lists.denx.de/msg389714.html) > > there is only 1 UCLASS_ETH device registered, just fec. The driver > > provides a UCLASS_ETH_PHY and its probe parses the dt to find the > > ports then registers an mdio bus for the indirect register access and > > registers a phy driver that matches the id's of the switch port. > > > > This only worked with another patch > > (https://www.mail-archive.com/u-boot@lists.denx.de/msg389712.html) to > > the UCLASS_ETH_PHY driver that allowed the phy driver to bind the the > > fec mac. Therefore this acts as a single phy on the MAC and when > > phy_config is called it sets up auto-negotiation on all the non-cpu > > ports and when phy_startup is called it performs link detect on all > > the non-cpu ports (if any port is linked its considered a link). The > > phy_config configured all the ports in forwarding mode. > > > > This was modeled after the drivers/net/phy/mv88e61xx.c (switch-as-phy) > > driver and the only difference between that is that it attempted to > > use driver-model and get its config from dt. The big downside of this > > method is that the switch is configured in forwarding mode so you end > > up with a bridge loop while active in U-Boot if you have more than one > > port connected to your network. > > > > I think if you look over that relatively simple driver it will make > > sense how the ksz switch works in case I'm explaining it wrong or with > > the wrong terminology. > > Ah, ok, so it enables switching. Basically my misunderstanding was, if > the strategy is simply 'if any of the switch internal PHYs has link then > the phy-device exposed to the host port has link', how can this work and > not confuse the user badly. Say a cable is plugged, but not into the > port you are trying to ping over. agreed, this is confusing but this is how the mv88e61xx.c switch-as-phy driver works which I modeled my switch-as-phy driver from. >From a user perspective with this kind of switch-as-phy approach network traffic works through any port with a link due to the switch being in forwarding mode and there is no need to know what port is active but personally if you are using DSA in Linux such that each port has a network interface then I do like the model of doing the same in U-Boot. > > But you've answered my question, the packets are replicated by the > switch to all user ports if the situation demands it (FDB entry not > present for that MAC DA), and once the destination is learned, packets > will flow only towards the desired port. > > I should have known better. > > Actually there's a third type of switch driver now in U-Boot, which is > drivers/net/vsc9953.c which uses some overly bloated struct ethsw_command_func > operations and a dedicated "ethsw" U-Boot command to manage/call them. > This seems to be completely missing the point of U-Boot networking (what > user in their right mind needs to manage VLANs, the FDB, link > aggregation groups, ingress filtering from U-Boot?). With this "ethsw" > framework, it's a bit of a mix between the switch-as-PHY model and the > DM DSA model. > > The switch is managed through a plain U-Boot command, so there's no DM > concept to speak of. The host port uses a fixed-link (same as DM DSA) > but is otherwise completely
Re: [PATCH V2] ARM: rmobile: beacon: Set CONFIG_RZ_G2 on Beacon boards
On 6/24/21 7:52 PM, Adam Ford wrote: The board detection is incorrectly stating it's an rcar3 variant instead of an RZ/G2 variant on all the r8a774*1_beacon boards. Set the flag to correctly display as RZ/G2[M/N/H] Applied, thanks.
[PATCH V2] ARM: rmobile: beacon: Set CONFIG_RZ_G2 on Beacon boards
The board detection is incorrectly stating it's an rcar3 variant instead of an RZ/G2 variant on all the r8a774*1_beacon boards. Set the flag to correctly display as RZ/G2[M/N/H] Signed-off-by: Adam Ford --- V2: Move the RZ_G2 option to Kconfig from defconfig diff --git a/arch/arm/mach-rmobile/Kconfig.64 b/arch/arm/mach-rmobile/Kconfig.64 index 3f7ec05379..c621f8a544 100644 --- a/arch/arm/mach-rmobile/Kconfig.64 +++ b/arch/arm/mach-rmobile/Kconfig.64 @@ -69,16 +69,19 @@ choice config TARGET_BEACON_RZG2H bool "Beacon EmbeddedWorks RZ/G2H Dev Kit" select R8A774E1 + select RZ_G2 select PINCTRL_PFC_R8A774E1 config TARGET_BEACON_RZG2M bool "Beacon EmbeddedWorks RZ/G2M Dev Kit" select R8A774A1 + select RZ_G2 select PINCTRL_PFC_R8A774A1 config TARGET_BEACON_RZG2N bool "Beacon EmbeddedWorks RZ/G2N Dev Kit" select R8A774B1 + select RZ_G2 select PINCTRL_PFC_R8A774B1 config TARGET_CONDOR -- 2.25.1
[PATCH] arm: mach-k3: am642_init: Add missing ddr guard
The `struct udevice *` reference is needed for either of the
K3_LOAD_SYSFW, K3_AM64_DDRSS config guards. Adding the missing
K3_AM64_DDRSS guard.
Signed-off-by: Gowtham Tammana
---
arch/arm/mach-k3/am642_init.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-k3/am642_init.c b/arch/arm/mach-k3/am642_init.c
index 87e762bc65..51f6e81def 100644
--- a/arch/arm/mach-k3/am642_init.c
+++ b/arch/arm/mach-k3/am642_init.c
@@ -141,7 +141,7 @@ void do_dt_magic(void)
void board_init_f(ulong dummy)
{
-#if defined(CONFIG_K3_LOAD_SYSFW)
+#if defined(CONFIG_K3_LOAD_SYSFW) || defined(CONFIG_K3_AM64_DDRSS)
struct udevice *dev;
int ret;
#endif
--
2.32.0
Re: [PATCH v2 0/5] arm: dts: Add PMIC node for J7200
On 6/24/21 8:16 AM, Tom Rini wrote: On Wed, Jun 23, 2021 at 04:14:49PM -0500, Gowtham Tammana wrote: The J7200 EVM has PMIC LP876441 for supporting CPU AVS. This patchset adds dt nodes, compatible string, and configs to enable the corresponding driver. v2: - rebased the changes are reordered patches 3/4 v1: - https://lore.kernel.org/u-boot/20200915113633.25449-1-g-tamm...@ti.com/ Can you confirm there are no new dts warnings with this series? Thanks! Yes, I dont see any new dts warnings with this series. Thanks, Gowtham
Re: [PATCH] ARM: rmobile: beacon: Set CONFIG_RZ_G2 on Beacon boards
On 6/24/21 4:12 PM, Adam Ford wrote: The board detection is incorrectly stating it's an rcar3 variant instead of an RZ/G2 variant on all the r8a774*1_beacon boards. Set the flag to correctly display as RZ/G2[M/N/H] Just select/imply the defaults in arch/arm/mach-rmobile/Kconfig.64 like e.g. the HIHOPE board does there. That would be much better.
[PATCH] ARM: rmobile: beacon: Set CONFIG_RZ_G2 on Beacon boards
The board detection is incorrectly stating it's an rcar3 variant instead of an RZ/G2 variant on all the r8a774*1_beacon boards. Set the flag to correctly display as RZ/G2[M/N/H] Signed-off-by: Adam Ford diff --git a/configs/r8a774a1_beacon_defconfig b/configs/r8a774a1_beacon_defconfig index 4a87a9a31f..40004a2b57 100644 --- a/configs/r8a774a1_beacon_defconfig +++ b/configs/r8a774a1_beacon_defconfig @@ -5,6 +5,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_ENV_OFFSET=0x0 CONFIG_DM_GPIO=y CONFIG_RCAR_GEN3=y +CONFIG_RZ_G2=y CONFIG_TARGET_BEACON_RZG2M=y # CONFIG_SPL is not set CONFIG_DEFAULT_DEVICE_TREE="r8a774a1-beacon-rzg2m-kit" diff --git a/configs/r8a774b1_beacon_defconfig b/configs/r8a774b1_beacon_defconfig index 2c31222525..46a94568a8 100644 --- a/configs/r8a774b1_beacon_defconfig +++ b/configs/r8a774b1_beacon_defconfig @@ -5,6 +5,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_ENV_OFFSET=0x0 CONFIG_DM_GPIO=y CONFIG_RCAR_GEN3=y +CONFIG_RZ_G2=y CONFIG_TARGET_BEACON_RZG2N=y # CONFIG_SPL is not set CONFIG_DEFAULT_DEVICE_TREE="r8a774b1-beacon-rzg2n-kit" diff --git a/configs/r8a774e1_beacon_defconfig b/configs/r8a774e1_beacon_defconfig index a814d6ad63..6cea7b9cc5 100644 --- a/configs/r8a774e1_beacon_defconfig +++ b/configs/r8a774e1_beacon_defconfig @@ -5,6 +5,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_ENV_OFFSET=0x0 CONFIG_DM_GPIO=y CONFIG_RCAR_GEN3=y +CONFIG_RZ_G2=y CONFIG_TARGET_BEACON_RZG2H=y # CONFIG_SPL is not set CONFIG_DEFAULT_DEVICE_TREE="r8a774e1-beacon-rzg2h-kit" -- 2.25.1
Pull request: u-boot-spi/master for next
Hi Tom, Please pull this PR for next. Summary: - SPI NOT OF partitions (Marek Behún) - Macronic SPI NAND (Jaime Liao) - Macronix MX66UW2G345G SPI NOR (zhengxun) CI: https://source.denx.de/u-boot/custodians/u-boot-spi/-/pipelines/7922 thanks, Jagan. The following changes since commit 28afb716463919c261cffc6fddd594fac87557bb: Merge tag 'u-boot-rockchip-20210618' of https://source.denx.de/u-boot/custodians/u-boot-rockchip into next (2021-06-19 08:20:12 -0400) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-spi master for you to fetch changes up to e41a2bc6b87397ef0aeda4132a8227d164cd592b: cmd: mtd: expand argument definition in command help (2021-06-24 11:55:13 +0530) Jaime Liao (1): mtd: spinand: macronix: Add support for serial NAND flash Marek Behún (10): dm: core: add non-translating version of ofnode_get_addr_size_index() dm: core: add ofnode_get_path() mtd: add support for parsing partitions defined in OF mtd: spi-nor: allow registering multiple MTDs when DM is enabled mtd: spi-nor: fill-in mtd->dev member mtd: remove mtd_probe() function mtd: probe SPI NOR devices in mtd_probe_devices() cmd: mtd: print device OF path in listing mtd: compare also with OF path and device name in get_mtd_device_nm() cmd: mtd: expand argument definition in command help zhengxun (1): mtd: spi-nor-ids: Add Macronix MX66UW2G345G cmd/mtd.c | 9 ++- drivers/core/ofnode.c | 44 +- drivers/mtd/mtd-uclass.c| 15 - drivers/mtd/mtd_uboot.c | 129 drivers/mtd/mtdcore.c | 35 +++ drivers/mtd/mtdpart.c | 63 drivers/mtd/nand/spi/macronix.c | 46 ++ drivers/mtd/spi/sf_internal.h | 4 +- drivers/mtd/spi/sf_mtd.c| 19 +- drivers/mtd/spi/sf_probe.c | 6 +- drivers/mtd/spi/spi-nor-core.c | 1 + drivers/mtd/spi/spi-nor-ids.c | 1 + drivers/mtd/spi/spi-nor-tiny.c | 1 + include/dm/ofnode.h | 27 + include/linux/mtd/mtd.h | 10 include/mtd.h | 1 - test/dm/ofnode.c| 26 17 files changed, 362 insertions(+), 75 deletions(-)
Re: [PATCH v2 0/5] arm: dts: Add PMIC node for J7200
On Wed, Jun 23, 2021 at 04:14:49PM -0500, Gowtham Tammana wrote: > The J7200 EVM has PMIC LP876441 for supporting CPU AVS. This patchset > adds dt nodes, compatible string, and configs to enable the > corresponding driver. > > v2: > - rebased the changes are reordered patches 3/4 > > v1: > - https://lore.kernel.org/u-boot/20200915113633.25449-1-g-tamm...@ti.com/ Can you confirm there are no new dts warnings with this series? Thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH] disk/part_dos.c: Fix a variable typo in write_mbr_partitions()
On Mon, Jun 07, 2021 at 11:21:15AM +0200, Christian Melki wrote:
> This function is passed *dev not *dev_desc, so pass the right name to
> part_init().
>
> Fixes: f14c5ee5ab8b ("disk: part_dos: update partition table entries after
> write")
> Signed-off-by: Christian Melki
With the above reworded commit message, applied to u-boot/master, thanks!
--
Tom
signature.asc
Description: PGP signature
Re: [PATCH] autoboot: fix typos of CONFIG_AUTOBOOT_USE_MENUKEY
On Mon, Jun 21, 2021 at 10:39:19PM -0400, Da Xue wrote: > replace typo CONFIG_USE_AUTOBOOT_MENUKEY with CONFIG_AUTOBOOT_USE_MENUKEY > > Signed-off-by: Da Xue Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH] Makefile: Adjust indention of GENENV quiet output
On Sun, Jun 20, 2021 at 10:29:13PM +0200, Jan Kiszka wrote: > From: Jan Kiszka > > The column width for a command name is 8. > > Signed-off-by: Jan Kiszka Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH 3/4] socfpga64: Do not define CONFIG_SYS_MEM_RESERVE_SECURE to 0
On Thu, Jun 03, 2021 at 09:39:01AM -0400, Tom Rini wrote: > Based on the comment in socfpga_soc64_common.h, the intention is for > CONFIG_SYS_MEM_RESERVE_SECURE to be unused. However, in the code we do: > ... > > and that will evaluate to true. This leads to unwanted code being > compiled. Further, as CONFIG_SYS_MEM_RESERVE_SECURE has not been > migrated to Kconfig, this leads to a mismatch in the size of gd > depending on if we have or have not also had also > included yet. > > Remove the define as it's not needed. > > Cc: Siew Chin Lim > Cc: Chee Hong Ang > Cc: Dalon Westergreen > Signed-off-by: Tom Rini Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH V3] MAINTAINER, git-mailrc: Update the mmc maintainer
On Tue, Jun 15, 2021 at 07:16:36AM +0900, Jaehoon Chung wrote: > Update to me as co-maintainer with Peng. > Additionally, update the mmc alias in git-mailrc. > > Signed-off-by: Jaehoon Chung > Reviewed-by: Bin Meng > Acked-by: Peng Fan Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH v1 1/1] test: Include /sbin to the PATH when creating file system
On Thu, Jun 10, 2021 at 06:08:42PM +0300, Andy Shevchenko wrote: > On some distributions the mkfs is under /sbin and /sbin is not set > for mere users. Include /sbin to the PATH when creating file system, > so that users won't get a scary traceback from Python. > > Signed-off-by: Andy Shevchenko Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH 4/4] global_data: Ensure we have when symbols are not in Kconfig yet
On Thu, Jun 03, 2021 at 09:39:02AM -0400, Tom Rini wrote: > All symbols that are defined in Kconfig will always be defined (or not) > prior to preprocessing due to the -include directive while building. > However, symbols which are not yet migrated will only be defined (or > not) once the board config.h is included, via . While the end > goal must be to migrate all symbols, today we have cases where the size > of gd will get mismatched within the build, based on include order. > Mitigate this by making sure that any that uses > symbols not in Kconfig does start with . Remove this when not > needed. > > Cc: Alexey Brodkin > Cc: Eugeniy Paltsev > Cc: Huan Wang > Cc: Angelo Dureghello > Cc: Rick Chen > Signed-off-by: Tom Rini Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH 2/4] Revert "powerpc: fix regression in arch_initr_trap()"
On Thu, Jun 03, 2021 at 09:39:00AM -0400, Tom Rini wrote:
> With the changes in commit 588efcdd72fc ("powerpc: Don't use relative
> include for config.h in global_data.h") fixing the root of the problem,
> we no longer need this re-inclusion.
>
> This reverts commit f6c0d365d3e8ee8e4fd3ebe2ed957c2bca9d3328.
>
> Cc: Matt Merhar
> Signed-off-by: Tom Rini
Applied to u-boot/master, thanks!
--
Tom
signature.asc
Description: PGP signature
Re: [PATCH 1/1] malloc: add SPDX license identifiers
On Sat, May 29, 2021 at 01:18:00PM +0200, Heinrich Schuchardt wrote: > The original code is in the public domain. Licenses/README states that the > general license for U-Boot is GPL 2.0+. So we can mark the malloc code as > GPL 2.0+ too. > > Signed-off-by: Heinrich Schuchardt Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH 1/4] powerpc: Don't use relative include for config.h in global_data.h
On Thu, Jun 03, 2021 at 09:38:59AM -0400, Tom Rini wrote: > As there is an arch/powerpc/include/asm/config.h file using "" to get > config.h here can lead to using that rather than include/config.h. This > in turn can lead to a mismatch in the size of gd. > > Cc: Matt Merhar > Signed-off-by: Tom Rini > Tested-by: Matt Merhar Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: Please pull u-boot-x86
On Wed, Jun 23, 2021 at 07:01:14PM +0800, Bin Meng wrote: > Hi Tom, > > This PR includes the following changes for v2021.07 release: > > - x86: Discard .note.gnu.property sections > - nvme: Skip block device creation for inactive namespaces > - nvme: Convert NVMe doc to reST, and various minor fixes > > Azure results: PASS > https://dev.azure.com/bmeng/GitHub/_build/results?buildId=381=results > > The following changes since commit 1ce892cb1ce970d8ee6ffcecc22351c84e67fca4: > > azure: Use msys2 20210604 installer for Windows build (2021-06-22 > 09:06:03 -0400) > > are available in the Git repository at: > > https://source.denx.de/u-boot/custodians/u-boot-x86 > > for you to fetch changes up to f68d5a66cd53a238d64d79cdd330b4dce17c7197: > > MAINTAINERS: Add an entry for NVMe (2021-06-23 17:21:14 +0800) > Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [Resend PULL] Please pull mmc-2021-6-22
On Wed, Jun 23, 2021 at 02:40:59AM +, Peng Fan (OSS) wrote: > Hi Tom, > > Resend with new mail address that subscribed to u-boot list. > > Please pull u-boot-mmc. > Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH -next] ARM: dts: k3-j7200-common-proc-board-u-boot.dtsi: Fix dtc warnings
On Mon, Jun 14, 2021 at 02:12:39PM +0530, Vignesh Raghavendra wrote: > Fix following dtc warning by explicitly setting up #size-cells > and #address-cells when overriding node in -u-boot.dtsi > > arch/arm/dts/k3-j7200-common-proc-board.dtb: Warning (reg_format): > /bus@10/bus@2838/mcu-navss/ringacc@2b80:reg: property has > invalid length (80 bytes) (#address-cells == 2, #size-cells == 1) > > Signed-off-by: Vignesh Raghavendra Applied to u-boot/next, thanks! -- Tom signature.asc Description: PGP signature
Re: [U-Boot] [PATCH v3 13/20] spl: nand: sunxi: use PIO instead of DMA
Hi Miquel, On Wed, Feb 28, 2018 at 08:51:55PM +0100, Miquel Raynal wrote: > SPL support was first written to support only the earlier generations of > Allwinner SoCs, and was only really enabled on the A13 / GR8. However, > those old SoCs had a DMA engine that has been replaced since the A31 by > another DMA controller that is no longer compatible. > > Since the code directly uses that DMA controller, it cannot operate > properly on the later SoCs, while the NAND controller has not changed. > > There's two paths forward, the first one would have been to add support > for that DMA controller too, the second to just remove the DMA usage > entirely and rely on PIO. > > The later has been chosen because CPU overload at this stage is not an > issue and it makes the driver more generic, and easier to understand. > > Signed-off-by: Miquel Raynal > Acked-by: Boris Brezillon I'm a bit late to the party, but this bricks the CHIP Pro too. While U-Boot proper seems to be flashed properly (re-reading it from the NAND after flashing brings up the same CRC than the original image), the SPL will only read 0s. The transfer does complete though, so maybe it's just the copy from the SRAM to the main memory that doesn't work? The offset looks correct though, so I'm not sure. Maxime
[PATCH] serial: Add additional depencies for PL010 and PL011 drivers
Both of these drivers are implemented with and without DM that's why more
symbols should be handled.
The most problematic one is enabling DEBUG_UART_PL011 based on
PL01X_SERIAL(DM based) because debug console has type selection based on
it.
enum pl01x_type type = CONFIG_IS_ENABLED(DEBUG_UART_PL011) ?
TYPE_PL011 : TYPE_PL010;
Without it pl01x_generic_setbrg() is configuring different registers.
Fixes: 4cc24aeaf420 ("serial: Add missing Kconfig dependencies for debug
consoles")
Signed-off-by: Michal Simek
---
drivers/serial/Kconfig | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index 6d1c4530ddf5..9f82467c4e3c 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -332,7 +332,7 @@ config DEBUG_UART_APBUART
config DEBUG_UART_PL010
bool "pl010"
- depends on PL01X_SERIAL
+ depends on PL01X_SERIAL || PL010_SERIAL
help
Select this to enable a debug UART using the pl01x driver with the
PL010 UART type. You will need to provide parameters to make this
@@ -341,7 +341,7 @@ config DEBUG_UART_PL010
config DEBUG_UART_PL011
bool "pl011"
- depends on PL011_SERIAL
+ depends on PL01X_SERIAL || PL011_SERIAL
help
Select this to enable a debug UART using the pl01x driver with the
PL011 UART type. You will need to provide parameters to make this
--
2.32.0
Re: [PATCH u-boot-dm + u-boot-spi v4 00/10] Support SPI NORs and OF partitions in `mtd list`
On Wed, May 26, 2021 at 5:39 PM Marek Behún wrote: > > Hello, > > this is v4 of patchset that adds support for U-Boot to parse MTD > partitions from device-tree, and also improves support for SPI NOR > access via the `mtd` command. > > Small rebase was needed since last version. > > Finally passing CI since LTO is now merged and can optimize away the > code increase. CI at https://github.com/u-boot/u-boot/pull/55 > > Changes since v3: > - rebased against current master (removed first patch, not needed > anymore) > - check for CONFIG_OF_CONTROL in addition to CONFIG_DM, since we are > also using ofnode_* functions > - match mtd's name in a separate function to make code more readable. > Also add non-DM version of this name matching function, since #if > macro must be used (otherwise CI will fail for configurations with > disabled DM) > - addressed Simon's comments about using IS_ENABLED instead of #ifdefs > - added Miquel's Reviewed-by and Patrice's Tested-by to the whole series > > Changes since v2: > - addressed Pali's comments in patch that adds partition parsing (4/7 in > this version): no check for whether the `compatible` property is > present in a partition node and added comment explaining mask flags) > - added 4 more patches: > 1) adding ofnode_get_path() function > 2) printing OF path in `mtd list` > 3) in `mtd read ...`, can now also be DM's device name > or OF path > 4) the fact from 3) is added to `mtd help` > > Changes since v1: > - added tests of ofnode_get_addr_size_index() and > ofnode_get_addr_size_index_notrans() as requested by Simon > - the last patch now probes SPI NORs in both versions of > mtd_probe_devices(), that is when MTDPARTS is enabled or disabled > > Marek > > Cc: Jagan Teki > Cc: Priyanka Jain > Cc: Simon Glass > Cc: Heiko Schocher > Cc: Jagan Teki > Cc: Patrick Delaunay > Cc: Patrice CHOTARD > Cc: Miquel Raynal > > Marek Behún (10): > dm: core: add non-translating version of ofnode_get_addr_size_index() > dm: core: add ofnode_get_path() > mtd: add support for parsing partitions defined in OF > mtd: spi-nor: allow registering multiple MTDs when DM is enabled > mtd: spi-nor: fill-in mtd->dev member > mtd: remove mtd_probe() function > mtd: probe SPI NOR devices in mtd_probe_devices() > cmd: mtd: print device OF path in listing > mtd: compare also with OF path and device name in get_mtd_device_nm() > cmd: mtd: expand argument definition in command help Applied to u-boot-spi/master
Re: [PATCH v9 00/28] mtd: spi-nor-core: add xSPI Octal DTR support
On 23/06/21 05:32PM, Jagan Teki wrote:
> On Wed, May 5, 2021 at 3:11 PM Pratyush Yadav wrote:
> >
> > Hi,
> >
> > This series adds support for octal DTR flashes in the SPI NOR framework,
> > and then adds hooks for the Cypress S28HS512T and Micron MT35XU512ABA
> > flashes.
> >
> > The Cadence QSPI controller driver is also updated to run in Octal DTR
> > mode.
> >
> > Tested on TI J721E for MT35XU512ABA and J7200 for S28HS512T. Also tested
> > on MT25QU512A for regressions.
> >
> > Changes in v9:
> > - Fix a typo in patch 26 commit message.
> >
> > - Add Sean's Reviewed-by in patch 3.
> >
> > - Drop the 2-byte check from spi_mem_dtr_supports_op(). Instead, perform
> > a even-byte length check on all 4 phases. Only do this when the
> > buswidth of the phase is 8.
> >
> > - Make template ops in spi_nor_check_readop() and spi_nor_check_pp()
> > have 2-byte data phase so they don't get rejected when 8D-8D-8D
> > protocol is being used.
> >
> > Changes in v8:
> > - Rebase on latest master, fixing merge conflicts.
> >
> > - Fix a regression related to address width that was discovered on
> > Linux.
> >
> > - Port spi_mem_dtr_supports_op() from Linux and use it in Cadence qspi
> > driver.
> >
> > - Do not set non-volatile Uniform Sector mode bit on S28HS512T. Instead
> > use Takahiro's non-uniform erase patch to enable non-uniform erases.
> >
> > - Make sure spi_nor_write_reg() does not set data direction to out when
> > there is no data to write, like in write enable.
> >
> > - Set buswidths to 0 before calling spi_nor_setup_op(), like how it is
> > done in Linux.
> >
> > Changes in v7:
> > - Port back changes requested on the Linux series.
> >
> > - Introduce the flag SPI_NOR_OCTAL_DTR_PP to indicate 8D page program
> > support since it can't be detected from SFDP.
> >
> > - Re-order Profile 1.0 related defines by DWORD order.
> >
> > - Drop local variables addr_width and dummy in spi_nor_read_sr()
> > spi_nor_read_fsr().
> >
> > - Do not make having command opcode extension as a reserved field fatal.
> >
> > - Update doc comment for spi_nor_parse_profile1() and
> > spi_nor_cypress_octal_dtr_enable() to add missing fields.
> >
> > - Move rdsr parameter parsing to where opcode is parsed because it is
> > from the same DWORD.
> >
> > - Convert a comment in Profile 1.0 parsing from multi-line to one line.
> >
> > - Rename 'table' to 'dwords' in xSPI Profile 1.0 parsing.
> >
> > - Update spi_nor_check_readop() and spi_nor_check_pp() to use
> > spi_nor_setup_op() so the buswidths are properly set up for DTR ops.
> >
> > - Do not set Uniform Sector bit on the Cypress S28HS512T flash if it is
> > already set. It will avoid wearing out the non-volatile bit.
> >
> > - Enable DQS for Micron MT35XU512ABA. No reason not to.
> >
> > - Avoid enabling 4-byte addressing mode for all DTR ops instead of just
> > Octal DTR ops. This is based on the assumption that DTR ops can only
> > use 4-byte addressing.
> >
> > - Make spi_nor_set_fixups() static.
> >
> > - Add flag SPI_NOR_OCTAL_DTR_PP to both Cypress S28HS512T and Micron
> > MT35XU512ABA.
> >
> > - Use values set up by spi-{rx,tx}-bus-width via device tree to
> > determine if the controller supports the op or not. Gives more
> > flexibility to choose protocol per-board.
> >
> > - Use tiny SPI NOR on x530 because of size constraints.
> >
> > Changes in v6:
> > - Use "# CONFIG_SPI_FLASH_SMART_HWCAPS is not set" instead of
> > "CONFIG_SPI_FLASH_SMART_HWCAPS=n" in x530_defconfig.
> >
> > Changes in v5:
> > - Fix build breaking when CONFIG_SPL_SPI_FLASH_TINY is enabled because
> > spi-nor-tiny did not have spi_nor_remove().
> >
> > - The build was breaking in x530 because of SPL size too big. Fix it by
> > the below changes.
> >
> > - Re-introduce old hwcaps selection logic and put the new one behind a
> > config. This lets boards with size restrictions use the old logic
> > which takes up less space. The code was getting hard to manage with
> > the old code behind ifdefs. So, re-structure the old hwcaps selection
> > logic and move it into one function: spi_nor_adjust_hwcaps(). This
> > way, the common code just calls spi_nor_adjust_hwcaps(), but the old
> > or new hwcaps selection is used based on the config option selected.
> >
> > - Put spi_nor_soft_reset() behind the config option SPI_NOR_SOFT_RESET.
> >
> > - Rename the config option used for soft resetting on boot to
> > SPI_NOR_SOFT_RESET_ON_BOOT to make its intention clearer.
> >
> > - Put the fixup hooks of MT35XU512ABA and S28HS512T flashes behind
> > config options to reduce code size on platforms that don't need them.
> >
> > - Introduce spi_nor_set_fixups(). Earlier, the fixup members of each
> > flash was specified in spi-nor-ids.c. This meant they had to be
> > declared as extern in sf_internal.h. But since spi-nor-tiny.c also
> > uses it, and it doesn't have those fixups, they had to be put behind
> > in an ifdef. The ".fixups = " assignment
Re: [PATCH] serial: zynq: Add support for serial parameters
Hi Michal, On 2021/06/23 20:15, Michal Simek wrote: Hi Kunihiko, On 6/23/21 12:52 PM, Kunihiko Hayashi wrote: Hi Michal, On 2021/06/22 21:44, Michal Simek wrote: Hi, On 6/22/21 6:24 AM, Kunihiko Hayashi wrote: This adds serial parameters that include stop bit mode, parity mode, and character length. Mark parity and space parity modes are not supported. Signed-off-by: Kunihiko Hayashi --- drivers/serial/serial_zynq.c | 64 1 file changed, 64 insertions(+) [snip] I am just curious how you have tested it because only hook is in test/dm/serial.c and I can't see no way how to change this setting via u-boot command line. I was misunderstanding. Surely there is no way to execute .setconfig function, and neither command line nor devicetree actually affects the serial mode. The mode just inherits that of the previous firmware. That being said I see that this change adds 184 bytes which is quite a lot especially for SPL on zynqmp. That's why would like to know how this feature should be used. If make sense for example to limit it to only full U-Boot. I see. I didn't think enough about the size limit of SPL. Anyway, I withdraw this patch. Up2you. Maybe someone will add any support for calling these functions. For me it is fine to add it to full U-Boot but not to SPL for DM testing. Ok, I expect to such support. I'll modify it to add the function when CONFIG_SPL_BUILD isn't defined if there is no concern, and resend it. Thank you, --- Best Regards Kunihiko Hayashi
[PATCH 2/3] net: xilinx: axi_mrmac: Add MRMAC driver
Add support for xilinx multirate(MRMAC) ethernet driver.
This driver uses multichannel DMA(MCDMA) for data transfers of MRMAC.
Added support for 4 ports of MRMAC for speeds 10G and 25G.
MCDMA supports upto 16 channels but in this driver we have setup only
one channel which is enough.
Tested 10G and 25G on all 4 ports.
Signed-off-by: Ashok Reddy Soma
---
MAINTAINERS| 1 +
drivers/net/Kconfig| 9 +
drivers/net/Makefile | 1 +
drivers/net/xilinx_axi_mrmac.c | 525 +
drivers/net/xilinx_axi_mrmac.h | 192
5 files changed, 728 insertions(+)
create mode 100644 drivers/net/xilinx_axi_mrmac.c
create mode 100644 drivers/net/xilinx_axi_mrmac.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 2accd1fb83..cc05e13968 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -543,6 +543,7 @@ M: Michal Simek
S: Maintained
T: git https://source.denx.de/u-boot/custodians/u-boot-microblaze.git
F: arch/arm/mach-versal/
+F: drivers/net/xilinx_axi_mrmac.*
F: drivers/watchdog/xilinx_wwdt.c
N: (?
+ * Michal Simek
+ *
+ * Copyright (C) 2021 Xilinx, Inc. All rights reserved.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include "xilinx_axi_mrmac.h"
+
+static u8 rxframe[RX_DESC * PKTSIZE_ALIGN] __attribute((aligned(DMAALIGN)));
+static u8 txminframe[MIN_PKT_SIZE] __attribute((aligned(DMAALIGN)));
+
+/* Static buffer descriptors:
+ * MRMAC needs atleast two buffer descriptors for the TX/RX to happen.
+ * Otherwise MRMAC will drop the packets. So, have two tx and rx bd's here.
+ */
+static struct mcdma_bd tx_bd[TX_DESC] __attribute((aligned(DMAALIGN)));
+static struct mcdma_bd rx_bd[RX_DESC] __attribute((aligned(DMAALIGN)));
+
+static void axi_mrmac_dma_write(struct mcdma_bd *bd, u32 *desc)
+{
+ if (IS_ENABLED(CONFIG_PHYS_64BIT))
+ writeq((unsigned long)bd, desc);
+ else
+ writel((uintptr_t)bd, desc);
+}
+
+static int axi_mrmac_ethernet_init(struct axi_mrmac_priv *priv)
+{
+ struct mrmac_regs *regs = priv->iobase;
+ u32 val, reg;
+ u32 ret;
+
+ /* Perform all the RESET's required */
+ val = readl(>reset);
+ val |= MRMAC_RX_SERDES_RST_MASK | MRMAC_TX_SERDES_RST_MASK |
+ MRMAC_RX_RST_MASK | MRMAC_TX_RST_MASK;
+ writel(val, >reset);
+
+ mdelay(MRMAC_RESET_DELAY);
+
+ /* Configure Mode register */
+ reg = readl(>mode);
+
+ debug("Configuring MRMAC speed to %d\n", priv->mrmac_rate);
+
+ if (priv->mrmac_rate == SPEED_25000) {
+ reg &= ~MRMAC_CTL_RATE_CFG_MASK;
+ reg |= MRMAC_CTL_DATA_RATE_25G;
+ reg |= (MRMAC_CTL_AXIS_CFG_25G_IND << MRMAC_CTL_AXIS_CFG_SHIFT);
+ reg |= (MRMAC_CTL_SERDES_WIDTH_25G <<
+ MRMAC_CTL_SERDES_WIDTH_SHIFT);
+ } else {
+ reg &= ~MRMAC_CTL_RATE_CFG_MASK;
+ reg |= MRMAC_CTL_DATA_RATE_10G;
+ reg |= (MRMAC_CTL_AXIS_CFG_10G_IND << MRMAC_CTL_AXIS_CFG_SHIFT);
+ reg |= (MRMAC_CTL_SERDES_WIDTH_10G <<
+ MRMAC_CTL_SERDES_WIDTH_SHIFT);
+ }
+
+ /* For tick reg */
+ reg |= MRMAC_CTL_PM_TICK_MASK;
+ writel(reg, >mode);
+
+ val = readl(>reset);
+ val &= ~(MRMAC_RX_SERDES_RST_MASK | MRMAC_TX_SERDES_RST_MASK |
+MRMAC_RX_RST_MASK | MRMAC_TX_RST_MASK);
+ writel(val, >reset);
+
+ mdelay(MRMAC_RESET_DELAY);
+
+ /* Setup MRMAC hardware options */
+ writel(readl(>rx_config) | MRMAC_RX_DEL_FCS_MASK,
+ >rx_config);
+ writel(readl(>tx_config) | MRMAC_TX_INS_FCS_MASK,
+ >tx_config);
+ writel(readl(>tx_config) | MRMAC_TX_EN_MASK, >tx_config);
+ writel(readl(>rx_config) | MRMAC_RX_EN_MASK, >rx_config);
+
+ /* Check for block lock bit to be set. This ensures that
+* MRMAC ethernet IP is functioning normally.
+*/
+ writel(MRMAC_STS_ALL_MASK, (phys_addr_t)priv->iobase +
+ MRMAC_TX_STS_OFFSET);
+ writel(MRMAC_STS_ALL_MASK, (phys_addr_t)priv->iobase +
+ MRMAC_RX_STS_OFFSET);
+ writel(MRMAC_STS_ALL_MASK, (phys_addr_t)priv->iobase +
+ MRMAC_STATRX_BLKLCK_OFFSET);
+
+ ret = wait_for_bit_le32((u32 *)((phys_addr_t)priv->iobase +
+ MRMAC_STATRX_BLKLCK_OFFSET),
+ MRMAC_RX_BLKLCK_MASK, true,
+ MRMAC_BLKLCK_TIMEOUT, true);
+ if (ret) {
+ printf("%s: MRMAC block lock not complete!\n", __func__);
+ return 1;
+ }
+
+ writel(MRMAC_TICK_TRIGGER, >tick_reg);
+
+ return 0;
+}
+
+/* Reset DMA engine */
+static int axi_mcdma_init(struct axi_mrmac_priv *priv)
+{
+ u32 ret;
+
+ /* Reset the engine so the hardware starts
[PATCH 0/3] Add MRMAC driver support
This patch set adds Xilinx AXI Multirate MAC(MRMAC) driver support. This MRMAC is a high performance, low latency, adaptable Ethernet integrated hard IP. This can be configured up to four ports with MAC rates from 10GE to 100GE. Supported Configuration Combinations: 1 × 100GE 2 × 50GE 1 × 40GE 4 × 25GE 4 × 10GE Currently added support and tested below configurations in the driver: 4 × 25GE 4 × 10GE Ashok Reddy Soma (3): net: ethtool: Add ethernet speed macros for higher speeds net: xilinx: axi_mrmac: Add MRMAC driver xilinx: versal: Enable Xilinx AXI MRMAC MAINTAINERS | 1 + configs/xilinx_versal_virt_defconfig | 1 + drivers/net/Kconfig | 9 + drivers/net/Makefile | 1 + drivers/net/xilinx_axi_mrmac.c | 525 +++ drivers/net/xilinx_axi_mrmac.h | 192 ++ include/linux/ethtool.h | 8 + 7 files changed, 737 insertions(+) create mode 100644 drivers/net/xilinx_axi_mrmac.c create mode 100644 drivers/net/xilinx_axi_mrmac.h -- 2.17.1
[PATCH 3/3] xilinx: versal: Enable Xilinx AXI MRMAC
Enable Xilinx AXI MRMAC for Versal platforms. Signed-off-by: Ashok Reddy Soma --- configs/xilinx_versal_virt_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/xilinx_versal_virt_defconfig b/configs/xilinx_versal_virt_defconfig index f4e9a80728..75feae318e 100644 --- a/configs/xilinx_versal_virt_defconfig +++ b/configs/xilinx_versal_virt_defconfig @@ -89,6 +89,7 @@ CONFIG_PHY_VITESSE=y CONFIG_PHY_FIXED=y CONFIG_PHY_GIGE=y CONFIG_XILINX_AXIEMAC=y +CONFIG_XILINX_AXIMRMAC=y CONFIG_ZYNQ_GEM=y CONFIG_ARM_DCC=y CONFIG_PL01X_SERIAL=y -- 2.17.1
[PATCH 1/3] net: ethtool: Add ethernet speed macros for higher speeds
Add speed macro's for higher ethernet speeds to be used in u-boot
networking drivers. Added Macros for speeds 14G, 20G, 25G, 40G, 50G,
56G, 100G and 200G inline with linux.
Signed-off-by: Ashok Reddy Soma
---
include/linux/ethtool.h | 8
1 file changed, 8 insertions(+)
diff --git a/include/linux/ethtool.h b/include/linux/ethtool.h
index f6dbdb096d..aa7d2fd58f 100644
--- a/include/linux/ethtool.h
+++ b/include/linux/ethtool.h
@@ -620,6 +620,14 @@ enum ethtool_sfeatures_retval_bits {
#define SPEED_1000 1000
#define SPEED_2500 2500
#define SPEED_11
+#define SPEED_1400014000
+#define SPEED_22
+#define SPEED_2500025000
+#define SPEED_44
+#define SPEED_55
+#define SPEED_5600056000
+#define SPEED_10 10
+#define SPEED_20 20
/* Duplex, half or full. */
#define DUPLEX_HALF0x00
--
2.17.1
[PATCH 2/2] net: xilinx: axi_emac: Add support for 10G/25G AXI ethernet
Add support for 10G/25G (XXV) high speed ethernet. This Makes use of
the exiting AXI DMA, similar to 1G.
Signed-off-by: Alessandro Temil
Signed-off-by: Ashok Reddy Soma
---
drivers/net/xilinx_axi_emac.c | 162 +-
1 file changed, 118 insertions(+), 44 deletions(-)
diff --git a/drivers/net/xilinx_axi_emac.c b/drivers/net/xilinx_axi_emac.c
index cfc6082475..2ec76d0f52 100644
--- a/drivers/net/xilinx_axi_emac.c
+++ b/drivers/net/xilinx_axi_emac.c
@@ -1,5 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
+ * Copyright (C) 2021 Waymo LLC
* Copyright (C) 2011 Michal Simek
* Copyright (C) 2011 PetaLogix
* Copyright (C) 2010 Xilinx, Inc. All rights reserved.
@@ -73,9 +74,22 @@ DECLARE_GLOBAL_DATA_PTR;
#define XAXIDMA_BD_CTRL_TXSOF_MASK 0x0800 /* First tx packet */
#define XAXIDMA_BD_CTRL_TXEOF_MASK 0x0400 /* Last tx packet */
-#define DMAALIGN 128
+/* Bitmasks for XXV Ethernet MAC */
+#define XXV_TC_TX_MASK 0x0001
+#define XXV_TC_FCS_MASK0x0002
+#define XXV_RCW1_RX_MASK 0x0001
+#define XXV_RCW1_FCS_MASK 0x0002
+
+#define DMAALIGN 128
+#define XXV_MIN_PKT_SIZE 60
static u8 rxframe[PKTSIZE_ALIGN] __attribute((aligned(DMAALIGN)));
+static u8 txminframe[XXV_MIN_PKT_SIZE] __attribute((aligned(DMAALIGN)));
+
+enum emac_variant {
+ EMAC_1G = 0,
+ EMAC_10G_25G = 1,
+};
/* Reflect dma offsets */
struct axidma_reg {
@@ -95,6 +109,7 @@ struct axidma_plat {
int phyaddr;
u8 eth_hasnobuf;
int phy_of_handle;
+ enum emac_variant mactype;
};
/* Private driver structures */
@@ -108,6 +123,7 @@ struct axidma_priv {
struct mii_dev *bus;
u8 eth_hasnobuf;
int phy_of_handle;
+ enum emac_variant mactype;
};
/* BD descriptors */
@@ -154,6 +170,14 @@ struct axi_regs {
u32 uaw1; /* 0x704: Unicast address word 1 */
};
+struct xxv_axi_regs {
+ u32 gt_reset; /* 0x0 */
+ u32 reserved[2];
+ u32 tc; /* 0xC: Tx Configuration */
+ u32 reserved2;
+ u32 rcw1; /* 0x14: Rx Configuration Word 1 */
+};
+
/* Use MII register 1 (MII status register) to detect PHY */
#define PHY_DETECT_REG 1
@@ -385,6 +409,18 @@ static void axiemac_stop(struct udevice *dev)
debug("axiemac: Halted\n");
}
+static int xxv_axi_ethernet_init(struct axidma_priv *priv)
+{
+ struct xxv_axi_regs *regs = (struct xxv_axi_regs *)priv->iobase;
+
+ writel(readl(>rcw1) | XXV_RCW1_FCS_MASK, >rcw1);
+ writel(readl(>tc) | XXV_TC_FCS_MASK, >tc);
+ writel(readl(>tc) | XXV_TC_TX_MASK, >tc);
+ writel(readl(>rcw1) | XXV_RCW1_RX_MASK, >rcw1);
+
+ return 0;
+}
+
static int axi_ethernet_init(struct axidma_priv *priv)
{
struct axi_regs *regs = priv->iobase;
@@ -440,6 +476,9 @@ static int axiemac_write_hwaddr(struct udevice *dev)
struct axidma_priv *priv = dev_get_priv(dev);
struct axi_regs *regs = priv->iobase;
+ if (priv->mactype != EMAC_1G)
+ return 0;
+
/* Set the MAC address */
int val = ((pdata->enetaddr[3] << 24) | (pdata->enetaddr[2] << 16) |
(pdata->enetaddr[1] << 8) | (pdata->enetaddr[0]));
@@ -477,7 +516,6 @@ static void axi_dma_init(struct axidma_priv *priv)
static int axiemac_start(struct udevice *dev)
{
struct axidma_priv *priv = dev_get_priv(dev);
- struct axi_regs *regs = priv->iobase;
u32 temp;
debug("axiemac: Init started\n");
@@ -490,8 +528,13 @@ static int axiemac_start(struct udevice *dev)
axi_dma_init(priv);
/* Initialize AxiEthernet hardware. */
- if (axi_ethernet_init(priv))
- return -1;
+ if (priv->mactype == EMAC_1G) {
+ if (axi_ethernet_init(priv))
+ return -1;
+ } else {
+ if (xxv_axi_ethernet_init(priv))
+ return -1;
+ }
/* Disable all RX interrupts before RxBD space setup */
temp = readl(>dmarx->control);
@@ -525,15 +568,25 @@ static int axiemac_start(struct udevice *dev)
/* Rx BD is ready - start */
axienet_dma_write(_bd, >dmarx->tail);
- /* Enable TX */
- writel(XAE_TC_TX_MASK, >tc);
- /* Enable RX */
- writel(XAE_RCW1_RX_MASK, >rcw1);
+ if (priv->mactype == EMAC_1G) {
+ struct axi_regs *regs = priv->iobase;
+ /* Enable TX */
+ writel(XAE_TC_TX_MASK, >tc);
+ /* Enable RX */
+ writel(XAE_RCW1_RX_MASK, >rcw1);
+
+ /* PHY setup */
+ if (!setup_phy(dev)) {
+ axiemac_stop(dev);
+ return -1;
+ }
+ } else {
+ struct xxv_axi_regs *regs = (struct xxv_axi_regs *)priv->iobase;
+ /* Enable TX */
+ writel(readl(>tc) | XXV_TC_TX_MASK, >tc);
-
[PATCH 1/2] net: xilinx: axi_emac: Cleanup of of_to_plat()
There are lot of accesses to priv data in of_to_plat(), which is incorrect.
Create a platform data structure and use it in of_to_plat(), then copy all
platform data to priv data in probe.
Signed-off-by: Ashok Reddy Soma
---
drivers/net/xilinx_axi_emac.c | 47 ---
1 file changed, 32 insertions(+), 15 deletions(-)
diff --git a/drivers/net/xilinx_axi_emac.c b/drivers/net/xilinx_axi_emac.c
index 2ce6271afe..cfc6082475 100644
--- a/drivers/net/xilinx_axi_emac.c
+++ b/drivers/net/xilinx_axi_emac.c
@@ -87,6 +87,16 @@ struct axidma_reg {
u32 tail_hi; /* TAILDESC high 32 bit */
};
+/* Platform data structures */
+struct axidma_plat {
+ struct eth_pdata eth_pdata;
+ struct axidma_reg *dmatx;
+ struct axidma_reg *dmarx;
+ int phyaddr;
+ u8 eth_hasnobuf;
+ int phy_of_handle;
+};
+
/* Private driver structures */
struct axidma_priv {
struct axidma_reg *dmatx;
@@ -690,9 +700,20 @@ static int axiemac_miiphy_write(struct mii_dev *bus, int
addr, int devad,
static int axi_emac_probe(struct udevice *dev)
{
+ struct axidma_plat *plat = dev_get_plat(dev);
+ struct eth_pdata *pdata = >eth_pdata;
struct axidma_priv *priv = dev_get_priv(dev);
int ret;
+ priv->iobase = (struct axi_regs *)pdata->iobase;
+ priv->dmatx = plat->dmatx;
+ /* RX channel offset is 0x30 */
+ priv->dmarx = (struct axidma_reg *)((phys_addr_t)priv->dmatx + 0x30);
+ priv->eth_hasnobuf = plat->eth_hasnobuf;
+ priv->phyaddr = plat->phyaddr;
+ priv->phy_of_handle = plat->phy_of_handle;
+ priv->interface = pdata->phy_interface;
+
priv->bus = mdio_alloc();
priv->bus->read = axiemac_miiphy_read;
priv->bus->write = axiemac_miiphy_write;
@@ -729,14 +750,13 @@ static const struct eth_ops axi_emac_ops = {
static int axi_emac_of_to_plat(struct udevice *dev)
{
- struct eth_pdata *pdata = dev_get_plat(dev);
- struct axidma_priv *priv = dev_get_priv(dev);
+ struct axidma_plat *plat = dev_get_plat(dev);
+ struct eth_pdata *pdata = >eth_pdata;
int node = dev_of_offset(dev);
int offset = 0;
const char *phy_mode;
pdata->iobase = dev_read_addr(dev);
- priv->iobase = (struct axi_regs *)pdata->iobase;
offset = fdtdec_lookup_phandle(gd->fdt_blob, node,
"axistream-connected");
@@ -744,21 +764,19 @@ static int axi_emac_of_to_plat(struct udevice *dev)
printf("%s: axistream is not found\n", __func__);
return -EINVAL;
}
- priv->dmatx = (struct axidma_reg *)fdtdec_get_addr(gd->fdt_blob,
+ plat->dmatx = (struct axidma_reg *)fdtdec_get_addr(gd->fdt_blob,
offset, "reg");
- if (!priv->dmatx) {
+ if (!plat->dmatx) {
printf("%s: axi_dma register space not found\n", __func__);
return -EINVAL;
}
- /* RX channel offset is 0x30 */
- priv->dmarx = (struct axidma_reg *)((phys_addr_t)priv->dmatx + 0x30);
- priv->phyaddr = -1;
+ plat->phyaddr = -1;
offset = fdtdec_lookup_phandle(gd->fdt_blob, node, "phy-handle");
if (offset > 0) {
- priv->phyaddr = fdtdec_get_int(gd->fdt_blob, offset, "reg", -1);
- priv->phy_of_handle = offset;
+ plat->phyaddr = fdtdec_get_int(gd->fdt_blob, offset, "reg", -1);
+ plat->phy_of_handle = offset;
}
phy_mode = fdt_getprop(gd->fdt_blob, node, "phy-mode", NULL);
@@ -768,13 +786,12 @@ static int axi_emac_of_to_plat(struct udevice *dev)
printf("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
return -EINVAL;
}
- priv->interface = pdata->phy_interface;
- priv->eth_hasnobuf = fdtdec_get_bool(gd->fdt_blob, node,
+ plat->eth_hasnobuf = fdtdec_get_bool(gd->fdt_blob, node,
"xlnx,eth-hasnobuf");
- printf("AXI EMAC: %lx, phyaddr %d, interface %s\n", (ulong)priv->iobase,
- priv->phyaddr, phy_string_for_interface(priv->interface));
+ printf("AXI EMAC: %lx, phyaddr %d, interface %s\n",
(ulong)pdata->iobase,
+ plat->phyaddr, phy_string_for_interface(pdata->phy_interface));
return 0;
}
@@ -793,5 +810,5 @@ U_BOOT_DRIVER(axi_emac) = {
.remove = axi_emac_remove,
.ops= _emac_ops,
.priv_auto = sizeof(struct axidma_priv),
- .plat_auto = sizeof(struct eth_pdata),
+ .plat_auto = sizeof(struct axidma_plat),
};
--
2.17.1
[PATCH 0/2] Add support for 10G/25G to AXI emac driver
- Cleanup of_to_plat() to access platform data only in it - Copy plat data to priv data in probe function - Add support for 10G/25G to the AXI emac driver - Keep all phy related activity in the driver for 1G only Ashok Reddy Soma (2): net: xilinx: axi_emac: Cleanup of of_to_plat() net: xilinx: axi_emac: Add support for 10G/25G AXI ethernet drivers/net/xilinx_axi_emac.c | 193 +- 1 file changed, 142 insertions(+), 51 deletions(-) -- 2.17.1
Re: [PATCH v2] mtd: spinand: macronix: Add support for serial NAND flash
On Mon, Jun 7, 2021 at 1:47 PM Jaime Liao wrote: > > Macronix NAND Flash devices are available in different configurations > and densities. > > MX"35" means SPI NAND > MX35"UF" , UF meands 1.8V > MX35LF"2G" , 2G means 2Gbits > MX35LF2G"E4" , E4 means internal ECC and Quad I/O(x4) > > MX35UF4GE4AD/MX35UF2GE4AD/MX35UF1GE4AD are 1.8V 4G/2Gbit serial > NAND flash device with 8-bit on-die ECC > https://www.mxic.com.tw/Lists/Datasheet/Attachments/7983/MX35UF4GE4AD,%201.8V,%204Gb,%20v0.00.pdf > > MX35UF2GE4AC/MX35UF1GE4AC are 1.8V 2G/1Gbit serial > NAND flash device with 8-bit on-die ECC > https://www.mxic.com.tw/Lists/Datasheet/Attachments/7974/MX35UF2GE4AC,%201.8V,%202Gb,%20v1.0.pdf > > Validated via normal(default) and QUAD mode by read, erase, read back, > on Xilinx Zynq PicoZed FPGA board which included Macronix > SPI Host(drivers/spi/spi-mxic.c). > > Signed-off-by: Jaime Liao > --- Applied to u-boot-spi/master
