Re: [PATCH v3] board: gateworks: venice: enable DM_SERIAL
HI Adam
On Thu, Apr 14, 2022 at 8:44 PM Adam Ford wrote:
>
> On Thu, Apr 14, 2022 at 1:34 PM Tim Harvey wrote:
> >
> > On Thu, Apr 14, 2022 at 11:02 AM Michael Nazzareno Trimarchi
> > wrote:
> > >
> > > HI Tim
> > >
> > > On Thu, Apr 14, 2022 at 7:53 PM Tim Harvey wrote:
> > > >
> > > > Enable DM_SERIAL for both U_Boot and the SPL. The uart2 and its pinmux
> > > > are already marked with u-boot,dm-spl but we need to move the call to
> > > > preloader_console_init() after spl_early_init() to avoid a board hang
> > > > as dm can't be used until after spl_early_init().
> > > >
> > > > Remove the manual config of the UART pinmux now that it is no longer
> > > > needed.
> > > >
> > > > Signed-off-by: Tim Harvey
> > > > Cc: Michael Nazzareno Trimarchi
> > > > ---
> > > > v3: enable DM_SERIAL for SPL as well per Michael's suggestion
> > > > v2: rebase on imx/master
> > > > ---
> > > > board/gateworks/venice/spl.c| 17 ++---
> > > > configs/imx8mm_venice_defconfig | 1 +
> > > > configs/imx8mn_venice_defconfig | 1 +
> > > > 3 files changed, 4 insertions(+), 15 deletions(-)
> > > >
> > > > diff --git a/board/gateworks/venice/spl.c b/board/gateworks/venice/spl.c
> > > > index b56e1b607d58..59a6a29f70d8 100644
> > > > --- a/board/gateworks/venice/spl.c
> > > > +++ b/board/gateworks/venice/spl.c
> > > > @@ -87,25 +87,14 @@ static void spl_dram_init(int size)
> > > > ddr_init(dram_timing);
> > > > }
> > > >
> > > > -#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
> > > > #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE |
> > > > PAD_CTL_PE)
> > > >
> > > > #ifdef CONFIG_IMX8MM
> > > > -static iomux_v3_cfg_t const uart_pads[] = {
> > > > - IMX8MM_PAD_UART2_RXD_UART2_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
> > > > - IMX8MM_PAD_UART2_TXD_UART2_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
> > > > -};
> > > > -
> > >
> > >
> > > What about the clock? I'm a bit surprised that it works without the
> > > clock enabled.
> > >
> >
> > Michael,
> >
> > The clock hasn't changed. Like Peng's series for converting
> > imx8mm-evk, imx8mn-evk, and imx8mp-evk to DM_SERIAL, the
> > board_init_f() function still calls 'init_uart_clk(1)' for UART2
> > (index is 0-based UART) and that is still required. I'm not sure why
> > the dm IMX driver can't do that but it doesn't currently and that
> > could always be an imx8mm general cleanup later.
>
> I think that's because the clock driver doesn't have the uart clocks
> in it. I was investigating the hanging in SPL with DM_SERIAL and
> noticed from the clk dump that the uart clocks were not present, so I
> added them to the clock driver, but I didn't have success. I also
> tried moving the preloader_console_init and switching to early spl
> init instead of a regular one. Because I wasn't successful, I didn't
> do anything with those patches, but I can post them to the mailing
> list if there is interest.
I have sent mine but I was thinking of doing the same. What I found
that is really
strange
commit b41d4b83f0203be79a3bfa1e4bde316355c7f2a0
Author: Sean Anderson
Date: Sun Feb 2 13:15:17 2020 -0500
serial: Set baudrate on boot
Currently, the baud rate is never set on boot. This works ok when a previous
bootloader has configured the baudrate properly, or when the
baudrate is set to
a reasonable default in the serial driver's probe(). However, when
this is not
the case, we could be using a different baud rate than what was configured.
Signed-off-by: Sean Anderson
Where I don't know if the probe is called later and we can not set or
get the clock from there. imx7d
enable all the clock for clock serial in clk init
Michael
>
> adam
> >
> > Are your questions because you are trying to implement DM_SERIAL for
> > one of your boards and having issues? If so, please submit your patch
> > as an RFC so we can try to help.
> >
> > Best Regards,
> >
> > Tim
> >
> > > Michael
> > >
> > > > static iomux_v3_cfg_t const wdog_pads[] = {
> > > > IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B |
> > > > MUX_PAD_CTRL(WDOG_PAD_CTRL),
> > > > };
> > > > #endif
> > > > #ifdef CONFIG_IMX8MN
> > > > -static const iomux_v3_cfg_t uart_pads[] = {
> > > > - IMX8MN_PAD_UART2_RXD__UART2_DCE_RX |
> > > > MUX_PAD_CTRL(UART_PAD_CTRL),
> > > > - IMX8MN_PAD_UART2_TXD__UART2_DCE_TX |
> > > > MUX_PAD_CTRL(UART_PAD_CTRL),
> > > > -};
> > > > -
> > > > static const iomux_v3_cfg_t wdog_pads[] = {
> > > > IMX8MN_PAD_GPIO1_IO02__WDOG1_WDOG_B |
> > > > MUX_PAD_CTRL(WDOG_PAD_CTRL),
> > > > };
> > > > @@ -119,8 +108,6 @@ int board_early_init_f(void)
> > > >
> > > > set_wdog_reset(wdog);
> > > >
> > > > - imx_iomux_v3_setup_multiple_pads(uart_pads,
> > > > ARRAY_SIZE(uart_pads));
> > > > -
> > > > return 0;
> > > > }
> > > >
> > > > @@ -232,8 +219,6 @@ void board_init_f(ulong dummy)
> > > >
> > > > timer_init();
> > > >
> > > > - preloader_console_init();
> > > > -
> > > > /*
Re: [PATCH v3] board: gateworks: venice: enable DM_SERIAL
Hi Tim
Il gio 14 apr 2022, 20:33 Tim Harvey ha scritto:
> On Thu, Apr 14, 2022 at 11:02 AM Michael Nazzareno Trimarchi
> wrote:
> >
> > HI Tim
> >
> > On Thu, Apr 14, 2022 at 7:53 PM Tim Harvey
> wrote:
> > >
> > > Enable DM_SERIAL for both U_Boot and the SPL. The uart2 and its pinmux
> > > are already marked with u-boot,dm-spl but we need to move the call to
> > > preloader_console_init() after spl_early_init() to avoid a board hang
> > > as dm can't be used until after spl_early_init().
> > >
> > > Remove the manual config of the UART pinmux now that it is no longer
> > > needed.
> > >
> > > Signed-off-by: Tim Harvey
> > > Cc: Michael Nazzareno Trimarchi
> > > ---
> > > v3: enable DM_SERIAL for SPL as well per Michael's suggestion
> > > v2: rebase on imx/master
> > > ---
> > > board/gateworks/venice/spl.c| 17 ++---
> > > configs/imx8mm_venice_defconfig | 1 +
> > > configs/imx8mn_venice_defconfig | 1 +
> > > 3 files changed, 4 insertions(+), 15 deletions(-)
> > >
> > > diff --git a/board/gateworks/venice/spl.c
> b/board/gateworks/venice/spl.c
> > > index b56e1b607d58..59a6a29f70d8 100644
> > > --- a/board/gateworks/venice/spl.c
> > > +++ b/board/gateworks/venice/spl.c
> > > @@ -87,25 +87,14 @@ static void spl_dram_init(int size)
> > > ddr_init(dram_timing);
> > > }
> > >
> > > -#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
> > > #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE |
> PAD_CTL_PE)
> > >
> > > #ifdef CONFIG_IMX8MM
> > > -static iomux_v3_cfg_t const uart_pads[] = {
> > > - IMX8MM_PAD_UART2_RXD_UART2_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
> > > - IMX8MM_PAD_UART2_TXD_UART2_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
> > > -};
> > > -
> >
> >
> > What about the clock? I'm a bit surprised that it works without the
> > clock enabled.
> >
>
> Michael,
>
> The clock hasn't changed. Like Peng's series for converting
> imx8mm-evk, imx8mn-evk, and imx8mp-evk to DM_SERIAL, the
> board_init_f() function still calls 'init_uart_clk(1)' for UART2
> (index is 0-based UART) and that is still required. I'm not sure why
> the dm IMX driver can't do that but it doesn't currently and that
> could always be an imx8mm general cleanup later.
>
> Are your questions because you are trying to implement DM_SERIAL for
> one of your boards and having issues? If so, please submit your patch
> as an RFC so we can try to help.
>
Was just a question on your changes. I already have my patch and I will
post. Clk for me is not removed.
Michael
> Best Regards,
>
> Tim
>
> > Michael
> >
> > > static iomux_v3_cfg_t const wdog_pads[] = {
> > > IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B |
> MUX_PAD_CTRL(WDOG_PAD_CTRL),
> > > };
> > > #endif
> > > #ifdef CONFIG_IMX8MN
> > > -static const iomux_v3_cfg_t uart_pads[] = {
> > > - IMX8MN_PAD_UART2_RXD__UART2_DCE_RX |
> MUX_PAD_CTRL(UART_PAD_CTRL),
> > > - IMX8MN_PAD_UART2_TXD__UART2_DCE_TX |
> MUX_PAD_CTRL(UART_PAD_CTRL),
> > > -};
> > > -
> > > static const iomux_v3_cfg_t wdog_pads[] = {
> > > IMX8MN_PAD_GPIO1_IO02__WDOG1_WDOG_B |
> MUX_PAD_CTRL(WDOG_PAD_CTRL),
> > > };
> > > @@ -119,8 +108,6 @@ int board_early_init_f(void)
> > >
> > > set_wdog_reset(wdog);
> > >
> > > - imx_iomux_v3_setup_multiple_pads(uart_pads,
> ARRAY_SIZE(uart_pads));
> > > -
> > > return 0;
> > > }
> > >
> > > @@ -232,8 +219,6 @@ void board_init_f(ulong dummy)
> > >
> > > timer_init();
> > >
> > > - preloader_console_init();
> > > -
> > > /* Clear the BSS. */
> > > memset(__bss_start, 0, __bss_end - __bss_start);
> > >
> > > @@ -243,6 +228,8 @@ void board_init_f(ulong dummy)
> > > hang();
> > > }
> > >
> > > + preloader_console_init();
> > > +
> > > ret = uclass_get_device_by_name(UCLASS_CLK,
> > > "clock-controller@3038",
> > > );
> > > diff --git a/configs/imx8mm_venice_defconfig
> b/configs/imx8mm_venice_defconfig
> > > index dd61ec9b70fb..1ccbe9970a6c 100644
> > > --- a/configs/imx8mm_venice_defconfig
> > > +++ b/configs/imx8mm_venice_defconfig
> > > @@ -110,6 +110,7 @@ CONFIG_SPL_DM_PMIC_MP5416=y
> > > CONFIG_DM_REGULATOR=y
> > > CONFIG_DM_REGULATOR_FIXED=y
> > > CONFIG_DM_REGULATOR_GPIO=y
> > > +CONFIG_DM_SERIAL=y
> > > CONFIG_MXC_UART=y
> > > CONFIG_SYSRESET=y
> > > CONFIG_SPL_SYSRESET=y
> > > diff --git a/configs/imx8mn_venice_defconfig
> b/configs/imx8mn_venice_defconfig
> > > index c3a96a378553..ff926dac0e18 100644
> > > --- a/configs/imx8mn_venice_defconfig
> > > +++ b/configs/imx8mn_venice_defconfig
> > > @@ -108,6 +108,7 @@ CONFIG_SPL_DM_PMIC_MP5416=y
> > > CONFIG_DM_REGULATOR=y
> > > CONFIG_DM_REGULATOR_FIXED=y
> > > CONFIG_DM_REGULATOR_GPIO=y
> > > +CONFIG_DM_SERIAL=y
> > > CONFIG_MXC_UART=y
> > > CONFIG_SYSRESET=y
> > > CONFIG_SPL_SYSRESET=y
> > > --
> > > 2.17.1
> > >
> >
> >
> > --
> > Michael Nazzareno Trimarchi
> >
[PATCH V2] board: bsh: imx8mn_bsh_smm_s2/s2pro: enable DM_SERIAL
Enable DM_SERIAL for both U_Boot and the SPL. The uart2 and its pinmux
are already marked with u-boot,dm-spl but we need to move the call to
preloader_console_init() after spl_init() to avoid a board hang
as dm can't be used until after spl_init().
Remove the manual config of the UART pinmux now that it is no longer
needed.
Signed-off-by: Michael Trimarchi
Cc: Tim Harvey
---
V1->V2:
- Follow Tim Harvery suggestion on Peng change
- Adjust the commit message as Tim
---
board/bsh/imx8mn_smm_s2/spl.c | 11 ++-
configs/imx8mn_bsh_smm_s2_defconfig| 1 +
configs/imx8mn_bsh_smm_s2pro_defconfig | 1 +
3 files changed, 4 insertions(+), 9 deletions(-)
diff --git a/board/bsh/imx8mn_smm_s2/spl.c b/board/bsh/imx8mn_smm_s2/spl.c
index 5f04731d72..0f61acc630 100644
--- a/board/bsh/imx8mn_smm_s2/spl.c
+++ b/board/bsh/imx8mn_smm_s2/spl.c
@@ -40,14 +40,8 @@ void spl_board_init(void)
puts("Failed to find clock node. Check device tree\n");
}
-#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
-static const iomux_v3_cfg_t uart_pads[] = {
- IMX8MN_PAD_UART4_RXD__UART4_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
- IMX8MN_PAD_UART4_TXD__UART4_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
-};
-
static const iomux_v3_cfg_t wdog_pads[] = {
IMX8MN_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
};
@@ -59,7 +53,6 @@ int board_early_init_f(void)
imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
set_wdog_reset(wdog);
- imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
init_uart_clk(3);
if (IS_ENABLED(CONFIG_NAND_MXS)) {
@@ -82,14 +75,14 @@ void board_init_f(ulong dummy)
timer_init();
- preloader_console_init();
-
ret = spl_init();
if (ret) {
debug("spl_init() failed: %d\n", ret);
hang();
}
+ preloader_console_init();
+
/* DDR initialization */
spl_dram_init();
diff --git a/configs/imx8mn_bsh_smm_s2_defconfig
b/configs/imx8mn_bsh_smm_s2_defconfig
index 3d67079a46..e864685a62 100644
--- a/configs/imx8mn_bsh_smm_s2_defconfig
+++ b/configs/imx8mn_bsh_smm_s2_defconfig
@@ -80,6 +80,7 @@ CONFIG_SPL_DM_PMIC_BD71837=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_SERIAL=y
CONFIG_MXC_UART=y
CONFIG_SYSRESET=y
CONFIG_SYSRESET_PSCI=y
diff --git a/configs/imx8mn_bsh_smm_s2pro_defconfig
b/configs/imx8mn_bsh_smm_s2pro_defconfig
index c5809f5d4b..dfc9c93809 100644
--- a/configs/imx8mn_bsh_smm_s2pro_defconfig
+++ b/configs/imx8mn_bsh_smm_s2pro_defconfig
@@ -77,6 +77,7 @@ CONFIG_SPL_DM_PMIC_BD71837=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_SERIAL=y
CONFIG_MXC_UART=y
CONFIG_SYSRESET=y
CONFIG_SYSRESET_PSCI=y
--
2.25.1
[PATCH V4 4/4] imx: imx8mq-evk: enable CONFIG_DM_SERIAL
From: Peng Fan
Marked related nodes as u-boot,dm-spl for serial driver model
Enable CONFIG_DM_SERIAL
Signed-off-by: Peng Fan
---
arch/arm/dts/imx8mq-evk-u-boot.dtsi | 32 +
configs/imx8mq_evk_defconfig| 1 +
2 files changed, 33 insertions(+)
diff --git a/arch/arm/dts/imx8mq-evk-u-boot.dtsi
b/arch/arm/dts/imx8mq-evk-u-boot.dtsi
index 6f9c81462ea..919c1f66d38 100644
--- a/arch/arm/dts/imx8mq-evk-u-boot.dtsi
+++ b/arch/arm/dts/imx8mq-evk-u-boot.dtsi
@@ -2,6 +2,34 @@
#include "imx8mq-u-boot.dtsi"
+&{/soc@0} {
+ u-boot,dm-spl;
+};
+
+&{/soc@0/bus@3000} {
+ u-boot,dm-spl;
+};
+
+&{/soc@0/bus@3040} {
+ u-boot,dm-spl;
+};
+
+&{/soc@0/bus@3080} {
+ u-boot,dm-spl;
+};
+
+&{/soc@0/bus@32c0} {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+_uart1 {
+ u-boot,dm-spl;
+};
+
{
mmc-hs400-1_8v;
};
@@ -10,3 +38,7 @@
sd-uhs-sdr104;
sd-uhs-ddr50;
};
+
+ {
+ u-boot,dm-spl;
+};
diff --git a/configs/imx8mq_evk_defconfig b/configs/imx8mq_evk_defconfig
index df7a259f35a..780f93103c7 100644
--- a/configs/imx8mq_evk_defconfig
+++ b/configs/imx8mq_evk_defconfig
@@ -80,6 +80,7 @@ CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_SPL_POWER_I2C=y
CONFIG_DM_RESET=y
+CONFIG_DM_SERIAL=y
CONFIG_MXC_UART=y
CONFIG_DM_THERMAL=y
CONFIG_USB=y
--
2.35.1
[PATCH V4 3/4] imx: imx8mn_evk: enable CONFIG_DM_SERIAL
From: Peng Fan
Enable CONFIG_DM_SERIAL. uart2 and its pinmux was already
marked with u-boot,dm-spl.
move the preloader_console_init() call after spl_init() to
avoid board hang
Signed-off-by: Peng Fan
---
board/freescale/imx8mn_evk/spl.c | 12 ++--
configs/imx8mn_ddr4_evk_defconfig | 1 +
configs/imx8mn_evk_defconfig | 1 -
3 files changed, 3 insertions(+), 11 deletions(-)
diff --git a/board/freescale/imx8mn_evk/spl.c b/board/freescale/imx8mn_evk/spl.c
index dfa81a0d652..63f335be3b0 100644
--- a/board/freescale/imx8mn_evk/spl.c
+++ b/board/freescale/imx8mn_evk/spl.c
@@ -115,14 +115,8 @@ int board_fit_config_name_match(const char *name)
}
#endif
-#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
-static iomux_v3_cfg_t const uart_pads[] = {
- IMX8MN_PAD_UART2_RXD__UART2_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
- IMX8MN_PAD_UART2_TXD__UART2_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
-};
-
static iomux_v3_cfg_t const wdog_pads[] = {
IMX8MN_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
};
@@ -135,8 +129,6 @@ int board_early_init_f(void)
set_wdog_reset(wdog);
- imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
-
return 0;
}
@@ -152,8 +144,6 @@ void board_init_f(ulong dummy)
timer_init();
- preloader_console_init();
-
/* Clear the BSS. */
memset(__bss_start, 0, __bss_end - __bss_start);
@@ -163,6 +153,8 @@ void board_init_f(ulong dummy)
hang();
}
+ preloader_console_init();
+
enable_tzc380();
/* DDR initialization */
diff --git a/configs/imx8mn_ddr4_evk_defconfig
b/configs/imx8mn_ddr4_evk_defconfig
index 917cdb5aa9d..474d9cfa4d2 100644
--- a/configs/imx8mn_ddr4_evk_defconfig
+++ b/configs/imx8mn_ddr4_evk_defconfig
@@ -76,6 +76,7 @@ CONFIG_PINCTRL_IMX8M=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_SERIAL=y
CONFIG_MXC_UART=y
CONFIG_SYSRESET=y
CONFIG_SPL_SYSRESET=y
diff --git a/configs/imx8mn_evk_defconfig b/configs/imx8mn_evk_defconfig
index b2981d1e369..5bc175154ba 100644
--- a/configs/imx8mn_evk_defconfig
+++ b/configs/imx8mn_evk_defconfig
@@ -84,7 +84,6 @@ CONFIG_SPL_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_DM_SERIAL=y
-# CONFIG_SPL_DM_SERIAL is not set
CONFIG_MXC_UART=y
CONFIG_SYSRESET=y
CONFIG_SPL_SYSRESET=y
--
2.35.1
[PATCH V4 2/4] imx: imx8mm_evk: enable CONFIG_DM_SERIAL
From: Peng Fan
Enable CONFIG_DM_SERIAL. uart2 and its pinmux was already
marked with u-boot,dm-spl.
move the preloader_console_init() call after spl_early_init() to
avoid board hang
Signed-off-by: Peng Fan
---
board/freescale/imx8mm_evk/spl.c | 12 ++--
configs/imx8mm_evk_defconfig | 1 +
2 files changed, 3 insertions(+), 10 deletions(-)
diff --git a/board/freescale/imx8mm_evk/spl.c b/board/freescale/imx8mm_evk/spl.c
index cf4882cd10c..7eeec6c485a 100644
--- a/board/freescale/imx8mm_evk/spl.c
+++ b/board/freescale/imx8mm_evk/spl.c
@@ -72,14 +72,8 @@ int board_fit_config_name_match(const char *name)
}
#endif
-#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
-static iomux_v3_cfg_t const uart_pads[] = {
- IMX8MM_PAD_UART2_RXD_UART2_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
- IMX8MM_PAD_UART2_TXD_UART2_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
-};
-
static iomux_v3_cfg_t const wdog_pads[] = {
IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
};
@@ -92,8 +86,6 @@ int board_early_init_f(void)
set_wdog_reset(wdog);
- imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
-
return 0;
}
@@ -147,8 +139,6 @@ void board_init_f(ulong dummy)
timer_init();
- preloader_console_init();
-
/* Clear the BSS. */
memset(__bss_start, 0, __bss_end - __bss_start);
@@ -166,6 +156,8 @@ void board_init_f(ulong dummy)
hang();
}
+ preloader_console_init();
+
enable_tzc380();
power_init_board();
diff --git a/configs/imx8mm_evk_defconfig b/configs/imx8mm_evk_defconfig
index 36bf17d1ac0..9ee157c214a 100644
--- a/configs/imx8mm_evk_defconfig
+++ b/configs/imx8mm_evk_defconfig
@@ -79,6 +79,7 @@ CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_DM_PWM=y
+CONFIG_DM_SERIAL=y
CONFIG_PWM_IMX=y
CONFIG_MXC_UART=y
CONFIG_SYSRESET=y
--
2.35.1
[PATCH V4 1/4] imx: imx8mp_evk: enable CONFIG_DM_SERIAL
From: Peng Fan
Enable CONFIG_DM_SERIAL. uart2 and its pinmux was already
marked with u-boot,dm-spl.
Signed-off-by: Peng Fan
---
board/freescale/imx8mp_evk/imx8mp_evk.c | 8
configs/imx8mp_evk_defconfig| 1 +
2 files changed, 1 insertion(+), 8 deletions(-)
diff --git a/board/freescale/imx8mp_evk/imx8mp_evk.c
b/board/freescale/imx8mp_evk/imx8mp_evk.c
index 62096c24fb7..fb6c61c39e7 100644
--- a/board/freescale/imx8mp_evk/imx8mp_evk.c
+++ b/board/freescale/imx8mp_evk/imx8mp_evk.c
@@ -20,14 +20,8 @@
DECLARE_GLOBAL_DATA_PTR;
-#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
-static iomux_v3_cfg_t const uart_pads[] = {
- MX8MP_PAD_UART2_RXD__UART2_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
- MX8MP_PAD_UART2_TXD__UART2_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
-};
-
static iomux_v3_cfg_t const wdog_pads[] = {
MX8MP_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
};
@@ -40,8 +34,6 @@ int board_early_init_f(void)
set_wdog_reset(wdog);
- imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
-
return 0;
}
diff --git a/configs/imx8mp_evk_defconfig b/configs/imx8mp_evk_defconfig
index c64b699e105..01240e543af 100644
--- a/configs/imx8mp_evk_defconfig
+++ b/configs/imx8mp_evk_defconfig
@@ -91,6 +91,7 @@ CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_SPL_POWER_I2C=y
+CONFIG_DM_SERIAL=y
CONFIG_MXC_UART=y
CONFIG_SYSRESET=y
CONFIG_SPL_SYSRESET=y
--
2.35.1
[PATCH V4 0/4] imx: imx8m: enable DM SERIAL
From: Peng Fan V4: Rebased, update commit log Per Tim's comments V3: Add missed Signed-off-by Rebased to only add CONFIG_DM_SERIAL, not touch other config change in defconfig V2: Include imx8mq-evk in this patchset. For i.MX8MN/M/P, drop board level uart pinmux settings, move preloader_console_init after driver probe. Tested on all four boards. Note i.MX8MQ-EVK not have SPL_DM, so pinmux for uart still there for spl usage. Peng Fan (4): imx: imx8mp_evk: enable CONFIG_DM_SERIAL imx: imx8mm_evk: enable CONFIG_DM_SERIAL imx: imx8mn_evk: enable CONFIG_DM_SERIAL imx: imx8mq-evk: enable CONFIG_DM_SERIAL arch/arm/dts/imx8mq-evk-u-boot.dtsi | 32 + board/freescale/imx8mm_evk/spl.c| 12 ++ board/freescale/imx8mn_evk/spl.c| 12 ++ board/freescale/imx8mp_evk/imx8mp_evk.c | 8 --- configs/imx8mm_evk_defconfig| 1 + configs/imx8mn_ddr4_evk_defconfig | 1 + configs/imx8mn_evk_defconfig| 1 - configs/imx8mp_evk_defconfig| 1 + configs/imx8mq_evk_defconfig| 1 + 9 files changed, 40 insertions(+), 29 deletions(-) -- 2.35.1
Re: [PATCH v7 09/15] disk: Correct the conditions for SPL
On Thu, Apr 14, 2022 at 08:31:12AM -0400, Tom Rini wrote: > On Thu, Apr 14, 2022 at 05:21:52PM +0900, AKASHI Takahiro wrote: > > Hi Simon, > > > > On Mon, Feb 28, 2022 at 07:16:51AM -0700, Simon Glass wrote: > > > These filesystems may have different settings for SPL and TPL. Use the > > > correct Makefile variable to handle this. > > > > > > Signed-off-by: Simon Glass > > > --- > > > > > > Changes in v7: > > > - Add new patch to correct the conditions for SPL > > > > > > disk/Makefile | 10 +- > > > 1 file changed, 5 insertions(+), 5 deletions(-) > > > > > > diff --git a/disk/Makefile b/disk/Makefile > > > index 6ce5a687b3..83f5af6069 100644 > > > --- a/disk/Makefile > > > +++ b/disk/Makefile > > > @@ -6,8 +6,8 @@ > > > #ccflags-y += -DET_DEBUG -DDEBUG > > > > > > obj-$(CONFIG_PARTITIONS) += part.o > > > -obj-$(CONFIG_$(SPL_)MAC_PARTITION) += part_mac.o > > > -obj-$(CONFIG_$(SPL_)DOS_PARTITION) += part_dos.o > > > -obj-$(CONFIG_$(SPL_)ISO_PARTITION) += part_iso.o > > > -obj-$(CONFIG_$(SPL_)AMIGA_PARTITION) += part_amiga.o > > > -obj-$(CONFIG_$(SPL_)EFI_PARTITION) += part_efi.o > > > +obj-$(CONFIG_$(SPL_TPL_)MAC_PARTITION) += part_mac.o > > > +obj-$(CONFIG_$(SPL_TPL_)DOS_PARTITION) += part_dos.o > > > +obj-$(CONFIG_$(SPL_TPL_)ISO_PARTITION) += part_iso.o > > > +obj-$(CONFIG_$(SPL_TPL_)AMIGA_PARTITION) += part_amiga.o > > > +obj-$(CONFIG_$(SPL_TPL_)EFI_PARTITION) += part_efi.o > > > > While none of CONFIG_TPL_xxx_PARTITION is defined, > > how do those rules work for TPL? > > The makefile logic means that if the options are added then they would > work as intended. With the options not being in Kconfig they'll simply > never be evaluated to y. Okay, so it is intentional. But I believe that the changes made around disk/ are not enough. For instance, in include/part.h, there still exist a couple of #ifdef CONFIG_PARTITIONS So some functions are nullified even if SPL_PARTITIONS (and particular partition table types) is enabled. I'm trying to fix some of issues when addressing the issue: https://lists.denx.de/pipermail/u-boot/2022-April/481258.html -Takahiro Akashi > > -- > Tom
[PATCH V2 12/12] configs: imx: drop IMX_FEC_BASE
From: Peng Fan
IMX_FEC_BASE is not used in these boards, so drop it.
Reviewed-by: Fabio Estevam
Signed-off-by: Peng Fan
---
include/configs/apalis-imx8x.h | 1 -
include/configs/aristainetos2.h | 1 -
include/configs/cm_fx6.h | 1 -
include/configs/colibri-imx6ull.h| 1 -
include/configs/dh_imx6.h| 1 -
include/configs/liteboard.h | 1 -
include/configs/m53menlo.h | 1 -
include/configs/mccmon6.h| 1 -
include/configs/mx6sxsabresd.h | 1 -
include/configs/mx6ul_14x14_evk.h| 2 --
include/configs/npi_imx6ull.h| 1 -
include/configs/pico-imx6.h | 1 -
include/configs/pico-imx6ul.h| 1 -
include/configs/somlabs_visionsom_6ull.h | 1 -
include/configs/tqma6.h | 1 -
include/configs/vf610twr.h | 1 -
include/configs/vining_2000.h| 1 -
include/configs/xpress.h | 1 -
18 files changed, 19 deletions(-)
diff --git a/include/configs/apalis-imx8x.h b/include/configs/apalis-imx8x.h
index 71a80f38bbb..762bc49e671 100644
--- a/include/configs/apalis-imx8x.h
+++ b/include/configs/apalis-imx8x.h
@@ -120,7 +120,6 @@
/* Networking */
#define CONFIG_FEC_ENET_DEV 0
-#define IMX_FEC_BASE 0x5b04
#define CONFIG_FEC_MXC_PHYADDR 0x4
#define PHY_ANEG_TIMEOUT 2
diff --git a/include/configs/aristainetos2.h b/include/configs/aristainetos2.h
index 0dcd4cae2fa..8ee97f1d4e3 100644
--- a/include/configs/aristainetos2.h
+++ b/include/configs/aristainetos2.h
@@ -30,7 +30,6 @@
/* MMC Configs */
#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR
-#define IMX_FEC_BASE ENET_BASE_ADDR
#define CONFIG_FEC_MXC_PHYADDR 0
#define CONFIG_SYS_SPI_ST_ENABLE_WP_PIN
diff --git a/include/configs/cm_fx6.h b/include/configs/cm_fx6.h
index f836f920bd8..600999b8e72 100644
--- a/include/configs/cm_fx6.h
+++ b/include/configs/cm_fx6.h
@@ -147,7 +147,6 @@
/* Ethernet */
#define CONFIG_FEC_MXC_PHYADDR 0
-#define IMX_FEC_BASE ENET_BASE_ADDR
/* USB */
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
diff --git a/include/configs/colibri-imx6ull.h
b/include/configs/colibri-imx6ull.h
index 281815e0863..5a7193a127f 100644
--- a/include/configs/colibri-imx6ull.h
+++ b/include/configs/colibri-imx6ull.h
@@ -16,7 +16,6 @@
#define PHYS_SDRAM_SIZESZ_1G
/* ENET1 */
-#define IMX_FEC_BASE ENET2_BASE_ADDR
/* MMC Config */
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
diff --git a/include/configs/dh_imx6.h b/include/configs/dh_imx6.h
index 3d3fab517e3..2b14464dff1 100644
--- a/include/configs/dh_imx6.h
+++ b/include/configs/dh_imx6.h
@@ -31,7 +31,6 @@
#define CONFIG_SYS_BOOTCOUNT_BE
/* FEC ethernet */
-#define IMX_FEC_BASE ENET_BASE_ADDR
#define CONFIG_FEC_MXC_PHYADDR 7
/* MMC Configs */
diff --git a/include/configs/liteboard.h b/include/configs/liteboard.h
index e8fd4e7a8e8..fdea7241b02 100644
--- a/include/configs/liteboard.h
+++ b/include/configs/liteboard.h
@@ -112,7 +112,6 @@
#ifdef CONFIG_CMD_NET
#define CONFIG_FEC_ENET_DEV0
-#define IMX_FEC_BASE ENET_BASE_ADDR
#define CONFIG_FEC_MXC_PHYADDR 0x0
#endif
diff --git a/include/configs/m53menlo.h b/include/configs/m53menlo.h
index 5bd6cbefc67..90877f548d6 100644
--- a/include/configs/m53menlo.h
+++ b/include/configs/m53menlo.h
@@ -69,7 +69,6 @@
* Ethernet on SOC (FEC)
*/
#ifdef CONFIG_CMD_NET
-#define IMX_FEC_BASE FEC_BASE_ADDR
#define CONFIG_FEC_MXC_PHYADDR 0x0
#endif
diff --git a/include/configs/mccmon6.h b/include/configs/mccmon6.h
index 59184290f37..dcce52eb7d3 100644
--- a/include/configs/mccmon6.h
+++ b/include/configs/mccmon6.h
@@ -40,7 +40,6 @@
#define CONFIG_SYS_FLASH_BANKS_SIZES { (32 * SZ_1M) }
/* Ethernet Configuration */
-#define IMX_FEC_BASE ENET_BASE_ADDR
#define CONFIG_FEC_MXC_PHYADDR 1
#define CONFIG_EXTRA_ENV_SETTINGS \
diff --git a/include/configs/mx6sxsabresd.h b/include/configs/mx6sxsabresd.h
index 2552fc0222e..76e3dc8b382 100644
--- a/include/configs/mx6sxsabresd.h
+++ b/include/configs/mx6sxsabresd.h
@@ -126,7 +126,6 @@
/* Network */
-#define IMX_FEC_BASE ENET_BASE_ADDR
#define CONFIG_FEC_MXC_PHYADDR 0x1
#ifdef CONFIG_CMD_USB
diff --git a/include/configs/mx6ul_14x14_evk.h
b/include/configs/mx6ul_14x14_evk.h
index 72554d18b0a..03d799ce654 100644
--- a/include/configs/mx6ul_14x14_evk.h
+++ b/include/configs/mx6ul_14x14_evk.h
@@ -134,10 +134,8 @@
#define CONFIG_FEC_ENET_DEV1
#if (CONFIG_FEC_ENET_DEV == 0)
-#define IMX_FEC_BASE ENET_BASE_ADDR
#define CONFIG_FEC_MXC_PHYADDR 0x2
#elif (CONFIG_FEC_ENET_DEV == 1)
-#define IMX_FEC_BASE ENET2_BASE_ADDR
#define
[PATCH V2 11/12] scripts: config_whitelist: drop CONFIG_MMCROOT
From: Peng Fan Drop CONFIG_MMCROOT, no users now. Reviewed-by: Fabio Estevam Signed-off-by: Peng Fan --- scripts/config_whitelist.txt | 1 - 1 file changed, 1 deletion(-) diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index ef7dbbfe982..12dd6e0302d 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -418,7 +418,6 @@ CONFIG_MII_DEFAULT_TSEC CONFIG_MISC_COMMON CONFIG_MIU_2BIT_21_7_INTERLEAVED CONFIG_MIU_2BIT_INTERLEAVED -CONFIG_MMCROOT CONFIG_MMC_DEFAULT_DEV CONFIG_MMC_SUNXI_SLOT CONFIG_MONITOR_IS_IN_RAM -- 2.35.1
[PATCH V2 10/12] configs: drop CONFIG_MMCROOT
From: Peng Fan
CONFIG_MMCROOT is only used to set mmcroot, no need a dedicated macro.
Script as below
"
for i in `ls include/configs/*.h`
do
mmcroot=`sed -n '/define.*MMCROOT/ p' $i | awk -F\" '{ print $2;}'`
if [ ! -n "$mmcroot" ]; then
continue
fi
sed -i '/define.*MMCROOT/ d' $i
sed -i 's,\" CONFIG_MMCROOT \",'$mmcroot',g' $i
done
"
Reviewed-by: Fabio Estevam
Signed-off-by: Peng Fan
---
include/configs/aristainetos2.h | 3 +--
include/configs/capricorn-common.h | 1 -
include/configs/cgtqmx8.h| 3 +--
include/configs/cl-som-imx7.h| 1 -
include/configs/imx7-cm.h| 3 +--
include/configs/imx8mm-cl-iot-gate.h | 3 +--
include/configs/imx8mm_evk.h | 3 +--
include/configs/imx8mn_evk.h | 3 +--
include/configs/imx8mp_evk.h | 3 +--
include/configs/imx8mp_rsb3720.h | 3 +--
include/configs/imx8mq_cm.h | 3 +--
include/configs/imx8mq_evk.h | 3 +--
include/configs/imx8mq_phanbell.h| 3 +--
include/configs/imx8qm_mek.h | 3 +--
include/configs/imx8qm_rom7720.h | 3 +--
include/configs/imx8qxp_mek.h| 3 +--
include/configs/imx8ulp_evk.h| 3 +--
include/configs/liteboard.h | 3 +--
include/configs/mx6sllevk.h | 3 +--
include/configs/mx6ul_14x14_evk.h| 3 +--
include/configs/mx6ullevk.h | 3 +--
include/configs/mx7ulp_com.h | 13 +++--
include/configs/mx7ulp_evk.h | 3 +--
include/configs/phycore_imx8mm.h | 1 -
include/configs/phycore_imx8mp.h | 1 -
include/configs/pico-imx8mq.h| 3 +--
include/configs/xpress.h | 3 +--
27 files changed, 33 insertions(+), 50 deletions(-)
diff --git a/include/configs/aristainetos2.h b/include/configs/aristainetos2.h
index 611b6d724e1..0dcd4cae2fa 100644
--- a/include/configs/aristainetos2.h
+++ b/include/configs/aristainetos2.h
@@ -26,7 +26,6 @@
#include "mx6_common.h"
-#define CONFIG_MMCROOT "/dev/mmcblk0p1"
/* MMC Configs */
#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR
@@ -183,7 +182,7 @@
"${pubkey}\0" \
"mainRargs=setenv bootargs console=${console},${baudrate} " \
"rescue_sysnum=${rescue_sysnum} root=${emmcroot}
rootfstype=ext4\0" \
- "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
+ "mmcroot=/dev/mmcblk0p1 rootwait rw\0" \
"mmcargs=setenv bootargs console=${console},${baudrate} " \
"root=${mmcroot}\0" \
"mmcRargs=setenv bootargs console=${console},${baudrate} " \
diff --git a/include/configs/capricorn-common.h
b/include/configs/capricorn-common.h
index 58d7a3a8ce2..08534cd1a30 100644
--- a/include/configs/capricorn-common.h
+++ b/include/configs/capricorn-common.h
@@ -109,7 +109,6 @@
#define CONFIG_SYS_INIT_SP_ADDR0x8020
/* On CCP board, USDHC1 is for eMMC */
-#define CONFIG_MMCROOT "/dev/mmcblk0p2" /* eMMC */
#define CONFIG_SYS_SDRAM_BASE 0x8000
#define PHYS_SDRAM_1 0x8000
diff --git a/include/configs/cgtqmx8.h b/include/configs/cgtqmx8.h
index bd5c072382a..4b4694ec071 100644
--- a/include/configs/cgtqmx8.h
+++ b/include/configs/cgtqmx8.h
@@ -78,7 +78,7 @@
"fdt_file=imx8qm-cgt-qmx8.dtb\0" \
"mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
"mmcpart=1\0" \
- "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
+ "mmcroot=/dev/mmcblk1p2 rootwait rw\0" \
"mmcautodetect=yes\0" \
"mmcargs=setenv bootargs console=${console},${baudrate} root=${mmcroot}
earlycon\0 " \
"loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr}
${script};\0" \
@@ -122,7 +122,6 @@
#define CONFIG_SYS_INIT_SP_ADDR0x8020
-#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */
#define CONFIG_SYS_FSL_USDHC_NUM 3
#define CONFIG_SYS_SDRAM_BASE 0x8000
diff --git a/include/configs/cl-som-imx7.h b/include/configs/cl-som-imx7.h
index 8af80f58f8e..4b494d8aeef 100644
--- a/include/configs/cl-som-imx7.h
+++ b/include/configs/cl-som-imx7.h
@@ -104,7 +104,6 @@
#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR
#define CONFIG_SYS_FSL_USDHC_NUM 2
-#define CONFIG_MMCROOT "/dev/mmcblk0p2" /* USDHC1 */
#endif
/* USB Configs */
diff --git a/include/configs/imx7-cm.h b/include/configs/imx7-cm.h
index 46ca1c58145..2d9f8bb510b 100644
--- a/include/configs/imx7-cm.h
+++ b/include/configs/imx7-cm.h
@@ -31,7 +31,7 @@
"fdt_addr=0x8300\0" \
"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
"mmcpart=1\0" \
- "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
+ "mmcroot=/dev/mmcblk0p2 rootwait rw\0" \
"mmcargs=setenv bootargs console=${console},${baudrate} " \
"root=${mmcroot}\0" \
"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr}
${image}\0" \
@@ -83,7 +83,6 @@
[PATCH V2 09/12] configs: phycore_imx8mm/p: drop unused SDHC macro
From: Peng Fan With SPL_DM_MMC and DM_MMC, the two macros not needed, drop it. CONFIG_SYS_FSL_USDHC_NUM CONFIG_SYS_FSL_ESDHC_ADDR Reviewed-by: Fabio Estevam Acked-By: Teresa Remmet Signed-off-by: Peng Fan --- include/configs/phycore_imx8mm.h | 4 include/configs/phycore_imx8mp.h | 4 2 files changed, 8 deletions(-) diff --git a/include/configs/phycore_imx8mm.h b/include/configs/phycore_imx8mm.h index 7438d0a4647..528cda0dbe3 100644 --- a/include/configs/phycore_imx8mm.h +++ b/include/configs/phycore_imx8mm.h @@ -92,8 +92,4 @@ #define CONFIG_SYS_MAXARGS 64 #define CONFIG_SYS_BARGSIZECONFIG_SYS_CBSIZE -/* USDHC */ -#define CONFIG_SYS_FSL_USDHC_NUM 2 -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 - #endif /* __PHYCORE_IMX8MM_H */ diff --git a/include/configs/phycore_imx8mp.h b/include/configs/phycore_imx8mp.h index 8c5ffeef544..db530965a2a 100644 --- a/include/configs/phycore_imx8mp.h +++ b/include/configs/phycore_imx8mp.h @@ -92,8 +92,4 @@ #define CONFIG_SYS_MAXARGS 64 #define CONFIG_SYS_BARGSIZECONFIG_SYS_CBSIZE -/* USDHC */ -#define CONFIG_SYS_FSL_USDHC_NUM 2 -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 - #endif /* __PHYCORE_IMX8MP_H */ -- 2.35.1
[PATCH V2 08/12] configs: imx8mm/n_venice: drop unused SDHC macro
From: Peng Fan With SPL_DM_MMC and DM_MMC, the two macros not needed, drop it. CONFIG_SYS_FSL_USDHC_NUM CONFIG_SYS_FSL_ESDHC_ADDR Reviewed-by: Fabio Estevam Acked-By: Tim Harvey Signed-off-by: Peng Fan --- include/configs/imx8mm_venice.h | 4 include/configs/imx8mn_venice.h | 3 --- 2 files changed, 7 deletions(-) diff --git a/include/configs/imx8mm_venice.h b/include/configs/imx8mm_venice.h index eee59a4ca57..70c743559f0 100644 --- a/include/configs/imx8mm_venice.h +++ b/include/configs/imx8mm_venice.h @@ -108,10 +108,6 @@ #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ sizeof(CONFIG_SYS_PROMPT) + 16) -/* USDHC */ -#define CONFIG_SYS_FSL_USDHC_NUM 2 -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 - /* FEC */ #define CONFIG_FEC_MXC_PHYADDR 0 #define FEC_QUIRK_ENET_MAC diff --git a/include/configs/imx8mn_venice.h b/include/configs/imx8mn_venice.h index d977d326520..b96af29e5d6 100644 --- a/include/configs/imx8mn_venice.h +++ b/include/configs/imx8mn_venice.h @@ -104,9 +104,6 @@ #define CONFIG_SYS_BARGSIZECONFIG_SYS_CBSIZE #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ sizeof(CONFIG_SYS_PROMPT) + 16) -/* USDHC */ -#define CONFIG_SYS_FSL_USDHC_NUM 2 -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 /* FEC */ #define CONFIG_FEC_MXC_PHYADDR 0 -- 2.35.1
[PATCH V2 07/12] configs: verdin-imx8m: drop unused SDHC macro
From: Peng Fan With SPL_DM_MMC and DM_MMC, the two macros not needed, drop it. CONFIG_SYS_FSL_USDHC_NUM CONFIG_SYS_FSL_ESDHC_ADDR Reviewed-by: Fabio Estevam Signed-off-by: Peng Fan --- include/configs/verdin-imx8mm.h | 3 --- include/configs/verdin-imx8mp.h | 4 2 files changed, 7 deletions(-) diff --git a/include/configs/verdin-imx8mm.h b/include/configs/verdin-imx8mm.h index 6c5b190dd95..4ccae42d669 100644 --- a/include/configs/verdin-imx8mm.h +++ b/include/configs/verdin-imx8mm.h @@ -97,9 +97,6 @@ #define CONFIG_SYS_BARGSIZECONFIG_SYS_CBSIZE #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ sizeof(CONFIG_SYS_PROMPT) + 16) -/* USDHC */ -#define CONFIG_SYS_FSL_USDHC_NUM 2 -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 /* ENET */ #define CONFIG_FEC_MXC_PHYADDR 7 diff --git a/include/configs/verdin-imx8mp.h b/include/configs/verdin-imx8mp.h index 9e29dc19033..eb2bd867edb 100644 --- a/include/configs/verdin-imx8mp.h +++ b/include/configs/verdin-imx8mp.h @@ -116,8 +116,4 @@ #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ sizeof(CONFIG_SYS_PROMPT) + 16) -/* USDHC */ -#define CONFIG_SYS_FSL_USDHC_NUM 2 -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 - #endif /* __VERDIN_IMX8MP_H */ -- 2.35.1
[PATCH V2 06/12] configs: imx8qm/qxp_evk: drop unused SDHC macro
From: Peng Fan With SPL_DM_MMC and DM_MMC, the two macros not needed, drop it. CONFIG_SYS_FSL_USDHC_NUM CONFIG_SYS_FSL_ESDHC_ADDR Reviewed-by: Fabio Estevam Signed-off-by: Peng Fan --- include/configs/imx8qm_mek.h | 5 - include/configs/imx8qxp_mek.h | 5 - 2 files changed, 10 deletions(-) diff --git a/include/configs/imx8qm_mek.h b/include/configs/imx8qm_mek.h index 0fe38e61c4b..8a269225778 100644 --- a/include/configs/imx8qm_mek.h +++ b/include/configs/imx8qm_mek.h @@ -29,10 +29,6 @@ #define CONFIG_SPL_ABORT_ON_RAW_IMAGE #endif -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 -#define USDHC1_BASE_ADDR0x5B01 -#define USDHC2_BASE_ADDR0x5B02 - #ifdef CONFIG_AHAB_BOOT #define AHAB_ENV "sec_boot=yes\0" #else @@ -122,7 +118,6 @@ /* On LPDDR4 board, USDHC1 is for eMMC, USDHC2 is for SD on CPU board */ #define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ -#define CONFIG_SYS_FSL_USDHC_NUM 2 #define CONFIG_SYS_SDRAM_BASE 0x8000 #define PHYS_SDRAM_1 0x8000 diff --git a/include/configs/imx8qxp_mek.h b/include/configs/imx8qxp_mek.h index beb35c93435..01577932884 100644 --- a/include/configs/imx8qxp_mek.h +++ b/include/configs/imx8qxp_mek.h @@ -27,10 +27,6 @@ #define CONFIG_SPL_ABORT_ON_RAW_IMAGE #endif -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 -#define USDHC1_BASE_ADDR0x5B01 -#define USDHC2_BASE_ADDR0x5B02 - #ifdef CONFIG_AHAB_BOOT #define AHAB_ENV "sec_boot=yes\0" #else @@ -120,7 +116,6 @@ /* On LPDDR4 board, USDHC1 is for eMMC, USDHC2 is for SD on CPU board */ #define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ -#define CONFIG_SYS_FSL_USDHC_NUM 2 #define CONFIG_SYS_SDRAM_BASE 0x8000 #define PHYS_SDRAM_1 0x8000 -- 2.35.1
[PATCH V2 05/12] configs: mx7dsabresd: drop unused SDHC macro
From: Peng Fan With SPL_DM_MMC and DM_MMC, the two macros not needed, drop it. CONFIG_SYS_FSL_USDHC_NUM CONFIG_SYS_FSL_ESDHC_ADDR Reviewed-by: Fabio Estevam Signed-off-by: Peng Fan --- include/configs/mx7dsabresd.h | 9 - 1 file changed, 9 deletions(-) diff --git a/include/configs/mx7dsabresd.h b/include/configs/mx7dsabresd.h index d411b1a3866..aaad232f0e4 100644 --- a/include/configs/mx7dsabresd.h +++ b/include/configs/mx7dsabresd.h @@ -14,9 +14,6 @@ #define CONFIG_MXC_UART_BASEUART1_IPS_BASE_ADDR -/* MMC Config*/ -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 - #ifdef CONFIG_IMX_BOOTAUX /* Set to QSPI1 A flash at default */ #define CONFIG_SYS_AUXCORE_BOOTDATA 0x6000 @@ -111,12 +108,6 @@ /* DMA stuff, needed for GPMI/MXS NAND support */ #endif -#ifdef CONFIG_NAND_MXS -#define CONFIG_SYS_FSL_USDHC_NUM 1 -#else -#define CONFIG_SYS_FSL_USDHC_NUM 2 -#endif - /* USB Configs */ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -- 2.35.1
[PATCH V2 04/12] configs: mx6sxsabresd: drop CONFIG_SYS_FSL_USDHC_NUM
From: Peng Fan With DM_MMC, CONFIG_SYS_FSL_USDHC_NUM is not needed. Reviewed-by: Fabio Estevam Signed-off-by: Peng Fan --- include/configs/mx6sxsabresd.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/include/configs/mx6sxsabresd.h b/include/configs/mx6sxsabresd.h index b679d13dc04..2552fc0222e 100644 --- a/include/configs/mx6sxsabresd.h +++ b/include/configs/mx6sxsabresd.h @@ -149,6 +149,4 @@ #endif #endif -#define CONFIG_SYS_FSL_USDHC_NUM 3 - #endif /* __CONFIG_H */ -- 2.35.1
[PATCH V2 03/12] configs: imx8mn_evk: drop unused SDHC macro
From: Peng Fan With SPL_DM_MMC and DM_MMC, the two macros not needed, drop it. #define CONFIG_SYS_FSL_USDHC_NUM 2 #define CONFIG_SYS_FSL_ESDHC_ADDR 0 Reviewed-by: Fabio Estevam Signed-off-by: Peng Fan --- include/configs/imx8mn_evk.h | 5 - 1 file changed, 5 deletions(-) diff --git a/include/configs/imx8mn_evk.h b/include/configs/imx8mn_evk.h index 142fc3e4fff..f969314d6b2 100644 --- a/include/configs/imx8mn_evk.h +++ b/include/configs/imx8mn_evk.h @@ -77,9 +77,4 @@ #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ sizeof(CONFIG_SYS_PROMPT) + 16) -/* USDHC */ - -#define CONFIG_SYS_FSL_USDHC_NUM 2 -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 - #endif -- 2.35.1
[PATCH V2 02/12] configs: imx8mp_evk: drop unused SDHC macro
From: Peng Fan With SPL_DM_MMC and DM_MMC, the two macros not needed, drop it. #define CONFIG_SYS_FSL_USDHC_NUM 2 #define CONFIG_SYS_FSL_ESDHC_ADDR 0 Reviewed-by: Fabio Estevam Signed-off-by: Peng Fan --- include/configs/imx8mp_evk.h | 3 --- 1 file changed, 3 deletions(-) diff --git a/include/configs/imx8mp_evk.h b/include/configs/imx8mp_evk.h index 5b185cf1de2..35fc27bb370 100644 --- a/include/configs/imx8mp_evk.h +++ b/include/configs/imx8mp_evk.h @@ -90,7 +90,4 @@ #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_FSL_USDHC_NUM 2 -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 - #endif -- 2.35.1
[PATCH V2 01/12] configs: imx8mm_evk: drop unused SDHC macro
From: Peng Fan With SPL_DM_MMC and DM_MMC, the two macros not needed, drop it. #define CONFIG_SYS_FSL_USDHC_NUM 2 #define CONFIG_SYS_FSL_ESDHC_ADDR 0 Reviewed-by: Fabio Estevam Signed-off-by: Peng Fan --- include/configs/imx8mm_evk.h | 5 - 1 file changed, 5 deletions(-) diff --git a/include/configs/imx8mm_evk.h b/include/configs/imx8mm_evk.h index 23467f599d6..f4b6353ea85 100644 --- a/include/configs/imx8mm_evk.h +++ b/include/configs/imx8mm_evk.h @@ -78,11 +78,6 @@ #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ sizeof(CONFIG_SYS_PROMPT) + 16) -/* USDHC */ - -#define CONFIG_SYS_FSL_USDHC_NUM 2 -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 - #define CONFIG_FEC_MXC_PHYADDR 0 #define FEC_QUIRK_ENET_MAC -- 2.35.1
[PATCH V2 00/12] configs: clean up SDHC marco and MMCROOT
From: Peng Fan V2: Rebase to resolve conflicts Add R-b/A-b For platforms with DM_MMC and SPL_DM_MMC, the SDHC macros are not needed. CONFIG_MMCROOT could be actually dropped. Drop IMX_FEC_BASE for boards that not use it Tom, Stefano this patches changes lots of files, not only imx, to avoid conflict, Tom would you directly pick up if no issues? Peng Fan (12): configs: imx8mm_evk: drop unused SDHC macro configs: imx8mp_evk: drop unused SDHC macro configs: imx8mn_evk: drop unused SDHC macro configs: mx6sxsabresd: drop CONFIG_SYS_FSL_USDHC_NUM configs: mx7dsabresd: drop unused SDHC macro configs: imx8qm/qxp_evk: drop unused SDHC macro configs: verdin-imx8m: drop unused SDHC macro configs: imx8mm/n_venice: drop unused SDHC macro configs: phycore_imx8mm/p: drop unused SDHC macro configs: drop CONFIG_MMCROOT scripts: config_whitelist: drop CONFIG_MMCROOT configs: imx: drop IMX_FEC_BASE include/configs/apalis-imx8x.h | 1 - include/configs/aristainetos2.h | 4 +--- include/configs/capricorn-common.h | 1 - include/configs/cgtqmx8.h| 3 +-- include/configs/cl-som-imx7.h| 1 - include/configs/cm_fx6.h | 1 - include/configs/colibri-imx6ull.h| 1 - include/configs/dh_imx6.h| 1 - include/configs/imx7-cm.h| 3 +-- include/configs/imx8mm-cl-iot-gate.h | 3 +-- include/configs/imx8mm_evk.h | 8 +--- include/configs/imx8mm_venice.h | 4 include/configs/imx8mn_evk.h | 8 +--- include/configs/imx8mn_venice.h | 3 --- include/configs/imx8mp_evk.h | 6 +- include/configs/imx8mp_rsb3720.h | 3 +-- include/configs/imx8mq_cm.h | 3 +-- include/configs/imx8mq_evk.h | 3 +-- include/configs/imx8mq_phanbell.h| 3 +-- include/configs/imx8qm_mek.h | 8 +--- include/configs/imx8qm_rom7720.h | 3 +-- include/configs/imx8qxp_mek.h| 8 +--- include/configs/imx8ulp_evk.h| 3 +-- include/configs/liteboard.h | 4 +--- include/configs/m53menlo.h | 1 - include/configs/mccmon6.h| 1 - include/configs/mx6sllevk.h | 3 +-- include/configs/mx6sxsabresd.h | 3 --- include/configs/mx6ul_14x14_evk.h| 5 + include/configs/mx6ullevk.h | 3 +-- include/configs/mx7dsabresd.h| 9 - include/configs/mx7ulp_com.h | 13 +++-- include/configs/mx7ulp_evk.h | 3 +-- include/configs/npi_imx6ull.h| 1 - include/configs/phycore_imx8mm.h | 5 - include/configs/phycore_imx8mp.h | 5 - include/configs/pico-imx6.h | 1 - include/configs/pico-imx6ul.h| 1 - include/configs/pico-imx8mq.h| 3 +-- include/configs/somlabs_visionsom_6ull.h | 1 - include/configs/tqma6.h | 1 - include/configs/verdin-imx8mm.h | 3 --- include/configs/verdin-imx8mp.h | 4 include/configs/vf610twr.h | 1 - include/configs/vining_2000.h| 1 - include/configs/xpress.h | 4 +--- scripts/config_whitelist.txt | 1 - 47 files changed, 33 insertions(+), 126 deletions(-) -- 2.35.1
Re: [PATCH v7 8/8] doc: uefi: Update the capsule update related documentation
On Thu, Apr 14, 2022 at 04:24:48PM +0530, Sughosh Ganu wrote:
> Update the capsule update functionality related documentation to
> refect the additional definitions that need to be made per platform
> for supporting the capsule update feature.
Your code seems to expect that a global variable, "update_info", exists
for each platform.
If so, please describe this requirement explicitly in a document.
-Takahiro Akashi
>
> Signed-off-by: Sughosh Ganu
> ---
>
> Changes since V6:
> * Add example for the struct efi_fw_image array and struct
> efi_capsule_update_info as suggested by Takahiro
>
> doc/develop/uefi/uefi.rst | 98 ++-
> 1 file changed, 96 insertions(+), 2 deletions(-)
>
> diff --git a/doc/develop/uefi/uefi.rst b/doc/develop/uefi/uefi.rst
> index fe337c88bd..1aea04a4e8 100644
> --- a/doc/develop/uefi/uefi.rst
> +++ b/doc/develop/uefi/uefi.rst
> @@ -312,8 +312,8 @@ Run the following command
> .. code-block:: console
>
> $ mkeficapsule \
> - --index 1 --instance 0 \
> - [--fit | --raw ] \
> + --index --instance 0 \
> + --guid \
>
>
> Performing the update
> @@ -333,9 +333,102 @@ won't be taken over across the reboot. If this is the
> case, you can skip
> this feature check with the Kconfig option (CONFIG_EFI_IGNORE_OSINDICATIONS)
> set.
>
> +A few values need to be defined in the board file for performing the
> +capsule update. These values are defined in the board file by
> +initialisation of a structure which provides information needed for
> +capsule updates. The following structures have been defined for
> +containing the image related information
> +
> +.. code-block:: c
> +
> + struct efi_fw_images {
> + efi_guid_t image_type_id;
> + u16 *fw_name;
> + u8 image_index;
> + };
> +
> + struct efi_capsule_update_info {
> + const char *dfu_string;
> + struct efi_fw_image *images;
> + };
> +
> +
> +A string is defined which is to be used for populating the
> +dfu_alt_info variable. This string is used by the function
> +set_dfu_alt_info. Instead of taking the variable from the environment,
> +the capsule update feature requires that the variable be set through
> +the function, since that is more robust. Allowing the user to change
> +the location of the firmware updates is not a very secure
> +practice. Getting this information from the firmware itself is more
> +secure, assuming the firmware has been verified by a previous stage
> +boot loader.
> +
> +The firmware images structure defines the GUID values, image index
> +values and the name of the images that are to be updated through
> +the capsule update feature. These values are to be defined as part of
> +an array. These GUID values would be used by the Firmware Management
> +Protocol(FMP) to populate the image descriptor array and also
> +displayed as part of the ESRT table. The image index values defined in
> +the array should be one greater than the dfu alt number that
> +corresponds to the firmware image. So, if the dfu alt number for an
> +image is 2, the value of image index in the fw_images array for that
> +image should be 3. The dfu alt number can be obtained by running the
> +following command::
> +
> +dfu list
> +
> +When using the FMP for FIT images, the image index value needs to be
> +set to 1.
> +
> Finally, the capsule update can be initiated by rebooting the board.
>
> +An example of setting the values in the struct efi_fw_image and
> +struct efi_capsule_update_info is shown below
> +
> +.. code-block:: c
> +
> + struct efi_fw_image fw_images[] = {
> + {
> + .image_type_id = DEVELOPERBOX_UBOOT_IMAGE_GUID,
> + .fw_name = u"DEVELOPERBOX-UBOOT",
> + .image_index = 1,
> + },
> + {
> + .image_type_id = DEVELOPERBOX_FIP_IMAGE_GUID,
> + .fw_name = u"DEVELOPERBOX-FIP",
> + .image_index = 2,
> + },
> + {
> + .image_type_id = DEVELOPERBOX_OPTEE_IMAGE_GUID,
> + .fw_name = u"DEVELOPERBOX-OPTEE",
> + .image_index = 3,
> + },
> + };
> +
> + struct efi_capsule_update_info update_info = {
> + .dfu_string = "mtd nor1=u-boot.bin raw 20 10;"
> + "fip.bin raw 18 78000;"
> + "optee.bin raw 50 10",
> + .images = fw_images,
> + };
> +
> +The platform will define a fw_images array which contains information
> +of all the firmware images that are to be updated through capsule
> +update mechanism. The dfu_string is the string that is to be set as
> +dfu_alt_info. In the example above, the image index to be set for
> +u-boot.bin binary is 0x1, for fip.bin is 0x2 and for optee.bin is 0x3.
> +
> +As an example, for generating
Re: [PATCH v3 09/12] arm: dts: rockchip: sync rk3288.dtsi from Linux
Hi Johan,
I got build fail for phycore-rk3288 after this patch:
+Error: SPL image is too large (size 0x8800 than 0x8000)
+Error: Bad parameters for image type
Thanks,
- Kever
On 2022/3/4 07:52, Johan Jonker wrote:
Sync rk3288.dtsi from Linux version 5.17.
Signed-off-by: Johan Jonker
---
Changed V3:
change reg size
Changed V2:
rename mipi_dsi0 label
move io_domains
remove hdmi_audio veyron node
change memory@0 reg size
---
arch/arm/dts/rk3288-evb.dtsi |2 +-
arch/arm/dts/rk3288-miqi.dtsi| 28 +-
arch/arm/dts/rk3288-phycore-som.dtsi | 30 +-
arch/arm/dts/rk3288-popmetal.dtsi| 30 +-
arch/arm/dts/rk3288-thermal.dtsi | 87 --
arch/arm/dts/rk3288-veyron-jerry.dts |6 -
arch/arm/dts/rk3288-veyron.dtsi | 33 +-
arch/arm/dts/rk3288.dtsi | 1367 +-
8 files changed, 970 insertions(+), 613 deletions(-)
delete mode 100644 arch/arm/dts/rk3288-thermal.dtsi
diff --git a/arch/arm/dts/rk3288-evb.dtsi b/arch/arm/dts/rk3288-evb.dtsi
index 04902c0b..72da8847 100644
--- a/arch/arm/dts/rk3288-evb.dtsi
+++ b/arch/arm/dts/rk3288-evb.dtsi
@@ -448,7 +448,7 @@
status = "okay";
};
-_dsi0 {
+_dsi {
status = "disabled";
rockchip,panel = <>;
display-timings {
diff --git a/arch/arm/dts/rk3288-miqi.dtsi b/arch/arm/dts/rk3288-miqi.dtsi
index cb80cbf2..b1c286c9 100644
--- a/arch/arm/dts/rk3288-miqi.dtsi
+++ b/arch/arm/dts/rk3288-miqi.dtsi
@@ -18,21 +18,6 @@
clock-output-names = "ext_gmac";
};
- io_domains: io-domains {
- compatible = "rockchip,rk3288-io-voltage-domain";
- rockchip,grf = <>;
-
- audio-supply = <_33>;
- flash0-supply = <_flash>;
- flash1-supply = <_lan>;
- gpio30-supply = <_io>;
- gpio1830-supply = <_io>;
- lcdc-supply = <_io>;
- sdcard-supply = <_sd>;
- wifi-supply = <_18>;
- };
-
-
leds {
compatible = "gpio-leds";
@@ -277,6 +262,19 @@
status = "okay";
};
+_domains {
+ status = "okay";
+
+ audio-supply = <_33>;
+ flash0-supply = <_flash>;
+ flash1-supply = <_lan>;
+ gpio30-supply = <_io>;
+ gpio1830-supply = <_io>;
+ lcdc-supply = <_io>;
+ sdcard-supply = <_sd>;
+ wifi-supply = <_18>;
+};
+
{
pcfg_output_high: pcfg-output-high {
output-high;
diff --git a/arch/arm/dts/rk3288-phycore-som.dtsi
b/arch/arm/dts/rk3288-phycore-som.dtsi
index 821525f7..8ac695c8 100644
--- a/arch/arm/dts/rk3288-phycore-som.dtsi
+++ b/arch/arm/dts/rk3288-phycore-som.dtsi
@@ -71,22 +71,6 @@
clock-output-names = "ext_gmac";
};
- io_domains: io_domains {
- compatible = "rockchip,rk3288-io-voltage-domain";
-
- status = "okay";
- sdcard-supply = <_io_sd>;
- flash0-supply = <_emmc_io>;
- flash1-supply = <_misc_1v8>;
- gpio1830-supply = <_3v3_io>;
- gpio30-supply = <_3v3_io>;
- bb-supply = <_3v3_io>;
- dvp-supply = <_3v3_io>;
- lcdc-supply = <_3v3_io>;
- wifi-supply = <_3v3_io>;
- audio-supply = <_3v3_io>;
- };
-
leds: user-leds {
compatible = "gpio-leds";
pinctrl-names = "default";
@@ -197,6 +181,20 @@
ddc-i2c-bus = <>;
};
+_domains {
+ status = "okay";
+ sdcard-supply = <_io_sd>;
+ flash0-supply = <_emmc_io>;
+ flash1-supply = <_misc_1v8>;
+ gpio1830-supply = <_3v3_io>;
+ gpio30-supply = <_3v3_io>;
+ bb-supply = <_3v3_io>;
+ dvp-supply = <_3v3_io>;
+ lcdc-supply = <_3v3_io>;
+ wifi-supply = <_3v3_io>;
+ audio-supply = <_3v3_io>;
+};
+
{
status = "okay";
clock-frequency = <40>;
diff --git a/arch/arm/dts/rk3288-popmetal.dtsi
b/arch/arm/dts/rk3288-popmetal.dtsi
index 63785eb5..bcd8fded 100644
--- a/arch/arm/dts/rk3288-popmetal.dtsi
+++ b/arch/arm/dts/rk3288-popmetal.dtsi
@@ -69,22 +69,6 @@
};
};
- io_domains: io-domains {
- compatible = "rockchip,rk3288-io-voltage-domain";
- rockchip,grf = <>;
-
- audio-supply = <_33>;
- bb-supply = <_io>;
- dvp-supply = <_dvp>;
- flash0-supply = <_flash>;
- flash1-supply = <_lan>;
- gpio30-supply = <_io>;
- gpio1830-supply = <_io>;
- lcdc-supply = <_io>;
- sdcard-supply = <_sd>;
- wifi-supply = <_wl>;
- };
-
ir: ir-receiver {
compatible = "gpio-ir-receiver";
gpios = < 6 GPIO_ACTIVE_LOW>;
@@ -441,6 +425,20 @@
status = "okay";
};
+_domains {
+ status = "okay";
+
Re: [PATCH v10 16/16] doc: rockchip: add rk3066 Rikomagic MK808
On 2022/4/11 09:29, Johan Jonker wrote: Add rk3066 Rikomagic MK808 to the list of mainline supported Rockchip boards. Include instructions for creating and programming images to NAND and SD card. Signed-off-by: Johan Jonker Reviewed-by: Kever Yang Thanks, - Kever --- Changed V10: add more info --- doc/board/rockchip/rockchip.rst | 111 1 file changed, 111 insertions(+) diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst index b8737dedda..7b428563a6 100644 --- a/doc/board/rockchip/rockchip.rst +++ b/doc/board/rockchip/rockchip.rst @@ -30,6 +30,8 @@ List of mainline supported Rockchip boards: * rk3036 - Rockchip Evb-RK3036 (evb-rk3036) - Kylin (kylin_rk3036) +* rk3066 + - Rikomagic MK808 (mk808) * rk3128 - Rockchip Evb-RK3128 (evb-rk3128) * rk3188 @@ -123,6 +125,13 @@ To build px30 boards: make evb-px30_defconfig make CROSS_COMPILE=aarch64-linux-gnu- +To build rk3066 boards: + +.. code-block:: bash + +make mk808_defconfig +make CROSS_COMPILE=arm-linux-gnueabihf- + To build rk3288 boards: .. code-block:: bash @@ -281,6 +290,108 @@ Note: 1. rkbin binaries are regularly updated, so it would be recommended to use the latest version. 2. 0x20 is a load address and is an option for some platforms. +3. Package the RK3066 image with U-Boot TPL/SPL on NAND +--- + +Unlike later SoC models the rk3066 BootROM doesn't have SDMMC support. +If all other boot options fail then it enters into a BootROM mode on the USB OTG port. +This method loads TPL/SPL on NAND with U-boot and kernel on SD card. + +SD Card +^^^ + +U-boot expects a GPT partition map and a boot directory structure with files on the SD card. + +.. code-block:: none + +Partition Map for MMC device 0 -- Partition Type: EFI +Part Start LBA End LBA Name + Attributes + Type GUID + Partition GUID +10x00400x1f7f"loader1" +20x40000x5fff"loader2" +30x60000x7fff"trust" +40x80000x0003"boot" +50x00040x00ed7fde"rootfs" + +Make sure boot and esp flag are set for the boot partition. +Loader1 partition is not used by RK3066. + +Boot partition: + +.. code-block:: none + +extlinux + extlinux.conf + +zImage +rk3066a-mk808.dtb + +To write a U-boot image to the SD card (assumed to be /dev/sda): + +.. code-block:: bash + +sudo dd if=u-boot-dtb.img of=/dev/sda seek=16384 +sync + +NAND + + +Bring device in BootROM mode: + +If bricked and no BootROM mode shows up then connect pin 8 and 9 of the NAND flash +with a needle while reconnecting to the USB OTG port to a PC. + +Show connected devices with: + +.. code-block:: bash + +lsusb +Bus 001 Device 004: ID 2207:300a Fuzhou Rockchip Electronics Company RK3066 in Mask ROM mode + + +Create NAND image: + +Size of SPL and TPL must be aligned to 2kb. + +Program with commands in a bash script ./flash.sh: + +.. code-block:: bash + + #!/bin/sh + + printf "RK30" > tplspl.bin + dd if=u-boot-tpl.bin >> tplspl.bin + truncate -s %2048 tplspl.bin + truncate -s %2048 u-boot-spl.bin + ../tools/boot_merger --verbose config-flash.ini + ../tools/upgrade_tool ul ./RK30xxLoader_uboot.bin + +config-flash.ini: + +.. code-block:: none + + [CHIP_NAME] + NAME=RK30 + [VERSION] + MAJOR=2 + MINOR=21 + [CODE471_OPTION] + NUM=1 + Path1=30_LPDDR2_300MHz_DD.bin + [CODE472_OPTION] + NUM=1 + Path1=rk30usbplug.bin + [LOADER_OPTION] + NUM=2 + LOADER1=FlashData + LOADER2=FlashBoot + FlashData=tplspl.bin + FlashBoot=u-boot-spl.bin + [OUTPUT] + PATH=RK30xxLoader_uboot.bin + TODO
Re: [PATCH v10 15/16] doc: rockchip: add px30/rk3326 boards and examples
On 2022/4/11 09:29, Johan Jonker wrote: There are several PX30/RK3326 boards in use without mentioning in rockchip.rst. Add boards and examples. Signed-off-by: Johan Jonker --- doc/board/rockchip/rockchip.rst | 16 Reviewed-by: Kever Yang Thanks, - Kever 1 file changed, 16 insertions(+) diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst index 7953203c75..b8737dedda 100644 --- a/doc/board/rockchip/rockchip.rst +++ b/doc/board/rockchip/rockchip.rst @@ -21,6 +21,12 @@ mainline U-Boot. List of mainline supported Rockchip boards: +* px30 + - Rockchip Evb-PX30 (evb-px30) + - Engicam PX30.Core C.TOUCH 2.0 (px30-core-ctouch2-px30) + - Engicam PX30.Core C.TOUCH 2.0 10.1 (px30-core-ctouch2-of10-px30) + - Engicam PX30.Core EDIMM2.2 Starter Kit (px30-core-edimm2.2-px30) + - Firefly Core-PX30-JD4 (firefly-px30) * rk3036 - Rockchip Evb-RK3036 (evb-rk3036) - Kylin (kylin_rk3036) @@ -46,6 +52,8 @@ List of mainline supported Rockchip boards: * rk3308 - Rockchip Evb-RK3308 (evb-rk3308) - Roc-cc-RK3308 (roc-cc-rk3308) +* rk3326 + - ODROID-GO Advance (odroid-go2) * rk3328 - Rockchip Evb-RK3328 (evb-rk3328) - Pine64 Rock64 (rock64-rk3328) @@ -107,6 +115,14 @@ U-Boot git clone --depth 1 https://source.denx.de/u-boot/u-boot.git cd u-boot +To build px30 boards: + +.. code-block:: bash + +export BL31=../arm-trusted-firmware/build/px30/release/bl31/bl31.elf +make evb-px30_defconfig +make CROSS_COMPILE=aarch64-linux-gnu- + To build rk3288 boards: .. code-block:: bash
Re: [PATCH v10 14/16] doc: rockchip: restyle rockchip.rst
On 2022/4/11 09:29, Johan Jonker wrote: With more text coming to the rockchip.rst document, give it a restyle first. Changed: sort build examples alphabetically add git clone example fix bash examples fix phrases (grammer) fix typos Signed-off-by: Johan Jonker Reviewed-by: Kever Yang Thanks, - Kever --- doc/board/rockchip/rockchip.rst | 138 1 file changed, 88 insertions(+), 50 deletions(-) diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst index a75e60b9fa..7953203c75 100644 --- a/doc/board/rockchip/rockchip.rst +++ b/doc/board/rockchip/rockchip.rst @@ -13,7 +13,7 @@ and it's usage steps. Rockchip boards --- -Rockchip is SoC solutions provider for tablets & PCs, streaming media +Rockchip is a SoC solutions provider for tablets & PCs, streaming media TV boxes, AI audio & vision, IoT hardware. A wide range of Rockchip SoCs with associated boards are supported in @@ -85,42 +85,58 @@ Building TF-A -TF-A would require to build for ARM64 Rockchip SoCs platforms. +TF-A is required when building ARM64 Rockchip SoCs images. -To build TF-A:: +To build TF-A: -git clone https://github.com/ARM-software/arm-trusted-firmware.git +.. code-block:: bash + +git clone --depth 1 https://github.com/ARM-software/arm-trusted-firmware.git cd arm-trusted-firmware make realclean make CROSS_COMPILE=aarch64-linux-gnu- PLAT=rk3399 +cd .. Specify the PLAT= with desired Rockchip platform to build TF-A for. U-Boot ^^ -To build rk3328 boards:: +.. code-block:: bash -export BL31=/path/to/arm-trusted-firmware/to/bl31.elf -make evb-rk3328_defconfig -make +git clone --depth 1 https://source.denx.de/u-boot/u-boot.git +cd u-boot + +To build rk3288 boards: -To build rk3288 boards:: +.. code-block:: bash make evb-rk3288_defconfig -make +make CROSS_COMPILE=arm-linux-gnueabihf- + +To build rk3328 boards: + +.. code-block:: bash + +export BL31=../arm-trusted-firmware/build/rk3328/release/bl31/bl31.elf +make evb-rk3328_defconfig +make CROSS_COMPILE=aarch64-linux-gnu- + +To build rk3368 boards: -To build rk3368 boards:: +.. code-block:: bash -export BL31=/path/to/arm-trusted-firmware/to/bl31.elf +export BL31=../arm-trusted-firmware/build/rk3368/release/bl31/bl31.elf make evb-px5_defconfig -make +make CROSS_COMPILE=aarch64-linux-gnu- + +To build rk3399 boards: -To build rk3399 boards:: +.. code-block:: bash -export BL31=/path/to/arm-trusted-firmware/to/bl31.elf +export BL31=../arm-trusted-firmware/build/rk3399/release/bl31/bl31.elf make evb-rk3399_defconfig -make +make CROSS_COMPILE=aarch64-linux-gnu- Flashing @@ -131,10 +147,12 @@ Flashing SD Card ^^^ -All Rockchip platforms, except rk3128 (which doesn't use SPL) are now -supporting single boot image using binman and pad_cat. +All Rockchip platforms (except rk3128 which doesn't use SPL) are now +supporting a single boot image using binman and pad_cat. -To write an image that boots from an SD card (assumed to be /dev/sda):: +To write an image that boots from a SD card (assumed to be /dev/sda): + +.. code-block:: bash sudo dd if=u-boot-rockchip.bin of=/dev/sda seek=64 sync @@ -144,45 +162,60 @@ eMMC eMMC flash would probe on mmc0 in most of the Rockchip platforms. -Create GPT partition layout as defined in configurations:: +Create GPT partition layout as defined in $partitions: + +.. code-block:: bash mmc dev 0 gpt write mmc 0 $partitions -Connect the USB-OTG cable between host and target device. +Connect the USB-OTG cable between the host and a target device. + +Launch fastboot on the target with: -Launch fastboot at target:: +.. code-block:: bash fastboot 0 -Upon successful gadget connection,host show the USB device like:: +Upon a successful gadget connection the host shows the USB device with: + +.. code-block:: bash lsusb Bus 001 Device 020: ID 2207:330c Fuzhou Rockchip Electronics Company RK3399 in Mask ROM mode -Program the flash:: +Program the flash with: + +.. code-block:: bash sudo fastboot -i 0x2207 flash loader1 idbloader.img sudo fastboot -i 0x2207 flash loader2 u-boot.itb -Note: for Rockchip 32-bit platforms the U-Boot proper image +Note: + +For Rockchip 32-bit platforms the U-Boot proper image is u-boot-dtb.img SPI ^^^ -Generating idbloader for SPI boot would require to input a multi image -image format to mkimage tool instead of concerting (like for MMC boot). +The SPI boot method requires the generation of idbloader.img with help of the mkimage tool. + +SPL-alone SPI boot image: -SPL-alone
Re: [PATCH v10 11/16] rockchip: rk3066: add core support
On 2022/4/11 09:29, Johan Jonker wrote: Add the core architecture code for the rk3066. Signed-off-by: Johan Jonker Reviewed-by: Kever Yang Thanks, - Kever --- arch/arm/include/asm/arch-rk3066/boot0.h | 8 +++ arch/arm/include/asm/arch-rk3066/gpio.h | 8 +++ arch/arm/include/asm/arch-rk3066/timer.h | 6 ++ arch/arm/mach-rockchip/Kconfig| 23 arch/arm/mach-rockchip/Makefile | 1 + arch/arm/mach-rockchip/rk3066/Kconfig | 30 ++ arch/arm/mach-rockchip/rk3066/Makefile| 5 ++ arch/arm/mach-rockchip/rk3066/clk_rk3066.c| 33 +++ arch/arm/mach-rockchip/rk3066/rk3066.c| 49 arch/arm/mach-rockchip/rk3066/syscon_rk3066.c | 55 ++ include/configs/mk808.h | 9 +++ include/configs/rk3066_common.h | 56 +++ 12 files changed, 283 insertions(+) create mode 100644 arch/arm/include/asm/arch-rk3066/boot0.h create mode 100644 arch/arm/include/asm/arch-rk3066/gpio.h create mode 100644 arch/arm/include/asm/arch-rk3066/timer.h create mode 100644 arch/arm/mach-rockchip/rk3066/Kconfig create mode 100644 arch/arm/mach-rockchip/rk3066/Makefile create mode 100644 arch/arm/mach-rockchip/rk3066/clk_rk3066.c create mode 100644 arch/arm/mach-rockchip/rk3066/rk3066.c create mode 100644 arch/arm/mach-rockchip/rk3066/syscon_rk3066.c create mode 100644 include/configs/mk808.h create mode 100644 include/configs/rk3066_common.h diff --git a/arch/arm/include/asm/arch-rk3066/boot0.h b/arch/arm/include/asm/arch-rk3066/boot0.h new file mode 100644 index 00..28c0fb9a4c --- /dev/null +++ b/arch/arm/include/asm/arch-rk3066/boot0.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#ifndef __ASM_ARCH_BOOT0_H__ +#define __ASM_ARCH_BOOT0_H__ + +#include + +#endif diff --git a/arch/arm/include/asm/arch-rk3066/gpio.h b/arch/arm/include/asm/arch-rk3066/gpio.h new file mode 100644 index 00..a4a3b3289c --- /dev/null +++ b/arch/arm/include/asm/arch-rk3066/gpio.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#ifndef __ASM_ARCH_GPIO_H__ +#define __ASM_ARCH_GPIO_H__ + +#include + +#endif diff --git a/arch/arm/include/asm/arch-rk3066/timer.h b/arch/arm/include/asm/arch-rk3066/timer.h new file mode 100644 index 00..3bb39428cd --- /dev/null +++ b/arch/arm/include/asm/arch-rk3066/timer.h @@ -0,0 +1,6 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#ifndef __ASM_ARCH_TIMER_H__ +#define __ASM_ARCH_TIMER_H__ + +#endif diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index 811964973a..18aff5480b 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -35,6 +35,28 @@ config ROCKCHIP_RK3036 and video codec support. Peripherals include Gigabit Ethernet, USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs. +config ROCKCHIP_RK3066 + bool "Support Rockchip RK3066" + select CPU_V7A + select SPL_BOARD_INIT if SPL + select SUPPORT_SPL + select SUPPORT_TPL + select SPL + select TPL + select TPL_ROCKCHIP_BACK_TO_BROM + select TPL_ROCKCHIP_EARLYRETURN_TO_BROM + imply ROCKCHIP_COMMON_BOARD + imply SPL_ROCKCHIP_COMMON_BOARD + imply SPL_SERIAL + imply TPL_ROCKCHIP_COMMON_BOARD + imply TPL_SERIAL + help + The Rockchip RK3066 is a ARM-based SoC with a dual-core Cortex-A9 + including NEON and GPU, 512KB L2 cache, Mali-400 graphics, two + video interfaces, several memory options and video codec support. + Peripherals include Fast Ethernet, USB2 host and OTG, SDIO, I2S, + UART, SPI, I2C and PWMs. + config ROCKCHIP_RK3128 bool "Support Rockchip RK3128" select CPU_V7A @@ -405,6 +427,7 @@ config LNX_KRNL_IMG_TEXT_OFFSET_BASE source "arch/arm/mach-rockchip/px30/Kconfig" source "arch/arm/mach-rockchip/rk3036/Kconfig" +source "arch/arm/mach-rockchip/rk3066/Kconfig" source "arch/arm/mach-rockchip/rk3128/Kconfig" source "arch/arm/mach-rockchip/rk3188/Kconfig" source "arch/arm/mach-rockchip/rk322x/Kconfig" diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile index 00aef0ecee..6c1c7b8a10 100644 --- a/arch/arm/mach-rockchip/Makefile +++ b/arch/arm/mach-rockchip/Makefile @@ -34,6 +34,7 @@ obj-$(CONFIG_$(SPL_TPL_)RAM) += sdram.o obj-$(CONFIG_ROCKCHIP_PX30) += px30/ obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036/ +obj-$(CONFIG_ROCKCHIP_RK3066) += rk3066/ obj-$(CONFIG_ROCKCHIP_RK3128) += rk3128/ obj-$(CONFIG_ROCKCHIP_RK3188) += rk3188/ obj-$(CONFIG_ROCKCHIP_RK322X) += rk322x/ diff --git a/arch/arm/mach-rockchip/rk3066/Kconfig b/arch/arm/mach-rockchip/rk3066/Kconfig new file mode 100644 index 00..335f49bc55 --- /dev/null +++ b/arch/arm/mach-rockchip/rk3066/Kconfig @@ -0,0 +1,30 @@ +if ROCKCHIP_RK3066 + +config ROCKCHIP_BOOT_MODE_REG +
Re: [PATCH 5/6] net: add MV88E61xx DSA driver
On Tue, Apr 12, 2022 at 7:13 AM Vladimir Oltean wrote: > > On Tue, Mar 29, 2022 at 03:52:39PM -0700, Tim Harvey wrote: > > Add a DSA driver for the MV88E61xx compatible GbE Ethernet switches. > > > > Signed-off-by: Tim Harvey > > --- > > drivers/net/Kconfig | 7 + > > drivers/net/Makefile| 1 + > > drivers/net/mv88e61xx.c | 982 > > 3 files changed, 990 insertions(+) > > create mode 100644 drivers/net/mv88e61xx.c > > > > diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig > > index a6171a7c7ffd..fc018f5ba47f 100644 > > --- a/drivers/net/Kconfig > > +++ b/drivers/net/Kconfig > > @@ -428,6 +428,13 @@ config LPC32XX_ETH > > depends on ARCH_LPC32XX > > default y > > > > +config MV88E61XX > > + bool "Marvell MV88E61xx GbE switch DSA driver" > > + depends on DM_DSA && DM_MDIO > > + help > > + This driver implements a DSA switch driver for the MV88E61xx family > > + of GbE switches using the MDIO interface > > + > > config MVGBE > > bool "Marvell Orion5x/Kirkwood network interface support" > > depends on ARCH_KIRKWOOD || ARCH_ORION5X > > diff --git a/drivers/net/Makefile b/drivers/net/Makefile > > index a6d0c23f02d3..11ada73658e9 100644 > > --- a/drivers/net/Makefile > > +++ b/drivers/net/Makefile > > @@ -66,6 +66,7 @@ obj-$(CONFIG_MEDIATEK_ETH) += mtk_eth.o > > obj-$(CONFIG_MPC8XX_FEC) += mpc8xx_fec.o > > obj-$(CONFIG_MT7620_ETH) += mt7620-eth.o > > obj-$(CONFIG_MT7628_ETH) += mt7628-eth.o > > +obj-$(CONFIG_MV88E61XX) += mv88e61xx.o > > obj-$(CONFIG_MVGBE) += mvgbe.o > > obj-$(CONFIG_MVMDIO) += mvmdio.o > > obj-$(CONFIG_MVNETA) += mvneta.o > > diff --git a/drivers/net/mv88e61xx.c b/drivers/net/mv88e61xx.c > > new file mode 100644 > > index ..9dd7a0c7f42e > > --- /dev/null > > +++ b/drivers/net/mv88e61xx.c > > @@ -0,0 +1,982 @@ > > +// SPDX-License-Identifier: GPL-2.0+ > > +/* > > + * (C) Copyright 2022 > > + * Gateworks Corporation > > + * Tim Harvey > > + * > > + * (C) Copyright 2015 > > + * Elecsys Corporation > > + * Kevin Smith > > + * > > + * Original driver: > > + * (C) Copyright 2009 > > + * Marvell Semiconductor > > + * Prafulla Wadaskar > > + */ > > + > > +/* > > + * DSA driver for mv88e61xx ethernet switches. > > + * > > + * This driver configures the mv88e61xx for basic use as a DSA switch. > > + * > > + * This driver was adapted from drivers/net/phy/mv88e61xx and tested > > + * on the mv88e6176 via an SGMII interface. > > + */ > > + > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > + > > +#define PORT_MASK(port_count)((1 << (port_count)) - 1) > Vladimir, Thanks for the review. > Not used. > will remove > > + > > +/* Device addresses */ > > +#define DEVADDR_PHY(p) (p) > > +#define DEVADDR_SERDES 0x0F > > + > > +/* SMI indirection registers for multichip addressing mode */ > > +#define SMI_CMD_REG 0x00 > > +#define SMI_DATA_REG 0x01 > > + > > +/* Global registers */ > > +#define GLOBAL1_STATUS 0x00 > > +#define GLOBAL1_CTRL 0x04 > > +#define GLOBAL1_MON_CTRL 0x1A > > + > > +/* Global 2 registers */ > > +#define GLOBAL2_REG_PHY_CMD 0x18 > > +#define GLOBAL2_REG_PHY_DATA 0x19 > > +#define GLOBAL2_REG_SCRATCH 0x1A > > + > > +/* Port registers */ > > +#define PORT_REG_STATUS 0x00 > > +#define PORT_REG_PHYS_CTRL 0x01 > > +#define PORT_REG_SWITCH_ID 0x03 > > +#define PORT_REG_CTRL0x04 > > +#define PORT_REG_VLAN_MAP0x06 > > +#define PORT_REG_VLAN_ID 0x07 > > +#define PORT_REG_LED_CTRL0x16 > > + > > +/* Phy registers */ > > +#define PHY_REG_CTRL10x10 > > +#define PHY_REG_STATUS1 0x11 > > +#define PHY_REG_PAGE 0x16 > > + > > +/* Serdes registers */ > > +#define SERDES_REG_CTRL_10x10 > > + > > +/* Phy page numbers */ > > +#define PHY_PAGE_COPPER 0 > > +#define PHY_PAGE_SERDES 1 > > + > > +/* Register fields */ > > +#define GLOBAL1_CTRL_SWRESET BIT(15) > > + > > +#define GLOBAL1_MON_CTRL_CPUDEST_SHIFT 4 > > +#define GLOBAL1_MON_CTRL_CPUDEST_WIDTH 4 > > + > > +#define PORT_REG_STATUS_SPEED_SHIFT 8 > > +#define PORT_REG_STATUS_SPEED_10 0 > > +#define PORT_REG_STATUS_SPEED_1001 > > +#define PORT_REG_STATUS_SPEED_1000 2 > > + > > +#define PORT_REG_STATUS_CMODE_MASK 0xF > > +#define PORT_REG_STATUS_CMODE_100BASE_X 0x8 > > +#define PORT_REG_STATUS_CMODE_1000BASE_X 0x9 > > +#define PORT_REG_STATUS_CMODE_SGMII 0xa > > + > > +#define PORT_REG_PHYS_CTRL_RGMII_DELAY_RXCLK BIT(15) > > +#define PORT_REG_PHYS_CTRL_RGMII_DELAY_TXCLK BIT(14) > >
Re: Bug in p1_p2_rdb_pc? Caching-inhibited bit for initial L2 SRAM entry in TLB
+ Sinan On Wednesday 13 April 2022 11:26:33 Pali Rohár wrote: > On Tuesday 05 April 2022 10:57:37 Pali Rohár wrote: > > Hello! > > > > I suspect that there is a bug in board/freescale/p1_p2_rdb_pc/tlb.c code > > which configures TLB entry for initial L2 SRAM. > > > > When L2 is 512 kB long (e.g. on P2020) then U-Boot *unsets* MAS2_I bit > > for first half of L2 and for second half of L2 U-Boot *sets* this bit. > > > > See code: > > https://source.denx.de/u-boot/u-boot/-/blob/v2022.04/board/freescale/p1_p2_rdb_pc/tlb.c#L99-104 > > > > I do not think that one part of L2 SRAM should be configured differently > > as second part. Therefore I think that this is a bug in U-Boot code. > > > > Do you know is correct configuration of TLB entries for initial L2 SRAM? > > > > MAS2_I is Caching-inhibited bit which is described as: > > > > Caching-inhibited: > > * 0 - Accesses to this page are considered cacheable. > > * 1 - The page is considered caching-inhibited. All loads and stores to > > the page bypass the caches and are performed directly to main > > memory. A read or write to a caching-inhibited page affects only > > the memory element specified by the operation. > > Hello! I found EREF: A Programmer’s Reference Manual for Freescale Power > Architecture Processors Supports e500 core family (e500v1, e500v2, > e500mc, e5500, e6500) e200 core family document at NXP web: > > https://www.nxp.com/files-static/32bit/doc/ref_manual/EREF_RM.pdf > > And section "Cache and MMU Architecture" in part 7.3.1.2.2 Unable to > Lock Conditions (page 763) contains following information: > > If no exceptions occur and no overlocking condition exists, an attempt > to set a lock can fail if any of the following is true: > > • The target address is marked cache-inhibited, or the storage > attributes of the address uses a coherency protocol that does not > support locking > > So for me it looks like that L2 SRAM (which works at L2 with locked > cache lines) should not set MA2_I (cache-inhibited) bit. > > Any opinion? Or you do have some more information?
[PATCH] pci: fsl: Change compatible string for mpc8548 to "fsl, mpc8548-pcie"
Upstream Linux kernel uses for mpc8548-based PCIe controllers compatible
string "fsl,mpc8548-pcie". So change U-Boot fsl PCIe driver and all DTS
files to use "fsl,mpc8548-pcie" instead of "fsl,pcie-mpc8548" to be
compatible with Linux kernel.
Signed-off-by: Pali Rohár
---
arch/powerpc/dts/mpc8548-post.dtsi | 2 +-
drivers/pci/pcie_fsl.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/dts/mpc8548-post.dtsi
b/arch/powerpc/dts/mpc8548-post.dtsi
index 2206f2da9feb..97c3ce6e74d6 100644
--- a/arch/powerpc/dts/mpc8548-post.dtsi
+++ b/arch/powerpc/dts/mpc8548-post.dtsi
@@ -27,7 +27,7 @@
};
{
- compatible = "fsl,pcie-mpc8548", "fsl,pcie-fsl-qoriq";
+ compatible = "fsl,mpc8548-pcie", "fsl,pcie-fsl-qoriq";
law_trgt_if = <2>;
#address-cells = <3>;
#size-cells = <2>;
diff --git a/drivers/pci/pcie_fsl.c b/drivers/pci/pcie_fsl.c
index cc6efdd5b464..be156daf8d49 100644
--- a/drivers/pci/pcie_fsl.c
+++ b/drivers/pci/pcie_fsl.c
@@ -646,7 +646,7 @@ static struct fsl_pcie_data t2080_data = {
};
static const struct udevice_id fsl_pcie_ids[] = {
- { .compatible = "fsl,pcie-mpc8548", .data = (ulong)_p2_data },
+ { .compatible = "fsl,mpc8548-pcie", .data = (ulong)_p2_data },
{ .compatible = "fsl,pcie-p1_p2", .data = (ulong)_p2_data },
{ .compatible = "fsl,pcie-p2041", .data = (ulong)_data },
{ .compatible = "fsl,pcie-p3041", .data = (ulong)_data },
--
2.20.1
Re: USB init before using usb_serial_acm gadget?
Hi Sergey, On Thu, 14 Apr 2022 at 20:31, Sergey Nazaryev wrote: > > Hi! > > As I can see, recently [1] the implementation of USB ACM gadget has > been merged into U-boot master. I tried to use it but the problem is > that running `setenv stdout usbacm` on my board based on STM32MP157 > leads to errors below: > > STM32MP> setenv stdout usbacm > couldn't find an available UDC > g_dnl_register: failed!, error: -19 > ## Error inserting "stdout" variable, errno=22 > > After some research I've found that USB OTG controller must be > initialized somehow before we can actually start using any gadget. > For instance, on my STM32MP board `dwc2_udc_otg_probe` should be > called. My research shows that `usb_gadget_initalize` is responsible > for it; so, for this reason, there are explicit calls of > `usb_gadget_initialize` (e.g. usb_dnl_dfu [2], usb_dnl_sdp [3]) > before actual usage of any gadget. > > However, unlike all other gadgets, usb_serial_acm code and code that > uses it don't call usb_gadget_initialize at all. Okay, I understand > that usb_serial_acm shouldn't initialize USB controllers by itself, > but it's still unclear who must be responsible for it. > > So, my main question is: what's the best place for > `usb_gadget_initialize` call? Should I put it to board-specific code > (board/vendor/xxx.c) or maybe it's better to put `usb_gadget_initialize` > into new `usb` subcommand (`usb otgstart` or something like that) and > call it before `setenv stdout usbacm`? Yes, you're right. I did not catch this problem because the iMX board/platform I've tested on automatically initializes the usb controller in the right role (peripheral) based on devicetree property... but it's specific to that host driver. So I think the right place to call usb_gadget_initialize is probably before registering the acm gadget function into acm_stdio_start(). Can you try this? and submit a follow_up fix patch if working? Regards, Loic
[PATCH v3 2/2] board: gateworks: venice: add imx8mp-venice-gw740x support
The GW74xx is based on the i.MX 8M Plus SoC featuring:
- LPDDR4 DRAM
- eMMC FLASH
- Gateworks System Controller
- PCIe Gen 3.0 switch (build option)
- USB 3.0 HUB
- USB Type-C front panel connector
- GPS
- 3-axis accelerometer
- CAN bus
- 6x GbE RJ45 front-panel jacks
- 1x IMX8M FEC RGMII GbE (with Passive PoE)
- 5x IMX8M EQOS RGMII 6 port GbE Switch
(1x with 802.3af class 5 Active PoE)
- RS232/RS485/RS422 serial transceiver
- MIPI header (DSI/CSI/GPIO/PWM/I2S)
- DigI/O header (UART/GPIO/I2C/ADC)
- 802.11ac WiFi
- Bluetooth BLE
- 3x MiniPCIe sockets with PCI/USB
- 1x M.2 Socket with USB2.0, PCIe, and dual-SIM
- PMIC
- Wide range DC input supply (8V to 60V DC)
Do the following to add support for this and future imx8mp-venice boards:
- add dts
- add DRAM config
- add PMIC config
- add IMX8MP support in spl.c and venice.c
Signed-off-by: Tim Harvey
---
v3:
- rebase on v3 of dm-serial
v2
- rebase on imx/master
---
arch/arm/dts/Makefile |2 +
arch/arm/dts/imx8mp-venice-gw74xx-u-boot.dtsi | 185 ++
arch/arm/dts/imx8mp-venice-gw74xx.dts | 923 +
arch/arm/dts/imx8mp-venice-u-boot.dtsi| 74 +
arch/arm/dts/imx8mp-venice.dts| 159 ++
arch/arm/mach-imx/imx8m/Kconfig |9 +
board/gateworks/venice/Kconfig| 15 +
board/gateworks/venice/Makefile |3 +
board/gateworks/venice/eeprom.c |4 +-
.../gateworks/venice/imximage-8mp-lpddr4.cfg |9 +
board/gateworks/venice/lpddr4_timing.h|2 +
board/gateworks/venice/lpddr4_timing_imx8mp.c | 1846 +
board/gateworks/venice/spl.c | 68 +-
board/gateworks/venice/venice.c | 25 +-
configs/imx8mp_venice_defconfig | 142 ++
include/configs/imx8mp_venice.h | 109 +
16 files changed, 3565 insertions(+), 10 deletions(-)
create mode 100644 arch/arm/dts/imx8mp-venice-gw74xx-u-boot.dtsi
create mode 100644 arch/arm/dts/imx8mp-venice-gw74xx.dts
create mode 100644 arch/arm/dts/imx8mp-venice-u-boot.dtsi
create mode 100644 arch/arm/dts/imx8mp-venice.dts
create mode 100644 board/gateworks/venice/imximage-8mp-lpddr4.cfg
create mode 100644 board/gateworks/venice/lpddr4_timing_imx8mp.c
create mode 100644 configs/imx8mp_venice_defconfig
create mode 100644 include/configs/imx8mp_venice.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index df7b4addf990..99243386ff4a 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -931,6 +931,8 @@ dtb-$(CONFIG_ARCH_IMX8M) += \
imx8mq-phanbell.dtb \
imx8mp-evk.dtb \
imx8mp-phyboard-pollux-rdk.dtb \
+ imx8mp-venice.dtb \
+ imx8mp-venice-gw74xx.dtb \
imx8mp-verdin.dtb \
imx8mq-pico-pi.dtb \
imx8mq-kontron-pitx-imx8m.dtb
diff --git a/arch/arm/dts/imx8mp-venice-gw74xx-u-boot.dtsi
b/arch/arm/dts/imx8mp-venice-gw74xx-u-boot.dtsi
new file mode 100644
index ..920246d577ed
--- /dev/null
+++ b/arch/arm/dts/imx8mp-venice-gw74xx-u-boot.dtsi
@@ -0,0 +1,185 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2022 Gateworks Corporation
+ */
+
+#include "imx8mp-u-boot.dtsi"
+
+/ {
+ firmware {
+ optee {
+ compatible = "linaro,optee-tz";
+ method = "smc";
+ };
+ };
+
+ wdt-reboot {
+ compatible = "wdt-reboot";
+ u-boot,dm-spl;
+ wdt = <>;
+ };
+};
+
+ {
+ /delete-property/ assigned-clocks;
+ /delete-property/ assigned-clock-parents;
+ /delete-property/ assigned-clock-rates;
+};
+
+ {
+ reset-gpios = < 30 GPIO_ACTIVE_LOW>;
+ reset-delay-us = <1000>;
+ reset-post-delay-us = <30>;
+};
+
+ {
+ phy-reset-gpios = < 29 GPIO_ACTIVE_LOW>;
+ phy-reset-duration = <15>;
+ phy-reset-post-delay = <100>;
+};
+
+ {
+ u-boot,dm-spl;
+
+ dio0_hog {
+ gpio-hog;
+ input;
+ gpios = <9 GPIO_ACTIVE_LOW>;
+ line-name = "dio0";
+ };
+
+ dio1_hog {
+ gpio-hog;
+ input;
+ gpios = <11 GPIO_ACTIVE_LOW>;
+ line-name = "dio1";
+ };
+};
+
+ {
+ u-boot,dm-spl;
+
+ pcie1_wdis_hog {
+ gpio-hog;
+ gpios = <17 GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "pcie1_wdis#";
+ };
+
+ pcie2_wdis_hog {
+ gpio-hog;
+ gpios = <18 GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "pcie2_wdis#";
+ };
+
+ pcie3_wdis_hog {
+ gpio-hog;
+ gpios = <14 GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "pcie3_wdis#";
+ };
+};
+
+ {
+ u-boot,dm-spl;
+
+ m2_dis2_hog {
+ gpio-hog;
+
[PATCH v3 1/2] board: gateworks: venice: add additional levels for dtb name match
Gateworks produces many products from a single PCB with subloaded components. Add an additional two levels of dtb name matching so that for example a GW7400-A matches the dtb name of gw74xx.dtb Signed-off-by: Tim Harvey --- v3: no changes - rebase --- board/gateworks/venice/eeprom.c | 8 1 file changed, 8 insertions(+) diff --git a/board/gateworks/venice/eeprom.c b/board/gateworks/venice/eeprom.c index 62b8125960c7..282d55f2ae30 100644 --- a/board/gateworks/venice/eeprom.c +++ b/board/gateworks/venice/eeprom.c @@ -259,8 +259,16 @@ const char *eeprom_get_dtb_name(int level, char *buf, int sz) break; case 2: /* don't care about PCB or BOM revision */ break; + case 3: /* don't care about last digit of model */ + buf[strlen(buf) - 1] = 'x'; + break; + case 4: /* don't care about last two digits of model */ + buf[strlen(buf) - 1] = 'x'; + buf[strlen(buf) - 2] = 'x'; + break; default: return NULL; + break; } } -- 2.17.1
[PATCH v4] board: gateworks: venice: use common GSC driver
Use the common GSC driver.
This allows us to do some additional cleanup:
- rename gsc{.c,.h} to eeprom{.c.h} for clarity
- collapse eeprom_get_dev
- remove unnecessary header files and alphabatize includes
- remove unnecessary check for clock-controller dt node
Signed-off-by: Tim Harvey
---
v4: rebase on top of v3 dm-serial patch and update commit log
v3: add to commit log about removing unnecessary check for
clock-controller dt node
v2: rebase on imx/master
---
arch/arm/dts/imx8mm-venice-u-boot.dtsi | 4 +
arch/arm/dts/imx8mm-venice.dts | 7 +
arch/arm/dts/imx8mn-venice-u-boot.dtsi | 4 +
arch/arm/dts/imx8mn-venice.dts | 7 +
arch/arm/mach-imx/imx8m/Kconfig| 4 +
board/gateworks/venice/Makefile| 2 +-
board/gateworks/venice/eeprom.c| 353 +++
board/gateworks/venice/{gsc.h => eeprom.h} | 26 +-
board/gateworks/venice/gsc.c | 700 -
board/gateworks/venice/spl.c | 53 +-
board/gateworks/venice/venice.c| 27 +-
configs/imx8mn_venice_defconfig| 1 +
12 files changed, 425 insertions(+), 763 deletions(-)
create mode 100644 board/gateworks/venice/eeprom.c
rename board/gateworks/venice/{gsc.h => eeprom.h} (55%)
delete mode 100644 board/gateworks/venice/gsc.c
diff --git a/arch/arm/dts/imx8mm-venice-u-boot.dtsi
b/arch/arm/dts/imx8mm-venice-u-boot.dtsi
index 42b2903f0409..c61c6de935fb 100644
--- a/arch/arm/dts/imx8mm-venice-u-boot.dtsi
+++ b/arch/arm/dts/imx8mm-venice-u-boot.dtsi
@@ -57,6 +57,10 @@
u-boot,dm-spl;
};
+ {
+ u-boot,dm-spl;
+};
+
{
u-boot,dm-spl;
};
diff --git a/arch/arm/dts/imx8mm-venice.dts b/arch/arm/dts/imx8mm-venice.dts
index 54505a03c6fa..39b030691e53 100644
--- a/arch/arm/dts/imx8mm-venice.dts
+++ b/arch/arm/dts/imx8mm-venice.dts
@@ -27,6 +27,13 @@
pinctrl-0 = <_i2c1>;
status = "okay";
+ gsc: gsc@20 {
+ compatible = "gw,gsc";
+ reg = <0x20>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
eeprom@51 {
compatible = "atmel,24c02";
reg = <0x51>;
diff --git a/arch/arm/dts/imx8mn-venice-u-boot.dtsi
b/arch/arm/dts/imx8mn-venice-u-boot.dtsi
index 055406e77b30..4f23da356763 100644
--- a/arch/arm/dts/imx8mn-venice-u-boot.dtsi
+++ b/arch/arm/dts/imx8mn-venice-u-boot.dtsi
@@ -94,6 +94,10 @@
u-boot,dm-spl;
};
+ {
+ u-boot,dm-spl;
+};
+
{
u-boot,dm-spl;
};
diff --git a/arch/arm/dts/imx8mn-venice.dts b/arch/arm/dts/imx8mn-venice.dts
index e906a560581d..eeae225632d7 100644
--- a/arch/arm/dts/imx8mn-venice.dts
+++ b/arch/arm/dts/imx8mn-venice.dts
@@ -27,6 +27,13 @@
pinctrl-0 = <_i2c1>;
status = "okay";
+ gsc: gsc@20 {
+ compatible = "gw,gsc";
+ reg = <0x20>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
eeprom@51 {
compatible = "atmel,24c02";
reg = <0x51>;
diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig
index 55db25062a9b..1abf52611232 100644
--- a/arch/arm/mach-imx/imx8m/Kconfig
+++ b/arch/arm/mach-imx/imx8m/Kconfig
@@ -97,6 +97,8 @@ config TARGET_IMX8MM_VENICE
select IMX8MM
select SUPPORT_SPL
select IMX8M_LPDDR4
+ select GATEWORKS_SC
+ select MISC
config TARGET_KONTRON_MX8MM
bool "Kontron Electronics N80xx"
@@ -143,6 +145,8 @@ config TARGET_IMX8MN_VENICE
select IMX8MN
select SUPPORT_SPL
select IMX8M_LPDDR4
+ select GATEWORKS_SC
+ select MISC
config TARGET_IMX8MP_EVK
bool "imx8mp LPDDR4 EVK board"
diff --git a/board/gateworks/venice/Makefile b/board/gateworks/venice/Makefile
index b8b53fdc0e80..fbb716ee852d 100644
--- a/board/gateworks/venice/Makefile
+++ b/board/gateworks/venice/Makefile
@@ -4,7 +4,7 @@
# SPDX-License-Identifier: GPL-2.0+
#
-obj-y += venice.o gsc.o
+obj-y += venice.o eeprom.o
ifdef CONFIG_SPL_BUILD
obj-y += spl.o
diff --git a/board/gateworks/venice/eeprom.c b/board/gateworks/venice/eeprom.c
new file mode 100644
index ..62b8125960c7
--- /dev/null
+++ b/board/gateworks/venice/eeprom.c
@@ -0,0 +1,353 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2021 Gateworks Corporation
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+#include "eeprom.h"
+
+/* I2C */
+#define SOM_EEPROM_BUSNO 0
+#define SOM_EEPROM_ADDR0x51
+#define BASEBOARD_EEPROM_BUSNO 1
+#define BASEBOARD_EEPROM_ADDR 0x52
+
+struct venice_board_info som_info;
+struct venice_board_info base_info;
+char venice_model[32];
+u32 venice_serial;
+
+/* return a mac address from EEPROM info */
+int eeprom_getmac(int index, uint8_t *address)
+{
+ int i, j;
+ u32 maclow, machigh;
+ u64 mac;
+
+ j = 0;
+ if
Re: [PATCH 6/6] arm_ffa: introduce FF-A MM communication
Hi Abdellatif,
Can you please keep me cc'ed in future revisions?
On Tue, Mar 29, 2022 at 04:16:59PM +0100, abdellatif.elkhl...@arm.com wrote:
> From: Abdellatif El Khlifi
>
> Add MM communication support using FF-A transport
>
> FF-A MM communication allows exchanging data with StandAlonneMM
> or smm-gateway secure partitions which run in OP-TEE.
>
> An MM shared buffer and a door bell event are used to exchange
> this data.
>
> The data is used by EFI services such as GetVariable()/SetVariable()
> and copied from the communication buffer to the MM shared buffer.
>
> The secure partition is notified about availability of data in the
> MM shared buffer by an FF-A message (door bell).
>
> On such event, MM SP can read the data and updates the MM shared
> buffer with the response data.
>
> The response data is copied back to the communication buffer and
> consumed by the EFI subsystem.
What I am missing from all this is a description on how to test this and
what's needed in OP-TEE and EDK2.
Unless I am reading this wrong, there is a "new" Secure Partition that will
handle both the efi variables (along with all the EFI rules you need to update
those and the crypto checks you need for authenticated variables). But StMM
includes the hardware drivers as well. How is that handled in the SP
context?
>
> Signed-off-by: Abdellatif El Khlifi
> Signed-off-by: Gowtham Suresh Kumar
> Cc: Tom Rini
> ---
> arch/arm/cpu/armv8/cache.S| 16 ++
> arch/arm/cpu/armv8/cache_v8.c | 3 +-
> include/mm_communication.h| 4 +-
> lib/efi_loader/Kconfig| 14 +-
> lib/efi_loader/efi_variable_tee.c | 294 +-
> 5 files changed, 321 insertions(+), 10 deletions(-)
>
> diff --git a/arch/arm/cpu/armv8/cache.S b/arch/arm/cpu/armv8/cache.S
> index d1cee23437..bdbe89e0c5 100644
> --- a/arch/arm/cpu/armv8/cache.S
> +++ b/arch/arm/cpu/armv8/cache.S
> @@ -21,7 +21,11 @@
> * x1: 0 clean & invalidate, 1 invalidate only
> * x2~x9: clobbered
> */
> +#ifdef CONFIG_ARM_FFA_TRANSPORT
> +.pushsection .text.efi_runtime, "ax"
> +#else
> .pushsection .text.__asm_dcache_level, "ax"
> +#endif
> ENTRY(__asm_dcache_level)
> lsl x12, x0, #1
> msr csselr_el1, x12 /* select cache level */
> @@ -65,7 +69,11 @@ ENDPROC(__asm_dcache_level)
> *
> * flush or invalidate all data cache by SET/WAY.
> */
> +#ifdef CONFIG_ARM_FFA_TRANSPORT
> +.pushsection .text.efi_runtime, "ax"
> +#else
> .pushsection .text.__asm_dcache_all, "ax"
> +#endif
> ENTRY(__asm_dcache_all)
> mov x1, x0
> dsb sy
> @@ -109,7 +117,11 @@ ENTRY(__asm_flush_dcache_all)
> ENDPROC(__asm_flush_dcache_all)
> .popsection
>
> +#ifdef CONFIG_ARM_FFA_TRANSPORT
> +.pushsection .text.efi_runtime, "ax"
> +#else
> .pushsection .text.__asm_invalidate_dcache_all, "ax"
> +#endif
> ENTRY(__asm_invalidate_dcache_all)
> mov x0, #0x1
> b __asm_dcache_all
> @@ -182,7 +194,11 @@ ENTRY(__asm_invalidate_icache_all)
> ENDPROC(__asm_invalidate_icache_all)
> .popsection
>
> +#ifdef CONFIG_ARM_FFA_TRANSPORT
> +.pushsection .text.efi_runtime, "ax"
> +#else
> .pushsection .text.__asm_invalidate_l3_dcache, "ax"
> +#endif
> WEAK(__asm_invalidate_l3_dcache)
> mov x0, #0 /* return status as success */
> ret
> diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c
> index 3de18c7675..187a4497a7 100644
> --- a/arch/arm/cpu/armv8/cache_v8.c
> +++ b/arch/arm/cpu/armv8/cache_v8.c
> @@ -9,6 +9,7 @@
>
> #include
> #include
> +#include
> #include
> #include
> #include
> @@ -425,7 +426,7 @@ __weak void mmu_setup(void)
> /*
> * Performs a invalidation of the entire data cache at all levels
> */
> -void invalidate_dcache_all(void)
> +void __efi_runtime invalidate_dcache_all(void)
> {
> __asm_invalidate_dcache_all();
> __asm_invalidate_l3_dcache();
> diff --git a/include/mm_communication.h b/include/mm_communication.h
> index e65fbde60d..bb99190956 100644
> --- a/include/mm_communication.h
> +++ b/include/mm_communication.h
> @@ -123,7 +123,7 @@ struct __packed efi_mm_communicate_header {
> *
> * Defined in EDK2 as SMM_VARIABLE_COMMUNICATE_HEADER.
> */
> -struct smm_variable_communicate_header {
> +struct __packed smm_variable_communicate_header {
Why is this converted to packed?
> efi_uintn_t function;
> efi_status_t ret_status;
> u8 data[];
> @@ -145,7 +145,7 @@ struct smm_variable_communicate_header {
> * Defined in EDK2 as SMM_VARIABLE_COMMUNICATE_ACCESS_VARIABLE.
> *
> */
> -struct smm_variable_access {
> +struct __packed smm_variable_access {
Ditto
> efi_guid_t guid;
> efi_uintn_t data_size;
> efi_uintn_t name_size;
> diff --git a/lib/efi_loader/Kconfig b/lib/efi_loader/Kconfig
> index 28657f50c9..0d69133595 100644
> --- a/lib/efi_loader/Kconfig
> +++ b/lib/efi_loader/Kconfig
> @@ -55,13 +55,23 @@ config
Re: [PATCH] sandbox: Increase default SYS_MALLOC_LEN
Hi Tom,
On Thu, 14 Apr 2022 at 09:36, Tom Rini wrote:
>
> Increase the malloc pool on sandbox in order to avoid spurious errors
> such as:
> ___ test_ut[ut_dm_dm_test_video_comp_bmp32]
>
> test/py/tests/test_ut.py:43: in test_ut
> assert output.endswith('Failures: 0')
> E AssertionError: assert False
> E+ where False = 0x7f5de85efb20>('Failures: 0')
> E+where =
> 'Test: dm_test_video_comp_bmp32: video.c\r\r\nSDL renderer does not
> exist\r\r\ntest/dm/video.c:86,
> compress_frame_buff..._test_video_comp_bmp32(): 2024 ==
> compress_frame_buffer(uts, dev): Expected 0x7e8 (2024), got 0x1
> (1)\r\r\nFailures: 2'.endswith
>
> Cc: Simon Glass
> Cc: Ramon Fried
> Signed-off-by: Tom Rini
> ---
> Kconfig| 1 +
> configs/sandbox64_defconfig| 1 -
> configs/sandbox_defconfig | 1 -
> configs/sandbox_flattree_defconfig | 1 -
> configs/sandbox_noinst_defconfig | 1 -
> configs/sandbox_spl_defconfig | 1 -
> 6 files changed, 1 insertion(+), 5 deletions(-)
This indicates a memory leak. The test system is supposed to detect
memory leaks but it seems not in this case. So this seems good as a
workaround for now.
Reviewed-by: Simon Glass
Regards,
Simon
>
> diff --git a/Kconfig b/Kconfig
> index 0ee3068b9a66..b45e60a75b93 100644
> --- a/Kconfig
> +++ b/Kconfig
> @@ -263,6 +263,7 @@ config SYS_MALLOC_F_LEN
>
> config SYS_MALLOC_LEN
> hex "Define memory for Dynamic allocation"
> + default 0x400 if SANDBOX
> default 0x200 if ARCH_ROCKCHIP || ARCH_OMAP2PLUS || ARCH_MESON
> default 0x20 if ARCH_BMIPS || X86
> default 0x12 if MACH_SUNIV
> diff --git a/configs/sandbox64_defconfig b/configs/sandbox64_defconfig
> index 88f9ecbb7fce..a13fa2e2c517 100644
> --- a/configs/sandbox64_defconfig
> +++ b/configs/sandbox64_defconfig
> @@ -1,5 +1,4 @@
> CONFIG_SYS_TEXT_BASE=0
> -CONFIG_SYS_MALLOC_LEN=0x200
> CONFIG_NR_DRAM_BANKS=1
> CONFIG_ENV_SIZE=0x2000
> CONFIG_DEFAULT_DEVICE_TREE="sandbox64"
> diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig
> index cb8d590eb642..4d3e4f317fca 100644
> --- a/configs/sandbox_defconfig
> +++ b/configs/sandbox_defconfig
> @@ -1,5 +1,4 @@
> CONFIG_SYS_TEXT_BASE=0
> -CONFIG_SYS_MALLOC_LEN=0x200
> CONFIG_NR_DRAM_BANKS=1
> CONFIG_ENV_SIZE=0x2000
> CONFIG_DEFAULT_DEVICE_TREE="sandbox"
> diff --git a/configs/sandbox_flattree_defconfig
> b/configs/sandbox_flattree_defconfig
> index 24b272068a19..d799f7ddcad3 100644
> --- a/configs/sandbox_flattree_defconfig
> +++ b/configs/sandbox_flattree_defconfig
> @@ -1,5 +1,4 @@
> CONFIG_SYS_TEXT_BASE=0
> -CONFIG_SYS_MALLOC_LEN=0x200
> CONFIG_NR_DRAM_BANKS=1
> CONFIG_ENV_SIZE=0x2000
> CONFIG_DEFAULT_DEVICE_TREE="sandbox"
> diff --git a/configs/sandbox_noinst_defconfig
> b/configs/sandbox_noinst_defconfig
> index 9eefe4f1051c..c9430da0f09e 100644
> --- a/configs/sandbox_noinst_defconfig
> +++ b/configs/sandbox_noinst_defconfig
> @@ -1,5 +1,4 @@
> CONFIG_SYS_TEXT_BASE=0x20
> -CONFIG_SYS_MALLOC_LEN=0x200
> CONFIG_SPL_GPIO=y
> CONFIG_SPL_LIBCOMMON_SUPPORT=y
> CONFIG_SPL_LIBGENERIC_SUPPORT=y
> diff --git a/configs/sandbox_spl_defconfig b/configs/sandbox_spl_defconfig
> index 0092fea76ba7..13a76e89ea52 100644
> --- a/configs/sandbox_spl_defconfig
> +++ b/configs/sandbox_spl_defconfig
> @@ -1,5 +1,4 @@
> CONFIG_SYS_TEXT_BASE=0x20
> -CONFIG_SYS_MALLOC_LEN=0x200
> CONFIG_SPL_GPIO=y
> CONFIG_SPL_LIBCOMMON_SUPPORT=y
> CONFIG_SPL_LIBGENERIC_SUPPORT=y
> --
> 2.25.1
>
USB init before using usb_serial_acm gadget?
Hi! As I can see, recently [1] the implementation of USB ACM gadget has been merged into U-boot master. I tried to use it but the problem is that running `setenv stdout usbacm` on my board based on STM32MP157 leads to errors below: STM32MP> setenv stdout usbacm couldn't find an available UDC g_dnl_register: failed!, error: -19 ## Error inserting "stdout" variable, errno=22 After some research I've found that USB OTG controller must be initialized somehow before we can actually start using any gadget. For instance, on my STM32MP board `dwc2_udc_otg_probe` should be called. My research shows that `usb_gadget_initalize` is responsible for it; so, for this reason, there are explicit calls of `usb_gadget_initialize` (e.g. usb_dnl_dfu [2], usb_dnl_sdp [3]) before actual usage of any gadget. However, unlike all other gadgets, usb_serial_acm code and code that uses it don't call usb_gadget_initialize at all. Okay, I understand that usb_serial_acm shouldn't initialize USB controllers by itself, but it's still unclear who must be responsible for it. So, my main question is: what's the best place for `usb_gadget_initialize` call? Should I put it to board-specific code (board/vendor/xxx.c) or maybe it's better to put `usb_gadget_initialize` into new `usb` subcommand (`usb otgstart` or something like that) and call it before `setenv stdout usbacm`? Thank you in advance, Sergey [1]: https://source.denx.de/u-boot/u-boot/-/commit/fc2b399ac03b91339a1cb1bfd4d1a9ca87fe95c6 [2]: https://source.denx.de/u-boot/u-boot/-/blob/master/common/dfu.c#L28 [3]: https://source.denx.de/u-boot/u-boot/-/blob/master/cmd/usb_gadget_sdp.c#L24
Re: [PATCH v3] board: gateworks: venice: enable DM_SERIAL
On Thu, Apr 14, 2022 at 1:34 PM Tim Harvey wrote:
>
> On Thu, Apr 14, 2022 at 11:02 AM Michael Nazzareno Trimarchi
> wrote:
> >
> > HI Tim
> >
> > On Thu, Apr 14, 2022 at 7:53 PM Tim Harvey wrote:
> > >
> > > Enable DM_SERIAL for both U_Boot and the SPL. The uart2 and its pinmux
> > > are already marked with u-boot,dm-spl but we need to move the call to
> > > preloader_console_init() after spl_early_init() to avoid a board hang
> > > as dm can't be used until after spl_early_init().
> > >
> > > Remove the manual config of the UART pinmux now that it is no longer
> > > needed.
> > >
> > > Signed-off-by: Tim Harvey
> > > Cc: Michael Nazzareno Trimarchi
> > > ---
> > > v3: enable DM_SERIAL for SPL as well per Michael's suggestion
> > > v2: rebase on imx/master
> > > ---
> > > board/gateworks/venice/spl.c| 17 ++---
> > > configs/imx8mm_venice_defconfig | 1 +
> > > configs/imx8mn_venice_defconfig | 1 +
> > > 3 files changed, 4 insertions(+), 15 deletions(-)
> > >
> > > diff --git a/board/gateworks/venice/spl.c b/board/gateworks/venice/spl.c
> > > index b56e1b607d58..59a6a29f70d8 100644
> > > --- a/board/gateworks/venice/spl.c
> > > +++ b/board/gateworks/venice/spl.c
> > > @@ -87,25 +87,14 @@ static void spl_dram_init(int size)
> > > ddr_init(dram_timing);
> > > }
> > >
> > > -#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
> > > #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE |
> > > PAD_CTL_PE)
> > >
> > > #ifdef CONFIG_IMX8MM
> > > -static iomux_v3_cfg_t const uart_pads[] = {
> > > - IMX8MM_PAD_UART2_RXD_UART2_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
> > > - IMX8MM_PAD_UART2_TXD_UART2_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
> > > -};
> > > -
> >
> >
> > What about the clock? I'm a bit surprised that it works without the
> > clock enabled.
> >
>
> Michael,
>
> The clock hasn't changed. Like Peng's series for converting
> imx8mm-evk, imx8mn-evk, and imx8mp-evk to DM_SERIAL, the
> board_init_f() function still calls 'init_uart_clk(1)' for UART2
> (index is 0-based UART) and that is still required. I'm not sure why
> the dm IMX driver can't do that but it doesn't currently and that
> could always be an imx8mm general cleanup later.
I think that's because the clock driver doesn't have the uart clocks
in it. I was investigating the hanging in SPL with DM_SERIAL and
noticed from the clk dump that the uart clocks were not present, so I
added them to the clock driver, but I didn't have success. I also
tried moving the preloader_console_init and switching to early spl
init instead of a regular one. Because I wasn't successful, I didn't
do anything with those patches, but I can post them to the mailing
list if there is interest.
adam
>
> Are your questions because you are trying to implement DM_SERIAL for
> one of your boards and having issues? If so, please submit your patch
> as an RFC so we can try to help.
>
> Best Regards,
>
> Tim
>
> > Michael
> >
> > > static iomux_v3_cfg_t const wdog_pads[] = {
> > > IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
> > > };
> > > #endif
> > > #ifdef CONFIG_IMX8MN
> > > -static const iomux_v3_cfg_t uart_pads[] = {
> > > - IMX8MN_PAD_UART2_RXD__UART2_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
> > > - IMX8MN_PAD_UART2_TXD__UART2_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
> > > -};
> > > -
> > > static const iomux_v3_cfg_t wdog_pads[] = {
> > > IMX8MN_PAD_GPIO1_IO02__WDOG1_WDOG_B |
> > > MUX_PAD_CTRL(WDOG_PAD_CTRL),
> > > };
> > > @@ -119,8 +108,6 @@ int board_early_init_f(void)
> > >
> > > set_wdog_reset(wdog);
> > >
> > > - imx_iomux_v3_setup_multiple_pads(uart_pads,
> > > ARRAY_SIZE(uart_pads));
> > > -
> > > return 0;
> > > }
> > >
> > > @@ -232,8 +219,6 @@ void board_init_f(ulong dummy)
> > >
> > > timer_init();
> > >
> > > - preloader_console_init();
> > > -
> > > /* Clear the BSS. */
> > > memset(__bss_start, 0, __bss_end - __bss_start);
> > >
> > > @@ -243,6 +228,8 @@ void board_init_f(ulong dummy)
> > > hang();
> > > }
> > >
> > > + preloader_console_init();
> > > +
> > > ret = uclass_get_device_by_name(UCLASS_CLK,
> > > "clock-controller@3038",
> > > );
> > > diff --git a/configs/imx8mm_venice_defconfig
> > > b/configs/imx8mm_venice_defconfig
> > > index dd61ec9b70fb..1ccbe9970a6c 100644
> > > --- a/configs/imx8mm_venice_defconfig
> > > +++ b/configs/imx8mm_venice_defconfig
> > > @@ -110,6 +110,7 @@ CONFIG_SPL_DM_PMIC_MP5416=y
> > > CONFIG_DM_REGULATOR=y
> > > CONFIG_DM_REGULATOR_FIXED=y
> > > CONFIG_DM_REGULATOR_GPIO=y
> > > +CONFIG_DM_SERIAL=y
> > > CONFIG_MXC_UART=y
> > > CONFIG_SYSRESET=y
> > > CONFIG_SPL_SYSRESET=y
> > > diff --git a/configs/imx8mn_venice_defconfig
> > > b/configs/imx8mn_venice_defconfig
> > > index c3a96a378553..ff926dac0e18 100644
> > > ---
Re: [PATCH v3] board: gateworks: venice: enable DM_SERIAL
On Thu, Apr 14, 2022 at 11:02 AM Michael Nazzareno Trimarchi
wrote:
>
> HI Tim
>
> On Thu, Apr 14, 2022 at 7:53 PM Tim Harvey wrote:
> >
> > Enable DM_SERIAL for both U_Boot and the SPL. The uart2 and its pinmux
> > are already marked with u-boot,dm-spl but we need to move the call to
> > preloader_console_init() after spl_early_init() to avoid a board hang
> > as dm can't be used until after spl_early_init().
> >
> > Remove the manual config of the UART pinmux now that it is no longer
> > needed.
> >
> > Signed-off-by: Tim Harvey
> > Cc: Michael Nazzareno Trimarchi
> > ---
> > v3: enable DM_SERIAL for SPL as well per Michael's suggestion
> > v2: rebase on imx/master
> > ---
> > board/gateworks/venice/spl.c| 17 ++---
> > configs/imx8mm_venice_defconfig | 1 +
> > configs/imx8mn_venice_defconfig | 1 +
> > 3 files changed, 4 insertions(+), 15 deletions(-)
> >
> > diff --git a/board/gateworks/venice/spl.c b/board/gateworks/venice/spl.c
> > index b56e1b607d58..59a6a29f70d8 100644
> > --- a/board/gateworks/venice/spl.c
> > +++ b/board/gateworks/venice/spl.c
> > @@ -87,25 +87,14 @@ static void spl_dram_init(int size)
> > ddr_init(dram_timing);
> > }
> >
> > -#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
> > #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE |
> > PAD_CTL_PE)
> >
> > #ifdef CONFIG_IMX8MM
> > -static iomux_v3_cfg_t const uart_pads[] = {
> > - IMX8MM_PAD_UART2_RXD_UART2_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
> > - IMX8MM_PAD_UART2_TXD_UART2_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
> > -};
> > -
>
>
> What about the clock? I'm a bit surprised that it works without the
> clock enabled.
>
Michael,
The clock hasn't changed. Like Peng's series for converting
imx8mm-evk, imx8mn-evk, and imx8mp-evk to DM_SERIAL, the
board_init_f() function still calls 'init_uart_clk(1)' for UART2
(index is 0-based UART) and that is still required. I'm not sure why
the dm IMX driver can't do that but it doesn't currently and that
could always be an imx8mm general cleanup later.
Are your questions because you are trying to implement DM_SERIAL for
one of your boards and having issues? If so, please submit your patch
as an RFC so we can try to help.
Best Regards,
Tim
> Michael
>
> > static iomux_v3_cfg_t const wdog_pads[] = {
> > IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
> > };
> > #endif
> > #ifdef CONFIG_IMX8MN
> > -static const iomux_v3_cfg_t uart_pads[] = {
> > - IMX8MN_PAD_UART2_RXD__UART2_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
> > - IMX8MN_PAD_UART2_TXD__UART2_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
> > -};
> > -
> > static const iomux_v3_cfg_t wdog_pads[] = {
> > IMX8MN_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
> > };
> > @@ -119,8 +108,6 @@ int board_early_init_f(void)
> >
> > set_wdog_reset(wdog);
> >
> > - imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
> > -
> > return 0;
> > }
> >
> > @@ -232,8 +219,6 @@ void board_init_f(ulong dummy)
> >
> > timer_init();
> >
> > - preloader_console_init();
> > -
> > /* Clear the BSS. */
> > memset(__bss_start, 0, __bss_end - __bss_start);
> >
> > @@ -243,6 +228,8 @@ void board_init_f(ulong dummy)
> > hang();
> > }
> >
> > + preloader_console_init();
> > +
> > ret = uclass_get_device_by_name(UCLASS_CLK,
> > "clock-controller@3038",
> > );
> > diff --git a/configs/imx8mm_venice_defconfig
> > b/configs/imx8mm_venice_defconfig
> > index dd61ec9b70fb..1ccbe9970a6c 100644
> > --- a/configs/imx8mm_venice_defconfig
> > +++ b/configs/imx8mm_venice_defconfig
> > @@ -110,6 +110,7 @@ CONFIG_SPL_DM_PMIC_MP5416=y
> > CONFIG_DM_REGULATOR=y
> > CONFIG_DM_REGULATOR_FIXED=y
> > CONFIG_DM_REGULATOR_GPIO=y
> > +CONFIG_DM_SERIAL=y
> > CONFIG_MXC_UART=y
> > CONFIG_SYSRESET=y
> > CONFIG_SPL_SYSRESET=y
> > diff --git a/configs/imx8mn_venice_defconfig
> > b/configs/imx8mn_venice_defconfig
> > index c3a96a378553..ff926dac0e18 100644
> > --- a/configs/imx8mn_venice_defconfig
> > +++ b/configs/imx8mn_venice_defconfig
> > @@ -108,6 +108,7 @@ CONFIG_SPL_DM_PMIC_MP5416=y
> > CONFIG_DM_REGULATOR=y
> > CONFIG_DM_REGULATOR_FIXED=y
> > CONFIG_DM_REGULATOR_GPIO=y
> > +CONFIG_DM_SERIAL=y
> > CONFIG_MXC_UART=y
> > CONFIG_SYSRESET=y
> > CONFIG_SPL_SYSRESET=y
> > --
> > 2.17.1
> >
>
>
> --
> Michael Nazzareno Trimarchi
> Co-Founder & Chief Executive Officer
> M. +39 347 913 2170
> mich...@amarulasolutions.com
> __
>
> Amarula Solutions BV
> Joop Geesinkweg 125, 1114 AB, Amsterdam, NL
> T. +31 (0)85 111 9172
> i...@amarulasolutions.com
> www.amarulasolutions.com
Re: [PATCH v3] board: gateworks: venice: enable DM_SERIAL
HI Tim
On Thu, Apr 14, 2022 at 7:53 PM Tim Harvey wrote:
>
> Enable DM_SERIAL for both U_Boot and the SPL. The uart2 and its pinmux
> are already marked with u-boot,dm-spl but we need to move the call to
> preloader_console_init() after spl_early_init() to avoid a board hang
> as dm can't be used until after spl_early_init().
>
> Remove the manual config of the UART pinmux now that it is no longer
> needed.
>
> Signed-off-by: Tim Harvey
> Cc: Michael Nazzareno Trimarchi
> ---
> v3: enable DM_SERIAL for SPL as well per Michael's suggestion
> v2: rebase on imx/master
> ---
> board/gateworks/venice/spl.c| 17 ++---
> configs/imx8mm_venice_defconfig | 1 +
> configs/imx8mn_venice_defconfig | 1 +
> 3 files changed, 4 insertions(+), 15 deletions(-)
>
> diff --git a/board/gateworks/venice/spl.c b/board/gateworks/venice/spl.c
> index b56e1b607d58..59a6a29f70d8 100644
> --- a/board/gateworks/venice/spl.c
> +++ b/board/gateworks/venice/spl.c
> @@ -87,25 +87,14 @@ static void spl_dram_init(int size)
> ddr_init(dram_timing);
> }
>
> -#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
> #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE |
> PAD_CTL_PE)
>
> #ifdef CONFIG_IMX8MM
> -static iomux_v3_cfg_t const uart_pads[] = {
> - IMX8MM_PAD_UART2_RXD_UART2_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
> - IMX8MM_PAD_UART2_TXD_UART2_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
> -};
> -
What about the clock? I'm a bit surprised that it works without the
clock enabled.
Michael
> static iomux_v3_cfg_t const wdog_pads[] = {
> IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
> };
> #endif
> #ifdef CONFIG_IMX8MN
> -static const iomux_v3_cfg_t uart_pads[] = {
> - IMX8MN_PAD_UART2_RXD__UART2_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
> - IMX8MN_PAD_UART2_TXD__UART2_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
> -};
> -
> static const iomux_v3_cfg_t wdog_pads[] = {
> IMX8MN_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
> };
> @@ -119,8 +108,6 @@ int board_early_init_f(void)
>
> set_wdog_reset(wdog);
>
> - imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
> -
> return 0;
> }
>
> @@ -232,8 +219,6 @@ void board_init_f(ulong dummy)
>
> timer_init();
>
> - preloader_console_init();
> -
> /* Clear the BSS. */
> memset(__bss_start, 0, __bss_end - __bss_start);
>
> @@ -243,6 +228,8 @@ void board_init_f(ulong dummy)
> hang();
> }
>
> + preloader_console_init();
> +
> ret = uclass_get_device_by_name(UCLASS_CLK,
> "clock-controller@3038",
> );
> diff --git a/configs/imx8mm_venice_defconfig b/configs/imx8mm_venice_defconfig
> index dd61ec9b70fb..1ccbe9970a6c 100644
> --- a/configs/imx8mm_venice_defconfig
> +++ b/configs/imx8mm_venice_defconfig
> @@ -110,6 +110,7 @@ CONFIG_SPL_DM_PMIC_MP5416=y
> CONFIG_DM_REGULATOR=y
> CONFIG_DM_REGULATOR_FIXED=y
> CONFIG_DM_REGULATOR_GPIO=y
> +CONFIG_DM_SERIAL=y
> CONFIG_MXC_UART=y
> CONFIG_SYSRESET=y
> CONFIG_SPL_SYSRESET=y
> diff --git a/configs/imx8mn_venice_defconfig b/configs/imx8mn_venice_defconfig
> index c3a96a378553..ff926dac0e18 100644
> --- a/configs/imx8mn_venice_defconfig
> +++ b/configs/imx8mn_venice_defconfig
> @@ -108,6 +108,7 @@ CONFIG_SPL_DM_PMIC_MP5416=y
> CONFIG_DM_REGULATOR=y
> CONFIG_DM_REGULATOR_FIXED=y
> CONFIG_DM_REGULATOR_GPIO=y
> +CONFIG_DM_SERIAL=y
> CONFIG_MXC_UART=y
> CONFIG_SYSRESET=y
> CONFIG_SPL_SYSRESET=y
> --
> 2.17.1
>
--
Michael Nazzareno Trimarchi
Co-Founder & Chief Executive Officer
M. +39 347 913 2170
mich...@amarulasolutions.com
__
Amarula Solutions BV
Joop Geesinkweg 125, 1114 AB, Amsterdam, NL
T. +31 (0)85 111 9172
i...@amarulasolutions.com
www.amarulasolutions.com
Re: [PATCH] ARM: imx: Fix parsing of ROM log event IDs on iMX8M
Hello Peng,
can you please check the parameter of event 0x82 internally? The AN12853
doesn't mention a parameter for ID 0x82, but we see something else coming
out of the bootrom of iMX8MN.
Best regards,
Fedor
Am Do., 14. Apr. 2022 um 18:37 Uhr schrieb :
>
> From: Fedor Ross
>
> It seems like the ROM log events for the iMX8M are not fully covered by
> AN12853 i.MX ROMs Log Events, Rev. 0, May 2020. On iMX8M the ROM event
> ID 0x82 seems to use parameter0 which stops the parsing because the end
> of list is detected too early.
>
> This patch adds ROM event ID 0x82 and skips the next word if ID 0x82 is
> parsed.
>
>
> Fixes: a5ee05cf71 ("ARM: imx: Pick correct eMMC boot partition from ROM
log")
>
> Signed-off-by: Fedor Ross
> Cc: Fabio Estevam
> Cc: Marek Vasut
> Cc: Peng Fan
> Cc: Stefano Babic
> ---
> arch/arm/mach-imx/imx8m/soc.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c
> index 8171631db1..4df57cb150 100644
> --- a/arch/arm/mach-imx/imx8m/soc.c
> +++ b/arch/arm/mach-imx/imx8m/soc.c
> @@ -677,6 +677,7 @@ int spl_mmc_emmc_boot_partition(struct mmc *mmc)
> /* Log entries with 1 parameter, skip 1 */
> case 0x80: /* Start to perform the device initialization
*/
> case 0x81: /* The boot device initialization completes */
> + case 0x82: /* Starts to execute boot device driver
pre-config */
> case 0x8f: /* The boot device initialization fails */
> case 0x90: /* Start to read data from boot device */
> case 0x91: /* Reading data from boot device completes */
> --
> 2.20.1
>
Re: [PATCH v3] board: gateworks: venice: enable DM_SERIAL
Hi Tim, On Thu, Apr 14, 2022 at 2:53 PM Tim Harvey wrote: > > Enable DM_SERIAL for both U_Boot and the SPL. The uart2 and its pinmux > are already marked with u-boot,dm-spl but we need to move the call to > preloader_console_init() after spl_early_init() to avoid a board hang > as dm can't be used until after spl_early_init(). This preloader_console_init() comment is what I was expecting when I went trough Peng's patches. It looks good now: Reviewed-by: Fabio Estevam
[PATCH v3] board: gateworks: venice: enable DM_SERIAL
Enable DM_SERIAL for both U_Boot and the SPL. The uart2 and its pinmux
are already marked with u-boot,dm-spl but we need to move the call to
preloader_console_init() after spl_early_init() to avoid a board hang
as dm can't be used until after spl_early_init().
Remove the manual config of the UART pinmux now that it is no longer
needed.
Signed-off-by: Tim Harvey
Cc: Michael Nazzareno Trimarchi
---
v3: enable DM_SERIAL for SPL as well per Michael's suggestion
v2: rebase on imx/master
---
board/gateworks/venice/spl.c| 17 ++---
configs/imx8mm_venice_defconfig | 1 +
configs/imx8mn_venice_defconfig | 1 +
3 files changed, 4 insertions(+), 15 deletions(-)
diff --git a/board/gateworks/venice/spl.c b/board/gateworks/venice/spl.c
index b56e1b607d58..59a6a29f70d8 100644
--- a/board/gateworks/venice/spl.c
+++ b/board/gateworks/venice/spl.c
@@ -87,25 +87,14 @@ static void spl_dram_init(int size)
ddr_init(dram_timing);
}
-#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
#ifdef CONFIG_IMX8MM
-static iomux_v3_cfg_t const uart_pads[] = {
- IMX8MM_PAD_UART2_RXD_UART2_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
- IMX8MM_PAD_UART2_TXD_UART2_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
-};
-
static iomux_v3_cfg_t const wdog_pads[] = {
IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
};
#endif
#ifdef CONFIG_IMX8MN
-static const iomux_v3_cfg_t uart_pads[] = {
- IMX8MN_PAD_UART2_RXD__UART2_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
- IMX8MN_PAD_UART2_TXD__UART2_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
-};
-
static const iomux_v3_cfg_t wdog_pads[] = {
IMX8MN_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
};
@@ -119,8 +108,6 @@ int board_early_init_f(void)
set_wdog_reset(wdog);
- imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
-
return 0;
}
@@ -232,8 +219,6 @@ void board_init_f(ulong dummy)
timer_init();
- preloader_console_init();
-
/* Clear the BSS. */
memset(__bss_start, 0, __bss_end - __bss_start);
@@ -243,6 +228,8 @@ void board_init_f(ulong dummy)
hang();
}
+ preloader_console_init();
+
ret = uclass_get_device_by_name(UCLASS_CLK,
"clock-controller@3038",
);
diff --git a/configs/imx8mm_venice_defconfig b/configs/imx8mm_venice_defconfig
index dd61ec9b70fb..1ccbe9970a6c 100644
--- a/configs/imx8mm_venice_defconfig
+++ b/configs/imx8mm_venice_defconfig
@@ -110,6 +110,7 @@ CONFIG_SPL_DM_PMIC_MP5416=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_SERIAL=y
CONFIG_MXC_UART=y
CONFIG_SYSRESET=y
CONFIG_SPL_SYSRESET=y
diff --git a/configs/imx8mn_venice_defconfig b/configs/imx8mn_venice_defconfig
index c3a96a378553..ff926dac0e18 100644
--- a/configs/imx8mn_venice_defconfig
+++ b/configs/imx8mn_venice_defconfig
@@ -108,6 +108,7 @@ CONFIG_SPL_DM_PMIC_MP5416=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_SERIAL=y
CONFIG_MXC_UART=y
CONFIG_SYSRESET=y
CONFIG_SPL_SYSRESET=y
--
2.17.1
Re: [PATCH v2] board: gateworks: venice: enable DM_SERIAL
On Thu, Apr 14, 2022 at 9:10 AM Tim Harvey wrote:
>
> On Wed, Apr 13, 2022 at 10:21 AM Michael Nazzareno Trimarchi
> wrote:
> >
> > Hi
> >
> > On Wed, Apr 13, 2022 at 6:09 PM Tim Harvey wrote:
> > >
> > > On Wed, Apr 13, 2022 at 8:56 AM Michael Nazzareno Trimarchi
> > > wrote:
> > > >
> > > > Hi Tim
> > > >
> > > > On Wed, Apr 13, 2022 at 5:47 PM Tim Harvey
> > > > wrote:
> > > > >
> > > > > Enable DM_SERIAL.
> > > > >
> > > > > Signed-off-by: Tim Harvey
> > > > > ---
> > > > > v2: rebase on imx/master
> > > > > ---
> > > > > configs/imx8mm_venice_defconfig | 2 ++
> > > > > configs/imx8mn_venice_defconfig | 2 ++
> > > > > 2 files changed, 4 insertions(+)
> > > > >
> > > > > diff --git a/configs/imx8mm_venice_defconfig
> > > > > b/configs/imx8mm_venice_defconfig
> > > > > index dd61ec9b70fb..09f7d8a58ca7 100644
> > > > > --- a/configs/imx8mm_venice_defconfig
> > > > > +++ b/configs/imx8mm_venice_defconfig
> > > > > @@ -110,6 +110,8 @@ CONFIG_SPL_DM_PMIC_MP5416=y
> > > > > CONFIG_DM_REGULATOR=y
> > > > > CONFIG_DM_REGULATOR_FIXED=y
> > > > > CONFIG_DM_REGULATOR_GPIO=y
> > > > > +CONFIG_DM_SERIAL=y
> > > > > +# CONFIG_SPL_DM_SERIAL is not set
> > > > > CONFIG_MXC_UART=y
> > > > > CONFIG_SYSRESET=y
> > > > > CONFIG_SPL_SYSRESET=y
> > > > > diff --git a/configs/imx8mn_venice_defconfig
> > > > > b/configs/imx8mn_venice_defconfig
> > > > > index c3a96a378553..41898da4aecf 100644
> > > > > --- a/configs/imx8mn_venice_defconfig
> > > > > +++ b/configs/imx8mn_venice_defconfig
> > > > > @@ -108,6 +108,8 @@ CONFIG_SPL_DM_PMIC_MP5416=y
> > > > > CONFIG_DM_REGULATOR=y
> > > > > CONFIG_DM_REGULATOR_FIXED=y
> > > > > CONFIG_DM_REGULATOR_GPIO=y
> > > > > +CONFIG_DM_SERIAL=y
> > > > > +# CONFIG_SPL_DM_SERIAL is not set
> > > > > CONFIG_MXC_UART=y
> > > > > CONFIG_SYSRESET=y
> > > > > CONFIG_SPL_SYSRESET=y
> > > > > --
> > > > > 2.17.1
> > > > >
> > > >
> > > > Should not select in your board kconfig?
> > > >
> > >
> > > Michael,
> > >
> > > I don't think it really matters. The other conversions to DM_SERIAL
> > > are going in defconfigs as well.
> >
> > Do we know why without # CONFIG_SPL_DM_SERIAL is not set
> >
> > board hang?
> >
>
> Michael,
>
> yes, if I also enable CONFIG_SPL_DM_SERIAL I get no serial output and
> the board hangs even if I add 'u-boot,dm-pre-proper' to
> uart2/pinctrl_uart2 nodes.
I see that Peng has a series [1] that moves imx8mn_evk, imx8mm_evk,
imx8mp_evk to DM_SERIAL and has figured out the hang.
I will re-submit the patch also enabling DM_SERIAL for SPL.
Best Regards,
Tim
[1] https://patchwork.ozlabs.org/project/uboot/list/?series=294869
>
> The requirement is to use DM_SERIAL in U-Boot, not in the SPL. I'm
> doing the same as was done for imx8mn-evk in ff1c7961d813 ("ARM: imx:
> imx8mn-evk: enable DM_SERIAL").
>
> Thus far, no ARCH_IMX8M boards have enabled CONFIG_SPL_DM_SERIAL so I
> suppose others have run into this as well but again the requirement is
> to enable CONFIG_DM_SERIAL not necessarily the SPL.
>
> Best Regards,
>
> Tim
Re: [PATCH V3 3/4] imx: imx8mn_evk: enable CONFIG_DM_SERIAL
On Thu, Apr 14, 2022 at 10:20 AM Tim Harvey wrote:
>
> On Tue, Apr 12, 2022 at 6:31 PM Peng Fan (OSS) wrote:
> >
> > From: Peng Fan
> >
> > Enable CONFIG_DM_SERIAL. uart2 and its pinmux was already
> > marked with u-boot,dm-spl.
> >
> > Signed-off-by: Peng Fan
> > ---
> > board/freescale/imx8mn_evk/spl.c | 12 ++--
> > configs/imx8mn_ddr4_evk_defconfig | 1 +
> > configs/imx8mn_evk_defconfig | 1 +
> > 3 files changed, 4 insertions(+), 10 deletions(-)
> >
> > diff --git a/board/freescale/imx8mn_evk/spl.c
> > b/board/freescale/imx8mn_evk/spl.c
> > index 03f2a56e805..8708c93fa34 100644
> > --- a/board/freescale/imx8mn_evk/spl.c
> > +++ b/board/freescale/imx8mn_evk/spl.c
> > @@ -110,14 +110,8 @@ int board_fit_config_name_match(const char *name)
> > }
> > #endif
> >
> > -#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
> > #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE |
> > PAD_CTL_PE)
> >
> > -static iomux_v3_cfg_t const uart_pads[] = {
> > - IMX8MN_PAD_UART2_RXD__UART2_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
> > - IMX8MN_PAD_UART2_TXD__UART2_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
> > -};
> > -
> > static iomux_v3_cfg_t const wdog_pads[] = {
> > IMX8MN_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
> > };
> > @@ -130,8 +124,6 @@ int board_early_init_f(void)
> >
> > set_wdog_reset(wdog);
> >
> > - imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
> > -
> > return 0;
> > }
> >
> > @@ -147,8 +139,6 @@ void board_init_f(ulong dummy)
> >
> > timer_init();
> >
> > - preloader_console_init();
> > -
> > /* Clear the BSS. */
> > memset(__bss_start, 0, __bss_end - __bss_start);
> >
> > @@ -158,6 +148,8 @@ void board_init_f(ulong dummy)
> > hang();
> > }
> >
> > + preloader_console_init();
> > +
> > enable_tzc380();
> >
> > /* DDR initialization */
> > diff --git a/configs/imx8mn_ddr4_evk_defconfig
> > b/configs/imx8mn_ddr4_evk_defconfig
> > index 917cdb5aa9d..474d9cfa4d2 100644
> > --- a/configs/imx8mn_ddr4_evk_defconfig
> > +++ b/configs/imx8mn_ddr4_evk_defconfig
> > @@ -76,6 +76,7 @@ CONFIG_PINCTRL_IMX8M=y
> > CONFIG_DM_REGULATOR=y
> > CONFIG_DM_REGULATOR_FIXED=y
> > CONFIG_DM_REGULATOR_GPIO=y
> > +CONFIG_DM_SERIAL=y
> > CONFIG_MXC_UART=y
> > CONFIG_SYSRESET=y
> > CONFIG_SPL_SYSRESET=y
> > diff --git a/configs/imx8mn_evk_defconfig b/configs/imx8mn_evk_defconfig
> > index 7749ebe537e..5bc175154ba 100644
> > --- a/configs/imx8mn_evk_defconfig
> > +++ b/configs/imx8mn_evk_defconfig
> > @@ -83,6 +83,7 @@ CONFIG_DM_REGULATOR=y
> > CONFIG_SPL_DM_REGULATOR=y
> > CONFIG_DM_REGULATOR_FIXED=y
> > CONFIG_DM_REGULATOR_GPIO=y
> > +CONFIG_DM_SERIAL=y
> > CONFIG_MXC_UART=y
> > CONFIG_SYSRESET=y
> > CONFIG_SPL_SYSRESET=y
> > --
> > 2.35.1
> >
>
> Peng,
>
> I see you've been able to get SPL DM_SERIAL to work on IMX8M. This
> patch won't apply by the way due to commit ff1c7961d813 ("ARM: imx:
> imx8mn-evk: enable DM_SERIAL") so I think you need to rebase.
>
> I have not been able to get SPL DM_SERIAL to work on IMX8MM/IMX8MN...
> it hangs my board. Is this due to moving preloader_console_init()
> perhaps? Moving it didn't work for me.
>
> Please explain the move of preloader_console_init() and please let me
> know if you have tested this on imx/master. Fabio, perhaps you can
> test?
>
Peng,
I see my mistake now... the preloader_console_init() must come after
spl_early_init().
You still need to rebase on imx/master and you should also add a
comment to the commit such as:
"move the preloader_console_init() call after spl_early_init() to
avoid board hang" or perhaps you can come up with a reason for why the
board hangs otherwise. Is it that spl_early_init() does the relocation
and we need to be after that?
Best Regards,
Tim
[PATCH] ARM: imx: Fix parsing of ROM log event IDs on iMX8M
From: Fedor Ross
It seems like the ROM log events for the iMX8M are not fully covered by
AN12853 i.MX ROMs Log Events, Rev. 0, May 2020. On iMX8M the ROM event
ID 0x82 seems to use parameter0 which stops the parsing because the end
of list is detected too early.
This patch adds ROM event ID 0x82 and skips the next word if ID 0x82 is
parsed.
Fixes: a5ee05cf71 ("ARM: imx: Pick correct eMMC boot partition from ROM log")
Signed-off-by: Fedor Ross
Cc: Fabio Estevam
Cc: Marek Vasut
Cc: Peng Fan
Cc: Stefano Babic
---
arch/arm/mach-imx/imx8m/soc.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c
index 8171631db1..4df57cb150 100644
--- a/arch/arm/mach-imx/imx8m/soc.c
+++ b/arch/arm/mach-imx/imx8m/soc.c
@@ -677,6 +677,7 @@ int spl_mmc_emmc_boot_partition(struct mmc *mmc)
/* Log entries with 1 parameter, skip 1 */
case 0x80: /* Start to perform the device initialization */
case 0x81: /* The boot device initialization completes */
+ case 0x82: /* Starts to execute boot device driver pre-config */
case 0x8f: /* The boot device initialization fails */
case 0x90: /* Start to read data from boot device */
case 0x91: /* Reading data from boot device completes */
--
2.20.1
Re: [PATCH] ram: stm32mp1: Conditionally enable ASR
On 4/14/22 18:48, Marek Vasut wrote:
On 4/14/22 18:37, Patrick DELAUNAY wrote:
Hi Marek,
Hi,
on ST platform the ASR/SSR/HSR request are already provided by the DDR
settings with pwrctl register value
it is managed in TF-A by
arm-trusted-firmware/drivers/st/ddr/stm32mp1_ddr_helpers.c
Sure, I don't use ATF and I have no intention of ever using ATF on this
platform.
enumstm32mp1_ddr_sr_mode ddr_read_sr_mode(void)
{
uint32_tpwrctl = mmio_read_32(stm32mp_ddrctrl_base() + DDRCTRL_PWRCTL);
switch(pwrctl & (DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE |
DDRCTRL_PWRCTL_SELFREF_EN)) {
case0U:
returnDDR_SSR_MODE;
caseDDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE:
returnDDR_HSR_MODE;
caseDDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE | DDRCTRL_PWRCTL_SELFREF_EN:
returnDDR_ASR_MODE;
default:
returnDDR_SR_MODE_INVALID;
}
}
no need to add an other property
This is for U-Boot, plain, stock, without any other software partaking
in it.
Note that this patch just reinstates the old behavior before v2022.04
release, except it adds a DT property to enable the new behavior with
ASR and makes it non-default.
Re: [PATCH V3 3/4] imx: imx8mn_evk: enable CONFIG_DM_SERIAL
On Tue, Apr 12, 2022 at 6:31 PM Peng Fan (OSS) wrote:
>
> From: Peng Fan
>
> Enable CONFIG_DM_SERIAL. uart2 and its pinmux was already
> marked with u-boot,dm-spl.
>
> Signed-off-by: Peng Fan
> ---
> board/freescale/imx8mn_evk/spl.c | 12 ++--
> configs/imx8mn_ddr4_evk_defconfig | 1 +
> configs/imx8mn_evk_defconfig | 1 +
> 3 files changed, 4 insertions(+), 10 deletions(-)
>
> diff --git a/board/freescale/imx8mn_evk/spl.c
> b/board/freescale/imx8mn_evk/spl.c
> index 03f2a56e805..8708c93fa34 100644
> --- a/board/freescale/imx8mn_evk/spl.c
> +++ b/board/freescale/imx8mn_evk/spl.c
> @@ -110,14 +110,8 @@ int board_fit_config_name_match(const char *name)
> }
> #endif
>
> -#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
> #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE |
> PAD_CTL_PE)
>
> -static iomux_v3_cfg_t const uart_pads[] = {
> - IMX8MN_PAD_UART2_RXD__UART2_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
> - IMX8MN_PAD_UART2_TXD__UART2_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
> -};
> -
> static iomux_v3_cfg_t const wdog_pads[] = {
> IMX8MN_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
> };
> @@ -130,8 +124,6 @@ int board_early_init_f(void)
>
> set_wdog_reset(wdog);
>
> - imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
> -
> return 0;
> }
>
> @@ -147,8 +139,6 @@ void board_init_f(ulong dummy)
>
> timer_init();
>
> - preloader_console_init();
> -
> /* Clear the BSS. */
> memset(__bss_start, 0, __bss_end - __bss_start);
>
> @@ -158,6 +148,8 @@ void board_init_f(ulong dummy)
> hang();
> }
>
> + preloader_console_init();
> +
> enable_tzc380();
>
> /* DDR initialization */
> diff --git a/configs/imx8mn_ddr4_evk_defconfig
> b/configs/imx8mn_ddr4_evk_defconfig
> index 917cdb5aa9d..474d9cfa4d2 100644
> --- a/configs/imx8mn_ddr4_evk_defconfig
> +++ b/configs/imx8mn_ddr4_evk_defconfig
> @@ -76,6 +76,7 @@ CONFIG_PINCTRL_IMX8M=y
> CONFIG_DM_REGULATOR=y
> CONFIG_DM_REGULATOR_FIXED=y
> CONFIG_DM_REGULATOR_GPIO=y
> +CONFIG_DM_SERIAL=y
> CONFIG_MXC_UART=y
> CONFIG_SYSRESET=y
> CONFIG_SPL_SYSRESET=y
> diff --git a/configs/imx8mn_evk_defconfig b/configs/imx8mn_evk_defconfig
> index 7749ebe537e..5bc175154ba 100644
> --- a/configs/imx8mn_evk_defconfig
> +++ b/configs/imx8mn_evk_defconfig
> @@ -83,6 +83,7 @@ CONFIG_DM_REGULATOR=y
> CONFIG_SPL_DM_REGULATOR=y
> CONFIG_DM_REGULATOR_FIXED=y
> CONFIG_DM_REGULATOR_GPIO=y
> +CONFIG_DM_SERIAL=y
> CONFIG_MXC_UART=y
> CONFIG_SYSRESET=y
> CONFIG_SPL_SYSRESET=y
> --
> 2.35.1
>
Peng,
I see you've been able to get SPL DM_SERIAL to work on IMX8M. This
patch won't apply by the way due to commit ff1c7961d813 ("ARM: imx:
imx8mn-evk: enable DM_SERIAL") so I think you need to rebase.
I have not been able to get SPL DM_SERIAL to work on IMX8MM/IMX8MN...
it hangs my board. Is this due to moving preloader_console_init()
perhaps? Moving it didn't work for me.
Please explain the move of preloader_console_init() and please let me
know if you have tested this on imx/master. Fabio, perhaps you can
test?
Best Regards,
Tim
[PATCH] doc: man-page for the env command
Describe the env command. Signed-off-by: Patrick Delaunay --- doc/usage/cmd/askenv.rst | 2 + doc/usage/cmd/env.rst | 365 ++ doc/usage/cmdline.rst | 2 +- doc/usage/environment.rst | 2 + doc/usage/index.rst | 1 + 5 files changed, 371 insertions(+), 1 deletion(-) create mode 100644 doc/usage/cmd/env.rst diff --git a/doc/usage/cmd/askenv.rst b/doc/usage/cmd/askenv.rst index 5c4ca35d4c..347bd59458 100644 --- a/doc/usage/cmd/askenv.rst +++ b/doc/usage/cmd/askenv.rst @@ -16,6 +16,8 @@ Description Display message and get environment variable name of max size characters from stdin. +See also *env ask* in :doc:`env`. + name name of the environment variable diff --git a/doc/usage/cmd/env.rst b/doc/usage/cmd/env.rst new file mode 100644 index 00..e8c5797abd --- /dev/null +++ b/doc/usage/cmd/env.rst @@ -0,0 +1,365 @@ +.. SPDX-License-Identifier: GPL-2.0-or-later: + +env command +=== + +Synopsis + + +:: + + env ask name [message] [size] + env callbacks + env default [-f] (-a | var [...]) + env delete [-f] var [...] + env edit name + env exists name + env export [-t | -b | -c] [-s size] addr [var ...] + env flags + env grep [-e] [-n | -v | -b] string [...] + env import [-d] [-t [-r] | -b | -c] addr [size] [var ...] + env info [-d] [-p] [-q] + env print [-a | name ...] + env print -e [-guid guid] [-n] [name ...] + env run var [...] + env save + env erase + env load + env select [target] + env set [-f] name [value] + env set -e [-nv][-bs][-rt][-at][-a][-i addr:size][-v] name [value] + +Description +--- +The *env* commands is used to handle the U-Boot (:doc:`../environment`) or +the UEFI variables. + +The next commands are kept as alias and for compatibility: + ++ *editenv* = *env edit* ++ *grepenv* = *env grep* ++ *setenv* = *env set* ++ *askenv* = *env ask* ++ *run* = *env run* + +Ask +~~~ + +The *env ask* command asks for environment variable (alias :doc:`askenv`). + +name +name of the environment variable. + +message +message is displayed while the command waits for the value to be +entered from stdin.if no message is specified,a default message +"Please enter name:" will be displayed. + +size +maximum number of characters that will be stored in environment +variable name.this is in decimal number format (unlike in +other commands where size values are in hexa-decimal). Default +value of size is 1023 (CONFIG_SYS_CBSIZE - 1). + +Callbacks +~ + +The *env callbacks* command prints callbacks and their associated variables. + +Default +~~~ + +The *env default* command resets the selected variables in the U-Boot +environment to their default values. + +var +list of variable name. +\-a +all U-Boot environment. +\-f +forcibly, overwrite read-only/write-once variables. + +Delete +~~ + +The *env delete* command deletes the selected variables in the U-Boot +environment. + +var +name of the variable to delete. +\-f +forcibly, overwrite read-only/write-once variables. + +Edit + + +The *env edit* command edits an environment variable. + +name +name of the variable. + +Exists +~~ + +The *env exists* command tests for existence of variable. + +name +name of the variable. + +Export +~~ + +The *env export* command exports the U-Boot environment in memory; on success, +the variable "filesize" will be set. + +addr +memory address where environment gets stored. +var +list of variable names that get included into the export. +Without arguments, the whole environment gets exported. +\-b +export as binary format (name=value pairs separated by +list end marked by double "\0\0"). +\-t +export as text format; if size is given, data will be +padded with '\0' bytes; if not, one terminating '\0' +will be added. +\-c +Export as checksum protected environment format as used by +'env save' command. +\-s size +size of output buffer. + +Flags +~ + +The *env flags* command prints variables that have non-default flags. + +Grep + + +The *env grep* command searches environment, list environment name=value pairs +matching the requested 'string'. + +string +string to search in U-Boot environment. +\-e +enable regular expressions. +\-n +search string in variable names. +\-v +search string in vairable values. +\-b +search both names and values (default). + +Import +~~ + +The *env import* command imports environment from memory. + +addr +memory address to read from. +size +length of input data; if missing, proper '\0' termination is mandatory
[PATCH v2] cmd: adc: Add support for storing ADC result in env variable
Add the ability to save ADC conversion result in an environment
variable. This is useful for further arbitrary processing by the
U-Boot scripts.
Signed-off-by: Marek Vasut
Cc: Fabrice Gasnier
Cc: Patrice Chotard
Cc: Patrick Delaunay
Cc: Simon Glass
---
V2: - Fix up commit message
- Call adc_raw_to_uV() only once
---
cmd/adc.c | 18 ++
1 file changed, 14 insertions(+), 4 deletions(-)
diff --git a/cmd/adc.c b/cmd/adc.c
index 75739bc8eed..8de9121cad6 100644
--- a/cmd/adc.c
+++ b/cmd/adc.c
@@ -71,13 +71,17 @@ static int do_adc_info(struct cmd_tbl *cmdtp, int flag, int
argc,
static int do_adc_single(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
{
+ char *varname = NULL;
struct udevice *dev;
unsigned int data;
- int ret, uV;
+ int ret, uV, val;
if (argc < 3)
return CMD_RET_USAGE;
+ if (argc >= 3)
+ varname = argv[2];
+
ret = adc_channel_single_shot(argv[1], simple_strtol(argv[2], NULL, 0),
);
if (ret) {
@@ -87,10 +91,16 @@ static int do_adc_single(struct cmd_tbl *cmdtp, int flag,
int argc,
}
ret = uclass_get_device_by_name(UCLASS_ADC, argv[1], );
- if (!ret && !adc_raw_to_uV(dev, data, ))
+ if (!ret && !adc_raw_to_uV(dev, data, )) {
+ val = uV;
printf("%u, %d uV\n", data, uV);
- else
+ } else {
+ val = data;
printf("%u\n", data);
+ }
+
+ if (varname)
+ env_set_ulong(varname, val);
return CMD_RET_SUCCESS;
}
@@ -149,7 +159,7 @@ static int do_adc_scan(struct cmd_tbl *cmdtp, int flag, int
argc,
static char adc_help_text[] =
"list - list ADC devices\n"
"adc info - Get ADC device info\n"
- "adc single - Get Single data of ADC device channel\n"
+ "adc single [varname] - Get Single data of ADC device
channel\n"
"adc scan [channel mask] - Scan all [or masked] ADC channels";
U_BOOT_CMD_WITH_SUBCMDS(adc, "ADC sub-system", adc_help_text,
--
2.35.1
Re: [PATCH] ram: stm32mp1: Conditionally enable ASR
On 4/14/22 18:37, Patrick DELAUNAY wrote:
Hi Marek,
Hi,
on ST platform the ASR/SSR/HSR request are already provided by the DDR
settings with pwrctl register value
it is managed in TF-A by
arm-trusted-firmware/drivers/st/ddr/stm32mp1_ddr_helpers.c
Sure, I don't use ATF and I have no intention of ever using ATF on this
platform.
enumstm32mp1_ddr_sr_mode ddr_read_sr_mode(void)
{
uint32_tpwrctl = mmio_read_32(stm32mp_ddrctrl_base() + DDRCTRL_PWRCTL);
switch(pwrctl & (DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE |
DDRCTRL_PWRCTL_SELFREF_EN)) {
case0U:
returnDDR_SSR_MODE;
caseDDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE:
returnDDR_HSR_MODE;
caseDDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE | DDRCTRL_PWRCTL_SELFREF_EN:
returnDDR_ASR_MODE;
default:
returnDDR_SR_MODE_INVALID;
}
}
no need to add an other property
This is for U-Boot, plain, stock, without any other software partaking
in it.
Re: [PATCH] cmd: adc: Add support for storing ADC result in env variable
Hi Marek,
On 4/13/22 04:17, Marek Vasut wrote:
Add the ability to start ADC conversion result in an environment
s/to start/to save/ ?
variable. This is useful for further arbitrary processing by the
U-Boot scripts.
Signed-off-by: Marek Vasut
Cc: Fabrice Gasnier
Cc: Simon Glass
---
cmd/adc.c | 13 -
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/cmd/adc.c b/cmd/adc.c
index 75739bc8eed..4f548b811ec 100644
--- a/cmd/adc.c
+++ b/cmd/adc.c
@@ -71,6 +71,7 @@ static int do_adc_info(struct cmd_tbl *cmdtp, int flag, int
argc,
static int do_adc_single(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
{
+ char *varname = NULL;
struct udevice *dev;
unsigned int data;
int ret, uV;
@@ -78,6 +79,9 @@ static int do_adc_single(struct cmd_tbl *cmdtp, int flag, int
argc,
if (argc < 3)
return CMD_RET_USAGE;
+ if (argc >= 3)
+ varname = argv[2];
+
ret = adc_channel_single_shot(argv[1], simple_strtol(argv[2], NULL, 0),
);
if (ret) {
@@ -92,6 +96,13 @@ static int do_adc_single(struct cmd_tbl *cmdtp, int flag,
int argc,
else
printf("%u\n", data);
+ if (varname) {
+ if (!adc_raw_to_uV(dev, data, ))
+ env_set_ulong(varname, uV);
+ else
+ env_set_ulong(varname, data);
+ }
+
Minor remark: no need to call 2 times adc_raw_to_uV()
conversion result can be saved in a local variable
+ ulong var_value;
ret = uclass_get_device_by_name(UCLASS_ADC, argv[1], );
if (!ret && !adc_raw_to_uV(dev, data, )) {
printf("%u, %d uV\n", data, uV);
+ var_value = uV;
} else {
printf("%u\n", data);
+ var_value = data;
}
+ if (varname)
+ env_set_ulong(varname, var_value);
return CMD_RET_SUCCESS;
}
@@ -149,7 +160,7 @@ static int do_adc_scan(struct cmd_tbl *cmdtp, int flag, int argc,
static char adc_help_text[] =
"list - list ADC devices\n"
"adc info - Get ADC device info\n"
- "adc single - Get Single data of ADC device channel\n"
+ "adc single [varname] - Get Single data of ADC device
channel\n"
"adc scan [channel mask] - Scan all [or masked] ADC channels";
U_BOOT_CMD_WITH_SUBCMDS(adc, "ADC sub-system", adc_help_text,
Regards
Patrick
Re: [PATCH] ram: stm32mp1: Conditionally enable ASR
Hi Marek,
on ST platform the ASR/SSR/HSR request are already provided by the DDR
settings with pwrctl register value
it is managed in TF-A by
arm-trusted-firmware/drivers/st/ddr/stm32mp1_ddr_helpers.c
enumstm32mp1_ddr_sr_mode ddr_read_sr_mode(void)
{
uint32_tpwrctl = mmio_read_32(stm32mp_ddrctrl_base() + DDRCTRL_PWRCTL);
switch(pwrctl & (DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE |
DDRCTRL_PWRCTL_SELFREF_EN)) {
case0U:
returnDDR_SSR_MODE;
caseDDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE:
returnDDR_HSR_MODE;
caseDDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE | DDRCTRL_PWRCTL_SELFREF_EN:
returnDDR_ASR_MODE;
default:
returnDDR_SR_MODE_INVALID;
}
}
no need to add an other property
I think
On 4/13/22 04:49, Marek Vasut wrote:
Enable DRAM ASR, auto self-refresh, conditionally, based on DT property
"st,mem-enable-asr" . While ASR does save considerable amount of power
at runtime automatically, it also causes LTDC underruns on large panels.
Let user select whether or not ASR is required or not, generally ASR
should be enabled on portable and battery operated devices.
Signed-off-by: Marek Vasut
Cc: Patrick Delaunay
Cc: Patrice Chotard
---
drivers/ram/stm32mp1/stm32mp1_ddr.c | 3 ++-
drivers/ram/stm32mp1/stm32mp1_ddr.h | 1 +
drivers/ram/stm32mp1/stm32mp1_ram.c | 1 +
3 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/ram/stm32mp1/stm32mp1_ddr.c
b/drivers/ram/stm32mp1/stm32mp1_ddr.c
index 528a171b454..fd11e02aff4 100644
--- a/drivers/ram/stm32mp1/stm32mp1_ddr.c
+++ b/drivers/ram/stm32mp1/stm32mp1_ddr.c
@@ -845,7 +845,8 @@ start:
config->c_reg.pwrctl);
/* Enable auto-self-refresh, which saves a bit of power at runtime. */
- stm32mp1_asr_enable(priv);
+ if (config->c_reg.pwrctl & (DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE |
DDRCTRL_PWRCTL_SELFREF_SW) ==
(DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE |DDRCTRL_PWRCTL_SELFREF_SW))
+ stm32mp1_asr_enable(priv);
in DDR setting
#define DDR_PWRCTL 0x
=> SSR
#define DDR_PWRCTL 0x0028
=> ASR
+ if (config->info.enable_asr)
+ stm32mp1_asr_enable(priv);
/* enable uMCTL2 AXI port 0 and 1 */
setbits_le32(>ctl->pctrl_0, DDRCTRL_PCTRL_N_PORT_EN);
diff --git a/drivers/ram/stm32mp1/stm32mp1_ddr.h
b/drivers/ram/stm32mp1/stm32mp1_ddr.h
index 861efff92be..c74a9cea2cc 100644
--- a/drivers/ram/stm32mp1/stm32mp1_ddr.h
+++ b/drivers/ram/stm32mp1/stm32mp1_ddr.h
@@ -144,6 +144,7 @@ struct stm32mp1_ddr_info {
const char *name;
u32 speed; /* in kHZ */
u32 size; /* memory size in byte = col * row * width */
+ bool enable_asr;
};
struct stm32mp1_ddr_config {
diff --git a/drivers/ram/stm32mp1/stm32mp1_ram.c
b/drivers/ram/stm32mp1/stm32mp1_ram.c
index 49b1262461b..f39cfad4764 100644
--- a/drivers/ram/stm32mp1/stm32mp1_ram.c
+++ b/drivers/ram/stm32mp1/stm32mp1_ram.c
@@ -122,6 +122,7 @@ static int stm32mp1_ddr_setup(struct udevice *dev)
config.info.speed = ofnode_read_u32_default(node, "st,mem-speed", 0);
config.info.size = ofnode_read_u32_default(node, "st,mem-size", 0);
config.info.name = ofnode_read_string(node, "st,mem-name");
+ config.info.enable_asr = ofnode_read_bool(node, "st,mem-enable-asr");
if (!config.info.name) {
dev_dbg(dev, "no st,mem-name\n");
return -EINVAL;
Regards
Patrick
Re: [PATCH 1/2] common: fdt: Add a function for reserving memory without kernel linear mapping
HI Tommaso,
Thank you to have time on this
Michael
On Tue, Feb 25, 2020 at 6:10 AM Michael Trimarchi
wrote:
>
> The intent is to reserve memory _and_ prevent it from being included
> in the kernel's linear map. For thos reason it is also necessary to include
> the
> 'no-map' property for this reserved-mem node.
>
> From Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt:
>
> no-map (optional) - empty property
> - Indicates the operating system must not create a virtual mapping
> of the region as part of its standard mapping of system memory,
> nor permit speculative access to it under any circumstances other
> than under the control of the device driver using the region.
>
> Signed-off-by: Michael Trimarchi
> ---
> Changes: RFC->v1
> - Add a better commit message
> ---
> common/fdt_support.c | 40
> include/fdt_support.h | 11 +++
> 2 files changed, 51 insertions(+)
>
> diff --git a/common/fdt_support.c b/common/fdt_support.c
> index 02cf5c6241..a3662f4358 100644
> --- a/common/fdt_support.c
> +++ b/common/fdt_support.c
> @@ -410,6 +410,46 @@ static int fdt_pack_reg(const void *fdt, void *buf, u64
> *address, u64 *size,
> return p - (char *)buf;
> }
>
> +int fdt_fixup_reserved_memory(void *blob, const char *area, u64 start[], u64
> size[])
> +{
> + int offs, len;
> + const char *subpath;
> + const char *path = "/reserved-memory";
> + fdt32_t address_cells = cpu_to_fdt32(fdt_address_cells(blob, 0));
> + fdt32_t size_cells = cpu_to_fdt32(fdt_size_cells(blob, 0));
> + u8 temp[16]; /* Up to 64-bit address + 64-bit size */
> +
> + offs = fdt_path_offset(blob, path);
> + if (offs < 0) {
> + debug("Node %s not found\n", path);
> + path = "/";
> + subpath = "reserved-memory";
> + offs = fdt_path_offset(blob, path);
> + offs = fdt_add_subnode(blob, offs, subpath);
> + if (offs < 0) {
> + printf("Could not create %s%s node.\n", path,
> subpath);
> + return -1;
> + }
> + path = "/reserved-memory";
> + offs = fdt_path_offset(blob, path);
> +
> + fdt_setprop(blob, offs, "#address-cells", _cells,
> sizeof(address_cells));
> + fdt_setprop(blob, offs, "#size-cells", _cells,
> sizeof(size_cells));
> + fdt_setprop(blob, offs, "ranges", NULL, 0);
> + }
> +
> + offs = fdt_add_subnode(blob, offs, area ? : "private");
> + if (offs < 0) {
> + printf("Could not create %s%s node.\n", path, subpath);
> + return -1;
> + }
> +
> + fdt_setprop(blob, offs, "no-map", NULL, 0);
> + len = fdt_pack_reg(blob, temp, start, size, 1);
> + fdt_setprop(blob, offs, "reg", temp, len);
> + return 0;
> +}
> +
> #if CONFIG_NR_DRAM_BANKS > 4
> #define MEMORY_BANKS_MAX CONFIG_NR_DRAM_BANKS
> #else
> diff --git a/include/fdt_support.h b/include/fdt_support.h
> index ba14acd7f6..7c8a280f53 100644
> --- a/include/fdt_support.h
> +++ b/include/fdt_support.h
> @@ -93,6 +93,17 @@ void do_fixup_by_compat_u32(void *fdt, const char *compat,
> */
> int fdt_fixup_memory(void *blob, u64 start, u64 size);
>
> +/**
> + * Setup the memory reserved node in the DT. Creates one if none was
> existing before.
> + *
> + * @param blob FDT blob to update
> + * @param area Reserved area name
> + * @param startBegin of DRAM mapping in physical memory
> + * @param size Size of the single memory bank
> + * @return 0 if ok, or -1 or -FDT_ERR_... on error
> + */
> +int fdt_fixup_reserved_memory(void *blob, const char *area, u64 start[], u64
> size[]);
> +
> /**
> * Fill the DT memory node with multiple memory banks.
> * Creates the node if none was existing before.
> --
> 2.17.1
>
--
Michael Nazzareno Trimarchi
Co-Founder & Chief Executive Officer
M. +39 347 913 2170
mich...@amarulasolutions.com
__
Amarula Solutions BV
Joop Geesinkweg 125, 1114 AB, Amsterdam, NL
T. +31 (0)85 111 9172
i...@amarulasolutions.com
www.amarulasolutions.com
Re: [PATCH v2] board: gateworks: venice: enable DM_SERIAL
On Wed, Apr 13, 2022 at 10:21 AM Michael Nazzareno Trimarchi
wrote:
>
> Hi
>
> On Wed, Apr 13, 2022 at 6:09 PM Tim Harvey wrote:
> >
> > On Wed, Apr 13, 2022 at 8:56 AM Michael Nazzareno Trimarchi
> > wrote:
> > >
> > > Hi Tim
> > >
> > > On Wed, Apr 13, 2022 at 5:47 PM Tim Harvey wrote:
> > > >
> > > > Enable DM_SERIAL.
> > > >
> > > > Signed-off-by: Tim Harvey
> > > > ---
> > > > v2: rebase on imx/master
> > > > ---
> > > > configs/imx8mm_venice_defconfig | 2 ++
> > > > configs/imx8mn_venice_defconfig | 2 ++
> > > > 2 files changed, 4 insertions(+)
> > > >
> > > > diff --git a/configs/imx8mm_venice_defconfig
> > > > b/configs/imx8mm_venice_defconfig
> > > > index dd61ec9b70fb..09f7d8a58ca7 100644
> > > > --- a/configs/imx8mm_venice_defconfig
> > > > +++ b/configs/imx8mm_venice_defconfig
> > > > @@ -110,6 +110,8 @@ CONFIG_SPL_DM_PMIC_MP5416=y
> > > > CONFIG_DM_REGULATOR=y
> > > > CONFIG_DM_REGULATOR_FIXED=y
> > > > CONFIG_DM_REGULATOR_GPIO=y
> > > > +CONFIG_DM_SERIAL=y
> > > > +# CONFIG_SPL_DM_SERIAL is not set
> > > > CONFIG_MXC_UART=y
> > > > CONFIG_SYSRESET=y
> > > > CONFIG_SPL_SYSRESET=y
> > > > diff --git a/configs/imx8mn_venice_defconfig
> > > > b/configs/imx8mn_venice_defconfig
> > > > index c3a96a378553..41898da4aecf 100644
> > > > --- a/configs/imx8mn_venice_defconfig
> > > > +++ b/configs/imx8mn_venice_defconfig
> > > > @@ -108,6 +108,8 @@ CONFIG_SPL_DM_PMIC_MP5416=y
> > > > CONFIG_DM_REGULATOR=y
> > > > CONFIG_DM_REGULATOR_FIXED=y
> > > > CONFIG_DM_REGULATOR_GPIO=y
> > > > +CONFIG_DM_SERIAL=y
> > > > +# CONFIG_SPL_DM_SERIAL is not set
> > > > CONFIG_MXC_UART=y
> > > > CONFIG_SYSRESET=y
> > > > CONFIG_SPL_SYSRESET=y
> > > > --
> > > > 2.17.1
> > > >
> > >
> > > Should not select in your board kconfig?
> > >
> >
> > Michael,
> >
> > I don't think it really matters. The other conversions to DM_SERIAL
> > are going in defconfigs as well.
>
> Do we know why without # CONFIG_SPL_DM_SERIAL is not set
>
> board hang?
>
Michael,
yes, if I also enable CONFIG_SPL_DM_SERIAL I get no serial output and
the board hangs even if I add 'u-boot,dm-pre-proper' to
uart2/pinctrl_uart2 nodes.
The requirement is to use DM_SERIAL in U-Boot, not in the SPL. I'm
doing the same as was done for imx8mn-evk in ff1c7961d813 ("ARM: imx:
imx8mn-evk: enable DM_SERIAL").
Thus far, no ARCH_IMX8M boards have enabled CONFIG_SPL_DM_SERIAL so I
suppose others have run into this as well but again the requirement is
to enable CONFIG_DM_SERIAL not necessarily the SPL.
Best Regards,
Tim
Re: [PATCH 03/11] arm: dts: Add Chameleonv3 devicetree
On Mon, Apr 11, 2022 at 8:35 PM Simon Glass wrote: > > On Fri, 1 Apr 2022 at 06:44, Paweł Anikiel wrote: > > > > Add devicetree for Google Chameleon V3 board > > > > Signed-off-by: Paweł Anikiel > > --- > > arch/arm/dts/Makefile | 2 ++ > > arch/arm/dts/socfpga_chameleonv3.dtsi | 21 + > > arch/arm/dts/socfpga_chameleonv3_270_3.dts | 9 + > > arch/arm/dts/socfpga_chameleonv3_480_2.dts | 9 + > > 4 files changed, 41 insertions(+) > > create mode 100644 arch/arm/dts/socfpga_chameleonv3.dtsi > > create mode 100644 arch/arm/dts/socfpga_chameleonv3_270_3.dts > > create mode 100644 arch/arm/dts/socfpga_chameleonv3_480_2.dts > > Reviewed-by: Simon Glass > > (has this been sent to Linux?) It has not been sent to Linux. Regards, Paweł
Re: EXT: [PATCH] pci: imx: use vpcie-supply if defined by device-tree
On Thu, Apr 14, 2022 at 2:14 AM Ian Ray wrote:
>
> On Wed, Apr 13, 2022 at 03:54:37PM -0700, Tim Harvey wrote:
> >
> > If vpcie-supply is defined by device-tree use that if
> > CONFIG_PCIE_IMX_POWER_GPIO is not defined.
> >
> > Note that after this the following boards which define
> > CONFIG_PCIE_IMX_POWER_GPIO in their board header file as well as their
> > device-tree should be able to remove CONFIG_PCIE_IMX_PERST_GPIO without
> > consequence:
> > - mx6sabresd
> > - mx6sxsabresd
> > - novena
> >
> > Note that the ge_bx50v3 board uses CONFIG_PCIE_IMX_POWER_GPIO and does
> > not have vpcie-supply defined in it's pcie node in the dt thus removing
> > CONFIG_PCIE_IMX_POWER_GPIO globally can't be done until that board adds
> > vpcie-supply.
>
> The use of CONFIG_PCIE_IMX_POWER_GPIO by ge_bx50v3 appears to be a
> mistake. That GPIO is actually an input "Q7_3V3_PCIE_WAKE#_IN". Thank
> you for the report -- I will prepare a patch to remove that #define.
>
Ian,
Great... cc me on that patch if you don't mind.
Marek, looks like you're the maintainer of the novena board, do you
have one around to test PCI reset with CONFIG_PCIE_IMX_POWER_GPIO
removed?
Fabio, looks like you're the maintainer of the mx6sabresd and
mx6sxsabresd boards, do you have one around to test PCI reset with
CONFIG_PCIE_IMX_POWER_GPIO removed?
If Marke and Fabio can confirm that removing
CONFIG_PCIE_IMX_POWER_GPIO isn't an issue I can submit a series with
this followed by the removal of CONFIG_PCIE_IMX_POWER_GPIO.
Best Regards,
Tim
>
> >
> > Cc: Ian Ray (maintainer:GE BX50V3 BOARD)
> > Cc: Sebastian Reichel (maintainer:GE
> > BX50V3 BOARD)
> > Cc: Fabio Estevam (maintainer:MX6SABRESD BOARD)
> > Cc: Marek Vasut (maintainer:NOVENA BOARD)
> > Signed-off-by: Tim Harvey
> > ---
> > arch/arm/include/asm/arch-mx6/sys_proto.h | 2 +-
> > drivers/pci/pcie_imx.c| 19 +--
> > 2 files changed, 18 insertions(+), 3 deletions(-)
> >
> > diff --git a/arch/arm/include/asm/arch-mx6/sys_proto.h
> > b/arch/arm/include/asm/arch-mx6/sys_proto.h
> > index c49759af92d1..c7542e4b04e1 100644
> > --- a/arch/arm/include/asm/arch-mx6/sys_proto.h
> > +++ b/arch/arm/include/asm/arch-mx6/sys_proto.h
> > @@ -18,7 +18,7 @@
> > #define is_usbotg_phy_active(void) (!(readl(USB_PHY0_BASE_ADDR +
> > USBPHY_PWD) & \
> > USBPHY_PWD_RXPWDRX))
> >
> > -int imx6_pcie_toggle_power(void);
> > +int imx6_pcie_toggle_power(struct udevice *vpcie);
> > int imx6_pcie_toggle_reset(struct gpio_desc *gpio, bool active_high);
> >
> > enum ldo_reg {
> > diff --git a/drivers/pci/pcie_imx.c b/drivers/pci/pcie_imx.c
> > index 2cec3900e9ad..f8daedbce359 100644
> > --- a/drivers/pci/pcie_imx.c
> > +++ b/drivers/pci/pcie_imx.c
> > @@ -14,6 +14,7 @@
> > #include
> > #include
> > #include
> > +#include
> > #include
> > #include
> > #include
> > @@ -102,6 +103,7 @@ struct imx_pcie_priv {
> > void __iomem*cfg_base;
> > struct gpio_descreset_gpio;
> > boolreset_active_high;
> > + struct udevice *vpcie;
> > };
> >
> > /*
> > @@ -530,7 +532,7 @@ static int imx6_pcie_init_phy(void)
> > return 0;
> > }
> >
> > -__weak int imx6_pcie_toggle_power(void)
> > +__weak int imx6_pcie_toggle_power(struct udevice *vpcie)
> > {
> > #ifdef CONFIG_PCIE_IMX_POWER_GPIO
> > gpio_request(CONFIG_PCIE_IMX_POWER_GPIO, "pcie_power");
> > @@ -540,6 +542,15 @@ __weak int imx6_pcie_toggle_power(void)
> > mdelay(20);
> > gpio_free(CONFIG_PCIE_IMX_POWER_GPIO);
> > #endif
> > +
> > +#if CONFIG_IS_ENABLED(DM_REGULATOR)
> > + if (vpcie) {
> > + regulator_set_enable(vpcie, false);
> > + mdelay(20);
> > + regulator_set_enable(vpcie, true);
> > + mdelay(20);
> > + }
> > +#endif
> > return 0;
> > }
> >
> > @@ -598,7 +609,7 @@ static int imx6_pcie_deassert_core_reset(struct
> > imx_pcie_priv *priv)
> > {
> > struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
> >
> > - imx6_pcie_toggle_power();
> > + imx6_pcie_toggle_power(priv->vpcie);
> >
> > enable_pcie_clock();
> >
> > @@ -717,6 +728,10 @@ static int imx_pcie_dm_probe(struct udevice *dev)
> > {
> > struct imx_pcie_priv *priv = dev_get_priv(dev);
> >
> > +#if CONFIG_IS_ENABLED(DM_REGULATOR)
> > + device_get_supply_regulator(dev, "vpcie-supply", >vpcie);
> > +#endif
> > +
> > /* if PERST# valid from dt then assert it */
> > gpio_request_by_name(dev, "reset-gpio", 0, >reset_gpio,
> >GPIOD_IS_OUT);
> > --
> > 2.17.1
> >
> >
Re: [PATCH 01/11] arm: dts: Add Mercury+ AA1 devicetree
On Mon, Apr 11, 2022 at 8:35 PM Simon Glass wrote:
>
> Hi Paweł,
>
> On Fri, 1 Apr 2022 at 06:44, Paweł Anikiel wrote:
> >
> > Device tree header for Mercury+ AA1 module
> >
> > Signed-off-by: Paweł Anikiel
> > ---
> > arch/arm/dts/socfpga_mercury_aa1.dtsi | 95 +++
> > 1 file changed, 95 insertions(+)
> > create mode 100644 arch/arm/dts/socfpga_mercury_aa1.dtsi
> >
>
> Has this been sent to Linux?
Yes, a while ago. It's under
arch/arm/boot/dts/socfpga_arria10_mercury_aa1.dts
>
> > diff --git a/arch/arm/dts/socfpga_mercury_aa1.dtsi
> > b/arch/arm/dts/socfpga_mercury_aa1.dtsi
> > new file mode 100644
> > index 00..7d0bf884a3
> > --- /dev/null
> > +++ b/arch/arm/dts/socfpga_mercury_aa1.dtsi
> > @@ -0,0 +1,95 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Copyright 2022 Google LLC
> > + */
> > +#include "socfpga_arria10.dtsi"
> > +#include "socfpga_arria10-u-boot.dtsi"
> > +
> > +/ {
> > + model = "Altera SOCFPGA Arria 10";
> > + compatible = "altr,socfpga-arria10", "altr,socfpga";
> > +
> > + aliases {
> > + ethernet0 =
> > + serial0 =
> > + };
> > +
> > + chosen {
> > + stdout-path = "serial0:115200n8";
> > + firmware-loader = <_loader0>;
> > + };
> > +
> > + memory@0 {
> > + name = "memory";
> > + device_type = "memory";
> > + reg = <0x0 0x8000>; /* 2GB */
> > + };
> > +
> > + fs_loader0: fs-loader {
> > + u-boot,dm-pre-reloc;
> > + compatible = "u-boot,fs-loader";
> > + phandlepart = < 1>;
> > + };
> > +};
> > +
> > +_mgr {
> > + u-boot,dm-pre-reloc;
> > + altr,bitstream = "fpga.itb";
> > +};
> > +
> > + {
> > + phy-mode = "rgmii";
> > + phy-addr = <0x>; /* probe for phy addr */
> > +
> > + txd0-skew-ps = <0>; /* -420ps */
> > + txd1-skew-ps = <0>; /* -420ps */
> > + txd2-skew-ps = <0>; /* -420ps */
> > + txd3-skew-ps = <0>; /* -420ps */
> > + rxd0-skew-ps = <420>; /* 0ps */
> > + rxd1-skew-ps = <420>; /* 0ps */
> > + rxd2-skew-ps = <420>; /* 0ps */
> > + rxd3-skew-ps = <420>; /* 0ps */
> > + txen-skew-ps = <0>; /* -420ps */
> > + txc-skew-ps = <1860>; /* 960ps */
> > + rxdv-skew-ps = <420>; /* 0ps */
> > + rxc-skew-ps = <1680>; /* 780ps */
> > + max-frame-size = <3800>;
> > +};
> > +
> > + {
> > + u-boot,dm-pre-reloc;
> > +
> > + atsha204a@64 {
> > + u-boot,dm-pre-reloc;
> > + compatible = "atmel,atsha204a";
> > + reg = <0x64>;
> > + };
> > +};
> > +
> > +_sdmmc_clk {
> > + u-boot,dm-pre-reloc;
> > +};
> > +
> > + {
> > + cap-sd-highspeed;
> > + cap-mmc-highspeed;
> > + broken-cd;
> > + bus-width = <4>;
> > + u-boot,dm-pre-reloc;
> > +};
> > +
> > +_sdmmc_clk {
> > + u-boot,dm-pre-reloc;
> > +};
> > +
> > +_clk {
> > + u-boot,dm-pre-reloc;
>
> These U-Boot tags should be in the u-boot.dtsi file that you include above.
I believe these are board-specific, so they shouldn't go into
socfpga_arria10-u-boot.dtsi.
I will make a seperate file socfpga_arria10_chameleonv3-u-boot.dtsi
and put them there.
Regards,
Paweł
Re: [PATCH 02/11] arm: dts: Add Chameleonv3 handoff headers
On Mon, Apr 11, 2022 at 8:35 PM Simon Glass wrote: > > On Fri, 1 Apr 2022 at 06:44, Paweł Anikiel wrote: > > > > Add handoff headers for the Google Chameleonv3 variants: 480-2 and > > 270-3. Both files were generated using qts-filter-a10.sh. > > > > Signed-off-by: Paweł Anikiel > > --- > > .../dts/socfpga_chameleonv3_270_3_handoff.h | 305 ++ > > .../dts/socfpga_chameleonv3_480_2_handoff.h | 305 ++ > > 2 files changed, 610 insertions(+) > > create mode 100644 arch/arm/dts/socfpga_chameleonv3_270_3_handoff.h > > create mode 100644 arch/arm/dts/socfpga_chameleonv3_480_2_handoff.h > > If these are binding files needed for the dts, should they not go into > include/dt-bindings ? > > If not, can they go into arch/arm/include/asm/arch-... ? These files are generated by Quartus, they include things like pinmux configurations and clock settings. I put them in the same place as the existing arria10_socdk handoff: arch/arm/dts/socfpga_arria10_socdk_sdmmc_handoff.h I don't mind putting them in include/dt-bindings, but then we should probably also move the arria10_socdk one. What do you think? Regards, Paweł
Re: [PATCH 07/11] sysreset: socfpga: Use parent device for reading base address
On Mon, Apr 11, 2022 at 8:36 PM Simon Glass wrote:
>
> On Fri, 1 Apr 2022 at 06:44, Paweł Anikiel wrote:
> >
> > This driver is a child of the rstmgr driver, both of which share the
> > same devicetree node. As a result, passing the child's udevice pointer
> > to dev_read_addr_ptr results in a failure of reading the #address-cells
> > property. Use the parent udevice pointer instead.
> >
> > Signed-off-by: Paweł Anikiel
> > ---
> > drivers/sysreset/sysreset_socfpga.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
>
> Reviewed-by: Simon Glass
>
> >
> > diff --git a/drivers/sysreset/sysreset_socfpga.c
> > b/drivers/sysreset/sysreset_socfpga.c
> > index e38296ac3f..9b62dd5eab 100644
> > --- a/drivers/sysreset/sysreset_socfpga.c
> > +++ b/drivers/sysreset/sysreset_socfpga.c
> > @@ -40,7 +40,7 @@ static int socfpga_sysreset_probe(struct udevice *dev)
>
> Perhaps this function
> > {
> > struct socfpga_sysreset_data *data = dev_get_priv(dev);
> >
> > - data->rstmgr_base = dev_read_addr_ptr(dev);
> > + data->rstmgr_base = dev_read_addr_ptr(dev_get_parent(dev));
> > return 0;
> > }
> >
> > --
> > 2.35.1.1094.g7c7d902a7c-goog
> >
>
> This is pretty odd and I think it could use a comment, particularly as
> this driver doesn't seem to be in the device tree.
It does get bound to a devicetree node by a different driver:
reset-socfpga (drivers/reset/reset-socfpga.c:141):
/*
* The sysreset driver does not have a device node, so bind it here.
* Bind it to the node, too, so that it can get its base address.
*/
ret = device_bind_driver_to_node(dev, "socfpga_sysreset", "sysreset",
dev_ofnode(dev), _child);
However, this makes it so that dev_read_addr_ptr doesn't behave the way
one would think, hence this patch.
It is pretty odd, it seems to be caused by the fact that Arria 10's
peripheral reset manager
is also responsible for system reset (see "ctrl" register in rst_mgr's
register map):
https://www.intel.com/content/www/us/en/programmable/hps/arria-10/hps.html#topic/sfo1429890591861.html
Because of this, the two drivers have to share the same devicetree node.
Do you see a different way this could be fixed? If not, I will add
a comment with an explanation similar to the commit message.
Regards,
Paweł
Re: [PATCH u-boot-net v4 03/14] net: introduce helpers to get PHY ofnode from MAC
On Wed, Apr 13, 2022 at 05:46:11PM -0400, Tom Rini wrote:
> On Thu, Apr 07, 2022 at 12:32:57AM +0200, Marek Behún wrote:
>
> > From: Marek Behún
> >
> > Add helpers ofnode_get_phy_node() and dev_get_phy_node() and use it in
> > net/mdio-uclass.c function dm_eth_connect_phy_handle(). Also add
> > corresponding UT test.
> >
> > This is useful because other part's of U-Boot may want to get PHY ofnode
> > without connecting a PHY.
> >
> > Signed-off-by: Marek Behún
> > Reviewed-by: Ramon Fried
> > Reviewed-by: Simon Glass
> > ---
> > arch/sandbox/dts/test.dts | 13 +
> > drivers/core/ofnode.c | 21 +
> > drivers/core/read.c | 5 +
> > include/dm/ofnode.h | 14 ++
> > include/dm/read.h | 19 +++
> > net/mdio-uclass.c | 24 ++--
> > test/dm/ofnode.c | 18 ++
> > 7 files changed, 96 insertions(+), 18 deletions(-)
> >
> > diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts
> > index 05c1cd5e1a..e536943503 100644
> > --- a/arch/sandbox/dts/test.dts
> > +++ b/arch/sandbox/dts/test.dts
> > @@ -530,6 +530,13 @@
> > fake-host-hwaddr = [00 00 66 44 22 22];
> > };
> >
> > + phy_eth0: phy-test-eth {
> > + compatible = "sandbox,eth";
> > + reg = <0x10007000 0x1000>;
> > + fake-host-hwaddr = [00 00 66 44 22 77];
> > + phy-handle = <>;
> > + };
> > +
> > dsa_eth0: dsa-test-eth {
> > compatible = "sandbox,eth";
> > reg = <0x10006000 0x1000>;
> > @@ -1555,6 +1562,12 @@
> >
> > mdio: mdio-test {
> > compatible = "sandbox,mdio";
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > +
> > + ethphy1: ethernet-phy@1 {
> > + reg = <1>;
> > + };
> > };
> >
> > pm-bus-test {
> > diff --git a/drivers/core/ofnode.c b/drivers/core/ofnode.c
> > index 8042847f3c..445b7ad5ad 100644
> > --- a/drivers/core/ofnode.c
> > +++ b/drivers/core/ofnode.c
> > @@ -1198,3 +1198,24 @@ const char *ofnode_conf_read_str(const char
> > *prop_name)
> >
> > return ofnode_read_string(node, prop_name);
> > }
> > +
> > +ofnode ofnode_get_phy_node(ofnode node)
> > +{
> > + /* DT node properties that reference a PHY node */
> > + static const char * const phy_handle_str[] = {
> > + "phy-handle", "phy", "phy-device",
> > + };
> > + struct ofnode_phandle_args args = {
> > + .node = ofnode_null()
> > + };
> > + int i;
> > +
> > + assert(ofnode_valid(node));
> > +
> > + for (i = 0; i < ARRAY_SIZE(phy_handle_str); i++)
> > + if (!ofnode_parse_phandle_with_args(node, phy_handle_str[i],
> > + NULL, 0, 0, ))
> > + break;
> > +
> > + return args.node;
> > +}
> > diff --git a/drivers/core/read.c b/drivers/core/read.c
> > index 31f9e78a06..7ff100218d 100644
> > --- a/drivers/core/read.c
> > +++ b/drivers/core/read.c
> > @@ -398,3 +398,8 @@ int dev_decode_display_timing(const struct udevice
> > *dev, int index,
> > {
> > return ofnode_decode_display_timing(dev_ofnode(dev), index, config);
> > }
> > +
> > +ofnode dev_get_phy_node(const struct udevice *dev)
> > +{
> > + return ofnode_get_phy_node(dev_ofnode(dev));
> > +}
> > diff --git a/include/dm/ofnode.h b/include/dm/ofnode.h
> > index 744dffe0a2..429aee2812 100644
> > --- a/include/dm/ofnode.h
> > +++ b/include/dm/ofnode.h
> > @@ -1217,4 +1217,18 @@ int ofnode_conf_read_int(const char *prop_name, int
> > default_val);
> > */
> > const char *ofnode_conf_read_str(const char *prop_name);
> >
> > +/**
> > + * ofnode_get_phy_node() - Get PHY node for a MAC (if not fixed-link)
> > + *
> > + * This function parses PHY handle from the Ethernet controller's ofnode
> > + * (trying all possible PHY handle property names), and returns the PHY
> > ofnode.
> > + *
> > + * Before this is used, ofnode_phy_is_fixed_link() should be checked
> > first, and
> > + * if the result to that is true, this function should not be called.
> > + *
> > + * @eth_node: ofnode belonging to the Ethernet controller
> > + * Return: ofnode of the PHY, if it exists, otherwise an invalid ofnode
> > + */
> > +ofnode ofnode_get_phy_node(ofnode eth_node);
> > +
> > #endif
> > diff --git a/include/dm/read.h b/include/dm/read.h
> > index 233af3c063..899eb813fd 100644
> > --- a/include/dm/read.h
> > +++ b/include/dm/read.h
> > @@ -743,6 +743,20 @@ int dev_read_pci_bus_range(const struct udevice *dev,
> > struct resource *res);
> > int dev_decode_display_timing(const struct udevice *dev, int index,
> > struct display_timing *config);
> >
> > +/**
> > + * dev_get_phy_node() - Get PHY node for a MAC (if not fixed-link)
> > + *
> > + * This function parses PHY handle from the Ethernet controller's ofnode
> > + * (trying all possible PHY handle property names),
[PATCH] sandbox: Increase default SYS_MALLOC_LEN
Increase the malloc pool on sandbox in order to avoid spurious errors
such as:
___ test_ut[ut_dm_dm_test_video_comp_bmp32]
test/py/tests/test_ut.py:43: in test_ut
assert output.endswith('Failures: 0')
E AssertionError: assert False
E+ where False = ('Failures: 0')
E+where =
'Test: dm_test_video_comp_bmp32: video.c\r\r\nSDL renderer does not
exist\r\r\ntest/dm/video.c:86, compress_frame_buff..._test_video_comp_bmp32():
2024 == compress_frame_buffer(uts, dev): Expected 0x7e8 (2024), got 0x1
(1)\r\r\nFailures: 2'.endswith
Cc: Simon Glass
Cc: Ramon Fried
Signed-off-by: Tom Rini
---
Kconfig| 1 +
configs/sandbox64_defconfig| 1 -
configs/sandbox_defconfig | 1 -
configs/sandbox_flattree_defconfig | 1 -
configs/sandbox_noinst_defconfig | 1 -
configs/sandbox_spl_defconfig | 1 -
6 files changed, 1 insertion(+), 5 deletions(-)
diff --git a/Kconfig b/Kconfig
index 0ee3068b9a66..b45e60a75b93 100644
--- a/Kconfig
+++ b/Kconfig
@@ -263,6 +263,7 @@ config SYS_MALLOC_F_LEN
config SYS_MALLOC_LEN
hex "Define memory for Dynamic allocation"
+ default 0x400 if SANDBOX
default 0x200 if ARCH_ROCKCHIP || ARCH_OMAP2PLUS || ARCH_MESON
default 0x20 if ARCH_BMIPS || X86
default 0x12 if MACH_SUNIV
diff --git a/configs/sandbox64_defconfig b/configs/sandbox64_defconfig
index 88f9ecbb7fce..a13fa2e2c517 100644
--- a/configs/sandbox64_defconfig
+++ b/configs/sandbox64_defconfig
@@ -1,5 +1,4 @@
CONFIG_SYS_TEXT_BASE=0
-CONFIG_SYS_MALLOC_LEN=0x200
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x2000
CONFIG_DEFAULT_DEVICE_TREE="sandbox64"
diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig
index cb8d590eb642..4d3e4f317fca 100644
--- a/configs/sandbox_defconfig
+++ b/configs/sandbox_defconfig
@@ -1,5 +1,4 @@
CONFIG_SYS_TEXT_BASE=0
-CONFIG_SYS_MALLOC_LEN=0x200
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x2000
CONFIG_DEFAULT_DEVICE_TREE="sandbox"
diff --git a/configs/sandbox_flattree_defconfig
b/configs/sandbox_flattree_defconfig
index 24b272068a19..d799f7ddcad3 100644
--- a/configs/sandbox_flattree_defconfig
+++ b/configs/sandbox_flattree_defconfig
@@ -1,5 +1,4 @@
CONFIG_SYS_TEXT_BASE=0
-CONFIG_SYS_MALLOC_LEN=0x200
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x2000
CONFIG_DEFAULT_DEVICE_TREE="sandbox"
diff --git a/configs/sandbox_noinst_defconfig b/configs/sandbox_noinst_defconfig
index 9eefe4f1051c..c9430da0f09e 100644
--- a/configs/sandbox_noinst_defconfig
+++ b/configs/sandbox_noinst_defconfig
@@ -1,5 +1,4 @@
CONFIG_SYS_TEXT_BASE=0x20
-CONFIG_SYS_MALLOC_LEN=0x200
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
diff --git a/configs/sandbox_spl_defconfig b/configs/sandbox_spl_defconfig
index 0092fea76ba7..13a76e89ea52 100644
--- a/configs/sandbox_spl_defconfig
+++ b/configs/sandbox_spl_defconfig
@@ -1,5 +1,4 @@
CONFIG_SYS_TEXT_BASE=0x20
-CONFIG_SYS_MALLOC_LEN=0x200
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
--
2.25.1
Re: RFC: Updating i.MX8M CPU thermal trip-point at runtime
On Thu, Apr 14, 2022 at 3:58 AM Peng Fan (OSS) wrote:
>
>
>
> On 2022/4/14 16:37, Frieder Schrempf wrote:
> > Hi Andrejs,
> >
> > +Cc: Jacky Bai
> >
> > Am 13.04.22 um 14:24 schrieb Andrejs Cainikovs:
> >> [Sie erhalten nicht oft E-Mail von "andrejs.cainik...@toradex.com".
> >> Weitere Informationen, warum dies wichtig ist, finden Sie unter
> >> "http://aka.ms/LearnAboutSenderIdentification;.]
> >>
> >> Hi everyone,
> >>
> >> Recent issue that I had to deal with sparkled a discussion within my
> >> team, and seems like we are not sure what would be a proper way to go,
> >> even if there are multiple ways to do it. We decided to ask this
> >> question to open-source community, in case someone has thoughts about it.
> >>
> >> At Toradex we have multiple computer on modules, each of those has few
> >> variants - different memory sizes, with or without WiFi/BT, etc. One of
> >> the options is also a temperature grade - IT and non-IT. Obviously, we
> >> want to keep number of device trees as minimal as possible, since number
> >> of device trees grows exponentially if we add a new option via device
> >> tree, i.e. imx8mm-verdin-it-wifi-dev.dts +
> >> imx8mm-verdin-nonit-wifi-dev.dts.
> >>
> >> Hence, we are working on a change that would update trips temperatures
> >> in Linux device tree on the fly, setting them to whatever is read from
> >> CPU fuses. Now, the question is - where would be the best place to do
> >> it? So far we were thinking about following options:
> >>
> >> - Patching U-Boot thermal driver so that it would propagate max
> >> temperature to Linux device tree.
> >> - Patching U-Boot board files to update Linux device tree via
> >> ft_board_setup(). This, however, will result in a duplicate code among
> >> different boards within same SoC family.
> >> - Anything else not listed here.
> >>
> >> I would appreciate any comments or thoughts regarding this topic. Thanks,
> >
> > Thanks for bringing up the topic. We've been discussing this previously
> > here: [1].
> >
> > The bootloader doesn't really benefit from the information about the
> > temperature grading, does it? Therefore I would rather think about a
> > solution where the kernel itself, or more specifically the TMU driver
> > reads the grading from the fuses and sets the trip points accordingly.
> > So we don't create another dependency between bootloader and kernel.
> >
> > Anyway, if you rather want to handle this in the bootloader and pass it
> > via device tree, I guess this would also be ok. In this case the code
> > should be added to the thermal driver or the platform code and not in
> > any board specific files to avoid duplication, as you already mentioned.
>
> I would prefer let bootloader handle this, that would be simple.
>
> Regards,
> Peng.
>
> >
> > Best regards
> > Frieder
> >
> > [1]
> > https://patchwork.kernel.org/project/linux-arm-kernel/patch/20210601174917.1979-1-thar...@gateworks.com/
> >
If you want to do it within the bootloader, dynamic during
ft_board_setup look at: f8a792e51d17 ("board: gateworks: venice:
update thermal temp thresholds per cpu grade")
I see no reason why this eventually couldn't be moved to somewhere
imx8m specific. I do agree the kernel should be doing this on its own
but as mentioned in the discussion it's not as simple.
Best Regards,
Tim
Re: [PATCH] ARM: imx: imx8m: Fix board_get_usable_ram_top()
Am 14.04.22 um 15:51 schrieb Marek Vasut:
> The 4 GiB boundary is at 0x+1 , not at 0x8000, fix this.
>
> The PHYS_SDRAM of i.MX8M is at 0x4000 , so to restrict ram_top
> below 4 GiB, the ram_top has to be set to 0x as it is not
> an offset from the start of PHYS_SDRAM, but rather a physical address
> marking the topmost allowed DRAM address.
>
> Fixes: e27bddff4b9 ("imx8m: Restrict usable memory to space below 4G
> boundary")
> Signed-off-by: Marek Vasut
Thanks for the fix!
Reviewed-by: Frieder Schrempf
> Cc: Fabio Estevam
> Cc: Frieder Schrempf
> Cc: Peng Fan
> Cc: Stefano Babic
> ---
> arch/arm/mach-imx/imx8m/soc.c | 5 ++---
> 1 file changed, 2 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c
> index 8171631db10..e7fe7c2fd88 100644
> --- a/arch/arm/mach-imx/imx8m/soc.c
> +++ b/arch/arm/mach-imx/imx8m/soc.c
> @@ -331,7 +331,7 @@ phys_size_t get_effective_memsize(void)
>
> ulong board_get_usable_ram_top(ulong total_size)
> {
> - ulong top_addr = PHYS_SDRAM + gd->ram_size;
> + ulong top_addr;
>
> /*
>* Some IPs have their accessible address space restricted by
> @@ -339,8 +339,7 @@ ulong board_get_usable_ram_top(ulong total_size)
>* space below the 4G address boundary (which is 3GiB big),
>* even when the effective available memory is bigger.
>*/
> - if (top_addr > 0x8000)
> - top_addr = 0x8000;
> + top_addr = clamp_val((u64)PHYS_SDRAM + gd->ram_size, 0, 0x);
>
> /*
>* rom_pointer[0] stores the TEE memory start address.
Re: [PATCH] ARM: imx: imx8m: Fix board_get_usable_ram_top()
Hi Marek,
On 14/04/2022 10:51, Marek Vasut wrote:
The 4 GiB boundary is at 0x+1 , not at 0x8000, fix this.
The PHYS_SDRAM of i.MX8M is at 0x4000 , so to restrict ram_top
below 4 GiB, the ram_top has to be set to 0x as it is not
an offset from the start of PHYS_SDRAM, but rather a physical address
marking the topmost allowed DRAM address.
Fixes: e27bddff4b9 ("imx8m: Restrict usable memory to space below 4G
boundary")
Signed-off-by: Marek Vasut
Cc: Fabio Estevam
Cc: Frieder Schrempf
Cc: Peng Fan
Cc: Stefano Babic
Good catch!
Reviewed-by: Fabio Estevam
[PATCH 2/2] led: pwm: Drop duplicate OF "label" property parsing
The OF "label" property parsing is now handled in LED core,
drop the duplicate implementation from this driver.
Signed-off-by: Tom Rini
---
drivers/led/led_pwm.c | 10 --
1 file changed, 10 deletions(-)
diff --git a/drivers/led/led_pwm.c b/drivers/led/led_pwm.c
index 4e5027225870..10bd1636c386 100644
--- a/drivers/led/led_pwm.c
+++ b/drivers/led/led_pwm.c
@@ -151,21 +151,11 @@ static int led_pwm_bind(struct udevice *parent)
int ret;
dev_for_each_subnode(node, parent) {
- struct led_uc_plat *uc_plat;
- const char *label;
-
- label = ofnode_read_string(node, "label");
- if (!label)
- label = ofnode_get_name(node);
-
ret = device_bind_driver_to_node(parent, LEDS_PWM_DRIVER_NAME,
ofnode_get_name(node),
node, );
if (ret)
return ret;
-
- uc_plat = dev_get_uclass_plat(dev);
- uc_plat->label = label;
}
return 0;
}
--
2.25.1
[PATCH 1/2] led: bcm6753: Drop duplicate OF "label" property parsing
The OF "label" property parsing is now handled in LED core,
drop the duplicate implementation from this driver.
Signed-off-by: Tom Rini
---
drivers/led/led_bcm6753.c | 12
1 file changed, 12 deletions(-)
diff --git a/drivers/led/led_bcm6753.c b/drivers/led/led_bcm6753.c
index a32bd8204fa0..88b650cbfca3 100644
--- a/drivers/led/led_bcm6753.c
+++ b/drivers/led/led_bcm6753.c
@@ -229,26 +229,14 @@ static int bcm6753_led_bind(struct udevice *parent)
ofnode node;
dev_for_each_subnode(node, parent) {
- struct led_uc_plat *uc_plat;
struct udevice *dev;
- const char *label;
int ret;
- label = ofnode_read_string(node, "label");
- if (!label) {
- debug("%s: node %s has no label\n", __func__,
- ofnode_get_name(node));
- return -EINVAL;
- }
-
ret = device_bind_driver_to_node(parent, "bcm6753-led",
ofnode_get_name(node),
node, );
if (ret)
return ret;
-
- uc_plat = dev_get_uclass_plat(dev);
- uc_plat->label = label;
}
return 0;
--
2.25.1
[PATCH v2 12/12] virtio_ring: Reduce logging noise
Demote logs about problems with the vrings to debug level rather than
always logging. This reduces noise from the logs, especially in the fuzz
test where these cases get reached frequently.
Signed-off-by: Andrew Scull
---
drivers/virtio/virtio_ring.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/virtio/virtio_ring.c b/drivers/virtio/virtio_ring.c
index 383d574cb0..b369bf1dc2 100644
--- a/drivers/virtio/virtio_ring.c
+++ b/drivers/virtio/virtio_ring.c
@@ -197,13 +197,13 @@ void *virtqueue_get_buf(struct virtqueue *vq, unsigned
int *len)
}
if (unlikely(i >= vq->vring.num)) {
- printf("(%s.%d): id %u out of range\n",
+ debug("(%s.%d): id %u out of range\n",
vq->vdev->name, vq->index, i);
return NULL;
}
if (unlikely(!vq->vring_desc_shadow[i].chain_head)) {
- printf("(%s.%d): id %u is not a head\n",
+ debug("(%s.%d): id %u is not a head\n",
vq->vdev->name, vq->index, i);
return NULL;
}
--
2.35.1.1178.g4f1659d476-goog
[PATCH v2 07/12] test: fuzz: Add framework for fuzzing
Add the basic infrastructure for declaring fuzz tests and a command to
invoke them.
Signed-off-by: Andrew Scull
Reviewed-by: Simon Glass
---
Kconfig | 9 +
include/test/fuzz.h | 51 +++
test/Makefile| 1 +
test/fuzz/Makefile | 7
test/fuzz/cmd_fuzz.c | 82
5 files changed, 150 insertions(+)
create mode 100644 include/test/fuzz.h
create mode 100644 test/fuzz/Makefile
create mode 100644 test/fuzz/cmd_fuzz.c
diff --git a/Kconfig b/Kconfig
index a2577bcce6..1d472a7862 100644
--- a/Kconfig
+++ b/Kconfig
@@ -161,6 +161,15 @@ config ASAN
Enables AddressSanitizer to discover out-of-bounds accesses,
use-after-free, double-free and memory leaks.
+config FUZZ
+ bool "Enable fuzzing"
+ depends on CC_IS_CLANG
+ depends on DM_FUZZING_ENGINE
+ select ASAN
+ help
+ Enables the fuzzing infrastructure to generate fuzzing data and run
+ fuzz tests.
+
config CC_HAS_ASM_INLINE
def_bool $(success,echo 'void foo(void) { asm inline (""); }' | $(CC)
-x c - -c -o /dev/null)
diff --git a/include/test/fuzz.h b/include/test/fuzz.h
new file mode 100644
index 00..d4c57540eb
--- /dev/null
+++ b/include/test/fuzz.h
@@ -0,0 +1,51 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2022 Google, Inc.
+ * Written by Andrew Scull
+ */
+
+#ifndef __TEST_FUZZ_H
+#define __TEST_FUZZ_H
+
+#include
+#include
+
+/**
+ * struct fuzz_test - Information about a fuzz test
+ *
+ * @name: Name of fuzz test
+ * @func: Function to call to perform fuzz test on an input
+ * @flags: Flags indicate pre-conditions for fuzz test
+ */
+struct fuzz_test {
+ const char *name;
+ int (*func)(const uint8_t * data, size_t size);
+ int flags;
+};
+
+/**
+ * FUZZ_TEST() - register a fuzz test
+ *
+ * The fuzz test function must return 0 as other values are reserved for future
+ * use.
+ *
+ * @_name: the name of the fuzz test function
+ * @_flags:an integer field that can be evaluated by the fuzzer
+ * implementation
+ */
+#define FUZZ_TEST(_name, _flags) \
+ ll_entry_declare(struct fuzz_test, _name, fuzz_tests) = { \
+ .name = #_name, \
+ .func = _name, \
+ .flags = _flags,\
+ }
+
+/** Get the start of the list of fuzz tests */
+#define FUZZ_TEST_START() \
+ ll_entry_start(struct fuzz_test, fuzz_tests)
+
+/** Get the number of elements in the list of fuzz tests */
+#define FUZZ_TEST_COUNT() \
+ ll_entry_count(struct fuzz_test, fuzz_tests)
+
+#endif /* __TEST_FUZZ_H */
diff --git a/test/Makefile b/test/Makefile
index b3b2902e2e..bb2b0b5c73 100644
--- a/test/Makefile
+++ b/test/Makefile
@@ -16,6 +16,7 @@ obj-$(CONFIG_$(SPL_)CMDLINE) += cmd_ut.o
obj-$(CONFIG_$(SPL_)CMDLINE) += command_ut.o
obj-$(CONFIG_$(SPL_)UT_COMPRESSION) += compression.o
obj-y += dm/
+obj-$(CONFIG_FUZZ) += fuzz/
obj-$(CONFIG_$(SPL_)CMDLINE) += print_ut.o
obj-$(CONFIG_$(SPL_)CMDLINE) += str_ut.o
obj-$(CONFIG_UT_TIME) += time_ut.o
diff --git a/test/fuzz/Makefile b/test/fuzz/Makefile
new file mode 100644
index 00..03b497
--- /dev/null
+++ b/test/fuzz/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (c) 2022 Google, Inc.
+# Written by Andrew Scull
+#
+
+obj-$(CONFIG_$(SPL_)CMDLINE) += cmd_fuzz.o
diff --git a/test/fuzz/cmd_fuzz.c b/test/fuzz/cmd_fuzz.c
new file mode 100644
index 00..0cc01dc199
--- /dev/null
+++ b/test/fuzz/cmd_fuzz.c
@@ -0,0 +1,82 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2022 Google, Inc.
+ * Written by Andrew Scull
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+static struct fuzz_test *find_fuzz_test(const char *name)
+{
+ struct fuzz_test *fuzzer = FUZZ_TEST_START();
+ size_t count = FUZZ_TEST_COUNT();
+ size_t i;
+
+ for (i = 0; i < count; ++i) {
+ if (strcmp(name, fuzzer->name) == 0)
+ return fuzzer;
+ ++fuzzer;
+ }
+
+ return NULL;
+}
+
+static struct udevice *find_fuzzing_engine(void)
+{
+ struct udevice *dev;
+
+ if (uclass_first_device(UCLASS_FUZZING_ENGINE, ))
+ return NULL;
+
+ return dev;
+}
+
+static int do_fuzz(struct cmd_tbl *cmdtp, int flag, int argc, char *const
argv[])
+{
+ struct fuzz_test *fuzzer;
+ struct udevice *dev;
+
+ if (argc != 2)
+ return CMD_RET_USAGE;
+
+ fuzzer = find_fuzz_test(argv[1]);
+ if (!fuzzer) {
+ printf("Could not find fuzzer: %s\n", argv[1]);
+ return 1;
+ }
+
+ dev = find_fuzzing_engine();
+ if (!dev) {
+ puts("No fuzzing engine available\n");
+
[PATCH v2 06/12] fuzzing_engine: Add fuzzing engine uclass
This new class of device will provide fuzzing inputs from a fuzzing
engine.
Signed-off-by: Andrew Scull
Reviewed-by: Simon Glass
---
drivers/Kconfig | 2 ++
drivers/Makefile | 1 +
drivers/fuzz/Kconfig | 9 +
drivers/fuzz/Makefile| 7
drivers/fuzz/fuzzing_engine-uclass.c | 28 +++
include/dm/uclass-id.h | 1 +
include/fuzzing_engine.h | 51
7 files changed, 99 insertions(+)
create mode 100644 drivers/fuzz/Kconfig
create mode 100644 drivers/fuzz/Makefile
create mode 100644 drivers/fuzz/fuzzing_engine-uclass.c
create mode 100644 include/fuzzing_engine.h
diff --git a/drivers/Kconfig b/drivers/Kconfig
index b26ca8cf70..8b6fead351 100644
--- a/drivers/Kconfig
+++ b/drivers/Kconfig
@@ -40,6 +40,8 @@ source "drivers/fastboot/Kconfig"
source "drivers/firmware/Kconfig"
+source "drivers/fuzz/Kconfig"
+
source "drivers/fpga/Kconfig"
source "drivers/gpio/Kconfig"
diff --git a/drivers/Makefile b/drivers/Makefile
index 4e7cf28440..b66d72d361 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -113,6 +113,7 @@ obj-$(CONFIG_W1) += w1/
obj-$(CONFIG_W1_EEPROM) += w1-eeprom/
obj-$(CONFIG_MACH_PIC32) += ddr/microchip/
+obj-$(CONFIG_FUZZ) += fuzz/
obj-$(CONFIG_DM_HWSPINLOCK) += hwspinlock/
obj-$(CONFIG_DM_RNG) += rng/
endif
diff --git a/drivers/fuzz/Kconfig b/drivers/fuzz/Kconfig
new file mode 100644
index 00..a03120f63a
--- /dev/null
+++ b/drivers/fuzz/Kconfig
@@ -0,0 +1,9 @@
+config DM_FUZZING_ENGINE
+ bool "Driver support for fuzzing engine devices"
+ depends on DM
+ help
+ Enable driver model for fuzzing engine devices. This interface is
+ used to get successive inputs from a fuzzing engine that aims to
+ explore different code paths in a fuzz test. The fuzzing engine may
+ be instrumenting the execution in order to more effectively generate
+ inputs that explore different code paths.
diff --git a/drivers/fuzz/Makefile b/drivers/fuzz/Makefile
new file mode 100644
index 00..acd894999c
--- /dev/null
+++ b/drivers/fuzz/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (c) 2022 Google, Inc.
+# Written by Andrew Scull
+#
+
+obj-$(CONFIG_DM_FUZZING_ENGINE) += fuzzing_engine-uclass.o
diff --git a/drivers/fuzz/fuzzing_engine-uclass.c
b/drivers/fuzz/fuzzing_engine-uclass.c
new file mode 100644
index 00..b16f1c4cfb
--- /dev/null
+++ b/drivers/fuzz/fuzzing_engine-uclass.c
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2022 Google, Inc.
+ * Written by Andrew Scull
+ */
+
+#define LOG_CATEGORY UCLASS_FUZZING_ENGINE
+
+#include
+#include
+#include
+
+int dm_fuzzing_engine_get_input(struct udevice *dev,
+ const uint8_t **data,
+ size_t *size)
+{
+ const struct dm_fuzzing_engine_ops *ops = device_get_ops(dev);
+
+ if (!ops->get_input)
+ return -ENOSYS;
+
+ return ops->get_input(dev, data, size);
+}
+
+UCLASS_DRIVER(fuzzing_engine) = {
+ .name = "fuzzing_engine",
+ .id = UCLASS_FUZZING_ENGINE,
+};
diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h
index 0e26e1d138..b9411f1d59 100644
--- a/include/dm/uclass-id.h
+++ b/include/dm/uclass-id.h
@@ -53,6 +53,7 @@ enum uclass_id {
UCLASS_ETH, /* Ethernet device */
UCLASS_ETH_PHY, /* Ethernet PHY device */
UCLASS_FIRMWARE,/* Firmware */
+ UCLASS_FUZZING_ENGINE, /* Fuzzing engine */
UCLASS_FS_FIRMWARE_LOADER, /* Generic loader */
UCLASS_GPIO,/* Bank of general-purpose I/O pins */
UCLASS_HASH,/* Hash device */
diff --git a/include/fuzzing_engine.h b/include/fuzzing_engine.h
new file mode 100644
index 00..357346e93d
--- /dev/null
+++ b/include/fuzzing_engine.h
@@ -0,0 +1,51 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2022 Google, Inc.
+ * Written by Andrew Scull
+ */
+
+#ifndef __FUZZING_ENGINE_H
+#define __FUZZING_ENGINE_H
+
+struct udevice;
+
+/**
+ * dm_fuzzing_engine_get_input() - get an input from the fuzzing engine device
+ *
+ * The function will return a pointer to the input data and the size of the
+ * data pointed to. The pointer will remain valid until the next invocation of
+ * this function.
+ *
+ * @dev: fuzzing engine device
+ * @data: output pointer to input data
+ * @size output size of input data
+ * Return: 0 if OK, -ve on error
+ */
+int dm_fuzzing_engine_get_input(struct udevice *dev,
+ const uint8_t **data,
+ size_t *size);
+
+/**
+ * struct dm_fuzzing_engine_ops - operations for the fuzzing engine uclass
+ *
+ * This contains the functions implemented by a fuzzing engine device.
+ */
+struct
[PATCH v2 05/12] sandbox: Add support for Address Sanitizer
Add CONFIG_ASAN to build with the Address Sanitizer. This only works
with the sandbox so the config is likewise dependent. The resulting
executable will have ASAN instrumentation, including the leak detector
that can be disabled with the ASAN_OPTIONS environment variable:
ASAN_OPTIONS=detect_leaks=0 ./u-boot
Since u-boot uses its own dlmalloc, dynamic allocations aren't
automatically instrumented, but stack variables and globals are.
Instrumentation could be added to dlmalloc to poison and unpoison memory
as it is allocated and deallocated, and to introduce redzones between
allocations. Alternatively, the sandbox may be able to play games with
the system allocator and somehow still keep the required memory
abstraction. No effort to address dynamic allocation is made by this
patch.
Signed-off-by: Andrew Scull
Reviewed-by: Simon Glass
---
Kconfig | 7 +++
arch/sandbox/config.mk| 8
configs/sandbox_defconfig | 1 +
3 files changed, 16 insertions(+)
diff --git a/Kconfig b/Kconfig
index 0ee3068b9a..a2577bcce6 100644
--- a/Kconfig
+++ b/Kconfig
@@ -154,6 +154,13 @@ config CC_COVERAGE
Enabling this option will pass "--coverage" to gcc to compile
and link code instrumented for coverage analysis.
+config ASAN
+ bool "Enable AddressSanitizer"
+ depends on SANDBOX
+ help
+ Enables AddressSanitizer to discover out-of-bounds accesses,
+ use-after-free, double-free and memory leaks.
+
config CC_HAS_ASM_INLINE
def_bool $(success,echo 'void foo(void) { asm inline (""); }' | $(CC)
-x c - -c -o /dev/null)
diff --git a/arch/sandbox/config.mk b/arch/sandbox/config.mk
index c42de2ff27..d7ce66fb6c 100644
--- a/arch/sandbox/config.mk
+++ b/arch/sandbox/config.mk
@@ -15,7 +15,14 @@ PLATFORM_LIBS += $(shell $(SDL_CONFIG) --libs)
PLATFORM_CPPFLAGS += $(shell $(SDL_CONFIG) --cflags)
endif
+SANITIZERS :=
+ifdef CONFIG_ASAN
+SANITIZERS += -fsanitize=address
+endif
+KBUILD_CFLAGS += $(SANITIZERS)
+
cmd_u-boot__ = $(CC) -o $@ -Wl,-T u-boot.lds $(u-boot-init) \
+ $(SANITIZERS) \
$(LTO_FINAL_LDFLAGS) \
-Wl,--whole-archive \
$(u-boot-main) \
@@ -24,6 +31,7 @@ cmd_u-boot__ = $(CC) -o $@ -Wl,-T u-boot.lds $(u-boot-init) \
$(PLATFORM_LIBS) -Wl,-Map -Wl,u-boot.map
cmd_u-boot-spl = (cd $(obj) && $(CC) -o $(SPL_BIN) -Wl,-T u-boot-spl.lds \
+ $(SANITIZERS) \
$(LTO_FINAL_LDFLAGS) \
$(patsubst $(obj)/%,%,$(u-boot-spl-init)) \
-Wl,--whole-archive \
diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig
index cb8d590eb6..462a0afb2e 100644
--- a/configs/sandbox_defconfig
+++ b/configs/sandbox_defconfig
@@ -1,3 +1,4 @@
+CONFIG_ASAN=y
CONFIG_SYS_TEXT_BASE=0
CONFIG_SYS_MALLOC_LEN=0x200
CONFIG_NR_DRAM_BANKS=1
--
2.35.1.1178.g4f1659d476-goog
[PATCH v2 04/12] linker_lists: Rename sections to remove . prefix
Rename the sections used to implement linker lists so they begin with
'__u_boot_list' rather than '.u_boot_list'. The double underscore at the
start is still distinct from the single underscore used by the symbol
names.
Having a '.' in the section names conflicts with clang's ASAN
instrumentation which tries to add redzones between the linker list
elements, causing expected accesses to fail. However, clang doesn't try
to add redzones to user sections, which are names with all alphanumeric
and underscore characters.
Signed-off-by: Andrew Scull
Reviewed-by: Simon Glass
---
arch/arc/cpu/u-boot.lds | 4 ++--
arch/arm/config.mk| 4 ++--
arch/arm/cpu/arm926ejs/sunxi/u-boot-spl.lds | 4 ++--
arch/arm/cpu/armv7/sunxi/u-boot-spl.lds | 4 ++--
arch/arm/cpu/armv8/u-boot-spl.lds | 4 ++--
arch/arm/cpu/armv8/u-boot.lds | 4 ++--
arch/arm/cpu/u-boot-spl.lds | 4 ++--
arch/arm/cpu/u-boot.lds | 6 ++---
arch/arm/mach-at91/arm926ejs/u-boot-spl.lds | 2 +-
arch/arm/mach-at91/armv7/u-boot-spl.lds | 2 +-
arch/arm/mach-omap2/u-boot-spl.lds| 4 ++--
arch/arm/mach-orion5x/u-boot-spl.lds | 4 ++--
arch/arm/mach-rockchip/u-boot-tpl-v8.lds | 4 ++--
arch/arm/mach-zynq/u-boot-spl.lds | 4 ++--
arch/arm/mach-zynq/u-boot.lds | 4 ++--
arch/m68k/cpu/u-boot.lds | 4 ++--
arch/microblaze/cpu/u-boot-spl.lds| 4 ++--
arch/microblaze/cpu/u-boot.lds| 4 ++--
arch/mips/config.mk | 2 +-
arch/mips/cpu/u-boot-spl.lds | 4 ++--
arch/mips/cpu/u-boot.lds | 4 ++--
arch/nds32/cpu/n1213/u-boot.lds | 4 ++--
arch/nios2/cpu/u-boot.lds | 4 ++--
arch/powerpc/cpu/mpc83xx/u-boot.lds | 4 ++--
arch/powerpc/cpu/mpc85xx/u-boot-nand.lds | 4 ++--
arch/powerpc/cpu/mpc85xx/u-boot-nand_spl.lds | 4 ++--
arch/powerpc/cpu/mpc85xx/u-boot-spl.lds | 4 ++--
arch/powerpc/cpu/mpc85xx/u-boot.lds | 4 ++--
arch/riscv/cpu/u-boot-spl.lds | 4 ++--
arch/riscv/cpu/u-boot.lds | 4 ++--
arch/sandbox/config.mk| 4 ++--
arch/sandbox/cpu/u-boot-spl.lds | 4 ++--
arch/sandbox/cpu/u-boot.lds | 4 ++--
arch/sh/cpu/u-boot.lds| 4 ++--
arch/x86/cpu/u-boot-64.lds| 6 ++---
arch/x86/cpu/u-boot-spl.lds | 6 ++---
arch/x86/cpu/u-boot.lds | 6 ++---
arch/x86/lib/elf_ia32_efi.lds | 4 ++--
arch/x86/lib/elf_x86_64_efi.lds | 4 ++--
arch/xtensa/cpu/u-boot.lds| 2 +-
arch/xtensa/include/asm/ldscript.h| 4 ++--
board/compulab/cm_t335/u-boot.lds | 4 ++--
board/cssi/MCR3000/u-boot.lds | 4 ++--
.../davinci/da8xxevm/u-boot-spl-da850evm.lds | 2 +-
board/qualcomm/dragonboard820c/u-boot.lds | 4 ++--
board/samsung/common/exynos-uboot-spl.lds | 4 ++--
board/synopsys/iot_devkit/u-boot.lds | 4 ++--
board/ti/am335x/u-boot.lds| 4 ++--
board/vscom/baltos/u-boot.lds | 4 ++--
doc/api/linker_lists.rst | 22 +--
doc/develop/commands.rst | 4 ++--
doc/develop/driver-model/of-plat.rst | 4 ++--
include/linker_lists.h| 18 +++
53 files changed, 121 insertions(+), 121 deletions(-)
diff --git a/arch/arc/cpu/u-boot.lds b/arch/arc/cpu/u-boot.lds
index e12145c768..9f2973da65 100644
--- a/arch/arc/cpu/u-boot.lds
+++ b/arch/arc/cpu/u-boot.lds
@@ -39,8 +39,8 @@ SECTIONS
}
. = ALIGN(4);
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
+ __u_boot_list : {
+ KEEP(*(SORT(__u_boot_list*)));
}
. = ALIGN(4);
diff --git a/arch/arm/config.mk b/arch/arm/config.mk
index b107b1af27..b3548ce243 100644
--- a/arch/arm/config.mk
+++ b/arch/arm/config.mk
@@ -141,11 +141,11 @@ endif
# limit ourselves to the sections we want in the .bin.
ifdef CONFIG_ARM64
OBJCOPYFLAGS += -j .text -j .secure_text -j .secure_data -j .rodata -j .data \
- -j .u_boot_list -j .rela.dyn -j .got -j .got.plt \
+ -j __u_boot_list -j .rela.dyn -j .got -j .got.plt \
-j .binman_sym_table -j .text_rest
else
OBJCOPYFLAGS += -j .text -j .secure_text -j .secure_data -j .rodata -j .hash \
- -j .data -j .got -j .got.plt -j .u_boot_list -j .rel.dyn \
+ -j .data -j .got -j .got.plt -j __u_boot_list -j .rel.dyn \
-j .binman_sym_table -j .text_rest
endif
diff --git a/arch/arm/cpu/arm926ejs/sunxi/u-boot-spl.lds
b/arch/arm/cpu/arm926ejs/sunxi/u-boot-spl.lds
index
[PATCH v2 03/12] sandbox: Migrate getopt section to linker list
Use the common infrastructure to create a linker list of the sandbox
command line flags rather than using a custom method.
The list is changed from containing pointers to containing structs and
the uses are updated accordingly.
Signed-off-by: Andrew Scull
Reviewed-by: Simon Glass
---
arch/sandbox/cpu/os.c | 21 ++---
arch/sandbox/cpu/start.c| 10 +-
arch/sandbox/cpu/u-boot-spl.lds | 6 --
arch/sandbox/cpu/u-boot.lds | 6 --
arch/sandbox/include/asm/getopt.h | 19 ---
arch/sandbox/include/asm/sections.h | 25 -
6 files changed, 27 insertions(+), 60 deletions(-)
diff --git a/arch/sandbox/cpu/os.c b/arch/sandbox/cpu/os.c
index d83c862182..72a72029f2 100644
--- a/arch/sandbox/cpu/os.c
+++ b/arch/sandbox/cpu/os.c
@@ -424,9 +424,8 @@ static struct option *long_opts;
int os_parse_args(struct sandbox_state *state, int argc, char *argv[])
{
- struct sandbox_cmdline_option **sb_opt =
- __u_boot_sandbox_option_start();
- size_t num_options = __u_boot_sandbox_option_count();
+ struct sandbox_cmdline_option *sb_opt = SANDBOX_CMDLINE_OPT_START();
+ size_t num_options = SANDBOX_CMDLINE_OPT_COUNT();
size_t i;
int hidden_short_opt;
@@ -455,17 +454,17 @@ int os_parse_args(struct sandbox_state *state, int argc,
char *argv[])
hidden_short_opt = 0x100;
si = 0;
for (i = 0; i < num_options; ++i) {
- long_opts[i].name = sb_opt[i]->flag;
- long_opts[i].has_arg = sb_opt[i]->has_arg ?
+ long_opts[i].name = sb_opt[i].flag;
+ long_opts[i].has_arg = sb_opt[i].has_arg ?
required_argument : no_argument;
long_opts[i].flag = NULL;
- if (sb_opt[i]->flag_short) {
- short_opts[si++] = long_opts[i].val =
sb_opt[i]->flag_short;
+ if (sb_opt[i].flag_short) {
+ short_opts[si++] = long_opts[i].val =
sb_opt[i].flag_short;
if (long_opts[i].has_arg == required_argument)
short_opts[si++] = ':';
} else
- long_opts[i].val = sb_opt[i]->flag_short =
hidden_short_opt++;
+ long_opts[i].val = sb_opt[i].flag_short =
hidden_short_opt++;
}
short_opts[si] = '\0';
@@ -480,9 +479,9 @@ int os_parse_args(struct sandbox_state *state, int argc,
char *argv[])
*/
while ((c = getopt_long(argc, argv, short_opts, long_opts, NULL)) !=
-1) {
for (i = 0; i < num_options; ++i) {
- if (sb_opt[i]->flag_short == c) {
- if (sb_opt[i]->callback(state, optarg)) {
- state->parse_err = sb_opt[i]->flag;
+ if (sb_opt[i].flag_short == c) {
+ if (sb_opt[i].callback(state, optarg)) {
+ state->parse_err = sb_opt[i].flag;
return 0;
}
break;
diff --git a/arch/sandbox/cpu/start.c b/arch/sandbox/cpu/start.c
index 0f5a87309d..6bcb8ffa28 100644
--- a/arch/sandbox/cpu/start.c
+++ b/arch/sandbox/cpu/start.c
@@ -59,9 +59,8 @@ static int h_compare_opt(const void *p1, const void *p2)
int sandbox_early_getopt_check(void)
{
struct sandbox_state *state = state_get_current();
- struct sandbox_cmdline_option **sb_opt =
- __u_boot_sandbox_option_start();
- size_t num_options = __u_boot_sandbox_option_count();
+ struct sandbox_cmdline_option *sb_opt = SANDBOX_CMDLINE_OPT_START();
+ size_t num_options = SANDBOX_CMDLINE_OPT_COUNT();
size_t i;
int max_arg_len, max_noarg_len;
struct sandbox_cmdline_option **sorted_opt;
@@ -85,7 +84,7 @@ int sandbox_early_getopt_check(void)
max_arg_len = 0;
for (i = 0; i < num_options; ++i)
- max_arg_len = max((int)strlen(sb_opt[i]->flag), max_arg_len);
+ max_arg_len = max((int)strlen(sb_opt[i].flag), max_arg_len);
max_noarg_len = max_arg_len + 7;
/* Sort the options */
@@ -95,7 +94,8 @@ int sandbox_early_getopt_check(void)
printf("No memory to sort options\n");
os_exit(1);
}
- memcpy(sorted_opt, sb_opt, size);
+ for (i = 0; i < num_options; ++i)
+ sorted_opt[i] = _opt[i];
qsort(sorted_opt, num_options, sizeof(*sorted_opt), h_compare_opt);
for (i = 0; i < num_options; ++i) {
diff --git a/arch/sandbox/cpu/u-boot-spl.lds b/arch/sandbox/cpu/u-boot-spl.lds
index 6754f4ef6c..5c19d090cb 100644
--- a/arch/sandbox/cpu/u-boot-spl.lds
+++ b/arch/sandbox/cpu/u-boot-spl.lds
@@ -20,12 +20,6 @@ SECTIONS
[PATCH v2 02/12] sandbox: Rename EFI runtime sections
Rename the sections used for placing the EFI runtime so they don't start
with a '.'. ELF says that sections starting with a '.' are reserved for
system use whereas they are actually user sections in sandbox.
When they weren't user sections, clang's ASAN added redzones to the
sections and the extra padding meant that the relocation list was no
longer in the expected format. Naming the sections as user sections
resolves this issue.
Signed-off-by: Andrew Scull
---
arch/sandbox/cpu/u-boot.lds | 22 ++
arch/sandbox/lib/sections.c | 8
2 files changed, 14 insertions(+), 16 deletions(-)
diff --git a/arch/sandbox/cpu/u-boot.lds b/arch/sandbox/cpu/u-boot.lds
index 64db801018..7abe232ad9 100644
--- a/arch/sandbox/cpu/u-boot.lds
+++ b/arch/sandbox/cpu/u-boot.lds
@@ -19,33 +19,31 @@ SECTIONS
*(.u_boot_sandbox_getopt_end)
}
- .__efi_runtime_start : {
- *(.__efi_runtime_start)
+ efi_runtime_start : {
+ *(___efi_runtime_start)
}
- .efi_runtime : {
+ efi_runtime : {
*(.text.efi_runtime*)
*(.rodata.efi_runtime*)
*(.data.efi_runtime*)
}
- .__efi_runtime_stop : {
- *(.__efi_runtime_stop)
+ efi_runtime_stop : {
+ *(___efi_runtime_stop)
}
- .efi_runtime_rel_start :
- {
- *(.__efi_runtime_rel_start)
+ efi_runtime_rel_start : {
+ *(___efi_runtime_rel_start)
}
- .efi_runtime_rel : {
+ efi_runtime_rel : {
*(.rel*.efi_runtime)
*(.rel*.efi_runtime.*)
}
- .efi_runtime_rel_stop :
- {
- *(.__efi_runtime_rel_stop)
+ efi_runtime_rel_stop : {
+ *(___efi_runtime_rel_stop)
}
.dynsym :
diff --git a/arch/sandbox/lib/sections.c b/arch/sandbox/lib/sections.c
index 2559eeea38..2f2f3fbfdb 100644
--- a/arch/sandbox/lib/sections.c
+++ b/arch/sandbox/lib/sections.c
@@ -5,9 +5,9 @@
*/
#include
-char __efi_runtime_start[0] __section(".__efi_runtime_start");
-char __efi_runtime_stop[0] __section(".__efi_runtime_stop");
+char __efi_runtime_start[0] __section("___efi_runtime_start");
+char __efi_runtime_stop[0] __section("___efi_runtime_stop");
char __efi_runtime_rel_start[0]
- __section(".__efi_runtime_rel_start");
+ __section("___efi_runtime_rel_start");
char __efi_runtime_rel_stop[0]
- __section(".__efi_runtime_rel_stop");
+ __section("___efi_runtime_rel_stop");
--
2.35.1.1178.g4f1659d476-goog
[PATCH v2 01/12] sandbox: Fix EFI runtime symbol placement
The EFI symbols are collected in subsections of the .text, .rodata,
.data and .rel sections. Use those when creating EFI runtime sections.
Fixes: 7bf07cf872 (Partially revert "efi_loader: Rename sections to allow for
implicit data")
Signed-off-by: Andrew Scull
Cc: Heinrich Schuchardt
Cc: Simon Glass
---
arch/sandbox/cpu/u-boot.lds | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/arch/sandbox/cpu/u-boot.lds b/arch/sandbox/cpu/u-boot.lds
index 6d710618f5..64db801018 100644
--- a/arch/sandbox/cpu/u-boot.lds
+++ b/arch/sandbox/cpu/u-boot.lds
@@ -24,8 +24,9 @@ SECTIONS
}
.efi_runtime : {
- *(efi_runtime_text)
- *(efi_runtime_data)
+ *(.text.efi_runtime*)
+ *(.rodata.efi_runtime*)
+ *(.data.efi_runtime*)
}
.__efi_runtime_stop : {
@@ -38,8 +39,8 @@ SECTIONS
}
.efi_runtime_rel : {
- *(.relefi_runtime_text)
- *(.relefi_runtime_data)
+ *(.rel*.efi_runtime)
+ *(.rel*.efi_runtime.*)
}
.efi_runtime_rel_stop :
--
2.35.1.1178.g4f1659d476-goog
[PATCH 00/11] Fuzzing and ASAN for sandbox
This series sets up a basic fuzzing infrastructure that works with sandbox. The example fuzz test towards the end of the series will find something pretty quickly. That something is fixed by the series "virtio: Harden and test vring" that needs to be applied for the final patch in this series. There is some refactoring to stop using '.' prefixed sections that elf defines as being for system use and clang's ASAN instrumentation happily adds redzones between, but that's not what we want for things like linker lists where the linker script has carefully placed the sections contiguously. It may require patches from the "Fix misc ASAN reports" series to be applied as I've already dealt with the first set of ASAN reports from running the tests. >From v1: - corrected handling of EFI symbols by sandbox linker script - per comments, some renaming and explaining - dropped RFC for dlmalloc ASAN instrumentation (work required to improve it) - added patch to reduce logging noise in fuzzer Andrew Scull (12): sandbox: Fix EFI runtime symbol placement sandbox: Rename EFI runtime sections sandbox: Migrate getopt section to linker list linker_lists: Rename sections to remove . prefix sandbox: Add support for Address Sanitizer fuzzing_engine: Add fuzzing engine uclass test: fuzz: Add framework for fuzzing sandbox: Decouple program entry from sandbox init sandbox: Add libfuzzer integration sandbox: Implement fuzzing engine driver fuzz: virtio: Add fuzzer for vring virtio_ring: Reduce logging noise Kconfig | 16 +++ arch/Kconfig | 2 + arch/arc/cpu/u-boot.lds | 4 +- arch/arm/config.mk| 4 +- arch/arm/cpu/arm926ejs/sunxi/u-boot-spl.lds | 4 +- arch/arm/cpu/armv7/sunxi/u-boot-spl.lds | 4 +- arch/arm/cpu/armv8/u-boot-spl.lds | 4 +- arch/arm/cpu/armv8/u-boot.lds | 4 +- arch/arm/cpu/u-boot-spl.lds | 4 +- arch/arm/cpu/u-boot.lds | 6 +- arch/arm/mach-at91/arm926ejs/u-boot-spl.lds | 2 +- arch/arm/mach-at91/armv7/u-boot-spl.lds | 2 +- arch/arm/mach-omap2/u-boot-spl.lds| 4 +- arch/arm/mach-orion5x/u-boot-spl.lds | 4 +- arch/arm/mach-rockchip/u-boot-tpl-v8.lds | 4 +- arch/arm/mach-zynq/u-boot-spl.lds | 4 +- arch/arm/mach-zynq/u-boot.lds | 4 +- arch/m68k/cpu/u-boot.lds | 4 +- arch/microblaze/cpu/u-boot-spl.lds| 4 +- arch/microblaze/cpu/u-boot.lds| 4 +- arch/mips/config.mk | 2 +- arch/mips/cpu/u-boot-spl.lds | 4 +- arch/mips/cpu/u-boot.lds | 4 +- arch/nds32/cpu/n1213/u-boot.lds | 4 +- arch/nios2/cpu/u-boot.lds | 4 +- arch/powerpc/cpu/mpc83xx/u-boot.lds | 4 +- arch/powerpc/cpu/mpc85xx/u-boot-nand.lds | 4 +- arch/powerpc/cpu/mpc85xx/u-boot-nand_spl.lds | 4 +- arch/powerpc/cpu/mpc85xx/u-boot-spl.lds | 4 +- arch/powerpc/cpu/mpc85xx/u-boot.lds | 4 +- arch/riscv/cpu/u-boot-spl.lds | 4 +- arch/riscv/cpu/u-boot.lds | 4 +- arch/sandbox/config.mk| 15 ++- arch/sandbox/cpu/os.c | 97 --- arch/sandbox/cpu/start.c | 12 +-- arch/sandbox/cpu/u-boot-spl.lds | 10 +- arch/sandbox/cpu/u-boot.lds | 41 arch/sandbox/dts/test.dts | 4 + arch/sandbox/include/asm/fuzzing_engine.h | 25 + arch/sandbox/include/asm/getopt.h | 19 ++-- arch/sandbox/include/asm/main.h | 18 arch/sandbox/include/asm/sections.h | 25 - arch/sandbox/lib/sections.c | 8 +- arch/sh/cpu/u-boot.lds| 4 +- arch/x86/cpu/u-boot-64.lds| 6 +- arch/x86/cpu/u-boot-spl.lds | 6 +- arch/x86/cpu/u-boot.lds | 6 +- arch/x86/lib/elf_ia32_efi.lds | 4 +- arch/x86/lib/elf_x86_64_efi.lds | 4 +- arch/xtensa/cpu/u-boot.lds| 2 +- arch/xtensa/include/asm/ldscript.h| 4 +- board/compulab/cm_t335/u-boot.lds | 4 +- board/cssi/MCR3000/u-boot.lds | 4 +- .../davinci/da8xxevm/u-boot-spl-da850evm.lds | 2 +- board/qualcomm/dragonboard820c/u-boot.lds | 4 +- board/samsung/common/exynos-uboot-spl.lds | 4 +- board/synopsys/iot_devkit/u-boot.lds | 4 +- board/ti/am335x/u-boot.lds| 4 +- board/vscom/baltos/u-boot.lds | 4 +- configs/sandbox_defconfig | 1 + doc/api/linker_lists.rst | 22 ++--- doc/develop/commands.rst | 4 +-
[PATCH] ARM: imx: imx8m: Fix board_get_usable_ram_top()
The 4 GiB boundary is at 0x+1 , not at 0x8000, fix this.
The PHYS_SDRAM of i.MX8M is at 0x4000 , so to restrict ram_top
below 4 GiB, the ram_top has to be set to 0x as it is not
an offset from the start of PHYS_SDRAM, but rather a physical address
marking the topmost allowed DRAM address.
Fixes: e27bddff4b9 ("imx8m: Restrict usable memory to space below 4G boundary")
Signed-off-by: Marek Vasut
Cc: Fabio Estevam
Cc: Frieder Schrempf
Cc: Peng Fan
Cc: Stefano Babic
---
arch/arm/mach-imx/imx8m/soc.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c
index 8171631db10..e7fe7c2fd88 100644
--- a/arch/arm/mach-imx/imx8m/soc.c
+++ b/arch/arm/mach-imx/imx8m/soc.c
@@ -331,7 +331,7 @@ phys_size_t get_effective_memsize(void)
ulong board_get_usable_ram_top(ulong total_size)
{
- ulong top_addr = PHYS_SDRAM + gd->ram_size;
+ ulong top_addr;
/*
* Some IPs have their accessible address space restricted by
@@ -339,8 +339,7 @@ ulong board_get_usable_ram_top(ulong total_size)
* space below the 4G address boundary (which is 3GiB big),
* even when the effective available memory is bigger.
*/
- if (top_addr > 0x8000)
- top_addr = 0x8000;
+ top_addr = clamp_val((u64)PHYS_SDRAM + gd->ram_size, 0, 0x);
/*
* rom_pointer[0] stores the TEE memory start address.
--
2.35.1
[PATCH] .mailmap: Start to use new amd.com email address
Xilinx has been acquired by AMD that's why emails should be also updated.
The patch is updating .mailmap file and also MAINTAINERS files as was done
by commit 5cd1ecb99490 ("ppc: qemu: Update MAINTAINERS for correct email
address").
The rest of my emails are not going to change.
Signed-off-by: Michal Simek
Signed-off-by: Michal Simek
---
.mailmap | 1 +
MAINTAINERS| 8
board/xilinx/versal/MAINTAINERS| 2 +-
board/xilinx/zynqmp/MAINTAINERS| 2 +-
board/xilinx/zynqmp_r5/MAINTAINERS | 2 +-
5 files changed, 8 insertions(+), 7 deletions(-)
diff --git a/.mailmap b/.mailmap
index 1f88ea953cec..3910e056f0de 100644
--- a/.mailmap
+++ b/.mailmap
@@ -43,6 +43,7 @@ Marek Vasut
Markus Klotzbuecher
Masahiro Yamada
Masahiro Yamada
+Michal Simek
Michal Simek
Michal Simek
Michal Simek
diff --git a/MAINTAINERS b/MAINTAINERS
index 7a9e3156f42c..a0d326c84e1a 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -594,7 +594,7 @@ F: configs/uniphier_*_defconfig
N: uniphier
ARM VERSAL
-M: Michal Simek
+M: Michal Simek
S: Maintained
T: git https://source.denx.de/u-boot/custodians/u-boot-microblaze.git
F: arch/arm/mach-versal/
@@ -639,7 +639,7 @@ F: tools/zynqimage.c
N: zynq
ARM ZYNQMP
-M: Michal Simek
+M: Michal Simek
S: Maintained
T: git https://source.denx.de/u-boot/custodians/u-boot-microblaze.git
F: arch/arm/mach-zynqmp/
@@ -676,7 +676,7 @@ N: ultra96
N: zynqmp
ARM ZYNQMP R5
-M: Michal Simek
+M: Michal Simek
S: Maintained
T: git https://source.denx.de/u-boot/custodians/u-boot-microblaze.git
F: arch/arm/mach-zynqmp-r5/
@@ -852,7 +852,7 @@ F: net/fastboot.c
F: test/dm/fastboot.c
FPGA
-M: Michal Simek
+M: Michal Simek
S: Maintained
T: git https://source.denx.de/u-boot/custodians/u-boot-microblaze.git
F: drivers/fpga/
diff --git a/board/xilinx/versal/MAINTAINERS b/board/xilinx/versal/MAINTAINERS
index bbab05136669..a13b65661646 100644
--- a/board/xilinx/versal/MAINTAINERS
+++ b/board/xilinx/versal/MAINTAINERS
@@ -1,5 +1,5 @@
XILINX_VERSAL BOARDS
-M: Michal Simek
+M: Michal Simek
S: Maintained
T: git https://source.denx.de/u-boot/custodians/u-boot-microblaze.git
F: arch/arm/dts/versal*
diff --git a/board/xilinx/zynqmp/MAINTAINERS b/board/xilinx/zynqmp/MAINTAINERS
index 56c637943f6e..17a2766413c6 100644
--- a/board/xilinx/zynqmp/MAINTAINERS
+++ b/board/xilinx/zynqmp/MAINTAINERS
@@ -1,5 +1,5 @@
XILINX_ZYNQMP BOARDS
-M: Michal Simek
+M: Michal Simek
S: Maintained
T: git https://source.denx.de/u-boot/custodians/u-boot-microblaze.git
F: arch/arm/dts/zynqmp-*
diff --git a/board/xilinx/zynqmp_r5/MAINTAINERS
b/board/xilinx/zynqmp_r5/MAINTAINERS
index ac267649781a..aa50e6dae5f5 100644
--- a/board/xilinx/zynqmp_r5/MAINTAINERS
+++ b/board/xilinx/zynqmp_r5/MAINTAINERS
@@ -1,5 +1,5 @@
XILINX_ZYNQMP_R5 BOARDS
-M: Michal Simek
+M: Michal Simek
S: Maintained
F: arch/arm/dts/zynqmp-r5*
F: board/xilinx/zynqmp_r5/
--
2.35.1
Re: [v3, 3/3] pinctrl: mediatek: add support for different types of IO pins
On Fri, Apr 01, 2022 at 04:55:10PM +0800, Sam Shih wrote: > There are many pins in an SoC, and register usage may vary by pins. > This patch introduces a concept of "io type" and "io type group" > to mediatek pinctrl drivers. This can provide different pinconf > handlers implementation (eg: "bias-pull-up/down", "driving" and > "input-enable") for IO pins that belong to different types. > > Signed-off-by: Sam Shih This fails to compile on mt8518_ap1_emmc and possibly more. -- Tom signature.asc Description: PGP signature
Re: [PATCH v7 8/8] doc: uefi: Update the capsule update related documentation
Hi Sughosh,
2022年4月14日(木) 19:55 Sughosh Ganu :
>
> Update the capsule update functionality related documentation to
> refect the additional definitions that need to be made per platform
> for supporting the capsule update feature.
Thanks for adding the example. This is good to me.
Reviewed-by: Masami Hiramatsu
Thank you,
>
> Signed-off-by: Sughosh Ganu
> ---
>
> Changes since V6:
> * Add example for the struct efi_fw_image array and struct
> efi_capsule_update_info as suggested by Takahiro
>
> doc/develop/uefi/uefi.rst | 98 ++-
> 1 file changed, 96 insertions(+), 2 deletions(-)
>
> diff --git a/doc/develop/uefi/uefi.rst b/doc/develop/uefi/uefi.rst
> index fe337c88bd..1aea04a4e8 100644
> --- a/doc/develop/uefi/uefi.rst
> +++ b/doc/develop/uefi/uefi.rst
> @@ -312,8 +312,8 @@ Run the following command
> .. code-block:: console
>
> $ mkeficapsule \
> - --index 1 --instance 0 \
> - [--fit | --raw ] \
> + --index --instance 0 \
> + --guid \
>
>
> Performing the update
> @@ -333,9 +333,102 @@ won't be taken over across the reboot. If this is the
> case, you can skip
> this feature check with the Kconfig option (CONFIG_EFI_IGNORE_OSINDICATIONS)
> set.
>
> +A few values need to be defined in the board file for performing the
> +capsule update. These values are defined in the board file by
> +initialisation of a structure which provides information needed for
> +capsule updates. The following structures have been defined for
> +containing the image related information
> +
> +.. code-block:: c
> +
> + struct efi_fw_images {
> + efi_guid_t image_type_id;
> + u16 *fw_name;
> + u8 image_index;
> + };
> +
> + struct efi_capsule_update_info {
> + const char *dfu_string;
> + struct efi_fw_image *images;
> + };
> +
> +
> +A string is defined which is to be used for populating the
> +dfu_alt_info variable. This string is used by the function
> +set_dfu_alt_info. Instead of taking the variable from the environment,
> +the capsule update feature requires that the variable be set through
> +the function, since that is more robust. Allowing the user to change
> +the location of the firmware updates is not a very secure
> +practice. Getting this information from the firmware itself is more
> +secure, assuming the firmware has been verified by a previous stage
> +boot loader.
> +
> +The firmware images structure defines the GUID values, image index
> +values and the name of the images that are to be updated through
> +the capsule update feature. These values are to be defined as part of
> +an array. These GUID values would be used by the Firmware Management
> +Protocol(FMP) to populate the image descriptor array and also
> +displayed as part of the ESRT table. The image index values defined in
> +the array should be one greater than the dfu alt number that
> +corresponds to the firmware image. So, if the dfu alt number for an
> +image is 2, the value of image index in the fw_images array for that
> +image should be 3. The dfu alt number can be obtained by running the
> +following command::
> +
> +dfu list
> +
> +When using the FMP for FIT images, the image index value needs to be
> +set to 1.
> +
> Finally, the capsule update can be initiated by rebooting the board.
>
> +An example of setting the values in the struct efi_fw_image and
> +struct efi_capsule_update_info is shown below
> +
> +.. code-block:: c
> +
> + struct efi_fw_image fw_images[] = {
> + {
> + .image_type_id = DEVELOPERBOX_UBOOT_IMAGE_GUID,
> + .fw_name = u"DEVELOPERBOX-UBOOT",
> + .image_index = 1,
> + },
> + {
> + .image_type_id = DEVELOPERBOX_FIP_IMAGE_GUID,
> + .fw_name = u"DEVELOPERBOX-FIP",
> + .image_index = 2,
> + },
> + {
> + .image_type_id = DEVELOPERBOX_OPTEE_IMAGE_GUID,
> + .fw_name = u"DEVELOPERBOX-OPTEE",
> + .image_index = 3,
> + },
> + };
> +
> + struct efi_capsule_update_info update_info = {
> + .dfu_string = "mtd nor1=u-boot.bin raw 20 10;"
> + "fip.bin raw 18 78000;"
> + "optee.bin raw 50 10",
> + .images = fw_images,
> + };
> +
> +The platform will define a fw_images array which contains information
> +of all the firmware images that are to be updated through capsule
> +update mechanism. The dfu_string is the string that is to be set as
> +dfu_alt_info. In the example above, the image index to be set for
> +u-boot.bin binary is 0x1, for fip.bin is 0x2 and for optee.bin is 0x3.
> +
> +As an example, for generating the capsule for the optee.bin image, the
[PATCH v2] bosch: Add initial board support for ACC
The Bosch ACC (Air Center Control) Board is based on the i.MX6D.
Signed-off-by: Philip Oberfichtner
---
Changes in v2:
- Adapt defconfig and device tree to new bootcount driver
- Clean up CONFIG_ENV_FLAGS_LIST_STATIC
- Fix style issues in device trees
- Migrate CONFIG options to Kconfig
This board supports depends on:
- "Add pmic bootcount driver", patchwork id 291027
- "crypto/fsl: Fallback to SW sha1/256 is misaligned buffers",
patchwork id 270524
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/imx6q-acc-common.dtsi | 893 +
arch/arm/dts/imx6q-acc-u-boot.dtsi | 76 +++
arch/arm/dts/imx6q-acc.dts | 280 +
arch/arm/mach-imx/mx6/Kconfig | 15 +
board/bosch/acc/Kconfig| 19 +
board/bosch/acc/MAINTAINERS| 10 +
board/bosch/acc/Makefile | 6 +
board/bosch/acc/acc.c | 755
configs/imx6q_acc_defconfig| 110
include/configs/imx6q-acc.h| 128 +
11 files changed, 2293 insertions(+)
create mode 100644 arch/arm/dts/imx6q-acc-common.dtsi
create mode 100644 arch/arm/dts/imx6q-acc-u-boot.dtsi
create mode 100644 arch/arm/dts/imx6q-acc.dts
create mode 100644 board/bosch/acc/Kconfig
create mode 100644 board/bosch/acc/MAINTAINERS
create mode 100644 board/bosch/acc/Makefile
create mode 100644 board/bosch/acc/acc.c
create mode 100644 configs/imx6q_acc_defconfig
create mode 100644 include/configs/imx6q-acc.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 644ba961a2..e39abda3b2 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -811,6 +811,7 @@ dtb-y += \
imx6q-sabreauto.dtb \
imx6q-sabrelite.dtb \
imx6q-sabresd.dtb \
+ imx6q-acc.dtb \
imx6q-tbs2910.dtb \
imx6q-wandboard-revd1.dtb \
imx6qp-sabreauto.dtb \
diff --git a/arch/arm/dts/imx6q-acc-common.dtsi
b/arch/arm/dts/imx6q-acc-common.dtsi
new file mode 100644
index 00..8359ad61b5
--- /dev/null
+++ b/arch/arm/dts/imx6q-acc-common.dtsi
@@ -0,0 +1,893 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/* Support for the i.MX6-based Bosch ACC board.
+ *
+ * Copyright (c) 2016 Garz & Fricke GmbH
+ * Copyright (c) 2018 DENX Software Engineering GmbH
+ * Heiko Schocher
+ * Niel Fourie
+ * Copyright (c) 2019,2020 Bosch Thermotechnik GmbH
+ *
+ * Based on work from:
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * Author: Fabio Estevam
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include
+
+/ {
+ soc {
+ bus@200 {
+ usbphy_nop1: usbphy_nop1 {
+ compatible = "usb-nop-xceiv";
+ clocks = < IMX6QDL_CLK_USBPHY1>;
+ clock-names = "main_clk";
+ };
+ };
+ };
+
+ wdt-reboot {
+ compatible = "wdt-reboot";
+ wdt = <>;
+ };
+
+ backlight: backlight {
+ status = "okay";
+
+ compatible = "pwm-backlight";
+ pwms = < 0 5>;
+ brightness-levels = <0 63 95 159 255 383 543 735 959 1215 1503>;
+ num-interpolated-steps = <10>;
+ default-brightness-level = <100>;
+ power-supply = <_lcd0_pwr>;
+ };
+
+ clk_12mhz_ref:clk_12mhz_ref {
+ compatible = "fixed-factor-clock";
+
+ clocks = < 201>;
+ clock-names = "cko";
+ clock-div = <1>;
+ clock-mult = <1>;
+
+ #clock-cells = <0>;
+ clock-output-names = "ck12mhzref";
+ };
+
+ leds {
+ compatible = "pwm-leds";
+
+ led_red: red {
+ label = "red";
+ max-brightness = <248>;
+ default-state = "off";
+ pwms = < 0 50>;
+ };
+
+ led_white: white {
+ label = "white";
+ max-brightness = <248>;
+ default-state = "off";
+ pwms = < 0 50>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+
+ /* Third gpio option are the flags, with custom meaning. */
+ /* bit 1 act-low*/
+ /* bit 2 init high */
+
+ gpio_export_keypad_fixed_in {
+ compatible = "gpio-export-of";
+ pinctrl-names = "default";
+ pinctrl-0 = <_gpio_export_gpio_fixed_in>;
+ dir-not-changeable;
+ dir-input;
+
+ gpios =
+ < 22 0>, /* DIG_IN1 */
+ < 23 0>, /* DIG_IN2 */
+ < 10 1>; /*
Re: [PATCH v7 09/15] disk: Correct the conditions for SPL
On Thu, Apr 14, 2022 at 05:21:52PM +0900, AKASHI Takahiro wrote: > Hi Simon, > > On Mon, Feb 28, 2022 at 07:16:51AM -0700, Simon Glass wrote: > > These filesystems may have different settings for SPL and TPL. Use the > > correct Makefile variable to handle this. > > > > Signed-off-by: Simon Glass > > --- > > > > Changes in v7: > > - Add new patch to correct the conditions for SPL > > > > disk/Makefile | 10 +- > > 1 file changed, 5 insertions(+), 5 deletions(-) > > > > diff --git a/disk/Makefile b/disk/Makefile > > index 6ce5a687b3..83f5af6069 100644 > > --- a/disk/Makefile > > +++ b/disk/Makefile > > @@ -6,8 +6,8 @@ > > #ccflags-y += -DET_DEBUG -DDEBUG > > > > obj-$(CONFIG_PARTITIONS) += part.o > > -obj-$(CONFIG_$(SPL_)MAC_PARTITION) += part_mac.o > > -obj-$(CONFIG_$(SPL_)DOS_PARTITION) += part_dos.o > > -obj-$(CONFIG_$(SPL_)ISO_PARTITION) += part_iso.o > > -obj-$(CONFIG_$(SPL_)AMIGA_PARTITION) += part_amiga.o > > -obj-$(CONFIG_$(SPL_)EFI_PARTITION) += part_efi.o > > +obj-$(CONFIG_$(SPL_TPL_)MAC_PARTITION) += part_mac.o > > +obj-$(CONFIG_$(SPL_TPL_)DOS_PARTITION) += part_dos.o > > +obj-$(CONFIG_$(SPL_TPL_)ISO_PARTITION) += part_iso.o > > +obj-$(CONFIG_$(SPL_TPL_)AMIGA_PARTITION) += part_amiga.o > > +obj-$(CONFIG_$(SPL_TPL_)EFI_PARTITION) += part_efi.o > > While none of CONFIG_TPL_xxx_PARTITION is defined, > how do those rules work for TPL? The makefile logic means that if the options are added then they would work as intended. With the options not being in Kconfig they'll simply never be evaluated to y. -- Tom signature.asc Description: PGP signature
RE: RFC: Updating i.MX8M CPU thermal trip-point at runtime
> Subject: Re: RFC: Updating i.MX8M CPU thermal trip-point at runtime > > Hi Andrejs, > > +Cc: Jacky Bai > > Am 13.04.22 um 14:24 schrieb Andrejs Cainikovs: > > [Sie erhalten nicht oft E-Mail von "andrejs.cainik...@toradex.com". > > Weitere Informationen, warum dies wichtig ist, finden Sie unter > > "http://aka.ms/LearnAboutSenderIdentification;.] > > > > Hi everyone, > > > > Recent issue that I had to deal with sparkled a discussion within my > > team, and seems like we are not sure what would be a proper way to go, > > even if there are multiple ways to do it. We decided to ask this > > question to open-source community, in case someone has thoughts about it. > > > > At Toradex we have multiple computer on modules, each of those has few > > variants - different memory sizes, with or without WiFi/BT, etc. One > > of the options is also a temperature grade - IT and non-IT. Obviously, > > we want to keep number of device trees as minimal as possible, since > > number of device trees grows exponentially if we add a new option via > > device tree, i.e. imx8mm-verdin-it-wifi-dev.dts + > > imx8mm-verdin-nonit-wifi-dev.dts. > > > > Hence, we are working on a change that would update trips temperatures > > in Linux device tree on the fly, setting them to whatever is read from > > CPU fuses. Now, the question is - where would be the best place to do > > it? So far we were thinking about following options: > > > > - Patching U-Boot thermal driver so that it would propagate max > > temperature to Linux device tree. > > - Patching U-Boot board files to update Linux device tree via > > ft_board_setup(). This, however, will result in a duplicate code among > > different boards within same SoC family. > > - Anything else not listed here. > > > > I would appreciate any comments or thoughts regarding this topic. > > Thanks, > > Thanks for bringing up the topic. We've been discussing this previously > here: [1]. > > The bootloader doesn't really benefit from the information about the > temperature grading, does it? Therefore I would rather think about a solution > where the kernel itself, or more specifically the TMU driver reads the grading > from the fuses and sets the trip points accordingly. > So we don't create another dependency between bootloader and kernel. > > Anyway, if you rather want to handle this in the bootloader and pass it via > device tree, I guess this would also be ok. In this case the code should be > added > to the thermal driver or the platform code and not in any board specific > files to > avoid duplication, as you already mentioned. > On old i.MX6/7, the thermal driver is not based thermal_of framework, so it is easy to check the temperature grading fuse, then update the trip point setting based on the fuse. But for i.MX8M, the thermal driver is based on thermal_of, so it seems no easy way in linux kernel to update the trip point as on i.MX6/7. Modifying the dts default trip point values base on grading fuse should be a feasible way. BR Jacky Bai > Best regards > Frieder > > [1] > https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpatchw > ork.kernel.org%2Fproject%2Flinux-arm-kernel%2Fpatch%2F20210601174917. > 1979-1-tharvey%40gateworks.com%2Fdata=04%7C01%7Cping.bai%40 > nxp.com%7Cb78589a916204ec81fb508da1df20c7a%7C686ea1d3bc2b4c6fa9 > 2cd99c5c301635%7C0%7C0%7C637855222675274340%7CUnknown%7CTW > FpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXV > CI6Mn0%3D%7C3000sdata=jkqzw1TBRvDA1FelABQUnZFTrCxG3sNZFTiu > P33p3EY%3Dreserved=0
[PATCH 5/8] arm: dts: aspeed: Update SPI flash node settings
For both AST2500 and AST2600, there are three
SPI controllers, FMC(Firmware Memory Controller),
SPI1 and SPI2. The clock source is HCLK. Following
is the basic information for ASPEED SPI controller.
AST2500:
- FMC:
CS number: 3
controller reg: 0x1e62 - 0x1e62
decoded address: 0x2000 - 0x2fff
- SPI1:
CS number: 2
controller reg: 0x1e63 - 0x1e630fff
decoded address: 0x3000 - 0x37ff
- SPI2:
CS number: 2
controller reg: 0x1e631000 - 0x1e631fff
decoded address: 0x3800 - 0x3fff
AST2600:
- FMC:
CS number: 3
controller reg: 0x1e62 - 0x1e62
decoded address: 0x2000 - 0x2fff
- SPI1:
CS number: 2
controller reg: 0x1e63 - 0x1e630fff
decoded address: 0x3000 - 0x3fff
- SPI2:
CS number: 3
controller reg: 0x1e631000 - 0x1e631fff
decoded address: 0x5000 - 0x5fff
Signed-off-by: Chin-Ting Kuo
---
arch/arm/dts/ast2500-evb.dts | 33 +
arch/arm/dts/ast2500.dtsi| 23 ---
arch/arm/dts/ast2600-evb.dts | 8
arch/arm/dts/ast2600.dtsi| 34 +++---
4 files changed, 68 insertions(+), 30 deletions(-)
diff --git a/arch/arm/dts/ast2500-evb.dts b/arch/arm/dts/ast2500-evb.dts
index 4796ed445f..c6b7675902 100644
--- a/arch/arm/dts/ast2500-evb.dts
+++ b/arch/arm/dts/ast2500-evb.dts
@@ -73,3 +73,36 @@
pinctrl-names = "default";
pinctrl-0 = <_sd2_default>;
};
+
+ {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <_fwspics1_default>;
+
+ flash@0 {
+ status = "okay";
+ spi-max-frequency = <5000>;
+ spi-tx-bus-width = <2>;
+ spi-rx-bus-width = <2>;
+ };
+
+ flash@1 {
+ status = "okay";
+ spi-max-frequency = <5000>;
+ spi-tx-bus-width = <2>;
+ spi-rx-bus-width = <2>;
+ };
+};
+
+ {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <_spi1cs1_default>;
+
+ flash@0 {
+ status = "okay";
+ spi-max-frequency = <5000>;
+ spi-tx-bus-width = <2>;
+ spi-rx-bus-width = <2>;
+ };
+};
diff --git a/arch/arm/dts/ast2500.dtsi b/arch/arm/dts/ast2500.dtsi
index ee66ef6704..d78a53aeb7 100644
--- a/arch/arm/dts/ast2500.dtsi
+++ b/arch/arm/dts/ast2500.dtsi
@@ -57,23 +57,26 @@
ranges;
fmc: flash-controller@1e62 {
- reg = < 0x1e62 0xc4
- 0x2000 0x1000 >;
+ reg = <0x1e62 0xc4>, <0x2000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
compatible = "aspeed,ast2500-fmc";
+ clocks = < ASPEED_CLK_AHB>;
+ num-cs = <3>;
status = "disabled";
- interrupts = <19>;
+
flash@0 {
reg = < 0 >;
compatible = "jedec,spi-nor";
status = "disabled";
};
+
flash@1 {
reg = < 1 >;
compatible = "jedec,spi-nor";
status = "disabled";
};
+
flash@2 {
reg = < 2 >;
compatible = "jedec,spi-nor";
@@ -82,17 +85,20 @@
};
spi1: flash-controller@1e63 {
- reg = < 0x1e63 0xc4
- 0x3000 0x0800 >;
+ reg = <0x1e63 0xc4>, <0x3000 0x0800>;
#address-cells = <1>;
#size-cells = <0>;
compatible = "aspeed,ast2500-spi";
+ clocks = < ASPEED_CLK_AHB>;
+ num-cs = <2>;
status = "disabled";
+
flash@0 {
reg = < 0 >;
compatible = "jedec,spi-nor";
status = "disabled";
};
+
flash@1 {
reg = < 1 >;
compatible = "jedec,spi-nor";
@@ -101,17 +107,20 @@
};
spi2: flash-controller@1e631000 {
- reg = < 0x1e631000 0xc4
- 0x3800 0x0800 >;
+ reg = <0x1e631000 0xc4>, <0x3800 0x0800>;
#address-cells = <1>;
#size-cells = <0>;
[PATCH 6/8] spi-mem: Add dirmap API from Linux
This adds the dirmap API originally introduced in Linux commit aa167f3
("spi: spi-mem: Add a new API to support direct mapping"). This also
includes several follow-up patches and fixes.
Changes from Linux include:
* Added Kconfig option
* Changed struct device to struct udevice
* Changed struct spi_mem to struct spi_slave
This patch is obtained from the following patch
https://patchwork.ozlabs.org/project/uboot/patch/20210205043924.149504-3-sean...@gmail.com/
Signed-off-by: Chin-Ting Kuo
Signed-off-by: Sean Anderson
---
drivers/spi/Kconfig | 10 ++
drivers/spi/spi-mem.c | 270 ++
include/spi-mem.h | 98 +++
3 files changed, 378 insertions(+)
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index dc05b3966f..cf0eaf1810 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -40,6 +40,16 @@ config SPI_MEM
This extension is meant to simplify interaction with SPI memories
by providing an high-level interface to send memory-like commands.
+config SPI_DIRMAP
+ bool "SPI direct mapping"
+ depends on SPI_MEM
+ help
+ Enable the SPI direct mapping API. Most modern SPI controllers can
+ directly map a SPI memory (or a portion of the SPI memory) in the CPU
+ address space. Most of the time this brings significant performance
+ improvements as it automates the whole process of sending SPI memory
+ operations every time a new region is accessed.
+
if DM_SPI
config ALTERA_SPI
diff --git a/drivers/spi/spi-mem.c b/drivers/spi/spi-mem.c
index 9c1ede1b61..8e4f37fb50 100644
--- a/drivers/spi/spi-mem.c
+++ b/drivers/spi/spi-mem.c
@@ -21,6 +21,8 @@
#include
#include
#include
+#include
+#include
#endif
#ifndef __UBOOT__
@@ -491,6 +493,274 @@ int spi_mem_adjust_op_size(struct spi_slave *slave,
struct spi_mem_op *op)
}
EXPORT_SYMBOL_GPL(spi_mem_adjust_op_size);
+#if CONFIG_IS_ENABLED(SPI_DIRMAP)
+static ssize_t spi_mem_no_dirmap_read(struct spi_mem_dirmap_desc *desc,
+ u64 offs, size_t len, void *buf)
+{
+ struct spi_mem_op op = desc->info.op_tmpl;
+ int ret;
+
+ op.addr.val = desc->info.offset + offs;
+ op.data.buf.in = buf;
+ op.data.nbytes = len;
+ ret = spi_mem_adjust_op_size(desc->slave, );
+ if (ret)
+ return ret;
+
+ ret = spi_mem_exec_op(desc->slave, );
+ if (ret)
+ return ret;
+
+ return op.data.nbytes;
+}
+
+static ssize_t spi_mem_no_dirmap_write(struct spi_mem_dirmap_desc *desc,
+ u64 offs, size_t len, const void *buf)
+{
+ struct spi_mem_op op = desc->info.op_tmpl;
+ int ret;
+
+ op.addr.val = desc->info.offset + offs;
+ op.data.buf.out = buf;
+ op.data.nbytes = len;
+ ret = spi_mem_adjust_op_size(desc->slave, );
+ if (ret)
+ return ret;
+
+ ret = spi_mem_exec_op(desc->slave, );
+ if (ret)
+ return ret;
+
+ return op.data.nbytes;
+}
+
+/**
+ * spi_mem_dirmap_create() - Create a direct mapping descriptor
+ * @mem: SPI mem device this direct mapping should be created for
+ * @info: direct mapping information
+ *
+ * This function is creating a direct mapping descriptor which can then be used
+ * to access the memory using spi_mem_dirmap_read() or spi_mem_dirmap_write().
+ * If the SPI controller driver does not support direct mapping, this function
+ * falls back to an implementation using spi_mem_exec_op(), so that the caller
+ * doesn't have to bother implementing a fallback on his own.
+ *
+ * Return: a valid pointer in case of success, and ERR_PTR() otherwise.
+ */
+struct spi_mem_dirmap_desc *
+spi_mem_dirmap_create(struct spi_slave *slave,
+ const struct spi_mem_dirmap_info *info)
+{
+ struct udevice *bus = slave->dev->parent;
+ struct dm_spi_ops *ops = spi_get_ops(bus);
+ struct spi_mem_dirmap_desc *desc;
+ int ret = -EOPNOTSUPP;
+
+ /* Make sure the number of address cycles is between 1 and 8 bytes. */
+ if (!info->op_tmpl.addr.nbytes || info->op_tmpl.addr.nbytes > 8)
+ return ERR_PTR(-EINVAL);
+
+ /* data.dir should either be SPI_MEM_DATA_IN or SPI_MEM_DATA_OUT. */
+ if (info->op_tmpl.data.dir == SPI_MEM_NO_DATA)
+ return ERR_PTR(-EINVAL);
+
+ desc = kzalloc(sizeof(*desc), GFP_KERNEL);
+ if (!desc)
+ return ERR_PTR(-ENOMEM);
+
+ desc->slave = slave;
+ desc->info = *info;
+ if (ops->mem_ops && ops->mem_ops->dirmap_create)
+ ret = ops->mem_ops->dirmap_create(desc);
+
+ if (ret) {
+ desc->nodirmap = true;
+ if (!spi_mem_supports_op(desc->slave, >info.op_tmpl))
+ ret = -EOPNOTSUPP;
+ else
+ ret = 0;
+ }
+
+ if (ret) {
+
[PATCH 7/8] mtd: spi-nor: use spi-mem dirmap API
This adds support for the dirmap API to the spi-nor subsystem, as
introduced in Linux commit df5c210 ("mtd: spi-nor: use spi-mem
dirmap API").
This patch is synchronize from the following patch
https://patchwork.ozlabs.org/project/uboot/patch/20210205043924.149504-4-sean...@gmail.com/
Signed-off-by: Chin-Ting Kuo
Signed-off-by: Sean Anderson
---
drivers/mtd/spi/sf_probe.c | 82 ++
drivers/mtd/spi/spi-nor-core.c | 55 ---
include/linux/mtd/spi-nor.h| 18
3 files changed, 139 insertions(+), 16 deletions(-)
diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c
index f461082e03..a3b38b6a29 100644
--- a/drivers/mtd/spi/sf_probe.c
+++ b/drivers/mtd/spi/sf_probe.c
@@ -10,13 +10,81 @@
#include
#include
#include
+#include
#include
#include
#include
#include
+#include
#include "sf_internal.h"
+#if CONFIG_IS_ENABLED(SPI_DIRMAP)
+static int spi_nor_create_read_dirmap(struct spi_nor *nor)
+{
+ struct spi_mem_dirmap_info info = {
+ .op_tmpl = SPI_MEM_OP(SPI_MEM_OP_CMD(nor->read_opcode, 0),
+ SPI_MEM_OP_ADDR(nor->addr_width, 0, 0),
+ SPI_MEM_OP_DUMMY(nor->read_dummy, 0),
+ SPI_MEM_OP_DATA_IN(0, NULL, 0)),
+ .offset = 0,
+ .length = nor->mtd.size,
+ };
+ struct spi_mem_op *op = _tmpl;
+
+ /* get transfer protocols. */
+ spi_nor_setup_op(nor, op, nor->read_proto);
+ op->data.buswidth = spi_nor_get_protocol_data_nbits(nor->read_proto);
+
+ /* convert the dummy cycles to the number of bytes */
+ op->dummy.nbytes = (nor->read_dummy * op->dummy.buswidth) / 8;
+ if (spi_nor_protocol_is_dtr(nor->read_proto))
+ op->dummy.nbytes *= 2;
+
+ nor->dirmap.rdesc = spi_mem_dirmap_create(nor->spi, );
+ if (IS_ERR(nor->dirmap.rdesc))
+ return PTR_ERR(nor->dirmap.rdesc);
+
+ return 0;
+}
+
+static int spi_nor_create_write_dirmap(struct spi_nor *nor)
+{
+ struct spi_mem_dirmap_info info = {
+ .op_tmpl = SPI_MEM_OP(SPI_MEM_OP_CMD(nor->program_opcode, 0),
+ SPI_MEM_OP_ADDR(nor->addr_width, 0, 0),
+ SPI_MEM_OP_NO_DUMMY,
+ SPI_MEM_OP_DATA_OUT(0, NULL, 0)),
+ .offset = 0,
+ .length = nor->mtd.size,
+ };
+ struct spi_mem_op *op = _tmpl;
+
+ /* get transfer protocols. */
+ spi_nor_setup_op(nor, op, nor->write_proto);
+ op->data.buswidth = spi_nor_get_protocol_data_nbits(nor->write_proto);
+
+ if (nor->program_opcode == SPINOR_OP_AAI_WP && nor->sst_write_second)
+ op->addr.nbytes = 0;
+
+ nor->dirmap.wdesc = spi_mem_dirmap_create(nor->spi, );
+ if (IS_ERR(nor->dirmap.wdesc))
+ return PTR_ERR(nor->dirmap.wdesc);
+
+ return 0;
+}
+#else
+static int spi_nor_create_read_dirmap(struct spi_nor *nor)
+{
+ return 0;
+}
+
+static int spi_nor_create_write_dirmap(struct spi_nor *nor)
+{
+ return 0;
+}
+#endif /* CONFIG_SPI_DIRMAP */
+
/**
* spi_flash_probe_slave() - Probe for a SPI flash device on a bus
*
@@ -45,6 +113,14 @@ static int spi_flash_probe_slave(struct spi_flash *flash)
if (ret)
goto err_read_id;
+ ret = spi_nor_create_read_dirmap(flash);
+ if (ret)
+ return ret;
+
+ ret = spi_nor_create_write_dirmap(flash);
+ if (ret)
+ return ret;
+
if (CONFIG_IS_ENABLED(SPI_FLASH_MTD))
ret = spi_flash_mtd_register(flash);
@@ -83,6 +159,9 @@ struct spi_flash *spi_flash_probe(unsigned int busnum,
unsigned int cs,
void spi_flash_free(struct spi_flash *flash)
{
+ spi_mem_dirmap_destroy(flash->dirmap.wdesc);
+ spi_mem_dirmap_destroy(flash->dirmap.rdesc);
+
if (CONFIG_IS_ENABLED(SPI_FLASH_MTD))
spi_flash_mtd_unregister(flash);
@@ -153,6 +232,9 @@ static int spi_flash_std_remove(struct udevice *dev)
struct spi_flash *flash = dev_get_uclass_priv(dev);
int ret;
+ spi_mem_dirmap_destroy(flash->dirmap.wdesc);
+ spi_mem_dirmap_destroy(flash->dirmap.rdesc);
+
ret = spi_nor_remove(flash);
if (ret)
return ret;
diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
index 3b7c817c02..0c6262b7fd 100644
--- a/drivers/mtd/spi/spi-nor-core.c
+++ b/drivers/mtd/spi/spi-nor-core.c
@@ -239,9 +239,9 @@ static u8 spi_nor_get_cmd_ext(const struct spi_nor *nor,
* need to be initialized.
* @proto: the protocol from which the properties need to be set.
*/
-static void spi_nor_setup_op(const struct spi_nor *nor,
-struct spi_mem_op *op,
-const enum spi_nor_protocol
[PATCH 8/8] spi: aspeed: SPI dirmap read support
>From the HW point of view, the performance of
command read mode is greater than user mode slightly.
Thus, dirmap read framework is introduced to achieve
this goal.
In dirmap_create, a specific decoded address area with
flash size is assigned to each CS. CPU can thus access
the SPI flash as normal memory in dirmap_read function.
Signed-off-by: Chin-Ting Kuo
---
configs/evb-ast2500_defconfig | 1 +
configs/evb-ast2600_defconfig | 1 +
drivers/spi/spi-aspeed.c | 93 +++
3 files changed, 95 insertions(+)
diff --git a/configs/evb-ast2500_defconfig b/configs/evb-ast2500_defconfig
index f00bded237..b702a92289 100644
--- a/configs/evb-ast2500_defconfig
+++ b/configs/evb-ast2500_defconfig
@@ -57,6 +57,7 @@ CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
+CONFIG_SPI_DIRMAP=y
CONFIG_SPI_ASPEED=y
CONFIG_SYSRESET=y
CONFIG_TIMER=y
diff --git a/configs/evb-ast2600_defconfig b/configs/evb-ast2600_defconfig
index e013976bb0..279e5a6238 100644
--- a/configs/evb-ast2600_defconfig
+++ b/configs/evb-ast2600_defconfig
@@ -90,6 +90,7 @@ CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
+CONFIG_SPI_DIRMAP=y
CONFIG_SPI_ASPEED=y
CONFIG_SYSRESET=y
CONFIG_SPL_SYSRESET=y
diff --git a/drivers/spi/spi-aspeed.c b/drivers/spi/spi-aspeed.c
index 9574aff793..e5e348eb7b 100644
--- a/drivers/spi/spi-aspeed.c
+++ b/drivers/spi/spi-aspeed.c
@@ -85,6 +85,8 @@ struct aspeed_spi_info {
static int aspeed_spi_trim_decoded_size(struct udevice *bus,
u32 decoded_sz_arr[]);
+static int aspeed_spi_decoded_range_config(struct udevice *bus,
+ u32 decoded_sz_arr[]);
static u32 aspeed_spi_get_io_mode(u32 bus_width)
{
@@ -509,6 +511,95 @@ static int aspeed_spi_exec_op_user_mode(struct spi_slave
*slave,
return 0;
}
+static int aspeed_spi_dirmap_create(struct spi_mem_dirmap_desc *desc)
+{
+ int ret = 0;
+ struct udevice *dev = desc->slave->dev;
+ struct udevice *bus = dev->parent;
+ struct aspeed_spi_plat *plat = dev_get_plat(bus);
+ struct aspeed_spi_priv *priv = dev_get_priv(bus);
+ struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
+ const struct aspeed_spi_info *info = priv->info;
+ struct spi_mem_op op_tmpl = desc->info.op_tmpl;
+ u32 i;
+ u32 cs = slave_plat->cs;
+ u32 decoded_sz_arr[ASPEED_SPI_MAX_CS];
+ u32 reg_val;
+
+ if (desc->info.op_tmpl.data.dir == SPI_MEM_DATA_IN) {
+ for (i = 0; i < priv->num_cs; i++) {
+ reg_val = readl(plat->ctrl_base +
+ REG_CE0_DECODED_ADDR_REG + i * 4);
+ decoded_sz_arr[i] =
+ info->segment_end(bus, reg_val) -
+ info->segment_start(bus, reg_val);
+ }
+
+ decoded_sz_arr[cs] = desc->info.length;
+
+ if (info->adjust_decoded_sz)
+ info->adjust_decoded_sz(bus, decoded_sz_arr);
+
+ for (i = 0; i < priv->num_cs; i++) {
+ dev_dbg(dev, "cs: %d, sz: 0x%x\n", i,
+ decoded_sz_arr[i]);
+ }
+
+ ret = aspeed_spi_decoded_range_config(bus, decoded_sz_arr);
+ if (ret)
+ return ret;
+
+ reg_val = readl(plat->ctrl_base + REG_CE0_CTRL_REG + cs * 4) &
+ (~info->cmd_io_ctrl_mask);
+ reg_val |= aspeed_spi_get_io_mode(op_tmpl.data.buswidth) |
+ op_tmpl.cmd.opcode << 16 |
+ ((op_tmpl.dummy.nbytes) & 0x3) << 6 |
+ ((op_tmpl.dummy.nbytes) & 0x4) << 14 |
+ CTRL_IO_MODE_CMD_READ;
+
+ writel(reg_val,
+ plat->ctrl_base + REG_CE0_CTRL_REG + cs * 4);
+ priv->flashes[cs].ce_ctrl_read = reg_val;
+
+ dev_dbg(dev, "read bus width: %d [0x%08x]\n",
+ op_tmpl.data.buswidth, priv->flashes[cs].ce_ctrl_read);
+ } else {
+ /*
+* dirmap_write is not supported currently due to a HW
+* limitation for command write mode: The written data
+* length should be multiple of 4-byte.
+*/
+ return -EOPNOTSUPP;
+ }
+
+ return ret;
+}
+
+static ssize_t aspeed_spi_dirmap_read(struct spi_mem_dirmap_desc *desc,
+ u64 offs, size_t len, void *buf)
+{
+ struct udevice *dev = desc->slave->dev;
+ struct aspeed_spi_priv *priv = dev_get_priv(dev->parent);
+ struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
+ u32 cs = slave_plat->cs;
+ int ret;
+
+ dev_dbg(dev, "read op:0x%x, addr:0x%llx, len:0x%x\n",
+
[PATCH 3/8] spi: aspeed: Add ASPEED SPI controller driver
Add ASPEED BMC FMC/SPI memory controller driver with spi-mem interface for AST2500 and AST2600 platform. There are three SPI memory controllers embedded in an ASPEED SoC. - FMC: Named as Firmware Memory Controller. After AC on, MCU ROM fetches initial device boot image from FMC chip select(CS) 0. - SPI1: Play the role of a SPI Master controller. Or, there is a dedicated path for HOST(X86) to access its BIOS flash mounted under BMC. spi-aspeed.c implements the control sequence when SPI1 is a SPI master. - SPI2: It is a pure SPI flash controller. For most scenarios, flashes mounted under it are for pure storage purpose. ASPEED SPI controller supports 1-1-1, 1-1-2 and 1-1-4 SPI flash mode. Three types of command mode are supported, normal mode, command read/write mode and user mode. - Normal mode: Default mode. After power on, normal read command 03h or 13h is used to fetch boot image from SPI flash. - AST2500: Only 03h command can be used after power on or reset. - AST2600: If FMC04[6:4] is set, 13h command is used, otherwise, 03h command. The address length is decided by FMC04[2:0]. - Command mode: SPI controller can send command and address automatically when CPU read/write the related remapped or decoded address area. The command used by this mode can be configured by FMC10/14/18[23:16]. Also, the address length is decided by FMC04[2:0]. This mode will be implemented in the following patch series. - User mode: It is a traditional and pure SPI operation, where SPI transmission is controlled by CPU. It is the main mode in this patch. Each SPI controller in ASPEED SoC has its own decoded address mapping. Within each SPI controller decoded address, driver can assign a specific address region for each CS of a SPI controller. The decoded address cannot overlap to each other. With normal mode and command mode, the decoded address accessed by the CPU determines which CS is active. When user mode is adopted, the CS decoded address is a FIFO, CPU can send/receive any SPI transmission by accessing the related decoded address for the target CS. Signed-off-by: Chin-Ting Kuo --- configs/evb-ast2500_defconfig | 13 + configs/evb-ast2600_defconfig | 13 + drivers/spi/Kconfig | 8 + drivers/spi/Makefile | 1 + drivers/spi/spi-aspeed.c | 822 ++ 5 files changed, 857 insertions(+) create mode 100644 drivers/spi/spi-aspeed.c diff --git a/configs/evb-ast2500_defconfig b/configs/evb-ast2500_defconfig index 53fe7776e9..f00bded237 100644 --- a/configs/evb-ast2500_defconfig +++ b/configs/evb-ast2500_defconfig @@ -36,6 +36,16 @@ CONFIG_DM_I2C=y CONFIG_SYS_I2C_ASPEED=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ASPEED=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_ISSI=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_SST=y +CONFIG_SPI_FLASH_WINBOND=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_PHY_REALTEK=y CONFIG_DM_ETH=y CONFIG_FTGMAC100=y @@ -45,6 +55,9 @@ CONFIG_RAM=y CONFIG_DM_RESET=y CONFIG_DM_SERIAL=y CONFIG_SYS_NS16550=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_SPI_ASPEED=y CONFIG_SYSRESET=y CONFIG_TIMER=y CONFIG_WDT=y diff --git a/configs/evb-ast2600_defconfig b/configs/evb-ast2600_defconfig index ea75762926..e013976bb0 100644 --- a/configs/evb-ast2600_defconfig +++ b/configs/evb-ast2600_defconfig @@ -66,6 +66,16 @@ CONFIG_MISC=y CONFIG_SPL_MISC=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ASPEED=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_ISSI=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_SST=y +CONFIG_SPI_FLASH_WINBOND=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_PHY_REALTEK=y CONFIG_DM_ETH=y CONFIG_DM_MDIO=y @@ -78,6 +88,9 @@ CONFIG_SPL_RAM=y CONFIG_DM_RESET=y CONFIG_DM_SERIAL=y CONFIG_SYS_NS16550=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_SPI_ASPEED=y CONFIG_SYSRESET=y CONFIG_SPL_SYSRESET=y CONFIG_WDT=y diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 8dba95ae4e..dc05b3966f 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -381,6 +381,14 @@ config SANDBOX_SPI }; }; +config SPI_ASPEED + bool "ASPEED SPI controller driver" + depends on DM_SPI && SPI_MEM + default n + help + Enable ASPEED SPI controller driver for AST2500 + and AST2600 SoCs. + config SPI_SIFIVE bool "SiFive SPI driver" help diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 7f43f843ca..6fbb3f30be 100644 --- a/drivers/spi/Makefile +++
[PATCH 1/8] clk: aspeed: Get HCLK frequency support
User can get correct HCLK frequency during driver probe stage
by adding the following configuration in the device tree.
"clocks = < ASPEED_CLK_AHB>".
Signed-off-by: Chin-Ting Kuo
---
drivers/clk/aspeed/clk_ast2500.c | 24
1 file changed, 24 insertions(+)
diff --git a/drivers/clk/aspeed/clk_ast2500.c b/drivers/clk/aspeed/clk_ast2500.c
index a1b4496ca2..d2a58a8462 100644
--- a/drivers/clk/aspeed/clk_ast2500.c
+++ b/drivers/clk/aspeed/clk_ast2500.c
@@ -29,6 +29,12 @@
#define D2PLL_DEFAULT_RATE (250 * 1000 * 1000)
+/*
+ * AXI/AHB clock selection, taken from Aspeed SDK
+ */
+#define SCU_HWSTRAP_AXIAHB_DIV_SHIFT9
+#define SCU_HWSTRAP_AXIAHB_DIV_MASK (0x7 << SCU_HWSTRAP_AXIAHB_DIV_SHIFT)
+
DECLARE_GLOBAL_DATA_PTR;
/*
@@ -85,6 +91,21 @@ static ulong ast2500_get_clkin(struct ast2500_scu *scu)
? 25 * 1000 * 1000 : 24 * 1000 * 1000;
}
+static u32 ast2500_get_hclk(struct ast2500_scu *scu)
+{
+ ulong clkin = ast2500_get_clkin(scu);
+ u32 hpll_reg = readl(>h_pll_param);
+ ulong axi_div = 2;
+ u32 rate;
+ ulong ahb_div = 1 + ((readl(>hwstrap)
+ & SCU_HWSTRAP_AXIAHB_DIV_MASK)
+>> SCU_HWSTRAP_AXIAHB_DIV_SHIFT);
+
+ rate = ast2500_get_hpll_rate(clkin, hpll_reg);
+
+ return (rate / axi_div / ahb_div);
+}
+
/**
* Get current rate or uart clock
*
@@ -146,6 +167,9 @@ static ulong ast2500_clk_get_rate(struct clk *clk)
rate = rate / apb_div;
}
break;
+ case ASPEED_CLK_AHB:
+ rate = ast2500_get_hclk(priv->scu);
+ break;
case ASPEED_CLK_SDIO:
{
ulong apb_div = 4 + 4 * ((readl(>scu->clk_sel1)
--
2.25.1
[PATCH 4/8] MAINTAINERS: Add ASPEED SPI driver file
Add spi-aspeed.c file for ARM ASPEED. Signed-off-by: Chin-Ting Kuo --- MAINTAINERS | 7 +++ 1 file changed, 7 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 0fc034f01f..c86ea34883 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -687,6 +687,13 @@ S: Maintained F: drivers/pci/pcie_phytium.c F: arch/arm/dts/phytium-durian.dts +ASPEED FMC SPI DRIVER +M: Chin-Ting Kuo +M: Cédric Le Goater +R: Aspeed BMC SW team +S: Maintained +F: drivers/spi/spi-aspeed.c + BINMAN M: Simon Glass S: Maintained -- 2.25.1
[PATCH 0/8] Add ASPEED SPI controller driver
This patch series aims to porting ASPEED FMC/SPI memory controller driver with spi-mem interface. spi-mem dirmap framework is also synchronized from Linux. These patches have been verified on both AST2600 and AST2500 EVBs. Chin-Ting Kuo (8): clk: aspeed: Get HCLK frequency support pinctrl: aspeed: FWSPICS1 and SPI1CS1 pin support spi: aspeed: Add ASPEED SPI controller driver MAINTAINERS: Add ASPEED SPI driver file arm: dts: aspeed: Update SPI flash node settings spi-mem: Add dirmap API from Linux mtd: spi-nor: use spi-mem dirmap API spi: aspeed: SPI dirmap read support MAINTAINERS | 7 + arch/arm/dts/ast2500-evb.dts | 33 + arch/arm/dts/ast2500.dtsi| 23 +- arch/arm/dts/ast2600-evb.dts | 8 - arch/arm/dts/ast2600.dtsi| 34 +- configs/evb-ast2500_defconfig| 14 + configs/evb-ast2600_defconfig| 14 + drivers/clk/aspeed/clk_ast2500.c | 24 + drivers/mtd/spi/sf_probe.c | 82 ++ drivers/mtd/spi/spi-nor-core.c | 55 +- drivers/pinctrl/aspeed/pinctrl_ast2500.c | 2 + drivers/spi/Kconfig | 18 + drivers/spi/Makefile | 1 + drivers/spi/spi-aspeed.c | 915 +++ drivers/spi/spi-mem.c| 270 +++ include/linux/mtd/spi-nor.h | 18 + include/spi-mem.h| 98 +++ 17 files changed, 1570 insertions(+), 46 deletions(-) create mode 100644 drivers/spi/spi-aspeed.c -- 2.25.1
[PATCH 2/8] pinctrl: aspeed: FWSPICS1 and SPI1CS1 pin support
Add FWSPICS1 and SPI1CS1 in AST2500 pinctrl group.
On AST2500 EVB, FWSPICS1 can be supported by default.
An extra jumper, J45, should be configured before
enabling SPI1CS1.
Signed-off-by: Chin-Ting Kuo
---
drivers/pinctrl/aspeed/pinctrl_ast2500.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/pinctrl/aspeed/pinctrl_ast2500.c
b/drivers/pinctrl/aspeed/pinctrl_ast2500.c
index 3c2e10b88e..93920a6389 100644
--- a/drivers/pinctrl/aspeed/pinctrl_ast2500.c
+++ b/drivers/pinctrl/aspeed/pinctrl_ast2500.c
@@ -61,6 +61,8 @@ static const struct ast2500_group_config ast2500_groups[] = {
{ "MDIO2", 5, (1 << 2) },
{ "SD1", 5, (1 << 0) },
{ "SD2", 5, (1 << 1) },
+ { "FWSPICS1", 3, (1 << 24) },
+ { "SPI1CS1", 1, (1 << 15) },
};
static int ast2500_pinctrl_get_groups_count(struct udevice *dev)
--
2.25.1
Re: [PATCH v7 4/8] efi: Define set_dfu_alt_info() for boards with UEFI capsule update enabled
2022年4月14日(木) 19:55 Sughosh Ganu :
>
> Currently, there are a bunch of boards which enable the UEFI capsule
> update feature. The actual update of the firmware images is done
> through the dfu framework which uses the dfu_alt_info environment
> variable for getting information on the update, like device, partition
> number/address etc. The dfu framework allows the variable to be set
> through the set_dfu_alt_info function defined by the platform, or if
> the function is not defined, it gets the variable from the
> environment. Using the value set in the environment is not very
> robust, since the variable can be modified from the u-boot command
> line and this can cause an incorrect update.
>
> To prevent this from happening, define the set_dfu_alt_info function
> when the capsule update feature is enabled. A weak function is defined
> which sets the dfu_alt_info environment variable by getting the string
> for the variable from the platform.
This sounds reasonable.
Reviewed-by: Masami Hiramatsu
Thank you,
>
> Signed-off-by: Sughosh Ganu
> ---
>
> Changes since V6: None
>
> lib/efi_loader/Kconfig| 2 ++
> lib/efi_loader/efi_firmware.c | 5 +
> 2 files changed, 7 insertions(+)
>
> diff --git a/lib/efi_loader/Kconfig b/lib/efi_loader/Kconfig
> index 559b95a599..d50cd2563d 100644
> --- a/lib/efi_loader/Kconfig
> +++ b/lib/efi_loader/Kconfig
> @@ -181,6 +181,7 @@ config EFI_CAPSULE_FIRMWARE_FIT
> depends on EFI_CAPSULE_FIRMWARE_MANAGEMENT
> select UPDATE_FIT
> select DFU
> + select SET_DFU_ALT_INFO
> select EFI_CAPSULE_FIRMWARE
> help
> Select this option if you want to enable firmware management
> protocol
> @@ -192,6 +193,7 @@ config EFI_CAPSULE_FIRMWARE_RAW
> depends on SANDBOX || (!SANDBOX && !EFI_CAPSULE_FIRMWARE_FIT)
> select DFU_WRITE_ALT
> select DFU
> + select SET_DFU_ALT_INFO
> select EFI_CAPSULE_FIRMWARE
> help
> Select this option if you want to enable firmware management
> protocol
> diff --git a/lib/efi_loader/efi_firmware.c b/lib/efi_loader/efi_firmware.c
> index 46aa7a001a..aff5519e54 100644
> --- a/lib/efi_loader/efi_firmware.c
> +++ b/lib/efi_loader/efi_firmware.c
> @@ -35,6 +35,11 @@ struct fmp_payload_header {
> u32 lowest_supported_version;
> };
>
> +__weak void set_dfu_alt_info(char *interface, char *devstr)
> +{
> + env_set("dfu_alt_info", update_info.dfu_string);
> +}
> +
> /* Place holder; not supported */
> static
> efi_status_t EFIAPI efi_firmware_get_image_unsupported(
> --
> 2.25.1
>
--
Masami Hiramatsu
Re: [PATCH v7 2/8] capsule: FMP: Populate the image descriptor array from platform data
Hi Sughosh,
2022年4月14日(木) 19:55 Sughosh Ganu :
>
> Currently, the image descriptor array that has been passed to the
> GetImageInfo function of the Firmware Management Protocol(FMP) gets
> populated through the data stored with the dfu framework. The
> dfu data is not restricted to contain information only of the images
> updatable through the capsule update mechanism, but it also contains
> information on other images. The image descriptor array is also parsed
> by the ESRT generation code, and thus the ESRT table contains entries
> for other images that are not being handled by the FMP for the capsule
> updates. Fix this by populating the image descriptor array from the
> structure initialised in the board file.
>
> The other issue fixed is assignment of a separate GUID for all images
> in the image descriptor array. The UEFI specification mandates that
> all entries in the ESRT table should have a unique GUID value as part
> of the FwClass member of the EFI_SYSTEM_RESOURCE_ENTRY. Currently, all
> images are assigned a single GUID value, either an FIT GUID or a raw
> image GUID. This is fixed by obtaining the GUID values from the
> efi_fw_images array defined per platform.
>
> Signed-off-by: Sughosh Ganu
> ---
>
> Changes since V6:
> * Use renamed struct efi_fw_image instead of struct efi_fw_images
>
>
> lib/efi_loader/efi_firmware.c | 95 +++
> 1 file changed, 28 insertions(+), 67 deletions(-)
>
> diff --git a/lib/efi_loader/efi_firmware.c b/lib/efi_loader/efi_firmware.c
> index a5ff32f121..46aa7a001a 100644
> --- a/lib/efi_loader/efi_firmware.c
> +++ b/lib/efi_loader/efi_firmware.c
> @@ -97,91 +97,58 @@ efi_status_t EFIAPI
> efi_firmware_set_package_info_unsupported(
> }
>
> /**
> - * efi_get_dfu_info - return information about the current firmware image
> + * efi_fill_image_desc_array - populate image descriptor array
> * @this: Protocol instance
> * @image_info_size: Size of @image_info
> * @image_info:Image information
> * @descriptor_version:Pointer to version number
> - * @descriptor_count: Pointer to number of descriptors
> + * @descriptor_count: Image count
> * @descriptor_size: Pointer to descriptor size
> - * package_version:Package version
> - * package_version_name: Package version's name
> - * image_type: Image type GUID
> + * @package_version: Package version
> + * @package_version_name: Package version's name
> *
> * Return information bout the current firmware image in @image_info.
> * @image_info will consist of a number of descriptors.
> - * Each descriptor will be created based on "dfu_alt_info" variable.
> + * Each descriptor will be created based on "efi_fw_images" variable.
nit: here is "efi_fw_images".
Except for that, this looks good to me.
Reviewed-by: Masami Hiramatsu
Thank you,
> *
> * Return status code
> */
> -static efi_status_t efi_get_dfu_info(
> +static efi_status_t efi_fill_image_desc_array(
> efi_uintn_t *image_info_size,
> struct efi_firmware_image_descriptor *image_info,
> u32 *descriptor_version,
> u8 *descriptor_count,
> efi_uintn_t *descriptor_size,
> u32 *package_version,
> - u16 **package_version_name,
> - const efi_guid_t *image_type)
> + u16 **package_version_name)
> {
> - struct dfu_entity *dfu;
> - size_t names_len, total_size;
> - int dfu_num, i;
> - u16 *name, *next;
> - int ret;
> -
> - ret = dfu_init_env_entities(NULL, NULL);
> - if (ret)
> - return EFI_SUCCESS;
> -
> - names_len = 0;
> - dfu_num = 0;
> - list_for_each_entry(dfu, _list, list) {
> - names_len += (utf8_utf16_strlen(dfu->name) + 1) * 2;
> - dfu_num++;
> - }
> - if (!dfu_num) {
> - log_warning("No entities in dfu_alt_info\n");
> - *image_info_size = 0;
> - dfu_free_entities();
> + size_t total_size;
> + struct efi_fw_image *fw_array;
> + int i;
>
> - return EFI_SUCCESS;
> - }
> + fw_array = update_info.images;
> + *descriptor_count = num_image_type_guids;
> +
> + total_size = sizeof(*image_info) * num_image_type_guids;
>
> - total_size = sizeof(*image_info) * dfu_num + names_len;
> - /*
> -* we will assume that sizeof(*image_info) * dfu_name
> -* is, at least, a multiple of 2. So the start address for
> -* image_id_name would be aligned with 2 bytes.
> -*/
> if (*image_info_size < total_size) {
> *image_info_size = total_size;
> - dfu_free_entities();
>
> return EFI_BUFFER_TOO_SMALL;
> }
> *image_info_size = total_size;
>
> *descriptor_version =
[PATCH v2] imx: add i.MX8MN DDR3L evk board support
Add the support for the 8MNANOD3L-EVK board. The board has an i.MX8MNano
UltraLite Quad SoC and uses 1GB DDR3L memory.
U-Boot 2022.04-00011-gf0e15e3761 (Apr 06 2022 - 13:54:41 +0200)
CPU: Freescale i.MX8MNano UltraLite Quad rev1.0 at 1200 MHz
Reset cause: WDOG
Model: NXP i.MX8MNano DDR3L EVK board
DRAM: 1 GiB
Core: 56 devices, 18 uclasses, devicetree: separate
WDT: Started watchdog@3028 with servicing (60s timeout)
MMC: FSL_SDHC: 1, FSL_SDHC: 2
Loading Environment from MMC... OK
In:serial@3089
Out: serial@3089
Err: serial@3089
BuildInfo:
- ATF
Net: eth0: ethernet@30be
u-boot=>
Signed-off-by: Heiko Thiery
---
v2:
- change license formatting (thanks Marcel)
arch/arm/dts/imx8mn-ddr3l-evk-u-boot.dtsi | 33 +
arch/arm/dts/imx8mn-ddr3l-evk.dts | 114 +++
arch/arm/dts/imx8mn-u-boot.dtsi | 12 +
arch/arm/mach-imx/imx8m/Kconfig | 7 +
board/freescale/imx8mn_evk/Kconfig| 2 +-
board/freescale/imx8mn_evk/Makefile | 1 +
board/freescale/imx8mn_evk/ddr3l_timing.c | 943 ++
board/freescale/imx8mn_evk/spl.c | 9 +
configs/imx8mn_ddr3l_evk_defconfig| 99 +++
include/configs/imx8mn_evk.h | 4 +
10 files changed, 1223 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/dts/imx8mn-ddr3l-evk-u-boot.dtsi
create mode 100644 arch/arm/dts/imx8mn-ddr3l-evk.dts
create mode 100644 board/freescale/imx8mn_evk/ddr3l_timing.c
create mode 100644 configs/imx8mn_ddr3l_evk_defconfig
diff --git a/arch/arm/dts/imx8mn-ddr3l-evk-u-boot.dtsi
b/arch/arm/dts/imx8mn-ddr3l-evk-u-boot.dtsi
new file mode 100644
index 00..2200d9a0f5
--- /dev/null
+++ b/arch/arm/dts/imx8mn-ddr3l-evk-u-boot.dtsi
@@ -0,0 +1,33 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include "imx8mn-u-boot.dtsi"
+
+
+&{/soc@0} {
+ u-boot,dm-pre-reloc;
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+ u-boot,dm-pre-reloc;
+ /delete-property/ assigned-clocks;
+ /delete-property/ assigned-clock-parents;
+ /delete-property/ assigned-clock-rates;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+&{/soc@0/bus@3080/i2c@30a2/pmic@25} {
+ u-boot,dm-spl;
+};
+
+&{/soc@0/bus@3080/i2c@30a2/pmic@25/regulators} {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
diff --git a/arch/arm/dts/imx8mn-ddr3l-evk.dts
b/arch/arm/dts/imx8mn-ddr3l-evk.dts
new file mode 100644
index 00..4cdc03c8f2
--- /dev/null
+++ b/arch/arm/dts/imx8mn-ddr3l-evk.dts
@@ -0,0 +1,114 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+/dts-v1/;
+
+#include "imx8mn.dtsi"
+#include "imx8mn-evk.dtsi"
+#include
+
+/ {
+ model = "NXP i.MX8MNano DDR3L EVK board";
+ compatible = "fsl,imx8mn-ddr3l-evk", "fsl,imx8mn";
+};
+
+_0 {
+ cpu-supply = <>;
+};
+
+_1 {
+ cpu-supply = <>;
+};
+
+_2 {
+ cpu-supply = <>;
+};
+
+_3 {
+ cpu-supply = <>;
+};
+
+ {
+ pmic: pmic@25 {
+ compatible = "nxp,pca9450b";
+ reg = <0x25>;
+ pinctrl-names = "default";
+ pinctrl-0 = <_pmic>;
+ interrupt-parent = <>;
+ interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
+
+ regulators {
+ buck1: BUCK1 {
+ regulator-name = "VDD_SOC_0V9";
+ regulator-min-microvolt = <85>;
+ regulator-max-microvolt = <95>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <3125>;
+ };
+
+ buck4: BUCK4 {
+ regulator-name = "VDD_3V3";
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ buck5: BUCK5 {
+ regulator-name = "VDD_1V8";
+ regulator-min-microvolt = <180>;
+ regulator-max-microvolt = <180>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ buck6: BUCK6 {
+ regulator-name = "NVCC_DRAM_1V35";
+ regulator-min-microvolt = <135>;
+ regulator-max-microvolt = <135>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo1: LDO1 {
+ regulator-name = "NVCC_SNVS_1V8";
+ regulator-min-microvolt = <180>;
+
Re: [PATCH] imx: add i.MX8MN DDR3L evk board support
Hi Marcel,
Am Mi., 6. Apr. 2022 um 15:14 Uhr schrieb Marcel Ziswiler
:
>
> Hi Heiko
>
> On Wed, 2022-04-06 at 14:08 +0200, Heiko Thiery wrote:
> > Add the support for the 8MNANOD3L-EVK board. The board has an i.MX8MNano
> > UltraLite Quad SoC and uses 1GB DDR3L memory.
> >
> > U-Boot 2022.04-00011-gf0e15e3761 (Apr 06 2022 - 13:54:41 +0200)
> >
> > CPU: Freescale i.MX8MNano UltraLite Quad rev1.0 at 1200 MHz
> > Reset cause: WDOG
> > Model: NXP i.MX8MNano DDR3L EVK board
> > DRAM: 1 GiB
> > Core: 56 devices, 18 uclasses, devicetree: separate
> > WDT: Started watchdog@3028 with servicing (60s timeout)
> > MMC: FSL_SDHC: 1, FSL_SDHC: 2
> > Loading Environment from MMC... OK
> > In:serial@3089
> > Out: serial@3089
> > Err: serial@3089
> >
> > BuildInfo:
> > - ATF
> >
> > Net: eth0: ethernet@30be
> > u-boot=>
> >
> > Signed-off-by: Heiko Thiery
> > ---
> > Applying this patch requires the previous sent patches that does
> > modifications on the other imx8mn evk boards.
> >
> > [1]
> > https://patchwork.ozlabs.org/project/uboot/patch/20220222144734.398258-1-heiko.thi...@gmail.com/
> > [2]
> > https://patchwork.ozlabs.org/project/uboot/patch/20220224094632.65583-1-heiko.thi...@gmail.com/
> > [3]
> > https://patchwork.ozlabs.org/project/uboot/patch/20220224094632.65583-2-heiko.thi...@gmail.com/
> >
> >
> > arch/arm/dts/imx8mn-ddr3l-evk-u-boot.dtsi | 36 +
> > arch/arm/dts/imx8mn-ddr3l-evk.dts | 117 +++
> > arch/arm/dts/imx8mn-u-boot.dtsi | 12 +
> > arch/arm/mach-imx/imx8m/Kconfig | 7 +
> > board/freescale/imx8mn_evk/Kconfig| 2 +-
> > board/freescale/imx8mn_evk/Makefile | 1 +
> > board/freescale/imx8mn_evk/ddr3l_timing.c | 944 ++
> > board/freescale/imx8mn_evk/spl.c | 9 +
> > configs/imx8mn_ddr3l_evk_defconfig| 99 +++
> > include/configs/imx8mn_evk.h | 4 +
> > 10 files changed, 1230 insertions(+), 1 deletion(-)
> > create mode 100644 arch/arm/dts/imx8mn-ddr3l-evk-u-boot.dtsi
> > create mode 100644 arch/arm/dts/imx8mn-ddr3l-evk.dts
> > create mode 100644 board/freescale/imx8mn_evk/ddr3l_timing.c
> > create mode 100644 configs/imx8mn_ddr3l_evk_defconfig
> >
> > diff --git a/arch/arm/dts/imx8mn-ddr3l-evk-u-boot.dtsi
> > b/arch/arm/dts/imx8mn-ddr3l-evk-u-boot.dtsi
> > new file mode 100644
> > index 00..fe1fbef97c
> > --- /dev/null
> > +++ b/arch/arm/dts/imx8mn-ddr3l-evk-u-boot.dtsi
> > @@ -0,0 +1,36 @@
> > +// SPDX-License-Identifier: GPL-2.0+
>
> Nowadays this gets written as:
>
> GPL-2.0-or-later
>
> Plus most device trees get dual licensed these days:
>
> GPL-2.0-or-later OR MIT
>
Ok .. for the ...u-boot.dtsi I will change this.
> > +/*
> > + * Copyright 2019 NXP
> > + */
> > +
> > +#include "imx8mn-u-boot.dtsi"
> > +
> > +
> > +&{/soc@0} {
> > + u-boot,dm-pre-reloc;
> > + u-boot,dm-spl;
> > +};
> > +
> > + {
> > + u-boot,dm-spl;
> > + u-boot,dm-pre-reloc;
> > + /delete-property/ assigned-clocks;
> > + /delete-property/ assigned-clock-parents;
> > + /delete-property/ assigned-clock-rates;
> > +};
> > +
> > + {
> > + u-boot,dm-spl;
> > +};
> > +
> > +&{/soc@0/bus@3080/i2c@30a2/pmic@25} {
> > + u-boot,dm-spl;
> > +};
> > +
> > +&{/soc@0/bus@3080/i2c@30a2/pmic@25/regulators} {
> > + u-boot,dm-spl;
> > +};
> > +
> > + {
> > + u-boot,dm-spl;
> > +};
> > diff --git a/arch/arm/dts/imx8mn-ddr3l-evk.dts
> > b/arch/arm/dts/imx8mn-ddr3l-evk.dts
> > new file mode 100644
> > index 00..47614446ad
> > --- /dev/null
> > +++ b/arch/arm/dts/imx8mn-ddr3l-evk.dts
> > @@ -0,0 +1,117 @@
> > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
>
> Ah, see. Anyway, neither parentheses are required nor is that 2.0+ the latest
> syntax.
The main dts is taken from a pending linux patch [1]. So I will keep
that here to be in sync with linux.
[1] https://lore.kernel.org/lkml/20220412143238.1925059-3-mich...@walle.cc/
> > +/*
> > + * Copyright 2019 NXP
> > + */
> > +
> > +/dts-v1/;
> > +
> > +#include "imx8mn.dtsi"
> > +#include "imx8mn-evk.dtsi"
> > +#include
> > +
> > +/ {
> > + model = "NXP i.MX8MNano DDR3L EVK board";
> > + compatible = "fsl,imx8mn-ddr3l-evk", "fsl,imx8mn";
> > +};
> > +
> > +_0 {
> > + cpu-supply = <>;
> > +};
> > +
> > +_1 {
> > + cpu-supply = <>;
> > +};
> > +
> > +_2 {
> > + cpu-supply = <>;
> > +};
> > +
> > +_3 {
> > + cpu-supply = <>;
> > +};
> > +
> > + {
> > + pmic: pmic@25 {
> > + compatible = "nxp,pca9450b";
> > + reg = <0x25>;
> > + pinctrl-names = "default";
> > + pinctrl-0 = <_pmic>;
> > + interrupt-parent = <>;
> > + interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
> > +
> > + regulators {
> > + buck1: BUCK1{
> > + regulator-name = "VDD_SOC_0V9";
> > +
[PATCH] configs: ge_bx50v3: remove CONFIG_PCIE_IMX_POWER_GPIO
This GPIO is actually an input "Q7_3V3_PCIE_WAKE#_IN" not an output, so remove the misleaading and incorrect definition. Cc: Tim Harvey (re: pci: imx: use vpcie-supply if defined by device-tree) Signed-off-by: Ian Ray --- include/configs/ge_bx50v3.h | 1 - 1 file changed, 1 deletion(-) diff --git a/include/configs/ge_bx50v3.h b/include/configs/ge_bx50v3.h index 8d467e4..c80a076 100644 --- a/include/configs/ge_bx50v3.h +++ b/include/configs/ge_bx50v3.h @@ -123,6 +123,5 @@ #define CONFIG_PCI_SCAN_SHOW #define CONFIG_PCIE_IMX -#define CONFIG_PCIE_IMX_POWER_GPIO IMX_GPIO_NR(1, 5) #endif /* __GE_BX50V3_CONFIG_H */ -- 2.10.1
Re: RFC: Updating i.MX8M CPU thermal trip-point at runtime
On 2022/4/14 16:37, Frieder Schrempf wrote: Hi Andrejs, +Cc: Jacky Bai Am 13.04.22 um 14:24 schrieb Andrejs Cainikovs: [Sie erhalten nicht oft E-Mail von "andrejs.cainik...@toradex.com". Weitere Informationen, warum dies wichtig ist, finden Sie unter "http://aka.ms/LearnAboutSenderIdentification;.] Hi everyone, Recent issue that I had to deal with sparkled a discussion within my team, and seems like we are not sure what would be a proper way to go, even if there are multiple ways to do it. We decided to ask this question to open-source community, in case someone has thoughts about it. At Toradex we have multiple computer on modules, each of those has few variants - different memory sizes, with or without WiFi/BT, etc. One of the options is also a temperature grade - IT and non-IT. Obviously, we want to keep number of device trees as minimal as possible, since number of device trees grows exponentially if we add a new option via device tree, i.e. imx8mm-verdin-it-wifi-dev.dts + imx8mm-verdin-nonit-wifi-dev.dts. Hence, we are working on a change that would update trips temperatures in Linux device tree on the fly, setting them to whatever is read from CPU fuses. Now, the question is - where would be the best place to do it? So far we were thinking about following options: - Patching U-Boot thermal driver so that it would propagate max temperature to Linux device tree. - Patching U-Boot board files to update Linux device tree via ft_board_setup(). This, however, will result in a duplicate code among different boards within same SoC family. - Anything else not listed here. I would appreciate any comments or thoughts regarding this topic. Thanks, Thanks for bringing up the topic. We've been discussing this previously here: [1]. The bootloader doesn't really benefit from the information about the temperature grading, does it? Therefore I would rather think about a solution where the kernel itself, or more specifically the TMU driver reads the grading from the fuses and sets the trip points accordingly. So we don't create another dependency between bootloader and kernel. Anyway, if you rather want to handle this in the bootloader and pass it via device tree, I guess this would also be ok. In this case the code should be added to the thermal driver or the platform code and not in any board specific files to avoid duplication, as you already mentioned. I would prefer let bootloader handle this, that would be simple. Regards, Peng. Best regards Frieder [1] https://patchwork.kernel.org/project/linux-arm-kernel/patch/20210601174917.1979-1-thar...@gateworks.com/
[PATCH v7 8/8] doc: uefi: Update the capsule update related documentation
Update the capsule update functionality related documentation to
refect the additional definitions that need to be made per platform
for supporting the capsule update feature.
Signed-off-by: Sughosh Ganu
---
Changes since V6:
* Add example for the struct efi_fw_image array and struct
efi_capsule_update_info as suggested by Takahiro
doc/develop/uefi/uefi.rst | 98 ++-
1 file changed, 96 insertions(+), 2 deletions(-)
diff --git a/doc/develop/uefi/uefi.rst b/doc/develop/uefi/uefi.rst
index fe337c88bd..1aea04a4e8 100644
--- a/doc/develop/uefi/uefi.rst
+++ b/doc/develop/uefi/uefi.rst
@@ -312,8 +312,8 @@ Run the following command
.. code-block:: console
$ mkeficapsule \
- --index 1 --instance 0 \
- [--fit | --raw ] \
+ --index --instance 0 \
+ --guid \
Performing the update
@@ -333,9 +333,102 @@ won't be taken over across the reboot. If this is the
case, you can skip
this feature check with the Kconfig option (CONFIG_EFI_IGNORE_OSINDICATIONS)
set.
+A few values need to be defined in the board file for performing the
+capsule update. These values are defined in the board file by
+initialisation of a structure which provides information needed for
+capsule updates. The following structures have been defined for
+containing the image related information
+
+.. code-block:: c
+
+ struct efi_fw_images {
+ efi_guid_t image_type_id;
+ u16 *fw_name;
+ u8 image_index;
+ };
+
+ struct efi_capsule_update_info {
+ const char *dfu_string;
+ struct efi_fw_image *images;
+ };
+
+
+A string is defined which is to be used for populating the
+dfu_alt_info variable. This string is used by the function
+set_dfu_alt_info. Instead of taking the variable from the environment,
+the capsule update feature requires that the variable be set through
+the function, since that is more robust. Allowing the user to change
+the location of the firmware updates is not a very secure
+practice. Getting this information from the firmware itself is more
+secure, assuming the firmware has been verified by a previous stage
+boot loader.
+
+The firmware images structure defines the GUID values, image index
+values and the name of the images that are to be updated through
+the capsule update feature. These values are to be defined as part of
+an array. These GUID values would be used by the Firmware Management
+Protocol(FMP) to populate the image descriptor array and also
+displayed as part of the ESRT table. The image index values defined in
+the array should be one greater than the dfu alt number that
+corresponds to the firmware image. So, if the dfu alt number for an
+image is 2, the value of image index in the fw_images array for that
+image should be 3. The dfu alt number can be obtained by running the
+following command::
+
+dfu list
+
+When using the FMP for FIT images, the image index value needs to be
+set to 1.
+
Finally, the capsule update can be initiated by rebooting the board.
+An example of setting the values in the struct efi_fw_image and
+struct efi_capsule_update_info is shown below
+
+.. code-block:: c
+
+ struct efi_fw_image fw_images[] = {
+ {
+ .image_type_id = DEVELOPERBOX_UBOOT_IMAGE_GUID,
+ .fw_name = u"DEVELOPERBOX-UBOOT",
+ .image_index = 1,
+ },
+ {
+ .image_type_id = DEVELOPERBOX_FIP_IMAGE_GUID,
+ .fw_name = u"DEVELOPERBOX-FIP",
+ .image_index = 2,
+ },
+ {
+ .image_type_id = DEVELOPERBOX_OPTEE_IMAGE_GUID,
+ .fw_name = u"DEVELOPERBOX-OPTEE",
+ .image_index = 3,
+ },
+ };
+
+ struct efi_capsule_update_info update_info = {
+ .dfu_string = "mtd nor1=u-boot.bin raw 20 10;"
+ "fip.bin raw 18 78000;"
+ "optee.bin raw 50 10",
+ .images = fw_images,
+ };
+
+The platform will define a fw_images array which contains information
+of all the firmware images that are to be updated through capsule
+update mechanism. The dfu_string is the string that is to be set as
+dfu_alt_info. In the example above, the image index to be set for
+u-boot.bin binary is 0x1, for fip.bin is 0x2 and for optee.bin is 0x3.
+
+As an example, for generating the capsule for the optee.bin image, the
+following command can be issued
+
+.. code-block:: bash
+
+$ ./tools/mkeficapsule \
+ --index 0x3 --instance 0 \
+ --guid c1b629f1-ce0e-4894-82bf-f0a38387e630 \
+ optee.bin optee.capsule
+
+
Enabling Capsule Authentication
***
--
2.25.1
