Pull request: u-boot-spi/master
Hi Tom, Please pull this PR. Summary: - NPCM7xx FIU SPI driver (Jim Liu) - AT45DB641E dataflash (Luca Ellero) CI: https://source.denx.de/u-boot/custodians/u-boot-spi/-/pipelines/11912 thanks, Jagan. The following changes since commit c70c0102af5413cadde6bf90044cb75aefef0584: Merge tag 'efi-2022-07-rc2' of https://source.denx.de/u-boot/custodians/u-boot-efi (2022-04-29 14:04:08 -0400) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-spi master for you to fetch changes up to c62f93a620f7c13564a0f4a5583e90a01047901d: sf: dataflash: add support for AT45DB641E (2022-05-03 17:57:19 +0530) Jim Liu (1): spi: npcm-fiu: add NPCM7xx FIU controller driver Luca Ellero (2): sf: dataflash: add support for "extended ID" sf: dataflash: add support for AT45DB641E Marek Vasut (1): mtd: spi-nor-ids: Add Winbond W25Q128JW ID Tien Fong Chee (1): mtd: spi-nor-ids: add Macronix mx25u51245g flash entry drivers/mtd/spi/sf_dataflash.c | 101 +++ drivers/mtd/spi/spi-nor-ids.c | 7 + drivers/spi/Kconfig| 6 + drivers/spi/Makefile | 1 + drivers/spi/npcm_fiu_spi.c | 387 + 5 files changed, 468 insertions(+), 34 deletions(-) create mode 100644 drivers/spi/npcm_fiu_spi.c
Re: [PATCH v2] spi: npcm-fiu: add NPCM7xx FIU controller driver
On Tue, May 3, 2022 at 5:51 PM Jagan Teki wrote: > > From: Jim Liu > > Add Nuvoton NPCM BMC Flash Interface Unit(FIU) SPI master > controller driver using SPI-MEM interface. > > The FIU supports single, dual or quad communication interface. > The FIU controller driver provides flash access in UMA(User > Mode Access) mode by using an indirect address/data mechanism. > > the dts node is followed upstream kernel dts name. > > Signed-off-by: Jim Liu > Signed-off-by: Stanley Chu > Reviewed-by: Jagan Teki > [Jagan: fixed the Kconfig, Makefile order] > Signed-off-by: Jagan Teki > --- Applied to u-boot-spi/master
Re: [PATCH 1/1] dm: fix DM_EVENT dependencies
On 5/3/22 21:35, Tom Rini wrote:
On Tue, May 03, 2022 at 09:18:33PM +0200, Heinrich Schuchardt wrote:
CONFIG_DM_EVENT without CONFIG_EVENT is non-functional. Select instead
of imply CONFIG_EVENT.
Remove superfluous stub in include/event.h.
Fixes: 5b896ed5856f ("event: Add events for device probe/remove")
Reported-by: Jan Kiszka
Signed-off-by: Heinrich Schuchardt
---
drivers/core/Kconfig | 2 +-
include/event.h | 7 +--
2 files changed, 2 insertions(+), 7 deletions(-)
I don't think it makes sense to have two symbols at all. It's part of
DM, it should always be DM_EVENT I suppose.
The event EVT_MISC_INIT_F is used outside of the driver model.
arch/sandbox/cpu/start.c:127:EVENT_SPY(EVT_MISC_INIT_F,
sandbox_misc_init_f);
board/google/chromebook_coral/coral.c:60:EVENT_SPY(EVT_MISC_INIT_F,
coral_check_ll_boot);
board/keymile/kmcent2/kmcent2.c:213:EVENT_SPY(EVT_MISC_INIT_F,
kmcent2_misc_init_f);
board/keymile/pg-wcom-ls102xa/pg-wcom-ls102xa.c:120:EVENT_SPY(EVT_MISC_INIT_F,
pg_wcom_misc_init_f);
Best regards
Heinrich
Re: [PATCH 1/1] cmd: mmc: don't assign unused values
Hi!
2022년 4월 26일 (화) 06:11, Heinrich Schuchardt <
heinrich.schucha...@canonical.com>님이 작성:
> Don't assign a value to variable speedmode which is never used.
>
> Signed-off-by: Heinrich Schuchardt
> ---
> cmd/mmc.c | 6 --
> 1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/cmd/mmc.c b/cmd/mmc.c
> index 7464f8d00c..63bf69b0bd 100644
> --- a/cmd/mmc.c
> +++ b/cmd/mmc.c
> @@ -501,11 +501,12 @@ static int do_mmc_rescan(struct cmd_tbl *cmdtp, int
> flag,
> int argc, char *const argv[])
> {
> struct mmc *mmc;
> - enum bus_mode speed_mode = MMC_MODES_END;
>
> if (argc == 1) {
> mmc = init_mmc_device(curr_device, true);
> } else if (argc == 2) {
> + enum bus_mode speed_mode;
> +
> speed_mode = (int)dectoul(argv[1], NULL);
> mmc = __init_mmc_device(curr_device, true, speed_mode);
> } else {
> @@ -543,7 +544,6 @@ static int do_mmc_dev(struct cmd_tbl *cmdtp, int flag,
> {
> int dev, part = 0, ret;
> struct mmc *mmc;
> - enum bus_mode speed_mode = MMC_MODES_END;
>
> if (argc == 1) {
> dev = curr_device;
> @@ -561,6 +561,8 @@ static int do_mmc_dev(struct cmd_tbl *cmdtp, int flag,
> }
> mmc = init_mmc_device(dev, true);
> } else if (argc == 4) {
> + enum bus_mode speed_mode;
> +
> dev = (int)dectoul(argv[1], NULL);
> part = (int)dectoul(argv[2], NULL);
> if (part > PART_ACCESS_MASK) {
> --
> 2.34.1
> Reviewed-by: Minkyu Kang
Thanks,
--
Thanks. Minkyu Kang.
Re: [PATCH v2] spi: npcm-fiu: add NPCM7xx FIU controller driver
Hi Jagan
Thanks for your reply and correction.
If you have any problems please let me know.
On Tue, May 3, 2022 at 8:21 PM Jagan Teki wrote:
>
> From: Jim Liu
>
> Add Nuvoton NPCM BMC Flash Interface Unit(FIU) SPI master
> controller driver using SPI-MEM interface.
>
> The FIU supports single, dual or quad communication interface.
> The FIU controller driver provides flash access in UMA(User
> Mode Access) mode by using an indirect address/data mechanism.
>
> the dts node is followed upstream kernel dts name.
>
> Signed-off-by: Jim Liu
> Signed-off-by: Stanley Chu
> Reviewed-by: Jagan Teki
> [Jagan: fixed the Kconfig, Makefile order]
> Signed-off-by: Jagan Teki
> ---
> Changes for v2:
> - fixed author e-mail
> - fixed Makefile and Kconfig order
>
> drivers/spi/Kconfig| 6 +
> drivers/spi/Makefile | 1 +
> drivers/spi/npcm_fiu_spi.c | 387 +
> 3 files changed, 394 insertions(+)
> create mode 100644 drivers/spi/npcm_fiu_spi.c
>
> diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
> index 8dba95ae4e..a1e515cb2b 100644
> --- a/drivers/spi/Kconfig
> +++ b/drivers/spi/Kconfig
> @@ -283,6 +283,12 @@ config SPI_MXIC
> can be used to access the SPI flash on platforms embedding
> this Macronix IP core.
>
> +config NPCM_FIU_SPI
> + bool "FIU driver for Nuvoton NPCM SoC"
> + help
> + This enables support for the Flash Interface Unit SPI controller
> + in master mode.
> +
> config NXP_FSPI
> bool "NXP FlexSPI driver"
> depends on SPI_MEM
> diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
> index 7f43f843ca..06e81b465b 100644
> --- a/drivers/spi/Makefile
> +++ b/drivers/spi/Makefile
> @@ -47,6 +47,7 @@ obj-$(CONFIG_MSCC_BB_SPI) += mscc_bb_spi.o
> obj-$(CONFIG_MVEBU_A3700_SPI) += mvebu_a3700_spi.o
> obj-$(CONFIG_MXC_SPI) += mxc_spi.o
> obj-$(CONFIG_MXS_SPI) += mxs_spi.o
> +obj-$(CONFIG_NPCM_FIU_SPI) += npcm_fiu_spi.o
> obj-$(CONFIG_NXP_FSPI) += nxp_fspi.o
> obj-$(CONFIG_ATCSPI200_SPI) += atcspi200_spi.o
> obj-$(CONFIG_OCTEON_SPI) += octeon_spi.o
> diff --git a/drivers/spi/npcm_fiu_spi.c b/drivers/spi/npcm_fiu_spi.c
> new file mode 100644
> index 00..7000fe5860
> --- /dev/null
> +++ b/drivers/spi/npcm_fiu_spi.c
> @@ -0,0 +1,387 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (c) 2022 Nuvoton Technology Corp.
> + * NPCM Flash Interface Unit(FIU) SPI master controller driver.
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +#define DW_SIZE4
> +#define CHUNK_SIZE 16
> +#define XFER_TIMEOUT 100
> +
> +/* FIU UMA Configuration Register (UMA_CFG) */
> +#define UMA_CFG_RDATSIZ_MASK GENMASK(28, 24)
> +#define UMA_CFG_DBSIZ_MASK GENMASK(23, 21)
> +#define UMA_CFG_WDATSIZ_MASK GENMASK(20, 16)
> +#define UMA_CFG_ADDSIZ_MASKGENMASK(13, 11)
> +#define UMA_CFG_RDBPCK_MASKGENMASK(9, 8)
> +#define UMA_CFG_DBPCK_MASK GENMASK(7, 6)
> +#define UMA_CFG_WDBPCK_MASKGENMASK(5, 4)
> +#define UMA_CFG_ADBPCK_MASKGENMASK(3, 2)
> +#define UMA_CFG_CMBPCK_MASKGENMASK(1, 0)
> +#define UMA_CFG_CMDSIZ_SHIFT 10
> +
> +/* FIU UMA Control and Status Register (UMA_CTS) */
> +#define UMA_CTS_SW_CS BIT(16)
> +#define UMA_CTS_EXEC_DONE BIT(0)
> +#define UMA_CTS_RDYST BIT(24)
> +#define UMA_CTS_DEV_NUM_MASK GENMASK(9, 8)
> +
> +struct npcm_fiu_regs {
> + unsigned intdrd_cfg;
> + unsigned intdwr_cfg;
> + unsigned intuma_cfg;
> + unsigned intuma_cts;
> + unsigned intuma_cmd;
> + unsigned intuma_addr;
> + unsigned intprt_cfg;
> + unsigned char res1[4];
> + unsigned intuma_dw0;
> + unsigned intuma_dw1;
> + unsigned intuma_dw2;
> + unsigned intuma_dw3;
> + unsigned intuma_dr0;
> + unsigned intuma_dr1;
> + unsigned intuma_dr2;
> + unsigned intuma_dr3;
> + unsigned intprt_cmd0;
> + unsigned intprt_cmd1;
> + unsigned intprt_cmd2;
> + unsigned intprt_cmd3;
> + unsigned intprt_cmd4;
> + unsigned intprt_cmd5;
> + unsigned intprt_cmd6;
> + unsigned intprt_cmd7;
> + unsigned intprt_cmd8;
> + unsigned intprt_cmd9;
> + unsigned intstuff[4];
> + unsigned intfiu_cfg;
> +};
> +
> +struct npcm_fiu_priv {
> + struct npcm_fiu_regs *regs;
> + struct clk clk;
> +};
> +
> +static int npcm_fiu_spi_set_speed(struct udevice *bus, uint speed)
> +{
> + struct npcm_fiu_priv *priv = dev_get_priv(bus);
> + int ret;
> +
> + debug("%s: set speed %u\n", bus->name, speed);
> + ret = clk_set_rate(&priv->clk, speed);
> + if (ret < 0)
> + return ret;
> +
> + return 0;
> +}
> +
> +static int npcm_fiu_spi_set_mode(struct udevice *bus
Re: [PATCH] Convert CONFIG_MTD_CONCAT to Kconfig
On 03.05.22 11:24, Chris Packham wrote: This converts the following to Kconfig: CONFIG_MTD_CONCAT Signed-off-by: Chris Packham --- This touches octeontx_common.h but only to remove a line that is already commented out. Other than that etamin was the only board that had this enabled. Reviewed-by: Stefan Roese Thanks, Stefan configs/etamin_defconfig | 1 + drivers/mtd/Kconfig | 8 include/configs/etamin.h | 1 - include/configs/octeontx_common.h | 1 - scripts/config_whitelist.txt | 1 - 5 files changed, 9 insertions(+), 3 deletions(-) diff --git a/configs/etamin_defconfig b/configs/etamin_defconfig index ba7a0665dedb..34b9fff5ded2 100644 --- a/configs/etamin_defconfig +++ b/configs/etamin_defconfig @@ -87,6 +87,7 @@ CONFIG_SPL_SYS_I2C_LEGACY=y # CONFIG_SPL_DM_MMC is not set CONFIG_MMC_OMAP_HS=y CONFIG_MTD=y +CONFIG_MTD_CONCAT=y CONFIG_MTD_RAW_NAND=y CONFIG_NAND_OMAP_ECCSCHEME_BCH16_CODE_HW=y CONFIG_SYS_NAND_BLOCK_SIZE=0x8 diff --git a/drivers/mtd/Kconfig b/drivers/mtd/Kconfig index 588ebe9119b9..4088267dd111 100644 --- a/drivers/mtd/Kconfig +++ b/drivers/mtd/Kconfig @@ -22,6 +22,14 @@ config MTD_NOR_FLASH help Enable support for parallel NOR flash. +config MTD_CONCAT + bool "Enable MTD device concatenation" + depends on MTD + help + Enable support for concatenating multiple physical MTD devices + into a single logical device. The larger logical device can then + be partitioned. + config SYS_MTDPARTS_RUNTIME bool "Allow MTDPARTS to be configured at runtime" depends on MTD diff --git a/include/configs/etamin.h b/include/configs/etamin.h index dc83ab71908b..9cf93924df93 100644 --- a/include/configs/etamin.h +++ b/include/configs/etamin.h @@ -151,7 +151,6 @@ #define ETAMIN_NAND_GPMC_CONFIG4 0x16051807 #define ETAMIN_NAND_GPMC_CONFIG5 0x00151e1e #define ETAMIN_NAND_GPMC_CONFIG6 0x16000f80 -#define CONFIG_MTD_CONCAT /* Default env settings */ #define CONFIG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/octeontx_common.h b/include/configs/octeontx_common.h index bcf8b41cfb63..81dbff2d672f 100644 --- a/include/configs/octeontx_common.h +++ b/include/configs/octeontx_common.h @@ -64,7 +64,6 @@ /** EMMC specific defines */ #if defined(CONFIG_NAND_OCTEONTX) -/*#define CONFIG_MTD_CONCAT */ #define CONFIG_SYS_MAX_NAND_DEVICE 8 #endif diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 5b882b2670ca..cecdda678191 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -389,7 +389,6 @@ CONFIG_MMC_SUNXI_SLOT CONFIG_MONITOR_IS_IN_RAM CONFIG_MPC85XX_FEC CONFIG_MPC85XX_FEC_NAME -CONFIG_MTD_CONCAT CONFIG_MTD_NAND_VERIFY_WRITE CONFIG_MTD_PARTITION CONFIG_MVGBE_PORTS Viele Grüße, Stefan Roese -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-51 Fax: (+49)-8142-66989-80 Email: s...@denx.de
Re: [PATCH] cmd: mvebu: Hide bubt specific options when bubt is disabled
On 03.05.22 11:13, Pali Rohár wrote: CONFIG_MVEBU_NAND_BOOT, CONFIG_MVEBU_SPI_BOOT, CONFIG_MVEBU_MMC_BOOT and CONFIG_MVEBU_UBOOT_DFLT_NAME are unused when CONFIG_CMD_MVEBU_BUBT is not enabled. So hide them. Signed-off-by: Pali Rohár Reviewed-by: Stefan Roese Thanks, Stefan --- cmd/mvebu/Kconfig | 4 1 file changed, 4 insertions(+) diff --git a/cmd/mvebu/Kconfig b/cmd/mvebu/Kconfig index ac8b0afd20e5..39963db82c98 100644 --- a/cmd/mvebu/Kconfig +++ b/cmd/mvebu/Kconfig @@ -9,6 +9,8 @@ config CMD_MVEBU_BUBT For details about bubt command please see the documentation in doc/mvebu/cmd/bubt.txt +if CMD_MVEBU_BUBT + choice prompt "Flash for image" default MVEBU_SPI_BOOT @@ -49,6 +51,8 @@ config MVEBU_UBOOT_DFLT_NAME This option should contain a default file name to be used with MVEBU "bubt" command if the source file name is omitted +endif + config CMD_MVEBU_COMPHY_RX_TRAINING bool "mvebu_comphy_rx_training" depends on ARMADA_8K Viele Grüße, Stefan Roese -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-51 Fax: (+49)-8142-66989-80 Email: s...@denx.de
Re: [PATCH] arm: mvebu: Espressobin: Add NVMe to boot targets
On 03.05.22 11:01, Pali Rohár wrote: NVMe support is already enabled, so add it into boot targets. Signed-off-by: Pali Rohár Reviewed-by: Stefan Roese Thanks, Stefan --- include/configs/mvebu_armada-37xx.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/configs/mvebu_armada-37xx.h b/include/configs/mvebu_armada-37xx.h index 778f8b828aa8..953dfe812558 100644 --- a/include/configs/mvebu_armada-37xx.h +++ b/include/configs/mvebu_armada-37xx.h @@ -50,6 +50,7 @@ func(MMC, mmc, 1) \ func(MMC, mmc, 0) \ func(USB, usb, 0) \ + func(NVME, nvme, 0) \ func(SCSI, scsi, 0) \ func(PXE, pxe, na) \ func(DHCP, dhcp, na) Viele Grüße, Stefan Roese -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-51 Fax: (+49)-8142-66989-80 Email: s...@denx.de
RE: [PATCH 3/8] spi: aspeed: Add ASPEED SPI controller driver
Hi Jagan, > -Original Message- > From: Jagan Teki > Sent: Tuesday, May 3, 2022 9:23 PM > To: Chin-Ting Kuo > Subject: Re: [PATCH 3/8] spi: aspeed: Add ASPEED SPI controller driver > > On Tue, May 3, 2022 at 6:44 PM Chin-Ting Kuo > wrote: > > > > Hi Jagan, > > > > Thanks for the review. > > > > > -Original Message- > > > From: Jagan Teki > > > Sent: Tuesday, May 3, 2022 8:32 PM > > > To: Chin-Ting Kuo > > > Subject: Re: [PATCH 3/8] spi: aspeed: Add ASPEED SPI controller > > > driver > > > > > > On Thu, Apr 14, 2022 at 4:54 PM Chin-Ting Kuo > > > wrote: > > > > > > > > Add ASPEED BMC FMC/SPI memory controller driver with spi-mem > > > > interface for AST2500 and AST2600 platform. > > > > > > > > There are three SPI memory controllers embedded in an ASPEED SoC. > > > > - FMC: Named as Firmware Memory Controller. After AC on, MCU ROM > > > >fetches initial device boot image from FMC chip select(CS) 0. > > > > > > > > - SPI1: Play the role of a SPI Master controller. Or, there is a > > > > dedicated path for HOST(X86) to access its BIOS flash mounted > > > > under BMC. spi-aspeed.c implements the control sequence > when > > > > SPI1 is a SPI master. > > > > > > > > - SPI2: It is a pure SPI flash controller. For most scenarios, flashes > > > > mounted under it are for pure storage purpose. > > > > > > > > ASPEED SPI controller supports 1-1-1, 1-1-2 and 1-1-4 SPI flash mode. > > > > Three types of command mode are supported, normal mode, command > > > > read/write mode and user mode. > > > > - Normal mode: Default mode. After power on, normal read command > > > > 03h > > > or > > > >13h is used to fetch boot image from SPI flash. > > > >- AST2500: Only 03h command can be used after > power > > > on > > > > or reset. > > > >- AST2600: If FMC04[6:4] is set, 13h command is used, > > > > otherwise, 03h command. > > > >The address length is decided by FMC04[2:0]. > > > > > > > > - Command mode: SPI controller can send command and address > > > > automatically when CPU read/write the related > > > remapped > > > > or decoded address area. The command used by this > > > mode > > > > can be configured by FMC10/14/18[23:16]. Also, the > > > > address length is decided by FMC04[2:0]. This mode > will > > > > be implemented in the following patch series. > > > > > > > > - User mode: It is a traditional and pure SPI operation, where > > > > SPI transmission is controlled by CPU. It is the main > > > > mode in this patch. > > > > > > > > Each SPI controller in ASPEED SoC has its own decoded address mapping. > > > > Within each SPI controller decoded address, driver can assign a > > > > specific address region for each CS of a SPI controller. The > > > > decoded address cannot overlap to each other. With normal mode and > > > > command mode, the decoded address accessed by the CPU determines > > > > which CS is > > > active. > > > > When user mode is adopted, the CS decoded address is a FIFO, CPU > > > > can send/receive any SPI transmission by accessing the related > > > > decoded address for the target CS. > > > > > > > > Signed-off-by: Chin-Ting Kuo > > > > --- > > > > configs/evb-ast2500_defconfig | 13 + > > > > configs/evb-ast2600_defconfig > > > > | 13 + > > > > drivers/spi/Kconfig | 8 + > > > > drivers/spi/Makefile | 1 + > > > > drivers/spi/spi-aspeed.c | 822 > > > ++ > > > > 5 files changed, 857 insertions(+) create mode 100644 > > > > drivers/spi/spi-aspeed.c > > > > > > > > diff --git a/configs/evb-ast2500_defconfig > > > > b/configs/evb-ast2500_defconfig index 53fe7776e9..f00bded237 > > > > 100644 > > > > --- a/configs/evb-ast2500_defconfig > > > > +++ b/configs/evb-ast2500_defconfig > > > > @@ -36,6 +36,16 @@ CONFIG_DM_I2C=y CONFIG_SYS_I2C_ASPEED=y > > > > CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ASPEED=y > > > > +CONFIG_DM_SPI_FLASH=y > > > > +CONFIG_SPI_FLASH_SFDP_SUPPORT=y > > > > +CONFIG_SPI_FLASH_GIGADEVICE=y > > > > +CONFIG_SPI_FLASH_ISSI=y > > > > +CONFIG_SPI_FLASH_MACRONIX=y > > > > +CONFIG_SPI_FLASH_SPANSION=y > > > > +CONFIG_SPI_FLASH_STMICRO=y > > > > +CONFIG_SPI_FLASH_SST=y > > > > +CONFIG_SPI_FLASH_WINBOND=y > > > > +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set > > > > CONFIG_PHY_REALTEK=y > > > > CONFIG_DM_ETH=y > > > > CONFIG_FTGMAC100=y > > > > @@ -45,6 +55,9 @@ CONFIG_RAM=y > > > > CONFIG_DM_RESET=y > > > > CONFIG_DM_SERIAL=y > > > > CONFIG_SYS_NS16550=y > > > > +CONFIG_SPI=y > > > > +CONFIG_DM_SPI=y > > > > +CONFIG_SPI_ASPEED=y > > > > CONFIG_SYSRESET=y > > > > CONFIG_TIMER=y > > > > CONFIG_WDT=y > > > > diff --git a/configs/evb-ast2600_defconfig > > > > b/configs/evb-ast2600_defconfig index ea75762926..e013976bb0 > > > > 100644 > > > > --- a/
Re: [PATCH v3 01/18] virtio: pci: Allow exclusion of legacy driver
On Thu, Apr 21, 2022 at 04:10:59PM +, Andrew Scull wrote: > Add a new config to control whether the driver for legacy virtio PCI > devices is included in the build. VIRTIO_PCI_LEGACY is included by > default when VIRTIO_PCI is selected, but it can also be independently > toggled. > > Signed-off-by: Andrew Scull > Reviewed-by: Bin Meng For the series, applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
[PATCH 7/7] sunxi: licheepi_nano: enable SPI flash
Many LicheePi Nano boards come with SPI flash soldered, which already works for booting the SPL and loading U-Boot proper. With the updated DTB, we can now also use the SPI flash from U-Boot proper, so enable the bits in the defconfig, to allow loading binaries from SPI flash. There seem to be board revisions with a Winbond SPI chip, but also others with an XTX chip, so include support for both: the actual chip used will be autodetected. Signed-off-by: Andre Przywara --- configs/licheepi_nano_defconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/configs/licheepi_nano_defconfig b/configs/licheepi_nano_defconfig index 9fd1dcc9958..dfdc7d46855 100644 --- a/configs/licheepi_nano_defconfig +++ b/configs/licheepi_nano_defconfig @@ -10,3 +10,6 @@ CONFIG_DRAM_CLK=156 CONFIG_DRAM_ZQ=0 # CONFIG_VIDEO_SUNXI is not set CONFIG_SPL_SPI_SUNXI=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SPI_FLASH_XTX=y +CONFIG_SPI=y -- 2.35.3
[PATCH 6/7] Revert "sunxi: f1c100s: Drop SYSRESET to enable reset functionality"
The original Allwinner F1C100 .dtsi imported from the Linux kernel tree used the wrong compatible string for the watchdog timer, so the Allwinner DM reset driver was not working properly. We worked around this by disabling the SYSRESET driver, so the hardcoded SPL reset driver took over. Now the issue was fixed in the DTs in mainline Linux, and we synced the fixed .dtsi file into U-Boot, so drop the hack and use the normal U-Boot proper reset infrastructure. This reverts commit cfcf1952c11e6ffcbbf88eb63c49edca2acf1d5e. Signed-off-by: Andre Przywara --- configs/licheepi_nano_defconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/configs/licheepi_nano_defconfig b/configs/licheepi_nano_defconfig index 67b7b85c491..9fd1dcc9958 100644 --- a/configs/licheepi_nano_defconfig +++ b/configs/licheepi_nano_defconfig @@ -10,4 +10,3 @@ CONFIG_DRAM_CLK=156 CONFIG_DRAM_ZQ=0 # CONFIG_VIDEO_SUNXI is not set CONFIG_SPL_SPI_SUNXI=y -# CONFIG_SYSRESET is not set -- 2.35.3
[PATCH 5/7] sunxi: F1C100s: update DT files from Linux
The initial U-Boot F1C100s port was based on the mainline kernel DT
files, which were quite basic and were missing the essential MMC and
SPI peripherals. While we could work around this in the SPL by
hardcoding the required information, this left U-Boot proper without SD
card or SPI flash support, so actual loading would require FEL boot.
Now the missing DT bits have been submitted and accepted in the kernel
tree, so lets sync back those files into U-Boot to enable MMC and
SPI, plus benefit from some fixes.
This is a verbatim copy of the .dts and .dtsi file from
linux-sunxi/dt-for-5.19[1], which have been part of linux-next for a
while as well.
[1]
https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux.git/log/?h=sunxi/dt-for-5.19
Link:
https://lore.kernel.org/linux-arm-kernel/20220317162349.739636-1-andre.przyw...@arm.com/
Signed-off-by: Andre Przywara
---
arch/arm/dts/suniv-f1c100s-licheepi-nano.dts | 31 ++
arch/arm/dts/suniv-f1c100s.dtsi | 104 +--
2 files changed, 125 insertions(+), 10 deletions(-)
diff --git a/arch/arm/dts/suniv-f1c100s-licheepi-nano.dts
b/arch/arm/dts/suniv-f1c100s-licheepi-nano.dts
index a1154e6c7cb..04e59b8381c 100644
--- a/arch/arm/dts/suniv-f1c100s-licheepi-nano.dts
+++ b/arch/arm/dts/suniv-f1c100s-licheepi-nano.dts
@@ -11,12 +11,43 @@
compatible = "licheepi,licheepi-nano", "allwinner,suniv-f1c100s";
aliases {
+ mmc0 = &mmc0;
serial0 = &uart0;
+ spi0 = &spi0;
};
chosen {
stdout-path = "serial0:115200n8";
};
+
+ reg_vcc3v3: vcc3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3";
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ };
+};
+
+&mmc0 {
+ broken-cd;
+ bus-width = <4>;
+ disable-wp;
+ status = "okay";
+ vmmc-supply = <®_vcc3v3>;
+};
+
+&spi0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi0_pc_pins>;
+ status = "okay";
+
+ flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "winbond,w25q128", "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <4000>;
+ };
};
&uart0 {
diff --git a/arch/arm/dts/suniv-f1c100s.dtsi b/arch/arm/dts/suniv-f1c100s.dtsi
index 6100d3b75f6..0edc1724407 100644
--- a/arch/arm/dts/suniv-f1c100s.dtsi
+++ b/arch/arm/dts/suniv-f1c100s.dtsi
@@ -4,6 +4,9 @@
* Copyright 2018 Mesih Kilinc
*/
+#include
+#include
+
/ {
#address-cells = <1>;
#size-cells = <1>;
@@ -26,9 +29,13 @@
};
cpus {
- cpu {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
compatible = "arm,arm926ej-s";
device_type = "cpu";
+ reg = <0x0>;
};
};
@@ -62,6 +69,70 @@
};
};
+ spi0: spi@1c05000 {
+ compatible = "allwinner,suniv-f1c100s-spi",
+"allwinner,sun8i-h3-spi";
+ reg = <0x01c05000 0x1000>;
+ interrupts = <10>;
+ clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_BUS_SPI0>;
+ clock-names = "ahb", "mod";
+ resets = <&ccu RST_BUS_SPI0>;
+ status = "disabled";
+ num-cs = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ spi1: spi@1c06000 {
+ compatible = "allwinner,suniv-f1c100s-spi",
+"allwinner,sun8i-h3-spi";
+ reg = <0x01c06000 0x1000>;
+ interrupts = <11>;
+ clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_BUS_SPI1>;
+ clock-names = "ahb", "mod";
+ resets = <&ccu RST_BUS_SPI1>;
+ status = "disabled";
+ num-cs = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mmc0: mmc@1c0f000 {
+ compatible = "allwinner,suniv-f1c100s-mmc",
+"allwinner,sun7i-a20-mmc";
+ reg = <0x01c0f000 0x1000>;
+ clocks = <&ccu CLK_BUS_MMC0>,
+<&ccu CLK_MMC0>,
+<&ccu CLK_MMC0_OUTPUT>,
+<&ccu CLK_MMC0_SAMPLE>;
+ clock-names = "ahb", "mmc", "output", "sample";
+ resets = <&ccu RST_BUS_MMC0>;
+ reset-names = "ahb";
+
[PATCH 4/7] spi: sunxi: Add support for F1C100s SPI controller
The SPI controllers in the Allwinner F1Cx00 series of SoCs are
compatible to the H3 IP. The only difference in the integration is
the missing mod clock in the F1C100, instead the SPI clock is directly
derived from the AHB clock.
We *should* be able to model this through the DT, but the addition of
get_rate() requires quite some refactoring, so it's not really worth in
this simple case: We programmed both the PLL_PERIPH to 600 MHz and the
PLL/AHB divider to 3 in the SPL, so we know the SPI base clock is 200
MHz. Since we used a hard coded fixed clock rate of 24 MHz for all the
other SoCs so far, we can as well do the same for the F1C100.
Define the SPI input clock and maximum frequency differently when
compiling for the F1C100 SoC.
Also adjust the power-of-2 divider programming, because that uses a
"minus one" encoding, compared to the other SoCs.
This allows to enable SPI flash support for the F1C100 boards.
Signed-off-by: Andre Przywara
---
drivers/spi/spi-sunxi.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/spi/spi-sunxi.c b/drivers/spi/spi-sunxi.c
index d1e8692ede2..2f7725e 100644
--- a/drivers/spi/spi-sunxi.c
+++ b/drivers/spi/spi-sunxi.c
@@ -72,9 +72,15 @@ DECLARE_GLOBAL_DATA_PTR;
#define SUN4I_XMIT_CNT(cnt)((cnt) & SUN4I_MAX_XFER_SIZE)
#define SUN4I_FIFO_STA_RF_CNT_BITS 0
+#ifdef CONFIG_MACH_SUNIV
+/* the AHB clock, which we programmed to be 1/3 of PLL_PERIPH@600MHz */
+#define SUNXI_INPUT_CLOCK 2 /* 200 MHz */
+#define SUN4I_SPI_MAX_RATE (SUNXI_INPUT_CLOCK / 2)
+#else
/* the SPI mod clock, defaulting to be 1/1 of the HOSC@24MHz */
#define SUNXI_INPUT_CLOCK 2400/* 24 MHz */
#define SUN4I_SPI_MAX_RATE SUNXI_INPUT_CLOCK
+#endif
#define SUN4I_SPI_MIN_RATE 3000
#define SUN4I_SPI_DEFAULT_RATE 100
#define SUN4I_SPI_TIMEOUT_US 100
@@ -256,6 +262,9 @@ static void sun4i_spi_set_speed_mode(struct udevice *dev)
reg |= SUN4I_CLK_CTL_CDR2(div) | SUN4I_CLK_CTL_DRS;
} else {
div = fls(div - 1);
+ /* The F1C100s encodes the divider as 2^(n+1) */
+ if (CONFIG_IS_ENABLED(CONFIG_MACH_SUNIV))
+ div--;
reg &= ~((SUN4I_CLK_CTL_CDR1_MASK << 8) | SUN4I_CLK_CTL_DRS);
reg |= SUN4I_CLK_CTL_CDR1(div);
}
--
2.35.3
[PATCH 2/7] spi: sunxi: refactor SPI speed/mode programming
As George rightfully pointed out [1], the spi-sunxi driver programs the
speed and mode settings only when the respective functions are called,
but this gets lost over a call to release_bus(). That asserts the
reset line, thus forces each SPI register back to its default value.
Adding to that, trying to program SPI_CCR and SPI_TCR might be pointless
in the first place, when the reset line is still asserted (before
claim_bus()), so those setting won't apply most of the time. In reality
I see two nested claim_bus() calls for the first use, so settings between
the two would work (for instance for the initial "sf probe"). However
later on the speed setting is not programmed into the hardware anymore.
So far we get away with that default frequency, because that is a rather
tame 24 MHz, which most SPI flash chips can handle just fine.
Move the actual register programming into a separate function, and use
.set_speed and .set_mode just to set the variables in our priv structure.
Then we only call this new function in claim_bus(), when we are sure
that register accesses actually work and are preserved.
[1] https://lore.kernel.org/u-boot/20210725231636.879913-17...@yifangu.com/
Signed-off-by: Andre Przywara
Reported-by: George Hilliard
---
drivers/spi/spi-sunxi.c | 95 ++---
1 file changed, 52 insertions(+), 43 deletions(-)
diff --git a/drivers/spi/spi-sunxi.c b/drivers/spi/spi-sunxi.c
index b6cd7ddafad..d6b2dd09514 100644
--- a/drivers/spi/spi-sunxi.c
+++ b/drivers/spi/spi-sunxi.c
@@ -221,6 +221,56 @@ err_ahb:
return ret;
}
+static void sun4i_spi_set_speed_mode(struct udevice *dev)
+{
+ struct sun4i_spi_priv *priv = dev_get_priv(dev);
+ unsigned int div;
+ u32 reg;
+
+ /*
+* Setup clock divider.
+*
+* We have two choices there. Either we can use the clock
+* divide rate 1, which is calculated thanks to this formula:
+* SPI_CLK = MOD_CLK / (2 ^ (cdr + 1))
+* Or we can use CDR2, which is calculated with the formula:
+* SPI_CLK = MOD_CLK / (2 * (cdr + 1))
+* Whether we use the former or the latter is set through the
+* DRS bit.
+*
+* First try CDR2, and if we can't reach the expected
+* frequency, fall back to CDR1.
+*/
+
+ div = SUN4I_SPI_MAX_RATE / (2 * priv->freq);
+ reg = readl(SPI_REG(priv, SPI_CCR));
+
+ if (div <= (SUN4I_CLK_CTL_CDR2_MASK + 1)) {
+ if (div > 0)
+ div--;
+
+ reg &= ~(SUN4I_CLK_CTL_CDR2_MASK | SUN4I_CLK_CTL_DRS);
+ reg |= SUN4I_CLK_CTL_CDR2(div) | SUN4I_CLK_CTL_DRS;
+ } else {
+ div = __ilog2(SUN4I_SPI_MAX_RATE) - __ilog2(priv->freq);
+ reg &= ~((SUN4I_CLK_CTL_CDR1_MASK << 8) | SUN4I_CLK_CTL_DRS);
+ reg |= SUN4I_CLK_CTL_CDR1(div);
+ }
+
+ writel(reg, SPI_REG(priv, SPI_CCR));
+
+ reg = readl(SPI_REG(priv, SPI_TCR));
+ reg &= ~(SPI_BIT(priv, SPI_TCR_CPOL) | SPI_BIT(priv, SPI_TCR_CPHA));
+
+ if (priv->mode & SPI_CPOL)
+ reg |= SPI_BIT(priv, SPI_TCR_CPOL);
+
+ if (priv->mode & SPI_CPHA)
+ reg |= SPI_BIT(priv, SPI_TCR_CPHA);
+
+ writel(reg, SPI_REG(priv, SPI_TCR));
+}
+
static int sun4i_spi_claim_bus(struct udevice *dev)
{
struct sun4i_spi_priv *priv = dev_get_priv(dev->parent);
@@ -240,6 +290,8 @@ static int sun4i_spi_claim_bus(struct udevice *dev)
setbits_le32(SPI_REG(priv, SPI_TCR), SPI_BIT(priv, SPI_TCR_CS_MANUAL) |
SPI_BIT(priv, SPI_TCR_CS_ACTIVE_LOW));
+ sun4i_spi_set_speed_mode(dev->parent);
+
return 0;
}
@@ -329,46 +381,14 @@ static int sun4i_spi_set_speed(struct udevice *dev, uint
speed)
{
struct sun4i_spi_plat *plat = dev_get_plat(dev);
struct sun4i_spi_priv *priv = dev_get_priv(dev);
- unsigned int div;
- u32 reg;
if (speed > plat->max_hz)
speed = plat->max_hz;
if (speed < SUN4I_SPI_MIN_RATE)
speed = SUN4I_SPI_MIN_RATE;
- /*
-* Setup clock divider.
-*
-* We have two choices there. Either we can use the clock
-* divide rate 1, which is calculated thanks to this formula:
-* SPI_CLK = MOD_CLK / (2 ^ (cdr + 1))
-* Or we can use CDR2, which is calculated with the formula:
-* SPI_CLK = MOD_CLK / (2 * (cdr + 1))
-* Whether we use the former or the latter is set through the
-* DRS bit.
-*
-* First try CDR2, and if we can't reach the expected
-* frequency, fall back to CDR1.
-*/
-
- div = SUN4I_SPI_MAX_RATE / (2 * speed);
- reg = readl(SPI_REG(priv, SPI_CCR));
-
- if (div <= (SUN4I_CLK_CTL_CDR2_MASK + 1)) {
- if (div > 0)
- div--;
-
- reg &= ~(SUN4I_CLK_CTL_CDR2_MASK | SUN4I_CLK_CTL_DRS);
- reg |= S
[PATCH 3/7] spi: sunxi: improve SPI clock calculation
The current SPI clock divider calculation has two problems:
- We use a normal round-down division, which results in a divider
typically being too small, resulting in a too high frequency on the bus.
- The calculation for the power-of-two divider is very inaccurate, and
again rounds down, which might lead to wild bus frequencies.
This wasn't a real problem so far, since most chips can handle slightly
higher bus frequencies just fine. Also the actual speed was mostly lost
anyway, due to release_bus() reseting the device. And the power-of-2
calculation was probably never used, because it only applies to
frequencies below 47 KHz.
However this will become a problem for the F1C100s support, due to its
much higher base frequency.
Calculate a safe divider correctly (using round-up), and re-use that
value when calculating the power-of-2 value. We also separate the
maximum frequency and the input clock on the way, since they will be
different for the F1C100s.
Signed-off-by: Andre Przywara
---
drivers/spi/spi-sunxi.c | 11 +++
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/drivers/spi/spi-sunxi.c b/drivers/spi/spi-sunxi.c
index d6b2dd09514..d1e8692ede2 100644
--- a/drivers/spi/spi-sunxi.c
+++ b/drivers/spi/spi-sunxi.c
@@ -72,7 +72,9 @@ DECLARE_GLOBAL_DATA_PTR;
#define SUN4I_XMIT_CNT(cnt)((cnt) & SUN4I_MAX_XFER_SIZE)
#define SUN4I_FIFO_STA_RF_CNT_BITS 0
-#define SUN4I_SPI_MAX_RATE 2400
+/* the SPI mod clock, defaulting to be 1/1 of the HOSC@24MHz */
+#define SUNXI_INPUT_CLOCK 2400/* 24 MHz */
+#define SUN4I_SPI_MAX_RATE SUNXI_INPUT_CLOCK
#define SUN4I_SPI_MIN_RATE 3000
#define SUN4I_SPI_DEFAULT_RATE 100
#define SUN4I_SPI_TIMEOUT_US 100
@@ -242,17 +244,18 @@ static void sun4i_spi_set_speed_mode(struct udevice *dev)
* frequency, fall back to CDR1.
*/
- div = SUN4I_SPI_MAX_RATE / (2 * priv->freq);
+ div = DIV_ROUND_UP(SUNXI_INPUT_CLOCK, priv->freq);
reg = readl(SPI_REG(priv, SPI_CCR));
- if (div <= (SUN4I_CLK_CTL_CDR2_MASK + 1)) {
+ if ((div / 2) <= (SUN4I_CLK_CTL_CDR2_MASK + 1)) {
+ div /= 2;
if (div > 0)
div--;
reg &= ~(SUN4I_CLK_CTL_CDR2_MASK | SUN4I_CLK_CTL_DRS);
reg |= SUN4I_CLK_CTL_CDR2(div) | SUN4I_CLK_CTL_DRS;
} else {
- div = __ilog2(SUN4I_SPI_MAX_RATE) - __ilog2(priv->freq);
+ div = fls(div - 1);
reg &= ~((SUN4I_CLK_CTL_CDR1_MASK << 8) | SUN4I_CLK_CTL_DRS);
reg |= SUN4I_CLK_CTL_CDR1(div);
}
--
2.35.3
[PATCH 1/7] clk: sunxi: implement clock driver for suniv f1c100s
From: George Hilliard
The f1c100s has a clock tree similar to those of other sunxi parts.
Add support for it.
Signed-off-by: George Hilliard
Signed-off-by: Yifan Gu
Acked-by: Sean Anderson
[Andre: add PIO and I2C]
Signed-off-by: Andre Przywara
---
drivers/clk/sunxi/Kconfig | 7
drivers/clk/sunxi/Makefile | 1 +
drivers/clk/sunxi/clk_f1c100s.c | 74 +
3 files changed, 82 insertions(+)
create mode 100644 drivers/clk/sunxi/clk_f1c100s.c
diff --git a/drivers/clk/sunxi/Kconfig b/drivers/clk/sunxi/Kconfig
index f19908113e1..bf11fad6eef 100644
--- a/drivers/clk/sunxi/Kconfig
+++ b/drivers/clk/sunxi/Kconfig
@@ -10,6 +10,13 @@ config CLK_SUNXI
if CLK_SUNXI
+config CLK_SUNIV_F1C100S
+ bool "Clock driver for Allwinner F1C100s"
+ default MACH_SUNIV
+ help
+ This enables common clock driver support for platforms based
+ on Allwinner F1C100s SoC.
+
config CLK_SUN4I_A10
bool "Clock driver for Allwinner A10/A20"
default MACH_SUN4I || MACH_SUN7I
diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile
index 48a48a2f000..895da02ebea 100644
--- a/drivers/clk/sunxi/Makefile
+++ b/drivers/clk/sunxi/Makefile
@@ -8,6 +8,7 @@ obj-$(CONFIG_CLK_SUNXI) += clk_sunxi.o
obj-$(CONFIG_CLK_SUNXI) += clk_sun6i_rtc.o
+obj-$(CONFIG_CLK_SUNIV_F1C100S) += clk_f1c100s.o
obj-$(CONFIG_CLK_SUN4I_A10) += clk_a10.o
obj-$(CONFIG_CLK_SUN5I_A10S) += clk_a10s.o
obj-$(CONFIG_CLK_SUN6I_A31) += clk_a31.o
diff --git a/drivers/clk/sunxi/clk_f1c100s.c b/drivers/clk/sunxi/clk_f1c100s.c
new file mode 100644
index 000..72cf8a6e5c0
--- /dev/null
+++ b/drivers/clk/sunxi/clk_f1c100s.c
@@ -0,0 +1,74 @@
+// SPDX-License-Identifier: (GPL-2.0+)
+/*
+ * Copyright (C) 2019 George Hilliard .
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+static struct ccu_clk_gate f1c100s_gates[] = {
+ [CLK_BUS_MMC0] = GATE(0x060, BIT(8)),
+ [CLK_BUS_MMC1] = GATE(0x060, BIT(9)),
+ [CLK_BUS_SPI0] = GATE(0x060, BIT(20)),
+ [CLK_BUS_SPI1] = GATE(0x060, BIT(21)),
+ [CLK_BUS_OTG] = GATE(0x060, BIT(24)),
+
+ [CLK_BUS_I2C0] = GATE(0x068, BIT(16)),
+ [CLK_BUS_I2C1] = GATE(0x068, BIT(17)),
+ [CLK_BUS_I2C2] = GATE(0x068, BIT(18)),
+ [CLK_BUS_PIO] = GATE(0x068, BIT(19)),
+
+ [CLK_BUS_UART0] = GATE(0x06c, BIT(20)),
+ [CLK_BUS_UART1] = GATE(0x06c, BIT(21)),
+ [CLK_BUS_UART2] = GATE(0x06c, BIT(22)),
+
+ [CLK_USB_PHY0] = GATE(0x0cc, BIT(1)),
+};
+
+static struct ccu_reset f1c100s_resets[] = {
+ [RST_USB_PHY0] = RESET(0x0cc, BIT(0)),
+
+ [RST_BUS_MMC0] = RESET(0x2c0, BIT(8)),
+ [RST_BUS_MMC1] = RESET(0x2c0, BIT(9)),
+ [RST_BUS_SPI0] = RESET(0x2c0, BIT(20)),
+ [RST_BUS_SPI1] = RESET(0x2c0, BIT(21)),
+ [RST_BUS_OTG] = RESET(0x2c0, BIT(24)),
+
+ [RST_BUS_I2C0] = RESET(0x2d0, BIT(16)),
+ [RST_BUS_I2C1] = RESET(0x2d0, BIT(17)),
+ [RST_BUS_I2C2] = RESET(0x2d0, BIT(18)),
+ [RST_BUS_UART0] = RESET(0x2d0, BIT(20)),
+ [RST_BUS_UART1] = RESET(0x2d0, BIT(21)),
+ [RST_BUS_UART2] = RESET(0x2d0, BIT(22)),
+};
+
+static const struct ccu_desc f1c100s_ccu_desc = {
+ .gates = f1c100s_gates,
+ .resets = f1c100s_resets,
+};
+
+static int f1c100s_clk_bind(struct udevice *dev)
+{
+ return sunxi_reset_bind(dev, ARRAY_SIZE(f1c100s_resets));
+}
+
+static const struct udevice_id f1c100s_clk_ids[] = {
+ { .compatible = "allwinner,suniv-f1c100s-ccu",
+ .data = (ulong)&f1c100s_ccu_desc },
+ { }
+};
+
+U_BOOT_DRIVER(clk_suniv_f1c100s) = {
+ .name = "suniv_f1c100s_ccu",
+ .id = UCLASS_CLK,
+ .of_match = f1c100s_clk_ids,
+ .priv_auto = sizeof(struct ccu_priv),
+ .ops= &sunxi_clk_ops,
+ .probe = sunxi_clk_probe,
+ .bind = f1c100s_clk_bind,
+};
--
2.35.3
[PATCH 0/7] sunxi: F1C100s: enable MMC and SPI in U-Boot proper
So far the U-Boot proper support for the Allwinner F1C100 family of SoCs was really limited: we could realistically only deal with FEL booting, as there was no storage or network device acessible from U-Boot proper. This series enables the MMC and SPI controller, to be able to actually load something from the device. This is made possible by the updates to the devicetree in Linux, which now describes those devices. The first patch is taken from George's/Yifan's older series, and adds DM_CLK support for the F1C100s. The DM_PINCTRL support was already added with the DM conversion a few weeks back. Patches 2-4 fix the SPI driver clock setup, and add support for the differing SPI clock on the F1C100. Patch 5 updates the devicetree files, freshly synced from linux-next. Patch 6 reverts a hack we introduced back then to fix the reset functionality, with the DT update this is now no longer needed. The final patch adds SPI flash support to the Licheepi Nano defconfig, as these boards mostly ship with SPI flash soldered. Please have a look and test! Cheers, Andre Andre Przywara (6): spi: sunxi: refactor SPI speed/mode programming spi: sunxi: improve SPI clock calculation spi: sunxi: Add support for F1C100s SPI controller sunxi: F1C100s: update DT files from Linux Revert "sunxi: f1c100s: Drop SYSRESET to enable reset functionality" sunxi: licheepi_nano: enable SPI flash George Hilliard (1): clk: sunxi: implement clock driver for suniv f1c100s arch/arm/dts/suniv-f1c100s-licheepi-nano.dts | 31 ++ arch/arm/dts/suniv-f1c100s.dtsi | 104 -- configs/licheepi_nano_defconfig | 4 +- drivers/clk/sunxi/Kconfig| 7 ++ drivers/clk/sunxi/Makefile | 1 + drivers/clk/sunxi/clk_f1c100s.c | 74 + drivers/spi/spi-sunxi.c | 109 +++ 7 files changed, 275 insertions(+), 55 deletions(-) create mode 100644 drivers/clk/sunxi/clk_f1c100s.c -- 2.35.3
Re: [PATCH 1/1] dm: fix DM_EVENT dependencies
On Tue, May 03, 2022 at 09:18:33PM +0200, Heinrich Schuchardt wrote:
> CONFIG_DM_EVENT without CONFIG_EVENT is non-functional. Select instead
> of imply CONFIG_EVENT.
>
> Remove superfluous stub in include/event.h.
>
> Fixes: 5b896ed5856f ("event: Add events for device probe/remove")
> Reported-by: Jan Kiszka
> Signed-off-by: Heinrich Schuchardt
> ---
> drivers/core/Kconfig | 2 +-
> include/event.h | 7 +--
> 2 files changed, 2 insertions(+), 7 deletions(-)
I don't think it makes sense to have two symbols at all. It's part of
DM, it should always be DM_EVENT I suppose.
--
Tom
signature.asc
Description: PGP signature
Re: [PATCH] imx8mn_evk: Add the missing spl.bin entry
On Tue, May 3, 2022 at 12:03 PM Fabio Estevam wrote:
>
> From: Fabio Estevam
>
> The generated flash.bin does not boot the imx8mn evk LPDDR4 variant
> as it misses the spl.bin description in binman.
>
> Add its entry to fix the boot on the imx8mn evk LPDDR4 variant.
>
> Signed-off-by: Fabio Estevam
> ---
> arch/arm/dts/imx8mn-evk-u-boot.dtsi | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm/dts/imx8mn-evk-u-boot.dtsi
> b/arch/arm/dts/imx8mn-evk-u-boot.dtsi
> index 3db46d4cbc..593cf06eb9 100644
> --- a/arch/arm/dts/imx8mn-evk-u-boot.dtsi
> +++ b/arch/arm/dts/imx8mn-evk-u-boot.dtsi
> @@ -58,7 +58,9 @@
> };
>
>
> - flash {
> + spl {
> + filename = "spl.bin";
> +
> mkimage {
> args = "-n spl/u-boot-spl.cfgout -T imx8mimage -e
> 0x912000";
>
> --
> 2.25.1
>
Sounds like there should be a Fixes tag here?
Tim
[PATCH 1/1] dm: fix DM_EVENT dependencies
CONFIG_DM_EVENT without CONFIG_EVENT is non-functional. Select instead
of imply CONFIG_EVENT.
Remove superfluous stub in include/event.h.
Fixes: 5b896ed5856f ("event: Add events for device probe/remove")
Reported-by: Jan Kiszka
Signed-off-by: Heinrich Schuchardt
---
drivers/core/Kconfig | 2 +-
include/event.h | 7 +--
2 files changed, 2 insertions(+), 7 deletions(-)
diff --git a/drivers/core/Kconfig b/drivers/core/Kconfig
index 5c3400417f..be956c79ff 100644
--- a/drivers/core/Kconfig
+++ b/drivers/core/Kconfig
@@ -80,7 +80,7 @@ config DM_DEVICE_REMOVE
config DM_EVENT
bool "Support events with driver model"
depends on DM
- imply EVENT
+ select EVENT
default y if SANDBOX
help
This enables support for generating events related to driver model
diff --git a/include/event.h b/include/event.h
index 62e72a7bd3..7765f07250 100644
--- a/include/event.h
+++ b/include/event.h
@@ -144,7 +144,6 @@ int event_register(const char *id, enum event_t type,
event_handler_t func,
/** event_show_spy_list( - Show a list of event spies */
void event_show_spy_list(void);
-#if CONFIG_IS_ENABLED(EVENT)
/**
* event_notify() - notify spies about an event
*
@@ -159,6 +158,7 @@ void event_show_spy_list(void);
*/
int event_notify(enum event_t type, void *data, int size);
+#if CONFIG_IS_ENABLED(EVENT)
/**
* event_notify_null() - notify spies about an event
*
@@ -169,11 +169,6 @@ int event_notify(enum event_t type, void *data, int size);
*/
int event_notify_null(enum event_t type);
#else
-static inline int event_notify(enum event_t type, void *data, int size)
-{
- return 0;
-}
-
static inline int event_notify_null(enum event_t type)
{
return 0;
--
2.34.1
Re: [PATCH 04/12] cmd: tlv_eeprom: convert functions used by command to api functions
\o/
Am 03.05.22 um 13:54 schrieb Stefan Roese:
Hi Josua,
On 03.05.22 09:17, Josua Mayer wrote:
Am 03.05.22 um 09:16 schrieb Stefan Roese:
On 02.05.22 16:18, Josua Mayer wrote:
- prog_eeprom: write_tlvinfo_tlv_eeprom
- update_crc: tlvinfo_update_crc
- is_valid_tlv: is_valid_tlvinfo_entry
- is_checksum_valid: tlvinfo_check_crc
So while creating a new API it makes sense to prepend the function
names identical IMHO to not "pollute" the namespace. Something like
- tlv_is_valid_entry
- tlv_check_crc
...
Just examples, you get the idea.
Yes. The hard part in this particular implementation is that the
naming is not consistent.
The most sense I could make is that prefix tlvinfo indicates all tlv
data, i.e. working with the whole structure, while tlvinfo_tlv
indicates working with one data entry. Further write, read and is_
are currently prefixed in the header, but for previously static
functions in the C file it was put in the middle ...
I found it quite difficult to prepare for splitting off a library in
a way that preserves history, i.e. diffs should still be readable for
spotting mistakes.
Yes, a decent history would be welcome. But still, when going global
here with a new API this should be consistant.
My view more like - patches 1-10 are not really new API, in that I am
only changing what is necessary to allow splitting the code.
I was considering to at the very end do a mass-rename and come up
with better naming, something like
tlv_{set,get}_{blob,string,mac}
tlv_find_entry
tlv_{read,write}_eeprom
But this is pending a refactoring and extension of the tlv parsing
code in board/solidrun/common/tlv_data.*, to figure out what is
required or useful.
So your plan is to this:
a) Get this patchset included
b) Use it in board specific code, e.g. solidrun
c) Do the mass-rename
Is this correct?
This is close. I would say
1) get the split merged
2) rebase board-specific code
2a) figure out what kinds of set/get/add/remove functions are useful
3) redesign api
- there are inconsistencies with the order of function arguments
- read/write functions imo should use the tlv header to determine
size, not a function argument
- at least one of the tlv data types can appear multiple times,
existing code does not support this
4) submit any renames and extensions to the tlv library
5) submit board-specific use of tlv eeprom data
If yes, why is it better to do the renaming at the end?
It is very difficult to work on a patch-set that touches the same code
before and after moving it to a different file, which I found myself
doing a lot while prototyping this.
So if now I went ahead and figured out proper names and purposes for all
functions that I think should be the tlv api, then I have to divide that
into those parts that are renames or refactoring of existing
functionality, and those parts that are strictly new - putting the
former before splitting off the library, and the latter to after.
I am not sure I can manage this level of complexity.
- Josua Mayer
Thanks,
Stefan
Thanks,
Stefan
Signed-off-by: Josua Mayer
---
cmd/tlv_eeprom.c | 56
+++
include/tlv_eeprom.h | 57
2 files changed, 76 insertions(+), 37 deletions(-)
diff --git a/cmd/tlv_eeprom.c b/cmd/tlv_eeprom.c
index 00c5b5f840..1b4f2537f6 100644
--- a/cmd/tlv_eeprom.c
+++ b/cmd/tlv_eeprom.c
@@ -28,13 +28,9 @@ DECLARE_GLOBAL_DATA_PTR;
#define MAX_TLV_DEVICES 2
/* File scope function prototypes */
-static bool is_checksum_valid(u8 *eeprom);
static int read_eeprom(int devnum, u8 *eeprom);
static void show_eeprom(int devnum, u8 *eeprom);
static void decode_tlv(struct tlvinfo_tlv *tlv);
-static void update_crc(u8 *eeprom);
-static int prog_eeprom(int devnum, u8 *eeprom);
-static bool tlvinfo_find_tlv(u8 *eeprom, u8 tcode, int
*eeprom_index);
static bool tlvinfo_delete_tlv(u8 *eeprom, u8 code);
static bool tlvinfo_add_tlv(u8 *eeprom, int tcode, char *strval);
static int set_mac(char *buf, const char *string);
@@ -58,18 +54,6 @@ static inline bool is_digit(char c)
return (c >= '0' && c <= '9');
}
-/**
- * is_valid_tlv
- *
- * Perform basic sanity checks on a TLV field. The TLV is pointed to
- * by the parameter provided.
- * 1. The type code is not reserved (0x00 or 0xFF)
- */
-static inline bool is_valid_tlv(struct tlvinfo_tlv *tlv)
-{
- return((tlv->type != 0x00) && (tlv->type != 0xFF));
-}
-
/**
* is_hex
*
@@ -83,14 +67,12 @@ static inline u8 is_hex(char p)
}
/**
- * is_checksum_valid
- *
* Validate the checksum in the provided TlvInfo EEPROM data.
First,
* verify that the TlvInfo header is valid, then make sure the last
* TLV is a CRC-32 TLV. Then calculate the CRC over the EEPROM data
* and compare it to the value stored in the EEPROM CRC-32 TLV.
*/
-static bool is_checksum_valid(u8 *eeprom)
+bool tlvinfo_check_crc(u8 *eeprom)
{
str
[PATCH] imx8mn_evk: Add the missing spl.bin entry
From: Fabio Estevam
The generated flash.bin does not boot the imx8mn evk LPDDR4 variant
as it misses the spl.bin description in binman.
Add its entry to fix the boot on the imx8mn evk LPDDR4 variant.
Signed-off-by: Fabio Estevam
---
arch/arm/dts/imx8mn-evk-u-boot.dtsi | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/arm/dts/imx8mn-evk-u-boot.dtsi
b/arch/arm/dts/imx8mn-evk-u-boot.dtsi
index 3db46d4cbc..593cf06eb9 100644
--- a/arch/arm/dts/imx8mn-evk-u-boot.dtsi
+++ b/arch/arm/dts/imx8mn-evk-u-boot.dtsi
@@ -58,7 +58,9 @@
};
- flash {
+ spl {
+ filename = "spl.bin";
+
mkimage {
args = "-n spl/u-boot-spl.cfgout -T imx8mimage -e
0x912000";
--
2.25.1
[PATCH] rockchip: rk3328: nanopi-r2s: Use the sdcard for the env
The NanoPi-R2S doesn't have eMMC so use the sdcard as the device to save the environment variables Signed-off-by: Emmanuel Vadot --- configs/nanopi-r2s-rk3328_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/nanopi-r2s-rk3328_defconfig b/configs/nanopi-r2s-rk3328_defconfig index 453e54295d..0665368c4d 100644 --- a/configs/nanopi-r2s-rk3328_defconfig +++ b/configs/nanopi-r2s-rk3328_defconfig @@ -44,6 +44,7 @@ CONFIG_TPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_TPL_OF_PLATDATA=y CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_MMC_ENV_DEV=1 CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_TPL_DM=y -- 2.36.0
[PATCH V2] nvmem: add driver handling U-Boot environment variables
From: Rafał Miłecki
U-Boot stores its setup as environment variables. It's a list of
key-value pairs stored on flash device with a custom header.
This commit adds an NVMEM driver that:
1. Provides NVMEM access to environment vars binary data
2. Extracts variables as NVMEM cells
It can be used for:
1. Accessing env variables from user-space
2. Reading NVMEM cells by Linux drivers
Signed-off-by: Rafał Miłecki
---
V2: Drop ARCH_BCM4908 dependency as there are plenty architectures using
U-Boot bootloader. Thanks Srinivas.
---
MAINTAINERS| 1 +
drivers/nvmem/Kconfig | 11 ++
drivers/nvmem/Makefile | 2 +
drivers/nvmem/u-boot-env.c | 236 +
4 files changed, 250 insertions(+)
create mode 100644 drivers/nvmem/u-boot-env.c
diff --git a/MAINTAINERS b/MAINTAINERS
index 2869a958f5e4..368e532444d0 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -20193,6 +20193,7 @@ U-BOOT ENVIRONMENT VARIABLES
M: Rafał Miłecki
S: Maintained
F: Documentation/devicetree/bindings/nvmem/u-boot,env.yaml
+F: drivers/nvmem/u-boot-env.c
UACCE ACCELERATOR FRAMEWORK
M: Zhangfei Gao
diff --git a/drivers/nvmem/Kconfig b/drivers/nvmem/Kconfig
index 967d0084800e..eee3ff668629 100644
--- a/drivers/nvmem/Kconfig
+++ b/drivers/nvmem/Kconfig
@@ -337,4 +337,15 @@ config NVMEM_APPLE_EFUSES
This driver can also be built as a module. If so, the module will
be called nvmem-apple-efuses.
+config NVMEM_U_BOOT_ENV
+ tristate "U-Boot environment variables support"
+ depends on OF && MTD
+ select CRC32
+ help
+ U-Boot stores its setup as environment variables. This driver adds
+ support for verifying & exporting such data. It also exposes variables
+ as NVMEM cells so they can be referenced by other drivers.
+
+ If compiled as module it will be called nvmem_u-boot-env.
+
endif
diff --git a/drivers/nvmem/Makefile b/drivers/nvmem/Makefile
index 00e136a0a123..d201a02a09ec 100644
--- a/drivers/nvmem/Makefile
+++ b/drivers/nvmem/Makefile
@@ -67,3 +67,5 @@ obj-$(CONFIG_NVMEM_SUNPLUS_OCOTP) += nvmem_sunplus_ocotp.o
nvmem_sunplus_ocotp-y := sunplus-ocotp.o
obj-$(CONFIG_NVMEM_APPLE_EFUSES) += nvmem-apple-efuses.o
nvmem-apple-efuses-y := apple-efuses.o
+obj-$(CONFIG_NVMEM_U_BOOT_ENV) += nvmem_u-boot-env.o
+nvmem_u-boot-env-y := u-boot-env.o
diff --git a/drivers/nvmem/u-boot-env.c b/drivers/nvmem/u-boot-env.c
new file mode 100644
index ..c7945d7d5750
--- /dev/null
+++ b/drivers/nvmem/u-boot-env.c
@@ -0,0 +1,236 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2022 Rafał Miłecki
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+enum u_boot_env_format {
+ U_BOOT_FORMAT_SINGLE,
+ U_BOOT_FORMAT_REDUNDANT,
+};
+
+struct u_boot_env {
+ struct device *dev;
+ enum u_boot_env_format format;
+
+ /* Parent device */
+ struct mtd_info *mtd;
+ size_t offset;
+ size_t size;
+
+ /* Cells */
+ struct nvmem_cell_info *cells;
+ int ncells;
+};
+
+struct u_boot_env_image_single {
+ __le32 crc32;
+ uint8_t data[0];
+} __packed;
+
+struct u_boot_env_image_redundant {
+ __le32 crc32;
+ u8 mark;
+ uint8_t data[0];
+} __packed;
+
+static int u_boot_env_read(void *context, unsigned int offset, void *val,
+ size_t bytes)
+{
+ struct u_boot_env *priv = context;
+ struct device *dev = priv->dev;
+ size_t bytes_read;
+ int err;
+
+ err = mtd_read(priv->mtd, priv->offset + offset, bytes, &bytes_read,
val);
+ if (err && !mtd_is_bitflip(err)) {
+ dev_err(dev, "Failed to read from mtd: %d\n", err);
+ return err;
+ }
+
+ if (bytes_read != bytes) {
+ dev_err(dev, "Failed to read %zd bytes\n", bytes);
+ return -EIO;
+ }
+
+ return 0;
+}
+
+static int u_boot_env_add_cells(struct u_boot_env *priv, uint8_t *buf,
+ size_t data_offset, size_t data_len)
+{
+ struct device *dev = priv->dev;
+ char *data = buf + data_offset;
+ char *var, *value, *eq;
+ int idx;
+
+ priv->ncells = 0;
+ for (var = data; var < data + data_len && *var; var += strlen(var) + 1)
+ priv->ncells++;
+
+ priv->cells = devm_kcalloc(dev, priv->ncells, sizeof(*priv->cells),
GFP_KERNEL);
+ if (!priv->cells)
+ return -ENOMEM;
+
+ for (var = data, idx = 0;
+var < data + data_len && *var;
+var = value + strlen(value) + 1, idx++) {
+ eq = strchr(var, '=');
+ if (!eq)
+ break;
+ *eq = '\0';
+ value = eq + 1;
+
+ priv->cells[idx].name = devm_kstrdup(dev, var, GFP_KERNEL);
+
Re: [PATCH 09/17] imx: imx8mm/n/p-venice: enable pinctrl_wdog in SPL
On Tue, May 3, 2022 at 4:42 AM Peng Fan (OSS) wrote:
>
> From: Peng Fan
>
> Mark pinctrl_wdog as u-boot,dm-spl to clean up board code,
> set_wdog_reset function could be handled by imx_watchdog.c driver.
>
> Signed-off-by: Peng Fan
> ---
> arch/arm/dts/imx8mm-venice-u-boot.dtsi | 4
> arch/arm/dts/imx8mn-venice-u-boot.dtsi | 4
> arch/arm/dts/imx8mp-venice-u-boot.dtsi | 4
> board/gateworks/venice/spl.c | 30 --
> 4 files changed, 12 insertions(+), 30 deletions(-)
>
> diff --git a/arch/arm/dts/imx8mm-venice-u-boot.dtsi
> b/arch/arm/dts/imx8mm-venice-u-boot.dtsi
> index c61c6de935f..68978a0413e 100644
> --- a/arch/arm/dts/imx8mm-venice-u-boot.dtsi
> +++ b/arch/arm/dts/imx8mm-venice-u-boot.dtsi
> @@ -72,3 +72,7 @@
> &wdog1 {
> u-boot,dm-spl;
> };
> +
> +&pinctrl_wdog {
> + u-boot,dm-spl;
> +};
> diff --git a/arch/arm/dts/imx8mn-venice-u-boot.dtsi
> b/arch/arm/dts/imx8mn-venice-u-boot.dtsi
> index 4f23da35676..35819553879 100644
> --- a/arch/arm/dts/imx8mn-venice-u-boot.dtsi
> +++ b/arch/arm/dts/imx8mn-venice-u-boot.dtsi
> @@ -110,6 +110,10 @@
> u-boot,dm-spl;
> };
>
> +&pinctrl_wdog {
> + u-boot,dm-spl;
> +};
> +
> &binman {
> u-boot-spl-ddr {
> align = <4>;
> diff --git a/arch/arm/dts/imx8mp-venice-u-boot.dtsi
> b/arch/arm/dts/imx8mp-venice-u-boot.dtsi
> index 37f3edc9817..96b9fa89cf4 100644
> --- a/arch/arm/dts/imx8mp-venice-u-boot.dtsi
> +++ b/arch/arm/dts/imx8mp-venice-u-boot.dtsi
> @@ -72,3 +72,7 @@
> &wdog1 {
> u-boot,dm-spl;
> };
> +
> +&pinctrl_wdog {
> + u-boot,dm-spl;
> +};
> diff --git a/board/gateworks/venice/spl.c b/board/gateworks/venice/spl.c
> index af196e5b87c..4c0feb4381c 100644
> --- a/board/gateworks/venice/spl.c
> +++ b/board/gateworks/venice/spl.c
> @@ -87,34 +87,6 @@ static void spl_dram_init(int size)
> ddr_init(dram_timing);
> }
>
> -#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE |
> PAD_CTL_PE)
> -
> -#ifdef CONFIG_IMX8MM
> -static iomux_v3_cfg_t const wdog_pads[] = {
> - IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
> -};
> -#elif CONFIG_IMX8MN
> -static const iomux_v3_cfg_t wdog_pads[] = {
> - IMX8MN_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
> -};
> -#elif CONFIG_IMX8MP
> -static const iomux_v3_cfg_t wdog_pads[] = {
> - MX8MP_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
> -};
> -
> -#endif
> -
> -int board_early_init_f(void)
> -{
> - struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
> -
> - imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
> -
> - set_wdog_reset(wdog);
> -
> - return 0;
> -}
> -
> /*
> * Model specific PMIC adjustments necessary prior to DRAM init
> *
> @@ -254,8 +226,6 @@ void board_init_f(ulong dummy)
>
> init_uart_clk(1);
>
> - board_early_init_f();
> -
> timer_init();
>
> /* Clear the BSS. */
> --
> 2.36.0
>
Peng,
Thanks for another great cleanup for imx8m!
If you do another version of this series I would suggest changing the
2nd sentence of the commit logs from:
set_wdog_reset function could be handled by imx_watchdog.c driver.
to:
The set_wdog_reset() function is not necessary as this is handled by
the imx_watchdog.c driver due to the 'fsl,ext-reset-output' property
being set.
Tested By: Tim Harvey #imx8m{m,n,p}-venice-*
Best Regards,
Tim
Re: [PATCH 3/4] configs: imx8m: use common imx8m.h for i.MX8MP
On Tue, May 3, 2022 at 4:39 AM Peng Fan (OSS) wrote: > > From: Peng Fan > > Some SPL definitions could be gerneralized, so use imx8m.h for iMX8MP. > > Signed-off-by: Peng Fan > --- > include/configs/imx8m.h | 8 > include/configs/imx8mp_evk.h | 17 + > include/configs/imx8mp_rsb3720.h | 16 +--- > include/configs/imx8mp_venice.h | 18 +- > include/configs/phycore_imx8mp.h | 16 +--- > include/configs/verdin-imx8mp.h | 16 +--- > 6 files changed, 13 insertions(+), 78 deletions(-) > > diff --git a/include/configs/imx8m.h b/include/configs/imx8m.h > index 30dc01221e6..b127d0fb847 100644 > --- a/include/configs/imx8m.h > +++ b/include/configs/imx8m.h > @@ -34,6 +34,14 @@ > #define CONFIG_SYS_SPL_MALLOC_START0x4220 > #define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K /* 512 KB */ > > +#elif defined(CONFIG_IMX8MP) > +/*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/ > +#define CONFIG_SPL_STACK 0x96 > +#define CONFIG_SPL_BSS_START_ADDR 0x0098FC00 > +#define CONFIG_SPL_BSS_MAX_SIZE0x400 /* 1 KB */ > +#define CONFIG_SYS_SPL_MALLOC_START0x4220 > +#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K /* 512 KB */ > + > #endif > #endif > #endif > diff --git a/include/configs/imx8mp_evk.h b/include/configs/imx8mp_evk.h > index 55691821f90..60c2d9ee4e4 100644 > --- a/include/configs/imx8mp_evk.h > +++ b/include/configs/imx8mp_evk.h > @@ -6,27 +6,12 @@ > #ifndef __IMX8MP_EVK_H > #define __IMX8MP_EVK_H > > -#include > -#include > -#include > +#include > > #define CONFIG_SYS_BOOTM_LEN (32 * SZ_1M) > > -#define CONFIG_SPL_MAX_SIZE(152 * 1024) > -#define CONFIG_SYS_MONITOR_LEN (512 * 1024) > -#define CONFIG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + > CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) > - > #ifdef CONFIG_SPL_BUILD > -/*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/ > -#define CONFIG_SPL_STACK 0x96 > -#define CONFIG_SPL_BSS_START_ADDR 0x0098FC00 > -#define CONFIG_SPL_BSS_MAX_SIZE0x400 /* 1 KB */ > -#define CONFIG_SYS_SPL_MALLOC_START0x4220 > -#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K /* 512 KB */ > - > - > #define CONFIG_POWER_PCA9450 > - > #endif > > #if defined(CONFIG_CMD_NET) > diff --git a/include/configs/imx8mp_rsb3720.h > b/include/configs/imx8mp_rsb3720.h > index 7c2babbb0ae..008439915d8 100644 > --- a/include/configs/imx8mp_rsb3720.h > +++ b/include/configs/imx8mp_rsb3720.h > @@ -7,17 +7,11 @@ > #ifndef __IMX8MP_RSB3720_H > #define __IMX8MP_RSB3720_H > > -#include > -#include > -#include > +#include > #include > > #define CONFIG_SYS_BOOTM_LEN (32 * SZ_1M) > > -#define CONFIG_SPL_MAX_SIZE(152 * 1024) > -#define CONFIG_SYS_MONITOR_LEN (512 * 1024) > -#define CONFIG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + > CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) > - > /* GUIDs for capsule updatable firmware images */ > #define IMX8MP_RSB3720A1_4G_FIT_IMAGE_GUID \ > EFI_GUID(0xb1251e89, 0x384a, 0x4635, 0xa8, 0x06, \ > @@ -28,18 +22,10 @@ > 0x5f, 0xd3, 0x6b, 0x9b, 0xe5, 0xb9) > > #ifdef CONFIG_SPL_BUILD > -#define CONFIG_SPL_STACK 0x96 > -#define CONFIG_SPL_BSS_START_ADDR 0x0098FC00 > -#define CONFIG_SPL_BSS_MAX_SIZE0x400 /* 1 KB */ > -#define CONFIG_SYS_SPL_MALLOC_START0x4220 > -#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K /* 512 KB */ > - > #define CONFIG_MALLOC_F_ADDR 0x184000 /* malloc f used before \ > * GD_FLG_FULL_MALLOC_INIT \ > * set \ > */ > - > - > #if defined(CONFIG_NAND_BOOT) > #define CONFIG_SPL_NAND_MXS > #endif > diff --git a/include/configs/imx8mp_venice.h b/include/configs/imx8mp_venice.h > index 161f2e8d366..0697a48b7ea 100644 > --- a/include/configs/imx8mp_venice.h > +++ b/include/configs/imx8mp_venice.h > @@ -6,23 +6,7 @@ > #ifndef __IMX8MP_VENICE_H > #define __IMX8MP_VENICE_H > > -#include > -#include > - > -#define CONFIG_SPL_MAX_SIZE(152 * 1024) > -#define CONFIG_SYS_MONITOR_LEN SZ_512K > -#define CONFIG_SYS_UBOOT_BASE \ > - (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) > - > -#ifdef CONFIG_SPL_BUILD > -#define CONFIG_SPL_STACK 0x96 > -#define CONFIG_SPL_BSS_START_ADDR 0x0098FC00 > -#define CONFIG_SPL_BSS_MAX_SIZE0x400 /* 1 KB */ > -#define CONFIG_SYS_SPL_MALLOC_START0x4220 > -#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K /* 512 KB */ > - > -/* For RAW image gives a error info not panic */ > -#endif > +#include > > #define MEM_LAYOUT_ENV_SETTINGS \ > "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ > diff --git a/include/configs/phycore_imx8mp.h > b/include/configs/phycore_imx8mp.
Re: [PATCH 2/4] configs: imx8m: use common imx8m.h for i.MX8MN
On Tue, May 3, 2022 at 4:39 AM Peng Fan (OSS) wrote: > > From: Peng Fan > > Some SPL definitions could be gerneralized, so use imx8m.h for iMX8MN. > Peng, s/gerneralized/generalized (looks like that typo is all the patches in your series) Great cleanup - thanks! This is a great start to getting rid of the remaining items in the config headers. If you do end up doing a 2nd version you can probably remove the comments on the sizes, for example 'SZ_8K /* 8 KB */'' as I think the comment is not needed. Works great for imx8mn-venice-*. Tested-by: Tim Harvey #imx8mm-venice-* > Signed-off-by: Peng Fan > --- > include/configs/imx8m.h| 10 ++ > include/configs/imx8mn_bsh_smm_s2_common.h | 17 + > include/configs/imx8mn_evk.h | 20 +--- > include/configs/imx8mn_var_som.h | 15 +-- > include/configs/imx8mn_venice.h| 18 +- > 5 files changed, 14 insertions(+), 66 deletions(-) > > diff --git a/include/configs/imx8m.h b/include/configs/imx8m.h > index 3d4ea834bd0..30dc01221e6 100644 > --- a/include/configs/imx8m.h > +++ b/include/configs/imx8m.h > @@ -16,6 +16,8 @@ > (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) > > #ifdef CONFIG_SPL_BUILD > + > +#ifdef CONFIG_IMX8MM > #define CONFIG_SPL_STACK 0x92 > #define CONFIG_SPL_BSS_START_ADDR 0x91 > #define CONFIG_SPL_BSS_MAX_SIZESZ_8K /* 8 KB */ > @@ -25,5 +27,13 @@ > /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ > #define CONFIG_MALLOC_F_ADDR 0x93 > > +#elif defined(CONFIG_IMX8MN) > +#define CONFIG_SPL_STACK 0x98 > +#define CONFIG_SPL_BSS_START_ADDR 0x95 > +#define CONFIG_SPL_BSS_MAX_SIZESZ_8K /* 8 KB */ > +#define CONFIG_SYS_SPL_MALLOC_START0x4220 > +#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K /* 512 KB */ > + > +#endif > #endif > #endif > diff --git a/include/configs/imx8mn_bsh_smm_s2_common.h > b/include/configs/imx8mn_bsh_smm_s2_common.h > index 57be38d9433..eb210dc597b 100644 > --- a/include/configs/imx8mn_bsh_smm_s2_common.h > +++ b/include/configs/imx8mn_bsh_smm_s2_common.h > @@ -6,25 +6,10 @@ > #ifndef __IMX8MN_BSH_SMM_S2_COMMON_H > #define __IMX8MN_BSH_SMM_S2_COMMON_H > > -#include > -#include > -#include > +#include > > #define CONFIG_SYS_BOOTM_LEN (32 * SZ_1M) > > -#define CONFIG_SPL_MAX_SIZE(148 * SZ_1K) > -#define CONFIG_SYS_MONITOR_LEN SZ_512K > -#define CONFIG_SYS_UBOOT_BASE \ > - (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) > - > -#define CONFIG_SPL_STACK 0x98 > -#define CONFIG_SPL_BSS_START_ADDR 0x95 > -#define CONFIG_SPL_BSS_MAX_SIZESZ_8K > -#define CONFIG_SYS_SPL_MALLOC_START0x4220 > -#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K > - > - > - > #define MEM_LAYOUT_ENV_SETTINGS \ > "scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ > "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ > diff --git a/include/configs/imx8mn_evk.h b/include/configs/imx8mn_evk.h > index c0e9b0e9872..6e21192ea03 100644 > --- a/include/configs/imx8mn_evk.h > +++ b/include/configs/imx8mn_evk.h > @@ -6,28 +6,10 @@ > #ifndef __IMX8MN_EVK_H > #define __IMX8MN_EVK_H > > -#include > -#include > -#include > +#include > > #define CONFIG_SYS_BOOTM_LEN (32 * SZ_1M) > > -#define CONFIG_SPL_MAX_SIZE(148 * 1024) > -#define CONFIG_SYS_MONITOR_LEN SZ_512K > -#define CONFIG_SYS_UBOOT_BASE \ > - (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) > - > -#ifdef CONFIG_SPL_BUILD > -#define CONFIG_SPL_STACK 0x98 > -#define CONFIG_SPL_BSS_START_ADDR 0x95 > -#define CONFIG_SPL_BSS_MAX_SIZESZ_8K /* 8 KB */ > -#define CONFIG_SYS_SPL_MALLOC_START0x4220 > -#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K /* 512 KB */ > - > -/* For RAW image gives a error info not panic */ > - > -#endif > - > #ifndef CONFIG_SPL_BUILD > #define BOOT_TARGET_DEVICES(func) \ > func(MMC, mmc, 1) \ > diff --git a/include/configs/imx8mn_var_som.h > b/include/configs/imx8mn_var_som.h > index 6ce60b0d704..fc9c4ca4530 100644 > --- a/include/configs/imx8mn_var_som.h > +++ b/include/configs/imx8mn_var_som.h > @@ -6,23 +6,10 @@ > #ifndef __IMX8MN_VAR_SOM_H > #define __IMX8MN_VAR_SOM_H > > -#include > -#include > -#include > +#include > > #define CONFIG_SYS_BOOTM_LEN (32 * SZ_1M) > > -#define CONFIG_SPL_MAX_SIZE(148 * SZ_1K) > -#define CONFIG_SYS_MONITOR_LEN SZ_512K > -#define CONFIG_SYS_UBOOT_BASE \ > - (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) > - > -#define CONFIG_SPL_STACK 0x98 > -#define CONFIG_SPL_BSS_START_ADDR 0x95 > -#define CONFIG_SPL_BSS_MAX_SIZESZ_8K > -#define CONFIG
Re: [PATCH 1/4] configs: imx8m: use common imx8m.h for i.MX8MM
On Tue, May 3, 2022 at 4:39 AM Peng Fan (OSS) wrote: > > From: Peng Fan > > Some SPL definitions could be gerneralized, so use imx8m.h for that. > i.MX8MN/Q/P will follow up. > > Signed-off-by: Peng Fan > --- > include/configs/imx8m.h | 29 + > include/configs/imx8mm-cl-iot-gate.h| 17 ++-- > include/configs/imx8mm_beacon.h | 21 +-- > include/configs/imx8mm_data_modul_edm_sbc.h | 15 +++ > include/configs/imx8mm_evk.h| 21 +-- > include/configs/imx8mm_icore_mx8mm.h| 20 +- > include/configs/imx8mm_venice.h | 18 ++--- > include/configs/kontron-sl-mx8mm.h | 14 +- > include/configs/phycore_imx8mm.h| 20 +- > include/configs/verdin-imx8mm.h | 20 +- > 10 files changed, 42 insertions(+), 153 deletions(-) > create mode 100644 include/configs/imx8m.h > > diff --git a/include/configs/imx8m.h b/include/configs/imx8m.h > new file mode 100644 > index 000..3d4ea834bd0 > --- /dev/null > +++ b/include/configs/imx8m.h > @@ -0,0 +1,29 @@ > +/* SPDX-License-Identifier: GPL-2.0+ */ > +/* > + * Copyright 2022 NXP > + */ > + > +#ifndef __IMX8MM_H > +#define __IMX8MM_H > + > +#include > +#include > +#include > + > +#define CONFIG_SPL_MAX_SIZE(148 * 1024) > +#define CONFIG_SYS_MONITOR_LEN SZ_512K > +#define CONFIG_SYS_UBOOT_BASE \ > + (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) > + > +#ifdef CONFIG_SPL_BUILD > +#define CONFIG_SPL_STACK 0x92 > +#define CONFIG_SPL_BSS_START_ADDR 0x91 > +#define CONFIG_SPL_BSS_MAX_SIZESZ_8K /* 8 KB */ > +#define CONFIG_SYS_SPL_MALLOC_START0x4220 > +#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K /* 512 KB */ > + > +/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ > +#define CONFIG_MALLOC_F_ADDR 0x93 > + > +#endif > +#endif > diff --git a/include/configs/imx8mm-cl-iot-gate.h > b/include/configs/imx8mm-cl-iot-gate.h > index e6c220bf0a8..80074a1a2ac 100644 > --- a/include/configs/imx8mm-cl-iot-gate.h > +++ b/include/configs/imx8mm-cl-iot-gate.h > @@ -6,28 +6,15 @@ > #ifndef __IMX8MM_CL_IOT_GATE_H > #define __IMX8MM_CL_IOT_GATE_H > > -#include > -#include > -#include > +#include > #include > > #define CONFIG_SYS_BOOTM_LEN (32 * SZ_1M) > -#define CONFIG_SPL_MAX_SIZE(148 * 1024) > -#define CONFIG_SYS_MONITOR_LEN SZ_512K > -#define CONFIG_SYS_UBOOT_BASE \ > - (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) > > #ifdef CONFIG_SPL_BUILD > -#define CONFIG_SPL_STACK 0x92 > -#define CONFIG_SPL_BSS_START_ADDR 0x91 > -#define CONFIG_SPL_BSS_MAX_SIZESZ_8K /* 8 KB */ > -#define CONFIG_SYS_SPL_MALLOC_START0x4220 > -#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K /* 512 KB */ > - > +#undef CONFIG_MALLOC_F_ADDR > /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ > #define CONFIG_MALLOC_F_ADDR 0x912000 > -/* For RAW image gives a error info not panic */ > - > #endif > > /* GUIDs for capsule updatable firmware images */ > diff --git a/include/configs/imx8mm_beacon.h b/include/configs/imx8mm_beacon.h > index a9ca13a9da4..c73188a16f2 100644 > --- a/include/configs/imx8mm_beacon.h > +++ b/include/configs/imx8mm_beacon.h > @@ -6,26 +6,7 @@ > #ifndef __IMX8MM_BEACON_H > #define __IMX8MM_BEACON_H > > -#include > -#include > - > -#define CONFIG_SPL_MAX_SIZE(148 * 1024) > -#define CONFIG_SYS_MONITOR_LEN SZ_512K > -#define CONFIG_SYS_UBOOT_BASE \ > - (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) > - > -#ifdef CONFIG_SPL_BUILD > -#define CONFIG_SPL_STACK 0x92 > -#define CONFIG_SPL_BSS_START_ADDR 0x91 > -#define CONFIG_SPL_BSS_MAX_SIZESZ_8K /* 8 KB */ > -#define CONFIG_SYS_SPL_MALLOC_START0x4220 > -#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K /* 512 KB */ > - > -/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ > -#define CONFIG_MALLOC_F_ADDR 0x93 > -/* For RAW image gives a error info not panic */ > - > -#endif > +#include > > /* Initial environment variables */ > #define CONFIG_EXTRA_ENV_SETTINGS \ > diff --git a/include/configs/imx8mm_data_modul_edm_sbc.h > b/include/configs/imx8mm_data_modul_edm_sbc.h > index b5c445df9ce..48a13dbc7f4 100644 > --- a/include/configs/imx8mm_data_modul_edm_sbc.h > +++ b/include/configs/imx8mm_data_modul_edm_sbc.h > @@ -6,26 +6,17 @@ > #ifndef __IMX8MM_DATA_MODUL_EDM_SBC_H > #define __IMX8MM_DATA_MODUL_EDM_SBC_H > > -#include > -#include > -#include > +#include > > #define CONFIG_SYS_BOOTM_LEN SZ_128M > > #define CONFIG_SPL_MAX_SIZE(148 * 1024) > +#undef CONFIG_SYS_MONITOR_LEN > #define CONFIG_SYS_MONITOR_LEN SZ_1M > > -#define CONFIG_SPL_STACK
Re: [PATCH] Convert CONFIG_MTD_CONCAT to Kconfig
On Tue, May 03, 2022 at 09:24:57PM +1200, Chris Packham wrote: > This converts the following to Kconfig: > CONFIG_MTD_CONCAT > > Signed-off-by: Chris Packham Reviewed-by: Tom Rini -- Tom signature.asc Description: PGP signature
Re: [PATCH] CI: Azure: Rework how we update MSYS2
On Tue, May 03, 2022 at 11:06:24AM -0400, Tom Rini wrote: > On Tue, May 03, 2022 at 08:30:14AM -0400, Tom Rini wrote: > > > Based on reading https://www.msys2.org/docs/ci/ and "Other Systems" > > rework how we update MSYS2 to the current version. We run it once, to > > perform nothing other than being the first run, then we run pacman > > twice. > > > > Signed-off-by: Tom Rini > > Applied to u-boot/master, thanks! For the record, I pushed this quickly because CI was breaking due to general upstream changes. Following the MSYS2 upstream instructions for how to update the system in CI resolved things, so I feel confident enough in this being the right set of changes to do here. -- Tom signature.asc Description: PGP signature
Re: [PATCH] CI: Azure: Rework how we update MSYS2
On Tue, May 03, 2022 at 08:30:14AM -0400, Tom Rini wrote: > Based on reading https://www.msys2.org/docs/ci/ and "Other Systems" > rework how we update MSYS2 to the current version. We run it once, to > perform nothing other than being the first run, then we run pacman > twice. > > Signed-off-by: Tom Rini Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH v8 01/13] doc: Convert SPL documentation to ReST
On Sat, Apr 30, 2022 at 12:56:45AM -0600, Simon Glass wrote: > Move this documentation over to .rst format. > > Signed-off-by: Simon Glass For the series, applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: Please pull u-boot-marvell/master
On Mon, May 02, 2022 at 05:53:36PM +0200, Stefan Roese wrote: > Hi Tom, > > please pull this next batch of Marvell related patches: > Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH 00/12] sunxi: Devicetree sync from Linux v5.18-rc1
On Mon, 2 May 2022 20:57:35 -0500 Samuel Holland wrote: Hi Samuel, > On 4/30/22 7:59 PM, Andre Przywara wrote: > >>> So those DT updates are really only important for mobile devices like > >>> the > >>> Pinephone, which probably don't use UEFI booting. > >> > >> We would really like to use UEFI booting on the PinePhone, and the > >> out-of-date > >> devicetree is one thing blocking that. We need to use $fdtcontroladdr to > >> pick up > >> the CPU idle states that are added at runtime by TF-A. > > > > Yes, I was wondering about that. I could imagine that suspend/resume is > > a killer feature for the PinePhone. It probably sounds useful to fully > > update just the Pinephone .dts, giving up compatibility for older > > kernels. IIUC the PinePhone doesn't run normal "desktop" distros, but > > relies more on custom OSes, tailored to a Phone use case in general? > > There is a mix of desktop distros, mobile spins of desktop distros (the > largest/most popular category), and mobile-specific OSes[1]. > > [1]: https://wiki.pine64.org/wiki/PinePhone_Software_Releases > > > What kernels are those OSes using? > > Most are using Ondrej's fork[2]. Some (at least Mobian) maintain their own > patch > set. So that means it's all quite Pinephone specific then, and none of them are using actual mainline kernels? So people don't run a stock Debian mini.iso on it, for instance? When I was asking for "kernels", I was hoping for mainline kernel *version numbers*, not forks, but I get the idea ;-) > [2]: https://github.com/megous/linux/tags > > > The only caveat would be that this adds to the mess and increases the > > diff to mainline, but maybe this could be solved by a > > sun50i-a64-pinephone-u-boot.dtsi? > > Devicetree changes are still needed for camera and USB Type C support, so the > r_intc changes could go in with those. I don't think we need to do anything > special from the U-Boot side at this point. I was thinking about putting the r_intc changes just in the pinephone-u-boot.dtsi, so that the Pinephone gets them, but every other (development) board does not. Sounds somewhat dodgy, but would pragmatically solve the problem of stability for devboards *and* the Pinephone being usable. Do Pinephone users actually use U-Boot? Also I am not so much concerned about non-essential devices like a camera or USB-C alternative functions, I guess those could even be fixed up using DT overlays while running Linux already, from some script. The problem with the r_intc changes is that last time I checked they break already when booting an initrd, because of the pinctrl driver not probing. > So, does that mean the plan is to keep the r_intc changes out of U-Boot > for now, but we can sync the rest, and come up with a plan to fully > update in time? > >>> > >>> That's one possible solution, yes, and so far the easiest, it provides > >>> a good balance between features and compatibility. > >> > >> This was my understanding of the plan as well. > >> > >>> Theoretically we can never fully sync, unless we decide to no longer > >>> support those older OSes (older Linux kernels and (current) *BSD). > >> > >> Do we have any guidance for when this could be? After the n+1 LTS > >> kernel/BSD > >> release? After the distro/BSD installers update their kernels? > > > > More the latter, I'd say when major distros stop shipping those > > old kernels in relevant releases. Especially Debian is one to keep an > > eye on I guess, since they are on 5.10 *currently*, and their installer > > properly stays there for a while. Ubuntu 20.04 shipped with 5.4, and I'd > > like to support that say at least one more year still. Don't really > > keep track of the kernels in other distros, but I think these two are > > among the more conservative ones. > > OK, that makes sense. > > > Samuel, since I have you here: With your new hat Linux hat on, can you > > say whether incompatible DT changes won't happen in the future anymore? > > No, I really cannot. > > As for major breaking changes, there is some push from the Linux clock > maintainers toward finishing the conversion from legacy to sunxi-ng clock > drivers. This affects A31, A23/A33, and A80. (In fact, this unfinished > conversion is causing me quite some trouble trying to expand the DM clock > drivers in U-Boot.) I am personally less concerned about those older devices, especially those SoCs you mentioned, which were mostly somewhat "embedded" anyway. Plus their DTs in the U-Boot tree are outdated already. In my understanding the A10/A20/H3 devices see quite some more wide-spread usage, some running off-the-shelf distros (I certainly do). And I care more about the v8 devices, especially since arm64 has a more grown-up boot story. > And then there are always little easy-to-miss things (like adding references > to > new ASoC widgets) that prevent drivers from loading on old kernels. As mentioned, if that affects secondary fe
Re: [PATCH 15/17] imx: phycore_imx8mm/p: clean up board watchdog code
Am Dienstag, dem 03.05.2022 um 20:24 +0800 schrieb Peng Fan (OSS):
> From: Peng Fan
>
> pinctrl_wdog already marked u-boot,dm-spl, so clean up board code.
> set_wdog_reset function could be handled by imx_watchdog.c driver.
Thank you for the cleanup!
Tested on phyCORE-i.MX8MM and phyCORE-i.MX8MP.
Tested-by: Teresa Remmet
Regards,
Teresa
>
> Signed-off-by: Peng Fan
> ---
> board/phytec/phycore_imx8mm/spl.c | 19 ---
> board/phytec/phycore_imx8mp/spl.c | 19 ---
> 2 files changed, 38 deletions(-)
>
> diff --git a/board/phytec/phycore_imx8mm/spl.c
> b/board/phytec/phycore_imx8mm/spl.c
> index 7f24a3affc8..d87ab6d4497 100644
> --- a/board/phytec/phycore_imx8mm/spl.c
> +++ b/board/phytec/phycore_imx8mm/spl.c
> @@ -57,23 +57,6 @@ int board_fit_config_name_match(const char *name)
> return 0;
> }
>
> -#define WDOG_PAD_CTRL(PAD_CTL_DSE6 | PAD_CTL_ODE)
> -
> -static iomux_v3_cfg_t const wdog_pads[] = {
> - IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B |
> MUX_PAD_CTRL(WDOG_PAD_CTRL),
> -};
> -
> -int board_early_init_f(void)
> -{
> - struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
> -
> - imx_iomux_v3_setup_multiple_pads(wdog_pads,
> ARRAY_SIZE(wdog_pads));
> -
> - set_wdog_reset(wdog);
> -
> - return 0;
> -}
> -
> void board_init_f(ulong dummy)
> {
> int ret;
> @@ -82,8 +65,6 @@ void board_init_f(ulong dummy)
>
> init_uart_clk(2);
>
> - board_early_init_f();
> -
> /* Clear the BSS. */
> memset(__bss_start, 0, __bss_end - __bss_start);
>
> diff --git a/board/phytec/phycore_imx8mp/spl.c
> b/board/phytec/phycore_imx8mp/spl.c
> index 38a581bef57..faed6fc3b76 100644
> --- a/board/phytec/phycore_imx8mp/spl.c
> +++ b/board/phytec/phycore_imx8mp/spl.c
> @@ -89,23 +89,6 @@ int board_fit_config_name_match(const char *name)
> return 0;
> }
>
> -#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE |
> PAD_CTL_PE)
> -
> -static iomux_v3_cfg_t const wdog_pads[] = {
> - MX8MP_PAD_GPIO1_IO02__WDOG1_WDOG_B |
> MUX_PAD_CTRL(WDOG_PAD_CTRL),
> -};
> -
> -int board_early_init_f(void)
> -{
> - struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
> -
> - imx_iomux_v3_setup_multiple_pads(wdog_pads,
> ARRAY_SIZE(wdog_pads));
> -
> - set_wdog_reset(wdog);
> -
> - return 0;
> -}
> -
> void board_init_f(ulong dummy)
> {
> int ret;
> @@ -114,8 +97,6 @@ void board_init_f(ulong dummy)
>
> init_uart_clk(0);
>
> - board_early_init_f();
> -
> ret = spl_early_init();
> if (ret) {
> debug("spl_early_init() failed: %d\n", ret);
--
PHYTEC Messtechnik GmbH | Robert-Koch-Str. 39 | 55129 Mainz, Germany
Geschäftsführer: Dipl.-Ing. Michael Mitezki, Dipl.-Ing. Bodo Huber |
Handelsregister Mainz HRB 4656 | Finanzamt Mainz | St.Nr. 266500608, DE
149059855
Re: [PATCH 06/17] imx: imx8mm-data-modul-edm-sbc: enable pinctrl_wdog in SPL
On 5/3/22 14:24, Peng Fan (OSS) wrote: From: Peng Fan Add pinctrl_wdog. Mark pinctrl_wdog as u-boot,dm-spl to clean up board code, set_wdog_reset function could be handled by imx_watchdog.c driver. There is already pinctrl_watchdog_gpio . Any changes to the main DT should really be submitted to Linux first, else the U-Boot and Linux DT will be out of sync.
Re: [PATCH 3/8] spi: aspeed: Add ASPEED SPI controller driver
On Tue, May 3, 2022 at 6:44 PM Chin-Ting Kuo wrote: > > Hi Jagan, > > Thanks for the review. > > > -Original Message- > > From: Jagan Teki > > Sent: Tuesday, May 3, 2022 8:32 PM > > To: Chin-Ting Kuo > > Subject: Re: [PATCH 3/8] spi: aspeed: Add ASPEED SPI controller driver > > > > On Thu, Apr 14, 2022 at 4:54 PM Chin-Ting Kuo > > wrote: > > > > > > Add ASPEED BMC FMC/SPI memory controller driver with spi-mem interface > > > for AST2500 and AST2600 platform. > > > > > > There are three SPI memory controllers embedded in an ASPEED SoC. > > > - FMC: Named as Firmware Memory Controller. After AC on, MCU ROM > > >fetches initial device boot image from FMC chip select(CS) 0. > > > > > > - SPI1: Play the role of a SPI Master controller. Or, there is a > > > dedicated path for HOST(X86) to access its BIOS flash mounted > > > under BMC. spi-aspeed.c implements the control sequence when > > > SPI1 is a SPI master. > > > > > > - SPI2: It is a pure SPI flash controller. For most scenarios, flashes > > > mounted under it are for pure storage purpose. > > > > > > ASPEED SPI controller supports 1-1-1, 1-1-2 and 1-1-4 SPI flash mode. > > > Three types of command mode are supported, normal mode, command > > > read/write mode and user mode. > > > - Normal mode: Default mode. After power on, normal read command 03h > > or > > >13h is used to fetch boot image from SPI flash. > > >- AST2500: Only 03h command can be used after power > > on > > > or reset. > > >- AST2600: If FMC04[6:4] is set, 13h command is used, > > > otherwise, 03h command. > > >The address length is decided by FMC04[2:0]. > > > > > > - Command mode: SPI controller can send command and address > > > automatically when CPU read/write the related > > remapped > > > or decoded address area. The command used by this > > mode > > > can be configured by FMC10/14/18[23:16]. Also, the > > > address length is decided by FMC04[2:0]. This mode will > > > be implemented in the following patch series. > > > > > > - User mode: It is a traditional and pure SPI operation, where > > > SPI transmission is controlled by CPU. It is the main > > > mode in this patch. > > > > > > Each SPI controller in ASPEED SoC has its own decoded address mapping. > > > Within each SPI controller decoded address, driver can assign a > > > specific address region for each CS of a SPI controller. The decoded > > > address cannot overlap to each other. With normal mode and command > > > mode, the decoded address accessed by the CPU determines which CS is > > active. > > > When user mode is adopted, the CS decoded address is a FIFO, CPU can > > > send/receive any SPI transmission by accessing the related decoded > > > address for the target CS. > > > > > > Signed-off-by: Chin-Ting Kuo > > > --- > > > configs/evb-ast2500_defconfig | 13 + configs/evb-ast2600_defconfig > > > | 13 + > > > drivers/spi/Kconfig | 8 + > > > drivers/spi/Makefile | 1 + > > > drivers/spi/spi-aspeed.c | 822 > > ++ > > > 5 files changed, 857 insertions(+) > > > create mode 100644 drivers/spi/spi-aspeed.c > > > > > > diff --git a/configs/evb-ast2500_defconfig > > > b/configs/evb-ast2500_defconfig index 53fe7776e9..f00bded237 100644 > > > --- a/configs/evb-ast2500_defconfig > > > +++ b/configs/evb-ast2500_defconfig > > > @@ -36,6 +36,16 @@ CONFIG_DM_I2C=y > > > CONFIG_SYS_I2C_ASPEED=y > > > CONFIG_MMC_SDHCI=y > > > CONFIG_MMC_SDHCI_ASPEED=y > > > +CONFIG_DM_SPI_FLASH=y > > > +CONFIG_SPI_FLASH_SFDP_SUPPORT=y > > > +CONFIG_SPI_FLASH_GIGADEVICE=y > > > +CONFIG_SPI_FLASH_ISSI=y > > > +CONFIG_SPI_FLASH_MACRONIX=y > > > +CONFIG_SPI_FLASH_SPANSION=y > > > +CONFIG_SPI_FLASH_STMICRO=y > > > +CONFIG_SPI_FLASH_SST=y > > > +CONFIG_SPI_FLASH_WINBOND=y > > > +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set > > > CONFIG_PHY_REALTEK=y > > > CONFIG_DM_ETH=y > > > CONFIG_FTGMAC100=y > > > @@ -45,6 +55,9 @@ CONFIG_RAM=y > > > CONFIG_DM_RESET=y > > > CONFIG_DM_SERIAL=y > > > CONFIG_SYS_NS16550=y > > > +CONFIG_SPI=y > > > +CONFIG_DM_SPI=y > > > +CONFIG_SPI_ASPEED=y > > > CONFIG_SYSRESET=y > > > CONFIG_TIMER=y > > > CONFIG_WDT=y > > > diff --git a/configs/evb-ast2600_defconfig > > > b/configs/evb-ast2600_defconfig index ea75762926..e013976bb0 100644 > > > --- a/configs/evb-ast2600_defconfig > > > +++ b/configs/evb-ast2600_defconfig > > > @@ -66,6 +66,16 @@ CONFIG_MISC=y > > > CONFIG_SPL_MISC=y > > > CONFIG_MMC_SDHCI=y > > > CONFIG_MMC_SDHCI_ASPEED=y > > > +CONFIG_DM_SPI_FLASH=y > > > +CONFIG_SPI_FLASH_SFDP_SUPPORT=y > > > +CONFIG_SPI_FLASH_GIGADEVICE=y > > > +CONFIG_SPI_FLASH_ISSI=y > > > +CONFIG_SPI_FLASH_MACRONIX=y > > > +CONFIG_SPI_FLASH_SPANSION=y > > > +CONFIG_SPI_FLASH_STMICRO=y > > > +CONFIG_SPI
RE: [PATCH 3/8] spi: aspeed: Add ASPEED SPI controller driver
Hi Jagan, Thanks for the review. > -Original Message- > From: Jagan Teki > Sent: Tuesday, May 3, 2022 8:32 PM > To: Chin-Ting Kuo > Subject: Re: [PATCH 3/8] spi: aspeed: Add ASPEED SPI controller driver > > On Thu, Apr 14, 2022 at 4:54 PM Chin-Ting Kuo > wrote: > > > > Add ASPEED BMC FMC/SPI memory controller driver with spi-mem interface > > for AST2500 and AST2600 platform. > > > > There are three SPI memory controllers embedded in an ASPEED SoC. > > - FMC: Named as Firmware Memory Controller. After AC on, MCU ROM > >fetches initial device boot image from FMC chip select(CS) 0. > > > > - SPI1: Play the role of a SPI Master controller. Or, there is a > > dedicated path for HOST(X86) to access its BIOS flash mounted > > under BMC. spi-aspeed.c implements the control sequence when > > SPI1 is a SPI master. > > > > - SPI2: It is a pure SPI flash controller. For most scenarios, flashes > > mounted under it are for pure storage purpose. > > > > ASPEED SPI controller supports 1-1-1, 1-1-2 and 1-1-4 SPI flash mode. > > Three types of command mode are supported, normal mode, command > > read/write mode and user mode. > > - Normal mode: Default mode. After power on, normal read command 03h > or > >13h is used to fetch boot image from SPI flash. > >- AST2500: Only 03h command can be used after power > on > > or reset. > >- AST2600: If FMC04[6:4] is set, 13h command is used, > > otherwise, 03h command. > >The address length is decided by FMC04[2:0]. > > > > - Command mode: SPI controller can send command and address > > automatically when CPU read/write the related > remapped > > or decoded address area. The command used by this > mode > > can be configured by FMC10/14/18[23:16]. Also, the > > address length is decided by FMC04[2:0]. This mode will > > be implemented in the following patch series. > > > > - User mode: It is a traditional and pure SPI operation, where > > SPI transmission is controlled by CPU. It is the main > > mode in this patch. > > > > Each SPI controller in ASPEED SoC has its own decoded address mapping. > > Within each SPI controller decoded address, driver can assign a > > specific address region for each CS of a SPI controller. The decoded > > address cannot overlap to each other. With normal mode and command > > mode, the decoded address accessed by the CPU determines which CS is > active. > > When user mode is adopted, the CS decoded address is a FIFO, CPU can > > send/receive any SPI transmission by accessing the related decoded > > address for the target CS. > > > > Signed-off-by: Chin-Ting Kuo > > --- > > configs/evb-ast2500_defconfig | 13 + configs/evb-ast2600_defconfig > > | 13 + > > drivers/spi/Kconfig | 8 + > > drivers/spi/Makefile | 1 + > > drivers/spi/spi-aspeed.c | 822 > ++ > > 5 files changed, 857 insertions(+) > > create mode 100644 drivers/spi/spi-aspeed.c > > > > diff --git a/configs/evb-ast2500_defconfig > > b/configs/evb-ast2500_defconfig index 53fe7776e9..f00bded237 100644 > > --- a/configs/evb-ast2500_defconfig > > +++ b/configs/evb-ast2500_defconfig > > @@ -36,6 +36,16 @@ CONFIG_DM_I2C=y > > CONFIG_SYS_I2C_ASPEED=y > > CONFIG_MMC_SDHCI=y > > CONFIG_MMC_SDHCI_ASPEED=y > > +CONFIG_DM_SPI_FLASH=y > > +CONFIG_SPI_FLASH_SFDP_SUPPORT=y > > +CONFIG_SPI_FLASH_GIGADEVICE=y > > +CONFIG_SPI_FLASH_ISSI=y > > +CONFIG_SPI_FLASH_MACRONIX=y > > +CONFIG_SPI_FLASH_SPANSION=y > > +CONFIG_SPI_FLASH_STMICRO=y > > +CONFIG_SPI_FLASH_SST=y > > +CONFIG_SPI_FLASH_WINBOND=y > > +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set > > CONFIG_PHY_REALTEK=y > > CONFIG_DM_ETH=y > > CONFIG_FTGMAC100=y > > @@ -45,6 +55,9 @@ CONFIG_RAM=y > > CONFIG_DM_RESET=y > > CONFIG_DM_SERIAL=y > > CONFIG_SYS_NS16550=y > > +CONFIG_SPI=y > > +CONFIG_DM_SPI=y > > +CONFIG_SPI_ASPEED=y > > CONFIG_SYSRESET=y > > CONFIG_TIMER=y > > CONFIG_WDT=y > > diff --git a/configs/evb-ast2600_defconfig > > b/configs/evb-ast2600_defconfig index ea75762926..e013976bb0 100644 > > --- a/configs/evb-ast2600_defconfig > > +++ b/configs/evb-ast2600_defconfig > > @@ -66,6 +66,16 @@ CONFIG_MISC=y > > CONFIG_SPL_MISC=y > > CONFIG_MMC_SDHCI=y > > CONFIG_MMC_SDHCI_ASPEED=y > > +CONFIG_DM_SPI_FLASH=y > > +CONFIG_SPI_FLASH_SFDP_SUPPORT=y > > +CONFIG_SPI_FLASH_GIGADEVICE=y > > +CONFIG_SPI_FLASH_ISSI=y > > +CONFIG_SPI_FLASH_MACRONIX=y > > +CONFIG_SPI_FLASH_SPANSION=y > > +CONFIG_SPI_FLASH_STMICRO=y > > +CONFIG_SPI_FLASH_SST=y > > +CONFIG_SPI_FLASH_WINBOND=y > > +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set > > CONFIG_PHY_REALTEK=y > > CONFIG_DM_ETH=y > > CONFIG_DM_MDIO=y > > @@ -78,6 +88,9 @@ CONFIG_SPL_RAM=y > > CONFIG_DM_RESET=y > > CONFIG_DM_SERIAL=y > > CONFIG_SYS_NS16550=y > > +CONFIG_SPI=y >
[PATCH] common/console.c: prevent pre-console buffer contents from being added to itself
I do not have any non-serial output devices, so a
print_pre_console_buffer(PRE_CONSOLE_FLUSHPOINT2_EVERYTHING_BUT_SERIAL)
does nothing for me.
However, I was manually inspected the pre-console buffer using md.b,
and I noticed that the early part of it was repeated. The reason is
that the first call of print_pre_console_buffer(), from
console_init_f(), ends up invoking puts() with the contents of the
buffer at that point, and puts() at that point ends up in the else
branch of
if (gd->flags & GD_FLG_DEVINIT) {
/* Send to the standard output */
fputs(stdout, s);
} else {
/* Send directly to the handler */
pre_console_puts(s);
serial_puts(s);
}
so indeed the contents is added again.
That can be somewhat confusing (both when reading the buffer manually,
but also if it did actually come out on some device). So disable all
use of the pre-console buffer while print_pre_console_buffer() is
emitting it.
Signed-off-by: Rasmus Villemoes
---
common/console.c | 10 +-
include/asm-generic/global_data.h | 12
2 files changed, 17 insertions(+), 5 deletions(-)
diff --git a/common/console.c b/common/console.c
index dc071f1ed6..c5a72d9a2a 100644
--- a/common/console.c
+++ b/common/console.c
@@ -599,6 +599,9 @@ static void pre_console_putc(const char c)
{
char *buffer;
+ if (gd->precon_buf_idx < 0)
+ return;
+
buffer = map_sysmem(CONFIG_VAL(PRE_CON_BUF_ADDR),
CONFIG_VAL(PRE_CON_BUF_SZ));
buffer[CIRC_BUF_IDX(gd->precon_buf_idx++)] = c;
@@ -608,13 +611,16 @@ static void pre_console_putc(const char c)
static void pre_console_puts(const char *s)
{
+ if (gd->precon_buf_idx < 0)
+ return;
+
while (*s)
pre_console_putc(*s++);
}
static void print_pre_console_buffer(int flushpoint)
{
- unsigned long in = 0, out = 0;
+ long in = 0, out = 0;
char buf_out[CONFIG_VAL(PRE_CON_BUF_SZ) + 1];
char *buf_in;
@@ -631,6 +637,7 @@ static void print_pre_console_buffer(int flushpoint)
buf_out[out] = 0;
+ gd->precon_buf_idx = -1;
switch (flushpoint) {
case PRE_CONSOLE_FLUSHPOINT1_SERIAL:
puts(buf_out);
@@ -639,6 +646,7 @@ static void print_pre_console_buffer(int flushpoint)
console_puts_select(stdout, false, buf_out);
break;
}
+ gd->precon_buf_idx = in;
}
#else
static inline void pre_console_putc(const char c) {}
diff --git a/include/asm-generic/global_data.h
b/include/asm-generic/global_data.h
index 805a6fd679..2a747d91e1 100644
--- a/include/asm-generic/global_data.h
+++ b/include/asm-generic/global_data.h
@@ -115,10 +115,14 @@ struct global_data {
/**
* @precon_buf_idx: pre-console buffer index
*
-* @precon_buf_idx indicates the current position of the buffer used to
-* collect output before the console becomes available
-*/
- unsigned long precon_buf_idx;
+* @precon_buf_idx indicates the current position of the
+* buffer used to collect output before the console becomes
+* available. When negative, the pre-console buffer is
+* temporarily disabled (used when the pre-console buffer is
+* being written out, to prevent adding its contents to
+* itself).
+*/
+ long precon_buf_idx;
#endif
/**
* @env_addr: address of environment structure
--
2.31.1
[PATCH] common/console.c: use CONFIG_VAL() with PRE_CON_BUF_* variables
There is currently no support for PRE_CONSOLE_BUFFER in SPL, but if
and when that gets implemented, one would almost certainly want to use
a different address and/or size for the buffer (e.g., U-Boot proper
might specify an address in DRAM and a generous buffer, while SPL
would be much more constrained).
So a prerequisite for adding SPL_PRE_CONSOLE_BUFFER is to make the
code use SPL_-specific values. No functional change.
Signed-off-by: Rasmus Villemoes
---
common/console.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/common/console.c b/common/console.c
index 92b1c93be1..dc071f1ed6 100644
--- a/common/console.c
+++ b/common/console.c
@@ -593,13 +593,13 @@ int tstc(void)
#define PRE_CONSOLE_FLUSHPOINT2_EVERYTHING_BUT_SERIAL 1
#if CONFIG_IS_ENABLED(PRE_CONSOLE_BUFFER)
-#define CIRC_BUF_IDX(idx) ((idx) % (unsigned long)CONFIG_PRE_CON_BUF_SZ)
+#define CIRC_BUF_IDX(idx) ((idx) % (unsigned long)CONFIG_VAL(PRE_CON_BUF_SZ))
static void pre_console_putc(const char c)
{
char *buffer;
- buffer = map_sysmem(CONFIG_PRE_CON_BUF_ADDR, CONFIG_PRE_CON_BUF_SZ);
+ buffer = map_sysmem(CONFIG_VAL(PRE_CON_BUF_ADDR),
CONFIG_VAL(PRE_CON_BUF_SZ));
buffer[CIRC_BUF_IDX(gd->precon_buf_idx++)] = c;
@@ -615,15 +615,15 @@ static void pre_console_puts(const char *s)
static void print_pre_console_buffer(int flushpoint)
{
unsigned long in = 0, out = 0;
- char buf_out[CONFIG_PRE_CON_BUF_SZ + 1];
+ char buf_out[CONFIG_VAL(PRE_CON_BUF_SZ) + 1];
char *buf_in;
if (IS_ENABLED(CONFIG_SILENT_CONSOLE) && (gd->flags & GD_FLG_SILENT))
return;
- buf_in = map_sysmem(CONFIG_PRE_CON_BUF_ADDR, CONFIG_PRE_CON_BUF_SZ);
- if (gd->precon_buf_idx > CONFIG_PRE_CON_BUF_SZ)
- in = gd->precon_buf_idx - CONFIG_PRE_CON_BUF_SZ;
+ buf_in = map_sysmem(CONFIG_VAL(PRE_CON_BUF_ADDR),
CONFIG_VAL(PRE_CON_BUF_SZ));
+ if (gd->precon_buf_idx > CONFIG_VAL(PRE_CON_BUF_SZ))
+ in = gd->precon_buf_idx - CONFIG_VAL(PRE_CON_BUF_SZ);
while (in < gd->precon_buf_idx)
buf_out[out++] = buf_in[CIRC_BUF_IDX(in++)];
--
2.31.1
Help porting U-Boot to samsung-espresso3g
Hello! I am trying to get u boot running on the samsung-espresso3g (https://wiki.postmarketos.org/wiki/Samsung_Galaxy_Tab_2_7.0%22_(samsung-espresso3g)) but it gets stuck at the bootsplash (ie the Samsung logo). Here is my fork https://github.com/MightyM17/u-boot/tree/espresso-dev. Any guidance on what i should do?
Re: [PATCH 3/8] spi: aspeed: Add ASPEED SPI controller driver
On Thu, Apr 14, 2022 at 4:54 PM Chin-Ting Kuo wrote: > > Add ASPEED BMC FMC/SPI memory controller driver with > spi-mem interface for AST2500 and AST2600 platform. > > There are three SPI memory controllers embedded in an ASPEED SoC. > - FMC: Named as Firmware Memory Controller. After AC on, MCU ROM >fetches initial device boot image from FMC chip select(CS) 0. > > - SPI1: Play the role of a SPI Master controller. Or, there is a > dedicated path for HOST(X86) to access its BIOS flash mounted > under BMC. spi-aspeed.c implements the control sequence when > SPI1 is a SPI master. > > - SPI2: It is a pure SPI flash controller. For most scenarios, flashes > mounted under it are for pure storage purpose. > > ASPEED SPI controller supports 1-1-1, 1-1-2 and 1-1-4 SPI flash mode. > Three types of command mode are supported, normal mode, command > read/write mode and user mode. > - Normal mode: Default mode. After power on, normal read command 03h or >13h is used to fetch boot image from SPI flash. >- AST2500: Only 03h command can be used after power on > or reset. >- AST2600: If FMC04[6:4] is set, 13h command is used, > otherwise, 03h command. >The address length is decided by FMC04[2:0]. > > - Command mode: SPI controller can send command and address > automatically when CPU read/write the related remapped > or decoded address area. The command used by this mode > can be configured by FMC10/14/18[23:16]. Also, the > address length is decided by FMC04[2:0]. This mode will > be implemented in the following patch series. > > - User mode: It is a traditional and pure SPI operation, where > SPI transmission is controlled by CPU. It is the main > mode in this patch. > > Each SPI controller in ASPEED SoC has its own decoded address mapping. > Within each SPI controller decoded address, driver can assign a specific > address region for each CS of a SPI controller. The decoded address > cannot overlap to each other. With normal mode and command mode, the > decoded address accessed by the CPU determines which CS is active. > When user mode is adopted, the CS decoded address is a FIFO, CPU can > send/receive any SPI transmission by accessing the related decoded > address for the target CS. > > Signed-off-by: Chin-Ting Kuo > --- > configs/evb-ast2500_defconfig | 13 + > configs/evb-ast2600_defconfig | 13 + > drivers/spi/Kconfig | 8 + > drivers/spi/Makefile | 1 + > drivers/spi/spi-aspeed.c | 822 ++ > 5 files changed, 857 insertions(+) > create mode 100644 drivers/spi/spi-aspeed.c > > diff --git a/configs/evb-ast2500_defconfig b/configs/evb-ast2500_defconfig > index 53fe7776e9..f00bded237 100644 > --- a/configs/evb-ast2500_defconfig > +++ b/configs/evb-ast2500_defconfig > @@ -36,6 +36,16 @@ CONFIG_DM_I2C=y > CONFIG_SYS_I2C_ASPEED=y > CONFIG_MMC_SDHCI=y > CONFIG_MMC_SDHCI_ASPEED=y > +CONFIG_DM_SPI_FLASH=y > +CONFIG_SPI_FLASH_SFDP_SUPPORT=y > +CONFIG_SPI_FLASH_GIGADEVICE=y > +CONFIG_SPI_FLASH_ISSI=y > +CONFIG_SPI_FLASH_MACRONIX=y > +CONFIG_SPI_FLASH_SPANSION=y > +CONFIG_SPI_FLASH_STMICRO=y > +CONFIG_SPI_FLASH_SST=y > +CONFIG_SPI_FLASH_WINBOND=y > +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set > CONFIG_PHY_REALTEK=y > CONFIG_DM_ETH=y > CONFIG_FTGMAC100=y > @@ -45,6 +55,9 @@ CONFIG_RAM=y > CONFIG_DM_RESET=y > CONFIG_DM_SERIAL=y > CONFIG_SYS_NS16550=y > +CONFIG_SPI=y > +CONFIG_DM_SPI=y > +CONFIG_SPI_ASPEED=y > CONFIG_SYSRESET=y > CONFIG_TIMER=y > CONFIG_WDT=y > diff --git a/configs/evb-ast2600_defconfig b/configs/evb-ast2600_defconfig > index ea75762926..e013976bb0 100644 > --- a/configs/evb-ast2600_defconfig > +++ b/configs/evb-ast2600_defconfig > @@ -66,6 +66,16 @@ CONFIG_MISC=y > CONFIG_SPL_MISC=y > CONFIG_MMC_SDHCI=y > CONFIG_MMC_SDHCI_ASPEED=y > +CONFIG_DM_SPI_FLASH=y > +CONFIG_SPI_FLASH_SFDP_SUPPORT=y > +CONFIG_SPI_FLASH_GIGADEVICE=y > +CONFIG_SPI_FLASH_ISSI=y > +CONFIG_SPI_FLASH_MACRONIX=y > +CONFIG_SPI_FLASH_SPANSION=y > +CONFIG_SPI_FLASH_STMICRO=y > +CONFIG_SPI_FLASH_SST=y > +CONFIG_SPI_FLASH_WINBOND=y > +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set > CONFIG_PHY_REALTEK=y > CONFIG_DM_ETH=y > CONFIG_DM_MDIO=y > @@ -78,6 +88,9 @@ CONFIG_SPL_RAM=y > CONFIG_DM_RESET=y > CONFIG_DM_SERIAL=y > CONFIG_SYS_NS16550=y > +CONFIG_SPI=y > +CONFIG_DM_SPI=y > +CONFIG_SPI_ASPEED=y > CONFIG_SYSRESET=y > CONFIG_SPL_SYSRESET=y > CONFIG_WDT=y Separate patches for spi driver and config enablements.
[PATCH] CI: Azure: Rework how we update MSYS2
Based on reading https://www.msys2.org/docs/ci/ and "Other Systems" rework how we update MSYS2 to the current version. We run it once, to perform nothing other than being the first run, then we run pacman twice. Signed-off-by: Tom Rini --- .azure-pipelines.yml | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/.azure-pipelines.yml b/.azure-pipelines.yml index f9acb9898ea9..3f211b86e4b2 100644 --- a/.azure-pipelines.yml +++ b/.azure-pipelines.yml @@ -22,8 +22,9 @@ stages: displayName: 'Install MSYS2' - script: | sfx.exe -y -o%CD:~0,2%\ - %CD:~0,2%\msys64\usr\bin\bash -lc "pacman --noconfirm -Syyuu" - %CD:~0,2%\msys64\usr\bin\bash -lc "pacman --noconfirm -Su" + %CD:~0,2%\msys64\usr\bin\bash -lc " " + %CD:~0,2%\msys64\usr\bin\bash -lc "pacman --noconfirm -Syuu" + %CD:~0,2%\msys64\usr\bin\bash -lc "pacman --noconfirm -Syuu" displayName: 'Update MSYS2' - script: | %CD:~0,2%\msys64\usr\bin\bash -lc "pacman --noconfirm --needed -Sy make gcc bison flex diffutils openssl-devel libgnutls-devel libutil-linux-devel" -- 2.25.1
Re: [PATCH v2 0/2] sf: dataflash: add support for AT45DB641E
On Tue, Apr 26, 2022 at 1:54 PM Luca Ellero wrote: > > Since AT45DB641E uses "extended device information" for reading JEDEC ID > we must first introduce support for this feature. > All code is borrowed from Linux kernel source code: > drivers/mtd/devices/mtd_dataflash.c > commit 1da8869a428317a6d3cd8d47184cf87feb34a98b > Author: Andrey Smirnov > > Changes for v2: > - add reference to Linux kernel commit > > Luca Ellero (2): > sf: dataflash: add support for "extended ID" > sf: dataflash: add support for AT45DB641E Applied to u-boot-spi/master
[PATCH v1] imx: enable ahab on imx8qm-rom7720
enable ahab on imx8qm-rom7720 Signed-off-by: Oliver Graute --- configs/imx8qm_rom7720_a1_4G_defconfig | 1 + include/configs/imx8qm_rom7720.h | 7 +++ 2 files changed, 8 insertions(+) diff --git a/configs/imx8qm_rom7720_a1_4G_defconfig b/configs/imx8qm_rom7720_a1_4G_defconfig index d9997cfa82..49deb283ff 100644 --- a/configs/imx8qm_rom7720_a1_4G_defconfig +++ b/configs/imx8qm_rom7720_a1_4G_defconfig @@ -85,4 +85,5 @@ CONFIG_SPL_DM_REGULATOR_GPIO=y CONFIG_DM_SERIAL=y CONFIG_FSL_LPUART=y CONFIG_SPL_TINY_MEMSET=y +CONFIG_AHAB_BOOT=y # CONFIG_EFI_LOADER is not set diff --git a/include/configs/imx8qm_rom7720.h b/include/configs/imx8qm_rom7720.h index 81ab5d8caa..b98e739e00 100644 --- a/include/configs/imx8qm_rom7720.h +++ b/include/configs/imx8qm_rom7720.h @@ -22,6 +22,12 @@ #define CONFIG_SYS_BOOTM_LEN SZ_64M +#ifdef CONFIG_AHAB_BOOT +#define AHAB_ENV "sec_boot=yes\0" +#else +#define AHAB_ENV "sec_boot=no\0" +#endif + /* FUSE command */ /* Boot M4 */ @@ -54,6 +60,7 @@ /* Initial environment variables */ #define CONFIG_EXTRA_ENV_SETTINGS \ + AHAB_ENV \ CONFIG_MFG_ENV_SETTINGS \ M4_BOOT_ENV \ "script=boot.scr\0" \ -- 2.17.1
[PATCH v2] spi: npcm-fiu: add NPCM7xx FIU controller driver
From: Jim Liu
Add Nuvoton NPCM BMC Flash Interface Unit(FIU) SPI master
controller driver using SPI-MEM interface.
The FIU supports single, dual or quad communication interface.
The FIU controller driver provides flash access in UMA(User
Mode Access) mode by using an indirect address/data mechanism.
the dts node is followed upstream kernel dts name.
Signed-off-by: Jim Liu
Signed-off-by: Stanley Chu
Reviewed-by: Jagan Teki
[Jagan: fixed the Kconfig, Makefile order]
Signed-off-by: Jagan Teki
---
Changes for v2:
- fixed author e-mail
- fixed Makefile and Kconfig order
drivers/spi/Kconfig| 6 +
drivers/spi/Makefile | 1 +
drivers/spi/npcm_fiu_spi.c | 387 +
3 files changed, 394 insertions(+)
create mode 100644 drivers/spi/npcm_fiu_spi.c
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 8dba95ae4e..a1e515cb2b 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -283,6 +283,12 @@ config SPI_MXIC
can be used to access the SPI flash on platforms embedding
this Macronix IP core.
+config NPCM_FIU_SPI
+ bool "FIU driver for Nuvoton NPCM SoC"
+ help
+ This enables support for the Flash Interface Unit SPI controller
+ in master mode.
+
config NXP_FSPI
bool "NXP FlexSPI driver"
depends on SPI_MEM
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 7f43f843ca..06e81b465b 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -47,6 +47,7 @@ obj-$(CONFIG_MSCC_BB_SPI) += mscc_bb_spi.o
obj-$(CONFIG_MVEBU_A3700_SPI) += mvebu_a3700_spi.o
obj-$(CONFIG_MXC_SPI) += mxc_spi.o
obj-$(CONFIG_MXS_SPI) += mxs_spi.o
+obj-$(CONFIG_NPCM_FIU_SPI) += npcm_fiu_spi.o
obj-$(CONFIG_NXP_FSPI) += nxp_fspi.o
obj-$(CONFIG_ATCSPI200_SPI) += atcspi200_spi.o
obj-$(CONFIG_OCTEON_SPI) += octeon_spi.o
diff --git a/drivers/spi/npcm_fiu_spi.c b/drivers/spi/npcm_fiu_spi.c
new file mode 100644
index 00..7000fe5860
--- /dev/null
+++ b/drivers/spi/npcm_fiu_spi.c
@@ -0,0 +1,387 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2022 Nuvoton Technology Corp.
+ * NPCM Flash Interface Unit(FIU) SPI master controller driver.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define DW_SIZE4
+#define CHUNK_SIZE 16
+#define XFER_TIMEOUT 100
+
+/* FIU UMA Configuration Register (UMA_CFG) */
+#define UMA_CFG_RDATSIZ_MASK GENMASK(28, 24)
+#define UMA_CFG_DBSIZ_MASK GENMASK(23, 21)
+#define UMA_CFG_WDATSIZ_MASK GENMASK(20, 16)
+#define UMA_CFG_ADDSIZ_MASKGENMASK(13, 11)
+#define UMA_CFG_RDBPCK_MASKGENMASK(9, 8)
+#define UMA_CFG_DBPCK_MASK GENMASK(7, 6)
+#define UMA_CFG_WDBPCK_MASKGENMASK(5, 4)
+#define UMA_CFG_ADBPCK_MASKGENMASK(3, 2)
+#define UMA_CFG_CMBPCK_MASKGENMASK(1, 0)
+#define UMA_CFG_CMDSIZ_SHIFT 10
+
+/* FIU UMA Control and Status Register (UMA_CTS) */
+#define UMA_CTS_SW_CS BIT(16)
+#define UMA_CTS_EXEC_DONE BIT(0)
+#define UMA_CTS_RDYST BIT(24)
+#define UMA_CTS_DEV_NUM_MASK GENMASK(9, 8)
+
+struct npcm_fiu_regs {
+ unsigned intdrd_cfg;
+ unsigned intdwr_cfg;
+ unsigned intuma_cfg;
+ unsigned intuma_cts;
+ unsigned intuma_cmd;
+ unsigned intuma_addr;
+ unsigned intprt_cfg;
+ unsigned char res1[4];
+ unsigned intuma_dw0;
+ unsigned intuma_dw1;
+ unsigned intuma_dw2;
+ unsigned intuma_dw3;
+ unsigned intuma_dr0;
+ unsigned intuma_dr1;
+ unsigned intuma_dr2;
+ unsigned intuma_dr3;
+ unsigned intprt_cmd0;
+ unsigned intprt_cmd1;
+ unsigned intprt_cmd2;
+ unsigned intprt_cmd3;
+ unsigned intprt_cmd4;
+ unsigned intprt_cmd5;
+ unsigned intprt_cmd6;
+ unsigned intprt_cmd7;
+ unsigned intprt_cmd8;
+ unsigned intprt_cmd9;
+ unsigned intstuff[4];
+ unsigned intfiu_cfg;
+};
+
+struct npcm_fiu_priv {
+ struct npcm_fiu_regs *regs;
+ struct clk clk;
+};
+
+static int npcm_fiu_spi_set_speed(struct udevice *bus, uint speed)
+{
+ struct npcm_fiu_priv *priv = dev_get_priv(bus);
+ int ret;
+
+ debug("%s: set speed %u\n", bus->name, speed);
+ ret = clk_set_rate(&priv->clk, speed);
+ if (ret < 0)
+ return ret;
+
+ return 0;
+}
+
+static int npcm_fiu_spi_set_mode(struct udevice *bus, uint mode)
+{
+ return 0;
+}
+
+static inline void activate_cs(struct npcm_fiu_regs *regs, int cs)
+{
+ writel(FIELD_PREP(UMA_CTS_DEV_NUM_MASK, cs), ®s->uma_cts);
+}
+
+static inline void deactivate_cs(struct npcm_fiu_regs *regs, int cs)
+{
+ writel(FIELD_PREP(UMA_CTS_DEV_NUM_MASK, cs) | UMA_CTS_SW_CS,
®s->uma_cts);
+}
+
+static int fiu_uma_read(struct udevice *bus, u8 *buf, u32 size)
+{
+ struct npcm_fiu
Re: [PATCH] mtd: spi-nor-ids: add Macronix flash entry
On Wed, Apr 27, 2022 at 9:27 AM wrote: > > From: Tien Fong Chee > > Add Macronix mx25u51245g flash entry, so this can be used on > SoCFPGA devices. > > Signed-off-by: Tien Fong Chee > --- Applied to u-boot-spi/master
[PATCH 13/17] imx: imx8mp_rsb7320a1: enable wdog driver model in SPL
From: Peng Fan
Mark wdog1/pinctrl_wdog as u-boot,dm-spl to clean up board code,
set_wdog_reset function could be handled by imx_watchdog.c driver.
Signed-off-by: Peng Fan
---
arch/arm/dts/imx8mp-rsb3720-a1-u-boot.dtsi | 8
board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c | 12
2 files changed, 8 insertions(+), 12 deletions(-)
diff --git a/arch/arm/dts/imx8mp-rsb3720-a1-u-boot.dtsi
b/arch/arm/dts/imx8mp-rsb3720-a1-u-boot.dtsi
index 2848b24f655..4419967ee42 100644
--- a/arch/arm/dts/imx8mp-rsb3720-a1-u-boot.dtsi
+++ b/arch/arm/dts/imx8mp-rsb3720-a1-u-boot.dtsi
@@ -89,6 +89,14 @@
u-boot,dm-spl;
};
+&wdog1 {
+ u-boot,dm-spl;
+};
+
+&pinctrl_wdog {
+ u-boot,dm-spl;
+};
+
&pinctrl_i2c1 {
u-boot,dm-spl;
};
diff --git a/board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c
b/board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c
index f129ebd429b..0a1b2c94161 100644
--- a/board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c
+++ b/board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c
@@ -28,12 +28,6 @@
DECLARE_GLOBAL_DATA_PTR;
-#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
-
-static const iomux_v3_cfg_t wdog_pads[] = {
- MX8MP_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
-};
-
#ifdef CONFIG_NAND_MXS
static void setup_gpmi_nand(void)
{
@@ -69,12 +63,6 @@ u8 num_image_type_guids = ARRAY_SIZE(fw_images);
int board_early_init_f(void)
{
- struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
-
- imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
-
- set_wdog_reset(wdog);
-
init_uart_clk(2);
return 0;
--
2.36.0
Re: [PATCH 07/17] imx: engicam-imx8mm: drop unused macro
Hi
On Tue, May 3, 2022 at 1:44 PM Peng Fan (OSS) wrote:
>
> From: Peng Fan
>
> Drop unused WDOG macro
>
> Signed-off-by: Peng Fan
> ---
> board/engicam/imx8mm/spl.c | 2 --
> 1 file changed, 2 deletions(-)
>
> diff --git a/board/engicam/imx8mm/spl.c b/board/engicam/imx8mm/spl.c
> index f75f2dc634c..1846134a492 100644
> --- a/board/engicam/imx8mm/spl.c
> +++ b/board/engicam/imx8mm/spl.c
> @@ -54,8 +54,6 @@ int board_fit_config_name_match(const char *name)
> }
> #endif
>
> -#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE |
> PAD_CTL_PE)
> -
> int board_early_init_f(void)
> {
> return 0;
> --
> 2.36.0
>
Reviewed-by: Michael Trimarchi
--
Michael Nazzareno Trimarchi
Co-Founder & Chief Executive Officer
M. +39 347 913 2170
mich...@amarulasolutions.com
__
Amarula Solutions BV
Joop Geesinkweg 125, 1114 AB, Amsterdam, NL
T. +31 (0)85 111 9172
i...@amarulasolutions.com
www.amarulasolutions.com
[PATCH 16/17] imx: verdin-imx8mm/p: cleanup board watchdog code
From: Peng Fan
pinctrl_wdog already marked u-boot,dm-spl, so clean up board code.
set_wdog_reset function could be handled by imx_watchdog.c driver.
Signed-off-by: Peng Fan
---
board/toradex/verdin-imx8mp/verdin-imx8mp.c | 11 ---
1 file changed, 11 deletions(-)
diff --git a/board/toradex/verdin-imx8mp/verdin-imx8mp.c
b/board/toradex/verdin-imx8mp/verdin-imx8mp.c
index 8334c9bb376..e3c1a1201da 100644
--- a/board/toradex/verdin-imx8mp/verdin-imx8mp.c
+++ b/board/toradex/verdin-imx8mp/verdin-imx8mp.c
@@ -24,7 +24,6 @@
DECLARE_GLOBAL_DATA_PTR;
#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
-#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
/* Verdin UART_3, Console/Debug UART */
static const iomux_v3_cfg_t uart_pads[] = {
@@ -32,18 +31,8 @@ static const iomux_v3_cfg_t uart_pads[] = {
MX8MP_PAD_UART3_TXD__UART3_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
};
-static const iomux_v3_cfg_t wdog_pads[] = {
- MX8MP_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
-};
-
int board_early_init_f(void)
{
- struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
-
- imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
-
- set_wdog_reset(wdog);
-
imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
init_uart_clk(2);
--
2.36.0
[PATCH 17/17] imx: toradex/verdin-imx8mm/p: cleanup board watchdog code
From: Peng Fan
pinctrl_wdog already marked u-boot,dm-spl, so clean up board code.
set_wdog_reset function could be handled by imx_watchdog.c driver.
Signed-off-by: Peng Fan
---
board/toradex/verdin-imx8mm/spl.c | 11 ---
1 file changed, 11 deletions(-)
diff --git a/board/toradex/verdin-imx8mm/spl.c
b/board/toradex/verdin-imx8mm/spl.c
index 1f3f38351ef..1f643129d98 100644
--- a/board/toradex/verdin-imx8mm/spl.c
+++ b/board/toradex/verdin-imx8mm/spl.c
@@ -75,7 +75,6 @@ int board_fit_config_name_match(const char *name)
#endif
#define UART_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_PE | PAD_CTL_DSE4)
-#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
/* Verdin UART_3, Console/Debug UART */
static iomux_v3_cfg_t const uart_pads[] = {
@@ -83,20 +82,10 @@ static iomux_v3_cfg_t const uart_pads[] = {
IMX8MM_PAD_SAI2_RXC_UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
};
-static iomux_v3_cfg_t const wdog_pads[] = {
- IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
-};
-
__weak void board_early_init(void)
{
- struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
-
init_uart_clk(0);
- imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
-
- set_wdog_reset(wdog);
-
imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
}
--
2.36.0
[PATCH 15/17] imx: phycore_imx8mm/p: clean up board watchdog code
From: Peng Fan
pinctrl_wdog already marked u-boot,dm-spl, so clean up board code.
set_wdog_reset function could be handled by imx_watchdog.c driver.
Signed-off-by: Peng Fan
---
board/phytec/phycore_imx8mm/spl.c | 19 ---
board/phytec/phycore_imx8mp/spl.c | 19 ---
2 files changed, 38 deletions(-)
diff --git a/board/phytec/phycore_imx8mm/spl.c
b/board/phytec/phycore_imx8mm/spl.c
index 7f24a3affc8..d87ab6d4497 100644
--- a/board/phytec/phycore_imx8mm/spl.c
+++ b/board/phytec/phycore_imx8mm/spl.c
@@ -57,23 +57,6 @@ int board_fit_config_name_match(const char *name)
return 0;
}
-#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE)
-
-static iomux_v3_cfg_t const wdog_pads[] = {
- IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
-};
-
-int board_early_init_f(void)
-{
- struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
-
- imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
-
- set_wdog_reset(wdog);
-
- return 0;
-}
-
void board_init_f(ulong dummy)
{
int ret;
@@ -82,8 +65,6 @@ void board_init_f(ulong dummy)
init_uart_clk(2);
- board_early_init_f();
-
/* Clear the BSS. */
memset(__bss_start, 0, __bss_end - __bss_start);
diff --git a/board/phytec/phycore_imx8mp/spl.c
b/board/phytec/phycore_imx8mp/spl.c
index 38a581bef57..faed6fc3b76 100644
--- a/board/phytec/phycore_imx8mp/spl.c
+++ b/board/phytec/phycore_imx8mp/spl.c
@@ -89,23 +89,6 @@ int board_fit_config_name_match(const char *name)
return 0;
}
-#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
-
-static iomux_v3_cfg_t const wdog_pads[] = {
- MX8MP_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
-};
-
-int board_early_init_f(void)
-{
- struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
-
- imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
-
- set_wdog_reset(wdog);
-
- return 0;
-}
-
void board_init_f(ulong dummy)
{
int ret;
@@ -114,8 +97,6 @@ void board_init_f(ulong dummy)
init_uart_clk(0);
- board_early_init_f();
-
ret = spl_early_init();
if (ret) {
debug("spl_early_init() failed: %d\n", ret);
--
2.36.0
[PATCH 14/17] imx: imx8mn-kontron-n801x: enable pinctrl_wdog in SPL
From: Peng Fan
Mark pinctrl_wdog as u-boot,dm-spl to clean up board code,
set_wdog_reset function could be handled by imx_watchdog.c driver.
Signed-off-by: Peng Fan
---
arch/arm/dts/imx8mm-kontron-n801x-u-boot.dtsi | 4
board/kontron/sl-mx8mm/spl.c | 18 --
2 files changed, 4 insertions(+), 18 deletions(-)
diff --git a/arch/arm/dts/imx8mm-kontron-n801x-u-boot.dtsi
b/arch/arm/dts/imx8mm-kontron-n801x-u-boot.dtsi
index 22d18e6f1cf..6882513f161 100644
--- a/arch/arm/dts/imx8mm-kontron-n801x-u-boot.dtsi
+++ b/arch/arm/dts/imx8mm-kontron-n801x-u-boot.dtsi
@@ -126,3 +126,7 @@
&wdog1 {
u-boot,dm-spl;
};
+
+&pinctrl_wdog {
+ u-boot,dm-spl;
+};
diff --git a/board/kontron/sl-mx8mm/spl.c b/board/kontron/sl-mx8mm/spl.c
index a58a75dc958..63361f1d2ab 100644
--- a/board/kontron/sl-mx8mm/spl.c
+++ b/board/kontron/sl-mx8mm/spl.c
@@ -32,7 +32,6 @@ enum {
#define GPIO_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
#define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
-#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
#define TOUCH_RESET_GPIO IMX_GPIO_NR(3, 23)
@@ -50,10 +49,6 @@ static iomux_v3_cfg_t const touch_gpio[] = {
IMX8MM_PAD_SAI5_RXD2_GPIO3_IO23 | MUX_PAD_CTRL(GPIO_PAD_CTRL)
};
-static iomux_v3_cfg_t const wdog_pads[] = {
- IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
-};
-
int spl_board_boot_device(enum boot_device boot_dev_spl)
{
switch (boot_dev_spl) {
@@ -216,17 +211,6 @@ void spl_board_init(void)
printf("Failed to find clock node. Check device tree\n");
}
-int board_early_init_f(void)
-{
- struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
-
- imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
-
- set_wdog_reset(wdog);
-
- return 0;
-}
-
static int power_init_board(void)
{
struct udevice *dev;
@@ -261,8 +245,6 @@ void board_init_f(ulong dummy)
init_uart_clk(2);
- board_early_init_f();
-
timer_init();
/* Clear the BSS. */
--
2.36.0
[PATCH 12/17] imx: imx8mn_var_som: clean up board watchdog code
From: Peng Fan
pinctrl_wdog already marked u-boot,dm-spl, so clean up board code.
set_wdog_reset function could be handled by imx_watchdog.c driver.
Signed-off-by: Peng Fan
---
board/variscite/imx8mn_var_som/spl.c | 11 ---
1 file changed, 11 deletions(-)
diff --git a/board/variscite/imx8mn_var_som/spl.c
b/board/variscite/imx8mn_var_som/spl.c
index 1a8b64fc0a9..41e70505774 100644
--- a/board/variscite/imx8mn_var_som/spl.c
+++ b/board/variscite/imx8mn_var_som/spl.c
@@ -40,19 +40,8 @@ void spl_board_init(void)
puts("Failed to find clock node. Check device tree\n");
}
-#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
-
-static const iomux_v3_cfg_t wdog_pads[] = {
- IMX8MN_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
-};
-
int board_early_init_f(void)
{
- struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
-
- imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
- set_wdog_reset(wdog);
-
init_uart_clk(3);
return 0;
--
2.36.0
[PATCH 11/17] imx: imx8mn_smm_s2: clean up board watchdog code
From: Peng Fan
pinctrl_wdog already marked u-boot,dm-spl, so clean up board code.
set_wdog_reset function could be handled by imx_watchdog.c driver.
Signed-off-by: Peng Fan
---
board/bsh/imx8mn_smm_s2/spl.c | 11 ---
1 file changed, 11 deletions(-)
diff --git a/board/bsh/imx8mn_smm_s2/spl.c b/board/bsh/imx8mn_smm_s2/spl.c
index 0f61acc6302..4ccee7c31a8 100644
--- a/board/bsh/imx8mn_smm_s2/spl.c
+++ b/board/bsh/imx8mn_smm_s2/spl.c
@@ -40,19 +40,8 @@ void spl_board_init(void)
puts("Failed to find clock node. Check device tree\n");
}
-#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
-
-static const iomux_v3_cfg_t wdog_pads[] = {
- IMX8MN_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
-};
-
int board_early_init_f(void)
{
- struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
-
- imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
- set_wdog_reset(wdog);
-
init_uart_clk(3);
if (IS_ENABLED(CONFIG_NAND_MXS)) {
--
2.36.0
[PATCH 10/17] imx: imx8mn-beacon: enable pinctrl_wdog in SPL
From: Peng Fan
Mark pinctrl_wdog as u-boot,dm-spl to clean up board code,
set_wdog_reset function could be handled by imx_watchdog.c driver.
Signed-off-by: Peng Fan
---
arch/arm/dts/imx8mn-beacon-kit-u-boot.dtsi | 4
board/beacon/imx8mn/spl.c | 10 --
2 files changed, 4 insertions(+), 10 deletions(-)
diff --git a/arch/arm/dts/imx8mn-beacon-kit-u-boot.dtsi
b/arch/arm/dts/imx8mn-beacon-kit-u-boot.dtsi
index 69fd69c8d02..eb1dd8debba 100644
--- a/arch/arm/dts/imx8mn-beacon-kit-u-boot.dtsi
+++ b/arch/arm/dts/imx8mn-beacon-kit-u-boot.dtsi
@@ -132,6 +132,10 @@
u-boot,dm-spl;
};
+&pinctrl_wdog {
+ u-boot,dm-spl;
+};
+
&binman {
u-boot-spl-ddr {
filename = "u-boot-spl-ddr.bin";
diff --git a/board/beacon/imx8mn/spl.c b/board/beacon/imx8mn/spl.c
index 4563446db19..029f71bc995 100644
--- a/board/beacon/imx8mn/spl.c
+++ b/board/beacon/imx8mn/spl.c
@@ -68,27 +68,17 @@ int board_fit_config_name_match(const char *name)
}
#endif
-#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
#define PWM1_PAD_CTRL (PAD_CTL_FSEL2 | PAD_CTL_DSE6)
static iomux_v3_cfg_t const pwm_pads[] = {
IMX8MN_PAD_GPIO1_IO01__PWM1_OUT | MUX_PAD_CTRL(PWM1_PAD_CTRL),
};
-static iomux_v3_cfg_t const wdog_pads[] = {
- IMX8MN_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
-};
-
int board_early_init_f(void)
{
- struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
-
/* Claiming pwm pins prevents LCD flicker during startup*/
imx_iomux_v3_setup_multiple_pads(pwm_pads, ARRAY_SIZE(pwm_pads));
- imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
- set_wdog_reset(wdog);
-
init_uart_clk(1);
return 0;
--
2.36.0
[PATCH 08/17] imx: imx8mm-mx8menlo: drop unneeded watchdog settings
From: Peng Fan
pinctrl_wdog as u-boot,dm-spl already marked in imx8mm-verdin-u-boot.dtsi,
set_wdog_reset function could be handled by imx_watchdog.c driver.
Signed-off-by: Peng Fan
---
board/menlo/mx8menlo/mx8menlo.c | 12
1 file changed, 12 deletions(-)
diff --git a/board/menlo/mx8menlo/mx8menlo.c b/board/menlo/mx8menlo/mx8menlo.c
index 95ff95ad360..9d3708a3637 100644
--- a/board/menlo/mx8menlo/mx8menlo.c
+++ b/board/menlo/mx8menlo/mx8menlo.c
@@ -12,12 +12,6 @@
#include
#include
-#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
-
-static iomux_v3_cfg_t const wdog_pads[] = {
- IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
-};
-
#define SNVS_BASE_ADDR 0x3037
#define SNVS_LPSR 0x4c
#define SNVS_LPLVDR0x64
@@ -35,12 +29,6 @@ static void setup_snvs(void)
void board_early_init(void)
{
- struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
-
- imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
-
- set_wdog_reset(wdog);
-
init_uart_clk(1);
setup_snvs();
--
2.36.0
[PATCH 09/17] imx: imx8mm/n/p-venice: enable pinctrl_wdog in SPL
From: Peng Fan
Mark pinctrl_wdog as u-boot,dm-spl to clean up board code,
set_wdog_reset function could be handled by imx_watchdog.c driver.
Signed-off-by: Peng Fan
---
arch/arm/dts/imx8mm-venice-u-boot.dtsi | 4
arch/arm/dts/imx8mn-venice-u-boot.dtsi | 4
arch/arm/dts/imx8mp-venice-u-boot.dtsi | 4
board/gateworks/venice/spl.c | 30 --
4 files changed, 12 insertions(+), 30 deletions(-)
diff --git a/arch/arm/dts/imx8mm-venice-u-boot.dtsi
b/arch/arm/dts/imx8mm-venice-u-boot.dtsi
index c61c6de935f..68978a0413e 100644
--- a/arch/arm/dts/imx8mm-venice-u-boot.dtsi
+++ b/arch/arm/dts/imx8mm-venice-u-boot.dtsi
@@ -72,3 +72,7 @@
&wdog1 {
u-boot,dm-spl;
};
+
+&pinctrl_wdog {
+ u-boot,dm-spl;
+};
diff --git a/arch/arm/dts/imx8mn-venice-u-boot.dtsi
b/arch/arm/dts/imx8mn-venice-u-boot.dtsi
index 4f23da35676..35819553879 100644
--- a/arch/arm/dts/imx8mn-venice-u-boot.dtsi
+++ b/arch/arm/dts/imx8mn-venice-u-boot.dtsi
@@ -110,6 +110,10 @@
u-boot,dm-spl;
};
+&pinctrl_wdog {
+ u-boot,dm-spl;
+};
+
&binman {
u-boot-spl-ddr {
align = <4>;
diff --git a/arch/arm/dts/imx8mp-venice-u-boot.dtsi
b/arch/arm/dts/imx8mp-venice-u-boot.dtsi
index 37f3edc9817..96b9fa89cf4 100644
--- a/arch/arm/dts/imx8mp-venice-u-boot.dtsi
+++ b/arch/arm/dts/imx8mp-venice-u-boot.dtsi
@@ -72,3 +72,7 @@
&wdog1 {
u-boot,dm-spl;
};
+
+&pinctrl_wdog {
+ u-boot,dm-spl;
+};
diff --git a/board/gateworks/venice/spl.c b/board/gateworks/venice/spl.c
index af196e5b87c..4c0feb4381c 100644
--- a/board/gateworks/venice/spl.c
+++ b/board/gateworks/venice/spl.c
@@ -87,34 +87,6 @@ static void spl_dram_init(int size)
ddr_init(dram_timing);
}
-#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
-
-#ifdef CONFIG_IMX8MM
-static iomux_v3_cfg_t const wdog_pads[] = {
- IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
-};
-#elif CONFIG_IMX8MN
-static const iomux_v3_cfg_t wdog_pads[] = {
- IMX8MN_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
-};
-#elif CONFIG_IMX8MP
-static const iomux_v3_cfg_t wdog_pads[] = {
- MX8MP_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
-};
-
-#endif
-
-int board_early_init_f(void)
-{
- struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
-
- imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
-
- set_wdog_reset(wdog);
-
- return 0;
-}
-
/*
* Model specific PMIC adjustments necessary prior to DRAM init
*
@@ -254,8 +226,6 @@ void board_init_f(ulong dummy)
init_uart_clk(1);
- board_early_init_f();
-
timer_init();
/* Clear the BSS. */
--
2.36.0
[PATCH 07/17] imx: engicam-imx8mm: drop unused macro
From: Peng Fan
Drop unused WDOG macro
Signed-off-by: Peng Fan
---
board/engicam/imx8mm/spl.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/board/engicam/imx8mm/spl.c b/board/engicam/imx8mm/spl.c
index f75f2dc634c..1846134a492 100644
--- a/board/engicam/imx8mm/spl.c
+++ b/board/engicam/imx8mm/spl.c
@@ -54,8 +54,6 @@ int board_fit_config_name_match(const char *name)
}
#endif
-#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
-
int board_early_init_f(void)
{
return 0;
--
2.36.0
[PATCH 06/17] imx: imx8mm-data-modul-edm-sbc: enable pinctrl_wdog in SPL
From: Peng Fan
Add pinctrl_wdog.
Mark pinctrl_wdog as u-boot,dm-spl to clean up board code,
set_wdog_reset function could be handled by imx_watchdog.c driver.
Signed-off-by: Peng Fan
---
.../dts/imx8mm-data-modul-edm-sbc-u-boot.dtsi | 4
arch/arm/dts/imx8mm-data-modul-edm-sbc.dts | 9 +
board/data_modul/imx8mm_edm_sbc/spl.c | 17 -
3 files changed, 13 insertions(+), 17 deletions(-)
diff --git a/arch/arm/dts/imx8mm-data-modul-edm-sbc-u-boot.dtsi
b/arch/arm/dts/imx8mm-data-modul-edm-sbc-u-boot.dtsi
index 184c30ab4a7..32413e98118 100644
--- a/arch/arm/dts/imx8mm-data-modul-edm-sbc-u-boot.dtsi
+++ b/arch/arm/dts/imx8mm-data-modul-edm-sbc-u-boot.dtsi
@@ -114,3 +114,7 @@
&wdog1 {
u-boot,dm-spl;
};
+
+&pinctrl_wdog {
+ u-boot,dm-spl;
+};
diff --git a/arch/arm/dts/imx8mm-data-modul-edm-sbc.dts
b/arch/arm/dts/imx8mm-data-modul-edm-sbc.dts
index 154116d01c9..b82be21 100644
--- a/arch/arm/dts/imx8mm-data-modul-edm-sbc.dts
+++ b/arch/arm/dts/imx8mm-data-modul-edm-sbc.dts
@@ -512,6 +512,12 @@
>;
};
+ pinctrl_wdog: wdoggrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B0x166
+ >;
+ };
+
pinctrl_hog_feature: hog-feature-grp {
fsl,pins = <
/* GPIO4_IO27 */
@@ -992,5 +998,8 @@
};
&wdog1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wdog>;
+ fsl,ext-reset-output;
status = "okay";
};
diff --git a/board/data_modul/imx8mm_edm_sbc/spl.c
b/board/data_modul/imx8mm_edm_sbc/spl.c
index f5063eb8c19..5a40bf3d682 100644
--- a/board/data_modul/imx8mm_edm_sbc/spl.c
+++ b/board/data_modul/imx8mm_edm_sbc/spl.c
@@ -28,21 +28,6 @@
DECLARE_GLOBAL_DATA_PTR;
-#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
-
-static const iomux_v3_cfg_t wdog_pads[] = {
- IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
-};
-
-static void data_modul_imx8mm_edm_sbc_early_init_f(void)
-{
- struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
-
- imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
-
- set_wdog_reset(wdog);
-}
-
static int data_modul_imx8mm_edm_sbc_board_power_init(void)
{
struct udevice *dev;
@@ -139,8 +124,6 @@ void board_init_f(ulong dummy)
init_uart_clk(2);
- data_modul_imx8mm_edm_sbc_early_init_f();
-
/* Clear the BSS. */
memset(__bss_start, 0, __bss_end - __bss_start);
--
2.36.0
[PATCH 05/17] imx: imx8mm-cl-iot-gate: enable pinctrl_wdog in SPL
From: Peng Fan
Mark pinctrl_wdog as u-boot,dm-spl to clean up board code,
set_wdog_reset function could be handled by imx_watchdog.c driver.
Signed-off-by: Peng Fan
---
arch/arm/dts/imx8mm-cl-iot-gate-u-boot.dtsi | 4
board/compulab/imx8mm-cl-iot-gate/spl.c | 19 ---
2 files changed, 4 insertions(+), 19 deletions(-)
diff --git a/arch/arm/dts/imx8mm-cl-iot-gate-u-boot.dtsi
b/arch/arm/dts/imx8mm-cl-iot-gate-u-boot.dtsi
index 433b02cceee..a7044b63699 100644
--- a/arch/arm/dts/imx8mm-cl-iot-gate-u-boot.dtsi
+++ b/arch/arm/dts/imx8mm-cl-iot-gate-u-boot.dtsi
@@ -84,6 +84,10 @@
u-boot,dm-spl;
};
+&pinctrl_wdog {
+ u-boot,dm-spl;
+};
+
&uart3 {
u-boot,dm-spl;
};
diff --git a/board/compulab/imx8mm-cl-iot-gate/spl.c
b/board/compulab/imx8mm-cl-iot-gate/spl.c
index f183704c9d2..d2d20269ba0 100644
--- a/board/compulab/imx8mm-cl-iot-gate/spl.c
+++ b/board/compulab/imx8mm-cl-iot-gate/spl.c
@@ -83,23 +83,6 @@ int board_fit_config_name_match(const char *name)
}
#endif
-#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
-
-static iomux_v3_cfg_t const wdog_pads[] = {
- IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
-};
-
-int board_early_init_f(void)
-{
- struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
-
- imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
-
- set_wdog_reset(wdog);
-
- return 0;
-}
-
static int power_init_board(void)
{
struct udevice *dev;
@@ -141,8 +124,6 @@ void board_init_f(ulong dummy)
arch_cpu_init();
- board_early_init_f();
-
init_uart_clk(2);
timer_init();
--
2.36.0
[PATCH 04/17] imx: imx8mm_beacon: enable pinctrl_wdog in SPL
From: Peng Fan
Mark pinctrl_wdog as u-boot,dm-spl to clean up board code,
set_wdog_reset function could be handled by imx_watchdog.c driver.
Signed-off-by: Peng Fan
---
arch/arm/dts/imx8mm-beacon-kit-u-boot.dtsi | 4
board/beacon/imx8mm/spl.c | 19 ---
2 files changed, 4 insertions(+), 19 deletions(-)
diff --git a/arch/arm/dts/imx8mm-beacon-kit-u-boot.dtsi
b/arch/arm/dts/imx8mm-beacon-kit-u-boot.dtsi
index e33e10ac129..c94b4ffa4c3 100644
--- a/arch/arm/dts/imx8mm-beacon-kit-u-boot.dtsi
+++ b/arch/arm/dts/imx8mm-beacon-kit-u-boot.dtsi
@@ -73,6 +73,10 @@
u-boot,dm-spl;
};
+&pinctrl_wdog {
+ u-boot,dm-spl;
+};
+
&uart2 {
u-boot,dm-spl;
};
diff --git a/board/beacon/imx8mm/spl.c b/board/beacon/imx8mm/spl.c
index f92b4c3ed0a..a93cc938784 100644
--- a/board/beacon/imx8mm/spl.c
+++ b/board/beacon/imx8mm/spl.c
@@ -59,23 +59,6 @@ int board_fit_config_name_match(const char *name)
}
#endif
-#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
-
-static iomux_v3_cfg_t const wdog_pads[] = {
- IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
-};
-
-int board_early_init_f(void)
-{
- struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
-
- imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
-
- set_wdog_reset(wdog);
-
- return 0;
-}
-
static int power_init_board(void)
{
struct udevice *dev;
@@ -116,8 +99,6 @@ void board_init_f(ulong dummy)
init_uart_clk(1);
- board_early_init_f();
-
timer_init();
/* Clear the BSS. */
--
2.36.0
[PATCH 03/17] imx: imx8mp_evk: enable pinctrl_wdog in SPL
From: Peng Fan
Mark pinctrl_wdog as u-boot,dm-spl to clean up board code,
set_wdog_reset function could be handled by imx_watchdog.c driver.
Signed-off-by: Peng Fan
---
arch/arm/dts/imx8mp-evk-u-boot.dtsi | 4
board/freescale/imx8mp_evk/imx8mp_evk.c | 17 -
board/freescale/imx8mp_evk/spl.c| 2 --
configs/imx8mp_evk_defconfig| 1 -
4 files changed, 4 insertions(+), 20 deletions(-)
diff --git a/arch/arm/dts/imx8mp-evk-u-boot.dtsi
b/arch/arm/dts/imx8mp-evk-u-boot.dtsi
index 7aa908304aa..f43eb6238d0 100644
--- a/arch/arm/dts/imx8mp-evk-u-boot.dtsi
+++ b/arch/arm/dts/imx8mp-evk-u-boot.dtsi
@@ -43,6 +43,10 @@
u-boot,dm-spl;
};
+&pinctrl_wdog {
+ u-boot,dm-spl;
+};
+
&gpio1 {
u-boot,dm-spl;
};
diff --git a/board/freescale/imx8mp_evk/imx8mp_evk.c
b/board/freescale/imx8mp_evk/imx8mp_evk.c
index fb6c61c39e7..8971a827df3 100644
--- a/board/freescale/imx8mp_evk/imx8mp_evk.c
+++ b/board/freescale/imx8mp_evk/imx8mp_evk.c
@@ -20,23 +20,6 @@
DECLARE_GLOBAL_DATA_PTR;
-#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
-
-static iomux_v3_cfg_t const wdog_pads[] = {
- MX8MP_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
-};
-
-int board_early_init_f(void)
-{
- struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
-
- imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
-
- set_wdog_reset(wdog);
-
- return 0;
-}
-
static void setup_fec(void)
{
struct iomuxc_gpr_base_regs *gpr =
diff --git a/board/freescale/imx8mp_evk/spl.c b/board/freescale/imx8mp_evk/spl.c
index 503a752ae98..a2732148f24 100644
--- a/board/freescale/imx8mp_evk/spl.c
+++ b/board/freescale/imx8mp_evk/spl.c
@@ -134,8 +134,6 @@ void board_init_f(ulong dummy)
init_uart_clk(1);
- board_early_init_f();
-
ret = spl_early_init();
if (ret) {
debug("spl_init() failed: %d\n", ret);
diff --git a/configs/imx8mp_evk_defconfig b/configs/imx8mp_evk_defconfig
index 081f7e08f8e..c3ffed85998 100644
--- a/configs/imx8mp_evk_defconfig
+++ b/configs/imx8mp_evk_defconfig
@@ -27,7 +27,6 @@ CONFIG_SPL_LOAD_FIT=y
# CONFIG_USE_SPL_FIT_GENERATOR is not set
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_DEFAULT_FDT_FILE="imx8mp-evk.dtb"
-CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_LATE_INIT=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_BOOTROM_SUPPORT=y
--
2.36.0
[PATCH 01/17] imx: imx8mn_evk: enable pinctrl_wdog in SPL
From: Peng Fan
Mark pinctrl_wdog as u-boot,dm-spl to clean up board code,
set_wdog_reset function could be handled by imx_watchdog.c driver.
Signed-off-by: Peng Fan
---
arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi | 4
board/freescale/imx8mn_evk/spl.c | 19 ---
2 files changed, 4 insertions(+), 19 deletions(-)
diff --git a/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi
b/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi
index 6f70722586d..4d0ecb07d4f 100644
--- a/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi
+++ b/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi
@@ -80,6 +80,10 @@
u-boot,dm-spl;
};
+&pinctrl_wdog {
+ u-boot,dm-spl;
+};
+
&gpio1 {
u-boot,dm-spl;
};
diff --git a/board/freescale/imx8mn_evk/spl.c b/board/freescale/imx8mn_evk/spl.c
index 63f335be3b0..3d9aa56d2c0 100644
--- a/board/freescale/imx8mn_evk/spl.c
+++ b/board/freescale/imx8mn_evk/spl.c
@@ -115,23 +115,6 @@ int board_fit_config_name_match(const char *name)
}
#endif
-#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
-
-static iomux_v3_cfg_t const wdog_pads[] = {
- IMX8MN_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
-};
-
-int board_early_init_f(void)
-{
- struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
-
- imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
-
- set_wdog_reset(wdog);
-
- return 0;
-}
-
void board_init_f(ulong dummy)
{
int ret;
@@ -140,8 +123,6 @@ void board_init_f(ulong dummy)
init_uart_clk(1);
- board_early_init_f();
-
timer_init();
/* Clear the BSS. */
--
2.36.0
[PATCH 02/17] imx: imx8mm_evk: enable pinctrl_wdog in SPL
From: Peng Fan
Mark pinctrl_wdog as u-boot,dm-spl to clean up board code,
set_wdog_reset function could be handled by imx_watchdog.c driver.
Signed-off-by: Peng Fan
---
arch/arm/dts/imx8mm-evk-u-boot.dtsi | 4
board/freescale/imx8mm_evk/spl.c| 19 ---
2 files changed, 4 insertions(+), 19 deletions(-)
diff --git a/arch/arm/dts/imx8mm-evk-u-boot.dtsi
b/arch/arm/dts/imx8mm-evk-u-boot.dtsi
index 8861542ec58..e9fbf7b8021 100644
--- a/arch/arm/dts/imx8mm-evk-u-boot.dtsi
+++ b/arch/arm/dts/imx8mm-evk-u-boot.dtsi
@@ -121,6 +121,10 @@
u-boot,dm-spl;
};
+&pinctrl_wdog {
+ u-boot,dm-spl;
+};
+
&fec1 {
phy-reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
};
diff --git a/board/freescale/imx8mm_evk/spl.c b/board/freescale/imx8mm_evk/spl.c
index 7eeec6c485a..ae2fb73fc51 100644
--- a/board/freescale/imx8mm_evk/spl.c
+++ b/board/freescale/imx8mm_evk/spl.c
@@ -72,23 +72,6 @@ int board_fit_config_name_match(const char *name)
}
#endif
-#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
-
-static iomux_v3_cfg_t const wdog_pads[] = {
- IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
-};
-
-int board_early_init_f(void)
-{
- struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
-
- imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
-
- set_wdog_reset(wdog);
-
- return 0;
-}
-
static int power_init_board(void)
{
struct udevice *dev;
@@ -135,8 +118,6 @@ void board_init_f(ulong dummy)
init_uart_clk(1);
- board_early_init_f();
-
timer_init();
/* Clear the BSS. */
--
2.36.0
[PATCH 00/17] imx: imx8m: clean up wdog code
From: Peng Fan Enable pinctrl wdog to clean up board level code imx_watchdog.c already has function of set_wdog_reset, so after watchdog driver enabled, no need that. Note: I only have NXP EVK board, so please help test if possible. Based on: https://patchwork.ozlabs.org/project/uboot/cover/20220430124317.17382-1-peng@oss.nxp.com/ Peng Fan (17): imx: imx8mn_evk: enable pinctrl_wdog in SPL imx: imx8mm_evk: enable pinctrl_wdog in SPL imx: imx8mp_evk: enable pinctrl_wdog in SPL imx: imx8mm_beacon: enable pinctrl_wdog in SPL imx: imx8mm-cl-iot-gate: enable pinctrl_wdog in SPL imx: imx8mm-data-modul-edm-sbc: enable pinctrl_wdog in SPL imx: engicam-imx8mm: drop unused macro imx: imx8mm-mx8menlo: drop unneeded watchdog settings imx: imx8mm/n/p-venice: enable pinctrl_wdog in SPL imx: imx8mn-beacon: enable pinctrl_wdog in SPL imx: imx8mn_smm_s2: clean up board watchdog code imx: imx8mn_var_som: clean up board watchdog code imx: imx8mp_rsb7320a1: enable wdog driver model in SPL imx: imx8mn-kontron-n801x: enable pinctrl_wdog in SPL imx: phycore_imx8mm/p: clean up board watchdog code imx: verdin-imx8mm/p: cleanup board watchdog code imx: toradex/verdin-imx8mm/p: cleanup board watchdog code arch/arm/dts/imx8mm-beacon-kit-u-boot.dtsi| 4 +++ arch/arm/dts/imx8mm-cl-iot-gate-u-boot.dtsi | 4 +++ .../dts/imx8mm-data-modul-edm-sbc-u-boot.dtsi | 4 +++ arch/arm/dts/imx8mm-data-modul-edm-sbc.dts| 9 ++ arch/arm/dts/imx8mm-evk-u-boot.dtsi | 4 +++ arch/arm/dts/imx8mm-kontron-n801x-u-boot.dtsi | 4 +++ arch/arm/dts/imx8mm-venice-u-boot.dtsi| 4 +++ arch/arm/dts/imx8mn-beacon-kit-u-boot.dtsi| 4 +++ arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi | 4 +++ arch/arm/dts/imx8mn-venice-u-boot.dtsi| 4 +++ arch/arm/dts/imx8mp-evk-u-boot.dtsi | 4 +++ arch/arm/dts/imx8mp-rsb3720-a1-u-boot.dtsi| 8 + arch/arm/dts/imx8mp-venice-u-boot.dtsi| 4 +++ .../imx8mp_rsb3720a1/imx8mp_rsb3720a1.c | 12 board/beacon/imx8mm/spl.c | 19 board/beacon/imx8mn/spl.c | 10 --- board/bsh/imx8mn_smm_s2/spl.c | 11 --- board/compulab/imx8mm-cl-iot-gate/spl.c | 19 board/data_modul/imx8mm_edm_sbc/spl.c | 17 --- board/engicam/imx8mm/spl.c| 2 -- board/freescale/imx8mm_evk/spl.c | 19 board/freescale/imx8mn_evk/spl.c | 19 board/freescale/imx8mp_evk/imx8mp_evk.c | 17 --- board/freescale/imx8mp_evk/spl.c | 2 -- board/gateworks/venice/spl.c | 30 --- board/kontron/sl-mx8mm/spl.c | 18 --- board/menlo/mx8menlo/mx8menlo.c | 12 board/phytec/phycore_imx8mm/spl.c | 19 board/phytec/phycore_imx8mp/spl.c | 19 board/toradex/verdin-imx8mm/spl.c | 11 --- board/toradex/verdin-imx8mp/verdin-imx8mp.c | 11 --- board/variscite/imx8mn_var_som/spl.c | 11 --- configs/imx8mp_evk_defconfig | 1 - 33 files changed, 61 insertions(+), 279 deletions(-) -- 2.36.0
[PATCH 4/4] configs: imx8m: use common imx8m.h for i.MX8MQ
From: Peng Fan Some SPL definitions could be gerneralized, so use imx8m.h for iMX8MQ. Signed-off-by: Peng Fan --- include/configs/imx8m.h | 10 ++ include/configs/imx8mq_cm.h | 24 +--- include/configs/imx8mq_evk.h | 19 +-- include/configs/imx8mq_phanbell.h| 19 ++- include/configs/kontron_pitx_imx8m.h | 19 +-- include/configs/pico-imx8mq.h| 20 +--- 6 files changed, 16 insertions(+), 95 deletions(-) diff --git a/include/configs/imx8m.h b/include/configs/imx8m.h index b127d0fb847..dcf6c38a2ce 100644 --- a/include/configs/imx8m.h +++ b/include/configs/imx8m.h @@ -42,6 +42,16 @@ #define CONFIG_SYS_SPL_MALLOC_START0x4220 #define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K /* 512 KB */ +#elif defined(CONFIG_IMX8MQ) +/*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/ +#define CONFIG_SPL_STACK 0x187FF0 +#define CONFIG_SPL_BSS_START_ADDR 0x0018 +#define CONFIG_SPL_BSS_MAX_SIZE0x2000 /* 8 KB */ +#define CONFIG_SYS_SPL_MALLOC_START0x4220 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x8 /* 512 KB */ +#define CONFIG_SYS_SPL_PTE_RAM_BASE0x4158 +/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ +#define CONFIG_MALLOC_F_ADDR 0x182000 #endif #endif #endif diff --git a/include/configs/imx8mq_cm.h b/include/configs/imx8mq_cm.h index 34d64f7ae45..016737f0907 100644 --- a/include/configs/imx8mq_cm.h +++ b/include/configs/imx8mq_cm.h @@ -6,32 +6,10 @@ #ifndef __IMX8M_CM_H #define __IMX8M_CM_H -#include -#include -#include +#include #define CONFIG_SYS_BOOTM_LEN (32 * SZ_1M) -#define CONFIG_SPL_MAX_SIZE(124 * 1024) -#define CONFIG_SYS_MONITOR_LEN (512 * 1024) - -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SPL_STACK 0x187FF0 -#define CONFIG_SPL_BSS_START_ADDR 0x0018 -#define CONFIG_SPL_BSS_MAX_SIZE0x2000 /* 8 KB */ -#define CONFIG_SYS_SPL_MALLOC_START0x4220 -#define CONFIG_SYS_SPL_MALLOC_SIZE0x8 /* 512 KB */ -#define CONFIG_SYS_SPL_PTE_RAM_BASE0x4158 - -/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ -#define CONFIG_MALLOC_F_ADDR 0x182000 -/* For RAW image gives a error info not panic */ - -#endif - -/* ENET Config */ -/* ENET1 */ - #ifndef CONFIG_SPL_BUILD #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 0) \ diff --git a/include/configs/imx8mq_evk.h b/include/configs/imx8mq_evk.h index 98257e8ba81..29683480be1 100644 --- a/include/configs/imx8mq_evk.h +++ b/include/configs/imx8mq_evk.h @@ -6,28 +6,11 @@ #ifndef __IMX8M_EVK_H #define __IMX8M_EVK_H -#include -#include -#include +#include #define CONFIG_SYS_BOOTM_LEN (64 * SZ_1M) -#define CONFIG_SPL_MAX_SIZE(124 * 1024) -#define CONFIG_SYS_MONITOR_LEN (512 * 1024) - #ifdef CONFIG_SPL_BUILD -/*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/ -#define CONFIG_SPL_STACK 0x187FF0 -#define CONFIG_SPL_BSS_START_ADDR 0x0018 -#define CONFIG_SPL_BSS_MAX_SIZE0x2000 /* 8 KB */ -#define CONFIG_SYS_SPL_MALLOC_START0x4220 -#define CONFIG_SYS_SPL_MALLOC_SIZE0x8 /* 512 KB */ -#define CONFIG_SYS_SPL_PTE_RAM_BASE0x4158 - -/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ -#define CONFIG_MALLOC_F_ADDR 0x182000 -/* For RAW image gives a error info not panic */ - #define CONFIG_POWER_PFUZE100 #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 #endif diff --git a/include/configs/imx8mq_phanbell.h b/include/configs/imx8mq_phanbell.h index 19381b6b778..646b384f342 100644 --- a/include/configs/imx8mq_phanbell.h +++ b/include/configs/imx8mq_phanbell.h @@ -6,25 +6,10 @@ #ifndef __IMX8M_PHANBELL_H #define __IMX8M_PHANBELL_H -#include -#include +#include +#undef CONFIG_SPL_MAX_SIZE #define CONFIG_SPL_MAX_SIZE(172 * 1024) -#define CONFIG_SYS_MONITOR_LEN (512 * 1024) - -#ifdef CONFIG_SPL_BUILD -/*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/ -#define CONFIG_SPL_STACK 0x187FF0 -#define CONFIG_SPL_BSS_START_ADDR 0x0018 -#define CONFIG_SPL_BSS_MAX_SIZE0x2000 /* 8 KB */ -#define CONFIG_SYS_SPL_MALLOC_START0x4220 -#define CONFIG_SYS_SPL_MALLOC_SIZE0x8 /* 512 KB */ -#define CONFIG_SYS_SPL_PTE_RAM_BASE0x4158 - -/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ -#define CONFIG_MALLOC_F_ADDR 0x182000 -/* For RAW image gives a error info not panic */ -#endif /* ENET Config */ /* ENET1 */ diff --git a/include/configs/kontron_pitx_imx8m.h b/include/configs/kontron_pitx_imx8m.h index d519935b064..1b8b4671bc5 100644 --- a/include/configs/kontron_pitx_imx8m.h +++ b/include/configs/kontron_pitx_imx8m.h @@ -3,33 +3,16 @@ #ifndef __KONTRON_PITX_IMX8M_H #define __KONTRON_PITX_IMX8M_H -#include -#include -#include +#include #define CONFIG_SYS_BOOTM_LEN (32 * SZ
[PATCH 3/4] configs: imx8m: use common imx8m.h for i.MX8MP
From: Peng Fan Some SPL definitions could be gerneralized, so use imx8m.h for iMX8MP. Signed-off-by: Peng Fan --- include/configs/imx8m.h | 8 include/configs/imx8mp_evk.h | 17 + include/configs/imx8mp_rsb3720.h | 16 +--- include/configs/imx8mp_venice.h | 18 +- include/configs/phycore_imx8mp.h | 16 +--- include/configs/verdin-imx8mp.h | 16 +--- 6 files changed, 13 insertions(+), 78 deletions(-) diff --git a/include/configs/imx8m.h b/include/configs/imx8m.h index 30dc01221e6..b127d0fb847 100644 --- a/include/configs/imx8m.h +++ b/include/configs/imx8m.h @@ -34,6 +34,14 @@ #define CONFIG_SYS_SPL_MALLOC_START0x4220 #define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K /* 512 KB */ +#elif defined(CONFIG_IMX8MP) +/*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/ +#define CONFIG_SPL_STACK 0x96 +#define CONFIG_SPL_BSS_START_ADDR 0x0098FC00 +#define CONFIG_SPL_BSS_MAX_SIZE0x400 /* 1 KB */ +#define CONFIG_SYS_SPL_MALLOC_START0x4220 +#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K /* 512 KB */ + #endif #endif #endif diff --git a/include/configs/imx8mp_evk.h b/include/configs/imx8mp_evk.h index 55691821f90..60c2d9ee4e4 100644 --- a/include/configs/imx8mp_evk.h +++ b/include/configs/imx8mp_evk.h @@ -6,27 +6,12 @@ #ifndef __IMX8MP_EVK_H #define __IMX8MP_EVK_H -#include -#include -#include +#include #define CONFIG_SYS_BOOTM_LEN (32 * SZ_1M) -#define CONFIG_SPL_MAX_SIZE(152 * 1024) -#define CONFIG_SYS_MONITOR_LEN (512 * 1024) -#define CONFIG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) - #ifdef CONFIG_SPL_BUILD -/*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/ -#define CONFIG_SPL_STACK 0x96 -#define CONFIG_SPL_BSS_START_ADDR 0x0098FC00 -#define CONFIG_SPL_BSS_MAX_SIZE0x400 /* 1 KB */ -#define CONFIG_SYS_SPL_MALLOC_START0x4220 -#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K /* 512 KB */ - - #define CONFIG_POWER_PCA9450 - #endif #if defined(CONFIG_CMD_NET) diff --git a/include/configs/imx8mp_rsb3720.h b/include/configs/imx8mp_rsb3720.h index 7c2babbb0ae..008439915d8 100644 --- a/include/configs/imx8mp_rsb3720.h +++ b/include/configs/imx8mp_rsb3720.h @@ -7,17 +7,11 @@ #ifndef __IMX8MP_RSB3720_H #define __IMX8MP_RSB3720_H -#include -#include -#include +#include #include #define CONFIG_SYS_BOOTM_LEN (32 * SZ_1M) -#define CONFIG_SPL_MAX_SIZE(152 * 1024) -#define CONFIG_SYS_MONITOR_LEN (512 * 1024) -#define CONFIG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) - /* GUIDs for capsule updatable firmware images */ #define IMX8MP_RSB3720A1_4G_FIT_IMAGE_GUID \ EFI_GUID(0xb1251e89, 0x384a, 0x4635, 0xa8, 0x06, \ @@ -28,18 +22,10 @@ 0x5f, 0xd3, 0x6b, 0x9b, 0xe5, 0xb9) #ifdef CONFIG_SPL_BUILD -#define CONFIG_SPL_STACK 0x96 -#define CONFIG_SPL_BSS_START_ADDR 0x0098FC00 -#define CONFIG_SPL_BSS_MAX_SIZE0x400 /* 1 KB */ -#define CONFIG_SYS_SPL_MALLOC_START0x4220 -#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K /* 512 KB */ - #define CONFIG_MALLOC_F_ADDR 0x184000 /* malloc f used before \ * GD_FLG_FULL_MALLOC_INIT \ * set \ */ - - #if defined(CONFIG_NAND_BOOT) #define CONFIG_SPL_NAND_MXS #endif diff --git a/include/configs/imx8mp_venice.h b/include/configs/imx8mp_venice.h index 161f2e8d366..0697a48b7ea 100644 --- a/include/configs/imx8mp_venice.h +++ b/include/configs/imx8mp_venice.h @@ -6,23 +6,7 @@ #ifndef __IMX8MP_VENICE_H #define __IMX8MP_VENICE_H -#include -#include - -#define CONFIG_SPL_MAX_SIZE(152 * 1024) -#define CONFIG_SYS_MONITOR_LEN SZ_512K -#define CONFIG_SYS_UBOOT_BASE \ - (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) - -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SPL_STACK 0x96 -#define CONFIG_SPL_BSS_START_ADDR 0x0098FC00 -#define CONFIG_SPL_BSS_MAX_SIZE0x400 /* 1 KB */ -#define CONFIG_SYS_SPL_MALLOC_START0x4220 -#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K /* 512 KB */ - -/* For RAW image gives a error info not panic */ -#endif +#include #define MEM_LAYOUT_ENV_SETTINGS \ "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ diff --git a/include/configs/phycore_imx8mp.h b/include/configs/phycore_imx8mp.h index 95d70bb92d1..eaa91f66bfd 100644 --- a/include/configs/phycore_imx8mp.h +++ b/include/configs/phycore_imx8mp.h @@ -7,26 +7,12 @@ #ifndef __PHYCORE_IMX8MP_H #define __PHYCORE_IMX8MP_H -#include -#include +#include #define CONFIG_SYS_BOOTM_LEN SZ_64M -#define CONFIG_SPL_MAX_SIZE
[PATCH 2/4] configs: imx8m: use common imx8m.h for i.MX8MN
From: Peng Fan Some SPL definitions could be gerneralized, so use imx8m.h for iMX8MN. Signed-off-by: Peng Fan --- include/configs/imx8m.h| 10 ++ include/configs/imx8mn_bsh_smm_s2_common.h | 17 + include/configs/imx8mn_evk.h | 20 +--- include/configs/imx8mn_var_som.h | 15 +-- include/configs/imx8mn_venice.h| 18 +- 5 files changed, 14 insertions(+), 66 deletions(-) diff --git a/include/configs/imx8m.h b/include/configs/imx8m.h index 3d4ea834bd0..30dc01221e6 100644 --- a/include/configs/imx8m.h +++ b/include/configs/imx8m.h @@ -16,6 +16,8 @@ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) #ifdef CONFIG_SPL_BUILD + +#ifdef CONFIG_IMX8MM #define CONFIG_SPL_STACK 0x92 #define CONFIG_SPL_BSS_START_ADDR 0x91 #define CONFIG_SPL_BSS_MAX_SIZESZ_8K /* 8 KB */ @@ -25,5 +27,13 @@ /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ #define CONFIG_MALLOC_F_ADDR 0x93 +#elif defined(CONFIG_IMX8MN) +#define CONFIG_SPL_STACK 0x98 +#define CONFIG_SPL_BSS_START_ADDR 0x95 +#define CONFIG_SPL_BSS_MAX_SIZESZ_8K /* 8 KB */ +#define CONFIG_SYS_SPL_MALLOC_START0x4220 +#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K /* 512 KB */ + +#endif #endif #endif diff --git a/include/configs/imx8mn_bsh_smm_s2_common.h b/include/configs/imx8mn_bsh_smm_s2_common.h index 57be38d9433..eb210dc597b 100644 --- a/include/configs/imx8mn_bsh_smm_s2_common.h +++ b/include/configs/imx8mn_bsh_smm_s2_common.h @@ -6,25 +6,10 @@ #ifndef __IMX8MN_BSH_SMM_S2_COMMON_H #define __IMX8MN_BSH_SMM_S2_COMMON_H -#include -#include -#include +#include #define CONFIG_SYS_BOOTM_LEN (32 * SZ_1M) -#define CONFIG_SPL_MAX_SIZE(148 * SZ_1K) -#define CONFIG_SYS_MONITOR_LEN SZ_512K -#define CONFIG_SYS_UBOOT_BASE \ - (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) - -#define CONFIG_SPL_STACK 0x98 -#define CONFIG_SPL_BSS_START_ADDR 0x95 -#define CONFIG_SPL_BSS_MAX_SIZESZ_8K -#define CONFIG_SYS_SPL_MALLOC_START0x4220 -#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K - - - #define MEM_LAYOUT_ENV_SETTINGS \ "scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ diff --git a/include/configs/imx8mn_evk.h b/include/configs/imx8mn_evk.h index c0e9b0e9872..6e21192ea03 100644 --- a/include/configs/imx8mn_evk.h +++ b/include/configs/imx8mn_evk.h @@ -6,28 +6,10 @@ #ifndef __IMX8MN_EVK_H #define __IMX8MN_EVK_H -#include -#include -#include +#include #define CONFIG_SYS_BOOTM_LEN (32 * SZ_1M) -#define CONFIG_SPL_MAX_SIZE(148 * 1024) -#define CONFIG_SYS_MONITOR_LEN SZ_512K -#define CONFIG_SYS_UBOOT_BASE \ - (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) - -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SPL_STACK 0x98 -#define CONFIG_SPL_BSS_START_ADDR 0x95 -#define CONFIG_SPL_BSS_MAX_SIZESZ_8K /* 8 KB */ -#define CONFIG_SYS_SPL_MALLOC_START0x4220 -#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K /* 512 KB */ - -/* For RAW image gives a error info not panic */ - -#endif - #ifndef CONFIG_SPL_BUILD #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 1) \ diff --git a/include/configs/imx8mn_var_som.h b/include/configs/imx8mn_var_som.h index 6ce60b0d704..fc9c4ca4530 100644 --- a/include/configs/imx8mn_var_som.h +++ b/include/configs/imx8mn_var_som.h @@ -6,23 +6,10 @@ #ifndef __IMX8MN_VAR_SOM_H #define __IMX8MN_VAR_SOM_H -#include -#include -#include +#include #define CONFIG_SYS_BOOTM_LEN (32 * SZ_1M) -#define CONFIG_SPL_MAX_SIZE(148 * SZ_1K) -#define CONFIG_SYS_MONITOR_LEN SZ_512K -#define CONFIG_SYS_UBOOT_BASE \ - (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) - -#define CONFIG_SPL_STACK 0x98 -#define CONFIG_SPL_BSS_START_ADDR 0x95 -#define CONFIG_SPL_BSS_MAX_SIZESZ_8K -#define CONFIG_SYS_SPL_MALLOC_START0x4220 -#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K - #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 1) \ func(MMC, mmc, 2) \ diff --git a/include/configs/imx8mn_venice.h b/include/configs/imx8mn_venice.h index 6f36440b4f2..0bd407c8e8d 100644 --- a/include/configs/imx8mn_venice.h +++ b/include/configs/imx8mn_venice.h @@ -6,23 +6,7 @@ #ifndef __IMX8MM_VENICE_H #define __IMX8MM_VENICE_H -#include -#include - -#define CONFIG_SPL_MAX_SIZE(148 * 1024) -#define CONFIG_SYS_MONITOR_LEN SZ_512K -#define CONFIG_SYS_UBOOT_BASE \ - (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) - -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SPL_STACK
[PATCH 1/4] configs: imx8m: use common imx8m.h for i.MX8MM
From: Peng Fan Some SPL definitions could be gerneralized, so use imx8m.h for that. i.MX8MN/Q/P will follow up. Signed-off-by: Peng Fan --- include/configs/imx8m.h | 29 + include/configs/imx8mm-cl-iot-gate.h| 17 ++-- include/configs/imx8mm_beacon.h | 21 +-- include/configs/imx8mm_data_modul_edm_sbc.h | 15 +++ include/configs/imx8mm_evk.h| 21 +-- include/configs/imx8mm_icore_mx8mm.h| 20 +- include/configs/imx8mm_venice.h | 18 ++--- include/configs/kontron-sl-mx8mm.h | 14 +- include/configs/phycore_imx8mm.h| 20 +- include/configs/verdin-imx8mm.h | 20 +- 10 files changed, 42 insertions(+), 153 deletions(-) create mode 100644 include/configs/imx8m.h diff --git a/include/configs/imx8m.h b/include/configs/imx8m.h new file mode 100644 index 000..3d4ea834bd0 --- /dev/null +++ b/include/configs/imx8m.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2022 NXP + */ + +#ifndef __IMX8MM_H +#define __IMX8MM_H + +#include +#include +#include + +#define CONFIG_SPL_MAX_SIZE(148 * 1024) +#define CONFIG_SYS_MONITOR_LEN SZ_512K +#define CONFIG_SYS_UBOOT_BASE \ + (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SPL_STACK 0x92 +#define CONFIG_SPL_BSS_START_ADDR 0x91 +#define CONFIG_SPL_BSS_MAX_SIZESZ_8K /* 8 KB */ +#define CONFIG_SYS_SPL_MALLOC_START0x4220 +#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K /* 512 KB */ + +/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ +#define CONFIG_MALLOC_F_ADDR 0x93 + +#endif +#endif diff --git a/include/configs/imx8mm-cl-iot-gate.h b/include/configs/imx8mm-cl-iot-gate.h index e6c220bf0a8..80074a1a2ac 100644 --- a/include/configs/imx8mm-cl-iot-gate.h +++ b/include/configs/imx8mm-cl-iot-gate.h @@ -6,28 +6,15 @@ #ifndef __IMX8MM_CL_IOT_GATE_H #define __IMX8MM_CL_IOT_GATE_H -#include -#include -#include +#include #include #define CONFIG_SYS_BOOTM_LEN (32 * SZ_1M) -#define CONFIG_SPL_MAX_SIZE(148 * 1024) -#define CONFIG_SYS_MONITOR_LEN SZ_512K -#define CONFIG_SYS_UBOOT_BASE \ - (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) #ifdef CONFIG_SPL_BUILD -#define CONFIG_SPL_STACK 0x92 -#define CONFIG_SPL_BSS_START_ADDR 0x91 -#define CONFIG_SPL_BSS_MAX_SIZESZ_8K /* 8 KB */ -#define CONFIG_SYS_SPL_MALLOC_START0x4220 -#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K /* 512 KB */ - +#undef CONFIG_MALLOC_F_ADDR /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ #define CONFIG_MALLOC_F_ADDR 0x912000 -/* For RAW image gives a error info not panic */ - #endif /* GUIDs for capsule updatable firmware images */ diff --git a/include/configs/imx8mm_beacon.h b/include/configs/imx8mm_beacon.h index a9ca13a9da4..c73188a16f2 100644 --- a/include/configs/imx8mm_beacon.h +++ b/include/configs/imx8mm_beacon.h @@ -6,26 +6,7 @@ #ifndef __IMX8MM_BEACON_H #define __IMX8MM_BEACON_H -#include -#include - -#define CONFIG_SPL_MAX_SIZE(148 * 1024) -#define CONFIG_SYS_MONITOR_LEN SZ_512K -#define CONFIG_SYS_UBOOT_BASE \ - (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) - -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SPL_STACK 0x92 -#define CONFIG_SPL_BSS_START_ADDR 0x91 -#define CONFIG_SPL_BSS_MAX_SIZESZ_8K /* 8 KB */ -#define CONFIG_SYS_SPL_MALLOC_START0x4220 -#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K /* 512 KB */ - -/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ -#define CONFIG_MALLOC_F_ADDR 0x93 -/* For RAW image gives a error info not panic */ - -#endif +#include /* Initial environment variables */ #define CONFIG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/imx8mm_data_modul_edm_sbc.h b/include/configs/imx8mm_data_modul_edm_sbc.h index b5c445df9ce..48a13dbc7f4 100644 --- a/include/configs/imx8mm_data_modul_edm_sbc.h +++ b/include/configs/imx8mm_data_modul_edm_sbc.h @@ -6,26 +6,17 @@ #ifndef __IMX8MM_DATA_MODUL_EDM_SBC_H #define __IMX8MM_DATA_MODUL_EDM_SBC_H -#include -#include -#include +#include #define CONFIG_SYS_BOOTM_LEN SZ_128M #define CONFIG_SPL_MAX_SIZE(148 * 1024) +#undef CONFIG_SYS_MONITOR_LEN #define CONFIG_SYS_MONITOR_LEN SZ_1M -#define CONFIG_SPL_STACK 0x92 #ifdef CONFIG_SPL_BUILD -#define CONFIG_SPL_BSS_START_ADDR 0x91 -#define CONFIG_SPL_BSS_MAX_SIZESZ_8K /* 8 kiB */ -#define CONFIG_SYS_SPL_MALLOC_START0x4220 +#undef CONFIG_SYS_SPL_MALLOC_SIZE #define CONFIG_SYS_SPL_MALLOC_SIZE SZ_16M /* 16 MiB */ - -#define CONFIG_M
Re: [PATCH 04/12] cmd: tlv_eeprom: convert functions used by command to api functions
Hi Josua,
On 03.05.22 09:17, Josua Mayer wrote:
Am 03.05.22 um 09:16 schrieb Stefan Roese:
On 02.05.22 16:18, Josua Mayer wrote:
- prog_eeprom: write_tlvinfo_tlv_eeprom
- update_crc: tlvinfo_update_crc
- is_valid_tlv: is_valid_tlvinfo_entry
- is_checksum_valid: tlvinfo_check_crc
So while creating a new API it makes sense to prepend the function
names identical IMHO to not "pollute" the namespace. Something like
- tlv_is_valid_entry
- tlv_check_crc
...
Just examples, you get the idea.
Yes. The hard part in this particular implementation is that the naming
is not consistent.
The most sense I could make is that prefix tlvinfo indicates all tlv
data, i.e. working with the whole structure, while tlvinfo_tlv indicates
working with one data entry. Further write, read and is_ are currently
prefixed in the header, but for previously static functions in the C
file it was put in the middle ...
I found it quite difficult to prepare for splitting off a library in a
way that preserves history, i.e. diffs should still be readable for
spotting mistakes.
Yes, a decent history would be welcome. But still, when going global
here with a new API this should be consistant.
I was considering to at the very end do a mass-rename and come up with
better naming, something like
tlv_{set,get}_{blob,string,mac}
tlv_find_entry
tlv_{read,write}_eeprom
But this is pending a refactoring and extension of the tlv parsing code
in board/solidrun/common/tlv_data.*, to figure out what is required or
useful.
So your plan is to this:
a) Get this patchset included
b) Use it in board specific code, e.g. solidrun
c) Do the mass-rename
Is this correct? If yes, why is it better to do the renaming at the end?
Thanks,
Stefan
Thanks,
Stefan
Signed-off-by: Josua Mayer
---
cmd/tlv_eeprom.c | 56 +++
include/tlv_eeprom.h | 57
2 files changed, 76 insertions(+), 37 deletions(-)
diff --git a/cmd/tlv_eeprom.c b/cmd/tlv_eeprom.c
index 00c5b5f840..1b4f2537f6 100644
--- a/cmd/tlv_eeprom.c
+++ b/cmd/tlv_eeprom.c
@@ -28,13 +28,9 @@ DECLARE_GLOBAL_DATA_PTR;
#define MAX_TLV_DEVICES 2
/* File scope function prototypes */
-static bool is_checksum_valid(u8 *eeprom);
static int read_eeprom(int devnum, u8 *eeprom);
static void show_eeprom(int devnum, u8 *eeprom);
static void decode_tlv(struct tlvinfo_tlv *tlv);
-static void update_crc(u8 *eeprom);
-static int prog_eeprom(int devnum, u8 *eeprom);
-static bool tlvinfo_find_tlv(u8 *eeprom, u8 tcode, int *eeprom_index);
static bool tlvinfo_delete_tlv(u8 *eeprom, u8 code);
static bool tlvinfo_add_tlv(u8 *eeprom, int tcode, char *strval);
static int set_mac(char *buf, const char *string);
@@ -58,18 +54,6 @@ static inline bool is_digit(char c)
return (c >= '0' && c <= '9');
}
-/**
- * is_valid_tlv
- *
- * Perform basic sanity checks on a TLV field. The TLV is pointed to
- * by the parameter provided.
- * 1. The type code is not reserved (0x00 or 0xFF)
- */
-static inline bool is_valid_tlv(struct tlvinfo_tlv *tlv)
-{
- return((tlv->type != 0x00) && (tlv->type != 0xFF));
-}
-
/**
* is_hex
*
@@ -83,14 +67,12 @@ static inline u8 is_hex(char p)
}
/**
- * is_checksum_valid
- *
* Validate the checksum in the provided TlvInfo EEPROM data. First,
* verify that the TlvInfo header is valid, then make sure the last
* TLV is a CRC-32 TLV. Then calculate the CRC over the EEPROM data
* and compare it to the value stored in the EEPROM CRC-32 TLV.
*/
-static bool is_checksum_valid(u8 *eeprom)
+bool tlvinfo_check_crc(u8 *eeprom)
{
struct tlvinfo_header *eeprom_hdr = to_header(eeprom);
struct tlvinfo_tlv *eeprom_crc;
@@ -137,11 +119,11 @@ static int read_eeprom(int devnum, u8 *eeprom)
// If the contents are invalid, start over with default contents
if (!is_valid_tlvinfo_header(eeprom_hdr) ||
- !is_checksum_valid(eeprom)) {
+ !tlvinfo_check_crc(eeprom)) {
strcpy(eeprom_hdr->signature, TLV_INFO_ID_STRING);
eeprom_hdr->version = TLV_INFO_VERSION;
eeprom_hdr->totallen = cpu_to_be16(0);
- update_crc(eeprom);
+ tlvinfo_update_crc(eeprom);
}
#ifdef DEBUG
@@ -183,7 +165,7 @@ static void show_eeprom(int devnum, u8 *eeprom)
tlv_end = HDR_SIZE + be16_to_cpu(eeprom_hdr->totallen);
while (curr_tlv < tlv_end) {
eeprom_tlv = to_entry(&eeprom[curr_tlv]);
- if (!is_valid_tlv(eeprom_tlv)) {
+ if (!is_valid_tlvinfo_entry(eeprom_tlv)) {
printf("Invalid TLV field starting at EEPROM offset %d\n",
curr_tlv);
return;
@@ -193,7 +175,7 @@ static void show_eeprom(int devnum, u8 *eeprom)
}
printf("Checksum is %s.\n",
- is_checksum_valid(eeprom) ? "valid" : "invalid");
+ tlvinfo_check_crc(eeprom) ? "valid" : "invalid");
#ifdef DEBUG
printf("EEPROM
[PATCH v3] imx: imx8qm: cgtqmx8: switch to binman
Switch to use binman to pack images
Signed-off-by: Oliver Graute
Reviewed-by: Fabio Estevam
Reviewed-by: Simon Glass
---
Changes for v3
-added Reviewed-by
-rebased on master
arch/arm/dts/imx8qm-cgtqmx8.dts | 1 +
arch/arm/mach-imx/imx8/Kconfig | 1 +
board/congatec/cgtqmx8/imximage.cfg | 4 ++--
configs/cgtqmx8_defconfig | 2 +-
doc/board/congatec/cgtqmx8.rst | 3 +--
5 files changed, 6 insertions(+), 5 deletions(-)
diff --git a/arch/arm/dts/imx8qm-cgtqmx8.dts b/arch/arm/dts/imx8qm-cgtqmx8.dts
index 555c357f6f..919d00644f 100644
--- a/arch/arm/dts/imx8qm-cgtqmx8.dts
+++ b/arch/arm/dts/imx8qm-cgtqmx8.dts
@@ -12,6 +12,7 @@
/memreserve/ 0x8000 0x0002;
#include "fsl-imx8qm.dtsi"
+#include "imx8qm-u-boot.dtsi"
/ {
model = "Congatec QMX8 Qseven series";
diff --git a/arch/arm/mach-imx/imx8/Kconfig b/arch/arm/mach-imx/imx8/Kconfig
index 4414cbc213..3094524460 100644
--- a/arch/arm/mach-imx/imx8/Kconfig
+++ b/arch/arm/mach-imx/imx8/Kconfig
@@ -74,6 +74,7 @@ config TARGET_IMX8QM_MEK
config TARGET_CONGA_QMX8
bool "Support congatec conga-QMX8 board"
+ select BINMAN
select BOARD_LATE_INIT
select SUPPORT_SPL
select IMX8QM
diff --git a/board/congatec/cgtqmx8/imximage.cfg
b/board/congatec/cgtqmx8/imximage.cfg
index 5ecde0c530..43035088e3 100644
--- a/board/congatec/cgtqmx8/imximage.cfg
+++ b/board/congatec/cgtqmx8/imximage.cfg
@@ -4,8 +4,8 @@
*/
-/* Boot from SD, sector size 0x400 */
-BOOT_FROM SD 0x400
+BOOT_FROM sd
+
/* SoC type IMX8QM */
SOC_TYPE IMX8QM
/* Append seco container image */
diff --git a/configs/cgtqmx8_defconfig b/configs/cgtqmx8_defconfig
index 2cf882f826..fb334bc4a4 100644
--- a/configs/cgtqmx8_defconfig
+++ b/configs/cgtqmx8_defconfig
@@ -21,7 +21,7 @@ CONFIG_SYS_LOAD_ADDR=0x8028
CONFIG_REMAKE_ELF=y
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT=y
-CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh"
+# CONFIG_USE_SPL_FIT_GENERATOR is not set
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTCOMMAND=y
diff --git a/doc/board/congatec/cgtqmx8.rst b/doc/board/congatec/cgtqmx8.rst
index bccdef2f16..16711a844d 100644
--- a/doc/board/congatec/cgtqmx8.rst
+++ b/doc/board/congatec/cgtqmx8.rst
@@ -57,8 +57,7 @@ Build U-Boot
$ export ATF_LOAD_ADDR=0x8000
$ export BL33_LOAD_ADDR=0x8002
$ make cgtqmx8_defconfig
- $ make u-boot.bin
- $ make flash.bin
+ $ make
Flash the binary into the SD card
-
--
2.17.1
Re: [RFC] Data structure for information handoff between firmware boot stages
Hi Jose, On Tue, 3 May 2022 at 02:26, Jose Marinho wrote: > > Hi Simon, > > Thank you for reviewing the draft proposal! > > Would you be able to share your review comments on the PDF? > Currently the document is not in a markup form and is yet to be hosted in a > repository. That's the intent for the long term. Yes it looks like I can do that, so will share with you when done. Regards, Simon > > Cheers, > Jose > > > -Original Message- > > From: Simon Glass > > Sent: 03 May 2022 08:59 > > To: Jose Marinho > > Cc: u-boot@lists.denx.de; Heinrich Schuchardt ; Ilias > > Apalodimas ; Tom Rini ; > > Samer El-Haj-Mahmoud ; Manish Pandey2 > > ; nd > > Subject: Re: [RFC] Data structure for information handoff between firmware > > boot stages > > > > Hi Jose, > > > > On Thu, 7 Apr 2022 at 13:23, Jose Marinho wrote: > > > > > > Hi All, > > > > > > The topic of information handoff between TF-A’s BL31 and BL33 (e.g. U-boot > > proper, EDK2) was discussed last year in the TF-A and U-boot mailing lists > > [1], > > [2]. > > > > > > Examples of information to be handed off between firmware stages are the > > TPM log, HOB nodes, etc. > > > Having a standard data structure which is usable/supported by every > > community contributes to code reuse and leads to simpler codebase > > maintenance. > > > > > > Some already existing data structures, such as the UEFI HOB list [3], and > > > the > > Bloblist from U-boot, were proposed to be employed for the handoffs. > > > There are pros and cons with both HOBs and Bloblist. > > > The discussion settled with a consensus that a data structure ought to be > > defined which encapsulates the best traits of HOBs and Bloblist. > > > > > > Properties that the data structure should have: > > > - node types identified by an integer, > > > - easily relocatable, > > > > > > - straightforward to append new nodes, > > > - easy to read and append to from resource constrained environments. > > > > > > The data structure should be suitable to pass information between > > > different > > firmware stages, such as: > > > U-boot SPL -> BL31 -> U-boot > > > BL1 -> BL2 -> BL31 -> U-boot > > > > > > As requested in the ML, an initial proposal was drafted [4]. > > > The document [4] is an initial proposal (at an alpha stage). > > > The document [4] is being circulated for the purpose of gathering initial > > feedback. > > > This proposal is closely aligned with an ongoing effort in the u-boot > > > mailing > > list [5]. > > > The proposal defines 1) a set of standard nodes and 2) the registers used > > > at > > the handoff boundary. > > > > > > Standard nodes: > > > - fdt node: HW description fdt, > > > - HOB node, > > > - ACPI table node: the main use-case for this node is to carry the TPM > > > log. > > > > > > The document [4] accommodates an OEM range, which enables IMPDEF > > nodes to be caried in the handoff list. > > > By definition, the nodes in the OEM range are not standard and can be > > defined per-platform. > > > > > > Note: the document [4] encapsulates the standard node definition as that > > > is > > the simplest approach for feedback gathering. > > > Once there is sufficient consensus around the proposal, the standard node > > definitions should be moved to a project independent repository. The > > repository location is TBD. > > > The list of standard nodes is expected to grow with community > > > contribution. > > > > Thank you for the document. Is there a way to comment on it or should I just > > send you my hand-written markup? > > > > Regards, > > Simon > > > > > > > > Kind Regards, > > > Jose > > > > > > > > > > > > [1] > > > https://lists.trustedfirmware.org/archives/list/tf-a@lists.trustedfirm > > > ware.org/message/LUIUOVGUMVWID5RUMTYA463KGIU2EHIU/ > > > > > > [2] > > > https://lore.kernel.org/u-boot/CAODwPW_FwFN1E84cV1+nC1aiahiwOL- > > TV=mP_6 > > > o8h0y9+pc...@mail.gmail.com/ > > > > > > [3] https://uefi.org/sites/default/files/resources/PI_Spec_1_6.pdf > > > > > > [4] https://developer.arm.com/documentation/den0135/a > > > [5] > > > https://lore.kernel.org/u-boot/20220113022625.413990-1-...@chromium.or > > > g/ > > > > > >
[PATCH] Convert CONFIG_MTD_CONCAT to Kconfig
This converts the following to Kconfig: CONFIG_MTD_CONCAT Signed-off-by: Chris Packham --- This touches octeontx_common.h but only to remove a line that is already commented out. Other than that etamin was the only board that had this enabled. configs/etamin_defconfig | 1 + drivers/mtd/Kconfig | 8 include/configs/etamin.h | 1 - include/configs/octeontx_common.h | 1 - scripts/config_whitelist.txt | 1 - 5 files changed, 9 insertions(+), 3 deletions(-) diff --git a/configs/etamin_defconfig b/configs/etamin_defconfig index ba7a0665dedb..34b9fff5ded2 100644 --- a/configs/etamin_defconfig +++ b/configs/etamin_defconfig @@ -87,6 +87,7 @@ CONFIG_SPL_SYS_I2C_LEGACY=y # CONFIG_SPL_DM_MMC is not set CONFIG_MMC_OMAP_HS=y CONFIG_MTD=y +CONFIG_MTD_CONCAT=y CONFIG_MTD_RAW_NAND=y CONFIG_NAND_OMAP_ECCSCHEME_BCH16_CODE_HW=y CONFIG_SYS_NAND_BLOCK_SIZE=0x8 diff --git a/drivers/mtd/Kconfig b/drivers/mtd/Kconfig index 588ebe9119b9..4088267dd111 100644 --- a/drivers/mtd/Kconfig +++ b/drivers/mtd/Kconfig @@ -22,6 +22,14 @@ config MTD_NOR_FLASH help Enable support for parallel NOR flash. +config MTD_CONCAT + bool "Enable MTD device concatenation" + depends on MTD + help + Enable support for concatenating multiple physical MTD devices + into a single logical device. The larger logical device can then + be partitioned. + config SYS_MTDPARTS_RUNTIME bool "Allow MTDPARTS to be configured at runtime" depends on MTD diff --git a/include/configs/etamin.h b/include/configs/etamin.h index dc83ab71908b..9cf93924df93 100644 --- a/include/configs/etamin.h +++ b/include/configs/etamin.h @@ -151,7 +151,6 @@ #define ETAMIN_NAND_GPMC_CONFIG4 0x16051807 #define ETAMIN_NAND_GPMC_CONFIG5 0x00151e1e #define ETAMIN_NAND_GPMC_CONFIG6 0x16000f80 -#define CONFIG_MTD_CONCAT /* Default env settings */ #define CONFIG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/octeontx_common.h b/include/configs/octeontx_common.h index bcf8b41cfb63..81dbff2d672f 100644 --- a/include/configs/octeontx_common.h +++ b/include/configs/octeontx_common.h @@ -64,7 +64,6 @@ /** EMMC specific defines */ #if defined(CONFIG_NAND_OCTEONTX) -/*#define CONFIG_MTD_CONCAT */ #define CONFIG_SYS_MAX_NAND_DEVICE 8 #endif diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 5b882b2670ca..cecdda678191 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -389,7 +389,6 @@ CONFIG_MMC_SUNXI_SLOT CONFIG_MONITOR_IS_IN_RAM CONFIG_MPC85XX_FEC CONFIG_MPC85XX_FEC_NAME -CONFIG_MTD_CONCAT CONFIG_MTD_NAND_VERIFY_WRITE CONFIG_MTD_PARTITION CONFIG_MVGBE_PORTS -- 2.36.0
[PATCH] cmd: mvebu: Hide bubt specific options when bubt is disabled
CONFIG_MVEBU_NAND_BOOT, CONFIG_MVEBU_SPI_BOOT, CONFIG_MVEBU_MMC_BOOT and CONFIG_MVEBU_UBOOT_DFLT_NAME are unused when CONFIG_CMD_MVEBU_BUBT is not enabled. So hide them. Signed-off-by: Pali Rohár --- cmd/mvebu/Kconfig | 4 1 file changed, 4 insertions(+) diff --git a/cmd/mvebu/Kconfig b/cmd/mvebu/Kconfig index ac8b0afd20e5..39963db82c98 100644 --- a/cmd/mvebu/Kconfig +++ b/cmd/mvebu/Kconfig @@ -9,6 +9,8 @@ config CMD_MVEBU_BUBT For details about bubt command please see the documentation in doc/mvebu/cmd/bubt.txt +if CMD_MVEBU_BUBT + choice prompt "Flash for image" default MVEBU_SPI_BOOT @@ -49,6 +51,8 @@ config MVEBU_UBOOT_DFLT_NAME This option should contain a default file name to be used with MVEBU "bubt" command if the source file name is omitted +endif + config CMD_MVEBU_COMPHY_RX_TRAINING bool "mvebu_comphy_rx_training" depends on ARMADA_8K -- 2.20.1
[PATCH] arm: mvebu: Espressobin: Add NVMe to boot targets
NVMe support is already enabled, so add it into boot targets. Signed-off-by: Pali Rohár --- include/configs/mvebu_armada-37xx.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/configs/mvebu_armada-37xx.h b/include/configs/mvebu_armada-37xx.h index 778f8b828aa8..953dfe812558 100644 --- a/include/configs/mvebu_armada-37xx.h +++ b/include/configs/mvebu_armada-37xx.h @@ -50,6 +50,7 @@ func(MMC, mmc, 1) \ func(MMC, mmc, 0) \ func(USB, usb, 0) \ + func(NVME, nvme, 0) \ func(SCSI, scsi, 0) \ func(PXE, pxe, na) \ func(DHCP, dhcp, na) -- 2.20.1
[PATCH 1/2] pmic: pca9450: add DM_I2C dependencies in Kconfig
The pca9450 driver uses dm_i2c_{read,write}, which
are (unsurprisingly) only available with DM_I2C. Make sure one can't
create an unbuildable .config by adding proper dependencies.
While here, append "in SPL" to the prompt for the SPL_ variant so it
doesn't read the same as the one for the non-SPL_ variant.
Signed-off-by: Rasmus Villemoes
---
drivers/power/pmic/Kconfig | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/power/pmic/Kconfig b/drivers/power/pmic/Kconfig
index 953c92e212..6c534aead7 100644
--- a/drivers/power/pmic/Kconfig
+++ b/drivers/power/pmic/Kconfig
@@ -158,13 +158,15 @@ config SPL_DM_PMIC_MP5416
config DM_PMIC_PCA9450
bool "Enable Driver Model for PMIC PCA9450"
+ depends on DM_I2C
help
This config enables implementation of driver-model pmic uclass
features
for PMIC PCA9450. The driver implements read/write operations.
config SPL_DM_PMIC_PCA9450
- bool "Enable Driver Model for PMIC PCA9450"
+ bool "Enable Driver Model for PMIC PCA9450 in SPL"
depends on SPL_DM_PMIC
+ depends on SPL_DM_I2C
help
This config enables implementation of driver-model pmic uclass
features
for PMIC PCA9450 in SPL. The driver implements read/write operations.
--
2.31.1
[PATCH 2/2] pmic: pca9450: drop pointless .data entries
These are the i2c addresses of the chips, but that comes from device
tree. Having that information duplicated here just adds confusion.
Signed-off-by: Rasmus Villemoes
---
drivers/power/pmic/pca9450.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/power/pmic/pca9450.c b/drivers/power/pmic/pca9450.c
index 2394b196c5..34cee34dba 100644
--- a/drivers/power/pmic/pca9450.c
+++ b/drivers/power/pmic/pca9450.c
@@ -81,9 +81,9 @@ static struct dm_pmic_ops pca9450_ops = {
};
static const struct udevice_id pca9450_ids[] = {
- { .compatible = "nxp,pca9450a", .data = 0x25, },
- { .compatible = "nxp,pca9450b", .data = 0x25, },
- { .compatible = "nxp,pca9450c", .data = 0x25, },
+ { .compatible = "nxp,pca9450a" },
+ { .compatible = "nxp,pca9450b" },
+ { .compatible = "nxp,pca9450c" },
{ }
};
--
2.31.1
Re: [PATCH v3 08/13] misc: Add support for nvmem cells
Hi Sean,
On Fri, 29 Apr 2022 at 13:40, Sean Anderson wrote:
>
> Hi Simon,
>
> On 4/25/22 11:24 AM, Sean Anderson wrote:
> >
> >
> > On 4/25/22 1:48 AM, Simon Glass wrote:
> >> Hi Sean,
> >>
> >> On Mon, 18 Apr 2022 at 13:37, Sean Anderson wrote:
> >>>
> >>> This adds support for "nvmem cells" as seen in Linux. The nvmem device
> >>> class in Linux is used for various assorted ROMs and EEPROMs. In this
> >>> sense, it is similar to UCLASS_MISC, but also includes
> >>> UCLASS_I2C_EEPROM, UCLASS_RTC, and UCLASS_MTD. New drivers corresponding
> >>> to a Linux-style nvmem device should be implemented as one of the
> >>> previously-mentioned uclasses. The nvmem API acts as a compatibility
> >>> layer to adapt the (slightly different) APIs of these uclasses. It also
> >>> handles the lookup of nvmem cells.
> >>>
> >>> While nvmem devices can be accessed directly, they are most often used
> >>> by reading/writing contiguous values called "cells". Cells typically
> >>> hold information like calibration, versions, or configuration (such as
> >>> mac addresses).
> >>>
> >>> nvmem devices can specify "cells" in their device tree:
> >>>
> >>> qfprom: eeprom@70 {
> >>> #address-cells = <1>;
> >>> #size-cells = <1>;
> >>> reg = <0x0070 0x10>;
> >>>
> >>> /* ... */
> >>>
> >>> tsens_calibration: calib@404 {
> >>> reg = <0x404 0x10>;
> >>> };
> >>> };
> >>>
> >>> which can then be referenced like:
> >>>
> >>> tsens {
> >>> /* ... */
> >>> nvmem-cells = <&tsens_calibration>;
> >>> nvmem-cell-names = "calibration";
> >>> };
> >>>
> >>> The tsens driver could then read the calibration value like:
> >>>
> >>> struct nvmem_cell cal_cell;
> >>> u8 cal[16];
> >>> nvmem_cell_get_by_name(dev, "calibration", &cal_cell);
> >>> nvmem_cell_read(&cal_cell, cal, sizeof(cal));
> >>>
> >>> Because nvmem devices are not all of the same uclass, supported uclasses
> >>> must register a nvmem_interface struct. This allows CONFIG_NVMEM to be
> >>> enabled without depending on specific uclasses. At the moment,
> >>> nvmem_interface is very bare-bones, and assumes that no initialization
> >>> is necessary. However, this could be amended in the future.
> >>>
> >>> Although I2C_EEPROM and MISC are quite similar (and could likely be
> >>> unified), they present different read/write function signatures. To
> >>> abstract over this, NVMEM uses the same read/write signature as Linux.
> >>> In particular, short read/writes are not allowed, which is allowed by
> >>> MISC.
> >>>
> >>> The functionality implemented by nvmem cells is very similar to that
> >>> provided by i2c_eeprom_partition. "fixed-partition"s for eeproms does
> >>> not seem to have made its way into Linux or into any device tree other
> >>> than sandbox. It is possible that with the introduction of this API it
> >>> would be possible to remove it.
> >>
> >> I still think this would be better as a separate uclass, with child
> >> devices created at bind time in each of the respective uclasses, like
> >> mmc_bind() does. Then you will see the nvmem devices in the DM tree.
> >> Wouldn't we want to add a command to access the nvmem devices?
> >
> > We already do. E.g. the misc/rtc/eeprom commands. The problem is that
> > for software to access them, they would have to use misc_read/dm_rtc_read/
> > i2c_eeprom_read.
> >
> >> This patch feels like a shortcut to me and I'm not sure of the
> >> benefit of that shortcut.
> > Well, I suppose it's because "nvmem" devices are strict subsets of
> > existing devices. There is no new functionality here (except adapting
> > between semantics like for misc). We should always be able to use the
> > existing API to implement support for a new underlying uclass. There
> > should never be device-specific read/write methods, because we can
> > use the existing read/write uclass methods.
> >
> > What I'm trying to get at is that we sort of already have an nvmem
> > uclass with nvmem devices, they're just not accessible in a uniform
> > way. This series is trying to address the uniformity aspect. But I
> > don't think we need new devices for each nvmem interface, because
> > all they would do would take up ram/rom.
> >
> > --Sean
> >
> > PS. In an ideal world we'd have something like
> >
> > struct nvmem_ops {
> > read();
> > write();
> > };
> >
> > struct dm_rtc_ops {
> > nvmem_ops nvmem;
> > /* the other ops minus read/write */
> > };
> >
> > int nvmem_read (...) {
> > struct nvmem_ops *ops = cell->nvmem->ops;
> > /* ... */
> >
> > return ops->read(...);
> > }
> >
> > but unfortunately, we already have fragmented implementations.
I don't see that as ideal as it involves a 'nested' API, something we
have avoided so far.
> >
>
> To follow up on this, I've conducted some size
[PATCH] arm: tegra: Update some DT compatibles
Some of the DT compatibles have changed upstream so add new DT compatibles
to ensure things continue to keep working if the device trees are
updated.
Signed-off-by: Peter Robinson
---
drivers/i2c/tegra_i2c.c | 1 +
drivers/video/tegra124/dp.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/drivers/i2c/tegra_i2c.c b/drivers/i2c/tegra_i2c.c
index 1e744845423..2394e9d0fb4 100644
--- a/drivers/i2c/tegra_i2c.c
+++ b/drivers/i2c/tegra_i2c.c
@@ -514,6 +514,7 @@ static const struct dm_i2c_ops tegra_i2c_ops = {
static const struct udevice_id tegra_i2c_ids[] = {
{ .compatible = "nvidia,tegra114-i2c", .data = TYPE_114 },
+ { .compatible = "nvidia,tegra124-i2c", .data = TYPE_114 },
{ .compatible = "nvidia,tegra20-i2c", .data = TYPE_STD },
{ .compatible = "nvidia,tegra20-i2c-dvc", .data = TYPE_DVC },
{ }
diff --git a/drivers/video/tegra124/dp.c b/drivers/video/tegra124/dp.c
index 8f5116fe7c8..ee4f09a0c49 100644
--- a/drivers/video/tegra124/dp.c
+++ b/drivers/video/tegra124/dp.c
@@ -1609,6 +1609,7 @@ static int dp_tegra_probe(struct udevice *dev)
static const struct udevice_id tegra_dp_ids[] = {
{ .compatible = "nvidia,tegra124-dpaux" },
+ { .compatible = "nvidia,tegra210-dpaux" },
{ }
};
--
2.36.0
[PATCH 2/2] pci: tegra: Update error prints with new lines
Add new lines to make errorr messages easier to read.
Signed-off-by: Peter Robinson
---
drivers/pci/pci_tegra.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/pci/pci_tegra.c b/drivers/pci/pci_tegra.c
index f8d66c0e1c6..bc489d5ec85 100644
--- a/drivers/pci/pci_tegra.c
+++ b/drivers/pci/pci_tegra.c
@@ -455,7 +455,7 @@ static int tegra_pcie_parse_port_info(ofnode node, uint
*index, uint *lanes)
err = ofnode_read_u32_default(node, "nvidia,num-lanes", -1);
if (err < 0) {
- pr_err("failed to parse \"nvidia,num-lanes\" property");
+ pr_err("failed to parse \"nvidia,num-lanes\" property\n");
return err;
}
@@ -463,7 +463,7 @@ static int tegra_pcie_parse_port_info(ofnode node, uint
*index, uint *lanes)
err = ofnode_read_pci_addr(node, 0, "reg", &addr);
if (err < 0) {
- pr_err("failed to parse \"reg\" property");
+ pr_err("failed to parse \"reg\" property\n");
return err;
}
--
2.36.0
[PATCH 1/2] ARM: tegra: XUSB padctl: Add new lines for errors
Add new lines for error messages to make them easier to read.
Signed-off-by: Peter Robinson
---
arch/arm/mach-tegra/xusb-padctl-common.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/arch/arm/mach-tegra/xusb-padctl-common.c
b/arch/arm/mach-tegra/xusb-padctl-common.c
index e56e27c8b6e..8bdd44ad7ac 100644
--- a/arch/arm/mach-tegra/xusb-padctl-common.c
+++ b/arch/arm/mach-tegra/xusb-padctl-common.c
@@ -84,7 +84,7 @@ tegra_xusb_padctl_group_parse_dt(struct tegra_xusb_padctl
*padctl,
len = ofnode_read_string_count(node, "nvidia,lanes");
if (len < 0) {
- pr_err("failed to parse \"nvidia,lanes\" property");
+ pr_err("failed to parse \"nvidia,lanes\" property\n");
return -EINVAL;
}
@@ -94,7 +94,7 @@ tegra_xusb_padctl_group_parse_dt(struct tegra_xusb_padctl
*padctl,
ret = ofnode_read_string_index(node, "nvidia,lanes", i,
&group->pins[i]);
if (ret) {
- pr_err("failed to read string from \"nvidia,lanes\"
property");
+ pr_err("failed to read string from \"nvidia,lanes\"
property\n");
return -EINVAL;
}
}
@@ -104,7 +104,7 @@ tegra_xusb_padctl_group_parse_dt(struct tegra_xusb_padctl
*padctl,
ret = ofnode_read_string_index(node, "nvidia,function", 0,
&group->func);
if (ret) {
- pr_err("failed to parse \"nvidia,func\" property");
+ pr_err("failed to parse \"nvidia,func\" property\n");
return -EINVAL;
}
@@ -232,7 +232,7 @@ tegra_xusb_padctl_config_parse_dt(struct tegra_xusb_padctl
*padctl,
err = tegra_xusb_padctl_group_parse_dt(padctl, group, subnode);
if (err < 0) {
- pr_err("failed to parse group %s", group->name);
+ pr_err("failed to parse group %s\n", group->name);
return err;
}
@@ -261,7 +261,7 @@ static int tegra_xusb_padctl_parse_dt(struct
tegra_xusb_padctl *padctl,
err = tegra_xusb_padctl_config_parse_dt(padctl, config,
subnode);
if (err < 0) {
- pr_err("failed to parse entry %s: %d",
+ pr_err("failed to parse entry %s: %d\n",
config->name, err);
continue;
}
@@ -289,7 +289,7 @@ int tegra_xusb_process_nodes(ofnode nodes[], unsigned int
count,
err = tegra_xusb_padctl_parse_dt(&padctl, nodes[i]);
if (err < 0) {
- pr_err("failed to parse DT: %d", err);
+ pr_err("failed to parse DT: %d\n", err);
continue;
}
--
2.36.0
RE: [RFC] Data structure for information handoff between firmware boot stages
Hi Simon, Thank you for reviewing the draft proposal! Would you be able to share your review comments on the PDF? Currently the document is not in a markup form and is yet to be hosted in a repository. That's the intent for the long term. Cheers, Jose > -Original Message- > From: Simon Glass > Sent: 03 May 2022 08:59 > To: Jose Marinho > Cc: u-boot@lists.denx.de; Heinrich Schuchardt ; Ilias > Apalodimas ; Tom Rini ; > Samer El-Haj-Mahmoud ; Manish Pandey2 > ; nd > Subject: Re: [RFC] Data structure for information handoff between firmware > boot stages > > Hi Jose, > > On Thu, 7 Apr 2022 at 13:23, Jose Marinho wrote: > > > > Hi All, > > > > The topic of information handoff between TF-A’s BL31 and BL33 (e.g. U-boot > proper, EDK2) was discussed last year in the TF-A and U-boot mailing lists > [1], > [2]. > > > > Examples of information to be handed off between firmware stages are the > TPM log, HOB nodes, etc. > > Having a standard data structure which is usable/supported by every > community contributes to code reuse and leads to simpler codebase > maintenance. > > > > Some already existing data structures, such as the UEFI HOB list [3], and > > the > Bloblist from U-boot, were proposed to be employed for the handoffs. > > There are pros and cons with both HOBs and Bloblist. > > The discussion settled with a consensus that a data structure ought to be > defined which encapsulates the best traits of HOBs and Bloblist. > > > > Properties that the data structure should have: > > - node types identified by an integer, > > - easily relocatable, > > > > - straightforward to append new nodes, > > - easy to read and append to from resource constrained environments. > > > > The data structure should be suitable to pass information between different > firmware stages, such as: > > U-boot SPL -> BL31 -> U-boot > > BL1 -> BL2 -> BL31 -> U-boot > > > > As requested in the ML, an initial proposal was drafted [4]. > > The document [4] is an initial proposal (at an alpha stage). > > The document [4] is being circulated for the purpose of gathering initial > feedback. > > This proposal is closely aligned with an ongoing effort in the u-boot > > mailing > list [5]. > > The proposal defines 1) a set of standard nodes and 2) the registers used at > the handoff boundary. > > > > Standard nodes: > > - fdt node: HW description fdt, > > - HOB node, > > - ACPI table node: the main use-case for this node is to carry the TPM log. > > > > The document [4] accommodates an OEM range, which enables IMPDEF > nodes to be caried in the handoff list. > > By definition, the nodes in the OEM range are not standard and can be > defined per-platform. > > > > Note: the document [4] encapsulates the standard node definition as that is > the simplest approach for feedback gathering. > > Once there is sufficient consensus around the proposal, the standard node > definitions should be moved to a project independent repository. The > repository location is TBD. > > The list of standard nodes is expected to grow with community contribution. > > Thank you for the document. Is there a way to comment on it or should I just > send you my hand-written markup? > > Regards, > Simon > > > > > Kind Regards, > > Jose > > > > > > > > [1] > > https://lists.trustedfirmware.org/archives/list/tf-a@lists.trustedfirm > > ware.org/message/LUIUOVGUMVWID5RUMTYA463KGIU2EHIU/ > > > > [2] > > https://lore.kernel.org/u-boot/CAODwPW_FwFN1E84cV1+nC1aiahiwOL- > TV=mP_6 > > o8h0y9+pc...@mail.gmail.com/ > > > > [3] https://uefi.org/sites/default/files/resources/PI_Spec_1_6.pdf > > > > [4] https://developer.arm.com/documentation/den0135/a > > [5] > > https://lore.kernel.org/u-boot/20220113022625.413990-1-...@chromium.or > > g/ > > > >
Re: [PATCH v1] imx: imx8qm-rom7720: switch to binman
On 20/04/22, Tom Rini wrote: > On Wed, Jan 26, 2022 at 04:52:04PM +0100, Oliver Graute wrote: > > > Switch to use binman to pack images > > > > Signed-off-by: Oliver Graute > > --- > > arch/arm/dts/imx8qm-rom7720-a1.dts| 1 + > > arch/arm/dts/imx8qm-u-boot.dtsi | 133 ++ > > arch/arm/mach-imx/imx8/Kconfig| 1 + > > .../advantech/imx8qm_rom7720_a1/imximage.cfg | 4 +- > > configs/imx8qm_rom7720_a1_4G_defconfig| 2 +- > > doc/board/advantech/imx8qm-rom7720-a1.rst | 3 +- > > 6 files changed, 139 insertions(+), 5 deletions(-) > > create mode 100644 arch/arm/dts/imx8qm-u-boot.dtsi > > Can you please re-spin this patch? Thanks. just send a v2 Best regards, Oliver
[PATCH v2] imx: imx8qm-rom7720: switch to binman
Switch to use binman to pack images
Signed-off-by: Oliver Graute
---
Changes for v2
- just rebased to master
arch/arm/dts/imx8qm-rom7720-a1.dts| 1 +
arch/arm/dts/imx8qm-u-boot.dtsi | 133 ++
arch/arm/mach-imx/imx8/Kconfig| 1 +
.../advantech/imx8qm_rom7720_a1/imximage.cfg | 4 +-
configs/imx8qm_rom7720_a1_4G_defconfig| 2 +-
doc/board/advantech/imx8qm-rom7720-a1.rst | 3 +-
6 files changed, 139 insertions(+), 5 deletions(-)
create mode 100644 arch/arm/dts/imx8qm-u-boot.dtsi
diff --git a/arch/arm/dts/imx8qm-rom7720-a1.dts
b/arch/arm/dts/imx8qm-rom7720-a1.dts
index d1f2fff869..332d441c6d 100644
--- a/arch/arm/dts/imx8qm-rom7720-a1.dts
+++ b/arch/arm/dts/imx8qm-rom7720-a1.dts
@@ -10,6 +10,7 @@
/memreserve/ 0x8000 0x0002;
#include "fsl-imx8qm.dtsi"
+#include "imx8qm-u-boot.dtsi"
/ {
model = "Advantech iMX8QM Qseven series";
diff --git a/arch/arm/dts/imx8qm-u-boot.dtsi b/arch/arm/dts/imx8qm-u-boot.dtsi
new file mode 100644
index 00..5da420ece6
--- /dev/null
+++ b/arch/arm/dts/imx8qm-u-boot.dtsi
@@ -0,0 +1,133 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2021 NXP
+ */
+
+/ {
+ binman: binman {
+ multiple-images;
+ };
+};
+
+&binman {
+ u-boot-spl-ddr {
+ align = <4>;
+ align-size = <4>;
+ filename = "u-boot-spl-ddr.bin";
+ pad-byte = <0xff>;
+
+ u-boot-spl {
+ align-end = <4>;
+ filename = "u-boot-spl.bin";
+ };
+ };
+
+ spl {
+ filename = "spl.bin";
+
+ mkimage {
+ args = "-n spl/u-boot-spl.cfgout -T imx8image -e
0x10";
+
+ blob {
+ filename = "u-boot-spl-ddr.bin";
+ };
+ };
+ };
+
+ itb {
+ filename = "u-boot.itb";
+
+ fit {
+ description = "Configuration to load ATF before U-Boot";
+ fit,external-offset = ;
+ fit,fdt-list = "of-list";
+ #address-cells = <1>;
+
+ images {
+ uboot {
+ arch = "arm64";
+ compression = "none";
+ description = "U-Boot (64-bit)";
+ load = ;
+ type = "standalone";
+
+ uboot_blob {
+ filename = "u-boot-nodtb.bin";
+ type = "blob-ext";
+ };
+ };
+
+ atf {
+ arch = "arm64";
+ compression = "none";
+ description = "ARM Trusted Firmware";
+ entry = <0x0091>;
+ load = <0x00091000>;
+ type = "firmware";
+
+ atf_blob {
+ filename = "bl31.bin";
+ type = "blob-ext";
+ };
+ };
+
+ scfw {
+ arch = "arm64";
+ compression = "none";
+ description = "System Controler
Firmware";
+ type = "firmware";
+
+ scfw_blob {
+ filename =
"mx8qm-val-scfw-tcm.bin";
+ type = "blob-ext";
+ };
+ };
+
+ seco {
+ arch = "arm64";
+ compression = "none";
+ description = "Seco Firmware";
+ type = "firmware";
+
+ seco_blob {
+ filename =
"mx8qm-ahab-container.img";
+ type = "blob-ext";
+ };
+ };
+
+ fdt {
+ filename = "imx8qm-rom7720-a1";
+ type = "flat_dt";
+ compression = "none";
Re: [RFC] Data structure for information handoff between firmware boot stages
Hi Jose, On Thu, 7 Apr 2022 at 13:23, Jose Marinho wrote: > > Hi All, > > The topic of information handoff between TF-A’s BL31 and BL33 (e.g. U-boot > proper, EDK2) was discussed last year in the TF-A and U-boot mailing lists > [1], [2]. > > Examples of information to be handed off between firmware stages are the TPM > log, HOB nodes, etc. > Having a standard data structure which is usable/supported by every community > contributes to code reuse and leads to simpler codebase maintenance. > > Some already existing data structures, such as the UEFI HOB list [3], and the > Bloblist from U-boot, were proposed to be employed for the handoffs. > There are pros and cons with both HOBs and Bloblist. > The discussion settled with a consensus that a data structure ought to be > defined which encapsulates the best traits of HOBs and Bloblist. > > Properties that the data structure should have: > - node types identified by an integer, > - easily relocatable, > > - straightforward to append new nodes, > - easy to read and append to from resource constrained environments. > > The data structure should be suitable to pass information between different > firmware stages, such as: > U-boot SPL -> BL31 -> U-boot > BL1 -> BL2 -> BL31 -> U-boot > > As requested in the ML, an initial proposal was drafted [4]. > The document [4] is an initial proposal (at an alpha stage). > The document [4] is being circulated for the purpose of gathering initial > feedback. > This proposal is closely aligned with an ongoing effort in the u-boot mailing > list [5]. > The proposal defines 1) a set of standard nodes and 2) the registers used at > the handoff boundary. > > Standard nodes: > - fdt node: HW description fdt, > - HOB node, > - ACPI table node: the main use-case for this node is to carry the TPM log. > > The document [4] accommodates an OEM range, which enables IMPDEF nodes to be > caried in the handoff list. > By definition, the nodes in the OEM range are not standard and can be defined > per-platform. > > Note: the document [4] encapsulates the standard node definition as that is > the simplest approach for feedback gathering. > Once there is sufficient consensus around the proposal, the standard node > definitions should be moved to a project independent repository. The > repository location is TBD. > The list of standard nodes is expected to grow with community contribution. Thank you for the document. Is there a way to comment on it or should I just send you my hand-written markup? Regards, Simon > > Kind Regards, > Jose > > > > [1] > https://lists.trustedfirmware.org/archives/list/t...@lists.trustedfirmware.org/message/LUIUOVGUMVWID5RUMTYA463KGIU2EHIU/ > > [2] > https://lore.kernel.org/u-boot/CAODwPW_FwFN1E84cV1+nC1aiahiwOL-TV=mp_6o8h0y9+pc...@mail.gmail.com/ > > [3] https://uefi.org/sites/default/files/resources/PI_Spec_1_6.pdf > > [4] https://developer.arm.com/documentation/den0135/a > [5] https://lore.kernel.org/u-boot/20220113022625.413990-1-...@chromium.org/ > >
Re: [PATCH v7 0/7] fpga: zynqmp: Adding support of loading authenticated images
On 4/11/22 20:00, Adrian Fiergolski wrote: This patchset introduces support for the authenticated FPGA images on ZynqMP boards, besides that introducing common way to pass the compatible property to any fpga driver. It bases on the initial work by Jorge Ramirez-Ortiz https://patchwork.ozlabs.org/project/uboot/patch/20211015091506.2602-1-jo...@foundries.io/ https://patchwork.ozlabs.org/project/uboot/patch/20211005111324.19749-3-jo...@foundries.io/ Changed in v7: - apply Michal Simek's suggestions As I applied changes on Oleksandr's patches, I indicated it by specifying myself as co-author in the commits logs. I am not sure if that is the convention of marking it. Changed in v6: - add support for the encrypted bitfiles Changes in v5: - replace ifdef with if() where it's possible Changes in v4: - change interface to xilinx_desc->operations->open() callback. - fix a bug from previous version of the patchset in dereferencing of a parent fpga_desc structure. Changes in v3: - remove the patch which introduced CMD_SPL_FPGA_LOAD_SECURE. - fix mixing definitions/declarations. - replace strcmp() calls with more secure strncmp(). - document the "u-boot,zynqmp-fpga-ddrauth" compatible string. - fix code style by check-patch recommendations. Changes in v2: - add function fit_fpga_load() to simplify calls of fpga_load() from contexts without a compatible attribute. - move all ZynqMP-specific logic to drivers/fpga/zynqmppl.c - prepare for passing a "compatible" FDT property to any fpga driver. Oleksandr Suvorov (6): fpga: add option for loading FPGA secure bitstreams fpga: add fit_fpga_load function fpga: xilinx: pass an address of xilinx_desc in fpga_desc fpga: xilinx: add missed identifier names fpga: xilinx: pass xilinx_desc pointer address into load() ops fpga: zynqmp: support loading authenticated images Adrian Fiergolski (1): fpga: zynqmp: support loading encrypted bitfiles boot/Kconfig | 4 +-- cmd/Kconfig | 3 ++- common/spl/spl_fit.c | 6 ++--- doc/uImage.FIT/source_file_format.txt | 7 +- drivers/fpga/Kconfig | 14 +++ drivers/fpga/fpga.c | 29 ++--- drivers/fpga/spartan2.c | 3 ++- drivers/fpga/spartan3.c | 3 ++- drivers/fpga/versalpl.c | 2 +- drivers/fpga/virtex2.c| 3 ++- drivers/fpga/xilinx.c | 8 +++--- drivers/fpga/zynqmppl.c | 36 --- drivers/fpga/zynqpl.c | 3 ++- include/fpga.h| 5 include/xilinx.h | 12 + 15 files changed, 109 insertions(+), 29 deletions(-) Thanks for continuing on this work. We are almost there. Just small things to finish and we are ready to go. Thanks, Michal
Re: [PATCH v7 6/7] fpga: zynqmp: support loading authenticated images
On 4/11/22 20:00, Adrian Fiergolski wrote:
From: Oleksandr Suvorov
Add supporting new compatible string "u-boot,zynqmp-fpga-ddrauth" to
handle loading authenticated images (DDR).
Based on solution by Jorge Ramirez-Ortiz
Signed-off-by: Oleksandr Suvorov
Co-developed-by: Ricardo Salveti
Signed-off-by: Ricardo Salveti
Tested-by: Ricardo Salveti
Co-developed-by: Adrian Fiergolski
Signed-off-by: Adrian Fiergolski
---
boot/Kconfig | 4 ++--
doc/uImage.FIT/source_file_format.txt | 5 -
drivers/fpga/zynqmppl.c | 21 +
3 files changed, 27 insertions(+), 3 deletions(-)
diff --git a/boot/Kconfig b/boot/Kconfig
index b83a4e8400..f7faafb29f 100644
--- a/boot/Kconfig
+++ b/boot/Kconfig
@@ -209,8 +209,8 @@ config SPL_LOAD_FIT
1. "loadables" images, other than FDTs, which do not have a "load"
property will not be loaded. This limitation also applies to FPGA
images with the correct "compatible" string.
- 2. For FPGA images, only the "compatible" = "u-boot,fpga-legacy"
-loading method is supported.
+ 2. For FPGA images, the supported "compatible" list is in the
+doc/uImage.FIT/source_file_format.txt.
3. FDTs are only loaded for images with an "os" property of "u-boot".
"linux" images are also supported with Falcon boot mode.
diff --git a/doc/uImage.FIT/source_file_format.txt b/doc/uImage.FIT/source_file_format.txt
index f93ac6d1c7..461e2af2a8 100644
--- a/doc/uImage.FIT/source_file_format.txt
+++ b/doc/uImage.FIT/source_file_format.txt
@@ -184,7 +184,10 @@ the '/images' node should have the following layout:
Mandatory for types: "firmware", and "kernel".
- compatible : compatible method for loading image.
Mandatory for types: "fpga", and images that do not specify a load
address.
-To use the generic fpga loading routine, use "u-boot,fpga-legacy".
+Supported compatible methods:
+"u-boot,fpga-legacy" - the generic fpga loading routine.
+"u-boot,zynqmp-fpga-ddrauth" - signed non-encrypted FPGA bitstream for
+Xilinx Zynq UltraScale+ (ZymqMP) device.
Optional nodes:
- hash-1 : Each hash sub-node represents separate hash or checksum
diff --git a/drivers/fpga/zynqmppl.c b/drivers/fpga/zynqmppl.c
index c7f9f4ae84..0ce641e495 100644
--- a/drivers/fpga/zynqmppl.c
+++ b/drivers/fpga/zynqmppl.c
@@ -9,6 +9,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -210,6 +211,26 @@ static int zynqmp_load(xilinx_desc **desc_ptr, const void
*buf, size_t bsize,
u32 ret_payload[PAYLOAD_ARG_CNT];
bool xilfpga_old = false;
xilinx_desc *desc = *desc_ptr;
+ fpga_desc *fdesc = container_of((void *)desc_ptr, fpga_desc, devdesc);
+
+ if (fdesc && fdesc->compatible &&
+ !strcmp(fdesc->compatible, "u-boot,zynqmp-fpga-ddrauth")) {
I think you should use directly here what you have in 7/7. It means to check
that it is not fpga-legacy.
+ struct fpga_secure_info info = { 0 };
+
+ if (!CONFIG_IS_ENABLED(FPGA_LOAD_SECURE)) {
+ printf("No support for %s\n", fdesc->compatible);
+ return FPGA_FAIL;
+ }
+
+ if (!desc->operations->loads) {
+ printf("%s: Missing load operation\n", __func__);
+ return FPGA_FAIL;
+ }
+ /* DDR authentication */
+ info.authflag = 1;
+ info.encflag = 2;
+ return desc->operations->loads(desc, buf, bsize, &info);
+ }
if (zynqmp_firmware_version() <= PMUFW_V1_0) {
puts("WARN: PMUFW v1.0 or less is detected\n");
Before you start to deal with secure bitstreams you should also likely check
this PMUFW checking before you call loads.
Thanks,
Michal
Re: [PATCH v7 5/7] fpga: xilinx: pass xilinx_desc pointer address into load() ops
On 4/11/22 20:00, Adrian Fiergolski wrote: From: Oleksandr Suvorov Pass an address of xilinx_desc pointer in an fpga_desc into a load() callback of struct xilinx_fpga_op. It allows getting parent fpga_desc structure members inside xilinx fpga drivers. Signed-off-by: Oleksandr Suvorov Tested-by: Ricardo Salveti missing your sob line here. M
Re: [PATCH v7 4/7] fpga: xilinx: add missed identifier names
On 4/11/22 20:00, Adrian Fiergolski wrote:
From: Oleksandr Suvorov
Function definition arguments should also have identifier names.
Add missed ones to struct xilinx_fpga_op callbacks, unifying code.
Signed-off-by: Oleksandr Suvorov
missing your sob line here.
M
---
include/xilinx.h | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/include/xilinx.h b/include/xilinx.h
index 57b0e7be11..06ecc9a842 100644
--- a/include/xilinx.h
+++ b/include/xilinx.h
@@ -48,12 +48,14 @@ typedef struct {/* typedef xilinx_desc */
} xilinx_desc;/* end, typedef xilinx_desc */
struct xilinx_fpga_op {
- int (*load)(xilinx_desc *, const void *, size_t, bitstream_type);
- int (*loadfs)(xilinx_desc *, const void *, size_t, fpga_fs_info *);
+ int (*load)(xilinx_desc *desc, const void *buf, size_t bsize,
+ bitstream_type bstype);
+ int (*loadfs)(xilinx_desc *desc, const void *buf, size_t bsize,
+ fpga_fs_info *fpga_fsinfo);
int (*loads)(xilinx_desc *desc, const void *buf, size_t bsize,
struct fpga_secure_info *fpga_sec_info);
- int (*dump)(xilinx_desc *, const void *, size_t);
- int (*info)(xilinx_desc *);
+ int (*dump)(xilinx_desc *desc, const void *buf, size_t bsize);
+ int (*info)(xilinx_desc *desc);
};
/* Generic Xilinx Functions
Re: [PATCH v7 2/7] fpga: add fit_fpga_load function
On 4/11/22 20:00, Adrian Fiergolski wrote:
From: Oleksandr Suvorov
Introduce a function which passes an fpga compatible string from
FIT images to FPGA drivers. This lets the different implementations
decide how to handle it.
Some code of Jorge Ramirez-Ortiz is reused.
Signed-off-by: Oleksandr Suvorov
Tested-by: Ricardo Salveti
Co-developed-by: Adrian Fiergolski
Signed-off-by: Adrian Fiergolski
---
common/spl/spl_fit.c | 6 ++
drivers/fpga/fpga.c | 23 ++-
include/fpga.h | 4
3 files changed, 28 insertions(+), 5 deletions(-)
diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c
index 1bbf824684..0e3c2a94b6 100644
--- a/common/spl/spl_fit.c
+++ b/common/spl/spl_fit.c
@@ -588,11 +588,9 @@ static int spl_fit_upload_fpga(struct spl_fit_info *ctx,
int node,
compatible = fdt_getprop(ctx->fit, node, "compatible", NULL);
if (!compatible)
warn_deprecated("'fpga' image without 'compatible' property");
- else if (strcmp(compatible, "u-boot,fpga-legacy"))
- printf("Ignoring compatible = %s property\n", compatible);
- ret = fpga_load(0, (void *)fpga_image->load_addr, fpga_image->size,
- BIT_FULL);
+ ret = fit_fpga_load(0, (void *)fpga_image->load_addr, fpga_image->size,
+ BIT_FULL, compatible);
if (ret) {
printf("%s: Cannot load the image to the FPGA\n", __func__);
return ret;
diff --git a/drivers/fpga/fpga.c b/drivers/fpga/fpga.c
index 3b0a44b242..a306dd81f9 100644
--- a/drivers/fpga/fpga.c
+++ b/drivers/fpga/fpga.c
@@ -249,8 +249,23 @@ int fpga_loads(int devnum, const void *buf, size_t size,
}
#endif
+int fit_fpga_load(int devnum, const void *buf, size_t bsize,
+ bitstream_type bstype, const char *compatible)
+{
+ fpga_desc *desc = fpga_get_desc(devnum);
this generates warning which you should fix.
+ fpga_desc *desc = fpga_get_desc(devnum);
+^
w+../drivers/fpga/fpga.c: In function ‘fit_fpga_load’:
w+../drivers/fpga/fpga.c:255:20: warning: initialization discards ‘const’
qualifier from pointer target type [-Wdiscarded-qualifiers]
+
+ /*
+* Store the compatible string to proceed it in underlying
+* functions
+*/
+ desc->compatible = (char *)compatible;
+
+ return fpga_load(devnum, buf, bsize, bstype);
+}
+
/*
- * Generic multiplexing code
+ * Generic multiplexing code:
+ * Each architecture must handle the mandatory FPGA DT compatible property.
*/
int fpga_load(int devnum, const void *buf, size_t bsize, bitstream_type
bstype)
{
@@ -270,6 +285,9 @@ int fpga_load(int devnum, const void *buf, size_t bsize,
bitstream_type bstype)
break;
case fpga_altera:
#if defined(CONFIG_FPGA_ALTERA)
+ if (strncmp(desc->compatible, "u-boot,fpga-legacy", 18))
+ printf("Ignoring compatible = %s property\n",
+ desc->compatible);
ret_val = altera_load(desc->devdesc, buf, bsize);
#else
fpga_no_sup((char *)__func__, "Altera devices");
@@ -277,6 +295,9 @@ int fpga_load(int devnum, const void *buf, size_t bsize,
bitstream_type bstype)
break;
case fpga_lattice:
#if defined(CONFIG_FPGA_LATTICE)
+ if (strncmp(desc->compatible, "u-boot,fpga-legacy", 18))
+ printf("Ignoring compatible = %s property\n",
+ desc->compatible);
ret_val = lattice_load(desc->devdesc, buf, bsize);
#else
fpga_no_sup((char *)__func__, "Lattice devices");
diff --git a/include/fpga.h b/include/fpga.h
index ec5144334d..2891f32106 100644
--- a/include/fpga.h
+++ b/include/fpga.h
@@ -35,6 +35,7 @@ typedef enum {/* typedef fpga_type */
typedef struct { /* typedef fpga_desc */
fpga_type devtype; /* switch value to select sub-functions */
void *devdesc; /* real device descriptor */
+ char *compatible; /* device compatible string */
} fpga_desc; /* end, typedef fpga_desc */
typedef struct {/* typedef fpga_desc */
@@ -63,6 +64,9 @@ int fpga_add(fpga_type devtype, void *desc);
int fpga_count(void);
const fpga_desc *const fpga_get_desc(int devnum);
int fpga_is_partial_data(int devnum, size_t img_len);
+/* the DT compatible property must be handled by the different FPGA archs */
+int fit_fpga_load(int devnum, const void *buf, size_t bsize,
+ bitstream_type bstype, const char *compatible);
int fpga_load(int devnum, const void *buf, size_t bsize,
bitstream_type bstype);
int fpga_fsload(int devnum, const void *buf, size_t size,
M
Re: [PATCH] xilinx: Handle board_get_usable_ram_top(0) properly
pá 29. 4. 2022 v 11:52 odesílatel Michal Simek napsal:
>
> board_get_usable_ram_top() was designed for getting the top most location
> for U-Boot allocation that's why function itself supports via total_size
> parameter to find out where the right location for U-Boot is.
> But function itself is also reused by different (EFI) which is passing
> total_size as 0 to find out where the usable ram top is. For this case
> doesn't make sense (a waste time) to call any lmb functions.
> That's why simply return gd->ram_top.
>
> And gd->ram_top is filled already based on previous call for U-Boot iself.
> The same solution is also used by stm32mp by commit 92b611e8b003 ("stm32mp:
> correctly handle board_get_usable_ram_top(0)") and commit c8510e397fad
> ("stm32mp: Fix board_get_usable_ram_top()").
>
> Signed-off-by: Michal Simek
> ---
>
> board/xilinx/versal/board.c | 3 +++
> board/xilinx/zynqmp/zynqmp.c | 3 +++
> 2 files changed, 6 insertions(+)
>
> diff --git a/board/xilinx/versal/board.c b/board/xilinx/versal/board.c
> index 2e2807eee463..a88f5bb177e2 100644
> --- a/board/xilinx/versal/board.c
> +++ b/board/xilinx/versal/board.c
> @@ -256,6 +256,9 @@ ulong board_get_usable_ram_top(ulong total_size)
> phys_addr_t reg;
> struct lmb lmb;
>
> + if (!total_size)
> + return gd->ram_top;
> +
> /* found enough not-reserved memory to relocated U-Boot */
> lmb_init(&lmb);
> lmb_add(&lmb, gd->ram_base, gd->ram_size);
> diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c
> index 41ecc9559c4b..e311aa772cce 100644
> --- a/board/xilinx/zynqmp/zynqmp.c
> +++ b/board/xilinx/zynqmp/zynqmp.c
> @@ -516,6 +516,9 @@ ulong board_get_usable_ram_top(ulong total_size)
> phys_addr_t reg;
> struct lmb lmb;
>
> + if (!total_size)
> + return gd->ram_top;
> +
> if (!IS_ALIGNED((ulong)gd->fdt_blob, 0x8))
> panic("Not 64bit aligned DT location: %p\n", gd->fdt_blob);
>
> --
> 2.36.0
>
Applied.
M
--
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Xilinx Microblaze
Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP ARM64 SoCs
U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP/Versal SoCs
Re: [PATCH 04/12] cmd: tlv_eeprom: convert functions used by command to api functions
Am 03.05.22 um 09:16 schrieb Stefan Roese:
On 02.05.22 16:18, Josua Mayer wrote:
- prog_eeprom: write_tlvinfo_tlv_eeprom
- update_crc: tlvinfo_update_crc
- is_valid_tlv: is_valid_tlvinfo_entry
- is_checksum_valid: tlvinfo_check_crc
So while creating a new API it makes sense to prepend the function
names identical IMHO to not "pollute" the namespace. Something like
- tlv_is_valid_entry
- tlv_check_crc
...
Just examples, you get the idea.
Yes. The hard part in this particular implementation is that the naming
is not consistent.
The most sense I could make is that prefix tlvinfo indicates all tlv
data, i.e. working with the whole structure, while tlvinfo_tlv indicates
working with one data entry. Further write, read and is_ are currently
prefixed in the header, but for previously static functions in the C
file it was put in the middle ...
I found it quite difficult to prepare for splitting off a library in a
way that preserves history, i.e. diffs should still be readable for
spotting mistakes.
I was considering to at the very end do a mass-rename and come up with
better naming, something like
tlv_{set,get}_{blob,string,mac}
tlv_find_entry
tlv_{read,write}_eeprom
But this is pending a refactoring and extension of the tlv parsing code
in board/solidrun/common/tlv_data.*, to figure out what is required or
useful.
Thanks,
Stefan
Signed-off-by: Josua Mayer
---
cmd/tlv_eeprom.c | 56 +++
include/tlv_eeprom.h | 57
2 files changed, 76 insertions(+), 37 deletions(-)
diff --git a/cmd/tlv_eeprom.c b/cmd/tlv_eeprom.c
index 00c5b5f840..1b4f2537f6 100644
--- a/cmd/tlv_eeprom.c
+++ b/cmd/tlv_eeprom.c
@@ -28,13 +28,9 @@ DECLARE_GLOBAL_DATA_PTR;
#define MAX_TLV_DEVICES 2
/* File scope function prototypes */
-static bool is_checksum_valid(u8 *eeprom);
static int read_eeprom(int devnum, u8 *eeprom);
static void show_eeprom(int devnum, u8 *eeprom);
static void decode_tlv(struct tlvinfo_tlv *tlv);
-static void update_crc(u8 *eeprom);
-static int prog_eeprom(int devnum, u8 *eeprom);
-static bool tlvinfo_find_tlv(u8 *eeprom, u8 tcode, int *eeprom_index);
static bool tlvinfo_delete_tlv(u8 *eeprom, u8 code);
static bool tlvinfo_add_tlv(u8 *eeprom, int tcode, char *strval);
static int set_mac(char *buf, const char *string);
@@ -58,18 +54,6 @@ static inline bool is_digit(char c)
return (c >= '0' && c <= '9');
}
-/**
- * is_valid_tlv
- *
- * Perform basic sanity checks on a TLV field. The TLV is pointed to
- * by the parameter provided.
- * 1. The type code is not reserved (0x00 or 0xFF)
- */
-static inline bool is_valid_tlv(struct tlvinfo_tlv *tlv)
-{
- return((tlv->type != 0x00) && (tlv->type != 0xFF));
-}
-
/**
* is_hex
*
@@ -83,14 +67,12 @@ static inline u8 is_hex(char p)
}
/**
- * is_checksum_valid
- *
* Validate the checksum in the provided TlvInfo EEPROM data. First,
* verify that the TlvInfo header is valid, then make sure the last
* TLV is a CRC-32 TLV. Then calculate the CRC over the EEPROM data
* and compare it to the value stored in the EEPROM CRC-32 TLV.
*/
-static bool is_checksum_valid(u8 *eeprom)
+bool tlvinfo_check_crc(u8 *eeprom)
{
struct tlvinfo_header *eeprom_hdr = to_header(eeprom);
struct tlvinfo_tlv *eeprom_crc;
@@ -137,11 +119,11 @@ static int read_eeprom(int devnum, u8 *eeprom)
// If the contents are invalid, start over with default contents
if (!is_valid_tlvinfo_header(eeprom_hdr) ||
- !is_checksum_valid(eeprom)) {
+ !tlvinfo_check_crc(eeprom)) {
strcpy(eeprom_hdr->signature, TLV_INFO_ID_STRING);
eeprom_hdr->version = TLV_INFO_VERSION;
eeprom_hdr->totallen = cpu_to_be16(0);
- update_crc(eeprom);
+ tlvinfo_update_crc(eeprom);
}
#ifdef DEBUG
@@ -183,7 +165,7 @@ static void show_eeprom(int devnum, u8 *eeprom)
tlv_end = HDR_SIZE + be16_to_cpu(eeprom_hdr->totallen);
while (curr_tlv < tlv_end) {
eeprom_tlv = to_entry(&eeprom[curr_tlv]);
- if (!is_valid_tlv(eeprom_tlv)) {
+ if (!is_valid_tlvinfo_entry(eeprom_tlv)) {
printf("Invalid TLV field starting at EEPROM offset %d\n",
curr_tlv);
return;
@@ -193,7 +175,7 @@ static void show_eeprom(int devnum, u8 *eeprom)
}
printf("Checksum is %s.\n",
- is_checksum_valid(eeprom) ? "valid" : "invalid");
+ tlvinfo_check_crc(eeprom) ? "valid" : "invalid");
#ifdef DEBUG
printf("EEPROM dump: (0x%x bytes)", TLV_INFO_MAX_LEN);
@@ -340,13 +322,13 @@ static void decode_tlv(struct tlvinfo_tlv *tlv)
}
/**
- * update_crc
+ * tlvinfo_update_crc
*
* This function updates the CRC-32 TLV. If there is no CRC-32
TLV, then
* one is added. This function should be called after each update
to the
* EEPROM structure, to make sure the CRC is always corre
Re: [PATCH] Revert "arm64: xilinx: Set CONFIG_ZYNQMP_FIRMWARE config for mini emmc"
st 27. 4. 2022 v 10:30 odesílatel Michal Simek napsal: > > From: T Karthik Reddy > > This reverts commit 122ca834f2f4a9d70abeece3d1ff200a3556ab24. > > Disable CONFIG_ZYNQMP_FIRMWARE config from zynqmp & versal mini emmc > defconfig files, as mini emmc does not use any firmware. > > Signed-off-by: T Karthik Reddy > Acked-by: Ashok Reddy Soma > Signed-off-by: Michal Simek > --- > > configs/xilinx_versal_mini_emmc0_defconfig | 1 - > configs/xilinx_versal_mini_emmc1_defconfig | 1 - > configs/xilinx_zynqmp_mini_emmc0_defconfig | 1 - > configs/xilinx_zynqmp_mini_emmc1_defconfig | 1 - > 4 files changed, 4 deletions(-) > > diff --git a/configs/xilinx_versal_mini_emmc0_defconfig > b/configs/xilinx_versal_mini_emmc0_defconfig > index ab14118fdcdf..9d2f97576bbd 100644 > --- a/configs/xilinx_versal_mini_emmc0_defconfig > +++ b/configs/xilinx_versal_mini_emmc0_defconfig > @@ -56,7 +56,6 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y > # CONFIG_NET is not set > # CONFIG_DM_WARN is not set > # CONFIG_DM_DEVICE_REMOVE is not set > -CONFIG_ZYNQMP_FIRMWARE=y > CONFIG_MMC_SDHCI=y > CONFIG_MMC_SDHCI_ZYNQ=y > CONFIG_ARM_DCC=y > diff --git a/configs/xilinx_versal_mini_emmc1_defconfig > b/configs/xilinx_versal_mini_emmc1_defconfig > index cab3d21cb71e..7efb9287561a 100644 > --- a/configs/xilinx_versal_mini_emmc1_defconfig > +++ b/configs/xilinx_versal_mini_emmc1_defconfig > @@ -56,7 +56,6 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y > # CONFIG_NET is not set > # CONFIG_DM_WARN is not set > # CONFIG_DM_DEVICE_REMOVE is not set > -CONFIG_ZYNQMP_FIRMWARE=y > CONFIG_MMC_SDHCI=y > CONFIG_MMC_SDHCI_ZYNQ=y > CONFIG_ARM_DCC=y > diff --git a/configs/xilinx_zynqmp_mini_emmc0_defconfig > b/configs/xilinx_zynqmp_mini_emmc0_defconfig > index e176175251f3..b40527715669 100644 > --- a/configs/xilinx_zynqmp_mini_emmc0_defconfig > +++ b/configs/xilinx_zynqmp_mini_emmc0_defconfig > @@ -58,7 +58,6 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y > # CONFIG_DM_WARN is not set > # CONFIG_DM_DEVICE_REMOVE is not set > CONFIG_SPL_DM_SEQ_ALIAS=y > -CONFIG_ZYNQMP_FIRMWARE=y > CONFIG_SUPPORT_EMMC_BOOT=y > CONFIG_MMC_SDHCI=y > CONFIG_MMC_SDHCI_ZYNQ=y > diff --git a/configs/xilinx_zynqmp_mini_emmc1_defconfig > b/configs/xilinx_zynqmp_mini_emmc1_defconfig > index f5b35fbb71cc..5fa1337d761c 100644 > --- a/configs/xilinx_zynqmp_mini_emmc1_defconfig > +++ b/configs/xilinx_zynqmp_mini_emmc1_defconfig > @@ -58,7 +58,6 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y > # CONFIG_DM_WARN is not set > # CONFIG_DM_DEVICE_REMOVE is not set > CONFIG_SPL_DM_SEQ_ALIAS=y > -CONFIG_ZYNQMP_FIRMWARE=y > CONFIG_SUPPORT_EMMC_BOOT=y > CONFIG_MMC_SDHCI=y > CONFIG_MMC_SDHCI_ZYNQ=y > -- > 2.36.0 > Applied. M -- Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91 w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel - Xilinx Microblaze Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP ARM64 SoCs U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP/Versal SoCs
Re: [PATCH] mmc: zynq_sdhci: Add weak function prototype
st 27. 4. 2022 v 10:27 odesílatel Michal Simek napsal:
>
> From: T Karthik Reddy
>
> zynqmp_pm_is_function_supported() which checks feature support on som,
> which is implemented in firmware_zynqmp.c driver. As mini configuration
> does not use firmware driver, so create a weak function to avoid
> compilation error on zynqmp mini configuration.
>
> Signed-off-by: T Karthik Reddy
> Acked-by: Ashok Reddy Soma
> Signed-off-by: Michal Simek
> ---
>
> drivers/mmc/zynq_sdhci.c | 5 +
> 1 file changed, 5 insertions(+)
>
> diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c
> index a59d96c6bdad..e978b6798854 100644
> --- a/drivers/mmc/zynq_sdhci.c
> +++ b/drivers/mmc/zynq_sdhci.c
> @@ -79,6 +79,11 @@ __weak int xilinx_pm_request(u32 api_id, u32 arg0, u32
> arg1, u32 arg2,
> return 0;
> }
>
> +__weak int zynqmp_pm_is_function_supported(const u32 api_id, const u32 id)
> +{
> + return 1;
> +}
> +
> #if defined(CONFIG_ARCH_ZYNQMP) || defined(CONFIG_ARCH_VERSAL)
> /* Default settings for ZynqMP Clock Phases */
> static const u32 zynqmp_iclk_phases[] = {0, 63, 63, 0, 63, 0,
> --
> 2.36.0
>
Applied.
M
--
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Xilinx Microblaze
Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP ARM64 SoCs
U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP/Versal SoCs
Re: [PATCH V2] imx: drop CONFIG_MXC_UART_BASE
On 03.05.22 06:14, Peng Fan (OSS) wrote: From: Peng Fan Since these boards has CONFIG_DM_SERIAL and/or CONFIG_SPL_DM_SERIAL, the legacy macro no need to be defined. Reviewed-by: Heiko Schocher Reviewed-by: Fabio Estevam Signed-off-by: Peng Fan For tbs2910: Acked-by: Soeren Moch Thanks, Soeren --- V2: Add R-b Drop comments add imx8mn_bsh_smm_s2_common.h include/configs/aristainetos2.h| 2 -- include/configs/imx8mm_evk.h | 1 - include/configs/imx8mn_bsh_smm_s2_common.h | 2 -- include/configs/imx8mn_evk.h | 1 - include/configs/imx8mp_evk.h | 1 - include/configs/mx7dsabresd.h | 1 - include/configs/somlabs_visionsom_6ull.h | 1 - include/configs/tbs2910.h | 3 --- include/configs/verdin-imx8mm.h| 3 --- include/configs/verdin-imx8mp.h| 3 --- 10 files changed, 18 deletions(-) diff --git a/include/configs/aristainetos2.h b/include/configs/aristainetos2.h index 8ee97f1d4e3..27adae5d6bf 100644 --- a/include/configs/aristainetos2.h +++ b/include/configs/aristainetos2.h @@ -14,10 +14,8 @@ #define CONFIG_HOSTNAME "aristainetos2" #if (CONFIG_SYS_BOARD_VERSION == 5) -#define CONFIG_MXC_UART_BASE UART2_BASE #define CONSOLE_DEV "ttymxc1" #elif (CONFIG_SYS_BOARD_VERSION == 6) -#define CONFIG_MXC_UART_BASE UART1_BASE #define CONSOLE_DEV "ttymxc0" #endif diff --git a/include/configs/imx8mm_evk.h b/include/configs/imx8mm_evk.h index 42b78485cfc..7dd66527c3d 100644 --- a/include/configs/imx8mm_evk.h +++ b/include/configs/imx8mm_evk.h @@ -68,7 +68,6 @@ #define PHYS_SDRAM 0x4000 #define PHYS_SDRAM_SIZE 0x8000 /* 2GB DDR */ -#define CONFIG_MXC_UART_BASE UART2_BASE_ADDR /* Monitor Command Prompt */ #define CONFIG_SYS_CBSIZE 2048 diff --git a/include/configs/imx8mn_bsh_smm_s2_common.h b/include/configs/imx8mn_bsh_smm_s2_common.h index 6387576c2da..57be38d9433 100644 --- a/include/configs/imx8mn_bsh_smm_s2_common.h +++ b/include/configs/imx8mn_bsh_smm_s2_common.h @@ -45,8 +45,6 @@ #define CONFIG_SYS_SDRAM_BASE 0x4000 #define PHYS_SDRAM0x4000 -#define CONFIG_MXC_UART_BASE UART4_BASE_ADDR - /* Monitor Command Prompt */ #define CONFIG_SYS_CBSIZE SZ_2K #define CONFIG_SYS_MAXARGS64 diff --git a/include/configs/imx8mn_evk.h b/include/configs/imx8mn_evk.h index 034132225c6..b20e0a5553d 100644 --- a/include/configs/imx8mn_evk.h +++ b/include/configs/imx8mn_evk.h @@ -75,7 +75,6 @@ #define PHYS_SDRAM 0x4000 #define PHYS_SDRAM_SIZE 0x8000 /* 2GB DDR */ -#define CONFIG_MXC_UART_BASE UART2_BASE_ADDR /* Monitor Command Prompt */ #define CONFIG_SYS_CBSIZE 2048 diff --git a/include/configs/imx8mp_evk.h b/include/configs/imx8mp_evk.h index cc8d65cb54e..cbdd490a300 100644 --- a/include/configs/imx8mp_evk.h +++ b/include/configs/imx8mp_evk.h @@ -80,7 +80,6 @@ #define PHYS_SDRAM_2 0x1 #define PHYS_SDRAM_2_SIZE 0xC000 /* 3 GB */ -#define CONFIG_MXC_UART_BASE UART2_BASE_ADDR /* Monitor Command Prompt */ #define CONFIG_SYS_CBSIZE 2048 diff --git a/include/configs/mx7dsabresd.h b/include/configs/mx7dsabresd.h index aaad232f0e4..62e62c6701f 100644 --- a/include/configs/mx7dsabresd.h +++ b/include/configs/mx7dsabresd.h @@ -12,7 +12,6 @@ #define PHYS_SDRAM_SIZE SZ_1G -#define CONFIG_MXC_UART_BASEUART1_IPS_BASE_ADDR #ifdef CONFIG_IMX_BOOTAUX /* Set to QSPI1 A flash at default */ diff --git a/include/configs/somlabs_visionsom_6ull.h b/include/configs/somlabs_visionsom_6ull.h index d4761296c75..e6aad386efe 100644 --- a/include/configs/somlabs_visionsom_6ull.h +++ b/include/configs/somlabs_visionsom_6ull.h @@ -16,7 +16,6 @@ /* SPL options */ #include "imx6_spl.h" -#define CONFIG_MXC_UART_BASE UART1_BASE /* MMC Configs */ #ifdef CONFIG_FSL_USDHC diff --git a/include/configs/tbs2910.h b/include/configs/tbs2910.h index b7a94812f35..5d8cb34ad9a 100644 --- a/include/configs/tbs2910.h +++ b/include/configs/tbs2910.h @@ -24,9 +24,6 @@ #define CONFIG_SYS_BOOTMAPSZ 0x1000 -/* Serial console */ -#define CONFIG_MXC_UART_BASE UART1_BASE /* select UART1/UART2 */ - /* Framebuffer */ #define CONFIG_IMX_HDMI #define CONFIG_IMX_VIDEO_SKIP diff --git a/include/configs/verdin-imx8mm.h b/include/configs/verdin-imx8mm.h index da3dc95f9ee..e0f0347fcf4 100644 --- a/include/configs/verdin-imx8mm.h +++ b/include/configs/verdin-imx8mm.h @@ -83,9 +83,6 @@ #define PHYS_SDRAM 0x4000 #define PHYS_SDRAM_SIZE SZ_2G /* 2GB DDR */ -/* UART */ -#define CONFIG_MXC_UART_BASE UART1_BASE_ADDR - /* Monitor Command Prompt */ #define CONFIG
