Re: [PATCH v2 2/3] efi_loader: bootmgr: fix a problem in loading an image from a short-path
On 5/12/22 04:29, AKASHI Takahiro wrote:
Booting from a short-form device path which starts with the first element
being a File Path Media Device Path failed because it doesn't contain
any valid device with simple file system protocol and efi_dp_find_obj()
in efi_load_image_from_path() will return NULL.
For instance,
/VenHw(e61d73b9-a384-4acc-aeab-82e828f3628b)/Scsi(0,0)/\helloworld.efi
-> shortened version: /\helloworld.efi
With this patch applied, all the media devices with simple file system
protocol are enumerated and the boot manager attempts to boot temporarily
generated device paths one-by-one.
This new implementation is still a bit incompatible with the UEFI
specification in terms of:
* not creating real boot options
* not try
"If a device does not support the EFI_SIMPLE_FILE_SYSTEM_PROTOCOL, but
supports the EFI_BLOCK_IO_PROTOCOL protocol, then the EFI Boot Service
ConnectController must be called for this device with DriverImageHandle
and RemainingDevicePath set to NULL and the Recursive flag is set to TRUE."
We already have the ConnectController() logic in lib/efi_driver/. We
just have to carry it to all block devices (in a future patch set).
(See section 3.1.2 "Load Option Processing".)
But it still gives us a closer and better solution than the current.
Fixes: commit 9cdf470274ff ("efi_loader: support booting via short-form
device-path")
Signed-off-by: AKASHI Takahiro
---
lib/efi_loader/efi_bootmgr.c | 98 ++--
1 file changed, 94 insertions(+), 4 deletions(-)
diff --git a/lib/efi_loader/efi_bootmgr.c b/lib/efi_loader/efi_bootmgr.c
index 631a25d76e9e..3608e433503e 100644
--- a/lib/efi_loader/efi_bootmgr.c
+++ b/lib/efi_loader/efi_bootmgr.c
@@ -76,6 +76,91 @@ struct efi_device_path *expand_media_path(struct
efi_device_path *device_path)
return full_path;
}
The logic in this patch looks good to me. Just some nits:
Please, provide a description of the function and its parameters.
+static efi_status_t __try_load(efi_handle_t *fs_handles, efi_uintn_t num,
Please, use a name not starting with underscores conveying what the
function is good for, e.g. efi_load_from_file_path().
+ struct efi_device_path *fp,
+ efi_handle_t *handle, bool removable)
+{
+ struct efi_handler *handler;
+ struct efi_device_path *dp;
+ int i;
+ efi_status_t ret;
+
+ for (i = 0; i < num; i++) {
+ if (removable && !efi_disk_is_removable(fs_handles[i]))
+ continue;
+ if (!removable && efi_disk_is_removable(fs_handles[i]))
+ continue;
+
+ ret = efi_search_protocol(fs_handles[i], &efi_guid_device_path,
+ &handler);
+ if (ret != EFI_SUCCESS)
+ /* unlikely */
If you want to tell the compiler that this path is unlikely:
if (unlikely(ret != EFI_SUCCESS))
But as this code is not called often I would simply remove the comment.
+ continue;
+
+ dp = handler->protocol_interface;
+ if (!dp)
+ /* unlikely */
ditto
+ continue;
+
+ dp = efi_dp_append(dp, fp);
You are leaking the original dp here. Please, avoid memory leaks.
+ if (!dp)
+ /* unlikely */
if (unlikely( ?
+ continue;
+
+ ret = EFI_CALL(efi_load_image(true, efi_root, dp, NULL, 0,
+ handle));
+ efi_free_pool(dp);
+ if (ret == EFI_SUCCESS)
+ return ret;
+ }
+
+ return EFI_NOT_FOUND;
+}
+
+/**
+ * try_load_from_short_path
+ * @fp:file path
+ * @handle:pointer to handle for newly installed image
+ *
+ * Enumerate all the devices which support file system operations,
+ * prepend its media device path to the file path, @fp, and
+ * try to load the file.
+ * This function should be called when handling a short-form path
+ * which is starting with a file device path.
+ *
+ * Return: status code
+ */
+static efi_status_t try_load_from_short_path(struct efi_device_path *fp,
+efi_handle_t *handle)
+{
+ efi_handle_t *fs_handles;
+ efi_uintn_t num;
+ efi_status_t ret;
+
+ ret = EFI_CALL(efi_locate_handle_buffer(
+ BY_PROTOCOL,
+ &efi_simple_file_system_protocol_guid,
+ NULL,
+ &num, &fs_handles));
+ if (ret != EFI_SUCCESS)
+ return ret;
+ if (!num)
+ return EFI_NOT_FOUND;
+
+ /* removable media first */
+ ret = __try_load(fs_handles, num, fp, handle, true);
+ if
Re: [PATCH v4 0/3] spi: spi_flash_probe_bus_cs() rely on DT for spi speed and mode
Hi All
This v4 is lying on mailing list since one month and waiting for being
reviewed/merged.
I am not sure this series is delegated to the correct people (Jagan Teki).
As this series is fixing spi-flash performance issue on some platform (STM32MP1
at least)
it would be great if this patchset was merged for v2022.07 release.
Thanks
Patrice
On 4/27/22 11:21, Patrice CHOTARD wrote:
> Hi Jagan
>
> Could you have a look at this series ?
> It would be great if this series can be merged in the v2022.07
>
> Thanks
>
> Patrice
>
>
> On 3/30/22 09:33, Patrice Chotard wrote:
>> Since commit e2e95e5e2542 ("spi: Update speed/mode on change")
>> when calling "sf probe" or "env save" on SPI flash,
>> spi_set_speed_mode() is called twice.
>>
>> spi_get_bus_and_cs()
>> |--> spi_claim_bus()
>> | |--> spi_set_speed_mode(speed and mode from DT)
>> ...
>> |--> spi_set_speed_mode(default speed and mode value)
>>
>> The first spi_set_speed_mode() call is done with speed and mode
>> values from DT, whereas the second call is done with speed
>> and mode set to default value (speed is set to CONFIG_SF_DEFAULT_SPEED)
>>
>> This is an issue because SPI flash performance are impacted by
>> using default speed which can be lower than the one defined in DT.
>>
>> One solution is to set CONFIG_SF_DEFAULT_SPEED to the speed defined
>> in DT, but we loose flexibility offered by DT.
>>
>> Another issue can be encountered with 2 SPI flashes using 2 different
>> speeds. In this specific case usage of CONFIG_SF_DEFAULT_SPEED is not
>> flexible compared to get the 2 different speeds from DT.
>>
>>
>> Changes in v4:
>> - Split previous series in 3 patches
>> - Update commit message with additionnal information
>>
>> Changes in v3:
>> - Update commit header to reflect what the patch really do.
>> - Rename legacy spi_get_bus_and_cs() to _spi_get_bus_and_cs().
>> - New spi_get_bus_and_cs() rely on DT for spi speed and mode values.
>> - spi_flash_probe_bus_cs() rely also on DT for spi and mode values.
>>
>> Changes in v2:
>> - add spi_flash_probe_bus_cs_default() which calls spi_get_bus_and_cs()
>> with "use_dt" param set to true, whereas spi_flash_probe_bus_cs() calls
>> spi_get_bus_and_cs() with "use_dt" param set to true.
>>
>> Patrice Chotard (3):
>> spi: spi-uclass: Add new spi_get_bus_and_cs() implementation
>> spi: spi_flash_probe_bus_cs() rely on DT for spi speed and mode
>> test: dm: spi: Replace _spi_get_bus_and_cs() by spi_get_bus_and_cs()
>> in some case
>>
>> board/CZ.NIC/turris_mox/turris_mox.c | 6 +--
>> cmd/sf.c | 15 +--
>> cmd/spi.c | 4 +-
>> drivers/mtd/spi/sf-uclass.c | 33 +++---
>> drivers/net/fm/fm.c | 4 +-
>> drivers/net/pfe_eth/pfe_firmware.c | 19 ++--
>> drivers/net/sni_netsec.c | 6 +--
>> drivers/spi/spi-uclass.c | 66 +---
>> drivers/usb/gadget/max3420_udc.c | 4 +-
>> env/sf.c | 1 -
>> include/spi.h | 19 +++-
>> include/spi_flash.h | 1 -
>> test/dm/spi.c | 33 +++---
>> 13 files changed, 137 insertions(+), 74 deletions(-)
>>
Re: [PATCH v2 1/2] common: spl: spl_spi: add support for dynamic override of sf bus
Hi Heiko, On 11/05/22 13:54, Heiko Schocher wrote: Hello Achath, On 11.05.22 08:03, Vaishnav Achath wrote: Currently the SPI flash to load from is defined through the compile time config CONFIG_SF_DEFAULT_BUS and CONFIG_SF_DEFAULT_CS, this prevents the loading of binaries from different SPI flash using the same build.E.g. supporting QSPI flash boot and OSPI flash boot on J721E platform is not possible due to this limitation. This commit adds lookup functions spl_spi_boot_bus() and spl_spi_boot_cs for identifying the flash device based on the selected boot device, when not overridden the lookup functions are weakly defined in common/spl/spl_spi.c. Signed-off-by: Vaishnav Achath --- you miss here change history. May you want to look into patman tool in u-boot:/tools/patman/README which can help you here much. Noted, sorry I missed this, will wait for further feedback and include the change history in next revision, please let me know if a v3 with the change history alone fixed is required. common/spl/spl_spi.c | 16 +--- include/spl.h| 16 2 files changed, 29 insertions(+), 3 deletions(-) Looks fine for me, thanks! Reviewed-by: Heiko Schocher Thank you for the review. bye, Heiko -- Regards, Vaishnav
Re: [PATCH v2 1/3] efi_loader: disk: add efi_disk_is_removable()
On 5/12/22 04:29, AKASHI Takahiro wrote:
This helper function will be used to determine if the device is
removable media, initially for handling a short-path loading.
Signed-off-by: AKASHI Takahiro
---
include/efi_loader.h | 3 +++
lib/efi_loader/efi_disk.c | 27 +++
2 files changed, 30 insertions(+)
diff --git a/include/efi_loader.h b/include/efi_loader.h
index 40fbab816e2d..839184acb7ff 100644
--- a/include/efi_loader.h
+++ b/include/efi_loader.h
@@ -659,6 +659,9 @@ efi_status_t efi_set_timer(struct efi_event *event, enum
efi_timer_delay type,
/* Call this to signal an event */
void efi_signal_event(struct efi_event *event);
+/* return true if the device is removable */
+bool efi_disk_is_removable(efi_handle_t handle);
+
/* open file system: */
struct efi_simple_file_system_protocol *efi_simple_file_system(
struct blk_desc *desc, int part, struct efi_device_path *dp);
diff --git a/lib/efi_loader/efi_disk.c b/lib/efi_loader/efi_disk.c
index f5b462fb164a..1e82f52dc070 100644
--- a/lib/efi_loader/efi_disk.c
+++ b/lib/efi_loader/efi_disk.c
@@ -73,6 +73,33 @@ static efi_status_t EFIAPI efi_disk_reset(struct
efi_block_io *this,
return EFI_EXIT(EFI_SUCCESS);
}
+/**
+ * efi_disk_is_removable() - check if the device is removable media
+ * @handle:efi object handle;
+ *
+ * Examine the device and determine if the device is a local block device
+ * and removable media.
+ *
+ * Return: true if removable, false otherwise
+ */
+bool efi_disk_is_removable(efi_handle_t handle)
+{
+ struct efi_handler *handler;
+ struct efi_block_io *io;
+ efi_status_t ret;
+
+ ret = efi_search_protocol(handle, &efi_block_io_guid, &handler);
+ if (ret != EFI_SUCCESS)
+ return false;
+
+ io = handler->protocol_interface;
+
+ if (!io || !io->media)
+ return false;
+
+ return (bool)io->media->removable_media;
Reviewed-by: Heinrich Schuchardt
+}
+
enum efi_disk_direction {
EFI_DISK_READ,
EFI_DISK_WRITE,
[PATCH] arch: arm: mach-k3: am642_init: bring back MCU_PADCFG_MMR1 unlock
Without this register unlock it is not possible to configure the
pinmux used for mcu spi0.
Fixes: 92e46092f2 ("arch: arm: mach-k3: am642_init: Probe ESM nodes")
Signed-off-by: Christian Gmeiner
---
arch/arm/mach-k3/am642_init.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/mach-k3/am642_init.c b/arch/arm/mach-k3/am642_init.c
index add7ea8377..b16de9c9f0 100644
--- a/arch/arm/mach-k3/am642_init.c
+++ b/arch/arm/mach-k3/am642_init.c
@@ -47,6 +47,9 @@ static void ctrl_mmr_unlock(void)
mmr_unlock(CTRL_MMR0_BASE, 3);
mmr_unlock(CTRL_MMR0_BASE, 5);
mmr_unlock(CTRL_MMR0_BASE, 6);
+
+ /* Unlock all MCU_PADCFG_MMR1 module registers */
+ mmr_unlock(MCU_PADCFG_MMR1_BASE, 1);
}
/*
--
2.36.1
Re: [PATCH] i2c: ast_i2c: Remove SCL direct drive mode
Hello Eddie, On 11.05.22 22:52, Eddie James wrote: > SCL direct drive mode prevents communication with devices that > do clock stretching, so disable. The Linux driver doesn't use > this mode, and the engine can handle clock stretching. My first thought was why not make this option configurable, as I do not know if there is any user of this mode configuration. But as linux does not use this option, we may can disable it. > Signed-off-by: Eddie James > --- > drivers/i2c/ast_i2c.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) Reviewed-by: Heiko Schocher It would be good to have here more comments from users of this driver. bye, Heiko -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-52 Fax: +49-8142-66989-80 Email: h...@denx.de
[PATCH v2 3/3] test: efi_bootmgr: add a test case for a short-form path
A short-form path starting with a file device path will be tested in
a new test case.
This type of short-form path will be created with "efidebug boot add -b",
in particular, when a file system has no partition table.
Signed-off-by: AKASHI Takahiro
---
test/py/tests/test_efi_bootmgr/conftest.py| 25 +++
.../test_efi_bootmgr/test_efi_bootmgr.py | 25 +++
2 files changed, 50 insertions(+)
diff --git a/test/py/tests/test_efi_bootmgr/conftest.py
b/test/py/tests/test_efi_bootmgr/conftest.py
index a0a754afbe1b..5cd7252671fa 100644
--- a/test/py/tests/test_efi_bootmgr/conftest.py
+++ b/test/py/tests/test_efi_bootmgr/conftest.py
@@ -38,3 +38,28 @@ def efi_bootmgr_data(u_boot_config):
shell=True)
return image_path
+
+@pytest.fixture(scope='session')
+def efi_bootmgr_data2(u_boot_config):
+"""Set up a file system without a partition table to be used
+ in UEFI bootmanager tests
+
+Args:
+u_boot_config -- U-boot configuration.
+
+Return:
+A path to disk image to be used for testing
+"""
+mnt_point = u_boot_config.persistent_data_dir + '/test_efi_bootmgr'
+image_path = u_boot_config.persistent_data_dir + '/efi_bootmgr_data2.img'
+
+shutil.rmtree(mnt_point, ignore_errors=True)
+os.mkdir(mnt_point, mode = 0o755)
+
+shutil.copyfile(u_boot_config.build_dir + '/lib/efi_loader/helloworld.efi',
+mnt_point + '/helloworld.efi')
+
+check_call(f'virt-make-fs --size=+1M --type=vfat {mnt_point} {image_path}',
+ shell=True)
+
+return image_path
diff --git a/test/py/tests/test_efi_bootmgr/test_efi_bootmgr.py
b/test/py/tests/test_efi_bootmgr/test_efi_bootmgr.py
index 75a6e7c96296..ab3d53a2dc95 100644
--- a/test/py/tests/test_efi_bootmgr/test_efi_bootmgr.py
+++ b/test/py/tests/test_efi_bootmgr/test_efi_bootmgr.py
@@ -41,3 +41,28 @@ def test_efi_bootmgr(u_boot_console, efi_bootmgr_data):
u_boot_console.run_command(cmd = 'efidebug boot rm 0001')
u_boot_console.run_command(cmd = 'efidebug boot rm 0002')
+
+@pytest.mark.boardspec('sandbox')
+@pytest.mark.buildconfigspec('cmd_efidebug')
+@pytest.mark.buildconfigspec('cmd_bootefi_bootmgr')
+def test_efi_bootmgr_short(u_boot_console, efi_bootmgr_data2):
+""" Unit test for UEFI bootmanager with a short-form path
+In this test case,
+- File system has no partition table
+- UEFI load option has a short-form path starting with a file device path
+
+Args:
+u_boot_console -- U-Boot console
+efi_bootmgr_data2 -- Path to the disk image used for testing.
+"""
+u_boot_console.run_command(cmd = f'host bind 0 {efi_bootmgr_data2}')
+
+u_boot_console.run_command(cmd = 'efidebug boot add ' \
+'-b 0001 TEST2 host 0:0 helloworld.efi')
+response = u_boot_console.run_command(cmd = 'efidebug boot dump')
+assert 'file_path: /helloworld.efi' in response
+u_boot_console.run_command(cmd = 'efidebug boot next 0001')
+response = u_boot_console.run_command(cmd = 'bootefi bootmgr')
+assert 'Hello, world!' in response
+
+u_boot_console.run_command(cmd = 'efidebug boot rm 0001')
--
2.33.0
[PATCH v2 2/3] efi_loader: bootmgr: fix a problem in loading an image from a short-path
Booting from a short-form device path which starts with the first element
being a File Path Media Device Path failed because it doesn't contain
any valid device with simple file system protocol and efi_dp_find_obj()
in efi_load_image_from_path() will return NULL.
For instance,
/VenHw(e61d73b9-a384-4acc-aeab-82e828f3628b)/Scsi(0,0)/\helloworld.efi
-> shortened version: /\helloworld.efi
With this patch applied, all the media devices with simple file system
protocol are enumerated and the boot manager attempts to boot temporarily
generated device paths one-by-one.
This new implementation is still a bit incompatible with the UEFI
specification in terms of:
* not creating real boot options
* not try
"If a device does not support the EFI_SIMPLE_FILE_SYSTEM_PROTOCOL, but
supports the EFI_BLOCK_IO_PROTOCOL protocol, then the EFI Boot Service
ConnectController must be called for this device with DriverImageHandle
and RemainingDevicePath set to NULL and the Recursive flag is set to TRUE."
(See section 3.1.2 "Load Option Processing".)
But it still gives us a closer and better solution than the current.
Fixes: commit 9cdf470274ff ("efi_loader: support booting via short-form
device-path")
Signed-off-by: AKASHI Takahiro
---
lib/efi_loader/efi_bootmgr.c | 98 ++--
1 file changed, 94 insertions(+), 4 deletions(-)
diff --git a/lib/efi_loader/efi_bootmgr.c b/lib/efi_loader/efi_bootmgr.c
index 631a25d76e9e..3608e433503e 100644
--- a/lib/efi_loader/efi_bootmgr.c
+++ b/lib/efi_loader/efi_bootmgr.c
@@ -76,6 +76,91 @@ struct efi_device_path *expand_media_path(struct
efi_device_path *device_path)
return full_path;
}
+static efi_status_t __try_load(efi_handle_t *fs_handles, efi_uintn_t num,
+ struct efi_device_path *fp,
+ efi_handle_t *handle, bool removable)
+{
+ struct efi_handler *handler;
+ struct efi_device_path *dp;
+ int i;
+ efi_status_t ret;
+
+ for (i = 0; i < num; i++) {
+ if (removable && !efi_disk_is_removable(fs_handles[i]))
+ continue;
+ if (!removable && efi_disk_is_removable(fs_handles[i]))
+ continue;
+
+ ret = efi_search_protocol(fs_handles[i], &efi_guid_device_path,
+ &handler);
+ if (ret != EFI_SUCCESS)
+ /* unlikely */
+ continue;
+
+ dp = handler->protocol_interface;
+ if (!dp)
+ /* unlikely */
+ continue;
+
+ dp = efi_dp_append(dp, fp);
+ if (!dp)
+ /* unlikely */
+ continue;
+
+ ret = EFI_CALL(efi_load_image(true, efi_root, dp, NULL, 0,
+ handle));
+ efi_free_pool(dp);
+ if (ret == EFI_SUCCESS)
+ return ret;
+ }
+
+ return EFI_NOT_FOUND;
+}
+
+/**
+ * try_load_from_short_path
+ * @fp:file path
+ * @handle:pointer to handle for newly installed image
+ *
+ * Enumerate all the devices which support file system operations,
+ * prepend its media device path to the file path, @fp, and
+ * try to load the file.
+ * This function should be called when handling a short-form path
+ * which is starting with a file device path.
+ *
+ * Return: status code
+ */
+static efi_status_t try_load_from_short_path(struct efi_device_path *fp,
+efi_handle_t *handle)
+{
+ efi_handle_t *fs_handles;
+ efi_uintn_t num;
+ efi_status_t ret;
+
+ ret = EFI_CALL(efi_locate_handle_buffer(
+ BY_PROTOCOL,
+ &efi_simple_file_system_protocol_guid,
+ NULL,
+ &num, &fs_handles));
+ if (ret != EFI_SUCCESS)
+ return ret;
+ if (!num)
+ return EFI_NOT_FOUND;
+
+ /* removable media first */
+ ret = __try_load(fs_handles, num, fp, handle, true);
+ if (ret == EFI_SUCCESS)
+ goto out;
+
+ /* fixed media */
+ ret = __try_load(fs_handles, num, fp, handle, false);
+ if (ret == EFI_SUCCESS)
+ goto out;
+
+out:
+ return ret;
+}
+
/**
* try_load_entry() - try to load image for boot option
*
@@ -116,10 +201,15 @@ static efi_status_t try_load_entry(u16 n, efi_handle_t
*handle,
log_debug("trying to load \"%ls\" from %pD\n", lo.label,
lo.file_path);
- file_path = expand_media_path(lo.file_path);
- ret = EFI_CALL(efi_load_image(true, efi_root, file_path,
- NULL, 0, handle));
- efi_free_pool(file_pa
[PATCH v2 1/3] efi_loader: disk: add efi_disk_is_removable()
This helper function will be used to determine if the device is
removable media, initially for handling a short-path loading.
Signed-off-by: AKASHI Takahiro
---
include/efi_loader.h | 3 +++
lib/efi_loader/efi_disk.c | 27 +++
2 files changed, 30 insertions(+)
diff --git a/include/efi_loader.h b/include/efi_loader.h
index 40fbab816e2d..839184acb7ff 100644
--- a/include/efi_loader.h
+++ b/include/efi_loader.h
@@ -659,6 +659,9 @@ efi_status_t efi_set_timer(struct efi_event *event, enum
efi_timer_delay type,
/* Call this to signal an event */
void efi_signal_event(struct efi_event *event);
+/* return true if the device is removable */
+bool efi_disk_is_removable(efi_handle_t handle);
+
/* open file system: */
struct efi_simple_file_system_protocol *efi_simple_file_system(
struct blk_desc *desc, int part, struct efi_device_path *dp);
diff --git a/lib/efi_loader/efi_disk.c b/lib/efi_loader/efi_disk.c
index f5b462fb164a..1e82f52dc070 100644
--- a/lib/efi_loader/efi_disk.c
+++ b/lib/efi_loader/efi_disk.c
@@ -73,6 +73,33 @@ static efi_status_t EFIAPI efi_disk_reset(struct
efi_block_io *this,
return EFI_EXIT(EFI_SUCCESS);
}
+/**
+ * efi_disk_is_removable() - check if the device is removable media
+ * @handle:efi object handle;
+ *
+ * Examine the device and determine if the device is a local block device
+ * and removable media.
+ *
+ * Return: true if removable, false otherwise
+ */
+bool efi_disk_is_removable(efi_handle_t handle)
+{
+ struct efi_handler *handler;
+ struct efi_block_io *io;
+ efi_status_t ret;
+
+ ret = efi_search_protocol(handle, &efi_block_io_guid, &handler);
+ if (ret != EFI_SUCCESS)
+ return false;
+
+ io = handler->protocol_interface;
+
+ if (!io || !io->media)
+ return false;
+
+ return (bool)io->media->removable_media;
+}
+
enum efi_disk_direction {
EFI_DISK_READ,
EFI_DISK_WRITE,
--
2.33.0
[PATCH v2 0/3] efi_loader: bootmgr: fix a problem in loading an image from a short-path
This is a reworked version of v1[1]. If a (root) file system does not have any partition table, the generated boot option (BOOT) by the command, => efidebug boot add -b ... does not work because a device path in the option is in a short-form and does not contain any valid media device path which should expectedly support EFI_SIMPLE_FILE_SYSTEM_PROTOCOL. [1] https://lists.denx.de/pipermail/u-boot/2022-April/482697.html Test: = * Azure CI passed[2] [2] https://dev.azure.com/u-boot/u-boot/_build/results?buildId=4220&view=results TODO: = The other types of short-form device paths, USB_CLASS and HARD_DRIVE, should also be implemented in boot manager rather than LoadImage API so as to more properly comply with the UEFI specification. See "3.1.2 Load Option Processing". Change history: === v2 (May, 12, 2022) * fully re-write the code to implement the feature in boot manager (patch#2) * try removable media first (patch#1,#2) * add a test case (patch#3) v1 (Apr 28, 2022) * initial patch AKASHI Takahiro (3): efi_loader: disk: add efi_disk_is_removable() efi_loader: bootmgr: fix a problem in loading an image from a short-path test: efi_bootmgr: add a test case for a short-form path include/efi_loader.h | 3 + lib/efi_loader/efi_bootmgr.c | 98 ++- lib/efi_loader/efi_disk.c | 27 + test/py/tests/test_efi_bootmgr/conftest.py| 25 + .../test_efi_bootmgr/test_efi_bootmgr.py | 25 + 5 files changed, 174 insertions(+), 4 deletions(-) -- 2.33.0
[PATCH 7/8] net: add MV88E61xx DSA driver
Add a DSA driver for the MV88E61xx compatible GbE Ethernet switches. Cc: Marek Behún Cc: Vladimir Oltean Signed-off-by: Tim Harvey --- v2: - rebase on v2022.07-rc1 (use ofnode_get_phy_node) - remove unused commented out fields from struct - remove unused PORT_MASK macro - remove phy from priv struct name - refactor code from original drivers/net/phy/mv88e61xx with suggestions from review to consolidate some functions into mv88e61xx_dsa_port_enable - remove unecessary skiping of disabling of CPU port - remove unecessary dev_set_parent_priv - remove unnecessary static init flag - replace debug with a dev_warn if switch device-id unsupported - remove unnecessary xmit/recv functions as we rely on the fact that only a single port is active instead of mangling packets --- drivers/net/Kconfig | 7 + drivers/net/Makefile| 1 + drivers/net/mv88e61xx.c | 843 3 files changed, 851 insertions(+) create mode 100644 drivers/net/mv88e61xx.c diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 7fe0e00649cf..edb1a0898986 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -433,6 +433,13 @@ config LPC32XX_ETH depends on ARCH_LPC32XX default y +config MV88E61XX + bool "Marvell MV88E61xx GbE switch DSA driver" + depends on DM_DSA && DM_MDIO + help + This driver implements a DSA switch driver for the MV88E61xx family + of GbE switches using the MDIO interface + config MVGBE bool "Marvell Orion5x/Kirkwood network interface support" depends on ARCH_KIRKWOOD || ARCH_ORION5X diff --git a/drivers/net/Makefile b/drivers/net/Makefile index 69fb3bbbf7cb..36b4c279430a 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -59,6 +59,7 @@ obj-$(CONFIG_MEDIATEK_ETH) += mtk_eth.o obj-$(CONFIG_MPC8XX_FEC) += mpc8xx_fec.o obj-$(CONFIG_MT7620_ETH) += mt7620-eth.o obj-$(CONFIG_MT7628_ETH) += mt7628-eth.o +obj-$(CONFIG_MV88E61XX) += mv88e61xx.o obj-$(CONFIG_MVGBE) += mvgbe.o obj-$(CONFIG_MVMDIO) += mvmdio.o obj-$(CONFIG_MVNETA) += mvneta.o diff --git a/drivers/net/mv88e61xx.c b/drivers/net/mv88e61xx.c new file mode 100644 index ..514835bf03b9 --- /dev/null +++ b/drivers/net/mv88e61xx.c @@ -0,0 +1,843 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2022 + * Gateworks Corporation + * Tim Harvey + * + * (C) Copyright 2015 + * Elecsys Corporation + * Kevin Smith + * + * Original driver: + * (C) Copyright 2009 + * Marvell Semiconductor + * Prafulla Wadaskar + */ + +/* + * DSA driver for mv88e61xx ethernet switches. + * + * This driver configures the mv88e61xx for basic use as a DSA switch. + * + * This driver was adapted from drivers/net/phy/mv88e61xx and tested + * on the mv88e6176 via an SGMII interface. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Device addresses */ +#define DEVADDR_PHY(p) (p) +#define DEVADDR_SERDES 0x0F + +/* SMI indirection registers for multichip addressing mode */ +#define SMI_CMD_REG0x00 +#define SMI_DATA_REG 0x01 + +/* Global registers */ +#define GLOBAL1_STATUS 0x00 +#define GLOBAL1_CTRL 0x04 +#define GLOBAL1_MON_CTRL 0x1A + +/* Global 2 registers */ +#define GLOBAL2_REG_PHY_CMD0x18 +#define GLOBAL2_REG_PHY_DATA 0x19 +#define GLOBAL2_REG_SCRATCH0x1A + +/* Port registers */ +#define PORT_REG_STATUS0x00 +#define PORT_REG_PHYS_CTRL 0x01 +#define PORT_REG_SWITCH_ID 0x03 +#define PORT_REG_CTRL 0x04 +#define PORT_REG_VLAN_MAP 0x06 +#define PORT_REG_VLAN_ID 0x07 +#define PORT_REG_LED_CTRL 0x16 + +/* Phy registers */ +#define PHY_REG_CTRL1 0x10 +#define PHY_REG_STATUS10x11 +#define PHY_REG_PAGE 0x16 + +/* Serdes registers */ +#define SERDES_REG_CTRL_1 0x10 + +/* Phy page numbers */ +#define PHY_PAGE_COPPER0 +#define PHY_PAGE_SERDES1 + +/* Register fields */ +#define GLOBAL1_CTRL_SWRESET BIT(15) + +#define GLOBAL1_MON_CTRL_CPUDEST_SHIFT 4 +#define GLOBAL1_MON_CTRL_CPUDEST_WIDTH 4 + +#define PORT_REG_STATUS_SPEED_SHIFT8 +#define PORT_REG_STATUS_SPEED_10 0 +#define PORT_REG_STATUS_SPEED_100 1 +#define PORT_REG_STATUS_SPEED_1000 2 + +#define PORT_REG_STATUS_CMODE_MASK 0xF +#define PORT_REG_STATUS_CMODE_100BASE_X0x8 +#define PORT_REG_STATUS_CMODE_1000BASE_X 0x9 +#define PORT_REG_STATUS_CMODE_SGMII0xa + +#define PORT_REG_PHYS_CTRL_RGMII_DELAY_RXCLK BIT(15) +#define PORT_REG_PHYS_CTRL_RGMII_DELAY_TXCLK BIT(14) +#define PORT_REG_PHYS_CTRL_PCS_AN_EN BIT(10) +#define PORT_REG_PHYS_CTRL_PCS_AN_RST BIT(9
[PATCH 8/8] board: gw_ventana: enable MV88E61XX DSA support
Add MV88E61XX DSA support:
- update dt: U-Boot dsa driver requires different device-tree syntax
than the linux driver in order to link the dsa ports to the mdio bus.
- update defconfig
- replace mv88e61xx_hw_reset weak override with board_phy_config support
for mv88e61xx configuration that is outside the scope of the DSA driver
Signed-off-by: Tim Harvey
---
v2: no changes
---
arch/arm/dts/imx6qdl-gw5904.dtsi| 35 +
board/gateworks/gw_ventana/gw_ventana.c | 50 +
configs/gwventana_gw5904_defconfig | 7 ++--
3 files changed, 56 insertions(+), 36 deletions(-)
diff --git a/arch/arm/dts/imx6qdl-gw5904.dtsi b/arch/arm/dts/imx6qdl-gw5904.dtsi
index 286c7a9924c2..63590a2debc7 100644
--- a/arch/arm/dts/imx6qdl-gw5904.dtsi
+++ b/arch/arm/dts/imx6qdl-gw5904.dtsi
@@ -219,6 +219,27 @@
compatible = "marvell,mv88e6085";
reg = <0>;
+ mdios {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ sw_phy0: ethernet-phy@0 {
+ reg = <0x0>;
+ };
+
+ sw_phy1: ethernet-phy@1 {
+ reg = <0x1>;
+ };
+
+ sw_phy2: ethernet-phy@2 {
+ reg = <0x2>;
+ };
+
+ sw_phy3: ethernet-phy@3 {
+ reg = <0x3>;
+ };
+ };
+
ports {
#address-cells = <1>;
#size-cells = <0>;
@@ -226,27 +247,41 @@
port@0 {
reg = <0>;
label = "lan4";
+ phy-mode = "internal";
+ phy-handle = <&sw_phy0>;
};
port@1 {
reg = <1>;
label = "lan3";
+ phy-mode = "internal";
+ phy-handle = <&sw_phy1>;
};
port@2 {
reg = <2>;
label = "lan2";
+ phy-mode = "internal";
+ phy-handle = <&sw_phy2>;
};
port@3 {
reg = <3>;
label = "lan1";
+ phy-mode = "internal";
+ phy-handle = <&sw_phy3>;
};
port@5 {
reg = <5>;
label = "cpu";
ethernet = <&fec>;
+ phy-mode = "rgmii-id";
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
};
};
};
diff --git a/board/gateworks/gw_ventana/gw_ventana.c
b/board/gateworks/gw_ventana/gw_ventana.c
index c06630a66b66..bef3f7ef0d2b 100644
--- a/board/gateworks/gw_ventana/gw_ventana.c
+++ b/board/gateworks/gw_ventana/gw_ventana.c
@@ -68,44 +68,30 @@ int board_phy_config(struct phy_device *phydev)
phy_write(phydev, MDIO_DEVAD_NONE, 14, val);
}
+ /* Fixed PHY: for GW5904/GW5909 this is Marvell 88E6176 GbE Switch */
+ else if (phydev->phy_id == 0xa5a55a5a &&
+((board_type == GW5904) || (board_type == GW5909))) {
+ struct mii_dev *bus = miiphy_get_dev_by_name("mdio");
+
+ puts("MV88E61XX ");
+ /* GPIO[0] output CLK125 for RGMII_REFCLK */
+ bus->write(bus, 0x1c, 0, 0x1a, (1 << 15) | (0x62 << 8) | 0xfe);
+ bus->write(bus, 0x1c, 0, 0x1a, (1 << 15) | (0x68 << 8) | 7);
+
+ /* Port 0-3 LED configuration: Table 80/82 */
+ /* LED configuration: 7:4-green (8=Activity) 3:0 amber
(8=Link) */
+ bus->write(bus, 0x10, 0, 0x16, 0x8088);
+ bus->write(bus, 0x11, 0, 0x16, 0x8088);
+ bus->write(bus, 0x12, 0, 0x16, 0x8088);
+ bus->write(bus, 0x13, 0, 0x16, 0x8088);
+ }
+
if (phydev->drv->config)
[PATCH 6/8] net: fec: add support for DM_MDIO
Add support for DM_MDIO by registering a UCLASS_MDIO driver and
attempting to use it. This is necessary if wanting to use a DSA
driver for example hanging off of the FEC MAC.
Care is taken to fallback to non DM_MDIO mii bus as several boards define
DM_MDIO without having the proper device-tree configuration necessary
such as an mdio subnode, a phy-mode prop, and either a valid phy-handle
prop or fixed-phy subnode which will cause dm_eth_phy_connect() to fail.
Signed-off-by: Tim Harvey
---
v2:
- fix fallback mechanism for legacy dt's that do not have phy-handle
and mdio subnode
---
drivers/net/fec_mxc.c | 90 ++-
1 file changed, 88 insertions(+), 2 deletions(-)
diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
index a623a5c45e4d..9553699e3306 100644
--- a/drivers/net/fec_mxc.c
+++ b/drivers/net/fec_mxc.c
@@ -30,6 +30,8 @@
#include
#include
#include
+#include
+#include
#include "fec_mxc.h"
#include
@@ -1025,6 +1027,81 @@ struct mii_dev *fec_get_miibus(ulong base_addr, int
dev_id)
return bus;
}
+#ifdef CONFIG_DM_MDIO
+struct dm_fec_mdio_priv {
+ struct ethernet_regs *regs;
+};
+
+static int dm_fec_mdio_read(struct udevice *dev, int addr, int devad, int reg)
+{
+ struct dm_fec_mdio_priv *priv = dev_get_priv(dev);
+
+ return fec_mdio_read(priv->regs, addr, reg);
+}
+
+static int dm_fec_mdio_write(struct udevice *dev, int addr, int devad, int
reg, u16 data)
+{
+ struct dm_fec_mdio_priv *priv = dev_get_priv(dev);
+
+ return fec_mdio_write(priv->regs, addr, reg, data);
+}
+
+static const struct mdio_ops dm_fec_mdio_ops = {
+ .read = dm_fec_mdio_read,
+ .write = dm_fec_mdio_write,
+};
+
+static int dm_fec_mdio_probe(struct udevice *dev)
+{
+ struct dm_fec_mdio_priv *priv = dev_get_priv(dev);
+
+ priv->regs = (struct ethernet_regs
*)ofnode_get_addr(dev_ofnode(dev->parent));
+
+ return 0;
+}
+
+U_BOOT_DRIVER(fec_mdio) = {
+ .name = "fec_mdio",
+ .id = UCLASS_MDIO,
+ .probe = dm_fec_mdio_probe,
+ .ops= &dm_fec_mdio_ops,
+ .priv_auto = sizeof(struct dm_fec_mdio_priv),
+};
+
+static int dm_fec_bind_mdio(struct udevice *dev)
+{
+ struct udevice *mdiodev;
+ const char *name;
+ ofnode mdio;
+ int ret = -ENODEV;
+
+ /* for a UCLASS_MDIO driver we need to bind and probe manually
+* for an internal MDIO bus that has no dt compatible of its own
+*/
+ ofnode_for_each_subnode(mdio, dev_ofnode(dev)) {
+ name = ofnode_get_name(mdio);
+
+ if (strcmp(name, "mdio"))
+ continue;
+
+ ret = device_bind_driver_to_node(dev, "fec_mdio",
+name, mdio, &mdiodev);
+ if (ret) {
+ printf("%s bind %s failed: %d\n", __func__, name, ret);
+ break;
+ }
+
+ /* need to probe it as there is no compatible to do so */
+ ret = uclass_get_device_by_ofnode(UCLASS_MDIO, mdio, &mdiodev);
+ if (!ret)
+ return 0;
+ printf("%s probe %s failed: %d\n", __func__, name, ret);
+ }
+
+ return ret;
+}
+#endif
+
static int fecmxc_read_rom_hwaddr(struct udevice *dev)
{
struct fec_priv *priv = dev_get_priv(dev);
@@ -1088,7 +1165,7 @@ static int device_get_phy_addr(struct fec_priv *priv,
struct udevice *dev)
static int fec_phy_init(struct fec_priv *priv, struct udevice *dev)
{
- struct phy_device *phydev;
+ struct phy_device *phydev = NULL;
int addr;
addr = device_get_phy_addr(priv, dev);
@@ -1096,7 +1173,10 @@ static int fec_phy_init(struct fec_priv *priv, struct
udevice *dev)
addr = CONFIG_FEC_MXC_PHYADDR;
#endif
- phydev = phy_connect(priv->bus, addr, dev, priv->interface);
+ if (IS_ENABLED(CONFIG_DM_MDIO))
+ phydev = dm_eth_phy_connect(dev);
+ if (!phydev)
+ phydev = phy_connect(priv->bus, addr, dev, priv->interface);
if (!phydev)
return -ENODEV;
@@ -1227,6 +1307,12 @@ static int fecmxc_probe(struct udevice *dev)
priv->dev_id = dev_seq(dev);
+ if (IS_ENABLED(CONFIG_DM_MDIO)) {
+ ret = dm_fec_bind_mdio(dev);
+ if (ret && ret != -ENODEV)
+ return ret;
+ }
+
#ifdef CONFIG_DM_ETH_PHY
bus = eth_phy_get_mdio_bus(dev);
#endif
--
2.17.1
[PATCH 3/8] net: dsa: ensure dsa driver has proper ops
Add a function to sanity check a dsa driver having proper ops.
Suggested-by: Vladimir Oltean
Signed-off-by: Tim Harvey
---
v2: new patch
---
net/dsa-uclass.c | 17 +
1 file changed, 17 insertions(+)
diff --git a/net/dsa-uclass.c b/net/dsa-uclass.c
index 07edc584daf3..b3033c97aa63 100644
--- a/net/dsa-uclass.c
+++ b/net/dsa-uclass.c
@@ -342,6 +342,19 @@ U_BOOT_DRIVER(dsa_port) = {
.plat_auto = sizeof(struct eth_pdata),
};
+static int dsa_sanitize_ops(struct udevice *dev)
+{
+ struct dsa_ops *ops = dsa_get_ops(dev);
+
+ if ((!ops->xmit || !ops->rcv) &&
+ (!ops->port_enable && !ops->port_disable)) {
+ dev_err(dev, "Packets cannot be steered to ports\n");
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
/*
* This function mostly deals with pulling information out of the device tree
* into the pdata structure.
@@ -358,6 +371,10 @@ static int dsa_post_bind(struct udevice *dev)
if (!ofnode_valid(node))
return -ENODEV;
+ err = dsa_sanitize_ops(dev);
+ if (err)
+ return err;
+
pdata->master_node = ofnode_null();
node = ofnode_find_subnode(node, "ports");
--
2.17.1
[PATCH 4/8] net: dsa: allow rcv() and xmit() to be optional
Allow rcv() and xmit() dsa driver ops to be optional in case a driver
does not care to mangle a packet as in U-Boot only one network port is
enabled at a time and thus no packet mangling is necessary.
Suggested-by: Vladimir Oltean
Signed-off-by: Tim Harvey
---
v2: new patch
---
net/dsa-uclass.c | 27 ++-
1 file changed, 18 insertions(+), 9 deletions(-)
diff --git a/net/dsa-uclass.c b/net/dsa-uclass.c
index b3033c97aa63..f82217e0d7a7 100644
--- a/net/dsa-uclass.c
+++ b/net/dsa-uclass.c
@@ -131,16 +131,14 @@ static void dsa_port_stop(struct udevice *pdev)
* We copy the frame to a stack buffer where we have reserved headroom and
* tailroom space. Headroom and tailroom are set to 0.
*/
-static int dsa_port_send(struct udevice *pdev, void *packet, int length)
+static int dsa_port_mangle_packet(struct udevice *pdev, void *packet, int
length)
{
+ struct dsa_port_pdata *port_pdata = dev_get_parent_plat(pdev);
struct udevice *dev = dev_get_parent(pdev);
struct dsa_priv *priv = dev_get_uclass_priv(dev);
int head = priv->headroom, tail = priv->tailroom;
- struct udevice *master = dsa_get_master(dev);
struct dsa_ops *ops = dsa_get_ops(dev);
uchar dsa_packet_tmp[PKTSIZE_ALIGN];
- struct dsa_port_pdata *port_pdata;
- int err;
if (length + head + tail > PKTSIZE_ALIGN)
return -EINVAL;
@@ -152,10 +150,21 @@ static int dsa_port_send(struct udevice *pdev, void
*packet, int length)
/* copy back to preserve original buffer alignment */
memcpy(packet, dsa_packet_tmp, length);
- port_pdata = dev_get_parent_plat(pdev);
- err = ops->xmit(dev, port_pdata->index, packet, length);
- if (err)
- return err;
+ return ops->xmit(dev, port_pdata->index, packet, length);
+}
+
+static int dsa_port_send(struct udevice *pdev, void *packet, int length)
+{
+ struct udevice *dev = dev_get_parent(pdev);
+ struct udevice *master = dsa_get_master(dev);
+ struct dsa_ops *ops = dsa_get_ops(dev);
+ int err;
+
+ if (ops->xmit) {
+ err = dsa_port_mangle_packet(pdev, packet, length);
+ if (err)
+ return err;
+ }
return eth_get_ops(master)->send(master, packet, length);
}
@@ -172,7 +181,7 @@ static int dsa_port_recv(struct udevice *pdev, int flags,
uchar **packetp)
int length, port_index, err;
length = eth_get_ops(master)->recv(master, flags, packetp);
- if (length <= 0)
+ if (length <= 0 || !ops->rcv)
return length;
/*
--
2.17.1
[PATCH v2 0/8] Add MV88E61xx DSA driver and use on gwventana
This series adds a DSA driver for the MV88E61xx based on drivers/net/phy/mv88e61xx and uses in on the gwventana_gw5904_defconfig. The hope is that the other three boards that use the MV88E61xx driver can move to this as well eventually so that we can remove the non-dm driver and the 4 Kconfig options it requires. The MV88E61xx has an MDIO interface thus DM_MDIO must be used so support for a UCLASS_MDIO driver is added to the fec_mxc ethernet driver in a way that allows a fallback to the previous non DM_MDIO case as there are many boards out there using this driver that define DM_MDIO but do not have the required dt props for a DM_MDIO driver which would cause a regression. Additionally some other patches are here suggested by Vladimir: - ensure MDIO children are scanned on post-bind is needed - sanity check DSA driver required ops are present - allow DSA drivers to not require xmit/recv functions - remove unecessary xmit/recv functions from ksz9477 driver v2: - added Ramon's rb tag's to first two patches - add patches for dsa-uclass to sanity check ops and make xmit/recv optional - fec: fix fallback for non conforming DM_MDIO dts - mv88e61xx: - rebase on v2022.07-rc2 (use ofnode_get_phy_node) - remove unused commented out fields from struct - remove unused PORT_MASK macro - remove phy from priv struct name - refactor code from original drivers/net/phy/mv88e61xx with suggestions from review to consolidate some functions into mv88e61xx_dsa_port_enable - remove unecessary skiping of disabling of CPU port - remove unecessary dev_set_parent_priv - remove unnecessary static init flag - replace debug with a dev_warn if switch device-id unsupported - remove unnecessary xmit/recv functions as we rely on the fact that only a single port is active instead of mangling packets Tested on a Gateworks GW5904 which has a Marvell 88E6176 switch hanging off the IMX6 FEC. Best Regards, Tim Tim Harvey (8): net: mdio-uclass: scan for dm mdio children on post-bind net: dsa: move cpu port probe to dsa_post_probe net: dsa: ensure dsa driver has proper ops net: dsa: allow rcv() and xmit() to be optional net: ksz9477: remove unnecessary xmit and recv functions net: fec: add support for DM_MDIO net: add MV88E61xx DSA driver board: gw_ventana: enable MV88E61XX DSA support arch/arm/dts/imx6qdl-gw5904.dtsi| 35 + board/gateworks/gw_ventana/gw_ventana.c | 50 +- configs/gwventana_gw5904_defconfig | 7 +- drivers/net/Kconfig | 7 + drivers/net/Makefile| 1 + drivers/net/fec_mxc.c | 90 ++- drivers/net/ksz9477.c | 23 - drivers/net/mv88e61xx.c | 843 net/dsa-uclass.c| 58 +- net/mdio-uclass.c | 4 + 10 files changed, 1045 insertions(+), 73 deletions(-) create mode 100644 drivers/net/mv88e61xx.c -- 2.17.1
[PATCH 5/8] net: ksz9477: remove unnecessary xmit and recv functions
Remove the unnecessary xmit and recv functions.
Signed-off-by: Tim Harvey
---
v2: new patch
---
drivers/net/ksz9477.c | 23 ---
1 file changed, 23 deletions(-)
diff --git a/drivers/net/ksz9477.c b/drivers/net/ksz9477.c
index ed8f1895cb12..fb5c76c600be 100644
--- a/drivers/net/ksz9477.c
+++ b/drivers/net/ksz9477.c
@@ -62,7 +62,6 @@
struct ksz_dsa_priv {
struct udevice *dev;
- int active_port;
};
static inline int ksz_read8(struct udevice *dev, u32 reg, u8 *val)
@@ -382,9 +381,6 @@ static int ksz_port_enable(struct udevice *dev, int port,
struct phy_device *phy
data8 |= SW_START;
ksz_write8(priv->dev, REG_SW_OPERATION, data8);
- /* keep track of current enabled non-cpu port */
- priv->active_port = port;
-
return 0;
}
@@ -413,28 +409,9 @@ static void ksz_port_disable(struct udevice *dev, int
port, struct phy_device *p
*/
}
-static int ksz_xmit(struct udevice *dev, int port, void *packet, int length)
-{
- dev_dbg(dev, "%s P%d %d\n", __func__, port + 1, length);
-
- return 0;
-}
-
-static int ksz_recv(struct udevice *dev, int *port, void *packet, int length)
-{
- struct ksz_dsa_priv *priv = dev_get_priv(dev);
-
- dev_dbg(dev, "%s P%d %d\n", __func__, priv->active_port + 1, length);
- *port = priv->active_port;
-
- return 0;
-};
-
static const struct dsa_ops ksz_dsa_ops = {
.port_enable = ksz_port_enable,
.port_disable = ksz_port_disable,
- .xmit = ksz_xmit,
- .rcv = ksz_recv,
};
static int ksz_probe_mdio(struct udevice *dev)
--
2.17.1
[PATCH 2/8] net: dsa: move cpu port probe to dsa_post_probe
In order to ensure that a DSA driver probe gets called before
dsa_ops->port_probe move the port_probe of the cpu_port to
a post-probe function.
Signed-off-by: Tim Harvey
Reviewed-by: Ramon Fried
---
v2:
- added Ramon's rb tag
---
net/dsa-uclass.c | 14 +++---
1 file changed, 11 insertions(+), 3 deletions(-)
diff --git a/net/dsa-uclass.c b/net/dsa-uclass.c
index 9ff55a02fb23..07edc584daf3 100644
--- a/net/dsa-uclass.c
+++ b/net/dsa-uclass.c
@@ -466,8 +466,6 @@ static int dsa_pre_probe(struct udevice *dev)
{
struct dsa_pdata *pdata = dev_get_uclass_plat(dev);
struct dsa_priv *priv = dev_get_uclass_priv(dev);
- struct dsa_ops *ops = dsa_get_ops(dev);
- int err;
priv->num_ports = pdata->num_ports;
priv->cpu_port = pdata->cpu_port;
@@ -480,6 +478,15 @@ static int dsa_pre_probe(struct udevice *dev)
uclass_find_device_by_ofnode(UCLASS_ETH, pdata->master_node,
&priv->master_dev);
+ return 0;
+}
+
+static int dsa_post_probe(struct udevice *dev)
+{
+ struct dsa_priv *priv = dev_get_uclass_priv(dev);
+ struct dsa_ops *ops = dsa_get_ops(dev);
+ int err;
+
/* Simulate a probing event for the CPU port */
if (ops->port_probe) {
err = ops->port_probe(dev, priv->cpu_port,
@@ -489,13 +496,14 @@ static int dsa_pre_probe(struct udevice *dev)
}
return 0;
-}
+};
UCLASS_DRIVER(dsa) = {
.id = UCLASS_DSA,
.name = "dsa",
.post_bind = dsa_post_bind,
.pre_probe = dsa_pre_probe,
+ .post_probe = dsa_post_probe,
.per_device_auto = sizeof(struct dsa_priv),
.per_device_plat_auto = sizeof(struct dsa_pdata),
.per_child_plat_auto = sizeof(struct dsa_port_pdata),
--
2.17.1
[PATCH 1/8] net: mdio-uclass: scan for dm mdio children on post-bind
If a DM_MDIO driver is used we need to scan the subnodes as well. Signed-off-by: Tim Harvey Signed-off-by: Vladimir Oltean Reviewed-by: Ramon Fried --- v2: - added Ramon's rb tag --- net/mdio-uclass.c | 4 1 file changed, 4 insertions(+) diff --git a/net/mdio-uclass.c b/net/mdio-uclass.c index 4401492ca015..d80037d0ac71 100644 --- a/net/mdio-uclass.c +++ b/net/mdio-uclass.c @@ -49,7 +49,11 @@ static int dm_mdio_post_bind(struct udevice *dev) return -EINVAL; } +#if CONFIG_IS_ENABLED(OF_REAL) + return dm_scan_fdt_dev(dev); +#else return 0; +#endif } int dm_mdio_read(struct udevice *mdio_dev, int addr, int devad, int reg) -- 2.17.1
[PATCH v2] Add SCSI scan for ENV in EXT4 or FAT
From: Rogier Stam When having environment stored in EXT4 or FAT and using an AHCI or SCSI device / partition the scan would not be performed early enough and hence the device would not be recognized. This change adds the scan when the interface is "scsi" in a similar way to mmc_initialize. Signed-off-by: Rogier Stam Reviewed-by: Pali Rohár --- env/ext4.c | 5 + env/fat.c | 8 +++- 2 files changed, 12 insertions(+), 1 deletion(-) diff --git a/env/ext4.c b/env/ext4.c index 9f65afb..47e05a4 100644 --- a/env/ext4.c +++ b/env/ext4.c @@ -31,6 +31,7 @@ #include #include #include +#include #include DECLARE_GLOBAL_DATA_PTR; @@ -146,6 +147,10 @@ static int env_ext4_load(void) if (!strcmp(ifname, "mmc")) mmc_initialize(NULL); #endif +#if defined(CONFIG_AHCI) || defined(CONFIG_SCSI) + if (!strcmp(ifname, "scsi")) + scsi_scan(true); +#endif part = blk_get_device_part_str(ifname, dev_and_part, &dev_desc, &info, 1); diff --git a/env/fat.c b/env/fat.c index 6251d96..3172130 100644 --- a/env/fat.c +++ b/env/fat.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include @@ -128,7 +129,12 @@ static int env_fat_load(void) if (!strcmp(ifname, "mmc")) mmc_initialize(NULL); #endif - +#ifndef CONFIG_SPL_BUILD +#if defined(CONFIG_AHCI) || defined(CONFIG_SCSI) + if (!strcmp(CONFIG_ENV_FAT_INTERFACE, "scsi")) + scsi_scan(true); +#endif +#endif part = blk_get_device_part_str(ifname, dev_and_part, &dev_desc, &info, 1); if (part < 0) -- 2.7.4
Add SCSI scan for ENV in EXT4 or FAT
Hi This updated version of the patch fixes a problem noticed by Stefan Roese where the CI build fails for the dra7xx_hs_evm_usb_defconfig target if this patch is included Let me know if any other changes are needed. Thanks and regards Rogier
Re: [PATCH] RFC: net: fec: get rid of CONFIG_FEC_MXC_MDIO_BASE
Hi Tim, On Wed, 11 May 2022 13:39:59 -0700 Tim Harvey thar...@gateworks.com wrote: ... > > Reviewed-by: Oleh Kravchenko > > Thanks Oleh. Do you know someone that does have a o4-imx6ull-nano > board to test with? > > Marcel, Fabio, Anatolij and Oliver, can you review and test your > boards with this? I do not have a working i.MX8QXP MEK board any more and can not test. Maybe Peng could test it? -- Anatolij
[PATCH] ARM: dts: stm32: Configure Buck3 voltage per PMIC NVM on Avenger96
The Avenger96 board comes in multiple regulator configurations.
- rev.100 or rev.200 have Buck3 preconfigured to 3V3 operation on
boot and contains extra Enpirion EP53A8LQI DCDC converter which
supplies the IO. Reduce Buck3 voltage to 2V9 to not waste power.
- rev.200L have Buck3 preconfigured to 1V8 operation and have no
Enpirion EP53A8LQI DCDC anymore, the IO is supplied from Buck3.
Configure the Buck3 voltage on this board per PMIC NVM settings and
update buck3 voltage limits in DT passed to OS before booting OS to
prevent potential hardware damage.
Signed-off-by: Marek Vasut
Cc: Patrice Chotard
Cc: Patrick Delaunay
---
arch/arm/dts/stm32mp15xx-dhcor-io1v8.dtsi | 2 +-
board/dhelectronics/dh_stm32mp1/board.c | 109 +-
2 files changed, 107 insertions(+), 4 deletions(-)
diff --git a/arch/arm/dts/stm32mp15xx-dhcor-io1v8.dtsi
b/arch/arm/dts/stm32mp15xx-dhcor-io1v8.dtsi
index 9937b28548c..e20917824bf 100644
--- a/arch/arm/dts/stm32mp15xx-dhcor-io1v8.dtsi
+++ b/arch/arm/dts/stm32mp15xx-dhcor-io1v8.dtsi
@@ -19,7 +19,7 @@
};
&vdd {
- regulator-min-microvolt = <290>;
+ regulator-min-microvolt = <180>;
regulator-max-microvolt = <290>;
};
diff --git a/board/dhelectronics/dh_stm32mp1/board.c
b/board/dhelectronics/dh_stm32mp1/board.c
index 67273f90992..d407f0bf592 100644
--- a/board/dhelectronics/dh_stm32mp1/board.c
+++ b/board/dhelectronics/dh_stm32mp1/board.c
@@ -594,14 +594,98 @@ static void board_init_fmc2(void)
setbits_le32(STM32_FMC2_BASE + STM32_FMC2_BCR1, STM32_FMC2_BCRx_FMCEN);
}
+#ifdef CONFIG_DM_REGULATOR
+#define STPMIC_NVM_BUCKS_VOUT_SHR 0xfc
+#define STPMIC_NVM_BUCKS_VOUT_SHR_BUCK_1V2 0
+#define STPMIC_NVM_BUCKS_VOUT_SHR_BUCK_1V8 1
+#define STPMIC_NVM_BUCKS_VOUT_SHR_BUCK_3V0 2
+#define STPMIC_NVM_BUCKS_VOUT_SHR_BUCK_3V3 3
+#define STPMIC_NVM_BUCKS_VOUT_SHR_BUCK_MASKGENMASK(1, 0)
+#define STPMIC_NVM_BUCKS_VOUT_SHR_BUCK_OFFSET(n) n) - 1) & 3) * 2)
+static int board_get_regulator_buck3_nvm_uv_av96(int *uv)
+{
+ const void *fdt = gd->fdt_blob;
+ struct udevice *dev;
+ u8 bucks_vout = 0;
+ const char *prop;
+ int len, ret;
+
+ /* Check whether this is Avenger96 board. */
+ prop = fdt_getprop(fdt, 0, "compatible", &len);
+ if (!prop || !len)
+ return -ENODEV;
+
+ if (!strstr(prop, "avenger96"))
+ return -EINVAL;
+
+ /* Read out STPMIC1 NVM and determine default Buck3 voltage. */
+ ret = uclass_get_device_by_driver(UCLASS_MISC,
+ DM_DRIVER_GET(stpmic1_nvm),
+ &dev);
+ if (ret)
+ return ret;
+
+ ret = misc_read(dev, STPMIC_NVM_BUCKS_VOUT_SHR, &bucks_vout, 1);
+ if (ret != 1)
+ return -EINVAL;
+
+ bucks_vout >>= STPMIC_NVM_BUCKS_VOUT_SHR_BUCK_OFFSET(3);
+ bucks_vout &= STPMIC_NVM_BUCKS_VOUT_SHR_BUCK_MASK;
+
+ /*
+* Avenger96 board comes in multiple regulator configurations:
+* - rev.100 or rev.200 have Buck3 preconfigured to 3V3 operation on
+* boot and contains extra Enpirion EP53A8LQI DCDC converter which
+* supplies the IO. Reduce Buck3 voltage to 2V9 to not waste power.
+* - rev.200L have Buck3 preconfigured to 1V8 operation and have no
+* Enpirion EP53A8LQI DCDC anymore, the IO is supplied from Buck3.
+*/
+ if (bucks_vout == STPMIC_NVM_BUCKS_VOUT_SHR_BUCK_3V3)
+ *uv = 290;
+ else
+ *uv = 180;
+
+ return 0;
+}
+
+static void board_init_regulator_av96(void)
+{
+ struct udevice *rdev;
+ int ret, uv;
+
+ ret = board_get_regulator_buck3_nvm_uv_av96(&uv);
+ if (ret)/* Not Avenger96 board. */
+ return;
+
+ ret = regulator_get_by_devname("buck3", &rdev);
+ if (ret)
+ return;
+
+ /* Adjust Buck3 per preconfigured PMIC voltage from NVM. */
+ regulator_set_value(rdev, uv);
+}
+
+static void board_init_regulator(void)
+{
+ board_init_regulator_av96();
+
+ regulators_enable_boot_on(_DEBUG);
+}
+#else
+static inline int board_get_regulator_buck3_nvm_uv_av96(int *uv)
+{
+ return -EINVAL;
+}
+
+static inline void board_init_regulator(void) {}
+#endif
+
/* board dependent setup after realloc */
int board_init(void)
{
board_key_check();
-#ifdef CONFIG_DM_REGULATOR
- regulators_enable_boot_on(_DEBUG);
-#endif
+ board_init_regulator();
sysconf_init();
@@ -721,6 +805,25 @@ int board_interface_eth_init(struct udevice *dev,
#if defined(CONFIG_OF_BOARD_SETUP)
int ft_board_setup(void *blob, struct bd_info *bd)
{
+ const char *buck3path = "/soc/i2c@5c002000/stpmic@33/regulators/buck3";
+ int buck3off, ret, uv;
+
+ ret = board_get_regulator_buck3_
Re: [PATCH 2/2] Add SCSI scan for ENV in EXT4 or FAT
Hi, Sorry for the late reply. Not much time lately, also had some trouble figuring the world build out. That said I have a fix. Not sure on the usual process, but I will repost it on the mailing list in a moment. Pali was quite close on the solution. I went a slightly different route as I did not want to deviate from style in fat.c, also from reading the recommended CONFIG_IS_ENABLED macro I got the impression you'd have to define separate vars for TPL and SPL which would deviate from normal usage for storing env in fat. Effectively it amounts to: +#ifndef CONFIG_SPL_BUILD +#if defined(CONFIG_AHCI) || defined(CONFIG_SCSI) + if (!strcmp(CONFIG_ENV_FAT_INTERFACE, "scsi")) + scsi_scan(true); +#endif +#endif Anyway, let me know if you disagree. Thanks and regards Rogier On 21-04-2022 12:57, Pali Rohár wrote: On Thursday 21 April 2022 12:34:30 Stefan Roese wrote: Hi Rogier, On 2/28/22 08:13, Pali Rohár wrote: + Simon, could you review this change? It would be nice to have this fix in upcoming U-Boot release. On Wednesday 09 February 2022 00:27:01 Rogier Stam wrote: When having environment stored in EXT4 or FAT and using an AHCI or SCSI device / partition the scan would not be performed early enough and hence the device would not be recognized. This change adds the scan when the interface is "scsi" in a similar way to mmc_initialize. Signed-off-by: Rogier Stam Reviewed-by: Pali Rohár While running some CI tests, this error occurs with this patch: $ make dra7xx_hs_evm_usb_defconfig ... $ make -s -j20 ... /opt/kernel.org/gcc-11.1.0-nolibc/arm-linux-gnueabi/bin/arm-linux-gnueabi-ld.bfd: env/fat.o: in function `env_fat_load': /home/stefan/git/u-boot/u-boot-marvell/env/fat.c:134: undefined reference to `scsi_scan' make[1]: *** [scripts/Makefile.spl:512: spl/u-boot-spl] Error 1 make: *** [Makefile:2101: spl/u-boot-spl] Error 2 This is failing while building SPL... Could you please take a look? And send a fixed version which also passed a "world build" for all supported targets? Thanks, Stefan --- env/ext4.c | 5 + env/fat.c | 5 + 2 files changed, 10 insertions(+) diff --git a/env/ext4.c b/env/ext4.c index 9f65afb..47e05a4 100644 --- a/env/ext4.c +++ b/env/ext4.c @@ -31,6 +31,7 @@ #include #include #include +#include #include DECLARE_GLOBAL_DATA_PTR; @@ -146,6 +147,10 @@ static int env_ext4_load(void) if (!strcmp(ifname, "mmc")) mmc_initialize(NULL); #endif +#if defined(CONFIG_AHCI) || defined(CONFIG_SCSI) + if (!strcmp(ifname, "scsi")) + scsi_scan(true); +#endif part = blk_get_device_part_str(ifname, dev_and_part, &dev_desc, &info, 1); diff --git a/env/fat.c b/env/fat.c index fdccd6c..dbd6a13 100644 --- a/env/fat.c +++ b/env/fat.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include @@ -122,6 +123,10 @@ static int env_fat_load(void) if (!strcmp(CONFIG_ENV_FAT_INTERFACE, "mmc")) mmc_initialize(NULL); #endif +#if defined(CONFIG_AHCI) || defined(CONFIG_SCSI) ... I guess that you should use CONFIG_IS_ENABLED(AHCI) instead of defined(CONFIG_AHCI) for proper SPL support. + if (!strcmp(CONFIG_ENV_FAT_INTERFACE, "scsi")) + scsi_scan(true); +#endif part = blk_get_device_part_str(CONFIG_ENV_FAT_INTERFACE, env_fat_device_and_part(), -- 2.7.4 Viele Grüße, Stefan Roese -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-51 Fax: (+49)-8142-66989-80 Email: s...@denx.de
Re: [PATCH 1/2] powerpc: mpc85xx: Add support for generating QorIQ pre-PBL eSDHC boot sector
On Monday 25 April 2022 14:36:14 Pali Rohár wrote: > On Monday 25 April 2022 05:25:34 Priyanka Jain (OSS) wrote: > > >-Original Message- > > >From: U-Boot On Behalf Of Pali Rohár > > >Sent: Tuesday, April 5, 2022 7:11 PM > > >To: Priyanka Jain ; Qiang Zhao ; > > >Shengzhou Liu ; Alexander Graf ; > > >Bin Meng ; Wolfgang Denk ; Sinan > > >Akman > > >Cc: u-boot@lists.denx.de > > >Subject: [PATCH 1/2] powerpc: mpc85xx: Add support for generating QorIQ > > >pre- > > >PBL eSDHC boot sector > > > > > >QorIQ U-Boot binary for SD card booting compiled during build process > > >(either u- > > >boot.bin or u-boot-with-spl.bin) cannot be directly loaded by QorIQ pre-PBL > > >BootROM. Compiled U-Boot binary first needs to be processed by Freescale > > >boot_format tool as described in doc/README.mpc85xx-sd-spi-boot > > > > > >BootROM requires that image on SD card must contain special boot sector. > > >Implement support for generating this special boot sector directly in > > >U-Boot start > > >code. Boot sector needs to be at the beginning of the image, so when > > >compiling > > >only proper U-Boot without SPL then it needs to be in proper U-Boot. When > > >compiling SPL with proper U-Boot then it needs to be only in SPL. > > > > > >Support can be enabled by a new config option > > >FSL_PREPBL_ESDHC_BOOT_SECTOR. > > >Via other two additional options FSL_PREPBL_ESDHC_BOOT_SECTOR_START and > > >FSL_PREPBL_ESDHC_BOOT_SECTOR_DATA it is possible to tune how final U-Boot > > >image could be stored on the SD card. > > > > > >Signed-off-by: Pali Rohár > > >--- > > > > Kindly rebase the series to master. > > > > Regards > > Priyanka > > Hello! Both patches still applies cleanly on master, just they depend > on another patch series (powerpc: mpc85xx: Fix and cleanup mpc85xx code) > which I mentioned in cover letter and therefore needs V2 patch of > "powerpc: mpc85xx: Set TEXT_BASE addresses to real base values" which I > sent recently. I sent a new version v2 of this patch, see email: [PATCH v2] powerpc: mpc85xx: Add support for generating QorIQ pre-PBL eSDHC boot sector
Re: [PATCH] mach-rockchip: make_fit_atf.py: support OP-TEE tee.bin v1 format
Hi Jerome,
On Wed, 11 May 2022 at 16:36, Jerome Forissier
wrote:
> This commit adds support for the OP-TEE 'tee.bin' v1 format for Rockchip
> platforms.
>
> Since OP-TEE 3.8.0, tee.bin contains meta-data in a proprietary format
> in addition to the ELF data. They are essential information for proper
> initialization of the TEE core, such as the size of the memory region
> covered by the TEE or a compact representation of runtime relocation
> data when ASLR is enabled.
>
> With OP-TEE 3.8.0 onwards, 'tee.elf' MUST NOT be used and 'tee.bin'
> MUST be used instead. Ignoring this recommendation can lead to crashes
> as described in [3].
>
> Link: [1]
> https://github.com/OP-TEE/optee_os/commit/5dd1570ac5b0f6563b1a9c074533a19107b8222d
> Link: [2]
> https://github.com/OP-TEE/optee_os/blob/3.17.0/scripts/gen_tee_bin.py#L275-L302
> Link: [3] https://github.com/OP-TEE/optee_os/issues/4542
> Signed-off-by: Jerome Forissier
>
Tested on my RockPi4b board, so
Tested-by: Peter Griffin
> ---
> arch/arm/mach-rockchip/make_fit_atf.py | 43 +-
> 1 file changed, 35 insertions(+), 8 deletions(-)
>
> diff --git a/arch/arm/mach-rockchip/make_fit_atf.py
> b/arch/arm/mach-rockchip/make_fit_atf.py
> index f3224d2555..fcea652388 100755
> --- a/arch/arm/mach-rockchip/make_fit_atf.py
> +++ b/arch/arm/mach-rockchip/make_fit_atf.py
> @@ -137,7 +137,7 @@ def generate_atf_fit_dts_bl31(fit_file,
> bl31_file_name, tee_file_name, dtbs_file
> num_segments = len(segments)
>
> if tee_file_name:
> -tee_segments = unpack_elf(tee_file_name)
> +tee_segments = unpack_tee_file(tee_file_name)
> for index, entry, paddr, data in tee_segments:
> append_tee_node(fit_file, num_segments + index + 1, paddr,
> entry)
> num_segments = num_segments + len(tee_segments)
> @@ -169,7 +169,7 @@ def generate_atf_binary(bl31_file_name):
>
> def generate_tee_binary(tee_file_name):
> if tee_file_name:
> -for index, entry, paddr, data in unpack_elf(tee_file_name):
> +for index, entry, paddr, data in unpack_tee_file(tee_file_name):
> file_name = 'tee_0x%08x.bin' % paddr
> with open(file_name, "wb") as atf:
> atf.write(data)
> @@ -194,6 +194,31 @@ def unpack_elf(filename):
> segments.append((index, e_entry, p_paddr, p_data))
> return segments
>
> +def unpack_tee_file(filename):
> +if filename.endswith('.elf'):
> +return unpack_elf(filename)
> +with open(filename, 'rb') as file:
> +bin = file.read()
> +segments = []
> +if bin[0:5] == b'OPTE\x01':
> +# OP-TEE v1 format (tee.bin)
> +init_sz, start_hi, start_lo, _, paged_sz =
> struct.unpack_from('<5I',
> + bin,
> + 0x8)
> +if paged_sz != 0:
> +raise ValueError("OP-TEE paged mode not supported")
> +e_entry = (start_hi << 32) + start_lo
> +p_addr = e_entry
> +p_data = bin[0x1c:]
> +if len(p_data) != init_sz:
> +raise ValueError("Invalid file '%s': size mismatch "
> + "(expected %d, have %d)" % (filename,
> init_sz,
> + len(p_data)))
> +segments.append((0, e_entry, p_addr, p_data))
> +else:
> +raise ValueError("Unknown format for TEE file '%s'" % filename)
> +return segments
> +
> def main():
> uboot_elf = "./u-boot"
> fit_its = sys.stdout
> @@ -210,11 +235,13 @@ def main():
> logging.warning(' Please read Building section in
> doc/README.rockchip')
>
> if "TEE" in os.environ:
> -tee_elf = os.getenv("TEE")
> +tee_file = os.getenv("TEE")
> +elif os.path.isfile("./tee.bin"):
> +tee_file = "./tee.bin"
> elif os.path.isfile("./tee.elf"):
> -tee_elf = "./tee.elf"
> +tee_file = "./tee.elf"
> else:
> -tee_elf = ""
> +tee_file = ""
>
> opts, args = getopt.getopt(sys.argv[1:], "o:u:b:t:h")
> for opt, val in opts:
> @@ -225,16 +252,16 @@ def main():
> elif opt == "-b":
> bl31_elf = val
> elif opt == "-t":
> -tee_elf = val
> +tee_file = val
> elif opt == "-h":
> print(__doc__)
> sys.exit(2)
>
> dtbs = args
>
> -generate_atf_fit_dts(fit_its, bl31_elf, tee_elf, uboot_elf, dtbs)
> +generate_atf_fit_dts(fit_its, bl31_elf, tee_file, uboot_elf, dtbs)
> generate_atf_binary(bl31_elf)
> -generate_tee_binary(tee_elf)
> +generate_tee_binary(tee_file)
>
> if __name__ == "__main__":
> main()
> --
> 2.17.1
>
>
[PATCH] powerpc: mpc85xx: Simplify jump to _start_cont in flash code
After more patches code for jumping to _start_cont symbol in flash memory involved to code with useless mathematical operations. Currently it does: r3 := CONFIG_SYS_MONITOR_BASE + ABS(_start_cont) - CONFIG_SYS_MONITOR_BASE jump to r3 Which is equivalent of just: r3 := ABS(_start_cont) jump to r3 The purpose of that code is just to jump to _start_code symbol, independently of program counter. So branch must be done to absolute address. Trying to write: ba _start_cont just cause linker error: LD u-boot powerpc-linux-gnuspe-ld.bfd: arch/powerpc/cpu/mpc85xx/start.o: in function `switch_as': (.bootpg+0x4b8): relocation truncated to fit: R_PPC_ADDR24 against symbol `_start_cont' defined in .text section in arch/powerpc/cpu/mpc85xx/start.o make: *** [Makefile:1801: u-boot] Error 1 Probably by the fact that absolute address cannot be expressed by 24-bits. So write the code via mtlr+blr pattern as it was before and load general purpose register with absolute address of the symbol: lis r3,_start_cont@h ori r3,r3,_start_cont@l mtlrr3 blr Seems that gcc and gnu ld linker support symbol@h and symbol@l syntax like number@h and number@l without any problem. And disassembling of compiler u-boot binary proved that lis+ori instructions are called with numbers which represent halves of absolute address of _start_cont symbol. Signed-off-by: Pali Rohár --- arch/powerpc/cpu/mpc85xx/start.S | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index 50b23a97662c..6e3900e7923b 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -1211,9 +1211,8 @@ switch_as: #else /* Calculate absolute address in FLASH and jump there */ /*--*/ - lis r3,CONFIG_SYS_MONITOR_BASE@h - ori r3,r3,CONFIG_SYS_MONITOR_BASE@l - addir3,r3,_start_cont - CONFIG_SYS_MONITOR_BASE + lis r3,_start_cont@h + ori r3,r3,_start_cont@l mtlrr3 blr #endif -- 2.20.1
[PATCH] i2c: ast_i2c: Remove SCL direct drive mode
SCL direct drive mode prevents communication with devices that do clock stretching, so disable. The Linux driver doesn't use this mode, and the engine can handle clock stretching. Signed-off-by: Eddie James --- drivers/i2c/ast_i2c.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/i2c/ast_i2c.c b/drivers/i2c/ast_i2c.c index 2d3fecaa14..8b24a260c0 100644 --- a/drivers/i2c/ast_i2c.c +++ b/drivers/i2c/ast_i2c.c @@ -76,7 +76,7 @@ static void ast_i2c_init_bus(struct udevice *dev) /* Enable Master Mode. Assuming single-master */ writel(I2CD_MASTER_EN | I2CD_M_SDA_LOCK_EN - | I2CD_MULTI_MASTER_DIS | I2CD_M_SCL_DRIVE_EN, + | I2CD_MULTI_MASTER_DIS, &priv->regs->fcr); /* Enable Interrupts */ writel(I2CD_INTR_TX_ACK -- 2.27.0
Re: [PATCH] RFC: net: fec: get rid of CONFIG_FEC_MXC_MDIO_BASE
On Sat, May 7, 2022 at 12:41 PM Oleh Kravchenko wrote: > > Hello Tim, > Your patch looks good, and I'm pleased to verify it. > But I don't have access to the o4-imx6ull-nano board. > > 06.05.22 01:12, Tim Harvey пише: > > A number of IMX8Q boards using FEC configure the address of the ethernet > > controller via defconfig as there are two FEC controllers in the SoC. > > > > Now that the FEC driver uses DM the register address should be coming from > > device-tree. > > > > Remove the hard coded config and while at it remove the unused > > CONFIG_FEC_MXC_SHARE_MDIO. > > > > This is an RFC as I do not have the affected boards to test with and > > would want to see a Tested-By from someone with each board. I am attempting > > to clean up some ugliness in the FEC driver. There appears to be > > multiple constructs to deal with shared MDIO busses when DM_MDIO should > > be the right solution for that. > > > > Signed-off-by: Tim Harvey > > Cc: Marcel Ziswiler (maintainer:Apalis iMX8) > > Cc: Oliver Graute (maintainer:i.MX8QM > > CGTQMX8 BOARD) > > Cc: Anatolij Gustschin (maintainer:CAPRICORN BOARD) > > Cc: Peng Fan (maintainer:i.MX8QM MEK BOARD) > > Cc: Fabio Estevam (maintainer:i.MX8QXP MEK BOARD) > > Cc: Oleh Kravchenko (maintainer:OUT4-IMX6ULL-NANO BOARD) > > Cc: Joe Hershberger (maintainer:NETWORK) > > Cc: Ramon Fried (maintainer:NETWORK) > > --- > > configs/apalis-imx8_defconfig | 2 -- > > configs/cgtqmx8_defconfig | 2 -- > > configs/colibri-imx8x_defconfig| 2 -- > > configs/deneb_defconfig| 2 -- > > configs/giedi_defconfig| 2 -- > > configs/imx8qm_mek_defconfig | 2 -- > > configs/imx8qm_rom7720_a1_4G_defconfig | 2 -- > > configs/imx8qxp_mek_defconfig | 2 -- > > configs/o4-imx6ull-nano_defconfig | 2 -- > > drivers/net/Kconfig| 11 --- > > drivers/net/fec_mxc.c | 5 - > > 11 files changed, 34 deletions(-) > > > > diff --git a/configs/apalis-imx8_defconfig b/configs/apalis-imx8_defconfig > > index beb20f6e1c01..bd8e7f01e493 100644 > > --- a/configs/apalis-imx8_defconfig > > +++ b/configs/apalis-imx8_defconfig > > @@ -56,8 +56,6 @@ CONFIG_PHY_ADDR_ENABLE=y > > CONFIG_PHY_MICREL=y > > CONFIG_PHY_MICREL_KSZ90X1=y > > CONFIG_DM_ETH=y > > -CONFIG_FEC_MXC_SHARE_MDIO=y > > -CONFIG_FEC_MXC_MDIO_BASE=0x5B04 > > CONFIG_FEC_MXC=y > > CONFIG_MII=y > > CONFIG_PINCTRL=y > > diff --git a/configs/cgtqmx8_defconfig b/configs/cgtqmx8_defconfig > > index 2cf882f826ab..fe62b639bd88 100644 > > --- a/configs/cgtqmx8_defconfig > > +++ b/configs/cgtqmx8_defconfig > > @@ -72,8 +72,6 @@ CONFIG_PHY_ADDR_ENABLE=y > > CONFIG_PHY_ATHEROS=y > > CONFIG_DM_ETH=y > > CONFIG_PHY_GIGE=y > > -CONFIG_FEC_MXC_SHARE_MDIO=y > > -CONFIG_FEC_MXC_MDIO_BASE=0x5B04 > > CONFIG_FEC_MXC=y > > CONFIG_MII=y > > CONFIG_PINCTRL=y > > diff --git a/configs/colibri-imx8x_defconfig > > b/configs/colibri-imx8x_defconfig > > index 0c9d6b64c1b6..03e899f51fed 100644 > > --- a/configs/colibri-imx8x_defconfig > > +++ b/configs/colibri-imx8x_defconfig > > @@ -54,8 +54,6 @@ CONFIG_PHYLIB=y > > CONFIG_PHY_ADDR_ENABLE=y > > CONFIG_PHY_MICREL=y > > CONFIG_DM_ETH=y > > -CONFIG_FEC_MXC_SHARE_MDIO=y > > -CONFIG_FEC_MXC_MDIO_BASE=0x5B04 > > CONFIG_FEC_MXC=y > > CONFIG_MII=y > > CONFIG_PINCTRL=y > > diff --git a/configs/deneb_defconfig b/configs/deneb_defconfig > > index 425fff6c70a6..d0fc11a774f8 100644 > > --- a/configs/deneb_defconfig > > +++ b/configs/deneb_defconfig > > @@ -94,8 +94,6 @@ CONFIG_MV88E61XX_CPU_PORT=5 > > CONFIG_MV88E61XX_PHY_PORTS=0x7 > > CONFIG_MV88E61XX_FIXED_PORTS=0x0 > > CONFIG_DM_ETH=y > > -CONFIG_FEC_MXC_SHARE_MDIO=y > > -CONFIG_FEC_MXC_MDIO_BASE=0x5B05 > > CONFIG_FEC_MXC=y > > CONFIG_MII=y > > CONFIG_PINCTRL=y > > diff --git a/configs/giedi_defconfig b/configs/giedi_defconfig > > index 4fbf7ebdcd95..24bc621cf184 100644 > > --- a/configs/giedi_defconfig > > +++ b/configs/giedi_defconfig > > @@ -94,8 +94,6 @@ CONFIG_MV88E61XX_CPU_PORT=5 > > CONFIG_MV88E61XX_PHY_PORTS=0x7 > > CONFIG_MV88E61XX_FIXED_PORTS=0x0 > > CONFIG_DM_ETH=y > > -CONFIG_FEC_MXC_SHARE_MDIO=y > > -CONFIG_FEC_MXC_MDIO_BASE=0x5B05 > > CONFIG_FEC_MXC=y > > CONFIG_MII=y > > CONFIG_PINCTRL=y > > diff --git a/configs/imx8qm_mek_defconfig b/configs/imx8qm_mek_defconfig > > index 2e42872f843d..448a20c7afd1 100644 > > --- a/configs/imx8qm_mek_defconfig > > +++ b/configs/imx8qm_mek_defconfig > > @@ -73,8 +73,6 @@ CONFIG_PHY_ADDR_ENABLE=y > > CONFIG_PHY_ATHEROS=y > > CONFIG_DM_ETH=y > > CONFIG_PHY_GIGE=y > > -CONFIG_FEC_MXC_SHARE_MDIO=y > > -CONFIG_FEC_MXC_MDIO_BASE=0x5B04 > > CONFIG_FEC_MXC=y > > CONFIG_MII=y > > CONFIG_PINCTRL=y > > diff --git a/configs/imx8qm_rom7720_a1_4G_defconfig > > b/configs/imx8qm_rom7720_a1_4G_defconfig > > index d9997cfa8280..0a8de612ea32 100644 > > --- a/configs/imx8qm_rom7720_a1_4G_defconfig > > +++ b
[PATCH] mtd: rawnand: fsl_elbc: Fix detection when nand_scan_ident() has not selected ecc.mode
ecc.mode is set to 0 (aliased to NAND_ECC_NONE) either when function
nand_scan_ident() has not selected ecc.mode or when it selected it to none
ecc mode.
Distinguish between these two states by checking of node property
"nand-ecc-mode" which function nand_scan_ident() uses for filling ecc.mode.
This change fixes usage of none ecc mode if it is specified in DTS file.
Fixes: c9ea9019c5aa ("mtd: rawnand: fsl_elbc: Use ECC configuration from device
tree")
Signed-off-by: Pali Rohár
---
drivers/mtd/nand/raw/fsl_elbc_nand.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/mtd/nand/raw/fsl_elbc_nand.c
b/drivers/mtd/nand/raw/fsl_elbc_nand.c
index b0e3eb607ed4..8e14739b3ee9 100644
--- a/drivers/mtd/nand/raw/fsl_elbc_nand.c
+++ b/drivers/mtd/nand/raw/fsl_elbc_nand.c
@@ -745,7 +745,8 @@ static int fsl_elbc_chip_init(int devnum, u8 *addr, struct
udevice *dev)
return ret;
/* If nand_scan_ident() has not selected ecc.mode, do it now */
- if (nand->ecc.mode == NAND_ECC_NONE) {
+ if (nand->ecc.mode == 0 &&
+ !ofnode_read_string(nand->flash_node, "nand-ecc-mode")) {
/* If CS Base Register selects full hardware ECC then use it */
if ((br & BR_DECC) == BR_DECC_CHK_GEN) {
nand->ecc.mode = NAND_ECC_HW;
--
2.20.1
Re: [PATCH 7/8] powerpc: mpc85xx: Set TEXT_BASE addresses to real base values
On Monday 25 April 2022 14:31:16 Pali Rohár wrote: > On Monday 25 April 2022 04:27:51 Priyanka Jain (OSS) wrote: > > >-Original Message- > > >From: U-Boot On Behalf Of Pali Rohár > > >Sent: Tuesday, April 5, 2022 6:43 PM > > >To: Priyanka Jain ; Qiang Zhao ; > > >Shengzhou Liu ; Alexander Graf ; > > >Bin Meng ; Wolfgang Denk ; Sinan > > >Akman > > >Cc: u-boot@lists.denx.de > > >Subject: [PATCH 7/8] powerpc: mpc85xx: Set TEXT_BASE addresses to real base > > >values > > > > > >Currently CONFIG_SPL_TEXT_BASE and CONFIG_SYS_TEXT_BASE addresses are > > >manually increased by 0x1000 due to .bootpg section. This section has size > > >of > > >0x1000 bytes and is manually put by linker script before .text section (and > > >therefore before base address) when CONFIG_SYS_MPC85XX_NO_RESETVEC is > > >set. Due to this fact lot of other config options are manually increased by > > >0x1000 value to make correct layout. Note that entry point is not on > > >CONFIG_SPL_TEXT_BASE (image+0x1000) but it is really on address > > >CONFIG_SPL_TEXT_BASE-0x1000 (means at the start of the image). > > > > > >Cleanup handling of .bootpg section when > > >CONFIG_SYS_MPC85XX_NO_RESETVEC is set. Put .bootpg code directly into .text > > >section and move text base address to the start of .bootpg code. And > > >finally > > >remove +0x1000 value from lot of config options. With this removal custom > > >PHDRS is not used anymore, so remove it too. > > > > > >After this change entry point would be at CONFIG_SPL_TEXT_BASE and not at > > >address -0x1000 anymore. > > > > > >Tested on P2020 board with SPL and proper U-Boot. > > > > > >Signed-off-by: Pali Rohár > > >--- > > > > Kindly rebase to top of tree. There has been changed related configs. > > I am picking patches till 6/8. So just send next version of 7/8 and 8/8 > > Done! I rebased 7/8 on top of master and sent V2 to ML. 8/8 in current > version still cleanly applied on 7/8, so I did not resent it. If there > is some issue, please let me know. PING?
[PATCH v2] powerpc: mpc85xx: Add support for generating QorIQ pre-PBL eSDHC boot sector
QorIQ U-Boot binary for SD card booting compiled during build process (either u-boot.bin or u-boot-with-spl.bin) cannot be directly loaded by QorIQ pre-PBL BootROM. Compiled U-Boot binary first needs to be processed by Freescale boot_format tool as described in doc/README.mpc85xx-sd-spi-boot BootROM requires that image on SD card must contain special boot sector. Implement support for generating this special boot sector directly in U-Boot start code. Boot sector needs to be at the beginning of the image, so when compiling only proper U-Boot without SPL then it needs to be in proper U-Boot. When compiling SPL with proper U-Boot then it needs to be only in SPL. Support can be enabled by a new config option FSL_PREPBL_ESDHC_BOOT_SECTOR. Via other two additional options FSL_PREPBL_ESDHC_BOOT_SECTOR_START and FSL_PREPBL_ESDHC_BOOT_SECTOR_DATA it is possible to tune how final U-Boot image could be stored on the SD card. Signed-off-by: Pali Rohár --- Changes in v2: * Replace addresses in start.S by named constants * Move bootsect from .text section to separate data section .bootsect which would be before TEXT_BASE. This boot sector is not used by the U-Boot nor SPL and it even is not loaded by BootROM into larget area, so it does not have to occupe data in TEXT_BASE. With this change U-Boot and SPL stay on the same addresses as before this change. --- arch/powerpc/cpu/mpc85xx/Kconfig| 53 ++ arch/powerpc/cpu/mpc85xx/start.S| 94 + arch/powerpc/cpu/mpc85xx/u-boot-spl.lds | 8 +++ arch/powerpc/cpu/mpc85xx/u-boot.lds | 8 +++ 4 files changed, 163 insertions(+) diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig index c308447d493a..6f8b7593d250 100644 --- a/arch/powerpc/cpu/mpc85xx/Kconfig +++ b/arch/powerpc/cpu/mpc85xx/Kconfig @@ -12,6 +12,59 @@ config CMD_ERRATA This enables the 'errata' command which displays a list of errata work-arounds which are enabled for the current board. +config FSL_PREPBL_ESDHC_BOOT_SECTOR + bool "Generate QorIQ pre-PBL eSDHC boot sector" + depends on MPC85xx + depends on SYS_EXTRA_OPTIONS = SDCARD + help + With this option final image would have prepended QorIQ pre-PBL eSDHC + boot sector suitable for SD card images. This boot sector instruct + BootROM to configure L2 SRAM and eSDHC then load image from SD card + into L2 SRAM and finally jump to image entry point. + + This is alternative to Freescale boot_format tool, but works only for + SD card images and only for L2 SRAM booting. U-Boot images generated + with this option should not passed to boot_format tool. + + For other configuration like booting from eSPI or configuring SDRAM + please use Freescale boot_format tool without this option. See file + doc/README.mpc85xx-sd-spi-boot + +config FSL_PREPBL_ESDHC_BOOT_SECTOR_START + int "QorIQ pre-PBL eSDHC boot sector start offset" + depends on FSL_PREPBL_ESDHC_BOOT_SECTOR + range 0 23 + default 0 + help + QorIQ pre-PBL eSDHC boot sector may be located on one of the first + 24 SD card sectors. Select SD card sector on which final U-Boot + image (with this boot sector) would be installed. + + By default first SD card sector (0) is used. But this may be changed + to allow installing U-Boot image on some partition (with fixed start + sector). + + Please note that any sector on SD card prior this boot sector must + not contain ASCII "BOOT" bytes at sector offset 0x40. + +config FSL_PREPBL_ESDHC_BOOT_SECTOR_DATA + int "Relative data sector for QorIQ pre-PBL eSDHC boot sector" + depends on FSL_PREPBL_ESDHC_BOOT_SECTOR + default 1 + range 1 8388607 + help + Select data sector from the beginning of QorIQ pre-PBL eSDHC boot + sector on which would be stored raw U-Boot image. + + By default is it second sector (1) which is the first available free + sector (on the first sector is stored boot sector). It can be any + sector number which offset in bytes can be expressed by 32-bit number. + + In case this final U-Boot image (with this boot sector) is put on + the FAT32 partition into reserved boot area, this data sector needs + to be at least 2 (third sector) because FAT32 use second sector for + its data. + choice prompt "Target select" optional diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index 796a58b929ec..3006d569b387 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -56,6 +56,100 @@ GOT_ENTRY(__bss_start) END_GOT +#ifdef CONFIG_FSL_PREPBL_ESDHC_BOOT_SECTOR +#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) + +/* Maximal size of the image */ +#ifdef CONFIG_SPL_BUILD +#d
[PATCH 1/3] mmc: fsl_esdhc_spl: Add support for loading proper U-Boot from unaligned location
This allows to concatenate SPL and proper U-Boot without extra alignment.
Signed-off-by: Pali Rohár
---
drivers/mmc/fsl_esdhc_spl.c | 25 ++---
1 file changed, 22 insertions(+), 3 deletions(-)
diff --git a/drivers/mmc/fsl_esdhc_spl.c b/drivers/mmc/fsl_esdhc_spl.c
index 760f13d24018..e3175de16bab 100644
--- a/drivers/mmc/fsl_esdhc_spl.c
+++ b/drivers/mmc/fsl_esdhc_spl.c
@@ -155,10 +155,21 @@ again:
* Load U-Boot image from mmc into RAM
*/
code_len = CONFIG_SYS_MMC_U_BOOT_SIZE;
- blk_start = ALIGN(offset, mmc->read_bl_len) / mmc->read_bl_len;
- blk_cnt = ALIGN(code_len, mmc->read_bl_len) / mmc->read_bl_len;
+ blk_start = offset / mmc->read_bl_len;
+ blk_off = offset % mmc->read_bl_len;
+ blk_cnt = ALIGN(code_len, mmc->read_bl_len) / mmc->read_bl_len + 1;
+ if (blk_off) {
+ err = mmc->block_dev.block_read(&mmc->block_dev,
+ blk_start, 1, tmp_buf);
+ if (err != 1) {
+ puts("spl: mmc read failed!!\n");
+ hang();
+ }
+ blk_start++;
+ }
err = mmc->block_dev.block_read(&mmc->block_dev, blk_start, blk_cnt,
- (uchar *)CONFIG_SYS_MMC_U_BOOT_DST);
+ (uchar *)CONFIG_SYS_MMC_U_BOOT_DST +
+ (blk_off ? (mmc->read_bl_len - blk_off)
: 0));
if (err != blk_cnt) {
puts("spl: mmc read failed!!\n");
#ifndef CONFIG_FSL_CORENET
@@ -166,6 +177,14 @@ again:
#endif
hang();
}
+ /*
+* SDHC DMA may erase bytes at dst + bl_len - blk_off - 8
+* due to unaligned access. So copy leading bytes from tmp_buf
+* after SDHC DMA transfer.
+*/
+ if (blk_off)
+ memcpy((uchar *)CONFIG_SYS_MMC_U_BOOT_DST,
+ tmp_buf + blk_off, mmc->read_bl_len - blk_off);
/*
* Clean d-cache and invalidate i-cache, to
--
2.20.1
[PATCH 2/3] mmc: fsl_esdhc_spl: Add support for builds without CONFIG_SYS_MMC_U_BOOT_OFFS
When fixed offset via CONFIG_SYS_MMC_U_BOOT_OFFS is not specified then
expects that U-Boot proper is placed immediately after SPL without any
additional padding.
This allows to generate smaller SPL+U-Boot final binary as it is not
required to specify fixed offset to U-Boot proper at SPL compile time.
In this case offset to U-Boot proper is calculated at SPL compile time in
linker script.
Signed-off-by: Pali Rohár
---
arch/powerpc/cpu/mpc85xx/u-boot-spl.lds | 10 ++
drivers/mmc/fsl_esdhc_spl.c | 8
2 files changed, 18 insertions(+)
diff --git a/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds
b/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds
index 272e94a1f169..cfb55939468a 100644
--- a/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds
+++ b/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds
@@ -59,6 +59,13 @@ SECTIONS
__init_begin = .;
__init_end = .;
_end = .;
+
+#ifdef CONFIG_SYS_MPC85XX_NO_RESETVEC
+#if defined(CONFIG_SDCARD) && !defined(CONFIG_SYS_MMC_U_BOOT_OFFS)
+ mmc_u_boot_offs = .;
+#endif
+#endif
+
#ifdef CONFIG_SPL_SKIP_RELOCATE
. = ALIGN(4);
__bss_start = .;
@@ -91,6 +98,9 @@ SECTIONS
.resetvec IMAGE_TEXT_BASE + RESET_VECTOR_OFFSET : {
KEEP(*(.resetvec))
} = 0x
+#if defined(CONFIG_SDCARD) && !defined(CONFIG_SYS_MMC_U_BOOT_OFFS)
+ mmc_u_boot_offs = .;
+#endif
#endif
#ifndef CONFIG_SPL_SKIP_RELOCATE
diff --git a/drivers/mmc/fsl_esdhc_spl.c b/drivers/mmc/fsl_esdhc_spl.c
index e3175de16bab..139b4d853b7a 100644
--- a/drivers/mmc/fsl_esdhc_spl.c
+++ b/drivers/mmc/fsl_esdhc_spl.c
@@ -9,6 +9,10 @@
#include
#include
+#ifndef CONFIG_SYS_MMC_U_BOOT_OFFS
+extern uchar mmc_u_boot_offs[];
+#endif
+
/*
* The environment variables are written to just after the u-boot image
* on SDCard, so we must read the MBR to get the start address and code
@@ -149,7 +153,11 @@ again:
val = *(tmp_buf + blk_off + ESDHC_BOOT_IMAGE_ADDR + i);
offset = (offset << 8) + val;
}
+#ifndef CONFIG_SYS_MMC_U_BOOT_OFFS
+ offset += (ulong)&mmc_u_boot_offs - CONFIG_SPL_TEXT_BASE;
+#else
offset += CONFIG_SYS_MMC_U_BOOT_OFFS;
+#endif
#endif
/*
* Load U-Boot image from mmc into RAM
--
2.20.1
Re: [PATCH RFC v2 00/11] Integration of sysfw, tispl and tiboot3
On 10/05/2022 23:05, Tom Rini wrote: > Adding the other binman maintainer.. Thanks. I haven't been able to focus on anything for a while. I'll try to review the few series that have accumulated, maybe can manage this week or so if things go well. Just wanted to send an update.
[PATCH 3/3] powerpc: mpc85xx: Fix loading U-Boot proper from SD card in SPL
Change 8-byte alignment of SPL binary to just 4-byte alignment as objcopy
trims trailing zero bytes when converting ELF file to RAW binary.
This is same fix for SPL linker script as was done fix for U-Boot linker
script in commit e8c0e0064c8a ("powerpc: mpc85xx: Fix CONFIG_OF_SEPARATE
support").
It is required for the patch "mmc: fsl_esdhc_spl: Add support for builds
without CONFIG_SYS_MMC_U_BOOT_OFFS" which triggered this issue in SPL.
Signed-off-by: Pali Rohár
---
arch/powerpc/cpu/mpc85xx/u-boot-spl.lds | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds
b/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds
index cfb55939468a..1b189b2f14d3 100644
--- a/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds
+++ b/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds
@@ -55,7 +55,7 @@ SECTIONS
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
- . = ALIGN(8);
+ . = ALIGN(4);
__init_begin = .;
__init_end = .;
_end = .;
--
2.20.1
[PATCH 1/2] mmc: fsl_esdhc: Set fallback mode to 1-bit
8-bit mode is not supported by SD cards and on P2020 are four SDHC pins
shared with SPI (so if P2020 board have also SPI then only 4-bit SDHC mode
is provided). So 8-bit SDHC mode is really bad default.
When max bus width is not provided then set mode to 1-bit. This mode is
supported by all cards, so it is the best option for fallback mode.
Also P2020 bootrom sets mode to 1-bit when booting from SD/MMC card.
Signed-off-by: Pali Rohár
---
drivers/mmc/fsl_esdhc.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index 3b3587bd8d72..834f8933b0c6 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -963,9 +963,8 @@ int fsl_esdhc_initialize(struct bd_info *bis, struct
fsl_esdhc_cfg *cfg)
} else if (cfg->max_bus_width == 1) {
mmc_cfg->host_caps |= MMC_MODE_1BIT;
} else {
- mmc_cfg->host_caps |= MMC_MODE_1BIT | MMC_MODE_4BIT |
- MMC_MODE_8BIT;
- printf("No max bus width provided. Assume 8-bit supported.\n");
+ mmc_cfg->host_caps |= MMC_MODE_1BIT;
+ printf("No max bus width provided. Fallback to 1-bit mode.\n");
}
if (IS_ENABLED(CONFIG_ESDHC_DETECT_8_BIT_QUIRK))
--
2.20.1
[PATCH] mmc: fsl_esdhc_spl: Fix checking for number of read sectors
Commit 0980cbba7b3c ("mmc: fsl_esdhc_spl: pre-PBL: implement redundancy
support") changed number of sectors which are read but did not adjusted
error check.
Fix it and check for if correct number of sectors were read.
Fixes: 0980cbba7b3c ("mmc: fsl_esdhc_spl: pre-PBL: implement redundancy
support")
Signed-off-by: Pali Rohár
---
drivers/mmc/fsl_esdhc_spl.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mmc/fsl_esdhc_spl.c b/drivers/mmc/fsl_esdhc_spl.c
index ea8f4cd66964..760f13d24018 100644
--- a/drivers/mmc/fsl_esdhc_spl.c
+++ b/drivers/mmc/fsl_esdhc_spl.c
@@ -106,7 +106,7 @@ again:
blk_off = (sector * 512) % mmc->read_bl_len;
blk_cnt = DIV_ROUND_UP(512, mmc->read_bl_len);
err = mmc->block_dev.block_read(&mmc->block_dev, blk_start, blk_cnt,
tmp_buf);
- if (err != 1) {
+ if (err != blk_cnt) {
puts("spl: mmc read failed!!\n");
hang();
}
--
2.20.1
[PATCH 2/2] mmc: fsl_esdhc: Add new config option for default fallback mode
Currently default fallback SDHC mode is 1-bit. Add new config option CONFIG_SYS_FSL_ESDHC_DEFAULT_BUS_WIDTH to allow specifying default fallback mode. This is useful e.g. for SPL builds which loads other parts from SD card during boot process. Signed-off-by: Pali Rohár --- drivers/mmc/Kconfig | 5 + drivers/mmc/fsl_esdhc.c | 1 + 2 files changed, 6 insertions(+) diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index f04cc44e1973..df15dff6248f 100644 --- a/drivers/mmc/Kconfig +++ b/drivers/mmc/Kconfig @@ -826,6 +826,11 @@ config FSL_ESDHC_VS33_NOT_SUPPORT For eSDHC, power supply is through peripheral circuit. 3.3V support is common. Select this if 3.3V power supply not supported. +config SYS_FSL_ESDHC_DEFAULT_BUS_WIDTH + int + depends on FSL_ESDHC + default 1 + config FSL_ESDHC_IMX bool "Freescale/NXP i.MX eSDHC controller support" help diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index 834f8933b0c6..a4c22942c2be 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -988,6 +988,7 @@ int fsl_esdhc_mmc_init(struct bd_info *bis) cfg = calloc(sizeof(struct fsl_esdhc_cfg), 1); cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR; + cfg->max_bus_width = CONFIG_SYS_FSL_ESDHC_DEFAULT_BUS_WIDTH; /* Prefer peripheral clock which provides higher frequency. */ if (gd->arch.sdhc_per_clk) cfg->sdhc_clk = gd->arch.sdhc_per_clk; -- 2.20.1
Re: [PATCH 4/4] boot: Kconfig: Enable FIT processing by default on TI secure devices
On Wed, May 04, 2022 at 03:52:28PM -0500, Andrew Davis wrote: > TI secure devices chain-of-trust depends on FIT image processing, > enable it by default on these devices. This also reduces the delta > between the secure and non-secure defconfig files. > > Signed-off-by: Andrew Davis > Reviewed-by: Tom Rini Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH 3/4] boot: Kconfig: Disable non-FIT loading for TI secure devices
On Wed, May 04, 2022 at 03:52:27PM -0500, Andrew Davis wrote: > Non-FIT image loading support should be disabled for TI secure > devices as the image handlers for those image types do not follow > our secure boot checks. > > Signed-off-by: Andrew Davis > Reviewed-by: Tom Rini Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH 2/4] spl: Force disable non-FIT loading for TI secure devices
On Wed, May 04, 2022 at 03:52:26PM -0500, Andrew Davis wrote: > Booting of non-FIT images bypass our chain-of-trust boot flow, > these options should not be allowed when high security is set. > > Signed-off-by: Andrew Davis > Reviewed-by: Tom Rini Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH 1/4] spl: Rename Kconfig SPL_LEGACY_IMAGE_SUPPORT to SPL_LEGACY_IMAGE_FORMAT
On Wed, May 04, 2022 at 03:52:25PM -0500, Andrew Davis wrote: > This matches what this support is called in the non-SPL case. The postfix > _SUPPORT is redundant as enabling Kconfig options implies support. > With this we can use CONFIG_IS_ENABLED() as needed. > > Signed-off-by: Andrew Davis > Reviewed-by: Tom Rini Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH] Makefile: update warning about CONFIG_OF_EMBED
On Thu, Apr 28, 2022 at 03:52:59PM -0400, Ralph Siemsen wrote:
> Update the diagnostic message with revised location of document, which
> changed in 3e9fddfc4f1 ("doc: Move devicetree control doc to rST")
>
> Signed-off-by: Ralph Siemsen
Applied to u-boot/master, thanks!
--
Tom
signature.asc
Description: PGP signature
Re: [PATCH] board_r: use IS_ENABLED(CONFIG_NEEDS_MANUAL_RELOC) in board_init_r()
On Mon, May 02, 2022 at 06:34:56PM +0300, Ovidiu Panait wrote: > Drop CONFIG_NEEDS_MANUAL_RELOC ifdefs in board_init_r() and use > IS_ENABLED() instead. Also, use the MANUAL_RELOC() macro to update the > initcall pointers. > > Signed-off-by: Ovidiu Panait Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH] common/console.c: use CONFIG_VAL() with PRE_CON_BUF_* variables
On Tue, May 03, 2022 at 02:37:39PM +0200, Rasmus Villemoes wrote: > There is currently no support for PRE_CONSOLE_BUFFER in SPL, but if > and when that gets implemented, one would almost certainly want to use > a different address and/or size for the buffer (e.g., U-Boot proper > might specify an address in DRAM and a generous buffer, while SPL > would be much more constrained). > > So a prerequisite for adding SPL_PRE_CONSOLE_BUFFER is to make the > code use SPL_-specific values. No functional change. > > Signed-off-by: Rasmus Villemoes Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH] Convert CONFIG_MTD_CONCAT to Kconfig
On Tue, May 03, 2022 at 09:24:57PM +1200, Chris Packham wrote: > This converts the following to Kconfig: > CONFIG_MTD_CONCAT > > Signed-off-by: Chris Packham > Reviewed-by: Tom Rini > Reviewed-by: Stefan Roese Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH 1/3] phy: stm32-usbphyc: add counter of PLL consumer
On 5/10/22 5:51 AM, Amelie Delaunay wrote:
Hi Patrick,
Hi Sean,
On 5/9/22 16:37, Patrick DELAUNAY wrote:
Hi Sean,
On 5/8/22 20:21, Sean Anderson wrote:
On 4/26/22 8:37 AM, Patrick Delaunay wrote:
Add the counter of the PLL user n_pll_cons managed by the 2 functions
stm32_usbphyc_pll_enable / stm32_usbphyc_pll_disable.
This counter allow to remove the function stm32_usbphyc_is_init
and it is a preliminary step for ck_usbo_48m introduction.
Is it necessary to disable this clock before booting to Linux? If it isn't,
then perhaps it is simpler to just not disable the clock.
--Sean
No, it is not necessary, we only need to enable the clock for the first user.
I copy the clock behavior from kernel,
but I agree that can be simpler.
Amelie any notice about this point ?
Do you prefer that I kept the behavior - same as kernel driver - or I simplify
the U-Boot driver ?
In case the PLL has not been disabled before Kernel boot, usbphyc Kernel driver
will wait for the PLL pwerdown.
USB could also not being used in Kernel, so PLL would remain enabled, and would
waste power.
I am rather in favor of disabling the PLL.
It should be disabled if clk_ignore_unused is not in the kernel parameters,
as long as Linux is also aware of the clock.
Generally, I would like to avoid refcounting if possible. Many U-Boot
drivers do not disable their clocks (because they don't do any cleanup),
so you can end up with the clock staying on anyway.
--Sean
Regards,
Amelie
Patrick
Signed-off-by: Patrick Delaunay
---
drivers/phy/phy-stm32-usbphyc.c | 76 +
1 file changed, 48 insertions(+), 28 deletions(-)
diff --git a/drivers/phy/phy-stm32-usbphyc.c b/drivers/phy/phy-stm32-usbphyc.c
index 9c1dcfae52..16c8799eca 100644
--- a/drivers/phy/phy-stm32-usbphyc.c
+++ b/drivers/phy/phy-stm32-usbphyc.c
@@ -65,6 +65,7 @@ struct stm32_usbphyc {
bool init;
bool powered;
} phys[MAX_PHYS];
+ int n_pll_cons;
};
static void stm32_usbphyc_get_pll_params(u32 clk_rate,
@@ -124,18 +125,6 @@ static int stm32_usbphyc_pll_init(struct stm32_usbphyc
*usbphyc)
return 0;
}
-static bool stm32_usbphyc_is_init(struct stm32_usbphyc *usbphyc)
-{
- int i;
-
- for (i = 0; i < MAX_PHYS; i++) {
- if (usbphyc->phys[i].init)
- return true;
- }
-
- return false;
-}
-
static bool stm32_usbphyc_is_powered(struct stm32_usbphyc *usbphyc)
{
int i;
@@ -148,18 +137,17 @@ static bool stm32_usbphyc_is_powered(struct stm32_usbphyc
*usbphyc)
return false;
}
-static int stm32_usbphyc_phy_init(struct phy *phy)
+static int stm32_usbphyc_pll_enable(struct stm32_usbphyc *usbphyc)
{
- struct stm32_usbphyc *usbphyc = dev_get_priv(phy->dev);
- struct stm32_usbphyc_phy *usbphyc_phy = usbphyc->phys + phy->id;
bool pllen = readl(usbphyc->base + STM32_USBPHYC_PLL) & PLLEN ?
true : false;
int ret;
- dev_dbg(phy->dev, "phy ID = %lu\n", phy->id);
- /* Check if one phy port has already configured the pll */
- if (pllen && stm32_usbphyc_is_init(usbphyc))
- goto initialized;
+ /* Check if one consumer has already configured the pll */
+ if (pllen && usbphyc->n_pll_cons) {
+ usbphyc->n_pll_cons++;
+ return 0;
+ }
if (usbphyc->vdda1v1) {
ret = regulator_set_enable(usbphyc->vdda1v1, true);
@@ -190,23 +178,19 @@ static int stm32_usbphyc_phy_init(struct phy *phy)
if (!(readl(usbphyc->base + STM32_USBPHYC_PLL) & PLLEN))
return -EIO;
-initialized:
- usbphyc_phy->init = true;
+ usbphyc->n_pll_cons++;
return 0;
}
-static int stm32_usbphyc_phy_exit(struct phy *phy)
+static int stm32_usbphyc_pll_disable(struct stm32_usbphyc *usbphyc)
{
- struct stm32_usbphyc *usbphyc = dev_get_priv(phy->dev);
- struct stm32_usbphyc_phy *usbphyc_phy = usbphyc->phys + phy->id;
int ret;
- dev_dbg(phy->dev, "phy ID = %lu\n", phy->id);
- usbphyc_phy->init = false;
+ usbphyc->n_pll_cons--;
- /* Check if other phy port requires pllen */
- if (stm32_usbphyc_is_init(usbphyc))
+ /* Check if other consumer requires pllen */
+ if (usbphyc->n_pll_cons)
return 0;
clrbits_le32(usbphyc->base + STM32_USBPHYC_PLL, PLLEN);
@@ -235,6 +219,42 @@ static int stm32_usbphyc_phy_exit(struct phy *phy)
return 0;
}
+static int stm32_usbphyc_phy_init(struct phy *phy)
+{
+ struct stm32_usbphyc *usbphyc = dev_get_priv(phy->dev);
+ struct stm32_usbphyc_phy *usbphyc_phy = usbphyc->phys + phy->id;
+ int ret;
+
+ dev_dbg(phy->dev, "phy ID = %lu\n", phy->id);
+ if (usbphyc_phy->init)
+ return 0;
+
+ ret = stm32_usbphyc_pll_enable(usbphyc);
+ if (ret)
+ return log_ret(ret);
+
+ usbphyc_phy->init = true;
+
+ return 0;
+}
+
+static int stm32_usbphyc_phy_exit(struct phy *phy)
+{
+ struct stm32_usbphyc *usbphyc = dev_get_priv(phy->dev);
+ struct stm32_usbphyc_phy *usbphyc_p
Re: [PATCH 0/4] stm32mp: add minimal RCC support for STM32MP13
Hi Patrick, On 5/10/22 3:51 AM, Patrick Delaunay wrote: Add a minimal support for STM32MP13 RCC, the reset and clock controller - update of the RCC MISC driver to bind the correct clock and reset driver - reset driver, same than STM32MP15x = drivers/reset/stm32-reset.c - clock driver, add a empty driver for STM32MP13x = drivers/clk/stm32/clk-stm32mp13.c - Add RCC node in SOC device tree with u-boot,dm-pre-reloc property This serie is only a preliminary step for STM32MP13 clock and reset support in U-Boot, based on Linux kernel binding introduced by [1] and it prepares the next device tree alignment with Linux kernel. The functional STMP13 clock driver based on CCF and on SCMI clocks provided by OP-TEE and the clock and reset references in SOC device tree will be pushed when the associated patches in [1] will be accepted. [1] Introduction of STM32MP13 RCC driver (Reset Clock Controller) https://lore.kernel.org/linux-arm-kernel/20220316131000.9874-1-gabriel.fernan...@foss.st.com/ I'm not really sure what the purpose of this series is. Can you elaborate a bit on why we need a dummy clock driver? Why don't you just add the binding to the device tree without the associated driver? --Sean
Re: [PATCH 1/4] clk: Add directory for STM32 clock drivers
On 5/10/22 3:51 AM, Patrick Delaunay wrote:
Add a directory in drivers/clk to regroup the clock drivers for all
STM32 Soc with CONFIG_ARCH_STM32 (MCUs with cortex M) or
CONFIG_ARCH_STM32MP (MPUs with cortex A).
Signed-off-by: Patrick Delaunay
---
MAINTAINERS| 2 +-
drivers/clk/Kconfig| 17 +
drivers/clk/Makefile | 5 ++---
drivers/clk/stm32/Kconfig | 23 +++
drivers/clk/stm32/Makefile | 7 +++
drivers/clk/{ => stm32}/clk_stm32f.c | 0
drivers/clk/{ => stm32}/clk_stm32h7.c | 0
drivers/clk/{ => stm32}/clk_stm32mp1.c | 0
8 files changed, 34 insertions(+), 20 deletions(-)
create mode 100644 drivers/clk/stm32/Kconfig
create mode 100644 drivers/clk/stm32/Makefile
rename drivers/clk/{ => stm32}/clk_stm32f.c (100%)
rename drivers/clk/{ => stm32}/clk_stm32h7.c (100%)
rename drivers/clk/{ => stm32}/clk_stm32mp1.c (100%)
diff --git a/MAINTAINERS b/MAINTAINERS
index 56be0bfad0..3f37edd716 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -469,7 +469,7 @@ S: Maintained
F:arch/arm/mach-stm32mp/
F:doc/board/st/
F:drivers/adc/stm32-adc*
-F: drivers/clk/clk_stm32mp1.c
+F: drivers/clk/stm32/
F:drivers/gpio/stm32_gpio.c
F:drivers/hwspinlock/stm32_hwspinlock.c
F:drivers/i2c/stm32f7_i2c.c
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 6dc271f71b..98ad481d9e 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -140,22 +140,6 @@ config CLK_SCMI
by a SCMI agent based on SCMI clock protocol communication
with a SCMI server.
-config CLK_STM32F
- bool "Enable clock driver support for STM32F family"
- depends on CLK && (STM32F7 || STM32F4)
- default y
- help
- This clock driver adds support for RCC clock management
- for STM32F4 and STM32F7 SoCs.
-
-config CLK_STM32MP1
- bool "Enable RCC clock driver for STM32MP1"
- depends on ARCH_STM32MP && CLK
- default y
- help
- Enable the STM32 clock (RCC) driver. Enable support for
- manipulating STM32MP1's on-SoC clocks.
-
config CLK_HSDK
bool "Enable cgu clock driver for HSDK boards"
depends on CLK && TARGET_HSDK
@@ -225,6 +209,7 @@ source "drivers/clk/owl/Kconfig"
source "drivers/clk/renesas/Kconfig"
source "drivers/clk/sunxi/Kconfig"
source "drivers/clk/sifive/Kconfig"
+source "drivers/clk/stm32/Kconfig"
source "drivers/clk/tegra/Kconfig"
source "drivers/clk/ti/Kconfig"
source "drivers/clk/uniphier/Kconfig"
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index bb4eee5d99..09fbaf6233 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -22,6 +22,8 @@ obj-$(CONFIG_ARCH_MESON) += meson/
obj-$(CONFIG_ARCH_MTMIPS) += mtmips/
obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
obj-$(CONFIG_ARCH_SOCFPGA) += altera/
+obj-$(CONFIG_ARCH_STM32) += stm32/
+obj-$(CONFIG_ARCH_STM32MP) += stm32/
obj-$(CONFIG_ARCH_SUNXI) += sunxi/
obj-$(CONFIG_CLK_AT91) += at91/
obj-$(CONFIG_CLK_BCM6345) += clk_bcm6345.o
@@ -38,8 +40,6 @@ obj-$(CONFIG_CLK_OWL) += owl/
obj-$(CONFIG_CLK_RENESAS) += renesas/
obj-$(CONFIG_CLK_SCMI) += clk_scmi.o
obj-$(CONFIG_CLK_SIFIVE) += sifive/
-obj-$(CONFIG_CLK_STM32F) += clk_stm32f.o
-obj-$(CONFIG_CLK_STM32MP1) += clk_stm32mp1.o
obj-$(CONFIG_CLK_UNIPHIER) += uniphier/
obj-$(CONFIG_CLK_VERSACLOCK) += clk_versaclock.o
obj-$(CONFIG_CLK_VERSAL) += clk_versal.o
@@ -52,4 +52,3 @@ obj-$(CONFIG_MACH_PIC32) += clk_pic32.o
obj-$(CONFIG_SANDBOX_CLK_CCF) += clk_sandbox_ccf.o
obj-$(CONFIG_SANDBOX) += clk_sandbox.o
obj-$(CONFIG_SANDBOX) += clk_sandbox_test.o
-obj-$(CONFIG_STM32H7) += clk_stm32h7.o
diff --git a/drivers/clk/stm32/Kconfig b/drivers/clk/stm32/Kconfig
new file mode 100644
index 00..eac3fc1e9d
--- /dev/null
+++ b/drivers/clk/stm32/Kconfig
@@ -0,0 +1,23 @@
+config CLK_STM32F
+ bool "Enable clock driver support for STM32F family"
+ depends on CLK && (STM32F7 || STM32F4)
+ default y
+ help
+ This clock driver adds support for RCC clock management
+ for STM32F4 and STM32F7 SoCs.
+
+config CLK_STM32H7
+ bool "Enable clock driver support for STM32H7 family"
+ depends on CLK && STM32H7
+ default y
+ help
+ This clock driver adds support for RCC clock management
+ for STM32H7 SoCs.
+
+config CLK_STM32MP1
+ bool "Enable RCC clock driver for STM32MP15"
+ depends on ARCH_STM32MP && CLK
+ default y if STM32MP15x
+ help
+ Enable the STM32 clock (RCC) driver. Enable support for
+ manipulating STM32MP15's on-SoC clocks.
diff --git a/drivers/clk/stm32/Makefile b/drivers/clk/stm32/Makefile
new file mode 100644
index 00..b420eeaa4e
--- /dev/null
+++ b/drivers/clk/stm32/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# Copyright (C) 2022, STMicroelectro
Re: [PATCH v4 05/25] mips: mtmips: add support for MediaTek MT7621 SoC
Hi Weijie,
I just commented on the device tree stuff.
On 5/10/22 8:18 AM, Weijie Gao wrote:
This patch adds support for MediaTek MT7621 SoC.
All files are dedicated for u-boot.
The default build target is u-boot-mt7621.bin.
The specification of this chip:
https://www.mediatek.com/products/homenetworking/mt7621
Signed-off-by: Weijie Gao
---
v4 changes:
Add full support for booting from flash (SPL/TPL support)
Boot all cores/VPEs
Use binman to generate final binary
Use binman to embed external binary blob
v3 changes:
Update clock name for mt7621.dtsi due to clk driver changed
v2 changes:
Add a kconfig for max supported ram size
Remove network configs from default config file
---
arch/mips/dts/mt7621-u-boot.dtsi | 79
arch/mips/dts/mt7621.dtsi| 370 +++
arch/mips/mach-mtmips/Kconfig| 49 ++-
arch/mips/mach-mtmips/Makefile | 4 +
arch/mips/mach-mtmips/cpu.c | 2 +-
arch/mips/mach-mtmips/mt7621/Kconfig | 95 +
arch/mips/mach-mtmips/mt7621/Makefile| 14 +
arch/mips/mach-mtmips/mt7621/init.c | 229
arch/mips/mach-mtmips/mt7621/mt7621.h| 229
arch/mips/mach-mtmips/mt7621/serial.c| 23 ++
arch/mips/mach-mtmips/mt7621/spl/Makefile| 9 +
arch/mips/mach-mtmips/mt7621/spl/cps.c | 152
arch/mips/mach-mtmips/mt7621/spl/dram.c | 143 +++
arch/mips/mach-mtmips/mt7621/spl/dram.h | 37 ++
arch/mips/mach-mtmips/mt7621/spl/launch.c| 100 +
arch/mips/mach-mtmips/mt7621/spl/launch.h| 52 +++
arch/mips/mach-mtmips/mt7621/spl/launch_ll.S | 357 ++
arch/mips/mach-mtmips/mt7621/spl/serial.c| 24 ++
arch/mips/mach-mtmips/mt7621/spl/spl.c | 95 +
arch/mips/mach-mtmips/mt7621/spl/start.S | 226 +++
arch/mips/mach-mtmips/mt7621/sram_init.S | 22 ++
arch/mips/mach-mtmips/mt7621/tpl/Makefile| 4 +
arch/mips/mach-mtmips/mt7621/tpl/start.S | 161
arch/mips/mach-mtmips/mt7621/tpl/tpl.c | 146
include/configs/mt7621.h | 67
25 files changed, 2683 insertions(+), 6 deletions(-)
create mode 100644 arch/mips/dts/mt7621-u-boot.dtsi
create mode 100644 arch/mips/dts/mt7621.dtsi
create mode 100644 arch/mips/mach-mtmips/mt7621/Kconfig
create mode 100644 arch/mips/mach-mtmips/mt7621/Makefile
create mode 100644 arch/mips/mach-mtmips/mt7621/init.c
create mode 100644 arch/mips/mach-mtmips/mt7621/mt7621.h
create mode 100644 arch/mips/mach-mtmips/mt7621/serial.c
create mode 100644 arch/mips/mach-mtmips/mt7621/spl/Makefile
create mode 100644 arch/mips/mach-mtmips/mt7621/spl/cps.c
create mode 100644 arch/mips/mach-mtmips/mt7621/spl/dram.c
create mode 100644 arch/mips/mach-mtmips/mt7621/spl/dram.h
create mode 100644 arch/mips/mach-mtmips/mt7621/spl/launch.c
create mode 100644 arch/mips/mach-mtmips/mt7621/spl/launch.h
create mode 100644 arch/mips/mach-mtmips/mt7621/spl/launch_ll.S
create mode 100644 arch/mips/mach-mtmips/mt7621/spl/serial.c
create mode 100644 arch/mips/mach-mtmips/mt7621/spl/spl.c
create mode 100644 arch/mips/mach-mtmips/mt7621/spl/start.S
create mode 100644 arch/mips/mach-mtmips/mt7621/sram_init.S
create mode 100644 arch/mips/mach-mtmips/mt7621/tpl/Makefile
create mode 100644 arch/mips/mach-mtmips/mt7621/tpl/start.S
create mode 100644 arch/mips/mach-mtmips/mt7621/tpl/tpl.c
create mode 100644 include/configs/mt7621.h
diff --git a/arch/mips/dts/mt7621-u-boot.dtsi b/arch/mips/dts/mt7621-u-boot.dtsi
new file mode 100644
index 00..b9b02003a5
--- /dev/null
+++ b/arch/mips/dts/mt7621-u-boot.dtsi
@@ -0,0 +1,79 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2022 MediaTek Inc. All rights reserved.
+ *
+ * Author: Weijie Gao
+ */
+
+#include
+
+/ {
+ binman: binman {
+ multiple-images;
+ };
+};
+
+&binman {
+ u-boot-spl-ddr {
+ align = <4>;
+ align-size = <4>;
+ filename = "u-boot-spl-ddr.bin";
+ pad-byte = <0xff>;
+
+ u-boot-spl {
+ align-end = <4>;
+ filename = "u-boot-spl.bin";
+ };
+
+ stage_bin {
+ filename = "mt7621_stage_sram.bin";
+ type = "blob-ext";
+ };
+ };
+
+ spl-img {
+ filename = "u-boot-spl-ddr.img";
+
+ mkimage {
+#ifdef CONFIG_MT7621_BOOT_FROM_NAND
+ args = "-T", "mtk_image", "-n", "mt7621=1",
+ "-a", __stringify(CONFIG_SPL_TEXT_BASE),
+ "-e", __stringify(CONFIG_SPL_TEXT_BASE);
+#else
+ args = "-A", "mips", "-T", "standalone", "-O", "u-boot",
+ "-C", "none", "-n", "MT7621 U-Boot SPL",
Re: [PATCH v4 08/25] clk: mtmips: add clock driver for MediaTek MT7621 SoC
Hi Weijie,
I found a copy of the MT7260 programming guide, which I am using
as a reference. I assume that they have not diverged too much,
but presumably most discrepencies will be accounted for in the
difference in part numbers.
On 5/10/22 8:18 AM, Weijie Gao wrote:
This patch adds a clock driver for MediaTek MT7621 SoC.
This driver provides clock gate control as well as getting clock frequency
for CPU/SYS/XTAL and some peripherals.
Signed-off-by: Weijie Gao
---
v4 changes: none
v3 changes: update clock definitions to match upstream kernel
v2 changes: none
---
drivers/clk/mtmips/Makefile| 1 +
drivers/clk/mtmips/clk-mt7621.c| 315 +
include/dt-bindings/clock/mt7621-clk.h | 46
3 files changed, 362 insertions(+)
create mode 100644 drivers/clk/mtmips/clk-mt7621.c
create mode 100644 include/dt-bindings/clock/mt7621-clk.h
diff --git a/drivers/clk/mtmips/Makefile b/drivers/clk/mtmips/Makefile
index 732e7f2545..ee8b5afe87 100644
--- a/drivers/clk/mtmips/Makefile
+++ b/drivers/clk/mtmips/Makefile
@@ -1,4 +1,5 @@
# SPDX-License-Identifier: GPL-2.0
obj-$(CONFIG_SOC_MT7620) += clk-mt7620.o
+obj-$(CONFIG_SOC_MT7621) += clk-mt7621.o
obj-$(CONFIG_SOC_MT7628) += clk-mt7628.o
diff --git a/drivers/clk/mtmips/clk-mt7621.c b/drivers/clk/mtmips/clk-mt7621.c
new file mode 100644
index 00..e8203016a5
--- /dev/null
+++ b/drivers/clk/mtmips/clk-mt7621.c
@@ -0,0 +1,315 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2022 MediaTek Inc. All rights reserved.
+ *
+ * Author: Weijie Gao
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define SYSC_MAP_SIZE 0x100
+#define MEMC_MAP_SIZE 0x1000
+
+/* SYSC */
+#define SYSCFG0_REG0x10
+#define XTAL_MODE_SEL_S6
+#define XTAL_MODE_SEL_M0x1c0
Please use GENMASK and BIT for these defines.
+
+#define CLKCFG0_REG0x2c
+#define CPU_CLK_SEL_S 30
+#define CPU_CLK_SEL_M 0xc000
+#define PERI_CLK_SEL 0x10
+
+#define CLKCFG1_REG0x30
+
+#define CUR_CLK_STS_REG0x44
+#define CUR_CPU_FDIV_S 8
+#define CUR_CPU_FDIV_M 0x1f00
+#define CUR_CPU_FFRAC_S0
+#define CUR_CPU_FFRAC_M0x1f
+
+/* MEMC */
+#define MEMPLL1_REG0x0604
+#define RG_MEPL_DIV2_SEL_S 1
+#define RG_MEPL_DIV2_SEL_M 0x06
+
+#define MEMPLL6_REG0x0618
+#define MEMPLL18_REG 0x0648
+#define RG_MEPL_PREDIV_S 12
+#define RG_MEPL_PREDIV_M 0x3000
+#define RG_MEPL_FBDIV_S4
+#define RG_MEPL_FBDIV_M0x7f0
+
+/* EPLL clock */
+#define EPLL_CLK 5000
+
+struct mt7621_clk_priv {
+ void __iomem *sysc_base;
+ void __iomem *memc_base;
+ int cpu_clk;
+ int ddr_clk;
+ int sys_clk;
+ int xtal_clk;
+};
+
+enum mt7621_clk_src {
+ CLK_SRC_CPU,
+ CLK_SRC_DDR,
+ CLK_SRC_SYS,
+ CLK_SRC_XTAL,
+ CLK_SRC_PERI,
+ CLK_SRC_125M,
+ CLK_SRC_150M,
+ CLK_SRC_250M,
+ CLK_SRC_270M,
+
+ __CLK_SRC_MAX
+};
+
+struct mt7621_clk_map {
+ u32 cgbit;
+ enum mt7621_clk_src clksrc;
+};
+
+#define CLK_MAP(_id, _cg, _src) \
+ [_id] = { .cgbit = (_cg), .clksrc = (_src) }
+
+#define CLK_MAP_SRC(_id, _src) \
+ [_id] = { .cgbit = UINT32_MAX, .clksrc = (_src) }
+
+static const struct mt7621_clk_map mt7621_clk_mappings[] = {
+ CLK_MAP_SRC(MT7621_CLK_XTAL, CLK_SRC_XTAL),
+ CLK_MAP_SRC(MT7621_CLK_CPU, CLK_SRC_CPU),
+ CLK_MAP_SRC(MT7621_CLK_BUS, CLK_SRC_SYS),
+ CLK_MAP_SRC(MT7621_CLK_50M, CLK_SRC_PERI),
+ CLK_MAP_SRC(MT7621_CLK_125M, CLK_SRC_125M),
+ CLK_MAP_SRC(MT7621_CLK_150M, CLK_SRC_150M),
+ CLK_MAP_SRC(MT7621_CLK_250M, CLK_SRC_250M),
+ CLK_MAP_SRC(MT7621_CLK_270M, CLK_SRC_270M),
+
+ CLK_MAP(MT7621_CLK_HSDMA, 5, CLK_SRC_150M),
+ CLK_MAP(MT7621_CLK_FE, 6, CLK_SRC_250M),
+ CLK_MAP(MT7621_CLK_SP_DIVTX, 7, CLK_SRC_270M),
+ CLK_MAP(MT7621_CLK_TIMER, 8, CLK_SRC_PERI),
+ CLK_MAP(MT7621_CLK_PCM, 11, CLK_SRC_270M),
+ CLK_MAP(MT7621_CLK_PIO, 13, CLK_SRC_PERI),
+ CLK_MAP(MT7621_CLK_GDMA, 14, CLK_SRC_SYS),
+ CLK_MAP(MT7621_CLK_NAND, 15, CLK_SRC_125M),
+ CLK_MAP(MT7621_CLK_I2C, 16, CLK_SRC_PERI),
+ CLK_MAP(MT7621_CLK_I2S, 17, CLK_SRC_270M),
Should this be PERI?
+ CLK_MAP(MT7621_CLK_SPI, 18, CLK_SRC_SYS),
+ CLK_MAP(MT7621_CLK_UART1, 19, CLK_SRC_PERI),
+ CLK_MAP(MT7621_CLK_UART2, 20, CLK_SRC_PERI),
+ CLK_MAP(MT7621_CLK_UART3, 21, CLK_SRC_PERI),
+ CLK_MAP(MT7621_CLK_ETH, 23, CLK_SRC_PERI),
+ CLK_MAP(MT7621_CLK_PCIE0, 2
Re: [PATCH 0/7] clk: sunxi: Out-of-bounds access fix and driver cleanup
On 5/9/22 1:29 AM, Samuel Holland wrote: This series fixes an issue with out-of-bounds access to the gate array (patches 1-2), uses the rearranged array size information to remove a bunch of duplicate code (patches 3-4), and then simplifies how the reset driver is bound (patches 5-7). The original motivation for these changes was adding a driver for the legacy A31/A23/A33 PRCM binding (which I will send separately), and trying to use OF_PLATDATA in SPL (which did not work out). But I think at least some of the cleanup is worth applying on its own. Patch 4 is generally the same change I made between v1 and v2 of the pinctrl series, using some #ifdefs to share a U_BOOT_DRIVER. It's not quite as clean as the pinctrl case, because here the SoC-specific parts are in different files, so all of the CCU descriptors have to be global. Samuel Holland (7): clk: sunxi: Store the array sizes in the CCU descriptor clk: sunxi: Prevent out-of-bounds gate array access reset: sunxi: Get the reset count from the CCU descriptor clk: sunxi: Use a single driver for all variants clk: sunxi: Convert driver private data to platform data reset: sunxi: Convert driver private data to platform data reset: sunxi: Reuse the platform data from the clock driver drivers/clk/sunxi/clk_a10.c | 27 +- drivers/clk/sunxi/clk_a10s.c | 27 +- drivers/clk/sunxi/clk_a23.c | 27 +- drivers/clk/sunxi/clk_a31.c | 25 + drivers/clk/sunxi/clk_a31_r.c | 29 +- drivers/clk/sunxi/clk_a64.c | 25 + drivers/clk/sunxi/clk_a80.c | 36 ++-- drivers/clk/sunxi/clk_a83t.c | 25 + drivers/clk/sunxi/clk_h3.c| 27 +- drivers/clk/sunxi/clk_h6.c| 25 + drivers/clk/sunxi/clk_h616.c | 25 + drivers/clk/sunxi/clk_h6_r.c | 27 +- drivers/clk/sunxi/clk_r40.c | 25 + drivers/clk/sunxi/clk_sunxi.c | 168 ++ drivers/clk/sunxi/clk_v3s.c | 27 +- drivers/reset/reset-sunxi.c | 55 ++- include/clk/sunxi.h | 21 + 17 files changed, 208 insertions(+), 413 deletions(-) For this series: Acked-by: Sean Anderson
[PATCH] mach-rockchip: make_fit_atf.py: support OP-TEE tee.bin v1 format
This commit adds support for the OP-TEE 'tee.bin' v1 format for Rockchip
platforms.
Since OP-TEE 3.8.0, tee.bin contains meta-data in a proprietary format
in addition to the ELF data. They are essential information for proper
initialization of the TEE core, such as the size of the memory region
covered by the TEE or a compact representation of runtime relocation
data when ASLR is enabled.
With OP-TEE 3.8.0 onwards, 'tee.elf' MUST NOT be used and 'tee.bin'
MUST be used instead. Ignoring this recommendation can lead to crashes
as described in [3].
Link: [1]
https://github.com/OP-TEE/optee_os/commit/5dd1570ac5b0f6563b1a9c074533a19107b8222d
Link: [2]
https://github.com/OP-TEE/optee_os/blob/3.17.0/scripts/gen_tee_bin.py#L275-L302
Link: [3] https://github.com/OP-TEE/optee_os/issues/4542
Signed-off-by: Jerome Forissier
---
arch/arm/mach-rockchip/make_fit_atf.py | 43 +-
1 file changed, 35 insertions(+), 8 deletions(-)
diff --git a/arch/arm/mach-rockchip/make_fit_atf.py
b/arch/arm/mach-rockchip/make_fit_atf.py
index f3224d2555..fcea652388 100755
--- a/arch/arm/mach-rockchip/make_fit_atf.py
+++ b/arch/arm/mach-rockchip/make_fit_atf.py
@@ -137,7 +137,7 @@ def generate_atf_fit_dts_bl31(fit_file, bl31_file_name,
tee_file_name, dtbs_file
num_segments = len(segments)
if tee_file_name:
-tee_segments = unpack_elf(tee_file_name)
+tee_segments = unpack_tee_file(tee_file_name)
for index, entry, paddr, data in tee_segments:
append_tee_node(fit_file, num_segments + index + 1, paddr, entry)
num_segments = num_segments + len(tee_segments)
@@ -169,7 +169,7 @@ def generate_atf_binary(bl31_file_name):
def generate_tee_binary(tee_file_name):
if tee_file_name:
-for index, entry, paddr, data in unpack_elf(tee_file_name):
+for index, entry, paddr, data in unpack_tee_file(tee_file_name):
file_name = 'tee_0x%08x.bin' % paddr
with open(file_name, "wb") as atf:
atf.write(data)
@@ -194,6 +194,31 @@ def unpack_elf(filename):
segments.append((index, e_entry, p_paddr, p_data))
return segments
+def unpack_tee_file(filename):
+if filename.endswith('.elf'):
+return unpack_elf(filename)
+with open(filename, 'rb') as file:
+bin = file.read()
+segments = []
+if bin[0:5] == b'OPTE\x01':
+# OP-TEE v1 format (tee.bin)
+init_sz, start_hi, start_lo, _, paged_sz = struct.unpack_from('<5I',
+ bin,
+ 0x8)
+if paged_sz != 0:
+raise ValueError("OP-TEE paged mode not supported")
+e_entry = (start_hi << 32) + start_lo
+p_addr = e_entry
+p_data = bin[0x1c:]
+if len(p_data) != init_sz:
+raise ValueError("Invalid file '%s': size mismatch "
+ "(expected %d, have %d)" % (filename, init_sz,
+ len(p_data)))
+segments.append((0, e_entry, p_addr, p_data))
+else:
+raise ValueError("Unknown format for TEE file '%s'" % filename)
+return segments
+
def main():
uboot_elf = "./u-boot"
fit_its = sys.stdout
@@ -210,11 +235,13 @@ def main():
logging.warning(' Please read Building section in doc/README.rockchip')
if "TEE" in os.environ:
-tee_elf = os.getenv("TEE")
+tee_file = os.getenv("TEE")
+elif os.path.isfile("./tee.bin"):
+tee_file = "./tee.bin"
elif os.path.isfile("./tee.elf"):
-tee_elf = "./tee.elf"
+tee_file = "./tee.elf"
else:
-tee_elf = ""
+tee_file = ""
opts, args = getopt.getopt(sys.argv[1:], "o:u:b:t:h")
for opt, val in opts:
@@ -225,16 +252,16 @@ def main():
elif opt == "-b":
bl31_elf = val
elif opt == "-t":
-tee_elf = val
+tee_file = val
elif opt == "-h":
print(__doc__)
sys.exit(2)
dtbs = args
-generate_atf_fit_dts(fit_its, bl31_elf, tee_elf, uboot_elf, dtbs)
+generate_atf_fit_dts(fit_its, bl31_elf, tee_file, uboot_elf, dtbs)
generate_atf_binary(bl31_elf)
-generate_tee_binary(tee_elf)
+generate_tee_binary(tee_file)
if __name__ == "__main__":
main()
--
2.17.1
Re: [PATCH V2 3/4] arm: mach-imx: cmd_nandbcb fix bad block handling
On Tue, May 10, 2022 at 11:49 PM Michael Nazzareno Trimarchi
wrote:
>
> Hi Tim
>
> Do you have an alternative board to test?
>
Michael,
Yes sorry... I tested the series and had the reply in my draft folder.
I sent it just now in response to the cover letter.
Best regards,
Tim
> Michael
>
> On Fri, May 6, 2022 at 4:41 PM Han Xu wrote:
> >
> > On 22/04/27 07:50AM, Michael Trimarchi wrote:
> > > The badblock should be skipped properly in reading and writing.
> > > Fix the logic. The bcb struct is written, skipping the bad block,
> > > so we need to read using the same logic. This was tested create
> > > bad block in the area and then flash it and read it back.
> > >
> > > Cc: Han Xu
> > > Cc: Fabio Estevam
> > > Signed-off-by: Michael Trimarchi
> >
> > Acked-by: Han Xu
> >
> > > ---
> > > V1->V2:
> > > - Adjust the commit message
> > > - Add Cc Han Xu and Fabio
> > > - move out from RFC
> > > ---
> > > arch/arm/mach-imx/cmd_nandbcb.c | 21 +++--
> > > 1 file changed, 7 insertions(+), 14 deletions(-)
> > >
> > > diff --git a/arch/arm/mach-imx/cmd_nandbcb.c
> > > b/arch/arm/mach-imx/cmd_nandbcb.c
> > > index f119e9f88d..c54f52b343 100644
> > > --- a/arch/arm/mach-imx/cmd_nandbcb.c
> > > +++ b/arch/arm/mach-imx/cmd_nandbcb.c
> > > @@ -506,10 +506,6 @@ static int read_fcb(struct boot_config *boot_cfg,
> > > struct fcb_block *fcb,
> > > int ret = 0;
> > >
> > > mtd = boot_cfg->mtd;
> > > - if (mtd_block_isbad(mtd, off)) {
> > > - printf("Block %d is bad, skipped\n",
> > > (int)CONV_TO_BLOCKS(off));
> > > - return 1;
> > > - }
> > >
> > > fcb_raw_page = kzalloc(mtd->writesize + mtd->oobsize, GFP_KERNEL);
> > > if (!fcb_raw_page) {
> > > @@ -530,7 +526,7 @@ static int read_fcb(struct boot_config *boot_cfg,
> > > struct fcb_block *fcb,
> > > else if (plat_config.misc_flags & FCB_ENCODE_BCH_40b)
> > > mxs_nand_mode_fcb_40bit(mtd);
> > >
> > > - ret = nand_read(mtd, off, &size, (u_char *)fcb);
> > > + ret = nand_read_skip_bad(mtd, off, &size, NULL, mtd->size,
> > > (u_char *)fcb);
> > >
> > > /* switch BCH back */
> > > mxs_nand_mode_normal(mtd);
> > > @@ -617,6 +613,7 @@ static int write_fcb(struct boot_config *boot_cfg,
> > > struct fcb_block *fcb)
> > > for (i = 0; i < g_boot_search_count; i++) {
> > > if (mtd_block_isbad(mtd, off)) {
> > > printf("Block %d is bad, skipped\n", i);
> > > + off += mtd->erasesize;
> > > continue;
> > > }
> > >
> > > @@ -676,20 +673,15 @@ static int read_dbbt(struct boot_config *boot_cfg,
> > > struct dbbt_block *dbbt,
> > > void *dbbt_data_page, loff_t off)
> > > {
> > > size_t size;
> > > + size_t actual_size;
> > > struct mtd_info *mtd;
> > > loff_t to;
> > > int ret;
> > >
> > > mtd = boot_cfg->mtd;
> > >
> > > - if (mtd_block_isbad(mtd, off)) {
> > > - printf("Block %d is bad, skipped\n",
> > > -(int)CONV_TO_BLOCKS(off));
> > > - return 1;
> > > - }
> > > -
> > > size = sizeof(struct dbbt_block);
> > > - ret = nand_read(mtd, off, &size, (u_char *)dbbt);
> > > + ret = nand_read_skip_bad(mtd, off, &size, &actual_size, mtd->size,
> > > (u_char *)dbbt);
> > > printf("NAND DBBT read from 0x%llx offset 0x%zx read: %s\n",
> > > off, size, ret ? "ERROR" : "OK");
> > > if (ret)
> > > @@ -697,9 +689,9 @@ static int read_dbbt(struct boot_config *boot_cfg,
> > > struct dbbt_block *dbbt,
> > >
> > > /* dbbtpages == 0 if no bad blocks */
> > > if (dbbt->dbbtpages > 0) {
> > > - to = off + 4 * mtd->writesize;
> > > + to = off + 4 * mtd->writesize + actual_size - size;
> > > size = mtd->writesize;
> > > - ret = nand_read(mtd, to, &size, dbbt_data_page);
> > > + ret = nand_read_skip_bad(mtd, to, &size, NULL, mtd->size,
> > > dbbt_data_page);
> > > printf("DBBT data read from 0x%llx offset 0x%zx read: %s\n",
> > > to, size, ret ? "ERROR" : "OK");
> > >
> > > @@ -729,6 +721,7 @@ static int write_dbbt(struct boot_config *boot_cfg,
> > > struct dbbt_block *dbbt,
> > > if (mtd_block_isbad(mtd, off)) {
> > > printf("Block %d is bad, skipped\n",
> > > (int)(i + CONV_TO_BLOCKS(off)));
> > > + off += mtd->erasesize;
> > > continue;
> > > }
> > >
> > > --
> > > 2.25.1
> > >
>
>
>
> --
> Michael Nazzareno Trimarchi
> Co-Founder & Chief Executive Officer
> M. +39 347 913 2170
> mich...@amarulasolutions.com
> __
>
> Amarula Solutions BV
> Joop Geesinkweg 125, 1114 AB, Amsterdam, NL
> T. +31 (0)85 111 9172
> i...@amaru
Re: [PATCH V2 0/4] MXS nand fixes in SPL
On Tue, Apr 26, 2022 at 10:50 PM Michael Trimarchi wrote: > > Those patches come after some testing of failing in factory on some > unit. We found out that the bootrom imx loader was not able to handling > badblock. This can be a limit of the implementation right now in imx8mn. > Anyway not all the imx platform has the support of this loader. I found > some problems on the implementation so I have fixed it up according the > experience of Sitara. I tested only using a Fit Image as a flash > container. This version add in the series the fix of cmd_nandbcb and > the fix of spl_nand load. I can imagine that a lot of boards and users > are affected. I have started to backport this changes in some older > uboot and adapt it > > Michael Trimarchi (4): > nand: raw: mxs_nand: Fix specific hook registration > mtd: nand: mxs_nand_spl: Fix bad block skipping > arm: mach-imx: cmd_nandbcb fix bad block handling > spl: spl_nand: Fix bad block handling in fitImage > > arch/arm/mach-imx/cmd_nandbcb.c | 21 +++ > common/spl/spl_nand.c | 5 +- > drivers/mtd/nand/raw/mxs_nand.c | 32 +- > drivers/mtd/nand/raw/mxs_nand_spl.c | 90 - > 4 files changed, 73 insertions(+), 75 deletions(-) > > -- > 2.25.1 > Tested By: Tim Harvey #gwventana_nand_defconfig (imx6qdl NAND) Best Regards, Tim
[PATCH] net: dwc_eth_qos: lift parsing of max-speed DT property to common code
I have an iMX8MP with a ti,dp83867 phy in front of the eqos
interface. The phy is Gbit capable - however, the C and D differential
pairs are not physically routed to the RJ45 connector. So I need to
prevent the phy from advertising 1000Mbps.
The necessary code is almost already there in the form of a
phy_set_supported() call in eqos_start(), but the max-speed DT
property is currently only parsed in
eqos_probe_resources_stm32(). Lift that parsing to eqos_probe().
Signed-off-by: Rasmus Villemoes
---
drivers/net/dwc_eth_qos.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
index 38ccb735ee..8a54e02114 100644
--- a/drivers/net/dwc_eth_qos.c
+++ b/drivers/net/dwc_eth_qos.c
@@ -1692,8 +1692,6 @@ static int eqos_probe_resources_stm32(struct udevice *dev)
if (ret)
return -EINVAL;
- eqos->max_speed = dev_read_u32_default(dev, "max-speed", 0);
-
ret = clk_get_by_name(dev, "stmmaceth", &eqos->clk_master_bus);
if (ret) {
pr_err("clk_get_by_name(master_bus) failed: %d", ret);
@@ -1842,6 +1840,8 @@ static int eqos_probe(struct udevice *dev)
eqos->dma_regs = (void *)(eqos->regs + EQOS_DMA_REGS_BASE);
eqos->tegra186_regs = (void *)(eqos->regs + EQOS_TEGRA186_REGS_BASE);
+ eqos->max_speed = dev_read_u32_default(dev, "max-speed", 0);
+
ret = eqos_probe_resources_core(dev);
if (ret < 0) {
pr_err("eqos_probe_resources_core() failed: %d", ret);
--
2.31.1
[PATCH] net: dwc_eth_qos: fix double resource leak in eqos_remove()
Not only does eqos_remove() fail to free the buffers that have been
allocated by eqos_probe_resources_core(), it repeats those allocations
and thus drops twice as much memory on the floor.
Signed-off-by: Rasmus Villemoes
---
drivers/net/dwc_eth_qos.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
index 9d255cf95f..82ee2d9706 100644
--- a/drivers/net/dwc_eth_qos.c
+++ b/drivers/net/dwc_eth_qos.c
@@ -1884,7 +1884,7 @@ static int eqos_remove(struct udevice *dev)
eqos->config->ops->eqos_stop_clks(dev);
eqos->config->ops->eqos_remove_resources(dev);
- eqos_probe_resources_core(dev);
+ eqos_remove_resources_core(dev);
debug("%s: OK\n", __func__);
return 0;
--
2.31.1
Re: [PATCH] crypto/fsl: fsl_hash: Fix dcache issue in caam_hash_finish
On 11/05/2022 10.53, Gaurav Jain wrote: > HW accelerated hash operations are giving incorrect hash output. > so add flush and invalidate for input/output hash buffers. > > Fixes: 94e3c8c4fd (crypto/fsl - Add progressive hashing support using > hardware acceleration.) AFAICT, it takes somewhat more to fix that commit; the progressive hashing is entirely broken. It doesn't actually do anything progressive, it just stashes the address/length pairs it is given, but doesn't feed the contents of those buffers to the hardware, folding it into the hash state. So the caller must not touch the buffers it passes until the finalization. I.e. I think this won't work: char buf[SOMETHING]; update_buffer(buf); hash_update(buf, len); update_buffer_again(buf); hash_update(buf, len); And this pattern can be found in e.g. drivers/dfu/dfu.c which seems to repeatedly pass the same address (dfu->i_buf_start) to ->hash_update. Am I reading the code wrong? Rasmus
Re: [PATCH v3 1/1] arm: bcmbca: introduce the bcmbca architecture and 47622 SOC
Hi William,
Le 09/05/2022 à 18:28, William Zhang a écrit :
This is the initial support for Broadcom's ARM-based 47622 SOC.
In this change, our first SOC is an armv7 platform called 47622. The
initial support includes a bare-bone implementation and dts with ARM
PL011 uart.
The SOC-specific code resides in arch/arm/mach-bcmbca/ and board
related code is in board/broadcom/bcmba.
The u-boot image can be loaded from flash or network to the entry
point address in the memory and boot from there.
Signed-off-by: William Zhang
Signed-off-by: Kursad Oney
Signed-off-by: Anand Gore
Reviewed-by: Philippe Reynes
---
Changes in v3:
- Remove the CONFIG_SYS_BAUDRATE_TABLE to use the u-boot default table
Changes in v2:
- Updated dts and dtsi files which are accpeted in linux-next upstream
- Changed CONFIG_SYS_TEXT_BASE to 0x0100 from 0x1000 to work
on boards with 256MB or less memory
MAINTAINERS| 11 +++
arch/arm/Kconfig | 7 ++
arch/arm/Makefile | 1 +
arch/arm/dts/Makefile | 3 +
arch/arm/dts/bcm47622.dtsi | 126 +
arch/arm/dts/bcm947622.dts | 30 ++
arch/arm/mach-bcmbca/Kconfig | 17
arch/arm/mach-bcmbca/Makefile | 6 ++
arch/arm/mach-bcmbca/bcm47622/Kconfig | 17
arch/arm/mach-bcmbca/bcm47622/Makefile | 5 +
board/broadcom/bcmbca/Kconfig | 17
board/broadcom/bcmbca/Makefile | 5 +
board/broadcom/bcmbca/board.c | 35 +++
configs/bcm947622_defconfig| 18
include/configs/bcm947622.h| 18
15 files changed, 316 insertions(+)
create mode 100644 arch/arm/dts/bcm47622.dtsi
create mode 100644 arch/arm/dts/bcm947622.dts
create mode 100644 arch/arm/mach-bcmbca/Kconfig
create mode 100644 arch/arm/mach-bcmbca/Makefile
create mode 100644 arch/arm/mach-bcmbca/bcm47622/Kconfig
create mode 100644 arch/arm/mach-bcmbca/bcm47622/Makefile
create mode 100644 board/broadcom/bcmbca/Kconfig
create mode 100644 board/broadcom/bcmbca/Makefile
create mode 100644 board/broadcom/bcmbca/board.c
create mode 100644 configs/bcm947622_defconfig
create mode 100644 include/configs/bcm947622.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 56be0bfad00c..96cd85dd1c7a 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -195,6 +195,17 @@ F: drivers/pinctrl/broadcom/
F:configs/rpi_*
T:git https://source.denx.de/u-boot/custodians/u-boot-arm.git
+ARM BROADCOM BCMBCA
+M: Anand Gore
+M: William Zhang
+M: Kursad Oney
+M: Joel Peshkin
+S: Maintained
+F: arch/arm/mach-bcmbca/
+F: board/broadcom/bcmbca/
+F: configs/bcm947622_defconfig
+F: include/configs/bcm947622.h
+
ARM BROADCOM BCMSTB
M:Thomas Fitzsimmons
S:Maintained
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 57946f61fabe..5e231fc72854 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -712,6 +712,11 @@ config ARCH_BCMSTB
This enables support for Broadcom ARM-based set-top box
chipsets, including the 7445 family of chips.
+config ARCH_BCMBCA
+ bool "Broadcom broadband chip family"
+ select DM
+ select OF_CONTROL
+
config TARGET_VEXPRESS_CA9X4
bool "Support vexpress_ca9x4"
select CPU_V7A
@@ -2175,6 +2180,8 @@ source "arch/arm/mach-at91/Kconfig"
source "arch/arm/mach-bcm283x/Kconfig"
+source "arch/arm/mach-bcmbca/Kconfig"
+
source "arch/arm/mach-bcmstb/Kconfig"
source "arch/arm/mach-davinci/Kconfig"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index ad757e982e37..0fd127e0e7e4 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -59,6 +59,7 @@ machine-$(CONFIG_ARCH_APPLE) += apple
machine-$(CONFIG_ARCH_ASPEED) += aspeed
machine-$(CONFIG_ARCH_AT91) += at91
machine-$(CONFIG_ARCH_BCM283X)+= bcm283x
+machine-$(CONFIG_ARCH_BCMBCA) += bcmbca
machine-$(CONFIG_ARCH_BCMSTB) += bcmstb
machine-$(CONFIG_ARCH_DAVINCI)+= davinci
machine-$(CONFIG_ARCH_EXYNOS) += exynos
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index ab2d0da192c6..db42475bba1c 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -1132,6 +1132,9 @@ dtb-$(CONFIG_TARGET_BCMNS3) += ns3-board.dtb
dtb-$(CONFIG_ARCH_BCMSTB) += bcm7xxx.dtb
+dtb-$(CONFIG_BCM47622) += \
+ bcm947622.dtb
+
dtb-$(CONFIG_ASPEED_AST2500) += ast2500-evb.dtb
dtb-$(CONFIG_ASPEED_AST2600) += ast2600-evb.dtb
diff --git a/arch/arm/dts/bcm47622.dtsi b/arch/arm/dts/bcm47622.dtsi
new file mode 100644
index ..c016e12b7372
--- /dev/null
+++ b/arch/arm/dts/bcm47622.dtsi
@@ -0,0 +1,126 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2022 Broadcom Ltd.
+ */
+
+#include
+#include
+
+/ {
+ compatible = "brcm,bcm47622", "brcm,bcmbca";
+ #a
Re: [PATCH v2 2/2] arm: add support to corstone1000 platform
On Wed, May 11, 2022 at 10:55:41AM +0100, Rui Miguel Silva wrote: > Corstone1000 is a platform from arm, which includes pre > verified Corstone SSE710 sub-system that combines Cortex-A and > Cortex-M processors [0]. > > This code adds the support for the Cortex-A35 implementation > at host side, it contains also the necessary bits to support > the Corstone 1000 FVP (Fixed Virtual Platform) [1] and also the > FPGA MPS3 board implementation of this platform. [2] > > 0: https://developer.arm.com/documentation/102360/ > 1: > https://developer.arm.com/tools-and-software/open-source-software/arm-platforms-software/arm-ecosystem-fvps > 2: https://developer.arm.com/documentation/dai0550/c/ > > Signed-off-by: Rui Miguel Silva Reviewed-by: Tom Rini -- Tom signature.asc Description: PGP signature
Re: [PATCH v2 1/2] cmd: load: add load command for memory mapped
On Wed, May 11, 2022 at 10:55:40AM +0100, Rui Miguel Silva wrote: > cp.b is used a lot as a way to load binaries to memory and execute > them, however we may need to integrate this with the efi subsystem to > set it up as a bootdev. > > So, introduce a loadm command that will be consistent with the other > loadX commands and will call the efi API's. > > ex: loadm $kernel_addr $kernel_addr_r $kernel_size > > with this a kernel with CONFIG_EFI_STUB enabled will be loaded and > then subsequently booted with bootefi command. > > Signed-off-by: Rui Miguel Silva Reviewed-by: Tom Rini -- Tom signature.asc Description: PGP signature
Re: [PATCH 3/3] exports: Fix export of SPI access functions
On Thu, May 05, 2022 at 03:32:42PM +, Paul Barker wrote: > * With CONFIG_DM_SPI defined, spi_get_bus_and_cs needs to be used > instead of spi_setup_slave to configure a SPI bus. As spi_setup_slave is > already present in the export list it is reasonable to also export > spi_get_bus_and_cs. > > * For the functions listed in the jump table to be callable they must > also be defined in the "exports.h" header. Define the various exported > SPI functions so that they can be used. > > Signed-off-by: Paul Barker Reviewed-by: Tom Rini -- Tom signature.asc Description: PGP signature
Re: [PATCH 2/3] examples: hello_world: Drop inclusion of common header
On Thu, May 05, 2022 at 03:32:41PM +, Paul Barker wrote: > The "common.h" header is not covered by the licensing exception for > standalone applications. Let's drop inclusion of this header from the > hello_world example to prove that a standalone app can be built without > it. > > Signed-off-by: Paul Barker Reviewed-by: Tom Rini -- Tom signature.asc Description: PGP signature
Re: [PATCH 1/3] Licenses: Clarify exceptions for standalone apps
On Thu, May 05, 2022 at 03:32:40PM +, Paul Barker wrote: > On 2010-01-27, an email [1] was sent to the mailing list by Wolfgang > Denk which clarified the intended licensing exceptions for standalone > applications. As the "export.h" header and the "stubs.c" source files > are required to implement a standalone application, the intention was > that these files be covered by the licensing exception. This is made > clear in the following quotes from that email: > > "exports.h" should be added to the "allowed" file list; there should > be no need to include "common.h". Eventually this needs fixing. > Patches are welcome. > > "examples/standalone/stubs.c" should be added to the "allowed" file > list (the ppc_*jmp.S files are LGPLed). > > There should be no doubts - the intention is clear, the current state > may need improvement. Help (read: patches) welcome. > > [1]: https://lists.denx.de/pipermail/u-boot/2010-January/067174.html > > Signed-off-by: Paul Barker > Cc: Wolfgang Denk > --- > Licenses/Exceptions | 12 > 1 file changed, 8 insertions(+), 4 deletions(-) > > diff --git a/Licenses/Exceptions b/Licenses/Exceptions > index c9b3cd981f51..4f241f4aff29 100644 > --- a/Licenses/Exceptions > +++ b/Licenses/Exceptions > @@ -7,9 +7,13 @@ use U-Boot services by means of the jump table provided by > U-Boot > exactly for this purpose - this is merely considered normal use of > U-Boot, and does *not* fall under the heading of "derived work". > > - The header files "include/image.h" and "arch/*/include/asm/u-boot.h" > -define interfaces to U-Boot. Including these (unmodified) header > -files in another file is considered normal use of U-Boot, and does > -*not* fall under the heading of "derived work". > +The following files define interfaces to U-Boot: > + * include/image.h > + * include/export.h > + * arch/*/include/asm/u-boot.h > + * examples/standalone/stubs.c > + > +Including these (unmodified) files in another file is considered normal > +use of U-Boot, and does *not* fall under the heading of "derived work". > -- Wolfgang Denk Wolfgang? -- Tom signature.asc Description: PGP signature
Re: [PATCH 1/1] Add mmc_set_env_dev to TI AM33xx, using the scratch reg of UART port
On Mon, May 09, 2022 at 05:15:25AM +, Da Shi Cao wrote: > Signed-off-by: Dashi Cao > --- > board/ti/am335x/board.c | 40 > common/spl/spl.c| 6 ++ > drivers/mmc/mmc.c | 4 > include/mmc.h | 1 + > 4 files changed, 51 insertions(+) So, this should be done more generically. And it's hard to say how exactly without seeing how you've done mmc_get_env_dev() for your platform. -- Tom signature.asc Description: PGP signature
Re: [PATCH] net: fix phy_string_for_interface
On Tue, 10 May 2022 15:49:10 -0700
Tim Harvey wrote:
> commit ffb0f6f488b9 ("treewide: Rename PHY_INTERFACE_MODE_NONE to
> PHY_INTERFACE_MODE_NA") broke the phy_string_for_interface function.
> Fix it.
>
> Fixes ffb0f6f488b9 ("treewide: Rename PHY_INTERFACE_MODE_NONE to
> PHY_INTERFACE_MODE_NA")
> Signed-off-by: Tim Harvey
> Cc: Marek Behún
> Cc: Stefan Roese
> Cc: Ramon Fried
> Cc: Vladimir Oltean
> ---
> include/phy_interface.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/include/phy_interface.h b/include/phy_interface.h
> index ce3b5004ec22..fed3357b9a26 100644
> --- a/include/phy_interface.h
> +++ b/include/phy_interface.h
> @@ -85,7 +85,7 @@ static const char * const backplane_mode_strings[] = {
> static inline const char *phy_string_for_interface(phy_interface_t i)
> {
> /* Default to unknown */
> - if (i > PHY_INTERFACE_MODE_NA)
> + if (i >= PHY_INTERFACE_MODE_MAX)
> i = PHY_INTERFACE_MODE_NA;
>
> return phy_interface_strings[i];
Yikes.
Reviewed-by: Marek Behún
[PATCH v2 2/2] arm: add support to corstone1000 platform
Corstone1000 is a platform from arm, which includes pre
verified Corstone SSE710 sub-system that combines Cortex-A and
Cortex-M processors [0].
This code adds the support for the Cortex-A35 implementation
at host side, it contains also the necessary bits to support
the Corstone 1000 FVP (Fixed Virtual Platform) [1] and also the
FPGA MPS3 board implementation of this platform. [2]
0: https://developer.arm.com/documentation/102360/
1:
https://developer.arm.com/tools-and-software/open-source-software/arm-platforms-software/arm-ecosystem-fvps
2: https://developer.arm.com/documentation/dai0550/c/
Signed-off-by: Rui Miguel Silva
---
arch/arm/Kconfig | 8 +-
arch/arm/dts/Makefile| 3 +
arch/arm/dts/corstone1000-fvp.dts| 51 +++
arch/arm/dts/corstone1000-mps3.dts | 32 +
arch/arm/dts/corstone1000.dtsi | 164 +++
board/armltd/corstone1000/Kconfig| 12 ++
board/armltd/corstone1000/MAINTAINERS| 7 +
board/armltd/corstone1000/Makefile | 7 +
board/armltd/corstone1000/corstone1000.c | 91 +
configs/corstone1000_defconfig | 48 +++
include/configs/corstone1000.h | 52 +++
11 files changed, 474 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/dts/corstone1000-fvp.dts
create mode 100644 arch/arm/dts/corstone1000-mps3.dts
create mode 100644 arch/arm/dts/corstone1000.dtsi
create mode 100644 board/armltd/corstone1000/Kconfig
create mode 100644 board/armltd/corstone1000/MAINTAINERS
create mode 100644 board/armltd/corstone1000/Makefile
create mode 100644 board/armltd/corstone1000/corstone1000.c
create mode 100644 configs/corstone1000_defconfig
create mode 100644 include/configs/corstone1000.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 0afec5155b1b..68ed0cd4709d 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1341,6 +1341,12 @@ config ARCH_VEXPRESS64
select ENV_IS_IN_FLASH if MTD
imply DISTRO_DEFAULTS
+config TARGET_CORSTONE1000
+ bool "Support Corstone1000 Platform"
+ select ARM64
+ select PL01X_SERIAL
+ select DM
+
config TARGET_TOTAL_COMPUTE
bool "Support Total Compute Platform"
select ARM64
@@ -2288,7 +2294,7 @@ source "arch/arm/mach-nexell/Kconfig"
source "arch/arm/mach-npcm/Kconfig"
source "board/armltd/total_compute/Kconfig"
-
+source "board/armltd/corstone1000/Kconfig"
source "board/bosch/shc/Kconfig"
source "board/bosch/guardian/Kconfig"
source "board/Marvell/octeontx/Kconfig"
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 83630af4f67b..964403ed0a70 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -1239,6 +1239,9 @@ dtb-$(CONFIG_TARGET_EA_LPC3250DEVKITV2) +=
lpc3250-ea3250.dtb
dtb-$(CONFIG_ARCH_QEMU) += qemu-arm.dtb qemu-arm64.dtb
+dtb-$(CONFIG_TARGET_CORSTONE1000) += corstone1000-mps3.dtb \
+ corstone1000-fvp.dtb
+
include $(srctree)/scripts/Makefile.dts
targets += $(dtb-y)
diff --git a/arch/arm/dts/corstone1000-fvp.dts
b/arch/arm/dts/corstone1000-fvp.dts
new file mode 100644
index ..26b0f1b3cea6
--- /dev/null
+++ b/arch/arm/dts/corstone1000-fvp.dts
@@ -0,0 +1,51 @@
+// SPDX-License-Identifier: GPL-2.0 or MIT
+/*
+ * Copyright (c) 2022, Arm Limited. All rights reserved.
+ * Copyright (c) 2022, Linaro Limited. All rights reserved.
+ *
+ */
+
+/dts-v1/;
+
+#include "corstone1000.dtsi"
+
+/ {
+ model = "ARM Corstone1000 FVP (Fixed Virtual Platform)";
+ compatible = "arm,corstone1000-fvp";
+
+ smsc: ethernet@401 {
+ compatible = "smsc,lan91c111";
+ reg = <0x4010 0x1>;
+ phy-mode = "mii";
+ interrupts = ;
+ reg-io-width = <2>;
+ };
+
+ vmmc_v3_3d: fixed_v3_3d {
+ compatible = "regulator-fixed";
+ regulator-name = "vmmc_supply";
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ regulator-always-on;
+ };
+
+ sdmmc0: mmc@4030 {
+ compatible = "arm,pl18x", "arm,primecell";
+ reg = <0x4030 0x1000>;
+ interrupts = ;
+ max-frequency = <1200>;
+ vmmc-supply = <&vmmc_v3_3d>;
+ clocks = <&smbclk>, <&refclk100mhz>;
+ clock-names = "smclk", "apb_pclk";
+ };
+
+ sdmmc1: mmc@5000 {
+ compatible = "arm,pl18x", "arm,primecell";
+ reg = <0x5000 0x1>;
+ interrupts = ;
+ max-frequency = <1200>;
+ vmmc-supply = <&vmmc_v3_3d>;
+ clocks = <&smbclk>, <&refclk100mhz>;
+ clock-names = "smclk", "apb_pclk";
+ };
+};
diff --git a/arch/arm/dts/corstone1000-mps3.dts
b/arch/arm/dts/corstone1000-mps3.dts
new file mode 100644
index 0
[PATCH v2 1/2] cmd: load: add load command for memory mapped
cp.b is used a lot as a way to load binaries to memory and execute
them, however we may need to integrate this with the efi subsystem to
set it up as a bootdev.
So, introduce a loadm command that will be consistent with the other
loadX commands and will call the efi API's.
ex: loadm $kernel_addr $kernel_addr_r $kernel_size
with this a kernel with CONFIG_EFI_STUB enabled will be loaded and
then subsequently booted with bootefi command.
Signed-off-by: Rui Miguel Silva
---
README | 1 +
cmd/Kconfig | 5 +++
cmd/bootefi.c| 12 ++
cmd/load.c | 48 +
configs/sandbox64_defconfig | 1 +
configs/sandbox_defconfig| 1 +
doc/usage/loadm.rst | 49 ++
include/efi_loader.h | 2 +
include/test/suites.h| 1 +
lib/efi_loader/efi_device_path.c | 9
test/cmd/Makefile| 1 +
test/cmd/loadm.c | 72
test/cmd_ut.c| 6 +++
13 files changed, 208 insertions(+)
create mode 100644 doc/usage/loadm.rst
create mode 100644 test/cmd/loadm.c
diff --git a/README b/README
index b7ab6e50708d..cd76f95e74c1 100644
--- a/README
+++ b/README
@@ -2578,6 +2578,7 @@ rarpboot- boot image via network using RARP/TFTP protocol
diskboot- boot from IDE devicebootd - boot default, i.e., run 'bootcmd'
loads - load S-Record file over serial line
loadb - load binary file over serial line (kermit mode)
+loadm - load binary blob from source address to destination address
md - memory display
mm - memory modify (auto-incrementing)
nm - memory modify (constant address)
diff --git a/cmd/Kconfig b/cmd/Kconfig
index 69c1814d24af..7f98cb16e2bc 100644
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -1153,6 +1153,11 @@ config CMD_LOADB
help
Load a binary file over serial line.
+config CMD_LOADM
+ bool "loadm"
+ help
+ Load a binary over memory mapped.
+
config CMD_LOADS
bool "loads"
default y
diff --git a/cmd/bootefi.c b/cmd/bootefi.c
index d80353fa7189..53b584231f07 100644
--- a/cmd/bootefi.c
+++ b/cmd/bootefi.c
@@ -34,6 +34,18 @@ static struct efi_device_path *bootefi_device_path;
static void *image_addr;
static size_t image_size;
+/**
+ * efi_get_image_parameters() - return image parameters
+ *
+ * @img_addr: address of loaded image in memory
+ * @img_size: size of loaded image
+ */
+void efi_get_image_parameters(void **img_addr, size_t *img_size)
+{
+ *img_addr = image_addr;
+ *img_size = image_size;
+}
+
/**
* efi_clear_bootdev() - clear boot device
*/
diff --git a/cmd/load.c b/cmd/load.c
index 7e4a552d90ef..1224a7f85bb3 100644
--- a/cmd/load.c
+++ b/cmd/load.c
@@ -1063,6 +1063,44 @@ static ulong load_serial_ymodem(ulong offset, int mode)
#endif
+#if defined(CONFIG_CMD_LOADM)
+static int do_load_memory_bin(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ ulong addr, dest, size;
+ void*src, *dst;
+
+ if (argc != 4)
+ return CMD_RET_USAGE;
+
+ addr = simple_strtoul(argv[1], NULL, 16);
+
+ dest = simple_strtoul(argv[2], NULL, 16);
+
+ size = simple_strtoul(argv[3], NULL, 16);
+
+ if (!size) {
+ printf("loadm: can not load zero bytes\n");
+ return 1;
+ }
+
+ src = map_sysmem(addr, size);
+ dst = map_sysmem(dest, size);
+
+ memcpy(dst, src, size);
+
+ unmap_sysmem(src);
+ unmap_sysmem(dst);
+
+ if (IS_ENABLED(CONFIG_CMD_BOOTEFI))
+ efi_set_bootdev("Mem", "", "", map_sysmem(dest, 0), size);
+
+ printf("loaded bin to memory: size: %lu\n", size);
+
+ return 0;
+}
+#endif
+
/* */
#if defined(CONFIG_CMD_LOADS)
@@ -1137,3 +1175,13 @@ U_BOOT_CMD(
);
#endif /* CONFIG_CMD_LOADB */
+
+#if defined(CONFIG_CMD_LOADM)
+U_BOOT_CMD(
+ loadm, 4, 0,do_load_memory_bin,
+ "load binary blob from source address to destination address",
+ "[src_addr] [dst_addr] [size]\n"
+ " - load a binary blob from one memory location to other"
+ " from src_addr to dst_addr by size bytes"
+);
+#endif /* CONFIG_CMD_LOADM */
diff --git a/configs/sandbox64_defconfig b/configs/sandbox64_defconfig
index d7f22b39ae51..7ab5698b20cd 100644
--- a/configs/sandbox64_defconfig
+++ b/configs/sandbox64_defconfig
@@ -47,6 +47,7 @@ CONFIG_CMD_GPT=y
CONFIG_CMD_GPT_RENAME=y
CONFIG_CMD_IDE=y
CONFIG_CMD_I2C=y
+CONFIG_CMD_LOADM=y
CONFIG_CMD_OSD=y
CONFIG_CMD_PCI=y
CONFIG_CMD_READ=y
diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig
index c509a924e6b3..82df5c2728e0 100644
--- a/configs/sandbox_defconfig
+++ b/configs/sandbox_defconfig
@@ -67,6 +67,7 @@ CONFIG_CMD_GPT=y
CONFIG_CMD_GPT_RENAME=y
[PATCH v2 0/2] board/armltd: add support for corstone1000
This series add support for arm's corstone1000 platform (see specific commit changelog for references to documentation), but first introduce a command (loadm which will integrate with efi subsystem) used in one of the boot sequence in this platform. v1 [0] -> v2: Tom: - device tree status (now on kernel next [1]) - loadm add documentation, testing, change the default value - kconfig extra line - dm_eth, dm_serial cleanups in platform code and headers - moving bootcommand to defconfig [0]: https://lore.kernel.org/all/20220322104118.573537-1-rui.si...@linaro.org/ [1]: https://lore.kernel.org/all/165089291072.1036016.13574796454085073736.b4...@arm.com/ Rui Miguel Silva (2): cmd: load: add load command for memory mapped arm: add support to corstone1000 platform README | 1 + arch/arm/Kconfig | 8 +- arch/arm/dts/Makefile| 3 + arch/arm/dts/corstone1000-fvp.dts| 51 +++ arch/arm/dts/corstone1000-mps3.dts | 32 + arch/arm/dts/corstone1000.dtsi | 164 +++ board/armltd/corstone1000/Kconfig| 12 ++ board/armltd/corstone1000/MAINTAINERS| 7 + board/armltd/corstone1000/Makefile | 7 + board/armltd/corstone1000/corstone1000.c | 91 + cmd/Kconfig | 5 + cmd/bootefi.c| 12 ++ cmd/load.c | 48 +++ configs/corstone1000_defconfig | 48 +++ configs/sandbox64_defconfig | 1 + configs/sandbox_defconfig| 1 + doc/usage/loadm.rst | 49 +++ include/configs/corstone1000.h | 52 +++ include/efi_loader.h | 2 + include/test/suites.h| 1 + lib/efi_loader/efi_device_path.c | 9 ++ test/cmd/Makefile| 1 + test/cmd/loadm.c | 72 ++ test/cmd_ut.c| 6 + 24 files changed, 682 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/corstone1000-fvp.dts create mode 100644 arch/arm/dts/corstone1000-mps3.dts create mode 100644 arch/arm/dts/corstone1000.dtsi create mode 100644 board/armltd/corstone1000/Kconfig create mode 100644 board/armltd/corstone1000/MAINTAINERS create mode 100644 board/armltd/corstone1000/Makefile create mode 100644 board/armltd/corstone1000/corstone1000.c create mode 100644 configs/corstone1000_defconfig create mode 100644 doc/usage/loadm.rst create mode 100644 include/configs/corstone1000.h create mode 100644 test/cmd/loadm.c -- 2.36.1
[PATCH 06/10] arm64: zynqmp: Add dmas, gpu, rtc, watchdogs and opp nodes for SOM
From: Michal Simek
There are couple of IPs which are enabled in origin HW design which are
missing in SOM dt. Add them to match default setup.
Signed-off-by: Michal Simek
Signed-off-by: Michal Simek
---
arch/arm/dts/zynqmp-sm-k26-revA.dts | 95 +
1 file changed, 95 insertions(+)
diff --git a/arch/arm/dts/zynqmp-sm-k26-revA.dts
b/arch/arm/dts/zynqmp-sm-k26-revA.dts
index 8b2cd512da56..35fab915172b 100644
--- a/arch/arm/dts/zynqmp-sm-k26-revA.dts
+++ b/arch/arm/dts/zynqmp-sm-k26-revA.dts
@@ -356,3 +356,98 @@
&zynqmp_dpsub {
status = "okay";
};
+
+&rtc {
+ status = "okay";
+};
+
+&lpd_dma_chan1 {
+ status = "okay";
+};
+
+&lpd_dma_chan2 {
+ status = "okay";
+};
+
+&lpd_dma_chan3 {
+ status = "okay";
+};
+
+&lpd_dma_chan4 {
+ status = "okay";
+};
+
+&lpd_dma_chan5 {
+ status = "okay";
+};
+
+&lpd_dma_chan6 {
+ status = "okay";
+};
+
+&lpd_dma_chan7 {
+ status = "okay";
+};
+
+&lpd_dma_chan8 {
+ status = "okay";
+};
+
+&fpd_dma_chan1 {
+ status = "okay";
+};
+
+&fpd_dma_chan2 {
+ status = "okay";
+};
+
+&fpd_dma_chan3 {
+ status = "okay";
+};
+
+&fpd_dma_chan4 {
+ status = "okay";
+};
+
+&fpd_dma_chan5 {
+ status = "okay";
+};
+
+&fpd_dma_chan6 {
+ status = "okay";
+};
+
+&fpd_dma_chan7 {
+ status = "okay";
+};
+
+&fpd_dma_chan8 {
+ status = "okay";
+};
+
+&gpu {
+ status = "okay";
+};
+
+&lpd_watchdog {
+ status = "okay";
+};
+
+&watchdog0 {
+ status = "okay";
+};
+
+&cpu_opp_table {
+ opp00 {
+ opp-hz = /bits/ 64 <13>;
+ };
+ opp01 {
+ opp-hz = /bits/ 64 <6>;
+ };
+ opp02 {
+ opp-hz = /bits/ 64 <4>;
+ };
+ opp03 {
+ opp-hz = /bits/ 64 <3>;
+ };
+};
--
2.36.0
[PATCH 09/10] arm64: zynqmp: Add linux,code for fwuen button
BTN_MISC looks like the most reasonable option for this button.
Button is used by firmware to indicate (after reset, power up) that user
wants to do firmware upgrade via firmware update utility.
For bootloader or OS is this just user button which is worth to have it
mapped.
Also button can be used as a wakeup source and pressing it for more time
can generate more chars that's why also adding wakeup-source and autorepeat
properties.
Signed-off-by: Michal Simek
Reviewed-by: Radhey Shyam Pandey
---
arch/arm/dts/zynqmp-sm-k26-revA.dts | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/dts/zynqmp-sm-k26-revA.dts
b/arch/arm/dts/zynqmp-sm-k26-revA.dts
index 35fab915172b..7c2bfa395da7 100644
--- a/arch/arm/dts/zynqmp-sm-k26-revA.dts
+++ b/arch/arm/dts/zynqmp-sm-k26-revA.dts
@@ -56,6 +56,9 @@
fwuen {
label = "fwuen";
gpios = <&gpio 12 GPIO_ACTIVE_LOW>;
+ linux,code = ;
+ wakeup-source;
+ autorepeat;
};
};
--
2.36.0
[PATCH 10/10] arm64: zynqmp: Add DT description for si5328 for zcu102/zcu106
From: Michal Simek
Origin DT binding just specify driver but wasn't aligned with DT binding
which came later. Extend description for zcu102 and zcu106 to cover latest
binding.
Signed-off-by: Michal Simek
Signed-off-by: Michal Simek
---
arch/arm/dts/zynqmp-zcu102-revA.dts | 21 -
arch/arm/dts/zynqmp-zcu106-revA.dts | 21 -
2 files changed, 40 insertions(+), 2 deletions(-)
diff --git a/arch/arm/dts/zynqmp-zcu102-revA.dts
b/arch/arm/dts/zynqmp-zcu102-revA.dts
index aac798d6e74a..c13b52a6aeaa 100644
--- a/arch/arm/dts/zynqmp-zcu102-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu102-revA.dts
@@ -604,7 +604,26 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <4>;
- /* SI5328 - u20 */
+ si5328: clock-generator@69 {/* SI5328 - u20 */
+ compatible = "silabs,si5328";
+ reg = <0x69>;
+ /*
+* Chip has interrupt present connected to PL
+* interrupt-parent = <&>;
+* interrupts = <>;
+*/
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #clock-cells = <1>;
+ clocks = <&refhdmi>;
+ clock-names = "xtal";
+ clock-output-names = "si5328";
+
+ si5328_clk: clk0@0 {
+ reg = <0>;
+ clock-frequency = <2700>;
+ };
+ };
};
/* 5 - 7 unconnected */
};
diff --git a/arch/arm/dts/zynqmp-zcu106-revA.dts
b/arch/arm/dts/zynqmp-zcu106-revA.dts
index 03624648cd71..6dfc8fe17bf2 100644
--- a/arch/arm/dts/zynqmp-zcu106-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu106-revA.dts
@@ -593,7 +593,26 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <4>;
- /* SI5328 - u20 */
+ si5328: clock-generator@69 {/* SI5328 - u20 */
+ compatible = "silabs,si5328";
+ reg = <0x69>;
+ /*
+* Chip has interrupt present connected to PL
+* interrupt-parent = <&>;
+* interrupts = <>;
+*/
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #clock-cells = <1>;
+ clocks = <&refhdmi>;
+ clock-names = "xtal";
+ clock-output-names = "si5328";
+
+ si5328_clk: clk0@0 {
+ reg = <0>;
+ clock-frequency = <2700>;
+ };
+ };
};
i2c@5 {
#address-cells = <1>;
--
2.36.0
[PATCH 07/10] Revert "arm64: zynqmp: Add zynqmp firmware specific DT nodes"
From: T Karthik Reddy
This reverts commit 50a6bd000f94832658f42fb01b9aaf9e39a52004.
As zynqmp mini emmc does not rely on firmware, remove firmware related
device tree modes from zynqmp mini emmc dts files.
Signed-off-by: T Karthik Reddy
Acked-by: Ashok Reddy Soma
Signed-off-by: Michal Simek
---
arch/arm/dts/zynqmp-mini-emmc0.dts | 40 --
arch/arm/dts/zynqmp-mini-emmc1.dts | 40 --
2 files changed, 80 deletions(-)
diff --git a/arch/arm/dts/zynqmp-mini-emmc0.dts
b/arch/arm/dts/zynqmp-mini-emmc0.dts
index 8d9f9ca37259..8467dd8e1cc7 100644
--- a/arch/arm/dts/zynqmp-mini-emmc0.dts
+++ b/arch/arm/dts/zynqmp-mini-emmc0.dts
@@ -41,46 +41,6 @@
clock-frequency = <2>;
};
- firmware {
- zynqmp_firmware: zynqmp-firmware {
- compatible = "xlnx,zynqmp-firmware";
- #power-domain-cells = <1>;
- method = "smc";
- u-boot,dm-pre-reloc;
-
- zynqmp_power: zynqmp-power {
- u-boot,dm-pre-reloc;
- compatible = "xlnx,zynqmp-power";
- mboxes = <&ipi_mailbox_pmu1 0>,
-<&ipi_mailbox_pmu1 1>;
- mbox-names = "tx", "rx";
- };
- };
- };
-
- zynqmp_ipi: zynqmp_ipi {
- u-boot,dm-pre-reloc;
- compatible = "xlnx,zynqmp-ipi-mailbox";
- xlnx,ipi-id = <0>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- ipi_mailbox_pmu1: mailbox@ff990400 {
- u-boot,dm-pre-reloc;
- reg = <0x0 0xff9905c0 0x0 0x20>,
- <0x0 0xff9905e0 0x0 0x20>,
- <0x0 0xff990e80 0x0 0x20>,
- <0x0 0xff990ea0 0x0 0x20>;
- reg-names = "local_request_region",
- "local_response_region",
- "remote_request_region",
- "remote_response_region";
- #mbox-cells = <1>;
- xlnx,ipi-id = <4>;
- };
- };
-
amba: amba {
compatible = "simple-bus";
#address-cells = <2>;
diff --git a/arch/arm/dts/zynqmp-mini-emmc1.dts
b/arch/arm/dts/zynqmp-mini-emmc1.dts
index 5722b762d679..2afcc7751b9f 100644
--- a/arch/arm/dts/zynqmp-mini-emmc1.dts
+++ b/arch/arm/dts/zynqmp-mini-emmc1.dts
@@ -41,46 +41,6 @@
clock-frequency = <2>;
};
- firmware {
- zynqmp_firmware: zynqmp-firmware {
- compatible = "xlnx,zynqmp-firmware";
- #power-domain-cells = <1>;
- method = "smc";
- u-boot,dm-pre-reloc;
-
- zynqmp_power: zynqmp-power {
- u-boot,dm-pre-reloc;
- compatible = "xlnx,zynqmp-power";
- mboxes = <&ipi_mailbox_pmu1 0>,
-<&ipi_mailbox_pmu1 1>;
- mbox-names = "tx", "rx";
- };
- };
- };
-
- zynqmp_ipi: zynqmp_ipi {
- u-boot,dm-pre-reloc;
- compatible = "xlnx,zynqmp-ipi-mailbox";
- xlnx,ipi-id = <0>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- ipi_mailbox_pmu1: mailbox@ff990400 {
- u-boot,dm-pre-reloc;
- reg = <0x0 0xff9905c0 0x0 0x20>,
- <0x0 0xff9905e0 0x0 0x20>,
- <0x0 0xff990e80 0x0 0x20>,
- <0x0 0xff990ea0 0x0 0x20>;
- reg-names = "local_request_region",
- "local_response_region",
- "remote_request_region",
- "remote_response_region";
- #mbox-cells = <1>;
- xlnx,ipi-id = <4>;
- };
- };
-
amba: amba {
compatible = "simple-bus";
#address-cells = <2>;
--
2.36.0
[PATCH 08/10] arm64: zynqmp: Add PHY description for SGMII on vck190 SC
From: Michal Simek
SGMII requires phy to be configured. The support for this has been added to
Linux and U-Boot already that's why also describe the phy via DT. Clock is
coming from si5332 chip (output 1) 125MHz which is only one GT line use on
this board.
Signed-off-by: Michal Simek
Signed-off-by: Michal Simek
---
arch/arm/dts/zynqmp-e-a2197-00-revA.dts | 15 +++
1 file changed, 15 insertions(+)
diff --git a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts
b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts
index f229880a7021..726183782305 100644
--- a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts
+++ b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts
@@ -42,6 +42,12 @@
reg = <0x0 0x0 0x0 0x8000>;
};
+ si5332_1: si5332_1 { /* u142 - GEM0 */
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <12500>;
+ };
+
ina226-vccint {
compatible = "iio-hwmon";
io-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint
3>;
@@ -135,8 +141,17 @@
xlnx,mio-bank = <1>;
};
+/* GEM SGMII */
+&psgtr {
+ status = "okay";
+ /* gem0 */
+ clocks = <&si5332_1>;
+ clock-names = "ref0";
+};
+
&gem0 {
status = "okay";
+ phys = <&psgtr 0 PHY_TYPE_SGMII 0 0>;
phy-handle = <&phy0>;
phy-mode = "sgmii";
is-internal-pcspma;
--
2.36.0
[PATCH 04/10] arm64: zynqmp: Add power domain description for PL
From: Michal Simek
PL has own power domain which is not described in DT. That's why add it
there by default.
Signed-off-by: Michal Simek
Signed-off-by: Michal Simek
---
arch/arm/dts/zynqmp.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi
index a0f664a59db6..dae8f0669df8 100644
--- a/arch/arm/dts/zynqmp.dtsi
+++ b/arch/arm/dts/zynqmp.dtsi
@@ -218,6 +218,7 @@
#address-cells = <2>;
#size-cells = <2>;
ranges;
+ power-domains = <&zynqmp_firmware PD_PL>;
};
amba: axi {
--
2.36.0
[PATCH 05/10] arm64: zynqmp: Add pwm-fan node and fix ttc0 pwm-cells property
From: Vishal Patel
Add pwm-fan node to control fan through hwmon and change
pwm-cells property to 3 to allow fancontrol utility to
function correctly.
Signed-off-by: Vishal Patel
Signed-off-by: Michal Simek
---
arch/arm/dts/zynqmp-sm-k26-revA.dts | 11 +++
1 file changed, 11 insertions(+)
diff --git a/arch/arm/dts/zynqmp-sm-k26-revA.dts
b/arch/arm/dts/zynqmp-sm-k26-revA.dts
index a2c88dc34c6b..8b2cd512da56 100644
--- a/arch/arm/dts/zynqmp-sm-k26-revA.dts
+++ b/arch/arm/dts/zynqmp-sm-k26-revA.dts
@@ -87,12 +87,23 @@
<&xilinx_ams 24>, <&xilinx_ams 25>, <&xilinx_ams 26>,
<&xilinx_ams 27>, <&xilinx_ams 28>, <&xilinx_ams 29>;
};
+
+ pwm-fan {
+ compatible = "pwm-fan";
+ status = "okay";
+ pwms = <&ttc0 2 4 0>;
+ };
};
&modepin_gpio {
label = "modepin";
};
+&ttc0 {
+ status = "okay";
+ #pwm-cells = <3>;
+};
+
&uart1 { /* MIO36/MIO37 */
status = "okay";
};
--
2.36.0
[PATCH 03/10] arm64: zynqmp: Fix opp-table-cpu
OPP table name now should start with "opp-table" and OPP entries
shouldn't contain commas and @ signs in accordance to the new schema
requirement.
The same change was done in Linux by commit c6d4a8977598 ("ARM: tegra:
Rename CPU and EMC OPP table device-tree nodes"), commit ffbe853a3f5a
("ARM: dts: sunxi: Fix OPPs node name") or commit b7072cc5704d ("arm64:
dts: qcom: qcs404: Rename CPU and CPR OPP tables").
Signed-off-by: Michal Simek
---
arch/arm/dts/zynqmp.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi
index 6b711c810e67..a0f664a59db6 100644
--- a/arch/arm/dts/zynqmp.dtsi
+++ b/arch/arm/dts/zynqmp.dtsi
@@ -76,7 +76,7 @@
};
};
- cpu_opp_table: cpu-opp-table {
+ cpu_opp_table: opp-table-cpu {
compatible = "operating-points-v2";
opp-shared;
opp00 {
--
2.36.0
[PATCH 02/10] arm64: zynqmp: Add gpio labels for modepin
From: Michal Simek
Using labels helps with better identifications of chips.
Signed-off-by: Michal Simek
Signed-off-by: Michal Simek
---
arch/arm/dts/zynqmp-sm-k26-revA.dts | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/dts/zynqmp-sm-k26-revA.dts
b/arch/arm/dts/zynqmp-sm-k26-revA.dts
index e904cd8ea093..a2c88dc34c6b 100644
--- a/arch/arm/dts/zynqmp-sm-k26-revA.dts
+++ b/arch/arm/dts/zynqmp-sm-k26-revA.dts
@@ -89,6 +89,10 @@
};
};
+&modepin_gpio {
+ label = "modepin";
+};
+
&uart1 { /* MIO36/MIO37 */
status = "okay";
};
--
2.36.0
[PATCH 00/10] arm64: zynqmp: Various DT fixes
Hi, I am sending couple of patches to extend DT for zynqmp boards. Modepin and si5328 dt bindings are available in the Linux kernel. The rest are small changes with the existing DT binding mostly in Linux. Thanks, Michal Michal Simek (7): arm64: zynqmp: Add gpio labels for modepin arm64: zynqmp: Fix opp-table-cpu arm64: zynqmp: Add power domain description for PL arm64: zynqmp: Add dmas, gpu, rtc, watchdogs and opp nodes for SOM arm64: zynqmp: Add PHY description for SGMII on vck190 SC arm64: zynqmp: Add linux,code for fwuen button arm64: zynqmp: Add DT description for si5328 for zcu102/zcu106 Piyush Mehta (1): arm64: zynqmp: Add mode-pin GPIO controller DT node T Karthik Reddy (1): Revert "arm64: zynqmp: Add zynqmp firmware specific DT nodes" Vishal Patel (1): arm64: zynqmp: Add pwm-fan node and fix ttc0 pwm-cells property arch/arm/dts/zynqmp-e-a2197-00-revA.dts | 15 arch/arm/dts/zynqmp-mini-emmc0.dts | 40 - arch/arm/dts/zynqmp-mini-emmc1.dts | 40 - arch/arm/dts/zynqmp-sm-k26-revA.dts | 113 arch/arm/dts/zynqmp-zcu102-revA.dts | 21 - arch/arm/dts/zynqmp-zcu106-revA.dts | 21 - arch/arm/dts/zynqmp.dtsi| 11 ++- 7 files changed, 178 insertions(+), 83 deletions(-) -- 2.36.0
[PATCH 01/10] arm64: zynqmp: Add mode-pin GPIO controller DT node
From: Piyush Mehta
Add mode-pin GPIO controller DT node in zynqmp.dtsi and also setup default
reset-gpios property for usb which is default Xilinx setup.
Signed-off-by: Piyush Mehta
Signed-off-by: Michal Simek
---
arch/arm/dts/zynqmp.dtsi | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi
index c44260885023..6b711c810e67 100644
--- a/arch/arm/dts/zynqmp.dtsi
+++ b/arch/arm/dts/zynqmp.dtsi
@@ -13,6 +13,7 @@
*/
#include
+#include
#include
#include
@@ -189,6 +190,12 @@
compatible = "xlnx,zynqmp-pinctrl";
status = "disabled";
};
+
+ modepin_gpio: gpio {
+ compatible = "xlnx,zynqmp-gpio-modepin";
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
};
};
@@ -874,6 +881,7 @@
<&zynqmp_reset ZYNQMP_RESET_USB0_HIBERRESET>,
<&zynqmp_reset ZYNQMP_RESET_USB0_APB>;
reset-names = "usb_crst", "usb_hibrst", "usb_apbrst";
+ reset-gpios = <&modepin_gpio 1 GPIO_ACTIVE_LOW>;
ranges;
dwc3_0: usb@fe20 {
--
2.36.0
Re: [PATCH] gpio: sunxi: Fix build with CONFIG_SPL_SERIAL=n
On Tue, 10 May 2022 19:03:34 -0500
Samuel Holland wrote:
Hi,
> This driver uses simple_strtol(), so it needs SPL_STRTO. Before commit
> 88ca8e26958b6 ("disk: Add an option for partitions in SPL"), SPL_STRTO
> was always selected indirectly. Now it is not, so select it here.
>
> Signed-off-by: Samuel Holland
From what I can see, CONFIG_MMC is the trigger, calling
sunxi_name_to_gpio(), which is the actual user of simple_strtol() in the
SPL. For the three boards not using MMC I don't see simple_strol() being
mentioned in the objdump.
But I think this patch is a more robust solution (compared to tying it to
MMC usage), so:
Reviewed-by: Andre Przywara
Cheers,
Andre
> ---
>
> drivers/gpio/Kconfig | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
> index 89068c7800..b955543e97 100644
> --- a/drivers/gpio/Kconfig
> +++ b/drivers/gpio/Kconfig
> @@ -347,6 +347,7 @@ config SANDBOX_GPIO_COUNT
> config SUNXI_GPIO
> bool "Allwinner GPIO driver"
> depends on ARCH_SUNXI
> + select SPL_STRTO if SPL
> help
> Support the GPIO device in Allwinner SoCs.
>
[PATCH] crypto/fsl: fsl_hash: Fix dcache issue in caam_hash_finish
HW accelerated hash operations are giving incorrect hash output.
so add flush and invalidate for input/output hash buffers.
Fixes: 94e3c8c4fd (crypto/fsl - Add progressive hashing support using hardware
acceleration.)
Signed-off-by: Gaurav Jain
---
drivers/crypto/fsl/fsl_hash.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/crypto/fsl/fsl_hash.c b/drivers/crypto/fsl/fsl_hash.c
index a52c4ac957..9e6829b7ad 100644
--- a/drivers/crypto/fsl/fsl_hash.c
+++ b/drivers/crypto/fsl/fsl_hash.c
@@ -149,12 +149,20 @@ static int caam_hash_finish(void *hash_ctx, void
*dest_buf,
driver_hash[caam_algo].digestsize,
1);
+ flush_dcache_range((ulong)ctx->sg_tbl, (ulong)(ctx->sg_tbl) + len);
+ flush_dcache_range((ulong)ctx->sha_desc,
+ (ulong)(ctx->sha_desc) + (sizeof(uint32_t) *
MAX_CAAM_DESCSIZE));
+ flush_dcache_range((ulong)ctx->hash,
+ (ulong)(ctx->hash) +
driver_hash[caam_algo].digestsize);
+
ret = run_descriptor_jr(ctx->sha_desc);
if (ret) {
debug("Error %x\n", ret);
return ret;
} else {
+ invalidate_dcache_range((ulong)ctx->hash,
+ (ulong)(ctx->hash) +
driver_hash[caam_algo].digestsize);
memcpy(dest_buf, ctx->hash, sizeof(ctx->hash));
}
free(ctx);
--
2.25.1
[PATCH] arm: gic_v2: Skip gic_init_secure when cpu is not in el3
From: Sai Pavan Boddu This would prevent configuring non-secure regs in case gic security extensions are not emulated in Qemu. Signed-off-by: Sai Pavan Boddu Signed-off-by: Michal Simek --- arch/arm/lib/gic_64.S | 5 + 1 file changed, 5 insertions(+) diff --git a/arch/arm/lib/gic_64.S b/arch/arm/lib/gic_64.S index 155212a419be..86cd882fc759 100644 --- a/arch/arm/lib/gic_64.S +++ b/arch/arm/lib/gic_64.S @@ -40,6 +40,8 @@ ENTRY(gic_init_secure) sub w10, w10, #0x1 cbnzw10, 0b #elif defined(CONFIG_GICV2) + switch_el x1, 2f, 1f, 1f +2: mov w9, #0x3/* EnableGrp0 | EnableGrp1 */ str w9, [x0, GICD_CTLR] /* Secure GICD_CTLR */ ldr w9, [x0, GICD_TYPER] @@ -141,6 +143,8 @@ ENTRY(gic_init_secure_percpu) * x0: Distributor Base * x1: Cpu Interface Base */ + switch_el x2, 4f, 5f, 5f +4: mov w9, #~0 /* Config SGIs and PPIs as Grp1 */ str w9, [x0, GICD_IGROUPRn] /* GICD_IGROUPR0 */ mov w9, #0x1/* Enable SGI 0 */ @@ -155,6 +159,7 @@ ENTRY(gic_init_secure_percpu) mov w9, #0x1 << 7 /* Non-Secure access to GICC_PMR */ str w9, [x1, GICC_PMR] #endif +5: ret ENDPROC(gic_init_secure_percpu) -- 2.36.0
[PATCH] i.MX8ULP: add display_ele_fw_version api
implement get f/w version api.
print ele f/w version in spl.
Signed-off-by: Gaurav Jain
Reviewed-by: Peng Fan
Reviewed-by: Pankaj Gupta
---
arch/arm/include/asm/arch-imx8ulp/s400_api.h | 2 +
board/freescale/imx8ulp_evk/spl.c| 19 +
drivers/misc/imx8ulp/s400_api.c | 41
3 files changed, 62 insertions(+)
diff --git a/arch/arm/include/asm/arch-imx8ulp/s400_api.h
b/arch/arm/include/asm/arch-imx8ulp/s400_api.h
index 1856659877..b3e6b3fa45 100644
--- a/arch/arm/include/asm/arch-imx8ulp/s400_api.h
+++ b/arch/arm/include/asm/arch-imx8ulp/s400_api.h
@@ -17,6 +17,7 @@
#define AHAB_WRITE_SECURE_FUSE_REQ_CID 0x91
#define AHAB_FWD_LIFECYCLE_UP_REQ_CID 0x95
#define AHAB_READ_FUSE_REQ_CID 0x97
+#define AHAB_GET_FW_VERSION_CID0x9D
#define AHAB_RELEASE_RDC_REQ_CID 0xC4
#define AHAB_WRITE_FUSE_REQ_CID0xD6
#define AHAB_CAAM_RELEASE_CID 0xD7
@@ -39,6 +40,7 @@ int ahab_forward_lifecycle(u16 life_cycle, u32 *response);
int ahab_write_fuse(u16 fuse_id, u32 fuse_val, bool lock, u32 *response);
int ahab_read_common_fuse(u16 fuse_id, u32 *fuse_words, u32 fuse_num, u32
*response);
int ahab_release_caam(u32 core_did, u32 *response);
+int ahab_get_fw_version(u32 *fw_version, u32 *sha1, u32 *response);
int ahab_dump_buffer(u32 *buffer, u32 buffer_length);
#endif
diff --git a/board/freescale/imx8ulp_evk/spl.c
b/board/freescale/imx8ulp_evk/spl.c
index 66bfc2bd0c..ece9ff26e9 100644
--- a/board/freescale/imx8ulp_evk/spl.c
+++ b/board/freescale/imx8ulp_evk/spl.c
@@ -58,6 +58,23 @@ int power_init_board(void)
return 0;
}
+void display_ele_fw_version(void)
+{
+ u32 fw_version, sha1, res;
+ int ret;
+
+ ret = ahab_get_fw_version(&fw_version, &sha1, &res);
+ if (ret) {
+ printf("ahab get firmware version failed %d, 0x%x\n", ret, res);
+ } else {
+ printf("ELE firmware version %u.%u.%u-%x",
+ (fw_version & (0x00ff)) >> 16,
+ (fw_version & (0xff00)) >> 8,
+ (fw_version & (0x00ff)), sha1);
+ ((fw_version & (0x8000)) >> 31) == 1 ? puts("-dirty\n") :
puts("\n");
+ }
+}
+
void spl_board_init(void)
{
struct udevice *dev;
@@ -77,6 +94,8 @@ void spl_board_init(void)
puts("Normal Boot\n");
+ display_ele_fw_version();
+
/* After AP set iomuxc0, the i2c can't work, Need M33 to set it now */
/* Load the lposc fuse to work around ROM issue. The fuse depends on
S400 to read. */
diff --git a/drivers/misc/imx8ulp/s400_api.c b/drivers/misc/imx8ulp/s400_api.c
index 3ffdeb2ad2..87f5880ccb 100644
--- a/drivers/misc/imx8ulp/s400_api.c
+++ b/drivers/misc/imx8ulp/s400_api.c
@@ -272,6 +272,47 @@ int ahab_release_caam(u32 core_did, u32 *response)
return ret;
}
+int ahab_get_fw_version(u32 *fw_version, u32 *sha1, u32 *response)
+{
+ struct udevice *dev = gd->arch.s400_dev;
+ int size = sizeof(struct imx8ulp_s400_msg);
+ struct imx8ulp_s400_msg msg;
+ int ret;
+
+ if (!dev) {
+ printf("s400 dev is not initialized\n");
+ return -ENODEV;
+ }
+
+ if (!fw_version) {
+ printf("Invalid parameters for f/w version read\n");
+ return -EINVAL;
+ }
+
+ if (!sha1) {
+ printf("Invalid parameters for commit sha1\n");
+ return -EINVAL;
+ }
+
+ msg.version = AHAB_VERSION;
+ msg.tag = AHAB_CMD_TAG;
+ msg.size = 1;
+ msg.command = AHAB_GET_FW_VERSION_CID;
+
+ ret = misc_call(dev, false, &msg, size, &msg, size);
+ if (ret)
+ printf("Error: %s: ret %d, response 0x%x\n",
+ __func__, ret, msg.data[0]);
+
+ if (response)
+ *response = msg.data[0];
+
+ *fw_version = msg.data[1];
+ *sha1 = msg.data[2];
+
+ return ret;
+}
+
int ahab_dump_buffer(u32 *buffer, u32 buffer_length)
{
struct udevice *dev = gd->arch.s400_dev;
--
2.25.1
[PATCH] caam: Fix crash in case caam_jr_probe failed
From: Ye Li
If probing caam_jr returns failure, the variable "dev" will not be
initialized, so we can't use dev->name for the error print.
Otherwise it will cause crash.
Signed-off-by: Ye Li
Reviewed-by: Gaurav Jain
---
arch/arm/cpu/armv7/ls102xa/cpu.c| 2 +-
arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 2 +-
arch/arm/mach-imx/imx8/cpu.c| 2 +-
arch/arm/mach-imx/imx8m/soc.c | 2 +-
arch/arm/mach-imx/mx6/soc.c | 2 +-
arch/arm/mach-imx/mx7/soc.c | 2 +-
arch/arm/mach-imx/mx7ulp/soc.c | 2 +-
arch/powerpc/cpu/mpc85xx/cpu_init.c | 2 +-
board/freescale/imx8mm_evk/spl.c| 2 +-
board/freescale/imx8mn_evk/spl.c| 2 +-
board/freescale/imx8mp_evk/spl.c| 2 +-
11 files changed, 11 insertions(+), 11 deletions(-)
diff --git a/arch/arm/cpu/armv7/ls102xa/cpu.c b/arch/arm/cpu/armv7/ls102xa/cpu.c
index 9fe1cd9048..0b3e3b2064 100644
--- a/arch/arm/cpu/armv7/ls102xa/cpu.c
+++ b/arch/arm/cpu/armv7/ls102xa/cpu.c
@@ -409,7 +409,7 @@ int arch_misc_init(void)
ret = uclass_get_device_by_driver(UCLASS_MISC,
DM_DRIVER_GET(caam_jr), &dev);
if (ret)
- printf("Failed to initialize %s: %d\n", dev->name, ret);
+ printf("Failed to initialize caam_jr: %d\n", ret);
}
return 0;
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index a71ee636af..253008a9c1 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -1648,7 +1648,7 @@ int arch_misc_init(void)
ret = uclass_get_device_by_driver(UCLASS_MISC,
DM_DRIVER_GET(caam_jr), &dev);
if (ret)
- printf("Failed to initialize %s: %d\n", dev->name, ret);
+ printf("Failed to initialize caam_jr: %d\n", ret);
}
serdes_misc_init();
diff --git a/arch/arm/mach-imx/imx8/cpu.c b/arch/arm/mach-imx/imx8/cpu.c
index 0858ea5f05..936c8f865a 100644
--- a/arch/arm/mach-imx/imx8/cpu.c
+++ b/arch/arm/mach-imx/imx8/cpu.c
@@ -100,7 +100,7 @@ int arch_misc_init(void)
ret = uclass_get_device_by_driver(UCLASS_MISC,
DM_DRIVER_GET(caam_jr), &dev);
if (ret)
- printf("Failed to initialize %s: %d\n", dev->name, ret);
+ printf("Failed to initialize caam_jr: %d\n", ret);
}
return 0;
diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c
index 8e23e6da32..66d6a21655 100644
--- a/arch/arm/mach-imx/imx8m/soc.c
+++ b/arch/arm/mach-imx/imx8m/soc.c
@@ -1410,7 +1410,7 @@ int arch_misc_init(void)
ret = uclass_get_device_by_driver(UCLASS_MISC,
DM_DRIVER_GET(caam_jr), &dev);
if (ret)
- printf("Failed to initialize %s: %d\n", dev->name, ret);
+ printf("Failed to initialize caam_jr: %d\n", ret);
}
return 0;
diff --git a/arch/arm/mach-imx/mx6/soc.c b/arch/arm/mach-imx/mx6/soc.c
index 2434bcfa98..67bd991989 100644
--- a/arch/arm/mach-imx/mx6/soc.c
+++ b/arch/arm/mach-imx/mx6/soc.c
@@ -744,7 +744,7 @@ int arch_misc_init(void)
ret = uclass_get_device_by_driver(UCLASS_MISC,
DM_DRIVER_GET(caam_jr), &dev);
if (ret)
- printf("Failed to initialize %s: %d\n", dev->name, ret);
+ printf("Failed to initialize caam_jr: %d\n", ret);
}
setup_serial_number();
return 0;
diff --git a/arch/arm/mach-imx/mx7/soc.c b/arch/arm/mach-imx/mx7/soc.c
index dc9ac31eb0..c672be5d5d 100644
--- a/arch/arm/mach-imx/mx7/soc.c
+++ b/arch/arm/mach-imx/mx7/soc.c
@@ -361,7 +361,7 @@ int arch_misc_init(void)
int ret;
ret = uclass_get_device_by_driver(UCLASS_MISC,
DM_DRIVER_GET(caam_jr), &dev);
if (ret)
- printf("Failed to initialize %s: %d\n", dev->name, ret);
+ printf("Failed to initialize caam_jr: %d\n", ret);
}
return 0;
diff --git a/arch/arm/mach-imx/mx7ulp/soc.c b/arch/arm/mach-imx/mx7ulp/soc.c
index 08bdc0c4af..217b7c4586 100644
--- a/arch/arm/mach-imx/mx7ulp/soc.c
+++ b/arch/arm/mach-imx/mx7ulp/soc.c
@@ -93,7 +93,7 @@ int arch_misc_init(void)
ret = uclass_get_device_by_driver(UCLASS_MISC,
DM_DRIVER_GET(caam_jr), &dev);
if (ret)
- printf("Failed to initialize %s: %d\n", dev->name, ret);
+ printf("Failed to initialize caam_jr: %d\n", ret);
}
return 0;
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c
b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index 16981de244..5fa4234fd0 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -950,7 +950,7 @@ int arch_misc_init(void)
ret = uclass_get_device_by_driver(UCLASS_MISC,
DM_DRIVER_GET(caam_j
Re: [PATCH v2 1/2] common: spl: spl_spi: add support for dynamic override of sf bus
Hello Achath, On 11.05.22 08:03, Vaishnav Achath wrote: > Currently the SPI flash to load from is defined through the compile > time config CONFIG_SF_DEFAULT_BUS and CONFIG_SF_DEFAULT_CS, this > prevents the loading of binaries from different SPI flash using the > same build.E.g. supporting QSPI flash boot and OSPI flash boot > on J721E platform is not possible due to this limitation. > > This commit adds lookup functions spl_spi_boot_bus() > and spl_spi_boot_cs for identifying the flash device based on the > selected boot device, when not overridden the lookup functions are > weakly defined in common/spl/spl_spi.c. > > Signed-off-by: Vaishnav Achath > --- you miss here change history. May you want to look into patman tool in u-boot:/tools/patman/README which can help you here much. > common/spl/spl_spi.c | 16 +--- > include/spl.h| 16 > 2 files changed, 29 insertions(+), 3 deletions(-) Looks fine for me, thanks! Reviewed-by: Heiko Schocher bye, Heiko -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-52 Fax: +49-8142-66989-80 Email: h...@denx.de
Re: [PATCH 2/2] stm32mp: fdt: update etzpc for STM32MP13x
Hi Patrick
On 5/9/22 17:13, Patrick Delaunay wrote:
> Add support of STM32MP13x the ETZPC part of fdt.c
>
> Signed-off-by: Patrick Delaunay
> Signed-off-by: Patrick Delaunay
> ---
>
> arch/arm/mach-stm32mp/fdt.c | 153 +++-
> 1 file changed, 151 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/mach-stm32mp/fdt.c b/arch/arm/mach-stm32mp/fdt.c
> index 5d37a44d97..bf2ef66034 100644
> --- a/arch/arm/mach-stm32mp/fdt.c
> +++ b/arch/arm/mach-stm32mp/fdt.c
> @@ -28,12 +28,119 @@
>
> #define ETZPC_RESERVED 0x
>
> +#define STM32MP13_FDCAN_BASE 0x4400F000
> +#define STM32MP13_ADC1_BASE 0x48003000
> +#define STM32MP13_TSC_BASE 0x5000B000
> +#define STM32MP13_CRYP_BASE 0x54002000
> +#define STM32MP13_ETH2_BASE 0x5800E000
> +#define STM32MP13_DCMIPP_BASE0x5A00
> +#define STM32MP13_LTDC_BASE 0x5A01
> +
> #define STM32MP15_FDCAN_BASE 0x4400e000
> #define STM32MP15_CRYP2_BASE 0x4c005000
> #define STM32MP15_CRYP1_BASE 0x54001000
> #define STM32MP15_GPU_BASE 0x5900
> #define STM32MP15_DSI_BASE 0x5a00
>
> +static const u32 stm32mp13_ip_addr[] = {
> + 0x50025000, /* 0 VREFBUF APB3 */
> + 0x50021000, /* 1 LPTIM2 APB3 */
> + 0x50022000, /* 2 LPTIM3 APB3 */
> + STM32MP13_LTDC_BASE,/* 3 LTDC APB4 */
> + STM32MP13_DCMIPP_BASE, /* 4 DCMIPP APB4 */
> + 0x5A006000, /* 5 USBPHYCTRL APB4 */
> + 0x5A003000, /* 6 DDRCTRLPHY APB4 */
> + ETZPC_RESERVED, /* 7 Reserved*/
> + ETZPC_RESERVED, /* 8 Reserved*/
> + ETZPC_RESERVED, /* 9 Reserved*/
> + 0x5C006000, /* 10 TZC APB5 */
> + 0x58001000, /* 11 MCE APB5 */
> + 0x5C00, /* 12 IWDG1 APB5 */
> + 0x5C008000, /* 13 STGENC APB5 */
> + ETZPC_RESERVED, /* 14 Reserved*/
> + ETZPC_RESERVED, /* 15 Reserved*/
> + 0x4C00, /* 16 USART1 APB6 */
> + 0x4C001000, /* 17 USART2 APB6 */
> + 0x4C002000, /* 18 SPI4 APB6 */
> + 0x4C003000, /* 19 SPI5 APB6 */
> + 0x4C004000, /* 20 I2C3 APB6 */
> + 0x4C005000, /* 21 I2C4 APB6 */
> + 0x4C006000, /* 22 I2C5 APB6 */
> + 0x4C007000, /* 23 TIM12 APB6 */
> + 0x4C008000, /* 24 TIM13 APB6 */
> + 0x4C009000, /* 25 TIM14 APB6 */
> + 0x4C00A000, /* 26 TIM15 APB6 */
> + 0x4C00B000, /* 27 TIM16 APB6 */
> + 0x4C00C000, /* 28 TIM17 APB6 */
> + ETZPC_RESERVED, /* 29 Reserved*/
> + ETZPC_RESERVED, /* 30 Reserved*/
> + ETZPC_RESERVED, /* 31 Reserved*/
> + STM32MP13_ADC1_BASE,/* 32 ADC1 AHB2 */
> + 0x48004000, /* 33 ADC2 AHB2 */
> + 0x4900, /* 34 OTG AHB2 */
> + ETZPC_RESERVED, /* 35 Reserved*/
> + ETZPC_RESERVED, /* 36 Reserved*/
> + STM32MP13_TSC_BASE, /* 37 TSC AHB4 */
> + ETZPC_RESERVED, /* 38 Reserved*/
> + ETZPC_RESERVED, /* 39 Reserved*/
> + 0x54004000, /* 40 RNG AHB5 */
> + 0x54003000, /* 41 HASH AHB5 */
> + STM32MP13_CRYP_BASE,/* 42 CRYPT AHB5 */
> + 0x54005000, /* 43 SAES AHB5 */
> + 0x54006000, /* 44 PKA AHB5 */
> + 0x5400, /* 45 BKPSRAM AHB5 */
> + ETZPC_RESERVED, /* 46 Reserved*/
> + ETZPC_RESERVED, /* 47 Reserved*/
> + 0x5800A000, /* 48 ETH1 AHB6 */
> + STM32MP13_ETH2_BASE,/* 49 ETH2 AHB6 */
> + 0x58005000, /* 50 SDMMC1 AHB6 */
> + 0x58007000, /* 51 SDMMC2 AHB6 */
> + ETZPC_RESERVED, /* 52 Reserved*/
> + ETZPC_RESERVED, /* 53 Reserved*/
> + 0x58002000, /* 54 FMC AHB6 */
> + 0x58003000, /* 55 QSPI AHB6 */
> + ETZPC_RESERVED, /* 56 Reserved*/
> + ETZPC_RESERVED, /* 57 Reserved*/
> + ETZPC_RESERVED, /* 58 Reserved*/
> + ETZPC_RESERVED, /* 59 Reserved*/
> + 0x3000, /* 60 SRAM1 MLAHB */
> + 0x30004000, /* 61 SRAM2 MLAHB */
> + 0x30006000, /* 62 SRAM3 MLAHB */
> + ETZPC_RESERVED, /* 63 Reserved*/
> + ETZPC_RESERVED, /* 64 Reserved*/
> + ETZPC_RESERVED, /* 65 Reserved*/
> + ETZPC_RESERVED, /* 66 Reserved*/
> + ETZPC_RESERVED, /* 67 Reserved*/
> + ETZPC_RESERVED, /* 68 Reserved*/
> + ETZPC_RESERVED, /* 69 Reserved*/
> + ETZPC_RESERVED, /* 70 Reserved*/
> + ETZPC_RESERVED, /* 71 Reserved*/
> + ETZPC_RESERVED, /* 72 Reserved*/
> + ETZPC_RESERVED, /* 73 Reserved*/
> + ETZPC_RESERVED, /* 74 Reserved*/
> + ETZPC_RESERVED, /* 75 Reserved*/
Re: [PATCH 1/2] stm32mp: fdt: update etzpc for STM32MP15x
Hi Patrick
On 5/9/22 17:13, Patrick Delaunay wrote:
> Introduce STM32MP15 function and defines to prepare the
> STM32MP13 introduction.
>
> Signed-off-by: Patrick Delaunay
> Signed-off-by: Patrick Delaunay
> ---
>
> arch/arm/mach-stm32mp/fdt.c | 123
> 1 file changed, 67 insertions(+), 56 deletions(-)
>
> diff --git a/arch/arm/mach-stm32mp/fdt.c b/arch/arm/mach-stm32mp/fdt.c
> index ad45728949..5d37a44d97 100644
> --- a/arch/arm/mach-stm32mp/fdt.c
> +++ b/arch/arm/mach-stm32mp/fdt.c
> @@ -28,13 +28,13 @@
>
> #define ETZPC_RESERVED 0x
>
> -#define STM32_FDCAN_BASE 0x4400e000
> -#define STM32_CRYP2_BASE 0x4c005000
> -#define STM32_CRYP1_BASE 0x54001000
> -#define STM32_GPU_BASE 0x5900
> -#define STM32_DSI_BASE 0x5a00
> +#define STM32MP15_FDCAN_BASE 0x4400e000
> +#define STM32MP15_CRYP2_BASE 0x4c005000
> +#define STM32MP15_CRYP1_BASE 0x54001000
> +#define STM32MP15_GPU_BASE 0x5900
> +#define STM32MP15_DSI_BASE 0x5a00
>
> -static const u32 stm32mp1_ip_addr[] = {
> +static const u32 stm32mp15_ip_addr[] = {
> 0x5c008000, /* 00 stgenc */
> 0x5400, /* 01 bkpsram */
> 0x5c003000, /* 02 iwdg1 */
> @@ -44,7 +44,7 @@ static const u32 stm32mp1_ip_addr[] = {
> ETZPC_RESERVED, /* 06 reserved */
> 0x54003000, /* 07 rng1 */
> 0x54002000, /* 08 hash1 */
> - STM32_CRYP1_BASE, /* 09 cryp1 */
> + STM32MP15_CRYP1_BASE, /* 09 cryp1 */
> 0x5a003000, /* 0A ddrctrl */
> 0x5a004000, /* 0B ddrphyc */
> 0x5c009000, /* 0C i2c6 */
> @@ -97,7 +97,7 @@ static const u32 stm32mp1_ip_addr[] = {
> 0x4400b000, /* 3B sai2 */
> 0x4400c000, /* 3C sai3 */
> 0x4400d000, /* 3D dfsdm */
> - STM32_FDCAN_BASE, /* 3E tt_fdcan */
> + STM32MP15_FDCAN_BASE, /* 3E tt_fdcan */
> ETZPC_RESERVED, /* 3F reserved */
> 0x50021000, /* 40 lptim2 */
> 0x50022000, /* 41 lptim3 */
> @@ -110,7 +110,7 @@ static const u32 stm32mp1_ip_addr[] = {
> 0x48003000, /* 48 adc */
> 0x4c002000, /* 49 hash2 */
> 0x4c003000, /* 4A rng2 */
> - STM32_CRYP2_BASE, /* 4B cryp2 */
> + STM32MP15_CRYP2_BASE, /* 4B cryp2 */
> ETZPC_RESERVED, /* 4C reserved */
> ETZPC_RESERVED, /* 4D reserved */
> ETZPC_RESERVED, /* 4E reserved */
> @@ -163,8 +163,13 @@ static int stm32_fdt_fixup_etzpc(void *fdt, int soc_node)
> int offset, shift;
> u32 addr, status, decprot[ETZPC_DECPROT_NB];
>
> - array = stm32mp1_ip_addr;
> - array_size = ARRAY_SIZE(stm32mp1_ip_addr);
> + if (IS_ENABLED(CONFIG_STM32MP13x))
> + return 0;
> +
> + if (IS_ENABLED(CONFIG_STM32MP15x)) {
> + array = stm32mp15_ip_addr;
> + array_size = ARRAY_SIZE(stm32mp15_ip_addr);
> + }
>
> for (i = 0; i < ETZPC_DECPROT_NB; i++)
> decprot[i] = readl(ETZPC_DECPROT(i));
> @@ -248,33 +253,9 @@ static void stm32_fdt_disable_optee(void *blob)
> }
> }
>
> -/*
> - * This function is called right before the kernel is booted. "blob" is the
> - * device tree that will be passed to the kernel.
> - */
> -int ft_system_setup(void *blob, struct bd_info *bd)
> +static void stm32mp15_fdt_fixup(void *blob, int soc, u32 cpu, char *name)
> {
> - int ret = 0;
> - int soc;
> - u32 pkg, cpu;
> - char name[SOC_NAME_SIZE];
> -
> - if (IS_ENABLED(CONFIG_STM32MP13x))
> - return 0;
> -
> - soc = fdt_path_offset(blob, "/soc");
> - if (soc < 0)
> - return soc;
> -
> - if (CONFIG_IS_ENABLED(STM32_ETZPC)) {
> - ret = stm32_fdt_fixup_etzpc(blob, soc);
> - if (ret)
> - return ret;
> - }
> -
> - /* MPUs Part Numbers and name*/
> - cpu = get_cpu_type();
> - get_soc_name(name);
> + u32 pkg;
>
> switch (cpu) {
> case CPU_STM32MP151Fxx:
> @@ -284,19 +265,18 @@ int ft_system_setup(void *blob, struct bd_info *bd)
> stm32_fdt_fixup_cpu(blob, name);
> /* after cpu delete we can't trust the soc offsets anymore */
> soc = fdt_path_offset(blob, "/soc");
> - stm32_fdt_disable(blob, soc, STM32_FDCAN_BASE, "can", name);
> - /* fall through */
> + stm32_fdt_disable(blob, soc, STM32MP15_FDCAN_BASE, "can", name);
> + fallthrough;
> case CPU_STM32MP153Fxx:
> case CPU_STM32MP153Dxx:
> case CPU_STM32MP153Cxx:
> case CPU_STM32MP153Axx:
> - stm32_fdt_disable(blob, soc, STM32_GPU_BASE, "gpu", name);
> - stm32_fdt_disable(blob, soc, STM32_DSI_BASE, "dsi", name);
> + stm32_fdt_disable(blob, soc, STM32MP15_GPU_BASE, "gpu", name);
> + stm32_fdt_disable(blob, soc, STM32MP15_DSI_BASE, "dsi", name);
> break;
> default:
>
Re: runtime configuration of env_addr
On 5/11/22 03:38, Hiren Mehta wrote: Hi All, I was wondering if there is a way to override the gd->env_addr that is initialized in env_flash_init() for flash based environment. As I see, env_addr depends on the env_ptr which is set to compile time value of CONFIG_ENV_ADDR. I was thinking of doing it in board_early_init_f(). But, as I understand, the env_init() will override it. Thanks, -h CONFIG_ENV_ADDR is the start address the flash sector containing the environment. gd->env_addr is the address in RAM where the environment is stored. Please, explain why you want to change gd->env_addr. What do you want to achieve? Have a look at then 'env import' command which allows you to import an alternative environment, e.g. as PREBOOT command. Cf. https://u-boot.readthedocs.io/en/latest/usage/cmd/env.html?highlight=env%20import#import Best regards Heinrich
[PATCH 1/2] watchdog: octeontx_wdt: Add MIPS Octeon support
This patch adds support for the Marvell Octeon watchdog driver, which
currently only support the ARM64 Octeon TX & TX2 platforms. Since the
IP is pretty similar, it makes sense to extend this driver to also
support the MIPS Octeon SoC.
A follow-up patch will enable this watchdog support on the EBB7304
eval board.
Signed-off-by: Stefan Roese
Cc: Aaron Williams
Cc: Chandrakala Chavva
---
drivers/watchdog/Kconfig| 9 ++---
drivers/watchdog/octeontx_wdt.c | 67 -
2 files changed, 53 insertions(+), 23 deletions(-)
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index c3eb8a8aec1b..2c6116fb7f9c 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -213,14 +213,13 @@ config WDT_NPCM
It performs full SoC reset.
config WDT_OCTEONTX
- bool "OcteonTX core watchdog support"
- depends on WDT && (ARCH_OCTEONTX || ARCH_OCTEONTX2)
+ bool "Octeon core watchdog support"
+ depends on WDT && (ARCH_OCTEON || ARCH_OCTEONTX || ARCH_OCTEONTX2)
default y
imply WATCHDOG
help
- This enables OcteonTX watchdog driver, which can be
- found on OcteonTX/TX2 chipsets and inline with driver model.
- Only supports watchdog reset.
+ This enables the Octeon watchdog driver, which can be found on
+ various Octeon parts such as Octeon II/III and OcteonTX/TX2.
config WDT_OMAP3
bool "TI OMAP watchdog timer support"
diff --git a/drivers/watchdog/octeontx_wdt.c b/drivers/watchdog/octeontx_wdt.c
index 01b244db8075..c79d9539c13f 100644
--- a/drivers/watchdog/octeontx_wdt.c
+++ b/drivers/watchdog/octeontx_wdt.c
@@ -15,16 +15,22 @@
DECLARE_GLOBAL_DATA_PTR;
-#define CORE0_WDOG_OFFSET 0x4
-#define CORE0_POKE_OFFSET 0x5
#define CORE0_POKE_OFFSET_MASK 0xfULL
#define WDOG_MODE GENMASK_ULL(1, 0)
#define WDOG_LEN GENMASK_ULL(19, 4)
#define WDOG_CNT GENMASK_ULL(43, 20)
+struct octeontx_wdt_data {
+ u32 wdog_offset;
+ u32 poke_offset;
+ int timer_shift;
+ bool has_clk;
+};
+
struct octeontx_wdt {
void __iomem *reg;
+ const struct octeontx_wdt_data *data;
struct clk clk;
};
@@ -34,12 +40,16 @@ static int octeontx_wdt_start(struct udevice *dev, u64
timeout_ms, ulong flags)
u64 clk_rate, val;
u64 tout_wdog;
- clk_rate = clk_get_rate(&priv->clk);
- if (IS_ERR_VALUE(clk_rate))
- return -EINVAL;
+ if (priv->data->has_clk) {
+ clk_rate = clk_get_rate(&priv->clk);
+ if (IS_ERR_VALUE(clk_rate))
+ return -EINVAL;
+ } else {
+ clk_rate = gd->bus_clk;
+ }
- /* Watchdog counts in 1024 cycle steps */
- tout_wdog = (clk_rate * timeout_ms / 1000) >> 10;
+ /* Watchdog counts in configured cycle steps */
+ tout_wdog = (clk_rate * timeout_ms / 1000) >> priv->data->timer_shift;
/*
* We can only specify the upper 16 bits of a 24 bit value.
@@ -54,7 +64,7 @@ static int octeontx_wdt_start(struct udevice *dev, u64
timeout_ms, ulong flags)
val = FIELD_PREP(WDOG_MODE, 0x3) |
FIELD_PREP(WDOG_LEN, tout_wdog) |
FIELD_PREP(WDOG_CNT, tout_wdog << 8);
- writeq(val, priv->reg + CORE0_WDOG_OFFSET);
+ writeq(val, priv->reg + priv->data->wdog_offset);
return 0;
}
@@ -63,7 +73,7 @@ static int octeontx_wdt_stop(struct udevice *dev)
{
struct octeontx_wdt *priv = dev_get_priv(dev);
- writeq(0, priv->reg + CORE0_WDOG_OFFSET);
+ writeq(0, priv->reg + priv->data->wdog_offset);
return 0;
}
@@ -82,7 +92,7 @@ static int octeontx_wdt_reset(struct udevice *dev)
{
struct octeontx_wdt *priv = dev_get_priv(dev);
- writeq(~0ULL, priv->reg + CORE0_POKE_OFFSET);
+ writeq(~0ULL, priv->reg + priv->data->poke_offset);
return 0;
}
@@ -103,6 +113,10 @@ static int octeontx_wdt_probe(struct udevice *dev)
if (!priv->reg)
return -EINVAL;
+ priv->data = (void *)dev_get_driver_data(dev);
+ if (!priv->data)
+ return -EINVAL;
+
/*
* Save base register address in reg masking lower 20 bits
* as 0xa appears when extracted from the DT
@@ -110,13 +124,15 @@ static int octeontx_wdt_probe(struct udevice *dev)
priv->reg = (void __iomem *)(((u64)priv->reg &
~CORE0_POKE_OFFSET_MASK));
- ret = clk_get_by_index(dev, 0, &priv->clk);
- if (ret < 0)
- return ret;
+ if (priv->data->has_clk) {
+ ret = clk_get_by_index(dev, 0, &priv->clk);
+ if (ret < 0)
+ return ret;
- ret = clk_enable(&priv->clk);
- if (ret)
- return ret;
+ ret = clk_enable(&priv->clk);
+ if (ret)
+
[PATCH 2/2] mips: octeon: octeon_ebb7304_defconfig: Enable watchdog support
This patch enables the recently added watchdog support on the MIPS Octeon EBB7304 eval board. Signed-off-by: Stefan Roese Cc: Aaron Williams Cc: Chandrakala Chavva Cc: Daniel Schwierzeck --- configs/octeon_ebb7304_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/configs/octeon_ebb7304_defconfig b/configs/octeon_ebb7304_defconfig index f70f0d214cf9..f6dc4feef742 100644 --- a/configs/octeon_ebb7304_defconfig +++ b/configs/octeon_ebb7304_defconfig @@ -25,6 +25,7 @@ CONFIG_CMD_MTD=y CONFIG_CMD_PART=y CONFIG_CMD_PCI=y CONFIG_CMD_USB=y +CONFIG_CMD_WDT=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y @@ -87,4 +88,5 @@ CONFIG_USB_ETHER_ASIX88179=y CONFIG_USB_ETHER_MCS7830=y CONFIG_USB_ETHER_RTL8152=y CONFIG_USB_ETHER_SMSC95XX=y +CONFIG_WDT=y CONFIG_HEXDUMP=y -- 2.36.1
Re: [PATCH 1/1] btrfs: simplify lookup_data_extent()
On 2022/5/11 06:48, Qu Wenruo wrote:
On 2022/5/11 03:43, Heinrich Schuchardt wrote:
After returning if ret <= 0 we know that ret > 0. No need to check it.
Signed-off-by: Heinrich Schuchardt
Reviewed-by: Qu Wenruo
Just to mention for other guys in the btrfs list, this patch is for
U-boot btrfs implementation.
And I also checked btrfs-fuse project, which has a similar function,
lookup_file_extent(), it already does the check properly and even do
extra quick exit for (ret > 0 && path->slots[0] == 0) case.
So you may want to also check btrfs-fuse project to find some possible
optimization and cross-port to U-boot.
(So far btrfs-fuse has better test coverage using fsstress, and
cross-checked against kernel).
Thanks,
Qu
Thanks,
Qu
---
fs/btrfs/inode.c | 15 ++-
1 file changed, 6 insertions(+), 9 deletions(-)
diff --git a/fs/btrfs/inode.c b/fs/btrfs/inode.c
index d00b515333..0173d30cd8 100644
--- a/fs/btrfs/inode.c
+++ b/fs/btrfs/inode.c
@@ -546,15 +546,12 @@ static int lookup_data_extent(struct btrfs_root
*root, struct btrfs_path *path,
/* Error or we're already at the file extent */
if (ret <= 0)
return ret;
- if (ret > 0) {
- /* Check previous file extent */
- ret = btrfs_previous_item(root, path, ino,
- BTRFS_EXTENT_DATA_KEY);
- if (ret < 0)
- return ret;
- if (ret > 0)
- goto check_next;
- }
+ /* Check previous file extent */
+ ret = btrfs_previous_item(root, path, ino, BTRFS_EXTENT_DATA_KEY);
+ if (ret < 0)
+ return ret;
+ if (ret > 0)
+ goto check_next;
/* Now the key.offset must be smaller than @file_offset */
btrfs_item_key_to_cpu(path->nodes[0], &key, path->slots[0]);
if (key.objectid != ino ||
