[v4 11/12] mtd: spi-nor-ids: Add Winbond W25Q512JV ID
Add ID for Winbond W25Q512JV device which is supported
on AST2600 EVB by default.
Signed-off-by: Chin-Ting Kuo
---
drivers/mtd/spi/spi-nor-ids.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c
index 7050ddc397..444affb5af 100644
--- a/drivers/mtd/spi/spi-nor-ids.c
+++ b/drivers/mtd/spi/spi-nor-ids.c
@@ -362,6 +362,11 @@ const struct flash_info spi_nor_ids[] = {
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
},
+ {
+ INFO("w25q512jv", 0xef4020, 0, 64 * 1024, 1024,
+SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
+SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
+ },
{
INFO("w25q01jv", 0xef4021, 0, 64 * 1024, 2048,
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
--
2.25.1
[v4 12/12] spi: aspeed: Fix bug when SPI_NOR_4B_OPCODES flag is set
When SPI_NOR_4B_OPCODES flag is set for a specific flash
in spi_nor_ids[] table, EN4B command will not be issued and
4-byte dedicated commands will be used to access SPI flash.
Thus, instead of EN4B command, address length is more suitable
for deciding whether the controller should be set to 4-byte mode.
Signed-off-by: Chin-Ting Kuo
---
drivers/spi/spi-aspeed.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/drivers/spi/spi-aspeed.c b/drivers/spi/spi-aspeed.c
index e5e348eb7b..687ddc370b 100644
--- a/drivers/spi/spi-aspeed.c
+++ b/drivers/spi/spi-aspeed.c
@@ -504,10 +504,6 @@ static int aspeed_spi_exec_op_user_mode(struct spi_slave
*slave,
/* Restore controller setting. */
writel(flash->ce_ctrl_read, ctrl_reg);
- /* Set controller to 4-byte mode when flash is in 4-byte mode. */
- if (op->cmd.opcode == SPINOR_OP_EN4B)
- priv->info->set_4byte(bus, cs);
-
return 0;
}
@@ -561,6 +557,9 @@ static int aspeed_spi_dirmap_create(struct
spi_mem_dirmap_desc *desc)
plat->ctrl_base + REG_CE0_CTRL_REG + cs * 4);
priv->flashes[cs].ce_ctrl_read = reg_val;
+ if (op_tmpl.addr.nbytes == 4)
+ priv->info->set_4byte(bus, cs);
+
dev_dbg(dev, "read bus width: %d [0x%08x]\n",
op_tmpl.data.buswidth, priv->flashes[cs].ce_ctrl_read);
} else {
--
2.25.1
[v4 10/12] configs: aspeed: Enable CONFIG_SPI_DIRMAP
Enable CONFIG_SPI_DIRMAP on ASPEED platforms. Signed-off-by: Chin-Ting Kuo --- configs/evb-ast2500_defconfig | 1 + configs/evb-ast2600_defconfig | 1 + 2 files changed, 2 insertions(+) diff --git a/configs/evb-ast2500_defconfig b/configs/evb-ast2500_defconfig index fd04fe5a60..097b991a1b 100644 --- a/configs/evb-ast2500_defconfig +++ b/configs/evb-ast2500_defconfig @@ -56,6 +56,7 @@ CONFIG_DM_SERIAL=y CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_DM_SPI=y +CONFIG_SPI_DIRMAP=y CONFIG_SPI_ASPEED=y CONFIG_SYSRESET=y CONFIG_TIMER=y diff --git a/configs/evb-ast2600_defconfig b/configs/evb-ast2600_defconfig index ccf63ec6d0..7caa04d5b7 100644 --- a/configs/evb-ast2600_defconfig +++ b/configs/evb-ast2600_defconfig @@ -89,6 +89,7 @@ CONFIG_DM_SERIAL=y CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_DM_SPI=y +CONFIG_SPI_DIRMAP=y CONFIG_SPI_ASPEED=y CONFIG_SYSRESET=y CONFIG_SPL_SYSRESET=y -- 2.25.1
[v4 02/12] pinctrl: aspeed: FWSPICS1 and SPI1CS1 pin support
Add FWSPICS1 and SPI1CS1 in AST2500 pinctrl group.
On AST2500 EVB, FWSPICS1 can be supported by default.
An extra jumper, J45, should be configured before
enabling SPI1CS1.
Signed-off-by: Chin-Ting Kuo
Reviewed-by: Cédric Le Goater
---
drivers/pinctrl/aspeed/pinctrl_ast2500.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/pinctrl/aspeed/pinctrl_ast2500.c
b/drivers/pinctrl/aspeed/pinctrl_ast2500.c
index 3c2e10b88e..93920a6389 100644
--- a/drivers/pinctrl/aspeed/pinctrl_ast2500.c
+++ b/drivers/pinctrl/aspeed/pinctrl_ast2500.c
@@ -61,6 +61,8 @@ static const struct ast2500_group_config ast2500_groups[] = {
{ "MDIO2", 5, (1 << 2) },
{ "SD1", 5, (1 << 0) },
{ "SD2", 5, (1 << 1) },
+ { "FWSPICS1", 3, (1 << 24) },
+ { "SPI1CS1", 1, (1 << 15) },
};
static int ast2500_pinctrl_get_groups_count(struct udevice *dev)
--
2.25.1
[v4 05/12] MAINTAINERS: Add ASPEED SPI driver file
Add spi-aspeed.c file for ARM ASPEED. Signed-off-by: Chin-Ting Kuo --- MAINTAINERS | 7 +++ 1 file changed, 7 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 56be0bfad0..f2cd707eda 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -688,6 +688,13 @@ S: Maintained F: drivers/pci/pcie_phytium.c F: arch/arm/dts/phytium-durian.dts +ASPEED FMC SPI DRIVER +M: Chin-Ting Kuo +M: Cédric Le Goater +R: Aspeed BMC SW team +S: Maintained +F: drivers/spi/spi-aspeed.c + BINMAN M: Simon Glass M: Alper Nebi Yasak -- 2.25.1
[v4 03/12] spi: aspeed: Add ASPEED SPI controller driver
Add ASPEED BMC FMC/SPI memory controller driver with
spi-mem interface for AST2500 and AST2600 platform.
There are three SPI memory controllers embedded in an ASPEED SoC.
- FMC: Named as Firmware Memory Controller. After AC on, MCU ROM
fetches initial device boot image from FMC chip select(CS) 0.
- SPI1: Play the role of a SPI Master controller. Or, there is a
dedicated path for HOST(X86) to access its BIOS flash mounted
under BMC. spi-aspeed.c implements the control sequence when
SPI1 is a SPI master.
- SPI2: It is a pure SPI flash controller. For most scenarios, flashes
mounted under it are for pure storage purpose.
ASPEED SPI controller supports 1-1-1, 1-1-2 and 1-1-4 SPI flash mode.
Three types of command mode are supported, normal mode, command
read/write mode and user mode.
- Normal mode: Default mode. After power on, normal read command 03h or
13h is used to fetch boot image from SPI flash.
- AST2500: Only 03h command can be used after power on
or reset.
- AST2600: If FMC04[6:4] is set, 13h command is used,
otherwise, 03h command.
The address length is decided by FMC04[2:0].
- Command mode: SPI controller can send command and address
automatically when CPU read/write the related remapped
or decoded address area. The command used by this mode
can be configured by FMC10/14/18[23:16]. Also, the
address length is decided by FMC04[2:0]. This mode will
be implemented in the following patch series.
- User mode: It is a traditional and pure SPI operation, where
SPI transmission is controlled by CPU. It is the main
mode in this patch.
Each SPI controller in ASPEED SoC has its own decoded address mapping.
Within each SPI controller decoded address, driver can assign a specific
address region for each CS of a SPI controller. The decoded address
cannot overlap to each other. With normal mode and command mode, the
decoded address accessed by the CPU determines which CS is active.
When user mode is adopted, the CS decoded address is a FIFO, CPU can
send/receive any SPI transmission by accessing the related decoded
address for the target CS.
Signed-off-by: Chin-Ting Kuo
---
v2: Remove defconfig files from this patch.
drivers/spi/Kconfig | 8 +
drivers/spi/Makefile | 1 +
drivers/spi/spi-aspeed.c | 822 +++
3 files changed, 831 insertions(+)
create mode 100644 drivers/spi/spi-aspeed.c
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index a1e515cb2b..a616294910 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -387,6 +387,14 @@ config SANDBOX_SPI
};
};
+config SPI_ASPEED
+ bool "ASPEED SPI controller driver"
+ depends on DM_SPI && SPI_MEM
+ default n
+ help
+ Enable ASPEED SPI controller driver for AST2500
+ and AST2600 SoCs.
+
config SPI_SIFIVE
bool "SiFive SPI driver"
help
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 06e81b465b..36a4bd5dce 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -9,6 +9,7 @@ obj-y += spi-uclass.o
obj-$(CONFIG_CADENCE_QSPI) += cadence_qspi.o cadence_qspi_apb.o
obj-$(CONFIG_SANDBOX) += spi-emul-uclass.o
obj-$(CONFIG_SOFT_SPI) += soft_spi.o
+obj-$(CONFIG_SPI_ASPEED) += spi-aspeed.o
obj-$(CONFIG_SPI_MEM) += spi-mem.o
obj-$(CONFIG_TI_QSPI) += ti_qspi.o
obj-$(CONFIG_FSL_QSPI) += fsl_qspi.o
diff --git a/drivers/spi/spi-aspeed.c b/drivers/spi/spi-aspeed.c
new file mode 100644
index 00..9574aff793
--- /dev/null
+++ b/drivers/spi/spi-aspeed.c
@@ -0,0 +1,822 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * ASPEED FMC/SPI Controller driver
+ *
+ * Copyright (c) 2022 ASPEED Corporation.
+ * Copyright (c) 2022 IBM Corporation.
+ *
+ * Author:
+ * Chin-Ting Kuo
+ * Cedric Le Goater
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+/* ASPEED FMC/SPI memory control register related */
+#define REG_CE_TYPE_SETTING 0x00
+#define REG_CE_ADDR_MODE_CTRL0x04
+#define REG_INTR_CTRL_STATUS 0x08
+#define REG_CE0_CTRL_REG 0x10
+#define REG_CE0_DECODED_ADDR_REG 0x30
+
+#define ASPEED_SPI_MAX_CS 3
+#define FLASH_CALIBRATION_LEN 0x400
+
+#define CTRL_IO_SINGLE_DATA 0
+#define CTRL_IO_QUAD_DATA BIT(30)
+#define CTRL_IO_DUAL_DATA BIT(29)
+
+#define CTRL_IO_MODE_USER GENMASK(1, 0)
+#define CTRL_IO_MODE_CMD_READ BIT(0)
+#define CTRL_IO_MODE_CMD_WRITE BIT(1)
+#define CTRL_STOP_ACTIVEBIT(2)
+
+struct aspeed_spi_plat {
+ fdt_addr_t ctrl_base;
+ void __iomem *ahb_base; /* AHB address base for all flash devices. */
+ fdt_size_t
[v4 04/12] configs: aspeed: Enable SPI flash features
- Enable ASPEED SPI controller driver. - Enable SPI flash memory configurations. - Enable configurations for SPI flash manufacturers supported on both ASPEED AST2500 and AST2600 AVL. Signed-off-by: Chin-Ting Kuo --- configs/evb-ast2500_defconfig | 13 + configs/evb-ast2600_defconfig | 13 + 2 files changed, 26 insertions(+) diff --git a/configs/evb-ast2500_defconfig b/configs/evb-ast2500_defconfig index 2371cc2742..fd04fe5a60 100644 --- a/configs/evb-ast2500_defconfig +++ b/configs/evb-ast2500_defconfig @@ -35,6 +35,16 @@ CONFIG_DM_I2C=y CONFIG_SYS_I2C_ASPEED=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ASPEED=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_ISSI=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_SST=y +CONFIG_SPI_FLASH_WINBOND=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_PHY_REALTEK=y CONFIG_DM_ETH=y CONFIG_FTGMAC100=y @@ -44,6 +54,9 @@ CONFIG_RAM=y CONFIG_DM_RESET=y CONFIG_DM_SERIAL=y CONFIG_SYS_NS16550=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_SPI_ASPEED=y CONFIG_SYSRESET=y CONFIG_TIMER=y CONFIG_WDT=y diff --git a/configs/evb-ast2600_defconfig b/configs/evb-ast2600_defconfig index f84b723bbb..ccf63ec6d0 100644 --- a/configs/evb-ast2600_defconfig +++ b/configs/evb-ast2600_defconfig @@ -65,6 +65,16 @@ CONFIG_DM_I2C=y CONFIG_MISC=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ASPEED=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_ISSI=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_SST=y +CONFIG_SPI_FLASH_WINBOND=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_PHY_REALTEK=y CONFIG_DM_ETH=y CONFIG_DM_MDIO=y @@ -77,6 +87,9 @@ CONFIG_SPL_RAM=y CONFIG_DM_RESET=y CONFIG_DM_SERIAL=y CONFIG_SYS_NS16550=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_SPI_ASPEED=y CONFIG_SYSRESET=y CONFIG_SPL_SYSRESET=y CONFIG_WDT=y -- 2.25.1
[v4 00/12] Add ASPEED SPI controller driver
This patch series aims to porting ASPEED FMC/SPI memory controller driver with spi-mem interface. spi-mem dirmap framework is also synchronized from Linux. These patches have been verified on both AST2600 and AST2500 EVBs. Changes in v2: - Separate defconfig files from the SPI driver patch. - Use "if (CONFIG_IS_ENABLED(SPI_DIRMAP))" to wrap spi_dirmap related functions. - Add Winbond w25q512jv flash ID. Changes in v3: - Get AHB bus clock frequency from the function parameter. - Fix a grammatical error in spi-mem.h. Changes in v4: - Fix bug when SPI_NOR_4B_OPCODES flag is set. Chin-Ting Kuo (12): clk: aspeed: Get HCLK frequency support pinctrl: aspeed: FWSPICS1 and SPI1CS1 pin support spi: aspeed: Add ASPEED SPI controller driver configs: aspeed: Enable SPI flash features MAINTAINERS: Add ASPEED SPI driver file arm: dts: aspeed: Update SPI flash node settings spi-mem: Add dirmap API from Linux mtd: spi-nor: Use spi-mem dirmap API spi: aspeed: SPI dirmap read support configs: aspeed: Enable CONFIG_SPI_DIRMAP mtd: spi-nor-ids: Add Winbond W25Q512JV ID spi: aspeed: Fix bug when SPI_NOR_4B_OPCODES flag is set MAINTAINERS | 7 + arch/arm/dts/ast2500-evb.dts | 33 + arch/arm/dts/ast2500.dtsi| 23 +- arch/arm/dts/ast2600-evb.dts | 8 - arch/arm/dts/ast2600.dtsi| 34 +- configs/evb-ast2500_defconfig| 14 + configs/evb-ast2600_defconfig| 14 + drivers/clk/aspeed/clk_ast2500.c | 23 + drivers/mtd/spi/sf_probe.c | 76 ++ drivers/mtd/spi/spi-nor-core.c | 55 +- drivers/mtd/spi/spi-nor-ids.c| 5 + drivers/pinctrl/aspeed/pinctrl_ast2500.c | 2 + drivers/spi/Kconfig | 18 + drivers/spi/Makefile | 1 + drivers/spi/spi-aspeed.c | 914 +++ drivers/spi/spi-mem.c| 268 +++ include/linux/mtd/spi-nor.h | 18 + include/spi-mem.h| 79 ++ 18 files changed, 1546 insertions(+), 46 deletions(-) create mode 100644 drivers/spi/spi-aspeed.c -- 2.25.1
[v4 01/12] clk: aspeed: Get HCLK frequency support
User can get correct HCLK frequency during driver probe stage
by adding the following configuration in the device tree.
"clocks = < ASPEED_CLK_AHB>".
Signed-off-by: Chin-Ting Kuo
Reviewed-by: Cédric Le Goater
---
v3: Get AHB bus clock frequency from the function parameter.
drivers/clk/aspeed/clk_ast2500.c | 23 +++
1 file changed, 23 insertions(+)
diff --git a/drivers/clk/aspeed/clk_ast2500.c b/drivers/clk/aspeed/clk_ast2500.c
index a1b4496ca2..d99964fcd7 100644
--- a/drivers/clk/aspeed/clk_ast2500.c
+++ b/drivers/clk/aspeed/clk_ast2500.c
@@ -29,6 +29,12 @@
#define D2PLL_DEFAULT_RATE (250 * 1000 * 1000)
+/*
+ * AXI/AHB clock selection, taken from Aspeed SDK
+ */
+#define SCU_HWSTRAP_AXIAHB_DIV_SHIFT9
+#define SCU_HWSTRAP_AXIAHB_DIV_MASK (0x7 << SCU_HWSTRAP_AXIAHB_DIV_SHIFT)
+
DECLARE_GLOBAL_DATA_PTR;
/*
@@ -85,6 +91,20 @@ static ulong ast2500_get_clkin(struct ast2500_scu *scu)
? 25 * 1000 * 1000 : 24 * 1000 * 1000;
}
+static u32 ast2500_get_hclk(ulong clkin, struct ast2500_scu *scu)
+{
+ u32 hpll_reg = readl(>h_pll_param);
+ ulong axi_div = 2;
+ u32 rate;
+ ulong ahb_div = 1 + ((readl(>hwstrap)
+ & SCU_HWSTRAP_AXIAHB_DIV_MASK)
+>> SCU_HWSTRAP_AXIAHB_DIV_SHIFT);
+
+ rate = ast2500_get_hpll_rate(clkin, hpll_reg);
+
+ return (rate / axi_div / ahb_div);
+}
+
/**
* Get current rate or uart clock
*
@@ -146,6 +166,9 @@ static ulong ast2500_clk_get_rate(struct clk *clk)
rate = rate / apb_div;
}
break;
+ case ASPEED_CLK_AHB:
+ rate = ast2500_get_hclk(clkin, priv->scu);
+ break;
case ASPEED_CLK_SDIO:
{
ulong apb_div = 4 + 4 * ((readl(>scu->clk_sel1)
--
2.25.1
Re: [PATCH V4 7/8] arm: dts: imx8m: shrink ddr firmware size to actual file size
Hi
Il lun 23 mag 2022, 23:13 Alper Nebi Yasak ha
scritto:
> On 20/05/2022 17:10, Peng Fan (OSS) wrote:
> > From: Peng Fan
> >
> > After we switch to use BINMAN_SYMBOLS, there is no need to pad
> > the file size to 0x8000 and 0x4000. After we use BINMAN_SYMBOLS,
> > the u-boot-spl-ddr.bin shrink about 36KB with i.MX8MP-EVK.
> >
> > Tested-by: Tim Harvey #imx8m[m,n,p]-venice
> > Signed-off-by: Peng Fan
> > ---
> > arch/arm/dts/imx8mm-u-boot.dtsi | 8
> > arch/arm/dts/imx8mn-beacon-kit-u-boot.dtsi | 8
> > arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi | 8
> > arch/arm/dts/imx8mn-evk-u-boot.dtsi | 8
> > arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi | 8
> > arch/arm/dts/imx8mn-venice-u-boot.dtsi | 8
> > arch/arm/dts/imx8mp-u-boot.dtsi | 8
> > arch/arm/dts/imx8mq-cm-u-boot.dtsi | 8
> > arch/arm/dts/imx8mq-u-boot.dtsi | 8
>
> Probably can be done for 'imx8mn-bsh-smm-s2-u-boot-common.dtsi' as well.
>
Let us test.
I did not find time
Michael
>
> > 9 files changed, 36 insertions(+), 36 deletions(-)
> >
> > diff --git a/arch/arm/dts/imx8mm-u-boot.dtsi
> b/arch/arm/dts/imx8mm-u-boot.dtsi
> > index 5de55a2d80b..19a2da30f51 100644
> > --- a/arch/arm/dts/imx8mm-u-boot.dtsi
> > +++ b/arch/arm/dts/imx8mm-u-boot.dtsi
> > @@ -41,25 +41,25 @@
> >
> > imem_1d: blob-ext@1 {
> > filename = "lpddr4_pmu_train_1d_imem.bin";
> > - size = <0x8000>;
> > + align-end = <4>;
> > type = "blob-ext";
> > };
> >
> > dmem_1d: blob-ext@2 {
> > filename = "lpddr4_pmu_train_1d_dmem.bin";
> > - size = <0x4000>;
> > + align-end = <4>;
> > type = "blob-ext";
> > };
> >
> > imem_2d: blob-ext@3 {
> > filename = "lpddr4_pmu_train_2d_imem.bin";
> > - size = <0x8000>;
> > + align-end = <4>;
> > type = "blob-ext";
> > };
> >
> > dmem_2d: blob-ext@4 {
> > filename = "lpddr4_pmu_train_2d_dmem.bin";
> > - size = <0x4000>;
> > + align-end = <4>;
> > type = "blob-ext";
> > };
> > };
> > diff --git a/arch/arm/dts/imx8mn-beacon-kit-u-boot.dtsi
> b/arch/arm/dts/imx8mn-beacon-kit-u-boot.dtsi
> > index eb1dd8debba..e1740fa31a6 100644
> > --- a/arch/arm/dts/imx8mn-beacon-kit-u-boot.dtsi
> > +++ b/arch/arm/dts/imx8mn-beacon-kit-u-boot.dtsi
> > @@ -149,22 +149,22 @@
> >
> > blob_1: blob-ext@1 {
> > filename = "lpddr4_pmu_train_1d_imem.bin";
> > - size = <0x8000>;
> > + align-end = <4>;
> > };
> >
> > blob_2: blob-ext@2 {
> > filename = "lpddr4_pmu_train_1d_dmem.bin";
> > - size = <0x4000>;
> > + align-end = <4>;
> > };
> >
> > blob_3: blob-ext@3 {
> > filename = "lpddr4_pmu_train_2d_imem.bin";
> > - size = <0x8000>;
> > + align-end = <4>;
> > };
> >
> > blob_4: blob-ext@4 {
> > filename = "lpddr4_pmu_train_2d_dmem.bin";
> > - size = <0x4000>;
> > + align-end = <4>;
> > };
> > };
> >
> > diff --git a/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi
> b/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi
> > index 4d0ecb07d4f..1fe2d0fd507 100644
> > --- a/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi
> > +++ b/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi
> > @@ -157,22 +157,22 @@
> >
> > blob_1: blob-ext@1 {
> > filename = "ddr4_imem_1d_201810.bin";
> > - size = <0x8000>;
> > + align-end = <4>;
> > };
> >
> > blob_2: blob-ext@2 {
> > filename = "ddr4_dmem_1d_201810.bin";
> > - size = <0x4000>;
> > + align-end = <4>;
> > };
> >
> > blob_3: blob-ext@3 {
> > filename = "ddr4_imem_2d_201810.bin";
> > - size = <0x8000>;
> > + align-end = <4>;
> > };
> >
> > blob_4: blob-ext@4 {
> > filename = "ddr4_dmem_2d_201810.bin";
> > - size = <0x4000>;
> > + align-end = <4>;
> > };
> > };
> >
> > diff --git a/arch/arm/dts/imx8mn-evk-u-boot.dtsi
> b/arch/arm/dts/imx8mn-evk-u-boot.dtsi
> > index 3db46d4cbcb..4f6dcf307b2 100644
> > ---
[PATCH 3/3] riscv: qemu: Set kernel_comp_addr_r for compressed kernel
Set kernel_comp_addr_r and kernel_comp_size for compressed kernel. Adjust existing addresses for ramdisk, so that kernel_comp_addr_r comes before the ramdisk image, since the decompressed kernel size is known to us. This way we can allow big ramdisk image to be loaded. Signed-off-by: Bin Meng --- include/configs/qemu-riscv.h | 10 ++ 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/include/configs/qemu-riscv.h b/include/configs/qemu-riscv.h index 618c3b63d4..f462895fb5 100644 --- a/include/configs/qemu-riscv.h +++ b/include/configs/qemu-riscv.h @@ -54,10 +54,12 @@ "fdt_high=0x\0" \ "initrd_high=0x\0" \ "kernel_addr_r=0x8400\0" \ - "fdt_addr_r=0x8800\0" \ - "scriptaddr=0x8810\0" \ - "pxefile_addr_r=0x8820\0" \ - "ramdisk_addr_r=0x8830\0" \ + "kernel_comp_addr_r=0x8800\0" \ + "kernel_comp_size=0x400\0" \ + "fdt_addr_r=0x8c00\0" \ + "scriptaddr=0x8c10\0" \ + "pxefile_addr_r=0x8c20\0" \ + "ramdisk_addr_r=0x8c30\0" \ BOOTENV #endif -- 2.34.1
[PATCH 2/3] riscv: sifive: unleashed: Set kernel_comp_addr_r for compressed kernel
Set kernel_comp_addr_r and kernel_comp_size for compressed kernel. Adjust existing addresses for ramdisk, so that kernel_comp_addr_r comes before the ramdisk image, since the decompressed kernel size is known to us. This way we can allow big ramdisk image to be loaded. Update unleashed.rst to remove the manual environment configuration for compressed kernel boot. Signed-off-by: Bin Meng --- doc/board/sifive/unleashed.rst | 2 -- include/configs/sifive-unleashed.h | 10 ++ 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/doc/board/sifive/unleashed.rst b/doc/board/sifive/unleashed.rst index c8a62068a7..ce38b701d7 100644 --- a/doc/board/sifive/unleashed.rst +++ b/doc/board/sifive/unleashed.rst @@ -216,8 +216,6 @@ Or if you want to use a compressed kernel image file such as Image.gz 1.2 MiB/s done Bytes transferred = 4809458 (4962f2 hex) - =>setenv kernel_comp_addr_r 0x9000 - =>setenv kernel_comp_size 0x50 By this time, correct kernel image is loaded and required environment variables are set. You can proceed to load the ramdisk and device tree from the tftp server diff --git a/include/configs/sifive-unleashed.h b/include/configs/sifive-unleashed.h index 920f3140f6..96e2eb6798 100644 --- a/include/configs/sifive-unleashed.h +++ b/include/configs/sifive-unleashed.h @@ -61,12 +61,14 @@ "fdt_high=0x\0" \ "initrd_high=0x\0" \ "kernel_addr_r=0x8400\0" \ - "fdt_addr_r=0x8800\0" \ - "scriptaddr=0x8810\0" \ + "kernel_comp_addr_r=0x8800\0" \ + "kernel_comp_size=0x400\0" \ + "fdt_addr_r=0x8c00\0" \ + "scriptaddr=0x8c10\0" \ "script_offset_f=0x1fff000\0" \ "script_size_f=0x1000\0" \ - "pxefile_addr_r=0x8820\0" \ - "ramdisk_addr_r=0x8830\0" \ + "pxefile_addr_r=0x8c20\0" \ + "ramdisk_addr_r=0x8c30\0" \ "type_guid_gpt_loader1=" TYPE_GUID_LOADER1 "\0" \ "type_guid_gpt_loader2=" TYPE_GUID_LOADER2 "\0" \ "type_guid_gpt_system=" TYPE_GUID_SYSTEM "\0" \ -- 2.34.1
[PATCH 1/3] riscv: sifive: unmatched: Adjust for big ramdisk image
Move kernel_comp_addr_r to an address that comes before the ramdisk image, since the decompressed kernel size is known to us. This way we can allow big ramdisk image to be loaded. Signed-off-by: Bin Meng --- include/configs/sifive-unmatched.h | 10 +- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/include/configs/sifive-unmatched.h b/include/configs/sifive-unmatched.h index 087764666b..fa734a66be 100644 --- a/include/configs/sifive-unmatched.h +++ b/include/configs/sifive-unmatched.h @@ -56,12 +56,12 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "kernel_addr_r=0x8400\0" \ - "fdt_addr_r=0x8800\0" \ - "scriptaddr=0x8810\0" \ - "pxefile_addr_r=0x8820\0" \ - "ramdisk_addr_r=0x8830\0" \ - "kernel_comp_addr_r=0x9000\0" \ + "kernel_comp_addr_r=0x8800\0" \ "kernel_comp_size=0x400\0" \ + "fdt_addr_r=0x8c00\0" \ + "scriptaddr=0x8c10\0" \ + "pxefile_addr_r=0x8c20\0" \ + "ramdisk_addr_r=0x8c30\0" \ "type_guid_gpt_loader1=" TYPE_GUID_LOADER1 "\0" \ "type_guid_gpt_loader2=" TYPE_GUID_LOADER2 "\0" \ "type_guid_gpt_system=" TYPE_GUID_SYSTEM "\0" \ -- 2.34.1
[PATCH] bootmenu: fix bootmenu title handling
The commit a3d0aa87acbe ("bootmenu: update bootmenu_entry structure")
changes the bootmenu title type from char to u16(UTF16 string)
to support EFI based system. If EFI_LOADER is not enabled,
printf("%ls") is not supported, so bootmenu does not appear
correctly.
This commit switches the menu title type from "char" to "u16"
only when the EFI_LOADER is enabled.
Fixes: a3d0aa87acbe ("bootmenu: update bootmenu_entry structure")
Signed-off-by: Masahisa Kojima
---
cmd/bootmenu.c | 48
1 file changed, 32 insertions(+), 16 deletions(-)
diff --git a/cmd/bootmenu.c b/cmd/bootmenu.c
index 8859eebea5..e422e0b348 100644
--- a/cmd/bootmenu.c
+++ b/cmd/bootmenu.c
@@ -20,6 +20,20 @@
/* maximum bootmenu entries */
#define MAX_COUNT 99
+#if (CONFIG_IS_ENABLED(EFI_LOADER))
+#define TITLE_CHAR u16
+#define titlefmt "ls"
+#define TITLE_STRDUP u16_strdup
+#define TITLE_STRNCPY(d, s, l) utf8_utf16_strncpy(, s, l)
+#define TITLE_STR(x) u##x
+#else
+#define TITLE_CHAR char
+#define titlefmt "s"
+#define TITLE_STRDUP strdup
+#define TITLE_STRNCPY(d, s, l) strncpy(d, s, l)
+#define TITLE_STR(x) x
+#endif
+
/* maximal size of bootmenu env
* 9 = strlen("bootmenu_")
* 2 = strlen(MAX_COUNT)
@@ -43,7 +57,7 @@ enum boot_type {
struct bootmenu_entry {
unsigned short int num; /* unique number 0 .. MAX_COUNT */
char key[3];/* key identifier of number */
- u16 *title; /* title of entry */
+ TITLE_CHAR *title; /* title of entry */
char *command; /* hush command of entry */
enum boot_type type;/* boot type of entry */
u16 bootorder; /* order for each boot type */
@@ -76,7 +90,7 @@ static void bootmenu_print_entry(void *data)
if (reverse)
puts(ANSI_COLOR_REVERSE);
- printf("%ls", entry->title);
+ printf("%" titlefmt "", entry->title);
if (reverse)
puts(ANSI_COLOR_RESET);
@@ -170,7 +184,7 @@ static int prepare_bootmenu_entry(struct bootmenu_data
*menu,
struct bootmenu_entry *iter = *current;
while ((option = bootmenu_getoption(i))) {
- u16 *buf;
+ TITLE_CHAR *buf;
sep = strchr(option, '=');
if (!sep) {
@@ -183,13 +197,13 @@ static int prepare_bootmenu_entry(struct bootmenu_data
*menu,
return -ENOMEM;
len = sep-option;
- buf = calloc(1, (len + 1) * sizeof(u16));
+ buf = calloc(1, (len + 1) * sizeof(TITLE_CHAR));
entry->title = buf;
if (!entry->title) {
free(entry);
return -ENOMEM;
}
- utf8_utf16_strncpy(, option, len);
+ TITLE_STRNCPY(buf, option, len);
len = strlen(sep + 1);
entry->command = malloc(len + 1);
@@ -227,6 +241,7 @@ static int prepare_bootmenu_entry(struct bootmenu_data
*menu,
return 1;
}
+#if (CONFIG_IS_ENABLED(CMD_BOOTEFI_BOOTMGR))
/**
* prepare_uefi_bootorder_entry() - generate the uefi bootmenu entries
*
@@ -315,6 +330,7 @@ static int prepare_uefi_bootorder_entry(struct
bootmenu_data *menu,
return 1;
}
+#endif
static struct bootmenu_data *bootmenu_create(int delay)
{
@@ -341,13 +357,13 @@ static struct bootmenu_data *bootmenu_create(int delay)
if (ret < 0)
goto cleanup;
- if (IS_ENABLED(CONFIG_CMD_BOOTEFI_BOOTMGR)) {
- if (i < MAX_COUNT - 1) {
- ret = prepare_uefi_bootorder_entry(menu, , );
- if (ret < 0 && ret != -ENOENT)
- goto cleanup;
- }
+#if (CONFIG_IS_ENABLED(CMD_BOOTEFI_BOOTMGR))
+ if (i < MAX_COUNT - 1) {
+ ret = prepare_uefi_bootorder_entry(menu, , );
+ if (ret < 0 && ret != -ENOENT)
+ goto cleanup;
}
+#endif
/* Add U-Boot console entry at the end */
if (i <= MAX_COUNT - 1) {
@@ -357,9 +373,9 @@ static struct bootmenu_data *bootmenu_create(int delay)
/* Add Quit entry if entering U-Boot console is disabled */
if (IS_ENABLED(CONFIG_CMD_BOOTMENU_ENTER_UBOOT_CONSOLE))
- entry->title = u16_strdup(u"U-Boot console");
+ entry->title = TITLE_STRDUP(TITLE_STR("U-Boot
console"));
else
- entry->title = u16_strdup(u"Quit");
+ entry->title = TITLE_STRDUP(TITLE_STR("Quit"));
if (!entry->title) {
free(entry);
@@ -461,7 +477,7 @@ static enum bootmenu_ret bootmenu_show(int delay)
int cmd_ret;
int init = 0;
void *choice = NULL;
- u16 *title = NULL;
+ TITLE_CHAR *title = NULL;
Re: [PATCH v1] i2c: nuvoton: Add NPCM7xx i2c driver
Hi Heiko
Thanks for your reply.
and i have some explanation about command check.
in the npcm_i2c_xfer, it can support 1 or 2 nmsgs so need for function .
the test as below:
---
U-Boot>i2c probe 0x50
Valid chip addresses:nmsgs= 1
50
U-Boot>i2c md 50 11.2 4
nmsgs= 2
0011: 12 13 14 15
U-Boot>i2c mw 50 11.2 11
nmsgs= 1
U-Boot>i2c md 50 11.2 4
nmsgs= 2
0011: 11 13 14 15
U-Boot>
If you have any questions please let me know.
On Mon, May 23, 2022 at 4:42 PM Heiko Schocher wrote:
>
> Hello Jim,
>
> On 23.05.22 10:16, Jim Liu wrote:
> > Hi Heiko
> >
> > Thanks for your reply.
> > I will follow your suggestion to modify it for version 2.
> > and some explain and question as below:
> >
> > 1. while function will do the i2c recovery feature .
> > the function will break when toggle 27 times or SDA is high.
> >> + while (1) {
> >> + /* toggle SCL line */
> >> + writeb(SMBCST_TGSCL, >cst);
> >> +
> >> + udelay(20);
> >> + val = readb(>ctl3);
> >> + if (val & SMBCTL3_SDA_LVL)
> >> + break;
> >> + if (iter-- == 0)
> >> + break;
> >> + }
>
> Ah, yes, seems I was blind... sorry.
>
> > 2. npcm845 is our new bmc and we are on-going to push it to linux.
> > This link is our push status.
> > https://patchwork.ozlabs.org/project/linux-i2c/patch/20220517101142.28421-10-warp...@gmail.com/
>
> Ah, thanks!
>
> > may i keep this npcm845 compatible or remove it?
>
> If it gets accepted in linux, I am fine with it... ah I see:
>
> https://lore.kernel.org/lkml/20220517101142.28421-2-warp...@gmail.com/
>
> you add there the new compatible entry and have already a Reviewed-by
> from Rob, so I think this is fine to accept it in u-boot too.
>
> bye,
> Heiko
>
> > On Thu, May 19, 2022 at 12:48 PM Heiko Schocher wrote:
> >>
> >> Hello Jim,
> >>
> >> On 17.05.22 10:25, Jim Liu wrote:
> >>> Add Nuvoton BMC NPCM750 i2c driver
> >>>
> >>> Signed-off-by: Jim Liu
> >>> ---
> >>> drivers/i2c/Kconfig| 5 +
> >>> drivers/i2c/Makefile | 1 +
> >>> drivers/i2c/npcm-i2c.c | 632 +
> >>> 3 files changed, 638 insertions(+)
> >>> create mode 100644 drivers/i2c/npcm-i2c.c
> >>>
> >>> diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig
> >>> index d25c5736ef..7e113b289e 100644
> >>> --- a/drivers/i2c/Kconfig
> >>> +++ b/drivers/i2c/Kconfig
> >>> @@ -447,6 +447,11 @@ config SYS_I2C_NEXELL
> >>> have several I2C ports and all are provided, controlled by the
> >>> device tree.
> >>>
> >>> +config SYS_I2C_NPCM
> >>> + bool "Nuvoton NPCM I2C driver"
> >>> + help
> >>> + Support for Nuvoton I2C controller driver.
> >>> +
> >>> config SYS_I2C_OCORES
> >>> bool "ocores I2C driver"
> >>> depends on DM_I2C
> >>> diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile
> >>> index 9d41f379bb..7e046f809a 100644
> >>> --- a/drivers/i2c/Makefile
> >>> +++ b/drivers/i2c/Makefile
> >>> @@ -33,6 +33,7 @@ obj-$(CONFIG_SYS_I2C_MV) += mv_i2c.o
> >>> obj-$(CONFIG_SYS_I2C_MVTWSI) += mvtwsi.o
> >>> obj-$(CONFIG_SYS_I2C_MXC) += mxc_i2c.o
> >>> obj-$(CONFIG_SYS_I2C_NEXELL) += nx_i2c.o
> >>> +obj-$(CONFIG_SYS_I2C_NPCM) += npcm_i2c.o
> >>> obj-$(CONFIG_SYS_I2C_OCORES) += ocores_i2c.o
> >>> obj-$(CONFIG_SYS_I2C_OCTEON) += octeon_i2c.o
> >>> obj-$(CONFIG_SYS_I2C_OMAP24XX) += omap24xx_i2c.o
> >>> diff --git a/drivers/i2c/npcm-i2c.c b/drivers/i2c/npcm-i2c.c
> >>> new file mode 100644
> >>> index 00..5a066a164b
> >>> --- /dev/null
> >>> +++ b/drivers/i2c/npcm-i2c.c
> >>> @@ -0,0 +1,632 @@
> >>> +// SPDX-License-Identifier: GPL-2.0+
> >>> +/*
> >>> + * Copyright (c) 2021 Nuvoton Technology Corp.
> >>> + */
> >>> +
> >>> +#include
> >>> +#include
> >>> +#include
> >>> +#include
> >>> +#include
> >>> +#include
> >>> +
> >>> +#define I2C_FREQ_100K10
> >>> +#define NPCM_I2C_TIMEOUT_MS 10
> >>> +#define NPCM7XX_I2CSEGCTL_INIT_VAL 0x0333F000
> >>> +#define NPCM8XX_I2CSEGCTL_INIT_VAL 0x9333F000
> >>> +
> >>> +/* SCLFRQ min/max field values */
> >>> +#define SCLFRQ_MIN 10
> >>> +#define SCLFRQ_MAX 511
> >>> +
> >>> +/* SMBCTL1 */
> >>> +#define SMBCTL1_STARTBIT(0)
> >>> +#define SMBCTL1_STOP BIT(1)
> >>> +#define SMBCTL1_INTENBIT(2)
> >>> +#define SMBCTL1_ACK BIT(4)
> >>> +#define SMBCTL1_STASTRE BIT(7)
> >>> +
> >>> +/* SMBCTL2 */
> >>> +#define SMBCTL2_ENABLE BIT(0)
> >>> +
> >>> +/* SMBCTL3 */
> >>> +#define SMBCTL3_SCL_LVL BIT(7)
> >>> +#define SMBCTL3_SDA_LVL BIT(6)
> >>> +
> >>> +/* SMBCST */
> >>> +#define SMBCST_BBBIT(1)
> >>> +#define SMBCST_TGSCL BIT(5)
> >>> +
> >>> +/* SMBST */
> >>> +#define SMBST_XMIT BIT(0)
> >>> +#define SMBST_MASTER BIT(1)
> >>> +#define SMBST_STASTR
Re: U-Boot v2022.07-rc2 regression: Bootmenu is completely broken
On Tue, 24 May 2022 at 04:41, Pali Rohár wrote:
>
> On Monday 23 May 2022 15:29:04 Tom Rini wrote:
> > On Mon, May 23, 2022 at 09:27:37PM +0200, Pali Rohár wrote:
> > > Hello!
> > >
> > > U-Boot Bootmenu in git master branch is completely broken and does not
> > > work. You can test it e.g. in qemu version of nokia n900 (see rx51.rst).
> > >
> > > Bootmenu just prints garbage on both serial console and VGA video
> > > output and no option works.
> > >
> > > *** U-Boot Boot Menu ***
> > >
> > > A
> > > I
> > > E
> > > U
> > > U
> > >
> > >
> > > Press UP/DOWN to move, ENTER to select, ESC/CTRL+C to quit
> > >
> > > I bisected this issue and problem is in:
> > >
> > > a3d0aa87acbec4b983f54c24a6e7fd8e9e7b9728 is the first bad commit
> > > commit a3d0aa87acbec4b983f54c24a6e7fd8e9e7b9728
> > > Author: Masahisa Kojima
> > > Date: Thu Apr 28 17:09:41 2022 +0900
> > >
> > > bootmenu: update bootmenu_entry structure
This patch modified the menu title from char* to
u16*(UTF16 string) to support the EFI system.
But if the system does not support EFI, printf("%ls") does not
work correctly.
# I think currently only the first character is displayed.
I will send a fix.
Sorry for bothering you.
Thanks,
Masahisa Kojima
> > >
> > > This is a preparation for succeeding addition of uefi boot
> > > and distro boot menu entries into bootmenu.
> > > The bootmenu_entry title is updated to u16 string because
> > > uefi use u16 string. This commit also factors out the function
> > > to prepare the entries generated by "bootmenu_x" U-Boot environment
> > > variable.
> > >
> > > Signed-off-by: Masahisa Kojima
> > > Reviewed-by: Heinrich Schuchardt
> > >
> > > :04 04 37c91714b049be307521831c0470b3b6c8af2407
> > > b3e865073a46108cccbf4dc0b401789ef0b05a2e M cmd
> > >
> > > Before that commit Bootmenu works fine and on serial console prints:
> > >
> > > *** U-Boot Boot Menu ***
> > >
> > > Attached kernel
> > > Internal eMMC
> > > External SD card
> > > U-Boot boot order
> > > U-Boot console
> > >
> > >
> > > Press UP/DOWN to move, ENTER to select, ESC/CTRL+C to quit
> > >
> > >
> > > Could you please look at it and fix it?
> >
> > To be clear, the bootmenu stuff is or is not supposed to be tested with
> > the current rx51 test script?
>
> rx51 test script sets bootmenu timeout to 1s and just let bootmenu
> timeout. Timeout cause that default boot action is taken. Script does
> not interact with stdin / bootmenu.
>
> So... not selecting anything in bootmenu is working and hence rx51 test
> script did not complained.
[PULL] u-boot-socfpga/master
The following changes since commit c0a1409d21e7b342566dccb9cc1d38209aabc5ff: configs: Resync with savedefconfig (2022-05-23 13:56:21 -0400) are available in the Git repository at: git://git.denx.de/u-boot-socfpga.git master for you to fetch changes up to 1b05136a6ca8387175ca7bf1aa66a9c40a153cc2: arm: socfpga: Add the terasic de10-standard board (2022-05-23 21:28:07 +0200) Humberto Naves (1): arm: socfpga: Add the terasic de10-standard board arch/arm/dts/socfpga_cyclone5_de10_standard.dts | 86 +++ arch/arm/mach-socfpga/Kconfig | 7 + board/terasic/de10-standard/MAINTAINERS | 5 + board/terasic/de10-standard/Makefile| 6 + board/terasic/de10-standard/qts/iocsr_config.h | 659 + board/terasic/de10-standard/qts/pinmux_config.h | 218 board/terasic/de10-standard/qts/pll_config.h| 84 +++ board/terasic/de10-standard/qts/sdram_config.h | 344 board/terasic/de10-standard/socfpga.c | 5 + configs/socfpga_de10_standard_defconfig | 66 + include/configs/socfpga_de10_standard.h | 18 +++ 11 files changed, 1498 insertions(+) create mode 100644 arch/arm/dts/socfpga_cyclone5_de10_standard.dts create mode 100644 board/terasic/de10-standard/MAINTAINERS create mode 100644 board/terasic/de10-standard/Makefile create mode 100644 board/terasic/de10-standard/qts/iocsr_config.h create mode 100644 board/terasic/de10-standard/qts/pinmux_config.h create mode 100644 board/terasic/de10-standard/qts/pll_config.h create mode 100644 board/terasic/de10-standard/qts/sdram_config.h create mode 100644 board/terasic/de10-standard/socfpga.c create mode 100644 configs/socfpga_de10_standard_defconfig create mode 100644 include/configs/socfpga_de10_standard.h
[PATCH] ubifs: Fix reference count leak in ubifsumount
Original ubifs code was designed that after ubifs_umount() call it is
required to also call ubi_close_volume() which closes underlying UBI
volume. But U-Boot ubifs modification have not implemented it properly
which caused that ubifsumount command contains resource leak. It can be
observed by calling simple sequence of commands:
=> ubi part mtd2
ubi0: attaching mtd2
...
=> ubifsmount ubi0
=> ubifsumount
Unmounting UBIFS volume rootfs!
=> ubi detach
ubi0 error: ubi_detach_mtd_dev: ubi0 reference count 1, destroy anyway
ubi0: detaching mtd2
ubi0: mtd2 is detached
Fix this issue by calling ubi_close_volume() and mutex_unlock() in
directly in ubifs_umount() function before freeing U-Boot's global
ubifs_sb. And remove duplicate calls of these two functions in remaining
places. With this change ubifsumount command does not throw that error
anymore.
=> ubi part rootfs
ubi0: attaching mtd2
...
=> ubifsmount ubi0
=> ubifsumount
Unmounting UBIFS volume rootfs!
=> ubi detach
ubi0: detaching mtd2
ubi0: mtd2 is detached
Signed-off-by: Pali Rohár
---
fs/ubifs/super.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/fs/ubifs/super.c b/fs/ubifs/super.c
index e3a4c0bca270..7677dcc2a140 100644
--- a/fs/ubifs/super.c
+++ b/fs/ubifs/super.c
@@ -1757,6 +1757,8 @@ void ubifs_umount(struct ubifs_info *c)
kfree(c->bottom_up_buf);
ubifs_debugging_exit(c);
#ifdef __UBOOT__
+ ubi_close_volume(c->ubi);
+ mutex_unlock(>umount_mutex);
/* Finally free U-Boot's global copy of superblock */
if (ubifs_sb != NULL) {
free(ubifs_sb->s_fs_info);
@@ -2058,9 +2060,9 @@ static void ubifs_put_super(struct super_block *sb)
ubifs_umount(c);
#ifndef __UBOOT__
bdi_destroy(>bdi);
-#endif
ubi_close_volume(c->ubi);
mutex_unlock(>umount_mutex);
+#endif
}
#endif
@@ -2328,13 +2330,13 @@ static int ubifs_fill_super(struct super_block *sb,
void *data, int silent)
out_umount:
ubifs_umount(c);
out_unlock:
- mutex_unlock(>umount_mutex);
#ifndef __UBOOT__
+ mutex_unlock(>umount_mutex);
out_bdi:
bdi_destroy(>bdi);
out_close:
-#endif
ubi_close_volume(c->ubi);
+#endif
out:
return err;
}
--
2.20.1
Re: [PATCH V4 7/8] arm: dts: imx8m: shrink ddr firmware size to actual file size
On 20/05/2022 17:10, Peng Fan (OSS) wrote:
> From: Peng Fan
>
> After we switch to use BINMAN_SYMBOLS, there is no need to pad
> the file size to 0x8000 and 0x4000. After we use BINMAN_SYMBOLS,
> the u-boot-spl-ddr.bin shrink about 36KB with i.MX8MP-EVK.
>
> Tested-by: Tim Harvey #imx8m[m,n,p]-venice
> Signed-off-by: Peng Fan
> ---
> arch/arm/dts/imx8mm-u-boot.dtsi | 8
> arch/arm/dts/imx8mn-beacon-kit-u-boot.dtsi | 8
> arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi | 8
> arch/arm/dts/imx8mn-evk-u-boot.dtsi | 8
> arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi | 8
> arch/arm/dts/imx8mn-venice-u-boot.dtsi | 8
> arch/arm/dts/imx8mp-u-boot.dtsi | 8
> arch/arm/dts/imx8mq-cm-u-boot.dtsi | 8
> arch/arm/dts/imx8mq-u-boot.dtsi | 8
Probably can be done for 'imx8mn-bsh-smm-s2-u-boot-common.dtsi' as well.
> 9 files changed, 36 insertions(+), 36 deletions(-)
>
> diff --git a/arch/arm/dts/imx8mm-u-boot.dtsi b/arch/arm/dts/imx8mm-u-boot.dtsi
> index 5de55a2d80b..19a2da30f51 100644
> --- a/arch/arm/dts/imx8mm-u-boot.dtsi
> +++ b/arch/arm/dts/imx8mm-u-boot.dtsi
> @@ -41,25 +41,25 @@
>
> imem_1d: blob-ext@1 {
> filename = "lpddr4_pmu_train_1d_imem.bin";
> - size = <0x8000>;
> + align-end = <4>;
> type = "blob-ext";
> };
>
> dmem_1d: blob-ext@2 {
> filename = "lpddr4_pmu_train_1d_dmem.bin";
> - size = <0x4000>;
> + align-end = <4>;
> type = "blob-ext";
> };
>
> imem_2d: blob-ext@3 {
> filename = "lpddr4_pmu_train_2d_imem.bin";
> - size = <0x8000>;
> + align-end = <4>;
> type = "blob-ext";
> };
>
> dmem_2d: blob-ext@4 {
> filename = "lpddr4_pmu_train_2d_dmem.bin";
> - size = <0x4000>;
> + align-end = <4>;
> type = "blob-ext";
> };
> };
> diff --git a/arch/arm/dts/imx8mn-beacon-kit-u-boot.dtsi
> b/arch/arm/dts/imx8mn-beacon-kit-u-boot.dtsi
> index eb1dd8debba..e1740fa31a6 100644
> --- a/arch/arm/dts/imx8mn-beacon-kit-u-boot.dtsi
> +++ b/arch/arm/dts/imx8mn-beacon-kit-u-boot.dtsi
> @@ -149,22 +149,22 @@
>
> blob_1: blob-ext@1 {
> filename = "lpddr4_pmu_train_1d_imem.bin";
> - size = <0x8000>;
> + align-end = <4>;
> };
>
> blob_2: blob-ext@2 {
> filename = "lpddr4_pmu_train_1d_dmem.bin";
> - size = <0x4000>;
> + align-end = <4>;
> };
>
> blob_3: blob-ext@3 {
> filename = "lpddr4_pmu_train_2d_imem.bin";
> - size = <0x8000>;
> + align-end = <4>;
> };
>
> blob_4: blob-ext@4 {
> filename = "lpddr4_pmu_train_2d_dmem.bin";
> - size = <0x4000>;
> + align-end = <4>;
> };
> };
>
> diff --git a/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi
> b/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi
> index 4d0ecb07d4f..1fe2d0fd507 100644
> --- a/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi
> +++ b/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi
> @@ -157,22 +157,22 @@
>
> blob_1: blob-ext@1 {
> filename = "ddr4_imem_1d_201810.bin";
> - size = <0x8000>;
> + align-end = <4>;
> };
>
> blob_2: blob-ext@2 {
> filename = "ddr4_dmem_1d_201810.bin";
> - size = <0x4000>;
> + align-end = <4>;
> };
>
> blob_3: blob-ext@3 {
> filename = "ddr4_imem_2d_201810.bin";
> - size = <0x8000>;
> + align-end = <4>;
> };
>
> blob_4: blob-ext@4 {
> filename = "ddr4_dmem_2d_201810.bin";
> - size = <0x4000>;
> + align-end = <4>;
> };
> };
>
> diff --git a/arch/arm/dts/imx8mn-evk-u-boot.dtsi
> b/arch/arm/dts/imx8mn-evk-u-boot.dtsi
> index 3db46d4cbcb..4f6dcf307b2 100644
> --- a/arch/arm/dts/imx8mn-evk-u-boot.dtsi
> +++ b/arch/arm/dts/imx8mn-evk-u-boot.dtsi
> @@ -38,22 +38,22 @@
>
> blob_1: blob-ext@1 {
> filename = "lpddr4_pmu_train_1d_imem.bin";
> - size = <0x8000>;
> + align-end = <4>;
> };
>
> blob_2:
Re: [PATCH V4 2/8] arm: dts: imx8m: update binman ddr firmware node name
On 23/05/2022 10:01, Peng Fan (OSS) wrote:
>> Subject: Re: [PATCH V4 2/8] arm: dts: imx8m: update binman ddr firmware
>> node name
>>
>> On 20/05/2022 17:10, Peng Fan (OSS) wrote:
>>> From: Peng Fan
>>>
>>> We are migrating to use BINMAN SYMBOLS, the current name is not a
>>> valid binman type, so update to use blob-ext@[1,2,3,4].
>>>
>>> Tested-by: Tim Harvey #imx8m[m,n,p]-venice
>>> Signed-off-by: Peng Fan
>>> ---
>>> arch/arm/dts/imx8mm-u-boot.dtsi | 8
>>> arch/arm/dts/imx8mn-bsh-smm-s2-u-boot-common.dtsi | 4 ++--
>>> arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi | 8
>>> arch/arm/dts/imx8mn-venice-u-boot.dtsi| 8
>>> arch/arm/dts/imx8mq-u-boot.dtsi | 8
>>> 5 files changed, 18 insertions(+), 18 deletions(-)
>>
>> I think descriptive entry names are better in general, so I prefer the old
>> names
>> to a bunch of 'blob-ext's. Symbol resolution is done using the entry names
>> anyway, I don't see why this change would be necessary.
>
> Binman understand blob-ext, it not understand 1d-imem. If keep id-imem, or
> else,
> need to add several new binman types which I would not prefer.
It would work as long as you set `type = "blob-ext";` in the entry block.
Please test this diff on top of your series:
diff --git a/arch/arm/dts/imx8mm-u-boot.dtsi b/arch/arm/dts/imx8mm-u-boot.dtsi
index 19a2da30f512..8c48678625d9 100644
--- a/arch/arm/dts/imx8mm-u-boot.dtsi
+++ b/arch/arm/dts/imx8mm-u-boot.dtsi
@@ -39,25 +39,25 @@
filename = "u-boot-spl.bin";
};
- imem_1d: blob-ext@1 {
+ ddr-1d-imem-fw {
filename = "lpddr4_pmu_train_1d_imem.bin";
align-end = <4>;
type = "blob-ext";
};
- dmem_1d: blob-ext@2 {
+ ddr-1d-dmem-fw {
filename = "lpddr4_pmu_train_1d_dmem.bin";
align-end = <4>;
type = "blob-ext";
};
- imem_2d: blob-ext@3 {
+ ddr-2d-imem-fw {
filename = "lpddr4_pmu_train_2d_imem.bin";
align-end = <4>;
type = "blob-ext";
};
- dmem_2d: blob-ext@4 {
+ ddr-2d-dmem-fw {
filename = "lpddr4_pmu_train_2d_dmem.bin";
align-end = <4>;
type = "blob-ext";
diff --git a/arch/arm/dts/imx8mn-beacon-kit-u-boot.dtsi
b/arch/arm/dts/imx8mn-beacon-kit-u-boot.dtsi
index 0f89c8f677fa..dc7afc05e8f9 100644
--- a/arch/arm/dts/imx8mn-beacon-kit-u-boot.dtsi
+++ b/arch/arm/dts/imx8mn-beacon-kit-u-boot.dtsi
@@ -143,24 +143,28 @@
align-end = <4>;
};
- blob_1: blob-ext@1 {
+ ddr-1d-imem-fw {
filename = "lpddr4_pmu_train_1d_imem.bin";
align-end = <4>;
+ type = "blob-ext";
};
- blob_2: blob-ext@2 {
+ ddr-1d-dmem-fw {
filename = "lpddr4_pmu_train_1d_dmem.bin";
align-end = <4>;
+ type = "blob-ext";
};
- blob_3: blob-ext@3 {
+ ddr-2d-imem-fw {
filename = "lpddr4_pmu_train_2d_imem.bin";
align-end = <4>;
+ type = "blob-ext";
};
- blob_4: blob-ext@4 {
+ ddr-2d-dmem-fw {
filename = "lpddr4_pmu_train_2d_dmem.bin";
align-end = <4>;
+ type = "blob-ext";
};
};
diff --git a/arch/arm/dts/imx8mn-bsh-smm-s2-u-boot-common.dtsi
b/arch/arm/dts/imx8mn-bsh-smm-s2-u-boot-common.dtsi
index 5a52b73d7e9c..dc4cec250efa 100644
--- a/arch/arm/dts/imx8mn-bsh-smm-s2-u-boot-common.dtsi
+++ b/arch/arm/dts/imx8mn-bsh-smm-s2-u-boot-common.dtsi
@@ -111,13 +111,13 @@
filename = "u-boot-spl.bin";
};
- imem_1d: blob-ext@1 {
+ ddr-1d-imem-fw {
filename = "ddr3_imem_1d.bin";
size = <0x8000>;
type = "blob-ext";
};
- dmem_1d: blob-ext@2 {
+ ddr-1d-dmem-fw {
filename = "ddr3_dmem_1d.bin";
size = <0x4000>;
type = "blob-ext";
diff --git a/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi
b/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi
index 6f3d5cfe3c18..3f02b4aac135 100644
--- a/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi
+++ b/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi
@@ -151,24 +151,28 @@
align-end = <4>;
};
-
Re: [PATCH V4 1/8] spl: guard u_boot_any with X86
On 23/05/2022 17:10, Tom Rini wrote: > On Mon, May 23, 2022 at 06:28:44AM +, Peng Fan (OSS) wrote: >>> Subject: Re: [PATCH V4 1/8] spl: guard u_boot_any with X86 >>> >>> Why are you mentioning LTO in the commit message? When I read the >>> commit message it sounds like you're saying the problem is that LTO doesn't >>> like how this symbol is handled, but if LTO was disabled, everything would >>> be >>> fine. If it's not LTO-related, please re-word the message instead. >> >> Sorry, I could reword the commit message, but currently I have no better >> idea to address the issue unless use X86 as a guard in the code as this >> patch does. If you agree the code in this patch, I could reword commit msg >> and send v5. > > Well, lets see what Alper says in the other part of the thread. I'd > really like to solve this not work around this. But I'll take > documenting the problem for the person that has X86 && LTO as good > enough for the moment. Alternatively, I think we can decide that all binman symbols are optional, and not raise an error when we can't find a value for them. They are de-facto optional anyway: people can use the non-binman-image build artifacts (which binman doesn't update wrt. symbols), thus the code that uses binman symbols should assume their values can be missing.
Re: [PATCH V4 1/8] spl: guard u_boot_any with X86
On 22/05/2022 17:50, Tom Rini wrote: > On Sun, May 22, 2022 at 04:56:08PM +0300, Alper Nebi Yasak wrote: >> It looks like we should be able to change things in common/spl/spl.c to: >> >> #if CONFIG_IS_ENABLED(BINMAN_SYMBOLS) >> /* See spl.h for information about this */ >> binman_sym_declare_optional(ulong, u_boot_any, image_pos); >> binman_sym_declare_optional(ulong, u_boot_any, size); >> #endif >> >> which would mark the symbol as 'weak' and turn the error into a warning >> on the binman side. But that is somehow being undone by LTO. > > So, looking at binman_sym_declare_optional we tell the linker that it's > weak and might even be unused. LTO gets very aggressive about finding > things that aren't used in the resulting binary and discarding them. > Typically we have the problem of a function that is used but it's hard > for LTO to see it, so we give it the "used" attribute. But for > something we're already saying is "unused" this would be wrong. So why > do we mark things as unused here? I assume it's marked weak as it could > be overridden at link time by a definition elsewhere. I don't know, but the GCC manual says marking things 'unused' will suppress a warning if the variable is actually unused. I guess binman symbols may become unused due to some other config options being unset, and it's done for those cases? I think the optional symbols are marked weak just to signal the python side that they are optional. If I understand it right, binman: 1. Packs an image using the finalized 'spl/u-boot-spl.bin' 2. Figures out the image-pos and size values of every entry 3. Inspects the 'spl/u-boot-spl' ELF file for declared binman symbols 4. Raises an error if any non-'weak' symbol's value is undetermined 5. Updates the u-boot-spl.bin (in memory) with the calculated values 6. Recreates the final image based on that updated bin file.
[PATCH] ubifs: Add missing dependency on GZIP
GZIP option can be manually de-selected when UBIFS is enabled. This cause following compile error because ubifs calls gzip functions. /tmp/ccxVrh2c.ltrans1.ltrans.o: in function `gzip_decompress.lto_priv.566': :(.text+0x768): undefined reference to `zunzip' collect2: error: ld returned 1 exit status make: *** [Makefile:1813: u-boot] Error 1 So add missing dependency on GZIP. Signed-off-by: Pali Rohár --- cmd/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/cmd/Kconfig b/cmd/Kconfig index 69c1814d24af..50e60fd4d5b6 100644 --- a/cmd/Kconfig +++ b/cmd/Kconfig @@ -2562,6 +2562,7 @@ config CMD_UBIFS depends on CMD_UBI default y if CMD_UBI select LZO + select GZIP help UBIFS is a file system for flash devices which works on top of UBI. -- 2.20.1
[ANN] U-Boot v2022.07-rc3 released
Hey all, It's release day and so here's v2022.07-rc3. I've grabbed all of the outstanding regression fixes I know of. I'm expecting a patch shortly to fix the use case of FIT images and device trees as generated most commonly by OpenEmbedded. Further, I'll grab the series from Bin to fix pytest console time-outs. Next, I'll be grabbing the change for CVE-2022-30767 shortly. For anything else, please reach out. In terms of a changelog, git log --merges v2022.07-rc2..v2022.07-rc3 contains what I've pulled but as always, better PR messages and tags will provide better results here. I plan to open the -next branch after -rc4, which I believe tracks with my usual frequency. So we're now looking at regular releases every other Monday, and with final release on July 4th, 2022. Thanks all! -- Tom signature.asc Description: PGP signature
Re: U-Boot v2022.07-rc2 regression: Bootmenu is completely broken
On Monday 23 May 2022 15:29:04 Tom Rini wrote: > On Mon, May 23, 2022 at 09:27:37PM +0200, Pali Rohár wrote: > > Hello! > > > > U-Boot Bootmenu in git master branch is completely broken and does not > > work. You can test it e.g. in qemu version of nokia n900 (see rx51.rst). > > > > Bootmenu just prints garbage on both serial console and VGA video > > output and no option works. > > > > *** U-Boot Boot Menu *** > > > > A > > I > > E > > U > > U > > > > > > Press UP/DOWN to move, ENTER to select, ESC/CTRL+C to quit > > > > I bisected this issue and problem is in: > > > > a3d0aa87acbec4b983f54c24a6e7fd8e9e7b9728 is the first bad commit > > commit a3d0aa87acbec4b983f54c24a6e7fd8e9e7b9728 > > Author: Masahisa Kojima > > Date: Thu Apr 28 17:09:41 2022 +0900 > > > > bootmenu: update bootmenu_entry structure > > > > This is a preparation for succeeding addition of uefi boot > > and distro boot menu entries into bootmenu. > > The bootmenu_entry title is updated to u16 string because > > uefi use u16 string. This commit also factors out the function > > to prepare the entries generated by "bootmenu_x" U-Boot environment > > variable. > > > > Signed-off-by: Masahisa Kojima > > Reviewed-by: Heinrich Schuchardt > > > > :04 04 37c91714b049be307521831c0470b3b6c8af2407 > > b3e865073a46108cccbf4dc0b401789ef0b05a2e M cmd > > > > Before that commit Bootmenu works fine and on serial console prints: > > > > *** U-Boot Boot Menu *** > > > > Attached kernel > > Internal eMMC > > External SD card > > U-Boot boot order > > U-Boot console > > > > > > Press UP/DOWN to move, ENTER to select, ESC/CTRL+C to quit > > > > > > Could you please look at it and fix it? > > To be clear, the bootmenu stuff is or is not supposed to be tested with > the current rx51 test script? rx51 test script sets bootmenu timeout to 1s and just let bootmenu timeout. Timeout cause that default boot action is taken. Script does not interact with stdin / bootmenu. So... not selecting anything in bootmenu is working and hence rx51 test script did not complained.
[PATCH 2/2] rockchip: Add option to prevent booting on power plug-in
From: Chris Morgan
For Rockchip boards with the all rk8xx series PMICs (excluding the
rk808), it is sometimes desirable to not boot whenever the device is
plugged in. An example would be for the Odroid Go Advance.
This provides a configurable option to check the PMIC says it was
powered because of a plug-in event. If the value is 1 and this option
is selected, the device shuts down shortly after printing a message
to console stating the reason why it's shutting down. Powering up the
board with the power button is not affected.
This patch parallels the work done in the following patch series:
https://lore.kernel.org/u-boot/20220121133732.2397273-1-andre.przyw...@arm.com/
Signed-off-by: Chris Morgan
---
arch/arm/mach-rockchip/Kconfig | 10 +
drivers/power/pmic/rk8xx.c | 37 ++
include/power/rk8xx_pmic.h | 3 +++
3 files changed, 50 insertions(+)
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index 18aff5480b..c561a77e6a 100644
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -361,6 +361,16 @@ config ROCKCHIP_BOOT_MODE_REG
The Soc will enter to different boot mode(defined in
asm/arch-rockchip/boot_mode.h)
according to the value from this register.
+config ROCKCHIP_RK8XX_DISABLE_BOOT_ON_POWERON
+ bool "Disable device boot on power plug-in"
+ depends on PMIC_RK8XX
+ default n
+ ---help---
+ Say Y here to prevent the device from booting up because of a plug-in
+ event. When set, the device will boot briefly to determine why it was
+ powered on, and if it was determined because of a plug-in event
+ instead of a button press event it will shut back off.
+
config ROCKCHIP_STIMER
bool "Rockchip STIMER support"
default y
diff --git a/drivers/power/pmic/rk8xx.c b/drivers/power/pmic/rk8xx.c
index 1ffbecc02a..b59675a10e 100644
--- a/drivers/power/pmic/rk8xx.c
+++ b/drivers/power/pmic/rk8xx.c
@@ -51,6 +51,41 @@ U_BOOT_DRIVER(rk8xx_sysreset) = {
.ops= _sysreset_ops,
};
+void rk8xx_off_for_plugin(struct udevice *dev)
+/* In the event of a plug-in and the appropriate option has been
+ * selected, we simply shutdown instead of continue the normal boot
+ * process. Please note the rk808 is not supported as it doesn't
+ * have the appropriate register.
+ */
+{
+ struct rk8xx_priv *priv = dev_get_priv(dev);
+ bool plug_in = 0;
+
+ switch (priv->variant) {
+ case RK805_ID:
+ case RK816_ID:
+ case RK818_ID:
+ plug_in = pmic_reg_read(dev, RK8XX_ON_SOURCE) &
RK8XX_ON_PLUG_IN;
+ if (plug_in) {
+ printf("Power Off due to plug-in event\n");
+ pmic_clrsetbits(dev, REG_DEVCTRL, 0, BIT(0));
+ }
+ break;
+ case RK809_ID:
+ case RK817_ID:
+ plug_in = pmic_reg_read(dev, RK817_ON_SOURCE) &
RK8XX_ON_PLUG_IN;
+ if (plug_in) {
+ printf("Power Off due to plug-in event\n");
+ pmic_clrsetbits(dev, RK817_REG_SYS_CFG3, 0,
+ BIT(0));
+ }
+ break;
+ default:
+ printf("PMIC RK%x: Cannot read boot reason.\n",
+ priv->variant);
+ }
+}
+
static struct reg_data rk817_init_reg[] = {
/* enable the under-voltage protection,
* the under-voltage protection will shutdown the LDO3 and reset the PMIC
@@ -211,6 +246,8 @@ static int rk8xx_probe(struct udevice *dev)
pmic_reg_read(dev, on_source),
pmic_reg_read(dev, off_source));
printf("\n");
+ if (CONFIG_IS_ENABLED(ROCKCHIP_RK8XX_DISABLE_BOOT_ON_POWERON))
+ rk8xx_off_for_plugin(dev);
return 0;
}
diff --git a/include/power/rk8xx_pmic.h b/include/power/rk8xx_pmic.h
index 8ff0af35c5..3cbfc02195 100644
--- a/include/power/rk8xx_pmic.h
+++ b/include/power/rk8xx_pmic.h
@@ -214,6 +214,9 @@ enum {
#define RK817_ON_SOURCE0xf5
#define RK817_OFF_SOURCE 0xf6
+#define RK8XX_ON_PWRON BIT(7)
+#define RK8XX_ON_PLUG_IN BIT(6)
+
struct reg_data {
u8 reg;
u8 val;
--
2.25.1
[PATCH 1/2] power: pmic: rk8xx: Support sysreset shutdown method
From: Chris Morgan
Add support for sysreset shutdown for this PMIC. The values were pulled
from the various datasheets, but for now it has only been tested on
the rk817 (for an Odroid Go Advance).
Signed-off-by: Chris Morgan
---
drivers/power/pmic/rk8xx.c | 50 +-
1 file changed, 49 insertions(+), 1 deletion(-)
diff --git a/drivers/power/pmic/rk8xx.c b/drivers/power/pmic/rk8xx.c
index 5f442fea68..1ffbecc02a 100644
--- a/drivers/power/pmic/rk8xx.c
+++ b/drivers/power/pmic/rk8xx.c
@@ -6,10 +6,50 @@
#include
#include
+#include
#include
#include
#include
#include
+#include
+
+static int rk8xx_sysreset_request(struct udevice *dev, enum sysreset_t type)
+{
+ struct rk8xx_priv *priv = dev_get_priv(dev->parent);
+
+ if (type != SYSRESET_POWER_OFF)
+ return -EPROTONOSUPPORT;
+
+ switch (priv->variant) {
+ case RK805_ID:
+ case RK808_ID:
+ case RK816_ID:
+ case RK818_ID:
+ pmic_clrsetbits(dev->parent, REG_DEVCTRL, 0, BIT(0));
+ break;
+ case RK809_ID:
+ case RK817_ID:
+ pmic_clrsetbits(dev->parent, RK817_REG_SYS_CFG3, 0,
+ BIT(0));
+ break;
+ default:
+ printf("Unknown PMIC RK%x: Cannot shutdown\n",
+ priv->variant);
+ return -EPROTONOSUPPORT;
+ };
+
+ return -EINPROGRESS;
+}
+
+static struct sysreset_ops rk8xx_sysreset_ops = {
+ .request= rk8xx_sysreset_request,
+};
+
+U_BOOT_DRIVER(rk8xx_sysreset) = {
+ .name = "rk8xx_sysreset",
+ .id = UCLASS_SYSRESET,
+ .ops= _sysreset_ops,
+};
static struct reg_data rk817_init_reg[] = {
/* enable the under-voltage protection,
@@ -61,7 +101,7 @@ static int rk8xx_read(struct udevice *dev, uint reg, uint8_t
*buff, int len)
static int rk8xx_bind(struct udevice *dev)
{
ofnode regulators_node;
- int children;
+ int children, ret;
regulators_node = dev_read_subnode(dev, "regulators");
if (!ofnode_valid(regulators_node)) {
@@ -72,6 +112,14 @@ static int rk8xx_bind(struct udevice *dev)
debug("%s: '%s' - found regulators subnode\n", __func__, dev->name);
+ if (CONFIG_IS_ENABLED(SYSRESET)) {
+ ret = device_bind_driver_to_node(dev, "rk8xx_sysreset",
+"rk8xx_sysreset",
+dev_ofnode(dev), NULL);
+ if (ret)
+ return ret;
+ }
+
children = pmic_bind_children(dev, regulators_node, pmic_children_info);
if (!children)
debug("%s: %s - no child found\n", __func__, dev->name);
--
2.25.1
[PATCH 0/2] Rockchip: Add option to prevent boot on plug-in
From: Chris Morgan Sometimes it is desirable to prevent a board from automatically booting as soon as the power cable is plugged in. For boards with an rk8xx PMIC, (excluding the rk808) we can actually query the power up source. Chris Morgan (2): power: pmic: rk8xx: Support sysreset shutdown method rockchip: Add option to prevent booting on power plug-in arch/arm/mach-rockchip/Kconfig | 10 drivers/power/pmic/rk8xx.c | 92 +- include/power/rk8xx_pmic.h | 3 ++ 3 files changed, 104 insertions(+), 1 deletion(-) -- 2.25.1
Re: U-Boot v2022.07-rc2 regression: Bootmenu is completely broken
On Mon, May 23, 2022 at 09:27:37PM +0200, Pali Rohár wrote: > Hello! > > U-Boot Bootmenu in git master branch is completely broken and does not > work. You can test it e.g. in qemu version of nokia n900 (see rx51.rst). > > Bootmenu just prints garbage on both serial console and VGA video > output and no option works. > > *** U-Boot Boot Menu *** > > A > I > E > U > U > > > Press UP/DOWN to move, ENTER to select, ESC/CTRL+C to quit > > I bisected this issue and problem is in: > > a3d0aa87acbec4b983f54c24a6e7fd8e9e7b9728 is the first bad commit > commit a3d0aa87acbec4b983f54c24a6e7fd8e9e7b9728 > Author: Masahisa Kojima > Date: Thu Apr 28 17:09:41 2022 +0900 > > bootmenu: update bootmenu_entry structure > > This is a preparation for succeeding addition of uefi boot > and distro boot menu entries into bootmenu. > The bootmenu_entry title is updated to u16 string because > uefi use u16 string. This commit also factors out the function > to prepare the entries generated by "bootmenu_x" U-Boot environment > variable. > > Signed-off-by: Masahisa Kojima > Reviewed-by: Heinrich Schuchardt > > :04 04 37c91714b049be307521831c0470b3b6c8af2407 > b3e865073a46108cccbf4dc0b401789ef0b05a2e M cmd > > Before that commit Bootmenu works fine and on serial console prints: > > *** U-Boot Boot Menu *** > > Attached kernel > Internal eMMC > External SD card > U-Boot boot order > U-Boot console > > > Press UP/DOWN to move, ENTER to select, ESC/CTRL+C to quit > > > Could you please look at it and fix it? To be clear, the bootmenu stuff is or is not supposed to be tested with the current rx51 test script? -- Tom signature.asc Description: PGP signature
U-Boot v2022.07-rc2 regression: Bootmenu is completely broken
Hello! U-Boot Bootmenu in git master branch is completely broken and does not work. You can test it e.g. in qemu version of nokia n900 (see rx51.rst). Bootmenu just prints garbage on both serial console and VGA video output and no option works. *** U-Boot Boot Menu *** A I E U U Press UP/DOWN to move, ENTER to select, ESC/CTRL+C to quit I bisected this issue and problem is in: a3d0aa87acbec4b983f54c24a6e7fd8e9e7b9728 is the first bad commit commit a3d0aa87acbec4b983f54c24a6e7fd8e9e7b9728 Author: Masahisa Kojima Date: Thu Apr 28 17:09:41 2022 +0900 bootmenu: update bootmenu_entry structure This is a preparation for succeeding addition of uefi boot and distro boot menu entries into bootmenu. The bootmenu_entry title is updated to u16 string because uefi use u16 string. This commit also factors out the function to prepare the entries generated by "bootmenu_x" U-Boot environment variable. Signed-off-by: Masahisa Kojima Reviewed-by: Heinrich Schuchardt :04 04 37c91714b049be307521831c0470b3b6c8af2407 b3e865073a46108cccbf4dc0b401789ef0b05a2e M cmd Before that commit Bootmenu works fine and on serial console prints: *** U-Boot Boot Menu *** Attached kernel Internal eMMC External SD card U-Boot boot order U-Boot console Press UP/DOWN to move, ENTER to select, ESC/CTRL+C to quit Could you please look at it and fix it?
[PATCH 4/4] Convert CONFIG_SPL_COMMON_INIT_DDR to Kconfig
This converts the following to Kconfig:
CONFIG_SPL_COMMON_INIT_DDR
Signed-off-by: Tom Rini
---
README | 4
board/freescale/p1010rdb/tlb.c | 3 +--
board/freescale/p1_p2_rdb_pc/tlb.c | 3 +--
configs/P1010RDB-PA_36BIT_NAND_defconfig | 1 +
configs/P1010RDB-PA_36BIT_NOR_defconfig | 2 ++
configs/P1010RDB-PA_36BIT_SDCARD_defconfig | 1 +
configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig | 1 +
configs/P1010RDB-PA_NAND_defconfig | 1 +
configs/P1010RDB-PA_NOR_defconfig| 2 ++
configs/P1010RDB-PA_SDCARD_defconfig | 1 +
configs/P1010RDB-PA_SPIFLASH_defconfig | 1 +
configs/P1010RDB-PB_36BIT_NAND_defconfig | 1 +
configs/P1010RDB-PB_36BIT_NOR_defconfig | 2 ++
configs/P1010RDB-PB_36BIT_SDCARD_defconfig | 1 +
configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig | 1 +
configs/P1010RDB-PB_NAND_defconfig | 1 +
configs/P1010RDB-PB_NOR_defconfig| 2 ++
configs/P1010RDB-PB_SDCARD_defconfig | 1 +
configs/P1010RDB-PB_SPIFLASH_defconfig | 1 +
configs/P1020RDB-PC_36BIT_NAND_defconfig | 1 +
configs/P1020RDB-PC_36BIT_SDCARD_defconfig | 1 +
configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig | 1 +
configs/P1020RDB-PC_36BIT_defconfig | 2 ++
configs/P1020RDB-PC_NAND_defconfig | 1 +
configs/P1020RDB-PC_SDCARD_defconfig | 1 +
configs/P1020RDB-PC_SPIFLASH_defconfig | 1 +
configs/P1020RDB-PC_defconfig| 2 ++
configs/P1020RDB-PD_NAND_defconfig | 1 +
configs/P1020RDB-PD_SDCARD_defconfig | 1 +
configs/P1020RDB-PD_SPIFLASH_defconfig | 1 +
configs/P1020RDB-PD_defconfig| 2 ++
configs/P2020RDB-PC_36BIT_NAND_defconfig | 1 +
configs/P2020RDB-PC_36BIT_SDCARD_defconfig | 1 +
configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig | 1 +
configs/P2020RDB-PC_36BIT_defconfig | 2 ++
configs/P2020RDB-PC_NAND_defconfig | 1 +
configs/P2020RDB-PC_SDCARD_defconfig | 1 +
configs/P2020RDB-PC_SPIFLASH_defconfig | 1 +
configs/P2020RDB-PC_defconfig| 2 ++
drivers/ddr/fsl/Kconfig | 14 ++
include/configs/P1010RDB.h | 7 ---
include/configs/T102xRDB.h | 1 -
include/configs/T104xRDB.h | 1 -
include/configs/T208xQDS.h | 1 -
include/configs/T208xRDB.h | 1 -
include/configs/T4240RDB.h | 2 --
include/configs/p1_p2_rdb_pc.h | 7 ---
scripts/config_whitelist.txt | 1 -
48 files changed, 61 insertions(+), 29 deletions(-)
diff --git a/README b/README
index 9f1561b92ca3..d6ff909e9a44 100644
--- a/README
+++ b/README
@@ -1712,10 +1712,6 @@ The following options need to be configured:
Support for a lightweight UBI (fastmap) scanner and
loader
- CONFIG_SPL_COMMON_INIT_DDR
- Set for common ddr init with serial presence detect in
- SPL binary.
-
CONFIG_SYS_NAND_5_ADDR_CYCLE, CONFIG_SYS_NAND_PAGE_COUNT,
CONFIG_SYS_NAND_PAGE_SIZE, CONFIG_SYS_NAND_OOBSIZE,
CONFIG_SYS_NAND_BLOCK_SIZE, CONFIG_SYS_NAND_BAD_BLOCK_POS,
diff --git a/board/freescale/p1010rdb/tlb.c b/board/freescale/p1010rdb/tlb.c
index 04faefe994d0..7992666e9307 100644
--- a/board/freescale/p1010rdb/tlb.c
+++ b/board/freescale/p1010rdb/tlb.c
@@ -72,8 +72,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 7, BOOKE_PAGESZ_1M, 1),
-#if defined(CONFIG_SYS_RAMBOOT) || \
- (defined(CONFIG_SPL) && !defined(CONFIG_SPL_COMMON_INIT_DDR))
+#if defined(CONFIG_SYS_RAMBOOT) || !CONFIG_IS_ENABLED(COMMON_INIT_DDR)
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
0, 8, BOOKE_PAGESZ_1G, 1),
diff --git a/board/freescale/p1_p2_rdb_pc/tlb.c
b/board/freescale/p1_p2_rdb_pc/tlb.c
index 5931ec650bd8..6ded38ac683e 100644
--- a/board/freescale/p1_p2_rdb_pc/tlb.c
+++ b/board/freescale/p1_p2_rdb_pc/tlb.c
@@ -77,8 +77,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
0, 7, BOOKE_PAGESZ_1M, 1),
#endif
-#if defined(CONFIG_SYS_RAMBOOT) || \
- (defined(CONFIG_SPL) && !defined(CONFIG_SPL_COMMON_INIT_DDR))
+#if defined(CONFIG_SYS_RAMBOOT) || !CONFIG_IS_ENABLED(COMMON_INIT_DDR)
/* **M** - 1G DDR for eSDHC/eSPI/NAND boot */
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
diff --git a/configs/P1010RDB-PA_36BIT_NAND_defconfig
b/configs/P1010RDB-PA_36BIT_NAND_defconfig
index 6b8c424c13b9..f6426f0c171c 100644
--- a/configs/P1010RDB-PA_36BIT_NAND_defconfig
+++
[PATCH 3/4] ppc / layerscape: Clean up CONFIG_SYS_CCSR_DO_NOT_RELOCATE usage
A number of PowerPC platforms define this, for SPL. To move this to Kconfig, it needs to be CONFIG_SPL_SYS_CCSR_DO_NOT_RELOCATE, so use CONFIG_IS_ENABLED() to check for usage. A number of layerscape platforms bring this logic from PowerPC, but only need a small part of it, for the fman driver. Remove their unused portion at least. Signed-off-by: Tom Rini --- README| 4 .../asm/arch-fsl-layerscape/immap_lsch2.h | 19 --- .../include/asm/arch-ls102xa/immap_ls102xa.h | 18 -- common/spl/Kconfig| 11 +++ configs/P1010RDB-PA_36BIT_NAND_defconfig | 1 + configs/P1010RDB-PA_36BIT_NOR_defconfig | 1 + configs/P1010RDB-PA_36BIT_SDCARD_defconfig| 1 + configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig | 1 + configs/P1010RDB-PA_NAND_defconfig| 1 + configs/P1010RDB-PA_NOR_defconfig | 1 + configs/P1010RDB-PA_SDCARD_defconfig | 1 + configs/P1010RDB-PA_SPIFLASH_defconfig| 1 + configs/P1010RDB-PB_36BIT_NAND_defconfig | 1 + configs/P1010RDB-PB_36BIT_NOR_defconfig | 1 + configs/P1010RDB-PB_36BIT_SDCARD_defconfig| 1 + configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig | 1 + configs/P1010RDB-PB_NAND_defconfig| 1 + configs/P1010RDB-PB_NOR_defconfig | 1 + configs/P1010RDB-PB_SDCARD_defconfig | 1 + configs/P1010RDB-PB_SPIFLASH_defconfig| 1 + configs/P1020RDB-PC_36BIT_NAND_defconfig | 1 + configs/P1020RDB-PC_36BIT_SDCARD_defconfig| 1 + configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig | 1 + configs/P1020RDB-PC_36BIT_defconfig | 1 + configs/P1020RDB-PC_NAND_defconfig| 1 + configs/P1020RDB-PC_SDCARD_defconfig | 1 + configs/P1020RDB-PC_SPIFLASH_defconfig| 1 + configs/P1020RDB-PC_defconfig | 1 + configs/P1020RDB-PD_NAND_defconfig| 1 + configs/P1020RDB-PD_SDCARD_defconfig | 1 + configs/P1020RDB-PD_SPIFLASH_defconfig| 1 + configs/P1020RDB-PD_defconfig | 1 + configs/P2020RDB-PC_36BIT_NAND_defconfig | 1 + configs/P2020RDB-PC_36BIT_SDCARD_defconfig| 1 + configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig | 1 + configs/P2020RDB-PC_36BIT_defconfig | 1 + configs/P2020RDB-PC_NAND_defconfig| 1 + configs/P2020RDB-PC_SDCARD_defconfig | 1 + configs/P2020RDB-PC_SPIFLASH_defconfig| 1 + configs/P2020RDB-PC_defconfig | 1 + configs/T1024RDB_NAND_defconfig | 1 + configs/T1024RDB_SDCARD_defconfig | 1 + configs/T1024RDB_SPIFLASH_defconfig | 1 + configs/T1042D4RDB_NAND_defconfig | 1 + configs/T1042D4RDB_SDCARD_defconfig | 1 + configs/T1042D4RDB_SPIFLASH_defconfig | 1 + configs/T2080QDS_NAND_defconfig | 1 + configs/T2080QDS_SDCARD_defconfig | 1 + configs/T2080QDS_SPIFLASH_defconfig | 1 + configs/T2080RDB_NAND_defconfig | 1 + configs/T2080RDB_SDCARD_defconfig | 1 + configs/T2080RDB_SPIFLASH_defconfig | 1 + configs/T2080RDB_revD_NAND_defconfig | 1 + configs/T2080RDB_revD_SDCARD_defconfig| 1 + configs/T2080RDB_revD_SPIFLASH_defconfig | 1 + configs/T4240RDB_SDCARD_defconfig | 1 + include/configs/P1010RDB.h| 5 - include/configs/T102xRDB.h| 3 --- include/configs/T104xRDB.h| 3 --- include/configs/T208xQDS.h| 3 --- include/configs/T208xRDB.h| 3 --- include/configs/T4240RDB.h| 3 --- include/configs/p1_p2_rdb_pc.h| 6 -- include/mpc85xx.h | 4 ++-- 64 files changed, 65 insertions(+), 69 deletions(-) diff --git a/README b/README index efec01a8aae8..9f1561b92ca3 100644 --- a/README +++ b/README @@ -2117,10 +2117,6 @@ Low Level (hardware related) configuration options: used in assembly code, so it must not contain typecasts or integer size suffixes (e.g. "ULL"). -- CONFIG_SYS_CCSR_DO_NOT_RELOCATE: - If this macro is defined, then CONFIG_SYS_CCSRBAR_PHYS will be - forced to a value that ensures that CCSR is not relocated. - - CONFIG_SYS_IMMR: Physical address of the Internal Memory. DO NOT CHANGE unless you know exactly what you're doing! (11-4) [MPC8xx systems only] diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h index 06adf669390f..61db1738f33a 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h @@ -142,25 +142,6 @@ #define TP_CLUSTER_INIT_MASK0x003f /* initiator mask */
[PATCH 2/4] Convert CONFIG_SPL_SYS_MALLOC_SIMPLE to Kconfig
This converts the following to Kconfig: CONFIG_SPL_SYS_MALLOC_SIMPLE The problem here is that a few platforms have been doing: #ifdef CONFIG_SPL_BUILD #define CONFIG_SYS_MALLOC_SIMPLE #endif instead of defining CONFIG_SPL_SYS_MALLOC_SIMPLE directly. Correct this and update the documentation in a few places to match usage. Signed-off-by: Tom Rini --- configs/clearfog_defconfig | 1 + configs/db-88f6720_defconfig| 1 + configs/db-88f6820-amc_defconfig| 1 + configs/db-88f6820-gp_defconfig | 1 + configs/db-mv784mp-gp_defconfig | 1 + configs/ds414_defconfig | 1 + configs/helios4_defconfig | 1 + configs/maxbcm_defconfig| 1 + configs/theadorable_debug_defconfig | 1 + configs/x530_defconfig | 1 + doc/develop/driver-model/design.rst | 2 +- drivers/core/Kconfig| 6 +++--- include/configs/clearfog.h | 4 include/configs/controlcenterdc.h | 4 include/configs/db-88f6720.h| 4 include/configs/db-88f6820-amc.h| 4 include/configs/db-88f6820-gp.h | 4 include/configs/db-mv784mp-gp.h | 4 include/configs/ds414.h | 4 include/configs/helios4.h | 4 include/configs/maxbcm.h| 4 include/configs/theadorable.h | 4 include/configs/x530.h | 4 23 files changed, 14 insertions(+), 48 deletions(-) diff --git a/configs/clearfog_defconfig b/configs/clearfog_defconfig index c26ee5bfacac..7f4ecc3f3ee4 100644 --- a/configs/clearfog_defconfig +++ b/configs/clearfog_defconfig @@ -26,6 +26,7 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_MAX_SIZE=0x22fd0 CONFIG_SPL_BSS_MAX_SIZE=0x4000 +CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_I2C=y CONFIG_SYS_MAXARGS=32 CONFIG_CMD_TLV_EEPROM=y diff --git a/configs/db-88f6720_defconfig b/configs/db-88f6720_defconfig index 8d48428c2257..5970e750a837 100644 --- a/configs/db-88f6720_defconfig +++ b/configs/db-88f6720_defconfig @@ -25,6 +25,7 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_MAX_SIZE=0x1ffd0 CONFIG_SPL_BSS_MAX_SIZE=0x4000 +CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_I2C=y CONFIG_SYS_MAXARGS=32 CONFIG_CMD_I2C=y diff --git a/configs/db-88f6820-amc_defconfig b/configs/db-88f6820-amc_defconfig index 7a208ad819b1..aebc1f75fa62 100644 --- a/configs/db-88f6820-amc_defconfig +++ b/configs/db-88f6820-amc_defconfig @@ -26,6 +26,7 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_MAX_SIZE=0x22fd0 CONFIG_SPL_BSS_MAX_SIZE=0x4000 +CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_I2C=y CONFIG_SYS_MAXARGS=96 # CONFIG_CMD_FLASH is not set diff --git a/configs/db-88f6820-gp_defconfig b/configs/db-88f6820-gp_defconfig index 339558545da5..934b36ae05f9 100644 --- a/configs/db-88f6820-gp_defconfig +++ b/configs/db-88f6820-gp_defconfig @@ -25,6 +25,7 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_MAX_SIZE=0x22fd0 CONFIG_SPL_BSS_MAX_SIZE=0x4000 +CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_I2C=y CONFIG_SYS_MAXARGS=32 CONFIG_CMD_I2C=y diff --git a/configs/db-mv784mp-gp_defconfig b/configs/db-mv784mp-gp_defconfig index 22f76eba174c..b8444e1ab366 100644 --- a/configs/db-mv784mp-gp_defconfig +++ b/configs/db-mv784mp-gp_defconfig @@ -25,6 +25,7 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_MAX_SIZE=0x1bfd0 CONFIG_SPL_BSS_MAX_SIZE=0x4000 +CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_I2C=y CONFIG_SYS_MAXARGS=32 # CONFIG_CMD_FLASH is not set diff --git a/configs/ds414_defconfig b/configs/ds414_defconfig index 8e1f69d636b2..7c25cce8ff5e 100644 --- a/configs/ds414_defconfig +++ b/configs/ds414_defconfig @@ -33,6 +33,7 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_MISC_INIT_R=y CONFIG_SPL_MAX_SIZE=0x1bfd0 CONFIG_SPL_BSS_MAX_SIZE=0x4000 +CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_I2C=y CONFIG_SYS_MAXARGS=32 # CONFIG_CMD_FLASH is not set diff --git a/configs/helios4_defconfig b/configs/helios4_defconfig index 30d65acbee99..6988e9bf0d4d 100644 --- a/configs/helios4_defconfig +++ b/configs/helios4_defconfig @@ -26,6 +26,7 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_MAX_SIZE=0x22fd0 CONFIG_SPL_BSS_MAX_SIZE=0x4000 +CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_I2C=y CONFIG_SYS_MAXARGS=32 CONFIG_CMD_TLV_EEPROM=y diff --git a/configs/maxbcm_defconfig b/configs/maxbcm_defconfig index 442af9cb3826..ba0e2089f559 100644 --- a/configs/maxbcm_defconfig +++ b/configs/maxbcm_defconfig @@ -24,6 +24,7 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_MAX_SIZE=0x1bfd0 CONFIG_SPL_BSS_MAX_SIZE=0x4000 +CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_I2C=y CONFIG_SYS_MAXARGS=32 CONFIG_CMD_I2C=y diff --git a/configs/theadorable_debug_defconfig b/configs/theadorable_debug_defconfig index c5bd8909c914..b6444b244082 100644 --- a/configs/theadorable_debug_defconfig +++
[PATCH v3 7/8] net: add MV88E61xx DSA driver
Add a DSA driver for the MV88E61xx compatible GbE Ethernet switches. Cc: Marek Behún Cc: Vladimir Oltean Signed-off-by: Tim Harvey Reviewed-by: Vladimir Oltean --- v3: - Added Vladimir's rb tag v2: - rebase on v2022.07-rc1 (use ofnode_get_phy_node) - remove unused commented out fields from struct - remove unused PORT_MASK macro - remove phy from priv struct name - refactor code from original drivers/net/phy/mv88e61xx with suggestions from review to consolidate some functions into mv88e61xx_dsa_port_enable - remove unecessary skiping of disabling of CPU port - remove unecessary dev_set_parent_priv - remove unnecessary static init flag - replace debug with a dev_warn if switch device-id unsupported - remove unnecessary xmit/recv functions as we rely on the fact that only a single port is active instead of mangling packets --- drivers/net/Kconfig | 7 + drivers/net/Makefile| 1 + drivers/net/mv88e61xx.c | 843 3 files changed, 851 insertions(+) create mode 100644 drivers/net/mv88e61xx.c diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 7fe0e00649cf..edb1a0898986 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -433,6 +433,13 @@ config LPC32XX_ETH depends on ARCH_LPC32XX default y +config MV88E61XX + bool "Marvell MV88E61xx GbE switch DSA driver" + depends on DM_DSA && DM_MDIO + help + This driver implements a DSA switch driver for the MV88E61xx family + of GbE switches using the MDIO interface + config MVGBE bool "Marvell Orion5x/Kirkwood network interface support" depends on ARCH_KIRKWOOD || ARCH_ORION5X diff --git a/drivers/net/Makefile b/drivers/net/Makefile index 69fb3bbbf7cb..36b4c279430a 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -59,6 +59,7 @@ obj-$(CONFIG_MEDIATEK_ETH) += mtk_eth.o obj-$(CONFIG_MPC8XX_FEC) += mpc8xx_fec.o obj-$(CONFIG_MT7620_ETH) += mt7620-eth.o obj-$(CONFIG_MT7628_ETH) += mt7628-eth.o +obj-$(CONFIG_MV88E61XX) += mv88e61xx.o obj-$(CONFIG_MVGBE) += mvgbe.o obj-$(CONFIG_MVMDIO) += mvmdio.o obj-$(CONFIG_MVNETA) += mvneta.o diff --git a/drivers/net/mv88e61xx.c b/drivers/net/mv88e61xx.c new file mode 100644 index ..514835bf03b9 --- /dev/null +++ b/drivers/net/mv88e61xx.c @@ -0,0 +1,843 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2022 + * Gateworks Corporation + * Tim Harvey + * + * (C) Copyright 2015 + * Elecsys Corporation + * Kevin Smith + * + * Original driver: + * (C) Copyright 2009 + * Marvell Semiconductor + * Prafulla Wadaskar + */ + +/* + * DSA driver for mv88e61xx ethernet switches. + * + * This driver configures the mv88e61xx for basic use as a DSA switch. + * + * This driver was adapted from drivers/net/phy/mv88e61xx and tested + * on the mv88e6176 via an SGMII interface. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Device addresses */ +#define DEVADDR_PHY(p) (p) +#define DEVADDR_SERDES 0x0F + +/* SMI indirection registers for multichip addressing mode */ +#define SMI_CMD_REG0x00 +#define SMI_DATA_REG 0x01 + +/* Global registers */ +#define GLOBAL1_STATUS 0x00 +#define GLOBAL1_CTRL 0x04 +#define GLOBAL1_MON_CTRL 0x1A + +/* Global 2 registers */ +#define GLOBAL2_REG_PHY_CMD0x18 +#define GLOBAL2_REG_PHY_DATA 0x19 +#define GLOBAL2_REG_SCRATCH0x1A + +/* Port registers */ +#define PORT_REG_STATUS0x00 +#define PORT_REG_PHYS_CTRL 0x01 +#define PORT_REG_SWITCH_ID 0x03 +#define PORT_REG_CTRL 0x04 +#define PORT_REG_VLAN_MAP 0x06 +#define PORT_REG_VLAN_ID 0x07 +#define PORT_REG_LED_CTRL 0x16 + +/* Phy registers */ +#define PHY_REG_CTRL1 0x10 +#define PHY_REG_STATUS10x11 +#define PHY_REG_PAGE 0x16 + +/* Serdes registers */ +#define SERDES_REG_CTRL_1 0x10 + +/* Phy page numbers */ +#define PHY_PAGE_COPPER0 +#define PHY_PAGE_SERDES1 + +/* Register fields */ +#define GLOBAL1_CTRL_SWRESET BIT(15) + +#define GLOBAL1_MON_CTRL_CPUDEST_SHIFT 4 +#define GLOBAL1_MON_CTRL_CPUDEST_WIDTH 4 + +#define PORT_REG_STATUS_SPEED_SHIFT8 +#define PORT_REG_STATUS_SPEED_10 0 +#define PORT_REG_STATUS_SPEED_100 1 +#define PORT_REG_STATUS_SPEED_1000 2 + +#define PORT_REG_STATUS_CMODE_MASK 0xF +#define PORT_REG_STATUS_CMODE_100BASE_X0x8 +#define PORT_REG_STATUS_CMODE_1000BASE_X 0x9 +#define PORT_REG_STATUS_CMODE_SGMII0xa + +#define PORT_REG_PHYS_CTRL_RGMII_DELAY_RXCLK BIT(15) +#define PORT_REG_PHYS_CTRL_RGMII_DELAY_TXCLK BIT(14) +#define
[PATCH v3 8/8] board: gw_ventana: enable MV88E61XX DSA support
Add MV88E61XX DSA support:
- update dt: U-Boot dsa driver requires different device-tree syntax
than the linux driver in order to link the dsa ports to the mdio bus.
- update defconfig
- replace mv88e61xx_hw_reset weak override with board_phy_config support
for mv88e61xx configuration that is outside the scope of the DSA driver
Signed-off-by: Tim Harvey
---
v3:
- move mdio's mdio@0 subnode
v2: no changes
---
arch/arm/dts/imx6qdl-gw5904.dtsi| 41
board/gateworks/gw_ventana/gw_ventana.c | 50 +
configs/gwventana_gw5904_defconfig | 7 ++--
3 files changed, 62 insertions(+), 36 deletions(-)
diff --git a/arch/arm/dts/imx6qdl-gw5904.dtsi b/arch/arm/dts/imx6qdl-gw5904.dtsi
index 286c7a9924c2..1b2f70d1ccb2 100644
--- a/arch/arm/dts/imx6qdl-gw5904.dtsi
+++ b/arch/arm/dts/imx6qdl-gw5904.dtsi
@@ -219,6 +219,33 @@
compatible = "marvell,mv88e6085";
reg = <0>;
+ mdios {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mdio@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ sw_phy0: ethernet-phy@0 {
+ reg = <0x0>;
+ };
+
+ sw_phy1: ethernet-phy@1 {
+ reg = <0x1>;
+ };
+
+ sw_phy2: ethernet-phy@2 {
+ reg = <0x2>;
+ };
+
+ sw_phy3: ethernet-phy@3 {
+ reg = <0x3>;
+ };
+ };
+ };
+
ports {
#address-cells = <1>;
#size-cells = <0>;
@@ -226,27 +253,41 @@
port@0 {
reg = <0>;
label = "lan4";
+ phy-mode = "internal";
+ phy-handle = <_phy0>;
};
port@1 {
reg = <1>;
label = "lan3";
+ phy-mode = "internal";
+ phy-handle = <_phy1>;
};
port@2 {
reg = <2>;
label = "lan2";
+ phy-mode = "internal";
+ phy-handle = <_phy2>;
};
port@3 {
reg = <3>;
label = "lan1";
+ phy-mode = "internal";
+ phy-handle = <_phy3>;
};
port@5 {
reg = <5>;
label = "cpu";
ethernet = <>;
+ phy-mode = "rgmii-id";
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
};
};
};
diff --git a/board/gateworks/gw_ventana/gw_ventana.c
b/board/gateworks/gw_ventana/gw_ventana.c
index c06630a66b66..bef3f7ef0d2b 100644
--- a/board/gateworks/gw_ventana/gw_ventana.c
+++ b/board/gateworks/gw_ventana/gw_ventana.c
@@ -68,44 +68,30 @@ int board_phy_config(struct phy_device *phydev)
phy_write(phydev, MDIO_DEVAD_NONE, 14, val);
}
+ /* Fixed PHY: for GW5904/GW5909 this is Marvell 88E6176 GbE Switch */
+ else if (phydev->phy_id == 0xa5a55a5a &&
+((board_type == GW5904) || (board_type == GW5909))) {
+ struct mii_dev *bus = miiphy_get_dev_by_name("mdio");
+
+ puts("MV88E61XX ");
+ /* GPIO[0] output CLK125 for RGMII_REFCLK */
+ bus->write(bus, 0x1c, 0, 0x1a, (1 << 15) | (0x62 << 8) | 0xfe);
+ bus->write(bus, 0x1c, 0, 0x1a, (1 << 15) | (0x68 << 8) | 7);
+
+ /* Port 0-3 LED configuration:
[PATCH v3 6/8] net: fec: add support for DM_MDIO
Add support for DM_MDIO by registering a UCLASS_MDIO driver and
attempting to use it. This is necessary if wanting to use a DSA
driver for example hanging off of the FEC MAC.
Care is taken to fallback to non DM_MDIO mii bus as several boards define
DM_MDIO without having the proper device-tree configuration necessary
such as an mdio subnode, a phy-mode prop, and either a valid phy-handle
prop or fixed-phy subnode which will cause dm_eth_phy_connect() to fail.
Signed-off-by: Tim Harvey
---
v2:
- fix fallback mechanism for legacy dt's that do not have phy-handle
and mdio subnode
---
drivers/net/fec_mxc.c | 90 ++-
1 file changed, 88 insertions(+), 2 deletions(-)
diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
index a623a5c45e4d..9553699e3306 100644
--- a/drivers/net/fec_mxc.c
+++ b/drivers/net/fec_mxc.c
@@ -30,6 +30,8 @@
#include
#include
#include
+#include
+#include
#include "fec_mxc.h"
#include
@@ -1025,6 +1027,81 @@ struct mii_dev *fec_get_miibus(ulong base_addr, int
dev_id)
return bus;
}
+#ifdef CONFIG_DM_MDIO
+struct dm_fec_mdio_priv {
+ struct ethernet_regs *regs;
+};
+
+static int dm_fec_mdio_read(struct udevice *dev, int addr, int devad, int reg)
+{
+ struct dm_fec_mdio_priv *priv = dev_get_priv(dev);
+
+ return fec_mdio_read(priv->regs, addr, reg);
+}
+
+static int dm_fec_mdio_write(struct udevice *dev, int addr, int devad, int
reg, u16 data)
+{
+ struct dm_fec_mdio_priv *priv = dev_get_priv(dev);
+
+ return fec_mdio_write(priv->regs, addr, reg, data);
+}
+
+static const struct mdio_ops dm_fec_mdio_ops = {
+ .read = dm_fec_mdio_read,
+ .write = dm_fec_mdio_write,
+};
+
+static int dm_fec_mdio_probe(struct udevice *dev)
+{
+ struct dm_fec_mdio_priv *priv = dev_get_priv(dev);
+
+ priv->regs = (struct ethernet_regs
*)ofnode_get_addr(dev_ofnode(dev->parent));
+
+ return 0;
+}
+
+U_BOOT_DRIVER(fec_mdio) = {
+ .name = "fec_mdio",
+ .id = UCLASS_MDIO,
+ .probe = dm_fec_mdio_probe,
+ .ops= _fec_mdio_ops,
+ .priv_auto = sizeof(struct dm_fec_mdio_priv),
+};
+
+static int dm_fec_bind_mdio(struct udevice *dev)
+{
+ struct udevice *mdiodev;
+ const char *name;
+ ofnode mdio;
+ int ret = -ENODEV;
+
+ /* for a UCLASS_MDIO driver we need to bind and probe manually
+* for an internal MDIO bus that has no dt compatible of its own
+*/
+ ofnode_for_each_subnode(mdio, dev_ofnode(dev)) {
+ name = ofnode_get_name(mdio);
+
+ if (strcmp(name, "mdio"))
+ continue;
+
+ ret = device_bind_driver_to_node(dev, "fec_mdio",
+name, mdio, );
+ if (ret) {
+ printf("%s bind %s failed: %d\n", __func__, name, ret);
+ break;
+ }
+
+ /* need to probe it as there is no compatible to do so */
+ ret = uclass_get_device_by_ofnode(UCLASS_MDIO, mdio, );
+ if (!ret)
+ return 0;
+ printf("%s probe %s failed: %d\n", __func__, name, ret);
+ }
+
+ return ret;
+}
+#endif
+
static int fecmxc_read_rom_hwaddr(struct udevice *dev)
{
struct fec_priv *priv = dev_get_priv(dev);
@@ -1088,7 +1165,7 @@ static int device_get_phy_addr(struct fec_priv *priv,
struct udevice *dev)
static int fec_phy_init(struct fec_priv *priv, struct udevice *dev)
{
- struct phy_device *phydev;
+ struct phy_device *phydev = NULL;
int addr;
addr = device_get_phy_addr(priv, dev);
@@ -1096,7 +1173,10 @@ static int fec_phy_init(struct fec_priv *priv, struct
udevice *dev)
addr = CONFIG_FEC_MXC_PHYADDR;
#endif
- phydev = phy_connect(priv->bus, addr, dev, priv->interface);
+ if (IS_ENABLED(CONFIG_DM_MDIO))
+ phydev = dm_eth_phy_connect(dev);
+ if (!phydev)
+ phydev = phy_connect(priv->bus, addr, dev, priv->interface);
if (!phydev)
return -ENODEV;
@@ -1227,6 +1307,12 @@ static int fecmxc_probe(struct udevice *dev)
priv->dev_id = dev_seq(dev);
+ if (IS_ENABLED(CONFIG_DM_MDIO)) {
+ ret = dm_fec_bind_mdio(dev);
+ if (ret && ret != -ENODEV)
+ return ret;
+ }
+
#ifdef CONFIG_DM_ETH_PHY
bus = eth_phy_get_mdio_bus(dev);
#endif
--
2.17.1
[PATCH v3 4/8] net: dsa: allow rcv() and xmit() to be optional
Allow rcv() and xmit() dsa driver ops to be optional in case a driver
does not care to mangle a packet as in U-Boot only one network port is
enabled at a time and thus no packet mangling is necessary.
Suggested-by: Vladimir Oltean
Signed-off-by: Tim Harvey
Reviewed-by: Vladimir Oltean
---
v3:
- added Vladimir's rb tag
v2: new patch
---
net/dsa-uclass.c | 27 ++-
1 file changed, 18 insertions(+), 9 deletions(-)
diff --git a/net/dsa-uclass.c b/net/dsa-uclass.c
index b3033c97aa63..f82217e0d7a7 100644
--- a/net/dsa-uclass.c
+++ b/net/dsa-uclass.c
@@ -131,16 +131,14 @@ static void dsa_port_stop(struct udevice *pdev)
* We copy the frame to a stack buffer where we have reserved headroom and
* tailroom space. Headroom and tailroom are set to 0.
*/
-static int dsa_port_send(struct udevice *pdev, void *packet, int length)
+static int dsa_port_mangle_packet(struct udevice *pdev, void *packet, int
length)
{
+ struct dsa_port_pdata *port_pdata = dev_get_parent_plat(pdev);
struct udevice *dev = dev_get_parent(pdev);
struct dsa_priv *priv = dev_get_uclass_priv(dev);
int head = priv->headroom, tail = priv->tailroom;
- struct udevice *master = dsa_get_master(dev);
struct dsa_ops *ops = dsa_get_ops(dev);
uchar dsa_packet_tmp[PKTSIZE_ALIGN];
- struct dsa_port_pdata *port_pdata;
- int err;
if (length + head + tail > PKTSIZE_ALIGN)
return -EINVAL;
@@ -152,10 +150,21 @@ static int dsa_port_send(struct udevice *pdev, void
*packet, int length)
/* copy back to preserve original buffer alignment */
memcpy(packet, dsa_packet_tmp, length);
- port_pdata = dev_get_parent_plat(pdev);
- err = ops->xmit(dev, port_pdata->index, packet, length);
- if (err)
- return err;
+ return ops->xmit(dev, port_pdata->index, packet, length);
+}
+
+static int dsa_port_send(struct udevice *pdev, void *packet, int length)
+{
+ struct udevice *dev = dev_get_parent(pdev);
+ struct udevice *master = dsa_get_master(dev);
+ struct dsa_ops *ops = dsa_get_ops(dev);
+ int err;
+
+ if (ops->xmit) {
+ err = dsa_port_mangle_packet(pdev, packet, length);
+ if (err)
+ return err;
+ }
return eth_get_ops(master)->send(master, packet, length);
}
@@ -172,7 +181,7 @@ static int dsa_port_recv(struct udevice *pdev, int flags,
uchar **packetp)
int length, port_index, err;
length = eth_get_ops(master)->recv(master, flags, packetp);
- if (length <= 0)
+ if (length <= 0 || !ops->rcv)
return length;
/*
--
2.17.1
[PATCH v3 5/8] net: ksz9477: remove unnecessary xmit and recv functions
Remove the unnecessary xmit and recv functions.
Signed-off-by: Tim Harvey
Reviewed-by: Vladimir Oltean
---
v3:
- added Vladimir's rb tag
v2: new patch
---
drivers/net/ksz9477.c | 23 ---
1 file changed, 23 deletions(-)
diff --git a/drivers/net/ksz9477.c b/drivers/net/ksz9477.c
index ed8f1895cb12..fb5c76c600be 100644
--- a/drivers/net/ksz9477.c
+++ b/drivers/net/ksz9477.c
@@ -62,7 +62,6 @@
struct ksz_dsa_priv {
struct udevice *dev;
- int active_port;
};
static inline int ksz_read8(struct udevice *dev, u32 reg, u8 *val)
@@ -382,9 +381,6 @@ static int ksz_port_enable(struct udevice *dev, int port,
struct phy_device *phy
data8 |= SW_START;
ksz_write8(priv->dev, REG_SW_OPERATION, data8);
- /* keep track of current enabled non-cpu port */
- priv->active_port = port;
-
return 0;
}
@@ -413,28 +409,9 @@ static void ksz_port_disable(struct udevice *dev, int
port, struct phy_device *p
*/
}
-static int ksz_xmit(struct udevice *dev, int port, void *packet, int length)
-{
- dev_dbg(dev, "%s P%d %d\n", __func__, port + 1, length);
-
- return 0;
-}
-
-static int ksz_recv(struct udevice *dev, int *port, void *packet, int length)
-{
- struct ksz_dsa_priv *priv = dev_get_priv(dev);
-
- dev_dbg(dev, "%s P%d %d\n", __func__, priv->active_port + 1, length);
- *port = priv->active_port;
-
- return 0;
-};
-
static const struct dsa_ops ksz_dsa_ops = {
.port_enable = ksz_port_enable,
.port_disable = ksz_port_disable,
- .xmit = ksz_xmit,
- .rcv = ksz_recv,
};
static int ksz_probe_mdio(struct udevice *dev)
--
2.17.1
[PATCH v3 3/8] net: dsa: ensure dsa driver has proper ops
Add a function to sanity check a dsa driver having proper ops.
Suggested-by: Vladimir Oltean
Signed-off-by: Tim Harvey
Reviewed-by: Vladimir Oltean
---
v3:
- added Vladimir's rb tag
v2: new patch
---
net/dsa-uclass.c | 17 +
1 file changed, 17 insertions(+)
diff --git a/net/dsa-uclass.c b/net/dsa-uclass.c
index 07edc584daf3..b3033c97aa63 100644
--- a/net/dsa-uclass.c
+++ b/net/dsa-uclass.c
@@ -342,6 +342,19 @@ U_BOOT_DRIVER(dsa_port) = {
.plat_auto = sizeof(struct eth_pdata),
};
+static int dsa_sanitize_ops(struct udevice *dev)
+{
+ struct dsa_ops *ops = dsa_get_ops(dev);
+
+ if ((!ops->xmit || !ops->rcv) &&
+ (!ops->port_enable && !ops->port_disable)) {
+ dev_err(dev, "Packets cannot be steered to ports\n");
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
/*
* This function mostly deals with pulling information out of the device tree
* into the pdata structure.
@@ -358,6 +371,10 @@ static int dsa_post_bind(struct udevice *dev)
if (!ofnode_valid(node))
return -ENODEV;
+ err = dsa_sanitize_ops(dev);
+ if (err)
+ return err;
+
pdata->master_node = ofnode_null();
node = ofnode_find_subnode(node, "ports");
--
2.17.1
[PATCH v3 1/8] net: mdio-uclass: scan for dm mdio children on post-bind
If a DM_MDIO driver is used we need to scan the subnodes as well. Signed-off-by: Tim Harvey Signed-off-by: Vladimir Oltean Reviewed-by: Ramon Fried --- v2: - added Ramon's rb tag --- net/mdio-uclass.c | 4 1 file changed, 4 insertions(+) diff --git a/net/mdio-uclass.c b/net/mdio-uclass.c index 4401492ca015..d80037d0ac71 100644 --- a/net/mdio-uclass.c +++ b/net/mdio-uclass.c @@ -49,7 +49,11 @@ static int dm_mdio_post_bind(struct udevice *dev) return -EINVAL; } +#if CONFIG_IS_ENABLED(OF_REAL) + return dm_scan_fdt_dev(dev); +#else return 0; +#endif } int dm_mdio_read(struct udevice *mdio_dev, int addr, int devad, int reg) -- 2.17.1
[PATCH v3 2/8] net: dsa: move cpu port probe to dsa_post_probe
In order to ensure that a DSA driver probe gets called before
dsa_ops->port_probe move the port_probe of the cpu_port to
a post-probe function.
Signed-off-by: Tim Harvey
Reviewed-by: Ramon Fried
Reviewed-by: Vladimir Oltean
---
v3:
- added Vladimir's rb tag
v2:
- added Ramon's rb tag
---
net/dsa-uclass.c | 14 +++---
1 file changed, 11 insertions(+), 3 deletions(-)
diff --git a/net/dsa-uclass.c b/net/dsa-uclass.c
index 9ff55a02fb23..07edc584daf3 100644
--- a/net/dsa-uclass.c
+++ b/net/dsa-uclass.c
@@ -466,8 +466,6 @@ static int dsa_pre_probe(struct udevice *dev)
{
struct dsa_pdata *pdata = dev_get_uclass_plat(dev);
struct dsa_priv *priv = dev_get_uclass_priv(dev);
- struct dsa_ops *ops = dsa_get_ops(dev);
- int err;
priv->num_ports = pdata->num_ports;
priv->cpu_port = pdata->cpu_port;
@@ -480,6 +478,15 @@ static int dsa_pre_probe(struct udevice *dev)
uclass_find_device_by_ofnode(UCLASS_ETH, pdata->master_node,
>master_dev);
+ return 0;
+}
+
+static int dsa_post_probe(struct udevice *dev)
+{
+ struct dsa_priv *priv = dev_get_uclass_priv(dev);
+ struct dsa_ops *ops = dsa_get_ops(dev);
+ int err;
+
/* Simulate a probing event for the CPU port */
if (ops->port_probe) {
err = ops->port_probe(dev, priv->cpu_port,
@@ -489,13 +496,14 @@ static int dsa_pre_probe(struct udevice *dev)
}
return 0;
-}
+};
UCLASS_DRIVER(dsa) = {
.id = UCLASS_DSA,
.name = "dsa",
.post_bind = dsa_post_bind,
.pre_probe = dsa_pre_probe,
+ .post_probe = dsa_post_probe,
.per_device_auto = sizeof(struct dsa_priv),
.per_device_plat_auto = sizeof(struct dsa_pdata),
.per_child_plat_auto = sizeof(struct dsa_port_pdata),
--
2.17.1
[PATCH v3 0/8] Add MV88E61xx DSA driver and use on gwventana
This series adds a DSA driver for the MV88E61xx based on drivers/net/phy/mv88e61xx and uses in on the gwventana_gw5904_defconfig. The hope is that the other three boards that use the MV88E61xx driver can move to this as well eventually so that we can remove the non-dm driver and the 4 Kconfig options it requires. The MV88E61xx has an MDIO interface thus DM_MDIO must be used so support for a UCLASS_MDIO driver is added to the fec_mxc ethernet driver in a way that allows a fallback to the previous non DM_MDIO case as there are many boards out there using this driver that define DM_MDIO but do not have the required dt props for a DM_MDIO driver which would cause a regression. Additionally some other patches are here suggested by Vladimir: - ensure MDIO children are scanned on post-bind is needed - sanity check DSA driver required ops are present - allow DSA drivers to not require xmit/recv functions - remove unecessary xmit/recv functions from ksz9477 driver v3: - fix mdios node in dt - add Vladimir's rb tag's v2: - added Ramon's rb tag's to first two patches - add patches for dsa-uclass to sanity check ops and make xmit/recv optional - fec: fix fallback for non conforming DM_MDIO dts - mv88e61xx: - rebase on v2022.07-rc2 (use ofnode_get_phy_node) - remove unused commented out fields from struct - remove unused PORT_MASK macro - remove phy from priv struct name - refactor code from original drivers/net/phy/mv88e61xx with suggestions from review to consolidate some functions into mv88e61xx_dsa_port_enable - remove unecessary skiping of disabling of CPU port - remove unecessary dev_set_parent_priv - remove unnecessary static init flag - replace debug with a dev_warn if switch device-id unsupported - remove unnecessary xmit/recv functions as we rely on the fact that only a single port is active instead of mangling packets Tested on a Gateworks GW5904 which has a Marvell 88E6176 switch hanging off the IMX6 FEC. Best Regards, Tim Tim Harvey (8): net: mdio-uclass: scan for dm mdio children on post-bind net: dsa: move cpu port probe to dsa_post_probe net: dsa: ensure dsa driver has proper ops net: dsa: allow rcv() and xmit() to be optional net: ksz9477: remove unnecessary xmit and recv functions net: fec: add support for DM_MDIO net: add MV88E61xx DSA driver board: gw_ventana: enable MV88E61XX DSA support arch/arm/dts/imx6qdl-gw5904.dtsi| 41 ++ board/gateworks/gw_ventana/gw_ventana.c | 50 +- configs/gwventana_gw5904_defconfig | 7 +- drivers/net/Kconfig | 7 + drivers/net/Makefile| 1 + drivers/net/fec_mxc.c | 90 ++- drivers/net/ksz9477.c | 23 - drivers/net/mv88e61xx.c | 843 net/dsa-uclass.c| 58 +- net/mdio-uclass.c | 4 + 10 files changed, 1051 insertions(+), 73 deletions(-) create mode 100644 drivers/net/mv88e61xx.c -- 2.17.1
Re: [PATCH 1/2] powerpc: mpc85xx: Fix CONFIG_OF_SEPARATE support for NOR booting
On Monday 23 May 2022 13:57:07 Tom Rini wrote:
> On Mon, May 02, 2022 at 06:36:38PM +0200, Pali Rohár wrote:
>
> > Commit e8c0e0064c8a ("powerpc: mpc85xx: Fix CONFIG_OF_SEPARATE support")
> > fixed SD card booting on mpc85xx boards but broke NOR booting on these
> > boards. Reason is that U-Boot build system for NOR images uses binman and
> > this binman ignores alignment defined in linker script. Instead it has own
> > config file where is alignment defined.
> >
> > Fix binman alignment for mpc85xx boards to match what is _now_ defined in
> > linker script.
> >
> > This change fixes building of U-Boot for NOR booting on P2020 board.
> >
> > Fixes: e8c0e0064c8a ("powerpc: mpc85xx: Fix CONFIG_OF_SEPARATE support")
> > Signed-off-by: Pali Rohár
>
> Applied to u-boot/master, thanks!
Perfect!!!
Re: [PATCH] net: fix phy_string_for_interface
On Tue, May 10, 2022 at 03:49:10PM -0700, Tim Harvey wrote:
> commit ffb0f6f488b9 ("treewide: Rename PHY_INTERFACE_MODE_NONE to
> PHY_INTERFACE_MODE_NA") broke the phy_string_for_interface function.
> Fix it.
>
> Fixes ffb0f6f488b9 ("treewide: Rename PHY_INTERFACE_MODE_NONE to
> PHY_INTERFACE_MODE_NA")
> Signed-off-by: Tim Harvey
> Cc: Marek Behún
> Cc: Stefan Roese
> Cc: Ramon Fried
> Cc: Vladimir Oltean
> Reviewed-by: Stefan Roese
> Reviewed-by: Marek Behún
> Reviewed-by: Ramon Fried
Applied to u-boot/master, thanks!
--
Tom
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Re: [PATCH v2] fs/squashfs: use lldiv function for math
On Thu, May 12, 2022 at 08:37:14PM +0200, Sean Nyekjaer wrote: > From: Sean Nyekjaer > > When compling for x86: > ld.bfd: fs/squashfs/sqfs.o: in function `sqfs_read': > u-boot/fs/squashfs/sqfs.c:1443: undefined reference to `__udivmoddi4' > ld.bfd: u-boot/fs/squashfs/sqfs.c:1521: undefined reference to `__udivmoddi4' > > Signed-off-by: Sean Nyekjaer > Reviewed-by: Miquel Raynal > Reviewed-by: Pali Rohár Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH] mmc: fsl_esdhc_spl: Fix checking for number of read sectors
On Wed, May 11, 2022 at 08:28:28PM +0200, Pali Rohár wrote:
> Commit 0980cbba7b3c ("mmc: fsl_esdhc_spl: pre-PBL: implement redundancy
> support") changed number of sectors which are read but did not adjusted
> error check.
>
> Fix it and check for if correct number of sectors were read.
>
> Fixes: 0980cbba7b3c ("mmc: fsl_esdhc_spl: pre-PBL: implement redundancy
> support")
> Signed-off-by: Pali Rohár
> Reviewed-by: Jaehoon Chung
Applied to u-boot/master, thanks!
--
Tom
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Re: [PATCH] arm: gic_v2: Skip gic_init_secure when cpu is not in el3
On Wed, May 11, 2022 at 10:39:07AM +0200, Michal Simek wrote: > From: Sai Pavan Boddu > > This would prevent configuring non-secure regs in case gic security > extensions are not emulated in Qemu. > > Signed-off-by: Sai Pavan Boddu > Signed-off-by: Michal Simek Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH v4 3/3] test: dm: spi: Replace _spi_get_bus_and_cs() by spi_get_bus_and_cs() in some case
On Wed, Mar 30, 2022 at 09:33:15AM +0200, Patrice Chotard wrote: > In case _spi_get_bus_and_cs()'s parameters drv_name and dev_name are > respectively set to NULL and 0, use spi_get_bus_and_cs() instead. > > Signed-off-by: Patrice Chotard > > Cc: Marek Behun > Cc: Jagan Teki > Cc: Vignesh R > Cc: Joe Hershberger > Cc: Ramon Fried > Cc: Lukasz Majewski > Cc: Marek Vasut > Cc: Wolfgang Denk > Cc: Simon Glass > Cc: Stefan Roese > Cc: "Pali Rohár" > Cc: Konstantin Porotchkin > Cc: Igal Liberman > Cc: Bin Meng > Cc: Pratyush Yadav > Cc: Sean Anderson > Cc: Anji J > Cc: Biwen Li > Cc: Priyanka Jain > Cc: Chaitanya Sakinam Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH v4 2/3] spi: spi_flash_probe_bus_cs() rely on DT for spi speed and mode
On Wed, Mar 30, 2022 at 09:33:14AM +0200, Patrice Chotard wrote: > Now, spi_flash_probe_bus_cs() relies on DT for spi speed and mode > and logically calls spi_get_bus_and_cs(). In case spi mode and speed are > not read from DT, make usage of spi_flash_probe() instead. > > To sum-up: > - Previous call tree was: > spi_flash_probe() -> spi_flash_probe_bus_cs() -> spi_get_bus_and_cs() > > - Current call tree is: > spi_flash_probe() -> _spi_get_bus_and_cs() > spi_flash_probe_bus_cs() -> spi_get_bus_and_cs() > > This patch impacts the following : > - cmd/sf.c: if spi mode and/or speed is passed in argument of > do_spi_flash_probe(), call spi_flash_probe() otherwise call > spi_flash_probe_bus_cs(). > > - drivers/net/fm/fm.c: as by default spi speed and mode was set to > 0 and a comment indicates that speed and mode are read from DT, > use spi_flash_probe_bus_cs(). > > - drivers/net/pfe_eth/pfe_firmware.c: spi speed and mode are not read > from DT by all platforms using this driver, so keep legacy and replace > spi_flash_probe_bus_cs() by spi_flash_probe(); > > - drivers/net/sni_netsec.c : spi speed and mode are not read from DT, > so replace spi_flash_probe_bus_cs() by spi_flash_probe(). > > - drivers/usb/gadget/max3420_udc.c: Can't find any platform which make > usage of this driver, nevertheless, keep legacy and replace > spi_get_bus_and_cs() by _spi_get_bus_and_cs(). > > - env/sf.c: a comment indicates that speed and mode are read > from DT. So use spi_flash_probe_bus_cs(). > > Signed-off-by: Patrice Chotard > > Cc: Marek Behun > Cc: Jagan Teki > Cc: Vignesh R > Cc: Joe Hershberger > Cc: Ramon Fried > Cc: Lukasz Majewski > Cc: Marek Vasut > Cc: Wolfgang Denk > Cc: Simon Glass > Cc: Stefan Roese > Cc: "Pali Rohár" > Cc: Konstantin Porotchkin > Cc: Igal Liberman > Cc: Bin Meng > Cc: Pratyush Yadav > Cc: Sean Anderson > Cc: Anji J > Cc: Biwen Li > Cc: Priyanka Jain > Cc: Chaitanya Sakinam Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH v4 1/3] spi: spi-uclass: Add new spi_get_bus_and_cs() implementation
On Wed, Mar 30, 2022 at 09:33:13AM +0200, Patrice Chotard wrote: > Move legacy spi_get_bus_and_cs() code to _spi_get_bus_and_cs(). > > Add new spi_get_bus_and_cs() implementation which rely on DT > for speed and mode and don't need any drv_name nor dev_name > parameters. This will prepare the ground for next patch. > > Update all callers to use _spi_get_bus_and_cs() to keep the > same behavior. > > Signed-off-by: Patrice Chotard > > Cc: Marek Behun > Cc: Jagan Teki > Cc: Vignesh R > Cc: Joe Hershberger > Cc: Ramon Fried > Cc: Lukasz Majewski > Cc: Marek Vasut > Cc: Wolfgang Denk > Cc: Simon Glass > Cc: Stefan Roese > Cc: "Pali Rohár" > Cc: Konstantin Porotchkin > Cc: Igal Liberman > Cc: Bin Meng > Cc: Pratyush Yadav > Cc: Sean Anderson > Cc: Anji J > Cc: Biwen Li > Cc: Priyanka Jain > Cc: Chaitanya Sakinam Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH 2/2] powerpc: mpc85xx: Fix CONFIG_OF_EMBED support for NOR booting
On Mon, May 02, 2022 at 06:36:39PM +0200, Pali Rohár wrote: > mpc85xx NOR binary contains also reset vector and therefore option > CONFIG_MPC85XX_HAVE_RESET_VECTOR must be defined. > > When build system uses binman, it takes care of constructing final image > which consist of u-boot-without-reset-vector, DTB and reset-vector. > > CONFIG_OF_EMBED does not use binman, there is no external DTB and Makefile > produce directly final u-boot.bin binary. > > So in this case mpc85xx reset vector must not be stripped from the final > u-boot.bin binary. Fix it. > > Signed-off-by: Pali Rohár Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH 1/2] powerpc: mpc85xx: Fix CONFIG_OF_SEPARATE support for NOR booting
On Mon, May 02, 2022 at 06:36:38PM +0200, Pali Rohár wrote:
> Commit e8c0e0064c8a ("powerpc: mpc85xx: Fix CONFIG_OF_SEPARATE support")
> fixed SD card booting on mpc85xx boards but broke NOR booting on these
> boards. Reason is that U-Boot build system for NOR images uses binman and
> this binman ignores alignment defined in linker script. Instead it has own
> config file where is alignment defined.
>
> Fix binman alignment for mpc85xx boards to match what is _now_ defined in
> linker script.
>
> This change fixes building of U-Boot for NOR booting on P2020 board.
>
> Fixes: e8c0e0064c8a ("powerpc: mpc85xx: Fix CONFIG_OF_SEPARATE support")
> Signed-off-by: Pali Rohár
Applied to u-boot/master, thanks!
--
Tom
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Re: Pull request: u-boot-imx u-boot-imx-20220523
On Mon, May 23, 2022 at 01:33:23PM +0200, Stefano Babic wrote: > Hi Tom, > > please pull from u-boot-imx, thanks ! > > The following changes since commit f83bd23e2a0e9861969c9d43395299a14f25ddda: > > Merge https://source.denx.de/u-boot/custodians/u-boot-marvell (2022-05-18 > 08:41:13 -0400) > > are available in the Git repository at: > > https://gitlab.denx.de/u-boot/custodians/u-boot-imx.git > tags/u-boot-imx-20220523 > > for you to fetch changes up to 4d573d5c98234cad328de77c773c3c3d79258255: > > ARM: dts: imx: Add support for DH electronics i.MX8M Plus DHCOM and PDK2 > (2022-05-23 11:37:58 +0200) > Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH 02/22] imx: imx8m[m/n/p]_venice: Enable SPL_DM_SERIAL
On Mon, May 23, 2022 at 4:58 AM Peng Fan (OSS) wrote: > > From: Peng Fan > > Enable CONFIG_SPL_DM_SERIAL. uart2 and its pinmux was already > marked with u-boot,dm-spl. > Move preloader_console_init after spl_early_init to make sure driver > model work. > > Signed-off-by: Peng Fan > Acked-by: Tim Harvey > Reviewed-by: Fabio Estevam > --- > include/configs/imx8mm_venice.h | 3 --- > include/configs/imx8mn_venice.h | 3 --- > include/configs/imx8mp_venice.h | 3 --- > 3 files changed, 9 deletions(-) > > diff --git a/include/configs/imx8mm_venice.h b/include/configs/imx8mm_venice.h > index 9836d5b73ca..90e8941a254 100644 > --- a/include/configs/imx8mm_venice.h > +++ b/include/configs/imx8mm_venice.h > @@ -101,9 +101,6 @@ > #define PHYS_SDRAM_SIZESZ_4G > #define CONFIG_SYS_BOOTM_LEN SZ_256M > > -/* UART */ > -#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(2) > - > /* Monitor Command Prompt */ > #define CONFIG_SYS_CBSIZE SZ_2K > #define CONFIG_SYS_MAXARGS 64 > diff --git a/include/configs/imx8mn_venice.h b/include/configs/imx8mn_venice.h > index 3cbe11a9035..6555dd4349c 100644 > --- a/include/configs/imx8mn_venice.h > +++ b/include/configs/imx8mn_venice.h > @@ -97,9 +97,6 @@ > #define PHYS_SDRAM_SIZESZ_4G > #define CONFIG_SYS_BOOTM_LEN SZ_256M > > -/* UART */ > -#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(2) > - > /* Monitor Command Prompt */ > #define CONFIG_SYS_CBSIZE SZ_2K > #define CONFIG_SYS_MAXARGS 64 > diff --git a/include/configs/imx8mp_venice.h b/include/configs/imx8mp_venice.h > index 4120e4cc6ba..c09a1b4572a 100644 > --- a/include/configs/imx8mp_venice.h > +++ b/include/configs/imx8mp_venice.h > @@ -97,9 +97,6 @@ > #define PHYS_SDRAM_SIZESZ_4G > #define CONFIG_SYS_BOOTM_LEN SZ_256M > > -/* UART */ > -#define CONFIG_MXC_UART_BASE UART2_BASE_ADDR > - > /* Monitor Command Prompt */ > #define CONFIG_SYS_CBSIZE SZ_2K > #define CONFIG_SYS_MAXARGS 64 > -- > 2.36.0 > Thanks Peng, Tested-By: Tim Harvey Best Regards, Tim
Re: [PATCH V4 1/8] spl: guard u_boot_any with X86
On Mon, May 23, 2022 at 06:28:44AM +, Peng Fan (OSS) wrote: > > Subject: Re: [PATCH V4 1/8] spl: guard u_boot_any with X86 > > > > On Sat, May 21, 2022 at 08:33:56AM +, Peng Fan wrote: > > > > Subject: Re: [PATCH V4 1/8] spl: guard u_boot_any with X86 > > > > > > > > On Fri, May 20, 2022 at 10:10:40PM +0800, Peng Fan (OSS) wrote: > > > > > > > > > From: Peng Fan > > > > > > > > > > set the symbol as weak not work if LTO is enabled. Since > > > > > u_boot_any is only used on X86 for now, so guard it with X86, > > > > > otherwise build break if we use BINMAN_SYMBOLS on i.MX. > > > > > > > > > > Tested-by: Tim Harvey #imx8m[m,n,p]-venice > > > > > Signed-off-by: Peng Fan > > > > > --- > > > > > common/spl/spl.c | 8 ++-- > > > > > common/spl/spl_ram.c | 4 > > > > > 2 files changed, 10 insertions(+), 2 deletions(-) > > > > > > > > I think we long term need to figure this out and address it so LTO > > > > works. But for now can you please guard this with a test on LTO > > > > instead, so it's clear where the problem is? > > > > > > Sorry, I could not get your point about guard with a test on LTO. > > > > > > Actually binman weak symbol will report a warning log if there is no > > > u_boot_any binman symbol. Since only X86 use it, I guard with X86. > > > > Why are you mentioning LTO in the commit message? When I read the > > commit message it sounds like you're saying the problem is that LTO doesn't > > like how this symbol is handled, but if LTO was disabled, everything would > > be > > fine. If it's not LTO-related, please re-word the message instead. > > Sorry, I could reword the commit message, but currently I have no better > idea to address the issue unless use X86 as a guard in the code as this > patch does. If you agree the code in this patch, I could reword commit msg > and send v5. Well, lets see what Alper says in the other part of the thread. I'd really like to solve this not work around this. But I'll take documenting the problem for the person that has X86 && LTO as good enough for the moment. -- Tom signature.asc Description: PGP signature
Re: [PATCH 2/2] tpm: add support for TPMv2.x I2C chips
On Mon, May 23, 2022 at 08:19:51AM -0500, Eddie James wrote:
>
> On 5/23/22 01:12, Ilias Apalodimas wrote:
> > Hi Eddie,
> >
> > Thanks for the patch.
> >
> > [...]
> >
> > > +static const struct tpm_tis_chip_data tpm_tis_std_chip_data = {
> > > + .pcr_count = 24,
> > > + .pcr_select_min = 3,
> > > +};
> > > +
> > > +static const struct udevice_id tpm_tis_i2c_ids[] = {
> > > + {
> > > + .compatible = "nuvoton,npct75x",
> > > + .data = (ulong)_tis_std_chip_data,
> > > + },
> > > + {
> > > + .compatible = "tcg,tpm-tis-i2c",
> > > + .data = (ulong)_tis_std_chip_data,
> > > + },
> > > + { }
> > > +};
> > > +
> > > +U_BOOT_DRIVER(tpm_tis_i2c) = {
> > > + .name = "tpm_tis_i2c",
> > > + .id = UCLASS_TPM,
> > > + .of_match = tpm_tis_i2c_ids,
> > > + .ops = _tis_i2c_ops,
> > > + .probe = tpm_tis_i2c_probe,
> > > + .remove = tpm_tis_i2c_remove,
> > > + .priv_auto_alloc_size = sizeof(struct tpm_chip),
> > Shouldn't this be .priv_auto only? IIRC we got rid of the
> > .priv_auto_alloc_size a while back? If so I can fix this while merging
>
>
> Yes, I think so. I tested with an older u-boot (openbmc uses a modified
> v2019.04) with all the TPM core patches, and I think I missed this bit in
> rebasing.
No worries, I can fix this while merging, there's no need for a v2. I
don't see anything obviously wrong with the patchset, unfortunately I
don't have an i2c tpm to test. Anyway
Reviewed-by: Ilias Apalodimas
P.S: Was the new TIS API useful?
Thanks
/Ilias
>
> Thanks,
>
> Eddie
>
>
> >
> > Regards
> > /Ilias
> >
> > > +};
> > > --
> > > 2.27.0
> > >
Re: [PATCH] cmd: pxe_utils: Check fdtcontroladdr in label_boot
On Mon, May 23, 2022 at 09:25:55AM +0200, Neil Armstrong wrote:
> Hi,
>
> On 19/05/2022 14:58, Peter Hoyes wrote:
> > On 18/05/2022 19:15, Neil Armstrong wrote:
> > > On 18/05/2022 17:52, Tom Rini wrote:
> > > > On Wed, May 18, 2022 at 10:40:12AM +0200, Neil Armstrong wrote:
> > > > > Hi,
> > > > >
> > > > > On 14/10/2021 10:40, Peter Hoyes wrote:
> > > > > > From: Peter Hoyes
> > > > > >
> > > > > > If using OF_CONTROL, fdtcontroladdr is set to the fdt used to
> > > > > > configure
> > > > > > U-Boot. When using PXE, if no fdt is defined in the menu file, and
> > > > > > there is no fdt at fdt_addr, add fall back on fdtcontroladdr too.
> > > > > >
> > > > > > We are developing board support for the Armv8r64 FVP using
> > > > > > config_distro_bootcmd. We are also using OF_BOARD and would like the
> > > > > > PXE boot option to default to the fdt provided by
> > > > > > board_fdt_blob_setup.
> > > > > >
> > > > > > Signed-off-by: Peter Hoyes
> > > > > > ---
> > > > > > cmd/pxe_utils.c | 8 +++-
> > > > > > 1 file changed, 7 insertions(+), 1 deletion(-)
> > > > > >
> > > > > > diff --git a/cmd/pxe_utils.c b/cmd/pxe_utils.c
> > > > > > index 067c24e5ff..8f8e69ca97 100644
> > > > > > --- a/cmd/pxe_utils.c
> > > > > > +++ b/cmd/pxe_utils.c
> > > > > > @@ -556,7 +556,10 @@ static int label_boot(struct cmd_tbl *cmdtp,
> > > > > > struct pxe_label *label)
> > > > > > * Scenario 2: If there is an fdt_addr specified, pass it
> > > > > > along to
> > > > > > * bootm, and adjust argc appropriately.
> > > > > > *
> > > > > > - * Scenario 3: fdt blob is not available.
> > > > > > + * Scenario 3: If there is an fdtcontroladdr specified, pass
> > > > > > it along to
> > > > > > + * bootm, and adjust argc appropriately.
> > > > > > + *
> > > > > > + * Scenario 4: fdt blob is not available.
> > > > > > */
> > > > > > bootm_argv[3] = env_get("fdt_addr_r");
> > > > > > @@ -646,6 +649,9 @@ static int label_boot(struct cmd_tbl *cmdtp,
> > > > > > struct pxe_label *label)
> > > > > > if (!bootm_argv[3])
> > > > > > bootm_argv[3] = env_get("fdt_addr");
> > > > > > + if (!bootm_argv[3])
> > > > > > + bootm_argv[3] = env_get("fdtcontroladdr");
> > > > > > +
> > > > > > if (bootm_argv[3]) {
> > > > > > if (!bootm_argv[2])
> > > > > > bootm_argv[2] = "-";
> > > > >
> > > > > This change makes a regression when using a FIT image as kernel image
> > > > > within an extlinux.conf
> > > > >
> > > > > Before this change, when a DT wasn't specified, the DT in the FIT
> > > > > image was selected,
> > > > > not the u-boot DT is selected.
> > > > >
> > > > > While it should work because the U-Boot DT should work in Linux, it's
> > > > > not always the case.
> > > > >
> > > > > Before:
> > > > > Found /extlinux/extlinux.conf
> > > > > Retrieving file: /extlinux/extlinux.conf
> > > > > 1: Yocto
> > > > > Retrieving file: /fitImage
> > > > > append: root=PARTUUID=fd26d57f-02 rootwait console=ttyAML0,115200
> > > > > ## Loading kernel from FIT Image at 0808 ...
> > > > > Using 'conf-amlogic_meson-gxl-s905x-libretech-cc.dtb'
> > > > > configuration
> > > > > Trying 'kernel-1' kernel subimage
> > > > > Description: Linux kernel
> > > > > Type: Kernel Image
> > > > > Compression: gzip compressed
> > > > > Data Start: 0x08080120
> > > > > Data Size: 9926956 Bytes = 9.5 MiB
> > > > > Architecture: AArch64
> > > > > OS: Linux
> > > > > Load Address: 0x0108
> > > > > Entry Point: 0x0108
> > > > > Hash algo: sha256
> > > > > Hash value:
> > > > > 5181a76e4e7a728e24cd8569f8e48c543ac259bf4d66591a3dc5e166d709429e
> > > > > Verifying Hash Integrity ... sha256+ OK
> > > > > ## Loading fdt from FIT Image at 0808 ...
> > > > > Using 'conf-amlogic_meson-gxl-s905x-libretech-cc.dtb'
> > > > > configuration
> > > > > Trying 'fdt-amlogic_meson-gxl-s905x-libretech-cc.dtb' fdt subimage
> > > > > Description: Flattened Device Tree blob
> > > > > Type: Flat Device Tree
> > > > > Compression: uncompressed
> > > > > Data Start: 0x089f7b78
> > > > > Data Size: 29092 Bytes = 28.4 KiB
> > > > > Architecture: AArch64
> > > > > Hash algo: sha256
> > > > > Hash value:
> > > > > 72e5e4fcbb4aa59042377720e5636132ba790d85b6c3f6442446acc63f48cf67
> > > > > Verifying Hash Integrity ... sha256+ OK
> > > > > Booting using the fdt blob at 0x89f7b78
> > > > > Uncompressing Kernel Image
> > > > > Loading Device Tree to 7bf2f000, end 7bf391a3 ...
> > > > > OK
> > > > >
> > > > >
> > > > > After:
> > > > > Found /extlinux/extlinux.conf
> > > > > Retrieving file: /extlinux/extlinux.conf
> > > > > 1: Yocto
> > > > > Retrieving file: /fitImage
> > > > > append: root=PARTUUID=fd26d57f-02 rootwait
[PATCH] riscv: fix compitible with binutils 2.38
commit 6df2a016c0c8a3d0933ef33dd192ea6606b115e3 from linux kernel Since binutils 2.38, default ISA spec version switch to 20191213, in this version, original I extension be split into I, Zicsr and Zifencei. Zicsr is csr read/write (csrr*/csrw*) instructions, and Zifencei is fence.i instruction. This will cause compile error like this: Error: unrecognized opcode `csrr a5,0xc01' Error: unrecognized opcode `fence.i' This commit add code to detect new Zicsr and Zifencei extensions, and enable it when needed. Signed-off-by: Coelacanthus Cc: Rick Chen Cc: Leo --- arch/riscv/Makefile | 9 - 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile index 0b80eb8d86..62712f8d38 100644 --- a/arch/riscv/Makefile +++ b/arch/riscv/Makefile @@ -24,7 +24,14 @@ ifeq ($(CONFIG_CMODEL_MEDANY),y) CMODEL = medany endif -ARCH_FLAGS = -march=$(ARCH_BASE)$(ARCH_A)$(ARCH_C) -mabi=$(ABI) \ +RISCV_MARCH_y = $(ARCH_BASE)$(ARCH_A)$(ARCH_C) + +# Newer binutils versions default to ISA spec version 20191213 which moves some +# instructions from the I extension to the Zicsr and Zifencei extensions. +toolchain-need-zicsr-zifencei := $(call cc-option-yn, -mabi=$(ABI) -march=$(RISCV_MARCH_y)_zicsr_zifencei) +RISCV_MARCH_$(toolchain-need-zicsr-zifencei) := $(RISCV_MARCH_y)_zicsr_zifencei + +ARCH_FLAGS = -march=$(RISCV_MARCH_y) -mabi=$(ABI) \ -mcmodel=$(CMODEL) PLATFORM_CPPFLAGS += $(ARCH_FLAGS) -- 2.36.1
[PATCH v2 2/3] usb: add isp1760 family driver
ISP1760/61/63 are a family of usb controllers, here the main
goal is to support the ISP1763 hcd part found in the MPS3 FPGA
board form Arm. This is based on the kernel driver and ported
to u-boot.
Signed-off-by: Rui Miguel Silva
---
Makefile|1 +
drivers/usb/Kconfig |2 +
drivers/usb/common/Makefile |1 +
drivers/usb/isp1760/Kconfig | 12 +
drivers/usb/isp1760/Makefile|6 +
drivers/usb/isp1760/isp1760-core.c | 380
drivers/usb/isp1760/isp1760-core.h | 96 ++
drivers/usb/isp1760/isp1760-hcd.c | 2477 +++
drivers/usb/isp1760/isp1760-hcd.h | 81 +
drivers/usb/isp1760/isp1760-if.c| 125 ++
drivers/usb/isp1760/isp1760-regs.h | 292
drivers/usb/isp1760/isp1760-uboot.c | 75 +
drivers/usb/isp1760/isp1760-uboot.h | 27 +
13 files changed, 3575 insertions(+)
create mode 100644 drivers/usb/isp1760/Kconfig
create mode 100644 drivers/usb/isp1760/Makefile
create mode 100644 drivers/usb/isp1760/isp1760-core.c
create mode 100644 drivers/usb/isp1760/isp1760-core.h
create mode 100644 drivers/usb/isp1760/isp1760-hcd.c
create mode 100644 drivers/usb/isp1760/isp1760-hcd.h
create mode 100644 drivers/usb/isp1760/isp1760-if.c
create mode 100644 drivers/usb/isp1760/isp1760-regs.h
create mode 100644 drivers/usb/isp1760/isp1760-uboot.c
create mode 100644 drivers/usb/isp1760/isp1760-uboot.h
diff --git a/Makefile b/Makefile
index e3ce28791869..471ac7170aab 100644
--- a/Makefile
+++ b/Makefile
@@ -841,6 +841,7 @@ libs-y += drivers/usb/host/
libs-y += drivers/usb/mtu3/
libs-y += drivers/usb/musb/
libs-y += drivers/usb/musb-new/
+libs-y += drivers/usb/isp1760/
libs-y += drivers/usb/phy/
libs-y += drivers/usb/ulpi/
ifdef CONFIG_POST
diff --git a/drivers/usb/Kconfig b/drivers/usb/Kconfig
index ab1d061bd0d5..86804166de3e 100644
--- a/drivers/usb/Kconfig
+++ b/drivers/usb/Kconfig
@@ -68,6 +68,8 @@ config SPL_DM_USB_GADGET
source "drivers/usb/host/Kconfig"
+source "drivers/usb/isp1760/Kconfig"
+
source "drivers/usb/cdns3/Kconfig"
source "drivers/usb/dwc3/Kconfig"
diff --git a/drivers/usb/common/Makefile b/drivers/usb/common/Makefile
index dc05cb0a5077..f08b064d2493 100644
--- a/drivers/usb/common/Makefile
+++ b/drivers/usb/common/Makefile
@@ -4,6 +4,7 @@
#
obj-$(CONFIG_$(SPL_)DM_USB) += common.o
+obj-$(CONFIG_USB_ISP1760) += usb_urb.o
obj-$(CONFIG_USB_MUSB_HCD) += usb_urb.o
obj-$(CONFIG_USB_MUSB_UDC) += usb_urb.o
obj-$(CONFIG_USB_EHCI_FSL) += fsl-dt-fixup.o fsl-errata.o
diff --git a/drivers/usb/isp1760/Kconfig b/drivers/usb/isp1760/Kconfig
new file mode 100644
index ..993d71e74cd2
--- /dev/null
+++ b/drivers/usb/isp1760/Kconfig
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0
+
+config USB_ISP1760
+ tristate "NXP ISP 1760/1761/1763 support"
+ select DM_USB
+ select USB_HOST
+ help
+ Say Y or M here if your system as an ISP1760/1761/1763 USB host
+ controller.
+
+ This USB controller is usually attached to a non-DMA-Master
+ capable bus.
diff --git a/drivers/usb/isp1760/Makefile b/drivers/usb/isp1760/Makefile
new file mode 100644
index ..2c809c01b118
--- /dev/null
+++ b/drivers/usb/isp1760/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0
+isp1760-y := isp1760-core.o isp1760-if.o isp1760-uboot.o isp1760-hcd.o
+
+#isp1760-hcd.o
+
+obj-$(CONFIG_USB_ISP1760) += isp1760.o
diff --git a/drivers/usb/isp1760/isp1760-core.c
b/drivers/usb/isp1760/isp1760-core.c
new file mode 100644
index ..d2d1b7e5ea5d
--- /dev/null
+++ b/drivers/usb/isp1760/isp1760-core.c
@@ -0,0 +1,380 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Driver for the NXP ISP1760 chip
+ *
+ * Copyright 2022 Linaro, Rui Miguel Silva
+ *
+ * This is based on linux kernel driver, original developed:
+ * Copyright 2014 Laurent Pinchart
+ * Copyright 2007 Sebastian Siewior
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "isp1760-core.h"
+#include "isp1760-hcd.h"
+#include "isp1760-regs.h"
+
+#define msleep(a) udelay((a) * 1000)
+
+static int isp1760_init_core(struct isp1760_device *isp)
+{
+ struct isp1760_hcd *hcd = >hcd;
+
+ /*
+* Reset the host controller, including the CPU interface
+* configuration.
+*/
+ isp1760_field_set(hcd->fields, SW_RESET_RESET_ALL);
+ msleep(100);
+
+ /* Setup HW Mode Control: This assumes a level active-low interrupt */
+ if ((isp->devflags & ISP1760_FLAG_ANALOG_OC) && hcd->is_isp1763)
+ return -EINVAL;
+
+ if (isp->devflags & ISP1760_FLAG_BUS_WIDTH_16)
+ isp1760_field_clear(hcd->fields, HW_DATA_BUS_WIDTH);
+ if (isp->devflags & ISP1760_FLAG_BUS_WIDTH_8)
+ isp1760_field_set(hcd->fields, HW_DATA_BUS_WIDTH);
+ if (isp->devflags & ISP1760_FLAG_ANALOG_OC)
+
[PATCH v2] arm: socfpga: Add the terasic de10-standard board
Use the de10-nano files as templates for the de10-standard board.
The files in qts directory are generated by quartus from the GHRD
design.
Signed-off-by: Humberto Naves
Reviewed-by: Marek Vasut
---
Changes for v2:
- Also use generated sdram_config.h from bsp-create-settings
- Update the copyright messages (for substantial changes)
---
.../dts/socfpga_cyclone5_de10_standard.dts| 86 +++
arch/arm/mach-socfpga/Kconfig | 7 +
board/terasic/de10-standard/MAINTAINERS | 5 +
board/terasic/de10-standard/Makefile | 6 +
.../terasic/de10-standard/qts/iocsr_config.h | 659 ++
.../terasic/de10-standard/qts/pinmux_config.h | 218 ++
board/terasic/de10-standard/qts/pll_config.h | 84 +++
.../terasic/de10-standard/qts/sdram_config.h | 344 +
board/terasic/de10-standard/socfpga.c | 5 +
configs/socfpga_de10_standard_defconfig | 66 ++
include/configs/socfpga_de10_standard.h | 18 +
11 files changed, 1498 insertions(+)
create mode 100644 arch/arm/dts/socfpga_cyclone5_de10_standard.dts
create mode 100644 board/terasic/de10-standard/MAINTAINERS
create mode 100644 board/terasic/de10-standard/Makefile
create mode 100644 board/terasic/de10-standard/qts/iocsr_config.h
create mode 100644 board/terasic/de10-standard/qts/pinmux_config.h
create mode 100644 board/terasic/de10-standard/qts/pll_config.h
create mode 100644 board/terasic/de10-standard/qts/sdram_config.h
create mode 100644 board/terasic/de10-standard/socfpga.c
create mode 100644 configs/socfpga_de10_standard_defconfig
create mode 100644 include/configs/socfpga_de10_standard.h
diff --git a/arch/arm/dts/socfpga_cyclone5_de10_standard.dts
b/arch/arm/dts/socfpga_cyclone5_de10_standard.dts
new file mode 100644
index 00..39bce3b2ac
--- /dev/null
+++ b/arch/arm/dts/socfpga_cyclone5_de10_standard.dts
@@ -0,0 +1,86 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2017, Intel Corporation
+ *
+ * Adapted from socfpga_cyclone5_de10_nano.dts
+ */
+
+#include "socfpga_cyclone5.dtsi"
+#include "socfpga-common-u-boot.dtsi"
+
+/ {
+ model = "Terasic DE10-Standard";
+ compatible = "altr,socfpga-cyclone5", "altr,socfpga";
+
+ chosen {
+ bootargs = "console=ttyS0,115200";
+ stdout-path = "serial0:115200n8";
+ };
+
+ aliases {
+ ethernet0 =
+ udc0 =
+ };
+
+ memory {
+ name = "memory";
+ device_type = "memory";
+ reg = <0x0 0x4000>; /* 1GB */
+ };
+};
+
+ {
+ status = "okay";
+ phy-mode = "rgmii";
+
+ rxd0-skew-ps = <420>;
+ rxd1-skew-ps = <420>;
+ rxd2-skew-ps = <420>;
+ rxd3-skew-ps = <420>;
+ txen-skew-ps = <0>;
+ txc-skew-ps = <1860>;
+ rxdv-skew-ps = <420>;
+ rxc-skew-ps = <1680>;
+};
+
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
+
+ {
+ bank-name = "porta";
+};
+
+ {
+ bank-name = "portb";
+};
+
+ {
+ bank-name = "portc";
+};
+
+ {
+ status = "okay";
+ u-boot,dm-pre-reloc;
+};
+
+ {
+ status = "okay";
+};
+
+ {
+ clock-frequency = <1>;
+ u-boot,dm-pre-reloc;
+};
+
+ {
+ status = "disabled";
+};
diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index 78a7549a41..547e47ed9d 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -180,6 +180,10 @@ config TARGET_SOCFPGA_TERASIC_DE10_NANO
bool "Terasic DE10-Nano (Cyclone V)"
select TARGET_SOCFPGA_CYCLONE5
+config TARGET_SOCFPGA_TERASIC_DE10_STANDARD
+ bool "Terasic DE10-Standard (Cyclone V)"
+ select TARGET_SOCFPGA_CYCLONE5
+
config TARGET_SOCFPGA_TERASIC_DE1_SOC
bool "Terasic DE1-SoC (Cyclone V)"
select TARGET_SOCFPGA_CYCLONE5
@@ -199,6 +203,7 @@ config SYS_BOARD
default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
default "de1-soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
default "de10-nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO
+ default "de10-standard" if TARGET_SOCFPGA_TERASIC_DE10_STANDARD
default "is1" if TARGET_SOCFPGA_IS1
default "mcvevk" if TARGET_SOCFPGA_ARIES_MCVEVK
default "n5x-socdk" if TARGET_SOCFPGA_N5X_SOCDK
@@ -224,6 +229,7 @@ config SYS_VENDOR
default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO
default "terasic" if TARGET_SOCFPGA_TERASIC_DE1_SOC
default "terasic" if TARGET_SOCFPGA_TERASIC_DE10_NANO
+ default "terasic" if TARGET_SOCFPGA_TERASIC_DE10_STANDARD
default "terasic" if TARGET_SOCFPGA_TERASIC_SOCKIT
config SYS_SOC
@@ -239,6 +245,7 @@ config SYS_CONFIG_NAME
default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
default "socfpga_de1_soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
default "socfpga_de10_nano" if
Re: [PATCH] arm: socfpga: Add the terasic de10-standard board
Hi Marek, Thanks for the quick review! > Doesn't the PLL config also come from quartus ? It should all come from > it. See doc/README.socfpga My mistake, I will update the patch using all the files created by the bsp-create-settings. > I think a lot of those board/config-specific copyright messages could > use an update, I think they should be assigned to you. Please do a quick > V2 with that change. Besides that: Please advise what I should do there. For this particular board I adapted the code from the de10-nano board, which already had these copyright messages. Best regards, On Sat, May 21, 2022 at 10:06 PM Marek Vasut wrote: > > On 5/21/22 19:32, Humberto Naves wrote: > > Used the de10-nano files as templates for the de10-standard board. > > Changed the iocsr_config.h and pinmux_config.h based on the handoff > > files generated by quartus. Finally, the pll_config.h was copied > > from the altera cyclone5-socdk board. > > Doesn't the PLL config also come from quartus ? It should all come from > it. See doc/README.socfpga > > > Signed-off-by: Humberto Naves > > Cc: Marek Vasut > > I think a lot of those board/config-specific copyright messages could > use an update, I think they should be assigned to you. Please do a quick > V2 with that change. Besides that: > > Reviewed-by: Marek Vasut
Raspberry Pi won’t boot from compressed subvolume (BTRFS)
Hello u-boot team, I’ve been experimenting for about a year with a NixOS-based Raspberry Pi image, with the end goal of a zstd-compressed image that uses BTRFS subvolumes, having the root filesystem at @ and boot at @boot (with several other subvolumes). The NixOS Raspberry Pi images use u-boot by default. I’ve started a few discussions in the NixOS community as I learn and iterate: https://discourse.nixos.org/t/raspberry-pi-nixos-on-btrfs-root/14081 and I’ve made my code available at: https://github.com/n8henrie/nixos-btrfs-pi . I’m sure it’s obvious (or will be soon) that I’m a hobbyist, a novice with NixOS, and that I understand very little about u-boot and bootloaders in general, so I hope you can be patient as I humbly ask for someone to point me in the right direction. For reference, the official NixOS code for generating u-boot images is here: https://github.com/NixOS/nixpkgs/blob/3d4e586313d292c9e764a8e88a1fdccb16ffb2d3/pkgs/misc/uboot/default.nix I’ve made a lot of progress, including an image that reliably boots from @boot to the @ root subvolume with the u-boot configuration: CONFIG_CMD_BTRFS=y CONFIG_ZSTD=y CONFIG_BOOTCOMMAND="setenv boot_prefixes / /boot/ /@/ /@boot/; run distro_bootcmd;" with kernel params: "root=LABEL=NIXOS_SD" "rootfstype=btrfs" "rootflags=subvol=@" Unfortunately, after the initial boot and going through the initial OS installation steps, if I have compression enabled, it reboots into a boot loop with the following error messages: Scanning mmc 0:2... Found /@boot/extlinux/extlinux.conf Retrieving file: /@boot/extlinux/extlinux.conf 2938 bytes read in 27 ms (105.5 KiB/s) 1 NixOS Default 2 NixOS Configuration 4 (2022-02-24 21:34 22.05pre356135.7f9b6c2babf) 3 NixOS Configuration 3 (2022-02-25 03:59 22.05pre356435.7/9b6eZbabf) 4: NixOS Configuration 2 (2022-02-24 21:34 22.05pre356435.7/9b6c2babr) 5: NixOS Enter choice: 1: NixOS - Default Retrieving file: /@boot/extlinux/..nixos/zhbharzhzqga617uc37uk0g6q1bx891u-initrd-linux-5.10.101-initrd 20588420 bytes read in 1910 ms (10.3 MiB/s) Retrieving file: /@boot/extlinux/..nixos/6c1m6j0k1gmjrmikOyyizariiry?Zlqr-linux-5.10.101-Image 50629120 bytes read in 6863 ms (7 MiB/s) append: init-mix/store/pikl8ju4077iaix36n8mifzu6l6rcajz-nixos-system-nixpi-22.05p re356435-7/9b6eZbabf/init console=tty1 console=ttyAMAO console=ttyS0, 1115200 root= LABEL=-NIXOS_SD rootfstype=btrfs rootflags=subvol=@ loglevel=4 Retrieving file: /@boot/extlinux/../nixos/6c16j0k1gmjrmikOyyizari1ry72lqr-linux-5.10.101-dtbs/broadcon/bcn2837-rpi-3-b.dtb 14310 bytes read in 66 ms (210.9 KiB/s) Moving Image from 0x8 to 0x20, end=32f ## Flattened Device Tree blob at 0370 Booting using the fdt blob at 0x370 Using Device Tree in place at 0370 end 037067e5 fdt_find_or_add_subnode: memory: FDT_ERR_BADSTRUCTURE ERROR: arch-specific fdt fixup failed - must RESET the board to recover. FDT creation failed! resetting ... This happens even though I have CONFIG_ZSTD=y. If I do *not* enable compression (in my BTRFS mount options), it reboots normally and everything works! I may have made some OCR / C errors above; I’ve posted some pictures of the error messages (and similar discussion to this email, with no responses) here: https://discourse.nixos.org/t/btrfs-pi-wont-boot-from-compressed-subvolume/18462/2 I’m not currently using BTRFS RAID, just a single device. One of my other (x86_64) machines uses a similar setup with @, @boot, and zstd-compression with grub and works well, so I’m hoping this is also possible with u-boot. Seeing that the errors mention the FDT and fixup, I tried CONFIG_ARCH_FIXUP_FDT_MEMORY with both =y and =n without interesting changes to the error messages. What I’m assuming, based on the above, is that re-writing the @boot subvolume with compression is moving the location of the device tree files and that u-boot is no longer able to find the necessary files (some of which I think may also be in the nix store in the @nix subvolume). Does that sound like a reasonable guess as to what is going on? If so, are there config options or settings that I might be able to use to help u-boot find the necessary files after things are re-written with compression? Many thanks in advance for your time and attention, and thanks for your hard work on u-boot!
[PATCH] cmd: cat: add new command
Add cat command to print file content to standard out
Signed-off-by: Roger Knecht
---
cmd/Kconfig | 6 ++
cmd/Makefile | 1 +
cmd/cat.c| 54
3 files changed, 61 insertions(+)
create mode 100644 cmd/cat.c
diff --git a/cmd/Kconfig b/cmd/Kconfig
index 69c1814d24..2cb719795c 100644
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -385,6 +385,12 @@ config CMD_ABOOTIMG
See doc/android/boot-image.rst for details.
+config CMD_CAT
+ bool "cat"
+ default y
+ help
+ print file to standard output
+
config CMD_ELF
bool "bootelf, bootvx"
default y
diff --git a/cmd/Makefile b/cmd/Makefile
index 5e43a1e022..589b9680ba 100644
--- a/cmd/Makefile
+++ b/cmd/Makefile
@@ -38,6 +38,7 @@ obj-$(CONFIG_CMD_BOOTZ) += bootz.o
obj-$(CONFIG_CMD_BOOTI) += booti.o
obj-$(CONFIG_CMD_BTRFS) += btrfs.o
obj-$(CONFIG_CMD_BUTTON) += button.o
+obj-$(CONFIG_CMD_CAT) += cat.o
obj-$(CONFIG_CMD_CACHE) += cache.o
obj-$(CONFIG_CMD_CBFS) += cbfs.o
obj-$(CONFIG_CMD_CLK) += clk.o
diff --git a/cmd/cat.c b/cmd/cat.c
new file mode 100644
index 00..4ba3b611aa
--- /dev/null
+++ b/cmd/cat.c
@@ -0,0 +1,54 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2022
+ * Roger Knecht
+ */
+
+#include
+#include
+#include
+#include
+
+static int do_cat(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ char *data;
+ loff_t index;
+ loff_t size;
+ int ret;
+
+ if (argc < 4)
+ return CMD_RET_USAGE;
+
+ ret = fs_set_blk_dev(argv[1], argv[2], FS_TYPE_ANY);
+ if (ret)
+ return ret;
+
+ ret = fs_size(argv[3], );
+ if (ret)
+ return ret;
+
+ data = malloc(size);
+ if (!data)
+ return -ENOMEM;
+
+ ret = fs_set_blk_dev(argv[1], argv[2], FS_TYPE_ANY);
+ if (ret)
+ return ret;
+
+ ret = fs_read(argv[3], (ulong)data, 0, 0, );
+ if (ret)
+ return ret;
+
+ for (index = 0; index < size; index++)
+ putc(data[index]);
+
+ free(data);
+
+ return 0;
+}
+
+U_BOOT_CMD(cat, 4, 1, do_cat,
+ "print file to standard output",
+ " file\n"
+ "- print file from 'dev' on 'interface' to standard output");
--
2.17.1
Re: [PATCH 2/2] tpm: add support for TPMv2.x I2C chips
On 5/23/22 01:12, Ilias Apalodimas wrote:
Hi Eddie,
Thanks for the patch.
[...]
+static const struct tpm_tis_chip_data tpm_tis_std_chip_data = {
+ .pcr_count = 24,
+ .pcr_select_min = 3,
+};
+
+static const struct udevice_id tpm_tis_i2c_ids[] = {
+ {
+ .compatible = "nuvoton,npct75x",
+ .data = (ulong)_tis_std_chip_data,
+ },
+ {
+ .compatible = "tcg,tpm-tis-i2c",
+ .data = (ulong)_tis_std_chip_data,
+ },
+ { }
+};
+
+U_BOOT_DRIVER(tpm_tis_i2c) = {
+ .name = "tpm_tis_i2c",
+ .id = UCLASS_TPM,
+ .of_match = tpm_tis_i2c_ids,
+ .ops = _tis_i2c_ops,
+ .probe = tpm_tis_i2c_probe,
+ .remove = tpm_tis_i2c_remove,
+ .priv_auto_alloc_size = sizeof(struct tpm_chip),
Shouldn't this be .priv_auto only? IIRC we got rid of the
.priv_auto_alloc_size a while back? If so I can fix this while merging
Yes, I think so. I tested with an older u-boot (openbmc uses a modified
v2019.04) with all the TPM core patches, and I think I missed this bit
in rebasing.
Thanks,
Eddie
Regards
/Ilias
+};
--
2.27.0
Re: dwc_eth_qos driver for tegra
On 5/23/22 13:46, Rasmus Villemoes wrote: On 23/05/2022 12.57, Marek Vasut wrote: On 5/23/22 11:17, Rasmus Villemoes wrote: Hi Hi, I'm looking at switching the dwc_eth_qos driver over to use dm_eth_phy_connect(). However, I'm a little puzzled by the code for the tegra variant. The comment at the top of the file, as well as tegra186.dtsi, says phy-mode = "rgmii"; But eqos_get_interface_tegra186() returns a hard-coded PHY_INTERFACE_MODE_MII. Now the commit which introduced the ->interface abstraction, ac2d4efb16e (net: dwc_eth_qos: add Ethernet stm32mp1 support), and that eqos_get_interface_tegra186() function, changed - eqos->phy = phy_connect(eqos->mii, 0, dev, 0); to + eqos->phy = phy_connect(eqos->mii, 0, dev, + eqos->config->interface(dev)); and that last hard-coded 0 in the former phy_connect() is indeed equivalent to PHY_INTERFACE_MODE_MII. So which is it? It would be nice if one could just rely on dm_eth_phy_connect() picking up the correct value from device tree, and drop all the code which duplicates parsing of phy-mode from the ethernet driver. linux-2.6$ git grep mii arch/arm64/boot/dts/nvidia/tegra186* arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi: phy-mode = "rgmii"; arch/arm64/boot/dts/nvidia/tegra186-p3509-+p3636-0001.dts: phy-mode = "rgmii-id"; So probably RGMII ? Well, yes, I also did check the linux device tree files which also says rgmii, but that doesn't explain why the U-Boot driver code seems to ignore that entirely and use mii hardcoded, both before and after ac2d4efb16e. So another way of asking: does this driver actually work today, and/or has it worked at some point? I assume the answer is yes - after all, the very first commit "supports the specific configuration used in NVIDIA's Tegra186 chip", but that commit also did that phy_connect() with a last argument of 0 aka PHY_INTERFACE_MODE_MII. And would it break if one started taking the phy-mode from device tree? If so, should device tree be updated to say "mii"? I think we wait for nvidia to answer all this, I don't have that SoC available.
[PATCH 16/22] imx: engicam-imx8mm: drop unused macro
From: Peng Fan
Drop unused WDOG macro
Signed-off-by: Peng Fan
Reviewed-by: Michael Trimarchi
---
board/engicam/imx8mm/spl.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/board/engicam/imx8mm/spl.c b/board/engicam/imx8mm/spl.c
index f75f2dc634c..1846134a492 100644
--- a/board/engicam/imx8mm/spl.c
+++ b/board/engicam/imx8mm/spl.c
@@ -54,8 +54,6 @@ int board_fit_config_name_match(const char *name)
}
#endif
-#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
-
int board_early_init_f(void)
{
return 0;
--
2.36.0
[PATCH 22/22] imx: phycore_imx8mm/p: clean up board watchdog code
From: Peng Fan
pinctrl_wdog already marked u-boot,dm-spl, so clean up board code.
The set_wdog_reset() function is not necessary as this is handled by
the imx_watchdog.c driver due to the 'fsl,ext-reset-output' property
being set.
Signed-off-by: Peng Fan
Tested-by: Teresa Remmet
---
board/phytec/phycore_imx8mm/spl.c | 19 ---
board/phytec/phycore_imx8mp/spl.c | 19 ---
2 files changed, 38 deletions(-)
diff --git a/board/phytec/phycore_imx8mm/spl.c
b/board/phytec/phycore_imx8mm/spl.c
index 7f24a3affc8..d87ab6d4497 100644
--- a/board/phytec/phycore_imx8mm/spl.c
+++ b/board/phytec/phycore_imx8mm/spl.c
@@ -57,23 +57,6 @@ int board_fit_config_name_match(const char *name)
return 0;
}
-#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE)
-
-static iomux_v3_cfg_t const wdog_pads[] = {
- IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
-};
-
-int board_early_init_f(void)
-{
- struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
-
- imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
-
- set_wdog_reset(wdog);
-
- return 0;
-}
-
void board_init_f(ulong dummy)
{
int ret;
@@ -82,8 +65,6 @@ void board_init_f(ulong dummy)
init_uart_clk(2);
- board_early_init_f();
-
/* Clear the BSS. */
memset(__bss_start, 0, __bss_end - __bss_start);
diff --git a/board/phytec/phycore_imx8mp/spl.c
b/board/phytec/phycore_imx8mp/spl.c
index 38a581bef57..faed6fc3b76 100644
--- a/board/phytec/phycore_imx8mp/spl.c
+++ b/board/phytec/phycore_imx8mp/spl.c
@@ -89,23 +89,6 @@ int board_fit_config_name_match(const char *name)
return 0;
}
-#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
-
-static iomux_v3_cfg_t const wdog_pads[] = {
- MX8MP_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
-};
-
-int board_early_init_f(void)
-{
- struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
-
- imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
-
- set_wdog_reset(wdog);
-
- return 0;
-}
-
void board_init_f(ulong dummy)
{
int ret;
@@ -114,8 +97,6 @@ void board_init_f(ulong dummy)
init_uart_clk(0);
- board_early_init_f();
-
ret = spl_early_init();
if (ret) {
debug("spl_early_init() failed: %d\n", ret);
--
2.36.0
[PATCH 21/22] imx: imx8mn-kontron-n801x: enable pinctrl_wdog in SPL
From: Peng Fan
Mark pinctrl_wdog as u-boot,dm-spl to clean up board code,
The set_wdog_reset() function is not necessary as this is handled by
the imx_watchdog.c driver due to the 'fsl,ext-reset-output' property
being set.
Signed-off-by: Peng Fan
---
arch/arm/dts/imx8mm-kontron-n801x-u-boot.dtsi | 4
board/kontron/sl-mx8mm/spl.c | 18 --
2 files changed, 4 insertions(+), 18 deletions(-)
diff --git a/arch/arm/dts/imx8mm-kontron-n801x-u-boot.dtsi
b/arch/arm/dts/imx8mm-kontron-n801x-u-boot.dtsi
index 22d18e6f1cf..6882513f161 100644
--- a/arch/arm/dts/imx8mm-kontron-n801x-u-boot.dtsi
+++ b/arch/arm/dts/imx8mm-kontron-n801x-u-boot.dtsi
@@ -126,3 +126,7 @@
{
u-boot,dm-spl;
};
+
+_wdog {
+ u-boot,dm-spl;
+};
diff --git a/board/kontron/sl-mx8mm/spl.c b/board/kontron/sl-mx8mm/spl.c
index a58a75dc958..63361f1d2ab 100644
--- a/board/kontron/sl-mx8mm/spl.c
+++ b/board/kontron/sl-mx8mm/spl.c
@@ -32,7 +32,6 @@ enum {
#define GPIO_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
#define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
-#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
#define TOUCH_RESET_GPIO IMX_GPIO_NR(3, 23)
@@ -50,10 +49,6 @@ static iomux_v3_cfg_t const touch_gpio[] = {
IMX8MM_PAD_SAI5_RXD2_GPIO3_IO23 | MUX_PAD_CTRL(GPIO_PAD_CTRL)
};
-static iomux_v3_cfg_t const wdog_pads[] = {
- IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
-};
-
int spl_board_boot_device(enum boot_device boot_dev_spl)
{
switch (boot_dev_spl) {
@@ -216,17 +211,6 @@ void spl_board_init(void)
printf("Failed to find clock node. Check device tree\n");
}
-int board_early_init_f(void)
-{
- struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
-
- imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
-
- set_wdog_reset(wdog);
-
- return 0;
-}
-
static int power_init_board(void)
{
struct udevice *dev;
@@ -261,8 +245,6 @@ void board_init_f(ulong dummy)
init_uart_clk(2);
- board_early_init_f();
-
timer_init();
/* Clear the BSS. */
--
2.36.0
[PATCH 20/22] imx: imx8mp_rsb7320a1: enable wdog driver model in SPL
From: Peng Fan
Mark wdog1/pinctrl_wdog as u-boot,dm-spl to clean up board code,
The set_wdog_reset() function is not necessary as this is handled by
the imx_watchdog.c driver due to the 'fsl,ext-reset-output' property
being set.
Signed-off-by: Peng Fan
---
arch/arm/dts/imx8mp-rsb3720-a1-u-boot.dtsi | 8
board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c | 12
2 files changed, 8 insertions(+), 12 deletions(-)
diff --git a/arch/arm/dts/imx8mp-rsb3720-a1-u-boot.dtsi
b/arch/arm/dts/imx8mp-rsb3720-a1-u-boot.dtsi
index 2848b24f655..4419967ee42 100644
--- a/arch/arm/dts/imx8mp-rsb3720-a1-u-boot.dtsi
+++ b/arch/arm/dts/imx8mp-rsb3720-a1-u-boot.dtsi
@@ -89,6 +89,14 @@
u-boot,dm-spl;
};
+ {
+ u-boot,dm-spl;
+};
+
+_wdog {
+ u-boot,dm-spl;
+};
+
_i2c1 {
u-boot,dm-spl;
};
diff --git a/board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c
b/board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c
index f129ebd429b..0a1b2c94161 100644
--- a/board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c
+++ b/board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c
@@ -28,12 +28,6 @@
DECLARE_GLOBAL_DATA_PTR;
-#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
-
-static const iomux_v3_cfg_t wdog_pads[] = {
- MX8MP_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
-};
-
#ifdef CONFIG_NAND_MXS
static void setup_gpmi_nand(void)
{
@@ -69,12 +63,6 @@ u8 num_image_type_guids = ARRAY_SIZE(fw_images);
int board_early_init_f(void)
{
- struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
-
- imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
-
- set_wdog_reset(wdog);
-
init_uart_clk(2);
return 0;
--
2.36.0
[PATCH 18/22] imx: imx8mn-beacon: enable pinctrl_wdog in SPL
From: Peng Fan
Mark pinctrl_wdog as u-boot,dm-spl to clean up board code,
The set_wdog_reset() function is not necessary as this is handled by
the imx_watchdog.c driver due to the 'fsl,ext-reset-output' property
being set.
Signed-off-by: Peng Fan
---
arch/arm/dts/imx8mn-beacon-kit-u-boot.dtsi | 4
board/beacon/imx8mn/spl.c | 10 --
2 files changed, 4 insertions(+), 10 deletions(-)
diff --git a/arch/arm/dts/imx8mn-beacon-kit-u-boot.dtsi
b/arch/arm/dts/imx8mn-beacon-kit-u-boot.dtsi
index 69fd69c8d02..eb1dd8debba 100644
--- a/arch/arm/dts/imx8mn-beacon-kit-u-boot.dtsi
+++ b/arch/arm/dts/imx8mn-beacon-kit-u-boot.dtsi
@@ -132,6 +132,10 @@
u-boot,dm-spl;
};
+_wdog {
+ u-boot,dm-spl;
+};
+
{
u-boot-spl-ddr {
filename = "u-boot-spl-ddr.bin";
diff --git a/board/beacon/imx8mn/spl.c b/board/beacon/imx8mn/spl.c
index 4563446db19..029f71bc995 100644
--- a/board/beacon/imx8mn/spl.c
+++ b/board/beacon/imx8mn/spl.c
@@ -68,27 +68,17 @@ int board_fit_config_name_match(const char *name)
}
#endif
-#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
#define PWM1_PAD_CTRL (PAD_CTL_FSEL2 | PAD_CTL_DSE6)
static iomux_v3_cfg_t const pwm_pads[] = {
IMX8MN_PAD_GPIO1_IO01__PWM1_OUT | MUX_PAD_CTRL(PWM1_PAD_CTRL),
};
-static iomux_v3_cfg_t const wdog_pads[] = {
- IMX8MN_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
-};
-
int board_early_init_f(void)
{
- struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
-
/* Claiming pwm pins prevents LCD flicker during startup*/
imx_iomux_v3_setup_multiple_pads(pwm_pads, ARRAY_SIZE(pwm_pads));
- imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
- set_wdog_reset(wdog);
-
init_uart_clk(1);
return 0;
--
2.36.0
[PATCH 19/22] imx: imx8mn_var_som: clean up board watchdog code
From: Peng Fan
pinctrl_wdog already marked u-boot,dm-spl, so clean up board code.
The set_wdog_reset() function is not necessary as this is handled by
the imx_watchdog.c driver due to the 'fsl,ext-reset-output' property
being set.
Signed-off-by: Peng Fan
Tested-by: Ariel D'Alessandro
---
board/variscite/imx8mn_var_som/spl.c | 11 ---
1 file changed, 11 deletions(-)
diff --git a/board/variscite/imx8mn_var_som/spl.c
b/board/variscite/imx8mn_var_som/spl.c
index 1a8b64fc0a9..41e70505774 100644
--- a/board/variscite/imx8mn_var_som/spl.c
+++ b/board/variscite/imx8mn_var_som/spl.c
@@ -40,19 +40,8 @@ void spl_board_init(void)
puts("Failed to find clock node. Check device tree\n");
}
-#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
-
-static const iomux_v3_cfg_t wdog_pads[] = {
- IMX8MN_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
-};
-
int board_early_init_f(void)
{
- struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
-
- imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
- set_wdog_reset(wdog);
-
init_uart_clk(3);
return 0;
--
2.36.0
[PATCH 15/22] imx: imx8mm-cl-iot-gate: enable pinctrl_wdog in SPL
From: Peng Fan
Mark pinctrl_wdog as u-boot,dm-spl to clean up board code,
The set_wdog_reset() function is not necessary as this is handled by
the imx_watchdog.c driver due to the 'fsl,ext-reset-output' property
being set.
Signed-off-by: Peng Fan
---
arch/arm/dts/imx8mm-cl-iot-gate-u-boot.dtsi | 4
board/compulab/imx8mm-cl-iot-gate/spl.c | 19 ---
2 files changed, 4 insertions(+), 19 deletions(-)
diff --git a/arch/arm/dts/imx8mm-cl-iot-gate-u-boot.dtsi
b/arch/arm/dts/imx8mm-cl-iot-gate-u-boot.dtsi
index 433b02cceee..a7044b63699 100644
--- a/arch/arm/dts/imx8mm-cl-iot-gate-u-boot.dtsi
+++ b/arch/arm/dts/imx8mm-cl-iot-gate-u-boot.dtsi
@@ -84,6 +84,10 @@
u-boot,dm-spl;
};
+_wdog {
+ u-boot,dm-spl;
+};
+
{
u-boot,dm-spl;
};
diff --git a/board/compulab/imx8mm-cl-iot-gate/spl.c
b/board/compulab/imx8mm-cl-iot-gate/spl.c
index f183704c9d2..d2d20269ba0 100644
--- a/board/compulab/imx8mm-cl-iot-gate/spl.c
+++ b/board/compulab/imx8mm-cl-iot-gate/spl.c
@@ -83,23 +83,6 @@ int board_fit_config_name_match(const char *name)
}
#endif
-#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
-
-static iomux_v3_cfg_t const wdog_pads[] = {
- IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
-};
-
-int board_early_init_f(void)
-{
- struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
-
- imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
-
- set_wdog_reset(wdog);
-
- return 0;
-}
-
static int power_init_board(void)
{
struct udevice *dev;
@@ -141,8 +124,6 @@ void board_init_f(ulong dummy)
arch_cpu_init();
- board_early_init_f();
-
init_uart_clk(2);
timer_init();
--
2.36.0
[PATCH 14/22] imx: imx8mm_beacon: enable pinctrl_wdog in SPL
From: Peng Fan
Mark pinctrl_wdog as u-boot,dm-spl to clean up board code,
The set_wdog_reset() function is not necessary as this is handled by
the imx_watchdog.c driver due to the 'fsl,ext-reset-output' property
being set.
Signed-off-by: Peng Fan
---
arch/arm/dts/imx8mm-beacon-kit-u-boot.dtsi | 4
board/beacon/imx8mm/spl.c | 19 ---
2 files changed, 4 insertions(+), 19 deletions(-)
diff --git a/arch/arm/dts/imx8mm-beacon-kit-u-boot.dtsi
b/arch/arm/dts/imx8mm-beacon-kit-u-boot.dtsi
index e33e10ac129..c94b4ffa4c3 100644
--- a/arch/arm/dts/imx8mm-beacon-kit-u-boot.dtsi
+++ b/arch/arm/dts/imx8mm-beacon-kit-u-boot.dtsi
@@ -73,6 +73,10 @@
u-boot,dm-spl;
};
+_wdog {
+ u-boot,dm-spl;
+};
+
{
u-boot,dm-spl;
};
diff --git a/board/beacon/imx8mm/spl.c b/board/beacon/imx8mm/spl.c
index f92b4c3ed0a..a93cc938784 100644
--- a/board/beacon/imx8mm/spl.c
+++ b/board/beacon/imx8mm/spl.c
@@ -59,23 +59,6 @@ int board_fit_config_name_match(const char *name)
}
#endif
-#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
-
-static iomux_v3_cfg_t const wdog_pads[] = {
- IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
-};
-
-int board_early_init_f(void)
-{
- struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
-
- imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
-
- set_wdog_reset(wdog);
-
- return 0;
-}
-
static int power_init_board(void)
{
struct udevice *dev;
@@ -116,8 +99,6 @@ void board_init_f(ulong dummy)
init_uart_clk(1);
- board_early_init_f();
-
timer_init();
/* Clear the BSS. */
--
2.36.0
[PATCH 12/22] configs: imx8m: use common imx8m.h for i.MX8MP
From: Peng Fan Some SPL definitions could be generalized, so use imx8m.h for iMX8MP. Tested-by: Tim Harvey #imx8mp-venice-* Signed-off-by: Peng Fan --- include/configs/imx8m.h | 8 include/configs/imx8mp_evk.h | 17 + include/configs/imx8mp_rsb3720.h | 16 +--- include/configs/imx8mp_venice.h | 18 +- include/configs/phycore_imx8mp.h | 16 +--- include/configs/verdin-imx8mp.h | 16 +--- 6 files changed, 13 insertions(+), 78 deletions(-) diff --git a/include/configs/imx8m.h b/include/configs/imx8m.h index 354a9b9fd0d..7894a1c1068 100644 --- a/include/configs/imx8m.h +++ b/include/configs/imx8m.h @@ -34,6 +34,14 @@ #define CONFIG_SYS_SPL_MALLOC_START0x4220 #define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K +#elif defined(CONFIG_IMX8MP) +/*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/ +#define CONFIG_SPL_STACK 0x96 +#define CONFIG_SPL_BSS_START_ADDR 0x0098FC00 +#define CONFIG_SPL_BSS_MAX_SIZE0x400 +#define CONFIG_SYS_SPL_MALLOC_START0x4220 +#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K + #endif #endif #endif diff --git a/include/configs/imx8mp_evk.h b/include/configs/imx8mp_evk.h index 4aac7c81d2e..b54b88a8f67 100644 --- a/include/configs/imx8mp_evk.h +++ b/include/configs/imx8mp_evk.h @@ -6,27 +6,12 @@ #ifndef __IMX8MP_EVK_H #define __IMX8MP_EVK_H -#include -#include -#include +#include #define CONFIG_SYS_BOOTM_LEN (32 * SZ_1M) -#define CONFIG_SPL_MAX_SIZE(152 * 1024) -#define CONFIG_SYS_MONITOR_LEN (512 * 1024) -#define CONFIG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) - #ifdef CONFIG_SPL_BUILD -/*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/ -#define CONFIG_SPL_STACK 0x96 -#define CONFIG_SPL_BSS_START_ADDR 0x0098FC00 -#define CONFIG_SPL_BSS_MAX_SIZE0x400 /* 1 KB */ -#define CONFIG_SYS_SPL_MALLOC_START0x4220 -#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K /* 512 KB */ - - #define CONFIG_POWER_PCA9450 - #endif #if defined(CONFIG_CMD_NET) diff --git a/include/configs/imx8mp_rsb3720.h b/include/configs/imx8mp_rsb3720.h index 7dcc2e16c71..b498aa5be2b 100644 --- a/include/configs/imx8mp_rsb3720.h +++ b/include/configs/imx8mp_rsb3720.h @@ -7,17 +7,11 @@ #ifndef __IMX8MP_RSB3720_H #define __IMX8MP_RSB3720_H -#include -#include -#include +#include #include #define CONFIG_SYS_BOOTM_LEN (32 * SZ_1M) -#define CONFIG_SPL_MAX_SIZE(152 * 1024) -#define CONFIG_SYS_MONITOR_LEN (512 * 1024) -#define CONFIG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) - /* GUIDs for capsule updatable firmware images */ #define IMX8MP_RSB3720A1_4G_FIT_IMAGE_GUID \ EFI_GUID(0xb1251e89, 0x384a, 0x4635, 0xa8, 0x06, \ @@ -28,18 +22,10 @@ 0x5f, 0xd3, 0x6b, 0x9b, 0xe5, 0xb9) #ifdef CONFIG_SPL_BUILD -#define CONFIG_SPL_STACK 0x96 -#define CONFIG_SPL_BSS_START_ADDR 0x0098FC00 -#define CONFIG_SPL_BSS_MAX_SIZE0x400 /* 1 KB */ -#define CONFIG_SYS_SPL_MALLOC_START0x4220 -#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K /* 512 KB */ - #define CONFIG_MALLOC_F_ADDR 0x184000 /* malloc f used before \ * GD_FLG_FULL_MALLOC_INIT \ * set \ */ - - #if defined(CONFIG_NAND_BOOT) #define CONFIG_SPL_NAND_MXS #endif diff --git a/include/configs/imx8mp_venice.h b/include/configs/imx8mp_venice.h index 17400cffc63..fb37f5d399c 100644 --- a/include/configs/imx8mp_venice.h +++ b/include/configs/imx8mp_venice.h @@ -6,23 +6,7 @@ #ifndef __IMX8MP_VENICE_H #define __IMX8MP_VENICE_H -#include -#include - -#define CONFIG_SPL_MAX_SIZE(152 * 1024) -#define CONFIG_SYS_MONITOR_LEN SZ_512K -#define CONFIG_SYS_UBOOT_BASE \ - (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) - -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SPL_STACK 0x96 -#define CONFIG_SPL_BSS_START_ADDR 0x0098FC00 -#define CONFIG_SPL_BSS_MAX_SIZE0x400 /* 1 KB */ -#define CONFIG_SYS_SPL_MALLOC_START0x4220 -#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K /* 512 KB */ - -/* For RAW image gives a error info not panic */ -#endif +#include #define MEM_LAYOUT_ENV_SETTINGS \ "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ diff --git a/include/configs/phycore_imx8mp.h b/include/configs/phycore_imx8mp.h index 95d70bb92d1..eaa91f66bfd 100644 --- a/include/configs/phycore_imx8mp.h +++ b/include/configs/phycore_imx8mp.h @@ -7,26 +7,12 @@ #ifndef __PHYCORE_IMX8MP_H #define __PHYCORE_IMX8MP_H -#include -#include +#include #define CONFIG_SYS_BOOTM_LEN SZ_64M -#define CONFIG_SPL_MAX_SIZE
[PATCH 17/22] imx: imx8mm/n/p-venice: enable pinctrl_wdog in SPL
From: Peng Fan
Mark pinctrl_wdog as u-boot,dm-spl to clean up board code,
The set_wdog_reset() function is not necessary as this is handled by
the imx_watchdog.c driver due to the 'fsl,ext-reset-output' property
being set.
Signed-off-by: Peng Fan
---
arch/arm/dts/imx8mm-venice-u-boot.dtsi | 4
arch/arm/dts/imx8mn-venice-u-boot.dtsi | 4
arch/arm/dts/imx8mp-venice-u-boot.dtsi | 4
board/gateworks/venice/spl.c | 29 --
4 files changed, 12 insertions(+), 29 deletions(-)
diff --git a/arch/arm/dts/imx8mm-venice-u-boot.dtsi
b/arch/arm/dts/imx8mm-venice-u-boot.dtsi
index c61c6de935f..68978a0413e 100644
--- a/arch/arm/dts/imx8mm-venice-u-boot.dtsi
+++ b/arch/arm/dts/imx8mm-venice-u-boot.dtsi
@@ -72,3 +72,7 @@
{
u-boot,dm-spl;
};
+
+_wdog {
+ u-boot,dm-spl;
+};
diff --git a/arch/arm/dts/imx8mn-venice-u-boot.dtsi
b/arch/arm/dts/imx8mn-venice-u-boot.dtsi
index 4f23da35676..35819553879 100644
--- a/arch/arm/dts/imx8mn-venice-u-boot.dtsi
+++ b/arch/arm/dts/imx8mn-venice-u-boot.dtsi
@@ -110,6 +110,10 @@
u-boot,dm-spl;
};
+_wdog {
+ u-boot,dm-spl;
+};
+
{
u-boot-spl-ddr {
align = <4>;
diff --git a/arch/arm/dts/imx8mp-venice-u-boot.dtsi
b/arch/arm/dts/imx8mp-venice-u-boot.dtsi
index 37f3edc9817..96b9fa89cf4 100644
--- a/arch/arm/dts/imx8mp-venice-u-boot.dtsi
+++ b/arch/arm/dts/imx8mp-venice-u-boot.dtsi
@@ -72,3 +72,7 @@
{
u-boot,dm-spl;
};
+
+_wdog {
+ u-boot,dm-spl;
+};
diff --git a/board/gateworks/venice/spl.c b/board/gateworks/venice/spl.c
index 6e6ce015f28..4c0feb4381c 100644
--- a/board/gateworks/venice/spl.c
+++ b/board/gateworks/venice/spl.c
@@ -87,33 +87,6 @@ static void spl_dram_init(int size)
ddr_init(dram_timing);
}
-#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
-
-#ifdef CONFIG_IMX8MM
-static iomux_v3_cfg_t const wdog_pads[] = {
- IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
-};
-#elif CONFIG_IMX8MN
-static const iomux_v3_cfg_t wdog_pads[] = {
- IMX8MN_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
-};
-#elif CONFIG_IMX8MP
-static const iomux_v3_cfg_t wdog_pads[] = {
- MX8MP_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
-};
-#endif
-
-int board_early_init_f(void)
-{
- struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
-
- imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
-
- set_wdog_reset(wdog);
-
- return 0;
-}
-
/*
* Model specific PMIC adjustments necessary prior to DRAM init
*
@@ -253,8 +226,6 @@ void board_init_f(ulong dummy)
init_uart_clk(1);
- board_early_init_f();
-
timer_init();
/* Clear the BSS. */
--
2.36.0
[PATCH 13/22] configs: imx8m: use common imx8m.h for i.MX8MQ
From: Peng Fan Some SPL definitions could be gerneralized, so use imx8m.h for iMX8MQ. Signed-off-by: Peng Fan --- include/configs/imx8m.h | 10 ++ include/configs/imx8mq_cm.h | 24 +--- include/configs/imx8mq_evk.h | 19 +-- include/configs/imx8mq_phanbell.h| 19 ++- include/configs/kontron_pitx_imx8m.h | 19 +-- include/configs/pico-imx8mq.h| 20 +--- 6 files changed, 16 insertions(+), 95 deletions(-) diff --git a/include/configs/imx8m.h b/include/configs/imx8m.h index 7894a1c1068..e0a030cb67e 100644 --- a/include/configs/imx8m.h +++ b/include/configs/imx8m.h @@ -42,6 +42,16 @@ #define CONFIG_SYS_SPL_MALLOC_START0x4220 #define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K +#elif defined(CONFIG_IMX8MQ) +/*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/ +#define CONFIG_SPL_STACK 0x187FF0 +#define CONFIG_SPL_BSS_START_ADDR 0x0018 +#define CONFIG_SPL_BSS_MAX_SIZE0x2000 /* 8 KB */ +#define CONFIG_SYS_SPL_MALLOC_START0x4220 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x8 /* 512 KB */ +#define CONFIG_SYS_SPL_PTE_RAM_BASE0x4158 +/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ +#define CONFIG_MALLOC_F_ADDR 0x182000 #endif #endif #endif diff --git a/include/configs/imx8mq_cm.h b/include/configs/imx8mq_cm.h index 7a9dd962ac2..f8518af83bd 100644 --- a/include/configs/imx8mq_cm.h +++ b/include/configs/imx8mq_cm.h @@ -6,32 +6,10 @@ #ifndef __IMX8M_CM_H #define __IMX8M_CM_H -#include -#include -#include +#include #define CONFIG_SYS_BOOTM_LEN (32 * SZ_1M) -#define CONFIG_SPL_MAX_SIZE(124 * 1024) -#define CONFIG_SYS_MONITOR_LEN (512 * 1024) - -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SPL_STACK 0x187FF0 -#define CONFIG_SPL_BSS_START_ADDR 0x0018 -#define CONFIG_SPL_BSS_MAX_SIZE0x2000 /* 8 KB */ -#define CONFIG_SYS_SPL_MALLOC_START0x4220 -#define CONFIG_SYS_SPL_MALLOC_SIZE0x8 /* 512 KB */ -#define CONFIG_SYS_SPL_PTE_RAM_BASE0x4158 - -/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ -#define CONFIG_MALLOC_F_ADDR 0x182000 -/* For RAW image gives a error info not panic */ - -#endif - -/* ENET Config */ -/* ENET1 */ - #ifndef CONFIG_SPL_BUILD #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 0) \ diff --git a/include/configs/imx8mq_evk.h b/include/configs/imx8mq_evk.h index b7294ebef1e..b0c77630f0f 100644 --- a/include/configs/imx8mq_evk.h +++ b/include/configs/imx8mq_evk.h @@ -6,28 +6,11 @@ #ifndef __IMX8M_EVK_H #define __IMX8M_EVK_H -#include -#include -#include +#include #define CONFIG_SYS_BOOTM_LEN (64 * SZ_1M) -#define CONFIG_SPL_MAX_SIZE(124 * 1024) -#define CONFIG_SYS_MONITOR_LEN (512 * 1024) - #ifdef CONFIG_SPL_BUILD -/*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/ -#define CONFIG_SPL_STACK 0x187FF0 -#define CONFIG_SPL_BSS_START_ADDR 0x0018 -#define CONFIG_SPL_BSS_MAX_SIZE0x2000 /* 8 KB */ -#define CONFIG_SYS_SPL_MALLOC_START0x4220 -#define CONFIG_SYS_SPL_MALLOC_SIZE0x8 /* 512 KB */ -#define CONFIG_SYS_SPL_PTE_RAM_BASE0x4158 - -/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ -#define CONFIG_MALLOC_F_ADDR 0x182000 -/* For RAW image gives a error info not panic */ - #define CONFIG_POWER_PFUZE100 #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 #endif diff --git a/include/configs/imx8mq_phanbell.h b/include/configs/imx8mq_phanbell.h index 93e531b66fd..f9c39aa82c7 100644 --- a/include/configs/imx8mq_phanbell.h +++ b/include/configs/imx8mq_phanbell.h @@ -6,25 +6,10 @@ #ifndef __IMX8M_PHANBELL_H #define __IMX8M_PHANBELL_H -#include -#include +#include +#undef CONFIG_SPL_MAX_SIZE #define CONFIG_SPL_MAX_SIZE(172 * 1024) -#define CONFIG_SYS_MONITOR_LEN (512 * 1024) - -#ifdef CONFIG_SPL_BUILD -/*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/ -#define CONFIG_SPL_STACK 0x187FF0 -#define CONFIG_SPL_BSS_START_ADDR 0x0018 -#define CONFIG_SPL_BSS_MAX_SIZE0x2000 /* 8 KB */ -#define CONFIG_SYS_SPL_MALLOC_START0x4220 -#define CONFIG_SYS_SPL_MALLOC_SIZE0x8 /* 512 KB */ -#define CONFIG_SYS_SPL_PTE_RAM_BASE0x4158 - -/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ -#define CONFIG_MALLOC_F_ADDR 0x182000 -/* For RAW image gives a error info not panic */ -#endif /* ENET Config */ /* ENET1 */ diff --git a/include/configs/kontron_pitx_imx8m.h b/include/configs/kontron_pitx_imx8m.h index 9089b76d26e..2abaf07f1a6 100644 --- a/include/configs/kontron_pitx_imx8m.h +++ b/include/configs/kontron_pitx_imx8m.h @@ -3,33 +3,16 @@ #ifndef __KONTRON_PITX_IMX8M_H #define __KONTRON_PITX_IMX8M_H -#include -#include -#include +#include #define CONFIG_SYS_BOOTM_LEN (32 * SZ_1M)
[PATCH 11/22] configs: imx8m: use common imx8m.h for i.MX8MN
From: Peng Fan Some SPL definitions could be generalized, so use imx8m.h for iMX8MN. Tested-by: Tim Harvey #imx8mn-venice-* Tested-by: Ariel D'Alessandro #i.MX8MN BSH SMM S2 PRO board Signed-off-by: Peng Fan --- include/configs/imx8m.h| 10 ++ include/configs/imx8mn_bsh_smm_s2_common.h | 17 + include/configs/imx8mn_evk.h | 20 +--- include/configs/imx8mn_var_som.h | 15 +-- include/configs/imx8mn_venice.h| 18 +- 5 files changed, 14 insertions(+), 66 deletions(-) diff --git a/include/configs/imx8m.h b/include/configs/imx8m.h index cb8ce5689ac..354a9b9fd0d 100644 --- a/include/configs/imx8m.h +++ b/include/configs/imx8m.h @@ -16,6 +16,8 @@ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) #ifdef CONFIG_SPL_BUILD + +#ifdef CONFIG_IMX8MM #define CONFIG_SPL_STACK 0x92 #define CONFIG_SPL_BSS_START_ADDR 0x91 #define CONFIG_SPL_BSS_MAX_SIZESZ_8K @@ -25,5 +27,13 @@ /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ #define CONFIG_MALLOC_F_ADDR 0x93 +#elif defined(CONFIG_IMX8MN) +#define CONFIG_SPL_STACK 0x98 +#define CONFIG_SPL_BSS_START_ADDR 0x95 +#define CONFIG_SPL_BSS_MAX_SIZESZ_8K +#define CONFIG_SYS_SPL_MALLOC_START0x4220 +#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K + +#endif #endif #endif diff --git a/include/configs/imx8mn_bsh_smm_s2_common.h b/include/configs/imx8mn_bsh_smm_s2_common.h index 57be38d9433..eb210dc597b 100644 --- a/include/configs/imx8mn_bsh_smm_s2_common.h +++ b/include/configs/imx8mn_bsh_smm_s2_common.h @@ -6,25 +6,10 @@ #ifndef __IMX8MN_BSH_SMM_S2_COMMON_H #define __IMX8MN_BSH_SMM_S2_COMMON_H -#include -#include -#include +#include #define CONFIG_SYS_BOOTM_LEN (32 * SZ_1M) -#define CONFIG_SPL_MAX_SIZE(148 * SZ_1K) -#define CONFIG_SYS_MONITOR_LEN SZ_512K -#define CONFIG_SYS_UBOOT_BASE \ - (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) - -#define CONFIG_SPL_STACK 0x98 -#define CONFIG_SPL_BSS_START_ADDR 0x95 -#define CONFIG_SPL_BSS_MAX_SIZESZ_8K -#define CONFIG_SYS_SPL_MALLOC_START0x4220 -#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K - - - #define MEM_LAYOUT_ENV_SETTINGS \ "scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ diff --git a/include/configs/imx8mn_evk.h b/include/configs/imx8mn_evk.h index 0b2eefa6368..902e0f8434f 100644 --- a/include/configs/imx8mn_evk.h +++ b/include/configs/imx8mn_evk.h @@ -6,28 +6,10 @@ #ifndef __IMX8MN_EVK_H #define __IMX8MN_EVK_H -#include -#include -#include +#include #define CONFIG_SYS_BOOTM_LEN (32 * SZ_1M) -#define CONFIG_SPL_MAX_SIZE(148 * 1024) -#define CONFIG_SYS_MONITOR_LEN SZ_512K -#define CONFIG_SYS_UBOOT_BASE \ - (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) - -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SPL_STACK 0x98 -#define CONFIG_SPL_BSS_START_ADDR 0x95 -#define CONFIG_SPL_BSS_MAX_SIZESZ_8K /* 8 KB */ -#define CONFIG_SYS_SPL_MALLOC_START0x4220 -#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K /* 512 KB */ - -/* For RAW image gives a error info not panic */ - -#endif - #ifndef CONFIG_SPL_BUILD #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 1) \ diff --git a/include/configs/imx8mn_var_som.h b/include/configs/imx8mn_var_som.h index 6ce60b0d704..fc9c4ca4530 100644 --- a/include/configs/imx8mn_var_som.h +++ b/include/configs/imx8mn_var_som.h @@ -6,23 +6,10 @@ #ifndef __IMX8MN_VAR_SOM_H #define __IMX8MN_VAR_SOM_H -#include -#include -#include +#include #define CONFIG_SYS_BOOTM_LEN (32 * SZ_1M) -#define CONFIG_SPL_MAX_SIZE(148 * SZ_1K) -#define CONFIG_SYS_MONITOR_LEN SZ_512K -#define CONFIG_SYS_UBOOT_BASE \ - (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) - -#define CONFIG_SPL_STACK 0x98 -#define CONFIG_SPL_BSS_START_ADDR 0x95 -#define CONFIG_SPL_BSS_MAX_SIZESZ_8K -#define CONFIG_SYS_SPL_MALLOC_START0x4220 -#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K - #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 1) \ func(MMC, mmc, 2) \ diff --git a/include/configs/imx8mn_venice.h b/include/configs/imx8mn_venice.h index 160ba9648db..d122a5a5a79 100644 --- a/include/configs/imx8mn_venice.h +++ b/include/configs/imx8mn_venice.h @@ -6,23 +6,7 @@ #ifndef __IMX8MM_VENICE_H #define __IMX8MM_VENICE_H -#include -#include - -#define CONFIG_SPL_MAX_SIZE(148 * 1024) -#define CONFIG_SYS_MONITOR_LEN SZ_512K -#define CONFIG_SYS_UBOOT_BASE \ - (QSPI0_AMBA_BASE +
[PATCH 10/22] configs: imx8m: use common imx8m.h for i.MX8MM
From: Peng Fan Some SPL definitions could be generalized, so use imx8m.h for that. i.MX8MN/Q/P will follow up. Signed-off-by: Peng Fan Tested-by: Tim Harvey #imx8mm-venice-* --- include/configs/imx8m.h | 29 + include/configs/imx8mm-cl-iot-gate.h| 17 ++-- include/configs/imx8mm_beacon.h | 21 +-- include/configs/imx8mm_data_modul_edm_sbc.h | 16 +++- include/configs/imx8mm_evk.h| 21 +-- include/configs/imx8mm_icore_mx8mm.h| 20 +- include/configs/imx8mm_venice.h | 18 ++--- include/configs/kontron-sl-mx8mm.h | 14 +- include/configs/phycore_imx8mm.h| 20 +- include/configs/verdin-imx8mm.h | 20 +- 10 files changed, 42 insertions(+), 154 deletions(-) create mode 100644 include/configs/imx8m.h diff --git a/include/configs/imx8m.h b/include/configs/imx8m.h new file mode 100644 index 000..cb8ce5689ac --- /dev/null +++ b/include/configs/imx8m.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2022 NXP + */ + +#ifndef __IMX8MM_H +#define __IMX8MM_H + +#include +#include +#include + +#define CONFIG_SPL_MAX_SIZE(172 * 1024) +#define CONFIG_SYS_MONITOR_LEN SZ_512K +#define CONFIG_SYS_UBOOT_BASE \ + (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SPL_STACK 0x92 +#define CONFIG_SPL_BSS_START_ADDR 0x91 +#define CONFIG_SPL_BSS_MAX_SIZESZ_8K +#define CONFIG_SYS_SPL_MALLOC_START0x4220 +#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K + +/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ +#define CONFIG_MALLOC_F_ADDR 0x93 + +#endif +#endif diff --git a/include/configs/imx8mm-cl-iot-gate.h b/include/configs/imx8mm-cl-iot-gate.h index cbb27db6be0..cbf33a76a09 100644 --- a/include/configs/imx8mm-cl-iot-gate.h +++ b/include/configs/imx8mm-cl-iot-gate.h @@ -6,28 +6,15 @@ #ifndef __IMX8MM_CL_IOT_GATE_H #define __IMX8MM_CL_IOT_GATE_H -#include -#include -#include +#include #include #define CONFIG_SYS_BOOTM_LEN (32 * SZ_1M) -#define CONFIG_SPL_MAX_SIZE(148 * 1024) -#define CONFIG_SYS_MONITOR_LEN SZ_512K -#define CONFIG_SYS_UBOOT_BASE \ - (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) #ifdef CONFIG_SPL_BUILD -#define CONFIG_SPL_STACK 0x92 -#define CONFIG_SPL_BSS_START_ADDR 0x91 -#define CONFIG_SPL_BSS_MAX_SIZESZ_8K /* 8 KB */ -#define CONFIG_SYS_SPL_MALLOC_START0x4220 -#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K /* 512 KB */ - +#undef CONFIG_MALLOC_F_ADDR /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ #define CONFIG_MALLOC_F_ADDR 0x912000 -/* For RAW image gives a error info not panic */ - #endif /* GUIDs for capsule updatable firmware images */ diff --git a/include/configs/imx8mm_beacon.h b/include/configs/imx8mm_beacon.h index a9ca13a9da4..c73188a16f2 100644 --- a/include/configs/imx8mm_beacon.h +++ b/include/configs/imx8mm_beacon.h @@ -6,26 +6,7 @@ #ifndef __IMX8MM_BEACON_H #define __IMX8MM_BEACON_H -#include -#include - -#define CONFIG_SPL_MAX_SIZE(148 * 1024) -#define CONFIG_SYS_MONITOR_LEN SZ_512K -#define CONFIG_SYS_UBOOT_BASE \ - (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) - -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SPL_STACK 0x92 -#define CONFIG_SPL_BSS_START_ADDR 0x91 -#define CONFIG_SPL_BSS_MAX_SIZESZ_8K /* 8 KB */ -#define CONFIG_SYS_SPL_MALLOC_START0x4220 -#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K /* 512 KB */ - -/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ -#define CONFIG_MALLOC_F_ADDR 0x93 -/* For RAW image gives a error info not panic */ - -#endif +#include /* Initial environment variables */ #define CONFIG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/imx8mm_data_modul_edm_sbc.h b/include/configs/imx8mm_data_modul_edm_sbc.h index 2f3608835a2..e098cddf967 100644 --- a/include/configs/imx8mm_data_modul_edm_sbc.h +++ b/include/configs/imx8mm_data_modul_edm_sbc.h @@ -6,26 +6,16 @@ #ifndef __IMX8MM_DATA_MODUL_EDM_SBC_H #define __IMX8MM_DATA_MODUL_EDM_SBC_H -#include -#include -#include +#include #define CONFIG_SYS_BOOTM_LEN SZ_128M -#define CONFIG_SPL_MAX_SIZE(148 * 1024) +#undef CONFIG_SYS_MONITOR_LEN #define CONFIG_SYS_MONITOR_LEN SZ_1M -#define CONFIG_SPL_STACK 0x92 #ifdef CONFIG_SPL_BUILD -#define CONFIG_SPL_BSS_START_ADDR 0x91 -#define CONFIG_SPL_BSS_MAX_SIZESZ_8K /* 8 kiB */ -#define CONFIG_SYS_SPL_MALLOC_START0x4220 +#undef CONFIG_SYS_SPL_MALLOC_SIZE #define CONFIG_SYS_SPL_MALLOC_SIZE SZ_16M /* 16 MiB */ -
[PATCH 09/22] configs: drop CONFIG_SPL_ABORT_ON_RAW_IMAGE
From: Peng Fan CONFIG_SPL_RAW_IMAGE_SUPPORT default y has been used to replace CONFIG_SPL_ABORT_ON_RAW_IMAGE for quite some time, so drop CONFIG_SPL_ABORT_ON_RAW_IMAGE. Signed-off-by: Peng Fan --- include/configs/capricorn-common.h | 1 - include/configs/cgtqmx8.h | 1 - include/configs/imx8mm-cl-iot-gate.h| 1 - include/configs/imx8mm_beacon.h | 1 - include/configs/imx8mm_data_modul_edm_sbc.h | 1 - include/configs/imx8mm_evk.h| 1 - include/configs/imx8mm_icore_mx8mm.h| 1 - include/configs/imx8mm_venice.h | 1 - include/configs/imx8mn_beacon.h | 1 - include/configs/imx8mn_evk.h| 1 - include/configs/imx8mn_venice.h | 1 - include/configs/imx8mp_evk.h| 1 - include/configs/imx8mp_rsb3720.h| 1 - include/configs/imx8mp_venice.h | 1 - include/configs/imx8mq_cm.h | 1 - include/configs/imx8mq_evk.h| 1 - include/configs/imx8mq_phanbell.h | 1 - include/configs/imx8qm_mek.h| 1 - include/configs/imx8qxp_mek.h | 1 - include/configs/imx8ulp_evk.h | 1 - include/configs/kontron_pitx_imx8m.h| 1 - include/configs/phycore_imx8mm.h| 1 - include/configs/phycore_imx8mp.h| 1 - include/configs/pico-imx8mq.h | 1 - include/configs/verdin-imx8mm.h | 1 - include/configs/verdin-imx8mp.h | 1 - 26 files changed, 26 deletions(-) diff --git a/include/configs/capricorn-common.h b/include/configs/capricorn-common.h index 364bd50b591..aa4c9818638 100644 --- a/include/configs/capricorn-common.h +++ b/include/configs/capricorn-common.h @@ -26,7 +26,6 @@ #define CONFIG_MALLOC_F_ADDR 0x0012 #define CONFIG_SPL_RAW_IMAGE_ARM_TRUSTED_FIRMWARE -#define CONFIG_SPL_ABORT_ON_RAW_IMAGE #endif /* CONFIG_SPL_BUILD */ diff --git a/include/configs/cgtqmx8.h b/include/configs/cgtqmx8.h index 4c04bbf6447..eee6e735b1f 100644 --- a/include/configs/cgtqmx8.h +++ b/include/configs/cgtqmx8.h @@ -25,7 +25,6 @@ #define CONFIG_SPL_RAW_IMAGE_ARM_TRUSTED_FIRMWARE -#define CONFIG_SPL_ABORT_ON_RAW_IMAGE #endif /* Flat Device Tree Definitions */ diff --git a/include/configs/imx8mm-cl-iot-gate.h b/include/configs/imx8mm-cl-iot-gate.h index f262ab08f04..cbb27db6be0 100644 --- a/include/configs/imx8mm-cl-iot-gate.h +++ b/include/configs/imx8mm-cl-iot-gate.h @@ -27,7 +27,6 @@ /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ #define CONFIG_MALLOC_F_ADDR 0x912000 /* For RAW image gives a error info not panic */ -#define CONFIG_SPL_ABORT_ON_RAW_IMAGE #endif diff --git a/include/configs/imx8mm_beacon.h b/include/configs/imx8mm_beacon.h index 4c9b5491f78..a9ca13a9da4 100644 --- a/include/configs/imx8mm_beacon.h +++ b/include/configs/imx8mm_beacon.h @@ -24,7 +24,6 @@ /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ #define CONFIG_MALLOC_F_ADDR 0x93 /* For RAW image gives a error info not panic */ -#define CONFIG_SPL_ABORT_ON_RAW_IMAGE #endif diff --git a/include/configs/imx8mm_data_modul_edm_sbc.h b/include/configs/imx8mm_data_modul_edm_sbc.h index 67667dd523d..2f3608835a2 100644 --- a/include/configs/imx8mm_data_modul_edm_sbc.h +++ b/include/configs/imx8mm_data_modul_edm_sbc.h @@ -25,7 +25,6 @@ #define CONFIG_MALLOC_F_ADDR 0x93 /* For RAW image gives a error info not panic */ -#define CONFIG_SPL_ABORT_ON_RAW_IMAGE #endif diff --git a/include/configs/imx8mm_evk.h b/include/configs/imx8mm_evk.h index 002b2e68bba..d216455ebd9 100644 --- a/include/configs/imx8mm_evk.h +++ b/include/configs/imx8mm_evk.h @@ -26,7 +26,6 @@ /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ #define CONFIG_MALLOC_F_ADDR 0x93 /* For RAW image gives a error info not panic */ -#define CONFIG_SPL_ABORT_ON_RAW_IMAGE #endif diff --git a/include/configs/imx8mm_icore_mx8mm.h b/include/configs/imx8mm_icore_mx8mm.h index 1a439370c09..34993cafdaf 100644 --- a/include/configs/imx8mm_icore_mx8mm.h +++ b/include/configs/imx8mm_icore_mx8mm.h @@ -25,7 +25,6 @@ /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ # define CONFIG_MALLOC_F_ADDR 0x93 /* For RAW image gives a error info not panic */ -# define CONFIG_SPL_ABORT_ON_RAW_IMAGE #endif /* CONFIG_SPL_BUILD */ #ifndef CONFIG_SPL_BUILD diff --git a/include/configs/imx8mm_venice.h b/include/configs/imx8mm_venice.h index 90e8941a254..75f7dae8349 100644 --- a/include/configs/imx8mm_venice.h +++ b/include/configs/imx8mm_venice.h @@ -24,7 +24,6 @@ /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ #define CONFIG_MALLOC_F_ADDR 0x93 /* For RAW image gives a error info not panic */ -#define CONFIG_SPL_ABORT_ON_RAW_IMAGE #endif diff --git a/include/configs/imx8mn_beacon.h b/include/configs/imx8mn_beacon.h index c16dda5e22c..57b99d5a110 100644 ---
[PATCH 08/22] imx: kontron-sl-mx8mm: enable DM_SERIAL
From: Peng Fan
Enable CONFIG_DM_SERIAL. uart and its pinmux was already
marked with u-boot,dm-spl.
Move preloader_console_init after spl_init to make sure driver
model work.
Signed-off-by: Peng Fan
Acked-by: Frieder Schrempf
Reviewed-by: Fabio Estevam
---
board/kontron/sl-mx8mm/spl.c | 12 ++--
configs/kontron-sl-mx8mm_defconfig | 1 +
include/configs/kontron-sl-mx8mm.h | 1 -
3 files changed, 3 insertions(+), 11 deletions(-)
diff --git a/board/kontron/sl-mx8mm/spl.c b/board/kontron/sl-mx8mm/spl.c
index 4ef03c8c172..a58a75dc958 100644
--- a/board/kontron/sl-mx8mm/spl.c
+++ b/board/kontron/sl-mx8mm/spl.c
@@ -32,7 +32,6 @@ enum {
#define GPIO_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
#define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
-#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
#define TOUCH_RESET_GPIO IMX_GPIO_NR(3, 23)
@@ -51,11 +50,6 @@ static iomux_v3_cfg_t const touch_gpio[] = {
IMX8MM_PAD_SAI5_RXD2_GPIO3_IO23 | MUX_PAD_CTRL(GPIO_PAD_CTRL)
};
-static iomux_v3_cfg_t const uart_pads[] = {
- IMX8MM_PAD_UART3_RXD_UART3_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
- IMX8MM_PAD_UART3_TXD_UART3_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
-};
-
static iomux_v3_cfg_t const wdog_pads[] = {
IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
};
@@ -230,8 +224,6 @@ int board_early_init_f(void)
set_wdog_reset(wdog);
- imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
-
return 0;
}
@@ -273,8 +265,6 @@ void board_init_f(ulong dummy)
timer_init();
- preloader_console_init();
-
/* Clear the BSS. */
memset(__bss_start, 0, __bss_end - __bss_start);
@@ -284,6 +274,8 @@ void board_init_f(ulong dummy)
hang();
}
+ preloader_console_init();
+
enable_tzc380();
/* PMIC initialization */
diff --git a/configs/kontron-sl-mx8mm_defconfig
b/configs/kontron-sl-mx8mm_defconfig
index f07b7890a0c..1abbbf41f5f 100644
--- a/configs/kontron-sl-mx8mm_defconfig
+++ b/configs/kontron-sl-mx8mm_defconfig
@@ -103,6 +103,7 @@ CONFIG_DM_REGULATOR=y
CONFIG_DM_RTC=y
CONFIG_RTC_RV8803=y
CONFIG_CONS_INDEX=2
+CONFIG_DM_SERIAL=y
CONFIG_MXC_UART=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
diff --git a/include/configs/kontron-sl-mx8mm.h
b/include/configs/kontron-sl-mx8mm.h
index 231571b05eb..10f06e66836 100644
--- a/include/configs/kontron-sl-mx8mm.h
+++ b/include/configs/kontron-sl-mx8mm.h
@@ -28,7 +28,6 @@
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
/* Board and environment settings */
-#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(3)
#define CONFIG_HOSTNAME"kontron-mx8mm"
#ifdef CONFIG_USB_EHCI_HCD
--
2.36.0
[PATCH 05/22] imx: imx8mm_icore: Enable SPL_DM_SERIAL
From: Peng Fan
Enable CONFIG_SPL_DM_SERIAL. uart2 and its pinmux was already
marked with u-boot,dm-spl.
Move preloader_console_init after spl_early_init to make sure driver
model work.
Signed-off-by: Peng Fan
Reviewed-by: Fabio Estevam
---
board/engicam/imx8mm/spl.c| 14 +++---
configs/imx8mm-icore-mx8mm-ctouch2_defconfig | 1 -
configs/imx8mm-icore-mx8mm-edimm2.2_defconfig | 1 -
include/configs/imx8mm_icore_mx8mm.h | 3 ---
4 files changed, 3 insertions(+), 16 deletions(-)
diff --git a/board/engicam/imx8mm/spl.c b/board/engicam/imx8mm/spl.c
index f9be769ec59..f75f2dc634c 100644
--- a/board/engicam/imx8mm/spl.c
+++ b/board/engicam/imx8mm/spl.c
@@ -54,19 +54,11 @@ int board_fit_config_name_match(const char *name)
}
#endif
-#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
-static iomux_v3_cfg_t const uart_pads[] = {
- IMX8MM_PAD_UART2_RXD_UART2_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
- IMX8MM_PAD_UART2_TXD_UART2_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
-};
-
int board_early_init_f(void)
{
- imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
-
- return 0;
+ return 0;
}
void board_init_f(ulong dummy)
@@ -81,8 +73,6 @@ void board_init_f(ulong dummy)
timer_init();
- preloader_console_init();
-
/* Clear the BSS. */
memset(__bss_start, 0, __bss_end - __bss_start);
@@ -92,6 +82,8 @@ void board_init_f(ulong dummy)
hang();
}
+ preloader_console_init();
+
enable_tzc380();
/* DDR initialization */
diff --git a/configs/imx8mm-icore-mx8mm-ctouch2_defconfig
b/configs/imx8mm-icore-mx8mm-ctouch2_defconfig
index 535ff6dcba5..d95a74a7237 100644
--- a/configs/imx8mm-icore-mx8mm-ctouch2_defconfig
+++ b/configs/imx8mm-icore-mx8mm-ctouch2_defconfig
@@ -74,7 +74,6 @@ CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_CONS_INDEX=2
CONFIG_DM_SERIAL=y
-# CONFIG_SPL_DM_SERIAL is not set
CONFIG_MXC_UART=y
CONFIG_SYSRESET=y
CONFIG_SPL_SYSRESET=y
diff --git a/configs/imx8mm-icore-mx8mm-edimm2.2_defconfig
b/configs/imx8mm-icore-mx8mm-edimm2.2_defconfig
index 101d5a00bc7..43c697a39d8 100644
--- a/configs/imx8mm-icore-mx8mm-edimm2.2_defconfig
+++ b/configs/imx8mm-icore-mx8mm-edimm2.2_defconfig
@@ -74,7 +74,6 @@ CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_CONS_INDEX=2
CONFIG_DM_SERIAL=y
-# CONFIG_SPL_DM_SERIAL is not set
CONFIG_MXC_UART=y
CONFIG_SYSRESET=y
CONFIG_SPL_SYSRESET=y
diff --git a/include/configs/imx8mm_icore_mx8mm.h
b/include/configs/imx8mm_icore_mx8mm.h
index b9b24a8c51d..1a439370c09 100644
--- a/include/configs/imx8mm_icore_mx8mm.h
+++ b/include/configs/imx8mm_icore_mx8mm.h
@@ -65,9 +65,6 @@
#define PHYS_SDRAM_SIZESZ_2G /* 2GB DDR */
#define CONFIG_SYS_BOOTM_LEN SZ_256M
-/* UART */
-#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(2)
-
/* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE 2048
#define CONFIG_SYS_MAXARGS 64
--
2.36.0
[PATCH 07/22] imx: imx8mn_var_som: enable DM_SERIAL
From: Peng Fan
Enable CONFIG_DM_SERIAL. uart and its pinmux was already
marked with u-boot,dm-spl.
Move preloader_console_init after spl_init to make sure driver
model work.
Signed-off-by: Peng Fan
Reviewed-by: Ariel D'Alessandro
Reviewed-by: Fabio Estevam
---
board/variscite/imx8mn_var_som/spl.c | 11 ++-
configs/imx8mn_var_som_defconfig | 1 +
include/configs/imx8mn_var_som.h | 2 --
3 files changed, 3 insertions(+), 11 deletions(-)
diff --git a/board/variscite/imx8mn_var_som/spl.c
b/board/variscite/imx8mn_var_som/spl.c
index 32703c5f0b3..1a8b64fc0a9 100644
--- a/board/variscite/imx8mn_var_som/spl.c
+++ b/board/variscite/imx8mn_var_som/spl.c
@@ -40,14 +40,8 @@ void spl_board_init(void)
puts("Failed to find clock node. Check device tree\n");
}
-#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
-static const iomux_v3_cfg_t uart_pads[] = {
- IMX8MN_PAD_UART4_RXD__UART4_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
- IMX8MN_PAD_UART4_TXD__UART4_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
-};
-
static const iomux_v3_cfg_t wdog_pads[] = {
IMX8MN_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
};
@@ -59,7 +53,6 @@ int board_early_init_f(void)
imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
set_wdog_reset(wdog);
- imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
init_uart_clk(3);
return 0;
@@ -78,14 +71,14 @@ void board_init_f(ulong dummy)
timer_init();
- preloader_console_init();
-
ret = spl_init();
if (ret) {
debug("spl_init() failed: %d\n", ret);
hang();
}
+ preloader_console_init();
+
/* DDR initialization */
spl_dram_init();
diff --git a/configs/imx8mn_var_som_defconfig b/configs/imx8mn_var_som_defconfig
index 5ec82f2a926..39209f62c46 100644
--- a/configs/imx8mn_var_som_defconfig
+++ b/configs/imx8mn_var_som_defconfig
@@ -83,6 +83,7 @@ CONFIG_SPL_DM_PMIC_BD71837=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_SERIAL=y
CONFIG_MXC_UART=y
CONFIG_SYSRESET=y
CONFIG_SYSRESET_PSCI=y
diff --git a/include/configs/imx8mn_var_som.h b/include/configs/imx8mn_var_som.h
index 00358892b28..6ce60b0d704 100644
--- a/include/configs/imx8mn_var_som.h
+++ b/include/configs/imx8mn_var_som.h
@@ -64,8 +64,6 @@
#define PHYS_SDRAM 0x4000
#define PHYS_SDRAM_SIZESZ_1G /* 1GB DDR */
-#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(4)
-
/* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE SZ_2K
#define CONFIG_SYS_MAXARGS 64
--
2.36.0
[PATCH 06/22] imx: imx8m[m/p]_phycore: Enable DM_SERIAL
From: Peng Fan
Enable CONFIG_DM_SERIAL. uart and its pinmux was already
marked with u-boot,dm-spl.
Move preloader_console_init after spl_early_init to make sure driver
model work.
Signed-off-by: Peng Fan
Tested-by: Teresa Remmet
Reviewed-by: Fabio Estevam
---
board/phytec/phycore_imx8mm/spl.c | 12 ++--
board/phytec/phycore_imx8mp/spl.c | 8
configs/phycore-imx8mm_defconfig | 1 +
configs/phycore-imx8mp_defconfig | 1 +
include/configs/phycore_imx8mm.h | 3 ---
include/configs/phycore_imx8mp.h | 3 ---
6 files changed, 4 insertions(+), 24 deletions(-)
diff --git a/board/phytec/phycore_imx8mm/spl.c
b/board/phytec/phycore_imx8mm/spl.c
index d54145ef995..7f24a3affc8 100644
--- a/board/phytec/phycore_imx8mm/spl.c
+++ b/board/phytec/phycore_imx8mm/spl.c
@@ -57,14 +57,8 @@ int board_fit_config_name_match(const char *name)
return 0;
}
-#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE)
-static iomux_v3_cfg_t const uart_pads[] = {
- IMX8MM_PAD_UART3_RXD_UART3_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
- IMX8MM_PAD_UART3_TXD_UART3_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
-};
-
static iomux_v3_cfg_t const wdog_pads[] = {
IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
};
@@ -77,8 +71,6 @@ int board_early_init_f(void)
set_wdog_reset(wdog);
- imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
-
return 0;
}
@@ -92,8 +84,6 @@ void board_init_f(ulong dummy)
board_early_init_f();
- preloader_console_init();
-
/* Clear the BSS. */
memset(__bss_start, 0, __bss_end - __bss_start);
@@ -103,6 +93,8 @@ void board_init_f(ulong dummy)
hang();
}
+ preloader_console_init();
+
enable_tzc380();
/* DDR initialization */
diff --git a/board/phytec/phycore_imx8mp/spl.c
b/board/phytec/phycore_imx8mp/spl.c
index 19c486e5517..38a581bef57 100644
--- a/board/phytec/phycore_imx8mp/spl.c
+++ b/board/phytec/phycore_imx8mp/spl.c
@@ -89,14 +89,8 @@ int board_fit_config_name_match(const char *name)
return 0;
}
-#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
-static iomux_v3_cfg_t const uart_pads[] = {
- MX8MP_PAD_UART1_RXD__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
- MX8MP_PAD_UART1_TXD__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
-};
-
static iomux_v3_cfg_t const wdog_pads[] = {
MX8MP_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
};
@@ -109,8 +103,6 @@ int board_early_init_f(void)
set_wdog_reset(wdog);
- imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
-
return 0;
}
diff --git a/configs/phycore-imx8mm_defconfig b/configs/phycore-imx8mm_defconfig
index ba5833f7060..9da222afc54 100644
--- a/configs/phycore-imx8mm_defconfig
+++ b/configs/phycore-imx8mm_defconfig
@@ -107,6 +107,7 @@ CONFIG_PINCTRL_IMX8M=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_SERIAL=y
CONFIG_MXC_UART=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
diff --git a/configs/phycore-imx8mp_defconfig b/configs/phycore-imx8mp_defconfig
index 86d0f4df7f6..a851b1bdccb 100644
--- a/configs/phycore-imx8mp_defconfig
+++ b/configs/phycore-imx8mp_defconfig
@@ -98,6 +98,7 @@ CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_SPL_POWER_I2C=y
+CONFIG_DM_SERIAL=y
CONFIG_MXC_UART=y
CONFIG_SYSRESET=y
CONFIG_SPL_SYSRESET=y
diff --git a/include/configs/phycore_imx8mm.h b/include/configs/phycore_imx8mm.h
index 46fadd56106..564b8125ba3 100644
--- a/include/configs/phycore_imx8mm.h
+++ b/include/configs/phycore_imx8mm.h
@@ -83,9 +83,6 @@
#define PHYS_SDRAM 0x4000
#define PHYS_SDRAM_SIZE SZ_2G /* 2GB DDR */
-/* UART */
-#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(3)
-
/* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE SZ_2K
#define CONFIG_SYS_MAXARGS 64
diff --git a/include/configs/phycore_imx8mp.h b/include/configs/phycore_imx8mp.h
index eb92c423392..3e4315f2b81 100644
--- a/include/configs/phycore_imx8mp.h
+++ b/include/configs/phycore_imx8mp.h
@@ -83,9 +83,6 @@
#define PHYS_SDRAM 0x4000
#define PHYS_SDRAM_SIZE0x8000
-/* UART */
-#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(1)
-
/* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE SZ_2K
#define CONFIG_SYS_MAXARGS 64
--
2.36.0
[PATCH 04/22] imx: imx8mm-cl-iot-gate: Enable DM_SERIAL
From: Peng Fan
Enable CONFIG_DM_SERIAL. uart3 and its pinmux was already
marked with u-boot,dm-spl.
Move preloader_console_init after spl_early_init to make sure driver
model work.
Signed-off-by: Peng Fan
Reviewed-by: Fabio Estevam
---
board/compulab/imx8mm-cl-iot-gate/spl.c| 12 ++--
configs/imx8mm-cl-iot-gate-optee_defconfig | 1 +
configs/imx8mm-cl-iot-gate_defconfig | 1 +
include/configs/imx8mm-cl-iot-gate.h | 2 --
4 files changed, 4 insertions(+), 12 deletions(-)
diff --git a/board/compulab/imx8mm-cl-iot-gate/spl.c
b/board/compulab/imx8mm-cl-iot-gate/spl.c
index 2dc62d6682e..f183704c9d2 100644
--- a/board/compulab/imx8mm-cl-iot-gate/spl.c
+++ b/board/compulab/imx8mm-cl-iot-gate/spl.c
@@ -83,14 +83,8 @@ int board_fit_config_name_match(const char *name)
}
#endif
-#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
-static iomux_v3_cfg_t const uart_pads[] = {
- IMX8MM_PAD_UART3_RXD_UART3_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
- IMX8MM_PAD_UART3_TXD_UART3_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
-};
-
static iomux_v3_cfg_t const wdog_pads[] = {
IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
};
@@ -103,8 +97,6 @@ int board_early_init_f(void)
set_wdog_reset(wdog);
- imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
-
return 0;
}
@@ -155,8 +147,6 @@ void board_init_f(ulong dummy)
timer_init();
- preloader_console_init();
-
/* Clear the BSS. */
memset(__bss_start, 0, __bss_end - __bss_start);
@@ -166,6 +156,8 @@ void board_init_f(ulong dummy)
hang();
}
+ preloader_console_init();
+
ret = uclass_get_device_by_name(UCLASS_CLK,
"clock-controller@3038",
);
diff --git a/configs/imx8mm-cl-iot-gate-optee_defconfig
b/configs/imx8mm-cl-iot-gate-optee_defconfig
index 8b3d1b3ef1a..0f0b34fecf9 100644
--- a/configs/imx8mm-cl-iot-gate-optee_defconfig
+++ b/configs/imx8mm-cl-iot-gate-optee_defconfig
@@ -108,6 +108,7 @@ CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_DM_RTC=y
CONFIG_RTC_ABX80X=y
+CONFIG_DM_SERIAL=y
CONFIG_MXC_UART=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
diff --git a/configs/imx8mm-cl-iot-gate_defconfig
b/configs/imx8mm-cl-iot-gate_defconfig
index b418e86248f..7bd5f6540e9 100644
--- a/configs/imx8mm-cl-iot-gate_defconfig
+++ b/configs/imx8mm-cl-iot-gate_defconfig
@@ -111,6 +111,7 @@ CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_DM_RTC=y
CONFIG_RTC_ABX80X=y
+CONFIG_DM_SERIAL=y
CONFIG_MXC_UART=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
diff --git a/include/configs/imx8mm-cl-iot-gate.h
b/include/configs/imx8mm-cl-iot-gate.h
index 8d9212ec64c..f262ab08f04 100644
--- a/include/configs/imx8mm-cl-iot-gate.h
+++ b/include/configs/imx8mm-cl-iot-gate.h
@@ -145,8 +145,6 @@
#define PHYS_SDRAM 0x4000
#define PHYS_SDRAM_SIZE0x8000 /* 2GB DDR */
-#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(3)
-
/* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE 2048
#define CONFIG_SYS_MAXARGS 64
--
2.36.0
[PATCH 02/22] imx: imx8m[m/n/p]_venice: Enable SPL_DM_SERIAL
From: Peng Fan Enable CONFIG_SPL_DM_SERIAL. uart2 and its pinmux was already marked with u-boot,dm-spl. Move preloader_console_init after spl_early_init to make sure driver model work. Signed-off-by: Peng Fan Acked-by: Tim Harvey Reviewed-by: Fabio Estevam --- include/configs/imx8mm_venice.h | 3 --- include/configs/imx8mn_venice.h | 3 --- include/configs/imx8mp_venice.h | 3 --- 3 files changed, 9 deletions(-) diff --git a/include/configs/imx8mm_venice.h b/include/configs/imx8mm_venice.h index 9836d5b73ca..90e8941a254 100644 --- a/include/configs/imx8mm_venice.h +++ b/include/configs/imx8mm_venice.h @@ -101,9 +101,6 @@ #define PHYS_SDRAM_SIZESZ_4G #define CONFIG_SYS_BOOTM_LEN SZ_256M -/* UART */ -#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(2) - /* Monitor Command Prompt */ #define CONFIG_SYS_CBSIZE SZ_2K #define CONFIG_SYS_MAXARGS 64 diff --git a/include/configs/imx8mn_venice.h b/include/configs/imx8mn_venice.h index 3cbe11a9035..6555dd4349c 100644 --- a/include/configs/imx8mn_venice.h +++ b/include/configs/imx8mn_venice.h @@ -97,9 +97,6 @@ #define PHYS_SDRAM_SIZESZ_4G #define CONFIG_SYS_BOOTM_LEN SZ_256M -/* UART */ -#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(2) - /* Monitor Command Prompt */ #define CONFIG_SYS_CBSIZE SZ_2K #define CONFIG_SYS_MAXARGS 64 diff --git a/include/configs/imx8mp_venice.h b/include/configs/imx8mp_venice.h index 4120e4cc6ba..c09a1b4572a 100644 --- a/include/configs/imx8mp_venice.h +++ b/include/configs/imx8mp_venice.h @@ -97,9 +97,6 @@ #define PHYS_SDRAM_SIZESZ_4G #define CONFIG_SYS_BOOTM_LEN SZ_256M -/* UART */ -#define CONFIG_MXC_UART_BASE UART2_BASE_ADDR - /* Monitor Command Prompt */ #define CONFIG_SYS_CBSIZE SZ_2K #define CONFIG_SYS_MAXARGS 64 -- 2.36.0
[PATCH 03/22] imx: imx8m[m/n]_beacon: Enable SPL_DM_SERIAL
From: Peng Fan
Enable CONFIG_SPL_DM_SERIAL. uart2 and its pinmux was already
marked with u-boot,dm-spl.
Move preloader_console_init after spl_init to make sure driver
model work.
Signed-off-by: Peng Fan
Tested-by: Adam Ford #imx8mm_beacon
Reviewed-by: Fabio Estevam
---
board/beacon/imx8mm/spl.c | 12 ++--
board/beacon/imx8mn/spl.c | 11 ++-
configs/imx8mm_beacon_defconfig| 1 -
configs/imx8mn_beacon_2g_defconfig | 1 -
configs/imx8mn_beacon_defconfig| 1 -
include/configs/imx8mm_beacon.h| 2 --
include/configs/imx8mn_beacon.h| 2 --
7 files changed, 4 insertions(+), 26 deletions(-)
diff --git a/board/beacon/imx8mm/spl.c b/board/beacon/imx8mm/spl.c
index 12266b22a42..f92b4c3ed0a 100644
--- a/board/beacon/imx8mm/spl.c
+++ b/board/beacon/imx8mm/spl.c
@@ -59,14 +59,8 @@ int board_fit_config_name_match(const char *name)
}
#endif
-#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
-static iomux_v3_cfg_t const uart_pads[] = {
- IMX8MM_PAD_UART2_RXD_UART2_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
- IMX8MM_PAD_UART2_TXD_UART2_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
-};
-
static iomux_v3_cfg_t const wdog_pads[] = {
IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
};
@@ -79,8 +73,6 @@ int board_early_init_f(void)
set_wdog_reset(wdog);
- imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
-
return 0;
}
@@ -128,8 +120,6 @@ void board_init_f(ulong dummy)
timer_init();
- preloader_console_init();
-
/* Clear the BSS. */
memset(__bss_start, 0, __bss_end - __bss_start);
@@ -139,6 +129,8 @@ void board_init_f(ulong dummy)
hang();
}
+ preloader_console_init();
+
ret = uclass_get_device_by_name(UCLASS_CLK,
"clock-controller@3038",
);
diff --git a/board/beacon/imx8mn/spl.c b/board/beacon/imx8mn/spl.c
index bb51be01c52..4563446db19 100644
--- a/board/beacon/imx8mn/spl.c
+++ b/board/beacon/imx8mn/spl.c
@@ -68,7 +68,6 @@ int board_fit_config_name_match(const char *name)
}
#endif
-#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
#define PWM1_PAD_CTRL (PAD_CTL_FSEL2 | PAD_CTL_DSE6)
@@ -76,11 +75,6 @@ static iomux_v3_cfg_t const pwm_pads[] = {
IMX8MN_PAD_GPIO1_IO01__PWM1_OUT | MUX_PAD_CTRL(PWM1_PAD_CTRL),
};
-static iomux_v3_cfg_t const uart_pads[] = {
- IMX8MN_PAD_UART2_RXD__UART2_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
- IMX8MN_PAD_UART2_TXD__UART2_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
-};
-
static iomux_v3_cfg_t const wdog_pads[] = {
IMX8MN_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
};
@@ -95,7 +89,6 @@ int board_early_init_f(void)
imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
set_wdog_reset(wdog);
- imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
init_uart_clk(1);
return 0;
@@ -114,14 +107,14 @@ void board_init_f(ulong dummy)
timer_init();
- preloader_console_init();
-
ret = spl_init();
if (ret) {
debug("spl_init() failed: %d\n", ret);
hang();
}
+ preloader_console_init();
+
enable_tzc380();
/* DDR initialization */
diff --git a/configs/imx8mm_beacon_defconfig b/configs/imx8mm_beacon_defconfig
index 9cd8ac97285..a8981975f66 100644
--- a/configs/imx8mm_beacon_defconfig
+++ b/configs/imx8mm_beacon_defconfig
@@ -112,7 +112,6 @@ CONFIG_SPL_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_CONS_INDEX=2
CONFIG_DM_SERIAL=y
-# CONFIG_SPL_DM_SERIAL is not set
CONFIG_MXC_UART=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
diff --git a/configs/imx8mn_beacon_2g_defconfig
b/configs/imx8mn_beacon_2g_defconfig
index 145f96d491d..cf1720725d0 100644
--- a/configs/imx8mn_beacon_2g_defconfig
+++ b/configs/imx8mn_beacon_2g_defconfig
@@ -114,7 +114,6 @@ CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_DM_RESET=y
CONFIG_DM_SERIAL=y
-# CONFIG_SPL_DM_SERIAL is not set
CONFIG_MXC_UART=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
diff --git a/configs/imx8mn_beacon_defconfig b/configs/imx8mn_beacon_defconfig
index 9052e68e967..882a6044989 100644
--- a/configs/imx8mn_beacon_defconfig
+++ b/configs/imx8mn_beacon_defconfig
@@ -118,7 +118,6 @@ CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_DM_RESET=y
CONFIG_DM_SERIAL=y
-# CONFIG_SPL_DM_SERIAL is not set
CONFIG_MXC_UART=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
diff --git a/include/configs/imx8mm_beacon.h b/include/configs/imx8mm_beacon.h
index 573ddaf2952..4c9b5491f78 100644
--- a/include/configs/imx8mm_beacon.h
+++ b/include/configs/imx8mm_beacon.h
@@ -91,8 +91,6 @@
#define PHYS_SDRAM
[PATCH 01/22] imx: drop CONFIG_MXC_UART_BASE
From: Peng Fan Since these boards has CONFIG_DM_SERIAL and/or CONFIG_SPL_DM_SERIAL, the legacy macro no need to be defined. Reviewed-by: Heiko Schocher Reviewed-by: Fabio Estevam Signed-off-by: Peng Fan Acked-by: Soeren Moch --- include/configs/aristainetos2.h| 2 -- include/configs/imx8mm_evk.h | 2 -- include/configs/imx8mn_bsh_smm_s2_common.h | 2 -- include/configs/imx8mn_evk.h | 2 -- include/configs/imx8mp_evk.h | 2 -- include/configs/mx7dsabresd.h | 1 - include/configs/somlabs_visionsom_6ull.h | 1 - include/configs/tbs2910.h | 3 --- include/configs/verdin-imx8mm.h| 3 --- include/configs/verdin-imx8mp.h| 3 --- 10 files changed, 21 deletions(-) diff --git a/include/configs/aristainetos2.h b/include/configs/aristainetos2.h index 8ee97f1d4e3..27adae5d6bf 100644 --- a/include/configs/aristainetos2.h +++ b/include/configs/aristainetos2.h @@ -14,10 +14,8 @@ #define CONFIG_HOSTNAME"aristainetos2" #if (CONFIG_SYS_BOARD_VERSION == 5) -#define CONFIG_MXC_UART_BASE UART2_BASE #define CONSOLE_DEV"ttymxc1" #elif (CONFIG_SYS_BOARD_VERSION == 6) -#define CONFIG_MXC_UART_BASE UART1_BASE #define CONSOLE_DEV"ttymxc0" #endif diff --git a/include/configs/imx8mm_evk.h b/include/configs/imx8mm_evk.h index 5e8f19c43fb..002b2e68bba 100644 --- a/include/configs/imx8mm_evk.h +++ b/include/configs/imx8mm_evk.h @@ -68,8 +68,6 @@ #define PHYS_SDRAM 0x4000 #define PHYS_SDRAM_SIZE0x8000 /* 2GB DDR */ -#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(2) - /* Monitor Command Prompt */ #define CONFIG_SYS_CBSIZE 2048 #define CONFIG_SYS_MAXARGS 64 diff --git a/include/configs/imx8mn_bsh_smm_s2_common.h b/include/configs/imx8mn_bsh_smm_s2_common.h index 6387576c2da..57be38d9433 100644 --- a/include/configs/imx8mn_bsh_smm_s2_common.h +++ b/include/configs/imx8mn_bsh_smm_s2_common.h @@ -45,8 +45,6 @@ #define CONFIG_SYS_SDRAM_BASE 0x4000 #define PHYS_SDRAM 0x4000 -#define CONFIG_MXC_UART_BASE UART4_BASE_ADDR - /* Monitor Command Prompt */ #define CONFIG_SYS_CBSIZE SZ_2K #define CONFIG_SYS_MAXARGS 64 diff --git a/include/configs/imx8mn_evk.h b/include/configs/imx8mn_evk.h index 805ae2a7518..86be1b8b3be 100644 --- a/include/configs/imx8mn_evk.h +++ b/include/configs/imx8mn_evk.h @@ -75,8 +75,6 @@ #define PHYS_SDRAM 0x4000 #define PHYS_SDRAM_SIZE0x8000 /* 2GB DDR */ -#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(2) - /* Monitor Command Prompt */ #define CONFIG_SYS_CBSIZE 2048 #define CONFIG_SYS_MAXARGS 64 diff --git a/include/configs/imx8mp_evk.h b/include/configs/imx8mp_evk.h index 1e7c44c42a4..373098f10c4 100644 --- a/include/configs/imx8mp_evk.h +++ b/include/configs/imx8mp_evk.h @@ -79,8 +79,6 @@ #define PHYS_SDRAM_2 0x1 #define PHYS_SDRAM_2_SIZE 0xC000 /* 3 GB */ -#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(2) - /* Monitor Command Prompt */ #define CONFIG_SYS_CBSIZE 2048 #define CONFIG_SYS_MAXARGS 64 diff --git a/include/configs/mx7dsabresd.h b/include/configs/mx7dsabresd.h index aaad232f0e4..62e62c6701f 100644 --- a/include/configs/mx7dsabresd.h +++ b/include/configs/mx7dsabresd.h @@ -12,7 +12,6 @@ #define PHYS_SDRAM_SIZESZ_1G -#define CONFIG_MXC_UART_BASEUART1_IPS_BASE_ADDR #ifdef CONFIG_IMX_BOOTAUX /* Set to QSPI1 A flash at default */ diff --git a/include/configs/somlabs_visionsom_6ull.h b/include/configs/somlabs_visionsom_6ull.h index d4761296c75..e6aad386efe 100644 --- a/include/configs/somlabs_visionsom_6ull.h +++ b/include/configs/somlabs_visionsom_6ull.h @@ -16,7 +16,6 @@ /* SPL options */ #include "imx6_spl.h" -#define CONFIG_MXC_UART_BASE UART1_BASE /* MMC Configs */ #ifdef CONFIG_FSL_USDHC diff --git a/include/configs/tbs2910.h b/include/configs/tbs2910.h index b7a94812f35..5d8cb34ad9a 100644 --- a/include/configs/tbs2910.h +++ b/include/configs/tbs2910.h @@ -24,9 +24,6 @@ #define CONFIG_SYS_BOOTMAPSZ 0x1000 -/* Serial console */ -#define CONFIG_MXC_UART_BASE UART1_BASE /* select UART1/UART2 */ - /* Framebuffer */ #define CONFIG_IMX_HDMI #define CONFIG_IMX_VIDEO_SKIP diff --git a/include/configs/verdin-imx8mm.h b/include/configs/verdin-imx8mm.h index cd950ad055e..9ed9da043f6 100644 --- a/include/configs/verdin-imx8mm.h +++ b/include/configs/verdin-imx8mm.h @@ -83,9 +83,6 @@ #define PHYS_SDRAM 0x4000 #define PHYS_SDRAM_SIZESZ_2G /* 2GB DDR */ -/* UART */ -#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(1) - /* Monitor Command Prompt */ #define CONFIG_SYS_CBSIZE
[PATCH 00/22] imx: patches in queue
From: Peng Fan Hi Stefano, This patchset is a rebase of your/master-next branch to make these patches in my patchwork queue could apply. I not send them as previous seperated patchset, hope this not matter. The two patches are not included, since they are just sent out. https://patchwork.ozlabs.org/project/uboot/patch/20220523113828.3837-1-peng@oss.nxp.com/ https://patchwork.ozlabs.org/project/uboot/patch/20220523113828.3837-2-peng@oss.nxp.com/ Thanks, Peng. Peng Fan (22): imx: drop CONFIG_MXC_UART_BASE imx: imx8m[m/n/p]_venice: Enable SPL_DM_SERIAL imx: imx8m[m/n]_beacon: Enable SPL_DM_SERIAL imx: imx8mm-cl-iot-gate: Enable DM_SERIAL imx: imx8mm_icore: Enable SPL_DM_SERIAL imx: imx8m[m/p]_phycore: Enable DM_SERIAL imx: imx8mn_var_som: enable DM_SERIAL imx: kontron-sl-mx8mm: enable DM_SERIAL configs: drop CONFIG_SPL_ABORT_ON_RAW_IMAGE configs: imx8m: use common imx8m.h for i.MX8MM configs: imx8m: use common imx8m.h for i.MX8MN configs: imx8m: use common imx8m.h for i.MX8MP configs: imx8m: use common imx8m.h for i.MX8MQ imx: imx8mm_beacon: enable pinctrl_wdog in SPL imx: imx8mm-cl-iot-gate: enable pinctrl_wdog in SPL imx: engicam-imx8mm: drop unused macro imx: imx8mm/n/p-venice: enable pinctrl_wdog in SPL imx: imx8mn-beacon: enable pinctrl_wdog in SPL imx: imx8mn_var_som: clean up board watchdog code imx: imx8mp_rsb7320a1: enable wdog driver model in SPL imx: imx8mn-kontron-n801x: enable pinctrl_wdog in SPL imx: phycore_imx8mm/p: clean up board watchdog code arch/arm/dts/imx8mm-beacon-kit-u-boot.dtsi| 4 ++ arch/arm/dts/imx8mm-cl-iot-gate-u-boot.dtsi | 4 ++ arch/arm/dts/imx8mm-kontron-n801x-u-boot.dtsi | 4 ++ arch/arm/dts/imx8mm-venice-u-boot.dtsi| 4 ++ arch/arm/dts/imx8mn-beacon-kit-u-boot.dtsi| 4 ++ arch/arm/dts/imx8mn-venice-u-boot.dtsi| 4 ++ arch/arm/dts/imx8mp-rsb3720-a1-u-boot.dtsi| 8 +++ arch/arm/dts/imx8mp-venice-u-boot.dtsi| 4 ++ .../imx8mp_rsb3720a1/imx8mp_rsb3720a1.c | 12 board/beacon/imx8mm/spl.c | 31 +- board/beacon/imx8mn/spl.c | 21 +-- board/compulab/imx8mm-cl-iot-gate/spl.c | 31 +- board/engicam/imx8mm/spl.c| 16 +- board/gateworks/venice/spl.c | 29 -- board/kontron/sl-mx8mm/spl.c | 30 +- board/phytec/phycore_imx8mm/spl.c | 31 +- board/phytec/phycore_imx8mp/spl.c | 27 - board/variscite/imx8mn_var_som/spl.c | 22 +-- configs/imx8mm-cl-iot-gate-optee_defconfig| 1 + configs/imx8mm-cl-iot-gate_defconfig | 1 + configs/imx8mm-icore-mx8mm-ctouch2_defconfig | 1 - configs/imx8mm-icore-mx8mm-edimm2.2_defconfig | 1 - configs/imx8mm_beacon_defconfig | 1 - configs/imx8mn_beacon_2g_defconfig| 1 - configs/imx8mn_beacon_defconfig | 1 - configs/imx8mn_var_som_defconfig | 1 + configs/kontron-sl-mx8mm_defconfig| 1 + configs/phycore-imx8mm_defconfig | 1 + configs/phycore-imx8mp_defconfig | 1 + include/configs/aristainetos2.h | 2 - include/configs/capricorn-common.h| 1 - include/configs/cgtqmx8.h | 1 - include/configs/imx8m.h | 57 +++ include/configs/imx8mm-cl-iot-gate.h | 20 +-- include/configs/imx8mm_beacon.h | 24 +--- include/configs/imx8mm_data_modul_edm_sbc.h | 17 +- include/configs/imx8mm_evk.h | 24 +--- include/configs/imx8mm_icore_mx8mm.h | 24 +--- include/configs/imx8mm_venice.h | 22 +-- include/configs/imx8mn_beacon.h | 3 - include/configs/imx8mn_bsh_smm_s2_common.h| 19 +-- include/configs/imx8mn_evk.h | 23 +--- include/configs/imx8mn_var_som.h | 17 +- include/configs/imx8mn_venice.h | 22 +-- include/configs/imx8mp_evk.h | 20 +-- include/configs/imx8mp_rsb3720.h | 17 +- include/configs/imx8mp_venice.h | 22 +-- include/configs/imx8mq_cm.h | 25 +--- include/configs/imx8mq_evk.h | 20 +-- include/configs/imx8mq_phanbell.h | 20 +-- include/configs/imx8qm_mek.h | 1 - include/configs/imx8qxp_mek.h | 1 - include/configs/imx8ulp_evk.h | 1 - include/configs/kontron-sl-mx8mm.h| 15 + include/configs/kontron_pitx_imx8m.h | 20 +-- include/configs/mx7dsabresd.h | 1 - include/configs/phycore_imx8mm.h | 24 +--- include/configs/phycore_imx8mp.h | 20 +-- include/configs/pico-imx8mq.h | 21 +--
Re: dwc_eth_qos driver for tegra
On 23/05/2022 12.57, Marek Vasut wrote: > On 5/23/22 11:17, Rasmus Villemoes wrote: >> Hi > > Hi, > >> I'm looking at switching the dwc_eth_qos driver over to use >> dm_eth_phy_connect(). However, I'm a little puzzled by the code for the >> tegra variant. The comment at the top of the file, as well as >> tegra186.dtsi, says >> >> phy-mode = "rgmii"; >> >> But eqos_get_interface_tegra186() returns a hard-coded >> PHY_INTERFACE_MODE_MII. Now the commit which introduced the ->interface >> abstraction, ac2d4efb16e (net: dwc_eth_qos: add Ethernet stm32mp1 >> support), and that eqos_get_interface_tegra186() function, changed >> >> - eqos->phy = phy_connect(eqos->mii, 0, dev, 0); >> >> to >> >> + eqos->phy = phy_connect(eqos->mii, 0, dev, >> + eqos->config->interface(dev)); >> >> and that last hard-coded 0 in the former phy_connect() is indeed >> equivalent to PHY_INTERFACE_MODE_MII. >> >> So which is it? It would be nice if one could just rely on >> dm_eth_phy_connect() picking up the correct value from device tree, and >> drop all the code which duplicates parsing of phy-mode from the ethernet >> driver. > > linux-2.6$ git grep mii arch/arm64/boot/dts/nvidia/tegra186* > arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi: phy-mode = "rgmii"; > arch/arm64/boot/dts/nvidia/tegra186-p3509-+p3636-0001.dts: phy-mode > = "rgmii-id"; > > So probably RGMII ? Well, yes, I also did check the linux device tree files which also says rgmii, but that doesn't explain why the U-Boot driver code seems to ignore that entirely and use mii hardcoded, both before and after ac2d4efb16e. So another way of asking: does this driver actually work today, and/or has it worked at some point? I assume the answer is yes - after all, the very first commit "supports the specific configuration used in NVIDIA's Tegra186 chip", but that commit also did that phy_connect() with a last argument of 0 aka PHY_INTERFACE_MODE_MII. And would it break if one started taking the phy-mode from device tree? If so, should device tree be updated to say "mii"? Rasmus
Re: [PATCH v1 0/8] Add support for the i.MXRT1170
Hi Jesse, patchset slipped away, sorry. I have tried to apply it in last MR, but the patchset is currently obsolete and patches should be rebased. I will drop this version of patchset, please rebase on top of current master and repost - thanks ! Best regards, Stefano On 17.03.22 19:32, Jesse Taube wrote: This patchset contains: - i.MXRT1170 clock driver adaption - i.MXRT1170-evk basic support Jesse Taube (8): imx: imxrt1170-evk: Add support for the NXP i.MXRT1170-EVK ARM: dts: imxrt11170-pinfunc: Add pinctrl binding header dt-bindings: imx: Add clock binding for i.MXRT1170 clk: imx: Add i.MXRT11xx pllv3 variant clk: imx: Add initial support for i.MXRT1170 clock driver RAM: Add changes for i.MXRT11xx series ARM: dts: imx: add i.MXRT1170-EVK support ARM: imxrt1170_defconfig: Add i.MXRT1170 defconfig arch/arm/dts/Makefile |3 +- arch/arm/dts/imxrt1170-evk-u-boot.dtsi| 106 ++ arch/arm/dts/imxrt1170-evk.dts| 246 +++ arch/arm/dts/imxrt1170-pinfunc.h | 1561 + arch/arm/dts/imxrt1170.dtsi | 274 +++ arch/arm/include/asm/arch-imx/cpu.h |1 + arch/arm/mach-imx/imxrt/Kconfig |9 + arch/arm/mach-imx/imxrt/soc.c |2 + board/freescale/imxrt1170-evk/Kconfig | 22 + board/freescale/imxrt1170-evk/MAINTAINERS |7 + board/freescale/imxrt1170-evk/Makefile|6 + board/freescale/imxrt1170-evk/imximage.cfg| 32 + board/freescale/imxrt1170-evk/imxrt1170-evk.c | 80 + configs/imxrt1170-evk_defconfig | 67 + drivers/clk/imx/Kconfig | 16 + drivers/clk/imx/Makefile |1 + drivers/clk/imx/clk-imxrt1170.c | 215 +++ drivers/clk/imx/clk-pllv3.c | 44 + drivers/clk/imx/clk.h |1 + drivers/ram/imxrt_sdram.c |9 + include/configs/imxrt1170-evk.h | 37 + include/dt-bindings/clock/imxrt1170-clock.h | 48 + include/dt-bindings/memory/imxrt-sdram.h |1 + 23 files changed, 2787 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/imxrt1170-evk-u-boot.dtsi create mode 100644 arch/arm/dts/imxrt1170-evk.dts create mode 100644 arch/arm/dts/imxrt1170-pinfunc.h create mode 100644 arch/arm/dts/imxrt1170.dtsi create mode 100644 board/freescale/imxrt1170-evk/Kconfig create mode 100644 board/freescale/imxrt1170-evk/MAINTAINERS create mode 100644 board/freescale/imxrt1170-evk/Makefile create mode 100644 board/freescale/imxrt1170-evk/imximage.cfg create mode 100644 board/freescale/imxrt1170-evk/imxrt1170-evk.c create mode 100644 configs/imxrt1170-evk_defconfig create mode 100644 drivers/clk/imx/clk-imxrt1170.c create mode 100644 include/configs/imxrt1170-evk.h create mode 100644 include/dt-bindings/clock/imxrt1170-clock.h -- = DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de =
[RESEND PATCH] gpio: rgpio2p: Enhance reading of GPIO pin value
> Add support for reading GPIO pin value when function is output. > With this patch applied, gpio toggle command is working. > Signed-off-by: Christoph Fritz > Reviewed-by: Peng Fan > Reviewed-by: Fabio Estevam Applied to u-boot-imx, master, thanks ! Best regards, Stefano Babic -- = DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de =
[PATCH v2] ARM: dts: imx: Add support for DH electronics i.MX8M Plus DHCOM and PDK2
> Add support for DH electronics i.MX8M Plus DHCOM SoM on PDK2 carrier board. > Currently supported are serial console, EQoS and FEC ethernets, eMMC, SD, > SPI NOR and USB 3.0 host. > Signed-off-by: Marek Vasut > Cc: Fabio Estevam > Cc: Peng Fan > Cc: Stefano Babic Applied to u-boot-imx, master, thanks ! Best regards, Stefano Babic -- = DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de =
[PATCH] ARM: imx: mx5: Convert MX53 Menlo board to DM I2C and DM RTC
> Convert the board to DM I2C and DM RTC. This leads to removal of board > side iomuxc configuration, which is now done using pin control driver, > and conversion of board side legacy I2C accessors to DM ones. > Signed-off-by: Marek Vasut > Cc: Stefano Babic Applied to u-boot-imx, master, thanks ! Best regards, Stefano Babic -- = DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de =
Pull request: u-boot-imx u-boot-imx-20220523
Hi Tom,
please pull from u-boot-imx, thanks !
The following changes since commit f83bd23e2a0e9861969c9d43395299a14f25ddda:
Merge https://source.denx.de/u-boot/custodians/u-boot-marvell
(2022-05-18 08:41:13 -0400)
are available in the Git repository at:
https://gitlab.denx.de/u-boot/custodians/u-boot-imx.git
tags/u-boot-imx-20220523
for you to fetch changes up to 4d573d5c98234cad328de77c773c3c3d79258255:
ARM: dts: imx: Add support for DH electronics i.MX8M Plus DHCOM and
PDK2 (2022-05-23 11:37:58 +0200)
u-boot-imx-20220523
---
CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/12087
Additionally to u-boot-imx20200520:
- DH MX8MP
- i.MX GPIO: reading GPIO when direction is output
- Menlo i.MX53: switch to DM
And from u-boot-imx20200520:
- fix Verdin hang
- add pca9450 regulator
- conversion to DM_SERIAL
- NAND block handling
- fix crypto
- enable cache on some boards
- add ACC board (MX6)
Christoph Fritz (1):
gpio: rgpio2p: Enhance reading of GPIO pin value
Fabio Estevam (8):
imx8mn_ddr4_evk: Add USB Mass Storage support
imx8mn/8mp: Allow booting via USB
mx6slevk: Remove duplicated "mmc dev" command
mx6sllevk: Remove duplicated "mmc dev" command
kontron-sl-mx8mm: Select the CONFIG_CMD_UNZIP option
imx8mm-cl-iot-gate: Enable cache in SPL
cgtqmx8: Enable cache in SPL
imx8mp_rsb3720a1: Enable cache in SPL
Gaurav Jain (4):
i.MX6SX: crypto/fsl: fix entropy delay value
i.MX8 crypto/fsl: Enable fsl CAAM rng driver
i.MX8ULP: add display_ele_fw_version api
crypto/fsl: fsl_hash: Fix dcache issue in caam_hash_finish
Marcel Ziswiler (1):
ARM: imx8mm: verdin-imx8mm: fix board hang in spl
Marek Vasut (8):
ARM: dts: imx: Use 100 kHz I2C2 on Data Modul i.MX8M Mini eDM SBC
ARM: imx: imx8m: Introduce and use UART_BASE_ADDR(n)
ARM: imx: imx27: Introduce and use UART_BASE_ADDR(n)
ARM: imx: imx31: Introduce and use UART_BASE_ADDR(n)
pmic: pca9450: Add upstream regulators subnode match
pmic: pca9450: Add regulator driver
ARM: imx: mx5: Convert MX53 Menlo board to DM I2C and DM RTC
ARM: dts: imx: Add support for DH electronics i.MX8M Plus DHCOM
and PDK2
Michael Trimarchi (5):
nand: raw: mxs_nand: Fix specific hook registration
mtd: nand: mxs_nand_spl: Fix bad block skipping
arm: mach-imx: cmd_nandbcb fix bad block handling
spl: spl_nand: Fix bad block handling in fitImage
imx: imx8mn_smm_s2/s2pro: Enable TrustZone
Peng Fan (19):
imx: bootaux: cleanup code
imx: bootaux: add missing newline
imx: bootaux: get stack from elf file
imx: imx8m: add rproc_att
imx: imx8m: drop uneeded check
imx: imx8mm_mx8menlo: Enable DM_SERIAL
imx: imx8mm_edm_sbc: Enable SPL_DM_SERIAL
imx: dts: move common changes to imx8mq-u-boot.dtsi
imx: imx8mq-cm: enable CONFIG_DM_SERIAL
imx: imx8mq-pico: enable CONFIG_DM_SERIAL
imx: imx8mq-phanbell: enable CONFIG_DM_SERIAL
imx: imx8mn_evk: enable pinctrl_wdog in SPL
imx: imx8mm_evk: enable pinctrl_wdog in SPL
imx: imx8mp_evk: enable pinctrl_wdog in SPL
imx: imx8mm-mx8menlo: drop unneeded watchdog settings
imx: imx8mn_smm_s2: clean up board watchdog code
imx: verdin-imx8mm/p: cleanup board watchdog code
imx: toradex/verdin-imx8mm/p: cleanup board watchdog code
imx: imx8mp_rsb3720a1: convert to DM_SERIAL
Philip Oberfichtner (9):
bosch: Add initial board support for ACC
ARM: imx6: Fix broken DT path in DH board file
ARM: dts: imx: Migrate iMX6QDL DRC02 DTs from Linux
ARM: dts: imx: Migrate iMX6QDL picoITX DTs from Linux
ARM: imx6: Remove CONFIG_FEC_MXC_PHYADDR from DH header
ARM: dts: imx: Simplify fec node for iMX6QDL DHCOM boards
ARM: dts: imx: Configure FEC for iMX6QDL picoITX
ARM: dts: imx: Configure FEC for iMX6QDL DRC02
ARM: imx6: Adapt device tree selection in DH board file
Rasmus Villemoes (1):
imx8m: fix reading of DDR4 MR registers
Tim Harvey (6):
configs: imx8m{m, n}_venice: remove unneeded CONFIG_FEC_MXC_PHYADDR
configs: imx8mp_venice: add FEC_QUIRK_ENET_MAC
configs: remove FEC_QUIRK_ENET_MAC from imx8m configs
board: gateworks: venice: enable SPL_DM_SERIAL
board: gateworks: gw_ventana: add support for GPY111 PHY
board: gateworks: gw_ventana: remove obsolete file
Ye Li (2):
mtd: rawnand: mxs_nand: Fix use_minimum_ecc for spl driver
caam: Fix crash in case caam_jr_probe failed
arch/arm/cpu/armv7/ls102xa/cpu.c|2 +-
arch/arm/cpu/armv8/fsl-layerscape/cpu.c |2 +-
arch/arm/dts/Makefile |4 +
arch/arm/dts/imx6dl-dhcom-picoitx-u-boot.dtsi
Re: dwc_eth_qos driver for tegra
On 5/23/22 11:17, Rasmus Villemoes wrote: Hi Hi, I'm looking at switching the dwc_eth_qos driver over to use dm_eth_phy_connect(). However, I'm a little puzzled by the code for the tegra variant. The comment at the top of the file, as well as tegra186.dtsi, says phy-mode = "rgmii"; But eqos_get_interface_tegra186() returns a hard-coded PHY_INTERFACE_MODE_MII. Now the commit which introduced the ->interface abstraction, ac2d4efb16e (net: dwc_eth_qos: add Ethernet stm32mp1 support), and that eqos_get_interface_tegra186() function, changed - eqos->phy = phy_connect(eqos->mii, 0, dev, 0); to + eqos->phy = phy_connect(eqos->mii, 0, dev, + eqos->config->interface(dev)); and that last hard-coded 0 in the former phy_connect() is indeed equivalent to PHY_INTERFACE_MODE_MII. So which is it? It would be nice if one could just rely on dm_eth_phy_connect() picking up the correct value from device tree, and drop all the code which duplicates parsing of phy-mode from the ethernet driver. linux-2.6$ git grep mii arch/arm64/boot/dts/nvidia/tegra186* arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi: phy-mode = "rgmii"; arch/arm64/boot/dts/nvidia/tegra186-p3509-+p3636-0001.dts: phy-mode = "rgmii-id"; So probably RGMII ?
[PATCH resend 2/2] imx: imx8mq: select CONFIG_CMD_CLK
From: Peng Fan select CONFIG_CMD_CLK to enable dump clk in uboot shell Signed-off-by: Peng Fan --- configs/imx8mq_evk_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/imx8mq_evk_defconfig b/configs/imx8mq_evk_defconfig index 780f93103c..9f54a280d9 100644 --- a/configs/imx8mq_evk_defconfig +++ b/configs/imx8mq_evk_defconfig @@ -40,6 +40,7 @@ CONFIG_SYS_PROMPT="u-boot=> " # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set # CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CLK=y CONFIG_CMD_FUSE=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y -- 2.36.0
[PATCH resend 1/2] imx: imx8mq: default select CLK_IMX8MQ
From: Peng Fan
Since the power domain driver default select CONFIG_CLK, so we will
meet lots failures without CLK_IMX8MQ, so default select it.
Fixes: commit 4eb82c2e56a7c ("imx: power-domain: Get rid of SMCCC dependency")
Signed-off-by: Peng Fan
---
arch/arm/mach-imx/imx8m/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig
index 24299ae037..7f23d687be 100644
--- a/arch/arm/mach-imx/imx8m/Kconfig
+++ b/arch/arm/mach-imx/imx8m/Kconfig
@@ -8,6 +8,7 @@ config IMX8M
config IMX8MQ
bool
select IMX8M
+ select CLK_IMX8MQ
config IMX8MM
bool
--
2.36.0
Re: [PATCH v1] mmc: nuvoton: Add NPCM7xx mmc driver
Hi Jaehoon
about the s/devic/device topic
I think I know what the problem with kconfig.
I will update it in the next version.
On Mon, May 23, 2022 at 5:08 PM Jim Liu wrote:
>
> Hi Jaehoon
>
> Thanks for your reply.
> I will follow your suggestion to modify it for version 2.
> and some explain and question as below:
>
> 1.
> what's mean for s/devic/device
> could you give more information?
>
> 2.
> vqmmc-supply is always on.
>
> On Wed, May 18, 2022 at 5:04 PM Jaehoon Chung wrote:
> >
> > Hi Jim
> >
> >
> > On 5/18/22 14:11, Jim Liu wrote:
> > > Hi Jaehoon
> > >
> > > Thanks for your reply.
> > > NPCM750 main patch is upstream on uboot master.
> >
> > Sorry. I missed them. Thanks for sharing an information.
> >
> > > it can build on uboot master branch.
> > > The default config is poleg_evb_defconfig and the log is as below:
> > >
> > > U-Boot 2022.07-rc2-00065-gc387e62614 (May 18 2022 - 10:19:05 +0800)
> > >
> > > CPU: NPCM750 A1 @ Model: Nuvoton npcm750 Development Board (Device Tree)
> > > DRAM: 464 MiB
> > > Core: 23 devices, 9 uclasses, devicetree: separate
> > > MMC:
> > > Loading Environment from SPIFlash... Invalid bus 0 (err=-19)
> > > *** Warning - spi_flash_probe_bus_cs() failed, using default environment
> > >
> > > In:serial@1000
> > > Out: serial@1000
> > > Err: serial@1000
> > > Net: No ethernet found.
> > > Hit any key to stop autoboot: 0
> > > U-Boot>
> > > -
> > >
> > > And now I want to add some extra features for NPCM750.
> > > If you have any questions or please let me know.
> > > I will wait for your suggestions.
> > >
> > > On Tue, May 17, 2022 at 5:42 PM Jaehoon Chung
> > > wrote:
> > >>
> > >> Hi,
> > >>
> > >> On 5/17/22 17:26, Jim Liu wrote:
> > >>> Add Nuvoton BMC NPCM750 mmc control driver.
> > >>
> > >> There is no where this driver is building.
> > >> If you have more patch to upstream, I think that it's better to send as
> > >> patchset than now.
> > >>
> > >> Best Regards,
> > >> Jaehoon Chung
> > >>
> > >>>
> > >>> Signed-off-by: Jim Liu
> > >>> ---
> > >>> drivers/mmc/Kconfig | 12 ++
> > >>> drivers/mmc/Makefile | 1 +
> > >>> drivers/mmc/npcm_sdhci.c | 89
> > >>> 3 files changed, 102 insertions(+)
> > >>> create mode 100644 drivers/mmc/npcm_sdhci.c
> > >>>
> > >>> diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
> > >>> index f04cc44e19..49850f5d40 100644
> > >>> --- a/drivers/mmc/Kconfig
> > >>> +++ b/drivers/mmc/Kconfig
> > >>> @@ -607,6 +607,18 @@ config MMC_SDHCI_MV
> > >>>
> > >>> If unsure, say N.
> > >>>
> > >>> +config MMC_SDHCI_NPCM
> > >>> + bool "SDHCI support on Nuvoton NPCM device"
> > >>> + depends on MMC_SDHCI
> > >>> + depends on DM_MMC
> > >>> + help
> > >>> + This selects the Secure Digital Host Controller Interface
> > >>> (SDHCI)
> > >>> + on Nuvoton NPCM devic.
> >
> > s/devic/device
> >
> > >>> +
> > >>> + If you have a controller with this interface, say Y here.
> > >>> +
> > >>> + If unsure, say N.
> > >>> +
> > >>> config MMC_SDHCI_PIC32
> > >>> bool "Microchip PIC32 on-chip SDHCI support"
> > >>> depends on DM_MMC && MACH_PIC32
> > >>> diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile
> > >>> index 9627509302..280da24567 100644
> > >>> --- a/drivers/mmc/Makefile
> > >>> +++ b/drivers/mmc/Makefile
> > >>> @@ -67,6 +67,7 @@ obj-$(CONFIG_MMC_SDHCI_IPROC) +=
> > >>> iproc_sdhci.o
> > >>> obj-$(CONFIG_MMC_SDHCI_KONA) += kona_sdhci.o
> > >>> obj-$(CONFIG_MMC_SDHCI_MSM) += msm_sdhci.o
> > >>> obj-$(CONFIG_MMC_SDHCI_MV) += mv_sdhci.o
> > >>> +obj-$(CONFIG_MMC_SDHCI_NPCM)+= npcm_sdhci.o
> > >>> obj-$(CONFIG_MMC_SDHCI_PIC32)+= pic32_sdhci.o
> > >>> obj-$(CONFIG_MMC_SDHCI_ROCKCHIP) += rockchip_sdhci.o
> > >>> obj-$(CONFIG_MMC_SDHCI_S5P) += s5p_sdhci.o
> > >>> diff --git a/drivers/mmc/npcm_sdhci.c b/drivers/mmc/npcm_sdhci.c
> > >>> new file mode 100644
> > >>> index 00..baec994e85
> > >>> --- /dev/null
> > >>> +++ b/drivers/mmc/npcm_sdhci.c
> > >>> @@ -0,0 +1,89 @@
> > >>> +// SPDX-License-Identifier: GPL-2.0+
> > >>> +/*
> > >>> + * Copyright (c) 2021 Nuvoton Technology Corp.
> >
> > 2022?
> >
> > >>> + */
> > >>> +
> > >>> +#include
> > >>> +#include
> > >>> +#include
> > >>> +#include
> > >>> +#include
> > >>> +
> > >>> +#define NPCM_SDHC_MIN_FREQ 40
> > >>> +
> > >>> +struct npcm_sdhci_plat {
> > >>> + struct mmc_config cfg;
> > >>> + struct mmc mmc;
> > >>> +};
> > >>> +
> > >>> +static int npcm_sdhci_probe(struct udevice *dev)
> > >>> +{
> > >>> + struct npcm_sdhci_plat *plat = dev_get_plat(dev);
> > >>> + struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
> > >>> + struct sdhci_host *host = dev_get_priv(dev);
> > >>> + struct udevice *vqmmc_supply;
> > >>> + int vqmmc_uv, ret;
> > >>>
Re: [PATCH] squashfs: Fix compilation on big endian systems
On Tuesday 10 May 2022 16:33:56 Pali Rohár wrote: > On Wednesday 06 April 2022 23:31:53 Pali Rohár wrote: > > Signed-off-by: Pali Rohár > > --- > > fs/squashfs/sqfs.c | 3 +-- > > fs/squashfs/sqfs_dir.c | 3 +-- > > 2 files changed, 2 insertions(+), 4 deletions(-) > > > > diff --git a/fs/squashfs/sqfs.c b/fs/squashfs/sqfs.c > > index 5d9c52af80ba..41cb811c1b32 100644 > > --- a/fs/squashfs/sqfs.c > > +++ b/fs/squashfs/sqfs.c > > @@ -11,8 +11,7 @@ > > #include > > #include > > #include > > -#include > > -#include > > +#include > > #include > > #include > > #include > > diff --git a/fs/squashfs/sqfs_dir.c b/fs/squashfs/sqfs_dir.c > > index a265b98fe685..ed83c90682ff 100644 > > --- a/fs/squashfs/sqfs_dir.c > > +++ b/fs/squashfs/sqfs_dir.c > > @@ -7,8 +7,7 @@ > > > > #include > > #include > > -#include > > -#include > > +#include > > #include > > #include > > #include > > -- > > 2.20.1 > > > > PING? PING?
Re: [ANN] U-Boot v2022.07-rc2 released
On Tuesday 10 May 2022 08:41:53 Tom Rini wrote: > On Tue, May 10, 2022 at 01:37:53PM +0200, Pali Rohár wrote: > > On Monday 09 May 2022 12:50:42 Tom Rini wrote: > > > Hey all, > > > > > > It's release day and so here's v2022.07-rc2. I believe things are > > > largely caught up in terms of big outstanding changes but if you know of > > > something you were expecting to be in by now, and is not, please speak > > > up. > > > > There are still more powerpc fixes which are not in v2022.07-rc2. > > I created "bundle" on patchwork for easier tracking: > > https://patchwork.ozlabs.org/bundle/pali/powerpc/ > > Thanks. For: > https://patchwork.ozlabs.org/project/uboot/patch/20220406213153.30437-1-p...@kernel.org/ > please follow-up and ask the maintainers to comment. No new comment yet :-( > > Important is patch which fixes regression introduced in v2022.07-rc2 > > which broke NOR booting. > > Are anything other than the first two patches there regression fixes? There is also small regression for SDHC: https://patchwork.ozlabs.org/project/uboot/patch/20220511182828.26890-1-p...@kernel.org/
